Coverage Report

Created: 2018-07-12 09:57

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Hexagon/HexagonGenInstrInfo.inc
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1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Instruction Enum Values and Descriptors                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_INSTRINFO_ENUM
10
#undef GET_INSTRINFO_ENUM
11
namespace llvm {
12
13
namespace Hexagon {
14
  enum {
15
    PHI = 0,
16
    INLINEASM = 1,
17
    CFI_INSTRUCTION = 2,
18
    EH_LABEL  = 3,
19
    GC_LABEL  = 4,
20
    ANNOTATION_LABEL  = 5,
21
    KILL  = 6,
22
    EXTRACT_SUBREG  = 7,
23
    INSERT_SUBREG = 8,
24
    IMPLICIT_DEF  = 9,
25
    SUBREG_TO_REG = 10,
26
    COPY_TO_REGCLASS  = 11,
27
    DBG_VALUE = 12,
28
    DBG_LABEL = 13,
29
    REG_SEQUENCE  = 14,
30
    COPY  = 15,
31
    BUNDLE  = 16,
32
    LIFETIME_START  = 17,
33
    LIFETIME_END  = 18,
34
    STACKMAP  = 19,
35
    FENTRY_CALL = 20,
36
    PATCHPOINT  = 21,
37
    LOAD_STACK_GUARD  = 22,
38
    STATEPOINT  = 23,
39
    LOCAL_ESCAPE  = 24,
40
    FAULTING_OP = 25,
41
    PATCHABLE_OP  = 26,
42
    PATCHABLE_FUNCTION_ENTER  = 27,
43
    PATCHABLE_RET = 28,
44
    PATCHABLE_FUNCTION_EXIT = 29,
45
    PATCHABLE_TAIL_CALL = 30,
46
    PATCHABLE_EVENT_CALL  = 31,
47
    PATCHABLE_TYPED_EVENT_CALL  = 32,
48
    ICALL_BRANCH_FUNNEL = 33,
49
    G_ADD = 34,
50
    G_SUB = 35,
51
    G_MUL = 36,
52
    G_SDIV  = 37,
53
    G_UDIV  = 38,
54
    G_SREM  = 39,
55
    G_UREM  = 40,
56
    G_AND = 41,
57
    G_OR  = 42,
58
    G_XOR = 43,
59
    G_IMPLICIT_DEF  = 44,
60
    G_PHI = 45,
61
    G_FRAME_INDEX = 46,
62
    G_GLOBAL_VALUE  = 47,
63
    G_EXTRACT = 48,
64
    G_UNMERGE_VALUES  = 49,
65
    G_INSERT  = 50,
66
    G_MERGE_VALUES  = 51,
67
    G_PTRTOINT  = 52,
68
    G_INTTOPTR  = 53,
69
    G_BITCAST = 54,
70
    G_LOAD  = 55,
71
    G_SEXTLOAD  = 56,
72
    G_ZEXTLOAD  = 57,
73
    G_STORE = 58,
74
    G_ATOMIC_CMPXCHG_WITH_SUCCESS = 59,
75
    G_ATOMIC_CMPXCHG  = 60,
76
    G_ATOMICRMW_XCHG  = 61,
77
    G_ATOMICRMW_ADD = 62,
78
    G_ATOMICRMW_SUB = 63,
79
    G_ATOMICRMW_AND = 64,
80
    G_ATOMICRMW_NAND  = 65,
81
    G_ATOMICRMW_OR  = 66,
82
    G_ATOMICRMW_XOR = 67,
83
    G_ATOMICRMW_MAX = 68,
84
    G_ATOMICRMW_MIN = 69,
85
    G_ATOMICRMW_UMAX  = 70,
86
    G_ATOMICRMW_UMIN  = 71,
87
    G_BRCOND  = 72,
88
    G_BRINDIRECT  = 73,
89
    G_INTRINSIC = 74,
90
    G_INTRINSIC_W_SIDE_EFFECTS  = 75,
91
    G_ANYEXT  = 76,
92
    G_TRUNC = 77,
93
    G_CONSTANT  = 78,
94
    G_FCONSTANT = 79,
95
    G_VASTART = 80,
96
    G_VAARG = 81,
97
    G_SEXT  = 82,
98
    G_ZEXT  = 83,
99
    G_SHL = 84,
100
    G_LSHR  = 85,
101
    G_ASHR  = 86,
102
    G_ICMP  = 87,
103
    G_FCMP  = 88,
104
    G_SELECT  = 89,
105
    G_UADDE = 90,
106
    G_USUBE = 91,
107
    G_SADDO = 92,
108
    G_SSUBO = 93,
109
    G_UMULO = 94,
110
    G_SMULO = 95,
111
    G_UMULH = 96,
112
    G_SMULH = 97,
113
    G_FADD  = 98,
114
    G_FSUB  = 99,
115
    G_FMUL  = 100,
116
    G_FMA = 101,
117
    G_FDIV  = 102,
118
    G_FREM  = 103,
119
    G_FPOW  = 104,
120
    G_FEXP  = 105,
121
    G_FEXP2 = 106,
122
    G_FLOG  = 107,
123
    G_FLOG2 = 108,
124
    G_FNEG  = 109,
125
    G_FPEXT = 110,
126
    G_FPTRUNC = 111,
127
    G_FPTOSI  = 112,
128
    G_FPTOUI  = 113,
129
    G_SITOFP  = 114,
130
    G_UITOFP  = 115,
131
    G_FABS  = 116,
132
    G_GEP = 117,
133
    G_PTR_MASK  = 118,
134
    G_BR  = 119,
135
    G_INSERT_VECTOR_ELT = 120,
136
    G_EXTRACT_VECTOR_ELT  = 121,
137
    G_SHUFFLE_VECTOR  = 122,
138
    G_BSWAP = 123,
139
    G_ADDRSPACE_CAST  = 124,
140
    A2_addsp  = 125,
141
    A2_iconst = 126,
142
    A2_neg  = 127,
143
    A2_not  = 128,
144
    A2_tfrf = 129,
145
    A2_tfrfnew  = 130,
146
    A2_tfrp = 131,
147
    A2_tfrpf  = 132,
148
    A2_tfrpfnew = 133,
149
    A2_tfrpi  = 134,
150
    A2_tfrpt  = 135,
151
    A2_tfrptnew = 136,
152
    A2_tfrt = 137,
153
    A2_tfrtnew  = 138,
154
    A2_vaddb_map  = 139,
155
    A2_vsubb_map  = 140,
156
    A2_zxtb = 141,
157
    A4_boundscheck  = 142,
158
    ADJCALLSTACKDOWN  = 143,
159
    ADJCALLSTACKUP  = 144,
160
    C2_cmpgei = 145,
161
    C2_cmpgeui  = 146,
162
    C2_cmplt  = 147,
163
    C2_cmpltu = 148,
164
    C2_pxfer_map  = 149,
165
    DUPLEX_Pseudo = 150,
166
    ENDLOOP0  = 151,
167
    ENDLOOP01 = 152,
168
    ENDLOOP1  = 153,
169
    J2_endloop0 = 154,
170
    J2_endloop01  = 155,
171
    J2_endloop1 = 156,
172
    J2_jumpf_nopred_map = 157,
173
    J2_jumprf_nopred_map  = 158,
174
    J2_jumprt_nopred_map  = 159,
175
    J2_jumpt_nopred_map = 160,
176
    J2_trap1_noregmap = 161,
177
    L2_loadalignb_zomap = 162,
178
    L2_loadalignh_zomap = 163,
179
    L2_loadbsw2_zomap = 164,
180
    L2_loadbsw4_zomap = 165,
181
    L2_loadbzw2_zomap = 166,
182
    L2_loadbzw4_zomap = 167,
183
    L2_loadrb_zomap = 168,
184
    L2_loadrd_zomap = 169,
185
    L2_loadrh_zomap = 170,
186
    L2_loadri_zomap = 171,
187
    L2_loadrub_zomap  = 172,
188
    L2_loadruh_zomap  = 173,
189
    L2_ploadrbf_zomap = 174,
190
    L2_ploadrbfnew_zomap  = 175,
191
    L2_ploadrbt_zomap = 176,
192
    L2_ploadrbtnew_zomap  = 177,
193
    L2_ploadrdf_zomap = 178,
194
    L2_ploadrdfnew_zomap  = 179,
195
    L2_ploadrdt_zomap = 180,
196
    L2_ploadrdtnew_zomap  = 181,
197
    L2_ploadrhf_zomap = 182,
198
    L2_ploadrhfnew_zomap  = 183,
199
    L2_ploadrht_zomap = 184,
200
    L2_ploadrhtnew_zomap  = 185,
201
    L2_ploadrif_zomap = 186,
202
    L2_ploadrifnew_zomap  = 187,
203
    L2_ploadrit_zomap = 188,
204
    L2_ploadritnew_zomap  = 189,
205
    L2_ploadrubf_zomap  = 190,
206
    L2_ploadrubfnew_zomap = 191,
207
    L2_ploadrubt_zomap  = 192,
208
    L2_ploadrubtnew_zomap = 193,
209
    L2_ploadruhf_zomap  = 194,
210
    L2_ploadruhfnew_zomap = 195,
211
    L2_ploadruht_zomap  = 196,
212
    L2_ploadruhtnew_zomap = 197,
213
    L4_add_memopb_zomap = 198,
214
    L4_add_memoph_zomap = 199,
215
    L4_add_memopw_zomap = 200,
216
    L4_and_memopb_zomap = 201,
217
    L4_and_memoph_zomap = 202,
218
    L4_and_memopw_zomap = 203,
219
    L4_iadd_memopb_zomap  = 204,
220
    L4_iadd_memoph_zomap  = 205,
221
    L4_iadd_memopw_zomap  = 206,
222
    L4_iand_memopb_zomap  = 207,
223
    L4_iand_memoph_zomap  = 208,
224
    L4_iand_memopw_zomap  = 209,
225
    L4_ior_memopb_zomap = 210,
226
    L4_ior_memoph_zomap = 211,
227
    L4_ior_memopw_zomap = 212,
228
    L4_isub_memopb_zomap  = 213,
229
    L4_isub_memoph_zomap  = 214,
230
    L4_isub_memopw_zomap  = 215,
231
    L4_or_memopb_zomap  = 216,
232
    L4_or_memoph_zomap  = 217,
233
    L4_or_memopw_zomap  = 218,
234
    L4_return_map_to_raw_f  = 219,
235
    L4_return_map_to_raw_fnew_pnt = 220,
236
    L4_return_map_to_raw_fnew_pt  = 221,
237
    L4_return_map_to_raw_t  = 222,
238
    L4_return_map_to_raw_tnew_pnt = 223,
239
    L4_return_map_to_raw_tnew_pt  = 224,
240
    L4_sub_memopb_zomap = 225,
241
    L4_sub_memoph_zomap = 226,
242
    L4_sub_memopw_zomap = 227,
243
    L6_deallocframe_map_to_raw  = 228,
244
    L6_return_map_to_raw  = 229,
245
    LDriw_ctr = 230,
246
    LDriw_pred  = 231,
247
    M2_mpysmi = 232,
248
    M2_mpyui  = 233,
249
    M2_vrcmpys_acc_s1 = 234,
250
    M2_vrcmpys_s1 = 235,
251
    M2_vrcmpys_s1rp = 236,
252
    PS_aligna = 237,
253
    PS_alloca = 238,
254
    PS_call_nr  = 239,
255
    PS_false  = 240,
256
    PS_fi = 241,
257
    PS_fia  = 242,
258
    PS_loadrb_pci = 243,
259
    PS_loadrb_pcr = 244,
260
    PS_loadrd_pci = 245,
261
    PS_loadrd_pcr = 246,
262
    PS_loadrh_pci = 247,
263
    PS_loadrh_pcr = 248,
264
    PS_loadri_pci = 249,
265
    PS_loadri_pcr = 250,
266
    PS_loadrub_pci  = 251,
267
    PS_loadrub_pcr  = 252,
268
    PS_loadruh_pci  = 253,
269
    PS_loadruh_pcr  = 254,
270
    PS_pselect  = 255,
271
    PS_qfalse = 256,
272
    PS_qtrue  = 257,
273
    PS_storerb_pci  = 258,
274
    PS_storerb_pcr  = 259,
275
    PS_storerd_pci  = 260,
276
    PS_storerd_pcr  = 261,
277
    PS_storerf_pci  = 262,
278
    PS_storerf_pcr  = 263,
279
    PS_storerh_pci  = 264,
280
    PS_storerh_pcr  = 265,
281
    PS_storeri_pci  = 266,
282
    PS_storeri_pcr  = 267,
283
    PS_tailcall_i = 268,
284
    PS_tailcall_r = 269,
285
    PS_true = 270,
286
    PS_vdd0 = 271,
287
    PS_vloadrq_ai = 272,
288
    PS_vloadrw_ai = 273,
289
    PS_vloadrw_nt_ai  = 274,
290
    PS_vloadrwu_ai  = 275,
291
    PS_vmulw  = 276,
292
    PS_vmulw_acc  = 277,
293
    PS_vselect  = 278,
294
    PS_vstorerq_ai  = 279,
295
    PS_vstorerw_ai  = 280,
296
    PS_vstorerw_nt_ai = 281,
297
    PS_vstorerwu_ai = 282,
298
    PS_wselect  = 283,
299
    S2_asr_i_p_rnd_goodsyntax = 284,
300
    S2_asr_i_r_rnd_goodsyntax = 285,
301
    S2_pstorerbf_zomap  = 286,
302
    S2_pstorerbnewf_zomap = 287,
303
    S2_pstorerbnewt_zomap = 288,
304
    S2_pstorerbt_zomap  = 289,
305
    S2_pstorerdf_zomap  = 290,
306
    S2_pstorerdt_zomap  = 291,
307
    S2_pstorerff_zomap  = 292,
308
    S2_pstorerft_zomap  = 293,
309
    S2_pstorerhf_zomap  = 294,
310
    S2_pstorerhnewf_zomap = 295,
311
    S2_pstorerhnewt_zomap = 296,
312
    S2_pstorerht_zomap  = 297,
313
    S2_pstorerif_zomap  = 298,
314
    S2_pstorerinewf_zomap = 299,
315
    S2_pstorerinewt_zomap = 300,
316
    S2_pstorerit_zomap  = 301,
317
    S2_storerb_zomap  = 302,
318
    S2_storerbnew_zomap = 303,
319
    S2_storerd_zomap  = 304,
320
    S2_storerf_zomap  = 305,
321
    S2_storerh_zomap  = 306,
322
    S2_storerhnew_zomap = 307,
323
    S2_storeri_zomap  = 308,
324
    S2_storerinew_zomap = 309,
325
    S2_tableidxb_goodsyntax = 310,
326
    S2_tableidxd_goodsyntax = 311,
327
    S2_tableidxh_goodsyntax = 312,
328
    S2_tableidxw_goodsyntax = 313,
329
    S4_pstorerbfnew_zomap = 314,
330
    S4_pstorerbnewfnew_zomap  = 315,
331
    S4_pstorerbnewtnew_zomap  = 316,
332
    S4_pstorerbtnew_zomap = 317,
333
    S4_pstorerdfnew_zomap = 318,
334
    S4_pstorerdtnew_zomap = 319,
335
    S4_pstorerffnew_zomap = 320,
336
    S4_pstorerftnew_zomap = 321,
337
    S4_pstorerhfnew_zomap = 322,
338
    S4_pstorerhnewfnew_zomap  = 323,
339
    S4_pstorerhnewtnew_zomap  = 324,
340
    S4_pstorerhtnew_zomap = 325,
341
    S4_pstorerifnew_zomap = 326,
342
    S4_pstorerinewfnew_zomap  = 327,
343
    S4_pstorerinewtnew_zomap  = 328,
344
    S4_pstoreritnew_zomap = 329,
345
    S4_storeirb_zomap = 330,
346
    S4_storeirbf_zomap  = 331,
347
    S4_storeirbfnew_zomap = 332,
348
    S4_storeirbt_zomap  = 333,
349
    S4_storeirbtnew_zomap = 334,
350
    S4_storeirh_zomap = 335,
351
    S4_storeirhf_zomap  = 336,
352
    S4_storeirhfnew_zomap = 337,
353
    S4_storeirht_zomap  = 338,
354
    S4_storeirhtnew_zomap = 339,
355
    S4_storeiri_zomap = 340,
356
    S4_storeirif_zomap  = 341,
357
    S4_storeirifnew_zomap = 342,
358
    S4_storeirit_zomap  = 343,
359
    S4_storeiritnew_zomap = 344,
360
    S5_asrhub_rnd_sat_goodsyntax  = 345,
361
    S5_vasrhrnd_goodsyntax  = 346,
362
    S6_allocframe_to_raw  = 347,
363
    STriw_ctr = 348,
364
    STriw_pred  = 349,
365
    V6_MAP_equb = 350,
366
    V6_MAP_equb_and = 351,
367
    V6_MAP_equb_ior = 352,
368
    V6_MAP_equb_xor = 353,
369
    V6_MAP_equh = 354,
370
    V6_MAP_equh_and = 355,
371
    V6_MAP_equh_ior = 356,
372
    V6_MAP_equh_xor = 357,
373
    V6_MAP_equw = 358,
374
    V6_MAP_equw_and = 359,
375
    V6_MAP_equw_ior = 360,
376
    V6_MAP_equw_xor = 361,
377
    V6_extractw_alt = 362,
378
    V6_hi = 363,
379
    V6_ld0  = 364,
380
    V6_ldcnp0 = 365,
381
    V6_ldcnpnt0 = 366,
382
    V6_ldcp0  = 367,
383
    V6_ldcpnt0  = 368,
384
    V6_ldnp0  = 369,
385
    V6_ldnpnt0  = 370,
386
    V6_ldnt0  = 371,
387
    V6_ldntnt0  = 372,
388
    V6_ldp0 = 373,
389
    V6_ldpnt0 = 374,
390
    V6_ldtnp0 = 375,
391
    V6_ldtnpnt0 = 376,
392
    V6_ldtp0  = 377,
393
    V6_ldtpnt0  = 378,
394
    V6_ldu0 = 379,
395
    V6_lo = 380,
396
    V6_st0  = 381,
397
    V6_stn0 = 382,
398
    V6_stnnt0 = 383,
399
    V6_stnp0  = 384,
400
    V6_stnpnt0  = 385,
401
    V6_stnq0  = 386,
402
    V6_stnqnt0  = 387,
403
    V6_stnt0  = 388,
404
    V6_stp0 = 389,
405
    V6_stpnt0 = 390,
406
    V6_stq0 = 391,
407
    V6_stqnt0 = 392,
408
    V6_stu0 = 393,
409
    V6_stunp0 = 394,
410
    V6_stup0  = 395,
411
    V6_vabsb_alt  = 396,
412
    V6_vabsb_sat_alt  = 397,
413
    V6_vabsdiffh_alt  = 398,
414
    V6_vabsdiffub_alt = 399,
415
    V6_vabsdiffuh_alt = 400,
416
    V6_vabsdiffw_alt  = 401,
417
    V6_vabsh_alt  = 402,
418
    V6_vabsh_sat_alt  = 403,
419
    V6_vabsub_alt = 404,
420
    V6_vabsuh_alt = 405,
421
    V6_vabsuw_alt = 406,
422
    V6_vabsw_alt  = 407,
423
    V6_vabsw_sat_alt  = 408,
424
    V6_vaddb_alt  = 409,
425
    V6_vaddb_dv_alt = 410,
426
    V6_vaddbnq_alt  = 411,
427
    V6_vaddbq_alt = 412,
428
    V6_vaddbsat_alt = 413,
429
    V6_vaddbsat_dv_alt  = 414,
430
    V6_vaddh_alt  = 415,
431
    V6_vaddh_dv_alt = 416,
432
    V6_vaddhnq_alt  = 417,
433
    V6_vaddhq_alt = 418,
434
    V6_vaddhsat_alt = 419,
435
    V6_vaddhsat_dv_alt  = 420,
436
    V6_vaddhw_acc_alt = 421,
437
    V6_vaddhw_alt = 422,
438
    V6_vaddubh_acc_alt  = 423,
439
    V6_vaddubh_alt  = 424,
440
    V6_vaddubsat_alt  = 425,
441
    V6_vaddubsat_dv_alt = 426,
442
    V6_vadduhsat_alt  = 427,
443
    V6_vadduhsat_dv_alt = 428,
444
    V6_vadduhw_acc_alt  = 429,
445
    V6_vadduhw_alt  = 430,
446
    V6_vadduwsat_alt  = 431,
447
    V6_vadduwsat_dv_alt = 432,
448
    V6_vaddw_alt  = 433,
449
    V6_vaddw_dv_alt = 434,
450
    V6_vaddwnq_alt  = 435,
451
    V6_vaddwq_alt = 436,
452
    V6_vaddwsat_alt = 437,
453
    V6_vaddwsat_dv_alt  = 438,
454
    V6_vandnqrt_acc_alt = 439,
455
    V6_vandnqrt_alt = 440,
456
    V6_vandqrt_acc_alt  = 441,
457
    V6_vandqrt_alt  = 442,
458
    V6_vandvrt_acc_alt  = 443,
459
    V6_vandvrt_alt  = 444,
460
    V6_vaslh_acc_alt  = 445,
461
    V6_vaslh_alt  = 446,
462
    V6_vaslhv_alt = 447,
463
    V6_vaslw_acc_alt  = 448,
464
    V6_vaslw_alt  = 449,
465
    V6_vaslwv_alt = 450,
466
    V6_vasrh_acc_alt  = 451,
467
    V6_vasrh_alt  = 452,
468
    V6_vasrhbrndsat_alt = 453,
469
    V6_vasrhubrndsat_alt  = 454,
470
    V6_vasrhubsat_alt = 455,
471
    V6_vasrhv_alt = 456,
472
    V6_vasrw_acc_alt  = 457,
473
    V6_vasrw_alt  = 458,
474
    V6_vasrwh_alt = 459,
475
    V6_vasrwhrndsat_alt = 460,
476
    V6_vasrwhsat_alt  = 461,
477
    V6_vasrwuhsat_alt = 462,
478
    V6_vasrwv_alt = 463,
479
    V6_vassignp = 464,
480
    V6_vavgb_alt  = 465,
481
    V6_vavgbrnd_alt = 466,
482
    V6_vavgh_alt  = 467,
483
    V6_vavghrnd_alt = 468,
484
    V6_vavgub_alt = 469,
485
    V6_vavgubrnd_alt  = 470,
486
    V6_vavguh_alt = 471,
487
    V6_vavguhrnd_alt  = 472,
488
    V6_vavguw_alt = 473,
489
    V6_vavguwrnd_alt  = 474,
490
    V6_vavgw_alt  = 475,
491
    V6_vavgwrnd_alt = 476,
492
    V6_vcl0h_alt  = 477,
493
    V6_vcl0w_alt  = 478,
494
    V6_vd0  = 479,
495
    V6_vdd0 = 480,
496
    V6_vdealb4w_alt = 481,
497
    V6_vdealb_alt = 482,
498
    V6_vdealh_alt = 483,
499
    V6_vdmpybus_acc_alt = 484,
500
    V6_vdmpybus_alt = 485,
501
    V6_vdmpybus_dv_acc_alt  = 486,
502
    V6_vdmpybus_dv_alt  = 487,
503
    V6_vdmpyhb_acc_alt  = 488,
504
    V6_vdmpyhb_alt  = 489,
505
    V6_vdmpyhb_dv_acc_alt = 490,
506
    V6_vdmpyhb_dv_alt = 491,
507
    V6_vdmpyhisat_acc_alt = 492,
508
    V6_vdmpyhisat_alt = 493,
509
    V6_vdmpyhsat_acc_alt  = 494,
510
    V6_vdmpyhsat_alt  = 495,
511
    V6_vdmpyhsuisat_acc_alt = 496,
512
    V6_vdmpyhsuisat_alt = 497,
513
    V6_vdmpyhsusat_acc_alt  = 498,
514
    V6_vdmpyhsusat_alt  = 499,
515
    V6_vdmpyhvsat_acc_alt = 500,
516
    V6_vdmpyhvsat_alt = 501,
517
    V6_vdsaduh_acc_alt  = 502,
518
    V6_vdsaduh_alt  = 503,
519
    V6_vgathermh_pseudo = 504,
520
    V6_vgathermhq_pseudo  = 505,
521
    V6_vgathermhw_pseudo  = 506,
522
    V6_vgathermhwq_pseudo = 507,
523
    V6_vgathermw_pseudo = 508,
524
    V6_vgathermwq_pseudo  = 509,
525
    V6_vlsrh_alt  = 510,
526
    V6_vlsrhv_alt = 511,
527
    V6_vlsrw_alt  = 512,
528
    V6_vlsrwv_alt = 513,
529
    V6_vmaxb_alt  = 514,
530
    V6_vmaxh_alt  = 515,
531
    V6_vmaxub_alt = 516,
532
    V6_vmaxuh_alt = 517,
533
    V6_vmaxw_alt  = 518,
534
    V6_vminb_alt  = 519,
535
    V6_vminh_alt  = 520,
536
    V6_vminub_alt = 521,
537
    V6_vminuh_alt = 522,
538
    V6_vminw_alt  = 523,
539
    V6_vmpabus_acc_alt  = 524,
540
    V6_vmpabus_alt  = 525,
541
    V6_vmpabusv_alt = 526,
542
    V6_vmpabuu_acc_alt  = 527,
543
    V6_vmpabuu_alt  = 528,
544
    V6_vmpabuuv_alt = 529,
545
    V6_vmpahb_acc_alt = 530,
546
    V6_vmpahb_alt = 531,
547
    V6_vmpauhb_acc_alt  = 532,
548
    V6_vmpauhb_alt  = 533,
549
    V6_vmpybus_acc_alt  = 534,
550
    V6_vmpybus_alt  = 535,
551
    V6_vmpybusv_acc_alt = 536,
552
    V6_vmpybusv_alt = 537,
553
    V6_vmpybv_acc_alt = 538,
554
    V6_vmpybv_alt = 539,
555
    V6_vmpyewuh_alt = 540,
556
    V6_vmpyh_acc_alt  = 541,
557
    V6_vmpyh_alt  = 542,
558
    V6_vmpyhsat_acc_alt = 543,
559
    V6_vmpyhsrs_alt = 544,
560
    V6_vmpyhss_alt  = 545,
561
    V6_vmpyhus_acc_alt  = 546,
562
    V6_vmpyhus_alt  = 547,
563
    V6_vmpyhv_acc_alt = 548,
564
    V6_vmpyhv_alt = 549,
565
    V6_vmpyhvsrs_alt  = 550,
566
    V6_vmpyiewh_acc_alt = 551,
567
    V6_vmpyiewuh_acc_alt  = 552,
568
    V6_vmpyiewuh_alt  = 553,
569
    V6_vmpyih_acc_alt = 554,
570
    V6_vmpyih_alt = 555,
571
    V6_vmpyihb_acc_alt  = 556,
572
    V6_vmpyihb_alt  = 557,
573
    V6_vmpyiowh_alt = 558,
574
    V6_vmpyiwb_acc_alt  = 559,
575
    V6_vmpyiwb_alt  = 560,
576
    V6_vmpyiwh_acc_alt  = 561,
577
    V6_vmpyiwh_alt  = 562,
578
    V6_vmpyiwub_acc_alt = 563,
579
    V6_vmpyiwub_alt = 564,
580
    V6_vmpyowh_alt  = 565,
581
    V6_vmpyowh_rnd_alt  = 566,
582
    V6_vmpyowh_rnd_sacc_alt = 567,
583
    V6_vmpyowh_sacc_alt = 568,
584
    V6_vmpyub_acc_alt = 569,
585
    V6_vmpyub_alt = 570,
586
    V6_vmpyubv_acc_alt  = 571,
587
    V6_vmpyubv_alt  = 572,
588
    V6_vmpyuh_acc_alt = 573,
589
    V6_vmpyuh_alt = 574,
590
    V6_vmpyuhv_acc_alt  = 575,
591
    V6_vmpyuhv_alt  = 576,
592
    V6_vnavgb_alt = 577,
593
    V6_vnavgh_alt = 578,
594
    V6_vnavgub_alt  = 579,
595
    V6_vnavgw_alt = 580,
596
    V6_vnormamth_alt  = 581,
597
    V6_vnormamtw_alt  = 582,
598
    V6_vpackeb_alt  = 583,
599
    V6_vpackeh_alt  = 584,
600
    V6_vpackhb_sat_alt  = 585,
601
    V6_vpackhub_sat_alt = 586,
602
    V6_vpackob_alt  = 587,
603
    V6_vpackoh_alt  = 588,
604
    V6_vpackwh_sat_alt  = 589,
605
    V6_vpackwuh_sat_alt = 590,
606
    V6_vpopcounth_alt = 591,
607
    V6_vrmpybub_rtt_acc_alt = 592,
608
    V6_vrmpybub_rtt_alt = 593,
609
    V6_vrmpybus_acc_alt = 594,
610
    V6_vrmpybus_alt = 595,
611
    V6_vrmpybusi_acc_alt  = 596,
612
    V6_vrmpybusi_alt  = 597,
613
    V6_vrmpybusv_acc_alt  = 598,
614
    V6_vrmpybusv_alt  = 599,
615
    V6_vrmpybv_acc_alt  = 600,
616
    V6_vrmpybv_alt  = 601,
617
    V6_vrmpyub_acc_alt  = 602,
618
    V6_vrmpyub_alt  = 603,
619
    V6_vrmpyub_rtt_acc_alt  = 604,
620
    V6_vrmpyub_rtt_alt  = 605,
621
    V6_vrmpyubi_acc_alt = 606,
622
    V6_vrmpyubi_alt = 607,
623
    V6_vrmpyubv_acc_alt = 608,
624
    V6_vrmpyubv_alt = 609,
625
    V6_vroundhb_alt = 610,
626
    V6_vroundhub_alt  = 611,
627
    V6_vrounduhub_alt = 612,
628
    V6_vrounduwuh_alt = 613,
629
    V6_vroundwh_alt = 614,
630
    V6_vroundwuh_alt  = 615,
631
    V6_vrsadubi_acc_alt = 616,
632
    V6_vrsadubi_alt = 617,
633
    V6_vsathub_alt  = 618,
634
    V6_vsatuwuh_alt = 619,
635
    V6_vsatwh_alt = 620,
636
    V6_vsb_alt  = 621,
637
    V6_vscattermh_add_alt = 622,
638
    V6_vscattermh_alt = 623,
639
    V6_vscattermhq_alt  = 624,
640
    V6_vscattermw_add_alt = 625,
641
    V6_vscattermw_alt = 626,
642
    V6_vscattermwh_add_alt  = 627,
643
    V6_vscattermwh_alt  = 628,
644
    V6_vscattermwhq_alt = 629,
645
    V6_vscattermwq_alt  = 630,
646
    V6_vsh_alt  = 631,
647
    V6_vshufeh_alt  = 632,
648
    V6_vshuffb_alt  = 633,
649
    V6_vshuffeb_alt = 634,
650
    V6_vshuffh_alt  = 635,
651
    V6_vshuffob_alt = 636,
652
    V6_vshufoeb_alt = 637,
653
    V6_vshufoeh_alt = 638,
654
    V6_vshufoh_alt  = 639,
655
    V6_vsubb_alt  = 640,
656
    V6_vsubb_dv_alt = 641,
657
    V6_vsubbnq_alt  = 642,
658
    V6_vsubbq_alt = 643,
659
    V6_vsubbsat_alt = 644,
660
    V6_vsubbsat_dv_alt  = 645,
661
    V6_vsubh_alt  = 646,
662
    V6_vsubh_dv_alt = 647,
663
    V6_vsubhnq_alt  = 648,
664
    V6_vsubhq_alt = 649,
665
    V6_vsubhsat_alt = 650,
666
    V6_vsubhsat_dv_alt  = 651,
667
    V6_vsubhw_alt = 652,
668
    V6_vsububh_alt  = 653,
669
    V6_vsububsat_alt  = 654,
670
    V6_vsububsat_dv_alt = 655,
671
    V6_vsubuhsat_alt  = 656,
672
    V6_vsubuhsat_dv_alt = 657,
673
    V6_vsubuhw_alt  = 658,
674
    V6_vsubuwsat_alt  = 659,
675
    V6_vsubuwsat_dv_alt = 660,
676
    V6_vsubw_alt  = 661,
677
    V6_vsubw_dv_alt = 662,
678
    V6_vsubwnq_alt  = 663,
679
    V6_vsubwq_alt = 664,
680
    V6_vsubwsat_alt = 665,
681
    V6_vsubwsat_dv_alt  = 666,
682
    V6_vtmpyb_acc_alt = 667,
683
    V6_vtmpyb_alt = 668,
684
    V6_vtmpybus_acc_alt = 669,
685
    V6_vtmpybus_alt = 670,
686
    V6_vtmpyhb_acc_alt  = 671,
687
    V6_vtmpyhb_alt  = 672,
688
    V6_vtran2x2_map = 673,
689
    V6_vunpackb_alt = 674,
690
    V6_vunpackh_alt = 675,
691
    V6_vunpackob_alt  = 676,
692
    V6_vunpackoh_alt  = 677,
693
    V6_vunpackub_alt  = 678,
694
    V6_vunpackuh_alt  = 679,
695
    V6_vzb_alt  = 680,
696
    V6_vzh_alt  = 681,
697
    Y2_dcfetch  = 682,
698
    A2_abs  = 683,
699
    A2_absp = 684,
700
    A2_abssat = 685,
701
    A2_add  = 686,
702
    A2_addh_h16_hh  = 687,
703
    A2_addh_h16_hl  = 688,
704
    A2_addh_h16_lh  = 689,
705
    A2_addh_h16_ll  = 690,
706
    A2_addh_h16_sat_hh  = 691,
707
    A2_addh_h16_sat_hl  = 692,
708
    A2_addh_h16_sat_lh  = 693,
709
    A2_addh_h16_sat_ll  = 694,
710
    A2_addh_l16_hl  = 695,
711
    A2_addh_l16_ll  = 696,
712
    A2_addh_l16_sat_hl  = 697,
713
    A2_addh_l16_sat_ll  = 698,
714
    A2_addi = 699,
715
    A2_addp = 700,
716
    A2_addpsat  = 701,
717
    A2_addsat = 702,
718
    A2_addsph = 703,
719
    A2_addspl = 704,
720
    A2_and  = 705,
721
    A2_andir  = 706,
722
    A2_andp = 707,
723
    A2_aslh = 708,
724
    A2_asrh = 709,
725
    A2_combine_hh = 710,
726
    A2_combine_hl = 711,
727
    A2_combine_lh = 712,
728
    A2_combine_ll = 713,
729
    A2_combineii  = 714,
730
    A2_combinew = 715,
731
    A2_max  = 716,
732
    A2_maxp = 717,
733
    A2_maxu = 718,
734
    A2_maxup  = 719,
735
    A2_min  = 720,
736
    A2_minp = 721,
737
    A2_minu = 722,
738
    A2_minup  = 723,
739
    A2_negp = 724,
740
    A2_negsat = 725,
741
    A2_nop  = 726,
742
    A2_notp = 727,
743
    A2_or = 728,
744
    A2_orir = 729,
745
    A2_orp  = 730,
746
    A2_paddf  = 731,
747
    A2_paddfnew = 732,
748
    A2_paddif = 733,
749
    A2_paddifnew  = 734,
750
    A2_paddit = 735,
751
    A2_padditnew  = 736,
752
    A2_paddt  = 737,
753
    A2_paddtnew = 738,
754
    A2_pandf  = 739,
755
    A2_pandfnew = 740,
756
    A2_pandt  = 741,
757
    A2_pandtnew = 742,
758
    A2_porf = 743,
759
    A2_porfnew  = 744,
760
    A2_port = 745,
761
    A2_portnew  = 746,
762
    A2_psubf  = 747,
763
    A2_psubfnew = 748,
764
    A2_psubt  = 749,
765
    A2_psubtnew = 750,
766
    A2_pxorf  = 751,
767
    A2_pxorfnew = 752,
768
    A2_pxort  = 753,
769
    A2_pxortnew = 754,
770
    A2_roundsat = 755,
771
    A2_sat  = 756,
772
    A2_satb = 757,
773
    A2_sath = 758,
774
    A2_satub  = 759,
775
    A2_satuh  = 760,
776
    A2_sub  = 761,
777
    A2_subh_h16_hh  = 762,
778
    A2_subh_h16_hl  = 763,
779
    A2_subh_h16_lh  = 764,
780
    A2_subh_h16_ll  = 765,
781
    A2_subh_h16_sat_hh  = 766,
782
    A2_subh_h16_sat_hl  = 767,
783
    A2_subh_h16_sat_lh  = 768,
784
    A2_subh_h16_sat_ll  = 769,
785
    A2_subh_l16_hl  = 770,
786
    A2_subh_l16_ll  = 771,
787
    A2_subh_l16_sat_hl  = 772,
788
    A2_subh_l16_sat_ll  = 773,
789
    A2_subp = 774,
790
    A2_subri  = 775,
791
    A2_subsat = 776,
792
    A2_svaddh = 777,
793
    A2_svaddhs  = 778,
794
    A2_svadduhs = 779,
795
    A2_svavgh = 780,
796
    A2_svavghs  = 781,
797
    A2_svnavgh  = 782,
798
    A2_svsubh = 783,
799
    A2_svsubhs  = 784,
800
    A2_svsubuhs = 785,
801
    A2_swiz = 786,
802
    A2_sxtb = 787,
803
    A2_sxth = 788,
804
    A2_sxtw = 789,
805
    A2_tfr  = 790,
806
    A2_tfrcrr = 791,
807
    A2_tfrih  = 792,
808
    A2_tfril  = 793,
809
    A2_tfrrcr = 794,
810
    A2_tfrsi  = 795,
811
    A2_vabsh  = 796,
812
    A2_vabshsat = 797,
813
    A2_vabsw  = 798,
814
    A2_vabswsat = 799,
815
    A2_vaddh  = 800,
816
    A2_vaddhs = 801,
817
    A2_vaddub = 802,
818
    A2_vaddubs  = 803,
819
    A2_vadduhs  = 804,
820
    A2_vaddw  = 805,
821
    A2_vaddws = 806,
822
    A2_vavgh  = 807,
823
    A2_vavghcr  = 808,
824
    A2_vavghr = 809,
825
    A2_vavgub = 810,
826
    A2_vavgubr  = 811,
827
    A2_vavguh = 812,
828
    A2_vavguhr  = 813,
829
    A2_vavguw = 814,
830
    A2_vavguwr  = 815,
831
    A2_vavgw  = 816,
832
    A2_vavgwcr  = 817,
833
    A2_vavgwr = 818,
834
    A2_vcmpbeq  = 819,
835
    A2_vcmpbgtu = 820,
836
    A2_vcmpheq  = 821,
837
    A2_vcmphgt  = 822,
838
    A2_vcmphgtu = 823,
839
    A2_vcmpweq  = 824,
840
    A2_vcmpwgt  = 825,
841
    A2_vcmpwgtu = 826,
842
    A2_vconj  = 827,
843
    A2_vmaxb  = 828,
844
    A2_vmaxh  = 829,
845
    A2_vmaxub = 830,
846
    A2_vmaxuh = 831,
847
    A2_vmaxuw = 832,
848
    A2_vmaxw  = 833,
849
    A2_vminb  = 834,
850
    A2_vminh  = 835,
851
    A2_vminub = 836,
852
    A2_vminuh = 837,
853
    A2_vminuw = 838,
854
    A2_vminw  = 839,
855
    A2_vnavgh = 840,
856
    A2_vnavghcr = 841,
857
    A2_vnavghr  = 842,
858
    A2_vnavgw = 843,
859
    A2_vnavgwcr = 844,
860
    A2_vnavgwr  = 845,
861
    A2_vraddub  = 846,
862
    A2_vraddub_acc  = 847,
863
    A2_vrsadub  = 848,
864
    A2_vrsadub_acc  = 849,
865
    A2_vsubh  = 850,
866
    A2_vsubhs = 851,
867
    A2_vsubub = 852,
868
    A2_vsububs  = 853,
869
    A2_vsubuhs  = 854,
870
    A2_vsubw  = 855,
871
    A2_vsubws = 856,
872
    A2_xor  = 857,
873
    A2_xorp = 858,
874
    A2_zxth = 859,
875
    A4_addp_c = 860,
876
    A4_andn = 861,
877
    A4_andnp  = 862,
878
    A4_bitsplit = 863,
879
    A4_bitspliti  = 864,
880
    A4_boundscheck_hi = 865,
881
    A4_boundscheck_lo = 866,
882
    A4_cmpbeq = 867,
883
    A4_cmpbeqi  = 868,
884
    A4_cmpbgt = 869,
885
    A4_cmpbgti  = 870,
886
    A4_cmpbgtu  = 871,
887
    A4_cmpbgtui = 872,
888
    A4_cmpheq = 873,
889
    A4_cmpheqi  = 874,
890
    A4_cmphgt = 875,
891
    A4_cmphgti  = 876,
892
    A4_cmphgtu  = 877,
893
    A4_cmphgtui = 878,
894
    A4_combineii  = 879,
895
    A4_combineir  = 880,
896
    A4_combineri  = 881,
897
    A4_cround_ri  = 882,
898
    A4_cround_rr  = 883,
899
    A4_ext  = 884,
900
    A4_modwrapu = 885,
901
    A4_orn  = 886,
902
    A4_ornp = 887,
903
    A4_paslhf = 888,
904
    A4_paslhfnew  = 889,
905
    A4_paslht = 890,
906
    A4_paslhtnew  = 891,
907
    A4_pasrhf = 892,
908
    A4_pasrhfnew  = 893,
909
    A4_pasrht = 894,
910
    A4_pasrhtnew  = 895,
911
    A4_psxtbf = 896,
912
    A4_psxtbfnew  = 897,
913
    A4_psxtbt = 898,
914
    A4_psxtbtnew  = 899,
915
    A4_psxthf = 900,
916
    A4_psxthfnew  = 901,
917
    A4_psxtht = 902,
918
    A4_psxthtnew  = 903,
919
    A4_pzxtbf = 904,
920
    A4_pzxtbfnew  = 905,
921
    A4_pzxtbt = 906,
922
    A4_pzxtbtnew  = 907,
923
    A4_pzxthf = 908,
924
    A4_pzxthfnew  = 909,
925
    A4_pzxtht = 910,
926
    A4_pzxthtnew  = 911,
927
    A4_rcmpeq = 912,
928
    A4_rcmpeqi  = 913,
929
    A4_rcmpneq  = 914,
930
    A4_rcmpneqi = 915,
931
    A4_round_ri = 916,
932
    A4_round_ri_sat = 917,
933
    A4_round_rr = 918,
934
    A4_round_rr_sat = 919,
935
    A4_subp_c = 920,
936
    A4_tfrcpp = 921,
937
    A4_tfrpcp = 922,
938
    A4_tlbmatch = 923,
939
    A4_vcmpbeq_any  = 924,
940
    A4_vcmpbeqi = 925,
941
    A4_vcmpbgt  = 926,
942
    A4_vcmpbgti = 927,
943
    A4_vcmpbgtui  = 928,
944
    A4_vcmpheqi = 929,
945
    A4_vcmphgti = 930,
946
    A4_vcmphgtui  = 931,
947
    A4_vcmpweqi = 932,
948
    A4_vcmpwgti = 933,
949
    A4_vcmpwgtui  = 934,
950
    A4_vrmaxh = 935,
951
    A4_vrmaxuh  = 936,
952
    A4_vrmaxuw  = 937,
953
    A4_vrmaxw = 938,
954
    A4_vrminh = 939,
955
    A4_vrminuh  = 940,
956
    A4_vrminuw  = 941,
957
    A4_vrminw = 942,
958
    A5_ACS  = 943,
959
    A5_vaddhubs = 944,
960
    A6_vcmpbeq_notany = 945,
961
    A6_vminub_RdP = 946,
962
    C2_all8 = 947,
963
    C2_and  = 948,
964
    C2_andn = 949,
965
    C2_any8 = 950,
966
    C2_bitsclr  = 951,
967
    C2_bitsclri = 952,
968
    C2_bitsset  = 953,
969
    C2_ccombinewf = 954,
970
    C2_ccombinewnewf  = 955,
971
    C2_ccombinewnewt  = 956,
972
    C2_ccombinewt = 957,
973
    C2_cmoveif  = 958,
974
    C2_cmoveit  = 959,
975
    C2_cmovenewif = 960,
976
    C2_cmovenewit = 961,
977
    C2_cmpeq  = 962,
978
    C2_cmpeqi = 963,
979
    C2_cmpeqp = 964,
980
    C2_cmpgt  = 965,
981
    C2_cmpgti = 966,
982
    C2_cmpgtp = 967,
983
    C2_cmpgtu = 968,
984
    C2_cmpgtui  = 969,
985
    C2_cmpgtup  = 970,
986
    C2_mask = 971,
987
    C2_mux  = 972,
988
    C2_muxii  = 973,
989
    C2_muxir  = 974,
990
    C2_muxri  = 975,
991
    C2_not  = 976,
992
    C2_or = 977,
993
    C2_orn  = 978,
994
    C2_tfrpr  = 979,
995
    C2_tfrrp  = 980,
996
    C2_vitpack  = 981,
997
    C2_vmux = 982,
998
    C2_xor  = 983,
999
    C4_addipc = 984,
1000
    C4_and_and  = 985,
1001
    C4_and_andn = 986,
1002
    C4_and_or = 987,
1003
    C4_and_orn  = 988,
1004
    C4_cmplte = 989,
1005
    C4_cmpltei  = 990,
1006
    C4_cmplteu  = 991,
1007
    C4_cmplteui = 992,
1008
    C4_cmpneq = 993,
1009
    C4_cmpneqi  = 994,
1010
    C4_fastcorner9  = 995,
1011
    C4_fastcorner9_not  = 996,
1012
    C4_nbitsclr = 997,
1013
    C4_nbitsclri  = 998,
1014
    C4_nbitsset = 999,
1015
    C4_or_and = 1000,
1016
    C4_or_andn  = 1001,
1017
    C4_or_or  = 1002,
1018
    C4_or_orn = 1003,
1019
    CALLProfile = 1004,
1020
    CONST32 = 1005,
1021
    CONST64 = 1006,
1022
    DuplexIClass0 = 1007,
1023
    DuplexIClass1 = 1008,
1024
    DuplexIClass2 = 1009,
1025
    DuplexIClass3 = 1010,
1026
    DuplexIClass4 = 1011,
1027
    DuplexIClass5 = 1012,
1028
    DuplexIClass6 = 1013,
1029
    DuplexIClass7 = 1014,
1030
    DuplexIClass8 = 1015,
1031
    DuplexIClass9 = 1016,
1032
    DuplexIClassA = 1017,
1033
    DuplexIClassB = 1018,
1034
    DuplexIClassC = 1019,
1035
    DuplexIClassD = 1020,
1036
    DuplexIClassE = 1021,
1037
    DuplexIClassF = 1022,
1038
    EH_RETURN_JMPR  = 1023,
1039
    F2_conv_d2df  = 1024,
1040
    F2_conv_d2sf  = 1025,
1041
    F2_conv_df2d  = 1026,
1042
    F2_conv_df2d_chop = 1027,
1043
    F2_conv_df2sf = 1028,
1044
    F2_conv_df2ud = 1029,
1045
    F2_conv_df2ud_chop  = 1030,
1046
    F2_conv_df2uw = 1031,
1047
    F2_conv_df2uw_chop  = 1032,
1048
    F2_conv_df2w  = 1033,
1049
    F2_conv_df2w_chop = 1034,
1050
    F2_conv_sf2d  = 1035,
1051
    F2_conv_sf2d_chop = 1036,
1052
    F2_conv_sf2df = 1037,
1053
    F2_conv_sf2ud = 1038,
1054
    F2_conv_sf2ud_chop  = 1039,
1055
    F2_conv_sf2uw = 1040,
1056
    F2_conv_sf2uw_chop  = 1041,
1057
    F2_conv_sf2w  = 1042,
1058
    F2_conv_sf2w_chop = 1043,
1059
    F2_conv_ud2df = 1044,
1060
    F2_conv_ud2sf = 1045,
1061
    F2_conv_uw2df = 1046,
1062
    F2_conv_uw2sf = 1047,
1063
    F2_conv_w2df  = 1048,
1064
    F2_conv_w2sf  = 1049,
1065
    F2_dfclass  = 1050,
1066
    F2_dfcmpeq  = 1051,
1067
    F2_dfcmpge  = 1052,
1068
    F2_dfcmpgt  = 1053,
1069
    F2_dfcmpuo  = 1054,
1070
    F2_dfimm_n  = 1055,
1071
    F2_dfimm_p  = 1056,
1072
    F2_sfadd  = 1057,
1073
    F2_sfclass  = 1058,
1074
    F2_sfcmpeq  = 1059,
1075
    F2_sfcmpge  = 1060,
1076
    F2_sfcmpgt  = 1061,
1077
    F2_sfcmpuo  = 1062,
1078
    F2_sffixupd = 1063,
1079
    F2_sffixupn = 1064,
1080
    F2_sffixupr = 1065,
1081
    F2_sffma  = 1066,
1082
    F2_sffma_lib  = 1067,
1083
    F2_sffma_sc = 1068,
1084
    F2_sffms  = 1069,
1085
    F2_sffms_lib  = 1070,
1086
    F2_sfimm_n  = 1071,
1087
    F2_sfimm_p  = 1072,
1088
    F2_sfinvsqrta = 1073,
1089
    F2_sfmax  = 1074,
1090
    F2_sfmin  = 1075,
1091
    F2_sfmpy  = 1076,
1092
    F2_sfrecipa = 1077,
1093
    F2_sfsub  = 1078,
1094
    G4_tfrgcpp  = 1079,
1095
    G4_tfrgcrr  = 1080,
1096
    G4_tfrgpcp  = 1081,
1097
    G4_tfrgrcr  = 1082,
1098
    HI  = 1083,
1099
    J2_call = 1084,
1100
    J2_callf  = 1085,
1101
    J2_callr  = 1086,
1102
    J2_callrf = 1087,
1103
    J2_callrt = 1088,
1104
    J2_callt  = 1089,
1105
    J2_jump = 1090,
1106
    J2_jumpf  = 1091,
1107
    J2_jumpfnew = 1092,
1108
    J2_jumpfnewpt = 1093,
1109
    J2_jumpfpt  = 1094,
1110
    J2_jumpr  = 1095,
1111
    J2_jumprf = 1096,
1112
    J2_jumprfnew  = 1097,
1113
    J2_jumprfnewpt  = 1098,
1114
    J2_jumprfpt = 1099,
1115
    J2_jumprgtez  = 1100,
1116
    J2_jumprgtezpt  = 1101,
1117
    J2_jumprltez  = 1102,
1118
    J2_jumprltezpt  = 1103,
1119
    J2_jumprnz  = 1104,
1120
    J2_jumprnzpt  = 1105,
1121
    J2_jumprt = 1106,
1122
    J2_jumprtnew  = 1107,
1123
    J2_jumprtnewpt  = 1108,
1124
    J2_jumprtpt = 1109,
1125
    J2_jumprz = 1110,
1126
    J2_jumprzpt = 1111,
1127
    J2_jumpt  = 1112,
1128
    J2_jumptnew = 1113,
1129
    J2_jumptnewpt = 1114,
1130
    J2_jumptpt  = 1115,
1131
    J2_loop0i = 1116,
1132
    J2_loop0iext  = 1117,
1133
    J2_loop0r = 1118,
1134
    J2_loop0rext  = 1119,
1135
    J2_loop1i = 1120,
1136
    J2_loop1iext  = 1121,
1137
    J2_loop1r = 1122,
1138
    J2_loop1rext  = 1123,
1139
    J2_pause  = 1124,
1140
    J2_ploop1si = 1125,
1141
    J2_ploop1sr = 1126,
1142
    J2_ploop2si = 1127,
1143
    J2_ploop2sr = 1128,
1144
    J2_ploop3si = 1129,
1145
    J2_ploop3sr = 1130,
1146
    J2_trap0  = 1131,
1147
    J2_trap1  = 1132,
1148
    J4_cmpeq_f_jumpnv_nt  = 1133,
1149
    J4_cmpeq_f_jumpnv_t = 1134,
1150
    J4_cmpeq_fp0_jump_nt  = 1135,
1151
    J4_cmpeq_fp0_jump_t = 1136,
1152
    J4_cmpeq_fp1_jump_nt  = 1137,
1153
    J4_cmpeq_fp1_jump_t = 1138,
1154
    J4_cmpeq_t_jumpnv_nt  = 1139,
1155
    J4_cmpeq_t_jumpnv_t = 1140,
1156
    J4_cmpeq_tp0_jump_nt  = 1141,
1157
    J4_cmpeq_tp0_jump_t = 1142,
1158
    J4_cmpeq_tp1_jump_nt  = 1143,
1159
    J4_cmpeq_tp1_jump_t = 1144,
1160
    J4_cmpeqi_f_jumpnv_nt = 1145,
1161
    J4_cmpeqi_f_jumpnv_t  = 1146,
1162
    J4_cmpeqi_fp0_jump_nt = 1147,
1163
    J4_cmpeqi_fp0_jump_t  = 1148,
1164
    J4_cmpeqi_fp1_jump_nt = 1149,
1165
    J4_cmpeqi_fp1_jump_t  = 1150,
1166
    J4_cmpeqi_t_jumpnv_nt = 1151,
1167
    J4_cmpeqi_t_jumpnv_t  = 1152,
1168
    J4_cmpeqi_tp0_jump_nt = 1153,
1169
    J4_cmpeqi_tp0_jump_t  = 1154,
1170
    J4_cmpeqi_tp1_jump_nt = 1155,
1171
    J4_cmpeqi_tp1_jump_t  = 1156,
1172
    J4_cmpeqn1_f_jumpnv_nt  = 1157,
1173
    J4_cmpeqn1_f_jumpnv_t = 1158,
1174
    J4_cmpeqn1_fp0_jump_nt  = 1159,
1175
    J4_cmpeqn1_fp0_jump_t = 1160,
1176
    J4_cmpeqn1_fp1_jump_nt  = 1161,
1177
    J4_cmpeqn1_fp1_jump_t = 1162,
1178
    J4_cmpeqn1_t_jumpnv_nt  = 1163,
1179
    J4_cmpeqn1_t_jumpnv_t = 1164,
1180
    J4_cmpeqn1_tp0_jump_nt  = 1165,
1181
    J4_cmpeqn1_tp0_jump_t = 1166,
1182
    J4_cmpeqn1_tp1_jump_nt  = 1167,
1183
    J4_cmpeqn1_tp1_jump_t = 1168,
1184
    J4_cmpgt_f_jumpnv_nt  = 1169,
1185
    J4_cmpgt_f_jumpnv_t = 1170,
1186
    J4_cmpgt_fp0_jump_nt  = 1171,
1187
    J4_cmpgt_fp0_jump_t = 1172,
1188
    J4_cmpgt_fp1_jump_nt  = 1173,
1189
    J4_cmpgt_fp1_jump_t = 1174,
1190
    J4_cmpgt_t_jumpnv_nt  = 1175,
1191
    J4_cmpgt_t_jumpnv_t = 1176,
1192
    J4_cmpgt_tp0_jump_nt  = 1177,
1193
    J4_cmpgt_tp0_jump_t = 1178,
1194
    J4_cmpgt_tp1_jump_nt  = 1179,
1195
    J4_cmpgt_tp1_jump_t = 1180,
1196
    J4_cmpgti_f_jumpnv_nt = 1181,
1197
    J4_cmpgti_f_jumpnv_t  = 1182,
1198
    J4_cmpgti_fp0_jump_nt = 1183,
1199
    J4_cmpgti_fp0_jump_t  = 1184,
1200
    J4_cmpgti_fp1_jump_nt = 1185,
1201
    J4_cmpgti_fp1_jump_t  = 1186,
1202
    J4_cmpgti_t_jumpnv_nt = 1187,
1203
    J4_cmpgti_t_jumpnv_t  = 1188,
1204
    J4_cmpgti_tp0_jump_nt = 1189,
1205
    J4_cmpgti_tp0_jump_t  = 1190,
1206
    J4_cmpgti_tp1_jump_nt = 1191,
1207
    J4_cmpgti_tp1_jump_t  = 1192,
1208
    J4_cmpgtn1_f_jumpnv_nt  = 1193,
1209
    J4_cmpgtn1_f_jumpnv_t = 1194,
1210
    J4_cmpgtn1_fp0_jump_nt  = 1195,
1211
    J4_cmpgtn1_fp0_jump_t = 1196,
1212
    J4_cmpgtn1_fp1_jump_nt  = 1197,
1213
    J4_cmpgtn1_fp1_jump_t = 1198,
1214
    J4_cmpgtn1_t_jumpnv_nt  = 1199,
1215
    J4_cmpgtn1_t_jumpnv_t = 1200,
1216
    J4_cmpgtn1_tp0_jump_nt  = 1201,
1217
    J4_cmpgtn1_tp0_jump_t = 1202,
1218
    J4_cmpgtn1_tp1_jump_nt  = 1203,
1219
    J4_cmpgtn1_tp1_jump_t = 1204,
1220
    J4_cmpgtu_f_jumpnv_nt = 1205,
1221
    J4_cmpgtu_f_jumpnv_t  = 1206,
1222
    J4_cmpgtu_fp0_jump_nt = 1207,
1223
    J4_cmpgtu_fp0_jump_t  = 1208,
1224
    J4_cmpgtu_fp1_jump_nt = 1209,
1225
    J4_cmpgtu_fp1_jump_t  = 1210,
1226
    J4_cmpgtu_t_jumpnv_nt = 1211,
1227
    J4_cmpgtu_t_jumpnv_t  = 1212,
1228
    J4_cmpgtu_tp0_jump_nt = 1213,
1229
    J4_cmpgtu_tp0_jump_t  = 1214,
1230
    J4_cmpgtu_tp1_jump_nt = 1215,
1231
    J4_cmpgtu_tp1_jump_t  = 1216,
1232
    J4_cmpgtui_f_jumpnv_nt  = 1217,
1233
    J4_cmpgtui_f_jumpnv_t = 1218,
1234
    J4_cmpgtui_fp0_jump_nt  = 1219,
1235
    J4_cmpgtui_fp0_jump_t = 1220,
1236
    J4_cmpgtui_fp1_jump_nt  = 1221,
1237
    J4_cmpgtui_fp1_jump_t = 1222,
1238
    J4_cmpgtui_t_jumpnv_nt  = 1223,
1239
    J4_cmpgtui_t_jumpnv_t = 1224,
1240
    J4_cmpgtui_tp0_jump_nt  = 1225,
1241
    J4_cmpgtui_tp0_jump_t = 1226,
1242
    J4_cmpgtui_tp1_jump_nt  = 1227,
1243
    J4_cmpgtui_tp1_jump_t = 1228,
1244
    J4_cmplt_f_jumpnv_nt  = 1229,
1245
    J4_cmplt_f_jumpnv_t = 1230,
1246
    J4_cmplt_t_jumpnv_nt  = 1231,
1247
    J4_cmplt_t_jumpnv_t = 1232,
1248
    J4_cmpltu_f_jumpnv_nt = 1233,
1249
    J4_cmpltu_f_jumpnv_t  = 1234,
1250
    J4_cmpltu_t_jumpnv_nt = 1235,
1251
    J4_cmpltu_t_jumpnv_t  = 1236,
1252
    J4_hintjumpr  = 1237,
1253
    J4_jumpseti = 1238,
1254
    J4_jumpsetr = 1239,
1255
    J4_tstbit0_f_jumpnv_nt  = 1240,
1256
    J4_tstbit0_f_jumpnv_t = 1241,
1257
    J4_tstbit0_fp0_jump_nt  = 1242,
1258
    J4_tstbit0_fp0_jump_t = 1243,
1259
    J4_tstbit0_fp1_jump_nt  = 1244,
1260
    J4_tstbit0_fp1_jump_t = 1245,
1261
    J4_tstbit0_t_jumpnv_nt  = 1246,
1262
    J4_tstbit0_t_jumpnv_t = 1247,
1263
    J4_tstbit0_tp0_jump_nt  = 1248,
1264
    J4_tstbit0_tp0_jump_t = 1249,
1265
    J4_tstbit0_tp1_jump_nt  = 1250,
1266
    J4_tstbit0_tp1_jump_t = 1251,
1267
    L2_deallocframe = 1252,
1268
    L2_loadalignb_io  = 1253,
1269
    L2_loadalignb_pbr = 1254,
1270
    L2_loadalignb_pci = 1255,
1271
    L2_loadalignb_pcr = 1256,
1272
    L2_loadalignb_pi  = 1257,
1273
    L2_loadalignb_pr  = 1258,
1274
    L2_loadalignh_io  = 1259,
1275
    L2_loadalignh_pbr = 1260,
1276
    L2_loadalignh_pci = 1261,
1277
    L2_loadalignh_pcr = 1262,
1278
    L2_loadalignh_pi  = 1263,
1279
    L2_loadalignh_pr  = 1264,
1280
    L2_loadbsw2_io  = 1265,
1281
    L2_loadbsw2_pbr = 1266,
1282
    L2_loadbsw2_pci = 1267,
1283
    L2_loadbsw2_pcr = 1268,
1284
    L2_loadbsw2_pi  = 1269,
1285
    L2_loadbsw2_pr  = 1270,
1286
    L2_loadbsw4_io  = 1271,
1287
    L2_loadbsw4_pbr = 1272,
1288
    L2_loadbsw4_pci = 1273,
1289
    L2_loadbsw4_pcr = 1274,
1290
    L2_loadbsw4_pi  = 1275,
1291
    L2_loadbsw4_pr  = 1276,
1292
    L2_loadbzw2_io  = 1277,
1293
    L2_loadbzw2_pbr = 1278,
1294
    L2_loadbzw2_pci = 1279,
1295
    L2_loadbzw2_pcr = 1280,
1296
    L2_loadbzw2_pi  = 1281,
1297
    L2_loadbzw2_pr  = 1282,
1298
    L2_loadbzw4_io  = 1283,
1299
    L2_loadbzw4_pbr = 1284,
1300
    L2_loadbzw4_pci = 1285,
1301
    L2_loadbzw4_pcr = 1286,
1302
    L2_loadbzw4_pi  = 1287,
1303
    L2_loadbzw4_pr  = 1288,
1304
    L2_loadrb_io  = 1289,
1305
    L2_loadrb_pbr = 1290,
1306
    L2_loadrb_pci = 1291,
1307
    L2_loadrb_pcr = 1292,
1308
    L2_loadrb_pi  = 1293,
1309
    L2_loadrb_pr  = 1294,
1310
    L2_loadrbgp = 1295,
1311
    L2_loadrd_io  = 1296,
1312
    L2_loadrd_pbr = 1297,
1313
    L2_loadrd_pci = 1298,
1314
    L2_loadrd_pcr = 1299,
1315
    L2_loadrd_pi  = 1300,
1316
    L2_loadrd_pr  = 1301,
1317
    L2_loadrdgp = 1302,
1318
    L2_loadrh_io  = 1303,
1319
    L2_loadrh_pbr = 1304,
1320
    L2_loadrh_pci = 1305,
1321
    L2_loadrh_pcr = 1306,
1322
    L2_loadrh_pi  = 1307,
1323
    L2_loadrh_pr  = 1308,
1324
    L2_loadrhgp = 1309,
1325
    L2_loadri_io  = 1310,
1326
    L2_loadri_pbr = 1311,
1327
    L2_loadri_pci = 1312,
1328
    L2_loadri_pcr = 1313,
1329
    L2_loadri_pi  = 1314,
1330
    L2_loadri_pr  = 1315,
1331
    L2_loadrigp = 1316,
1332
    L2_loadrub_io = 1317,
1333
    L2_loadrub_pbr  = 1318,
1334
    L2_loadrub_pci  = 1319,
1335
    L2_loadrub_pcr  = 1320,
1336
    L2_loadrub_pi = 1321,
1337
    L2_loadrub_pr = 1322,
1338
    L2_loadrubgp  = 1323,
1339
    L2_loadruh_io = 1324,
1340
    L2_loadruh_pbr  = 1325,
1341
    L2_loadruh_pci  = 1326,
1342
    L2_loadruh_pcr  = 1327,
1343
    L2_loadruh_pi = 1328,
1344
    L2_loadruh_pr = 1329,
1345
    L2_loadruhgp  = 1330,
1346
    L2_loadw_locked = 1331,
1347
    L2_ploadrbf_io  = 1332,
1348
    L2_ploadrbf_pi  = 1333,
1349
    L2_ploadrbfnew_io = 1334,
1350
    L2_ploadrbfnew_pi = 1335,
1351
    L2_ploadrbt_io  = 1336,
1352
    L2_ploadrbt_pi  = 1337,
1353
    L2_ploadrbtnew_io = 1338,
1354
    L2_ploadrbtnew_pi = 1339,
1355
    L2_ploadrdf_io  = 1340,
1356
    L2_ploadrdf_pi  = 1341,
1357
    L2_ploadrdfnew_io = 1342,
1358
    L2_ploadrdfnew_pi = 1343,
1359
    L2_ploadrdt_io  = 1344,
1360
    L2_ploadrdt_pi  = 1345,
1361
    L2_ploadrdtnew_io = 1346,
1362
    L2_ploadrdtnew_pi = 1347,
1363
    L2_ploadrhf_io  = 1348,
1364
    L2_ploadrhf_pi  = 1349,
1365
    L2_ploadrhfnew_io = 1350,
1366
    L2_ploadrhfnew_pi = 1351,
1367
    L2_ploadrht_io  = 1352,
1368
    L2_ploadrht_pi  = 1353,
1369
    L2_ploadrhtnew_io = 1354,
1370
    L2_ploadrhtnew_pi = 1355,
1371
    L2_ploadrif_io  = 1356,
1372
    L2_ploadrif_pi  = 1357,
1373
    L2_ploadrifnew_io = 1358,
1374
    L2_ploadrifnew_pi = 1359,
1375
    L2_ploadrit_io  = 1360,
1376
    L2_ploadrit_pi  = 1361,
1377
    L2_ploadritnew_io = 1362,
1378
    L2_ploadritnew_pi = 1363,
1379
    L2_ploadrubf_io = 1364,
1380
    L2_ploadrubf_pi = 1365,
1381
    L2_ploadrubfnew_io  = 1366,
1382
    L2_ploadrubfnew_pi  = 1367,
1383
    L2_ploadrubt_io = 1368,
1384
    L2_ploadrubt_pi = 1369,
1385
    L2_ploadrubtnew_io  = 1370,
1386
    L2_ploadrubtnew_pi  = 1371,
1387
    L2_ploadruhf_io = 1372,
1388
    L2_ploadruhf_pi = 1373,
1389
    L2_ploadruhfnew_io  = 1374,
1390
    L2_ploadruhfnew_pi  = 1375,
1391
    L2_ploadruht_io = 1376,
1392
    L2_ploadruht_pi = 1377,
1393
    L2_ploadruhtnew_io  = 1378,
1394
    L2_ploadruhtnew_pi  = 1379,
1395
    L4_add_memopb_io  = 1380,
1396
    L4_add_memoph_io  = 1381,
1397
    L4_add_memopw_io  = 1382,
1398
    L4_and_memopb_io  = 1383,
1399
    L4_and_memoph_io  = 1384,
1400
    L4_and_memopw_io  = 1385,
1401
    L4_iadd_memopb_io = 1386,
1402
    L4_iadd_memoph_io = 1387,
1403
    L4_iadd_memopw_io = 1388,
1404
    L4_iand_memopb_io = 1389,
1405
    L4_iand_memoph_io = 1390,
1406
    L4_iand_memopw_io = 1391,
1407
    L4_ior_memopb_io  = 1392,
1408
    L4_ior_memoph_io  = 1393,
1409
    L4_ior_memopw_io  = 1394,
1410
    L4_isub_memopb_io = 1395,
1411
    L4_isub_memoph_io = 1396,
1412
    L4_isub_memopw_io = 1397,
1413
    L4_loadalignb_ap  = 1398,
1414
    L4_loadalignb_ur  = 1399,
1415
    L4_loadalignh_ap  = 1400,
1416
    L4_loadalignh_ur  = 1401,
1417
    L4_loadbsw2_ap  = 1402,
1418
    L4_loadbsw2_ur  = 1403,
1419
    L4_loadbsw4_ap  = 1404,
1420
    L4_loadbsw4_ur  = 1405,
1421
    L4_loadbzw2_ap  = 1406,
1422
    L4_loadbzw2_ur  = 1407,
1423
    L4_loadbzw4_ap  = 1408,
1424
    L4_loadbzw4_ur  = 1409,
1425
    L4_loadd_locked = 1410,
1426
    L4_loadrb_ap  = 1411,
1427
    L4_loadrb_rr  = 1412,
1428
    L4_loadrb_ur  = 1413,
1429
    L4_loadrd_ap  = 1414,
1430
    L4_loadrd_rr  = 1415,
1431
    L4_loadrd_ur  = 1416,
1432
    L4_loadrh_ap  = 1417,
1433
    L4_loadrh_rr  = 1418,
1434
    L4_loadrh_ur  = 1419,
1435
    L4_loadri_ap  = 1420,
1436
    L4_loadri_rr  = 1421,
1437
    L4_loadri_ur  = 1422,
1438
    L4_loadrub_ap = 1423,
1439
    L4_loadrub_rr = 1424,
1440
    L4_loadrub_ur = 1425,
1441
    L4_loadruh_ap = 1426,
1442
    L4_loadruh_rr = 1427,
1443
    L4_loadruh_ur = 1428,
1444
    L4_or_memopb_io = 1429,
1445
    L4_or_memoph_io = 1430,
1446
    L4_or_memopw_io = 1431,
1447
    L4_ploadrbf_abs = 1432,
1448
    L4_ploadrbf_rr  = 1433,
1449
    L4_ploadrbfnew_abs  = 1434,
1450
    L4_ploadrbfnew_rr = 1435,
1451
    L4_ploadrbt_abs = 1436,
1452
    L4_ploadrbt_rr  = 1437,
1453
    L4_ploadrbtnew_abs  = 1438,
1454
    L4_ploadrbtnew_rr = 1439,
1455
    L4_ploadrdf_abs = 1440,
1456
    L4_ploadrdf_rr  = 1441,
1457
    L4_ploadrdfnew_abs  = 1442,
1458
    L4_ploadrdfnew_rr = 1443,
1459
    L4_ploadrdt_abs = 1444,
1460
    L4_ploadrdt_rr  = 1445,
1461
    L4_ploadrdtnew_abs  = 1446,
1462
    L4_ploadrdtnew_rr = 1447,
1463
    L4_ploadrhf_abs = 1448,
1464
    L4_ploadrhf_rr  = 1449,
1465
    L4_ploadrhfnew_abs  = 1450,
1466
    L4_ploadrhfnew_rr = 1451,
1467
    L4_ploadrht_abs = 1452,
1468
    L4_ploadrht_rr  = 1453,
1469
    L4_ploadrhtnew_abs  = 1454,
1470
    L4_ploadrhtnew_rr = 1455,
1471
    L4_ploadrif_abs = 1456,
1472
    L4_ploadrif_rr  = 1457,
1473
    L4_ploadrifnew_abs  = 1458,
1474
    L4_ploadrifnew_rr = 1459,
1475
    L4_ploadrit_abs = 1460,
1476
    L4_ploadrit_rr  = 1461,
1477
    L4_ploadritnew_abs  = 1462,
1478
    L4_ploadritnew_rr = 1463,
1479
    L4_ploadrubf_abs  = 1464,
1480
    L4_ploadrubf_rr = 1465,
1481
    L4_ploadrubfnew_abs = 1466,
1482
    L4_ploadrubfnew_rr  = 1467,
1483
    L4_ploadrubt_abs  = 1468,
1484
    L4_ploadrubt_rr = 1469,
1485
    L4_ploadrubtnew_abs = 1470,
1486
    L4_ploadrubtnew_rr  = 1471,
1487
    L4_ploadruhf_abs  = 1472,
1488
    L4_ploadruhf_rr = 1473,
1489
    L4_ploadruhfnew_abs = 1474,
1490
    L4_ploadruhfnew_rr  = 1475,
1491
    L4_ploadruht_abs  = 1476,
1492
    L4_ploadruht_rr = 1477,
1493
    L4_ploadruhtnew_abs = 1478,
1494
    L4_ploadruhtnew_rr  = 1479,
1495
    L4_return = 1480,
1496
    L4_return_f = 1481,
1497
    L4_return_fnew_pnt  = 1482,
1498
    L4_return_fnew_pt = 1483,
1499
    L4_return_t = 1484,
1500
    L4_return_tnew_pnt  = 1485,
1501
    L4_return_tnew_pt = 1486,
1502
    L4_sub_memopb_io  = 1487,
1503
    L4_sub_memoph_io  = 1488,
1504
    L4_sub_memopw_io  = 1489,
1505
    LO  = 1490,
1506
    M2_acci = 1491,
1507
    M2_accii  = 1492,
1508
    M2_cmaci_s0 = 1493,
1509
    M2_cmacr_s0 = 1494,
1510
    M2_cmacs_s0 = 1495,
1511
    M2_cmacs_s1 = 1496,
1512
    M2_cmacsc_s0  = 1497,
1513
    M2_cmacsc_s1  = 1498,
1514
    M2_cmpyi_s0 = 1499,
1515
    M2_cmpyr_s0 = 1500,
1516
    M2_cmpyrs_s0  = 1501,
1517
    M2_cmpyrs_s1  = 1502,
1518
    M2_cmpyrsc_s0 = 1503,
1519
    M2_cmpyrsc_s1 = 1504,
1520
    M2_cmpys_s0 = 1505,
1521
    M2_cmpys_s1 = 1506,
1522
    M2_cmpysc_s0  = 1507,
1523
    M2_cmpysc_s1  = 1508,
1524
    M2_cnacs_s0 = 1509,
1525
    M2_cnacs_s1 = 1510,
1526
    M2_cnacsc_s0  = 1511,
1527
    M2_cnacsc_s1  = 1512,
1528
    M2_dpmpyss_acc_s0 = 1513,
1529
    M2_dpmpyss_nac_s0 = 1514,
1530
    M2_dpmpyss_rnd_s0 = 1515,
1531
    M2_dpmpyss_s0 = 1516,
1532
    M2_dpmpyuu_acc_s0 = 1517,
1533
    M2_dpmpyuu_nac_s0 = 1518,
1534
    M2_dpmpyuu_s0 = 1519,
1535
    M2_hmmpyh_rs1 = 1520,
1536
    M2_hmmpyh_s1  = 1521,
1537
    M2_hmmpyl_rs1 = 1522,
1538
    M2_hmmpyl_s1  = 1523,
1539
    M2_maci = 1524,
1540
    M2_macsin = 1525,
1541
    M2_macsip = 1526,
1542
    M2_mmachs_rs0 = 1527,
1543
    M2_mmachs_rs1 = 1528,
1544
    M2_mmachs_s0  = 1529,
1545
    M2_mmachs_s1  = 1530,
1546
    M2_mmacls_rs0 = 1531,
1547
    M2_mmacls_rs1 = 1532,
1548
    M2_mmacls_s0  = 1533,
1549
    M2_mmacls_s1  = 1534,
1550
    M2_mmacuhs_rs0  = 1535,
1551
    M2_mmacuhs_rs1  = 1536,
1552
    M2_mmacuhs_s0 = 1537,
1553
    M2_mmacuhs_s1 = 1538,
1554
    M2_mmaculs_rs0  = 1539,
1555
    M2_mmaculs_rs1  = 1540,
1556
    M2_mmaculs_s0 = 1541,
1557
    M2_mmaculs_s1 = 1542,
1558
    M2_mmpyh_rs0  = 1543,
1559
    M2_mmpyh_rs1  = 1544,
1560
    M2_mmpyh_s0 = 1545,
1561
    M2_mmpyh_s1 = 1546,
1562
    M2_mmpyl_rs0  = 1547,
1563
    M2_mmpyl_rs1  = 1548,
1564
    M2_mmpyl_s0 = 1549,
1565
    M2_mmpyl_s1 = 1550,
1566
    M2_mmpyuh_rs0 = 1551,
1567
    M2_mmpyuh_rs1 = 1552,
1568
    M2_mmpyuh_s0  = 1553,
1569
    M2_mmpyuh_s1  = 1554,
1570
    M2_mmpyul_rs0 = 1555,
1571
    M2_mmpyul_rs1 = 1556,
1572
    M2_mmpyul_s0  = 1557,
1573
    M2_mmpyul_s1  = 1558,
1574
    M2_mpy_acc_hh_s0  = 1559,
1575
    M2_mpy_acc_hh_s1  = 1560,
1576
    M2_mpy_acc_hl_s0  = 1561,
1577
    M2_mpy_acc_hl_s1  = 1562,
1578
    M2_mpy_acc_lh_s0  = 1563,
1579
    M2_mpy_acc_lh_s1  = 1564,
1580
    M2_mpy_acc_ll_s0  = 1565,
1581
    M2_mpy_acc_ll_s1  = 1566,
1582
    M2_mpy_acc_sat_hh_s0  = 1567,
1583
    M2_mpy_acc_sat_hh_s1  = 1568,
1584
    M2_mpy_acc_sat_hl_s0  = 1569,
1585
    M2_mpy_acc_sat_hl_s1  = 1570,
1586
    M2_mpy_acc_sat_lh_s0  = 1571,
1587
    M2_mpy_acc_sat_lh_s1  = 1572,
1588
    M2_mpy_acc_sat_ll_s0  = 1573,
1589
    M2_mpy_acc_sat_ll_s1  = 1574,
1590
    M2_mpy_hh_s0  = 1575,
1591
    M2_mpy_hh_s1  = 1576,
1592
    M2_mpy_hl_s0  = 1577,
1593
    M2_mpy_hl_s1  = 1578,
1594
    M2_mpy_lh_s0  = 1579,
1595
    M2_mpy_lh_s1  = 1580,
1596
    M2_mpy_ll_s0  = 1581,
1597
    M2_mpy_ll_s1  = 1582,
1598
    M2_mpy_nac_hh_s0  = 1583,
1599
    M2_mpy_nac_hh_s1  = 1584,
1600
    M2_mpy_nac_hl_s0  = 1585,
1601
    M2_mpy_nac_hl_s1  = 1586,
1602
    M2_mpy_nac_lh_s0  = 1587,
1603
    M2_mpy_nac_lh_s1  = 1588,
1604
    M2_mpy_nac_ll_s0  = 1589,
1605
    M2_mpy_nac_ll_s1  = 1590,
1606
    M2_mpy_nac_sat_hh_s0  = 1591,
1607
    M2_mpy_nac_sat_hh_s1  = 1592,
1608
    M2_mpy_nac_sat_hl_s0  = 1593,
1609
    M2_mpy_nac_sat_hl_s1  = 1594,
1610
    M2_mpy_nac_sat_lh_s0  = 1595,
1611
    M2_mpy_nac_sat_lh_s1  = 1596,
1612
    M2_mpy_nac_sat_ll_s0  = 1597,
1613
    M2_mpy_nac_sat_ll_s1  = 1598,
1614
    M2_mpy_rnd_hh_s0  = 1599,
1615
    M2_mpy_rnd_hh_s1  = 1600,
1616
    M2_mpy_rnd_hl_s0  = 1601,
1617
    M2_mpy_rnd_hl_s1  = 1602,
1618
    M2_mpy_rnd_lh_s0  = 1603,
1619
    M2_mpy_rnd_lh_s1  = 1604,
1620
    M2_mpy_rnd_ll_s0  = 1605,
1621
    M2_mpy_rnd_ll_s1  = 1606,
1622
    M2_mpy_sat_hh_s0  = 1607,
1623
    M2_mpy_sat_hh_s1  = 1608,
1624
    M2_mpy_sat_hl_s0  = 1609,
1625
    M2_mpy_sat_hl_s1  = 1610,
1626
    M2_mpy_sat_lh_s0  = 1611,
1627
    M2_mpy_sat_lh_s1  = 1612,
1628
    M2_mpy_sat_ll_s0  = 1613,
1629
    M2_mpy_sat_ll_s1  = 1614,
1630
    M2_mpy_sat_rnd_hh_s0  = 1615,
1631
    M2_mpy_sat_rnd_hh_s1  = 1616,
1632
    M2_mpy_sat_rnd_hl_s0  = 1617,
1633
    M2_mpy_sat_rnd_hl_s1  = 1618,
1634
    M2_mpy_sat_rnd_lh_s0  = 1619,
1635
    M2_mpy_sat_rnd_lh_s1  = 1620,
1636
    M2_mpy_sat_rnd_ll_s0  = 1621,
1637
    M2_mpy_sat_rnd_ll_s1  = 1622,
1638
    M2_mpy_up = 1623,
1639
    M2_mpy_up_s1  = 1624,
1640
    M2_mpy_up_s1_sat  = 1625,
1641
    M2_mpyd_acc_hh_s0 = 1626,
1642
    M2_mpyd_acc_hh_s1 = 1627,
1643
    M2_mpyd_acc_hl_s0 = 1628,
1644
    M2_mpyd_acc_hl_s1 = 1629,
1645
    M2_mpyd_acc_lh_s0 = 1630,
1646
    M2_mpyd_acc_lh_s1 = 1631,
1647
    M2_mpyd_acc_ll_s0 = 1632,
1648
    M2_mpyd_acc_ll_s1 = 1633,
1649
    M2_mpyd_hh_s0 = 1634,
1650
    M2_mpyd_hh_s1 = 1635,
1651
    M2_mpyd_hl_s0 = 1636,
1652
    M2_mpyd_hl_s1 = 1637,
1653
    M2_mpyd_lh_s0 = 1638,
1654
    M2_mpyd_lh_s1 = 1639,
1655
    M2_mpyd_ll_s0 = 1640,
1656
    M2_mpyd_ll_s1 = 1641,
1657
    M2_mpyd_nac_hh_s0 = 1642,
1658
    M2_mpyd_nac_hh_s1 = 1643,
1659
    M2_mpyd_nac_hl_s0 = 1644,
1660
    M2_mpyd_nac_hl_s1 = 1645,
1661
    M2_mpyd_nac_lh_s0 = 1646,
1662
    M2_mpyd_nac_lh_s1 = 1647,
1663
    M2_mpyd_nac_ll_s0 = 1648,
1664
    M2_mpyd_nac_ll_s1 = 1649,
1665
    M2_mpyd_rnd_hh_s0 = 1650,
1666
    M2_mpyd_rnd_hh_s1 = 1651,
1667
    M2_mpyd_rnd_hl_s0 = 1652,
1668
    M2_mpyd_rnd_hl_s1 = 1653,
1669
    M2_mpyd_rnd_lh_s0 = 1654,
1670
    M2_mpyd_rnd_lh_s1 = 1655,
1671
    M2_mpyd_rnd_ll_s0 = 1656,
1672
    M2_mpyd_rnd_ll_s1 = 1657,
1673
    M2_mpyi = 1658,
1674
    M2_mpysin = 1659,
1675
    M2_mpysip = 1660,
1676
    M2_mpysu_up = 1661,
1677
    M2_mpyu_acc_hh_s0 = 1662,
1678
    M2_mpyu_acc_hh_s1 = 1663,
1679
    M2_mpyu_acc_hl_s0 = 1664,
1680
    M2_mpyu_acc_hl_s1 = 1665,
1681
    M2_mpyu_acc_lh_s0 = 1666,
1682
    M2_mpyu_acc_lh_s1 = 1667,
1683
    M2_mpyu_acc_ll_s0 = 1668,
1684
    M2_mpyu_acc_ll_s1 = 1669,
1685
    M2_mpyu_hh_s0 = 1670,
1686
    M2_mpyu_hh_s1 = 1671,
1687
    M2_mpyu_hl_s0 = 1672,
1688
    M2_mpyu_hl_s1 = 1673,
1689
    M2_mpyu_lh_s0 = 1674,
1690
    M2_mpyu_lh_s1 = 1675,
1691
    M2_mpyu_ll_s0 = 1676,
1692
    M2_mpyu_ll_s1 = 1677,
1693
    M2_mpyu_nac_hh_s0 = 1678,
1694
    M2_mpyu_nac_hh_s1 = 1679,
1695
    M2_mpyu_nac_hl_s0 = 1680,
1696
    M2_mpyu_nac_hl_s1 = 1681,
1697
    M2_mpyu_nac_lh_s0 = 1682,
1698
    M2_mpyu_nac_lh_s1 = 1683,
1699
    M2_mpyu_nac_ll_s0 = 1684,
1700
    M2_mpyu_nac_ll_s1 = 1685,
1701
    M2_mpyu_up  = 1686,
1702
    M2_mpyud_acc_hh_s0  = 1687,
1703
    M2_mpyud_acc_hh_s1  = 1688,
1704
    M2_mpyud_acc_hl_s0  = 1689,
1705
    M2_mpyud_acc_hl_s1  = 1690,
1706
    M2_mpyud_acc_lh_s0  = 1691,
1707
    M2_mpyud_acc_lh_s1  = 1692,
1708
    M2_mpyud_acc_ll_s0  = 1693,
1709
    M2_mpyud_acc_ll_s1  = 1694,
1710
    M2_mpyud_hh_s0  = 1695,
1711
    M2_mpyud_hh_s1  = 1696,
1712
    M2_mpyud_hl_s0  = 1697,
1713
    M2_mpyud_hl_s1  = 1698,
1714
    M2_mpyud_lh_s0  = 1699,
1715
    M2_mpyud_lh_s1  = 1700,
1716
    M2_mpyud_ll_s0  = 1701,
1717
    M2_mpyud_ll_s1  = 1702,
1718
    M2_mpyud_nac_hh_s0  = 1703,
1719
    M2_mpyud_nac_hh_s1  = 1704,
1720
    M2_mpyud_nac_hl_s0  = 1705,
1721
    M2_mpyud_nac_hl_s1  = 1706,
1722
    M2_mpyud_nac_lh_s0  = 1707,
1723
    M2_mpyud_nac_lh_s1  = 1708,
1724
    M2_mpyud_nac_ll_s0  = 1709,
1725
    M2_mpyud_nac_ll_s1  = 1710,
1726
    M2_nacci  = 1711,
1727
    M2_naccii = 1712,
1728
    M2_subacc = 1713,
1729
    M2_vabsdiffh  = 1714,
1730
    M2_vabsdiffw  = 1715,
1731
    M2_vcmac_s0_sat_i = 1716,
1732
    M2_vcmac_s0_sat_r = 1717,
1733
    M2_vcmpy_s0_sat_i = 1718,
1734
    M2_vcmpy_s0_sat_r = 1719,
1735
    M2_vcmpy_s1_sat_i = 1720,
1736
    M2_vcmpy_s1_sat_r = 1721,
1737
    M2_vdmacs_s0  = 1722,
1738
    M2_vdmacs_s1  = 1723,
1739
    M2_vdmpyrs_s0 = 1724,
1740
    M2_vdmpyrs_s1 = 1725,
1741
    M2_vdmpys_s0  = 1726,
1742
    M2_vdmpys_s1  = 1727,
1743
    M2_vmac2  = 1728,
1744
    M2_vmac2es  = 1729,
1745
    M2_vmac2es_s0 = 1730,
1746
    M2_vmac2es_s1 = 1731,
1747
    M2_vmac2s_s0  = 1732,
1748
    M2_vmac2s_s1  = 1733,
1749
    M2_vmac2su_s0 = 1734,
1750
    M2_vmac2su_s1 = 1735,
1751
    M2_vmpy2es_s0 = 1736,
1752
    M2_vmpy2es_s1 = 1737,
1753
    M2_vmpy2s_s0  = 1738,
1754
    M2_vmpy2s_s0pack  = 1739,
1755
    M2_vmpy2s_s1  = 1740,
1756
    M2_vmpy2s_s1pack  = 1741,
1757
    M2_vmpy2su_s0 = 1742,
1758
    M2_vmpy2su_s1 = 1743,
1759
    M2_vraddh = 1744,
1760
    M2_vradduh  = 1745,
1761
    M2_vrcmaci_s0 = 1746,
1762
    M2_vrcmaci_s0c  = 1747,
1763
    M2_vrcmacr_s0 = 1748,
1764
    M2_vrcmacr_s0c  = 1749,
1765
    M2_vrcmpyi_s0 = 1750,
1766
    M2_vrcmpyi_s0c  = 1751,
1767
    M2_vrcmpyr_s0 = 1752,
1768
    M2_vrcmpyr_s0c  = 1753,
1769
    M2_vrcmpys_acc_s1_h = 1754,
1770
    M2_vrcmpys_acc_s1_l = 1755,
1771
    M2_vrcmpys_s1_h = 1756,
1772
    M2_vrcmpys_s1_l = 1757,
1773
    M2_vrcmpys_s1rp_h = 1758,
1774
    M2_vrcmpys_s1rp_l = 1759,
1775
    M2_vrmac_s0 = 1760,
1776
    M2_vrmpy_s0 = 1761,
1777
    M2_xor_xacc = 1762,
1778
    M4_and_and  = 1763,
1779
    M4_and_andn = 1764,
1780
    M4_and_or = 1765,
1781
    M4_and_xor  = 1766,
1782
    M4_cmpyi_wh = 1767,
1783
    M4_cmpyi_whc  = 1768,
1784
    M4_cmpyr_wh = 1769,
1785
    M4_cmpyr_whc  = 1770,
1786
    M4_mac_up_s1_sat  = 1771,
1787
    M4_mpyri_addi = 1772,
1788
    M4_mpyri_addr = 1773,
1789
    M4_mpyri_addr_u2  = 1774,
1790
    M4_mpyrr_addi = 1775,
1791
    M4_mpyrr_addr = 1776,
1792
    M4_nac_up_s1_sat  = 1777,
1793
    M4_or_and = 1778,
1794
    M4_or_andn  = 1779,
1795
    M4_or_or  = 1780,
1796
    M4_or_xor = 1781,
1797
    M4_pmpyw  = 1782,
1798
    M4_pmpyw_acc  = 1783,
1799
    M4_vpmpyh = 1784,
1800
    M4_vpmpyh_acc = 1785,
1801
    M4_vrmpyeh_acc_s0 = 1786,
1802
    M4_vrmpyeh_acc_s1 = 1787,
1803
    M4_vrmpyeh_s0 = 1788,
1804
    M4_vrmpyeh_s1 = 1789,
1805
    M4_vrmpyoh_acc_s0 = 1790,
1806
    M4_vrmpyoh_acc_s1 = 1791,
1807
    M4_vrmpyoh_s0 = 1792,
1808
    M4_vrmpyoh_s1 = 1793,
1809
    M4_xor_and  = 1794,
1810
    M4_xor_andn = 1795,
1811
    M4_xor_or = 1796,
1812
    M4_xor_xacc = 1797,
1813
    M5_vdmacbsu = 1798,
1814
    M5_vdmpybsu = 1799,
1815
    M5_vmacbsu  = 1800,
1816
    M5_vmacbuu  = 1801,
1817
    M5_vmpybsu  = 1802,
1818
    M5_vmpybuu  = 1803,
1819
    M5_vrmacbsu = 1804,
1820
    M5_vrmacbuu = 1805,
1821
    M5_vrmpybsu = 1806,
1822
    M5_vrmpybuu = 1807,
1823
    M6_vabsdiffb  = 1808,
1824
    M6_vabsdiffub = 1809,
1825
    PS_call_stk = 1810,
1826
    PS_callr_nr = 1811,
1827
    PS_jmpret = 1812,
1828
    PS_jmpretf  = 1813,
1829
    PS_jmpretfnew = 1814,
1830
    PS_jmpretfnewpt = 1815,
1831
    PS_jmprett  = 1816,
1832
    PS_jmprettnew = 1817,
1833
    PS_jmprettnewpt = 1818,
1834
    PS_loadrbabs  = 1819,
1835
    PS_loadrdabs  = 1820,
1836
    PS_loadrhabs  = 1821,
1837
    PS_loadriabs  = 1822,
1838
    PS_loadrubabs = 1823,
1839
    PS_loadruhabs = 1824,
1840
    PS_storerbabs = 1825,
1841
    PS_storerbnewabs  = 1826,
1842
    PS_storerdabs = 1827,
1843
    PS_storerfabs = 1828,
1844
    PS_storerhabs = 1829,
1845
    PS_storerhnewabs  = 1830,
1846
    PS_storeriabs = 1831,
1847
    PS_storerinewabs  = 1832,
1848
    RESTORE_DEALLOC_BEFORE_TAILCALL_V4  = 1833,
1849
    RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT  = 1834,
1850
    RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC  = 1835,
1851
    RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC  = 1836,
1852
    RESTORE_DEALLOC_RET_JMP_V4  = 1837,
1853
    RESTORE_DEALLOC_RET_JMP_V4_EXT  = 1838,
1854
    RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC  = 1839,
1855
    RESTORE_DEALLOC_RET_JMP_V4_PIC  = 1840,
1856
    S2_addasl_rrri  = 1841,
1857
    S2_allocframe = 1842,
1858
    S2_asl_i_p  = 1843,
1859
    S2_asl_i_p_acc  = 1844,
1860
    S2_asl_i_p_and  = 1845,
1861
    S2_asl_i_p_nac  = 1846,
1862
    S2_asl_i_p_or = 1847,
1863
    S2_asl_i_p_xacc = 1848,
1864
    S2_asl_i_r  = 1849,
1865
    S2_asl_i_r_acc  = 1850,
1866
    S2_asl_i_r_and  = 1851,
1867
    S2_asl_i_r_nac  = 1852,
1868
    S2_asl_i_r_or = 1853,
1869
    S2_asl_i_r_sat  = 1854,
1870
    S2_asl_i_r_xacc = 1855,
1871
    S2_asl_i_vh = 1856,
1872
    S2_asl_i_vw = 1857,
1873
    S2_asl_r_p  = 1858,
1874
    S2_asl_r_p_acc  = 1859,
1875
    S2_asl_r_p_and  = 1860,
1876
    S2_asl_r_p_nac  = 1861,
1877
    S2_asl_r_p_or = 1862,
1878
    S2_asl_r_p_xor  = 1863,
1879
    S2_asl_r_r  = 1864,
1880
    S2_asl_r_r_acc  = 1865,
1881
    S2_asl_r_r_and  = 1866,
1882
    S2_asl_r_r_nac  = 1867,
1883
    S2_asl_r_r_or = 1868,
1884
    S2_asl_r_r_sat  = 1869,
1885
    S2_asl_r_vh = 1870,
1886
    S2_asl_r_vw = 1871,
1887
    S2_asr_i_p  = 1872,
1888
    S2_asr_i_p_acc  = 1873,
1889
    S2_asr_i_p_and  = 1874,
1890
    S2_asr_i_p_nac  = 1875,
1891
    S2_asr_i_p_or = 1876,
1892
    S2_asr_i_p_rnd  = 1877,
1893
    S2_asr_i_r  = 1878,
1894
    S2_asr_i_r_acc  = 1879,
1895
    S2_asr_i_r_and  = 1880,
1896
    S2_asr_i_r_nac  = 1881,
1897
    S2_asr_i_r_or = 1882,
1898
    S2_asr_i_r_rnd  = 1883,
1899
    S2_asr_i_svw_trun = 1884,
1900
    S2_asr_i_vh = 1885,
1901
    S2_asr_i_vw = 1886,
1902
    S2_asr_r_p  = 1887,
1903
    S2_asr_r_p_acc  = 1888,
1904
    S2_asr_r_p_and  = 1889,
1905
    S2_asr_r_p_nac  = 1890,
1906
    S2_asr_r_p_or = 1891,
1907
    S2_asr_r_p_xor  = 1892,
1908
    S2_asr_r_r  = 1893,
1909
    S2_asr_r_r_acc  = 1894,
1910
    S2_asr_r_r_and  = 1895,
1911
    S2_asr_r_r_nac  = 1896,
1912
    S2_asr_r_r_or = 1897,
1913
    S2_asr_r_r_sat  = 1898,
1914
    S2_asr_r_svw_trun = 1899,
1915
    S2_asr_r_vh = 1900,
1916
    S2_asr_r_vw = 1901,
1917
    S2_brev = 1902,
1918
    S2_brevp  = 1903,
1919
    S2_cabacdecbin  = 1904,
1920
    S2_cl0  = 1905,
1921
    S2_cl0p = 1906,
1922
    S2_cl1  = 1907,
1923
    S2_cl1p = 1908,
1924
    S2_clb  = 1909,
1925
    S2_clbnorm  = 1910,
1926
    S2_clbp = 1911,
1927
    S2_clrbit_i = 1912,
1928
    S2_clrbit_r = 1913,
1929
    S2_ct0  = 1914,
1930
    S2_ct0p = 1915,
1931
    S2_ct1  = 1916,
1932
    S2_ct1p = 1917,
1933
    S2_deinterleave = 1918,
1934
    S2_extractu = 1919,
1935
    S2_extractu_rp  = 1920,
1936
    S2_extractup  = 1921,
1937
    S2_extractup_rp = 1922,
1938
    S2_insert = 1923,
1939
    S2_insert_rp  = 1924,
1940
    S2_insertp  = 1925,
1941
    S2_insertp_rp = 1926,
1942
    S2_interleave = 1927,
1943
    S2_lfsp = 1928,
1944
    S2_lsl_r_p  = 1929,
1945
    S2_lsl_r_p_acc  = 1930,
1946
    S2_lsl_r_p_and  = 1931,
1947
    S2_lsl_r_p_nac  = 1932,
1948
    S2_lsl_r_p_or = 1933,
1949
    S2_lsl_r_p_xor  = 1934,
1950
    S2_lsl_r_r  = 1935,
1951
    S2_lsl_r_r_acc  = 1936,
1952
    S2_lsl_r_r_and  = 1937,
1953
    S2_lsl_r_r_nac  = 1938,
1954
    S2_lsl_r_r_or = 1939,
1955
    S2_lsl_r_vh = 1940,
1956
    S2_lsl_r_vw = 1941,
1957
    S2_lsr_i_p  = 1942,
1958
    S2_lsr_i_p_acc  = 1943,
1959
    S2_lsr_i_p_and  = 1944,
1960
    S2_lsr_i_p_nac  = 1945,
1961
    S2_lsr_i_p_or = 1946,
1962
    S2_lsr_i_p_xacc = 1947,
1963
    S2_lsr_i_r  = 1948,
1964
    S2_lsr_i_r_acc  = 1949,
1965
    S2_lsr_i_r_and  = 1950,
1966
    S2_lsr_i_r_nac  = 1951,
1967
    S2_lsr_i_r_or = 1952,
1968
    S2_lsr_i_r_xacc = 1953,
1969
    S2_lsr_i_vh = 1954,
1970
    S2_lsr_i_vw = 1955,
1971
    S2_lsr_r_p  = 1956,
1972
    S2_lsr_r_p_acc  = 1957,
1973
    S2_lsr_r_p_and  = 1958,
1974
    S2_lsr_r_p_nac  = 1959,
1975
    S2_lsr_r_p_or = 1960,
1976
    S2_lsr_r_p_xor  = 1961,
1977
    S2_lsr_r_r  = 1962,
1978
    S2_lsr_r_r_acc  = 1963,
1979
    S2_lsr_r_r_and  = 1964,
1980
    S2_lsr_r_r_nac  = 1965,
1981
    S2_lsr_r_r_or = 1966,
1982
    S2_lsr_r_vh = 1967,
1983
    S2_lsr_r_vw = 1968,
1984
    S2_packhl = 1969,
1985
    S2_parityp  = 1970,
1986
    S2_pstorerbf_io = 1971,
1987
    S2_pstorerbf_pi = 1972,
1988
    S2_pstorerbfnew_pi  = 1973,
1989
    S2_pstorerbnewf_io  = 1974,
1990
    S2_pstorerbnewf_pi  = 1975,
1991
    S2_pstorerbnewfnew_pi = 1976,
1992
    S2_pstorerbnewt_io  = 1977,
1993
    S2_pstorerbnewt_pi  = 1978,
1994
    S2_pstorerbnewtnew_pi = 1979,
1995
    S2_pstorerbt_io = 1980,
1996
    S2_pstorerbt_pi = 1981,
1997
    S2_pstorerbtnew_pi  = 1982,
1998
    S2_pstorerdf_io = 1983,
1999
    S2_pstorerdf_pi = 1984,
2000
    S2_pstorerdfnew_pi  = 1985,
2001
    S2_pstorerdt_io = 1986,
2002
    S2_pstorerdt_pi = 1987,
2003
    S2_pstorerdtnew_pi  = 1988,
2004
    S2_pstorerff_io = 1989,
2005
    S2_pstorerff_pi = 1990,
2006
    S2_pstorerffnew_pi  = 1991,
2007
    S2_pstorerft_io = 1992,
2008
    S2_pstorerft_pi = 1993,
2009
    S2_pstorerftnew_pi  = 1994,
2010
    S2_pstorerhf_io = 1995,
2011
    S2_pstorerhf_pi = 1996,
2012
    S2_pstorerhfnew_pi  = 1997,
2013
    S2_pstorerhnewf_io  = 1998,
2014
    S2_pstorerhnewf_pi  = 1999,
2015
    S2_pstorerhnewfnew_pi = 2000,
2016
    S2_pstorerhnewt_io  = 2001,
2017
    S2_pstorerhnewt_pi  = 2002,
2018
    S2_pstorerhnewtnew_pi = 2003,
2019
    S2_pstorerht_io = 2004,
2020
    S2_pstorerht_pi = 2005,
2021
    S2_pstorerhtnew_pi  = 2006,
2022
    S2_pstorerif_io = 2007,
2023
    S2_pstorerif_pi = 2008,
2024
    S2_pstorerifnew_pi  = 2009,
2025
    S2_pstorerinewf_io  = 2010,
2026
    S2_pstorerinewf_pi  = 2011,
2027
    S2_pstorerinewfnew_pi = 2012,
2028
    S2_pstorerinewt_io  = 2013,
2029
    S2_pstorerinewt_pi  = 2014,
2030
    S2_pstorerinewtnew_pi = 2015,
2031
    S2_pstorerit_io = 2016,
2032
    S2_pstorerit_pi = 2017,
2033
    S2_pstoreritnew_pi  = 2018,
2034
    S2_setbit_i = 2019,
2035
    S2_setbit_r = 2020,
2036
    S2_shuffeb  = 2021,
2037
    S2_shuffeh  = 2022,
2038
    S2_shuffob  = 2023,
2039
    S2_shuffoh  = 2024,
2040
    S2_storerb_io = 2025,
2041
    S2_storerb_pbr  = 2026,
2042
    S2_storerb_pci  = 2027,
2043
    S2_storerb_pcr  = 2028,
2044
    S2_storerb_pi = 2029,
2045
    S2_storerb_pr = 2030,
2046
    S2_storerbgp  = 2031,
2047
    S2_storerbnew_io  = 2032,
2048
    S2_storerbnew_pbr = 2033,
2049
    S2_storerbnew_pci = 2034,
2050
    S2_storerbnew_pcr = 2035,
2051
    S2_storerbnew_pi  = 2036,
2052
    S2_storerbnew_pr  = 2037,
2053
    S2_storerbnewgp = 2038,
2054
    S2_storerd_io = 2039,
2055
    S2_storerd_pbr  = 2040,
2056
    S2_storerd_pci  = 2041,
2057
    S2_storerd_pcr  = 2042,
2058
    S2_storerd_pi = 2043,
2059
    S2_storerd_pr = 2044,
2060
    S2_storerdgp  = 2045,
2061
    S2_storerf_io = 2046,
2062
    S2_storerf_pbr  = 2047,
2063
    S2_storerf_pci  = 2048,
2064
    S2_storerf_pcr  = 2049,
2065
    S2_storerf_pi = 2050,
2066
    S2_storerf_pr = 2051,
2067
    S2_storerfgp  = 2052,
2068
    S2_storerh_io = 2053,
2069
    S2_storerh_pbr  = 2054,
2070
    S2_storerh_pci  = 2055,
2071
    S2_storerh_pcr  = 2056,
2072
    S2_storerh_pi = 2057,
2073
    S2_storerh_pr = 2058,
2074
    S2_storerhgp  = 2059,
2075
    S2_storerhnew_io  = 2060,
2076
    S2_storerhnew_pbr = 2061,
2077
    S2_storerhnew_pci = 2062,
2078
    S2_storerhnew_pcr = 2063,
2079
    S2_storerhnew_pi  = 2064,
2080
    S2_storerhnew_pr  = 2065,
2081
    S2_storerhnewgp = 2066,
2082
    S2_storeri_io = 2067,
2083
    S2_storeri_pbr  = 2068,
2084
    S2_storeri_pci  = 2069,
2085
    S2_storeri_pcr  = 2070,
2086
    S2_storeri_pi = 2071,
2087
    S2_storeri_pr = 2072,
2088
    S2_storerigp  = 2073,
2089
    S2_storerinew_io  = 2074,
2090
    S2_storerinew_pbr = 2075,
2091
    S2_storerinew_pci = 2076,
2092
    S2_storerinew_pcr = 2077,
2093
    S2_storerinew_pi  = 2078,
2094
    S2_storerinew_pr  = 2079,
2095
    S2_storerinewgp = 2080,
2096
    S2_storew_locked  = 2081,
2097
    S2_svsathb  = 2082,
2098
    S2_svsathub = 2083,
2099
    S2_tableidxb  = 2084,
2100
    S2_tableidxd  = 2085,
2101
    S2_tableidxh  = 2086,
2102
    S2_tableidxw  = 2087,
2103
    S2_togglebit_i  = 2088,
2104
    S2_togglebit_r  = 2089,
2105
    S2_tstbit_i = 2090,
2106
    S2_tstbit_r = 2091,
2107
    S2_valignib = 2092,
2108
    S2_valignrb = 2093,
2109
    S2_vcnegh = 2094,
2110
    S2_vcrotate = 2095,
2111
    S2_vrcnegh  = 2096,
2112
    S2_vrndpackwh = 2097,
2113
    S2_vrndpackwhs  = 2098,
2114
    S2_vsathb = 2099,
2115
    S2_vsathb_nopack  = 2100,
2116
    S2_vsathub  = 2101,
2117
    S2_vsathub_nopack = 2102,
2118
    S2_vsatwh = 2103,
2119
    S2_vsatwh_nopack  = 2104,
2120
    S2_vsatwuh  = 2105,
2121
    S2_vsatwuh_nopack = 2106,
2122
    S2_vsplatrb = 2107,
2123
    S2_vsplatrh = 2108,
2124
    S2_vspliceib  = 2109,
2125
    S2_vsplicerb  = 2110,
2126
    S2_vsxtbh = 2111,
2127
    S2_vsxthw = 2112,
2128
    S2_vtrunehb = 2113,
2129
    S2_vtrunewh = 2114,
2130
    S2_vtrunohb = 2115,
2131
    S2_vtrunowh = 2116,
2132
    S2_vzxtbh = 2117,
2133
    S2_vzxthw = 2118,
2134
    S4_addaddi  = 2119,
2135
    S4_addi_asl_ri  = 2120,
2136
    S4_addi_lsr_ri  = 2121,
2137
    S4_andi_asl_ri  = 2122,
2138
    S4_andi_lsr_ri  = 2123,
2139
    S4_clbaddi  = 2124,
2140
    S4_clbpaddi = 2125,
2141
    S4_clbpnorm = 2126,
2142
    S4_extract  = 2127,
2143
    S4_extract_rp = 2128,
2144
    S4_extractp = 2129,
2145
    S4_extractp_rp  = 2130,
2146
    S4_lsli = 2131,
2147
    S4_ntstbit_i  = 2132,
2148
    S4_ntstbit_r  = 2133,
2149
    S4_or_andi  = 2134,
2150
    S4_or_andix = 2135,
2151
    S4_or_ori = 2136,
2152
    S4_ori_asl_ri = 2137,
2153
    S4_ori_lsr_ri = 2138,
2154
    S4_parity = 2139,
2155
    S4_pstorerbf_abs  = 2140,
2156
    S4_pstorerbf_rr = 2141,
2157
    S4_pstorerbfnew_abs = 2142,
2158
    S4_pstorerbfnew_io  = 2143,
2159
    S4_pstorerbfnew_rr  = 2144,
2160
    S4_pstorerbnewf_abs = 2145,
2161
    S4_pstorerbnewf_rr  = 2146,
2162
    S4_pstorerbnewfnew_abs  = 2147,
2163
    S4_pstorerbnewfnew_io = 2148,
2164
    S4_pstorerbnewfnew_rr = 2149,
2165
    S4_pstorerbnewt_abs = 2150,
2166
    S4_pstorerbnewt_rr  = 2151,
2167
    S4_pstorerbnewtnew_abs  = 2152,
2168
    S4_pstorerbnewtnew_io = 2153,
2169
    S4_pstorerbnewtnew_rr = 2154,
2170
    S4_pstorerbt_abs  = 2155,
2171
    S4_pstorerbt_rr = 2156,
2172
    S4_pstorerbtnew_abs = 2157,
2173
    S4_pstorerbtnew_io  = 2158,
2174
    S4_pstorerbtnew_rr  = 2159,
2175
    S4_pstorerdf_abs  = 2160,
2176
    S4_pstorerdf_rr = 2161,
2177
    S4_pstorerdfnew_abs = 2162,
2178
    S4_pstorerdfnew_io  = 2163,
2179
    S4_pstorerdfnew_rr  = 2164,
2180
    S4_pstorerdt_abs  = 2165,
2181
    S4_pstorerdt_rr = 2166,
2182
    S4_pstorerdtnew_abs = 2167,
2183
    S4_pstorerdtnew_io  = 2168,
2184
    S4_pstorerdtnew_rr  = 2169,
2185
    S4_pstorerff_abs  = 2170,
2186
    S4_pstorerff_rr = 2171,
2187
    S4_pstorerffnew_abs = 2172,
2188
    S4_pstorerffnew_io  = 2173,
2189
    S4_pstorerffnew_rr  = 2174,
2190
    S4_pstorerft_abs  = 2175,
2191
    S4_pstorerft_rr = 2176,
2192
    S4_pstorerftnew_abs = 2177,
2193
    S4_pstorerftnew_io  = 2178,
2194
    S4_pstorerftnew_rr  = 2179,
2195
    S4_pstorerhf_abs  = 2180,
2196
    S4_pstorerhf_rr = 2181,
2197
    S4_pstorerhfnew_abs = 2182,
2198
    S4_pstorerhfnew_io  = 2183,
2199
    S4_pstorerhfnew_rr  = 2184,
2200
    S4_pstorerhnewf_abs = 2185,
2201
    S4_pstorerhnewf_rr  = 2186,
2202
    S4_pstorerhnewfnew_abs  = 2187,
2203
    S4_pstorerhnewfnew_io = 2188,
2204
    S4_pstorerhnewfnew_rr = 2189,
2205
    S4_pstorerhnewt_abs = 2190,
2206
    S4_pstorerhnewt_rr  = 2191,
2207
    S4_pstorerhnewtnew_abs  = 2192,
2208
    S4_pstorerhnewtnew_io = 2193,
2209
    S4_pstorerhnewtnew_rr = 2194,
2210
    S4_pstorerht_abs  = 2195,
2211
    S4_pstorerht_rr = 2196,
2212
    S4_pstorerhtnew_abs = 2197,
2213
    S4_pstorerhtnew_io  = 2198,
2214
    S4_pstorerhtnew_rr  = 2199,
2215
    S4_pstorerif_abs  = 2200,
2216
    S4_pstorerif_rr = 2201,
2217
    S4_pstorerifnew_abs = 2202,
2218
    S4_pstorerifnew_io  = 2203,
2219
    S4_pstorerifnew_rr  = 2204,
2220
    S4_pstorerinewf_abs = 2205,
2221
    S4_pstorerinewf_rr  = 2206,
2222
    S4_pstorerinewfnew_abs  = 2207,
2223
    S4_pstorerinewfnew_io = 2208,
2224
    S4_pstorerinewfnew_rr = 2209,
2225
    S4_pstorerinewt_abs = 2210,
2226
    S4_pstorerinewt_rr  = 2211,
2227
    S4_pstorerinewtnew_abs  = 2212,
2228
    S4_pstorerinewtnew_io = 2213,
2229
    S4_pstorerinewtnew_rr = 2214,
2230
    S4_pstorerit_abs  = 2215,
2231
    S4_pstorerit_rr = 2216,
2232
    S4_pstoreritnew_abs = 2217,
2233
    S4_pstoreritnew_io  = 2218,
2234
    S4_pstoreritnew_rr  = 2219,
2235
    S4_stored_locked  = 2220,
2236
    S4_storeirb_io  = 2221,
2237
    S4_storeirbf_io = 2222,
2238
    S4_storeirbfnew_io  = 2223,
2239
    S4_storeirbt_io = 2224,
2240
    S4_storeirbtnew_io  = 2225,
2241
    S4_storeirh_io  = 2226,
2242
    S4_storeirhf_io = 2227,
2243
    S4_storeirhfnew_io  = 2228,
2244
    S4_storeirht_io = 2229,
2245
    S4_storeirhtnew_io  = 2230,
2246
    S4_storeiri_io  = 2231,
2247
    S4_storeirif_io = 2232,
2248
    S4_storeirifnew_io  = 2233,
2249
    S4_storeirit_io = 2234,
2250
    S4_storeiritnew_io  = 2235,
2251
    S4_storerb_ap = 2236,
2252
    S4_storerb_rr = 2237,
2253
    S4_storerb_ur = 2238,
2254
    S4_storerbnew_ap  = 2239,
2255
    S4_storerbnew_rr  = 2240,
2256
    S4_storerbnew_ur  = 2241,
2257
    S4_storerd_ap = 2242,
2258
    S4_storerd_rr = 2243,
2259
    S4_storerd_ur = 2244,
2260
    S4_storerf_ap = 2245,
2261
    S4_storerf_rr = 2246,
2262
    S4_storerf_ur = 2247,
2263
    S4_storerh_ap = 2248,
2264
    S4_storerh_rr = 2249,
2265
    S4_storerh_ur = 2250,
2266
    S4_storerhnew_ap  = 2251,
2267
    S4_storerhnew_rr  = 2252,
2268
    S4_storerhnew_ur  = 2253,
2269
    S4_storeri_ap = 2254,
2270
    S4_storeri_rr = 2255,
2271
    S4_storeri_ur = 2256,
2272
    S4_storerinew_ap  = 2257,
2273
    S4_storerinew_rr  = 2258,
2274
    S4_storerinew_ur  = 2259,
2275
    S4_subaddi  = 2260,
2276
    S4_subi_asl_ri  = 2261,
2277
    S4_subi_lsr_ri  = 2262,
2278
    S4_vrcrotate  = 2263,
2279
    S4_vrcrotate_acc  = 2264,
2280
    S4_vxaddsubh  = 2265,
2281
    S4_vxaddsubhr = 2266,
2282
    S4_vxaddsubw  = 2267,
2283
    S4_vxsubaddh  = 2268,
2284
    S4_vxsubaddhr = 2269,
2285
    S4_vxsubaddw  = 2270,
2286
    S5_asrhub_rnd_sat = 2271,
2287
    S5_asrhub_sat = 2272,
2288
    S5_popcountp  = 2273,
2289
    S5_vasrhrnd = 2274,
2290
    S6_rol_i_p  = 2275,
2291
    S6_rol_i_p_acc  = 2276,
2292
    S6_rol_i_p_and  = 2277,
2293
    S6_rol_i_p_nac  = 2278,
2294
    S6_rol_i_p_or = 2279,
2295
    S6_rol_i_p_xacc = 2280,
2296
    S6_rol_i_r  = 2281,
2297
    S6_rol_i_r_acc  = 2282,
2298
    S6_rol_i_r_and  = 2283,
2299
    S6_rol_i_r_nac  = 2284,
2300
    S6_rol_i_r_or = 2285,
2301
    S6_rol_i_r_xacc = 2286,
2302
    S6_vsplatrbp  = 2287,
2303
    S6_vtrunehb_ppp = 2288,
2304
    S6_vtrunohb_ppp = 2289,
2305
    SA1_addi  = 2290,
2306
    SA1_addrx = 2291,
2307
    SA1_addsp = 2292,
2308
    SA1_and1  = 2293,
2309
    SA1_clrf  = 2294,
2310
    SA1_clrfnew = 2295,
2311
    SA1_clrt  = 2296,
2312
    SA1_clrtnew = 2297,
2313
    SA1_cmpeqi  = 2298,
2314
    SA1_combine0i = 2299,
2315
    SA1_combine1i = 2300,
2316
    SA1_combine2i = 2301,
2317
    SA1_combine3i = 2302,
2318
    SA1_combinerz = 2303,
2319
    SA1_combinezr = 2304,
2320
    SA1_dec = 2305,
2321
    SA1_inc = 2306,
2322
    SA1_seti  = 2307,
2323
    SA1_setin1  = 2308,
2324
    SA1_sxtb  = 2309,
2325
    SA1_sxth  = 2310,
2326
    SA1_tfr = 2311,
2327
    SA1_zxtb  = 2312,
2328
    SA1_zxth  = 2313,
2329
    SAVE_REGISTERS_CALL_V4  = 2314,
2330
    SAVE_REGISTERS_CALL_V4STK = 2315,
2331
    SAVE_REGISTERS_CALL_V4STK_EXT = 2316,
2332
    SAVE_REGISTERS_CALL_V4STK_EXT_PIC = 2317,
2333
    SAVE_REGISTERS_CALL_V4STK_PIC = 2318,
2334
    SAVE_REGISTERS_CALL_V4_EXT  = 2319,
2335
    SAVE_REGISTERS_CALL_V4_EXT_PIC  = 2320,
2336
    SAVE_REGISTERS_CALL_V4_PIC  = 2321,
2337
    SL1_loadri_io = 2322,
2338
    SL1_loadrub_io  = 2323,
2339
    SL2_deallocframe  = 2324,
2340
    SL2_jumpr31 = 2325,
2341
    SL2_jumpr31_f = 2326,
2342
    SL2_jumpr31_fnew  = 2327,
2343
    SL2_jumpr31_t = 2328,
2344
    SL2_jumpr31_tnew  = 2329,
2345
    SL2_loadrb_io = 2330,
2346
    SL2_loadrd_sp = 2331,
2347
    SL2_loadrh_io = 2332,
2348
    SL2_loadri_sp = 2333,
2349
    SL2_loadruh_io  = 2334,
2350
    SL2_return  = 2335,
2351
    SL2_return_f  = 2336,
2352
    SL2_return_fnew = 2337,
2353
    SL2_return_t  = 2338,
2354
    SL2_return_tnew = 2339,
2355
    SS1_storeb_io = 2340,
2356
    SS1_storew_io = 2341,
2357
    SS2_allocframe  = 2342,
2358
    SS2_storebi0  = 2343,
2359
    SS2_storebi1  = 2344,
2360
    SS2_stored_sp = 2345,
2361
    SS2_storeh_io = 2346,
2362
    SS2_storew_sp = 2347,
2363
    SS2_storewi0  = 2348,
2364
    SS2_storewi1  = 2349,
2365
    TFRI64_V2_ext = 2350,
2366
    TFRI64_V4 = 2351,
2367
    V6_extractw = 2352,
2368
    V6_lvsplatb = 2353,
2369
    V6_lvsplath = 2354,
2370
    V6_lvsplatw = 2355,
2371
    V6_pred_and = 2356,
2372
    V6_pred_and_n = 2357,
2373
    V6_pred_not = 2358,
2374
    V6_pred_or  = 2359,
2375
    V6_pred_or_n  = 2360,
2376
    V6_pred_scalar2 = 2361,
2377
    V6_pred_scalar2v2 = 2362,
2378
    V6_pred_xor = 2363,
2379
    V6_shuffeqh = 2364,
2380
    V6_shuffeqw = 2365,
2381
    V6_vL32Ub_ai  = 2366,
2382
    V6_vL32Ub_pi  = 2367,
2383
    V6_vL32Ub_ppu = 2368,
2384
    V6_vL32b_ai = 2369,
2385
    V6_vL32b_cur_ai = 2370,
2386
    V6_vL32b_cur_npred_ai = 2371,
2387
    V6_vL32b_cur_npred_pi = 2372,
2388
    V6_vL32b_cur_npred_ppu  = 2373,
2389
    V6_vL32b_cur_pi = 2374,
2390
    V6_vL32b_cur_ppu  = 2375,
2391
    V6_vL32b_cur_pred_ai  = 2376,
2392
    V6_vL32b_cur_pred_pi  = 2377,
2393
    V6_vL32b_cur_pred_ppu = 2378,
2394
    V6_vL32b_npred_ai = 2379,
2395
    V6_vL32b_npred_pi = 2380,
2396
    V6_vL32b_npred_ppu  = 2381,
2397
    V6_vL32b_nt_ai  = 2382,
2398
    V6_vL32b_nt_cur_ai  = 2383,
2399
    V6_vL32b_nt_cur_npred_ai  = 2384,
2400
    V6_vL32b_nt_cur_npred_pi  = 2385,
2401
    V6_vL32b_nt_cur_npred_ppu = 2386,
2402
    V6_vL32b_nt_cur_pi  = 2387,
2403
    V6_vL32b_nt_cur_ppu = 2388,
2404
    V6_vL32b_nt_cur_pred_ai = 2389,
2405
    V6_vL32b_nt_cur_pred_pi = 2390,
2406
    V6_vL32b_nt_cur_pred_ppu  = 2391,
2407
    V6_vL32b_nt_npred_ai  = 2392,
2408
    V6_vL32b_nt_npred_pi  = 2393,
2409
    V6_vL32b_nt_npred_ppu = 2394,
2410
    V6_vL32b_nt_pi  = 2395,
2411
    V6_vL32b_nt_ppu = 2396,
2412
    V6_vL32b_nt_pred_ai = 2397,
2413
    V6_vL32b_nt_pred_pi = 2398,
2414
    V6_vL32b_nt_pred_ppu  = 2399,
2415
    V6_vL32b_nt_tmp_ai  = 2400,
2416
    V6_vL32b_nt_tmp_npred_ai  = 2401,
2417
    V6_vL32b_nt_tmp_npred_pi  = 2402,
2418
    V6_vL32b_nt_tmp_npred_ppu = 2403,
2419
    V6_vL32b_nt_tmp_pi  = 2404,
2420
    V6_vL32b_nt_tmp_ppu = 2405,
2421
    V6_vL32b_nt_tmp_pred_ai = 2406,
2422
    V6_vL32b_nt_tmp_pred_pi = 2407,
2423
    V6_vL32b_nt_tmp_pred_ppu  = 2408,
2424
    V6_vL32b_pi = 2409,
2425
    V6_vL32b_ppu  = 2410,
2426
    V6_vL32b_pred_ai  = 2411,
2427
    V6_vL32b_pred_pi  = 2412,
2428
    V6_vL32b_pred_ppu = 2413,
2429
    V6_vL32b_tmp_ai = 2414,
2430
    V6_vL32b_tmp_npred_ai = 2415,
2431
    V6_vL32b_tmp_npred_pi = 2416,
2432
    V6_vL32b_tmp_npred_ppu  = 2417,
2433
    V6_vL32b_tmp_pi = 2418,
2434
    V6_vL32b_tmp_ppu  = 2419,
2435
    V6_vL32b_tmp_pred_ai  = 2420,
2436
    V6_vL32b_tmp_pred_pi  = 2421,
2437
    V6_vL32b_tmp_pred_ppu = 2422,
2438
    V6_vS32Ub_ai  = 2423,
2439
    V6_vS32Ub_npred_ai  = 2424,
2440
    V6_vS32Ub_npred_pi  = 2425,
2441
    V6_vS32Ub_npred_ppu = 2426,
2442
    V6_vS32Ub_pi  = 2427,
2443
    V6_vS32Ub_ppu = 2428,
2444
    V6_vS32Ub_pred_ai = 2429,
2445
    V6_vS32Ub_pred_pi = 2430,
2446
    V6_vS32Ub_pred_ppu  = 2431,
2447
    V6_vS32b_ai = 2432,
2448
    V6_vS32b_new_ai = 2433,
2449
    V6_vS32b_new_npred_ai = 2434,
2450
    V6_vS32b_new_npred_pi = 2435,
2451
    V6_vS32b_new_npred_ppu  = 2436,
2452
    V6_vS32b_new_pi = 2437,
2453
    V6_vS32b_new_ppu  = 2438,
2454
    V6_vS32b_new_pred_ai  = 2439,
2455
    V6_vS32b_new_pred_pi  = 2440,
2456
    V6_vS32b_new_pred_ppu = 2441,
2457
    V6_vS32b_npred_ai = 2442,
2458
    V6_vS32b_npred_pi = 2443,
2459
    V6_vS32b_npred_ppu  = 2444,
2460
    V6_vS32b_nqpred_ai  = 2445,
2461
    V6_vS32b_nqpred_pi  = 2446,
2462
    V6_vS32b_nqpred_ppu = 2447,
2463
    V6_vS32b_nt_ai  = 2448,
2464
    V6_vS32b_nt_new_ai  = 2449,
2465
    V6_vS32b_nt_new_npred_ai  = 2450,
2466
    V6_vS32b_nt_new_npred_pi  = 2451,
2467
    V6_vS32b_nt_new_npred_ppu = 2452,
2468
    V6_vS32b_nt_new_pi  = 2453,
2469
    V6_vS32b_nt_new_ppu = 2454,
2470
    V6_vS32b_nt_new_pred_ai = 2455,
2471
    V6_vS32b_nt_new_pred_pi = 2456,
2472
    V6_vS32b_nt_new_pred_ppu  = 2457,
2473
    V6_vS32b_nt_npred_ai  = 2458,
2474
    V6_vS32b_nt_npred_pi  = 2459,
2475
    V6_vS32b_nt_npred_ppu = 2460,
2476
    V6_vS32b_nt_nqpred_ai = 2461,
2477
    V6_vS32b_nt_nqpred_pi = 2462,
2478
    V6_vS32b_nt_nqpred_ppu  = 2463,
2479
    V6_vS32b_nt_pi  = 2464,
2480
    V6_vS32b_nt_ppu = 2465,
2481
    V6_vS32b_nt_pred_ai = 2466,
2482
    V6_vS32b_nt_pred_pi = 2467,
2483
    V6_vS32b_nt_pred_ppu  = 2468,
2484
    V6_vS32b_nt_qpred_ai  = 2469,
2485
    V6_vS32b_nt_qpred_pi  = 2470,
2486
    V6_vS32b_nt_qpred_ppu = 2471,
2487
    V6_vS32b_pi = 2472,
2488
    V6_vS32b_ppu  = 2473,
2489
    V6_vS32b_pred_ai  = 2474,
2490
    V6_vS32b_pred_pi  = 2475,
2491
    V6_vS32b_pred_ppu = 2476,
2492
    V6_vS32b_qpred_ai = 2477,
2493
    V6_vS32b_qpred_pi = 2478,
2494
    V6_vS32b_qpred_ppu  = 2479,
2495
    V6_vS32b_srls_ai  = 2480,
2496
    V6_vS32b_srls_pi  = 2481,
2497
    V6_vS32b_srls_ppu = 2482,
2498
    V6_vabsb  = 2483,
2499
    V6_vabsb_sat  = 2484,
2500
    V6_vabsdiffh  = 2485,
2501
    V6_vabsdiffub = 2486,
2502
    V6_vabsdiffuh = 2487,
2503
    V6_vabsdiffw  = 2488,
2504
    V6_vabsh  = 2489,
2505
    V6_vabsh_sat  = 2490,
2506
    V6_vabsw  = 2491,
2507
    V6_vabsw_sat  = 2492,
2508
    V6_vaddb  = 2493,
2509
    V6_vaddb_dv = 2494,
2510
    V6_vaddbnq  = 2495,
2511
    V6_vaddbq = 2496,
2512
    V6_vaddbsat = 2497,
2513
    V6_vaddbsat_dv  = 2498,
2514
    V6_vaddcarry  = 2499,
2515
    V6_vaddclbh = 2500,
2516
    V6_vaddclbw = 2501,
2517
    V6_vaddh  = 2502,
2518
    V6_vaddh_dv = 2503,
2519
    V6_vaddhnq  = 2504,
2520
    V6_vaddhq = 2505,
2521
    V6_vaddhsat = 2506,
2522
    V6_vaddhsat_dv  = 2507,
2523
    V6_vaddhw = 2508,
2524
    V6_vaddhw_acc = 2509,
2525
    V6_vaddubh  = 2510,
2526
    V6_vaddubh_acc  = 2511,
2527
    V6_vaddubsat  = 2512,
2528
    V6_vaddubsat_dv = 2513,
2529
    V6_vaddububb_sat  = 2514,
2530
    V6_vadduhsat  = 2515,
2531
    V6_vadduhsat_dv = 2516,
2532
    V6_vadduhw  = 2517,
2533
    V6_vadduhw_acc  = 2518,
2534
    V6_vadduwsat  = 2519,
2535
    V6_vadduwsat_dv = 2520,
2536
    V6_vaddw  = 2521,
2537
    V6_vaddw_dv = 2522,
2538
    V6_vaddwnq  = 2523,
2539
    V6_vaddwq = 2524,
2540
    V6_vaddwsat = 2525,
2541
    V6_vaddwsat_dv  = 2526,
2542
    V6_valignb  = 2527,
2543
    V6_valignbi = 2528,
2544
    V6_vand = 2529,
2545
    V6_vandnqrt = 2530,
2546
    V6_vandnqrt_acc = 2531,
2547
    V6_vandqrt  = 2532,
2548
    V6_vandqrt_acc  = 2533,
2549
    V6_vandvnqv = 2534,
2550
    V6_vandvqv  = 2535,
2551
    V6_vandvrt  = 2536,
2552
    V6_vandvrt_acc  = 2537,
2553
    V6_vaslh  = 2538,
2554
    V6_vaslh_acc  = 2539,
2555
    V6_vaslhv = 2540,
2556
    V6_vaslw  = 2541,
2557
    V6_vaslw_acc  = 2542,
2558
    V6_vaslwv = 2543,
2559
    V6_vasrh  = 2544,
2560
    V6_vasrh_acc  = 2545,
2561
    V6_vasrhbrndsat = 2546,
2562
    V6_vasrhbsat  = 2547,
2563
    V6_vasrhubrndsat  = 2548,
2564
    V6_vasrhubsat = 2549,
2565
    V6_vasrhv = 2550,
2566
    V6_vasruhubrndsat = 2551,
2567
    V6_vasruhubsat  = 2552,
2568
    V6_vasruwuhrndsat = 2553,
2569
    V6_vasruwuhsat  = 2554,
2570
    V6_vasrw  = 2555,
2571
    V6_vasrw_acc  = 2556,
2572
    V6_vasrwh = 2557,
2573
    V6_vasrwhrndsat = 2558,
2574
    V6_vasrwhsat  = 2559,
2575
    V6_vasrwuhrndsat  = 2560,
2576
    V6_vasrwuhsat = 2561,
2577
    V6_vasrwv = 2562,
2578
    V6_vassign  = 2563,
2579
    V6_vavgb  = 2564,
2580
    V6_vavgbrnd = 2565,
2581
    V6_vavgh  = 2566,
2582
    V6_vavghrnd = 2567,
2583
    V6_vavgub = 2568,
2584
    V6_vavgubrnd  = 2569,
2585
    V6_vavguh = 2570,
2586
    V6_vavguhrnd  = 2571,
2587
    V6_vavguw = 2572,
2588
    V6_vavguwrnd  = 2573,
2589
    V6_vavgw  = 2574,
2590
    V6_vavgwrnd = 2575,
2591
    V6_vccombine  = 2576,
2592
    V6_vcl0h  = 2577,
2593
    V6_vcl0w  = 2578,
2594
    V6_vcmov  = 2579,
2595
    V6_vcombine = 2580,
2596
    V6_vdeal  = 2581,
2597
    V6_vdealb = 2582,
2598
    V6_vdealb4w = 2583,
2599
    V6_vdealh = 2584,
2600
    V6_vdealvdd = 2585,
2601
    V6_vdelta = 2586,
2602
    V6_vdmpybus = 2587,
2603
    V6_vdmpybus_acc = 2588,
2604
    V6_vdmpybus_dv  = 2589,
2605
    V6_vdmpybus_dv_acc  = 2590,
2606
    V6_vdmpyhb  = 2591,
2607
    V6_vdmpyhb_acc  = 2592,
2608
    V6_vdmpyhb_dv = 2593,
2609
    V6_vdmpyhb_dv_acc = 2594,
2610
    V6_vdmpyhisat = 2595,
2611
    V6_vdmpyhisat_acc = 2596,
2612
    V6_vdmpyhsat  = 2597,
2613
    V6_vdmpyhsat_acc  = 2598,
2614
    V6_vdmpyhsuisat = 2599,
2615
    V6_vdmpyhsuisat_acc = 2600,
2616
    V6_vdmpyhsusat  = 2601,
2617
    V6_vdmpyhsusat_acc  = 2602,
2618
    V6_vdmpyhvsat = 2603,
2619
    V6_vdmpyhvsat_acc = 2604,
2620
    V6_vdsaduh  = 2605,
2621
    V6_vdsaduh_acc  = 2606,
2622
    V6_veqb = 2607,
2623
    V6_veqb_and = 2608,
2624
    V6_veqb_or  = 2609,
2625
    V6_veqb_xor = 2610,
2626
    V6_veqh = 2611,
2627
    V6_veqh_and = 2612,
2628
    V6_veqh_or  = 2613,
2629
    V6_veqh_xor = 2614,
2630
    V6_veqw = 2615,
2631
    V6_veqw_and = 2616,
2632
    V6_veqw_or  = 2617,
2633
    V6_veqw_xor = 2618,
2634
    V6_vgathermh  = 2619,
2635
    V6_vgathermhq = 2620,
2636
    V6_vgathermhw = 2621,
2637
    V6_vgathermhwq  = 2622,
2638
    V6_vgathermw  = 2623,
2639
    V6_vgathermwq = 2624,
2640
    V6_vgtb = 2625,
2641
    V6_vgtb_and = 2626,
2642
    V6_vgtb_or  = 2627,
2643
    V6_vgtb_xor = 2628,
2644
    V6_vgth = 2629,
2645
    V6_vgth_and = 2630,
2646
    V6_vgth_or  = 2631,
2647
    V6_vgth_xor = 2632,
2648
    V6_vgtub  = 2633,
2649
    V6_vgtub_and  = 2634,
2650
    V6_vgtub_or = 2635,
2651
    V6_vgtub_xor  = 2636,
2652
    V6_vgtuh  = 2637,
2653
    V6_vgtuh_and  = 2638,
2654
    V6_vgtuh_or = 2639,
2655
    V6_vgtuh_xor  = 2640,
2656
    V6_vgtuw  = 2641,
2657
    V6_vgtuw_and  = 2642,
2658
    V6_vgtuw_or = 2643,
2659
    V6_vgtuw_xor  = 2644,
2660
    V6_vgtw = 2645,
2661
    V6_vgtw_and = 2646,
2662
    V6_vgtw_or  = 2647,
2663
    V6_vgtw_xor = 2648,
2664
    V6_vhist  = 2649,
2665
    V6_vhistq = 2650,
2666
    V6_vinsertwr  = 2651,
2667
    V6_vlalignb = 2652,
2668
    V6_vlalignbi  = 2653,
2669
    V6_vlsrb  = 2654,
2670
    V6_vlsrh  = 2655,
2671
    V6_vlsrhv = 2656,
2672
    V6_vlsrw  = 2657,
2673
    V6_vlsrwv = 2658,
2674
    V6_vlut4  = 2659,
2675
    V6_vlutvvb  = 2660,
2676
    V6_vlutvvb_nm = 2661,
2677
    V6_vlutvvb_oracc  = 2662,
2678
    V6_vlutvvb_oracci = 2663,
2679
    V6_vlutvvbi = 2664,
2680
    V6_vlutvwh  = 2665,
2681
    V6_vlutvwh_nm = 2666,
2682
    V6_vlutvwh_oracc  = 2667,
2683
    V6_vlutvwh_oracci = 2668,
2684
    V6_vlutvwhi = 2669,
2685
    V6_vmaxb  = 2670,
2686
    V6_vmaxh  = 2671,
2687
    V6_vmaxub = 2672,
2688
    V6_vmaxuh = 2673,
2689
    V6_vmaxw  = 2674,
2690
    V6_vminb  = 2675,
2691
    V6_vminh  = 2676,
2692
    V6_vminub = 2677,
2693
    V6_vminuh = 2678,
2694
    V6_vminw  = 2679,
2695
    V6_vmpabus  = 2680,
2696
    V6_vmpabus_acc  = 2681,
2697
    V6_vmpabusv = 2682,
2698
    V6_vmpabuu  = 2683,
2699
    V6_vmpabuu_acc  = 2684,
2700
    V6_vmpabuuv = 2685,
2701
    V6_vmpahb = 2686,
2702
    V6_vmpahb_acc = 2687,
2703
    V6_vmpahhsat  = 2688,
2704
    V6_vmpauhb  = 2689,
2705
    V6_vmpauhb_acc  = 2690,
2706
    V6_vmpauhuhsat  = 2691,
2707
    V6_vmpsuhuhsat  = 2692,
2708
    V6_vmpybus  = 2693,
2709
    V6_vmpybus_acc  = 2694,
2710
    V6_vmpybusv = 2695,
2711
    V6_vmpybusv_acc = 2696,
2712
    V6_vmpybv = 2697,
2713
    V6_vmpybv_acc = 2698,
2714
    V6_vmpyewuh = 2699,
2715
    V6_vmpyewuh_64  = 2700,
2716
    V6_vmpyh  = 2701,
2717
    V6_vmpyh_acc  = 2702,
2718
    V6_vmpyhsat_acc = 2703,
2719
    V6_vmpyhsrs = 2704,
2720
    V6_vmpyhss  = 2705,
2721
    V6_vmpyhus  = 2706,
2722
    V6_vmpyhus_acc  = 2707,
2723
    V6_vmpyhv = 2708,
2724
    V6_vmpyhv_acc = 2709,
2725
    V6_vmpyhvsrs  = 2710,
2726
    V6_vmpyieoh = 2711,
2727
    V6_vmpyiewh_acc = 2712,
2728
    V6_vmpyiewuh  = 2713,
2729
    V6_vmpyiewuh_acc  = 2714,
2730
    V6_vmpyih = 2715,
2731
    V6_vmpyih_acc = 2716,
2732
    V6_vmpyihb  = 2717,
2733
    V6_vmpyihb_acc  = 2718,
2734
    V6_vmpyiowh = 2719,
2735
    V6_vmpyiwb  = 2720,
2736
    V6_vmpyiwb_acc  = 2721,
2737
    V6_vmpyiwh  = 2722,
2738
    V6_vmpyiwh_acc  = 2723,
2739
    V6_vmpyiwub = 2724,
2740
    V6_vmpyiwub_acc = 2725,
2741
    V6_vmpyowh  = 2726,
2742
    V6_vmpyowh_64_acc = 2727,
2743
    V6_vmpyowh_rnd  = 2728,
2744
    V6_vmpyowh_rnd_sacc = 2729,
2745
    V6_vmpyowh_sacc = 2730,
2746
    V6_vmpyub = 2731,
2747
    V6_vmpyub_acc = 2732,
2748
    V6_vmpyubv  = 2733,
2749
    V6_vmpyubv_acc  = 2734,
2750
    V6_vmpyuh = 2735,
2751
    V6_vmpyuh_acc = 2736,
2752
    V6_vmpyuhe  = 2737,
2753
    V6_vmpyuhe_acc  = 2738,
2754
    V6_vmpyuhv  = 2739,
2755
    V6_vmpyuhv_acc  = 2740,
2756
    V6_vmux = 2741,
2757
    V6_vnavgb = 2742,
2758
    V6_vnavgh = 2743,
2759
    V6_vnavgub  = 2744,
2760
    V6_vnavgw = 2745,
2761
    V6_vnccombine = 2746,
2762
    V6_vncmov = 2747,
2763
    V6_vnormamth  = 2748,
2764
    V6_vnormamtw  = 2749,
2765
    V6_vnot = 2750,
2766
    V6_vor  = 2751,
2767
    V6_vpackeb  = 2752,
2768
    V6_vpackeh  = 2753,
2769
    V6_vpackhb_sat  = 2754,
2770
    V6_vpackhub_sat = 2755,
2771
    V6_vpackob  = 2756,
2772
    V6_vpackoh  = 2757,
2773
    V6_vpackwh_sat  = 2758,
2774
    V6_vpackwuh_sat = 2759,
2775
    V6_vpopcounth = 2760,
2776
    V6_vprefixqb  = 2761,
2777
    V6_vprefixqh  = 2762,
2778
    V6_vprefixqw  = 2763,
2779
    V6_vrdelta  = 2764,
2780
    V6_vrmpybub_rtt = 2765,
2781
    V6_vrmpybub_rtt_acc = 2766,
2782
    V6_vrmpybus = 2767,
2783
    V6_vrmpybus_acc = 2768,
2784
    V6_vrmpybusi  = 2769,
2785
    V6_vrmpybusi_acc  = 2770,
2786
    V6_vrmpybusv  = 2771,
2787
    V6_vrmpybusv_acc  = 2772,
2788
    V6_vrmpybv  = 2773,
2789
    V6_vrmpybv_acc  = 2774,
2790
    V6_vrmpyub  = 2775,
2791
    V6_vrmpyub_acc  = 2776,
2792
    V6_vrmpyub_rtt  = 2777,
2793
    V6_vrmpyub_rtt_acc  = 2778,
2794
    V6_vrmpyubi = 2779,
2795
    V6_vrmpyubi_acc = 2780,
2796
    V6_vrmpyubv = 2781,
2797
    V6_vrmpyubv_acc = 2782,
2798
    V6_vror = 2783,
2799
    V6_vroundhb = 2784,
2800
    V6_vroundhub  = 2785,
2801
    V6_vrounduhub = 2786,
2802
    V6_vrounduwuh = 2787,
2803
    V6_vroundwh = 2788,
2804
    V6_vroundwuh  = 2789,
2805
    V6_vrsadubi = 2790,
2806
    V6_vrsadubi_acc = 2791,
2807
    V6_vsathub  = 2792,
2808
    V6_vsatuwuh = 2793,
2809
    V6_vsatwh = 2794,
2810
    V6_vsb  = 2795,
2811
    V6_vscattermh = 2796,
2812
    V6_vscattermh_add = 2797,
2813
    V6_vscattermhq  = 2798,
2814
    V6_vscattermhw  = 2799,
2815
    V6_vscattermhw_add  = 2800,
2816
    V6_vscattermhwq = 2801,
2817
    V6_vscattermw = 2802,
2818
    V6_vscattermw_add = 2803,
2819
    V6_vscattermwq  = 2804,
2820
    V6_vsh  = 2805,
2821
    V6_vshufeh  = 2806,
2822
    V6_vshuff = 2807,
2823
    V6_vshuffb  = 2808,
2824
    V6_vshuffeb = 2809,
2825
    V6_vshuffh  = 2810,
2826
    V6_vshuffob = 2811,
2827
    V6_vshuffvdd  = 2812,
2828
    V6_vshufoeb = 2813,
2829
    V6_vshufoeh = 2814,
2830
    V6_vshufoh  = 2815,
2831
    V6_vsubb  = 2816,
2832
    V6_vsubb_dv = 2817,
2833
    V6_vsubbnq  = 2818,
2834
    V6_vsubbq = 2819,
2835
    V6_vsubbsat = 2820,
2836
    V6_vsubbsat_dv  = 2821,
2837
    V6_vsubcarry  = 2822,
2838
    V6_vsubh  = 2823,
2839
    V6_vsubh_dv = 2824,
2840
    V6_vsubhnq  = 2825,
2841
    V6_vsubhq = 2826,
2842
    V6_vsubhsat = 2827,
2843
    V6_vsubhsat_dv  = 2828,
2844
    V6_vsubhw = 2829,
2845
    V6_vsububh  = 2830,
2846
    V6_vsububsat  = 2831,
2847
    V6_vsububsat_dv = 2832,
2848
    V6_vsubububb_sat  = 2833,
2849
    V6_vsubuhsat  = 2834,
2850
    V6_vsubuhsat_dv = 2835,
2851
    V6_vsubuhw  = 2836,
2852
    V6_vsubuwsat  = 2837,
2853
    V6_vsubuwsat_dv = 2838,
2854
    V6_vsubw  = 2839,
2855
    V6_vsubw_dv = 2840,
2856
    V6_vsubwnq  = 2841,
2857
    V6_vsubwq = 2842,
2858
    V6_vsubwsat = 2843,
2859
    V6_vsubwsat_dv  = 2844,
2860
    V6_vswap  = 2845,
2861
    V6_vtmpyb = 2846,
2862
    V6_vtmpyb_acc = 2847,
2863
    V6_vtmpybus = 2848,
2864
    V6_vtmpybus_acc = 2849,
2865
    V6_vtmpyhb  = 2850,
2866
    V6_vtmpyhb_acc  = 2851,
2867
    V6_vunpackb = 2852,
2868
    V6_vunpackh = 2853,
2869
    V6_vunpackob  = 2854,
2870
    V6_vunpackoh  = 2855,
2871
    V6_vunpackub  = 2856,
2872
    V6_vunpackuh  = 2857,
2873
    V6_vwhist128  = 2858,
2874
    V6_vwhist128m = 2859,
2875
    V6_vwhist128q = 2860,
2876
    V6_vwhist128qm  = 2861,
2877
    V6_vwhist256  = 2862,
2878
    V6_vwhist256_sat  = 2863,
2879
    V6_vwhist256q = 2864,
2880
    V6_vwhist256q_sat = 2865,
2881
    V6_vxor = 2866,
2882
    V6_vzb  = 2867,
2883
    V6_vzh  = 2868,
2884
    Y2_barrier  = 2869,
2885
    Y2_break  = 2870,
2886
    Y2_dccleana = 2871,
2887
    Y2_dccleaninva  = 2872,
2888
    Y2_dcfetchbo  = 2873,
2889
    Y2_dcinva = 2874,
2890
    Y2_dczeroa  = 2875,
2891
    Y2_icinva = 2876,
2892
    Y2_isync  = 2877,
2893
    Y2_syncht = 2878,
2894
    Y4_l2fetch  = 2879,
2895
    Y4_trace  = 2880,
2896
    Y5_l2fetch  = 2881,
2897
    dep_A2_addsat = 2882,
2898
    dep_A2_subsat = 2883,
2899
    dep_S2_packhl = 2884,
2900
    INSTRUCTION_LIST_END = 2885
2901
  };
2902
2903
} // end Hexagon namespace
2904
} // end llvm namespace
2905
#endif // GET_INSTRINFO_ENUM
2906
2907
#ifdef GET_INSTRINFO_SCHED_ENUM
2908
#undef GET_INSTRINFO_SCHED_ENUM
2909
namespace llvm {
2910
2911
namespace Hexagon {
2912
namespace Sched {
2913
  enum {
2914
    NoInstrModel  = 0,
2915
    tc_897d1a9d = 1,
2916
    PSEUDO  = 2,
2917
    tc_68cb12ce = 3,
2918
    tc_d6bf0472 = 4,
2919
    tc_2b2f4060 = 5,
2920
    tc_b9488031 = 6,
2921
    tc_5f6847a1 = 7,
2922
    tc_540fdfbc = 8,
2923
    tc_1e856f58 = 9,
2924
    tc_6ebb4a12 = 10,
2925
    tc_53bc8a6a = 11,
2926
    DUPLEX  = 12,
2927
    tc_ENDLOOP  = 13,
2928
    tc_52d7bbea = 14,
2929
    tc_e9fae2d6 = 15,
2930
    tc_e0739b8c = 16,
2931
    tc_59a01ead = 17,
2932
    tc_ef52ed71 = 18,
2933
    tc_7f881c76 = 19,
2934
    tc_2fc0c436 = 20,
2935
    tc_44126683 = 21,
2936
    tc_513bef45 = 22,
2937
    tc_395dc00f = 23,
2938
    tc_3bc2c5d3 = 24,
2939
    tc_e7624c08 = 25,
2940
    tc_d1090e34 = 26,
2941
    tc_3d04548d = 27,
2942
    LD_tc_ld_SLOT01 = 28,
2943
    tc_1853ea6d = 29,
2944
    tc_8fd5f294 = 30,
2945
    tc_e913dc32 = 31,
2946
    tc_4403ca65 = 32,
2947
    tc_bbaf280e = 33,
2948
    tc_9fdb5406 = 34,
2949
    tc_f86c328a = 35,
2950
    tc_9faf76ae = 36,
2951
    tc_97c165b9 = 37,
2952
    tc_b712833a = 38,
2953
    tc_35e92f8e = 39,
2954
    PSEUDOM = 40,
2955
    tc_b06ab583 = 41,
2956
    tc_e3748cdf = 42,
2957
    tc_354299ad = 43,
2958
    tc_2171ebae = 44,
2959
    tc_2b6f77c6 = 45,
2960
    tc_8b15472a = 46,
2961
    tc_594ab548 = 47,
2962
    tc_05b6c987 = 48,
2963
    tc_f7dd9c9f = 49,
2964
    tc_87735c3b = 50,
2965
    tc_e7d02c66 = 51,
2966
    tc_e216a5db = 52,
2967
    ST_tc_st_SLOT01 = 53,
2968
    CVI_VA  = 54,
2969
    tc_71337255 = 55,
2970
    tc_7fa8b40f = 56,
2971
    tc_8a6eb39a = 57,
2972
    CVI_GATHER_PSEUDO = 58,
2973
    tc_3da80ba5 = 59,
2974
    tc_c2f7d806 = 60,
2975
    tc_b44c6e2a = 61,
2976
    tc_1b9c9ee5 = 62,
2977
    tc_5ba5997d = 63,
2978
    tc_cde8b071 = 64,
2979
    tc_6efc556e = 65,
2980
    tc_8fe6b782 = 66,
2981
    tc_29175780 = 67,
2982
    tc_a21dc435 = 68,
2983
    tc_dbdffe3d = 69,
2984
    tc_523fcf30 = 70,
2985
    tc_7a830544 = 71,
2986
    tc_452f85af = 72,
2987
    tc_04c9decc = 73,
2988
    tc_c6ce9b3f = 74,
2989
    tc_caaebcba = 75,
2990
    tc_55050d58 = 76,
2991
    tc_ef84f62f = 77,
2992
    tc_f2704b9a = 78,
2993
    tc_c6aa82f7 = 79,
2994
    tc_351fed2d = 80,
2995
    tc_f8eeed7a = 81,
2996
    tc_b9c4623f = 82,
2997
    tc_481e5e5c = 83,
2998
    tc_a27582fa = 84,
2999
    tc_f3eaa14b = 85,
3000
    tc_234a11a5 = 86,
3001
    tc_6792d5ff = 87,
3002
    tc_d580173f = 88,
3003
    tc_038a1342 = 89,
3004
    tc_4d99bca9 = 90,
3005
    tc_976ddc4f = 91,
3006
    tc_9c00ce8d = 92,
3007
    tc_6fa4db47 = 93,
3008
    tc_994333cd = 94,
3009
    tc_2f185f5c = 95,
3010
    tc_15411484 = 96,
3011
    tc_10b97e27 = 97,
3012
    tc_3669266a = 98,
3013
    tc_a46f0df5 = 99,
3014
    tc_e1e99bfa = 100,
3015
    tc_181af5d0 = 101,
3016
    tc_97743097 = 102,
3017
    tc_73043bf4 = 103,
3018
    tc_cf59f215 = 104,
3019
    tc_7934b9df = 105,
3020
    tc_681a2300 = 106,
3021
    tc_c5e2426d = 107,
3022
    tc_4f7cd700 = 108,
3023
    tc_14cd4cfa = 109,
3024
    tc_51b866be = 110,
3025
    tc_855b0b61 = 111,
3026
    tc_bde7aaf4 = 112,
3027
    tc_99be14ca = 113,
3028
    tc_5eb851fc = 114,
3029
    tc_49eb22c8 = 115,
3030
    tc_746baa8e = 116,
3031
    tc_3cb8ea06 = 117,
3032
    tc_bad2bcaf = 118,
3033
    tc_03220ffa = 119,
3034
    tc_9c98e8af = 120,
3035
    tc_6aa5711a = 121,
3036
    tc_63fe3df7 = 122,
3037
    tc_5acef64a = 123,
3038
    tc_0cd51c76 = 124,
3039
    tc_b77c481f = 125,
3040
    tc_cf47a43f = 126,
3041
    tc_f47d212f = 127,
3042
    tc_1d5a38a8 = 128,
3043
    tc_9ef61e5c = 129,
3044
    tc_b7dd427e = 130,
3045
    tc_c74f796f = 131,
3046
    tc_16d0d8d5 = 132,
3047
    tc_84df2cd3 = 133,
3048
    tc_bcc96cee = 134,
3049
    tc_f49e76f4 = 135,
3050
    tc_a788683e = 136,
3051
    tc_ff9ee76e = 137,
3052
    tc_d088982c = 138,
3053
    tc_c6ebf8dd = 139,
3054
    tc_cd7374a0 = 140,
3055
    tc_74e47fd9 = 141,
3056
    tc_d9f95eef = 142,
3057
    tc_d24b2d85 = 143,
3058
    tc_9d5941c7 = 144,
3059
    tc_1372bca1 = 145,
3060
    tc_238d91d2 = 146,
3061
    tc_5274e61a = 147,
3062
    tc_66888ded = 148,
3063
    tc_3e07fb90 = 149,
3064
    tc_6ac37025 = 150,
3065
    tc_adb14c66 = 151,
3066
    tc_53bdb2f6 = 152,
3067
    tc_e421e012 = 153,
3068
    tc_d9709180 = 154,
3069
    tc_0dc560de = 155,
3070
    tc_b166348b = 156,
3071
    tc_a8acdac0 = 157,
3072
    tc_b9c0b731 = 158,
3073
    tc_60571023 = 159,
3074
    tc_00afc57e = 160,
3075
    tc_41d5298e = 161,
3076
    tc_be706f30 = 162,
3077
    tc_609d2efe = 163,
3078
    tc_a904d137 = 164,
3079
    tc_1b82a277 = 165,
3080
    tc_e9c822f7 = 166,
3081
    tc_90f3e30c = 167,
3082
    tc_36c68ad1 = 168,
3083
    tc_2a160009 = 169,
3084
    tc_fcab4871 = 170,
3085
    tc_0fc1ae07 = 171,
3086
    tc_57288781 = 172,
3087
    tc_9777e6bf = 173,
3088
    tc_6b78cf13 = 174,
3089
    tc_4105d6b5 = 175,
3090
    tc_4fd8566e = 176,
3091
    tc_5cbf490b = 177,
3092
    tc_da979fb3 = 178,
3093
    tc_eb669007 = 179,
3094
    tc_77a4c701 = 180,
3095
    tc_51cd3aab = 181,
3096
    tc_38208312 = 182,
3097
    tc_9c267309 = 183,
3098
    tc_d642eff3 = 184,
3099
    tc_6fd9ad30 = 185,
3100
    tc_7fa82b08 = 186,
3101
    tc_1b93bdc6 = 187,
3102
    tc_d5090f3e = 188,
3103
    tc_8b6a873f = 189,
3104
    tc_db5b9e2f = 190,
3105
    tc_85d237e3 = 191,
3106
    tc_0317c6ca = 192,
3107
    tc_aedb9f9e = 193,
3108
    tc_99093773 = 194,
3109
    tc_a4c9df3b = 195,
3110
    tc_29841470 = 196,
3111
    tc_5c03dc63 = 197,
3112
    tc_908a4c8c = 198,
3113
    tc_a3127e12 = 199,
3114
    tc_5a9fc4ec = 200,
3115
    tc_45453b98 = 201,
3116
    tc_eda67dcd = 202,
3117
    tc_e172d86a = 203,
3118
    tc_c4b515c5 = 204,
3119
    tc_e231aa4f = 205,
3120
    tc_9311da3f = 206,
3121
    tc_41f4b64e = 207,
3122
    tc_c00bf9c9 = 208,
3123
    tc_d2cb81ea = 209,
3124
    tc_5c120602 = 210,
3125
    tc_e6299d16 = 211,
3126
    tc_f3fc3f83 = 212,
3127
    tc_4e2a5159 = 213,
3128
    tc_69b6dd20 = 214,
3129
    tc_d725e5b0 = 215,
3130
    tc_7c3f55c4 = 216,
3131
    tc_d98f4d63 = 217,
3132
    tc_66bb62ea = 218,
3133
    tc_63e3d94c = 219,
3134
    tc_bfe309d5 = 220,
3135
    tc_98733e9d = 221,
3136
    tc_e5053c8f = 222,
3137
    tc_cedf314b = 223,
3138
    tc_fa99dc24 = 224,
3139
    tc_cbf6d1dc = 225,
3140
    tc_7474003e = 226,
3141
    tc_a807365d = 227,
3142
    tc_ee927c0e = 228,
3143
    tc_7e9f581b = 229,
3144
    tc_41f99e1c = 230,
3145
    tc_bf142ae2 = 231,
3146
    tc_9b9642a1 = 232,
3147
    tc_644584f8 = 233,
3148
    tc_4f190ba3 = 234,
3149
    tc_df54ad52 = 235,
3150
    tc_ec58f88a = 236,
3151
    tc_94f43c04 = 237,
3152
    tc_316c637c = 238,
3153
    tc_d7bea0ec = 239,
3154
    tc_72ad7b54 = 240,
3155
    tc_b77635b4 = 241,
3156
    tc_28978789 = 242,
3157
    tc_367f7f3d = 243,
3158
    tc_4ca572d4 = 244,
3159
    tc_00e7c26e = 245,
3160
    tc_4d9914c9 = 246,
3161
    tc_999d32db = 247,
3162
    tc_b13761ae = 248,
3163
    tc_daa058fa = 249,
3164
    tc_c82dc1ff = 250,
3165
    SCHED_LIST_END = 251
3166
  };
3167
} // end Sched namespace
3168
} // end Hexagon namespace
3169
} // end llvm namespace
3170
#endif // GET_INSTRINFO_SCHED_ENUM
3171
3172
#ifdef GET_INSTRINFO_MC_DESC
3173
#undef GET_INSTRINFO_MC_DESC
3174
namespace llvm {
3175
3176
static const MCPhysReg ImplicitList1[] = { Hexagon::R31, Hexagon::R30, Hexagon::R29, 0 };
3177
static const MCPhysReg ImplicitList2[] = { Hexagon::R29, Hexagon::R30, 0 };
3178
static const MCPhysReg ImplicitList3[] = { Hexagon::R29, 0 };
3179
static const MCPhysReg ImplicitList4[] = { Hexagon::R29, Hexagon::R30, Hexagon::R31, 0 };
3180
static const MCPhysReg ImplicitList5[] = { Hexagon::SA0, Hexagon::LC0, 0 };
3181
static const MCPhysReg ImplicitList6[] = { Hexagon::PC, Hexagon::LC0, 0 };
3182
static const MCPhysReg ImplicitList7[] = { Hexagon::SA0, Hexagon::SA1, Hexagon::LC0, Hexagon::LC1, 0 };
3183
static const MCPhysReg ImplicitList8[] = { Hexagon::PC, Hexagon::LC0, Hexagon::LC1, 0 };
3184
static const MCPhysReg ImplicitList9[] = { Hexagon::SA1, Hexagon::LC1, 0 };
3185
static const MCPhysReg ImplicitList10[] = { Hexagon::PC, Hexagon::LC1, 0 };
3186
static const MCPhysReg ImplicitList11[] = { Hexagon::LC0, Hexagon::SA0, 0 };
3187
static const MCPhysReg ImplicitList12[] = { Hexagon::LC0, Hexagon::P3, Hexagon::PC, Hexagon::USR, 0 };
3188
static const MCPhysReg ImplicitList13[] = { Hexagon::LC0, Hexagon::LC1, Hexagon::SA0, Hexagon::SA1, 0 };
3189
static const MCPhysReg ImplicitList14[] = { Hexagon::LC0, Hexagon::LC1, Hexagon::P3, Hexagon::PC, Hexagon::USR, 0 };
3190
static const MCPhysReg ImplicitList15[] = { Hexagon::LC1, Hexagon::SA1, 0 };
3191
static const MCPhysReg ImplicitList16[] = { Hexagon::LC1, Hexagon::PC, 0 };
3192
static const MCPhysReg ImplicitList17[] = { Hexagon::R30, 0 };
3193
static const MCPhysReg ImplicitList18[] = { Hexagon::CS, 0 };
3194
static const MCPhysReg ImplicitList19[] = { Hexagon::PC, 0 };
3195
static const MCPhysReg ImplicitList20[] = { Hexagon::USR_OVF, 0 };
3196
static const MCPhysReg ImplicitList21[] = { Hexagon::R16, 0 };
3197
static const MCPhysReg ImplicitList22[] = { Hexagon::R28, 0 };
3198
static const MCPhysReg ImplicitList23[] = { Hexagon::USR, 0 };
3199
static const MCPhysReg ImplicitList24[] = { Hexagon::PC, Hexagon::R31, 0 };
3200
static const MCPhysReg ImplicitList25[] = { Hexagon::LC0, Hexagon::SA0, Hexagon::USR, 0 };
3201
static const MCPhysReg ImplicitList26[] = { Hexagon::SA0, Hexagon::LC0, Hexagon::USR, 0 };
3202
static const MCPhysReg ImplicitList27[] = { Hexagon::LC0, Hexagon::P3, Hexagon::SA0, Hexagon::USR, 0 };
3203
static const MCPhysReg ImplicitList28[] = { Hexagon::GOSP, 0 };
3204
static const MCPhysReg ImplicitList29[] = { Hexagon::GOSP, Hexagon::PC, 0 };
3205
static const MCPhysReg ImplicitList30[] = { Hexagon::P0, 0 };
3206
static const MCPhysReg ImplicitList31[] = { Hexagon::P0, Hexagon::PC, 0 };
3207
static const MCPhysReg ImplicitList32[] = { Hexagon::P1, 0 };
3208
static const MCPhysReg ImplicitList33[] = { Hexagon::P1, Hexagon::PC, 0 };
3209
static const MCPhysReg ImplicitList34[] = { Hexagon::FRAMEKEY, 0 };
3210
static const MCPhysReg ImplicitList35[] = { Hexagon::GP, 0 };
3211
static const MCPhysReg ImplicitList36[] = { Hexagon::PC, Hexagon::R29, 0 };
3212
static const MCPhysReg ImplicitList37[] = { Hexagon::PC, Hexagon::R31, Hexagon::R6, Hexagon::R7, Hexagon::P0, 0 };
3213
static const MCPhysReg ImplicitList38[] = { Hexagon::R29, Hexagon::R30, Hexagon::R31, Hexagon::PC, 0 };
3214
static const MCPhysReg ImplicitList39[] = { Hexagon::R14, Hexagon::R15, Hexagon::R28, Hexagon::R29, Hexagon::R30, Hexagon::R31, Hexagon::PC, 0 };
3215
static const MCPhysReg ImplicitList40[] = { Hexagon::FRAMEKEY, Hexagon::FRAMELIMIT, Hexagon::R30, Hexagon::R31, 0 };
3216
static const MCPhysReg ImplicitList41[] = { Hexagon::R29, Hexagon::R31, 0 };
3217
static const MCPhysReg ImplicitList42[] = { Hexagon::R14, Hexagon::R15, Hexagon::R28, Hexagon::P0, 0 };
3218
static const MCPhysReg ImplicitList43[] = { Hexagon::R14, Hexagon::R15, Hexagon::R28, 0 };
3219
static const MCPhysReg ImplicitList44[] = { Hexagon::FRAMEKEY, Hexagon::R30, 0 };
3220
static const MCPhysReg ImplicitList45[] = { Hexagon::R30, Hexagon::R29, Hexagon::R31, 0 };
3221
static const MCPhysReg ImplicitList46[] = { Hexagon::R31, 0 };
3222
static const MCPhysReg ImplicitList47[] = { Hexagon::P0, Hexagon::R31, 0 };
3223
static const MCPhysReg ImplicitList48[] = { Hexagon::PC, Hexagon::R30, Hexagon::R29, Hexagon::R31, 0 };
3224
static const MCPhysReg ImplicitList49[] = { Hexagon::FRAMEKEY, Hexagon::P0, Hexagon::R30, 0 };
3225
static const MCPhysReg ImplicitList50[] = { Hexagon::FRAMEKEY, Hexagon::FRAMELIMIT, Hexagon::R30, Hexagon::R29, Hexagon::R31, 0 };
3226
static const MCPhysReg ImplicitList51[] = { Hexagon::R30, Hexagon::R29, 0 };
3227
static const MCPhysReg ImplicitList52[] = { Hexagon::VTMP, 0 };
3228
3229
static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3230
static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3231
static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3232
static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3233
static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3234
static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3235
static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3236
static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3237
static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
3238
static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3239
static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3240
static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3241
static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3242
static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3243
static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3244
static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
3245
static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3246
static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3247
static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3248
static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3249
static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
3250
static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
3251
static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3252
static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3253
static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
3254
static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3255
static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
3256
static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
3257
static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
3258
static const MCOperandInfo OperandInfo31[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3259
static const MCOperandInfo OperandInfo32[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3260
static const MCOperandInfo OperandInfo33[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3261
static const MCOperandInfo OperandInfo34[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3262
static const MCOperandInfo OperandInfo35[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3263
static const MCOperandInfo OperandInfo36[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3264
static const MCOperandInfo OperandInfo37[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3265
static const MCOperandInfo OperandInfo38[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3266
static const MCOperandInfo OperandInfo39[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3267
static const MCOperandInfo OperandInfo40[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3268
static const MCOperandInfo OperandInfo41[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3269
static const MCOperandInfo OperandInfo42[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3270
static const MCOperandInfo OperandInfo43[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3271
static const MCOperandInfo OperandInfo44[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3272
static const MCOperandInfo OperandInfo45[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3273
static const MCOperandInfo OperandInfo46[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3274
static const MCOperandInfo OperandInfo47[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3275
static const MCOperandInfo OperandInfo48[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3276
static const MCOperandInfo OperandInfo49[] = { { Hexagon::CtrRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3277
static const MCOperandInfo OperandInfo50[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3278
static const MCOperandInfo OperandInfo51[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3279
static const MCOperandInfo OperandInfo52[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3280
static const MCOperandInfo OperandInfo53[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3281
static const MCOperandInfo OperandInfo54[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3282
static const MCOperandInfo OperandInfo55[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3283
static const MCOperandInfo OperandInfo56[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3284
static const MCOperandInfo OperandInfo57[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3285
static const MCOperandInfo OperandInfo58[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3286
static const MCOperandInfo OperandInfo59[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3287
static const MCOperandInfo OperandInfo60[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3288
static const MCOperandInfo OperandInfo61[] = { { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3289
static const MCOperandInfo OperandInfo62[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3290
static const MCOperandInfo OperandInfo63[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3291
static const MCOperandInfo OperandInfo64[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3292
static const MCOperandInfo OperandInfo65[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3293
static const MCOperandInfo OperandInfo66[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3294
static const MCOperandInfo OperandInfo67[] = { { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3295
static const MCOperandInfo OperandInfo68[] = { { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3296
static const MCOperandInfo OperandInfo69[] = { { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3297
static const MCOperandInfo OperandInfo70[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3298
static const MCOperandInfo OperandInfo71[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3299
static const MCOperandInfo OperandInfo72[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3300
static const MCOperandInfo OperandInfo73[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3301
static const MCOperandInfo OperandInfo74[] = { { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3302
static const MCOperandInfo OperandInfo75[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3303
static const MCOperandInfo OperandInfo76[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3304
static const MCOperandInfo OperandInfo77[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3305
static const MCOperandInfo OperandInfo78[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3306
static const MCOperandInfo OperandInfo79[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::CtrRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3307
static const MCOperandInfo OperandInfo80[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3308
static const MCOperandInfo OperandInfo81[] = { { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3309
static const MCOperandInfo OperandInfo82[] = { { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3310
static const MCOperandInfo OperandInfo83[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3311
static const MCOperandInfo OperandInfo84[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3312
static const MCOperandInfo OperandInfo85[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3313
static const MCOperandInfo OperandInfo86[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3314
static const MCOperandInfo OperandInfo87[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3315
static const MCOperandInfo OperandInfo88[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3316
static const MCOperandInfo OperandInfo89[] = { { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3317
static const MCOperandInfo OperandInfo90[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3318
static const MCOperandInfo OperandInfo91[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3319
static const MCOperandInfo OperandInfo92[] = { { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3320
static const MCOperandInfo OperandInfo93[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3321
static const MCOperandInfo OperandInfo94[] = { { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3322
static const MCOperandInfo OperandInfo95[] = { { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3323
static const MCOperandInfo OperandInfo96[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3324
static const MCOperandInfo OperandInfo97[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3325
static const MCOperandInfo OperandInfo98[] = { { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3326
static const MCOperandInfo OperandInfo99[] = { { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3327
static const MCOperandInfo OperandInfo100[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3328
static const MCOperandInfo OperandInfo101[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3329
static const MCOperandInfo OperandInfo102[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsLow8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3330
static const MCOperandInfo OperandInfo103[] = { { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3331
static const MCOperandInfo OperandInfo104[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3332
static const MCOperandInfo OperandInfo105[] = { { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3333
static const MCOperandInfo OperandInfo106[] = { { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3334
static const MCOperandInfo OperandInfo107[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3335
static const MCOperandInfo OperandInfo108[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3336
static const MCOperandInfo OperandInfo109[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3337
static const MCOperandInfo OperandInfo110[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3338
static const MCOperandInfo OperandInfo111[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3339
static const MCOperandInfo OperandInfo112[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3340
static const MCOperandInfo OperandInfo113[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3341
static const MCOperandInfo OperandInfo114[] = { { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3342
static const MCOperandInfo OperandInfo115[] = { { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3343
static const MCOperandInfo OperandInfo116[] = { { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3344
static const MCOperandInfo OperandInfo117[] = { { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3345
static const MCOperandInfo OperandInfo118[] = { { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3346
static const MCOperandInfo OperandInfo119[] = { { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3347
static const MCOperandInfo OperandInfo120[] = { { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3348
static const MCOperandInfo OperandInfo121[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3349
static const MCOperandInfo OperandInfo122[] = { { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3350
static const MCOperandInfo OperandInfo123[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3351
static const MCOperandInfo OperandInfo124[] = { { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3352
static const MCOperandInfo OperandInfo125[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3353
static const MCOperandInfo OperandInfo126[] = { { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3354
static const MCOperandInfo OperandInfo127[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3355
static const MCOperandInfo OperandInfo128[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3356
static const MCOperandInfo OperandInfo129[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3357
static const MCOperandInfo OperandInfo130[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3358
static const MCOperandInfo OperandInfo131[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3359
static const MCOperandInfo OperandInfo132[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::CtrRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3360
static const MCOperandInfo OperandInfo133[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3361
static const MCOperandInfo OperandInfo134[] = { { Hexagon::CtrRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3362
static const MCOperandInfo OperandInfo135[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3363
static const MCOperandInfo OperandInfo136[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
3364
static const MCOperandInfo OperandInfo137[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3365
static const MCOperandInfo OperandInfo138[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3366
static const MCOperandInfo OperandInfo139[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::CtrRegs64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3367
static const MCOperandInfo OperandInfo140[] = { { Hexagon::CtrRegs64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3368
static const MCOperandInfo OperandInfo141[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3369
static const MCOperandInfo OperandInfo142[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3370
static const MCOperandInfo OperandInfo143[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3371
static const MCOperandInfo OperandInfo144[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3372
static const MCOperandInfo OperandInfo145[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3373
static const MCOperandInfo OperandInfo146[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3374
static const MCOperandInfo OperandInfo147[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3375
static const MCOperandInfo OperandInfo148[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3376
static const MCOperandInfo OperandInfo149[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3377
static const MCOperandInfo OperandInfo150[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3378
static const MCOperandInfo OperandInfo151[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3379
static const MCOperandInfo OperandInfo152[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3380
static const MCOperandInfo OperandInfo153[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3381
static const MCOperandInfo OperandInfo154[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3382
static const MCOperandInfo OperandInfo155[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3383
static const MCOperandInfo OperandInfo156[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3384
static const MCOperandInfo OperandInfo157[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3385
static const MCOperandInfo OperandInfo158[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::GuestRegs64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3386
static const MCOperandInfo OperandInfo159[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::GuestRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3387
static const MCOperandInfo OperandInfo160[] = { { Hexagon::GuestRegs64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3388
static const MCOperandInfo OperandInfo161[] = { { Hexagon::GuestRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3389
static const MCOperandInfo OperandInfo162[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3390
static const MCOperandInfo OperandInfo163[] = { { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3391
static const MCOperandInfo OperandInfo164[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3392
static const MCOperandInfo OperandInfo165[] = { { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3393
static const MCOperandInfo OperandInfo166[] = { { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3394
static const MCOperandInfo OperandInfo167[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3395
static const MCOperandInfo OperandInfo168[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3396
static const MCOperandInfo OperandInfo169[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3397
static const MCOperandInfo OperandInfo170[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3398
static const MCOperandInfo OperandInfo171[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3399
static const MCOperandInfo OperandInfo172[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3400
static const MCOperandInfo OperandInfo173[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3401
static const MCOperandInfo OperandInfo174[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3402
static const MCOperandInfo OperandInfo175[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3403
static const MCOperandInfo OperandInfo176[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3404
static const MCOperandInfo OperandInfo177[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3405
static const MCOperandInfo OperandInfo178[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3406
static const MCOperandInfo OperandInfo179[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3407
static const MCOperandInfo OperandInfo180[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3408
static const MCOperandInfo OperandInfo181[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3409
static const MCOperandInfo OperandInfo182[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3410
static const MCOperandInfo OperandInfo183[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3411
static const MCOperandInfo OperandInfo184[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3412
static const MCOperandInfo OperandInfo185[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3413
static const MCOperandInfo OperandInfo186[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3414
static const MCOperandInfo OperandInfo187[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3415
static const MCOperandInfo OperandInfo188[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3416
static const MCOperandInfo OperandInfo189[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3417
static const MCOperandInfo OperandInfo190[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3418
static const MCOperandInfo OperandInfo191[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3419
static const MCOperandInfo OperandInfo192[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3420
static const MCOperandInfo OperandInfo193[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3421
static const MCOperandInfo OperandInfo194[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3422
static const MCOperandInfo OperandInfo195[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3423
static const MCOperandInfo OperandInfo196[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3424
static const MCOperandInfo OperandInfo197[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3425
static const MCOperandInfo OperandInfo198[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3426
static const MCOperandInfo OperandInfo199[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3427
static const MCOperandInfo OperandInfo200[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3428
static const MCOperandInfo OperandInfo201[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3429
static const MCOperandInfo OperandInfo202[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3430
static const MCOperandInfo OperandInfo203[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3431
static const MCOperandInfo OperandInfo204[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3432
static const MCOperandInfo OperandInfo205[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3433
static const MCOperandInfo OperandInfo206[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3434
static const MCOperandInfo OperandInfo207[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3435
static const MCOperandInfo OperandInfo208[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3436
static const MCOperandInfo OperandInfo209[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3437
static const MCOperandInfo OperandInfo210[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3438
static const MCOperandInfo OperandInfo211[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3439
static const MCOperandInfo OperandInfo212[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3440
static const MCOperandInfo OperandInfo213[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3441
static const MCOperandInfo OperandInfo214[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3442
static const MCOperandInfo OperandInfo215[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3443
static const MCOperandInfo OperandInfo216[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3444
static const MCOperandInfo OperandInfo217[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3445
static const MCOperandInfo OperandInfo218[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3446
static const MCOperandInfo OperandInfo219[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3447
static const MCOperandInfo OperandInfo220[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3448
static const MCOperandInfo OperandInfo221[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3449
static const MCOperandInfo OperandInfo222[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3450
static const MCOperandInfo OperandInfo223[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3451
static const MCOperandInfo OperandInfo224[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3452
static const MCOperandInfo OperandInfo225[] = { { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3453
static const MCOperandInfo OperandInfo226[] = { { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3454
static const MCOperandInfo OperandInfo227[] = { { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3455
static const MCOperandInfo OperandInfo228[] = { { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3456
static const MCOperandInfo OperandInfo229[] = { { Hexagon::GeneralDoubleLow8RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3457
static const MCOperandInfo OperandInfo230[] = { { Hexagon::GeneralDoubleLow8RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3458
static const MCOperandInfo OperandInfo231[] = { { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3459
static const MCOperandInfo OperandInfo232[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::GeneralDoubleLow8RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3460
static const MCOperandInfo OperandInfo233[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::GeneralSubRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3461
static const MCOperandInfo OperandInfo234[] = { { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3462
static const MCOperandInfo OperandInfo235[] = { { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3463
static const MCOperandInfo OperandInfo236[] = { { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3464
static const MCOperandInfo OperandInfo237[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3465
static const MCOperandInfo OperandInfo238[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3466
static const MCOperandInfo OperandInfo239[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3467
static const MCOperandInfo OperandInfo240[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3468
static const MCOperandInfo OperandInfo241[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3469
static const MCOperandInfo OperandInfo242[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3470
static const MCOperandInfo OperandInfo243[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3471
static const MCOperandInfo OperandInfo244[] = { { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3472
static const MCOperandInfo OperandInfo245[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3473
static const MCOperandInfo OperandInfo246[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3474
static const MCOperandInfo OperandInfo247[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3475
static const MCOperandInfo OperandInfo248[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3476
static const MCOperandInfo OperandInfo249[] = { { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3477
static const MCOperandInfo OperandInfo250[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3478
static const MCOperandInfo OperandInfo251[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3479
static const MCOperandInfo OperandInfo252[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3480
static const MCOperandInfo OperandInfo253[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
3481
static const MCOperandInfo OperandInfo254[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3482
static const MCOperandInfo OperandInfo255[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3483
static const MCOperandInfo OperandInfo256[] = { { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3484
static const MCOperandInfo OperandInfo257[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3485
static const MCOperandInfo OperandInfo258[] = { { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsLow8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3486
static const MCOperandInfo OperandInfo259[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3487
static const MCOperandInfo OperandInfo260[] = { { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3488
static const MCOperandInfo OperandInfo261[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3489
static const MCOperandInfo OperandInfo262[] = { { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3490
static const MCOperandInfo OperandInfo263[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3491
static const MCOperandInfo OperandInfo264[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3492
static const MCOperandInfo OperandInfo265[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsLow8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3493
static const MCOperandInfo OperandInfo266[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3494
static const MCOperandInfo OperandInfo267[] = { { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsLow8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3495
static const MCOperandInfo OperandInfo268[] = { { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3496
static const MCOperandInfo OperandInfo269[] = { { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3497
static const MCOperandInfo OperandInfo270[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3498
static const MCOperandInfo OperandInfo271[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3499
static const MCOperandInfo OperandInfo272[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3500
static const MCOperandInfo OperandInfo273[] = { { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3501
static const MCOperandInfo OperandInfo274[] = { { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3502
3503
extern const MCInstrDesc HexagonInsts[] = {
3504
  { 0,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
3505
  { 1,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
3506
  { 2,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #2 = CFI_INSTRUCTION
3507
  { 3,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = EH_LABEL
3508
  { 4,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = GC_LABEL
3509
  { 5,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = ANNOTATION_LABEL
3510
  { 6,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #6 = KILL
3511
  { 7,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #7 = EXTRACT_SUBREG
3512
  { 8,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #8 = INSERT_SUBREG
3513
  { 9,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #9 = IMPLICIT_DEF
3514
  { 10, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #10 = SUBREG_TO_REG
3515
  { 11, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #11 = COPY_TO_REGCLASS
3516
  { 12, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #12 = DBG_VALUE
3517
  { 13, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #13 = DBG_LABEL
3518
  { 14, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #14 = REG_SEQUENCE
3519
  { 15, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #15 = COPY
3520
  { 16, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #16 = BUNDLE
3521
  { 17, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #17 = LIFETIME_START
3522
  { 18, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #18 = LIFETIME_END
3523
  { 19, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #19 = STACKMAP
3524
  { 20, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #20 = FENTRY_CALL
3525
  { 21, 6,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #21 = PATCHPOINT
3526
  { 22, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #22 = LOAD_STACK_GUARD
3527
  { 23, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #23 = STATEPOINT
3528
  { 24, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #24 = LOCAL_ESCAPE
3529
  { 25, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #25 = FAULTING_OP
3530
  { 26, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #26 = PATCHABLE_OP
3531
  { 27, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #27 = PATCHABLE_FUNCTION_ENTER
3532
  { 28, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #28 = PATCHABLE_RET
3533
  { 29, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #29 = PATCHABLE_FUNCTION_EXIT
3534
  { 30, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #30 = PATCHABLE_TAIL_CALL
3535
  { 31, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #31 = PATCHABLE_EVENT_CALL
3536
  { 32, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #32 = PATCHABLE_TYPED_EVENT_CALL
3537
  { 33, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #33 = ICALL_BRANCH_FUNNEL
3538
  { 34, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #34 = G_ADD
3539
  { 35, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #35 = G_SUB
3540
  { 36, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #36 = G_MUL
3541
  { 37, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #37 = G_SDIV
3542
  { 38, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #38 = G_UDIV
3543
  { 39, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #39 = G_SREM
3544
  { 40, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #40 = G_UREM
3545
  { 41, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_AND
3546
  { 42, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_OR
3547
  { 43, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #43 = G_XOR
3548
  { 44, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #44 = G_IMPLICIT_DEF
3549
  { 45, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #45 = G_PHI
3550
  { 46, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #46 = G_FRAME_INDEX
3551
  { 47, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #47 = G_GLOBAL_VALUE
3552
  { 48, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #48 = G_EXTRACT
3553
  { 49, 2,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #49 = G_UNMERGE_VALUES
3554
  { 50, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #50 = G_INSERT
3555
  { 51, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #51 = G_MERGE_VALUES
3556
  { 52, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #52 = G_PTRTOINT
3557
  { 53, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = G_INTTOPTR
3558
  { 54, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #54 = G_BITCAST
3559
  { 55, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #55 = G_LOAD
3560
  { 56, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #56 = G_SEXTLOAD
3561
  { 57, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #57 = G_ZEXTLOAD
3562
  { 58, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #58 = G_STORE
3563
  { 59, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #59 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
3564
  { 60, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #60 = G_ATOMIC_CMPXCHG
3565
  { 61, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #61 = G_ATOMICRMW_XCHG
3566
  { 62, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #62 = G_ATOMICRMW_ADD
3567
  { 63, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #63 = G_ATOMICRMW_SUB
3568
  { 64, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #64 = G_ATOMICRMW_AND
3569
  { 65, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #65 = G_ATOMICRMW_NAND
3570
  { 66, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #66 = G_ATOMICRMW_OR
3571
  { 67, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #67 = G_ATOMICRMW_XOR
3572
  { 68, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #68 = G_ATOMICRMW_MAX
3573
  { 69, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #69 = G_ATOMICRMW_MIN
3574
  { 70, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #70 = G_ATOMICRMW_UMAX
3575
  { 71, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #71 = G_ATOMICRMW_UMIN
3576
  { 72, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #72 = G_BRCOND
3577
  { 73, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #73 = G_BRINDIRECT
3578
  { 74, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #74 = G_INTRINSIC
3579
  { 75, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #75 = G_INTRINSIC_W_SIDE_EFFECTS
3580
  { 76, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #76 = G_ANYEXT
3581
  { 77, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #77 = G_TRUNC
3582
  { 78, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #78 = G_CONSTANT
3583
  { 79, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #79 = G_FCONSTANT
3584
  { 80, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #80 = G_VASTART
3585
  { 81, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #81 = G_VAARG
3586
  { 82, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #82 = G_SEXT
3587
  { 83, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #83 = G_ZEXT
3588
  { 84, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #84 = G_SHL
3589
  { 85, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #85 = G_LSHR
3590
  { 86, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #86 = G_ASHR
3591
  { 87, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #87 = G_ICMP
3592
  { 88, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #88 = G_FCMP
3593
  { 89, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #89 = G_SELECT
3594
  { 90, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #90 = G_UADDE
3595
  { 91, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #91 = G_USUBE
3596
  { 92, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #92 = G_SADDO
3597
  { 93, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #93 = G_SSUBO
3598
  { 94, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #94 = G_UMULO
3599
  { 95, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #95 = G_SMULO
3600
  { 96, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #96 = G_UMULH
3601
  { 97, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #97 = G_SMULH
3602
  { 98, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #98 = G_FADD
3603
  { 99, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #99 = G_FSUB
3604
  { 100,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #100 = G_FMUL
3605
  { 101,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #101 = G_FMA
3606
  { 102,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #102 = G_FDIV
3607
  { 103,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #103 = G_FREM
3608
  { 104,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #104 = G_FPOW
3609
  { 105,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #105 = G_FEXP
3610
  { 106,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #106 = G_FEXP2
3611
  { 107,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #107 = G_FLOG
3612
  { 108,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #108 = G_FLOG2
3613
  { 109,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #109 = G_FNEG
3614
  { 110,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #110 = G_FPEXT
3615
  { 111,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #111 = G_FPTRUNC
3616
  { 112,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #112 = G_FPTOSI
3617
  { 113,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #113 = G_FPTOUI
3618
  { 114,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #114 = G_SITOFP
3619
  { 115,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #115 = G_UITOFP
3620
  { 116,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #116 = G_FABS
3621
  { 117,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #117 = G_GEP
3622
  { 118,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #118 = G_PTR_MASK
3623
  { 119,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #119 = G_BR
3624
  { 120,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #120 = G_INSERT_VECTOR_ELT
3625
  { 121,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #121 = G_EXTRACT_VECTOR_ELT
3626
  { 122,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #122 = G_SHUFFLE_VECTOR
3627
  { 123,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #123 = G_BSWAP
3628
  { 124,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #124 = G_ADDRSPACE_CAST
3629
  { 125,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x3ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #125 = A2_addsp
3630
  { 126,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x29ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #126 = A2_iconst
3631
  { 127,  2,  1,  4,  3,  0|(1ULL<<MCID::Pseudo), 0x4000ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #127 = A2_neg
3632
  { 128,  2,  1,  4,  3,  0|(1ULL<<MCID::Pseudo), 0x4000ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #128 = A2_not
3633
  { 129,  3,  1,  4,  4,  0|(1ULL<<MCID::Pseudo), 0x4600ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #129 = A2_tfrf
3634
  { 130,  3,  1,  4,  5,  0|(1ULL<<MCID::Pseudo), 0x4e00ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #130 = A2_tfrfnew
3635
  { 131,  2,  1,  4,  6,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #131 = A2_tfrp
3636
  { 132,  3,  1,  4,  6,  0|(1ULL<<MCID::Pseudo), 0x600ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #132 = A2_tfrpf
3637
  { 133,  3,  1,  4,  7,  0|(1ULL<<MCID::Pseudo), 0xe00ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #133 = A2_tfrpfnew
3638
  { 134,  2,  1,  4,  6,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x3ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #134 = A2_tfrpi
3639
  { 135,  3,  1,  4,  6,  0|(1ULL<<MCID::Pseudo), 0x200ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #135 = A2_tfrpt
3640
  { 136,  3,  1,  4,  7,  0|(1ULL<<MCID::Pseudo), 0xa00ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #136 = A2_tfrptnew
3641
  { 137,  3,  1,  4,  4,  0|(1ULL<<MCID::Pseudo), 0x4200ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #137 = A2_tfrt
3642
  { 138,  3,  1,  4,  5,  0|(1ULL<<MCID::Pseudo), 0x4a00ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #138 = A2_tfrtnew
3643
  { 139,  3,  1,  4,  8,  0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #139 = A2_vaddb_map
3644
  { 140,  3,  1,  4,  8,  0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #140 = A2_vsubb_map
3645
  { 141,  2,  1,  4,  6,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x4000ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #141 = A2_zxtb
3646
  { 142,  3,  1,  4,  9,  0|(1ULL<<MCID::Pseudo), 0x3ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #142 = A4_boundscheck
3647
  { 143,  2,  0,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x29ULL, ImplicitList1, ImplicitList2, OperandInfo8, -1 ,nullptr },  // Inst #143 = ADJCALLSTACKDOWN
3648
  { 144,  2,  0,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x29ULL, ImplicitList3, ImplicitList4, OperandInfo8, -1 ,nullptr },  // Inst #144 = ADJCALLSTACKUP
3649
  { 145,  3,  1,  4,  10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #145 = C2_cmpgei
3650
  { 146,  3,  1,  4,  10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #146 = C2_cmpgeui
3651
  { 147,  3,  1,  4,  10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x1ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #147 = C2_cmplt
3652
  { 148,  3,  1,  4,  10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x1ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #148 = C2_cmpltu
3653
  { 149,  2,  1,  4,  11, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #149 = C2_pxfer_map
3654
  { 150,  1,  0,  4,  12, 0|(1ULL<<MCID::Pseudo), 0x29ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #150 = DUPLEX_Pseudo
3655
  { 151,  1,  0,  4,  13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x22ULL, ImplicitList5, ImplicitList6, OperandInfo2, -1 ,nullptr },  // Inst #151 = ENDLOOP0
3656
  { 152,  1,  0,  4,  13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x22ULL, ImplicitList7, ImplicitList8, OperandInfo2, -1 ,nullptr },  // Inst #152 = ENDLOOP01
3657
  { 153,  1,  0,  4,  13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x22ULL, ImplicitList9, ImplicitList10, OperandInfo2, -1 ,nullptr },  // Inst #153 = ENDLOOP1
3658
  { 154,  0,  0,  4,  14, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x24ULL, ImplicitList11, ImplicitList12, nullptr, -1 ,nullptr },  // Inst #154 = J2_endloop0
3659
  { 155,  0,  0,  4,  14, 0|(1ULL<<MCID::Pseudo), 0x24ULL, ImplicitList13, ImplicitList14, nullptr, -1 ,nullptr },  // Inst #155 = J2_endloop01
3660
  { 156,  0,  0,  4,  14, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x24ULL, ImplicitList15, ImplicitList16, nullptr, -1 ,nullptr },  // Inst #156 = J2_endloop1
3661
  { 157,  2,  0,  4,  15, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #157 = J2_jumpf_nopred_map
3662
  { 158,  2,  0,  4,  16, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #158 = J2_jumprf_nopred_map
3663
  { 159,  2,  0,  4,  16, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #159 = J2_jumprt_nopred_map
3664
  { 160,  2,  0,  4,  15, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #160 = J2_jumpt_nopred_map
3665
  { 161,  1,  0,  4,  17, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #161 = J2_trap1_noregmap
3666
  { 162,  3,  1,  4,  18, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #162 = L2_loadalignb_zomap
3667
  { 163,  3,  1,  4,  18, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #163 = L2_loadalignh_zomap
3668
  { 164,  2,  1,  4,  19, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #164 = L2_loadbsw2_zomap
3669
  { 165,  2,  1,  4,  19, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #165 = L2_loadbsw4_zomap
3670
  { 166,  2,  1,  4,  19, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #166 = L2_loadbzw2_zomap
3671
  { 167,  2,  1,  4,  19, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #167 = L2_loadbzw4_zomap
3672
  { 168,  2,  1,  4,  19, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #168 = L2_loadrb_zomap
3673
  { 169,  2,  1,  4,  19, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #169 = L2_loadrd_zomap
3674
  { 170,  2,  1,  4,  19, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #170 = L2_loadrh_zomap
3675
  { 171,  2,  1,  4,  19, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #171 = L2_loadri_zomap
3676
  { 172,  2,  1,  4,  19, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #172 = L2_loadrub_zomap
3677
  { 173,  2,  1,  4,  19, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #173 = L2_loadruh_zomap
3678
  { 174,  3,  1,  4,  18, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #174 = L2_ploadrbf_zomap
3679
  { 175,  3,  1,  4,  20, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #175 = L2_ploadrbfnew_zomap
3680
  { 176,  3,  1,  4,  18, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #176 = L2_ploadrbt_zomap
3681
  { 177,  3,  1,  4,  20, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #177 = L2_ploadrbtnew_zomap
3682
  { 178,  3,  1,  4,  18, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #178 = L2_ploadrdf_zomap
3683
  { 179,  3,  1,  4,  20, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #179 = L2_ploadrdfnew_zomap
3684
  { 180,  3,  1,  4,  18, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #180 = L2_ploadrdt_zomap
3685
  { 181,  3,  1,  4,  20, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #181 = L2_ploadrdtnew_zomap
3686
  { 182,  3,  1,  4,  18, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #182 = L2_ploadrhf_zomap
3687
  { 183,  3,  1,  4,  20, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #183 = L2_ploadrhfnew_zomap
3688
  { 184,  3,  1,  4,  18, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #184 = L2_ploadrht_zomap
3689
  { 185,  3,  1,  4,  20, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #185 = L2_ploadrhtnew_zomap
3690
  { 186,  3,  1,  4,  18, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #186 = L2_ploadrif_zomap
3691
  { 187,  3,  1,  4,  20, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #187 = L2_ploadrifnew_zomap
3692
  { 188,  3,  1,  4,  18, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #188 = L2_ploadrit_zomap
3693
  { 189,  3,  1,  4,  20, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #189 = L2_ploadritnew_zomap
3694
  { 190,  3,  1,  4,  18, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #190 = L2_ploadrubf_zomap
3695
  { 191,  3,  1,  4,  20, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #191 = L2_ploadrubfnew_zomap
3696
  { 192,  3,  1,  4,  18, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #192 = L2_ploadrubt_zomap
3697
  { 193,  3,  1,  4,  20, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #193 = L2_ploadrubtnew_zomap
3698
  { 194,  3,  1,  4,  18, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #194 = L2_ploadruhf_zomap
3699
  { 195,  3,  1,  4,  20, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #195 = L2_ploadruhfnew_zomap
3700
  { 196,  3,  1,  4,  18, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #196 = L2_ploadruht_zomap
3701
  { 197,  3,  1,  4,  20, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #197 = L2_ploadruhtnew_zomap
3702
  { 198,  2,  0,  4,  21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #198 = L4_add_memopb_zomap
3703
  { 199,  2,  0,  4,  21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #199 = L4_add_memoph_zomap
3704
  { 200,  2,  0,  4,  21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #200 = L4_add_memopw_zomap
3705
  { 201,  2,  0,  4,  21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #201 = L4_and_memopb_zomap
3706
  { 202,  2,  0,  4,  21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #202 = L4_and_memoph_zomap
3707
  { 203,  2,  0,  4,  21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #203 = L4_and_memopw_zomap
3708
  { 204,  2,  0,  4,  21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #204 = L4_iadd_memopb_zomap
3709
  { 205,  2,  0,  4,  21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #205 = L4_iadd_memoph_zomap
3710
  { 206,  2,  0,  4,  21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #206 = L4_iadd_memopw_zomap
3711
  { 207,  2,  0,  4,  21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #207 = L4_iand_memopb_zomap
3712
  { 208,  2,  0,  4,  21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #208 = L4_iand_memoph_zomap
3713
  { 209,  2,  0,  4,  21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #209 = L4_iand_memopw_zomap
3714
  { 210,  2,  0,  4,  21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #210 = L4_ior_memopb_zomap
3715
  { 211,  2,  0,  4,  21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #211 = L4_ior_memoph_zomap
3716
  { 212,  2,  0,  4,  21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #212 = L4_ior_memopw_zomap
3717
  { 213,  2,  0,  4,  21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #213 = L4_isub_memopb_zomap
3718
  { 214,  2,  0,  4,  21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #214 = L4_isub_memoph_zomap
3719
  { 215,  2,  0,  4,  21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #215 = L4_isub_memopw_zomap
3720
  { 216,  2,  0,  4,  21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #216 = L4_or_memopb_zomap
3721
  { 217,  2,  0,  4,  21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #217 = L4_or_memoph_zomap
3722
  { 218,  2,  0,  4,  21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #218 = L4_or_memopw_zomap
3723
  { 219,  1,  0,  4,  22, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #219 = L4_return_map_to_raw_f
3724
  { 220,  1,  0,  4,  23, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #220 = L4_return_map_to_raw_fnew_pnt
3725
  { 221,  1,  0,  4,  23, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #221 = L4_return_map_to_raw_fnew_pt
3726
  { 222,  1,  0,  4,  24, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #222 = L4_return_map_to_raw_t
3727
  { 223,  1,  0,  4,  25, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #223 = L4_return_map_to_raw_tnew_pnt
3728
  { 224,  1,  0,  4,  25, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #224 = L4_return_map_to_raw_tnew_pt
3729
  { 225,  2,  0,  4,  21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #225 = L4_sub_memopb_zomap
3730
  { 226,  2,  0,  4,  21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #226 = L4_sub_memoph_zomap
3731
  { 227,  2,  0,  4,  21, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #227 = L4_sub_memopw_zomap
3732
  { 228,  0,  0,  4,  26, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #228 = L6_deallocframe_map_to_raw
3733
  { 229,  0,  0,  4,  27, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #229 = L6_return_map_to_raw
3734
  { 230,  3,  1,  4,  28, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0xda400025ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #230 = LDriw_ctr
3735
  { 231,  3,  1,  4,  28, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0xda400025ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #231 = LDriw_pred
3736
  { 232,  3,  1,  4,  29, 0|(1ULL<<MCID::Pseudo), 0x9a404026ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #232 = M2_mpysmi
3737
  { 233,  3,  1,  4,  30, 0|(1ULL<<MCID::Pseudo), 0x4026ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #233 = M2_mpyui
3738
  { 234,  4,  1,  4,  31, 0|(1ULL<<MCID::Pseudo), 0x26ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #234 = M2_vrcmpys_acc_s1
3739
  { 235,  3,  1,  4,  30, 0|(1ULL<<MCID::Pseudo), 0x26ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #235 = M2_vrcmpys_s1
3740
  { 236,  3,  1,  4,  30, 0|(1ULL<<MCID::Pseudo), 0x4026ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #236 = M2_vrcmpys_s1rp
3741
  { 237,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x29ULL, ImplicitList17, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #237 = PS_aligna
3742
  { 238,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x29ULL, nullptr, ImplicitList3, OperandInfo50, -1 ,nullptr },  // Inst #238 = PS_alloca
3743
  { 239,  1,  0,  4,  2,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x588400029ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #239 = PS_call_nr
3744
  { 240,  1,  1,  4,  11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #240 = PS_false
3745
  { 241,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10a400029ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #241 = PS_fi
3746
  { 242,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10b400029ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #242 = PS_fia
3747
  { 243,  6,  2,  4,  32, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1c0000000025ULL, ImplicitList18, ImplicitList18, OperandInfo56, -1 ,nullptr },  // Inst #243 = PS_loadrb_pci
3748
  { 244,  5,  2,  4,  20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1c0000000025ULL, ImplicitList18, ImplicitList18, OperandInfo57, -1 ,nullptr },  // Inst #244 = PS_loadrb_pcr
3749
  { 245,  6,  2,  4,  32, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4c0000000025ULL, ImplicitList18, ImplicitList18, OperandInfo58, -1 ,nullptr },  // Inst #245 = PS_loadrd_pci
3750
  { 246,  5,  2,  4,  20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4c0000000025ULL, ImplicitList18, ImplicitList18, OperandInfo59, -1 ,nullptr },  // Inst #246 = PS_loadrd_pcr
3751
  { 247,  6,  2,  4,  32, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x2c0000000025ULL, ImplicitList18, ImplicitList18, OperandInfo56, -1 ,nullptr },  // Inst #247 = PS_loadrh_pci
3752
  { 248,  5,  2,  4,  20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x2c0000000025ULL, ImplicitList18, ImplicitList18, OperandInfo57, -1 ,nullptr },  // Inst #248 = PS_loadrh_pcr
3753
  { 249,  6,  2,  4,  32, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x3c0000000025ULL, ImplicitList18, ImplicitList18, OperandInfo56, -1 ,nullptr },  // Inst #249 = PS_loadri_pci
3754
  { 250,  5,  2,  4,  20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x3c0000000025ULL, ImplicitList18, ImplicitList18, OperandInfo57, -1 ,nullptr },  // Inst #250 = PS_loadri_pcr
3755
  { 251,  6,  2,  4,  32, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1c0000000025ULL, ImplicitList18, ImplicitList18, OperandInfo56, -1 ,nullptr },  // Inst #251 = PS_loadrub_pci
3756
  { 252,  5,  2,  4,  20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x1c0000000025ULL, ImplicitList18, ImplicitList18, OperandInfo57, -1 ,nullptr },  // Inst #252 = PS_loadrub_pcr
3757
  { 253,  6,  2,  4,  32, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x2c0000000025ULL, ImplicitList18, ImplicitList18, OperandInfo56, -1 ,nullptr },  // Inst #253 = PS_loadruh_pci
3758
  { 254,  5,  2,  4,  20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x2c0000000025ULL, ImplicitList18, ImplicitList18, OperandInfo57, -1 ,nullptr },  // Inst #254 = PS_loadruh_pcr
3759
  { 255,  4,  1,  4,  6,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #255 = PS_pselect
3760
  { 256,  1,  1,  4,  33, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x10ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #256 = PS_qfalse
3761
  { 257,  1,  1,  4,  33, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x10ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #257 = PS_qtrue
3762
  { 258,  6,  1,  4,  34, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1c000000002aULL, ImplicitList18, ImplicitList18, OperandInfo62, -1 ,nullptr },  // Inst #258 = PS_storerb_pci
3763
  { 259,  5,  1,  4,  35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1c000000002aULL, ImplicitList18, ImplicitList18, OperandInfo63, -1 ,nullptr },  // Inst #259 = PS_storerb_pcr
3764
  { 260,  6,  1,  4,  34, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x3c000000002aULL, ImplicitList18, ImplicitList18, OperandInfo64, -1 ,nullptr },  // Inst #260 = PS_storerd_pci
3765
  { 261,  5,  1,  4,  35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x3c000000002aULL, ImplicitList18, ImplicitList18, OperandInfo65, -1 ,nullptr },  // Inst #261 = PS_storerd_pcr
3766
  { 262,  6,  1,  4,  34, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x2c000000002aULL, ImplicitList18, ImplicitList18, OperandInfo62, -1 ,nullptr },  // Inst #262 = PS_storerf_pci
3767
  { 263,  5,  1,  4,  35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x2c000000002aULL, ImplicitList18, ImplicitList18, OperandInfo63, -1 ,nullptr },  // Inst #263 = PS_storerf_pcr
3768
  { 264,  6,  1,  4,  34, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x2c000000002aULL, ImplicitList18, ImplicitList18, OperandInfo62, -1 ,nullptr },  // Inst #264 = PS_storerh_pci
3769
  { 265,  5,  1,  4,  35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x2c000000002aULL, ImplicitList18, ImplicitList18, OperandInfo63, -1 ,nullptr },  // Inst #265 = PS_storerh_pcr
3770
  { 266,  6,  1,  4,  34, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x3c000000002aULL, ImplicitList18, ImplicitList18, OperandInfo62, -1 ,nullptr },  // Inst #266 = PS_storeri_pci
3771
  { 267,  5,  1,  4,  35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x3c000000002aULL, ImplicitList18, ImplicitList18, OperandInfo63, -1 ,nullptr },  // Inst #267 = PS_storeri_pcr
3772
  { 268,  1,  0,  4,  2,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x29ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #268 = PS_tailcall_i
3773
  { 269,  1,  0,  4,  36, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x800000024ULL, nullptr, ImplicitList19, OperandInfo66, -1 ,nullptr },  // Inst #269 = PS_tailcall_r
3774
  { 270,  1,  1,  4,  11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #270 = PS_true
3775
  { 271,  1,  1,  4,  37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x11ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #271 = PS_vdd0
3776
  { 272,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x29ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #272 = PS_vloadrq_ai
3777
  { 273,  3,  1,  4,  38, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x500000000013ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #273 = PS_vloadrw_ai
3778
  { 274,  3,  1,  4,  38, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x500000000013ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #274 = PS_vloadrw_nt_ai
3779
  { 275,  3,  1,  4,  39, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x500000000018ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #275 = PS_vloadrwu_ai
3780
  { 276,  3,  1,  4,  40, 0|(1ULL<<MCID::Pseudo), 0x29ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #276 = PS_vmulw
3781
  { 277,  4,  1,  4,  40, 0|(1ULL<<MCID::Pseudo), 0x29ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #277 = PS_vmulw_acc
3782
  { 278,  4,  1,  4,  41, 0|(1ULL<<MCID::Pseudo), 0x10ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #278 = PS_vselect
3783
  { 279,  3,  0,  4,  2,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x29ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #279 = PS_vstorerq_ai
3784
  { 280,  3,  0,  4,  42, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x500000000015ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr },  // Inst #280 = PS_vstorerw_ai
3785
  { 281,  3,  0,  4,  42, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x500000000015ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr },  // Inst #281 = PS_vstorerw_nt_ai
3786
  { 282,  3,  0,  4,  43, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x500000000016ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr },  // Inst #282 = PS_vstorerwu_ai
3787
  { 283,  4,  1,  4,  44, 0|(1ULL<<MCID::Pseudo), 0x11ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr },  // Inst #283 = PS_wselect
3788
  { 284,  3,  1,  4,  45, 0|(1ULL<<MCID::Pseudo), 0x2cULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr },  // Inst #284 = S2_asr_i_p_rnd_goodsyntax
3789
  { 285,  3,  1,  4,  45, 0|(1ULL<<MCID::Pseudo), 0x402cULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #285 = S2_asr_i_r_rnd_goodsyntax
3790
  { 286,  3,  0,  4,  46, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #286 = S2_pstorerbf_zomap
3791
  { 287,  3,  0,  4,  47, 0|(1ULL<<MCID::Pseudo), 0x10027ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #287 = S2_pstorerbnewf_zomap
3792
  { 288,  3,  0,  4,  47, 0|(1ULL<<MCID::Pseudo), 0x10027ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #288 = S2_pstorerbnewt_zomap
3793
  { 289,  3,  0,  4,  46, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #289 = S2_pstorerbt_zomap
3794
  { 290,  3,  0,  4,  46, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #290 = S2_pstorerdf_zomap
3795
  { 291,  3,  0,  4,  46, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #291 = S2_pstorerdt_zomap
3796
  { 292,  3,  0,  4,  46, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #292 = S2_pstorerff_zomap
3797
  { 293,  3,  0,  4,  46, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #293 = S2_pstorerft_zomap
3798
  { 294,  3,  0,  4,  46, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #294 = S2_pstorerhf_zomap
3799
  { 295,  3,  0,  4,  47, 0|(1ULL<<MCID::Pseudo), 0x10027ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #295 = S2_pstorerhnewf_zomap
3800
  { 296,  3,  0,  4,  47, 0|(1ULL<<MCID::Pseudo), 0x10027ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #296 = S2_pstorerhnewt_zomap
3801
  { 297,  3,  0,  4,  46, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #297 = S2_pstorerht_zomap
3802
  { 298,  3,  0,  4,  46, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #298 = S2_pstorerif_zomap
3803
  { 299,  3,  0,  4,  47, 0|(1ULL<<MCID::Pseudo), 0x10027ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #299 = S2_pstorerinewf_zomap
3804
  { 300,  3,  0,  4,  47, 0|(1ULL<<MCID::Pseudo), 0x10027ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #300 = S2_pstorerinewt_zomap
3805
  { 301,  3,  0,  4,  46, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #301 = S2_pstorerit_zomap
3806
  { 302,  2,  0,  4,  48, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #302 = S2_storerb_zomap
3807
  { 303,  2,  0,  4,  49, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #303 = S2_storerbnew_zomap
3808
  { 304,  2,  0,  4,  48, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr },  // Inst #304 = S2_storerd_zomap
3809
  { 305,  2,  0,  4,  48, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #305 = S2_storerf_zomap
3810
  { 306,  2,  0,  4,  48, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #306 = S2_storerh_zomap
3811
  { 307,  2,  0,  4,  49, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #307 = S2_storerhnew_zomap
3812
  { 308,  2,  0,  4,  48, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #308 = S2_storeri_zomap
3813
  { 309,  2,  0,  4,  49, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #309 = S2_storerinew_zomap
3814
  { 310,  5,  1,  4,  50, 0|(1ULL<<MCID::Pseudo), 0x402cULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr },  // Inst #310 = S2_tableidxb_goodsyntax
3815
  { 311,  5,  1,  4,  50, 0|(1ULL<<MCID::Pseudo), 0x402cULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr },  // Inst #311 = S2_tableidxd_goodsyntax
3816
  { 312,  5,  1,  4,  50, 0|(1ULL<<MCID::Pseudo), 0x402cULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr },  // Inst #312 = S2_tableidxh_goodsyntax
3817
  { 313,  5,  1,  4,  50, 0|(1ULL<<MCID::Pseudo), 0x402cULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr },  // Inst #313 = S2_tableidxw_goodsyntax
3818
  { 314,  3,  0,  4,  35, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #314 = S4_pstorerbfnew_zomap
3819
  { 315,  3,  0,  4,  51, 0|(1ULL<<MCID::Pseudo), 0x10027ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #315 = S4_pstorerbnewfnew_zomap
3820
  { 316,  3,  0,  4,  51, 0|(1ULL<<MCID::Pseudo), 0x10027ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #316 = S4_pstorerbnewtnew_zomap
3821
  { 317,  3,  0,  4,  35, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #317 = S4_pstorerbtnew_zomap
3822
  { 318,  3,  0,  4,  35, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #318 = S4_pstorerdfnew_zomap
3823
  { 319,  3,  0,  4,  35, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #319 = S4_pstorerdtnew_zomap
3824
  { 320,  3,  0,  4,  35, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #320 = S4_pstorerffnew_zomap
3825
  { 321,  3,  0,  4,  35, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #321 = S4_pstorerftnew_zomap
3826
  { 322,  3,  0,  4,  35, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #322 = S4_pstorerhfnew_zomap
3827
  { 323,  3,  0,  4,  51, 0|(1ULL<<MCID::Pseudo), 0x10027ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #323 = S4_pstorerhnewfnew_zomap
3828
  { 324,  3,  0,  4,  51, 0|(1ULL<<MCID::Pseudo), 0x10027ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #324 = S4_pstorerhnewtnew_zomap
3829
  { 325,  3,  0,  4,  35, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #325 = S4_pstorerhtnew_zomap
3830
  { 326,  3,  0,  4,  35, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #326 = S4_pstorerifnew_zomap
3831
  { 327,  3,  0,  4,  51, 0|(1ULL<<MCID::Pseudo), 0x10027ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #327 = S4_pstorerinewfnew_zomap
3832
  { 328,  3,  0,  4,  51, 0|(1ULL<<MCID::Pseudo), 0x10027ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #328 = S4_pstorerinewtnew_zomap
3833
  { 329,  3,  0,  4,  35, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #329 = S4_pstoreritnew_zomap
3834
  { 330,  2,  0,  4,  48, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #330 = S4_storeirb_zomap
3835
  { 331,  3,  0,  4,  46, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #331 = S4_storeirbf_zomap
3836
  { 332,  3,  0,  4,  35, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #332 = S4_storeirbfnew_zomap
3837
  { 333,  3,  0,  4,  46, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #333 = S4_storeirbt_zomap
3838
  { 334,  3,  0,  4,  35, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #334 = S4_storeirbtnew_zomap
3839
  { 335,  2,  0,  4,  48, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #335 = S4_storeirh_zomap
3840
  { 336,  3,  0,  4,  46, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #336 = S4_storeirhf_zomap
3841
  { 337,  3,  0,  4,  35, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #337 = S4_storeirhfnew_zomap
3842
  { 338,  3,  0,  4,  46, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #338 = S4_storeirht_zomap
3843
  { 339,  3,  0,  4,  35, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #339 = S4_storeirhtnew_zomap
3844
  { 340,  2,  0,  4,  48, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #340 = S4_storeiri_zomap
3845
  { 341,  3,  0,  4,  46, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #341 = S4_storeirif_zomap
3846
  { 342,  3,  0,  4,  35, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #342 = S4_storeirifnew_zomap
3847
  { 343,  3,  0,  4,  46, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #343 = S4_storeirit_zomap
3848
  { 344,  3,  0,  4,  35, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #344 = S4_storeiritnew_zomap
3849
  { 345,  3,  1,  4,  45, 0|(1ULL<<MCID::Pseudo), 0x402cULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr },  // Inst #345 = S5_asrhub_rnd_sat_goodsyntax
3850
  { 346,  3,  1,  4,  45, 0|(1ULL<<MCID::Pseudo), 0x2cULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr },  // Inst #346 = S5_vasrhrnd_goodsyntax
3851
  { 347,  1,  0,  4,  52, 0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #347 = S6_allocframe_to_raw
3852
  { 348,  3,  0,  4,  53, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0xd940002aULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #348 = STriw_ctr
3853
  { 349,  3,  0,  4,  53, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0xd940002aULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #349 = STriw_pred
3854
  { 350,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #350 = V6_MAP_equb
3855
  { 351,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #351 = V6_MAP_equb_and
3856
  { 352,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000000027ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #352 = V6_MAP_equb_ior
3857
  { 353,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #353 = V6_MAP_equb_xor
3858
  { 354,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #354 = V6_MAP_equh
3859
  { 355,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #355 = V6_MAP_equh_and
3860
  { 356,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000000027ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #356 = V6_MAP_equh_ior
3861
  { 357,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #357 = V6_MAP_equh_xor
3862
  { 358,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #358 = V6_MAP_equw
3863
  { 359,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #359 = V6_MAP_equw_and
3864
  { 360,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000000027ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #360 = V6_MAP_equw_ior
3865
  { 361,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #361 = V6_MAP_equw_xor
3866
  { 362,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #362 = V6_extractw_alt
3867
  { 363,  2,  1,  4,  54, 0|(1ULL<<MCID::Pseudo), 0x4010ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr },  // Inst #363 = V6_hi
3868
  { 364,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4013ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr },  // Inst #364 = V6_ld0
3869
  { 365,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #365 = V6_ldcnp0
3870
  { 366,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #366 = V6_ldcnpnt0
3871
  { 367,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #367 = V6_ldcp0
3872
  { 368,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #368 = V6_ldcpnt0
3873
  { 369,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #369 = V6_ldnp0
3874
  { 370,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #370 = V6_ldnpnt0
3875
  { 371,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4013ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr },  // Inst #371 = V6_ldnt0
3876
  { 372,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr },  // Inst #372 = V6_ldntnt0
3877
  { 373,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #373 = V6_ldp0
3878
  { 374,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #374 = V6_ldpnt0
3879
  { 375,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #375 = V6_ldtnp0
3880
  { 376,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #376 = V6_ldtnpnt0
3881
  { 377,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #377 = V6_ldtp0
3882
  { 378,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #378 = V6_ldtpnt0
3883
  { 379,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4013ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr },  // Inst #379 = V6_ldu0
3884
  { 380,  2,  1,  4,  54, 0|(1ULL<<MCID::Pseudo), 0x4010ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr },  // Inst #380 = V6_lo
3885
  { 381,  2,  0,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x15ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #381 = V6_st0
3886
  { 382,  2,  0,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x8015ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #382 = V6_stn0
3887
  { 383,  2,  0,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x8015ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #383 = V6_stnnt0
3888
  { 384,  3,  0,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x15ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #384 = V6_stnp0
3889
  { 385,  3,  0,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x15ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #385 = V6_stnpnt0
3890
  { 386,  3,  0,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x15ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #386 = V6_stnq0
3891
  { 387,  3,  0,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x15ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #387 = V6_stnqnt0
3892
  { 388,  2,  0,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x15ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #388 = V6_stnt0
3893
  { 389,  3,  0,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x15ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #389 = V6_stp0
3894
  { 390,  3,  0,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x15ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #390 = V6_stpnt0
3895
  { 391,  3,  0,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x15ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #391 = V6_stq0
3896
  { 392,  3,  0,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x15ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #392 = V6_stqnt0
3897
  { 393,  2,  0,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x15ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #393 = V6_stu0
3898
  { 394,  3,  0,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x15ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #394 = V6_stunp0
3899
  { 395,  3,  0,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x15ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #395 = V6_stup0
3900
  { 396,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #396 = V6_vabsb_alt
3901
  { 397,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #397 = V6_vabsb_sat_alt
3902
  { 398,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #398 = V6_vabsdiffh_alt
3903
  { 399,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #399 = V6_vabsdiffub_alt
3904
  { 400,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #400 = V6_vabsdiffuh_alt
3905
  { 401,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #401 = V6_vabsdiffw_alt
3906
  { 402,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #402 = V6_vabsh_alt
3907
  { 403,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #403 = V6_vabsh_sat_alt
3908
  { 404,  2,  1,  4,  55, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #404 = V6_vabsub_alt
3909
  { 405,  2,  1,  4,  55, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #405 = V6_vabsuh_alt
3910
  { 406,  2,  1,  4,  55, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #406 = V6_vabsuw_alt
3911
  { 407,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #407 = V6_vabsw_alt
3912
  { 408,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #408 = V6_vabsw_sat_alt
3913
  { 409,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #409 = V6_vaddb_alt
3914
  { 410,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #410 = V6_vaddb_dv_alt
3915
  { 411,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #411 = V6_vaddbnq_alt
3916
  { 412,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #412 = V6_vaddbq_alt
3917
  { 413,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #413 = V6_vaddbsat_alt
3918
  { 414,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #414 = V6_vaddbsat_dv_alt
3919
  { 415,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #415 = V6_vaddh_alt
3920
  { 416,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #416 = V6_vaddh_dv_alt
3921
  { 417,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #417 = V6_vaddhnq_alt
3922
  { 418,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #418 = V6_vaddhq_alt
3923
  { 419,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #419 = V6_vaddhsat_alt
3924
  { 420,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #420 = V6_vaddhsat_dv_alt
3925
  { 421,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #421 = V6_vaddhw_acc_alt
3926
  { 422,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #422 = V6_vaddhw_alt
3927
  { 423,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #423 = V6_vaddubh_acc_alt
3928
  { 424,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #424 = V6_vaddubh_alt
3929
  { 425,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #425 = V6_vaddubsat_alt
3930
  { 426,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #426 = V6_vaddubsat_dv_alt
3931
  { 427,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #427 = V6_vadduhsat_alt
3932
  { 428,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #428 = V6_vadduhsat_dv_alt
3933
  { 429,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #429 = V6_vadduhw_acc_alt
3934
  { 430,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #430 = V6_vadduhw_alt
3935
  { 431,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #431 = V6_vadduwsat_alt
3936
  { 432,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #432 = V6_vadduwsat_dv_alt
3937
  { 433,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #433 = V6_vaddw_alt
3938
  { 434,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #434 = V6_vaddw_dv_alt
3939
  { 435,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #435 = V6_vaddwnq_alt
3940
  { 436,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #436 = V6_vaddwq_alt
3941
  { 437,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #437 = V6_vaddwsat_alt
3942
  { 438,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #438 = V6_vaddwsat_dv_alt
3943
  { 439,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr },  // Inst #439 = V6_vandnqrt_acc_alt
3944
  { 440,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #440 = V6_vandnqrt_alt
3945
  { 441,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr },  // Inst #441 = V6_vandqrt_acc_alt
3946
  { 442,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #442 = V6_vandqrt_alt
3947
  { 443,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000000027ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr },  // Inst #443 = V6_vandvrt_acc_alt
3948
  { 444,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr },  // Inst #444 = V6_vandvrt_alt
3949
  { 445,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #445 = V6_vaslh_acc_alt
3950
  { 446,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #446 = V6_vaslh_alt
3951
  { 447,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #447 = V6_vaslhv_alt
3952
  { 448,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #448 = V6_vaslw_acc_alt
3953
  { 449,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #449 = V6_vaslw_alt
3954
  { 450,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #450 = V6_vaslwv_alt
3955
  { 451,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #451 = V6_vasrh_acc_alt
3956
  { 452,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #452 = V6_vasrh_alt
3957
  { 453,  4,  1,  4,  56, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #453 = V6_vasrhbrndsat_alt
3958
  { 454,  4,  1,  4,  56, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #454 = V6_vasrhubrndsat_alt
3959
  { 455,  4,  1,  4,  56, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #455 = V6_vasrhubsat_alt
3960
  { 456,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #456 = V6_vasrhv_alt
3961
  { 457,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #457 = V6_vasrw_acc_alt
3962
  { 458,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #458 = V6_vasrw_alt
3963
  { 459,  4,  1,  4,  56, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #459 = V6_vasrwh_alt
3964
  { 460,  4,  1,  4,  56, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #460 = V6_vasrwhrndsat_alt
3965
  { 461,  4,  1,  4,  56, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #461 = V6_vasrwhsat_alt
3966
  { 462,  4,  1,  4,  56, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #462 = V6_vasrwuhsat_alt
3967
  { 463,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #463 = V6_vasrwv_alt
3968
  { 464,  2,  1,  4,  54, 0|(1ULL<<MCID::Pseudo), 0x4011ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr },  // Inst #464 = V6_vassignp
3969
  { 465,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #465 = V6_vavgb_alt
3970
  { 466,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #466 = V6_vavgbrnd_alt
3971
  { 467,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #467 = V6_vavgh_alt
3972
  { 468,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #468 = V6_vavghrnd_alt
3973
  { 469,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #469 = V6_vavgub_alt
3974
  { 470,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #470 = V6_vavgubrnd_alt
3975
  { 471,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #471 = V6_vavguh_alt
3976
  { 472,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #472 = V6_vavguhrnd_alt
3977
  { 473,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #473 = V6_vavguw_alt
3978
  { 474,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #474 = V6_vavguwrnd_alt
3979
  { 475,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #475 = V6_vavgw_alt
3980
  { 476,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #476 = V6_vavgwrnd_alt
3981
  { 477,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #477 = V6_vcl0h_alt
3982
  { 478,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #478 = V6_vcl0w_alt
3983
  { 479,  1,  1,  4,  54, 0|(1ULL<<MCID::Pseudo), 0x4010ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr },  // Inst #479 = V6_vd0
3984
  { 480,  1,  1,  4,  57, 0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #480 = V6_vdd0
3985
  { 481,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #481 = V6_vdealb4w_alt
3986
  { 482,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #482 = V6_vdealb_alt
3987
  { 483,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #483 = V6_vdealh_alt
3988
  { 484,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #484 = V6_vdmpybus_acc_alt
3989
  { 485,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #485 = V6_vdmpybus_alt
3990
  { 486,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #486 = V6_vdmpybus_dv_acc_alt
3991
  { 487,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #487 = V6_vdmpybus_dv_alt
3992
  { 488,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #488 = V6_vdmpyhb_acc_alt
3993
  { 489,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #489 = V6_vdmpyhb_alt
3994
  { 490,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #490 = V6_vdmpyhb_dv_acc_alt
3995
  { 491,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #491 = V6_vdmpyhb_dv_alt
3996
  { 492,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #492 = V6_vdmpyhisat_acc_alt
3997
  { 493,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #493 = V6_vdmpyhisat_alt
3998
  { 494,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #494 = V6_vdmpyhsat_acc_alt
3999
  { 495,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #495 = V6_vdmpyhsat_alt
4000
  { 496,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #496 = V6_vdmpyhsuisat_acc_alt
4001
  { 497,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #497 = V6_vdmpyhsuisat_alt
4002
  { 498,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #498 = V6_vdmpyhsusat_acc_alt
4003
  { 499,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #499 = V6_vdmpyhsusat_alt
4004
  { 500,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #500 = V6_vdmpyhvsat_acc_alt
4005
  { 501,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #501 = V6_vdmpyhvsat_alt
4006
  { 502,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #502 = V6_vdsaduh_acc_alt
4007
  { 503,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #503 = V6_vdsaduh_alt
4008
  { 504,  4,  0,  4,  58, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr },  // Inst #504 = V6_vgathermh_pseudo
4009
  { 505,  5,  0,  4,  58, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #505 = V6_vgathermhq_pseudo
4010
  { 506,  4,  0,  4,  58, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr },  // Inst #506 = V6_vgathermhw_pseudo
4011
  { 507,  5,  0,  4,  58, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr },  // Inst #507 = V6_vgathermhwq_pseudo
4012
  { 508,  4,  0,  4,  58, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr },  // Inst #508 = V6_vgathermw_pseudo
4013
  { 509,  5,  0,  4,  58, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #509 = V6_vgathermwq_pseudo
4014
  { 510,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #510 = V6_vlsrh_alt
4015
  { 511,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #511 = V6_vlsrhv_alt
4016
  { 512,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #512 = V6_vlsrw_alt
4017
  { 513,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #513 = V6_vlsrwv_alt
4018
  { 514,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #514 = V6_vmaxb_alt
4019
  { 515,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #515 = V6_vmaxh_alt
4020
  { 516,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #516 = V6_vmaxub_alt
4021
  { 517,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #517 = V6_vmaxuh_alt
4022
  { 518,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #518 = V6_vmaxw_alt
4023
  { 519,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #519 = V6_vminb_alt
4024
  { 520,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #520 = V6_vminh_alt
4025
  { 521,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #521 = V6_vminub_alt
4026
  { 522,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #522 = V6_vminuh_alt
4027
  { 523,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #523 = V6_vminw_alt
4028
  { 524,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #524 = V6_vmpabus_acc_alt
4029
  { 525,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #525 = V6_vmpabus_alt
4030
  { 526,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #526 = V6_vmpabusv_alt
4031
  { 527,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #527 = V6_vmpabuu_acc_alt
4032
  { 528,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #528 = V6_vmpabuu_alt
4033
  { 529,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #529 = V6_vmpabuuv_alt
4034
  { 530,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #530 = V6_vmpahb_acc_alt
4035
  { 531,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #531 = V6_vmpahb_alt
4036
  { 532,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #532 = V6_vmpauhb_acc_alt
4037
  { 533,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #533 = V6_vmpauhb_alt
4038
  { 534,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #534 = V6_vmpybus_acc_alt
4039
  { 535,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #535 = V6_vmpybus_alt
4040
  { 536,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #536 = V6_vmpybusv_acc_alt
4041
  { 537,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #537 = V6_vmpybusv_alt
4042
  { 538,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #538 = V6_vmpybv_acc_alt
4043
  { 539,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #539 = V6_vmpybv_alt
4044
  { 540,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #540 = V6_vmpyewuh_alt
4045
  { 541,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #541 = V6_vmpyh_acc_alt
4046
  { 542,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #542 = V6_vmpyh_alt
4047
  { 543,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #543 = V6_vmpyhsat_acc_alt
4048
  { 544,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #544 = V6_vmpyhsrs_alt
4049
  { 545,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #545 = V6_vmpyhss_alt
4050
  { 546,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #546 = V6_vmpyhus_acc_alt
4051
  { 547,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #547 = V6_vmpyhus_alt
4052
  { 548,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #548 = V6_vmpyhv_acc_alt
4053
  { 549,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #549 = V6_vmpyhv_alt
4054
  { 550,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #550 = V6_vmpyhvsrs_alt
4055
  { 551,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #551 = V6_vmpyiewh_acc_alt
4056
  { 552,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #552 = V6_vmpyiewuh_acc_alt
4057
  { 553,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #553 = V6_vmpyiewuh_alt
4058
  { 554,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #554 = V6_vmpyih_acc_alt
4059
  { 555,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #555 = V6_vmpyih_alt
4060
  { 556,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #556 = V6_vmpyihb_acc_alt
4061
  { 557,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #557 = V6_vmpyihb_alt
4062
  { 558,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #558 = V6_vmpyiowh_alt
4063
  { 559,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #559 = V6_vmpyiwb_acc_alt
4064
  { 560,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #560 = V6_vmpyiwb_alt
4065
  { 561,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #561 = V6_vmpyiwh_acc_alt
4066
  { 562,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #562 = V6_vmpyiwh_alt
4067
  { 563,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #563 = V6_vmpyiwub_acc_alt
4068
  { 564,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #564 = V6_vmpyiwub_alt
4069
  { 565,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #565 = V6_vmpyowh_alt
4070
  { 566,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #566 = V6_vmpyowh_rnd_alt
4071
  { 567,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #567 = V6_vmpyowh_rnd_sacc_alt
4072
  { 568,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #568 = V6_vmpyowh_sacc_alt
4073
  { 569,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #569 = V6_vmpyub_acc_alt
4074
  { 570,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #570 = V6_vmpyub_alt
4075
  { 571,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #571 = V6_vmpyubv_acc_alt
4076
  { 572,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #572 = V6_vmpyubv_alt
4077
  { 573,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #573 = V6_vmpyuh_acc_alt
4078
  { 574,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #574 = V6_vmpyuh_alt
4079
  { 575,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #575 = V6_vmpyuhv_acc_alt
4080
  { 576,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #576 = V6_vmpyuhv_alt
4081
  { 577,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #577 = V6_vnavgb_alt
4082
  { 578,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #578 = V6_vnavgh_alt
4083
  { 579,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #579 = V6_vnavgub_alt
4084
  { 580,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #580 = V6_vnavgw_alt
4085
  { 581,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #581 = V6_vnormamth_alt
4086
  { 582,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #582 = V6_vnormamtw_alt
4087
  { 583,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #583 = V6_vpackeb_alt
4088
  { 584,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #584 = V6_vpackeh_alt
4089
  { 585,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #585 = V6_vpackhb_sat_alt
4090
  { 586,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #586 = V6_vpackhub_sat_alt
4091
  { 587,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #587 = V6_vpackob_alt
4092
  { 588,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #588 = V6_vpackoh_alt
4093
  { 589,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #589 = V6_vpackwh_sat_alt
4094
  { 590,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #590 = V6_vpackwuh_sat_alt
4095
  { 591,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #591 = V6_vpopcounth_alt
4096
  { 592,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #592 = V6_vrmpybub_rtt_acc_alt
4097
  { 593,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr },  // Inst #593 = V6_vrmpybub_rtt_alt
4098
  { 594,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #594 = V6_vrmpybus_acc_alt
4099
  { 595,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #595 = V6_vrmpybus_alt
4100
  { 596,  5,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #596 = V6_vrmpybusi_acc_alt
4101
  { 597,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #597 = V6_vrmpybusi_alt
4102
  { 598,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #598 = V6_vrmpybusv_acc_alt
4103
  { 599,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #599 = V6_vrmpybusv_alt
4104
  { 600,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #600 = V6_vrmpybv_acc_alt
4105
  { 601,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #601 = V6_vrmpybv_alt
4106
  { 602,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #602 = V6_vrmpyub_acc_alt
4107
  { 603,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #603 = V6_vrmpyub_alt
4108
  { 604,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #604 = V6_vrmpyub_rtt_acc_alt
4109
  { 605,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr },  // Inst #605 = V6_vrmpyub_rtt_alt
4110
  { 606,  5,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #606 = V6_vrmpyubi_acc_alt
4111
  { 607,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #607 = V6_vrmpyubi_alt
4112
  { 608,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #608 = V6_vrmpyubv_acc_alt
4113
  { 609,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #609 = V6_vrmpyubv_alt
4114
  { 610,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #610 = V6_vroundhb_alt
4115
  { 611,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #611 = V6_vroundhub_alt
4116
  { 612,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #612 = V6_vrounduhub_alt
4117
  { 613,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #613 = V6_vrounduwuh_alt
4118
  { 614,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #614 = V6_vroundwh_alt
4119
  { 615,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #615 = V6_vroundwuh_alt
4120
  { 616,  5,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #616 = V6_vrsadubi_acc_alt
4121
  { 617,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #617 = V6_vrsadubi_alt
4122
  { 618,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #618 = V6_vsathub_alt
4123
  { 619,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #619 = V6_vsatuwuh_alt
4124
  { 620,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #620 = V6_vsatwh_alt
4125
  { 621,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #621 = V6_vsb_alt
4126
  { 622,  4,  0,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000000027ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #622 = V6_vscattermh_add_alt
4127
  { 623,  4,  0,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #623 = V6_vscattermh_alt
4128
  { 624,  5,  0,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #624 = V6_vscattermhq_alt
4129
  { 625,  4,  0,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000000027ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #625 = V6_vscattermw_add_alt
4130
  { 626,  4,  0,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #626 = V6_vscattermw_alt
4131
  { 627,  4,  0,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000000027ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #627 = V6_vscattermwh_add_alt
4132
  { 628,  4,  0,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #628 = V6_vscattermwh_alt
4133
  { 629,  5,  0,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr },  // Inst #629 = V6_vscattermwhq_alt
4134
  { 630,  5,  0,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x27ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #630 = V6_vscattermwq_alt
4135
  { 631,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #631 = V6_vsh_alt
4136
  { 632,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #632 = V6_vshufeh_alt
4137
  { 633,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #633 = V6_vshuffb_alt
4138
  { 634,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #634 = V6_vshuffeb_alt
4139
  { 635,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #635 = V6_vshuffh_alt
4140
  { 636,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #636 = V6_vshuffob_alt
4141
  { 637,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #637 = V6_vshufoeb_alt
4142
  { 638,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #638 = V6_vshufoeh_alt
4143
  { 639,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #639 = V6_vshufoh_alt
4144
  { 640,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #640 = V6_vsubb_alt
4145
  { 641,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #641 = V6_vsubb_dv_alt
4146
  { 642,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #642 = V6_vsubbnq_alt
4147
  { 643,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #643 = V6_vsubbq_alt
4148
  { 644,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #644 = V6_vsubbsat_alt
4149
  { 645,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #645 = V6_vsubbsat_dv_alt
4150
  { 646,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #646 = V6_vsubh_alt
4151
  { 647,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #647 = V6_vsubh_dv_alt
4152
  { 648,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #648 = V6_vsubhnq_alt
4153
  { 649,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #649 = V6_vsubhq_alt
4154
  { 650,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #650 = V6_vsubhsat_alt
4155
  { 651,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #651 = V6_vsubhsat_dv_alt
4156
  { 652,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #652 = V6_vsubhw_alt
4157
  { 653,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #653 = V6_vsububh_alt
4158
  { 654,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #654 = V6_vsububsat_alt
4159
  { 655,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #655 = V6_vsububsat_dv_alt
4160
  { 656,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #656 = V6_vsubuhsat_alt
4161
  { 657,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #657 = V6_vsubuhsat_dv_alt
4162
  { 658,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #658 = V6_vsubuhw_alt
4163
  { 659,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #659 = V6_vsubuwsat_alt
4164
  { 660,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #660 = V6_vsubuwsat_dv_alt
4165
  { 661,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #661 = V6_vsubw_alt
4166
  { 662,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #662 = V6_vsubw_dv_alt
4167
  { 663,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #663 = V6_vsubwnq_alt
4168
  { 664,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #664 = V6_vsubwq_alt
4169
  { 665,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #665 = V6_vsubwsat_alt
4170
  { 666,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #666 = V6_vsubwsat_dv_alt
4171
  { 667,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #667 = V6_vtmpyb_acc_alt
4172
  { 668,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #668 = V6_vtmpyb_alt
4173
  { 669,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #669 = V6_vtmpybus_acc_alt
4174
  { 670,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #670 = V6_vtmpybus_alt
4175
  { 671,  4,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #671 = V6_vtmpyhb_acc_alt
4176
  { 672,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #672 = V6_vtmpyhb_alt
4177
  { 673,  5,  2,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x18000000004027ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #673 = V6_vtran2x2_map
4178
  { 674,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #674 = V6_vunpackb_alt
4179
  { 675,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #675 = V6_vunpackh_alt
4180
  { 676,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr },  // Inst #676 = V6_vunpackob_alt
4181
  { 677,  3,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x80000000004027ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr },  // Inst #677 = V6_vunpackoh_alt
4182
  { 678,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #678 = V6_vunpackub_alt
4183
  { 679,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #679 = V6_vunpackuh_alt
4184
  { 680,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #680 = V6_vzb_alt
4185
  { 681,  2,  1,  4,  2,  0|(1ULL<<MCID::Pseudo), 0x4027ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #681 = V6_vzh_alt
4186
  { 682,  1,  0,  4,  59, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x27ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #682 = Y2_dcfetch
4187
  { 683,  2,  1,  4,  60, 0, 0x10000000000402cULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #683 = A2_abs
4188
  { 684,  2,  1,  4,  60, 0, 0x10000000000002cULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #684 = A2_absp
4189
  { 685,  2,  1,  4,  60, 0, 0x10000000000402cULL, nullptr, ImplicitList20, OperandInfo33, -1 ,nullptr },  // Inst #685 = A2_abssat
4190
  { 686,  3,  1,  4,  6,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x4001ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #686 = A2_add
4191
  { 687,  3,  1,  4,  1,  0, 0x100000000004003ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #687 = A2_addh_h16_hh
4192
  { 688,  3,  1,  4,  1,  0, 0x100000000004003ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #688 = A2_addh_h16_hl
4193
  { 689,  3,  1,  4,  1,  0, 0x100000000004003ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #689 = A2_addh_h16_lh
4194
  { 690,  3,  1,  4,  1,  0, 0x100000000004003ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #690 = A2_addh_h16_ll
4195
  { 691,  3,  1,  4,  61, 0, 0x100000000004003ULL, nullptr, ImplicitList20, OperandInfo51, -1 ,nullptr },  // Inst #691 = A2_addh_h16_sat_hh
4196
  { 692,  3,  1,  4,  61, 0, 0x100000000004003ULL, nullptr, ImplicitList20, OperandInfo51, -1 ,nullptr },  // Inst #692 = A2_addh_h16_sat_hl
4197
  { 693,  3,  1,  4,  61, 0, 0x100000000004003ULL, nullptr, ImplicitList20, OperandInfo51, -1 ,nullptr },  // Inst #693 = A2_addh_h16_sat_lh
4198
  { 694,  3,  1,  4,  61, 0, 0x100000000004003ULL, nullptr, ImplicitList20, OperandInfo51, -1 ,nullptr },  // Inst #694 = A2_addh_h16_sat_ll
4199
  { 695,  3,  1,  4,  62, 0, 0x100000000004003ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #695 = A2_addh_l16_hl
4200
  { 696,  3,  1,  4,  62, 0, 0x100000000004003ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #696 = A2_addh_l16_ll
4201
  { 697,  3,  1,  4,  61, 0, 0x100000000004003ULL, nullptr, ImplicitList20, OperandInfo51, -1 ,nullptr },  // Inst #697 = A2_addh_l16_sat_hl
4202
  { 698,  3,  1,  4,  61, 0, 0x100000000004003ULL, nullptr, ImplicitList20, OperandInfo51, -1 ,nullptr },  // Inst #698 = A2_addh_l16_sat_ll
4203
  { 699,  3,  1,  4,  6,  0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable), 0x10a404002ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #699 = A2_addi
4204
  { 700,  3,  1,  4,  8,  0|(1ULL<<MCID::Add)|(1ULL<<MCID::Commutable), 0x3ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #700 = A2_addp
4205
  { 701,  3,  1,  4,  61, 0|(1ULL<<MCID::Commutable), 0x100000000000003ULL, nullptr, ImplicitList20, OperandInfo38, -1 ,nullptr },  // Inst #701 = A2_addpsat
4206
  { 702,  3,  1,  4,  63, 0|(1ULL<<MCID::Commutable), 0x100000000004001ULL, nullptr, ImplicitList20, OperandInfo51, -1 ,nullptr },  // Inst #702 = A2_addsat
4207
  { 703,  3,  1,  4,  1,  0, 0x100000000000003ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #703 = A2_addsph
4208
  { 704,  3,  1,  4,  1,  0, 0x100000000000003ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #704 = A2_addspl
4209
  { 705,  3,  1,  4,  6,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x4001ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #705 = A2_and
4210
  { 706,  3,  1,  4,  6,  0, 0xaa404000ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #706 = A2_andir
4211
  { 707,  3,  1,  4,  8,  0|(1ULL<<MCID::Commutable), 0x3ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #707 = A2_andp
4212
  { 708,  2,  1,  4,  3,  0|(1ULL<<MCID::Predicable), 0x4000ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #708 = A2_aslh
4213
  { 709,  2,  1,  4,  3,  0|(1ULL<<MCID::Predicable), 0x4000ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #709 = A2_asrh
4214
  { 710,  3,  1,  4,  6,  0, 0x4001ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #710 = A2_combine_hh
4215
  { 711,  3,  1,  4,  6,  0, 0x4001ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #711 = A2_combine_hl
4216
  { 712,  3,  1,  4,  6,  0, 0x4001ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #712 = A2_combine_lh
4217
  { 713,  3,  1,  4,  6,  0, 0x4001ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #713 = A2_combine_ll
4218
  { 714,  3,  1,  4,  6,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x89400000ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr },  // Inst #714 = A2_combineii
4219
  { 715,  3,  1,  4,  6,  0|(1ULL<<MCID::Predicable), 0x1ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr },  // Inst #715 = A2_combinew
4220
  { 716,  3,  1,  4,  61, 0, 0x100000000004003ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #716 = A2_max
4221
  { 717,  3,  1,  4,  61, 0, 0x100000000000003ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #717 = A2_maxp
4222
  { 718,  3,  1,  4,  61, 0, 0x100000000004003ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #718 = A2_maxu
4223
  { 719,  3,  1,  4,  61, 0, 0x100000000000003ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #719 = A2_maxup
4224
  { 720,  3,  1,  4,  61, 0, 0x100000000004003ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #720 = A2_min
4225
  { 721,  3,  1,  4,  61, 0, 0x100000000000003ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #721 = A2_minp
4226
  { 722,  3,  1,  4,  61, 0, 0x100000000004003ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #722 = A2_minu
4227
  { 723,  3,  1,  4,  61, 0, 0x100000000000003ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #723 = A2_minup
4228
  { 724,  2,  1,  4,  64, 0, 0x2cULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #724 = A2_negp
4229
  { 725,  2,  1,  4,  60, 0, 0x10000000000402cULL, nullptr, ImplicitList20, OperandInfo33, -1 ,nullptr },  // Inst #725 = A2_negsat
4230
  { 726,  0,  0,  4,  65, 0, 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #726 = A2_nop
4231
  { 727,  2,  1,  4,  64, 0, 0x2cULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #727 = A2_notp
4232
  { 728,  3,  1,  4,  6,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x4001ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #728 = A2_or
4233
  { 729,  3,  1,  4,  6,  0, 0xaa404000ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #729 = A2_orir
4234
  { 730,  3,  1,  4,  8,  0|(1ULL<<MCID::Commutable), 0x3ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #730 = A2_orp
4235
  { 731,  4,  1,  4,  4,  0, 0x4601ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #731 = A2_paddf
4236
  { 732,  4,  1,  4,  5,  0, 0x4e01ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #732 = A2_paddfnew
4237
  { 733,  4,  1,  4,  4,  0, 0x8b404600ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr },  // Inst #733 = A2_paddif
4238
  { 734,  4,  1,  4,  5,  0, 0x8b404e00ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr },  // Inst #734 = A2_paddifnew
4239
  { 735,  4,  1,  4,  4,  0, 0x8b404200ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr },  // Inst #735 = A2_paddit
4240
  { 736,  4,  1,  4,  5,  0, 0x8b404a00ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr },  // Inst #736 = A2_padditnew
4241
  { 737,  4,  1,  4,  4,  0, 0x4201ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #737 = A2_paddt
4242
  { 738,  4,  1,  4,  5,  0, 0x4a01ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #738 = A2_paddtnew
4243
  { 739,  4,  1,  4,  4,  0, 0x4601ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #739 = A2_pandf
4244
  { 740,  4,  1,  4,  5,  0, 0x4e01ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #740 = A2_pandfnew
4245
  { 741,  4,  1,  4,  4,  0, 0x4201ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #741 = A2_pandt
4246
  { 742,  4,  1,  4,  5,  0, 0x4a01ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #742 = A2_pandtnew
4247
  { 743,  4,  1,  4,  4,  0, 0x4601ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #743 = A2_porf
4248
  { 744,  4,  1,  4,  5,  0, 0x4e01ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #744 = A2_porfnew
4249
  { 745,  4,  1,  4,  4,  0, 0x4201ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #745 = A2_port
4250
  { 746,  4,  1,  4,  5,  0, 0x4a01ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #746 = A2_portnew
4251
  { 747,  4,  1,  4,  4,  0, 0x4601ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #747 = A2_psubf
4252
  { 748,  4,  1,  4,  5,  0, 0x4e01ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #748 = A2_psubfnew
4253
  { 749,  4,  1,  4,  4,  0, 0x4201ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #749 = A2_psubt
4254
  { 750,  4,  1,  4,  5,  0, 0x4a01ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #750 = A2_psubtnew
4255
  { 751,  4,  1,  4,  4,  0, 0x4601ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #751 = A2_pxorf
4256
  { 752,  4,  1,  4,  5,  0, 0x4e01ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #752 = A2_pxorfnew
4257
  { 753,  4,  1,  4,  4,  0, 0x4201ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #753 = A2_pxort
4258
  { 754,  4,  1,  4,  5,  0, 0x4a01ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #754 = A2_pxortnew
4259
  { 755,  2,  1,  4,  60, 0, 0x10000000000402cULL, nullptr, ImplicitList20, OperandInfo76, -1 ,nullptr },  // Inst #755 = A2_roundsat
4260
  { 756,  2,  1,  4,  64, 0, 0x402cULL, nullptr, ImplicitList20, OperandInfo76, -1 ,nullptr },  // Inst #756 = A2_sat
4261
  { 757,  2,  1,  4,  64, 0, 0x402cULL, nullptr, ImplicitList20, OperandInfo33, -1 ,nullptr },  // Inst #757 = A2_satb
4262
  { 758,  2,  1,  4,  64, 0, 0x402cULL, nullptr, ImplicitList20, OperandInfo33, -1 ,nullptr },  // Inst #758 = A2_sath
4263
  { 759,  2,  1,  4,  64, 0, 0x402cULL, nullptr, ImplicitList20, OperandInfo33, -1 ,nullptr },  // Inst #759 = A2_satub
4264
  { 760,  2,  1,  4,  64, 0, 0x402cULL, nullptr, ImplicitList20, OperandInfo33, -1 ,nullptr },  // Inst #760 = A2_satuh
4265
  { 761,  3,  1,  4,  6,  0|(1ULL<<MCID::Predicable), 0x4001ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #761 = A2_sub
4266
  { 762,  3,  1,  4,  1,  0, 0x100000000004003ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #762 = A2_subh_h16_hh
4267
  { 763,  3,  1,  4,  1,  0, 0x100000000004003ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #763 = A2_subh_h16_hl
4268
  { 764,  3,  1,  4,  1,  0, 0x100000000004003ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #764 = A2_subh_h16_lh
4269
  { 765,  3,  1,  4,  1,  0, 0x100000000004003ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #765 = A2_subh_h16_ll
4270
  { 766,  3,  1,  4,  61, 0, 0x100000000004003ULL, nullptr, ImplicitList20, OperandInfo51, -1 ,nullptr },  // Inst #766 = A2_subh_h16_sat_hh
4271
  { 767,  3,  1,  4,  61, 0, 0x100000000004003ULL, nullptr, ImplicitList20, OperandInfo51, -1 ,nullptr },  // Inst #767 = A2_subh_h16_sat_hl
4272
  { 768,  3,  1,  4,  61, 0, 0x100000000004003ULL, nullptr, ImplicitList20, OperandInfo51, -1 ,nullptr },  // Inst #768 = A2_subh_h16_sat_lh
4273
  { 769,  3,  1,  4,  61, 0, 0x100000000004003ULL, nullptr, ImplicitList20, OperandInfo51, -1 ,nullptr },  // Inst #769 = A2_subh_h16_sat_ll
4274
  { 770,  3,  1,  4,  62, 0, 0x100000000004003ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #770 = A2_subh_l16_hl
4275
  { 771,  3,  1,  4,  62, 0, 0x100000000004003ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #771 = A2_subh_l16_ll
4276
  { 772,  3,  1,  4,  61, 0, 0x100000000004003ULL, nullptr, ImplicitList20, OperandInfo51, -1 ,nullptr },  // Inst #772 = A2_subh_l16_sat_hl
4277
  { 773,  3,  1,  4,  61, 0, 0x100000000004003ULL, nullptr, ImplicitList20, OperandInfo51, -1 ,nullptr },  // Inst #773 = A2_subh_l16_sat_ll
4278
  { 774,  3,  1,  4,  8,  0, 0x3ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #774 = A2_subp
4279
  { 775,  3,  1,  4,  6,  0, 0xa9404000ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #775 = A2_subri
4280
  { 776,  3,  1,  4,  63, 0, 0x100000000004001ULL, nullptr, ImplicitList20, OperandInfo51, -1 ,nullptr },  // Inst #776 = A2_subsat
4281
  { 777,  3,  1,  4,  6,  0|(1ULL<<MCID::Commutable), 0x4001ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #777 = A2_svaddh
4282
  { 778,  3,  1,  4,  63, 0|(1ULL<<MCID::Commutable), 0x100000000004001ULL, nullptr, ImplicitList20, OperandInfo51, -1 ,nullptr },  // Inst #778 = A2_svaddhs
4283
  { 779,  3,  1,  4,  63, 0|(1ULL<<MCID::Commutable), 0x100000000004001ULL, nullptr, ImplicitList20, OperandInfo51, -1 ,nullptr },  // Inst #779 = A2_svadduhs
4284
  { 780,  3,  1,  4,  6,  0|(1ULL<<MCID::Commutable), 0x4001ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #780 = A2_svavgh
4285
  { 781,  3,  1,  4,  66, 0|(1ULL<<MCID::Commutable), 0x4001ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #781 = A2_svavghs
4286
  { 782,  3,  1,  4,  6,  0, 0x4001ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #782 = A2_svnavgh
4287
  { 783,  3,  1,  4,  6,  0, 0x4001ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #783 = A2_svsubh
4288
  { 784,  3,  1,  4,  63, 0, 0x100000000004001ULL, nullptr, ImplicitList20, OperandInfo51, -1 ,nullptr },  // Inst #784 = A2_svsubhs
4289
  { 785,  3,  1,  4,  63, 0, 0x100000000004001ULL, nullptr, ImplicitList20, OperandInfo51, -1 ,nullptr },  // Inst #785 = A2_svsubuhs
4290
  { 786,  2,  1,  4,  64, 0, 0x402cULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #786 = A2_swiz
4291
  { 787,  2,  1,  4,  3,  0|(1ULL<<MCID::Predicable), 0x4000ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #787 = A2_sxtb
4292
  { 788,  2,  1,  4,  3,  0|(1ULL<<MCID::Predicable), 0x4000ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #788 = A2_sxth
4293
  { 789,  2,  1,  4,  64, 0, 0x2cULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #789 = A2_sxtw
4294
  { 790,  2,  1,  4,  3,  0|(1ULL<<MCID::Predicable), 0x4000ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #790 = A2_tfr
4295
  { 791,  2,  1,  4,  67, 0, 0x4006ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr },  // Inst #791 = A2_tfrcrr
4296
  { 792,  3,  1,  4,  6,  0, 0x4000ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr },  // Inst #792 = A2_tfrih
4297
  { 793,  3,  1,  4,  6,  0, 0x4000ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr },  // Inst #793 = A2_tfril
4298
  { 794,  2,  1,  4,  68, 0, 0x4006ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #794 = A2_tfrrcr
4299
  { 795,  2,  1,  4,  3,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x109404000ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #795 = A2_tfrsi
4300
  { 796,  2,  1,  4,  60, 0, 0x10000000000002cULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #796 = A2_vabsh
4301
  { 797,  2,  1,  4,  60, 0, 0x10000000000002cULL, nullptr, ImplicitList20, OperandInfo35, -1 ,nullptr },  // Inst #797 = A2_vabshsat
4302
  { 798,  2,  1,  4,  60, 0, 0x10000000000002cULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #798 = A2_vabsw
4303
  { 799,  2,  1,  4,  60, 0, 0x10000000000002cULL, nullptr, ImplicitList20, OperandInfo35, -1 ,nullptr },  // Inst #799 = A2_vabswsat
4304
  { 800,  3,  1,  4,  8,  0, 0x3ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #800 = A2_vaddh
4305
  { 801,  3,  1,  4,  61, 0, 0x100000000000003ULL, nullptr, ImplicitList20, OperandInfo38, -1 ,nullptr },  // Inst #801 = A2_vaddhs
4306
  { 802,  3,  1,  4,  8,  0, 0x3ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #802 = A2_vaddub
4307
  { 803,  3,  1,  4,  61, 0, 0x100000000000003ULL, nullptr, ImplicitList20, OperandInfo38, -1 ,nullptr },  // Inst #803 = A2_vaddubs
4308
  { 804,  3,  1,  4,  61, 0, 0x100000000000003ULL, nullptr, ImplicitList20, OperandInfo38, -1 ,nullptr },  // Inst #804 = A2_vadduhs
4309
  { 805,  3,  1,  4,  8,  0, 0x3ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #805 = A2_vaddw
4310
  { 806,  3,  1,  4,  61, 0, 0x100000000000003ULL, nullptr, ImplicitList20, OperandInfo38, -1 ,nullptr },  // Inst #806 = A2_vaddws
4311
  { 807,  3,  1,  4,  8,  0, 0x3ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #807 = A2_vavgh
4312
  { 808,  3,  1,  4,  45, 0, 0x100000000000003ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #808 = A2_vavghcr
4313
  { 809,  3,  1,  4,  69, 0, 0x3ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #809 = A2_vavghr
4314
  { 810,  3,  1,  4,  8,  0, 0x3ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #810 = A2_vavgub
4315
  { 811,  3,  1,  4,  69, 0, 0x3ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #811 = A2_vavgubr
4316
  { 812,  3,  1,  4,  8,  0, 0x3ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #812 = A2_vavguh
4317
  { 813,  3,  1,  4,  69, 0, 0x3ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #813 = A2_vavguhr
4318
  { 814,  3,  1,  4,  8,  0, 0x3ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #814 = A2_vavguw
4319
  { 815,  3,  1,  4,  69, 0, 0x3ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #815 = A2_vavguwr
4320
  { 816,  3,  1,  4,  8,  0, 0x3ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #816 = A2_vavgw
4321
  { 817,  3,  1,  4,  45, 0, 0x100000000000003ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #817 = A2_vavgwcr
4322
  { 818,  3,  1,  4,  69, 0, 0x3ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #818 = A2_vavgwr
4323
  { 819,  3,  1,  4,  9,  0, 0x3ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #819 = A2_vcmpbeq
4324
  { 820,  3,  1,  4,  9,  0, 0x3ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #820 = A2_vcmpbgtu
4325
  { 821,  3,  1,  4,  9,  0, 0x3ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #821 = A2_vcmpheq
4326
  { 822,  3,  1,  4,  9,  0, 0x3ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #822 = A2_vcmphgt
4327
  { 823,  3,  1,  4,  9,  0, 0x3ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #823 = A2_vcmphgtu
4328
  { 824,  3,  1,  4,  9,  0, 0x3ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #824 = A2_vcmpweq
4329
  { 825,  3,  1,  4,  9,  0, 0x3ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #825 = A2_vcmpwgt
4330
  { 826,  3,  1,  4,  9,  0, 0x3ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #826 = A2_vcmpwgtu
4331
  { 827,  2,  1,  4,  60, 0, 0x10000000000002cULL, nullptr, ImplicitList20, OperandInfo35, -1 ,nullptr },  // Inst #827 = A2_vconj
4332
  { 828,  3,  1,  4,  61, 0, 0x100000000000003ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #828 = A2_vmaxb
4333
  { 829,  3,  1,  4,  61, 0, 0x100000000000003ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #829 = A2_vmaxh
4334
  { 830,  3,  1,  4,  61, 0, 0x100000000000003ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #830 = A2_vmaxub
4335
  { 831,  3,  1,  4,  61, 0, 0x100000000000003ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #831 = A2_vmaxuh
4336
  { 832,  3,  1,  4,  61, 0, 0x100000000000003ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #832 = A2_vmaxuw
4337
  { 833,  3,  1,  4,  61, 0, 0x100000000000003ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #833 = A2_vmaxw
4338
  { 834,  3,  1,  4,  61, 0, 0x100000000000003ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #834 = A2_vminb
4339
  { 835,  3,  1,  4,  61, 0, 0x100000000000003ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #835 = A2_vminh
4340
  { 836,  3,  1,  4,  61, 0, 0x100000000000003ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #836 = A2_vminub
4341
  { 837,  3,  1,  4,  61, 0, 0x100000000000003ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #837 = A2_vminuh
4342
  { 838,  3,  1,  4,  61, 0, 0x100000000000003ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #838 = A2_vminuw
4343
  { 839,  3,  1,  4,  61, 0, 0x100000000000003ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #839 = A2_vminw
4344
  { 840,  3,  1,  4,  8,  0, 0x3ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #840 = A2_vnavgh
4345
  { 841,  3,  1,  4,  45, 0, 0x100000000000003ULL, nullptr, ImplicitList20, OperandInfo38, -1 ,nullptr },  // Inst #841 = A2_vnavghcr
4346
  { 842,  3,  1,  4,  45, 0, 0x100000000000003ULL, nullptr, ImplicitList20, OperandInfo38, -1 ,nullptr },  // Inst #842 = A2_vnavghr
4347
  { 843,  3,  1,  4,  8,  0, 0x3ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #843 = A2_vnavgw
4348
  { 844,  3,  1,  4,  45, 0, 0x100000000000003ULL, nullptr, ImplicitList20, OperandInfo38, -1 ,nullptr },  // Inst #844 = A2_vnavgwcr
4349
  { 845,  3,  1,  4,  45, 0, 0x100000000000003ULL, nullptr, ImplicitList20, OperandInfo38, -1 ,nullptr },  // Inst #845 = A2_vnavgwr
4350
  { 846,  3,  1,  4,  30, 0, 0x100000000000026ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #846 = A2_vraddub
4351
  { 847,  4,  1,  4,  31, 0, 0x100000000000026ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #847 = A2_vraddub_acc
4352
  { 848,  3,  1,  4,  30, 0, 0x100000000000026ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #848 = A2_vrsadub
4353
  { 849,  4,  1,  4,  31, 0, 0x100000000000026ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #849 = A2_vrsadub_acc
4354
  { 850,  3,  1,  4,  8,  0, 0x3ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #850 = A2_vsubh
4355
  { 851,  3,  1,  4,  61, 0, 0x100000000000003ULL, nullptr, ImplicitList20, OperandInfo38, -1 ,nullptr },  // Inst #851 = A2_vsubhs
4356
  { 852,  3,  1,  4,  8,  0, 0x3ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #852 = A2_vsubub
4357
  { 853,  3,  1,  4,  61, 0, 0x100000000000003ULL, nullptr, ImplicitList20, OperandInfo38, -1 ,nullptr },  // Inst #853 = A2_vsububs
4358
  { 854,  3,  1,  4,  61, 0, 0x100000000000003ULL, nullptr, ImplicitList20, OperandInfo38, -1 ,nullptr },  // Inst #854 = A2_vsubuhs
4359
  { 855,  3,  1,  4,  8,  0, 0x3ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #855 = A2_vsubw
4360
  { 856,  3,  1,  4,  61, 0, 0x100000000000003ULL, nullptr, ImplicitList20, OperandInfo38, -1 ,nullptr },  // Inst #856 = A2_vsubws
4361
  { 857,  3,  1,  4,  6,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x4001ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #857 = A2_xor
4362
  { 858,  3,  1,  4,  8,  0|(1ULL<<MCID::Commutable), 0x3ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #858 = A2_xorp
4363
  { 859,  2,  1,  4,  3,  0|(1ULL<<MCID::Predicable), 0x4000ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #859 = A2_zxth
4364
  { 860,  5,  2,  4,  70, 0, 0x102dULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #860 = A4_addp_c
4365
  { 861,  3,  1,  4,  6,  0, 0x4001ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #861 = A4_andn
4366
  { 862,  3,  1,  4,  8,  0, 0x3ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #862 = A4_andnp
4367
  { 863,  3,  1,  4,  62, 0, 0x100000000000003ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr },  // Inst #863 = A4_bitsplit
4368
  { 864,  3,  1,  4,  62, 0, 0x10000000000002cULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #864 = A4_bitspliti
4369
  { 865,  3,  1,  4,  9,  0, 0x3ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #865 = A4_boundscheck_hi
4370
  { 866,  3,  1,  4,  9,  0, 0x3ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #866 = A4_boundscheck_lo
4371
  { 867,  3,  1,  4,  9,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x2dULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #867 = A4_cmpbeq
4372
  { 868,  3,  1,  4,  71, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x3ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #868 = A4_cmpbeqi
4373
  { 869,  3,  1,  4,  9,  0|(1ULL<<MCID::Compare), 0x2dULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #869 = A4_cmpbgt
4374
  { 870,  3,  1,  4,  71, 0|(1ULL<<MCID::Compare), 0x3ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #870 = A4_cmpbgti
4375
  { 871,  3,  1,  4,  9,  0|(1ULL<<MCID::Compare), 0x2dULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #871 = A4_cmpbgtu
4376
  { 872,  3,  1,  4,  71, 0|(1ULL<<MCID::Compare), 0x72400003ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #872 = A4_cmpbgtui
4377
  { 873,  3,  1,  4,  9,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x2dULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #873 = A4_cmpheq
4378
  { 874,  3,  1,  4,  71, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x8a400003ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #874 = A4_cmpheqi
4379
  { 875,  3,  1,  4,  9,  0|(1ULL<<MCID::Compare), 0x2dULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #875 = A4_cmphgt
4380
  { 876,  3,  1,  4,  71, 0|(1ULL<<MCID::Compare), 0x8a400003ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #876 = A4_cmphgti
4381
  { 877,  3,  1,  4,  9,  0|(1ULL<<MCID::Compare), 0x2dULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #877 = A4_cmphgtu
4382
  { 878,  3,  1,  4,  71, 0|(1ULL<<MCID::Compare), 0x72400003ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #878 = A4_cmphgtui
4383
  { 879,  3,  1,  4,  6,  0, 0x62400000ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr },  // Inst #879 = A4_combineii
4384
  { 880,  3,  1,  4,  6,  0, 0x89400000ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr },  // Inst #880 = A4_combineir
4385
  { 881,  3,  1,  4,  6,  0, 0x8a400000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #881 = A4_combineri
4386
  { 882,  3,  1,  4,  45, 0, 0x10000000000402cULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #882 = A4_cround_ri
4387
  { 883,  3,  1,  4,  45, 0, 0x10000000000402dULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #883 = A4_cround_rr
4388
  { 884,  1,  0,  4,  72, 0, 0x23ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #884 = A4_ext
4389
  { 885,  3,  1,  4,  61, 0, 0x100000000004003ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #885 = A4_modwrapu
4390
  { 886,  3,  1,  4,  6,  0, 0x4001ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #886 = A4_orn
4391
  { 887,  3,  1,  4,  8,  0, 0x3ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #887 = A4_ornp
4392
  { 888,  3,  1,  4,  6,  0, 0x4600ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #888 = A4_paslhf
4393
  { 889,  3,  1,  4,  7,  0, 0x4e00ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #889 = A4_paslhfnew
4394
  { 890,  3,  1,  4,  6,  0, 0x4200ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #890 = A4_paslht
4395
  { 891,  3,  1,  4,  7,  0, 0x4a00ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #891 = A4_paslhtnew
4396
  { 892,  3,  1,  4,  6,  0, 0x4600ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #892 = A4_pasrhf
4397
  { 893,  3,  1,  4,  7,  0, 0x4e00ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #893 = A4_pasrhfnew
4398
  { 894,  3,  1,  4,  6,  0, 0x4200ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #894 = A4_pasrht
4399
  { 895,  3,  1,  4,  7,  0, 0x4a00ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #895 = A4_pasrhtnew
4400
  { 896,  3,  1,  4,  6,  0, 0x4600ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #896 = A4_psxtbf
4401
  { 897,  3,  1,  4,  7,  0, 0x4e00ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #897 = A4_psxtbfnew
4402
  { 898,  3,  1,  4,  6,  0, 0x4200ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #898 = A4_psxtbt
4403
  { 899,  3,  1,  4,  7,  0, 0x4a00ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #899 = A4_psxtbtnew
4404
  { 900,  3,  1,  4,  6,  0, 0x4600ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #900 = A4_psxthf
4405
  { 901,  3,  1,  4,  7,  0, 0x4e00ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #901 = A4_psxthfnew
4406
  { 902,  3,  1,  4,  6,  0, 0x4200ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #902 = A4_psxtht
4407
  { 903,  3,  1,  4,  7,  0, 0x4a00ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #903 = A4_psxthtnew
4408
  { 904,  3,  1,  4,  6,  0, 0x4600ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #904 = A4_pzxtbf
4409
  { 905,  3,  1,  4,  7,  0, 0x4e00ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #905 = A4_pzxtbfnew
4410
  { 906,  3,  1,  4,  6,  0, 0x4200ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #906 = A4_pzxtbt
4411
  { 907,  3,  1,  4,  7,  0, 0x4a00ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #907 = A4_pzxtbtnew
4412
  { 908,  3,  1,  4,  6,  0, 0x4600ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #908 = A4_pzxthf
4413
  { 909,  3,  1,  4,  7,  0, 0x4e00ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #909 = A4_pzxthfnew
4414
  { 910,  3,  1,  4,  6,  0, 0x4200ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #910 = A4_pzxtht
4415
  { 911,  3,  1,  4,  7,  0, 0x4a00ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #911 = A4_pzxthtnew
4416
  { 912,  3,  1,  4,  6,  0|(1ULL<<MCID::Commutable), 0x4001ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #912 = A4_rcmpeq
4417
  { 913,  3,  1,  4,  6,  0, 0x8a404000ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #913 = A4_rcmpeqi
4418
  { 914,  3,  1,  4,  6,  0|(1ULL<<MCID::Commutable), 0x4001ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #914 = A4_rcmpneq
4419
  { 915,  3,  1,  4,  6,  0, 0x8a404000ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #915 = A4_rcmpneqi
4420
  { 916,  3,  1,  4,  45, 0, 0x10000000000402cULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #916 = A4_round_ri
4421
  { 917,  3,  1,  4,  45, 0, 0x10000000000402cULL, nullptr, ImplicitList20, OperandInfo50, -1 ,nullptr },  // Inst #917 = A4_round_ri_sat
4422
  { 918,  3,  1,  4,  45, 0, 0x10000000000402dULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #918 = A4_round_rr
4423
  { 919,  3,  1,  4,  45, 0, 0x10000000000402dULL, nullptr, ImplicitList20, OperandInfo51, -1 ,nullptr },  // Inst #919 = A4_round_rr_sat
4424
  { 920,  5,  2,  4,  70, 0, 0x102dULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #920 = A4_subp_c
4425
  { 921,  2,  1,  4,  67, 0, 0x6ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr },  // Inst #921 = A4_tfrcpp
4426
  { 922,  2,  1,  4,  68, 0, 0x6ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #922 = A4_tfrpcp
4427
  { 923,  3,  1,  4,  73, 0, 0x1003ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr },  // Inst #923 = A4_tlbmatch
4428
  { 924,  3,  1,  4,  9,  0, 0x3ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #924 = A4_vcmpbeq_any
4429
  { 925,  3,  1,  4,  71, 0, 0x3ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #925 = A4_vcmpbeqi
4430
  { 926,  3,  1,  4,  9,  0, 0x3ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #926 = A4_vcmpbgt
4431
  { 927,  3,  1,  4,  71, 0, 0x3ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #927 = A4_vcmpbgti
4432
  { 928,  3,  1,  4,  71, 0, 0x3ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #928 = A4_vcmpbgtui
4433
  { 929,  3,  1,  4,  71, 0, 0x3ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #929 = A4_vcmpheqi
4434
  { 930,  3,  1,  4,  71, 0, 0x3ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #930 = A4_vcmphgti
4435
  { 931,  3,  1,  4,  71, 0, 0x3ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #931 = A4_vcmphgtui
4436
  { 932,  3,  1,  4,  71, 0, 0x3ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #932 = A4_vcmpweqi
4437
  { 933,  3,  1,  4,  71, 0, 0x3ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #933 = A4_vcmpwgti
4438
  { 934,  3,  1,  4,  71, 0, 0x3ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #934 = A4_vcmpwgtui
4439
  { 935,  4,  1,  4,  74, 0, 0x10000000000002dULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #935 = A4_vrmaxh
4440
  { 936,  4,  1,  4,  74, 0, 0x10000000000002dULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #936 = A4_vrmaxuh
4441
  { 937,  4,  1,  4,  74, 0, 0x10000000000002dULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #937 = A4_vrmaxuw
4442
  { 938,  4,  1,  4,  74, 0, 0x10000000000002dULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #938 = A4_vrmaxw
4443
  { 939,  4,  1,  4,  74, 0, 0x10000000000002dULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #939 = A4_vrminh
4444
  { 940,  4,  1,  4,  74, 0, 0x10000000000002dULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #940 = A4_vrminuh
4445
  { 941,  4,  1,  4,  74, 0, 0x10000000000002dULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #941 = A4_vrminuw
4446
  { 942,  4,  1,  4,  74, 0, 0x10000000000002dULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #942 = A4_vrminw
4447
  { 943,  5,  2,  4,  75, 0, 0x100000000001026ULL, nullptr, ImplicitList20, OperandInfo143, -1 ,nullptr },  // Inst #943 = A5_ACS
4448
  { 944,  3,  1,  4,  45, 0, 0x10000000000402dULL, nullptr, ImplicitList20, OperandInfo144, -1 ,nullptr },  // Inst #944 = A5_vaddhubs
4449
  { 945,  3,  1,  4,  76, 0, 0x3ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #945 = A6_vcmpbeq_notany
4450
  { 946,  4,  2,  4,  77, 0, 0x100000000001026ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #946 = A6_vminub_RdP
4451
  { 947,  2,  1,  4,  78, 0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #947 = C2_all8
4452
  { 948,  3,  1,  4,  11, 0, 0x6ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #948 = C2_and
4453
  { 949,  3,  1,  4,  11, 0, 0x6ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #949 = C2_andn
4454
  { 950,  2,  1,  4,  78, 0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #950 = C2_any8
4455
  { 951,  3,  1,  4,  9,  0, 0x2dULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #951 = C2_bitsclr
4456
  { 952,  3,  1,  4,  71, 0, 0x2cULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #952 = C2_bitsclri
4457
  { 953,  3,  1,  4,  9,  0, 0x2dULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #953 = C2_bitsset
4458
  { 954,  4,  1,  4,  4,  0, 0x601ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #954 = C2_ccombinewf
4459
  { 955,  4,  1,  4,  5,  0, 0xe01ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #955 = C2_ccombinewnewf
4460
  { 956,  4,  1,  4,  5,  0, 0xa01ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #956 = C2_ccombinewnewt
4461
  { 957,  4,  1,  4,  4,  0, 0x201ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #957 = C2_ccombinewt
4462
  { 958,  3,  1,  4,  6,  0|(1ULL<<MCID::MoveImm), 0xca404600ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #958 = C2_cmoveif
4463
  { 959,  3,  1,  4,  6,  0|(1ULL<<MCID::MoveImm), 0xca404200ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #959 = C2_cmoveit
4464
  { 960,  3,  1,  4,  7,  0|(1ULL<<MCID::MoveImm), 0xca404e00ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #960 = C2_cmovenewif
4465
  { 961,  3,  1,  4,  7,  0|(1ULL<<MCID::MoveImm), 0xca404a00ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #961 = C2_cmovenewit
4466
  { 962,  3,  1,  4,  79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #962 = C2_cmpeq
4467
  { 963,  3,  1,  4,  10, 0|(1ULL<<MCID::Compare), 0xaa400000ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #963 = C2_cmpeqi
4468
  { 964,  3,  1,  4,  9,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x3ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #964 = C2_cmpeqp
4469
  { 965,  3,  1,  4,  79, 0|(1ULL<<MCID::Compare), 0x1ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #965 = C2_cmpgt
4470
  { 966,  3,  1,  4,  10, 0|(1ULL<<MCID::Compare), 0xaa400000ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #966 = C2_cmpgti
4471
  { 967,  3,  1,  4,  9,  0|(1ULL<<MCID::Compare), 0x3ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #967 = C2_cmpgtp
4472
  { 968,  3,  1,  4,  79, 0|(1ULL<<MCID::Compare), 0x1ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #968 = C2_cmpgtu
4473
  { 969,  3,  1,  4,  10, 0|(1ULL<<MCID::Compare), 0x92400000ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #969 = C2_cmpgtui
4474
  { 970,  3,  1,  4,  9,  0|(1ULL<<MCID::Compare), 0x3ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #970 = C2_cmpgtup
4475
  { 971,  2,  1,  4,  64, 0, 0x2cULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #971 = C2_mask
4476
  { 972,  4,  1,  4,  4,  0, 0x4001ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #972 = C2_mux
4477
  { 973,  4,  1,  4,  4,  0, 0x8a404000ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #973 = C2_muxii
4478
  { 974,  4,  1,  4,  4,  0, 0x8b404000ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr },  // Inst #974 = C2_muxir
4479
  { 975,  4,  1,  4,  4,  0, 0x8a404000ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #975 = C2_muxri
4480
  { 976,  2,  1,  4,  78, 0, 0x6ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #976 = C2_not
4481
  { 977,  3,  1,  4,  11, 0, 0x6ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #977 = C2_or
4482
  { 978,  3,  1,  4,  11, 0, 0x6ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #978 = C2_orn
4483
  { 979,  2,  1,  4,  64, 0, 0x402cULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #979 = C2_tfrpr
4484
  { 980,  2,  1,  4,  80, 0, 0x2cULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #980 = C2_tfrrp
4485
  { 981,  3,  1,  4,  62, 0, 0x10000000000402cULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #981 = C2_vitpack
4486
  { 982,  4,  1,  4,  81, 0, 0x3ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #982 = C2_vmux
4487
  { 983,  3,  1,  4,  11, 0, 0x6ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #983 = C2_xor
4488
  { 984,  2,  1,  4,  82, 0, 0x61404006ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #984 = C4_addipc
4489
  { 985,  4,  1,  4,  83, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #985 = C4_and_and
4490
  { 986,  4,  1,  4,  83, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #986 = C4_and_andn
4491
  { 987,  4,  1,  4,  83, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #987 = C4_and_or
4492
  { 988,  4,  1,  4,  83, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #988 = C4_and_orn
4493
  { 989,  3,  1,  4,  79, 0|(1ULL<<MCID::Compare), 0x1ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #989 = C4_cmplte
4494
  { 990,  3,  1,  4,  10, 0|(1ULL<<MCID::Compare), 0xaa400000ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #990 = C4_cmpltei
4495
  { 991,  3,  1,  4,  79, 0|(1ULL<<MCID::Compare), 0x1ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #991 = C4_cmplteu
4496
  { 992,  3,  1,  4,  10, 0|(1ULL<<MCID::Compare), 0x92400000ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #992 = C4_cmplteui
4497
  { 993,  3,  1,  4,  79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #993 = C4_cmpneq
4498
  { 994,  3,  1,  4,  10, 0|(1ULL<<MCID::Compare), 0xaa400000ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #994 = C4_cmpneqi
4499
  { 995,  3,  1,  4,  11, 0, 0x6ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #995 = C4_fastcorner9
4500
  { 996,  3,  1,  4,  11, 0, 0x6ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #996 = C4_fastcorner9_not
4501
  { 997,  3,  1,  4,  9,  0, 0x2dULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #997 = C4_nbitsclr
4502
  { 998,  3,  1,  4,  71, 0, 0x2cULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #998 = C4_nbitsclri
4503
  { 999,  3,  1,  4,  9,  0, 0x2dULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #999 = C4_nbitsset
4504
  { 1000, 4,  1,  4,  83, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #1000 = C4_or_and
4505
  { 1001, 4,  1,  4,  83, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #1001 = C4_or_andn
4506
  { 1002, 4,  1,  4,  83, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #1002 = C4_or_or
4507
  { 1003, 4,  1,  4,  83, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #1003 = C4_or_orn
4508
  { 1004, 1,  0,  4,  84, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x588400024ULL, nullptr, ImplicitList21, OperandInfo2, -1 ,nullptr },  // Inst #1004 = CALLProfile
4509
  { 1005, 2,  1,  4,  28, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x25ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr },  // Inst #1005 = CONST32
4510
  { 1006, 2,  1,  4,  28, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x25ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr },  // Inst #1006 = CONST64
4511
  { 1007, 0,  0,  4,  12, 0, 0x21ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1007 = DuplexIClass0
4512
  { 1008, 0,  0,  4,  12, 0, 0x21ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1008 = DuplexIClass1
4513
  { 1009, 0,  0,  4,  12, 0, 0x21ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1009 = DuplexIClass2
4514
  { 1010, 0,  0,  4,  12, 0, 0x10021ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1010 = DuplexIClass3
4515
  { 1011, 0,  0,  4,  12, 0, 0x10021ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1011 = DuplexIClass4
4516
  { 1012, 0,  0,  4,  12, 0, 0x10021ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1012 = DuplexIClass5
4517
  { 1013, 0,  0,  4,  12, 0, 0x10021ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1013 = DuplexIClass6
4518
  { 1014, 0,  0,  4,  12, 0, 0x10021ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1014 = DuplexIClass7
4519
  { 1015, 0,  0,  4,  12, 0, 0x21ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1015 = DuplexIClass8
4520
  { 1016, 0,  0,  4,  12, 0, 0x21ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1016 = DuplexIClass9
4521
  { 1017, 0,  0,  4,  12, 0, 0x21ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1017 = DuplexIClassA
4522
  { 1018, 0,  0,  4,  12, 0, 0x21ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1018 = DuplexIClassB
4523
  { 1019, 0,  0,  4,  12, 0, 0x21ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1019 = DuplexIClassC
4524
  { 1020, 0,  0,  4,  12, 0, 0x21ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1020 = DuplexIClassD
4525
  { 1021, 0,  0,  4,  12, 0, 0x21ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1021 = DuplexIClassE
4526
  { 1022, 0,  0,  4,  12, 0, 0x21ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1022 = DuplexIClassF
4527
  { 1023, 1,  0,  4,  36, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x800000024ULL, ImplicitList22, ImplicitList19, OperandInfo66, -1 ,nullptr },  // Inst #1023 = EH_RETURN_JMPR
4528
  { 1024, 2,  1,  4,  85, 0, 0x200000000002cULL, ImplicitList23, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #1024 = F2_conv_d2df
4529
  { 1025, 2,  1,  4,  85, 0, 0x200000000402cULL, ImplicitList23, nullptr, OperandInfo76, -1 ,nullptr },  // Inst #1025 = F2_conv_d2sf
4530
  { 1026, 2,  1,  4,  85, 0, 0x200000000002cULL, ImplicitList23, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #1026 = F2_conv_df2d
4531
  { 1027, 2,  1,  4,  85, 0, 0x200000000002cULL, ImplicitList23, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #1027 = F2_conv_df2d_chop
4532
  { 1028, 2,  1,  4,  85, 0, 0x200000000402cULL, ImplicitList23, nullptr, OperandInfo76, -1 ,nullptr },  // Inst #1028 = F2_conv_df2sf
4533
  { 1029, 2,  1,  4,  85, 0, 0x200000000002cULL, ImplicitList23, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #1029 = F2_conv_df2ud
4534
  { 1030, 2,  1,  4,  85, 0, 0x200000000002cULL, ImplicitList23, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #1030 = F2_conv_df2ud_chop
4535
  { 1031, 2,  1,  4,  85, 0, 0x200000000402cULL, ImplicitList23, nullptr, OperandInfo76, -1 ,nullptr },  // Inst #1031 = F2_conv_df2uw
4536
  { 1032, 2,  1,  4,  85, 0, 0x200000000402cULL, ImplicitList23, nullptr, OperandInfo76, -1 ,nullptr },  // Inst #1032 = F2_conv_df2uw_chop
4537
  { 1033, 2,  1,  4,  85, 0, 0x200000000402cULL, ImplicitList23, nullptr, OperandInfo76, -1 ,nullptr },  // Inst #1033 = F2_conv_df2w
4538
  { 1034, 2,  1,  4,  85, 0, 0x200000000402cULL, ImplicitList23, nullptr, OperandInfo76, -1 ,nullptr },  // Inst #1034 = F2_conv_df2w_chop
4539
  { 1035, 2,  1,  4,  85, 0, 0x200000000002cULL, ImplicitList23, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #1035 = F2_conv_sf2d
4540
  { 1036, 2,  1,  4,  85, 0, 0x200000000002cULL, ImplicitList23, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #1036 = F2_conv_sf2d_chop
4541
  { 1037, 2,  1,  4,  85, 0, 0x200000000002cULL, ImplicitList23, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #1037 = F2_conv_sf2df
4542
  { 1038, 2,  1,  4,  85, 0, 0x200000000002cULL, ImplicitList23, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #1038 = F2_conv_sf2ud
4543
  { 1039, 2,  1,  4,  85, 0, 0x200000000002cULL, ImplicitList23, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #1039 = F2_conv_sf2ud_chop
4544
  { 1040, 2,  1,  4,  85, 0, 0x200000000402cULL, ImplicitList23, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1040 = F2_conv_sf2uw
4545
  { 1041, 2,  1,  4,  85, 0, 0x200000000402cULL, ImplicitList23, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1041 = F2_conv_sf2uw_chop
4546
  { 1042, 2,  1,  4,  85, 0, 0x200000000402cULL, ImplicitList23, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1042 = F2_conv_sf2w
4547
  { 1043, 2,  1,  4,  85, 0, 0x200000000402cULL, ImplicitList23, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1043 = F2_conv_sf2w_chop
4548
  { 1044, 2,  1,  4,  85, 0, 0x200000000002cULL, ImplicitList23, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #1044 = F2_conv_ud2df
4549
  { 1045, 2,  1,  4,  85, 0, 0x200000000402cULL, ImplicitList23, nullptr, OperandInfo76, -1 ,nullptr },  // Inst #1045 = F2_conv_ud2sf
4550
  { 1046, 2,  1,  4,  85, 0, 0x200000000002cULL, ImplicitList23, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #1046 = F2_conv_uw2df
4551
  { 1047, 2,  1,  4,  85, 0, 0x200000000402cULL, ImplicitList23, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1047 = F2_conv_uw2sf
4552
  { 1048, 2,  1,  4,  85, 0, 0x200000000002cULL, ImplicitList23, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #1048 = F2_conv_w2df
4553
  { 1049, 2,  1,  4,  85, 0, 0x200000000402cULL, ImplicitList23, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1049 = F2_conv_w2sf
4554
  { 1050, 3,  1,  4,  71, 0, 0x2000000000003ULL, ImplicitList23, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #1050 = F2_dfclass
4555
  { 1051, 3,  1,  4,  9,  0|(1ULL<<MCID::Compare), 0x2000000000003ULL, ImplicitList23, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1051 = F2_dfcmpeq
4556
  { 1052, 3,  1,  4,  9,  0|(1ULL<<MCID::Compare), 0x2000000000003ULL, ImplicitList23, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1052 = F2_dfcmpge
4557
  { 1053, 3,  1,  4,  9,  0|(1ULL<<MCID::Compare), 0x2000000000003ULL, ImplicitList23, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1053 = F2_dfcmpgt
4558
  { 1054, 3,  1,  4,  9,  0|(1ULL<<MCID::Compare), 0x2000000000003ULL, ImplicitList23, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #1054 = F2_dfcmpuo
4559
  { 1055, 2,  1,  4,  86, 0, 0x100000000000003ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1055 = F2_dfimm_n
4560
  { 1056, 2,  1,  4,  86, 0, 0x100000000000003ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #1056 = F2_dfimm_p
4561
  { 1057, 3,  1,  4,  87, 0|(1ULL<<MCID::Commutable), 0x2000000004026ULL, ImplicitList23, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #1057 = F2_sfadd
4562
  { 1058, 3,  1,  4,  71, 0, 0x200000000002cULL, ImplicitList23, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #1058 = F2_sfclass
4563
  { 1059, 3,  1,  4,  9,  0|(1ULL<<MCID::Compare), 0x200000000002dULL, ImplicitList23, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1059 = F2_sfcmpeq
4564
  { 1060, 3,  1,  4,  9,  0|(1ULL<<MCID::Compare), 0x200000000002dULL, ImplicitList23, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1060 = F2_sfcmpge
4565
  { 1061, 3,  1,  4,  9,  0|(1ULL<<MCID::Compare), 0x200000000002dULL, ImplicitList23, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1061 = F2_sfcmpgt
4566
  { 1062, 3,  1,  4,  9,  0|(1ULL<<MCID::Compare), 0x200000000002dULL, ImplicitList23, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #1062 = F2_sfcmpuo
4567
  { 1063, 3,  1,  4,  87, 0, 0x2000000004026ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #1063 = F2_sffixupd
4568
  { 1064, 3,  1,  4,  87, 0, 0x2000000004026ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #1064 = F2_sffixupn
4569
  { 1065, 2,  1,  4,  85, 0, 0x200000000402cULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #1065 = F2_sffixupr
4570
  { 1066, 4,  1,  4,  88, 0, 0x2000000004026ULL, ImplicitList23, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #1066 = F2_sffma
4571
  { 1067, 4,  1,  4,  88, 0, 0x2000000004026ULL, ImplicitList23, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #1067 = F2_sffma_lib
4572
  { 1068, 5,  1,  4,  89, 0, 0x2000000004026ULL, ImplicitList23, nullptr, OperandInfo157, -1 ,nullptr },  // Inst #1068 = F2_sffma_sc
4573
  { 1069, 4,  1,  4,  88, 0, 0x2000000004026ULL, ImplicitList23, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #1069 = F2_sffms
4574
  { 1070, 4,  1,  4,  88, 0, 0x2000000004026ULL, ImplicitList23, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #1070 = F2_sffms_lib
4575
  { 1071, 2,  1,  4,  86, 0, 0x100000000004003ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1071 = F2_sfimm_n
4576
  { 1072, 2,  1,  4,  86, 0, 0x100000000004003ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1072 = F2_sfimm_p
4577
  { 1073, 3,  2,  4,  90, 0, 0x200000000502cULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #1073 = F2_sfinvsqrta
4578
  { 1074, 3,  1,  4,  91, 0, 0x102000000004026ULL, ImplicitList23, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #1074 = F2_sfmax
4579
  { 1075, 3,  1,  4,  91, 0, 0x102000000004026ULL, ImplicitList23, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #1075 = F2_sfmin
4580
  { 1076, 3,  1,  4,  87, 0|(1ULL<<MCID::Commutable), 0x2000000004026ULL, ImplicitList23, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #1076 = F2_sfmpy
4581
  { 1077, 4,  2,  4,  92, 0, 0x2000000005026ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #1077 = F2_sfrecipa
4582
  { 1078, 3,  1,  4,  87, 0, 0x2000000004026ULL, ImplicitList23, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #1078 = F2_sfsub
4583
  { 1079, 2,  1,  4,  93, 0, 0x6ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr },  // Inst #1079 = G4_tfrgcpp
4584
  { 1080, 2,  1,  4,  93, 0, 0x4006ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr },  // Inst #1080 = G4_tfrgcrr
4585
  { 1081, 2,  1,  4,  94, 0, 0x4006ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr },  // Inst #1081 = G4_tfrgpcp
4586
  { 1082, 2,  1,  4,  94, 0, 0x4006ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #1082 = G4_tfrgrcr
4587
  { 1083, 2,  1,  4,  6,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x4000ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #1083 = HI
4588
  { 1084, 1,  0,  4,  84, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100002d88400024ULL, ImplicitList3, ImplicitList24, OperandInfo2, -1 ,nullptr },  // Inst #1084 = J2_call
4589
  { 1085, 2,  0,  4,  95, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x100003d19400624ULL, ImplicitList3, ImplicitList24, OperandInfo43, -1 ,nullptr },  // Inst #1085 = J2_callf
4590
  { 1086, 1,  0,  4,  96, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x100000800000024ULL, ImplicitList3, ImplicitList24, OperandInfo66, -1 ,nullptr },  // Inst #1086 = J2_callr
4591
  { 1087, 2,  0,  4,  97, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x100000800000624ULL, ImplicitList3, ImplicitList24, OperandInfo44, -1 ,nullptr },  // Inst #1087 = J2_callrf
4592
  { 1088, 2,  0,  4,  97, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x100000800000224ULL, ImplicitList3, ImplicitList24, OperandInfo44, -1 ,nullptr },  // Inst #1088 = J2_callrt
4593
  { 1089, 2,  0,  4,  95, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x100003d19400224ULL, ImplicitList3, ImplicitList24, OperandInfo43, -1 ,nullptr },  // Inst #1089 = J2_callt
4594
  { 1090, 1,  0,  4,  98, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x2d88400024ULL, nullptr, ImplicitList19, OperandInfo2, -1 ,nullptr },  // Inst #1090 = J2_jump
4595
  { 1091, 2,  0,  4,  15, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3d19400624ULL, nullptr, ImplicitList19, OperandInfo43, -1 ,nullptr },  // Inst #1091 = J2_jumpf
4596
  { 1092, 2,  0,  4,  99, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3d19400e24ULL, nullptr, ImplicitList19, OperandInfo43, -1 ,nullptr },  // Inst #1092 = J2_jumpfnew
4597
  { 1093, 2,  0,  4,  99, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003d19400e24ULL, nullptr, ImplicitList19, OperandInfo43, -1 ,nullptr },  // Inst #1093 = J2_jumpfnewpt
4598
  { 1094, 2,  0,  4,  100,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003d19400624ULL, nullptr, ImplicitList19, OperandInfo43, -1 ,nullptr },  // Inst #1094 = J2_jumpfpt
4599
  { 1095, 1,  0,  4,  36, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x800000024ULL, nullptr, ImplicitList19, OperandInfo66, -1 ,nullptr },  // Inst #1095 = J2_jumpr
4600
  { 1096, 2,  0,  4,  16, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x800000624ULL, nullptr, ImplicitList19, OperandInfo44, -1 ,nullptr },  // Inst #1096 = J2_jumprf
4601
  { 1097, 2,  0,  4,  101,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x800000e24ULL, nullptr, ImplicitList19, OperandInfo44, -1 ,nullptr },  // Inst #1097 = J2_jumprfnew
4602
  { 1098, 2,  0,  4,  101,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000800000e24ULL, nullptr, ImplicitList19, OperandInfo44, -1 ,nullptr },  // Inst #1098 = J2_jumprfnewpt
4603
  { 1099, 2,  0,  4,  102,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000800000624ULL, nullptr, ImplicitList19, OperandInfo44, -1 ,nullptr },  // Inst #1099 = J2_jumprfpt
4604
  { 1100, 2,  0,  4,  103,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3800000a06ULL, nullptr, ImplicitList19, OperandInfo32, -1 ,nullptr },  // Inst #1100 = J2_jumprgtez
4605
  { 1101, 2,  0,  4,  103,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003800000a06ULL, nullptr, ImplicitList19, OperandInfo32, -1 ,nullptr },  // Inst #1101 = J2_jumprgtezpt
4606
  { 1102, 2,  0,  4,  103,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3800000a06ULL, nullptr, ImplicitList19, OperandInfo32, -1 ,nullptr },  // Inst #1102 = J2_jumprltez
4607
  { 1103, 2,  0,  4,  103,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003800000a06ULL, nullptr, ImplicitList19, OperandInfo32, -1 ,nullptr },  // Inst #1103 = J2_jumprltezpt
4608
  { 1104, 2,  0,  4,  103,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3800000a06ULL, nullptr, ImplicitList19, OperandInfo32, -1 ,nullptr },  // Inst #1104 = J2_jumprnz
4609
  { 1105, 2,  0,  4,  103,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003800000a06ULL, nullptr, ImplicitList19, OperandInfo32, -1 ,nullptr },  // Inst #1105 = J2_jumprnzpt
4610
  { 1106, 2,  0,  4,  16, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x800000224ULL, nullptr, ImplicitList19, OperandInfo44, -1 ,nullptr },  // Inst #1106 = J2_jumprt
4611
  { 1107, 2,  0,  4,  101,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x800000a24ULL, nullptr, ImplicitList19, OperandInfo44, -1 ,nullptr },  // Inst #1107 = J2_jumprtnew
4612
  { 1108, 2,  0,  4,  101,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000800000a24ULL, nullptr, ImplicitList19, OperandInfo44, -1 ,nullptr },  // Inst #1108 = J2_jumprtnewpt
4613
  { 1109, 2,  0,  4,  102,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000800000224ULL, nullptr, ImplicitList19, OperandInfo44, -1 ,nullptr },  // Inst #1109 = J2_jumprtpt
4614
  { 1110, 2,  0,  4,  103,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3800000a06ULL, nullptr, ImplicitList19, OperandInfo32, -1 ,nullptr },  // Inst #1110 = J2_jumprz
4615
  { 1111, 2,  0,  4,  103,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003800000a06ULL, nullptr, ImplicitList19, OperandInfo32, -1 ,nullptr },  // Inst #1111 = J2_jumprzpt
4616
  { 1112, 2,  0,  4,  15, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3d19400224ULL, nullptr, ImplicitList19, OperandInfo43, -1 ,nullptr },  // Inst #1112 = J2_jumpt
4617
  { 1113, 2,  0,  4,  99, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3d19400a24ULL, nullptr, ImplicitList19, OperandInfo43, -1 ,nullptr },  // Inst #1113 = J2_jumptnew
4618
  { 1114, 2,  0,  4,  99, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003d19400a24ULL, nullptr, ImplicitList19, OperandInfo43, -1 ,nullptr },  // Inst #1114 = J2_jumptnewpt
4619
  { 1115, 2,  0,  4,  100,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003d19400224ULL, nullptr, ImplicitList19, OperandInfo43, -1 ,nullptr },  // Inst #1115 = J2_jumptpt
4620
  { 1116, 2,  0,  4,  104,  0, 0x3498400006ULL, nullptr, ImplicitList25, OperandInfo7, -1 ,nullptr },  // Inst #1116 = J2_loop0i
4621
  { 1117, 2,  0,  4,  104,  0, 0x498c00006ULL, nullptr, ImplicitList26, OperandInfo7, -1 ,nullptr },  // Inst #1117 = J2_loop0iext
4622
  { 1118, 2,  0,  4,  105,  0, 0x3498400006ULL, nullptr, ImplicitList25, OperandInfo162, -1 ,nullptr },  // Inst #1118 = J2_loop0r
4623
  { 1119, 2,  0,  4,  105,  0, 0x498c00006ULL, nullptr, ImplicitList9, OperandInfo162, -1 ,nullptr },  // Inst #1119 = J2_loop0rext
4624
  { 1120, 2,  0,  4,  104,  0, 0x3498400006ULL, nullptr, ImplicitList15, OperandInfo7, -1 ,nullptr },  // Inst #1120 = J2_loop1i
4625
  { 1121, 2,  0,  4,  104,  0, 0x498c00006ULL, nullptr, ImplicitList26, OperandInfo7, -1 ,nullptr },  // Inst #1121 = J2_loop1iext
4626
  { 1122, 2,  0,  4,  105,  0, 0x3498400006ULL, nullptr, ImplicitList15, OperandInfo162, -1 ,nullptr },  // Inst #1122 = J2_loop1r
4627
  { 1123, 2,  0,  4,  105,  0, 0x498c00006ULL, nullptr, ImplicitList9, OperandInfo162, -1 ,nullptr },  // Inst #1123 = J2_loop1rext
4628
  { 1124, 1,  0,  4,  106,  0, 0x64ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #1124 = J2_pause
4629
  { 1125, 2,  0,  4,  107,  0, 0x3498401006ULL, nullptr, ImplicitList27, OperandInfo7, -1 ,nullptr },  // Inst #1125 = J2_ploop1si
4630
  { 1126, 2,  0,  4,  108,  0, 0x3498401006ULL, nullptr, ImplicitList27, OperandInfo162, -1 ,nullptr },  // Inst #1126 = J2_ploop1sr
4631
  { 1127, 2,  0,  4,  107,  0, 0x3498401006ULL, nullptr, ImplicitList27, OperandInfo7, -1 ,nullptr },  // Inst #1127 = J2_ploop2si
4632
  { 1128, 2,  0,  4,  108,  0, 0x3498401006ULL, nullptr, ImplicitList27, OperandInfo162, -1 ,nullptr },  // Inst #1128 = J2_ploop2sr
4633
  { 1129, 2,  0,  4,  107,  0, 0x3498401006ULL, nullptr, ImplicitList27, OperandInfo7, -1 ,nullptr },  // Inst #1129 = J2_ploop3si
4634
  { 1130, 2,  0,  4,  108,  0, 0x3498401006ULL, nullptr, ImplicitList27, OperandInfo162, -1 ,nullptr },  // Inst #1130 = J2_ploop3sr
4635
  { 1131, 1,  0,  4,  109,  0, 0x64ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #1131 = J2_trap0
4636
  { 1132, 3,  1,  4,  17, 0, 0x4064ULL, ImplicitList28, ImplicitList29, OperandInfo133, -1 ,nullptr },  // Inst #1132 = J2_trap1
4637
  { 1133, 3,  0,  4,  110,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x4cba402628ULL, nullptr, ImplicitList19, OperandInfo50, -1 ,nullptr },  // Inst #1133 = J4_cmpeq_f_jumpnv_nt
4638
  { 1134, 3,  0,  4,  110,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1004cba402628ULL, nullptr, ImplicitList19, OperandInfo50, -1 ,nullptr },  // Inst #1134 = J4_cmpeq_f_jumpnv_t
4639
  { 1135, 3,  0,  4,  111,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3cba400e04ULL, ImplicitList30, ImplicitList31, OperandInfo163, -1 ,nullptr },  // Inst #1135 = J4_cmpeq_fp0_jump_nt
4640
  { 1136, 3,  0,  4,  111,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003cba400e04ULL, ImplicitList30, ImplicitList31, OperandInfo163, -1 ,nullptr },  // Inst #1136 = J4_cmpeq_fp0_jump_t
4641
  { 1137, 3,  0,  4,  111,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3cba400e04ULL, ImplicitList32, ImplicitList33, OperandInfo163, -1 ,nullptr },  // Inst #1137 = J4_cmpeq_fp1_jump_nt
4642
  { 1138, 3,  0,  4,  111,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003cba400e04ULL, ImplicitList32, ImplicitList33, OperandInfo163, -1 ,nullptr },  // Inst #1138 = J4_cmpeq_fp1_jump_t
4643
  { 1139, 3,  0,  4,  110,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x4cba402228ULL, nullptr, ImplicitList19, OperandInfo50, -1 ,nullptr },  // Inst #1139 = J4_cmpeq_t_jumpnv_nt
4644
  { 1140, 3,  0,  4,  110,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1004cba402228ULL, nullptr, ImplicitList19, OperandInfo50, -1 ,nullptr },  // Inst #1140 = J4_cmpeq_t_jumpnv_t
4645
  { 1141, 3,  0,  4,  111,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3cba400a04ULL, ImplicitList30, ImplicitList31, OperandInfo163, -1 ,nullptr },  // Inst #1141 = J4_cmpeq_tp0_jump_nt
4646
  { 1142, 3,  0,  4,  111,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003cba400a04ULL, ImplicitList30, ImplicitList31, OperandInfo163, -1 ,nullptr },  // Inst #1142 = J4_cmpeq_tp0_jump_t
4647
  { 1143, 3,  0,  4,  111,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3cba400a04ULL, ImplicitList32, ImplicitList33, OperandInfo163, -1 ,nullptr },  // Inst #1143 = J4_cmpeq_tp1_jump_nt
4648
  { 1144, 3,  0,  4,  111,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003cba400a04ULL, ImplicitList32, ImplicitList33, OperandInfo163, -1 ,nullptr },  // Inst #1144 = J4_cmpeq_tp1_jump_t
4649
  { 1145, 3,  0,  4,  112,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x4cba402628ULL, nullptr, ImplicitList19, OperandInfo164, -1 ,nullptr },  // Inst #1145 = J4_cmpeqi_f_jumpnv_nt
4650
  { 1146, 3,  0,  4,  112,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1004cba402628ULL, nullptr, ImplicitList19, OperandInfo164, -1 ,nullptr },  // Inst #1146 = J4_cmpeqi_f_jumpnv_t
4651
  { 1147, 3,  0,  4,  113,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3cba400e04ULL, ImplicitList30, ImplicitList31, OperandInfo165, -1 ,nullptr },  // Inst #1147 = J4_cmpeqi_fp0_jump_nt
4652
  { 1148, 3,  0,  4,  113,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003cba400e04ULL, ImplicitList30, ImplicitList31, OperandInfo165, -1 ,nullptr },  // Inst #1148 = J4_cmpeqi_fp0_jump_t
4653
  { 1149, 3,  0,  4,  113,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3cba400e04ULL, ImplicitList32, ImplicitList33, OperandInfo165, -1 ,nullptr },  // Inst #1149 = J4_cmpeqi_fp1_jump_nt
4654
  { 1150, 3,  0,  4,  113,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003cba400e04ULL, ImplicitList32, ImplicitList33, OperandInfo165, -1 ,nullptr },  // Inst #1150 = J4_cmpeqi_fp1_jump_t
4655
  { 1151, 3,  0,  4,  112,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x4cba402228ULL, nullptr, ImplicitList19, OperandInfo164, -1 ,nullptr },  // Inst #1151 = J4_cmpeqi_t_jumpnv_nt
4656
  { 1152, 3,  0,  4,  112,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1004cba402228ULL, nullptr, ImplicitList19, OperandInfo164, -1 ,nullptr },  // Inst #1152 = J4_cmpeqi_t_jumpnv_t
4657
  { 1153, 3,  0,  4,  113,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3cba400a04ULL, ImplicitList30, ImplicitList31, OperandInfo165, -1 ,nullptr },  // Inst #1153 = J4_cmpeqi_tp0_jump_nt
4658
  { 1154, 3,  0,  4,  113,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003cba400a04ULL, ImplicitList30, ImplicitList31, OperandInfo165, -1 ,nullptr },  // Inst #1154 = J4_cmpeqi_tp0_jump_t
4659
  { 1155, 3,  0,  4,  113,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3cba400a04ULL, ImplicitList32, ImplicitList33, OperandInfo165, -1 ,nullptr },  // Inst #1155 = J4_cmpeqi_tp1_jump_nt
4660
  { 1156, 3,  0,  4,  113,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003cba400a04ULL, ImplicitList32, ImplicitList33, OperandInfo165, -1 ,nullptr },  // Inst #1156 = J4_cmpeqi_tp1_jump_t
4661
  { 1157, 3,  0,  4,  112,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x4cba402628ULL, nullptr, ImplicitList19, OperandInfo164, -1 ,nullptr },  // Inst #1157 = J4_cmpeqn1_f_jumpnv_nt
4662
  { 1158, 3,  0,  4,  112,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1004cba402628ULL, nullptr, ImplicitList19, OperandInfo164, -1 ,nullptr },  // Inst #1158 = J4_cmpeqn1_f_jumpnv_t
4663
  { 1159, 3,  0,  4,  113,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3cba400e04ULL, ImplicitList30, ImplicitList31, OperandInfo165, -1 ,nullptr },  // Inst #1159 = J4_cmpeqn1_fp0_jump_nt
4664
  { 1160, 3,  0,  4,  113,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003cba400e04ULL, ImplicitList30, ImplicitList31, OperandInfo165, -1 ,nullptr },  // Inst #1160 = J4_cmpeqn1_fp0_jump_t
4665
  { 1161, 3,  0,  4,  113,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3cba400e04ULL, ImplicitList32, ImplicitList33, OperandInfo165, -1 ,nullptr },  // Inst #1161 = J4_cmpeqn1_fp1_jump_nt
4666
  { 1162, 3,  0,  4,  113,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003cba400e04ULL, ImplicitList32, ImplicitList33, OperandInfo165, -1 ,nullptr },  // Inst #1162 = J4_cmpeqn1_fp1_jump_t
4667
  { 1163, 3,  0,  4,  112,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x4cba402228ULL, nullptr, ImplicitList19, OperandInfo164, -1 ,nullptr },  // Inst #1163 = J4_cmpeqn1_t_jumpnv_nt
4668
  { 1164, 3,  0,  4,  112,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1004cba402228ULL, nullptr, ImplicitList19, OperandInfo164, -1 ,nullptr },  // Inst #1164 = J4_cmpeqn1_t_jumpnv_t
4669
  { 1165, 3,  0,  4,  113,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3cba400a04ULL, ImplicitList30, ImplicitList31, OperandInfo165, -1 ,nullptr },  // Inst #1165 = J4_cmpeqn1_tp0_jump_nt
4670
  { 1166, 3,  0,  4,  113,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003cba400a04ULL, ImplicitList30, ImplicitList31, OperandInfo165, -1 ,nullptr },  // Inst #1166 = J4_cmpeqn1_tp0_jump_t
4671
  { 1167, 3,  0,  4,  113,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3cba400a04ULL, ImplicitList32, ImplicitList33, OperandInfo165, -1 ,nullptr },  // Inst #1167 = J4_cmpeqn1_tp1_jump_nt
4672
  { 1168, 3,  0,  4,  113,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003cba400a04ULL, ImplicitList32, ImplicitList33, OperandInfo165, -1 ,nullptr },  // Inst #1168 = J4_cmpeqn1_tp1_jump_t
4673
  { 1169, 3,  0,  4,  110,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x4cba402628ULL, nullptr, ImplicitList19, OperandInfo50, -1 ,nullptr },  // Inst #1169 = J4_cmpgt_f_jumpnv_nt
4674
  { 1170, 3,  0,  4,  110,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1004cba402628ULL, nullptr, ImplicitList19, OperandInfo50, -1 ,nullptr },  // Inst #1170 = J4_cmpgt_f_jumpnv_t
4675
  { 1171, 3,  0,  4,  111,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3cba400e04ULL, ImplicitList30, ImplicitList31, OperandInfo163, -1 ,nullptr },  // Inst #1171 = J4_cmpgt_fp0_jump_nt
4676
  { 1172, 3,  0,  4,  111,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003cba400e04ULL, ImplicitList30, ImplicitList31, OperandInfo163, -1 ,nullptr },  // Inst #1172 = J4_cmpgt_fp0_jump_t
4677
  { 1173, 3,  0,  4,  111,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3cba400e04ULL, ImplicitList32, ImplicitList33, OperandInfo163, -1 ,nullptr },  // Inst #1173 = J4_cmpgt_fp1_jump_nt
4678
  { 1174, 3,  0,  4,  111,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003cba400e04ULL, ImplicitList32, ImplicitList33, OperandInfo163, -1 ,nullptr },  // Inst #1174 = J4_cmpgt_fp1_jump_t
4679
  { 1175, 3,  0,  4,  110,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x4cba402228ULL, nullptr, ImplicitList19, OperandInfo50, -1 ,nullptr },  // Inst #1175 = J4_cmpgt_t_jumpnv_nt
4680
  { 1176, 3,  0,  4,  110,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1004cba402228ULL, nullptr, ImplicitList19, OperandInfo50, -1 ,nullptr },  // Inst #1176 = J4_cmpgt_t_jumpnv_t
4681
  { 1177, 3,  0,  4,  111,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3cba400a04ULL, ImplicitList30, ImplicitList31, OperandInfo163, -1 ,nullptr },  // Inst #1177 = J4_cmpgt_tp0_jump_nt
4682
  { 1178, 3,  0,  4,  111,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003cba400a04ULL, ImplicitList30, ImplicitList31, OperandInfo163, -1 ,nullptr },  // Inst #1178 = J4_cmpgt_tp0_jump_t
4683
  { 1179, 3,  0,  4,  111,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3cba400a04ULL, ImplicitList32, ImplicitList33, OperandInfo163, -1 ,nullptr },  // Inst #1179 = J4_cmpgt_tp1_jump_nt
4684
  { 1180, 3,  0,  4,  111,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003cba400a04ULL, ImplicitList32, ImplicitList33, OperandInfo163, -1 ,nullptr },  // Inst #1180 = J4_cmpgt_tp1_jump_t
4685
  { 1181, 3,  0,  4,  112,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x4cba402628ULL, nullptr, ImplicitList19, OperandInfo164, -1 ,nullptr },  // Inst #1181 = J4_cmpgti_f_jumpnv_nt
4686
  { 1182, 3,  0,  4,  112,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1004cba402628ULL, nullptr, ImplicitList19, OperandInfo164, -1 ,nullptr },  // Inst #1182 = J4_cmpgti_f_jumpnv_t
4687
  { 1183, 3,  0,  4,  113,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3cba400e04ULL, ImplicitList30, ImplicitList31, OperandInfo165, -1 ,nullptr },  // Inst #1183 = J4_cmpgti_fp0_jump_nt
4688
  { 1184, 3,  0,  4,  113,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003cba400e04ULL, ImplicitList30, ImplicitList31, OperandInfo165, -1 ,nullptr },  // Inst #1184 = J4_cmpgti_fp0_jump_t
4689
  { 1185, 3,  0,  4,  113,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3cba400e04ULL, ImplicitList32, ImplicitList33, OperandInfo165, -1 ,nullptr },  // Inst #1185 = J4_cmpgti_fp1_jump_nt
4690
  { 1186, 3,  0,  4,  113,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003cba400e04ULL, ImplicitList32, ImplicitList33, OperandInfo165, -1 ,nullptr },  // Inst #1186 = J4_cmpgti_fp1_jump_t
4691
  { 1187, 3,  0,  4,  112,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x4cba402228ULL, nullptr, ImplicitList19, OperandInfo164, -1 ,nullptr },  // Inst #1187 = J4_cmpgti_t_jumpnv_nt
4692
  { 1188, 3,  0,  4,  112,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1004cba402228ULL, nullptr, ImplicitList19, OperandInfo164, -1 ,nullptr },  // Inst #1188 = J4_cmpgti_t_jumpnv_t
4693
  { 1189, 3,  0,  4,  113,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3cba400a04ULL, ImplicitList30, ImplicitList31, OperandInfo165, -1 ,nullptr },  // Inst #1189 = J4_cmpgti_tp0_jump_nt
4694
  { 1190, 3,  0,  4,  113,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003cba400a04ULL, ImplicitList30, ImplicitList31, OperandInfo165, -1 ,nullptr },  // Inst #1190 = J4_cmpgti_tp0_jump_t
4695
  { 1191, 3,  0,  4,  113,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3cba400a04ULL, ImplicitList32, ImplicitList33, OperandInfo165, -1 ,nullptr },  // Inst #1191 = J4_cmpgti_tp1_jump_nt
4696
  { 1192, 3,  0,  4,  113,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003cba400a04ULL, ImplicitList32, ImplicitList33, OperandInfo165, -1 ,nullptr },  // Inst #1192 = J4_cmpgti_tp1_jump_t
4697
  { 1193, 3,  0,  4,  112,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x4cba402628ULL, nullptr, ImplicitList19, OperandInfo164, -1 ,nullptr },  // Inst #1193 = J4_cmpgtn1_f_jumpnv_nt
4698
  { 1194, 3,  0,  4,  112,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1004cba402628ULL, nullptr, ImplicitList19, OperandInfo164, -1 ,nullptr },  // Inst #1194 = J4_cmpgtn1_f_jumpnv_t
4699
  { 1195, 3,  0,  4,  113,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x3cba400e04ULL, ImplicitList30, ImplicitList31, OperandInfo165, -1 ,nullptr },  // Inst #1195 = J4_cmpgtn1_fp0_jump_nt
4700
  { 1196, 3,  0,  4,  113,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1003cba400e04ULL, ImplicitList30, ImplicitList31, OperandInfo165, -1 ,nullptr },  // Inst #1196 = J4_cmpgtn1_fp0_jump_t
4701
  { 1197