Coverage Report

Created: 2018-11-16 02:38

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Hexagon/HexagonGenRegisterInfo.inc
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Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Register Enum Values                                                *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
#ifdef GET_REGINFO_ENUM
11
#undef GET_REGINFO_ENUM
12
13
namespace llvm {
14
15
class MCRegisterClass;
16
extern const MCRegisterClass HexagonMCRegisterClasses[];
17
18
namespace Hexagon {
19
enum {
20
  NoRegister,
21
  CS = 1,
22
  FRAMEKEY = 2,
23
  FRAMELIMIT = 3,
24
  GELR = 4,
25
  GOSP = 5,
26
  GP = 6,
27
  GPCYCLEHI = 7,
28
  GPCYCLELO = 8,
29
  GSR = 9,
30
  PC = 10,
31
  PKTCOUNT = 11,
32
  PKTCOUNTHI = 12,
33
  PKTCOUNTLO = 13,
34
  UGP = 14,
35
  UPCYCLE = 15,
36
  UPCYCLEHI = 16,
37
  UPCYCLELO = 17,
38
  USR = 18,
39
  USR_OVF = 19,
40
  UTIMER = 20,
41
  UTIMERHI = 21,
42
  UTIMERLO = 22,
43
  VTMP = 23,
44
  C5 = 24,
45
  C8 = 25,
46
  CS0 = 26,
47
  CS1 = 27,
48
  D0 = 28,
49
  D1 = 29,
50
  D2 = 30,
51
  D3 = 31,
52
  D4 = 32,
53
  D5 = 33,
54
  D6 = 34,
55
  D7 = 35,
56
  D8 = 36,
57
  D9 = 37,
58
  D10 = 38,
59
  D11 = 39,
60
  D12 = 40,
61
  D13 = 41,
62
  D14 = 42,
63
  D15 = 43,
64
  G3 = 44,
65
  G4 = 45,
66
  G5 = 46,
67
  G6 = 47,
68
  G7 = 48,
69
  G8 = 49,
70
  G9 = 50,
71
  G10 = 51,
72
  G11 = 52,
73
  G12 = 53,
74
  G13 = 54,
75
  G14 = 55,
76
  G15 = 56,
77
  G20 = 57,
78
  G21 = 58,
79
  G22 = 59,
80
  G23 = 60,
81
  G30 = 61,
82
  G31 = 62,
83
  GPMUCNT0 = 63,
84
  GPMUCNT1 = 64,
85
  GPMUCNT2 = 65,
86
  GPMUCNT3 = 66,
87
  GPMUCNT4 = 67,
88
  GPMUCNT5 = 68,
89
  GPMUCNT6 = 69,
90
  GPMUCNT7 = 70,
91
  LC0 = 71,
92
  LC1 = 72,
93
  M0 = 73,
94
  M1 = 74,
95
  P0 = 75,
96
  P1 = 76,
97
  P2 = 77,
98
  P3 = 78,
99
  Q0 = 79,
100
  Q1 = 80,
101
  Q2 = 81,
102
  Q3 = 82,
103
  R0 = 83,
104
  R1 = 84,
105
  R2 = 85,
106
  R3 = 86,
107
  R4 = 87,
108
  R5 = 88,
109
  R6 = 89,
110
  R7 = 90,
111
  R8 = 91,
112
  R9 = 92,
113
  R10 = 93,
114
  R11 = 94,
115
  R12 = 95,
116
  R13 = 96,
117
  R14 = 97,
118
  R15 = 98,
119
  R16 = 99,
120
  R17 = 100,
121
  R18 = 101,
122
  R19 = 102,
123
  R20 = 103,
124
  R21 = 104,
125
  R22 = 105,
126
  R23 = 106,
127
  R24 = 107,
128
  R25 = 108,
129
  R26 = 109,
130
  R27 = 110,
131
  R28 = 111,
132
  R29 = 112,
133
  R30 = 113,
134
  R31 = 114,
135
  SA0 = 115,
136
  SA1 = 116,
137
  V0 = 117,
138
  V1 = 118,
139
  V2 = 119,
140
  V3 = 120,
141
  V4 = 121,
142
  V5 = 122,
143
  V6 = 123,
144
  V7 = 124,
145
  V8 = 125,
146
  V9 = 126,
147
  V10 = 127,
148
  V11 = 128,
149
  V12 = 129,
150
  V13 = 130,
151
  V14 = 131,
152
  V15 = 132,
153
  V16 = 133,
154
  V17 = 134,
155
  V18 = 135,
156
  V19 = 136,
157
  V20 = 137,
158
  V21 = 138,
159
  V22 = 139,
160
  V23 = 140,
161
  V24 = 141,
162
  V25 = 142,
163
  V26 = 143,
164
  V27 = 144,
165
  V28 = 145,
166
  V29 = 146,
167
  V30 = 147,
168
  V31 = 148,
169
  W0 = 149,
170
  W1 = 150,
171
  W2 = 151,
172
  W3 = 152,
173
  W4 = 153,
174
  W5 = 154,
175
  W6 = 155,
176
  W7 = 156,
177
  W8 = 157,
178
  W9 = 158,
179
  W10 = 159,
180
  W11 = 160,
181
  W12 = 161,
182
  W13 = 162,
183
  W14 = 163,
184
  W15 = 164,
185
  C1_0 = 165,
186
  C3_2 = 166,
187
  C5_4 = 167,
188
  C7_6 = 168,
189
  C9_8 = 169,
190
  C11_10 = 170,
191
  C17_16 = 171,
192
  G1_0 = 172,
193
  G3_2 = 173,
194
  G5_4 = 174,
195
  G7_6 = 175,
196
  G9_8 = 176,
197
  G11_10 = 177,
198
  G13_12 = 178,
199
  G15_14 = 179,
200
  G17_16 = 180,
201
  G19_18 = 181,
202
  G21_20 = 182,
203
  G23_22 = 183,
204
  G25_24 = 184,
205
  G27_26 = 185,
206
  G29_28 = 186,
207
  G31_30 = 187,
208
  P3_0 = 188,
209
  NUM_TARGET_REGS   // 189
210
};
211
} // end namespace Hexagon
212
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// Register classes
214
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namespace Hexagon {
216
enum {
217
  UsrBitsRegClassID = 0,
218
  GuestRegsRegClassID = 1,
219
  IntRegsRegClassID = 2,
220
  CtrRegsRegClassID = 3,
221
  GeneralSubRegsRegClassID = 4,
222
  V62RegsRegClassID = 5,
223
  IntRegsLow8RegClassID = 6,
224
  CtrRegs_and_V62RegsRegClassID = 7,
225
  PredRegsRegClassID = 8,
226
  V62Regs_with_isub_hiRegClassID = 9,
227
  ModRegsRegClassID = 10,
228
  CtrRegs_with_subreg_overflowRegClassID = 11,
229
  V65RegsRegClassID = 12,
230
  DoubleRegsRegClassID = 13,
231
  GuestRegs64RegClassID = 14,
232
  CtrRegs64RegClassID = 15,
233
  GeneralDoubleLow8RegsRegClassID = 16,
234
  DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID = 17,
235
  CtrRegs64_and_V62RegsRegClassID = 18,
236
  CtrRegs64_with_isub_hi_in_ModRegsRegClassID = 19,
237
  HvxVRRegClassID = 20,
238
  HvxQRRegClassID = 21,
239
  HvxVR_and_V65RegsRegClassID = 22,
240
  HvxWRRegClassID = 23,
241
242
  };
243
} // end namespace Hexagon
244
245
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// Subregister indices
247
248
namespace Hexagon {
249
enum {
250
  NoSubRegister,
251
  isub_hi,  // 1
252
  isub_lo,  // 2
253
  subreg_overflow,  // 3
254
  vsub_hi,  // 4
255
  vsub_lo,  // 5
256
  NUM_TARGET_SUBREGS
257
};
258
} // end namespace Hexagon
259
260
} // end namespace llvm
261
262
#endif // GET_REGINFO_ENUM
263
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
265
|*                                                                            *|
266
|* MC Register Information                                                    *|
267
|*                                                                            *|
268
|* Automatically generated file, do not edit!                                 *|
269
|*                                                                            *|
270
\*===----------------------------------------------------------------------===*/
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#ifdef GET_REGINFO_MC_DESC
274
#undef GET_REGINFO_MC_DESC
275
276
namespace llvm {
277
278
extern const MCPhysReg HexagonRegDiffLists[] = {
279
  /* 0 */ 0, 0,
280
  /* 2 */ 0, 1, 0,
281
  /* 5 */ 21, 64, 1, 1, 1, 0,
282
  /* 11 */ 85, 1, 1, 1, 0,
283
  /* 16 */ 7, 1, 0,
284
  /* 19 */ 11, 1, 0,
285
  /* 22 */ 14, 1, 0,
286
  /* 25 */ 16, 1, 0,
287
  /* 28 */ 18, 1, 0,
288
  /* 31 */ 25, 1, 0,
289
  /* 34 */ 55, 1, 0,
290
  /* 37 */ 56, 1, 0,
291
  /* 40 */ 57, 1, 0,
292
  /* 43 */ 58, 1, 0,
293
  /* 46 */ 59, 1, 0,
294
  /* 49 */ 60, 1, 0,
295
  /* 52 */ 61, 1, 0,
296
  /* 55 */ 62, 1, 0,
297
  /* 58 */ 63, 1, 0,
298
  /* 61 */ 64, 1, 0,
299
  /* 64 */ 65, 1, 0,
300
  /* 67 */ 66, 1, 0,
301
  /* 70 */ 67, 1, 0,
302
  /* 73 */ 68, 1, 0,
303
  /* 76 */ 69, 1, 0,
304
  /* 79 */ 70, 1, 0,
305
  /* 82 */ 71, 1, 0,
306
  /* 85 */ 83, 1, 0,
307
  /* 88 */ 65196, 1, 0,
308
  /* 91 */ 65239, 1, 0,
309
  /* 94 */ 65243, 1, 0,
310
  /* 97 */ 65253, 1, 0,
311
  /* 100 */ 65333, 1, 0,
312
  /* 103 */ 65407, 1, 0,
313
  /* 106 */ 65408, 1, 0,
314
  /* 109 */ 65409, 1, 0,
315
  /* 112 */ 65410, 1, 0,
316
  /* 115 */ 65411, 1, 0,
317
  /* 118 */ 65412, 1, 0,
318
  /* 121 */ 65414, 1, 0,
319
  /* 124 */ 65415, 1, 0,
320
  /* 127 */ 65423, 1, 0,
321
  /* 130 */ 65424, 1, 0,
322
  /* 133 */ 65441, 1, 0,
323
  /* 136 */ 65502, 1, 0,
324
  /* 139 */ 65504, 1, 0,
325
  /* 142 */ 65505, 1, 0,
326
  /* 145 */ 65506, 1, 0,
327
  /* 148 */ 65507, 1, 0,
328
  /* 151 */ 65508, 1, 0,
329
  /* 154 */ 65509, 1, 0,
330
  /* 157 */ 65510, 1, 0,
331
  /* 160 */ 65511, 1, 0,
332
  /* 163 */ 65512, 1, 0,
333
  /* 166 */ 65513, 1, 0,
334
  /* 169 */ 65514, 1, 0,
335
  /* 172 */ 65515, 1, 0,
336
  /* 175 */ 65516, 1, 0,
337
  /* 178 */ 65517, 1, 0,
338
  /* 181 */ 65518, 1, 0,
339
  /* 184 */ 65519, 1, 0,
340
  /* 187 */ 65368, 5, 0,
341
  /* 190 */ 6, 7, 0,
342
  /* 193 */ 10, 7, 0,
343
  /* 196 */ 10, 0,
344
  /* 198 */ 65452, 12, 0,
345
  /* 201 */ 14, 0,
346
  /* 203 */ 15, 0,
347
  /* 205 */ 16, 0,
348
  /* 207 */ 17, 0,
349
  /* 209 */ 18, 0,
350
  /* 211 */ 19, 0,
351
  /* 213 */ 20, 0,
352
  /* 215 */ 21, 0,
353
  /* 217 */ 22, 0,
354
  /* 219 */ 23, 0,
355
  /* 221 */ 24, 0,
356
  /* 223 */ 25, 0,
357
  /* 225 */ 26, 0,
358
  /* 227 */ 27, 0,
359
  /* 229 */ 28, 0,
360
  /* 231 */ 29, 0,
361
  /* 233 */ 30, 0,
362
  /* 235 */ 31, 0,
363
  /* 237 */ 32, 0,
364
  /* 239 */ 65368, 39, 0,
365
  /* 242 */ 65368, 49, 0,
366
  /* 245 */ 50, 0,
367
  /* 247 */ 94, 0,
368
  /* 249 */ 95, 0,
369
  /* 251 */ 111, 0,
370
  /* 253 */ 112, 0,
371
  /* 255 */ 113, 0,
372
  /* 257 */ 120, 0,
373
  /* 259 */ 121, 0,
374
  /* 261 */ 122, 0,
375
  /* 263 */ 123, 0,
376
  /* 265 */ 124, 0,
377
  /* 267 */ 125, 0,
378
  /* 269 */ 126, 0,
379
  /* 271 */ 127, 0,
380
  /* 273 */ 128, 0,
381
  /* 275 */ 129, 0,
382
  /* 277 */ 143, 0,
383
  /* 279 */ 144, 0,
384
  /* 281 */ 156, 0,
385
  /* 283 */ 159, 0,
386
  /* 285 */ 163, 0,
387
  /* 287 */ 164, 0,
388
  /* 289 */ 168, 0,
389
  /* 291 */ 169, 0,
390
  /* 293 */ 176, 0,
391
  /* 295 */ 177, 0,
392
  /* 297 */ 21, 65372, 0,
393
  /* 300 */ 65465, 0,
394
  /* 302 */ 65466, 0,
395
  /* 304 */ 65467, 0,
396
  /* 306 */ 65468, 0,
397
  /* 308 */ 65469, 0,
398
  /* 310 */ 65470, 0,
399
  /* 312 */ 65471, 0,
400
  /* 314 */ 65472, 0,
401
  /* 316 */ 65473, 0,
402
  /* 318 */ 65474, 0,
403
  /* 320 */ 65475, 0,
404
  /* 322 */ 65476, 0,
405
  /* 324 */ 65477, 0,
406
  /* 326 */ 65478, 0,
407
  /* 328 */ 65479, 0,
408
  /* 330 */ 65480, 0,
409
  /* 332 */ 65481, 0,
410
  /* 334 */ 65486, 65492, 0,
411
  /* 337 */ 65510, 0,
412
  /* 339 */ 65511, 0,
413
  /* 341 */ 65514, 0,
414
  /* 343 */ 65515, 0,
415
  /* 345 */ 65392, 65521, 0,
416
  /* 348 */ 65380, 65528, 0,
417
  /* 351 */ 65533, 0,
418
  /* 353 */ 65534, 0,
419
  /* 355 */ 2, 65535, 0,
420
  /* 358 */ 65360, 65535, 0,
421
  /* 361 */ 65368, 65535, 0,
422
};
423
424
extern const LaneBitmask HexagonLaneMaskLists[] = {
425
  /* 0 */ LaneBitmask(0x00000000), LaneBitmask(0x00000000), LaneBitmask(0x00000000), LaneBitmask(0x00000000), LaneBitmask::getAll(),
426
  /* 5 */ LaneBitmask(0x00000004), LaneBitmask(0x00000000), LaneBitmask::getAll(),
427
  /* 8 */ LaneBitmask(0x00000002), LaneBitmask(0x00000001), LaneBitmask::getAll(),
428
  /* 11 */ LaneBitmask(0x00000001), LaneBitmask(0x00000002), LaneBitmask::getAll(),
429
  /* 14 */ LaneBitmask(0x00000001), LaneBitmask(0x00000002), LaneBitmask(0x00000002), LaneBitmask(0x00000002), LaneBitmask(0x00000002), LaneBitmask::getAll(),
430
  /* 20 */ LaneBitmask(0x00000010), LaneBitmask(0x00000008), LaneBitmask::getAll(),
431
};
432
433
extern const uint16_t HexagonSubRegIdxLists[] = {
434
  /* 0 */ 2, 1, 0,
435
  /* 3 */ 3, 0,
436
  /* 5 */ 5, 4, 0,
437
};
438
439
extern const MCRegisterInfo::SubRegCoveredBits HexagonSubRegIdxRanges[] = {
440
  { 65535, 65535 },
441
  { 32, 32 }, // isub_hi
442
  { 0, 32 },  // isub_lo
443
  { 0, 1 }, // subreg_overflow
444
  { 512, 512 }, // vsub_hi
445
  { 0, 512 }, // vsub_lo
446
};
447
448
extern const char HexagonRegStrings[] = {
449
  /* 0 */ 'D', '1', '0', 0,
450
  /* 4 */ 'G', '1', '0', 0,
451
  /* 8 */ 'R', '1', '0', 0,
452
  /* 12 */ 'V', '1', '0', 0,
453
  /* 16 */ 'W', '1', '0', 0,
454
  /* 20 */ 'C', '1', '1', '_', '1', '0', 0,
455
  /* 27 */ 'G', '1', '1', '_', '1', '0', 0,
456
  /* 34 */ 'G', '2', '0', 0,
457
  /* 38 */ 'R', '2', '0', 0,
458
  /* 42 */ 'V', '2', '0', 0,
459
  /* 46 */ 'G', '2', '1', '_', '2', '0', 0,
460
  /* 53 */ 'G', '3', '0', 0,
461
  /* 57 */ 'R', '3', '0', 0,
462
  /* 61 */ 'V', '3', '0', 0,
463
  /* 65 */ 'G', '3', '1', '_', '3', '0', 0,
464
  /* 72 */ 'S', 'A', '0', 0,
465
  /* 76 */ 'L', 'C', '0', 0,
466
  /* 80 */ 'D', '0', 0,
467
  /* 83 */ 'M', '0', 0,
468
  /* 86 */ 'P', '0', 0,
469
  /* 89 */ 'Q', '0', 0,
470
  /* 92 */ 'R', '0', 0,
471
  /* 95 */ 'C', 'S', '0', 0,
472
  /* 99 */ 'G', 'P', 'M', 'U', 'C', 'N', 'T', '0', 0,
473
  /* 108 */ 'V', '0', 0,
474
  /* 111 */ 'W', '0', 0,
475
  /* 114 */ 'C', '1', '_', '0', 0,
476
  /* 119 */ 'G', '1', '_', '0', 0,
477
  /* 124 */ 'P', '3', '_', '0', 0,
478
  /* 129 */ 'D', '1', '1', 0,
479
  /* 133 */ 'G', '1', '1', 0,
480
  /* 137 */ 'R', '1', '1', 0,
481
  /* 141 */ 'V', '1', '1', 0,
482
  /* 145 */ 'W', '1', '1', 0,
483
  /* 149 */ 'G', '2', '1', 0,
484
  /* 153 */ 'R', '2', '1', 0,
485
  /* 157 */ 'V', '2', '1', 0,
486
  /* 161 */ 'G', '3', '1', 0,
487
  /* 165 */ 'R', '3', '1', 0,
488
  /* 169 */ 'V', '3', '1', 0,
489
  /* 173 */ 'S', 'A', '1', 0,
490
  /* 177 */ 'L', 'C', '1', 0,
491
  /* 181 */ 'D', '1', 0,
492
  /* 184 */ 'M', '1', 0,
493
  /* 187 */ 'P', '1', 0,
494
  /* 190 */ 'Q', '1', 0,
495
  /* 193 */ 'R', '1', 0,
496
  /* 196 */ 'C', 'S', '1', 0,
497
  /* 200 */ 'G', 'P', 'M', 'U', 'C', 'N', 'T', '1', 0,
498
  /* 209 */ 'V', '1', 0,
499
  /* 212 */ 'W', '1', 0,
500
  /* 215 */ 'D', '1', '2', 0,
501
  /* 219 */ 'G', '1', '2', 0,
502
  /* 223 */ 'R', '1', '2', 0,
503
  /* 227 */ 'V', '1', '2', 0,
504
  /* 231 */ 'W', '1', '2', 0,
505
  /* 235 */ 'G', '1', '3', '_', '1', '2', 0,
506
  /* 242 */ 'G', '2', '2', 0,
507
  /* 246 */ 'R', '2', '2', 0,
508
  /* 250 */ 'V', '2', '2', 0,
509
  /* 254 */ 'G', '2', '3', '_', '2', '2', 0,
510
  /* 261 */ 'D', '2', 0,
511
  /* 264 */ 'P', '2', 0,
512
  /* 267 */ 'Q', '2', 0,
513
  /* 270 */ 'R', '2', 0,
514
  /* 273 */ 'G', 'P', 'M', 'U', 'C', 'N', 'T', '2', 0,
515
  /* 282 */ 'V', '2', 0,
516
  /* 285 */ 'W', '2', 0,
517
  /* 288 */ 'C', '3', '_', '2', 0,
518
  /* 293 */ 'G', '3', '_', '2', 0,
519
  /* 298 */ 'D', '1', '3', 0,
520
  /* 302 */ 'G', '1', '3', 0,
521
  /* 306 */ 'R', '1', '3', 0,
522
  /* 310 */ 'V', '1', '3', 0,
523
  /* 314 */ 'W', '1', '3', 0,
524
  /* 318 */ 'G', '2', '3', 0,
525
  /* 322 */ 'R', '2', '3', 0,
526
  /* 326 */ 'V', '2', '3', 0,
527
  /* 330 */ 'D', '3', 0,
528
  /* 333 */ 'G', '3', 0,
529
  /* 336 */ 'P', '3', 0,
530
  /* 339 */ 'Q', '3', 0,
531
  /* 342 */ 'R', '3', 0,
532
  /* 345 */ 'G', 'P', 'M', 'U', 'C', 'N', 'T', '3', 0,
533
  /* 354 */ 'V', '3', 0,
534
  /* 357 */ 'W', '3', 0,
535
  /* 360 */ 'D', '1', '4', 0,
536
  /* 364 */ 'G', '1', '4', 0,
537
  /* 368 */ 'R', '1', '4', 0,
538
  /* 372 */ 'V', '1', '4', 0,
539
  /* 376 */ 'W', '1', '4', 0,
540
  /* 380 */ 'G', '1', '5', '_', '1', '4', 0,
541
  /* 387 */ 'R', '2', '4', 0,
542
  /* 391 */ 'V', '2', '4', 0,
543
  /* 395 */ 'G', '2', '5', '_', '2', '4', 0,
544
  /* 402 */ 'D', '4', 0,
545
  /* 405 */ 'G', '4', 0,
546
  /* 408 */ 'R', '4', 0,
547
  /* 411 */ 'G', 'P', 'M', 'U', 'C', 'N', 'T', '4', 0,
548
  /* 420 */ 'V', '4', 0,
549
  /* 423 */ 'W', '4', 0,
550
  /* 426 */ 'C', '5', '_', '4', 0,
551
  /* 431 */ 'G', '5', '_', '4', 0,
552
  /* 436 */ 'D', '1', '5', 0,
553
  /* 440 */ 'G', '1', '5', 0,
554
  /* 444 */ 'R', '1', '5', 0,
555
  /* 448 */ 'V', '1', '5', 0,
556
  /* 452 */ 'W', '1', '5', 0,
557
  /* 456 */ 'R', '2', '5', 0,
558
  /* 460 */ 'V', '2', '5', 0,
559
  /* 464 */ 'C', '5', 0,
560
  /* 467 */ 'D', '5', 0,
561
  /* 470 */ 'G', '5', 0,
562
  /* 473 */ 'R', '5', 0,
563
  /* 476 */ 'G', 'P', 'M', 'U', 'C', 'N', 'T', '5', 0,
564
  /* 485 */ 'V', '5', 0,
565
  /* 488 */ 'W', '5', 0,
566
  /* 491 */ 'R', '1', '6', 0,
567
  /* 495 */ 'V', '1', '6', 0,
568
  /* 499 */ 'C', '1', '7', '_', '1', '6', 0,
569
  /* 506 */ 'G', '1', '7', '_', '1', '6', 0,
570
  /* 513 */ 'R', '2', '6', 0,
571
  /* 517 */ 'V', '2', '6', 0,
572
  /* 521 */ 'G', '2', '7', '_', '2', '6', 0,
573
  /* 528 */ 'D', '6', 0,
574
  /* 531 */ 'G', '6', 0,
575
  /* 534 */ 'R', '6', 0,
576
  /* 537 */ 'G', 'P', 'M', 'U', 'C', 'N', 'T', '6', 0,
577
  /* 546 */ 'V', '6', 0,
578
  /* 549 */ 'W', '6', 0,
579
  /* 552 */ 'C', '7', '_', '6', 0,
580
  /* 557 */ 'G', '7', '_', '6', 0,
581
  /* 562 */ 'R', '1', '7', 0,
582
  /* 566 */ 'V', '1', '7', 0,
583
  /* 570 */ 'R', '2', '7', 0,
584
  /* 574 */ 'V', '2', '7', 0,
585
  /* 578 */ 'D', '7', 0,
586
  /* 581 */ 'G', '7', 0,
587
  /* 584 */ 'R', '7', 0,
588
  /* 587 */ 'G', 'P', 'M', 'U', 'C', 'N', 'T', '7', 0,
589
  /* 596 */ 'V', '7', 0,
590
  /* 599 */ 'W', '7', 0,
591
  /* 602 */ 'R', '1', '8', 0,
592
  /* 606 */ 'V', '1', '8', 0,
593
  /* 610 */ 'G', '1', '9', '_', '1', '8', 0,
594
  /* 617 */ 'R', '2', '8', 0,
595
  /* 621 */ 'V', '2', '8', 0,
596
  /* 625 */ 'G', '2', '9', '_', '2', '8', 0,
597
  /* 632 */ 'C', '8', 0,
598
  /* 635 */ 'D', '8', 0,
599
  /* 638 */ 'G', '8', 0,
600
  /* 641 */ 'R', '8', 0,
601
  /* 644 */ 'V', '8', 0,
602
  /* 647 */ 'W', '8', 0,
603
  /* 650 */ 'C', '9', '_', '8', 0,
604
  /* 655 */ 'G', '9', '_', '8', 0,
605
  /* 660 */ 'R', '1', '9', 0,
606
  /* 664 */ 'V', '1', '9', 0,
607
  /* 668 */ 'R', '2', '9', 0,
608
  /* 672 */ 'V', '2', '9', 0,
609
  /* 676 */ 'D', '9', 0,
610
  /* 679 */ 'G', '9', 0,
611
  /* 682 */ 'R', '9', 0,
612
  /* 685 */ 'V', '9', 0,
613
  /* 688 */ 'W', '9', 0,
614
  /* 691 */ 'P', 'C', 0,
615
  /* 694 */ 'U', 'P', 'C', 'Y', 'C', 'L', 'E', 0,
616
  /* 702 */ 'U', 'S', 'R', '_', 'O', 'V', 'F', 0,
617
  /* 710 */ 'G', 'P', 'C', 'Y', 'C', 'L', 'E', 'H', 'I', 0,
618
  /* 720 */ 'U', 'P', 'C', 'Y', 'C', 'L', 'E', 'H', 'I', 0,
619
  /* 730 */ 'U', 'T', 'I', 'M', 'E', 'R', 'H', 'I', 0,
620
  /* 739 */ 'P', 'K', 'T', 'C', 'O', 'U', 'N', 'T', 'H', 'I', 0,
621
  /* 750 */ 'G', 'P', 'C', 'Y', 'C', 'L', 'E', 'L', 'O', 0,
622
  /* 760 */ 'U', 'P', 'C', 'Y', 'C', 'L', 'E', 'L', 'O', 0,
623
  /* 770 */ 'U', 'T', 'I', 'M', 'E', 'R', 'L', 'O', 0,
624
  /* 779 */ 'P', 'K', 'T', 'C', 'O', 'U', 'N', 'T', 'L', 'O', 0,
625
  /* 790 */ 'U', 'G', 'P', 0,
626
  /* 794 */ 'V', 'T', 'M', 'P', 0,
627
  /* 799 */ 'G', 'O', 'S', 'P', 0,
628
  /* 804 */ 'U', 'T', 'I', 'M', 'E', 'R', 0,
629
  /* 811 */ 'G', 'E', 'L', 'R', 0,
630
  /* 816 */ 'G', 'S', 'R', 0,
631
  /* 820 */ 'U', 'S', 'R', 0,
632
  /* 824 */ 'C', 'S', 0,
633
  /* 827 */ 'F', 'R', 'A', 'M', 'E', 'L', 'I', 'M', 'I', 'T', 0,
634
  /* 838 */ 'P', 'K', 'T', 'C', 'O', 'U', 'N', 'T', 0,
635
  /* 847 */ 'F', 'R', 'A', 'M', 'E', 'K', 'E', 'Y', 0,
636
};
637
638
extern const MCRegisterDesc HexagonRegDesc[] = { // Descriptors
639
  { 3, 0, 0, 0, 0, 0 },
640
  { 824, 31, 1, 0, 32, 8 },
641
  { 847, 1, 291, 2, 1, 3 },
642
  { 827, 1, 289, 2, 1, 3 },
643
  { 811, 1, 289, 2, 1, 3 },
644
  { 799, 1, 289, 2, 1, 3 },
645
  { 791, 1, 287, 2, 1, 3 },
646
  { 710, 1, 295, 2, 1, 3 },
647
  { 750, 1, 293, 2, 1, 3 },
648
  { 816, 1, 285, 2, 1, 3 },
649
  { 691, 1, 283, 2, 1, 3 },
650
  { 838, 355, 1, 0, 304, 8 },
651
  { 739, 1, 356, 2, 3184, 3 },
652
  { 779, 1, 353, 2, 5538, 3 },
653
  { 790, 1, 281, 2, 5538, 3 },
654
  { 694, 355, 1, 0, 352, 8 },
655
  { 720, 1, 356, 2, 3248, 3 },
656
  { 760, 1, 353, 2, 3216, 3 },
657
  { 820, 3, 1, 3, 400, 5 },
658
  { 702, 1, 356, 2, 3280, 3 },
659
  { 804, 355, 1, 0, 448, 8 },
660
  { 730, 1, 356, 2, 3376, 3 },
661
  { 770, 1, 353, 2, 5394, 3 },
662
  { 794, 1, 1, 2, 5617, 3 },
663
  { 464, 1, 277, 2, 5617, 3 },
664
  { 632, 1, 279, 2, 3312, 3 },
665
  { 95, 1, 339, 2, 5393, 3 },
666
  { 196, 1, 337, 2, 5393, 3 },
667
  { 80, 34, 1, 0, 2178, 8 },
668
  { 181, 37, 1, 0, 2178, 8 },
669
  { 261, 40, 1, 0, 2178, 8 },
670
  { 330, 43, 1, 0, 2178, 8 },
671
  { 402, 46, 1, 0, 2178, 8 },
672
  { 467, 49, 1, 0, 2178, 8 },
673
  { 528, 52, 1, 0, 2178, 8 },
674
  { 578, 55, 1, 0, 2178, 8 },
675
  { 635, 58, 1, 0, 2178, 8 },
676
  { 676, 61, 1, 0, 2178, 8 },
677
  { 0, 64, 1, 0, 2178, 8 },
678
  { 129, 67, 1, 0, 2178, 8 },
679
  { 215, 70, 1, 0, 2178, 8 },
680
  { 298, 73, 1, 0, 2178, 8 },
681
  { 360, 76, 1, 0, 2178, 8 },
682
  { 436, 79, 1, 0, 2178, 8 },
683
  { 333, 1, 275, 2, 3137, 3 },
684
  { 405, 1, 275, 2, 3137, 3 },
685
  { 470, 1, 273, 2, 3137, 3 },
686
  { 531, 1, 273, 2, 3137, 3 },
687
  { 581, 1, 271, 2, 3137, 3 },
688
  { 638, 1, 271, 2, 3137, 3 },
689
  { 679, 1, 269, 2, 3137, 3 },
690
  { 4, 1, 269, 2, 3137, 3 },
691
  { 133, 1, 267, 2, 3137, 3 },
692
  { 219, 1, 267, 2, 3137, 3 },
693
  { 302, 1, 265, 2, 3137, 3 },
694
  { 364, 1, 265, 2, 3137, 3 },
695
  { 440, 1, 263, 2, 3137, 3 },
696
  { 34, 1, 267, 2, 3137, 3 },
697
  { 149, 1, 265, 2, 3137, 3 },
698
  { 242, 1, 265, 2, 3137, 3 },
699
  { 318, 1, 263, 2, 3137, 3 },
700
  { 53, 1, 269, 2, 3137, 3 },
701
  { 161, 1, 267, 2, 3137, 3 },
702
  { 99, 1, 261, 2, 3137, 3 },
703
  { 200, 1, 259, 2, 3137, 3 },
704
  { 273, 1, 259, 2, 3137, 3 },
705
  { 345, 1, 257, 2, 3137, 3 },
706
  { 411, 1, 255, 2, 3137, 3 },
707
  { 476, 1, 253, 2, 3137, 3 },
708
  { 537, 1, 253, 2, 3137, 3 },
709
  { 587, 1, 251, 2, 3137, 3 },
710
  { 76, 1, 247, 2, 3137, 3 },
711
  { 177, 1, 247, 2, 3137, 3 },
712
  { 83, 1, 249, 2, 3137, 3 },
713
  { 184, 1, 247, 2, 3137, 3 },
714
  { 86, 1, 1, 2, 3137, 3 },
715
  { 187, 1, 1, 2, 3137, 3 },
716
  { 264, 1, 1, 2, 3137, 3 },
717
  { 336, 1, 1, 2, 3137, 3 },
718
  { 89, 1, 1, 2, 3137, 3 },
719
  { 190, 1, 1, 2, 3137, 3 },
720
  { 267, 1, 1, 2, 3137, 3 },
721
  { 339, 1, 1, 2, 3137, 3 },
722
  { 92, 1, 332, 2, 5121, 3 },
723
  { 193, 1, 330, 2, 5121, 3 },
724
  { 270, 1, 330, 2, 5121, 3 },
725
  { 342, 1, 328, 2, 5121, 3 },
726
  { 408, 1, 328, 2, 5121, 3 },
727
  { 473, 1, 326, 2, 5121, 3 },
728
  { 534, 1, 326, 2, 5121, 3 },
729
  { 584, 1, 324, 2, 5121, 3 },
730
  { 641, 1, 324, 2, 5121, 3 },
731
  { 682, 1, 322, 2, 5121, 3 },
732
  { 8, 1, 322, 2, 5121, 3 },
733
  { 137, 1, 320, 2, 5121, 3 },
734
  { 223, 1, 320, 2, 5121, 3 },
735
  { 306, 1, 318, 2, 5121, 3 },
736
  { 368, 1, 318, 2, 5121, 3 },
737
  { 444, 1, 316, 2, 5121, 3 },
738
  { 491, 1, 316, 2, 5121, 3 },
739
  { 562, 1, 314, 2, 5121, 3 },
740
  { 602, 1, 314, 2, 5121, 3 },
741
  { 660, 1, 312, 2, 5121, 3 },
742
  { 38, 1, 312, 2, 5121, 3 },
743
  { 153, 1, 310, 2, 5121, 3 },
744
  { 246, 1, 310, 2, 5121, 3 },
745
  { 322, 1, 308, 2, 5121, 3 },
746
  { 387, 1, 308, 2, 5121, 3 },
747
  { 456, 1, 306, 2, 5121, 3 },
748
  { 513, 1, 306, 2, 5121, 3 },
749
  { 570, 1, 304, 2, 5121, 3 },
750
  { 617, 1, 304, 2, 5121, 3 },
751
  { 668, 1, 302, 2, 5121, 3 },
752
  { 57, 1, 302, 2, 5121, 3 },
753
  { 165, 1, 300, 2, 5121, 3 },
754
  { 72, 1, 245, 2, 5457, 3 },
755
  { 173, 1, 245, 2, 5457, 3 },
756
  { 108, 1, 237, 2, 5457, 3 },
757
  { 209, 1, 235, 2, 5457, 3 },
758
  { 282, 1, 235, 2, 5457, 3 },
759
  { 354, 1, 233, 2, 5457, 3 },
760
  { 420, 1, 233, 2, 5457, 3 },
761
  { 485, 1, 231, 2, 5457, 3 },
762
  { 546, 1, 231, 2, 5457, 3 },
763
  { 596, 1, 229, 2, 5457, 3 },
764
  { 644, 1, 229, 2, 5457, 3 },
765
  { 685, 1, 227, 2, 5457, 3 },
766
  { 12, 1, 227, 2, 5457, 3 },
767
  { 141, 1, 225, 2, 5457, 3 },
768
  { 227, 1, 225, 2, 5457, 3 },
769
  { 310, 1, 223, 2, 5457, 3 },
770
  { 372, 1, 223, 2, 5457, 3 },
771
  { 448, 1, 221, 2, 5457, 3 },
772
  { 495, 1, 221, 2, 5457, 3 },
773
  { 566, 1, 219, 2, 5457, 3 },
774
  { 606, 1, 219, 2, 5457, 3 },
775
  { 664, 1, 217, 2, 5457, 3 },
776
  { 42, 1, 217, 2, 5457, 3 },
777
  { 157, 1, 215, 2, 5457, 3 },
778
  { 250, 1, 215, 2, 5457, 3 },
779
  { 326, 1, 213, 2, 5457, 3 },
780
  { 391, 1, 213, 2, 5457, 3 },
781
  { 460, 1, 211, 2, 5457, 3 },
782
  { 517, 1, 211, 2, 5457, 3 },
783
  { 574, 1, 209, 2, 5457, 3 },
784
  { 621, 1, 209, 2, 5457, 3 },
785
  { 672, 1, 207, 2, 5457, 3 },
786
  { 61, 1, 207, 2, 5457, 3 },
787
  { 169, 1, 205, 2, 5457, 3 },
788
  { 111, 139, 1, 5, 1602, 20 },
789
  { 212, 142, 1, 5, 1602, 20 },
790
  { 285, 145, 1, 5, 1602, 20 },
791
  { 357, 148, 1, 5, 1602, 20 },
792
  { 423, 151, 1, 5, 1602, 20 },
793
  { 488, 154, 1, 5, 1602, 20 },
794
  { 549, 157, 1, 5, 1602, 20 },
795
  { 599, 160, 1, 5, 1602, 20 },
796
  { 647, 163, 1, 5, 1602, 20 },
797
  { 688, 166, 1, 5, 1602, 20 },
798
  { 16, 169, 1, 5, 1602, 20 },
799
  { 145, 172, 1, 5, 1602, 20 },
800
  { 231, 175, 1, 5, 1602, 20 },
801
  { 314, 178, 1, 5, 1602, 20 },
802
  { 376, 181, 1, 5, 1602, 20 },
803
  { 452, 184, 1, 5, 1602, 20 },
804
  { 114, 334, 1, 0, 3169, 11 },
805
  { 288, 334, 1, 0, 3169, 11 },
806
  { 426, 297, 1, 0, 80, 14 },
807
  { 552, 133, 1, 0, 1360, 8 },
808
  { 650, 345, 1, 0, 3088, 11 },
809
  { 20, 348, 1, 0, 3040, 11 },
810
  { 499, 361, 1, 0, 1410, 11 },
811
  { 119, 187, 1, 0, 2993, 8 },
812
  { 293, 239, 1, 0, 3873, 8 },
813
  { 431, 103, 1, 0, 1506, 8 },
814
  { 557, 106, 1, 0, 1506, 8 },
815
  { 655, 109, 1, 0, 1506, 8 },
816
  { 27, 112, 1, 0, 1506, 8 },
817
  { 235, 115, 1, 0, 1506, 8 },
818
  { 380, 118, 1, 0, 1506, 8 },
819
  { 506, 127, 1, 0, 1554, 8 },
820
  { 610, 130, 1, 0, 1554, 8 },
821
  { 46, 115, 1, 0, 1458, 8 },
822
  { 254, 118, 1, 0, 1458, 8 },
823
  { 395, 358, 1, 0, 256, 11 },
824
  { 521, 121, 1, 0, 1458, 8 },
825
  { 625, 124, 1, 0, 1458, 8 },
826
  { 65, 112, 1, 0, 1312, 8 },
827
  { 124, 1, 343, 2, 176, 0 },
828
};
829
830
extern const MCPhysReg HexagonRegUnitRoots[][2] = {
831
  { Hexagon::CS0 },
832
  { Hexagon::CS1 },
833
  { Hexagon::FRAMEKEY },
834
  { Hexagon::FRAMELIMIT },
835
  { Hexagon::GELR },
836
  { Hexagon::GOSP },
837
  { Hexagon::GP },
838
  { Hexagon::GPCYCLEHI },
839
  { Hexagon::GPCYCLELO },
840
  { Hexagon::GSR },
841
  { Hexagon::PC },
842
  { Hexagon::PKTCOUNTLO },
843
  { Hexagon::PKTCOUNTHI },
844
  { Hexagon::UGP },
845
  { Hexagon::UPCYCLELO },
846
  { Hexagon::UPCYCLEHI },
847
  { Hexagon::USR_OVF },
848
  { Hexagon::USR, Hexagon::C8 },
849
  { Hexagon::UTIMERLO },
850
  { Hexagon::UTIMERHI },
851
  { Hexagon::VTMP },
852
  { Hexagon::C5 },
853
  { Hexagon::R0 },
854
  { Hexagon::R1 },
855
  { Hexagon::R2 },
856
  { Hexagon::R3 },
857
  { Hexagon::R4 },
858
  { Hexagon::R5 },
859
  { Hexagon::R6 },
860
  { Hexagon::R7 },
861
  { Hexagon::R8 },
862
  { Hexagon::R9 },
863
  { Hexagon::R10 },
864
  { Hexagon::R11 },
865
  { Hexagon::R12 },
866
  { Hexagon::R13 },
867
  { Hexagon::R14 },
868
  { Hexagon::R15 },
869
  { Hexagon::R16 },
870
  { Hexagon::R17 },
871
  { Hexagon::R18 },
872
  { Hexagon::R19 },
873
  { Hexagon::R20 },
874
  { Hexagon::R21 },
875
  { Hexagon::R22 },
876
  { Hexagon::R23 },
877
  { Hexagon::R24 },
878
  { Hexagon::R25 },
879
  { Hexagon::R26 },
880
  { Hexagon::R27 },
881
  { Hexagon::R28 },
882
  { Hexagon::R29 },
883
  { Hexagon::R30 },
884
  { Hexagon::R31 },
885
  { Hexagon::G3 },
886
  { Hexagon::G4 },
887
  { Hexagon::G5 },
888
  { Hexagon::G6 },
889
  { Hexagon::G7 },
890
  { Hexagon::G8 },
891
  { Hexagon::G9 },
892
  { Hexagon::G10 },
893
  { Hexagon::G11 },
894
  { Hexagon::G12 },
895
  { Hexagon::G13 },
896
  { Hexagon::G14 },
897
  { Hexagon::G15 },
898
  { Hexagon::G20 },
899
  { Hexagon::G21 },
900
  { Hexagon::G22 },
901
  { Hexagon::G23 },
902
  { Hexagon::G30 },
903
  { Hexagon::G31 },
904
  { Hexagon::GPMUCNT0 },
905
  { Hexagon::GPMUCNT1 },
906
  { Hexagon::GPMUCNT2 },
907
  { Hexagon::GPMUCNT3 },
908
  { Hexagon::GPMUCNT4 },
909
  { Hexagon::GPMUCNT5 },
910
  { Hexagon::GPMUCNT6 },
911
  { Hexagon::GPMUCNT7 },
912
  { Hexagon::LC0 },
913
  { Hexagon::LC1 },
914
  { Hexagon::M0 },
915
  { Hexagon::M1 },
916
  { Hexagon::P0, Hexagon::P3_0 },
917
  { Hexagon::P1, Hexagon::P3_0 },
918
  { Hexagon::P2, Hexagon::P3_0 },
919
  { Hexagon::P3, Hexagon::P3_0 },
920
  { Hexagon::Q0 },
921
  { Hexagon::Q1 },
922
  { Hexagon::Q2 },
923
  { Hexagon::Q3 },
924
  { Hexagon::SA0 },
925
  { Hexagon::SA1 },
926
  { Hexagon::V0 },
927
  { Hexagon::V1 },
928
  { Hexagon::V2 },
929
  { Hexagon::V3 },
930
  { Hexagon::V4 },
931
  { Hexagon::V5 },
932
  { Hexagon::V6 },
933
  { Hexagon::V7 },
934
  { Hexagon::V8 },
935
  { Hexagon::V9 },
936
  { Hexagon::V10 },
937
  { Hexagon::V11 },
938
  { Hexagon::V12 },
939
  { Hexagon::V13 },
940
  { Hexagon::V14 },
941
  { Hexagon::V15 },
942
  { Hexagon::V16 },
943
  { Hexagon::V17 },
944
  { Hexagon::V18 },
945
  { Hexagon::V19 },
946
  { Hexagon::V20 },
947
  { Hexagon::V21 },
948
  { Hexagon::V22 },
949
  { Hexagon::V23 },
950
  { Hexagon::V24 },
951
  { Hexagon::V25 },
952
  { Hexagon::V26 },
953
  { Hexagon::V27 },
954
  { Hexagon::V28 },
955
  { Hexagon::V29 },
956
  { Hexagon::V30 },
957
  { Hexagon::V31 },
958
};
959
960
namespace {     // Register classes...
961
  // UsrBits Register Class...
962
  const MCPhysReg UsrBits[] = {
963
    Hexagon::USR_OVF, 
964
  };
965
966
  // UsrBits Bit set.
967
  const uint8_t UsrBitsBits[] = {
968
    0x00, 0x00, 0x08, 
969
  };
970
971
  // GuestRegs Register Class...
972
  const MCPhysReg GuestRegs[] = {
973
    Hexagon::GELR, Hexagon::GSR, Hexagon::GOSP, Hexagon::G3, Hexagon::G4, Hexagon::G5, Hexagon::G6, Hexagon::G7, Hexagon::G8, Hexagon::G9, Hexagon::G10, Hexagon::G11, Hexagon::G12, Hexagon::G13, Hexagon::G14, Hexagon::G15, Hexagon::GPMUCNT4, Hexagon::GPMUCNT5, Hexagon::GPMUCNT6, Hexagon::GPMUCNT7, Hexagon::G20, Hexagon::G21, Hexagon::G22, Hexagon::G23, Hexagon::GPCYCLELO, Hexagon::GPCYCLEHI, Hexagon::GPMUCNT0, Hexagon::GPMUCNT1, Hexagon::GPMUCNT2, Hexagon::GPMUCNT3, Hexagon::G30, Hexagon::G31, 
974
  };
975
976
  // GuestRegs Bit set.
977
  const uint8_t GuestRegsBits[] = {
978
    0xb0, 0x03, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0x7f, 
979
  };
980
981
  // IntRegs Register Class...
982
  const MCPhysReg IntRegs[] = {
983
    Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, Hexagon::R12, Hexagon::R13, Hexagon::R14, Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R10, Hexagon::R11, Hexagon::R29, Hexagon::R30, Hexagon::R31, 
984
  };
985
986
  // IntRegs Bit set.
987
  const uint8_t IntRegsBits[] = {
988
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
989
  };
990
991
  // CtrRegs Register Class...
992
  const MCPhysReg CtrRegs[] = {
993
    Hexagon::LC0, Hexagon::SA0, Hexagon::LC1, Hexagon::SA1, Hexagon::P3_0, Hexagon::C5, Hexagon::C8, Hexagon::PC, Hexagon::UGP, Hexagon::GP, Hexagon::CS0, Hexagon::CS1, Hexagon::UPCYCLELO, Hexagon::UPCYCLEHI, Hexagon::FRAMELIMIT, Hexagon::FRAMEKEY, Hexagon::PKTCOUNTLO, Hexagon::PKTCOUNTHI, Hexagon::UTIMERLO, Hexagon::UTIMERHI, Hexagon::M0, Hexagon::M1, Hexagon::USR, 
994
  };
995
996
  // CtrRegs Bit set.
997
  const uint8_t CtrRegsBits[] = {
998
    0x4c, 0x74, 0x67, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 
999
  };
1000
1001
  // GeneralSubRegs Register Class...
1002
  const MCPhysReg GeneralSubRegs[] = {
1003
    Hexagon::R23, Hexagon::R22, Hexagon::R21, Hexagon::R20, Hexagon::R19, Hexagon::R18, Hexagon::R17, Hexagon::R16, Hexagon::R7, Hexagon::R6, Hexagon::R5, Hexagon::R4, Hexagon::R3, Hexagon::R2, Hexagon::R1, Hexagon::R0, 
1004
  };
1005
1006
  // GeneralSubRegs Bit set.
1007
  const uint8_t GeneralSubRegsBits[] = {
1008
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 0xf8, 0x07, 
1009
  };
1010
1011
  // V62Regs Register Class...
1012
  const MCPhysReg V62Regs[] = {
1013
    Hexagon::FRAMELIMIT, Hexagon::FRAMEKEY, Hexagon::C17_16, Hexagon::PKTCOUNTLO, Hexagon::PKTCOUNTHI, Hexagon::PKTCOUNT, Hexagon::UTIMERLO, Hexagon::UTIMERHI, Hexagon::UTIMER, 
1014
  };
1015
1016
  // V62Regs Bit set.
1017
  const uint8_t V62RegsBits[] = {
1018
    0x0c, 0x38, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 
1019
  };
1020
1021
  // IntRegsLow8 Register Class...
1022
  const MCPhysReg IntRegsLow8[] = {
1023
    Hexagon::R7, Hexagon::R6, Hexagon::R5, Hexagon::R4, Hexagon::R3, Hexagon::R2, Hexagon::R1, Hexagon::R0, 
1024
  };
1025
1026
  // IntRegsLow8 Bit set.
1027
  const uint8_t IntRegsLow8Bits[] = {
1028
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 
1029
  };
1030
1031
  // CtrRegs_and_V62Regs Register Class...
1032
  const MCPhysReg CtrRegs_and_V62Regs[] = {
1033
    Hexagon::FRAMELIMIT, Hexagon::FRAMEKEY, Hexagon::PKTCOUNTLO, Hexagon::PKTCOUNTHI, Hexagon::UTIMERLO, Hexagon::UTIMERHI, 
1034
  };
1035
1036
  // CtrRegs_and_V62Regs Bit set.
1037
  const uint8_t CtrRegs_and_V62RegsBits[] = {
1038
    0x0c, 0x30, 0x60, 
1039
  };
1040
1041
  // PredRegs Register Class...
1042
  const MCPhysReg PredRegs[] = {
1043
    Hexagon::P0, Hexagon::P1, Hexagon::P2, Hexagon::P3, 
1044
  };
1045
1046
  // PredRegs Bit set.
1047
  const uint8_t PredRegsBits[] = {
1048
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 
1049
  };
1050
1051
  // V62Regs_with_isub_hi Register Class...
1052
  const MCPhysReg V62Regs_with_isub_hi[] = {
1053
    Hexagon::C17_16, Hexagon::PKTCOUNT, Hexagon::UTIMER, 
1054
  };
1055
1056
  // V62Regs_with_isub_hi Bit set.
1057
  const uint8_t V62Regs_with_isub_hiBits[] = {
1058
    0x00, 0x08, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 
1059
  };
1060
1061
  // ModRegs Register Class...
1062
  const MCPhysReg ModRegs[] = {
1063
    Hexagon::M0, Hexagon::M1, 
1064
  };
1065
1066
  // ModRegs Bit set.
1067
  const uint8_t ModRegsBits[] = {
1068
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 
1069
  };
1070
1071
  // CtrRegs_with_subreg_overflow Register Class...
1072
  const MCPhysReg CtrRegs_with_subreg_overflow[] = {
1073
    Hexagon::USR, 
1074
  };
1075
1076
  // CtrRegs_with_subreg_overflow Bit set.
1077
  const uint8_t CtrRegs_with_subreg_overflowBits[] = {
1078
    0x00, 0x00, 0x04, 
1079
  };
1080
1081
  // V65Regs Register Class...
1082
  const MCPhysReg V65Regs[] = {
1083
    Hexagon::VTMP, 
1084
  };
1085
1086
  // V65Regs Bit set.
1087
  const uint8_t V65RegsBits[] = {
1088
    0x00, 0x00, 0x80, 
1089
  };
1090
1091
  // DoubleRegs Register Class...
1092
  const MCPhysReg DoubleRegs[] = {
1093
    Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, Hexagon::D4, Hexagon::D6, Hexagon::D7, Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, Hexagon::D12, Hexagon::D13, Hexagon::D5, Hexagon::D14, Hexagon::D15, 
1094
  };
1095
1096
  // DoubleRegs Bit set.
1097
  const uint8_t DoubleRegsBits[] = {
1098
    0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, 
1099
  };
1100
1101
  // GuestRegs64 Register Class...
1102
  const MCPhysReg GuestRegs64[] = {
1103
    Hexagon::G1_0, Hexagon::G3_2, Hexagon::G5_4, Hexagon::G7_6, Hexagon::G9_8, Hexagon::G11_10, Hexagon::G13_12, Hexagon::G15_14, Hexagon::G17_16, Hexagon::G19_18, Hexagon::G21_20, Hexagon::G23_22, Hexagon::G25_24, Hexagon::G27_26, Hexagon::G29_28, Hexagon::G31_30, 
1104
  };
1105
1106
  // GuestRegs64 Bit set.
1107
  const uint8_t GuestRegs64Bits[] = {
1108
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, 
1109
  };
1110
1111
  // CtrRegs64 Register Class...
1112
  const MCPhysReg CtrRegs64[] = {
1113
    Hexagon::C1_0, Hexagon::C3_2, Hexagon::C5_4, Hexagon::C7_6, Hexagon::C9_8, Hexagon::C11_10, Hexagon::CS, Hexagon::UPCYCLE, Hexagon::C17_16, Hexagon::PKTCOUNT, Hexagon::UTIMER, 
1114
  };
1115
1116
  // CtrRegs64 Bit set.
1117
  const uint8_t CtrRegs64Bits[] = {
1118
    0x02, 0x88, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
1119
  };
1120
1121
  // GeneralDoubleLow8Regs Register Class...
1122
  const MCPhysReg GeneralDoubleLow8Regs[] = {
1123
    Hexagon::D11, Hexagon::D10, Hexagon::D9, Hexagon::D8, Hexagon::D3, Hexagon::D2, Hexagon::D1, Hexagon::D0, 
1124
  };
1125
1126
  // GeneralDoubleLow8Regs Bit set.
1127
  const uint8_t GeneralDoubleLow8RegsBits[] = {
1128
    0x00, 0x00, 0x00, 0xf0, 0xf0, 
1129
  };
1130
1131
  // DoubleRegs_with_isub_hi_in_IntRegsLow8 Register Class...
1132
  const MCPhysReg DoubleRegs_with_isub_hi_in_IntRegsLow8[] = {
1133
    Hexagon::D3, Hexagon::D2, Hexagon::D1, Hexagon::D0, 
1134
  };
1135
1136
  // DoubleRegs_with_isub_hi_in_IntRegsLow8 Bit set.
1137
  const uint8_t DoubleRegs_with_isub_hi_in_IntRegsLow8Bits[] = {
1138
    0x00, 0x00, 0x00, 0xf0, 
1139
  };
1140
1141
  // CtrRegs64_and_V62Regs Register Class...
1142
  const MCPhysReg CtrRegs64_and_V62Regs[] = {
1143
    Hexagon::C17_16, Hexagon::PKTCOUNT, Hexagon::UTIMER, 
1144
  };
1145
1146
  // CtrRegs64_and_V62Regs Bit set.
1147
  const uint8_t CtrRegs64_and_V62RegsBits[] = {
1148
    0x00, 0x08, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 
1149
  };
1150
1151
  // CtrRegs64_with_isub_hi_in_ModRegs Register Class...
1152
  const MCPhysReg CtrRegs64_with_isub_hi_in_ModRegs[] = {
1153
    Hexagon::C7_6, 
1154
  };
1155
1156
  // CtrRegs64_with_isub_hi_in_ModRegs Bit set.
1157
  const uint8_t CtrRegs64_with_isub_hi_in_ModRegsBits[] = {
1158
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 
1159
  };
1160
1161
  // HvxVR Register Class...
1162
  const MCPhysReg HvxVR[] = {
1163
    Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19, Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24, Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, Hexagon::V30, Hexagon::V31, Hexagon::VTMP, 
1164
  };
1165
1166
  // HvxVR Bit set.
1167
  const uint8_t HvxVRBits[] = {
1168
    0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
1169
  };
1170
1171
  // HvxQR Register Class...
1172
  const MCPhysReg HvxQR[] = {
1173
    Hexagon::Q0, Hexagon::Q1, Hexagon::Q2, Hexagon::Q3, 
1174
  };
1175
1176
  // HvxQR Bit set.
1177
  const uint8_t HvxQRBits[] = {
1178
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 
1179
  };
1180
1181
  // HvxVR_and_V65Regs Register Class...
1182
  const MCPhysReg HvxVR_and_V65Regs[] = {
1183
    Hexagon::VTMP, 
1184
  };
1185
1186
  // HvxVR_and_V65Regs Bit set.
1187
  const uint8_t HvxVR_and_V65RegsBits[] = {
1188
    0x00, 0x00, 0x80, 
1189
  };
1190
1191
  // HvxWR Register Class...
1192
  const MCPhysReg HvxWR[] = {
1193
    Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7, Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11, Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15, 
1194
  };
1195
1196
  // HvxWR Bit set.
1197
  const uint8_t HvxWRBits[] = {
1198
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
1199
  };
1200
1201
} // end anonymous namespace
1202
1203
extern const char HexagonRegClassStrings[] = {
1204
  /* 0 */ 'C', 't', 'r', 'R', 'e', 'g', 's', '6', '4', 0,
1205
  /* 10 */ 'G', 'u', 'e', 's', 't', 'R', 'e', 'g', 's', '6', '4', 0,
1206
  /* 22 */ 'D', 'o', 'u', 'b', 'l', 'e', 'R', 'e', 'g', 's', '_', 'w', 'i', 't', 'h', '_', 'i', 's', 'u', 'b', '_', 'h', 'i', '_', 'i', 'n', '_', 'I', 'n', 't', 'R', 'e', 'g', 's', 'L', 'o', 'w', '8', 0,
1207
  /* 61 */ 'H', 'v', 'x', 'Q', 'R', 0,
1208
  /* 67 */ 'H', 'v', 'x', 'V', 'R', 0,
1209
  /* 73 */ 'H', 'v', 'x', 'W', 'R', 0,
1210
  /* 79 */ 'V', '6', '2', 'R', 'e', 'g', 's', '_', 'w', 'i', 't', 'h', '_', 'i', 's', 'u', 'b', '_', 'h', 'i', 0,
1211
  /* 100 */ 'C', 't', 'r', 'R', 'e', 'g', 's', '6', '4', '_', 'a', 'n', 'd', '_', 'V', '6', '2', 'R', 'e', 'g', 's', 0,
1212
  /* 122 */ 'C', 't', 'r', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'V', '6', '2', 'R', 'e', 'g', 's', 0,
1213
  /* 142 */ 'H', 'v', 'x', 'V', 'R', '_', 'a', 'n', 'd', '_', 'V', '6', '5', 'R', 'e', 'g', 's', 0,
1214
  /* 160 */ 'G', 'e', 'n', 'e', 'r', 'a', 'l', 'D', 'o', 'u', 'b', 'l', 'e', 'L', 'o', 'w', '8', 'R', 'e', 'g', 's', 0,
1215
  /* 182 */ 'G', 'e', 'n', 'e', 'r', 'a', 'l', 'S', 'u', 'b', 'R', 'e', 'g', 's', 0,
1216
  /* 197 */ 'P', 'r', 'e', 'd', 'R', 'e', 'g', 's', 0,
1217
  /* 206 */ 'C', 't', 'r', 'R', 'e', 'g', 's', '6', '4', '_', 'w', 'i', 't', 'h', '_', 'i', 's', 'u', 'b', '_', 'h', 'i', '_', 'i', 'n', '_', 'M', 'o', 'd', 'R', 'e', 'g', 's', 0,
1218
  /* 240 */ 'D', 'o', 'u', 'b', 'l', 'e', 'R', 'e', 'g', 's', 0,
1219
  /* 251 */ 'C', 't', 'r', 'R', 'e', 'g', 's', 0,
1220
  /* 259 */ 'I', 'n', 't', 'R', 'e', 'g', 's', 0,
1221
  /* 267 */ 'G', 'u', 'e', 's', 't', 'R', 'e', 'g', 's', 0,
1222
  /* 277 */ 'U', 's', 'r', 'B', 'i', 't', 's', 0,
1223
  /* 285 */ 'C', 't', 'r', 'R', 'e', 'g', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'r', 'e', 'g', '_', 'o', 'v', 'e', 'r', 'f', 'l', 'o', 'w', 0,
1224
};
1225
1226
extern const MCRegisterClass HexagonMCRegisterClasses[] = {
1227
  { UsrBits, UsrBitsBits, 277, 1, sizeof(UsrBitsBits), Hexagon::UsrBitsRegClassID, 1, false },
1228
  { GuestRegs, GuestRegsBits, 267, 32, sizeof(GuestRegsBits), Hexagon::GuestRegsRegClassID, 1, false },
1229
  { IntRegs, IntRegsBits, 259, 32, sizeof(IntRegsBits), Hexagon::IntRegsRegClassID, 1, true },
1230
  { CtrRegs, CtrRegsBits, 251, 23, sizeof(CtrRegsBits), Hexagon::CtrRegsRegClassID, 1, false },
1231
  { GeneralSubRegs, GeneralSubRegsBits, 182, 16, sizeof(GeneralSubRegsBits), Hexagon::GeneralSubRegsRegClassID, 1, true },
1232
  { V62Regs, V62RegsBits, 114, 9, sizeof(V62RegsBits), Hexagon::V62RegsRegClassID, 1, false },
1233
  { IntRegsLow8, IntRegsLow8Bits, 49, 8, sizeof(IntRegsLow8Bits), Hexagon::IntRegsLow8RegClassID, 1, true },
1234
  { CtrRegs_and_V62Regs, CtrRegs_and_V62RegsBits, 122, 6, sizeof(CtrRegs_and_V62RegsBits), Hexagon::CtrRegs_and_V62RegsRegClassID, 1, false },
1235
  { PredRegs, PredRegsBits, 197, 4, sizeof(PredRegsBits), Hexagon::PredRegsRegClassID, 1, true },
1236
  { V62Regs_with_isub_hi, V62Regs_with_isub_hiBits, 79, 3, sizeof(V62Regs_with_isub_hiBits), Hexagon::V62Regs_with_isub_hiRegClassID, 1, false },
1237
  { ModRegs, ModRegsBits, 232, 2, sizeof(ModRegsBits), Hexagon::ModRegsRegClassID, 1, true },
1238
  { CtrRegs_with_subreg_overflow, CtrRegs_with_subreg_overflowBits, 285, 1, sizeof(CtrRegs_with_subreg_overflowBits), Hexagon::CtrRegs_with_subreg_overflowRegClassID, 1, false },
1239
  { V65Regs, V65RegsBits, 152, 1, sizeof(V65RegsBits), Hexagon::V65RegsRegClassID, 1, false },
1240
  { DoubleRegs, DoubleRegsBits, 240, 16, sizeof(DoubleRegsBits), Hexagon::DoubleRegsRegClassID, 1, true },
1241
  { GuestRegs64, GuestRegs64Bits, 10, 16, sizeof(GuestRegs64Bits), Hexagon::GuestRegs64RegClassID, 1, false },
1242
  { CtrRegs64, CtrRegs64Bits, 0, 11, sizeof(CtrRegs64Bits), Hexagon::CtrRegs64RegClassID, 1, false },
1243
  { GeneralDoubleLow8Regs, GeneralDoubleLow8RegsBits, 160, 8, sizeof(GeneralDoubleLow8RegsBits), Hexagon::GeneralDoubleLow8RegsRegClassID, 1, true },
1244
  { DoubleRegs_with_isub_hi_in_IntRegsLow8, DoubleRegs_with_isub_hi_in_IntRegsLow8Bits, 22, 4, sizeof(DoubleRegs_with_isub_hi_in_IntRegsLow8Bits), Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID, 1, true },
1245
  { CtrRegs64_and_V62Regs, CtrRegs64_and_V62RegsBits, 100, 3, sizeof(CtrRegs64_and_V62RegsBits), Hexagon::CtrRegs64_and_V62RegsRegClassID, 1, false },
1246
  { CtrRegs64_with_isub_hi_in_ModRegs, CtrRegs64_with_isub_hi_in_ModRegsBits, 206, 1, sizeof(CtrRegs64_with_isub_hi_in_ModRegsBits), Hexagon::CtrRegs64_with_isub_hi_in_ModRegsRegClassID, 1, false },
1247
  { HvxVR, HvxVRBits, 67, 33, sizeof(HvxVRBits), Hexagon::HvxVRRegClassID, 1, true },
1248
  { HvxQR, HvxQRBits, 61, 4, sizeof(HvxQRBits), Hexagon::HvxQRRegClassID, 1, true },
1249
  { HvxVR_and_V65Regs, HvxVR_and_V65RegsBits, 142, 1, sizeof(HvxVR_and_V65RegsBits), Hexagon::HvxVR_and_V65RegsRegClassID, 1, true },
1250
  { HvxWR, HvxWRBits, 73, 16, sizeof(HvxWRBits), Hexagon::HvxWRRegClassID, 1, true },
1251
};
1252
1253
// Hexagon Dwarf<->LLVM register mappings.
1254
extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0Dwarf2L[] = {
1255
  { 0U, Hexagon::R0 },
1256
  { 1U, Hexagon::R1 },
1257
  { 2U, Hexagon::R2 },
1258
  { 3U, Hexagon::R3 },
1259
  { 4U, Hexagon::R4 },
1260
  { 5U, Hexagon::R5 },
1261
  { 6U, Hexagon::R6 },
1262
  { 7U, Hexagon::R7 },
1263
  { 8U, Hexagon::R8 },
1264
  { 9U, Hexagon::R9 },
1265
  { 10U, Hexagon::R10 },
1266
  { 11U, Hexagon::R11 },
1267
  { 12U, Hexagon::R12 },
1268
  { 13U, Hexagon::R13 },
1269
  { 14U, Hexagon::R14 },
1270
  { 15U, Hexagon::R15 },
1271
  { 16U, Hexagon::R16 },
1272
  { 17U, Hexagon::R17 },
1273
  { 18U, Hexagon::R18 },
1274
  { 19U, Hexagon::R19 },
1275
  { 20U, Hexagon::R20 },
1276
  { 21U, Hexagon::R21 },
1277
  { 22U, Hexagon::R22 },
1278
  { 23U, Hexagon::R23 },
1279
  { 24U, Hexagon::R24 },
1280
  { 25U, Hexagon::R25 },
1281
  { 26U, Hexagon::R26 },
1282
  { 27U, Hexagon::R27 },
1283
  { 28U, Hexagon::R28 },
1284
  { 29U, Hexagon::R29 },
1285
  { 30U, Hexagon::R30 },
1286
  { 31U, Hexagon::R31 },
1287
  { 32U, Hexagon::D0 },
1288
  { 34U, Hexagon::D1 },
1289
  { 36U, Hexagon::D2 },
1290
  { 38U, Hexagon::D3 },
1291
  { 40U, Hexagon::D4 },
1292
  { 42U, Hexagon::D5 },
1293
  { 44U, Hexagon::D6 },
1294
  { 46U, Hexagon::D7 },
1295
  { 48U, Hexagon::D8 },
1296
  { 50U, Hexagon::D9 },
1297
  { 52U, Hexagon::D10 },
1298
  { 54U, Hexagon::D11 },
1299
  { 56U, Hexagon::D12 },
1300
  { 58U, Hexagon::D13 },
1301
  { 60U, Hexagon::D14 },
1302
  { 62U, Hexagon::D15 },
1303
  { 63U, Hexagon::P0 },
1304
  { 64U, Hexagon::P1 },
1305
  { 65U, Hexagon::P2 },
1306
  { 66U, Hexagon::P3 },
1307
  { 67U, Hexagon::C1_0 },
1308
  { 68U, Hexagon::LC0 },
1309
  { 69U, Hexagon::C3_2 },
1310
  { 70U, Hexagon::LC1 },
1311
  { 71U, Hexagon::P3_0 },
1312
  { 72U, Hexagon::C7_6 },
1313
  { 73U, Hexagon::M0 },
1314
  { 74U, Hexagon::C9_8 },
1315
  { 75U, Hexagon::C8 },
1316
  { 76U, Hexagon::C11_10 },
1317
  { 77U, Hexagon::UGP },
1318
  { 78U, Hexagon::GP },
1319
  { 79U, Hexagon::CS0 },
1320
  { 80U, Hexagon::CS1 },
1321
  { 81U, Hexagon::UPCYCLELO },
1322
  { 82U, Hexagon::UPCYCLEHI },
1323
  { 83U, Hexagon::C17_16 },
1324
  { 84U, Hexagon::FRAMEKEY },
1325
  { 85U, Hexagon::PKTCOUNTLO },
1326
  { 86U, Hexagon::PKTCOUNTHI },
1327
  { 97U, Hexagon::UTIMERLO },
1328
  { 98U, Hexagon::UTIMERHI },
1329
  { 99U, Hexagon::W0 },
1330
  { 100U, Hexagon::V1 },
1331
  { 101U, Hexagon::W1 },
1332
  { 102U, Hexagon::V3 },
1333
  { 103U, Hexagon::W2 },
1334
  { 104U, Hexagon::V5 },
1335
  { 105U, Hexagon::W3 },
1336
  { 106U, Hexagon::V7 },
1337
  { 107U, Hexagon::W4 },
1338
  { 108U, Hexagon::V9 },
1339
  { 109U, Hexagon::W5 },
1340
  { 110U, Hexagon::V11 },
1341
  { 111U, Hexagon::W6 },
1342
  { 112U, Hexagon::V13 },
1343
  { 113U, Hexagon::W7 },
1344
  { 114U, Hexagon::V15 },
1345
  { 115U, Hexagon::W8 },
1346
  { 116U, Hexagon::V17 },
1347
  { 117U, Hexagon::W9 },
1348
  { 118U, Hexagon::V19 },
1349
  { 119U, Hexagon::W10 },
1350
  { 120U, Hexagon::V21 },
1351
  { 121U, Hexagon::W11 },
1352
  { 122U, Hexagon::V23 },
1353
  { 123U, Hexagon::W12 },
1354
  { 124U, Hexagon::V25 },
1355
  { 125U, Hexagon::W13 },
1356
  { 126U, Hexagon::V27 },
1357
  { 127U, Hexagon::W14 },
1358
  { 128U, Hexagon::V29 },
1359
  { 129U, Hexagon::W15 },
1360
  { 130U, Hexagon::V31 },
1361
  { 131U, Hexagon::Q0 },
1362
  { 132U, Hexagon::Q1 },
1363
  { 133U, Hexagon::Q2 },
1364
  { 134U, Hexagon::Q3 },
1365
  { 220U, Hexagon::G1_0 },
1366
  { 221U, Hexagon::GSR },
1367
  { 222U, Hexagon::G3_2 },
1368
  { 223U, Hexagon::G3 },
1369
  { 224U, Hexagon::G5_4 },
1370
  { 225U, Hexagon::G5 },
1371
  { 226U, Hexagon::G7_6 },
1372
  { 227U, Hexagon::G7 },
1373
  { 228U, Hexagon::G9_8 },
1374
  { 229U, Hexagon::G9 },
1375
  { 230U, Hexagon::G11_10 },
1376
  { 231U, Hexagon::G11 },
1377
  { 232U, Hexagon::G13_12 },
1378
  { 233U, Hexagon::G13 },
1379
  { 234U, Hexagon::G15_14 },
1380
  { 235U, Hexagon::G15 },
1381
  { 236U, Hexagon::G17_16 },
1382
  { 237U, Hexagon::GPMUCNT5 },
1383
  { 238U, Hexagon::G19_18 },
1384
  { 239U, Hexagon::GPMUCNT7 },
1385
  { 240U, Hexagon::G21_20 },
1386
  { 241U, Hexagon::G21 },
1387
  { 242U, Hexagon::G23_22 },
1388
  { 243U, Hexagon::G23 },
1389
  { 244U, Hexagon::G25_24 },
1390
  { 245U, Hexagon::GPCYCLEHI },
1391
  { 246U, Hexagon::G27_26 },
1392
  { 247U, Hexagon::GPMUCNT1 },
1393
  { 248U, Hexagon::G29_28 },
1394
  { 249U, Hexagon::GPMUCNT3 },
1395
  { 250U, Hexagon::G31_30 },
1396
  { 251U, Hexagon::G31 },
1397
};
1398
extern const unsigned HexagonDwarfFlavour0Dwarf2LSize = array_lengthof(HexagonDwarfFlavour0Dwarf2L);
1399
1400
extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0Dwarf2L[] = {
1401
  { 0U, Hexagon::R0 },
1402
  { 1U, Hexagon::R1 },
1403
  { 2U, Hexagon::R2 },
1404
  { 3U, Hexagon::R3 },
1405
  { 4U, Hexagon::R4 },
1406
  { 5U, Hexagon::R5 },
1407
  { 6U, Hexagon::R6 },
1408
  { 7U, Hexagon::R7 },
1409
  { 8U, Hexagon::R8 },
1410
  { 9U, Hexagon::R9 },
1411
  { 10U, Hexagon::R10 },
1412
  { 11U, Hexagon::R11 },
1413
  { 12U, Hexagon::R12 },
1414
  { 13U, Hexagon::R13 },
1415
  { 14U, Hexagon::R14 },
1416
  { 15U, Hexagon::R15 },
1417
  { 16U, Hexagon::R16 },
1418
  { 17U, Hexagon::R17 },
1419
  { 18U, Hexagon::R18 },
1420
  { 19U, Hexagon::R19 },
1421
  { 20U, Hexagon::R20 },
1422
  { 21U, Hexagon::R21 },
1423
  { 22U, Hexagon::R22 },
1424
  { 23U, Hexagon::R23 },
1425
  { 24U, Hexagon::R24 },
1426
  { 25U, Hexagon::R25 },
1427
  { 26U, Hexagon::R26 },
1428
  { 27U, Hexagon::R27 },
1429
  { 28U, Hexagon::R28 },
1430
  { 29U, Hexagon::R29 },
1431
  { 30U, Hexagon::R30 },
1432
  { 31U, Hexagon::R31 },
1433
  { 32U, Hexagon::D0 },
1434
  { 34U, Hexagon::D1 },
1435
  { 36U, Hexagon::D2 },
1436
  { 38U, Hexagon::D3 },
1437
  { 40U, Hexagon::D4 },
1438
  { 42U, Hexagon::D5 },
1439
  { 44U, Hexagon::D6 },
1440
  { 46U, Hexagon::D7 },
1441
  { 48U, Hexagon::D8 },
1442
  { 50U, Hexagon::D9 },
1443
  { 52U, Hexagon::D10 },
1444
  { 54U, Hexagon::D11 },
1445
  { 56U, Hexagon::D12 },
1446
  { 58U, Hexagon::D13 },
1447
  { 60U, Hexagon::D14 },
1448
  { 62U, Hexagon::D15 },
1449
  { 63U, Hexagon::P0 },
1450
  { 64U, Hexagon::P1 },
1451
  { 65U, Hexagon::P2 },
1452
  { 66U, Hexagon::P3 },
1453
  { 67U, Hexagon::C1_0 },
1454
  { 68U, Hexagon::LC0 },
1455
  { 69U, Hexagon::C3_2 },
1456
  { 70U, Hexagon::LC1 },
1457
  { 71U, Hexagon::P3_0 },
1458
  { 72U, Hexagon::C7_6 },
1459
  { 73U, Hexagon::M0 },
1460
  { 74U, Hexagon::C9_8 },
1461
  { 75U, Hexagon::C8 },
1462
  { 76U, Hexagon::C11_10 },
1463
  { 77U, Hexagon::UGP },
1464
  { 78U, Hexagon::GP },
1465
  { 79U, Hexagon::CS0 },
1466
  { 80U, Hexagon::CS1 },
1467
  { 81U, Hexagon::UPCYCLELO },
1468
  { 82U, Hexagon::UPCYCLEHI },
1469
  { 83U, Hexagon::C17_16 },
1470
  { 84U, Hexagon::FRAMEKEY },
1471
  { 85U, Hexagon::PKTCOUNTLO },
1472
  { 86U, Hexagon::PKTCOUNTHI },
1473
  { 97U, Hexagon::UTIMERLO },
1474
  { 98U, Hexagon::UTIMERHI },
1475
  { 99U, Hexagon::W0 },
1476
  { 100U, Hexagon::V1 },
1477
  { 101U, Hexagon::W1 },
1478
  { 102U, Hexagon::V3 },
1479
  { 103U, Hexagon::W2 },
1480
  { 104U, Hexagon::V5 },
1481
  { 105U, Hexagon::W3 },
1482
  { 106U, Hexagon::V7 },
1483
  { 107U, Hexagon::W4 },
1484
  { 108U, Hexagon::V9 },
1485
  { 109U, Hexagon::W5 },
1486
  { 110U, Hexagon::V11 },
1487
  { 111U, Hexagon::W6 },
1488
  { 112U, Hexagon::V13 },
1489
  { 113U, Hexagon::W7 },
1490
  { 114U, Hexagon::V15 },
1491
  { 115U, Hexagon::W8 },
1492
  { 116U, Hexagon::V17 },
1493
  { 117U, Hexagon::W9 },
1494
  { 118U, Hexagon::V19 },
1495
  { 119U, Hexagon::W10 },
1496
  { 120U, Hexagon::V21 },
1497
  { 121U, Hexagon::W11 },
1498
  { 122U, Hexagon::V23 },
1499
  { 123U, Hexagon::W12 },
1500
  { 124U, Hexagon::V25 },
1501
  { 125U, Hexagon::W13 },
1502
  { 126U, Hexagon::V27 },
1503
  { 127U, Hexagon::W14 },
1504
  { 128U, Hexagon::V29 },
1505
  { 129U, Hexagon::W15 },
1506
  { 130U, Hexagon::V31 },
1507
  { 131U, Hexagon::Q0 },
1508
  { 132U, Hexagon::Q1 },
1509
  { 133U, Hexagon::Q2 },
1510
  { 134U, Hexagon::Q3 },
1511
  { 220U, Hexagon::G1_0 },
1512
  { 221U, Hexagon::GSR },
1513
  { 222U, Hexagon::G3_2 },
1514
  { 223U, Hexagon::G3 },
1515
  { 224U, Hexagon::G5_4 },
1516
  { 225U, Hexagon::G5 },
1517
  { 226U, Hexagon::G7_6 },
1518
  { 227U, Hexagon::G7 },
1519
  { 228U, Hexagon::G9_8 },
1520
  { 229U, Hexagon::G9 },
1521
  { 230U, Hexagon::G11_10 },
1522
  { 231U, Hexagon::G11 },
1523
  { 232U, Hexagon::G13_12 },
1524
  { 233U, Hexagon::G13 },
1525
  { 234U, Hexagon::G15_14 },
1526
  { 235U, Hexagon::G15 },
1527
  { 236U, Hexagon::G17_16 },
1528
  { 237U, Hexagon::GPMUCNT5 },
1529
  { 238U, Hexagon::G19_18 },
1530
  { 239U, Hexagon::GPMUCNT7 },
1531
  { 240U, Hexagon::G21_20 },
1532
  { 241U, Hexagon::G21 },
1533
  { 242U, Hexagon::G23_22 },
1534
  { 243U, Hexagon::G23 },
1535
  { 244U, Hexagon::G25_24 },
1536
  { 245U, Hexagon::GPCYCLEHI },
1537
  { 246U, Hexagon::G27_26 },
1538
  { 247U, Hexagon::GPMUCNT1 },
1539
  { 248U, Hexagon::G29_28 },
1540
  { 249U, Hexagon::GPMUCNT3 },
1541
  { 250U, Hexagon::G31_30 },
1542
  { 251U, Hexagon::G31 },
1543
};
1544
extern const unsigned HexagonEHFlavour0Dwarf2LSize = array_lengthof(HexagonEHFlavour0Dwarf2L);
1545
1546
extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0L2Dwarf[] = {
1547
  { Hexagon::CS, 78U },
1548
  { Hexagon::FRAMEKEY, 84U },
1549
  { Hexagon::FRAMELIMIT, 83U },
1550
  { Hexagon::GELR, 220U },
1551
  { Hexagon::GOSP, 222U },
1552
  { Hexagon::GP, 78U },
1553
  { Hexagon::GPCYCLEHI, 245U },
1554
  { Hexagon::GPCYCLELO, 244U },
1555
  { Hexagon::GSR, 221U },
1556
  { Hexagon::PC, 76U },
1557
  { Hexagon::PKTCOUNT, 85U },
1558
  { Hexagon::PKTCOUNTHI, 86U },
1559
  { Hexagon::PKTCOUNTLO, 85U },
1560
  { Hexagon::UGP, 77U },
1561
  { Hexagon::UPCYCLE, 80U },
1562
  { Hexagon::UPCYCLEHI, 82U },
1563
  { Hexagon::UPCYCLELO, 81U },
1564
  { Hexagon::USR, 75U },
1565
  { Hexagon::UTIMER, 97U },
1566
  { Hexagon::UTIMERHI, 98U },
1567
  { Hexagon::UTIMERLO, 97U },
1568
  { Hexagon::VTMP, 131U },
1569
  { Hexagon::C5, 72U },
1570
  { Hexagon::C8, 75U },
1571
  { Hexagon::CS0, 79U },
1572
  { Hexagon::CS1, 80U },
1573
  { Hexagon::D0, 32U },
1574
  { Hexagon::D1, 34U },
1575
  { Hexagon::D2, 36U },
1576
  { Hexagon::D3, 38U },
1577
  { Hexagon::D4, 40U },
1578
  { Hexagon::D5, 42U },
1579
  { Hexagon::D6, 44U },
1580
  { Hexagon::D7, 46U },
1581
  { Hexagon::D8, 48U },
1582
  { Hexagon::D9, 50U },
1583
  { Hexagon::D10, 52U },
1584
  { Hexagon::D11, 54U },
1585
  { Hexagon::D12, 56U },
1586
  { Hexagon::D13, 58U },
1587
  { Hexagon::D14, 60U },
1588
  { Hexagon::D15, 62U },
1589
  { Hexagon::G3, 223U },
1590
  { Hexagon::G4, 224U },
1591
  { Hexagon::G5, 225U },
1592
  { Hexagon::G6, 226U },
1593
  { Hexagon::G7, 227U },
1594
  { Hexagon::G8, 228U },
1595
  { Hexagon::G9, 229U },
1596
  { Hexagon::G10, 230U },
1597
  { Hexagon::G11, 231U },
1598
  { Hexagon::G12, 232U },
1599
  { Hexagon::G13, 233U },
1600
  { Hexagon::G14, 234U },
1601
  { Hexagon::G15, 235U },
1602
  { Hexagon::G20, 240U },
1603
  { Hexagon::G21, 241U },
1604
  { Hexagon::G22, 242U },
1605
  { Hexagon::G23, 243U },
1606
  { Hexagon::G30, 250U },
1607
  { Hexagon::G31, 251U },
1608
  { Hexagon::GPMUCNT0, 246U },
1609
  { Hexagon::GPMUCNT1, 247U },
1610
  { Hexagon::GPMUCNT2, 248U },
1611
  { Hexagon::GPMUCNT3, 249U },
1612
  { Hexagon::GPMUCNT4, 236U },
1613
  { Hexagon::GPMUCNT5, 237U },
1614
  { Hexagon::GPMUCNT6, 238U },
1615
  { Hexagon::GPMUCNT7, 239U },
1616
  { Hexagon::LC0, 68U },
1617
  { Hexagon::LC1, 70U },
1618
  { Hexagon::M0, 73U },
1619
  { Hexagon::M1, 74U },
1620
  { Hexagon::P0, 63U },
1621
  { Hexagon::P1, 64U },
1622
  { Hexagon::P2, 65U },
1623
  { Hexagon::P3, 66U },
1624
  { Hexagon::Q0, 131U },
1625
  { Hexagon::Q1, 132U },
1626
  { Hexagon::Q2, 133U },
1627
  { Hexagon::Q3, 134U },
1628
  { Hexagon::R0, 0U },
1629
  { Hexagon::R1, 1U },
1630
  { Hexagon::R2, 2U },
1631
  { Hexagon::R3, 3U },
1632
  { Hexagon::R4, 4U },
1633
  { Hexagon::R5, 5U },
1634
  { Hexagon::R6, 6U },
1635
  { Hexagon::R7, 7U },
1636
  { Hexagon::R8, 8U },
1637
  { Hexagon::R9, 9U },
1638
  { Hexagon::R10, 10U },
1639
  { Hexagon::R11, 11U },
1640
  { Hexagon::R12, 12U },
1641
  { Hexagon::R13, 13U },
1642
  { Hexagon::R14, 14U },
1643
  { Hexagon::R15, 15U },
1644
  { Hexagon::R16, 16U },
1645
  { Hexagon::R17, 17U },
1646
  { Hexagon::R18, 18U },
1647
  { Hexagon::R19, 19U },
1648
  { Hexagon::R20, 20U },
1649
  { Hexagon::R21, 21U },
1650
  { Hexagon::R22, 22U },
1651
  { Hexagon::R23, 23U },
1652
  { Hexagon::R24, 24U },
1653
  { Hexagon::R25, 25U },
1654
  { Hexagon::R26, 26U },
1655
  { Hexagon::R27, 27U },
1656
  { Hexagon::R28, 28U },
1657
  { Hexagon::R29, 29U },
1658
  { Hexagon::R30, 30U },
1659
  { Hexagon::R31, 31U },
1660
  { Hexagon::SA0, 67U },
1661
  { Hexagon::SA1, 69U },
1662
  { Hexagon::V0, 99U },
1663
  { Hexagon::V1, 100U },
1664
  { Hexagon::V2, 101U },
1665
  { Hexagon::V3, 102U },
1666
  { Hexagon::V4, 103U },
1667
  { Hexagon::V5, 104U },
1668
  { Hexagon::V6, 105U },
1669
  { Hexagon::V7, 106U },
1670
  { Hexagon::V8, 107U },
1671
  { Hexagon::V9, 108U },
1672
  { Hexagon::V10, 109U },
1673
  { Hexagon::V11, 110U },
1674
  { Hexagon::V12, 111U },
1675
  { Hexagon::V13, 112U },
1676
  { Hexagon::V14, 113U },
1677
  { Hexagon::V15, 114U },
1678
  { Hexagon::V16, 115U },
1679
  { Hexagon::V17, 116U },
1680
  { Hexagon::V18, 117U },
1681
  { Hexagon::V19, 118U },
1682
  { Hexagon::V20, 119U },
1683
  { Hexagon::V21, 120U },
1684
  { Hexagon::V22, 121U },
1685
  { Hexagon::V23, 122U },
1686
  { Hexagon::V24, 123U },
1687
  { Hexagon::V25, 124U },
1688
  { Hexagon::V26, 125U },
1689
  { Hexagon::V27, 126U },
1690
  { Hexagon::V28, 127U },
1691
  { Hexagon::V29, 128U },
1692
  { Hexagon::V30, 129U },
1693
  { Hexagon::V31, 130U },
1694
  { Hexagon::W0, 99U },
1695
  { Hexagon::W1, 101U },
1696
  { Hexagon::W2, 103U },
1697
  { Hexagon::W3, 105U },
1698
  { Hexagon::W4, 107U },
1699
  { Hexagon::W5, 109U },
1700
  { Hexagon::W6, 111U },
1701
  { Hexagon::W7, 113U },
1702
  { Hexagon::W8, 115U },
1703
  { Hexagon::W9, 117U },
1704
  { Hexagon::W10, 119U },
1705
  { Hexagon::W11, 121U },
1706
  { Hexagon::W12, 123U },
1707
  { Hexagon::W13, 125U },
1708
  { Hexagon::W14, 127U },
1709
  { Hexagon::W15, 129U },
1710
  { Hexagon::C1_0, 67U },
1711
  { Hexagon::C3_2, 69U },
1712
  { Hexagon::C5_4, 71U },
1713
  { Hexagon::C7_6, 72U },
1714
  { Hexagon::C9_8, 74U },
1715
  { Hexagon::C11_10, 76U },
1716
  { Hexagon::C17_16, 83U },
1717
  { Hexagon::G1_0, 220U },
1718
  { Hexagon::G3_2, 222U },
1719
  { Hexagon::G5_4, 224U },
1720
  { Hexagon::G7_6, 226U },
1721
  { Hexagon::G9_8, 228U },
1722
  { Hexagon::G11_10, 230U },
1723
  { Hexagon::G13_12, 232U },
1724
  { Hexagon::G15_14, 234U },
1725
  { Hexagon::G17_16, 236U },
1726
  { Hexagon::G19_18, 238U },
1727
  { Hexagon::G21_20, 240U },
1728
  { Hexagon::G23_22, 242U },
1729
  { Hexagon::G25_24, 244U },
1730
  { Hexagon::G27_26, 246U },
1731
  { Hexagon::G29_28, 248U },
1732
  { Hexagon::G31_30, 250U },
1733
  { Hexagon::P3_0, 71U },
1734
};
1735
extern const unsigned HexagonDwarfFlavour0L2DwarfSize = array_lengthof(HexagonDwarfFlavour0L2Dwarf);
1736
1737
extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0L2Dwarf[] = {
1738
  { Hexagon::CS, 78U },
1739
  { Hexagon::FRAMEKEY, 84U },
1740
  { Hexagon::FRAMELIMIT, 83U },
1741
  { Hexagon::GELR, 220U },
1742
  { Hexagon::GOSP, 222U },
1743
  { Hexagon::GP, 78U },
1744
  { Hexagon::GPCYCLEHI, 245U },
1745
  { Hexagon::GPCYCLELO, 244U },
1746
  { Hexagon::GSR, 221U },
1747
  { Hexagon::PC, 76U },
1748
  { Hexagon::PKTCOUNT, 85U },
1749
  { Hexagon::PKTCOUNTHI, 86U },
1750
  { Hexagon::PKTCOUNTLO, 85U },
1751
  { Hexagon::UGP, 77U },
1752
  { Hexagon::UPCYCLE, 80U },
1753
  { Hexagon::UPCYCLEHI, 82U },
1754
  { Hexagon::UPCYCLELO, 81U },
1755
  { Hexagon::USR, 75U },
1756
  { Hexagon::UTIMER, 97U },
1757
  { Hexagon::UTIMERHI, 98U },
1758
  { Hexagon::UTIMERLO, 97U },
1759
  { Hexagon::VTMP, 131U },
1760
  { Hexagon::C5, 72U },
1761
  { Hexagon::C8, 75U },
1762
  { Hexagon::CS0, 79U },
1763
  { Hexagon::CS1, 80U },
1764
  { Hexagon::D0, 32U },
1765
  { Hexagon::D1, 34U },
1766
  { Hexagon::D2, 36U },
1767
  { Hexagon::D3, 38U },
1768
  { Hexagon::D4, 40U },
1769
  { Hexagon::D5, 42U },
1770
  { Hexagon::D6, 44U },
1771
  { Hexagon::D7, 46U },
1772
  { Hexagon::D8, 48U },
1773
  { Hexagon::D9, 50U },
1774
  { Hexagon::D10, 52U },
1775
  { Hexagon::D11, 54U },
1776
  { Hexagon::D12, 56U },
1777
  { Hexagon::D13, 58U },
1778
  { Hexagon::D14, 60U },
1779
  { Hexagon::D15, 62U },
1780
  { Hexagon::G3, 223U },
1781
  { Hexagon::G4, 224U },
1782
  { Hexagon::G5, 225U },
1783
  { Hexagon::G6, 226U },
1784
  { Hexagon::G7, 227U },
1785
  { Hexagon::G8, 228U },
1786
  { Hexagon::G9, 229U },
1787
  { Hexagon::G10, 230U },
1788
  { Hexagon::G11, 231U },
1789
  { Hexagon::G12, 232U },
1790
  { Hexagon::G13, 233U },
1791
  { Hexagon::G14, 234U },
1792
  { Hexagon::G15, 235U },
1793
  { Hexagon::G20, 240U },
1794
  { Hexagon::G21, 241U },
1795
  { Hexagon::G22, 242U },
1796
  { Hexagon::G23, 243U },
1797
  { Hexagon::G30, 250U },
1798
  { Hexagon::G31, 251U },
1799
  { Hexagon::GPMUCNT0, 246U },
1800
  { Hexagon::GPMUCNT1, 247U },
1801
  { Hexagon::GPMUCNT2, 248U },
1802
  { Hexagon::GPMUCNT3, 249U },
1803
  { Hexagon::GPMUCNT4, 236U },
1804
  { Hexagon::GPMUCNT5, 237U },
1805
  { Hexagon::GPMUCNT6, 238U },
1806
  { Hexagon::GPMUCNT7, 239U },
1807
  { Hexagon::LC0, 68U },
1808
  { Hexagon::LC1, 70U },
1809
  { Hexagon::M0, 73U },
1810
  { Hexagon::M1, 74U },
1811
  { Hexagon::P0, 63U },
1812
  { Hexagon::P1, 64U },
1813
  { Hexagon::P2, 65U },
1814
  { Hexagon::P3, 66U },
1815
  { Hexagon::Q0, 131U },
1816
  { Hexagon::Q1, 132U },
1817
  { Hexagon::Q2, 133U },
1818
  { Hexagon::Q3, 134U },
1819
  { Hexagon::R0, 0U },
1820
  { Hexagon::R1, 1U },
1821
  { Hexagon::R2, 2U },
1822
  { Hexagon::R3, 3U },
1823
  { Hexagon::R4, 4U },
1824
  { Hexagon::R5, 5U },
1825
  { Hexagon::R6, 6U },
1826
  { Hexagon::R7, 7U },
1827
  { Hexagon::R8, 8U },
1828
  { Hexagon::R9, 9U },
1829
  { Hexagon::R10, 10U },
1830
  { Hexagon::R11, 11U },
1831
  { Hexagon::R12, 12U },
1832
  { Hexagon::R13, 13U },
1833
  { Hexagon::R14, 14U },
1834
  { Hexagon::R15, 15U },
1835
  { Hexagon::R16, 16U },
1836
  { Hexagon::R17, 17U },
1837
  { Hexagon::R18, 18U },
1838
  { Hexagon::R19, 19U },
1839
  { Hexagon::R20, 20U },
1840
  { Hexagon::R21, 21U },
1841
  { Hexagon::R22, 22U },
1842
  { Hexagon::R23, 23U },
1843
  { Hexagon::R24, 24U },
1844
  { Hexagon::R25, 25U },
1845
  { Hexagon::R26, 26U },
1846
  { Hexagon::R27, 27U },
1847
  { Hexagon::R28, 28U },
1848
  { Hexagon::R29, 29U },
1849
  { Hexagon::R30, 30U },
1850
  { Hexagon::R31, 31U },
1851
  { Hexagon::SA0, 67U },
1852
  { Hexagon::SA1, 69U },
1853
  { Hexagon::V0, 99U },
1854
  { Hexagon::V1, 100U },
1855
  { Hexagon::V2, 101U },
1856
  { Hexagon::V3, 102U },
1857
  { Hexagon::V4, 103U },
1858
  { Hexagon::V5, 104U },
1859
  { Hexagon::V6, 105U },
1860
  { Hexagon::V7, 106U },
1861
  { Hexagon::V8, 107U },
1862
  { Hexagon::V9, 108U },
1863
  { Hexagon::V10, 109U },
1864
  { Hexagon::V11, 110U },
1865
  { Hexagon::V12, 111U },
1866
  { Hexagon::V13, 112U },
1867
  { Hexagon::V14, 113U },
1868
  { Hexagon::V15, 114U },
1869
  { Hexagon::V16, 115U },
1870
  { Hexagon::V17, 116U },
1871
  { Hexagon::V18, 117U },
1872
  { Hexagon::V19, 118U },
1873
  { Hexagon::V20, 119U },
1874
  { Hexagon::V21, 120U },
1875
  { Hexagon::V22, 121U },
1876
  { Hexagon::V23, 122U },
1877
  { Hexagon::V24, 123U },
1878
  { Hexagon::V25, 124U },
1879
  { Hexagon::V26, 125U },
1880
  { Hexagon::V27, 126U },
1881
  { Hexagon::V28, 127U },
1882
  { Hexagon::V29, 128U },
1883
  { Hexagon::V30, 129U },
1884
  { Hexagon::V31, 130U },
1885
  { Hexagon::W0, 99U },
1886
  { Hexagon::W1, 101U },
1887
  { Hexagon::W2, 103U },
1888
  { Hexagon::W3, 105U },
1889
  { Hexagon::W4, 107U },
1890
  { Hexagon::W5, 109U },
1891
  { Hexagon::W6, 111U },
1892
  { Hexagon::W7, 113U },
1893
  { Hexagon::W8, 115U },
1894
  { Hexagon::W9, 117U },
1895
  { Hexagon::W10, 119U },
1896
  { Hexagon::W11, 121U },
1897
  { Hexagon::W12, 123U },
1898
  { Hexagon::W13, 125U },
1899
  { Hexagon::W14, 127U },
1900
  { Hexagon::W15, 129U },
1901
  { Hexagon::C1_0, 67U },
1902
  { Hexagon::C3_2, 69U },
1903
  { Hexagon::C5_4, 71U },
1904
  { Hexagon::C7_6, 72U },
1905
  { Hexagon::C9_8, 74U },
1906
  { Hexagon::C11_10, 76U },
1907
  { Hexagon::C17_16, 83U },
1908
  { Hexagon::G1_0, 220U },
1909
  { Hexagon::G3_2, 222U },
1910
  { Hexagon::G5_4, 224U },
1911
  { Hexagon::G7_6, 226U },
1912
  { Hexagon::G9_8, 228U },
1913
  { Hexagon::G11_10, 230U },
1914
  { Hexagon::G13_12, 232U },
1915
  { Hexagon::G15_14, 234U },
1916
  { Hexagon::G17_16, 236U },
1917
  { Hexagon::G19_18, 238U },
1918
  { Hexagon::G21_20, 240U },
1919
  { Hexagon::G23_22, 242U },
1920
  { Hexagon::G25_24, 244U },
1921
  { Hexagon::G27_26, 246U },
1922
  { Hexagon::G29_28, 248U },
1923
  { Hexagon::G31_30, 250U },
1924
  { Hexagon::P3_0, 71U },
1925
};
1926
extern const unsigned HexagonEHFlavour0L2DwarfSize = array_lengthof(HexagonEHFlavour0L2Dwarf);
1927
1928
extern const uint16_t HexagonRegEncodingTable[] = {
1929
  0,
1930
  12,
1931
  17,
1932
  16,
1933
  0,
1934
  2,
1935
  11,
1936
  25,
1937
  24,
1938
  1,
1939
  9,
1940
  18,
1941
  19,
1942
  18,
1943
  10,
1944
  14,
1945
  15,
1946
  14,
1947
  8,
1948
  0,
1949
  30,
1950
  31,
1951
  30,
1952
  0,
1953
  5,
1954
  8,
1955
  12,
1956
  13,
1957
  0,
1958
  2,
1959
  4,
1960
  6,
1961
  8,
1962
  10,
1963
  12,
1964
  14,
1965
  16,
1966
  18,
1967
  20,
1968
  22,
1969
  24,
1970
  26,
1971
  28,
1972
  30,
1973
  3,
1974
  4,
1975
  5,
1976
  6,
1977
  7,
1978
  8,
1979
  9,
1980
  10,
1981
  11,
1982
  12,
1983
  13,
1984
  14,
1985
  15,
1986
  20,
1987
  21,
1988
  22,
1989
  23,
1990
  30,
1991
  31,
1992
  26,
1993
  27,
1994
  28,
1995
  29,
1996
  16,
1997
  17,
1998
  18,
1999
  19,
2000
  1,
2001
  3,
2002
  6,
2003
  7,
2004
  0,
2005
  1,
2006
  2,
2007
  3,
2008
  0,
2009
  1,
2010
  2,
2011
  3,
2012
  0,
2013
  1,
2014
  2,
2015
  3,
2016
  4,
2017
  5,
2018
  6,
2019
  7,
2020
  8,
2021
  9,
2022
  10,
2023
  11,
2024
  12,
2025
  13,
2026
  14,
2027
  15,
2028
  16,
2029
  17,
2030
  18,
2031
  19,
2032
  20,
2033
  21,
2034
  22,
2035
  23,
2036
  24,
2037
  25,
2038
  26,
2039
  27,
2040
  28,
2041
  29,
2042
  30,
2043
  31,
2044
  0,
2045
  2,
2046
  0,
2047
  1,
2048
  2,
2049
  3,
2050
  4,
2051
  5,
2052
  6,
2053
  7,
2054
  8,
2055
  9,
2056
  10,
2057
  11,
2058
  12,
2059
  13,
2060
  14,
2061
  15,
2062
  16,
2063
  17,
2064
  18,
2065
  19,
2066
  20,
2067
  21,
2068
  22,
2069
  23,
2070
  24,
2071
  25,
2072
  26,
2073
  27,
2074
  28,
2075
  29,
2076
  30,
2077
  31,
2078
  0,
2079
  2,
2080
  4,
2081
  6,
2082
  8,
2083
  10,
2084
  12,
2085
  14,
2086
  16,
2087
  18,
2088
  20,
2089
  22,
2090
  24,
2091
  26,
2092
  28,
2093
  30,
2094
  0,
2095
  2,
2096
  4,
2097
  6,
2098
  8,
2099
  10,
2100
  16,
2101
  0,
2102
  2,
2103
  4,
2104
  6,
2105
  8,
2106
  10,
2107
  12,
2108
  14,
2109
  16,
2110
  18,
2111
  20,
2112
  22,
2113
  24,
2114
  26,
2115
  28,
2116
  30,
2117
  4,
2118
};
2119
1.25k
static inline void InitHexagonMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
2120
1.25k
  RI->InitMCRegisterInfo(HexagonRegDesc, 189, RA, PC, HexagonMCRegisterClasses, 24, HexagonRegUnitRoots, 127, HexagonRegDiffLists, HexagonLaneMaskLists, HexagonRegStrings, HexagonRegClassStrings, HexagonSubRegIdxLists, 6,
2121
1.25k
HexagonSubRegIdxRanges, HexagonRegEncodingTable);
2122
1.25k
2123
1.25k
  switch (DwarfFlavour) {
2124
1.25k
  default:
2125
0
    llvm_unreachable("Unknown DWARF flavour");
2126
1.25k
  case 0:
2127
1.25k
    RI->mapDwarfRegsToLLVMRegs(HexagonDwarfFlavour0Dwarf2L, HexagonDwarfFlavour0Dwarf2LSize, false);
2128
1.25k
    break;
2129
1.25k
  }
2130
1.25k
  switch (EHFlavour) {
2131
1.25k
  default:
2132
0
    llvm_unreachable("Unknown DWARF flavour");
2133
1.25k
  case 0:
2134
1.25k
    RI->mapDwarfRegsToLLVMRegs(HexagonEHFlavour0Dwarf2L, HexagonEHFlavour0Dwarf2LSize, true);
2135
1.25k
    break;
2136
1.25k
  }
2137
1.25k
  switch (DwarfFlavour) {
2138
1.25k
  default:
2139
0
    llvm_unreachable("Unknown DWARF flavour");
2140
1.25k
  case 0:
2141
1.25k
    RI->mapLLVMRegsToDwarfRegs(HexagonDwarfFlavour0L2Dwarf, HexagonDwarfFlavour0L2DwarfSize, false);
2142
1.25k
    break;
2143
1.25k
  }
2144
1.25k
  switch (EHFlavour) {
2145
1.25k
  default:
2146
0
    llvm_unreachable("Unknown DWARF flavour");
2147
1.25k
  case 0:
2148
1.25k
    RI->mapLLVMRegsToDwarfRegs(HexagonEHFlavour0L2Dwarf, HexagonEHFlavour0L2DwarfSize, true);
2149
1.25k
    break;
2150
1.25k
  }
2151
1.25k
}
2152
2153
} // end namespace llvm
2154
2155
#endif // GET_REGINFO_MC_DESC
2156
2157
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2158
|*                                                                            *|
2159
|* Register Information Header Fragment                                       *|
2160
|*                                                                            *|
2161
|* Automatically generated file, do not edit!                                 *|
2162
|*                                                                            *|
2163
\*===----------------------------------------------------------------------===*/
2164
2165
2166
#ifdef GET_REGINFO_HEADER
2167
#undef GET_REGINFO_HEADER
2168
2169
#include "llvm/CodeGen/TargetRegisterInfo.h"
2170
2171
namespace llvm {
2172
2173
class HexagonFrameLowering;
2174
2175
struct HexagonGenRegisterInfo : public TargetRegisterInfo {
2176
  explicit HexagonGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
2177
      unsigned PC = 0, unsigned HwMode = 0);
2178
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
2179
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
2180
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
2181
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
2182
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
2183
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
2184
  unsigned getNumRegPressureSets() const override;
2185
  const char *getRegPressureSetName(unsigned Idx) const override;
2186
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
2187
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
2188
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
2189
  ArrayRef<const char *> getRegMaskNames() const override;
2190
  ArrayRef<const uint32_t *> getRegMasks() const override;
2191
  /// Devirtualized TargetFrameLowering.
2192
  static const HexagonFrameLowering *getFrameLowering(
2193
      const MachineFunction &MF);
2194
};
2195
2196
namespace Hexagon { // Register classes
2197
  extern const TargetRegisterClass UsrBitsRegClass;
2198
  extern const TargetRegisterClass GuestRegsRegClass;
2199
  extern const TargetRegisterClass IntRegsRegClass;
2200
  extern const TargetRegisterClass CtrRegsRegClass;
2201
  extern const TargetRegisterClass GeneralSubRegsRegClass;
2202
  extern const TargetRegisterClass V62RegsRegClass;
2203
  extern const TargetRegisterClass IntRegsLow8RegClass;
2204
  extern const TargetRegisterClass CtrRegs_and_V62RegsRegClass;
2205
  extern const TargetRegisterClass PredRegsRegClass;
2206
  extern const TargetRegisterClass V62Regs_with_isub_hiRegClass;
2207
  extern const TargetRegisterClass ModRegsRegClass;
2208
  extern const TargetRegisterClass CtrRegs_with_subreg_overflowRegClass;
2209
  extern const TargetRegisterClass V65RegsRegClass;
2210
  extern const TargetRegisterClass DoubleRegsRegClass;
2211
  extern const TargetRegisterClass GuestRegs64RegClass;
2212
  extern const TargetRegisterClass CtrRegs64RegClass;
2213
  extern const TargetRegisterClass GeneralDoubleLow8RegsRegClass;
2214
  extern const TargetRegisterClass DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass;
2215
  extern const TargetRegisterClass CtrRegs64_and_V62RegsRegClass;
2216
  extern const TargetRegisterClass CtrRegs64_with_isub_hi_in_ModRegsRegClass;
2217
  extern const TargetRegisterClass HvxVRRegClass;
2218
  extern const TargetRegisterClass HvxQRRegClass;
2219
  extern const TargetRegisterClass HvxVR_and_V65RegsRegClass;
2220
  extern const TargetRegisterClass HvxWRRegClass;
2221
} // end namespace Hexagon
2222
2223
} // end namespace llvm
2224
2225
#endif // GET_REGINFO_HEADER
2226
2227
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2228
|*                                                                            *|
2229
|* Target Register and Register Classes Information                           *|
2230
|*                                                                            *|
2231
|* Automatically generated file, do not edit!                                 *|
2232
|*                                                                            *|
2233
\*===----------------------------------------------------------------------===*/
2234
2235
2236
#ifdef GET_REGINFO_TARGET_DESC
2237
#undef GET_REGINFO_TARGET_DESC
2238
2239
namespace llvm {
2240
2241
extern const MCRegisterClass HexagonMCRegisterClasses[];
2242
2243
static const MVT::SimpleValueType VTLists[] = {
2244
  /* 0 */ MVT::i1, MVT::Other,
2245
  /* 2 */ MVT::i1, MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v4i8, MVT::v2i16, MVT::i32, MVT::Other,
2246
  /* 10 */ MVT::i64, MVT::Other,
2247
  /* 12 */ MVT::v512i1, MVT::v64i1, MVT::v32i1, MVT::v16i1, MVT::Other,
2248
  /* 17 */ MVT::v1024i1, MVT::v128i1, MVT::v64i1, MVT::v32i1, MVT::Other,
2249
  /* 22 */ MVT::i32, MVT::f32, MVT::v4i8, MVT::v2i16, MVT::Other,
2250
  /* 27 */ MVT::i64, MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::Other,
2251
  /* 33 */ MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::Other,
2252
  /* 37 */ MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::Other,
2253
  /* 41 */ MVT::v256i8, MVT::v128i16, MVT::v64i32, MVT::Other,
2254
};
2255
2256
static const char *const SubRegIndexNameTable[] = { "isub_hi", "isub_lo", "subreg_overflow", "vsub_hi", "vsub_lo", "" };
2257
2258
2259
static const LaneBitmask SubRegIndexLaneMaskTable[] = {
2260
  LaneBitmask::getAll(),
2261
  LaneBitmask(0x00000001), // isub_hi
2262
  LaneBitmask(0x00000002), // isub_lo
2263
  LaneBitmask(0x00000004), // subreg_overflow
2264
  LaneBitmask(0x00000008), // vsub_hi
2265
  LaneBitmask(0x00000010), // vsub_lo
2266
 };
2267
2268
2269
2270
static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
2271
  // Mode = 0 (Default)
2272
  { 1, 1, 0, VTLists+0 },    // UsrBits
2273
  { 32, 32, 32, VTLists+8 },    // GuestRegs
2274
  { 32, 32, 32, VTLists+22 },    // IntRegs
2275
  { 32, 32, 32, VTLists+8 },    // CtrRegs
2276
  { 32, 32, 32, VTLists+8 },    // GeneralSubRegs
2277
  { 32, 32, 32, VTLists+8 },    // V62Regs
2278
  { 32, 32, 32, VTLists+8 },    // IntRegsLow8
2279
  { 32, 32, 32, VTLists+8 },    // CtrRegs_and_V62Regs
2280
  { 32, 32, 32, VTLists+2 },    // PredRegs
2281
  { 32, 32, 32, VTLists+8 },    // V62Regs_with_isub_hi
2282
  { 32, 32, 32, VTLists+8 },    // ModRegs
2283
  { 32, 32, 32, VTLists+8 },    // CtrRegs_with_subreg_overflow
2284
  { 32, 32, 32, VTLists+8 },    // V65Regs
2285
  { 64, 64, 64, VTLists+27 },    // DoubleRegs
2286
  { 64, 64, 64, VTLists+10 },    // GuestRegs64
2287
  { 64, 64, 64, VTLists+10 },    // CtrRegs64
2288
  { 64, 64, 64, VTLists+10 },    // GeneralDoubleLow8Regs
2289
  { 64, 64, 64, VTLists+10 },    // DoubleRegs_with_isub_hi_in_IntRegsLow8
2290
  { 64, 64, 64, VTLists+10 },    // CtrRegs64_and_V62Regs
2291
  { 64, 64, 64, VTLists+10 },    // CtrRegs64_with_isub_hi_in_ModRegs
2292
  { 512, 512, 512, VTLists+33 },    // HvxVR
2293
  { 512, 512, 512, VTLists+12 },    // HvxQR
2294
  { 512, 512, 512, VTLists+33 },    // HvxVR_and_V65Regs
2295
  { 1024, 1024, 1024, VTLists+37 },    // HvxWR
2296
  // Mode = 1 (Hvx128)
2297
  { 1, 1, 0, VTLists+0 },    // UsrBits
2298
  { 32, 32, 32, VTLists+8 },    // GuestRegs
2299
  { 32, 32, 32, VTLists+22 },    // IntRegs
2300
  { 32, 32, 32, VTLists+8 },    // CtrRegs
2301
  { 32, 32, 32, VTLists+8 },    // GeneralSubRegs
2302
  { 32, 32, 32, VTLists+8 },    // V62Regs
2303
  { 32, 32, 32, VTLists+8 },    // IntRegsLow8
2304
  { 32, 32, 32, VTLists+8 },    // CtrRegs_and_V62Regs
2305
  { 32, 32, 32, VTLists+2 },    // PredRegs
2306
  { 32, 32, 32, VTLists+8 },    // V62Regs_with_isub_hi
2307
  { 32, 32, 32, VTLists+8 },    // ModRegs
2308
  { 32, 32, 32, VTLists+8 },    // CtrRegs_with_subreg_overflow
2309
  { 32, 32, 32, VTLists+8 },    // V65Regs
2310
  { 64, 64, 64, VTLists+27 },    // DoubleRegs
2311
  { 64, 64, 64, VTLists+10 },    // GuestRegs64
2312
  { 64, 64, 64, VTLists+10 },    // CtrRegs64
2313
  { 64, 64, 64, VTLists+10 },    // GeneralDoubleLow8Regs
2314
  { 64, 64, 64, VTLists+10 },    // DoubleRegs_with_isub_hi_in_IntRegsLow8
2315
  { 64, 64, 64, VTLists+10 },    // CtrRegs64_and_V62Regs
2316
  { 64, 64, 64, VTLists+10 },    // CtrRegs64_with_isub_hi_in_ModRegs
2317
  { 1024, 1024, 1024, VTLists+37 },    // HvxVR
2318
  { 1024, 1024, 1024, VTLists+17 },    // HvxQR
2319
  { 1024, 1024, 1024, VTLists+37 },    // HvxVR_and_V65Regs
2320
  { 2048, 2048, 2048, VTLists+41 },    // HvxWR
2321
  // Mode = 2 (Hvx64)
2322
  { 1, 1, 0, VTLists+0 },    // UsrBits
2323
  { 32, 32, 32, VTLists+8 },    // GuestRegs
2324
  { 32, 32, 32, VTLists+22 },    // IntRegs
2325
  { 32, 32, 32, VTLists+8 },    // CtrRegs
2326
  { 32, 32, 32, VTLists+8 },    // GeneralSubRegs
2327
  { 32, 32, 32, VTLists+8 },    // V62Regs
2328
  { 32, 32, 32, VTLists+8 },    // IntRegsLow8
2329
  { 32, 32, 32, VTLists+8 },    // CtrRegs_and_V62Regs
2330
  { 32, 32, 32, VTLists+2 },    // PredRegs
2331
  { 32, 32, 32, VTLists+8 },    // V62Regs_with_isub_hi
2332
  { 32, 32, 32, VTLists+8 },    // ModRegs
2333
  { 32, 32, 32, VTLists+8 },    // CtrRegs_with_subreg_overflow
2334
  { 32, 32, 32, VTLists+8 },    // V65Regs
2335
  { 64, 64, 64, VTLists+27 },    // DoubleRegs
2336
  { 64, 64, 64, VTLists+10 },    // GuestRegs64
2337
  { 64, 64, 64, VTLists+10 },    // CtrRegs64
2338
  { 64, 64, 64, VTLists+10 },    // GeneralDoubleLow8Regs
2339
  { 64, 64, 64, VTLists+10 },    // DoubleRegs_with_isub_hi_in_IntRegsLow8
2340
  { 64, 64, 64, VTLists+10 },    // CtrRegs64_and_V62Regs
2341
  { 64, 64, 64, VTLists+10 },    // CtrRegs64_with_isub_hi_in_ModRegs
2342
  { 512, 512, 512, VTLists+33 },    // HvxVR
2343
  { 512, 512, 512, VTLists+12 },    // HvxQR
2344
  { 512, 512, 512, VTLists+33 },    // HvxVR_and_V65Regs
2345
  { 1024, 1024, 1024, VTLists+37 },    // HvxWR
2346
};
2347
2348
static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
2349
2350
static const uint32_t UsrBitsSubClassMask[] = {
2351
  0x00000001, 
2352
  0x00000800, // subreg_overflow
2353
};
2354
2355
static const uint32_t GuestRegsSubClassMask[] = {
2356
  0x00000002, 
2357
  0x00004000, // isub_hi
2358
  0x00004000, // isub_lo
2359
};
2360
2361
static const uint32_t IntRegsSubClassMask[] = {
2362
  0x00000054, 
2363
  0x00032000, // isub_hi
2364
  0x00032000, // isub_lo
2365
};
2366
2367
static const uint32_t CtrRegsSubClassMask[] = {
2368
  0x00000c88, 
2369
  0x000c8200, // isub_hi
2370
  0x000c8200, // isub_lo
2371
};
2372
2373
static const uint32_t GeneralSubRegsSubClassMask[] = {
2374
  0x00000050, 
2375
  0x00030000, // isub_hi
2376
  0x00030000, // isub_lo
2377
};
2378
2379
static const uint32_t V62RegsSubClassMask[] = {
2380
  0x000402a0, 
2381
  0x00040200, // isub_hi
2382
  0x00040200, // isub_lo
2383
};
2384
2385
static const uint32_t IntRegsLow8SubClassMask[] = {
2386
  0x00000040, 
2387
  0x00020000, // isub_hi
2388
  0x00020000, // isub_lo
2389
};
2390
2391
static const uint32_t CtrRegs_and_V62RegsSubClassMask[] = {
2392
  0x00000080, 
2393
  0x00040200, // isub_hi
2394
  0x00040200, // isub_lo
2395
};
2396
2397
static const uint32_t PredRegsSubClassMask[] = {
2398
  0x00000100, 
2399
};
2400
2401
static const uint32_t V62Regs_with_isub_hiSubClassMask[] = {
2402
  0x00040200, 
2403
};
2404
2405
static const uint32_t ModRegsSubClassMask[] = {
2406
  0x00000400, 
2407
  0x00080000, // isub_hi
2408
  0x00080000, // isub_lo
2409
};
2410
2411
static const uint32_t CtrRegs_with_subreg_overflowSubClassMask[] = {
2412
  0x00000800, 
2413
};
2414
2415
static const uint32_t V65RegsSubClassMask[] = {
2416
  0x00401000, 
2417
};
2418
2419
static const uint32_t DoubleRegsSubClassMask[] = {
2420
  0x00032000, 
2421
};
2422
2423
static const uint32_t GuestRegs64SubClassMask[] = {
2424
  0x00004000, 
2425
};
2426
2427
static const uint32_t CtrRegs64SubClassMask[] = {
2428
  0x000c8000, 
2429
};
2430
2431
static const uint32_t GeneralDoubleLow8RegsSubClassMask[] = {
2432
  0x00030000, 
2433
};
2434
2435
static const uint32_t DoubleRegs_with_isub_hi_in_IntRegsLow8SubClassMask[] = {
2436
  0x00020000, 
2437
};
2438
2439
static const uint32_t CtrRegs64_and_V62RegsSubClassMask[] = {
2440
  0x00040000, 
2441
};
2442
2443
static const uint32_t CtrRegs64_with_isub_hi_in_ModRegsSubClassMask[] = {
2444
  0x00080000, 
2445
};
2446
2447
static const uint32_t HvxVRSubClassMask[] = {
2448
  0x00500000, 
2449
  0x00800000, // vsub_hi
2450
  0x00800000, // vsub_lo
2451
};
2452
2453
static const uint32_t HvxQRSubClassMask[] = {
2454
  0x00200000, 
2455
};
2456
2457
static const uint32_t HvxVR_and_V65RegsSubClassMask[] = {
2458
  0x00400000, 
2459
};
2460
2461
static const uint32_t HvxWRSubClassMask[] = {
2462
  0x00800000, 
2463
};
2464
2465
static const uint16_t SuperRegIdxSeqs[] = {
2466
  /* 0 */ 1, 2, 0,
2467
  /* 3 */ 3, 0,
2468
  /* 5 */ 4, 5, 0,
2469
};
2470
2471
static const TargetRegisterClass *const GeneralSubRegsSuperclasses[] = {
2472
  &Hexagon::IntRegsRegClass,
2473
  nullptr
2474
};
2475
2476
static const TargetRegisterClass *const IntRegsLow8Superclasses[] = {
2477
  &Hexagon::IntRegsRegClass,
2478
  &Hexagon::GeneralSubRegsRegClass,
2479
  nullptr
2480
};
2481
2482
static const TargetRegisterClass *const CtrRegs_and_V62RegsSuperclasses[] = {
2483
  &Hexagon::CtrRegsRegClass,
2484
  &Hexagon::V62RegsRegClass,
2485
  nullptr
2486
};
2487
2488
static const TargetRegisterClass *const V62Regs_with_isub_hiSuperclasses[] = {
2489
  &Hexagon::V62RegsRegClass,
2490
  nullptr
2491
};
2492
2493
static const TargetRegisterClass *const ModRegsSuperclasses[] = {
2494
  &Hexagon::CtrRegsRegClass,
2495
  nullptr
2496
};
2497
2498
static const TargetRegisterClass *const CtrRegs_with_subreg_overflowSuperclasses[] = {
2499
  &Hexagon::CtrRegsRegClass,
2500
  nullptr
2501
};
2502
2503
static const TargetRegisterClass *const GeneralDoubleLow8RegsSuperclasses[] = {
2504
  &Hexagon::DoubleRegsRegClass,
2505
  nullptr
2506
};
2507
2508
static const TargetRegisterClass *const DoubleRegs_with_isub_hi_in_IntRegsLow8Superclasses[] = {
2509
  &Hexagon::DoubleRegsRegClass,
2510
  &Hexagon::GeneralDoubleLow8RegsRegClass,
2511
  nullptr
2512
};
2513
2514
static const TargetRegisterClass *const CtrRegs64_and_V62RegsSuperclasses[] = {
2515
  &Hexagon::V62RegsRegClass,
2516
  &Hexagon::V62Regs_with_isub_hiRegClass,
2517
  &Hexagon::CtrRegs64RegClass,
2518
  nullptr
2519
};
2520
2521
static const TargetRegisterClass *const CtrRegs64_with_isub_hi_in_ModRegsSuperclasses[] = {
2522
  &Hexagon::CtrRegs64RegClass,
2523
  nullptr
2524
};
2525
2526
static const TargetRegisterClass *const HvxVR_and_V65RegsSuperclasses[] = {
2527
  &Hexagon::V65RegsRegClass,
2528
  &Hexagon::HvxVRRegClass,
2529
  nullptr
2530
};
2531
2532
2533
namespace Hexagon {   // Register class instances
2534
  extern const TargetRegisterClass UsrBitsRegClass = {
2535
    &HexagonMCRegisterClasses[UsrBitsRegClassID],
2536
    UsrBitsSubClassMask,
2537
    SuperRegIdxSeqs + 3,
2538
    LaneBitmask(0x00000001),
2539
    0,
2540
    false, /* HasDisjunctSubRegs */
2541
    false, /* CoveredBySubRegs */
2542
    NullRegClasses,
2543
    nullptr
2544
  };
2545
2546
  extern const TargetRegisterClass GuestRegsRegClass = {
2547
    &HexagonMCRegisterClasses[GuestRegsRegClassID],
2548
    GuestRegsSubClassMask,
2549
    SuperRegIdxSeqs + 0,
2550
    LaneBitmask(0x00000001),
2551
    0,
2552
    false, /* HasDisjunctSubRegs */
2553
    false, /* CoveredBySubRegs */
2554
    NullRegClasses,
2555
    nullptr
2556
  };
2557
2558
  extern const TargetRegisterClass IntRegsRegClass = {
2559
    &HexagonMCRegisterClasses[IntRegsRegClassID],
2560
    IntRegsSubClassMask,
2561
    SuperRegIdxSeqs + 0,
2562
    LaneBitmask(0x00000001),
2563
    0,
2564
    false, /* HasDisjunctSubRegs */
2565
    false, /* CoveredBySubRegs */
2566
    NullRegClasses,
2567
    nullptr
2568
  };
2569
2570
  extern const TargetRegisterClass CtrRegsRegClass = {
2571
    &HexagonMCRegisterClasses[CtrRegsRegClassID],
2572
    CtrRegsSubClassMask,
2573
    SuperRegIdxSeqs + 0,
2574
    LaneBitmask(0x00000004),
2575
    0,
2576
    false, /* HasDisjunctSubRegs */
2577
    false, /* CoveredBySubRegs */
2578
    NullRegClasses,
2579
    nullptr
2580
  };
2581
2582
  extern const TargetRegisterClass GeneralSubRegsRegClass = {
2583
    &HexagonMCRegisterClasses[GeneralSubRegsRegClassID],
2584
    GeneralSubRegsSubClassMask,
2585
    SuperRegIdxSeqs + 0,
2586
    LaneBitmask(0x00000001),
2587
    0,
2588
    false, /* HasDisjunctSubRegs */
2589
    false, /* CoveredBySubRegs */
2590
    GeneralSubRegsSuperclasses,
2591
    nullptr
2592
  };
2593
2594
  extern const TargetRegisterClass V62RegsRegClass = {
2595
    &HexagonMCRegisterClasses[V62RegsRegClassID],
2596
    V62RegsSubClassMask,
2597
    SuperRegIdxSeqs + 0,
2598
    LaneBitmask(0x00000003),
2599
    0,
2600
    true, /* HasDisjunctSubRegs */
2601
    false, /* CoveredBySubRegs */
2602
    NullRegClasses,
2603
    nullptr
2604
  };
2605
2606
  extern const TargetRegisterClass IntRegsLow8RegClass = {
2607
    &HexagonMCRegisterClasses[IntRegsLow8RegClassID],
2608
    IntRegsLow8SubClassMask,
2609
    SuperRegIdxSeqs + 0,
2610
    LaneBitmask(0x00000001),
2611
    0,
2612
    false, /* HasDisjunctSubRegs */
2613
    false, /* CoveredBySubRegs */
2614
    IntRegsLow8Superclasses,
2615
    nullptr
2616
  };
2617
2618
  extern const TargetRegisterClass CtrRegs_and_V62RegsRegClass = {
2619
    &HexagonMCRegisterClasses[CtrRegs_and_V62RegsRegClassID],
2620
    CtrRegs_and_V62RegsSubClassMask,
2621
    SuperRegIdxSeqs + 0,
2622
    LaneBitmask(0x00000001),
2623
    0,
2624
    false, /* HasDisjunctSubRegs */
2625
    false, /* CoveredBySubRegs */
2626
    CtrRegs_and_V62RegsSuperclasses,
2627
    nullptr
2628
  };
2629
2630
  extern const TargetRegisterClass PredRegsRegClass = {
2631
    &HexagonMCRegisterClasses[PredRegsRegClassID],
2632
    PredRegsSubClassMask,
2633
    SuperRegIdxSeqs + 2,
2634
    LaneBitmask(0x00000001),
2635
    0,
2636
    false, /* HasDisjunctSubRegs */
2637
    false, /* CoveredBySubRegs */
2638
    NullRegClasses,
2639
    nullptr
2640
  };
2641
2642
  extern const TargetRegisterClass V62Regs_with_isub_hiRegClass = {
2643
    &HexagonMCRegisterClasses[V62Regs_with_isub_hiRegClassID],
2644
    V62Regs_with_isub_hiSubClassMask,
2645
    SuperRegIdxSeqs + 2,
2646
    LaneBitmask(0x00000003),
2647
    0,
2648
    true, /* HasDisjunctSubRegs */
2649
    true, /* CoveredBySubRegs */
2650
    V62Regs_with_isub_hiSuperclasses,
2651
    nullptr
2652
  };
2653
2654
  extern const TargetRegisterClass ModRegsRegClass = {
2655
    &HexagonMCRegisterClasses[ModRegsRegClassID],
2656
    ModRegsSubClassMask,
2657
    SuperRegIdxSeqs + 0,
2658
    LaneBitmask(0x00000001),
2659
    0,
2660
    false, /* HasDisjunctSubRegs */
2661
    false, /* CoveredBySubRegs */
2662
    ModRegsSuperclasses,
2663
    nullptr
2664
  };
2665
2666
  extern const TargetRegisterClass CtrRegs_with_subreg_overflowRegClass = {
2667
    &HexagonMCRegisterClasses[CtrRegs_with_subreg_overflowRegClassID],
2668
    CtrRegs_with_subreg_overflowSubClassMask,
2669
    SuperRegIdxSeqs + 2,
2670
    LaneBitmask(0x00000004),
2671
    0,
2672
    false, /* HasDisjunctSubRegs */
2673
    false, /* CoveredBySubRegs */
2674
    CtrRegs_with_subreg_overflowSuperclasses,
2675
    nullptr
2676
  };
2677
2678
  extern const TargetRegisterClass V65RegsRegClass = {
2679
    &HexagonMCRegisterClasses[V65RegsRegClassID],
2680
    V65RegsSubClassMask,
2681
    SuperRegIdxSeqs + 2,
2682
    LaneBitmask(0x00000001),
2683
    0,
2684
    false, /* HasDisjunctSubRegs */
2685
    false, /* CoveredBySubRegs */
2686
    NullRegClasses,
2687
    nullptr
2688
  };
2689
2690
  extern const TargetRegisterClass DoubleRegsRegClass = {
2691
    &HexagonMCRegisterClasses[DoubleRegsRegClassID],
2692
    DoubleRegsSubClassMask,
2693
    SuperRegIdxSeqs + 2,
2694
    LaneBitmask(0x00000003),
2695
    0,
2696
    true, /* HasDisjunctSubRegs */
2697
    true, /* CoveredBySubRegs */
2698
    NullRegClasses,
2699
    nullptr
2700
  };
2701
2702
  extern const TargetRegisterClass GuestRegs64RegClass = {
2703
    &HexagonMCRegisterClasses[GuestRegs64RegClassID],
2704
    GuestRegs64SubClassMask,
2705
    SuperRegIdxSeqs + 2,
2706
    LaneBitmask(0x00000003),
2707
    0,
2708
    true, /* HasDisjunctSubRegs */
2709
    true, /* CoveredBySubRegs */
2710
    NullRegClasses,
2711
    nullptr
2712
  };
2713
2714
  extern const TargetRegisterClass CtrRegs64RegClass = {
2715
    &HexagonMCRegisterClasses[CtrRegs64RegClassID],
2716
    CtrRegs64SubClassMask,
2717
    SuperRegIdxSeqs + 2,
2718
    LaneBitmask(0x00000003),
2719
    0,
2720
    true, /* HasDisjunctSubRegs */
2721
    true, /* CoveredBySubRegs */
2722
    NullRegClasses,
2723
    nullptr
2724
  };
2725
2726
  extern const TargetRegisterClass GeneralDoubleLow8RegsRegClass = {
2727
    &HexagonMCRegisterClasses[GeneralDoubleLow8RegsRegClassID],
2728
    GeneralDoubleLow8RegsSubClassMask,
2729
    SuperRegIdxSeqs + 2,
2730
    LaneBitmask(0x00000003),
2731
    0,
2732
    true, /* HasDisjunctSubRegs */
2733
    true, /* CoveredBySubRegs */
2734
    GeneralDoubleLow8RegsSuperclasses,
2735
    nullptr
2736
  };
2737
2738
  extern const TargetRegisterClass DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass = {
2739
    &HexagonMCRegisterClasses[DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID],
2740
    DoubleRegs_with_isub_hi_in_IntRegsLow8SubClassMask,
2741
    SuperRegIdxSeqs + 2,
2742
    LaneBitmask(0x00000003),
2743
    0,
2744
    true, /* HasDisjunctSubRegs */
2745
    true, /* CoveredBySubRegs */
2746
    DoubleRegs_with_isub_hi_in_IntRegsLow8Superclasses,
2747
    nullptr
2748
  };
2749
2750
  extern const TargetRegisterClass CtrRegs64_and_V62RegsRegClass = {
2751
    &HexagonMCRegisterClasses[CtrRegs64_and_V62RegsRegClassID],
2752
    CtrRegs64_and_V62RegsSubClassMask,
2753
    SuperRegIdxSeqs + 2,
2754
    LaneBitmask(0x00000003),
2755
    0,
2756
    true, /* HasDisjunctSubRegs */
2757
    true, /* CoveredBySubRegs */
2758
    CtrRegs64_and_V62RegsSuperclasses,
2759
    nullptr
2760
  };
2761
2762
  extern const TargetRegisterClass CtrRegs64_with_isub_hi_in_ModRegsRegClass = {
2763
    &HexagonMCRegisterClasses[CtrRegs64_with_isub_hi_in_ModRegsRegClassID],
2764
    CtrRegs64_with_isub_hi_in_ModRegsSubClassMask,
2765
    SuperRegIdxSeqs + 2,
2766
    LaneBitmask(0x00000003),
2767
    0,
2768
    true, /* HasDisjunctSubRegs */
2769
    true, /* CoveredBySubRegs */
2770
    CtrRegs64_with_isub_hi_in_ModRegsSuperclasses,
2771
    nullptr
2772
  };
2773
2774
  extern const TargetRegisterClass HvxVRRegClass = {
2775
    &HexagonMCRegisterClasses[HvxVRRegClassID],
2776
    HvxVRSubClassMask,
2777
    SuperRegIdxSeqs + 5,
2778
    LaneBitmask(0x00000001),
2779
    0,
2780
    false, /* HasDisjunctSubRegs */
2781
    false, /* CoveredBySubRegs */
2782
    NullRegClasses,
2783
    nullptr
2784
  };
2785
2786
  extern const TargetRegisterClass HvxQRRegClass = {
2787
    &HexagonMCRegisterClasses[HvxQRRegClassID],
2788
    HvxQRSubClassMask,
2789
    SuperRegIdxSeqs + 2,
2790
    LaneBitmask(0x00000001),
2791
    0,
2792
    false, /* HasDisjunctSubRegs */
2793
    false, /* CoveredBySubRegs */
2794
    NullRegClasses,
2795
    nullptr
2796
  };
2797
2798
  extern const TargetRegisterClass HvxVR_and_V65RegsRegClass = {
2799
    &HexagonMCRegisterClasses[HvxVR_and_V65RegsRegClassID],
2800
    HvxVR_and_V65RegsSubClassMask,
2801
    SuperRegIdxSeqs + 2,
2802
    LaneBitmask(0x00000001),
2803
    0,
2804
    false, /* HasDisjunctSubRegs */
2805
    false, /* CoveredBySubRegs */
2806
    HvxVR_and_V65RegsSuperclasses,
2807
    nullptr
2808
  };
2809
2810
  extern const TargetRegisterClass HvxWRRegClass = {
2811
    &HexagonMCRegisterClasses[HvxWRRegClassID],
2812
    HvxWRSubClassMask,
2813
    SuperRegIdxSeqs + 2,
2814
    LaneBitmask(0x00000018),
2815
    0,
2816
    true, /* HasDisjunctSubRegs */
2817
    true, /* CoveredBySubRegs */
2818
    NullRegClasses,
2819
    nullptr
2820
  };
2821
2822
} // end namespace Hexagon
2823
2824
namespace {
2825
  const TargetRegisterClass* const RegisterClasses[] = {
2826
    &Hexagon::UsrBitsRegClass,
2827
    &Hexagon::GuestRegsRegClass,
2828
    &Hexagon::IntRegsRegClass,
2829
    &Hexagon::CtrRegsRegClass,
2830
    &Hexagon::GeneralSubRegsRegClass,
2831
    &Hexagon::V62RegsRegClass,
2832
    &Hexagon::IntRegsLow8RegClass,
2833
    &Hexagon::CtrRegs_and_V62RegsRegClass,
2834
    &Hexagon::PredRegsRegClass,
2835
    &Hexagon::V62Regs_with_isub_hiRegClass,
2836
    &Hexagon::ModRegsRegClass,
2837
    &Hexagon::CtrRegs_with_subreg_overflowRegClass,
2838
    &Hexagon::V65RegsRegClass,
2839
    &Hexagon::DoubleRegsRegClass,
2840
    &Hexagon::GuestRegs64RegClass,
2841
    &Hexagon::CtrRegs64RegClass,
2842
    &Hexagon::GeneralDoubleLow8RegsRegClass,
2843
    &Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass,
2844
    &Hexagon::CtrRegs64_and_V62RegsRegClass,
2845
    &Hexagon::CtrRegs64_with_isub_hi_in_ModRegsRegClass,
2846
    &Hexagon::HvxVRRegClass,
2847
    &Hexagon::HvxQRRegClass,
2848
    &Hexagon::HvxVR_and_V65RegsRegClass,
2849
    &Hexagon::HvxWRRegClass,
2850
  };
2851
} // end anonymous namespace
2852
2853
static const TargetRegisterInfoDesc HexagonRegInfoDesc[] = { // Extra Descriptors
2854
  { 0, false },
2855
  { 0, false },
2856
  { 0, false },
2857
  { 0, false },
2858
  { 0, false },
2859
  { 0, false },
2860
  { 0, false },
2861
  { 0, false },
2862
  { 0, false },
2863
  { 0, false },
2864
  { 0, false },
2865
  { 0, false },
2866
  { 0, false },
2867
  { 0, false },
2868
  { 0, false },
2869
  { 0, false },
2870
  { 0, false },
2871
  { 0, false },
2872
  { 0, false },
2873
  { 0, false },
2874
  { 0, false },
2875
  { 0, false },
2876
  { 0, false },
2877
  { 0, true },
2878
  { 0, false },
2879
  { 0, false },
2880
  { 0, false },
2881
  { 0, false },
2882
  { 0, true },
2883
  { 0, true },
2884
  { 0, true },
2885
  { 0, true },
2886
  { 0, true },
2887
  { 0, true },
2888
  { 0, true },
2889
  { 0, true },
2890
  { 0, true },
2891
  { 0, true },
2892
  { 0, true },
2893
  { 0, true },
2894
  { 0, true },
2895
  { 0, true },
2896
  { 0, true },
2897
  { 0, true },
2898
  { 0, false },
2899
  { 0, false },
2900
  { 0, false },
2901
  { 0, false },
2902
  { 0, false },
2903
  { 0, false },
2904
  { 0, false },
2905
  { 0, false },
2906
  { 0, false },
2907
  { 0, false },
2908
  { 0, false },
2909
  { 0, false },
2910
  { 0, false },
2911
  { 0, false },
2912
  { 0, false },
2913
  { 0, false },
2914
  { 0, false },
2915
  { 0, false },
2916
  { 0, false },
2917
  { 0, false },
2918
  { 0, false },
2919
  { 0, false },
2920
  { 0, false },
2921
  { 0, false },
2922
  { 0, false },
2923
  { 0, false },
2924
  { 0, false },
2925
  { 0, false },
2926
  { 0, false },
2927
  { 0, true },
2928
  { 0, true },
2929
  { 0, true },
2930
  { 0, true },
2931
  { 0, true },
2932
  { 0, true },
2933
  { 0, true },
2934
  { 0, true },
2935
  { 0, true },
2936
  { 0, true },
2937
  { 0, true },
2938
  { 0, true },
2939
  { 0, true },
2940
  { 0, true },
2941
  { 0, true },
2942
  { 0, true },
2943
  { 0, true },
2944
  { 0, true },
2945
  { 0, true },
2946
  { 0, true },
2947
  { 0, true },
2948
  { 0, true },
2949
  { 0, true },
2950
  { 0, true },
2951
  { 0, true },
2952
  { 0, true },
2953
  { 0, true },
2954
  { 0, true },
2955
  { 0, true },
2956
  { 0, true },
2957
  { 0, true },
2958
  { 0, true },
2959
  { 0, true },
2960
  { 0, true },
2961
  { 0, true },
2962
  { 0, true },
2963
  { 0, true },
2964
  { 0, true },
2965
  { 0, true },
2966
  { 0, true },
2967
  { 0, true },
2968
  { 0, true },
2969
  { 0, false },
2970
  { 0, false },
2971
  { 0, true },
2972
  { 0, true },
2973
  { 0, true },
2974
  { 0, true },
2975
  { 0, true },
2976
  { 0, true },
2977
  { 0, true },
2978
  { 0, true },
2979
  { 0, true },
2980
  { 0, true },
2981
  { 0, true },
2982
  { 0, true },
2983
  { 0, true },
2984
  { 0, true },
2985
  { 0, true },
2986
  { 0, true },
2987
  { 0, true },
2988
  { 0, true },
2989
  { 0, true },
2990
  { 0, true },
2991
  { 0, true },
2992
  { 0, true },
2993
  { 0, true },
2994
  { 0, true },
2995
  { 0, true },
2996
  { 0, true },
2997
  { 0, true },
2998
  { 0, true },
2999
  { 0, true },
3000
  { 0, true },
3001
  { 0, true },
3002
  { 0, true },
3003
  { 0, true },
3004
  { 0, true },
3005
  { 0, true },
3006
  { 0, true },
3007
  { 0, true },
3008
  { 0, true },
3009
  { 0, true },
3010
  { 0, true },
3011
  { 0, true },
3012
  { 0, true },
3013
  { 0, true },
3014
  { 0, true },
3015
  { 0, true },
3016
  { 0, true },
3017
  { 0, true },
3018
  { 0, true },
3019
  { 0, false },
3020
  { 0, false },
3021
  { 0, false },
3022
  { 0, false },
3023
  { 0, false },
3024
  { 0, false },
3025
  { 0, false },
3026
  { 0, false },
3027
  { 0, false },
3028
  { 0, false },
3029
  { 0, false },
3030
  { 0, false },
3031
  { 0, false },
3032
  { 0, false },
3033
  { 0, false },
3034
  { 0, false },
3035
  { 0, false },
3036
  { 0, false },
3037
  { 0, false },
3038
  { 0, false },
3039
  { 0, false },
3040
  { 0, false },
3041
  { 0, false },
3042
  { 0, false },
3043
};
3044
0
unsigned HexagonGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
3045
0
  static const uint8_t Rows[1][5] = {
3046
0
    { 0, 0, 0, 0, 0, },
3047
0
  };
3048
0
3049
0
  --IdxA; assert(IdxA < 5);
3050
0
  --IdxB; assert(IdxB < 5);
3051
0
  return Rows[0][IdxB];
3052
0
}
3053
3054
  struct MaskRolOp {
3055
    LaneBitmask Mask;
3056
    uint8_t  RotateLeft;
3057
  };
3058
  static const MaskRolOp LaneMaskComposeSequences[] = {
3059
    { LaneBitmask(0xFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
3060
    { LaneBitmask(0xFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 2
3061
    { LaneBitmask(0xFFFFFFFF),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 4
3062
    { LaneBitmask(0xFFFFFFFF),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 6
3063
    { LaneBitmask(0xFFFFFFFF),  4 }, { LaneBitmask::getNone(), 0 }  // Sequence 8
3064
  };
3065
  static const MaskRolOp *const CompositeSequences[] = {
3066
    &LaneMaskComposeSequences[0], // to isub_hi
3067
    &LaneMaskComposeSequences[2], // to isub_lo
3068
    &LaneMaskComposeSequences[4], // to subreg_overflow
3069
    &LaneMaskComposeSequences[6], // to vsub_hi
3070
    &LaneMaskComposeSequences[8] // to vsub_lo
3071
  };
3072
3073
2.47k
LaneBitmask HexagonGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
3074
2.47k
  --IdxA; assert(IdxA < 5 && "Subregister index out of bounds");
3075
2.47k
  LaneBitmask Result;
3076
4.94k
  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); 
++Ops2.47k
) {
3077
2.47k
    LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
3078
2.47k
    if (unsigned S = Ops->RotateLeft)
3079
2.15k
      Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
3080
314
    else
3081
314
      Result |= LaneBitmask(M);
3082
2.47k
  }
3083
2.47k
  return Result;
3084
2.47k
}
3085
3086
17.8k
LaneBitmask HexagonGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
3087
17.8k
  LaneMask &= getSubRegIndexLaneMask(IdxA);
3088
17.8k
  --IdxA; assert(IdxA < 5 && "Subregister index out of bounds");
3089
17.8k
  LaneBitmask Result;
3090
35.6k
  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); 
++Ops17.8k
) {
3091
17.8k
    LaneBitmask::Type M = LaneMask.getAsInteger();
3092
17.8k
    if (unsigned S = Ops->RotateLeft)
3093
10.5k
      Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
3094
7.34k
    else
3095
7.34k
      Result |= LaneBitmask(M);
3096
17.8k
  }
3097
17.8k
  return Result;
3098
17.8k
}
3099
3100
4.14k
const TargetRegisterClass *HexagonGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
3101
4.14k
  static const uint8_t Table[24][5] = {
3102
4.14k
    { // UsrBits
3103
4.14k
      0,  // isub_hi
3104
4.14k
      0,  // isub_lo
3105
4.14k
      0,  // subreg_overflow
3106
4.14k
      0,  // vsub_hi
3107
4.14k
      0,  // vsub_lo
3108
4.14k
    },
3109
4.14k
    { // GuestRegs
3110
4.14k
      0,  // isub_hi
3111
4.14k
      0,  // isub_lo
3112
4.14k
      0,  // subreg_overflow
3113
4.14k
      0,  // vsub_hi
3114
4.14k
      0,  // vsub_lo
3115
4.14k
    },
3116
4.14k
    { // IntRegs
3117
4.14k
      0,  // isub_hi
3118
4.14k
      0,  // isub_lo
3119
4.14k
      0,  // subreg_overflow
3120
4.14k
      0,  // vsub_hi
3121
4.14k
      0,  // vsub_lo
3122
4.14k
    },
3123
4.14k
    { // CtrRegs
3124
4.14k
      0,  // isub_hi
3125
4.14k
      0,  // isub_lo
3126
4.14k
      12, // subreg_overflow -> CtrRegs_with_subreg_overflow
3127
4.14k
      0,  // vsub_hi
3128
4.14k
      0,  // vsub_lo
3129
4.14k
    },
3130
4.14k
    { // GeneralSubRegs
3131
4.14k
      0,  // isub_hi
3132
4.14k
      0,  // isub_lo
3133
4.14k
      0,  // subreg_overflow
3134
4.14k
      0,  // vsub_hi
3135
4.14k
      0,  // vsub_lo
3136
4.14k
    },
3137
4.14k
    { // V62Regs
3138
4.14k
      10, // isub_hi -> V62Regs_with_isub_hi
3139
4.14k
      10, // isub_lo -> V62Regs_with_isub_hi
3140
4.14k
      0,  // subreg_overflow
3141
4.14k
      0,  // vsub_hi
3142
4.14k
      0,  // vsub_lo
3143
4.14k
    },
3144
4.14k
    { // IntRegsLow8
3145
4.14k
      0,  // isub_hi
3146
4.14k
      0,  // isub_lo
3147
4.14k
      0,  // subreg_overflow
3148
4.14k
      0,  // vsub_hi
3149
4.14k
      0,  // vsub_lo
3150
4.14k
    },
3151
4.14k
    { // CtrRegs_and_V62Regs
3152
4.14k
      0,  // isub_hi
3153
4.14k
      0,  // isub_lo
3154
4.14k
      0,  // subreg_overflow
3155
4.14k
      0,  // vsub_hi
3156
4.14k
      0,  // vsub_lo
3157
4.14k
    },
3158
4.14k
    { // PredRegs
3159
4.14k
      0,  // isub_hi
3160
4.14k
      0,  // isub_lo
3161
4.14k
      0,  // subreg_overflow
3162
4.14k
      0,  // vsub_hi
3163
4.14k
      0,  // vsub_lo
3164
4.14k
    },
3165
4.14k
    { // V62Regs_with_isub_hi
3166
4.14k
      10, // isub_hi -> V62Regs_with_isub_hi
3167
4.14k
      10, // isub_lo -> V62Regs_with_isub_hi
3168
4.14k
      0,  // subreg_overflow
3169
4.14k
      0,  // vsub_hi
3170
4.14k
      0,  // vsub_lo
3171
4.14k
    },
3172
4.14k
    { // ModRegs
3173
4.14k
      0,  // isub_hi
3174
4.14k
      0,  // isub_lo
3175
4.14k
      0,  // subreg_overflow
3176
4.14k
      0,  // vsub_hi
3177
4.14k
      0,  // vsub_lo
3178
4.14k
    },
3179
4.14k
    { // CtrRegs_with_subreg_overflow
3180
4.14k
      0,  // isub_hi
3181
4.14k
      0,  // isub_lo
3182
4.14k
      12, // subreg_overflow -> CtrRegs_with_subreg_overflow
3183
4.14k
      0,  // vsub_hi
3184
4.14k
      0,  // vsub_lo
3185
4.14k
    },
3186
4.14k
    { // V65Regs
3187
4.14k
      0,  // isub_hi
3188
4.14k
      0,  // isub_lo
3189
4.14k
      0,  // subreg_overflow
3190
4.14k
      0,  // vsub_hi
3191
4.14k
      0,  // vsub_lo
3192
4.14k
    },
3193
4.14k
    { // DoubleRegs
3194
4.14k
      14, // isub_hi -> DoubleRegs
3195
4.14k
      14, // isub_lo -> DoubleRegs
3196
4.14k
      0,  // subreg_overflow
3197
4.14k
      0,  // vsub_hi
3198
4.14k
      0,  // vsub_lo
3199
4.14k
    },
3200
4.14k
    { // GuestRegs64
3201
4.14k
      15, // isub_hi -> GuestRegs64
3202
4.14k
      15, // isub_lo -> GuestRegs64
3203
4.14k
      0,  // subreg_overflow
3204
4.14k
      0,  // vsub_hi
3205
4.14k
      0,  // vsub_lo
3206
4.14k
    },
3207
4.14k
    { // CtrRegs64
3208
4.14k
      16, // isub_hi -> CtrRegs64
3209
4.14k
      16, // isub_lo -> CtrRegs64
3210
4.14k
      0,  // subreg_overflow
3211
4.14k
      0,  // vsub_hi
3212
4.14k
      0,  // vsub_lo
3213
4.14k
    },
3214
4.14k
    { // GeneralDoubleLow8Regs
3215
4.14k
      17, // isub_hi -> GeneralDoubleLow8Regs
3216
4.14k
      17, // isub_lo -> GeneralDoubleLow8Regs
3217
4.14k
      0,  // subreg_overflow
3218
4.14k
      0,  // vsub_hi
3219
4.14k
      0,  // vsub_lo
3220
4.14k
    },
3221
4.14k
    { // DoubleRegs_with_isub_hi_in_IntRegsLow8
3222
4.14k
      18, // isub_hi -> DoubleRegs_with_isub_hi_in_IntRegsLow8
3223
4.14k
      18, // isub_lo -> DoubleRegs_with_isub_hi_in_IntRegsLow8
3224
4.14k
      0,  // subreg_overflow
3225
4.14k
      0,  // vsub_hi
3226
4.14k
      0,  // vsub_lo
3227
4.14k
    },
3228
4.14k
    { // CtrRegs64_and_V62Regs
3229
4.14k
      19, // isub_hi -> CtrRegs64_and_V62Regs
3230
4.14k
      19, // isub_lo -> CtrRegs64_and_V62Regs
3231
4.14k
      0,  // subreg_overflow
3232
4.14k
      0,  // vsub_hi
3233
4.14k
      0,  // vsub_lo
3234
4.14k
    },
3235
4.14k
    { // CtrRegs64_with_isub_hi_in_ModRegs
3236
4.14k
      20, // isub_hi -> CtrRegs64_with_isub_hi_in_ModRegs
3237
4.14k
      20, // isub_lo -> CtrRegs64_with_isub_hi_in_ModRegs
3238
4.14k
      0,  // subreg_overflow
3239
4.14k
      0,  // vsub_hi
3240
4.14k
      0,  // vsub_lo
3241
4.14k
    },
3242
4.14k
    { // HvxVR
3243
4.14k
      0,  // isub_hi
3244
4.14k
      0,  // isub_lo
3245
4.14k
      0,  // subreg_overflow
3246
4.14k
      0,  // vsub_hi
3247
4.14k
      0,  // vsub_lo
3248
4.14k
    },
3249
4.14k
    { // HvxQR
3250
4.14k
      0,  // isub_hi
3251
4.14k
      0,  // isub_lo
3252
4.14k
      0,  // subreg_overflow
3253
4.14k
      0,  // vsub_hi
3254
4.14k
      0,  // vsub_lo
3255
4.14k
    },
3256
4.14k
    { // HvxVR_and_V65Regs
3257
4.14k
      0,  // isub_hi
3258
4.14k
      0,  // isub_lo
3259
4.14k
      0,  // subreg_overflow
3260
4.14k
      0,  // vsub_hi
3261
4.14k
      0,  // vsub_lo
3262
4.14k
    },
3263
4.14k
    { // HvxWR
3264
4.14k
      0,  // isub_hi
3265
4.14k
      0,  // isub_lo
3266
4.14k
      0,  // subreg_overflow
3267
4.14k
      24, // vsub_hi -> HvxWR
3268
4.14k
      24, // vsub_lo -> HvxWR
3269
4.14k
    },
3270
4.14k
  };
3271
4.14k
  assert(RC && "Missing regclass");
3272
4.14k
  if (!Idx) 
return RC0
;
3273
4.14k
  --Idx;
3274
4.14k
  assert(Idx < 5 && "Bad subreg");
3275
4.14k
  unsigned TV = Table[RC->getID()][Idx];
3276
4.14k
  return TV ? getRegClass(TV - 1) : 
nullptr0
;
3277
4.14k
}
3278
3279
/// Get the weight in units of pressure for this register class.
3280
const RegClassWeight &HexagonGenRegisterInfo::
3281
361k
getRegClassWeight(const TargetRegisterClass *RC) const {
3282
361k
  static const RegClassWeight RCWeightTable[] = {
3283
361k
    {0, 0},   // UsrBits
3284
361k
    {0, 0},   // GuestRegs
3285
361k
    {1, 32},    // IntRegs
3286
361k
    {0, 6},   // CtrRegs
3287
361k
    {1, 16},    // GeneralSubRegs
3288
361k
    {0, 0},   // V62Regs
3289
361k
    {1, 8},   // IntRegsLow8
3290
361k
    {0, 0},   // CtrRegs_and_V62Regs
3291
361k
    {1, 4},   // PredRegs
3292
361k
    {0, 0},   // V62Regs_with_isub_hi
3293
361k
    {1, 2},   // ModRegs
3294
361k
    {0, 0},   // CtrRegs_with_subreg_overflow
3295
361k
    {1, 1},   // V65Regs
3296
361k
    {2, 32},    // DoubleRegs
3297
361k
    {0, 0},   // GuestRegs64
3298
361k
    {0, 6},   // CtrRegs64
3299
361k
    {2, 16},    // GeneralDoubleLow8Regs
3300
361k
    {2, 8},   // DoubleRegs_with_isub_hi_in_IntRegsLow8
3301
361k
    {0, 0},   // CtrRegs64_and_V62Regs
3302
361k
    {2, 2},   // CtrRegs64_with_isub_hi_in_ModRegs
3303
361k
    {1, 33},    // HvxVR
3304
361k
    {1, 4},   // HvxQR
3305
361k
    {1, 1},   // HvxVR_and_V65Regs
3306
361k
    {2, 32},    // HvxWR
3307
361k
  };
3308
361k
  return RCWeightTable[RC->getID()];
3309
361k
}
3310
3311
/// Get the weight in units of pressure for this register unit.
3312
unsigned HexagonGenRegisterInfo::
3313
66.8k
getRegUnitWeight(unsigned RegUnit) const {
3314
66.8k
  assert(RegUnit < 127 && "invalid register unit");
3315
66.8k
  // All register units have unit weight.
3316
66.8k
  return 1;
3317
66.8k
}
3318
3319
3320
// Get the number of dimensions of register pressure.
3321
28.6k
unsigned HexagonGenRegisterInfo::getNumRegPressureSets() const {
3322
28.6k
  return 8;
3323
28.6k
}
3324
3325
// Get the name of this register unit pressure set.
3326
const char *HexagonGenRegisterInfo::
3327
0
getRegPressureSetName(unsigned Idx) const {
3328
0
  static const char *const PressureNameTable[] = {
3329
0
    "HvxVR_and_V65Regs",
3330
0
    "ModRegs",
3331
0
    "PredRegs",
3332
0
    "HvxQR",
3333
0
    "IntRegsLow8",
3334
0
    "GeneralSubRegs",
3335
0
    "IntRegs",
3336
0
    "HvxVR",
3337
0
  };
3338
0
  return PressureNameTable[Idx];
3339
0
}
3340
3341
// Get the register unit pressure limit for this dimension.
3342
// This limit must be adjusted dynamically for reserved registers.
3343
unsigned HexagonGenRegisterInfo::
3344
42.2k
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
3345
42.2k
  static const uint8_t PressureLimitTable[] = {
3346
42.2k
    1,    // 0: HvxVR_and_V65Regs
3347
42.2k
    2,    // 1: ModRegs
3348
42.2k
    4,    // 2: PredRegs
3349
42.2k
    4,    // 3: HvxQR
3350
42.2k
    8,    // 4: IntRegsLow8
3351
42.2k
    16,   // 5: GeneralSubRegs
3352
42.2k
    32,   // 6: IntRegs
3353
42.2k
    33,   // 7: HvxVR
3354
42.2k
  };
3355
42.2k
  return PressureLimitTable[Idx];
3356
42.2k
}
3357
3358
/// Table of pressure sets per register class or unit.
3359
static const int RCSetsTable[] = {
3360
  /* 0 */ 1, -1,
3361
  /* 2 */ 2, -1,
3362
  /* 4 */ 3, -1,
3363
  /* 6 */ 4, 5, 6, -1,
3364
  /* 10 */ 0, 7, -1,
3365
};
3366
3367
/// Get the dimensions of register pressure impacted by this register class.
3368
/// Returns a -1 terminated array of pressure set IDs
3369
const int* HexagonGenRegisterInfo::
3370
697k
getRegClassPressureSets(const TargetRegisterClass *RC) const {
3371
697k
  static const uint8_t RCSetStartTable[] = {
3372
697k
    1,1,8,1,7,1,6,1,2,1,0,1,1,8,1,1,7,6,1,1,11,4,10,11,};
3373
697k
  return &RCSetsTable[RCSetStartTable[RC->getID()]];
3374
697k
}
3375
3376
/// Get the dimensions of register pressure impacted by this register unit.
3377
/// Returns a -1 terminated array of pressure set IDs
3378
const int* HexagonGenRegisterInfo::
3379
66.8k
getRegUnitPressureSets(unsigned RegUnit) const {
3380
66.8k
  assert(RegUnit < 127 && "invalid register unit");
3381
66.8k
  static const uint8_t RUSetStartTable[] = {
3382
66.8k
    1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,10,1,6,6,6,6,6,6,6,6,8,8,8,8,8,8,8,8,7,7,7,7,7,7,7,7,8,8,8,8,8,8,8,8,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,2,2,2,2,4,4,4,4,1,1,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,};
3383
66.8k
  return &RCSetsTable[RUSetStartTable[RegUnit]];
3384
66.8k
}
3385
3386
extern const MCRegisterDesc HexagonRegDesc[];
3387
extern const MCPhysReg HexagonRegDiffLists[];
3388
extern const LaneBitmask HexagonLaneMaskLists[];
3389
extern const char HexagonRegStrings[];
3390
extern const char HexagonRegClassStrings[];
3391
extern const MCPhysReg HexagonRegUnitRoots[][2];
3392
extern const uint16_t HexagonSubRegIdxLists[];
3393
extern const MCRegisterInfo::SubRegCoveredBits HexagonSubRegIdxRanges[];
3394
extern const uint16_t HexagonRegEncodingTable[];
3395
// Hexagon Dwarf<->LLVM register mappings.
3396
extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0Dwarf2L[];
3397
extern const unsigned HexagonDwarfFlavour0Dwarf2LSize;
3398
3399
extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0Dwarf2L[];
3400
extern const unsigned HexagonEHFlavour0Dwarf2LSize;
3401
3402
extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0L2Dwarf[];
3403
extern const unsigned HexagonDwarfFlavour0L2DwarfSize;
3404
3405
extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0L2Dwarf[];
3406
extern const unsigned HexagonEHFlavour0L2DwarfSize;
3407
3408
HexagonGenRegisterInfo::
3409
HexagonGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
3410
      unsigned PC, unsigned HwMode)
3411
  : TargetRegisterInfo(HexagonRegInfoDesc, RegisterClasses, RegisterClasses+24,
3412
             SubRegIndexNameTable, SubRegIndexLaneMaskTable,
3413
999
             LaneBitmask(0xFFFFFFFB), RegClassInfos, HwMode) {
3414
999
  InitMCRegisterInfo(HexagonRegDesc, 189, RA, PC,
3415
999
                     HexagonMCRegisterClasses, 24,
3416
999
                     HexagonRegUnitRoots,
3417
999
                     127,
3418
999
                     HexagonRegDiffLists,
3419
999
                     HexagonLaneMaskLists,
3420
999
                     HexagonRegStrings,
3421
999
                     HexagonRegClassStrings,
3422
999
                     HexagonSubRegIdxLists,
3423
999
                     6,
3424
999
                     HexagonSubRegIdxRanges,
3425
999
                     HexagonRegEncodingTable);
3426
999
3427
999
  switch (DwarfFlavour) {
3428
999
  default:
3429
0
    llvm_unreachable("Unknown DWARF flavour");
3430
999
  case 0:
3431
999
    mapDwarfRegsToLLVMRegs(HexagonDwarfFlavour0Dwarf2L, HexagonDwarfFlavour0Dwarf2LSize, false);
3432
999
    break;
3433
999
  }
3434
999
  switch (EHFlavour) {
3435
999
  default:
3436
0
    llvm_unreachable("Unknown DWARF flavour");
3437
999
  case 0:
3438
999
    mapDwarfRegsToLLVMRegs(HexagonEHFlavour0Dwarf2L, HexagonEHFlavour0Dwarf2LSize, true);
3439
999
    break;
3440
999
  }
3441
999
  switch (DwarfFlavour) {
3442
999
  default:
3443
0
    llvm_unreachable("Unknown DWARF flavour");
3444
999
  case 0:
3445
999
    mapLLVMRegsToDwarfRegs(HexagonDwarfFlavour0L2Dwarf, HexagonDwarfFlavour0L2DwarfSize, false);
3446
999
    break;
3447
999
  }
3448
999
  switch (EHFlavour) {
3449
999
  default:
3450
0
    llvm_unreachable("Unknown DWARF flavour");
3451
999
  case 0:
3452
999
    mapLLVMRegsToDwarfRegs(HexagonEHFlavour0L2Dwarf, HexagonEHFlavour0L2DwarfSize, true);
3453
999
    break;
3454
999
  }
3455
999
}
3456
3457
static const MCPhysReg HexagonCSR_SaveList[] = { Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 };
3458
static const uint32_t HexagonCSR_RegMask[] = { 0x00000000, 0x000003f0, 0x00000000, 0x00007ff8, 0x00000000, 0x00000000, };
3459
3460
3461
6.68k
ArrayRef<const uint32_t *> HexagonGenRegisterInfo::getRegMasks() const {
3462
6.68k
  static const uint32_t *const Masks[] = {
3463
6.68k
    HexagonCSR_RegMask,
3464
6.68k
  };
3465
6.68k
  return makeArrayRef(Masks);
3466
6.68k
}
3467
3468
4
ArrayRef<const char *> HexagonGenRegisterInfo::getRegMaskNames() const {
3469
4
  static const char *const Names[] = {
3470
4
    "HexagonCSR",
3471
4
  };
3472
4
  return makeArrayRef(Names);
3473
4
}
3474
3475
const HexagonFrameLowering *
3476
24
HexagonGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
3477
24
  return static_cast<const HexagonFrameLowering *>(
3478
24
      MF.getSubtarget().getFrameLowering());
3479
24
}
3480
3481
} // end namespace llvm
3482
3483
#endif // GET_REGINFO_TARGET_DESC
3484