Coverage Report

Created: 2019-02-15 18:59

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Hexagon/HexagonGenRegisterInfo.inc
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Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Register Enum Values                                                *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
#ifdef GET_REGINFO_ENUM
11
#undef GET_REGINFO_ENUM
12
13
namespace llvm {
14
15
class MCRegisterClass;
16
extern const MCRegisterClass HexagonMCRegisterClasses[];
17
18
namespace Hexagon {
19
enum {
20
  NoRegister,
21
  CS = 1,
22
  FRAMEKEY = 2,
23
  FRAMELIMIT = 3,
24
  GELR = 4,
25
  GOSP = 5,
26
  GP = 6,
27
  GPCYCLEHI = 7,
28
  GPCYCLELO = 8,
29
  GSR = 9,
30
  PC = 10,
31
  PKTCOUNT = 11,
32
  PKTCOUNTHI = 12,
33
  PKTCOUNTLO = 13,
34
  UGP = 14,
35
  UPCYCLE = 15,
36
  UPCYCLEHI = 16,
37
  UPCYCLELO = 17,
38
  USR = 18,
39
  USR_OVF = 19,
40
  UTIMER = 20,
41
  UTIMERHI = 21,
42
  UTIMERLO = 22,
43
  VTMP = 23,
44
  C5 = 24,
45
  C8 = 25,
46
  CS0 = 26,
47
  CS1 = 27,
48
  D0 = 28,
49
  D1 = 29,
50
  D2 = 30,
51
  D3 = 31,
52
  D4 = 32,
53
  D5 = 33,
54
  D6 = 34,
55
  D7 = 35,
56
  D8 = 36,
57
  D9 = 37,
58
  D10 = 38,
59
  D11 = 39,
60
  D12 = 40,
61
  D13 = 41,
62
  D14 = 42,
63
  D15 = 43,
64
  G3 = 44,
65
  G4 = 45,
66
  G5 = 46,
67
  G6 = 47,
68
  G7 = 48,
69
  G8 = 49,
70
  G9 = 50,
71
  G10 = 51,
72
  G11 = 52,
73
  G12 = 53,
74
  G13 = 54,
75
  G14 = 55,
76
  G15 = 56,
77
  G20 = 57,
78
  G21 = 58,
79
  G22 = 59,
80
  G23 = 60,
81
  G30 = 61,
82
  G31 = 62,
83
  GPMUCNT0 = 63,
84
  GPMUCNT1 = 64,
85
  GPMUCNT2 = 65,
86
  GPMUCNT3 = 66,
87
  GPMUCNT4 = 67,
88
  GPMUCNT5 = 68,
89
  GPMUCNT6 = 69,
90
  GPMUCNT7 = 70,
91
  LC0 = 71,
92
  LC1 = 72,
93
  M0 = 73,
94
  M1 = 74,
95
  P0 = 75,
96
  P1 = 76,
97
  P2 = 77,
98
  P3 = 78,
99
  Q0 = 79,
100
  Q1 = 80,
101
  Q2 = 81,
102
  Q3 = 82,
103
  R0 = 83,
104
  R1 = 84,
105
  R2 = 85,
106
  R3 = 86,
107
  R4 = 87,
108
  R5 = 88,
109
  R6 = 89,
110
  R7 = 90,
111
  R8 = 91,
112
  R9 = 92,
113
  R10 = 93,
114
  R11 = 94,
115
  R12 = 95,
116
  R13 = 96,
117
  R14 = 97,
118
  R15 = 98,
119
  R16 = 99,
120
  R17 = 100,
121
  R18 = 101,
122
  R19 = 102,
123
  R20 = 103,
124
  R21 = 104,
125
  R22 = 105,
126
  R23 = 106,
127
  R24 = 107,
128
  R25 = 108,
129
  R26 = 109,
130
  R27 = 110,
131
  R28 = 111,
132
  R29 = 112,
133
  R30 = 113,
134
  R31 = 114,
135
  SA0 = 115,
136
  SA1 = 116,
137
  V0 = 117,
138
  V1 = 118,
139
  V2 = 119,
140
  V3 = 120,
141
  V4 = 121,
142
  V5 = 122,
143
  V6 = 123,
144
  V7 = 124,
145
  V8 = 125,
146
  V9 = 126,
147
  V10 = 127,
148
  V11 = 128,
149
  V12 = 129,
150
  V13 = 130,
151
  V14 = 131,
152
  V15 = 132,
153
  V16 = 133,
154
  V17 = 134,
155
  V18 = 135,
156
  V19 = 136,
157
  V20 = 137,
158
  V21 = 138,
159
  V22 = 139,
160
  V23 = 140,
161
  V24 = 141,
162
  V25 = 142,
163
  V26 = 143,
164
  V27 = 144,
165
  V28 = 145,
166
  V29 = 146,
167
  V30 = 147,
168
  V31 = 148,
169
  VQ0 = 149,
170
  VQ1 = 150,
171
  VQ2 = 151,
172
  VQ3 = 152,
173
  VQ4 = 153,
174
  VQ5 = 154,
175
  VQ6 = 155,
176
  VQ7 = 156,
177
  W0 = 157,
178
  W1 = 158,
179
  W2 = 159,
180
  W3 = 160,
181
  W4 = 161,
182
  W5 = 162,
183
  W6 = 163,
184
  W7 = 164,
185
  W8 = 165,
186
  W9 = 166,
187
  W10 = 167,
188
  W11 = 168,
189
  W12 = 169,
190
  W13 = 170,
191
  W14 = 171,
192
  W15 = 172,
193
  C1_0 = 173,
194
  C3_2 = 174,
195
  C5_4 = 175,
196
  C7_6 = 176,
197
  C9_8 = 177,
198
  C11_10 = 178,
199
  C17_16 = 179,
200
  G1_0 = 180,
201
  G3_2 = 181,
202
  G5_4 = 182,
203
  G7_6 = 183,
204
  G9_8 = 184,
205
  G11_10 = 185,
206
  G13_12 = 186,
207
  G15_14 = 187,
208
  G17_16 = 188,
209
  G19_18 = 189,
210
  G21_20 = 190,
211
  G23_22 = 191,
212
  G25_24 = 192,
213
  G27_26 = 193,
214
  G29_28 = 194,
215
  G31_30 = 195,
216
  P3_0 = 196,
217
  NUM_TARGET_REGS   // 197
218
};
219
} // end namespace Hexagon
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// Register classes
222
223
namespace Hexagon {
224
enum {
225
  UsrBitsRegClassID = 0,
226
  GuestRegsRegClassID = 1,
227
  IntRegsRegClassID = 2,
228
  CtrRegsRegClassID = 3,
229
  GeneralSubRegsRegClassID = 4,
230
  V62RegsRegClassID = 5,
231
  IntRegsLow8RegClassID = 6,
232
  CtrRegs_and_V62RegsRegClassID = 7,
233
  PredRegsRegClassID = 8,
234
  V62Regs_with_isub_hiRegClassID = 9,
235
  ModRegsRegClassID = 10,
236
  CtrRegs_with_subreg_overflowRegClassID = 11,
237
  V65RegsRegClassID = 12,
238
  DoubleRegsRegClassID = 13,
239
  GuestRegs64RegClassID = 14,
240
  CtrRegs64RegClassID = 15,
241
  GeneralDoubleLow8RegsRegClassID = 16,
242
  DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID = 17,
243
  CtrRegs64_and_V62RegsRegClassID = 18,
244
  CtrRegs64_with_isub_hi_in_ModRegsRegClassID = 19,
245
  HvxVRRegClassID = 20,
246
  HvxQRRegClassID = 21,
247
  HvxVR_and_V65RegsRegClassID = 22,
248
  HvxWRRegClassID = 23,
249
  HvxVQRRegClassID = 24,
250
251
  };
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} // end namespace Hexagon
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// Subregister indices
256
257
namespace Hexagon {
258
enum {
259
  NoSubRegister,
260
  isub_hi,  // 1
261
  isub_lo,  // 2
262
  subreg_overflow,  // 3
263
  vsub_hi,  // 4
264
  vsub_lo,  // 5
265
  wsub_hi,  // 6
266
  wsub_lo,  // 7
267
  wsub_hi_then_vsub_hi, // 8
268
  wsub_hi_then_vsub_lo, // 9
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  NUM_TARGET_SUBREGS
270
};
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} // end namespace Hexagon
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} // end namespace llvm
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#endif // GET_REGINFO_ENUM
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
278
|*                                                                            *|
279
|* MC Register Information                                                    *|
280
|*                                                                            *|
281
|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
283
\*===----------------------------------------------------------------------===*/
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285
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#ifdef GET_REGINFO_MC_DESC
287
#undef GET_REGINFO_MC_DESC
288
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namespace llvm {
290
291
extern const MCPhysReg HexagonRegDiffLists[] = {
292
  /* 0 */ 0, 0,
293
  /* 2 */ 0, 1, 0,
294
  /* 5 */ 21, 64, 1, 1, 1, 0,
295
  /* 11 */ 85, 1, 1, 1, 0,
296
  /* 16 */ 65035, 1, 1, 1, 0,
297
  /* 21 */ 7, 1, 0,
298
  /* 24 */ 11, 1, 0,
299
  /* 27 */ 14, 1, 0,
300
  /* 30 */ 16, 1, 0,
301
  /* 33 */ 18, 1, 0,
302
  /* 36 */ 25, 1, 0,
303
  /* 39 */ 55, 1, 0,
304
  /* 42 */ 56, 1, 0,
305
  /* 45 */ 57, 1, 0,
306
  /* 48 */ 58, 1, 0,
307
  /* 51 */ 59, 1, 0,
308
  /* 54 */ 60, 1, 0,
309
  /* 57 */ 61, 1, 0,
310
  /* 60 */ 62, 1, 0,
311
  /* 63 */ 63, 1, 0,
312
  /* 66 */ 64, 1, 0,
313
  /* 69 */ 65, 1, 0,
314
  /* 72 */ 66, 1, 0,
315
  /* 75 */ 67, 1, 0,
316
  /* 78 */ 68, 1, 0,
317
  /* 81 */ 69, 1, 0,
318
  /* 84 */ 70, 1, 0,
319
  /* 87 */ 71, 1, 0,
320
  /* 90 */ 83, 1, 0,
321
  /* 93 */ 65180, 1, 0,
322
  /* 96 */ 65223, 1, 0,
323
  /* 99 */ 65227, 1, 0,
324
  /* 102 */ 65237, 1, 0,
325
  /* 105 */ 65317, 1, 0,
326
  /* 108 */ 65399, 1, 0,
327
  /* 111 */ 65400, 1, 0,
328
  /* 114 */ 65401, 1, 0,
329
  /* 117 */ 65402, 1, 0,
330
  /* 120 */ 65403, 1, 0,
331
  /* 123 */ 65404, 1, 0,
332
  /* 126 */ 65406, 1, 0,
333
  /* 129 */ 65407, 1, 0,
334
  /* 132 */ 65415, 1, 0,
335
  /* 135 */ 65416, 1, 0,
336
  /* 138 */ 65433, 1, 0,
337
  /* 141 */ 65496, 1, 0,
338
  /* 144 */ 8, 65496, 1, 40, 65497, 1, 0,
339
  /* 151 */ 65498, 1, 0,
340
  /* 154 */ 9, 65498, 1, 38, 65499, 1, 0,
341
  /* 161 */ 65500, 1, 0,
342
  /* 164 */ 10, 65500, 1, 36, 65501, 1, 0,
343
  /* 171 */ 65502, 1, 0,
344
  /* 174 */ 11, 65502, 1, 34, 65503, 1, 0,
345
  /* 181 */ 65504, 1, 0,
346
  /* 184 */ 12, 65504, 1, 32, 65505, 1, 0,
347
  /* 191 */ 65506, 1, 0,
348
  /* 194 */ 13, 65506, 1, 30, 65507, 1, 0,
349
  /* 201 */ 65508, 1, 0,
350
  /* 204 */ 14, 65508, 1, 28, 65509, 1, 0,
351
  /* 211 */ 65510, 1, 0,
352
  /* 214 */ 15, 65510, 1, 26, 65511, 1, 0,
353
  /* 221 */ 65360, 5, 0,
354
  /* 224 */ 6, 7, 0,
355
  /* 227 */ 10, 7, 0,
356
  /* 230 */ 10, 0,
357
  /* 232 */ 65444, 12, 0,
358
  /* 235 */ 14, 0,
359
  /* 237 */ 15, 0,
360
  /* 239 */ 16, 0,
361
  /* 241 */ 17, 0,
362
  /* 243 */ 19, 0,
363
  /* 245 */ 65360, 39, 0,
364
  /* 248 */ 65360, 49, 0,
365
  /* 251 */ 58, 0,
366
  /* 253 */ 102, 0,
367
  /* 255 */ 103, 0,
368
  /* 257 */ 119, 0,
369
  /* 259 */ 120, 0,
370
  /* 261 */ 121, 0,
371
  /* 263 */ 128, 0,
372
  /* 265 */ 129, 0,
373
  /* 267 */ 130, 0,
374
  /* 269 */ 131, 0,
375
  /* 271 */ 132, 0,
376
  /* 273 */ 133, 0,
377
  /* 275 */ 134, 0,
378
  /* 277 */ 135, 0,
379
  /* 279 */ 136, 0,
380
  /* 281 */ 137, 0,
381
  /* 283 */ 151, 0,
382
  /* 285 */ 152, 0,
383
  /* 287 */ 164, 0,
384
  /* 289 */ 167, 0,
385
  /* 291 */ 171, 0,
386
  /* 293 */ 172, 0,
387
  /* 295 */ 176, 0,
388
  /* 297 */ 177, 0,
389
  /* 299 */ 184, 0,
390
  /* 301 */ 185, 0,
391
  /* 303 */ 21, 65364, 0,
392
  /* 306 */ 65465, 0,
393
  /* 308 */ 65466, 0,
394
  /* 310 */ 65467, 0,
395
  /* 312 */ 65468, 0,
396
  /* 314 */ 65469, 0,
397
  /* 316 */ 65470, 0,
398
  /* 318 */ 65471, 0,
399
  /* 320 */ 65472, 0,
400
  /* 322 */ 65473, 0,
401
  /* 324 */ 65474, 0,
402
  /* 326 */ 65475, 0,
403
  /* 328 */ 65476, 0,
404
  /* 330 */ 65477, 0,
405
  /* 332 */ 65478, 0,
406
  /* 334 */ 65479, 0,
407
  /* 336 */ 65480, 0,
408
  /* 338 */ 65481, 0,
409
  /* 340 */ 65478, 65492, 0,
410
  /* 343 */ 65510, 0,
411
  /* 345 */ 65511, 0,
412
  /* 347 */ 65514, 0,
413
  /* 349 */ 65515, 0,
414
  /* 351 */ 24, 65520, 0,
415
  /* 354 */ 25, 65520, 0,
416
  /* 357 */ 25, 65521, 0,
417
  /* 360 */ 26, 65521, 0,
418
  /* 363 */ 27, 65521, 0,
419
  /* 366 */ 65384, 65521, 0,
420
  /* 369 */ 27, 65522, 0,
421
  /* 372 */ 28, 65522, 0,
422
  /* 375 */ 29, 65522, 0,
423
  /* 378 */ 29, 65523, 0,
424
  /* 381 */ 30, 65523, 0,
425
  /* 384 */ 31, 65523, 0,
426
  /* 387 */ 31, 65524, 0,
427
  /* 390 */ 32, 65524, 0,
428
  /* 393 */ 33, 65524, 0,
429
  /* 396 */ 33, 65525, 0,
430
  /* 399 */ 34, 65525, 0,
431
  /* 402 */ 35, 65525, 0,
432
  /* 405 */ 35, 65526, 0,
433
  /* 408 */ 36, 65526, 0,
434
  /* 411 */ 37, 65526, 0,
435
  /* 414 */ 37, 65527, 0,
436
  /* 417 */ 38, 65527, 0,
437
  /* 420 */ 39, 65527, 0,
438
  /* 423 */ 39, 65528, 0,
439
  /* 426 */ 40, 65528, 0,
440
  /* 429 */ 65372, 65528, 0,
441
  /* 432 */ 65533, 0,
442
  /* 434 */ 65534, 0,
443
  /* 436 */ 2, 65535, 0,
444
  /* 439 */ 65352, 65535, 0,
445
  /* 442 */ 65360, 65535, 0,
446
};
447
448
extern const LaneBitmask HexagonLaneMaskLists[] = {
449
  /* 0 */ LaneBitmask(0x00000000), LaneBitmask(0x00000000), LaneBitmask(0x00000000), LaneBitmask(0x00000000), LaneBitmask::getAll(),
450
  /* 5 */ LaneBitmask(0x00000004), LaneBitmask(0x00000000), LaneBitmask::getAll(),
451
  /* 8 */ LaneBitmask(0x00000002), LaneBitmask(0x00000001), LaneBitmask::getAll(),
452
  /* 11 */ LaneBitmask(0x00000001), LaneBitmask(0x00000002), LaneBitmask::getAll(),
453
  /* 14 */ LaneBitmask(0x00000001), LaneBitmask(0x00000002), LaneBitmask(0x00000002), LaneBitmask(0x00000002), LaneBitmask(0x00000002), LaneBitmask::getAll(),
454
  /* 20 */ LaneBitmask(0x00000010), LaneBitmask(0x00000008), LaneBitmask::getAll(),
455
  /* 23 */ LaneBitmask(0x00000010), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000020), LaneBitmask::getAll(),
456
};
457
458
extern const uint16_t HexagonSubRegIdxLists[] = {
459
  /* 0 */ 2, 1, 0,
460
  /* 3 */ 3, 0,
461
  /* 5 */ 5, 4, 0,
462
  /* 8 */ 7, 5, 4, 6, 9, 8, 0,
463
};
464
465
extern const MCRegisterInfo::SubRegCoveredBits HexagonSubRegIdxRanges[] = {
466
  { 65535, 65535 },
467
  { 32, 32 }, // isub_hi
468
  { 0, 32 },  // isub_lo
469
  { 0, 1 }, // subreg_overflow
470
  { 512, 512 }, // vsub_hi
471
  { 0, 512 }, // vsub_lo
472
  { 1024, 1024 }, // wsub_hi
473
  { 0, 1024 },  // wsub_lo
474
  { 1536, 512 },  // wsub_hi_then_vsub_hi
475
  { 1024, 512 },  // wsub_hi_then_vsub_lo
476
};
477
478
extern const char HexagonRegStrings[] = {
479
  /* 0 */ 'D', '1', '0', 0,
480
  /* 4 */ 'G', '1', '0', 0,
481
  /* 8 */ 'R', '1', '0', 0,
482
  /* 12 */ 'V', '1', '0', 0,
483
  /* 16 */ 'W', '1', '0', 0,
484
  /* 20 */ 'C', '1', '1', '_', '1', '0', 0,
485
  /* 27 */ 'G', '1', '1', '_', '1', '0', 0,
486
  /* 34 */ 'G', '2', '0', 0,
487
  /* 38 */ 'R', '2', '0', 0,
488
  /* 42 */ 'V', '2', '0', 0,
489
  /* 46 */ 'G', '2', '1', '_', '2', '0', 0,
490
  /* 53 */ 'G', '3', '0', 0,
491
  /* 57 */ 'R', '3', '0', 0,
492
  /* 61 */ 'V', '3', '0', 0,
493
  /* 65 */ 'G', '3', '1', '_', '3', '0', 0,
494
  /* 72 */ 'S', 'A', '0', 0,
495
  /* 76 */ 'L', 'C', '0', 0,
496
  /* 80 */ 'D', '0', 0,
497
  /* 83 */ 'M', '0', 0,
498
  /* 86 */ 'P', '0', 0,
499
  /* 89 */ 'V', 'Q', '0', 0,
500
  /* 93 */ 'R', '0', 0,
501
  /* 96 */ 'C', 'S', '0', 0,
502
  /* 100 */ 'G', 'P', 'M', 'U', 'C', 'N', 'T', '0', 0,
503
  /* 109 */ 'V', '0', 0,
504
  /* 112 */ 'W', '0', 0,
505
  /* 115 */ 'C', '1', '_', '0', 0,
506
  /* 120 */ 'G', '1', '_', '0', 0,
507
  /* 125 */ 'P', '3', '_', '0', 0,
508
  /* 130 */ 'D', '1', '1', 0,
509
  /* 134 */ 'G', '1', '1', 0,
510
  /* 138 */ 'R', '1', '1', 0,
511
  /* 142 */ 'V', '1', '1', 0,
512
  /* 146 */ 'W', '1', '1', 0,
513
  /* 150 */ 'G', '2', '1', 0,
514
  /* 154 */ 'R', '2', '1', 0,
515
  /* 158 */ 'V', '2', '1', 0,
516
  /* 162 */ 'G', '3', '1', 0,
517
  /* 166 */ 'R', '3', '1', 0,
518
  /* 170 */ 'V', '3', '1', 0,
519
  /* 174 */ 'S', 'A', '1', 0,
520
  /* 178 */ 'L', 'C', '1', 0,
521
  /* 182 */ 'D', '1', 0,
522
  /* 185 */ 'M', '1', 0,
523
  /* 188 */ 'P', '1', 0,
524
  /* 191 */ 'V', 'Q', '1', 0,
525
  /* 195 */ 'R', '1', 0,
526
  /* 198 */ 'C', 'S', '1', 0,
527
  /* 202 */ 'G', 'P', 'M', 'U', 'C', 'N', 'T', '1', 0,
528
  /* 211 */ 'V', '1', 0,
529
  /* 214 */ 'W', '1', 0,
530
  /* 217 */ 'D', '1', '2', 0,
531
  /* 221 */ 'G', '1', '2', 0,
532
  /* 225 */ 'R', '1', '2', 0,
533
  /* 229 */ 'V', '1', '2', 0,
534
  /* 233 */ 'W', '1', '2', 0,
535
  /* 237 */ 'G', '1', '3', '_', '1', '2', 0,
536
  /* 244 */ 'G', '2', '2', 0,
537
  /* 248 */ 'R', '2', '2', 0,
538
  /* 252 */ 'V', '2', '2', 0,
539
  /* 256 */ 'G', '2', '3', '_', '2', '2', 0,
540
  /* 263 */ 'D', '2', 0,
541
  /* 266 */ 'P', '2', 0,
542
  /* 269 */ 'V', 'Q', '2', 0,
543
  /* 273 */ 'R', '2', 0,
544
  /* 276 */ 'G', 'P', 'M', 'U', 'C', 'N', 'T', '2', 0,
545
  /* 285 */ 'V', '2', 0,
546
  /* 288 */ 'W', '2', 0,
547
  /* 291 */ 'C', '3', '_', '2', 0,
548
  /* 296 */ 'G', '3', '_', '2', 0,
549
  /* 301 */ 'D', '1', '3', 0,
550
  /* 305 */ 'G', '1', '3', 0,
551
  /* 309 */ 'R', '1', '3', 0,
552
  /* 313 */ 'V', '1', '3', 0,
553
  /* 317 */ 'W', '1', '3', 0,
554
  /* 321 */ 'G', '2', '3', 0,
555
  /* 325 */ 'R', '2', '3', 0,
556
  /* 329 */ 'V', '2', '3', 0,
557
  /* 333 */ 'D', '3', 0,
558
  /* 336 */ 'G', '3', 0,
559
  /* 339 */ 'P', '3', 0,
560
  /* 342 */ 'V', 'Q', '3', 0,
561
  /* 346 */ 'R', '3', 0,
562
  /* 349 */ 'G', 'P', 'M', 'U', 'C', 'N', 'T', '3', 0,
563
  /* 358 */ 'V', '3', 0,
564
  /* 361 */ 'W', '3', 0,
565
  /* 364 */ 'D', '1', '4', 0,
566
  /* 368 */ 'G', '1', '4', 0,
567
  /* 372 */ 'R', '1', '4', 0,
568
  /* 376 */ 'V', '1', '4', 0,
569
  /* 380 */ 'W', '1', '4', 0,
570
  /* 384 */ 'G', '1', '5', '_', '1', '4', 0,
571
  /* 391 */ 'R', '2', '4', 0,
572
  /* 395 */ 'V', '2', '4', 0,
573
  /* 399 */ 'G', '2', '5', '_', '2', '4', 0,
574
  /* 406 */ 'D', '4', 0,
575
  /* 409 */ 'G', '4', 0,
576
  /* 412 */ 'V', 'Q', '4', 0,
577
  /* 416 */ 'R', '4', 0,
578
  /* 419 */ 'G', 'P', 'M', 'U', 'C', 'N', 'T', '4', 0,
579
  /* 428 */ 'V', '4', 0,
580
  /* 431 */ 'W', '4', 0,
581
  /* 434 */ 'C', '5', '_', '4', 0,
582
  /* 439 */ 'G', '5', '_', '4', 0,
583
  /* 444 */ 'D', '1', '5', 0,
584
  /* 448 */ 'G', '1', '5', 0,
585
  /* 452 */ 'R', '1', '5', 0,
586
  /* 456 */ 'V', '1', '5', 0,
587
  /* 460 */ 'W', '1', '5', 0,
588
  /* 464 */ 'R', '2', '5', 0,
589
  /* 468 */ 'V', '2', '5', 0,
590
  /* 472 */ 'C', '5', 0,
591
  /* 475 */ 'D', '5', 0,
592
  /* 478 */ 'G', '5', 0,
593
  /* 481 */ 'V', 'Q', '5', 0,
594
  /* 485 */ 'R', '5', 0,
595
  /* 488 */ 'G', 'P', 'M', 'U', 'C', 'N', 'T', '5', 0,
596
  /* 497 */ 'V', '5', 0,
597
  /* 500 */ 'W', '5', 0,
598
  /* 503 */ 'R', '1', '6', 0,
599
  /* 507 */ 'V', '1', '6', 0,
600
  /* 511 */ 'C', '1', '7', '_', '1', '6', 0,
601
  /* 518 */ 'G', '1', '7', '_', '1', '6', 0,
602
  /* 525 */ 'R', '2', '6', 0,
603
  /* 529 */ 'V', '2', '6', 0,
604
  /* 533 */ 'G', '2', '7', '_', '2', '6', 0,
605
  /* 540 */ 'D', '6', 0,
606
  /* 543 */ 'G', '6', 0,
607
  /* 546 */ 'V', 'Q', '6', 0,
608
  /* 550 */ 'R', '6', 0,
609
  /* 553 */ 'G', 'P', 'M', 'U', 'C', 'N', 'T', '6', 0,
610
  /* 562 */ 'V', '6', 0,
611
  /* 565 */ 'W', '6', 0,
612
  /* 568 */ 'C', '7', '_', '6', 0,
613
  /* 573 */ 'G', '7', '_', '6', 0,
614
  /* 578 */ 'R', '1', '7', 0,
615
  /* 582 */ 'V', '1', '7', 0,
616
  /* 586 */ 'R', '2', '7', 0,
617
  /* 590 */ 'V', '2', '7', 0,
618
  /* 594 */ 'D', '7', 0,
619
  /* 597 */ 'G', '7', 0,
620
  /* 600 */ 'V', 'Q', '7', 0,
621
  /* 604 */ 'R', '7', 0,
622
  /* 607 */ 'G', 'P', 'M', 'U', 'C', 'N', 'T', '7', 0,
623
  /* 616 */ 'V', '7', 0,
624
  /* 619 */ 'W', '7', 0,
625
  /* 622 */ 'R', '1', '8', 0,
626
  /* 626 */ 'V', '1', '8', 0,
627
  /* 630 */ 'G', '1', '9', '_', '1', '8', 0,
628
  /* 637 */ 'R', '2', '8', 0,
629
  /* 641 */ 'V', '2', '8', 0,
630
  /* 645 */ 'G', '2', '9', '_', '2', '8', 0,
631
  /* 652 */ 'C', '8', 0,
632
  /* 655 */ 'D', '8', 0,
633
  /* 658 */ 'G', '8', 0,
634
  /* 661 */ 'R', '8', 0,
635
  /* 664 */ 'V', '8', 0,
636
  /* 667 */ 'W', '8', 0,
637
  /* 670 */ 'C', '9', '_', '8', 0,
638
  /* 675 */ 'G', '9', '_', '8', 0,
639
  /* 680 */ 'R', '1', '9', 0,
640
  /* 684 */ 'V', '1', '9', 0,
641
  /* 688 */ 'R', '2', '9', 0,
642
  /* 692 */ 'V', '2', '9', 0,
643
  /* 696 */ 'D', '9', 0,
644
  /* 699 */ 'G', '9', 0,
645
  /* 702 */ 'R', '9', 0,
646
  /* 705 */ 'V', '9', 0,
647
  /* 708 */ 'W', '9', 0,
648
  /* 711 */ 'P', 'C', 0,
649
  /* 714 */ 'U', 'P', 'C', 'Y', 'C', 'L', 'E', 0,
650
  /* 722 */ 'U', 'S', 'R', '_', 'O', 'V', 'F', 0,
651
  /* 730 */ 'G', 'P', 'C', 'Y', 'C', 'L', 'E', 'H', 'I', 0,
652
  /* 740 */ 'U', 'P', 'C', 'Y', 'C', 'L', 'E', 'H', 'I', 0,
653
  /* 750 */ 'U', 'T', 'I', 'M', 'E', 'R', 'H', 'I', 0,
654
  /* 759 */ 'P', 'K', 'T', 'C', 'O', 'U', 'N', 'T', 'H', 'I', 0,
655
  /* 770 */ 'G', 'P', 'C', 'Y', 'C', 'L', 'E', 'L', 'O', 0,
656
  /* 780 */ 'U', 'P', 'C', 'Y', 'C', 'L', 'E', 'L', 'O', 0,
657
  /* 790 */ 'U', 'T', 'I', 'M', 'E', 'R', 'L', 'O', 0,
658
  /* 799 */ 'P', 'K', 'T', 'C', 'O', 'U', 'N', 'T', 'L', 'O', 0,
659
  /* 810 */ 'U', 'G', 'P', 0,
660
  /* 814 */ 'V', 'T', 'M', 'P', 0,
661
  /* 819 */ 'G', 'O', 'S', 'P', 0,
662
  /* 824 */ 'U', 'T', 'I', 'M', 'E', 'R', 0,
663
  /* 831 */ 'G', 'E', 'L', 'R', 0,
664
  /* 836 */ 'G', 'S', 'R', 0,
665
  /* 840 */ 'U', 'S', 'R', 0,
666
  /* 844 */ 'C', 'S', 0,
667
  /* 847 */ 'F', 'R', 'A', 'M', 'E', 'L', 'I', 'M', 'I', 'T', 0,
668
  /* 858 */ 'P', 'K', 'T', 'C', 'O', 'U', 'N', 'T', 0,
669
  /* 867 */ 'F', 'R', 'A', 'M', 'E', 'K', 'E', 'Y', 0,
670
};
671
672
extern const MCRegisterDesc HexagonRegDesc[] = { // Descriptors
673
  { 3, 0, 0, 0, 0, 0 },
674
  { 844, 36, 1, 0, 32, 8 },
675
  { 867, 1, 297, 2, 1, 3 },
676
  { 847, 1, 295, 2, 1, 3 },
677
  { 831, 1, 295, 2, 1, 3 },
678
  { 819, 1, 295, 2, 1, 3 },
679
  { 811, 1, 293, 2, 1, 3 },
680
  { 730, 1, 301, 2, 1, 3 },
681
  { 770, 1, 299, 2, 1, 3 },
682
  { 836, 1, 291, 2, 1, 3 },
683
  { 711, 1, 289, 2, 1, 3 },
684
  { 858, 436, 1, 0, 384, 8 },
685
  { 759, 1, 437, 2, 3728, 3 },
686
  { 799, 1, 434, 2, 5730, 3 },
687
  { 810, 1, 287, 2, 5730, 3 },
688
  { 714, 436, 1, 0, 432, 8 },
689
  { 740, 1, 437, 2, 3792, 3 },
690
  { 780, 1, 434, 2, 3760, 3 },
691
  { 840, 3, 1, 3, 480, 5 },
692
  { 722, 1, 437, 2, 3824, 3 },
693
  { 824, 436, 1, 0, 528, 8 },
694
  { 750, 1, 437, 2, 3888, 3 },
695
  { 790, 1, 434, 2, 5490, 3 },
696
  { 814, 1, 1, 2, 6913, 3 },
697
  { 472, 1, 283, 2, 6913, 3 },
698
  { 652, 1, 285, 2, 3856, 3 },
699
  { 96, 1, 345, 2, 5489, 3 },
700
  { 198, 1, 343, 2, 5489, 3 },
701
  { 80, 39, 1, 0, 2738, 8 },
702
  { 182, 42, 1, 0, 2738, 8 },
703
  { 263, 45, 1, 0, 2738, 8 },
704
  { 333, 48, 1, 0, 2738, 8 },
705
  { 406, 51, 1, 0, 2738, 8 },
706
  { 475, 54, 1, 0, 2738, 8 },
707
  { 540, 57, 1, 0, 2738, 8 },
708
  { 594, 60, 1, 0, 2738, 8 },
709
  { 655, 63, 1, 0, 2738, 8 },
710
  { 696, 66, 1, 0, 2738, 8 },
711
  { 0, 69, 1, 0, 2738, 8 },
712
  { 130, 72, 1, 0, 2738, 8 },
713
  { 217, 75, 1, 0, 2738, 8 },
714
  { 301, 78, 1, 0, 2738, 8 },
715
  { 364, 81, 1, 0, 2738, 8 },
716
  { 444, 84, 1, 0, 2738, 8 },
717
  { 336, 1, 281, 2, 3681, 3 },
718
  { 409, 1, 281, 2, 3681, 3 },
719
  { 478, 1, 279, 2, 3681, 3 },
720
  { 543, 1, 279, 2, 3681, 3 },
721
  { 597, 1, 277, 2, 3681, 3 },
722
  { 658, 1, 277, 2, 3681, 3 },
723
  { 699, 1, 275, 2, 3681, 3 },
724
  { 4, 1, 275, 2, 3681, 3 },
725
  { 134, 1, 273, 2, 3681, 3 },
726
  { 221, 1, 273, 2, 3681, 3 },
727
  { 305, 1, 271, 2, 3681, 3 },
728
  { 368, 1, 271, 2, 3681, 3 },
729
  { 448, 1, 269, 2, 3681, 3 },
730
  { 34, 1, 273, 2, 3681, 3 },
731
  { 150, 1, 271, 2, 3681, 3 },
732
  { 244, 1, 271, 2, 3681, 3 },
733
  { 321, 1, 269, 2, 3681, 3 },
734
  { 53, 1, 275, 2, 3681, 3 },
735
  { 162, 1, 273, 2, 3681, 3 },
736
  { 100, 1, 267, 2, 3681, 3 },
737
  { 202, 1, 265, 2, 3681, 3 },
738
  { 276, 1, 265, 2, 3681, 3 },
739
  { 349, 1, 263, 2, 3681, 3 },
740
  { 419, 1, 261, 2, 3681, 3 },
741
  { 488, 1, 259, 2, 3681, 3 },
742
  { 553, 1, 259, 2, 3681, 3 },
743
  { 607, 1, 257, 2, 3681, 3 },
744
  { 76, 1, 253, 2, 3681, 3 },
745
  { 178, 1, 253, 2, 3681, 3 },
746
  { 83, 1, 255, 2, 3681, 3 },
747
  { 185, 1, 253, 2, 3681, 3 },
748
  { 86, 1, 1, 2, 3681, 3 },
749
  { 188, 1, 1, 2, 3681, 3 },
750
  { 266, 1, 1, 2, 3681, 3 },
751
  { 339, 1, 1, 2, 3681, 3 },
752
  { 90, 1, 1, 2, 3681, 3 },
753
  { 192, 1, 1, 2, 3681, 3 },
754
  { 270, 1, 1, 2, 3681, 3 },
755
  { 343, 1, 1, 2, 3681, 3 },
756
  { 93, 1, 338, 2, 5217, 3 },
757
  { 195, 1, 336, 2, 5217, 3 },
758
  { 273, 1, 336, 2, 5217, 3 },
759
  { 346, 1, 334, 2, 5217, 3 },
760
  { 416, 1, 334, 2, 5217, 3 },
761
  { 485, 1, 332, 2, 5217, 3 },
762
  { 550, 1, 332, 2, 5217, 3 },
763
  { 604, 1, 330, 2, 5217, 3 },
764
  { 661, 1, 330, 2, 5217, 3 },
765
  { 702, 1, 328, 2, 5217, 3 },
766
  { 8, 1, 328, 2, 5217, 3 },
767
  { 138, 1, 326, 2, 5217, 3 },
768
  { 225, 1, 326, 2, 5217, 3 },
769
  { 309, 1, 324, 2, 5217, 3 },
770
  { 372, 1, 324, 2, 5217, 3 },
771
  { 452, 1, 322, 2, 5217, 3 },
772
  { 503, 1, 322, 2, 5217, 3 },
773
  { 578, 1, 320, 2, 5217, 3 },
774
  { 622, 1, 320, 2, 5217, 3 },
775
  { 680, 1, 318, 2, 5217, 3 },
776
  { 38, 1, 318, 2, 5217, 3 },
777
  { 154, 1, 316, 2, 5217, 3 },
778
  { 248, 1, 316, 2, 5217, 3 },
779
  { 325, 1, 314, 2, 5217, 3 },
780
  { 391, 1, 314, 2, 5217, 3 },
781
  { 464, 1, 312, 2, 5217, 3 },
782
  { 525, 1, 312, 2, 5217, 3 },
783
  { 586, 1, 310, 2, 5217, 3 },
784
  { 637, 1, 310, 2, 5217, 3 },
785
  { 688, 1, 308, 2, 5217, 3 },
786
  { 57, 1, 308, 2, 5217, 3 },
787
  { 166, 1, 306, 2, 5217, 3 },
788
  { 72, 1, 251, 2, 5553, 3 },
789
  { 174, 1, 251, 2, 5553, 3 },
790
  { 109, 1, 426, 2, 5553, 3 },
791
  { 211, 1, 423, 2, 5553, 3 },
792
  { 285, 1, 420, 2, 5553, 3 },
793
  { 358, 1, 417, 2, 5553, 3 },
794
  { 428, 1, 417, 2, 5553, 3 },
795
  { 497, 1, 414, 2, 5553, 3 },
796
  { 562, 1, 411, 2, 5553, 3 },
797
  { 616, 1, 408, 2, 5553, 3 },
798
  { 664, 1, 408, 2, 5553, 3 },
799
  { 705, 1, 405, 2, 5553, 3 },
800
  { 12, 1, 402, 2, 5553, 3 },
801
  { 142, 1, 399, 2, 5553, 3 },
802
  { 229, 1, 399, 2, 5553, 3 },
803
  { 313, 1, 396, 2, 5553, 3 },
804
  { 376, 1, 393, 2, 5553, 3 },
805
  { 456, 1, 390, 2, 5553, 3 },
806
  { 507, 1, 390, 2, 5553, 3 },
807
  { 582, 1, 387, 2, 5553, 3 },
808
  { 626, 1, 384, 2, 5553, 3 },
809
  { 684, 1, 381, 2, 5553, 3 },
810
  { 42, 1, 381, 2, 5553, 3 },
811
  { 158, 1, 378, 2, 5553, 3 },
812
  { 252, 1, 375, 2, 5553, 3 },
813
  { 329, 1, 372, 2, 5553, 3 },
814
  { 395, 1, 372, 2, 5553, 3 },
815
  { 468, 1, 369, 2, 5553, 3 },
816
  { 529, 1, 363, 2, 5553, 3 },
817
  { 590, 1, 360, 2, 5553, 3 },
818
  { 641, 1, 360, 2, 5553, 3 },
819
  { 692, 1, 357, 2, 5553, 3 },
820
  { 61, 1, 354, 2, 5553, 3 },
821
  { 170, 1, 351, 2, 5553, 3 },
822
  { 89, 144, 1, 8, 260, 23 },
823
  { 191, 154, 1, 8, 260, 23 },
824
  { 269, 164, 1, 8, 260, 23 },
825
  { 342, 174, 1, 8, 260, 23 },
826
  { 412, 184, 1, 8, 260, 23 },
827
  { 481, 194, 1, 8, 260, 23 },
828
  { 546, 204, 1, 8, 260, 23 },
829
  { 600, 214, 1, 8, 260, 23 },
830
  { 112, 141, 424, 5, 1682, 20 },
831
  { 214, 148, 415, 5, 1682, 20 },
832
  { 288, 151, 415, 5, 1682, 20 },
833
  { 361, 158, 406, 5, 1682, 20 },
834
  { 431, 161, 406, 5, 1682, 20 },
835
  { 500, 168, 397, 5, 1682, 20 },
836
  { 565, 171, 397, 5, 1682, 20 },
837
  { 619, 178, 388, 5, 1682, 20 },
838
  { 667, 181, 388, 5, 1682, 20 },
839
  { 708, 188, 379, 5, 1682, 20 },
840
  { 16, 191, 379, 5, 1682, 20 },
841
  { 146, 198, 370, 5, 1682, 20 },
842
  { 233, 201, 370, 5, 1682, 20 },
843
  { 317, 208, 358, 5, 1682, 20 },
844
  { 380, 211, 358, 5, 1682, 20 },
845
  { 460, 218, 352, 5, 1682, 20 },
846
  { 115, 340, 1, 0, 3713, 11 },
847
  { 291, 340, 1, 0, 3713, 11 },
848
  { 434, 303, 1, 0, 80, 14 },
849
  { 568, 138, 1, 0, 1440, 8 },
850
  { 670, 366, 1, 0, 3632, 11 },
851
  { 20, 429, 1, 0, 3584, 11 },
852
  { 511, 442, 1, 0, 1490, 11 },
853
  { 120, 221, 1, 0, 3537, 8 },
854
  { 296, 245, 1, 0, 3969, 8 },
855
  { 439, 108, 1, 0, 1586, 8 },
856
  { 573, 111, 1, 0, 1586, 8 },
857
  { 675, 114, 1, 0, 1586, 8 },
858
  { 27, 117, 1, 0, 1586, 8 },
859
  { 237, 120, 1, 0, 1586, 8 },
860
  { 384, 123, 1, 0, 1586, 8 },
861
  { 518, 132, 1, 0, 1634, 8 },
862
  { 630, 135, 1, 0, 1634, 8 },
863
  { 46, 120, 1, 0, 1538, 8 },
864
  { 256, 123, 1, 0, 1538, 8 },
865
  { 399, 439, 1, 0, 336, 11 },
866
  { 533, 126, 1, 0, 1538, 8 },
867
  { 645, 129, 1, 0, 1538, 8 },
868
  { 65, 117, 1, 0, 1392, 8 },
869
  { 125, 1, 349, 2, 176, 0 },
870
};
871
872
extern const MCPhysReg HexagonRegUnitRoots[][2] = {
873
  { Hexagon::CS0 },
874
  { Hexagon::CS1 },
875
  { Hexagon::FRAMEKEY },
876
  { Hexagon::FRAMELIMIT },
877
  { Hexagon::GELR },
878
  { Hexagon::GOSP },
879
  { Hexagon::GP },
880
  { Hexagon::GPCYCLEHI },
881
  { Hexagon::GPCYCLELO },
882
  { Hexagon::GSR },
883
  { Hexagon::PC },
884
  { Hexagon::PKTCOUNTLO },
885
  { Hexagon::PKTCOUNTHI },
886
  { Hexagon::UGP },
887
  { Hexagon::UPCYCLELO },
888
  { Hexagon::UPCYCLEHI },
889
  { Hexagon::USR_OVF },
890
  { Hexagon::USR, Hexagon::C8 },
891
  { Hexagon::UTIMERLO },
892
  { Hexagon::UTIMERHI },
893
  { Hexagon::VTMP },
894
  { Hexagon::C5 },
895
  { Hexagon::R0 },
896
  { Hexagon::R1 },
897
  { Hexagon::R2 },
898
  { Hexagon::R3 },
899
  { Hexagon::R4 },
900
  { Hexagon::R5 },
901
  { Hexagon::R6 },
902
  { Hexagon::R7 },
903
  { Hexagon::R8 },
904
  { Hexagon::R9 },
905
  { Hexagon::R10 },
906
  { Hexagon::R11 },
907
  { Hexagon::R12 },
908
  { Hexagon::R13 },
909
  { Hexagon::R14 },
910
  { Hexagon::R15 },
911
  { Hexagon::R16 },
912
  { Hexagon::R17 },
913
  { Hexagon::R18 },
914
  { Hexagon::R19 },
915
  { Hexagon::R20 },
916
  { Hexagon::R21 },
917
  { Hexagon::R22 },
918
  { Hexagon::R23 },
919
  { Hexagon::R24 },
920
  { Hexagon::R25 },
921
  { Hexagon::R26 },
922
  { Hexagon::R27 },
923
  { Hexagon::R28 },
924
  { Hexagon::R29 },
925
  { Hexagon::R30 },
926
  { Hexagon::R31 },
927
  { Hexagon::G3 },
928
  { Hexagon::G4 },
929
  { Hexagon::G5 },
930
  { Hexagon::G6 },
931
  { Hexagon::G7 },
932
  { Hexagon::G8 },
933
  { Hexagon::G9 },
934
  { Hexagon::G10 },
935
  { Hexagon::G11 },
936
  { Hexagon::G12 },
937
  { Hexagon::G13 },
938
  { Hexagon::G14 },
939
  { Hexagon::G15 },
940
  { Hexagon::G20 },
941
  { Hexagon::G21 },
942
  { Hexagon::G22 },
943
  { Hexagon::G23 },
944
  { Hexagon::G30 },
945
  { Hexagon::G31 },
946
  { Hexagon::GPMUCNT0 },
947
  { Hexagon::GPMUCNT1 },
948
  { Hexagon::GPMUCNT2 },
949
  { Hexagon::GPMUCNT3 },
950
  { Hexagon::GPMUCNT4 },
951
  { Hexagon::GPMUCNT5 },
952
  { Hexagon::GPMUCNT6 },
953
  { Hexagon::GPMUCNT7 },
954
  { Hexagon::LC0 },
955
  { Hexagon::LC1 },
956
  { Hexagon::M0 },
957
  { Hexagon::M1 },
958
  { Hexagon::P0, Hexagon::P3_0 },
959
  { Hexagon::P1, Hexagon::P3_0 },
960
  { Hexagon::P2, Hexagon::P3_0 },
961
  { Hexagon::P3, Hexagon::P3_0 },
962
  { Hexagon::Q0 },
963
  { Hexagon::Q1 },
964
  { Hexagon::Q2 },
965
  { Hexagon::Q3 },
966
  { Hexagon::SA0 },
967
  { Hexagon::SA1 },
968
  { Hexagon::V0 },
969
  { Hexagon::V1 },
970
  { Hexagon::V2 },
971
  { Hexagon::V3 },
972
  { Hexagon::V4 },
973
  { Hexagon::V5 },
974
  { Hexagon::V6 },
975
  { Hexagon::V7 },
976
  { Hexagon::V8 },
977
  { Hexagon::V9 },
978
  { Hexagon::V10 },
979
  { Hexagon::V11 },
980
  { Hexagon::V12 },
981
  { Hexagon::V13 },
982
  { Hexagon::V14 },
983
  { Hexagon::V15 },
984
  { Hexagon::V16 },
985
  { Hexagon::V17 },
986
  { Hexagon::V18 },
987
  { Hexagon::V19 },
988
  { Hexagon::V20 },
989
  { Hexagon::V21 },
990
  { Hexagon::V22 },
991
  { Hexagon::V23 },
992
  { Hexagon::V24 },
993
  { Hexagon::V25 },
994
  { Hexagon::V26 },
995
  { Hexagon::V27 },
996
  { Hexagon::V28 },
997
  { Hexagon::V29 },
998
  { Hexagon::V30 },
999
  { Hexagon::V31 },
1000
};
1001
1002
namespace {     // Register classes...
1003
  // UsrBits Register Class...
1004
  const MCPhysReg UsrBits[] = {
1005
    Hexagon::USR_OVF, 
1006
  };
1007
1008
  // UsrBits Bit set.
1009
  const uint8_t UsrBitsBits[] = {
1010
    0x00, 0x00, 0x08, 
1011
  };
1012
1013
  // GuestRegs Register Class...
1014
  const MCPhysReg GuestRegs[] = {
1015
    Hexagon::GELR, Hexagon::GSR, Hexagon::GOSP, Hexagon::G3, Hexagon::G4, Hexagon::G5, Hexagon::G6, Hexagon::G7, Hexagon::G8, Hexagon::G9, Hexagon::G10, Hexagon::G11, Hexagon::G12, Hexagon::G13, Hexagon::G14, Hexagon::G15, Hexagon::GPMUCNT4, Hexagon::GPMUCNT5, Hexagon::GPMUCNT6, Hexagon::GPMUCNT7, Hexagon::G20, Hexagon::G21, Hexagon::G22, Hexagon::G23, Hexagon::GPCYCLELO, Hexagon::GPCYCLEHI, Hexagon::GPMUCNT0, Hexagon::GPMUCNT1, Hexagon::GPMUCNT2, Hexagon::GPMUCNT3, Hexagon::G30, Hexagon::G31, 
1016
  };
1017
1018
  // GuestRegs Bit set.
1019
  const uint8_t GuestRegsBits[] = {
1020
    0xb0, 0x03, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0x7f, 
1021
  };
1022
1023
  // IntRegs Register Class...
1024
  const MCPhysReg IntRegs[] = {
1025
    Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, Hexagon::R12, Hexagon::R13, Hexagon::R14, Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R10, Hexagon::R11, Hexagon::R29, Hexagon::R30, Hexagon::R31, 
1026
  };
1027
1028
  // IntRegs Bit set.
1029
  const uint8_t IntRegsBits[] = {
1030
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
1031
  };
1032
1033
  // CtrRegs Register Class...
1034
  const MCPhysReg CtrRegs[] = {
1035
    Hexagon::LC0, Hexagon::SA0, Hexagon::LC1, Hexagon::SA1, Hexagon::P3_0, Hexagon::C5, Hexagon::C8, Hexagon::PC, Hexagon::UGP, Hexagon::GP, Hexagon::CS0, Hexagon::CS1, Hexagon::UPCYCLELO, Hexagon::UPCYCLEHI, Hexagon::FRAMELIMIT, Hexagon::FRAMEKEY, Hexagon::PKTCOUNTLO, Hexagon::PKTCOUNTHI, Hexagon::UTIMERLO, Hexagon::UTIMERHI, Hexagon::M0, Hexagon::M1, Hexagon::USR, 
1036
  };
1037
1038
  // CtrRegs Bit set.
1039
  const uint8_t CtrRegsBits[] = {
1040
    0x4c, 0x74, 0x67, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 
1041
  };
1042
1043
  // GeneralSubRegs Register Class...
1044
  const MCPhysReg GeneralSubRegs[] = {
1045
    Hexagon::R23, Hexagon::R22, Hexagon::R21, Hexagon::R20, Hexagon::R19, Hexagon::R18, Hexagon::R17, Hexagon::R16, Hexagon::R7, Hexagon::R6, Hexagon::R5, Hexagon::R4, Hexagon::R3, Hexagon::R2, Hexagon::R1, Hexagon::R0, 
1046
  };
1047
1048
  // GeneralSubRegs Bit set.
1049
  const uint8_t GeneralSubRegsBits[] = {
1050
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 0xf8, 0x07, 
1051
  };
1052
1053
  // V62Regs Register Class...
1054
  const MCPhysReg V62Regs[] = {
1055
    Hexagon::FRAMELIMIT, Hexagon::FRAMEKEY, Hexagon::C17_16, Hexagon::PKTCOUNTLO, Hexagon::PKTCOUNTHI, Hexagon::PKTCOUNT, Hexagon::UTIMERLO, Hexagon::UTIMERHI, Hexagon::UTIMER, 
1056
  };
1057
1058
  // V62Regs Bit set.
1059
  const uint8_t V62RegsBits[] = {
1060
    0x0c, 0x38, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 
1061
  };
1062
1063
  // IntRegsLow8 Register Class...
1064
  const MCPhysReg IntRegsLow8[] = {
1065
    Hexagon::R7, Hexagon::R6, Hexagon::R5, Hexagon::R4, Hexagon::R3, Hexagon::R2, Hexagon::R1, Hexagon::R0, 
1066
  };
1067
1068
  // IntRegsLow8 Bit set.
1069
  const uint8_t IntRegsLow8Bits[] = {
1070
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 
1071
  };
1072
1073
  // CtrRegs_and_V62Regs Register Class...
1074
  const MCPhysReg CtrRegs_and_V62Regs[] = {
1075
    Hexagon::FRAMELIMIT, Hexagon::FRAMEKEY, Hexagon::PKTCOUNTLO, Hexagon::PKTCOUNTHI, Hexagon::UTIMERLO, Hexagon::UTIMERHI, 
1076
  };
1077
1078
  // CtrRegs_and_V62Regs Bit set.
1079
  const uint8_t CtrRegs_and_V62RegsBits[] = {
1080
    0x0c, 0x30, 0x60, 
1081
  };
1082
1083
  // PredRegs Register Class...
1084
  const MCPhysReg PredRegs[] = {
1085
    Hexagon::P0, Hexagon::P1, Hexagon::P2, Hexagon::P3, 
1086
  };
1087
1088
  // PredRegs Bit set.
1089
  const uint8_t PredRegsBits[] = {
1090
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 
1091
  };
1092
1093
  // V62Regs_with_isub_hi Register Class...
1094
  const MCPhysReg V62Regs_with_isub_hi[] = {
1095
    Hexagon::C17_16, Hexagon::PKTCOUNT, Hexagon::UTIMER, 
1096
  };
1097
1098
  // V62Regs_with_isub_hi Bit set.
1099
  const uint8_t V62Regs_with_isub_hiBits[] = {
1100
    0x00, 0x08, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 
1101
  };
1102
1103
  // ModRegs Register Class...
1104
  const MCPhysReg ModRegs[] = {
1105
    Hexagon::M0, Hexagon::M1, 
1106
  };
1107
1108
  // ModRegs Bit set.
1109
  const uint8_t ModRegsBits[] = {
1110
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 
1111
  };
1112
1113
  // CtrRegs_with_subreg_overflow Register Class...
1114
  const MCPhysReg CtrRegs_with_subreg_overflow[] = {
1115
    Hexagon::USR, 
1116
  };
1117
1118
  // CtrRegs_with_subreg_overflow Bit set.
1119
  const uint8_t CtrRegs_with_subreg_overflowBits[] = {
1120
    0x00, 0x00, 0x04, 
1121
  };
1122
1123
  // V65Regs Register Class...
1124
  const MCPhysReg V65Regs[] = {
1125
    Hexagon::VTMP, 
1126
  };
1127
1128
  // V65Regs Bit set.
1129
  const uint8_t V65RegsBits[] = {
1130
    0x00, 0x00, 0x80, 
1131
  };
1132
1133
  // DoubleRegs Register Class...
1134
  const MCPhysReg DoubleRegs[] = {
1135
    Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, Hexagon::D4, Hexagon::D6, Hexagon::D7, Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, Hexagon::D12, Hexagon::D13, Hexagon::D5, Hexagon::D14, Hexagon::D15, 
1136
  };
1137
1138
  // DoubleRegs Bit set.
1139
  const uint8_t DoubleRegsBits[] = {
1140
    0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, 
1141
  };
1142
1143
  // GuestRegs64 Register Class...
1144
  const MCPhysReg GuestRegs64[] = {
1145
    Hexagon::G1_0, Hexagon::G3_2, Hexagon::G5_4, Hexagon::G7_6, Hexagon::G9_8, Hexagon::G11_10, Hexagon::G13_12, Hexagon::G15_14, Hexagon::G17_16, Hexagon::G19_18, Hexagon::G21_20, Hexagon::G23_22, Hexagon::G25_24, Hexagon::G27_26, Hexagon::G29_28, Hexagon::G31_30, 
1146
  };
1147
1148
  // GuestRegs64 Bit set.
1149
  const uint8_t GuestRegs64Bits[] = {
1150
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, 
1151
  };
1152
1153
  // CtrRegs64 Register Class...
1154
  const MCPhysReg CtrRegs64[] = {
1155
    Hexagon::C1_0, Hexagon::C3_2, Hexagon::C5_4, Hexagon::C7_6, Hexagon::C9_8, Hexagon::C11_10, Hexagon::CS, Hexagon::UPCYCLE, Hexagon::C17_16, Hexagon::PKTCOUNT, Hexagon::UTIMER, 
1156
  };
1157
1158
  // CtrRegs64 Bit set.
1159
  const uint8_t CtrRegs64Bits[] = {
1160
    0x02, 0x88, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
1161
  };
1162
1163
  // GeneralDoubleLow8Regs Register Class...
1164
  const MCPhysReg GeneralDoubleLow8Regs[] = {
1165
    Hexagon::D11, Hexagon::D10, Hexagon::D9, Hexagon::D8, Hexagon::D3, Hexagon::D2, Hexagon::D1, Hexagon::D0, 
1166
  };
1167
1168
  // GeneralDoubleLow8Regs Bit set.
1169
  const uint8_t GeneralDoubleLow8RegsBits[] = {
1170
    0x00, 0x00, 0x00, 0xf0, 0xf0, 
1171
  };
1172
1173
  // DoubleRegs_with_isub_hi_in_IntRegsLow8 Register Class...
1174
  const MCPhysReg DoubleRegs_with_isub_hi_in_IntRegsLow8[] = {
1175
    Hexagon::D3, Hexagon::D2, Hexagon::D1, Hexagon::D0, 
1176
  };
1177
1178
  // DoubleRegs_with_isub_hi_in_IntRegsLow8 Bit set.
1179
  const uint8_t DoubleRegs_with_isub_hi_in_IntRegsLow8Bits[] = {
1180
    0x00, 0x00, 0x00, 0xf0, 
1181
  };
1182
1183
  // CtrRegs64_and_V62Regs Register Class...
1184
  const MCPhysReg CtrRegs64_and_V62Regs[] = {
1185
    Hexagon::C17_16, Hexagon::PKTCOUNT, Hexagon::UTIMER, 
1186
  };
1187
1188
  // CtrRegs64_and_V62Regs Bit set.
1189
  const uint8_t CtrRegs64_and_V62RegsBits[] = {
1190
    0x00, 0x08, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 
1191
  };
1192
1193
  // CtrRegs64_with_isub_hi_in_ModRegs Register Class...
1194
  const MCPhysReg CtrRegs64_with_isub_hi_in_ModRegs[] = {
1195
    Hexagon::C7_6, 
1196
  };
1197
1198
  // CtrRegs64_with_isub_hi_in_ModRegs Bit set.
1199
  const uint8_t CtrRegs64_with_isub_hi_in_ModRegsBits[] = {
1200
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 
1201
  };
1202
1203
  // HvxVR Register Class...
1204
  const MCPhysReg HvxVR[] = {
1205
    Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19, Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24, Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, Hexagon::V30, Hexagon::V31, Hexagon::VTMP, 
1206
  };
1207
1208
  // HvxVR Bit set.
1209
  const uint8_t HvxVRBits[] = {
1210
    0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
1211
  };
1212
1213
  // HvxQR Register Class...
1214
  const MCPhysReg HvxQR[] = {
1215
    Hexagon::Q0, Hexagon::Q1, Hexagon::Q2, Hexagon::Q3, 
1216
  };
1217
1218
  // HvxQR Bit set.
1219
  const uint8_t HvxQRBits[] = {
1220
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 
1221
  };
1222
1223
  // HvxVR_and_V65Regs Register Class...
1224
  const MCPhysReg HvxVR_and_V65Regs[] = {
1225
    Hexagon::VTMP, 
1226
  };
1227
1228
  // HvxVR_and_V65Regs Bit set.
1229
  const uint8_t HvxVR_and_V65RegsBits[] = {
1230
    0x00, 0x00, 0x80, 
1231
  };
1232
1233
  // HvxWR Register Class...
1234
  const MCPhysReg HvxWR[] = {
1235
    Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7, Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11, Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15, 
1236
  };
1237
1238
  // HvxWR Bit set.
1239
  const uint8_t HvxWRBits[] = {
1240
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
1241
  };
1242
1243
  // HvxVQR Register Class...
1244
  const MCPhysReg HvxVQR[] = {
1245
    Hexagon::VQ0, Hexagon::VQ1, Hexagon::VQ2, Hexagon::VQ3, Hexagon::VQ4, Hexagon::VQ5, Hexagon::VQ6, Hexagon::VQ7, 
1246
  };
1247
1248
  // HvxVQR Bit set.
1249
  const uint8_t HvxVQRBits[] = {
1250
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
1251
  };
1252
1253
} // end anonymous namespace
1254
1255
extern const char HexagonRegClassStrings[] = {
1256
  /* 0 */ 'C', 't', 'r', 'R', 'e', 'g', 's', '6', '4', 0,
1257
  /* 10 */ 'G', 'u', 'e', 's', 't', 'R', 'e', 'g', 's', '6', '4', 0,
1258
  /* 22 */ 'D', 'o', 'u', 'b', 'l', 'e', 'R', 'e', 'g', 's', '_', 'w', 'i', 't', 'h', '_', 'i', 's', 'u', 'b', '_', 'h', 'i', '_', 'i', 'n', '_', 'I', 'n', 't', 'R', 'e', 'g', 's', 'L', 'o', 'w', '8', 0,
1259
  /* 61 */ 'H', 'v', 'x', 'V', 'Q', 'R', 0,
1260
  /* 68 */ 'H', 'v', 'x', 'Q', 'R', 0,
1261
  /* 74 */ 'H', 'v', 'x', 'V', 'R', 0,
1262
  /* 80 */ 'H', 'v', 'x', 'W', 'R', 0,
1263
  /* 86 */ 'V', '6', '2', 'R', 'e', 'g', 's', '_', 'w', 'i', 't', 'h', '_', 'i', 's', 'u', 'b', '_', 'h', 'i', 0,
1264
  /* 107 */ 'C', 't', 'r', 'R', 'e', 'g', 's', '6', '4', '_', 'a', 'n', 'd', '_', 'V', '6', '2', 'R', 'e', 'g', 's', 0,
1265
  /* 129 */ 'C', 't', 'r', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'V', '6', '2', 'R', 'e', 'g', 's', 0,
1266
  /* 149 */ 'H', 'v', 'x', 'V', 'R', '_', 'a', 'n', 'd', '_', 'V', '6', '5', 'R', 'e', 'g', 's', 0,
1267
  /* 167 */ 'G', 'e', 'n', 'e', 'r', 'a', 'l', 'D', 'o', 'u', 'b', 'l', 'e', 'L', 'o', 'w', '8', 'R', 'e', 'g', 's', 0,
1268
  /* 189 */ 'G', 'e', 'n', 'e', 'r', 'a', 'l', 'S', 'u', 'b', 'R', 'e', 'g', 's', 0,
1269
  /* 204 */ 'P', 'r', 'e', 'd', 'R', 'e', 'g', 's', 0,
1270
  /* 213 */ 'C', 't', 'r', 'R', 'e', 'g', 's', '6', '4', '_', 'w', 'i', 't', 'h', '_', 'i', 's', 'u', 'b', '_', 'h', 'i', '_', 'i', 'n', '_', 'M', 'o', 'd', 'R', 'e', 'g', 's', 0,
1271
  /* 247 */ 'D', 'o', 'u', 'b', 'l', 'e', 'R', 'e', 'g', 's', 0,
1272
  /* 258 */ 'C', 't', 'r', 'R', 'e', 'g', 's', 0,
1273
  /* 266 */ 'I', 'n', 't', 'R', 'e', 'g', 's', 0,
1274
  /* 274 */ 'G', 'u', 'e', 's', 't', 'R', 'e', 'g', 's', 0,
1275
  /* 284 */ 'U', 's', 'r', 'B', 'i', 't', 's', 0,
1276
  /* 292 */ 'C', 't', 'r', 'R', 'e', 'g', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'r', 'e', 'g', '_', 'o', 'v', 'e', 'r', 'f', 'l', 'o', 'w', 0,
1277
};
1278
1279
extern const MCRegisterClass HexagonMCRegisterClasses[] = {
1280
  { UsrBits, UsrBitsBits, 284, 1, sizeof(UsrBitsBits), Hexagon::UsrBitsRegClassID, 1, false },
1281
  { GuestRegs, GuestRegsBits, 274, 32, sizeof(GuestRegsBits), Hexagon::GuestRegsRegClassID, 1, false },
1282
  { IntRegs, IntRegsBits, 266, 32, sizeof(IntRegsBits), Hexagon::IntRegsRegClassID, 1, true },
1283
  { CtrRegs, CtrRegsBits, 258, 23, sizeof(CtrRegsBits), Hexagon::CtrRegsRegClassID, 1, false },
1284
  { GeneralSubRegs, GeneralSubRegsBits, 189, 16, sizeof(GeneralSubRegsBits), Hexagon::GeneralSubRegsRegClassID, 1, true },
1285
  { V62Regs, V62RegsBits, 121, 9, sizeof(V62RegsBits), Hexagon::V62RegsRegClassID, 1, false },
1286
  { IntRegsLow8, IntRegsLow8Bits, 49, 8, sizeof(IntRegsLow8Bits), Hexagon::IntRegsLow8RegClassID, 1, true },
1287
  { CtrRegs_and_V62Regs, CtrRegs_and_V62RegsBits, 129, 6, sizeof(CtrRegs_and_V62RegsBits), Hexagon::CtrRegs_and_V62RegsRegClassID, 1, false },
1288
  { PredRegs, PredRegsBits, 204, 4, sizeof(PredRegsBits), Hexagon::PredRegsRegClassID, 1, true },
1289
  { V62Regs_with_isub_hi, V62Regs_with_isub_hiBits, 86, 3, sizeof(V62Regs_with_isub_hiBits), Hexagon::V62Regs_with_isub_hiRegClassID, 1, false },
1290
  { ModRegs, ModRegsBits, 239, 2, sizeof(ModRegsBits), Hexagon::ModRegsRegClassID, 1, true },
1291
  { CtrRegs_with_subreg_overflow, CtrRegs_with_subreg_overflowBits, 292, 1, sizeof(CtrRegs_with_subreg_overflowBits), Hexagon::CtrRegs_with_subreg_overflowRegClassID, 1, false },
1292
  { V65Regs, V65RegsBits, 159, 1, sizeof(V65RegsBits), Hexagon::V65RegsRegClassID, 1, false },
1293
  { DoubleRegs, DoubleRegsBits, 247, 16, sizeof(DoubleRegsBits), Hexagon::DoubleRegsRegClassID, 1, true },
1294
  { GuestRegs64, GuestRegs64Bits, 10, 16, sizeof(GuestRegs64Bits), Hexagon::GuestRegs64RegClassID, 1, false },
1295
  { CtrRegs64, CtrRegs64Bits, 0, 11, sizeof(CtrRegs64Bits), Hexagon::CtrRegs64RegClassID, 1, false },
1296
  { GeneralDoubleLow8Regs, GeneralDoubleLow8RegsBits, 167, 8, sizeof(GeneralDoubleLow8RegsBits), Hexagon::GeneralDoubleLow8RegsRegClassID, 1, true },
1297
  { DoubleRegs_with_isub_hi_in_IntRegsLow8, DoubleRegs_with_isub_hi_in_IntRegsLow8Bits, 22, 4, sizeof(DoubleRegs_with_isub_hi_in_IntRegsLow8Bits), Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID, 1, true },
1298
  { CtrRegs64_and_V62Regs, CtrRegs64_and_V62RegsBits, 107, 3, sizeof(CtrRegs64_and_V62RegsBits), Hexagon::CtrRegs64_and_V62RegsRegClassID, 1, false },
1299
  { CtrRegs64_with_isub_hi_in_ModRegs, CtrRegs64_with_isub_hi_in_ModRegsBits, 213, 1, sizeof(CtrRegs64_with_isub_hi_in_ModRegsBits), Hexagon::CtrRegs64_with_isub_hi_in_ModRegsRegClassID, 1, false },
1300
  { HvxVR, HvxVRBits, 74, 33, sizeof(HvxVRBits), Hexagon::HvxVRRegClassID, 1, true },
1301
  { HvxQR, HvxQRBits, 68, 4, sizeof(HvxQRBits), Hexagon::HvxQRRegClassID, 1, true },
1302
  { HvxVR_and_V65Regs, HvxVR_and_V65RegsBits, 149, 1, sizeof(HvxVR_and_V65RegsBits), Hexagon::HvxVR_and_V65RegsRegClassID, 1, true },
1303
  { HvxWR, HvxWRBits, 80, 16, sizeof(HvxWRBits), Hexagon::HvxWRRegClassID, 1, true },
1304
  { HvxVQR, HvxVQRBits, 61, 8, sizeof(HvxVQRBits), Hexagon::HvxVQRRegClassID, 1, true },
1305
};
1306
1307
// Hexagon Dwarf<->LLVM register mappings.
1308
extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0Dwarf2L[] = {
1309
  { 0U, Hexagon::R0 },
1310
  { 1U, Hexagon::R1 },
1311
  { 2U, Hexagon::R2 },
1312
  { 3U, Hexagon::R3 },
1313
  { 4U, Hexagon::R4 },
1314
  { 5U, Hexagon::R5 },
1315
  { 6U, Hexagon::R6 },
1316
  { 7U, Hexagon::R7 },
1317
  { 8U, Hexagon::R8 },
1318
  { 9U, Hexagon::R9 },
1319
  { 10U, Hexagon::R10 },
1320
  { 11U, Hexagon::R11 },
1321
  { 12U, Hexagon::R12 },
1322
  { 13U, Hexagon::R13 },
1323
  { 14U, Hexagon::R14 },
1324
  { 15U, Hexagon::R15 },
1325
  { 16U, Hexagon::R16 },
1326
  { 17U, Hexagon::R17 },
1327
  { 18U, Hexagon::R18 },
1328
  { 19U, Hexagon::R19 },
1329
  { 20U, Hexagon::R20 },
1330
  { 21U, Hexagon::R21 },
1331
  { 22U, Hexagon::R22 },
1332
  { 23U, Hexagon::R23 },
1333
  { 24U, Hexagon::R24 },
1334
  { 25U, Hexagon::R25 },
1335
  { 26U, Hexagon::R26 },
1336
  { 27U, Hexagon::R27 },
1337
  { 28U, Hexagon::R28 },
1338
  { 29U, Hexagon::R29 },
1339
  { 30U, Hexagon::R30 },
1340
  { 31U, Hexagon::R31 },
1341
  { 32U, Hexagon::D0 },
1342
  { 34U, Hexagon::D1 },
1343
  { 36U, Hexagon::D2 },
1344
  { 38U, Hexagon::D3 },
1345
  { 40U, Hexagon::D4 },
1346
  { 42U, Hexagon::D5 },
1347
  { 44U, Hexagon::D6 },
1348
  { 46U, Hexagon::D7 },
1349
  { 48U, Hexagon::D8 },
1350
  { 50U, Hexagon::D9 },
1351
  { 52U, Hexagon::D10 },
1352
  { 54U, Hexagon::D11 },
1353
  { 56U, Hexagon::D12 },
1354
  { 58U, Hexagon::D13 },
1355
  { 60U, Hexagon::D14 },
1356
  { 62U, Hexagon::D15 },
1357
  { 63U, Hexagon::P0 },
1358
  { 64U, Hexagon::P1 },
1359
  { 65U, Hexagon::P2 },
1360
  { 66U, Hexagon::P3 },
1361
  { 67U, Hexagon::C1_0 },
1362
  { 68U, Hexagon::LC0 },
1363
  { 69U, Hexagon::C3_2 },
1364
  { 70U, Hexagon::LC1 },
1365
  { 71U, Hexagon::P3_0 },
1366
  { 72U, Hexagon::C7_6 },
1367
  { 73U, Hexagon::M0 },
1368
  { 74U, Hexagon::C9_8 },
1369
  { 75U, Hexagon::C8 },
1370
  { 76U, Hexagon::C11_10 },
1371
  { 77U, Hexagon::UGP },
1372
  { 78U, Hexagon::GP },
1373
  { 79U, Hexagon::CS0 },
1374
  { 80U, Hexagon::CS1 },
1375
  { 81U, Hexagon::UPCYCLELO },
1376
  { 82U, Hexagon::UPCYCLEHI },
1377
  { 83U, Hexagon::C17_16 },
1378
  { 84U, Hexagon::FRAMEKEY },
1379
  { 85U, Hexagon::PKTCOUNTLO },
1380
  { 86U, Hexagon::PKTCOUNTHI },
1381
  { 97U, Hexagon::UTIMERLO },
1382
  { 98U, Hexagon::UTIMERHI },
1383
  { 99U, Hexagon::W0 },
1384
  { 100U, Hexagon::V1 },
1385
  { 101U, Hexagon::W1 },
1386
  { 102U, Hexagon::V3 },
1387
  { 103U, Hexagon::W2 },
1388
  { 104U, Hexagon::V5 },
1389
  { 105U, Hexagon::W3 },
1390
  { 106U, Hexagon::V7 },
1391
  { 107U, Hexagon::W4 },
1392
  { 108U, Hexagon::V9 },
1393
  { 109U, Hexagon::W5 },
1394
  { 110U, Hexagon::V11 },
1395
  { 111U, Hexagon::W6 },
1396
  { 112U, Hexagon::V13 },
1397
  { 113U, Hexagon::W7 },
1398
  { 114U, Hexagon::V15 },
1399
  { 115U, Hexagon::W8 },
1400
  { 116U, Hexagon::V17 },
1401
  { 117U, Hexagon::W9 },
1402
  { 118U, Hexagon::V19 },
1403
  { 119U, Hexagon::W10 },
1404
  { 120U, Hexagon::V21 },
1405
  { 121U, Hexagon::W11 },
1406
  { 122U, Hexagon::V23 },
1407
  { 123U, Hexagon::W12 },
1408
  { 124U, Hexagon::V25 },
1409
  { 125U, Hexagon::W13 },
1410
  { 126U, Hexagon::V27 },
1411
  { 127U, Hexagon::W14 },
1412
  { 128U, Hexagon::V29 },
1413
  { 129U, Hexagon::W15 },
1414
  { 130U, Hexagon::V31 },
1415
  { 131U, Hexagon::Q0 },
1416
  { 132U, Hexagon::Q1 },
1417
  { 133U, Hexagon::Q2 },
1418
  { 134U, Hexagon::Q3 },
1419
  { 220U, Hexagon::G1_0 },
1420
  { 221U, Hexagon::GSR },
1421
  { 222U, Hexagon::G3_2 },
1422
  { 223U, Hexagon::G3 },
1423
  { 224U, Hexagon::G5_4 },
1424
  { 225U, Hexagon::G5 },
1425
  { 226U, Hexagon::G7_6 },
1426
  { 227U, Hexagon::G7 },
1427
  { 228U, Hexagon::G9_8 },
1428
  { 229U, Hexagon::G9 },
1429
  { 230U, Hexagon::G11_10 },
1430
  { 231U, Hexagon::G11 },
1431
  { 232U, Hexagon::G13_12 },
1432
  { 233U, Hexagon::G13 },
1433
  { 234U, Hexagon::G15_14 },
1434
  { 235U, Hexagon::G15 },
1435
  { 236U, Hexagon::G17_16 },
1436
  { 237U, Hexagon::GPMUCNT5 },
1437
  { 238U, Hexagon::G19_18 },
1438
  { 239U, Hexagon::GPMUCNT7 },
1439
  { 240U, Hexagon::G21_20 },
1440
  { 241U, Hexagon::G21 },
1441
  { 242U, Hexagon::G23_22 },
1442
  { 243U, Hexagon::G23 },
1443
  { 244U, Hexagon::G25_24 },
1444
  { 245U, Hexagon::GPCYCLEHI },
1445
  { 246U, Hexagon::G27_26 },
1446
  { 247U, Hexagon::GPMUCNT1 },
1447
  { 248U, Hexagon::G29_28 },
1448
  { 249U, Hexagon::GPMUCNT3 },
1449
  { 250U, Hexagon::G31_30 },
1450
  { 251U, Hexagon::G31 },
1451
  { 252U, Hexagon::VQ0 },
1452
  { 253U, Hexagon::VQ1 },
1453
  { 254U, Hexagon::VQ2 },
1454
  { 255U, Hexagon::VQ3 },
1455
  { 256U, Hexagon::VQ4 },
1456
  { 257U, Hexagon::VQ5 },
1457
  { 258U, Hexagon::VQ6 },
1458
  { 259U, Hexagon::VQ7 },
1459
};
1460
extern const unsigned HexagonDwarfFlavour0Dwarf2LSize = array_lengthof(HexagonDwarfFlavour0Dwarf2L);
1461
1462
extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0Dwarf2L[] = {
1463
  { 0U, Hexagon::R0 },
1464
  { 1U, Hexagon::R1 },
1465
  { 2U, Hexagon::R2 },
1466
  { 3U, Hexagon::R3 },
1467
  { 4U, Hexagon::R4 },
1468
  { 5U, Hexagon::R5 },
1469
  { 6U, Hexagon::R6 },
1470
  { 7U, Hexagon::R7 },
1471
  { 8U, Hexagon::R8 },
1472
  { 9U, Hexagon::R9 },
1473
  { 10U, Hexagon::R10 },
1474
  { 11U, Hexagon::R11 },
1475
  { 12U, Hexagon::R12 },
1476
  { 13U, Hexagon::R13 },
1477
  { 14U, Hexagon::R14 },
1478
  { 15U, Hexagon::R15 },
1479
  { 16U, Hexagon::R16 },
1480
  { 17U, Hexagon::R17 },
1481
  { 18U, Hexagon::R18 },
1482
  { 19U, Hexagon::R19 },
1483
  { 20U, Hexagon::R20 },
1484
  { 21U, Hexagon::R21 },
1485
  { 22U, Hexagon::R22 },
1486
  { 23U, Hexagon::R23 },
1487
  { 24U, Hexagon::R24 },
1488
  { 25U, Hexagon::R25 },
1489
  { 26U, Hexagon::R26 },
1490
  { 27U, Hexagon::R27 },
1491
  { 28U, Hexagon::R28 },
1492
  { 29U, Hexagon::R29 },
1493
  { 30U, Hexagon::R30 },
1494
  { 31U, Hexagon::R31 },
1495
  { 32U, Hexagon::D0 },
1496
  { 34U, Hexagon::D1 },
1497
  { 36U, Hexagon::D2 },
1498
  { 38U, Hexagon::D3 },
1499
  { 40U, Hexagon::D4 },
1500
  { 42U, Hexagon::D5 },
1501
  { 44U, Hexagon::D6 },
1502
  { 46U, Hexagon::D7 },
1503
  { 48U, Hexagon::D8 },
1504
  { 50U, Hexagon::D9 },
1505
  { 52U, Hexagon::D10 },
1506
  { 54U, Hexagon::D11 },
1507
  { 56U, Hexagon::D12 },
1508
  { 58U, Hexagon::D13 },
1509
  { 60U, Hexagon::D14 },
1510
  { 62U, Hexagon::D15 },
1511
  { 63U, Hexagon::P0 },
1512
  { 64U, Hexagon::P1 },
1513
  { 65U, Hexagon::P2 },
1514
  { 66U, Hexagon::P3 },
1515
  { 67U, Hexagon::C1_0 },
1516
  { 68U, Hexagon::LC0 },
1517
  { 69U, Hexagon::C3_2 },
1518
  { 70U, Hexagon::LC1 },
1519
  { 71U, Hexagon::P3_0 },
1520
  { 72U, Hexagon::C7_6 },
1521
  { 73U, Hexagon::M0 },
1522
  { 74U, Hexagon::C9_8 },
1523
  { 75U, Hexagon::C8 },
1524
  { 76U, Hexagon::C11_10 },
1525
  { 77U, Hexagon::UGP },
1526
  { 78U, Hexagon::GP },
1527
  { 79U, Hexagon::CS0 },
1528
  { 80U, Hexagon::CS1 },
1529
  { 81U, Hexagon::UPCYCLELO },
1530
  { 82U, Hexagon::UPCYCLEHI },
1531
  { 83U, Hexagon::C17_16 },
1532
  { 84U, Hexagon::FRAMEKEY },
1533
  { 85U, Hexagon::PKTCOUNTLO },
1534
  { 86U, Hexagon::PKTCOUNTHI },
1535
  { 97U, Hexagon::UTIMERLO },
1536
  { 98U, Hexagon::UTIMERHI },
1537
  { 99U, Hexagon::W0 },
1538
  { 100U, Hexagon::V1 },
1539
  { 101U, Hexagon::W1 },
1540
  { 102U, Hexagon::V3 },
1541
  { 103U, Hexagon::W2 },
1542
  { 104U, Hexagon::V5 },
1543
  { 105U, Hexagon::W3 },
1544
  { 106U, Hexagon::V7 },
1545
  { 107U, Hexagon::W4 },
1546
  { 108U, Hexagon::V9 },
1547
  { 109U, Hexagon::W5 },
1548
  { 110U, Hexagon::V11 },
1549
  { 111U, Hexagon::W6 },
1550
  { 112U, Hexagon::V13 },
1551
  { 113U, Hexagon::W7 },
1552
  { 114U, Hexagon::V15 },
1553
  { 115U, Hexagon::W8 },
1554
  { 116U, Hexagon::V17 },
1555
  { 117U, Hexagon::W9 },
1556
  { 118U, Hexagon::V19 },
1557
  { 119U, Hexagon::W10 },
1558
  { 120U, Hexagon::V21 },
1559
  { 121U, Hexagon::W11 },
1560
  { 122U, Hexagon::V23 },
1561
  { 123U, Hexagon::W12 },
1562
  { 124U, Hexagon::V25 },
1563
  { 125U, Hexagon::W13 },
1564
  { 126U, Hexagon::V27 },
1565
  { 127U, Hexagon::W14 },
1566
  { 128U, Hexagon::V29 },
1567
  { 129U, Hexagon::W15 },
1568
  { 130U, Hexagon::V31 },
1569
  { 131U, Hexagon::Q0 },
1570
  { 132U, Hexagon::Q1 },
1571
  { 133U, Hexagon::Q2 },
1572
  { 134U, Hexagon::Q3 },
1573
  { 220U, Hexagon::G1_0 },
1574
  { 221U, Hexagon::GSR },
1575
  { 222U, Hexagon::G3_2 },
1576
  { 223U, Hexagon::G3 },
1577
  { 224U, Hexagon::G5_4 },
1578
  { 225U, Hexagon::G5 },
1579
  { 226U, Hexagon::G7_6 },
1580
  { 227U, Hexagon::G7 },
1581
  { 228U, Hexagon::G9_8 },
1582
  { 229U, Hexagon::G9 },
1583
  { 230U, Hexagon::G11_10 },
1584
  { 231U, Hexagon::G11 },
1585
  { 232U, Hexagon::G13_12 },
1586
  { 233U, Hexagon::G13 },
1587
  { 234U, Hexagon::G15_14 },
1588
  { 235U, Hexagon::G15 },
1589
  { 236U, Hexagon::G17_16 },
1590
  { 237U, Hexagon::GPMUCNT5 },
1591
  { 238U, Hexagon::G19_18 },
1592
  { 239U, Hexagon::GPMUCNT7 },
1593
  { 240U, Hexagon::G21_20 },
1594
  { 241U, Hexagon::G21 },
1595
  { 242U, Hexagon::G23_22 },
1596
  { 243U, Hexagon::G23 },
1597
  { 244U, Hexagon::G25_24 },
1598
  { 245U, Hexagon::GPCYCLEHI },
1599
  { 246U, Hexagon::G27_26 },
1600
  { 247U, Hexagon::GPMUCNT1 },
1601
  { 248U, Hexagon::G29_28 },
1602
  { 249U, Hexagon::GPMUCNT3 },
1603
  { 250U, Hexagon::G31_30 },
1604
  { 251U, Hexagon::G31 },
1605
  { 252U, Hexagon::VQ0 },
1606
  { 253U, Hexagon::VQ1 },
1607
  { 254U, Hexagon::VQ2 },
1608
  { 255U, Hexagon::VQ3 },
1609
  { 256U, Hexagon::VQ4 },
1610
  { 257U, Hexagon::VQ5 },
1611
  { 258U, Hexagon::VQ6 },
1612
  { 259U, Hexagon::VQ7 },
1613
};
1614
extern const unsigned HexagonEHFlavour0Dwarf2LSize = array_lengthof(HexagonEHFlavour0Dwarf2L);
1615
1616
extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0L2Dwarf[] = {
1617
  { Hexagon::CS, 78U },
1618
  { Hexagon::FRAMEKEY, 84U },
1619
  { Hexagon::FRAMELIMIT, 83U },
1620
  { Hexagon::GELR, 220U },
1621
  { Hexagon::GOSP, 222U },
1622
  { Hexagon::GP, 78U },
1623
  { Hexagon::GPCYCLEHI, 245U },
1624
  { Hexagon::GPCYCLELO, 244U },
1625
  { Hexagon::GSR, 221U },
1626
  { Hexagon::PC, 76U },
1627
  { Hexagon::PKTCOUNT, 85U },
1628
  { Hexagon::PKTCOUNTHI, 86U },
1629
  { Hexagon::PKTCOUNTLO, 85U },
1630
  { Hexagon::UGP, 77U },
1631
  { Hexagon::UPCYCLE, 80U },
1632
  { Hexagon::UPCYCLEHI, 82U },
1633
  { Hexagon::UPCYCLELO, 81U },
1634
  { Hexagon::USR, 75U },
1635
  { Hexagon::UTIMER, 97U },
1636
  { Hexagon::UTIMERHI, 98U },
1637
  { Hexagon::UTIMERLO, 97U },
1638
  { Hexagon::VTMP, 131U },
1639
  { Hexagon::C5, 72U },
1640
  { Hexagon::C8, 75U },
1641
  { Hexagon::CS0, 79U },
1642
  { Hexagon::CS1, 80U },
1643
  { Hexagon::D0, 32U },
1644
  { Hexagon::D1, 34U },
1645
  { Hexagon::D2, 36U },
1646
  { Hexagon::D3, 38U },
1647
  { Hexagon::D4, 40U },
1648
  { Hexagon::D5, 42U },
1649
  { Hexagon::D6, 44U },
1650
  { Hexagon::D7, 46U },
1651
  { Hexagon::D8, 48U },
1652
  { Hexagon::D9, 50U },
1653
  { Hexagon::D10, 52U },
1654
  { Hexagon::D11, 54U },
1655
  { Hexagon::D12, 56U },
1656
  { Hexagon::D13, 58U },
1657
  { Hexagon::D14, 60U },
1658
  { Hexagon::D15, 62U },
1659
  { Hexagon::G3, 223U },
1660
  { Hexagon::G4, 224U },
1661
  { Hexagon::G5, 225U },
1662
  { Hexagon::G6, 226U },
1663
  { Hexagon::G7, 227U },
1664
  { Hexagon::G8, 228U },
1665
  { Hexagon::G9, 229U },
1666
  { Hexagon::G10, 230U },
1667
  { Hexagon::G11, 231U },
1668
  { Hexagon::G12, 232U },
1669
  { Hexagon::G13, 233U },
1670
  { Hexagon::G14, 234U },
1671
  { Hexagon::G15, 235U },
1672
  { Hexagon::G20, 240U },
1673
  { Hexagon::G21, 241U },
1674
  { Hexagon::G22, 242U },
1675
  { Hexagon::G23, 243U },
1676
  { Hexagon::G30, 250U },
1677
  { Hexagon::G31, 251U },
1678
  { Hexagon::GPMUCNT0, 246U },
1679
  { Hexagon::GPMUCNT1, 247U },
1680
  { Hexagon::GPMUCNT2, 248U },
1681
  { Hexagon::GPMUCNT3, 249U },
1682
  { Hexagon::GPMUCNT4, 236U },
1683
  { Hexagon::GPMUCNT5, 237U },
1684
  { Hexagon::GPMUCNT6, 238U },
1685
  { Hexagon::GPMUCNT7, 239U },
1686
  { Hexagon::LC0, 68U },
1687
  { Hexagon::LC1, 70U },
1688
  { Hexagon::M0, 73U },
1689
  { Hexagon::M1, 74U },
1690
  { Hexagon::P0, 63U },
1691
  { Hexagon::P1, 64U },
1692
  { Hexagon::P2, 65U },
1693
  { Hexagon::P3, 66U },
1694
  { Hexagon::Q0, 131U },
1695
  { Hexagon::Q1, 132U },
1696
  { Hexagon::Q2, 133U },
1697
  { Hexagon::Q3, 134U },
1698
  { Hexagon::R0, 0U },
1699
  { Hexagon::R1, 1U },
1700
  { Hexagon::R2, 2U },
1701
  { Hexagon::R3, 3U },
1702
  { Hexagon::R4, 4U },
1703
  { Hexagon::R5, 5U },
1704
  { Hexagon::R6, 6U },
1705
  { Hexagon::R7, 7U },
1706
  { Hexagon::R8, 8U },
1707
  { Hexagon::R9, 9U },
1708
  { Hexagon::R10, 10U },
1709
  { Hexagon::R11, 11U },
1710
  { Hexagon::R12, 12U },
1711
  { Hexagon::R13, 13U },
1712
  { Hexagon::R14, 14U },
1713
  { Hexagon::R15, 15U },
1714
  { Hexagon::R16, 16U },
1715
  { Hexagon::R17, 17U },
1716
  { Hexagon::R18, 18U },
1717
  { Hexagon::R19, 19U },
1718
  { Hexagon::R20, 20U },
1719
  { Hexagon::R21, 21U },
1720
  { Hexagon::R22, 22U },
1721
  { Hexagon::R23, 23U },
1722
  { Hexagon::R24, 24U },
1723
  { Hexagon::R25, 25U },
1724
  { Hexagon::R26, 26U },
1725
  { Hexagon::R27, 27U },
1726
  { Hexagon::R28, 28U },
1727
  { Hexagon::R29, 29U },
1728
  { Hexagon::R30, 30U },
1729
  { Hexagon::R31, 31U },
1730
  { Hexagon::SA0, 67U },
1731
  { Hexagon::SA1, 69U },
1732
  { Hexagon::V0, 99U },
1733
  { Hexagon::V1, 100U },
1734
  { Hexagon::V2, 101U },
1735
  { Hexagon::V3, 102U },
1736
  { Hexagon::V4, 103U },
1737
  { Hexagon::V5, 104U },
1738
  { Hexagon::V6, 105U },
1739
  { Hexagon::V7, 106U },
1740
  { Hexagon::V8, 107U },
1741
  { Hexagon::V9, 108U },
1742
  { Hexagon::V10, 109U },
1743
  { Hexagon::V11, 110U },
1744
  { Hexagon::V12, 111U },
1745
  { Hexagon::V13, 112U },
1746
  { Hexagon::V14, 113U },
1747
  { Hexagon::V15, 114U },
1748
  { Hexagon::V16, 115U },
1749
  { Hexagon::V17, 116U },
1750
  { Hexagon::V18, 117U },
1751
  { Hexagon::V19, 118U },
1752
  { Hexagon::V20, 119U },
1753
  { Hexagon::V21, 120U },
1754
  { Hexagon::V22, 121U },
1755
  { Hexagon::V23, 122U },
1756
  { Hexagon::V24, 123U },
1757
  { Hexagon::V25, 124U },
1758
  { Hexagon::V26, 125U },
1759
  { Hexagon::V27, 126U },
1760
  { Hexagon::V28, 127U },
1761
  { Hexagon::V29, 128U },
1762
  { Hexagon::V30, 129U },
1763
  { Hexagon::V31, 130U },
1764
  { Hexagon::VQ0, 252U },
1765
  { Hexagon::VQ1, 253U },
1766
  { Hexagon::VQ2, 254U },
1767
  { Hexagon::VQ3, 255U },
1768
  { Hexagon::VQ4, 256U },
1769
  { Hexagon::VQ5, 257U },
1770
  { Hexagon::VQ6, 258U },
1771
  { Hexagon::VQ7, 259U },
1772
  { Hexagon::W0, 99U },
1773
  { Hexagon::W1, 101U },
1774
  { Hexagon::W2, 103U },
1775
  { Hexagon::W3, 105U },
1776
  { Hexagon::W4, 107U },
1777
  { Hexagon::W5, 109U },
1778
  { Hexagon::W6, 111U },
1779
  { Hexagon::W7, 113U },
1780
  { Hexagon::W8, 115U },
1781
  { Hexagon::W9, 117U },
1782
  { Hexagon::W10, 119U },
1783
  { Hexagon::W11, 121U },
1784
  { Hexagon::W12, 123U },
1785
  { Hexagon::W13, 125U },
1786
  { Hexagon::W14, 127U },
1787
  { Hexagon::W15, 129U },
1788
  { Hexagon::C1_0, 67U },
1789
  { Hexagon::C3_2, 69U },
1790
  { Hexagon::C5_4, 71U },
1791
  { Hexagon::C7_6, 72U },
1792
  { Hexagon::C9_8, 74U },
1793
  { Hexagon::C11_10, 76U },
1794
  { Hexagon::C17_16, 83U },
1795
  { Hexagon::G1_0, 220U },
1796
  { Hexagon::G3_2, 222U },
1797
  { Hexagon::G5_4, 224U },
1798
  { Hexagon::G7_6, 226U },
1799
  { Hexagon::G9_8, 228U },
1800
  { Hexagon::G11_10, 230U },
1801
  { Hexagon::G13_12, 232U },
1802
  { Hexagon::G15_14, 234U },
1803
  { Hexagon::G17_16, 236U },
1804
  { Hexagon::G19_18, 238U },
1805
  { Hexagon::G21_20, 240U },
1806
  { Hexagon::G23_22, 242U },
1807
  { Hexagon::G25_24, 244U },
1808
  { Hexagon::G27_26, 246U },
1809
  { Hexagon::G29_28, 248U },
1810
  { Hexagon::G31_30, 250U },
1811
  { Hexagon::P3_0, 71U },
1812
};
1813
extern const unsigned HexagonDwarfFlavour0L2DwarfSize = array_lengthof(HexagonDwarfFlavour0L2Dwarf);
1814
1815
extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0L2Dwarf[] = {
1816
  { Hexagon::CS, 78U },
1817
  { Hexagon::FRAMEKEY, 84U },
1818
  { Hexagon::FRAMELIMIT, 83U },
1819
  { Hexagon::GELR, 220U },
1820
  { Hexagon::GOSP, 222U },
1821
  { Hexagon::GP, 78U },
1822
  { Hexagon::GPCYCLEHI, 245U },
1823
  { Hexagon::GPCYCLELO, 244U },
1824
  { Hexagon::GSR, 221U },
1825
  { Hexagon::PC, 76U },
1826
  { Hexagon::PKTCOUNT, 85U },
1827
  { Hexagon::PKTCOUNTHI, 86U },
1828
  { Hexagon::PKTCOUNTLO, 85U },
1829
  { Hexagon::UGP, 77U },
1830
  { Hexagon::UPCYCLE, 80U },
1831
  { Hexagon::UPCYCLEHI, 82U },
1832
  { Hexagon::UPCYCLELO, 81U },
1833
  { Hexagon::USR, 75U },
1834
  { Hexagon::UTIMER, 97U },
1835
  { Hexagon::UTIMERHI, 98U },
1836
  { Hexagon::UTIMERLO, 97U },
1837
  { Hexagon::VTMP, 131U },
1838
  { Hexagon::C5, 72U },
1839
  { Hexagon::C8, 75U },
1840
  { Hexagon::CS0, 79U },
1841
  { Hexagon::CS1, 80U },
1842
  { Hexagon::D0, 32U },
1843
  { Hexagon::D1, 34U },
1844
  { Hexagon::D2, 36U },
1845
  { Hexagon::D3, 38U },
1846
  { Hexagon::D4, 40U },
1847
  { Hexagon::D5, 42U },
1848
  { Hexagon::D6, 44U },
1849
  { Hexagon::D7, 46U },
1850
  { Hexagon::D8, 48U },
1851
  { Hexagon::D9, 50U },
1852
  { Hexagon::D10, 52U },
1853
  { Hexagon::D11, 54U },
1854
  { Hexagon::D12, 56U },
1855
  { Hexagon::D13, 58U },
1856
  { Hexagon::D14, 60U },
1857
  { Hexagon::D15, 62U },
1858
  { Hexagon::G3, 223U },
1859
  { Hexagon::G4, 224U },
1860
  { Hexagon::G5, 225U },
1861
  { Hexagon::G6, 226U },
1862
  { Hexagon::G7, 227U },
1863
  { Hexagon::G8, 228U },
1864
  { Hexagon::G9, 229U },
1865
  { Hexagon::G10, 230U },
1866
  { Hexagon::G11, 231U },
1867
  { Hexagon::G12, 232U },
1868
  { Hexagon::G13, 233U },
1869
  { Hexagon::G14, 234U },
1870
  { Hexagon::G15, 235U },
1871
  { Hexagon::G20, 240U },
1872
  { Hexagon::G21, 241U },
1873
  { Hexagon::G22, 242U },
1874
  { Hexagon::G23, 243U },
1875
  { Hexagon::G30, 250U },
1876
  { Hexagon::G31, 251U },
1877
  { Hexagon::GPMUCNT0, 246U },
1878
  { Hexagon::GPMUCNT1, 247U },
1879
  { Hexagon::GPMUCNT2, 248U },
1880
  { Hexagon::GPMUCNT3, 249U },
1881
  { Hexagon::GPMUCNT4, 236U },
1882
  { Hexagon::GPMUCNT5, 237U },
1883
  { Hexagon::GPMUCNT6, 238U },
1884
  { Hexagon::GPMUCNT7, 239U },
1885
  { Hexagon::LC0, 68U },
1886
  { Hexagon::LC1, 70U },
1887
  { Hexagon::M0, 73U },
1888
  { Hexagon::M1, 74U },
1889
  { Hexagon::P0, 63U },
1890
  { Hexagon::P1, 64U },
1891
  { Hexagon::P2, 65U },
1892
  { Hexagon::P3, 66U },
1893
  { Hexagon::Q0, 131U },
1894
  { Hexagon::Q1, 132U },
1895
  { Hexagon::Q2, 133U },
1896
  { Hexagon::Q3, 134U },
1897
  { Hexagon::R0, 0U },
1898
  { Hexagon::R1, 1U },
1899
  { Hexagon::R2, 2U },
1900
  { Hexagon::R3, 3U },
1901
  { Hexagon::R4, 4U },
1902
  { Hexagon::R5, 5U },
1903
  { Hexagon::R6, 6U },
1904
  { Hexagon::R7, 7U },
1905
  { Hexagon::R8, 8U },
1906
  { Hexagon::R9, 9U },
1907
  { Hexagon::R10, 10U },
1908
  { Hexagon::R11, 11U },
1909
  { Hexagon::R12, 12U },
1910
  { Hexagon::R13, 13U },
1911
  { Hexagon::R14, 14U },
1912
  { Hexagon::R15, 15U },
1913
  { Hexagon::R16, 16U },
1914
  { Hexagon::R17, 17U },
1915
  { Hexagon::R18, 18U },
1916
  { Hexagon::R19, 19U },
1917
  { Hexagon::R20, 20U },
1918
  { Hexagon::R21, 21U },
1919
  { Hexagon::R22, 22U },
1920
  { Hexagon::R23, 23U },
1921
  { Hexagon::R24, 24U },
1922
  { Hexagon::R25, 25U },
1923
  { Hexagon::R26, 26U },
1924
  { Hexagon::R27, 27U },
1925
  { Hexagon::R28, 28U },
1926
  { Hexagon::R29, 29U },
1927
  { Hexagon::R30, 30U },
1928
  { Hexagon::R31, 31U },
1929
  { Hexagon::SA0, 67U },
1930
  { Hexagon::SA1, 69U },
1931
  { Hexagon::V0, 99U },
1932
  { Hexagon::V1, 100U },
1933
  { Hexagon::V2, 101U },
1934
  { Hexagon::V3, 102U },
1935
  { Hexagon::V4, 103U },
1936
  { Hexagon::V5, 104U },
1937
  { Hexagon::V6, 105U },
1938
  { Hexagon::V7, 106U },
1939
  { Hexagon::V8, 107U },
1940
  { Hexagon::V9, 108U },
1941
  { Hexagon::V10, 109U },
1942
  { Hexagon::V11, 110U },
1943
  { Hexagon::V12, 111U },
1944
  { Hexagon::V13, 112U },
1945
  { Hexagon::V14, 113U },
1946
  { Hexagon::V15, 114U },
1947
  { Hexagon::V16, 115U },
1948
  { Hexagon::V17, 116U },
1949
  { Hexagon::V18, 117U },
1950
  { Hexagon::V19, 118U },
1951
  { Hexagon::V20, 119U },
1952
  { Hexagon::V21, 120U },
1953
  { Hexagon::V22, 121U },
1954
  { Hexagon::V23, 122U },
1955
  { Hexagon::V24, 123U },
1956
  { Hexagon::V25, 124U },
1957
  { Hexagon::V26, 125U },
1958
  { Hexagon::V27, 126U },
1959
  { Hexagon::V28, 127U },
1960
  { Hexagon::V29, 128U },
1961
  { Hexagon::V30, 129U },
1962
  { Hexagon::V31, 130U },
1963
  { Hexagon::VQ0, 252U },
1964
  { Hexagon::VQ1, 253U },
1965
  { Hexagon::VQ2, 254U },
1966
  { Hexagon::VQ3, 255U },
1967
  { Hexagon::VQ4, 256U },
1968
  { Hexagon::VQ5, 257U },
1969
  { Hexagon::VQ6, 258U },
1970
  { Hexagon::VQ7, 259U },
1971
  { Hexagon::W0, 99U },
1972
  { Hexagon::W1, 101U },
1973
  { Hexagon::W2, 103U },
1974
  { Hexagon::W3, 105U },
1975
  { Hexagon::W4, 107U },
1976
  { Hexagon::W5, 109U },
1977
  { Hexagon::W6, 111U },
1978
  { Hexagon::W7, 113U },
1979
  { Hexagon::W8, 115U },
1980
  { Hexagon::W9, 117U },
1981
  { Hexagon::W10, 119U },
1982
  { Hexagon::W11, 121U },
1983
  { Hexagon::W12, 123U },
1984
  { Hexagon::W13, 125U },
1985
  { Hexagon::W14, 127U },
1986
  { Hexagon::W15, 129U },
1987
  { Hexagon::C1_0, 67U },
1988
  { Hexagon::C3_2, 69U },
1989
  { Hexagon::C5_4, 71U },
1990
  { Hexagon::C7_6, 72U },
1991
  { Hexagon::C9_8, 74U },
1992
  { Hexagon::C11_10, 76U },
1993
  { Hexagon::C17_16, 83U },
1994
  { Hexagon::G1_0, 220U },
1995
  { Hexagon::G3_2, 222U },
1996
  { Hexagon::G5_4, 224U },
1997
  { Hexagon::G7_6, 226U },
1998
  { Hexagon::G9_8, 228U },
1999
  { Hexagon::G11_10, 230U },
2000
  { Hexagon::G13_12, 232U },
2001
  { Hexagon::G15_14, 234U },
2002
  { Hexagon::G17_16, 236U },
2003
  { Hexagon::G19_18, 238U },
2004
  { Hexagon::G21_20, 240U },
2005
  { Hexagon::G23_22, 242U },
2006
  { Hexagon::G25_24, 244U },
2007
  { Hexagon::G27_26, 246U },
2008
  { Hexagon::G29_28, 248U },
2009
  { Hexagon::G31_30, 250U },
2010
  { Hexagon::P3_0, 71U },
2011
};
2012
extern const unsigned HexagonEHFlavour0L2DwarfSize = array_lengthof(HexagonEHFlavour0L2Dwarf);
2013
2014
extern const uint16_t HexagonRegEncodingTable[] = {
2015
  0,
2016
  12,
2017
  17,
2018
  16,
2019
  0,
2020
  2,
2021
  11,
2022
  25,
2023
  24,
2024
  1,
2025
  9,
2026
  18,
2027
  19,
2028
  18,
2029
  10,
2030
  14,
2031
  15,
2032
  14,
2033
  8,
2034
  0,
2035
  30,
2036
  31,
2037
  30,
2038
  0,
2039
  5,
2040
  8,
2041
  12,
2042
  13,
2043
  0,
2044
  2,
2045
  4,
2046
  6,
2047
  8,
2048
  10,
2049
  12,
2050
  14,
2051
  16,
2052
  18,
2053
  20,
2054
  22,
2055
  24,
2056
  26,
2057
  28,
2058
  30,
2059
  3,
2060
  4,
2061
  5,
2062
  6,
2063
  7,
2064
  8,
2065
  9,
2066
  10,
2067
  11,
2068
  12,
2069
  13,
2070
  14,
2071
  15,
2072
  20,
2073
  21,
2074
  22,
2075
  23,
2076
  30,
2077
  31,
2078
  26,
2079
  27,
2080
  28,
2081
  29,
2082
  16,
2083
  17,
2084
  18,
2085
  19,
2086
  1,
2087
  3,
2088
  6,
2089
  7,
2090
  0,
2091
  1,
2092
  2,
2093
  3,
2094
  0,
2095
  1,
2096
  2,
2097
  3,
2098
  0,
2099
  1,
2100
  2,
2101
  3,
2102
  4,
2103
  5,
2104
  6,
2105
  7,
2106
  8,
2107
  9,
2108
  10,
2109
  11,
2110
  12,
2111
  13,
2112
  14,
2113
  15,
2114
  16,
2115
  17,
2116
  18,
2117
  19,
2118
  20,
2119
  21,
2120
  22,
2121
  23,
2122
  24,
2123
  25,
2124
  26,
2125
  27,
2126
  28,
2127
  29,
2128
  30,
2129
  31,
2130
  0,
2131
  2,
2132
  0,
2133
  1,
2134
  2,
2135
  3,
2136
  4,
2137
  5,
2138
  6,
2139
  7,
2140
  8,
2141
  9,
2142
  10,
2143
  11,
2144
  12,
2145
  13,
2146
  14,
2147
  15,
2148
  16,
2149
  17,
2150
  18,
2151
  19,
2152
  20,
2153
  21,
2154
  22,
2155
  23,
2156
  24,
2157
  25,
2158
  26,
2159
  27,
2160
  28,
2161
  29,
2162
  30,
2163
  31,
2164
  0,
2165
  4,
2166
  8,
2167
  12,
2168
  16,
2169
  20,
2170
  24,
2171
  28,
2172
  0,
2173
  2,
2174
  4,
2175
  6,
2176
  8,
2177
  10,
2178
  12,
2179
  14,
2180
  16,
2181
  18,
2182
  20,
2183
  22,
2184
  24,
2185
  26,
2186
  28,
2187
  30,
2188
  0,
2189
  2,
2190
  4,
2191
  6,
2192
  8,
2193
  10,
2194
  16,
2195
  0,
2196
  2,
2197
  4,
2198
  6,
2199
  8,
2200
  10,
2201
  12,
2202
  14,
2203
  16,
2204
  18,
2205
  20,
2206
  22,
2207
  24,
2208
  26,
2209
  28,
2210
  30,
2211
  4,
2212
};
2213
1.27k
static inline void InitHexagonMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
2214
1.27k
  RI->InitMCRegisterInfo(HexagonRegDesc, 197, RA, PC, HexagonMCRegisterClasses, 25, HexagonRegUnitRoots, 127, HexagonRegDiffLists, HexagonLaneMaskLists, HexagonRegStrings, HexagonRegClassStrings, HexagonSubRegIdxLists, 10,
2215
1.27k
HexagonSubRegIdxRanges, HexagonRegEncodingTable);
2216
1.27k
2217
1.27k
  switch (DwarfFlavour) {
2218
1.27k
  default:
2219
0
    llvm_unreachable("Unknown DWARF flavour");
2220
1.27k
  case 0:
2221
1.27k
    RI->mapDwarfRegsToLLVMRegs(HexagonDwarfFlavour0Dwarf2L, HexagonDwarfFlavour0Dwarf2LSize, false);
2222
1.27k
    break;
2223
1.27k
  }
2224
1.27k
  switch (EHFlavour) {
2225
1.27k
  default:
2226
0
    llvm_unreachable("Unknown DWARF flavour");
2227
1.27k
  case 0:
2228
1.27k
    RI->mapDwarfRegsToLLVMRegs(HexagonEHFlavour0Dwarf2L, HexagonEHFlavour0Dwarf2LSize, true);
2229
1.27k
    break;
2230
1.27k
  }
2231
1.27k
  switch (DwarfFlavour) {
2232
1.27k
  default:
2233
0
    llvm_unreachable("Unknown DWARF flavour");
2234
1.27k
  case 0:
2235
1.27k
    RI->mapLLVMRegsToDwarfRegs(HexagonDwarfFlavour0L2Dwarf, HexagonDwarfFlavour0L2DwarfSize, false);
2236
1.27k
    break;
2237
1.27k
  }
2238
1.27k
  switch (EHFlavour) {
2239
1.27k
  default:
2240
0
    llvm_unreachable("Unknown DWARF flavour");
2241
1.27k
  case 0:
2242
1.27k
    RI->mapLLVMRegsToDwarfRegs(HexagonEHFlavour0L2Dwarf, HexagonEHFlavour0L2DwarfSize, true);
2243
1.27k
    break;
2244
1.27k
  }
2245
1.27k
}
2246
2247
} // end namespace llvm
2248
2249
#endif // GET_REGINFO_MC_DESC
2250
2251
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2252
|*                                                                            *|
2253
|* Register Information Header Fragment                                       *|
2254
|*                                                                            *|
2255
|* Automatically generated file, do not edit!                                 *|
2256
|*                                                                            *|
2257
\*===----------------------------------------------------------------------===*/
2258
2259
2260
#ifdef GET_REGINFO_HEADER
2261
#undef GET_REGINFO_HEADER
2262
2263
#include "llvm/CodeGen/TargetRegisterInfo.h"
2264
2265
namespace llvm {
2266
2267
class HexagonFrameLowering;
2268
2269
struct HexagonGenRegisterInfo : public TargetRegisterInfo {
2270
  explicit HexagonGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
2271
      unsigned PC = 0, unsigned HwMode = 0);
2272
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
2273
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
2274
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
2275
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
2276
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
2277
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
2278
  unsigned getNumRegPressureSets() const override;
2279
  const char *getRegPressureSetName(unsigned Idx) const override;
2280
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
2281
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
2282
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
2283
  ArrayRef<const char *> getRegMaskNames() const override;
2284
  ArrayRef<const uint32_t *> getRegMasks() const override;
2285
  /// Devirtualized TargetFrameLowering.
2286
  static const HexagonFrameLowering *getFrameLowering(
2287
      const MachineFunction &MF);
2288
};
2289
2290
namespace Hexagon { // Register classes
2291
  extern const TargetRegisterClass UsrBitsRegClass;
2292
  extern const TargetRegisterClass GuestRegsRegClass;
2293
  extern const TargetRegisterClass IntRegsRegClass;
2294
  extern const TargetRegisterClass CtrRegsRegClass;
2295
  extern const TargetRegisterClass GeneralSubRegsRegClass;
2296
  extern const TargetRegisterClass V62RegsRegClass;
2297
  extern const TargetRegisterClass IntRegsLow8RegClass;
2298
  extern const TargetRegisterClass CtrRegs_and_V62RegsRegClass;
2299
  extern const TargetRegisterClass PredRegsRegClass;
2300
  extern const TargetRegisterClass V62Regs_with_isub_hiRegClass;
2301
  extern const TargetRegisterClass ModRegsRegClass;
2302
  extern const TargetRegisterClass CtrRegs_with_subreg_overflowRegClass;
2303
  extern const TargetRegisterClass V65RegsRegClass;
2304
  extern const TargetRegisterClass DoubleRegsRegClass;
2305
  extern const TargetRegisterClass GuestRegs64RegClass;
2306
  extern const TargetRegisterClass CtrRegs64RegClass;
2307
  extern const TargetRegisterClass GeneralDoubleLow8RegsRegClass;
2308
  extern const TargetRegisterClass DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass;
2309
  extern const TargetRegisterClass CtrRegs64_and_V62RegsRegClass;
2310
  extern const TargetRegisterClass CtrRegs64_with_isub_hi_in_ModRegsRegClass;
2311
  extern const TargetRegisterClass HvxVRRegClass;
2312
  extern const TargetRegisterClass HvxQRRegClass;
2313
  extern const TargetRegisterClass HvxVR_and_V65RegsRegClass;
2314
  extern const TargetRegisterClass HvxWRRegClass;
2315
  extern const TargetRegisterClass HvxVQRRegClass;
2316
} // end namespace Hexagon
2317
2318
} // end namespace llvm
2319
2320
#endif // GET_REGINFO_HEADER
2321
2322
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2323
|*                                                                            *|
2324
|* Target Register and Register Classes Information                           *|
2325
|*                                                                            *|
2326
|* Automatically generated file, do not edit!                                 *|
2327
|*                                                                            *|
2328
\*===----------------------------------------------------------------------===*/
2329
2330
2331
#ifdef GET_REGINFO_TARGET_DESC
2332
#undef GET_REGINFO_TARGET_DESC
2333
2334
namespace llvm {
2335
2336
extern const MCRegisterClass HexagonMCRegisterClasses[];
2337
2338
static const MVT::SimpleValueType VTLists[] = {
2339
  /* 0 */ MVT::i1, MVT::Other,
2340
  /* 2 */ MVT::i1, MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v4i8, MVT::v2i16, MVT::i32, MVT::Other,
2341
  /* 10 */ MVT::i64, MVT::Other,
2342
  /* 12 */ MVT::v512i1, MVT::v64i1, MVT::v32i1, MVT::v16i1, MVT::Other,
2343
  /* 17 */ MVT::v1024i1, MVT::v128i1, MVT::v64i1, MVT::v32i1, MVT::Other,
2344
  /* 22 */ MVT::i32, MVT::f32, MVT::v4i8, MVT::v2i16, MVT::Other,
2345
  /* 27 */ MVT::i64, MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::Other,
2346
  /* 33 */ MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::Other,
2347
  /* 37 */ MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::Other,
2348
  /* 41 */ MVT::v256i8, MVT::v128i16, MVT::v64i32, MVT::Other,
2349
  /* 45 */ MVT::Untyped, MVT::Other,
2350
};
2351
2352
static const char *const SubRegIndexNameTable[] = { "isub_hi", "isub_lo", "subreg_overflow", "vsub_hi", "vsub_lo", "wsub_hi", "wsub_lo", "wsub_hi_then_vsub_hi", "wsub_hi_then_vsub_lo", "" };
2353
2354
2355
static const LaneBitmask SubRegIndexLaneMaskTable[] = {
2356
  LaneBitmask::getAll(),
2357
  LaneBitmask(0x00000001), // isub_hi
2358
  LaneBitmask(0x00000002), // isub_lo
2359
  LaneBitmask(0x00000004), // subreg_overflow
2360
  LaneBitmask(0x00000008), // vsub_hi
2361
  LaneBitmask(0x00000010), // vsub_lo
2362
  LaneBitmask(0x00000060), // wsub_hi
2363
  LaneBitmask(0x00000018), // wsub_lo
2364
  LaneBitmask(0x00000020), // wsub_hi_then_vsub_hi
2365
  LaneBitmask(0x00000040), // wsub_hi_then_vsub_lo
2366
 };
2367
2368
2369
2370
static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
2371
  // Mode = 0 (Default)
2372
  { 1, 1, 0, VTLists+0 },    // UsrBits
2373
  { 32, 32, 32, VTLists+8 },    // GuestRegs
2374
  { 32, 32, 32, VTLists+22 },    // IntRegs
2375
  { 32, 32, 32, VTLists+8 },    // CtrRegs
2376
  { 32, 32, 32, VTLists+8 },    // GeneralSubRegs
2377
  { 32, 32, 32, VTLists+8 },    // V62Regs
2378
  { 32, 32, 32, VTLists+8 },    // IntRegsLow8
2379
  { 32, 32, 32, VTLists+8 },    // CtrRegs_and_V62Regs
2380
  { 32, 32, 32, VTLists+2 },    // PredRegs
2381
  { 32, 32, 32, VTLists+8 },    // V62Regs_with_isub_hi
2382
  { 32, 32, 32, VTLists+8 },    // ModRegs
2383
  { 32, 32, 32, VTLists+8 },    // CtrRegs_with_subreg_overflow
2384
  { 32, 32, 32, VTLists+8 },    // V65Regs
2385
  { 64, 64, 64, VTLists+27 },    // DoubleRegs
2386
  { 64, 64, 64, VTLists+10 },    // GuestRegs64
2387
  { 64, 64, 64, VTLists+10 },    // CtrRegs64
2388
  { 64, 64, 64, VTLists+10 },    // GeneralDoubleLow8Regs
2389
  { 64, 64, 64, VTLists+10 },    // DoubleRegs_with_isub_hi_in_IntRegsLow8
2390
  { 64, 64, 64, VTLists+10 },    // CtrRegs64_and_V62Regs
2391
  { 64, 64, 64, VTLists+10 },    // CtrRegs64_with_isub_hi_in_ModRegs
2392
  { 512, 512, 512, VTLists+33 },    // HvxVR
2393
  { 512, 512, 512, VTLists+12 },    // HvxQR
2394
  { 512, 512, 512, VTLists+33 },    // HvxVR_and_V65Regs
2395
  { 1024, 1024, 1024, VTLists+37 },    // HvxWR
2396
  { 2048, 2048, 2048, VTLists+45 },    // HvxVQR
2397
  // Mode = 1 (Hvx128)
2398
  { 1, 1, 0, VTLists+0 },    // UsrBits
2399
  { 32, 32, 32, VTLists+8 },    // GuestRegs
2400
  { 32, 32, 32, VTLists+22 },    // IntRegs
2401
  { 32, 32, 32, VTLists+8 },    // CtrRegs
2402
  { 32, 32, 32, VTLists+8 },    // GeneralSubRegs
2403
  { 32, 32, 32, VTLists+8 },    // V62Regs
2404
  { 32, 32, 32, VTLists+8 },    // IntRegsLow8
2405
  { 32, 32, 32, VTLists+8 },    // CtrRegs_and_V62Regs
2406
  { 32, 32, 32, VTLists+2 },    // PredRegs
2407
  { 32, 32, 32, VTLists+8 },    // V62Regs_with_isub_hi
2408
  { 32, 32, 32, VTLists+8 },    // ModRegs
2409
  { 32, 32, 32, VTLists+8 },    // CtrRegs_with_subreg_overflow
2410
  { 32, 32, 32, VTLists+8 },    // V65Regs
2411
  { 64, 64, 64, VTLists+27 },    // DoubleRegs
2412
  { 64, 64, 64, VTLists+10 },    // GuestRegs64
2413
  { 64, 64, 64, VTLists+10 },    // CtrRegs64
2414
  { 64, 64, 64, VTLists+10 },    // GeneralDoubleLow8Regs
2415
  { 64, 64, 64, VTLists+10 },    // DoubleRegs_with_isub_hi_in_IntRegsLow8
2416
  { 64, 64, 64, VTLists+10 },    // CtrRegs64_and_V62Regs
2417
  { 64, 64, 64, VTLists+10 },    // CtrRegs64_with_isub_hi_in_ModRegs
2418
  { 1024, 1024, 1024, VTLists+37 },    // HvxVR
2419
  { 1024, 1024, 1024, VTLists+17 },    // HvxQR
2420
  { 1024, 1024, 1024, VTLists+37 },    // HvxVR_and_V65Regs
2421
  { 2048, 2048, 2048, VTLists+41 },    // HvxWR
2422
  { 4096, 4096, 4096, VTLists+45 },    // HvxVQR
2423
  // Mode = 2 (Hvx64)
2424
  { 1, 1, 0, VTLists+0 },    // UsrBits
2425
  { 32, 32, 32, VTLists+8 },    // GuestRegs
2426
  { 32, 32, 32, VTLists+22 },    // IntRegs
2427
  { 32, 32, 32, VTLists+8 },    // CtrRegs
2428
  { 32, 32, 32, VTLists+8 },    // GeneralSubRegs
2429
  { 32, 32, 32, VTLists+8 },    // V62Regs
2430
  { 32, 32, 32, VTLists+8 },    // IntRegsLow8
2431
  { 32, 32, 32, VTLists+8 },    // CtrRegs_and_V62Regs
2432
  { 32, 32, 32, VTLists+2 },    // PredRegs
2433
  { 32, 32, 32, VTLists+8 },    // V62Regs_with_isub_hi
2434
  { 32, 32, 32, VTLists+8 },    // ModRegs
2435
  { 32, 32, 32, VTLists+8 },    // CtrRegs_with_subreg_overflow
2436
  { 32, 32, 32, VTLists+8 },    // V65Regs
2437
  { 64, 64, 64, VTLists+27 },    // DoubleRegs
2438
  { 64, 64, 64, VTLists+10 },    // GuestRegs64
2439
  { 64, 64, 64, VTLists+10 },    // CtrRegs64
2440
  { 64, 64, 64, VTLists+10 },    // GeneralDoubleLow8Regs
2441
  { 64, 64, 64, VTLists+10 },    // DoubleRegs_with_isub_hi_in_IntRegsLow8
2442
  { 64, 64, 64, VTLists+10 },    // CtrRegs64_and_V62Regs
2443
  { 64, 64, 64, VTLists+10 },    // CtrRegs64_with_isub_hi_in_ModRegs
2444
  { 512, 512, 512, VTLists+33 },    // HvxVR
2445
  { 512, 512, 512, VTLists+12 },    // HvxQR
2446
  { 512, 512, 512, VTLists+33 },    // HvxVR_and_V65Regs
2447
  { 1024, 1024, 1024, VTLists+37 },    // HvxWR
2448
  { 2048, 2048, 2048, VTLists+45 },    // HvxVQR
2449
};
2450
2451
static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
2452
2453
static const uint32_t UsrBitsSubClassMask[] = {
2454
  0x00000001, 
2455
  0x00000800, // subreg_overflow
2456
};
2457
2458
static const uint32_t GuestRegsSubClassMask[] = {
2459
  0x00000002, 
2460
  0x00004000, // isub_hi
2461
  0x00004000, // isub_lo
2462
};
2463
2464
static const uint32_t IntRegsSubClassMask[] = {
2465
  0x00000054, 
2466
  0x00032000, // isub_hi
2467
  0x00032000, // isub_lo
2468
};
2469
2470
static const uint32_t CtrRegsSubClassMask[] = {
2471
  0x00000c88, 
2472
  0x000c8200, // isub_hi
2473
  0x000c8200, // isub_lo
2474
};
2475
2476
static const uint32_t GeneralSubRegsSubClassMask[] = {
2477
  0x00000050, 
2478
  0x00030000, // isub_hi
2479
  0x00030000, // isub_lo
2480
};
2481
2482
static const uint32_t V62RegsSubClassMask[] = {
2483
  0x000402a0, 
2484
  0x00040200, // isub_hi
2485
  0x00040200, // isub_lo
2486
};
2487
2488
static const uint32_t IntRegsLow8SubClassMask[] = {
2489
  0x00000040, 
2490
  0x00020000, // isub_hi
2491
  0x00020000, // isub_lo
2492
};
2493
2494
static const uint32_t CtrRegs_and_V62RegsSubClassMask[] = {
2495
  0x00000080, 
2496
  0x00040200, // isub_hi
2497
  0x00040200, // isub_lo
2498
};
2499
2500
static const uint32_t PredRegsSubClassMask[] = {
2501
  0x00000100, 
2502
};
2503
2504
static const uint32_t V62Regs_with_isub_hiSubClassMask[] = {
2505
  0x00040200, 
2506
};
2507
2508
static const uint32_t ModRegsSubClassMask[] = {
2509
  0x00000400, 
2510
  0x00080000, // isub_hi
2511
  0x00080000, // isub_lo
2512
};
2513
2514
static const uint32_t CtrRegs_with_subreg_overflowSubClassMask[] = {
2515
  0x00000800, 
2516
};
2517
2518
static const uint32_t V65RegsSubClassMask[] = {
2519
  0x00401000, 
2520
};
2521
2522
static const uint32_t DoubleRegsSubClassMask[] = {
2523
  0x00032000, 
2524
};
2525
2526
static const uint32_t GuestRegs64SubClassMask[] = {
2527
  0x00004000, 
2528
};
2529
2530
static const uint32_t CtrRegs64SubClassMask[] = {
2531
  0x000c8000, 
2532
};
2533
2534
static const uint32_t GeneralDoubleLow8RegsSubClassMask[] = {
2535
  0x00030000, 
2536
};
2537
2538
static const uint32_t DoubleRegs_with_isub_hi_in_IntRegsLow8SubClassMask[] = {
2539
  0x00020000, 
2540
};
2541
2542
static const uint32_t CtrRegs64_and_V62RegsSubClassMask[] = {
2543
  0x00040000, 
2544
};
2545
2546
static const uint32_t CtrRegs64_with_isub_hi_in_ModRegsSubClassMask[] = {
2547
  0x00080000, 
2548
};
2549
2550
static const uint32_t HvxVRSubClassMask[] = {
2551
  0x00500000, 
2552
  0x01800000, // vsub_hi
2553
  0x01800000, // vsub_lo
2554
  0x01000000, // wsub_hi_then_vsub_hi
2555
  0x01000000, // wsub_hi_then_vsub_lo
2556
};
2557
2558
static const uint32_t HvxQRSubClassMask[] = {
2559
  0x00200000, 
2560
};
2561
2562
static const uint32_t HvxVR_and_V65RegsSubClassMask[] = {
2563
  0x00400000, 
2564
};
2565
2566
static const uint32_t HvxWRSubClassMask[] = {
2567
  0x00800000, 
2568
  0x01000000, // wsub_hi
2569
  0x01000000, // wsub_lo
2570
};
2571
2572
static const uint32_t HvxVQRSubClassMask[] = {
2573
  0x01000000, 
2574
};
2575
2576
static const uint16_t SuperRegIdxSeqs[] = {
2577
  /* 0 */ 1, 2, 0,
2578
  /* 3 */ 3, 0,
2579
  /* 5 */ 6, 7, 0,
2580
  /* 8 */ 4, 5, 8, 9, 0,
2581
};
2582
2583
static const TargetRegisterClass *const GeneralSubRegsSuperclasses[] = {
2584
  &Hexagon::IntRegsRegClass,
2585
  nullptr
2586
};
2587
2588
static const TargetRegisterClass *const IntRegsLow8Superclasses[] = {
2589
  &Hexagon::IntRegsRegClass,
2590
  &Hexagon::GeneralSubRegsRegClass,
2591
  nullptr
2592
};
2593
2594
static const TargetRegisterClass *const CtrRegs_and_V62RegsSuperclasses[] = {
2595
  &Hexagon::CtrRegsRegClass,
2596
  &Hexagon::V62RegsRegClass,
2597
  nullptr
2598
};
2599
2600
static const TargetRegisterClass *const V62Regs_with_isub_hiSuperclasses[] = {
2601
  &Hexagon::V62RegsRegClass,
2602
  nullptr
2603
};
2604
2605
static const TargetRegisterClass *const ModRegsSuperclasses[] = {
2606
  &Hexagon::CtrRegsRegClass,
2607
  nullptr
2608
};
2609
2610
static const TargetRegisterClass *const CtrRegs_with_subreg_overflowSuperclasses[] = {
2611
  &Hexagon::CtrRegsRegClass,
2612
  nullptr
2613
};
2614
2615
static const TargetRegisterClass *const GeneralDoubleLow8RegsSuperclasses[] = {
2616
  &Hexagon::DoubleRegsRegClass,
2617
  nullptr
2618
};
2619
2620
static const TargetRegisterClass *const DoubleRegs_with_isub_hi_in_IntRegsLow8Superclasses[] = {
2621
  &Hexagon::DoubleRegsRegClass,
2622
  &Hexagon::GeneralDoubleLow8RegsRegClass,
2623
  nullptr
2624
};
2625
2626
static const TargetRegisterClass *const CtrRegs64_and_V62RegsSuperclasses[] = {
2627
  &Hexagon::V62RegsRegClass,
2628
  &Hexagon::V62Regs_with_isub_hiRegClass,
2629
  &Hexagon::CtrRegs64RegClass,
2630
  nullptr
2631
};
2632
2633
static const TargetRegisterClass *const CtrRegs64_with_isub_hi_in_ModRegsSuperclasses[] = {
2634
  &Hexagon::CtrRegs64RegClass,
2635
  nullptr
2636
};
2637
2638
static const TargetRegisterClass *const HvxVR_and_V65RegsSuperclasses[] = {
2639
  &Hexagon::V65RegsRegClass,
2640
  &Hexagon::HvxVRRegClass,
2641
  nullptr
2642
};
2643
2644
2645
namespace Hexagon {   // Register class instances
2646
  extern const TargetRegisterClass UsrBitsRegClass = {
2647
    &HexagonMCRegisterClasses[UsrBitsRegClassID],
2648
    UsrBitsSubClassMask,
2649
    SuperRegIdxSeqs + 3,
2650
    LaneBitmask(0x00000001),
2651
    0,
2652
    false, /* HasDisjunctSubRegs */
2653
    false, /* CoveredBySubRegs */
2654
    NullRegClasses,
2655
    nullptr
2656
  };
2657
2658
  extern const TargetRegisterClass GuestRegsRegClass = {
2659
    &HexagonMCRegisterClasses[GuestRegsRegClassID],
2660
    GuestRegsSubClassMask,
2661
    SuperRegIdxSeqs + 0,
2662
    LaneBitmask(0x00000001),
2663
    0,
2664
    false, /* HasDisjunctSubRegs */
2665
    false, /* CoveredBySubRegs */
2666
    NullRegClasses,
2667
    nullptr
2668
  };
2669
2670
  extern const TargetRegisterClass IntRegsRegClass = {
2671
    &HexagonMCRegisterClasses[IntRegsRegClassID],
2672
    IntRegsSubClassMask,
2673
    SuperRegIdxSeqs + 0,
2674
    LaneBitmask(0x00000001),
2675
    0,
2676
    false, /* HasDisjunctSubRegs */
2677
    false, /* CoveredBySubRegs */
2678
    NullRegClasses,
2679
    nullptr
2680
  };
2681
2682
  extern const TargetRegisterClass CtrRegsRegClass = {
2683
    &HexagonMCRegisterClasses[CtrRegsRegClassID],
2684
    CtrRegsSubClassMask,
2685
    SuperRegIdxSeqs + 0,
2686
    LaneBitmask(0x00000004),
2687
    0,
2688
    false, /* HasDisjunctSubRegs */
2689
    false, /* CoveredBySubRegs */
2690
    NullRegClasses,
2691
    nullptr
2692
  };
2693
2694
  extern const TargetRegisterClass GeneralSubRegsRegClass = {
2695
    &HexagonMCRegisterClasses[GeneralSubRegsRegClassID],
2696
    GeneralSubRegsSubClassMask,
2697
    SuperRegIdxSeqs + 0,
2698
    LaneBitmask(0x00000001),
2699
    0,
2700
    false, /* HasDisjunctSubRegs */
2701
    false, /* CoveredBySubRegs */
2702
    GeneralSubRegsSuperclasses,
2703
    nullptr
2704
  };
2705
2706
  extern const TargetRegisterClass V62RegsRegClass = {
2707
    &HexagonMCRegisterClasses[V62RegsRegClassID],
2708
    V62RegsSubClassMask,
2709
    SuperRegIdxSeqs + 0,
2710
    LaneBitmask(0x00000003),
2711
    0,
2712
    true, /* HasDisjunctSubRegs */
2713
    false, /* CoveredBySubRegs */
2714
    NullRegClasses,
2715
    nullptr
2716
  };
2717
2718
  extern const TargetRegisterClass IntRegsLow8RegClass = {
2719
    &HexagonMCRegisterClasses[IntRegsLow8RegClassID],
2720
    IntRegsLow8SubClassMask,
2721
    SuperRegIdxSeqs + 0,
2722
    LaneBitmask(0x00000001),
2723
    0,
2724
    false, /* HasDisjunctSubRegs */
2725
    false, /* CoveredBySubRegs */
2726
    IntRegsLow8Superclasses,
2727
    nullptr
2728
  };
2729
2730
  extern const TargetRegisterClass CtrRegs_and_V62RegsRegClass = {
2731
    &HexagonMCRegisterClasses[CtrRegs_and_V62RegsRegClassID],
2732
    CtrRegs_and_V62RegsSubClassMask,
2733
    SuperRegIdxSeqs + 0,
2734
    LaneBitmask(0x00000001),
2735
    0,
2736
    false, /* HasDisjunctSubRegs */
2737
    false, /* CoveredBySubRegs */
2738
    CtrRegs_and_V62RegsSuperclasses,
2739
    nullptr
2740
  };
2741
2742
  extern const TargetRegisterClass PredRegsRegClass = {
2743
    &HexagonMCRegisterClasses[PredRegsRegClassID],
2744
    PredRegsSubClassMask,
2745
    SuperRegIdxSeqs + 2,
2746
    LaneBitmask(0x00000001),
2747
    0,
2748
    false, /* HasDisjunctSubRegs */
2749
    false, /* CoveredBySubRegs */
2750
    NullRegClasses,
2751
    nullptr
2752
  };
2753
2754
  extern const TargetRegisterClass V62Regs_with_isub_hiRegClass = {
2755
    &HexagonMCRegisterClasses[V62Regs_with_isub_hiRegClassID],
2756
    V62Regs_with_isub_hiSubClassMask,
2757
    SuperRegIdxSeqs + 2,
2758
    LaneBitmask(0x00000003),
2759
    0,
2760
    true, /* HasDisjunctSubRegs */
2761
    true, /* CoveredBySubRegs */
2762
    V62Regs_with_isub_hiSuperclasses,
2763
    nullptr
2764
  };
2765
2766
  extern const TargetRegisterClass ModRegsRegClass = {
2767
    &HexagonMCRegisterClasses[ModRegsRegClassID],
2768
    ModRegsSubClassMask,
2769
    SuperRegIdxSeqs + 0,
2770
    LaneBitmask(0x00000001),
2771
    0,
2772
    false, /* HasDisjunctSubRegs */
2773
    false, /* CoveredBySubRegs */
2774
    ModRegsSuperclasses,
2775
    nullptr
2776
  };
2777
2778
  extern const TargetRegisterClass CtrRegs_with_subreg_overflowRegClass = {
2779
    &HexagonMCRegisterClasses[CtrRegs_with_subreg_overflowRegClassID],
2780
    CtrRegs_with_subreg_overflowSubClassMask,
2781
    SuperRegIdxSeqs + 2,
2782
    LaneBitmask(0x00000004),
2783
    0,
2784
    false, /* HasDisjunctSubRegs */
2785
    false, /* CoveredBySubRegs */
2786
    CtrRegs_with_subreg_overflowSuperclasses,
2787
    nullptr
2788
  };
2789
2790
  extern const TargetRegisterClass V65RegsRegClass = {
2791
    &HexagonMCRegisterClasses[V65RegsRegClassID],
2792
    V65RegsSubClassMask,
2793
    SuperRegIdxSeqs + 2,
2794
    LaneBitmask(0x00000001),
2795
    0,
2796
    false, /* HasDisjunctSubRegs */
2797
    false, /* CoveredBySubRegs */
2798
    NullRegClasses,
2799
    nullptr
2800
  };
2801
2802
  extern const TargetRegisterClass DoubleRegsRegClass = {
2803
    &HexagonMCRegisterClasses[DoubleRegsRegClassID],
2804
    DoubleRegsSubClassMask,
2805
    SuperRegIdxSeqs + 2,
2806
    LaneBitmask(0x00000003),
2807
    0,
2808
    true, /* HasDisjunctSubRegs */
2809
    true, /* CoveredBySubRegs */
2810
    NullRegClasses,
2811
    nullptr
2812
  };
2813
2814
  extern const TargetRegisterClass GuestRegs64RegClass = {
2815
    &HexagonMCRegisterClasses[GuestRegs64RegClassID],
2816
    GuestRegs64SubClassMask,
2817
    SuperRegIdxSeqs + 2,
2818
    LaneBitmask(0x00000003),
2819
    0,
2820
    true, /* HasDisjunctSubRegs */
2821
    true, /* CoveredBySubRegs */
2822
    NullRegClasses,
2823
    nullptr
2824
  };
2825
2826
  extern const TargetRegisterClass CtrRegs64RegClass = {
2827
    &HexagonMCRegisterClasses[CtrRegs64RegClassID],
2828
    CtrRegs64SubClassMask,
2829
    SuperRegIdxSeqs + 2,
2830
    LaneBitmask(0x00000003),
2831
    0,
2832
    true, /* HasDisjunctSubRegs */
2833
    true, /* CoveredBySubRegs */
2834
    NullRegClasses,
2835
    nullptr
2836
  };
2837
2838
  extern const TargetRegisterClass GeneralDoubleLow8RegsRegClass = {
2839
    &HexagonMCRegisterClasses[GeneralDoubleLow8RegsRegClassID],
2840
    GeneralDoubleLow8RegsSubClassMask,
2841
    SuperRegIdxSeqs + 2,
2842
    LaneBitmask(0x00000003),
2843
    0,
2844
    true, /* HasDisjunctSubRegs */
2845
    true, /* CoveredBySubRegs */
2846
    GeneralDoubleLow8RegsSuperclasses,
2847
    nullptr
2848
  };
2849
2850
  extern const TargetRegisterClass DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass = {
2851
    &HexagonMCRegisterClasses[DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID],
2852
    DoubleRegs_with_isub_hi_in_IntRegsLow8SubClassMask,
2853
    SuperRegIdxSeqs + 2,
2854
    LaneBitmask(0x00000003),
2855
    0,
2856
    true, /* HasDisjunctSubRegs */
2857
    true, /* CoveredBySubRegs */
2858
    DoubleRegs_with_isub_hi_in_IntRegsLow8Superclasses,
2859
    nullptr
2860
  };
2861
2862
  extern const TargetRegisterClass CtrRegs64_and_V62RegsRegClass = {
2863
    &HexagonMCRegisterClasses[CtrRegs64_and_V62RegsRegClassID],
2864
    CtrRegs64_and_V62RegsSubClassMask,
2865
    SuperRegIdxSeqs + 2,
2866
    LaneBitmask(0x00000003),
2867
    0,
2868
    true, /* HasDisjunctSubRegs */
2869
    true, /* CoveredBySubRegs */
2870
    CtrRegs64_and_V62RegsSuperclasses,
2871
    nullptr
2872
  };
2873
2874
  extern const TargetRegisterClass CtrRegs64_with_isub_hi_in_ModRegsRegClass = {
2875
    &HexagonMCRegisterClasses[CtrRegs64_with_isub_hi_in_ModRegsRegClassID],
2876
    CtrRegs64_with_isub_hi_in_ModRegsSubClassMask,
2877
    SuperRegIdxSeqs + 2,
2878
    LaneBitmask(0x00000003),
2879
    0,
2880
    true, /* HasDisjunctSubRegs */
2881
    true, /* CoveredBySubRegs */
2882
    CtrRegs64_with_isub_hi_in_ModRegsSuperclasses,
2883
    nullptr
2884
  };
2885
2886
  extern const TargetRegisterClass HvxVRRegClass = {
2887
    &HexagonMCRegisterClasses[HvxVRRegClassID],
2888
    HvxVRSubClassMask,
2889
    SuperRegIdxSeqs + 8,
2890
    LaneBitmask(0x00000001),
2891
    0,
2892
    false, /* HasDisjunctSubRegs */
2893
    false, /* CoveredBySubRegs */
2894
    NullRegClasses,
2895
    nullptr
2896
  };
2897
2898
  extern const TargetRegisterClass HvxQRRegClass = {
2899
    &HexagonMCRegisterClasses[HvxQRRegClassID],
2900
    HvxQRSubClassMask,
2901
    SuperRegIdxSeqs + 2,
2902
    LaneBitmask(0x00000001),
2903
    0,
2904
    false, /* HasDisjunctSubRegs */
2905
    false, /* CoveredBySubRegs */
2906
    NullRegClasses,
2907
    nullptr
2908
  };
2909
2910
  extern const TargetRegisterClass HvxVR_and_V65RegsRegClass = {
2911
    &HexagonMCRegisterClasses[HvxVR_and_V65RegsRegClassID],
2912
    HvxVR_and_V65RegsSubClassMask,
2913
    SuperRegIdxSeqs + 2,
2914
    LaneBitmask(0x00000001),
2915
    0,
2916
    false, /* HasDisjunctSubRegs */
2917
    false, /* CoveredBySubRegs */
2918
    HvxVR_and_V65RegsSuperclasses,
2919
    nullptr
2920
  };
2921
2922
  extern const TargetRegisterClass HvxWRRegClass = {
2923
    &HexagonMCRegisterClasses[HvxWRRegClassID],
2924
    HvxWRSubClassMask,
2925
    SuperRegIdxSeqs + 5,
2926
    LaneBitmask(0x00000018),
2927
    0,
2928
    true, /* HasDisjunctSubRegs */
2929
    true, /* CoveredBySubRegs */
2930
    NullRegClasses,
2931
    nullptr
2932
  };
2933
2934
  extern const TargetRegisterClass HvxVQRRegClass = {
2935
    &HexagonMCRegisterClasses[HvxVQRRegClassID],
2936
    HvxVQRSubClassMask,
2937
    SuperRegIdxSeqs + 2,
2938
    LaneBitmask(0x00000078),
2939
    0,
2940
    true, /* HasDisjunctSubRegs */
2941
    true, /* CoveredBySubRegs */
2942
    NullRegClasses,
2943
    nullptr
2944
  };
2945
2946
} // end namespace Hexagon
2947
2948
namespace {
2949
  const TargetRegisterClass* const RegisterClasses[] = {
2950
    &Hexagon::UsrBitsRegClass,
2951
    &Hexagon::GuestRegsRegClass,
2952
    &Hexagon::IntRegsRegClass,
2953
    &Hexagon::CtrRegsRegClass,
2954
    &Hexagon::GeneralSubRegsRegClass,
2955
    &Hexagon::V62RegsRegClass,
2956
    &Hexagon::IntRegsLow8RegClass,
2957
    &Hexagon::CtrRegs_and_V62RegsRegClass,
2958
    &Hexagon::PredRegsRegClass,
2959
    &Hexagon::V62Regs_with_isub_hiRegClass,
2960
    &Hexagon::ModRegsRegClass,
2961
    &Hexagon::CtrRegs_with_subreg_overflowRegClass,
2962
    &Hexagon::V65RegsRegClass,
2963
    &Hexagon::DoubleRegsRegClass,
2964
    &Hexagon::GuestRegs64RegClass,
2965
    &Hexagon::CtrRegs64RegClass,
2966
    &Hexagon::GeneralDoubleLow8RegsRegClass,
2967
    &Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass,
2968
    &Hexagon::CtrRegs64_and_V62RegsRegClass,
2969
    &Hexagon::CtrRegs64_with_isub_hi_in_ModRegsRegClass,
2970
    &Hexagon::HvxVRRegClass,
2971
    &Hexagon::HvxQRRegClass,
2972
    &Hexagon::HvxVR_and_V65RegsRegClass,
2973
    &Hexagon::HvxWRRegClass,
2974
    &Hexagon::HvxVQRRegClass,
2975
  };
2976
} // end anonymous namespace
2977
2978
static const TargetRegisterInfoDesc HexagonRegInfoDesc[] = { // Extra Descriptors
2979
  { 0, false },
2980
  { 0, false },
2981
  { 0, false },
2982
  { 0, false },
2983
  { 0, false },
2984
  { 0, false },
2985
  { 0, false },
2986
  { 0, false },
2987
  { 0, false },
2988
  { 0, false },
2989
  { 0, false },
2990
  { 0, false },
2991
  { 0, false },
2992
  { 0, false },
2993
  { 0, false },
2994
  { 0, false },
2995
  { 0, false },
2996
  { 0, false },
2997
  { 0, false },
2998
  { 0, false },
2999
  { 0, false },
3000
  { 0, false },
3001
  { 0, false },
3002
  { 0, true },
3003
  { 0, false },
3004
  { 0, false },
3005
  { 0, false },
3006
  { 0, false },
3007
  { 0, true },
3008
  { 0, true },
3009
  { 0, true },
3010
  { 0, true },
3011
  { 0, true },
3012
  { 0, true },
3013
  { 0, true },
3014
  { 0, true },
3015
  { 0, true },
3016
  { 0, true },
3017
  { 0, true },
3018
  { 0, true },
3019
  { 0, true },
3020
  { 0, true },
3021
  { 0, true },
3022
  { 0, true },
3023
  { 0, false },
3024
  { 0, false },
3025
  { 0, false },
3026
  { 0, false },
3027
  { 0, false },
3028
  { 0, false },
3029
  { 0, false },
3030
  { 0, false },
3031
  { 0, false },
3032
  { 0, false },
3033
  { 0, false },
3034
  { 0, false },
3035
  { 0, false },
3036
  { 0, false },
3037
  { 0, false },
3038
  { 0, false },
3039
  { 0, false },
3040
  { 0, false },
3041
  { 0, false },
3042
  { 0, false },
3043
  { 0, false },
3044
  { 0, false },
3045
  { 0, false },
3046
  { 0, false },
3047
  { 0, false },
3048
  { 0, false },
3049
  { 0, false },
3050
  { 0, false },
3051
  { 0, false },
3052
  { 0, true },
3053
  { 0, true },
3054
  { 0, true },
3055
  { 0, true },
3056
  { 0, true },
3057
  { 0, true },
3058
  { 0, true },
3059
  { 0, true },
3060
  { 0, true },
3061
  { 0, true },
3062
  { 0, true },
3063
  { 0, true },
3064
  { 0, true },
3065
  { 0, true },
3066
  { 0, true },
3067
  { 0, true },
3068
  { 0, true },
3069
  { 0, true },
3070
  { 0, true },
3071
  { 0, true },
3072
  { 0, true },
3073
  { 0, true },
3074
  { 0, true },
3075
  { 0, true },
3076
  { 0, true },
3077
  { 0, true },
3078
  { 0, true },
3079
  { 0, true },
3080
  { 0, true },
3081
  { 0, true },
3082
  { 0, true },
3083
  { 0, true },
3084
  { 0, true },
3085
  { 0, true },
3086
  { 0, true },
3087
  { 0, true },
3088
  { 0, true },
3089
  { 0, true },
3090
  { 0, true },
3091
  { 0, true },
3092
  { 0, true },
3093
  { 0, true },
3094
  { 0, false },
3095
  { 0, false },
3096
  { 0, true },
3097
  { 0, true },
3098
  { 0, true },
3099
  { 0, true },
3100
  { 0, true },
3101
  { 0, true },
3102
  { 0, true },
3103
  { 0, true },
3104
  { 0, true },
3105
  { 0, true },
3106
  { 0, true },
3107
  { 0, true },
3108
  { 0, true },
3109
  { 0, true },
3110
  { 0, true },
3111
  { 0, true },
3112
  { 0, true },
3113
  { 0, true },
3114
  { 0, true },
3115
  { 0, true },
3116
  { 0, true },
3117
  { 0, true },
3118
  { 0, true },
3119
  { 0, true },
3120
  { 0, true },
3121
  { 0, true },
3122
  { 0, true },
3123
  { 0, true },
3124
  { 0, true },
3125
  { 0, true },
3126
  { 0, true },
3127
  { 0, true },
3128
  { 0, true },
3129
  { 0, true },
3130
  { 0, true },
3131
  { 0, true },
3132
  { 0, true },
3133
  { 0, true },
3134
  { 0, true },
3135
  { 0, true },
3136
  { 0, true },
3137
  { 0, true },
3138
  { 0, true },
3139
  { 0, true },
3140
  { 0, true },
3141
  { 0, true },
3142
  { 0, true },
3143
  { 0, true },
3144
  { 0, true },
3145
  { 0, true },
3146
  { 0, true },
3147
  { 0, true },
3148
  { 0, true },
3149
  { 0, true },
3150
  { 0, true },
3151
  { 0, true },
3152
  { 0, false },
3153
  { 0, false },
3154
  { 0, false },
3155
  { 0, false },
3156
  { 0, false },
3157
  { 0, false },
3158
  { 0, false },
3159
  { 0, false },
3160
  { 0, false },
3161
  { 0, false },
3162
  { 0, false },
3163
  { 0, false },
3164
  { 0, false },
3165
  { 0, false },
3166
  { 0, false },
3167
  { 0, false },
3168
  { 0, false },
3169
  { 0, false },
3170
  { 0, false },
3171
  { 0, false },
3172
  { 0, false },
3173
  { 0, false },
3174
  { 0, false },
3175
  { 0, false },
3176
};
3177
132
unsigned HexagonGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
3178
132
  static const uint8_t RowMap[9] = {
3179
132
    0, 0, 0, 0, 0, 0, 1, 0, 0, 
3180
132
  };
3181
132
  static const uint8_t Rows[2][9] = {
3182
132
    { 0, 0, 0, 8, 9, 0, 0, 0, 0, },
3183
132
    { 0, 0, 0, 4, 5, 0, 0, 0, 0, },
3184
132
  };
3185
132
3186
132
  --IdxA; assert(IdxA < 9);
3187
132
  --IdxB; assert(IdxB < 9);
3188
132
  return Rows[RowMap[IdxA]][IdxB];
3189
132
}
3190
3191
  struct MaskRolOp {
3192
    LaneBitmask Mask;
3193
    uint8_t  RotateLeft;
3194
  };
3195
  static const MaskRolOp LaneMaskComposeSequences[] = {
3196
    { LaneBitmask(0xFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
3197
    { LaneBitmask(0xFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 2
3198
    { LaneBitmask(0xFFFFFFFF),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 4
3199
    { LaneBitmask(0xFFFFFFFF),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 6
3200
    { LaneBitmask(0xFFFFFFFF),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 8
3201
    { LaneBitmask(0xFFFFFFFF),  5 }, { LaneBitmask::getNone(), 0 },   // Sequence 10
3202
    { LaneBitmask(0xFFFFFFFF),  6 }, { LaneBitmask::getNone(), 0 }  // Sequence 12
3203
  };
3204
  static const MaskRolOp *const CompositeSequences[] = {
3205
    &LaneMaskComposeSequences[0], // to isub_hi
3206
    &LaneMaskComposeSequences[2], // to isub_lo
3207
    &LaneMaskComposeSequences[4], // to subreg_overflow
3208
    &LaneMaskComposeSequences[6], // to vsub_hi
3209
    &LaneMaskComposeSequences[8], // to vsub_lo
3210
    &LaneMaskComposeSequences[4], // to wsub_hi
3211
    &LaneMaskComposeSequences[0], // to wsub_lo
3212
    &LaneMaskComposeSequences[10], // to wsub_hi_then_vsub_hi
3213
    &LaneMaskComposeSequences[12] // to wsub_hi_then_vsub_lo
3214
  };
3215
3216
2.48k
LaneBitmask HexagonGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
3217
2.48k
  --IdxA; assert(IdxA < 9 && "Subregister index out of bounds");
3218
2.48k
  LaneBitmask Result;
3219
4.97k
  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); 
++Ops2.48k
) {
3220
2.48k
    LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
3221
2.48k
    if (unsigned S = Ops->RotateLeft)
3222
2.17k
      Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
3223
310
    else
3224
310
      Result |= LaneBitmask(M);
3225
2.48k
  }
3226
2.48k
  return Result;
3227
2.48k
}
3228
3229
18.9k
LaneBitmask HexagonGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
3230
18.9k
  LaneMask &= getSubRegIndexLaneMask(IdxA);
3231
18.9k
  --IdxA; assert(IdxA < 9 && "Subregister index out of bounds");
3232
18.9k
  LaneBitmask Result;
3233
37.8k
  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); 
++Ops18.9k
) {
3234
18.9k
    LaneBitmask::Type M = LaneMask.getAsInteger();
3235
18.9k
    if (unsigned S = Ops->RotateLeft)
3236
11.0k
      Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
3237
7.90k
    else
3238
7.90k
      Result |= LaneBitmask(M);
3239
18.9k
  }
3240
18.9k
  return Result;
3241
18.9k
}
3242
3243
4.15k
const TargetRegisterClass *HexagonGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
3244
4.15k
  static const uint8_t Table[25][9] = {
3245
4.15k
    { // UsrBits
3246
4.15k
      0,  // isub_hi
3247
4.15k
      0,  // isub_lo
3248
4.15k
      0,  // subreg_overflow
3249
4.15k
      0,  // vsub_hi
3250
4.15k
      0,  // vsub_lo
3251
4.15k
      0,  // wsub_hi
3252
4.15k
      0,  // wsub_lo
3253
4.15k
      0,  // wsub_hi_then_vsub_hi
3254
4.15k
      0,  // wsub_hi_then_vsub_lo
3255
4.15k
    },
3256
4.15k
    { // GuestRegs
3257
4.15k
      0,  // isub_hi
3258
4.15k
      0,  // isub_lo
3259
4.15k
      0,  // subreg_overflow
3260
4.15k
      0,  // vsub_hi
3261
4.15k
      0,  // vsub_lo
3262
4.15k
      0,  // wsub_hi
3263
4.15k
      0,  // wsub_lo
3264
4.15k
      0,  // wsub_hi_then_vsub_hi
3265
4.15k
      0,  // wsub_hi_then_vsub_lo
3266
4.15k
    },
3267
4.15k
    { // IntRegs
3268
4.15k
      0,  // isub_hi
3269
4.15k
      0,  // isub_lo
3270
4.15k
      0,  // subreg_overflow
3271
4.15k
      0,  // vsub_hi
3272
4.15k
      0,  // vsub_lo
3273
4.15k
      0,  // wsub_hi
3274
4.15k
      0,  // wsub_lo
3275
4.15k
      0,  // wsub_hi_then_vsub_hi
3276
4.15k
      0,  // wsub_hi_then_vsub_lo
3277
4.15k
    },
3278
4.15k
    { // CtrRegs
3279
4.15k
      0,  // isub_hi
3280
4.15k
      0,  // isub_lo
3281
4.15k
      12, // subreg_overflow -> CtrRegs_with_subreg_overflow
3282
4.15k
      0,  // vsub_hi
3283
4.15k
      0,  // vsub_lo
3284
4.15k
      0,  // wsub_hi
3285
4.15k
      0,  // wsub_lo
3286
4.15k
      0,  // wsub_hi_then_vsub_hi
3287
4.15k
      0,  // wsub_hi_then_vsub_lo
3288
4.15k
    },
3289
4.15k
    { // GeneralSubRegs
3290
4.15k
      0,  // isub_hi
3291
4.15k
      0,  // isub_lo
3292
4.15k
      0,  // subreg_overflow
3293
4.15k
      0,  // vsub_hi
3294
4.15k
      0,  // vsub_lo
3295
4.15k
      0,  // wsub_hi
3296
4.15k
      0,  // wsub_lo
3297
4.15k
      0,  // wsub_hi_then_vsub_hi
3298
4.15k
      0,  // wsub_hi_then_vsub_lo
3299
4.15k
    },
3300
4.15k
    { // V62Regs
3301
4.15k
      10, // isub_hi -> V62Regs_with_isub_hi
3302
4.15k
      10, // isub_lo -> V62Regs_with_isub_hi
3303
4.15k
      0,  // subreg_overflow
3304
4.15k
      0,  // vsub_hi
3305
4.15k
      0,  // vsub_lo
3306
4.15k
      0,  // wsub_hi
3307
4.15k
      0,  // wsub_lo
3308
4.15k
      0,  // wsub_hi_then_vsub_hi
3309
4.15k
      0,  // wsub_hi_then_vsub_lo
3310
4.15k
    },
3311
4.15k
    { // IntRegsLow8
3312
4.15k
      0,  // isub_hi
3313
4.15k
      0,  // isub_lo
3314
4.15k
      0,  // subreg_overflow
3315
4.15k
      0,  // vsub_hi
3316
4.15k
      0,  // vsub_lo
3317
4.15k
      0,  // wsub_hi
3318
4.15k
      0,  // wsub_lo
3319
4.15k
      0,  // wsub_hi_then_vsub_hi
3320
4.15k
      0,  // wsub_hi_then_vsub_lo
3321
4.15k
    },
3322
4.15k
    { // CtrRegs_and_V62Regs
3323
4.15k
      0,  // isub_hi
3324
4.15k
      0,  // isub_lo
3325
4.15k
      0,  // subreg_overflow
3326
4.15k
      0,  // vsub_hi
3327
4.15k
      0,  // vsub_lo
3328
4.15k
      0,  // wsub_hi
3329
4.15k
      0,  // wsub_lo
3330
4.15k
      0,  // wsub_hi_then_vsub_hi
3331
4.15k
      0,  // wsub_hi_then_vsub_lo
3332
4.15k
    },
3333
4.15k
    { // PredRegs
3334
4.15k
      0,  // isub_hi
3335
4.15k
      0,  // isub_lo
3336
4.15k
      0,  // subreg_overflow
3337
4.15k
      0,  // vsub_hi
3338
4.15k
      0,  // vsub_lo
3339
4.15k
      0,  // wsub_hi
3340
4.15k
      0,  // wsub_lo
3341
4.15k
      0,  // wsub_hi_then_vsub_hi
3342
4.15k
      0,  // wsub_hi_then_vsub_lo
3343
4.15k
    },
3344
4.15k
    { // V62Regs_with_isub_hi
3345
4.15k
      10, // isub_hi -> V62Regs_with_isub_hi
3346
4.15k
      10, // isub_lo -> V62Regs_with_isub_hi
3347
4.15k
      0,  // subreg_overflow
3348
4.15k
      0,  // vsub_hi
3349
4.15k
      0,  // vsub_lo
3350
4.15k
      0,  // wsub_hi
3351
4.15k
      0,  // wsub_lo
3352
4.15k
      0,  // wsub_hi_then_vsub_hi
3353
4.15k
      0,  // wsub_hi_then_vsub_lo
3354
4.15k
    },
3355
4.15k
    { // ModRegs
3356
4.15k
      0,  // isub_hi
3357
4.15k
      0,  // isub_lo
3358
4.15k
      0,  // subreg_overflow
3359
4.15k
      0,  // vsub_hi
3360
4.15k
      0,  // vsub_lo
3361
4.15k
      0,  // wsub_hi
3362
4.15k
      0,  // wsub_lo
3363
4.15k
      0,  // wsub_hi_then_vsub_hi
3364
4.15k
      0,  // wsub_hi_then_vsub_lo
3365
4.15k
    },
3366
4.15k
    { // CtrRegs_with_subreg_overflow
3367
4.15k
      0,  // isub_hi
3368
4.15k
      0,  // isub_lo
3369
4.15k
      12, // subreg_overflow -> CtrRegs_with_subreg_overflow
3370
4.15k
      0,  // vsub_hi
3371
4.15k
      0,  // vsub_lo
3372
4.15k
      0,  // wsub_hi
3373
4.15k
      0,  // wsub_lo
3374
4.15k
      0,  // wsub_hi_then_vsub_hi
3375
4.15k
      0,  // wsub_hi_then_vsub_lo
3376
4.15k
    },
3377
4.15k
    { // V65Regs
3378
4.15k
      0,  // isub_hi
3379
4.15k
      0,  // isub_lo
3380
4.15k
      0,  // subreg_overflow
3381
4.15k
      0,  // vsub_hi
3382
4.15k
      0,  // vsub_lo
3383
4.15k
      0,  // wsub_hi
3384
4.15k
      0,  // wsub_lo
3385
4.15k
      0,  // wsub_hi_then_vsub_hi
3386
4.15k
      0,  // wsub_hi_then_vsub_lo
3387
4.15k
    },
3388
4.15k
    { // DoubleRegs
3389
4.15k
      14, // isub_hi -> DoubleRegs
3390
4.15k
      14, // isub_lo -> DoubleRegs
3391
4.15k
      0,  // subreg_overflow
3392
4.15k
      0,  // vsub_hi
3393
4.15k
      0,  // vsub_lo
3394
4.15k
      0,  // wsub_hi
3395
4.15k
      0,  // wsub_lo
3396
4.15k
      0,  // wsub_hi_then_vsub_hi
3397
4.15k
      0,  // wsub_hi_then_vsub_lo
3398
4.15k
    },
3399
4.15k
    { // GuestRegs64
3400
4.15k
      15, // isub_hi -> GuestRegs64
3401
4.15k
      15, // isub_lo -> GuestRegs64
3402
4.15k
      0,  // subreg_overflow
3403
4.15k
      0,  // vsub_hi
3404
4.15k
      0,  // vsub_lo
3405
4.15k
      0,  // wsub_hi
3406
4.15k
      0,  // wsub_lo
3407
4.15k
      0,  // wsub_hi_then_vsub_hi
3408
4.15k
      0,  // wsub_hi_then_vsub_lo
3409
4.15k
    },
3410
4.15k
    { // CtrRegs64
3411
4.15k
      16, // isub_hi -> CtrRegs64
3412
4.15k
      16, // isub_lo -> CtrRegs64
3413
4.15k
      0,  // subreg_overflow
3414
4.15k
      0,  // vsub_hi
3415
4.15k
      0,  // vsub_lo
3416
4.15k
      0,  // wsub_hi
3417
4.15k
      0,  // wsub_lo
3418
4.15k
      0,  // wsub_hi_then_vsub_hi
3419
4.15k
      0,  // wsub_hi_then_vsub_lo
3420
4.15k
    },
3421
4.15k
    { // GeneralDoubleLow8Regs
3422
4.15k
      17, // isub_hi -> GeneralDoubleLow8Regs
3423
4.15k
      17, // isub_lo -> GeneralDoubleLow8Regs
3424
4.15k
      0,  // subreg_overflow
3425
4.15k
      0,  // vsub_hi
3426
4.15k
      0,  // vsub_lo
3427
4.15k
      0,  // wsub_hi
3428
4.15k
      0,  // wsub_lo
3429
4.15k
      0,  // wsub_hi_then_vsub_hi
3430
4.15k
      0,  // wsub_hi_then_vsub_lo
3431
4.15k
    },
3432
4.15k
    { // DoubleRegs_with_isub_hi_in_IntRegsLow8
3433
4.15k
      18, // isub_hi -> DoubleRegs_with_isub_hi_in_IntRegsLow8
3434
4.15k
      18, // isub_lo -> DoubleRegs_with_isub_hi_in_IntRegsLow8
3435
4.15k
      0,  // subreg_overflow
3436
4.15k
      0,  // vsub_hi
3437
4.15k
      0,  // vsub_lo
3438
4.15k
      0,  // wsub_hi
3439
4.15k
      0,  // wsub_lo
3440
4.15k
      0,  // wsub_hi_then_vsub_hi
3441
4.15k
      0,  // wsub_hi_then_vsub_lo
3442
4.15k
    },
3443
4.15k
    { // CtrRegs64_and_V62Regs
3444
4.15k
      19, // isub_hi -> CtrRegs64_and_V62Regs
3445
4.15k
      19, // isub_lo -> CtrRegs64_and_V62Regs
3446
4.15k
      0,  // subreg_overflow
3447
4.15k
      0,  // vsub_hi
3448
4.15k
      0,  // vsub_lo
3449
4.15k
      0,  // wsub_hi
3450
4.15k
      0,  // wsub_lo
3451
4.15k
      0,  // wsub_hi_then_vsub_hi
3452
4.15k
      0,  // wsub_hi_then_vsub_lo
3453
4.15k
    },
3454
4.15k
    { // CtrRegs64_with_isub_hi_in_ModRegs
3455
4.15k
      20, // isub_hi -> CtrRegs64_with_isub_hi_in_ModRegs
3456
4.15k
      20, // isub_lo -> CtrRegs64_with_isub_hi_in_ModRegs
3457
4.15k
      0,  // subreg_overflow
3458
4.15k
      0,  // vsub_hi
3459
4.15k
      0,  // vsub_lo
3460
4.15k
      0,  // wsub_hi
3461
4.15k
      0,  // wsub_lo
3462
4.15k
      0,  // wsub_hi_then_vsub_hi
3463
4.15k
      0,  // wsub_hi_then_vsub_lo
3464
4.15k
    },
3465
4.15k
    { // HvxVR
3466
4.15k
      0,  // isub_hi
3467
4.15k
      0,  // isub_lo
3468
4.15k
      0,  // subreg_overflow
3469
4.15k
      0,  // vsub_hi
3470
4.15k
      0,  // vsub_lo
3471
4.15k
      0,  // wsub_hi
3472
4.15k
      0,  // wsub_lo
3473
4.15k
      0,  // wsub_hi_then_vsub_hi
3474
4.15k
      0,  // wsub_hi_then_vsub_lo
3475
4.15k
    },
3476
4.15k
    { // HvxQR
3477
4.15k
      0,  // isub_hi
3478
4.15k
      0,  // isub_lo
3479
4.15k
      0,  // subreg_overflow
3480
4.15k
      0,  // vsub_hi
3481
4.15k
      0,  // vsub_lo
3482
4.15k
      0,  // wsub_hi
3483
4.15k
      0,  // wsub_lo
3484
4.15k
      0,  // wsub_hi_then_vsub_hi
3485
4.15k
      0,  // wsub_hi_then_vsub_lo
3486
4.15k
    },
3487
4.15k
    { // HvxVR_and_V65Regs
3488
4.15k
      0,  // isub_hi
3489
4.15k
      0,  // isub_lo
3490
4.15k
      0,  // subreg_overflow
3491
4.15k
      0,  // vsub_hi
3492
4.15k
      0,  // vsub_lo
3493
4.15k
      0,  // wsub_hi
3494
4.15k
      0,  // wsub_lo
3495
4.15k
      0,  // wsub_hi_then_vsub_hi
3496
4.15k
      0,  // wsub_hi_then_vsub_lo
3497
4.15k
    },
3498
4.15k
    { // HvxWR
3499
4.15k
      0,  // isub_hi
3500
4.15k
      0,  // isub_lo
3501
4.15k
      0,  // subreg_overflow
3502
4.15k
      24, // vsub_hi -> HvxWR
3503
4.15k
      24, // vsub_lo -> HvxWR
3504
4.15k
      0,  // wsub_hi
3505
4.15k
      0,  // wsub_lo
3506
4.15k
      0,  // wsub_hi_then_vsub_hi
3507
4.15k
      0,  // wsub_hi_then_vsub_lo
3508
4.15k
    },
3509
4.15k
    { // HvxVQR
3510
4.15k
      0,  // isub_hi
3511
4.15k
      0,  // isub_lo
3512
4.15k
      0,  // subreg_overflow
3513
4.15k
      25, // vsub_hi -> HvxVQR
3514
4.15k
      25, // vsub_lo -> HvxVQR
3515
4.15k
      25, // wsub_hi -> HvxVQR
3516
4.15k
      25, // wsub_lo -> HvxVQR
3517
4.15k
      25, // wsub_hi_then_vsub_hi -> HvxVQR
3518
4.15k
      25, // wsub_hi_then_vsub_lo -> HvxVQR
3519
4.15k
    },
3520
4.15k
  };
3521
4.15k
  assert(RC && "Missing regclass");
3522
4.15k
  if (!Idx) 
return RC0
;
3523
4.15k
  --Idx;
3524
4.15k
  assert(Idx < 9 && "Bad subreg");
3525
4.15k
  unsigned TV = Table[RC->getID()][Idx];
3526
4.15k
  return TV ? getRegClass(TV - 1) : 
nullptr0
;
3527
4.15k
}
3528
3529
/// Get the weight in units of pressure for this register class.
3530
const RegClassWeight &HexagonGenRegisterInfo::
3531
361k
getRegClassWeight(const TargetRegisterClass *RC) const {
3532
361k
  static const RegClassWeight RCWeightTable[] = {
3533
361k
    {0, 0},   // UsrBits
3534
361k
    {0, 0},   // GuestRegs
3535
361k
    {1, 32},    // IntRegs
3536
361k
    {0, 6},   // CtrRegs
3537
361k
    {1, 16},    // GeneralSubRegs
3538
361k
    {0, 0},   // V62Regs
3539
361k
    {1, 8},   // IntRegsLow8
3540
361k
    {0, 0},   // CtrRegs_and_V62Regs
3541
361k
    {1, 4},   // PredRegs
3542
361k
    {0, 0},   // V62Regs_with_isub_hi
3543
361k
    {1, 2},   // ModRegs
3544
361k
    {0, 0},   // CtrRegs_with_subreg_overflow
3545
361k
    {1, 1},   // V65Regs
3546
361k
    {2, 32},    // DoubleRegs
3547
361k
    {0, 0},   // GuestRegs64
3548
361k
    {0, 6},   // CtrRegs64
3549
361k
    {2, 16},    // GeneralDoubleLow8Regs
3550
361k
    {2, 8},   // DoubleRegs_with_isub_hi_in_IntRegsLow8
3551
361k
    {0, 0},   // CtrRegs64_and_V62Regs
3552
361k
    {2, 2},   // CtrRegs64_with_isub_hi_in_ModRegs
3553
361k
    {1, 33},    // HvxVR
3554
361k
    {1, 4},   // HvxQR
3555
361k
    {1, 1},   // HvxVR_and_V65Regs
3556
361k
    {2, 32},    // HvxWR
3557
361k
    {4, 32},    // HvxVQR
3558
361k
  };
3559
361k
  return RCWeightTable[RC->getID()];
3560
361k
}
3561
3562
/// Get the weight in units of pressure for this register unit.
3563
unsigned HexagonGenRegisterInfo::
3564
68.0k
getRegUnitWeight(unsigned RegUnit) const {
3565
68.0k
  assert(RegUnit < 127 && "invalid register unit");
3566
68.0k
  // All register units have unit weight.
3567
68.0k
  return 1;
3568
68.0k
}
3569
3570
3571
// Get the number of dimensions of register pressure.
3572
28.8k
unsigned HexagonGenRegisterInfo::getNumRegPressureSets() const {
3573
28.8k
  return 8;
3574
28.8k
}
3575
3576
// Get the name of this register unit pressure set.
3577
const char *HexagonGenRegisterInfo::
3578
0
getRegPressureSetName(unsigned Idx) const {
3579
0
  static const char *const PressureNameTable[] = {
3580
0
    "HvxVR_and_V65Regs",
3581
0
    "ModRegs",
3582
0
    "PredRegs",
3583
0
    "HvxQR",
3584
0
    "IntRegsLow8",
3585
0
    "GeneralSubRegs",
3586
0
    "IntRegs",
3587
0
    "HvxVR",
3588
0
  };
3589
0
  return PressureNameTable[Idx];
3590
0
}
3591
3592
// Get the register unit pressure limit for this dimension.
3593
// This limit must be adjusted dynamically for reserved registers.
3594
unsigned HexagonGenRegisterInfo::
3595
42.6k
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
3596
42.6k
  static const uint8_t PressureLimitTable[] = {
3597
42.6k
    1,    // 0: HvxVR_and_V65Regs
3598
42.6k
    2,    // 1: ModRegs
3599
42.6k
    4,    // 2: PredRegs
3600
42.6k
    4,    // 3: HvxQR
3601
42.6k
    8,    // 4: IntRegsLow8
3602
42.6k
    16,   // 5: GeneralSubRegs
3603
42.6k
    32,   // 6: IntRegs
3604
42.6k
    33,   // 7: HvxVR
3605
42.6k
  };
3606
42.6k
  return PressureLimitTable[Idx];
3607
42.6k
}
3608
3609
/// Table of pressure sets per register class or unit.
3610
static const int RCSetsTable[] = {
3611
  /* 0 */ 1, -1,
3612
  /* 2 */ 2, -1,
3613
  /* 4 */ 3, -1,
3614
  /* 6 */ 4, 5, 6, -1,
3615
  /* 10 */ 0, 7, -1,
3616
};
3617
3618
/// Get the dimensions of register pressure impacted by this register class.
3619
/// Returns a -1 terminated array of pressure set IDs
3620
const int* HexagonGenRegisterInfo::
3621
714k
getRegClassPressureSets(const TargetRegisterClass *RC) const {
3622
714k
  static const uint8_t RCSetStartTable[] = {
3623
714k
    1,1,8,1,7,1,6,1,2,1,0,1,1,8,1,1,7,6,1,1,11,4,10,11,11,};
3624
714k
  return &RCSetsTable[RCSetStartTable[RC->getID()]];
3625
714k
}
3626
3627
/// Get the dimensions of register pressure impacted by this register unit.
3628
/// Returns a -1 terminated array of pressure set IDs
3629
const int* HexagonGenRegisterInfo::
3630
68.0k
getRegUnitPressureSets(unsigned RegUnit) const {
3631
68.0k
  assert(RegUnit < 127 && "invalid register unit");
3632
68.0k
  static const uint8_t RUSetStartTable[] = {
3633
68.0k
    1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,10,1,6,6,6,6,6,6,6,6,8,8,8,8,8,8,8,8,7,7,7,7,7,7,7,7,8,8,8,8,8,8,8,8,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,2,2,2,2,4,4,4,4,1,1,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,};
3634
68.0k
  return &RCSetsTable[RUSetStartTable[RegUnit]];
3635
68.0k
}
3636
3637
extern const MCRegisterDesc HexagonRegDesc[];
3638
extern const MCPhysReg HexagonRegDiffLists[];
3639
extern const LaneBitmask HexagonLaneMaskLists[];
3640
extern const char HexagonRegStrings[];
3641
extern const char HexagonRegClassStrings[];
3642
extern const MCPhysReg HexagonRegUnitRoots[][2];
3643
extern const uint16_t HexagonSubRegIdxLists[];
3644
extern const MCRegisterInfo::SubRegCoveredBits HexagonSubRegIdxRanges[];
3645
extern const uint16_t HexagonRegEncodingTable[];
3646
// Hexagon Dwarf<->LLVM register mappings.
3647
extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0Dwarf2L[];
3648
extern const unsigned HexagonDwarfFlavour0Dwarf2LSize;
3649
3650
extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0Dwarf2L[];
3651
extern const unsigned HexagonEHFlavour0Dwarf2LSize;
3652
3653
extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0L2Dwarf[];
3654
extern const unsigned HexagonDwarfFlavour0L2DwarfSize;
3655
3656
extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0L2Dwarf[];
3657
extern const unsigned HexagonEHFlavour0L2DwarfSize;
3658
3659
HexagonGenRegisterInfo::
3660
HexagonGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
3661
      unsigned PC, unsigned HwMode)
3662
  : TargetRegisterInfo(HexagonRegInfoDesc, RegisterClasses, RegisterClasses+25,
3663
             SubRegIndexNameTable, SubRegIndexLaneMaskTable,
3664
1.00k
             LaneBitmask(0xFFFFFFFB), RegClassInfos, HwMode) {
3665
1.00k
  InitMCRegisterInfo(HexagonRegDesc, 197, RA, PC,
3666
1.00k
                     HexagonMCRegisterClasses, 25,
3667
1.00k
                     HexagonRegUnitRoots,
3668
1.00k
                     127,
3669
1.00k
                     HexagonRegDiffLists,
3670
1.00k
                     HexagonLaneMaskLists,
3671
1.00k
                     HexagonRegStrings,
3672
1.00k
                     HexagonRegClassStrings,
3673
1.00k
                     HexagonSubRegIdxLists,
3674
1.00k
                     10,
3675
1.00k
                     HexagonSubRegIdxRanges,
3676
1.00k
                     HexagonRegEncodingTable);
3677
1.00k
3678
1.00k
  switch (DwarfFlavour) {
3679
1.00k
  default:
3680
0
    llvm_unreachable("Unknown DWARF flavour");
3681
1.00k
  case 0:
3682
1.00k
    mapDwarfRegsToLLVMRegs(HexagonDwarfFlavour0Dwarf2L, HexagonDwarfFlavour0Dwarf2LSize, false);
3683
1.00k
    break;
3684
1.00k
  }
3685
1.00k
  switch (EHFlavour) {
3686
1.00k
  default:
3687
0
    llvm_unreachable("Unknown DWARF flavour");
3688
1.00k
  case 0:
3689
1.00k
    mapDwarfRegsToLLVMRegs(HexagonEHFlavour0Dwarf2L, HexagonEHFlavour0Dwarf2LSize, true);
3690
1.00k
    break;
3691
1.00k
  }
3692
1.00k
  switch (DwarfFlavour) {
3693
1.00k
  default:
3694
0
    llvm_unreachable("Unknown DWARF flavour");
3695
1.00k
  case 0:
3696
1.00k
    mapLLVMRegsToDwarfRegs(HexagonDwarfFlavour0L2Dwarf, HexagonDwarfFlavour0L2DwarfSize, false);
3697
1.00k
    break;
3698
1.00k
  }
3699
1.00k
  switch (EHFlavour) {
3700
1.00k
  default:
3701
0
    llvm_unreachable("Unknown DWARF flavour");
3702
1.00k
  case 0:
3703
1.00k
    mapLLVMRegsToDwarfRegs(HexagonEHFlavour0L2Dwarf, HexagonEHFlavour0L2DwarfSize, true);
3704
1.00k
    break;
3705
1.00k
  }
3706
1.00k
}
3707
3708
static const MCPhysReg HexagonCSR_SaveList[] = { Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 };
3709
static const uint32_t HexagonCSR_RegMask[] = { 0x00000000, 0x000003f0, 0x00000000, 0x00007ff8, 0x00000000, 0x00000000, 0x00000000, };
3710
3711
3712
6.75k
ArrayRef<const uint32_t *> HexagonGenRegisterInfo::getRegMasks() const {
3713
6.75k
  static const uint32_t *const Masks[] = {
3714
6.75k
    HexagonCSR_RegMask,
3715
6.75k
  };
3716
6.75k
  return makeArrayRef(Masks);
3717
6.75k
}
3718
3719
4
ArrayRef<const char *> HexagonGenRegisterInfo::getRegMaskNames() const {
3720
4
  static const char *const Names[] = {
3721
4
    "HexagonCSR",
3722
4
  };
3723
4
  return makeArrayRef(Names);
3724
4
}
3725
3726
const HexagonFrameLowering *
3727
24
HexagonGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
3728
24
  return static_cast<const HexagonFrameLowering *>(
3729
24
      MF.getSubtarget().getFrameLowering());
3730
24
}
3731
3732
} // end namespace llvm
3733
3734
#endif // GET_REGINFO_TARGET_DESC
3735