Coverage Report

Created: 2018-11-16 02:38

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Lanai/LanaiGenAsmMatcher.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Assembly Matcher Source Fragment                                           *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
#ifdef GET_ASSEMBLER_HEADER
11
#undef GET_ASSEMBLER_HEADER
12
  // This should be included into the middle of the declaration of
13
  // your subclasses implementation of MCTargetAsmParser.
14
  uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;
15
  void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
16
                       const OperandVector &Operands);
17
  void convertToMapAndConstraints(unsigned Kind,
18
                           const OperandVector &Operands) override;
19
  unsigned MatchInstructionImpl(const OperandVector &Operands,
20
                                MCInst &Inst,
21
                                uint64_t &ErrorInfo,
22
                                bool matchingInlineAsm,
23
                                unsigned VariantID = 0);
24
  OperandMatchResultTy MatchOperandParserImpl(
25
    OperandVector &Operands,
26
    StringRef Mnemonic,
27
    bool ParseForAllFeatures = false);
28
  OperandMatchResultTy tryCustomParseOperand(
29
    OperandVector &Operands,
30
    unsigned MCK);
31
32
#endif // GET_ASSEMBLER_HEADER_INFO
33
34
35
#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
36
#undef GET_OPERAND_DIAGNOSTIC_TYPES
37
38
#endif // GET_OPERAND_DIAGNOSTIC_TYPES
39
40
41
#ifdef GET_REGISTER_MATCHER
42
#undef GET_REGISTER_MATCHER
43
44
// Flags for subtarget features that participate in instruction matching.
45
enum SubtargetFeatureFlag : uint8_t {
46
  Feature_None = 0
47
};
48
49
996
static unsigned MatchRegisterName(StringRef Name) {
50
996
  switch (Name.size()) {
51
996
  
default: break2
;
52
996
  case 2:  // 15 strings to match.
53
65
    switch (Name[0]) {
54
65
    
default: break2
;
55
65
    case 'f':  // 1 string to match.
56
0
      if (Name[1] != 'p')
57
0
        break;
58
0
      return 1;  // "fp"
59
3
    case 'p':  // 1 string to match.
60
3
      if (Name[1] != 'c')
61
0
        break;
62
3
      return 2;  // "pc"
63
60
    case 'r':  // 11 strings to match.
64
60
      switch (Name[1]) {
65
60
      
default: break0
;
66
60
      case '0':  // 1 string to match.
67
0
        return 7;  // "r0"
68
60
      case '1':  // 1 string to match.
69
0
        return 8;  // "r1"
70
60
      case '2':  // 1 string to match.
71
0
        return 9;  // "r2"
72
60
      case '3':  // 1 string to match.
73
4
        return 10;  // "r3"
74
60
      case '4':  // 1 string to match.
75
1
        return 11;  // "r4"
76
60
      case '5':  // 1 string to match.
77
1
        return 12;  // "r5"
78
60
      case '6':  // 1 string to match.
79
16
        return 13;  // "r6"
80
60
      case '7':  // 1 string to match.
81
13
        return 14;  // "r7"
82
60
      case '8':  // 1 string to match.
83
0
        return 15;  // "r8"
84
60
      case '9':  // 1 string to match.
85
25
        return 16;  // "r9"
86
60
      case 'v':  // 1 string to match.
87
0
        return 4;  // "rv"
88
0
      }
89
0
      break;
90
0
    case 's':  // 2 strings to match.
91
0
      switch (Name[1]) {
92
0
      default: break;
93
0
      case 'p':  // 1 string to match.
94
0
        return 5;  // "sp"
95
0
      case 'w':  // 1 string to match.
96
0
        return 6;  // "sw"
97
0
      }
98
0
      break;
99
2
    }
100
2
    break;
101
929
  case 3:  // 25 strings to match.
102
929
    if (Name[0] != 'r')
103
1
      break;
104
928
    switch (Name[1]) {
105
928
    
default: break0
;
106
928
    case '1':  // 10 strings to match.
107
613
      switch (Name[2]) {
108
613
      
default: break0
;
109
613
      case '0':  // 1 string to match.
110
0
        return 17;  // "r10"
111
613
      case '1':  // 1 string to match.
112
0
        return 18;  // "r11"
113
613
      case '2':  // 1 string to match.
114
26
        return 19;  // "r12"
115
613
      case '3':  // 1 string to match.
116
3
        return 20;  // "r13"
117
613
      case '4':  // 1 string to match.
118
3
        return 21;  // "r14"
119
613
      case '5':  // 1 string to match.
120
19
        return 22;  // "r15"
121
613
      case '6':  // 1 string to match.
122
0
        return 23;  // "r16"
123
613
      case '7':  // 1 string to match.
124
355
        return 24;  // "r17"
125
613
      case '8':  // 1 string to match.
126
144
        return 25;  // "r18"
127
613
      case '9':  // 1 string to match.
128
63
        return 26;  // "r19"
129
0
      }
130
0
      break;
131
314
    case '2':  // 10 strings to match.
132
314
      switch (Name[2]) {
133
314
      
default: break0
;
134
314
      case '0':  // 1 string to match.
135
7
        return 27;  // "r20"
136
314
      case '1':  // 1 string to match.
137
307
        return 28;  // "r21"
138
314
      case '2':  // 1 string to match.
139
0
        return 29;  // "r22"
140
314
      case '3':  // 1 string to match.
141
0
        return 30;  // "r23"
142
314
      case '4':  // 1 string to match.
143
0
        return 31;  // "r24"
144
314
      case '5':  // 1 string to match.
145
0
        return 32;  // "r25"
146
314
      case '6':  // 1 string to match.
147
0
        return 33;  // "r26"
148
314
      case '7':  // 1 string to match.
149
0
        return 34;  // "r27"
150
314
      case '8':  // 1 string to match.
151
0
        return 35;  // "r28"
152
314
      case '9':  // 1 string to match.
153
0
        return 36;  // "r29"
154
0
      }
155
0
      break;
156
1
    case '3':  // 2 strings to match.
157
1
      switch (Name[2]) {
158
1
      
default: break0
;
159
1
      case '0':  // 1 string to match.
160
1
        return 37;  // "r30"
161
1
      case '1':  // 1 string to match.
162
0
        return 38;  // "r31"
163
0
      }
164
0
      break;
165
0
    case 'c':  // 1 string to match.
166
0
      if (Name[2] != 'a')
167
0
        break;
168
0
      return 3;  // "rca"
169
0
    case 'r':  // 2 strings to match.
170
0
      switch (Name[2]) {
171
0
      default: break;
172
0
      case '1':  // 1 string to match.
173
0
        return 39;  // "rr1"
174
0
      case '2':  // 1 string to match.
175
0
        return 40;  // "rr2"
176
0
      }
177
0
      break;
178
0
    }
179
0
    break;
180
5
  }
181
5
  return 0;
182
5
}
183
184
#endif // GET_REGISTER_MATCHER
185
186
187
#ifdef GET_SUBTARGET_FEATURE_NAME
188
#undef GET_SUBTARGET_FEATURE_NAME
189
190
// User-level names for subtarget features that participate in
191
// instruction matching.
192
static const char *getSubtargetFeatureName(uint64_t Val) {
193
  return "(unknown)";
194
}
195
196
#endif // GET_SUBTARGET_FEATURE_NAME
197
198
199
#ifdef GET_MATCHER_IMPLEMENTATION
200
#undef GET_MATCHER_IMPLEMENTATION
201
202
static const uint8_t TiedAsmOperandTable[][3] = { /* empty  */ {0, 0, 0} };
203
204
namespace {
205
enum OperatorConversionKind {
206
  CVT_Done,
207
  CVT_Reg,
208
  CVT_Tied,
209
  CVT_95_addImmOperands,
210
  CVT_95_Reg,
211
  CVT_95_addHiImm16Operands,
212
  CVT_95_addLoImm16Operands,
213
  CVT_95_addCondCodeOperands,
214
  CVT_95_addHiImm16AndOperands,
215
  CVT_95_addLoImm16AndOperands,
216
  CVT_95_addBrTargetOperands,
217
  CVT_95_addMemImmOperands,
218
  CVT_95_addMemRegImmOperands,
219
  CVT_95_addMemRegRegOperands,
220
  CVT_95_addMemSplsOperands,
221
  CVT_regR0,
222
  CVT_imm_95_0,
223
  CVT_regR1,
224
  CVT_95_addLoImm21Operands,
225
  CVT_95_addImmShiftOperands,
226
  CVT_NUM_CONVERTERS
227
};
228
229
enum InstructionConversionKind {
230
  Convert__Imm1_0__Imm1_1,
231
  Convert__Reg1_0__Reg1_1,
232
  Convert__Reg1_2__Reg1_0__HiImm161_1,
233
  Convert__Reg1_2__Reg1_0__LoImm161_1,
234
  Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0,
235
  Convert__Reg1_2__Reg1_0__HiImm16And1_1,
236
  Convert__Reg1_2__Reg1_0__LoImm16And1_1,
237
  Convert__Reg1_1__Imm1_0,
238
  Convert__BrTarget1_1__Imm1_0,
239
  Convert__Imm1_2__Imm1_0,
240
  Convert__Reg1_1__Reg1_3__Imm1_0,
241
  Convert__Reg1_0,
242
  Convert__BrTarget1_0,
243
  Convert__Reg1_1__MemImm1_0,
244
  Convert__Reg1_1__MemRegImm3_0,
245
  Convert__Reg1_1__MemRegReg3_0,
246
  Convert_NoOperands,
247
  Convert__Reg1_1__MemSpls3_0,
248
  Convert__Reg1_1__Reg1_0,
249
  Convert__Reg1_1__Reg1_0__regR0__imm_95_0,
250
  Convert__Reg1_1__regR1__HiImm16And1_0,
251
  Convert__Reg1_1__regR0__HiImm161_0,
252
  Convert__Reg1_1__regR1__LoImm16And1_0,
253
  Convert__Reg1_1__regR0__LoImm161_0,
254
  Convert__Reg1_1__LoImm211_0,
255
  Convert__Reg1_3__Reg1_1__Reg1_2__Imm1_0,
256
  Convert__Reg1_2__Reg1_0__ImmShift1_1,
257
  Convert__Reg1_0__MemImm1_1,
258
  Convert__Reg1_0__MemRegImm3_1,
259
  Convert__Reg1_0__MemRegReg3_1,
260
  Convert__Reg1_0__MemSpls3_1,
261
  CVT_NUM_SIGNATURES
262
};
263
264
} // end anonymous namespace
265
266
static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][9] = {
267
  // Convert__Imm1_0__Imm1_1
268
  { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
269
  // Convert__Reg1_0__Reg1_1
270
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
271
  // Convert__Reg1_2__Reg1_0__HiImm161_1
272
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addHiImm16Operands, 2, CVT_Done },
273
  // Convert__Reg1_2__Reg1_0__LoImm161_1
274
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addLoImm16Operands, 2, CVT_Done },
275
  // Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0
276
  { CVT_95_Reg, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
277
  // Convert__Reg1_2__Reg1_0__HiImm16And1_1
278
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addHiImm16AndOperands, 2, CVT_Done },
279
  // Convert__Reg1_2__Reg1_0__LoImm16And1_1
280
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addLoImm16AndOperands, 2, CVT_Done },
281
  // Convert__Reg1_1__Imm1_0
282
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
283
  // Convert__BrTarget1_1__Imm1_0
284
  { CVT_95_addBrTargetOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
285
  // Convert__Imm1_2__Imm1_0
286
  { CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
287
  // Convert__Reg1_1__Reg1_3__Imm1_0
288
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addImmOperands, 1, CVT_Done },
289
  // Convert__Reg1_0
290
  { CVT_95_Reg, 1, CVT_Done },
291
  // Convert__BrTarget1_0
292
  { CVT_95_addBrTargetOperands, 1, CVT_Done },
293
  // Convert__Reg1_1__MemImm1_0
294
  { CVT_95_Reg, 2, CVT_95_addMemImmOperands, 1, CVT_Done },
295
  // Convert__Reg1_1__MemRegImm3_0
296
  { CVT_95_Reg, 2, CVT_95_addMemRegImmOperands, 1, CVT_Done },
297
  // Convert__Reg1_1__MemRegReg3_0
298
  { CVT_95_Reg, 2, CVT_95_addMemRegRegOperands, 1, CVT_Done },
299
  // Convert_NoOperands
300
  { CVT_Done },
301
  // Convert__Reg1_1__MemSpls3_0
302
  { CVT_95_Reg, 2, CVT_95_addMemSplsOperands, 1, CVT_Done },
303
  // Convert__Reg1_1__Reg1_0
304
  { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
305
  // Convert__Reg1_1__Reg1_0__regR0__imm_95_0
306
  { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_regR0, 0, CVT_imm_95_0, 0, CVT_Done },
307
  // Convert__Reg1_1__regR1__HiImm16And1_0
308
  { CVT_95_Reg, 2, CVT_regR1, 0, CVT_95_addHiImm16AndOperands, 1, CVT_Done },
309
  // Convert__Reg1_1__regR0__HiImm161_0
310
  { CVT_95_Reg, 2, CVT_regR0, 0, CVT_95_addHiImm16Operands, 1, CVT_Done },
311
  // Convert__Reg1_1__regR1__LoImm16And1_0
312
  { CVT_95_Reg, 2, CVT_regR1, 0, CVT_95_addLoImm16AndOperands, 1, CVT_Done },
313
  // Convert__Reg1_1__regR0__LoImm161_0
314
  { CVT_95_Reg, 2, CVT_regR0, 0, CVT_95_addLoImm16Operands, 1, CVT_Done },
315
  // Convert__Reg1_1__LoImm211_0
316
  { CVT_95_Reg, 2, CVT_95_addLoImm21Operands, 1, CVT_Done },
317
  // Convert__Reg1_3__Reg1_1__Reg1_2__Imm1_0
318
  { CVT_95_Reg, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
319
  // Convert__Reg1_2__Reg1_0__ImmShift1_1
320
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmShiftOperands, 2, CVT_Done },
321
  // Convert__Reg1_0__MemImm1_1
322
  { CVT_95_Reg, 1, CVT_95_addMemImmOperands, 2, CVT_Done },
323
  // Convert__Reg1_0__MemRegImm3_1
324
  { CVT_95_Reg, 1, CVT_95_addMemRegImmOperands, 2, CVT_Done },
325
  // Convert__Reg1_0__MemRegReg3_1
326
  { CVT_95_Reg, 1, CVT_95_addMemRegRegOperands, 2, CVT_Done },
327
  // Convert__Reg1_0__MemSpls3_1
328
  { CVT_95_Reg, 1, CVT_95_addMemSplsOperands, 2, CVT_Done },
329
};
330
331
void LanaiAsmParser::
332
convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
333
481
                const OperandVector &Operands) {
334
481
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
335
481
  const uint8_t *Converter = ConversionTable[Kind];
336
481
  unsigned OpIdx;
337
481
  Inst.setOpcode(Opcode);
338
1.57k
  for (const uint8_t *p = Converter; *p; 
p+= 21.09k
) {
339
1.09k
    OpIdx = *(p + 1);
340
1.09k
    switch (*p) {
341
1.09k
    
default: 0
llvm_unreachable0
("invalid conversion entry!");
342
1.09k
    case CVT_Reg:
343
0
      static_cast<LanaiOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
344
0
      break;
345
1.09k
    case CVT_Tied: {
346
0
      assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
347
0
                          std::begin(TiedAsmOperandTable)) &&
348
0
             "Tied operand not found");
349
0
      unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];
350
0
      if (TiedResOpnd != (uint8_t) -1)
351
0
        Inst.addOperand(Inst.getOperand(TiedResOpnd));
352
0
      break;
353
1.09k
    }
354
1.09k
    case CVT_95_addImmOperands:
355
99
      static_cast<LanaiOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
356
99
      break;
357
1.09k
    case CVT_95_Reg:
358
573
      static_cast<LanaiOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
359
573
      break;
360
1.09k
    case CVT_95_addHiImm16Operands:
361
16
      static_cast<LanaiOperand&>(*Operands[OpIdx]).addHiImm16Operands(Inst, 1);
362
16
      break;
363
1.09k
    case CVT_95_addLoImm16Operands:
364
26
      static_cast<LanaiOperand&>(*Operands[OpIdx]).addLoImm16Operands(Inst, 1);
365
26
      break;
366
1.09k
    case CVT_95_addCondCodeOperands:
367
23
      static_cast<LanaiOperand&>(*Operands[OpIdx]).addCondCodeOperands(Inst, 1);
368
23
      break;
369
1.09k
    case CVT_95_addHiImm16AndOperands:
370
3
      static_cast<LanaiOperand&>(*Operands[OpIdx]).addHiImm16AndOperands(Inst, 1);
371
3
      break;
372
1.09k
    case CVT_95_addLoImm16AndOperands:
373
3
      static_cast<LanaiOperand&>(*Operands[OpIdx]).addLoImm16AndOperands(Inst, 1);
374
3
      break;
375
1.09k
    case CVT_95_addBrTargetOperands:
376
27
      static_cast<LanaiOperand&>(*Operands[OpIdx]).addBrTargetOperands(Inst, 1);
377
27
      break;
378
1.09k
    case CVT_95_addMemImmOperands:
379
5
      static_cast<LanaiOperand&>(*Operands[OpIdx]).addMemImmOperands(Inst, 1);
380
5
      break;
381
1.09k
    case CVT_95_addMemRegImmOperands:
382
65
      static_cast<LanaiOperand&>(*Operands[OpIdx]).addMemRegImmOperands(Inst, 3);
383
65
      break;
384
1.09k
    case CVT_95_addMemRegRegOperands:
385
127
      static_cast<LanaiOperand&>(*Operands[OpIdx]).addMemRegRegOperands(Inst, 3);
386
127
      break;
387
1.09k
    case CVT_95_addMemSplsOperands:
388
102
      static_cast<LanaiOperand&>(*Operands[OpIdx]).addMemSplsOperands(Inst, 3);
389
102
      break;
390
1.09k
    case CVT_regR0:
391
7
      Inst.addOperand(MCOperand::createReg(Lanai::R0));
392
7
      break;
393
1.09k
    case CVT_imm_95_0:
394
1
      Inst.addOperand(MCOperand::createImm(0));
395
1
      break;
396
1.09k
    case CVT_regR1:
397
2
      Inst.addOperand(MCOperand::createReg(Lanai::R1));
398
2
      break;
399
1.09k
    case CVT_95_addLoImm21Operands:
400
1
      static_cast<LanaiOperand&>(*Operands[OpIdx]).addLoImm21Operands(Inst, 1);
401
1
      break;
402
1.09k
    case CVT_95_addImmShiftOperands:
403
16
      static_cast<LanaiOperand&>(*Operands[OpIdx]).addImmShiftOperands(Inst, 1);
404
16
      break;
405
1.09k
    }
406
1.09k
  }
407
481
}
408
409
void LanaiAsmParser::
410
convertToMapAndConstraints(unsigned Kind,
411
0
                           const OperandVector &Operands) {
412
0
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
413
0
  unsigned NumMCOperands = 0;
414
0
  const uint8_t *Converter = ConversionTable[Kind];
415
0
  for (const uint8_t *p = Converter; *p; p+= 2) {
416
0
    switch (*p) {
417
0
    default: llvm_unreachable("invalid conversion entry!");
418
0
    case CVT_Reg:
419
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
420
0
      Operands[*(p + 1)]->setConstraint("r");
421
0
      ++NumMCOperands;
422
0
      break;
423
0
    case CVT_Tied:
424
0
      ++NumMCOperands;
425
0
      break;
426
0
    case CVT_95_addImmOperands:
427
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
428
0
      Operands[*(p + 1)]->setConstraint("m");
429
0
      NumMCOperands += 1;
430
0
      break;
431
0
    case CVT_95_Reg:
432
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
433
0
      Operands[*(p + 1)]->setConstraint("r");
434
0
      NumMCOperands += 1;
435
0
      break;
436
0
    case CVT_95_addHiImm16Operands:
437
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
438
0
      Operands[*(p + 1)]->setConstraint("m");
439
0
      NumMCOperands += 1;
440
0
      break;
441
0
    case CVT_95_addLoImm16Operands:
442
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
443
0
      Operands[*(p + 1)]->setConstraint("m");
444
0
      NumMCOperands += 1;
445
0
      break;
446
0
    case CVT_95_addCondCodeOperands:
447
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
448
0
      Operands[*(p + 1)]->setConstraint("m");
449
0
      NumMCOperands += 1;
450
0
      break;
451
0
    case CVT_95_addHiImm16AndOperands:
452
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
453
0
      Operands[*(p + 1)]->setConstraint("m");
454
0
      NumMCOperands += 1;
455
0
      break;
456
0
    case CVT_95_addLoImm16AndOperands:
457
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
458
0
      Operands[*(p + 1)]->setConstraint("m");
459
0
      NumMCOperands += 1;
460
0
      break;
461
0
    case CVT_95_addBrTargetOperands:
462
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
463
0
      Operands[*(p + 1)]->setConstraint("m");
464
0
      NumMCOperands += 1;
465
0
      break;
466
0
    case CVT_95_addMemImmOperands:
467
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
468
0
      Operands[*(p + 1)]->setConstraint("m");
469
0
      NumMCOperands += 1;
470
0
      break;
471
0
    case CVT_95_addMemRegImmOperands:
472
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
473
0
      Operands[*(p + 1)]->setConstraint("m");
474
0
      NumMCOperands += 3;
475
0
      break;
476
0
    case CVT_95_addMemRegRegOperands:
477
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
478
0
      Operands[*(p + 1)]->setConstraint("m");
479
0
      NumMCOperands += 3;
480
0
      break;
481
0
    case CVT_95_addMemSplsOperands:
482
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
483
0
      Operands[*(p + 1)]->setConstraint("m");
484
0
      NumMCOperands += 3;
485
0
      break;
486
0
    case CVT_regR0:
487
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
488
0
      Operands[*(p + 1)]->setConstraint("m");
489
0
      ++NumMCOperands;
490
0
      break;
491
0
    case CVT_imm_95_0:
492
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
493
0
      Operands[*(p + 1)]->setConstraint("");
494
0
      ++NumMCOperands;
495
0
      break;
496
0
    case CVT_regR1:
497
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
498
0
      Operands[*(p + 1)]->setConstraint("m");
499
0
      ++NumMCOperands;
500
0
      break;
501
0
    case CVT_95_addLoImm21Operands:
502
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
503
0
      Operands[*(p + 1)]->setConstraint("m");
504
0
      NumMCOperands += 1;
505
0
      break;
506
0
    case CVT_95_addImmShiftOperands:
507
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
508
0
      Operands[*(p + 1)]->setConstraint("m");
509
0
      NumMCOperands += 1;
510
0
      break;
511
0
    }
512
0
  }
513
0
}
514
515
namespace {
516
517
/// MatchClassKind - The kinds of classes which participate in
518
/// instruction matching.
519
enum MatchClassKind {
520
  InvalidMatchClass = 0,
521
  OptionalMatchClass = 1,
522
  MCK__EXCLAIM_, // '!'
523
  MCK__PCT_fp, // '%fp'
524
  MCK__PCT_pc, // '%pc'
525
  MCK__MINUS_4, // '-4'
526
  MCK__DOT_r, // '.r'
527
  MCK__91_, // '['
528
  MCK__93_, // ']'
529
  MCK_add, // 'add'
530
  MCK_return, // 'return'
531
  MCK_LAST_TOKEN = MCK_return,
532
  MCK_CCR, // register class 'CCR'
533
  MCK_Reg1, // derived register class
534
  MCK_GPR, // register class 'GPR'
535
  MCK_LAST_REGISTER = MCK_GPR,
536
  MCK_BrTarget, // user defined class 'BrTargetAsmOperand'
537
  MCK_CallTarget, // user defined class 'CallTargetAsmOperand'
538
  MCK_CondCode, // user defined class 'CondCodeOperand'
539
  MCK_HiImm16And, // user defined class 'HiImm16AndAsmOperand'
540
  MCK_HiImm16, // user defined class 'HiImm16AsmOperand'
541
  MCK_Imm10, // user defined class 'Imm10AsmOperand'
542
  MCK_Imm, // user defined class 'ImmAsmOperand'
543
  MCK_ImmShift, // user defined class 'ImmShiftAsmOperand'
544
  MCK_LoImm16And, // user defined class 'LoImm16AndAsmOperand'
545
  MCK_LoImm16, // user defined class 'LoImm16AsmOperand'
546
  MCK_LoImm21, // user defined class 'LoImm21AsmOperand'
547
  MCK_MemImm, // user defined class 'MemImmAsmOperand'
548
  MCK_MemRegImm, // user defined class 'MemRegImmAsmOperand'
549
  MCK_MemRegReg, // user defined class 'MemRegRegAsmOperand'
550
  MCK_MemSpls, // user defined class 'MemSplsAsmOperand'
551
  NumMatchClassKinds
552
};
553
554
}
555
556
98
static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
557
98
  return MCTargetAsmParser::Match_InvalidOperand;
558
98
}
559
560
20
static MatchClassKind matchTokenString(StringRef Name) {
561
20
  switch (Name.size()) {
562
20
  
default: break0
;
563
20
  case 1:  // 3 strings to match.
564
0
    switch (Name[0]) {
565
0
    default: break;
566
0
    case '!':  // 1 string to match.
567
0
      return MCK__EXCLAIM_;  // "!"
568
0
    case '[':  // 1 string to match.
569
0
      return MCK__91_;  // "["
570
0
    case ']':  // 1 string to match.
571
0
      return MCK__93_;  // "]"
572
0
    }
573
0
    break;
574
20
  case 2:  // 2 strings to match.
575
20
    switch (Name[0]) {
576
20
    
default: break0
;
577
20
    case '-':  // 1 string to match.
578
0
      if (Name[1] != '4')
579
0
        break;
580
0
      return MCK__MINUS_4;   // "-4"
581
20
    case '.':  // 1 string to match.
582
20
      if (Name[1] != 'r')
583
0
        break;
584
20
      return MCK__DOT_r;  // ".r"
585
0
    }
586
0
    break;
587
0
  case 3:  // 3 strings to match.
588
0
    switch (Name[0]) {
589
0
    default: break;
590
0
    case '%':  // 2 strings to match.
591
0
      switch (Name[1]) {
592
0
      default: break;
593
0
      case 'f':  // 1 string to match.
594
0
        if (Name[2] != 'p')
595
0
          break;
596
0
        return MCK__PCT_fp;  // "%fp"
597
0
      case 'p':  // 1 string to match.
598
0
        if (Name[2] != 'c')
599
0
          break;
600
0
        return MCK__PCT_pc;  // "%pc"
601
0
      }
602
0
      break;
603
0
    case 'a':  // 1 string to match.
604
0
      if (memcmp(Name.data()+1, "dd", 2) != 0)
605
0
        break;
606
0
      return MCK_add;  // "add"
607
0
    }
608
0
    break;
609
0
  case 6:  // 1 string to match.
610
0
    if (memcmp(Name.data()+0, "return", 6) != 0)
611
0
      break;
612
0
    return MCK_return;  // "return"
613
0
  }
614
0
  return InvalidMatchClass;
615
0
}
616
617
/// isSubclass - Compute whether \p A is a subclass of \p B.
618
1.18k
static bool isSubclass(MatchClassKind A, MatchClassKind B) {
619
1.18k
  if (A == B)
620
734
    return true;
621
446
622
446
  switch (A) {
623
446
  default:
624
443
    return false;
625
446
626
446
  case MCK_Reg1:
627
3
    return B == MCK_GPR;
628
446
  }
629
446
}
630
631
1.77k
static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
632
1.77k
  LanaiOperand &Operand = (LanaiOperand&)GOp;
633
1.77k
  if (Kind == InvalidMatchClass)
634
20
    return MCTargetAsmParser::Match_InvalidOperand;
635
1.75k
636
1.75k
  if (Operand.isToken() && 
Kind <= MCK_LAST_TOKEN60
)
637
20
    return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
638
20
             MCTargetAsmParser::Match_Success :
639
20
             
MCTargetAsmParser::Match_InvalidOperand0
;
640
1.73k
641
1.73k
  switch (Kind) {
642
1.73k
  
default: break815
;
643
1.73k
  // 'BrTarget' class
644
1.73k
  case MCK_BrTarget: {
645
47
    DiagnosticPredicate DP(Operand.isBrTarget());
646
47
    if (DP.isMatch())
647
47
      return MCTargetAsmParser::Match_Success;
648
0
    break;
649
0
    }
650
0
  // 'CallTarget' class
651
0
  case MCK_CallTarget: {
652
0
    DiagnosticPredicate DP(Operand.isCallTarget());
653
0
    if (DP.isMatch())
654
0
      return MCTargetAsmParser::Match_Success;
655
0
    break;
656
0
    }
657
0
  // 'CondCode' class
658
23
  case MCK_CondCode: {
659
23
    DiagnosticPredicate DP(Operand.isCondCode());
660
23
    if (DP.isMatch())
661
23
      return MCTargetAsmParser::Match_Success;
662
0
    break;
663
0
    }
664
0
  // 'HiImm16And' class
665
13
  case MCK_HiImm16And: {
666
13
    DiagnosticPredicate DP(Operand.isHiImm16And());
667
13
    if (DP.isMatch())
668
3
      return MCTargetAsmParser::Match_Success;
669
10
    break;
670
10
    }
671
10
  // 'HiImm16' class
672
44
  case MCK_HiImm16: {
673
44
    DiagnosticPredicate DP(Operand.isHiImm16());
674
44
    if (DP.isMatch())
675
16
      return MCTargetAsmParser::Match_Success;
676
28
    break;
677
28
    }
678
28
  // 'Imm10' class
679
28
  case MCK_Imm10: {
680
0
    DiagnosticPredicate DP(Operand.isImm10());
681
0
    if (DP.isMatch())
682
0
      return MCTargetAsmParser::Match_Success;
683
0
    break;
684
0
    }
685
0
  // 'Imm' class
686
160
  case MCK_Imm: {
687
160
    DiagnosticPredicate DP(Operand.isImm());
688
160
    if (DP.isMatch())
689
160
      return MCTargetAsmParser::Match_Success;
690
0
    break;
691
0
    }
692
0
  // 'ImmShift' class
693
16
  case MCK_ImmShift: {
694
16
    DiagnosticPredicate DP(Operand.isImmShift());
695
16
    if (DP.isMatch())
696
16
      return MCTargetAsmParser::Match_Success;
697
0
    break;
698
0
    }
699
0
  // 'LoImm16And' class
700
6
  case MCK_LoImm16And: {
701
6
    DiagnosticPredicate DP(Operand.isLoImm16And());
702
6
    if (DP.isMatch())
703
3
      return MCTargetAsmParser::Match_Success;
704
3
    break;
705
3
    }
706
3
  // 'LoImm16' class
707
27
  case MCK_LoImm16: {
708
27
    DiagnosticPredicate DP(Operand.isLoImm16());
709
27
    if (DP.isMatch())
710
26
      return MCTargetAsmParser::Match_Success;
711
1
    break;
712
1
    }
713
1
  // 'LoImm21' class
714
1
  case MCK_LoImm21: {
715
1
    DiagnosticPredicate DP(Operand.isLoImm21());
716
1
    if (DP.isMatch())
717
1
      return MCTargetAsmParser::Match_Success;
718
0
    break;
719
0
    }
720
0
  // 'MemImm' class
721
119
  case MCK_MemImm: {
722
119
    DiagnosticPredicate DP(Operand.isMemImm());
723
119
    if (DP.isMatch())
724
5
      return MCTargetAsmParser::Match_Success;
725
114
    break;
726
114
    }
727
114
  // 'MemRegImm' class
728
132
  case MCK_MemRegImm: {
729
132
    DiagnosticPredicate DP(Operand.isMemRegImm());
730
132
    if (DP.isMatch())
731
65
      return MCTargetAsmParser::Match_Success;
732
67
    break;
733
67
    }
734
67
  // 'MemRegReg' class
735
229
  case MCK_MemRegReg: {
736
229
    DiagnosticPredicate DP(Operand.isMemRegReg());
737
229
    if (DP.isMatch())
738
127
      return MCTargetAsmParser::Match_Success;
739
102
    break;
740
102
    }
741
102
  // 'MemSpls' class
742
102
  case MCK_MemSpls: {
743
102
    DiagnosticPredicate DP(Operand.isMemSpls());
744
102
    if (DP.isMatch())
745
102
      return MCTargetAsmParser::Match_Success;
746
0
    break;
747
0
    }
748
1.14k
  } // end switch (Kind)
749
1.14k
750
1.14k
  if (Operand.isReg()) {
751
717
    MatchClassKind OpKind;
752
717
    switch (Operand.getReg()) {
753
717
    
default: OpKind = InvalidMatchClass; break0
;
754
717
    
case Lanai::R0: OpKind = MCK_GPR; break0
;
755
717
    
case Lanai::R1: OpKind = MCK_GPR; break0
;
756
717
    
case Lanai::R2: OpKind = MCK_GPR; break0
;
757
717
    
case Lanai::R3: OpKind = MCK_GPR; break8
;
758
717
    
case Lanai::R4: OpKind = MCK_GPR; break1
;
759
717
    
case Lanai::R5: OpKind = MCK_GPR; break1
;
760
717
    
case Lanai::R6: OpKind = MCK_GPR; break14
;
761
717
    
case Lanai::R7: OpKind = MCK_GPR; break3
;
762
717
    
case Lanai::R8: OpKind = MCK_GPR; break0
;
763
717
    
case Lanai::R9: OpKind = MCK_GPR; break18
;
764
717
    
case Lanai::R10: OpKind = MCK_GPR; break0
;
765
717
    
case Lanai::R11: OpKind = MCK_GPR; break0
;
766
717
    
case Lanai::R12: OpKind = MCK_GPR; break19
;
767
717
    
case Lanai::R13: OpKind = MCK_GPR; break3
;
768
717
    
case Lanai::R14: OpKind = MCK_GPR; break3
;
769
717
    
case Lanai::R15: OpKind = MCK_GPR; break19
;
770
717
    
case Lanai::R16: OpKind = MCK_GPR; break0
;
771
717
    
case Lanai::R17: OpKind = MCK_GPR; break229
;
772
717
    
case Lanai::R18: OpKind = MCK_GPR; break24
;
773
717
    
case Lanai::R19: OpKind = MCK_GPR; break3
;
774
717
    
case Lanai::R20: OpKind = MCK_GPR; break9
;
775
717
    
case Lanai::R21: OpKind = MCK_GPR; break359
;
776
717
    
case Lanai::R22: OpKind = MCK_GPR; break0
;
777
717
    
case Lanai::R23: OpKind = MCK_GPR; break0
;
778
717
    
case Lanai::R24: OpKind = MCK_GPR; break0
;
779
717
    
case Lanai::R25: OpKind = MCK_GPR; break0
;
780
717
    
case Lanai::R26: OpKind = MCK_GPR; break0
;
781
717
    
case Lanai::R27: OpKind = MCK_GPR; break0
;
782
717
    
case Lanai::R28: OpKind = MCK_GPR; break0
;
783
717
    
case Lanai::R29: OpKind = MCK_GPR; break0
;
784
717
    
case Lanai::R30: OpKind = MCK_GPR; break1
;
785
717
    
case Lanai::R31: OpKind = MCK_GPR; break0
;
786
717
    
case Lanai::PC: OpKind = MCK_Reg1; break3
;
787
717
    
case Lanai::SP: OpKind = MCK_Reg1; break0
;
788
717
    
case Lanai::FP: OpKind = MCK_Reg1; break0
;
789
717
    
case Lanai::RV: OpKind = MCK_Reg1; break0
;
790
717
    
case Lanai::RR1: OpKind = MCK_Reg1; break0
;
791
717
    
case Lanai::RR2: OpKind = MCK_Reg1; break0
;
792
717
    
case Lanai::RCA: OpKind = MCK_Reg1; break0
;
793
717
    
case Lanai::SR: OpKind = MCK_CCR; break0
;
794
717
    }
795
717
    return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
796
717
                                      
getDiagKindFromRegisterClass(Kind)0
;
797
717
  }
798
423
799
423
  if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
800
98
    return getDiagKindFromRegisterClass(Kind);
801
325
802
325
  return MCTargetAsmParser::Match_InvalidOperand;
803
325
}
804
805
#ifndef NDEBUG
806
const char *getMatchClassName(MatchClassKind Kind) {
807
  switch (Kind) {
808
  case InvalidMatchClass: return "InvalidMatchClass";
809
  case OptionalMatchClass: return "OptionalMatchClass";
810
  case MCK__EXCLAIM_: return "MCK__EXCLAIM_";
811
  case MCK__PCT_fp: return "MCK__PCT_fp";
812
  case MCK__PCT_pc: return "MCK__PCT_pc";
813
  case MCK__MINUS_4: return "MCK__MINUS_4";
814
  case MCK__DOT_r: return "MCK__DOT_r";
815
  case MCK__91_: return "MCK__91_";
816
  case MCK__93_: return "MCK__93_";
817
  case MCK_add: return "MCK_add";
818
  case MCK_return: return "MCK_return";
819
  case MCK_CCR: return "MCK_CCR";
820
  case MCK_Reg1: return "MCK_Reg1";
821
  case MCK_GPR: return "MCK_GPR";
822
  case MCK_BrTarget: return "MCK_BrTarget";
823
  case MCK_CallTarget: return "MCK_CallTarget";
824
  case MCK_CondCode: return "MCK_CondCode";
825
  case MCK_HiImm16And: return "MCK_HiImm16And";
826
  case MCK_HiImm16: return "MCK_HiImm16";
827
  case MCK_Imm10: return "MCK_Imm10";
828
  case MCK_Imm: return "MCK_Imm";
829
  case MCK_ImmShift: return "MCK_ImmShift";
830
  case MCK_LoImm16And: return "MCK_LoImm16And";
831
  case MCK_LoImm16: return "MCK_LoImm16";
832
  case MCK_LoImm21: return "MCK_LoImm21";
833
  case MCK_MemImm: return "MCK_MemImm";
834
  case MCK_MemRegImm: return "MCK_MemRegImm";
835
  case MCK_MemRegReg: return "MCK_MemRegReg";
836
  case MCK_MemSpls: return "MCK_MemSpls";
837
  case NumMatchClassKinds: return "NumMatchClassKinds";
838
  }
839
  llvm_unreachable("unhandled MatchClassKind!");
840
}
841
842
#endif // NDEBUG
843
uint64_t LanaiAsmParser::
844
4
ComputeAvailableFeatures(const FeatureBitset& FB) const {
845
4
  uint64_t Features = 0;
846
4
  return Features;
847
4
}
848
849
static bool checkAsmTiedOperandConstraints(const LanaiAsmParser&AsmParser,
850
                               unsigned Kind,
851
                               const OperandVector &Operands,
852
481
                               uint64_t &ErrorInfo) {
853
481
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
854
481
  const uint8_t *Converter = ConversionTable[Kind];
855
1.57k
  for (const uint8_t *p = Converter; *p; 
p+= 21.09k
) {
856
1.09k
    switch (*p) {
857
1.09k
    case CVT_Tied: {
858
0
      unsigned OpIdx = *(p+1);
859
0
      assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
860
0
                              std::begin(TiedAsmOperandTable)) &&
861
0
             "Tied operand not found");
862
0
      unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];
863
0
      unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];
864
0
      if (OpndNum1 != OpndNum2) {
865
0
        auto &SrcOp1 = Operands[OpndNum1];
866
0
        auto &SrcOp2 = Operands[OpndNum2];
867
0
        if (SrcOp1->isReg() && SrcOp2->isReg()) {
868
0
          if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) {
869
0
            ErrorInfo = OpndNum2;
870
0
            return false;
871
0
          }
872
0
        }
873
0
      }
874
0
      break;
875
0
    }
876
1.09k
    default:
877
1.09k
      break;
878
1.09k
    }
879
1.09k
  }
880
481
  return true;
881
481
}
882
883
static const char *const MnemonicTable =
884
    "\021#ADJCALLSTACKDOWN\017#ADJCALLSTACKUP\014#ADJDYNALLOC\003add\005add."
885
    "f\004addc\006addc.f\003and\005and.f\001b\002bt\002ld\004ld.b\004ld.h\005"
886
    "leadz\005log_0\005log_1\005log_2\005log_3\005log_4\003mov\003nop\002or\004"
887
    "or.f\004popc\001s\004sel.\002sh\004sh.f\003sha\005sha.f\002st\004st.b\004"
888
    "st.h\003sub\005sub.f\004subb\006subb.f\006trailz\003uld\005uld.b\005uld"
889
    ".h\003xor\005xor.f";
890
891
namespace {
892
  struct MatchEntry {
893
    uint8_t Mnemonic;
894
    uint16_t Opcode;
895
    uint8_t ConvertFn;
896
    uint8_t RequiredFeatures;
897
    uint8_t Classes[7];
898
5.44k
    StringRef getMnemonic() const {
899
5.44k
      return StringRef(MnemonicTable + Mnemonic + 1,
900
5.44k
                       MnemonicTable[Mnemonic]);
901
5.44k
    }
902
  };
903
904
  // Predicate for searching for an opcode.
905
  struct LessOpcode {
906
3.12k
    bool operator()(const MatchEntry &LHS, StringRef RHS) {
907
3.12k
      return LHS.getMnemonic() < RHS;
908
3.12k
    }
909
2.32k
    bool operator()(StringRef LHS, const MatchEntry &RHS) {
910
2.32k
      return LHS < RHS.getMnemonic();
911
2.32k
    }
912
0
    bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
913
0
      return LHS.getMnemonic() < RHS.getMnemonic();
914
0
    }
915
  };
916
} // end anonymous namespace.
917
918
static const MatchEntry MatchTable0[] = {
919
  { 0 /* #ADJCALLSTACKDOWN */, Lanai::ADJCALLSTACKDOWN, Convert__Imm1_0__Imm1_1, 0, { MCK_Imm, MCK_Imm }, },
920
  { 18 /* #ADJCALLSTACKUP */, Lanai::ADJCALLSTACKUP, Convert__Imm1_0__Imm1_1, 0, { MCK_Imm, MCK_Imm }, },
921
  { 34 /* #ADJDYNALLOC */, Lanai::ADJDYNALLOC, Convert__Reg1_0__Reg1_1, 0, { MCK_GPR, MCK_GPR }, },
922
  { 47 /* add */, Lanai::ADD_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
923
  { 47 /* add */, Lanai::ADD_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
924
  { 47 /* add */, Lanai::ADD_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
925
  { 51 /* add.f */, Lanai::ADD_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
926
  { 51 /* add.f */, Lanai::ADD_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
927
  { 51 /* add.f */, Lanai::ADD_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
928
  { 57 /* addc */, Lanai::ADDC_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
929
  { 57 /* addc */, Lanai::ADDC_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
930
  { 57 /* addc */, Lanai::ADDC_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
931
  { 62 /* addc.f */, Lanai::ADDC_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
932
  { 62 /* addc.f */, Lanai::ADDC_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
933
  { 62 /* addc.f */, Lanai::ADDC_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
934
  { 69 /* and */, Lanai::AND_I_HI, Convert__Reg1_2__Reg1_0__HiImm16And1_1, 0, { MCK_GPR, MCK_HiImm16And, MCK_GPR }, },
935
  { 69 /* and */, Lanai::AND_I_LO, Convert__Reg1_2__Reg1_0__LoImm16And1_1, 0, { MCK_GPR, MCK_LoImm16And, MCK_GPR }, },
936
  { 69 /* and */, Lanai::AND_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
937
  { 73 /* and.f */, Lanai::AND_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm16And1_1, 0, { MCK_GPR, MCK_HiImm16And, MCK_GPR }, },
938
  { 73 /* and.f */, Lanai::AND_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm16And1_1, 0, { MCK_GPR, MCK_LoImm16And, MCK_GPR }, },
939
  { 73 /* and.f */, Lanai::AND_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
940
  { 79 /* b */, Lanai::BRIND_CC, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GPR }, },
941
  { 79 /* b */, Lanai::BRCC, Convert__BrTarget1_1__Imm1_0, 0, { MCK_Imm, MCK_BrTarget }, },
942
  { 79 /* b */, Lanai::BRR, Convert__Imm1_2__Imm1_0, 0, { MCK_Imm, MCK__DOT_r, MCK_Imm }, },
943
  { 79 /* b */, Lanai::BRIND_CCA, Convert__Reg1_1__Reg1_3__Imm1_0, 0, { MCK_Imm, MCK_GPR, MCK_add, MCK_GPR }, },
944
  { 81 /* bt */, Lanai::JR, Convert__Reg1_0, 0, { MCK_GPR }, },
945
  { 81 /* bt */, Lanai::BT, Convert__BrTarget1_0, 0, { MCK_BrTarget }, },
946
  { 84 /* ld */, Lanai::LDADDR, Convert__Reg1_1__MemImm1_0, 0, { MCK_MemImm, MCK_GPR }, },
947
  { 84 /* ld */, Lanai::LDW_RI, Convert__Reg1_1__MemRegImm3_0, 0, { MCK_MemRegImm, MCK_GPR }, },
948
  { 84 /* ld */, Lanai::LDW_RR, Convert__Reg1_1__MemRegReg3_0, 0, { MCK_MemRegReg, MCK_GPR }, },
949
  { 84 /* ld */, Lanai::RET, Convert_NoOperands, 0, { MCK__MINUS_4, MCK__91_, MCK__PCT_fp, MCK__93_, MCK__PCT_pc, MCK__EXCLAIM_, MCK_return }, },
950
  { 87 /* ld.b */, Lanai::LDBs_RR, Convert__Reg1_1__MemRegReg3_0, 0, { MCK_MemRegReg, MCK_GPR }, },
951
  { 87 /* ld.b */, Lanai::LDBs_RI, Convert__Reg1_1__MemSpls3_0, 0, { MCK_MemSpls, MCK_GPR }, },
952
  { 92 /* ld.h */, Lanai::LDHs_RR, Convert__Reg1_1__MemRegReg3_0, 0, { MCK_MemRegReg, MCK_GPR }, },
953
  { 92 /* ld.h */, Lanai::LDHs_RI, Convert__Reg1_1__MemSpls3_0, 0, { MCK_MemSpls, MCK_GPR }, },
954
  { 97 /* leadz */, Lanai::LEADZ, Convert__Reg1_1__Reg1_0, 0, { MCK_GPR, MCK_GPR }, },
955
  { 103 /* log_0 */, Lanai::LOG0, Convert_NoOperands, 0, {  }, },
956
  { 109 /* log_1 */, Lanai::LOG1, Convert_NoOperands, 0, {  }, },
957
  { 115 /* log_2 */, Lanai::LOG2, Convert_NoOperands, 0, {  }, },
958
  { 121 /* log_3 */, Lanai::LOG3, Convert_NoOperands, 0, {  }, },
959
  { 127 /* log_4 */, Lanai::LOG4, Convert_NoOperands, 0, {  }, },
960
  { 133 /* mov */, Lanai::ADD_R, Convert__Reg1_1__Reg1_0__regR0__imm_95_0, 0, { MCK_GPR, MCK_GPR }, },
961
  { 133 /* mov */, Lanai::AND_I_HI, Convert__Reg1_1__regR1__HiImm16And1_0, 0, { MCK_HiImm16And, MCK_GPR }, },
962
  { 133 /* mov */, Lanai::ADD_I_HI, Convert__Reg1_1__regR0__HiImm161_0, 0, { MCK_HiImm16, MCK_GPR }, },
963
  { 133 /* mov */, Lanai::AND_I_LO, Convert__Reg1_1__regR1__LoImm16And1_0, 0, { MCK_LoImm16And, MCK_GPR }, },
964
  { 133 /* mov */, Lanai::ADD_I_LO, Convert__Reg1_1__regR0__LoImm161_0, 0, { MCK_LoImm16, MCK_GPR }, },
965
  { 133 /* mov */, Lanai::SLI, Convert__Reg1_1__LoImm211_0, 0, { MCK_LoImm21, MCK_GPR }, },
966
  { 137 /* nop */, Lanai::NOP, Convert_NoOperands, 0, {  }, },
967
  { 141 /* or */, Lanai::OR_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
968
  { 141 /* or */, Lanai::OR_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
969
  { 141 /* or */, Lanai::OR_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
970
  { 144 /* or.f */, Lanai::OR_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
971
  { 144 /* or.f */, Lanai::OR_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
972
  { 144 /* or.f */, Lanai::OR_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
973
  { 149 /* popc */, Lanai::POPC, Convert__Reg1_1__Reg1_0, 0, { MCK_GPR, MCK_GPR }, },
974
  { 154 /* s */, Lanai::SCC, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GPR }, },
975
  { 156 /* sel. */, Lanai::SELECT, Convert__Reg1_3__Reg1_1__Reg1_2__Imm1_0, 0, { MCK_Imm, MCK_GPR, MCK_GPR, MCK_GPR }, },
976
  { 161 /* sh */, Lanai::SL_I, Convert__Reg1_2__Reg1_0__ImmShift1_1, 0, { MCK_GPR, MCK_ImmShift, MCK_GPR }, },
977
  { 161 /* sh */, Lanai::SHL_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
978
  { 164 /* sh.f */, Lanai::SL_F_I, Convert__Reg1_2__Reg1_0__ImmShift1_1, 0, { MCK_GPR, MCK_ImmShift, MCK_GPR }, },
979
  { 164 /* sh.f */, Lanai::SHL_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
980
  { 169 /* sha */, Lanai::SA_I, Convert__Reg1_2__Reg1_0__ImmShift1_1, 0, { MCK_GPR, MCK_ImmShift, MCK_GPR }, },
981
  { 169 /* sha */, Lanai::SRA_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
982
  { 173 /* sha.f */, Lanai::SA_F_I, Convert__Reg1_2__Reg1_0__ImmShift1_1, 0, { MCK_GPR, MCK_ImmShift, MCK_GPR }, },
983
  { 173 /* sha.f */, Lanai::SRA_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
984
  { 179 /* st */, Lanai::STADDR, Convert__Reg1_0__MemImm1_1, 0, { MCK_GPR, MCK_MemImm }, },
985
  { 179 /* st */, Lanai::SW_RI, Convert__Reg1_0__MemRegImm3_1, 0, { MCK_GPR, MCK_MemRegImm }, },
986
  { 179 /* st */, Lanai::SW_RR, Convert__Reg1_0__MemRegReg3_1, 0, { MCK_GPR, MCK_MemRegReg }, },
987
  { 182 /* st.b */, Lanai::STB_RR, Convert__Reg1_0__MemRegReg3_1, 0, { MCK_GPR, MCK_MemRegReg }, },
988
  { 182 /* st.b */, Lanai::STB_RI, Convert__Reg1_0__MemSpls3_1, 0, { MCK_GPR, MCK_MemSpls }, },
989
  { 187 /* st.h */, Lanai::STH_RR, Convert__Reg1_0__MemRegReg3_1, 0, { MCK_GPR, MCK_MemRegReg }, },
990
  { 187 /* st.h */, Lanai::STH_RI, Convert__Reg1_0__MemSpls3_1, 0, { MCK_GPR, MCK_MemSpls }, },
991
  { 192 /* sub */, Lanai::SUB_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
992
  { 192 /* sub */, Lanai::SUB_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
993
  { 192 /* sub */, Lanai::SUB_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
994
  { 196 /* sub.f */, Lanai::SUB_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
995
  { 196 /* sub.f */, Lanai::SUB_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
996
  { 196 /* sub.f */, Lanai::SUB_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
997
  { 202 /* subb */, Lanai::SUBB_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
998
  { 202 /* subb */, Lanai::SUBB_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
999
  { 202 /* subb */, Lanai::SUBB_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
1000
  { 207 /* subb.f */, Lanai::SUBB_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
1001
  { 207 /* subb.f */, Lanai::SUBB_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
1002
  { 207 /* subb.f */, Lanai::SUBB_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
1003
  { 214 /* trailz */, Lanai::TRAILZ, Convert__Reg1_1__Reg1_0, 0, { MCK_GPR, MCK_GPR }, },
1004
  { 221 /* uld */, Lanai::LDW_RI, Convert__Reg1_1__MemRegImm3_0, 0, { MCK_MemRegImm, MCK_GPR }, },
1005
  { 221 /* uld */, Lanai::LDWz_RR, Convert__Reg1_1__MemRegReg3_0, 0, { MCK_MemRegReg, MCK_GPR }, },
1006
  { 225 /* uld.b */, Lanai::LDBz_RR, Convert__Reg1_1__MemRegReg3_0, 0, { MCK_MemRegReg, MCK_GPR }, },
1007
  { 225 /* uld.b */, Lanai::LDBz_RI, Convert__Reg1_1__MemSpls3_0, 0, { MCK_MemSpls, MCK_GPR }, },
1008
  { 231 /* uld.h */, Lanai::LDHz_RR, Convert__Reg1_1__MemRegReg3_0, 0, { MCK_MemRegReg, MCK_GPR }, },
1009
  { 231 /* uld.h */, Lanai::LDHz_RI, Convert__Reg1_1__MemSpls3_0, 0, { MCK_MemSpls, MCK_GPR }, },
1010
  { 237 /* xor */, Lanai::XOR_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
1011
  { 237 /* xor */, Lanai::XOR_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
1012
  { 237 /* xor */, Lanai::XOR_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
1013
  { 241 /* xor.f */, Lanai::XOR_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
1014
  { 241 /* xor.f */, Lanai::XOR_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
1015
  { 241 /* xor.f */, Lanai::XOR_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
1016
};
1017
1018
#include "llvm/Support/Debug.h"
1019
#include "llvm/Support/Format.h"
1020
1021
unsigned LanaiAsmParser::
1022
MatchInstructionImpl(const OperandVector &Operands,
1023
                     MCInst &Inst,
1024
                     uint64_t &ErrorInfo,
1025
481
                     bool matchingInlineAsm, unsigned VariantID) {
1026
481
  // Eliminate obvious mismatches.
1027
481
  if (Operands.size() > 8) {
1028
0
    ErrorInfo = 8;
1029
0
    return Match_InvalidOperand;
1030
0
  }
1031
481
1032
481
  // Get the current feature set.
1033
481
  uint64_t AvailableFeatures = getAvailableFeatures();
1034
481
1035
481
  // Get the instruction mnemonic, which is the first token.
1036
481
  StringRef Mnemonic = ((LanaiOperand&)*Operands[0]).getToken();
1037
481
1038
481
  // Some state to try to produce better error messages.
1039
481
  bool HadMatchOtherThanFeatures = false;
1040
481
  bool HadMatchOtherThanPredicate = false;
1041
481
  unsigned RetCode = Match_InvalidOperand;
1042
481
  uint64_t MissingFeatures = ~0ULL;
1043
481
  // Set ErrorInfo to the operand that mismatches if it is
1044
481
  // wrong for all instances of the instruction.
1045
481
  ErrorInfo = ~0ULL;
1046
481
  // Find the appropriate table for this asm variant.
1047
481
  const MatchEntry *Start, *End;
1048
481
  switch (VariantID) {
1049
481
  
default: 0
llvm_unreachable0
("invalid variant!");
1050
481
  case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
1051
481
  }
1052
481
  // Search the table.
1053
481
  auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
1054
481
1055
481
  DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
1056
481
  std::distance(MnemonicRange.first, MnemonicRange.second) << 
1057
481
  " encodings with mnemonic '" << Mnemonic << "'\n");
1058
481
1059
481
  // Return a more specific error code if no mnemonics match.
1060
481
  if (MnemonicRange.first == MnemonicRange.second)
1061
0
    return Match_MnemonicFail;
1062
481
1063
481
  for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
1064
924
       it != ie; 
++it443
) {
1065
924
    bool HasRequiredFeatures =
1066
924
      (AvailableFeatures & it->RequiredFeatures) == it->RequiredFeatures;
1067
924
    DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
1068
924
                                          << MII.getName(it->Opcode) << "\n");
1069
924
    // equal_range guarantees that instruction mnemonic matches.
1070
924
    assert(Mnemonic == it->getMnemonic());
1071
924
    bool OperandsValid = true;
1072
2.25k
    for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 7; 
++FormalIdx1.33k
) {
1073
2.25k
      auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
1074
2.25k
      DEBUG_WITH_TYPE("asm-matcher",
1075
2.25k
                      dbgs() << "  Matching formal operand class " << getMatchClassName(Formal)
1076
2.25k
                             << " against actual operand at index " << ActualIdx);
1077
2.25k
      if (ActualIdx < Operands.size())
1078
2.25k
        
DEBUG_WITH_TYPE1.77k
("asm-matcher", dbgs() << " (";
1079
2.25k
                        Operands[ActualIdx]->print(dbgs()); dbgs() << "): ");
1080
2.25k
      else
1081
2.25k
        
DEBUG_WITH_TYPE481
("asm-matcher", dbgs() << ": ");
1082
2.25k
      if (ActualIdx >= Operands.size()) {
1083
481
        DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range ");
1084
481
        OperandsValid = (Formal == InvalidMatchClass) || 
isSubclass(Formal, OptionalMatchClass)0
;
1085
481
        if (!OperandsValid) 
ErrorInfo = ActualIdx0
;
1086
481
        break;
1087
481
      }
1088
1.77k
      MCParsedAsmOperand &Actual = *Operands[ActualIdx];
1089
1.77k
      unsigned Diag = validateOperandClass(Actual, Formal);
1090
1.77k
      if (Diag == Match_Success) {
1091
1.33k
        DEBUG_WITH_TYPE("asm-matcher",
1092
1.33k
                        dbgs() << "match success using generic matcher\n");
1093
1.33k
        ++ActualIdx;
1094
1.33k
        continue;
1095
1.33k
      }
1096
443
      // If the generic handler indicates an invalid operand
1097
443
      // failure, check for a special case.
1098
443
      if (Diag != Match_Success) {
1099
443
        unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
1100
443
        if (TargetDiag == Match_Success) {
1101
0
          DEBUG_WITH_TYPE("asm-matcher",
1102
0
                          dbgs() << "match success using target matcher\n");
1103
0
          ++ActualIdx;
1104
0
          continue;
1105
0
        }
1106
443
        // If the target matcher returned a specific error code use
1107
443
        // that, else use the one from the generic matcher.
1108
443
        if (TargetDiag != Match_InvalidOperand && 
HasRequiredFeatures0
)
1109
0
          Diag = TargetDiag;
1110
443
      }
1111
443
      // If current formal operand wasn't matched and it is optional
1112
443
      // then try to match next formal operand
1113
443
      if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
1114
0
        DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
1115
0
        continue;
1116
0
      }
1117
443
      // If this operand is broken for all of the instances of this
1118
443
      // mnemonic, keep track of it so we can report loc info.
1119
443
      // If we already had a match that only failed due to a
1120
443
      // target predicate, that diagnostic is preferred.
1121
443
      if (!HadMatchOtherThanPredicate &&
1122
443
          (it == MnemonicRange.first || 
ErrorInfo <= ActualIdx119
)) {
1123
443
        if (HasRequiredFeatures && (ErrorInfo != ActualIdx || 
Diag != Match_InvalidOperand99
))
1124
344
          RetCode = Diag;
1125
443
        ErrorInfo = ActualIdx;
1126
443
      }
1127
443
      // Otherwise, just reject this instance of the mnemonic.
1128
443
      OperandsValid = false;
1129
443
      break;
1130
443
    }
1131
924
1132
924
    if (!OperandsValid) {
1133
443
      DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
1134
443
                                               "operand mismatches, ignoring "
1135
443
                                               "this opcode\n");
1136
443
      continue;
1137
443
    }
1138
481
    if (!HasRequiredFeatures) {
1139
0
      HadMatchOtherThanFeatures = true;
1140
0
      uint64_t NewMissingFeatures = it->RequiredFeatures & ~AvailableFeatures;
1141
0
      DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features: "
1142
0
                                            << format_hex(NewMissingFeatures, 18)
1143
0
                                            << "\n");
1144
0
      if (countPopulation(NewMissingFeatures) <=
1145
0
          countPopulation(MissingFeatures))
1146
0
        MissingFeatures = NewMissingFeatures;
1147
0
      continue;
1148
0
    }
1149
481
1150
481
    Inst.clear();
1151
481
1152
481
    Inst.setOpcode(it->Opcode);
1153
481
    // We have a potential match but have not rendered the operands.
1154
481
    // Check the target predicate to handle any context sensitive
1155
481
    // constraints.
1156
481
    // For example, Ties that are referenced multiple times must be
1157
481
    // checked here to ensure the input is the same for each match
1158
481
    // constraints. If we leave it any later the ties will have been
1159
481
    // canonicalized
1160
481
    unsigned MatchResult;
1161
481
    if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
1162
0
      Inst.clear();
1163
0
      DEBUG_WITH_TYPE(
1164
0
          "asm-matcher",
1165
0
          dbgs() << "Early target match predicate failed with diag code "
1166
0
                 << MatchResult << "\n");
1167
0
      RetCode = MatchResult;
1168
0
      HadMatchOtherThanPredicate = true;
1169
0
      continue;
1170
0
    }
1171
481
1172
481
    if (matchingInlineAsm) {
1173
0
      convertToMapAndConstraints(it->ConvertFn, Operands);
1174
0
      if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo))
1175
0
        return Match_InvalidTiedOperand;
1176
0
1177
0
      return Match_Success;
1178
0
    }
1179
481
1180
481
    // We have selected a definite instruction, convert the parsed
1181
481
    // operands into the appropriate MCInst.
1182
481
    convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);
1183
481
1184
481
    // We have a potential match. Check the target predicate to
1185
481
    // handle any context sensitive constraints.
1186
481
    if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
1187
0
      DEBUG_WITH_TYPE("asm-matcher",
1188
0
                      dbgs() << "Target match predicate failed with diag code "
1189
0
                             << MatchResult << "\n");
1190
0
      Inst.clear();
1191
0
      RetCode = MatchResult;
1192
0
      HadMatchOtherThanPredicate = true;
1193
0
      continue;
1194
0
    }
1195
481
1196
481
    if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo))
1197
0
      return Match_InvalidTiedOperand;
1198
481
1199
481
    DEBUG_WITH_TYPE(
1200
481
        "asm-matcher",
1201
481
        dbgs() << "Opcode result: complete match, selecting this opcode\n");
1202
481
    return Match_Success;
1203
481
  }
1204
481
1205
481
  // Okay, we had no match.  Try to return a useful error code.
1206
481
  
if (0
HadMatchOtherThanPredicate0
||
!HadMatchOtherThanFeatures0
)
1207
0
    return RetCode;
1208
0
1209
0
  // Missing feature matches return which features were missing
1210
0
  ErrorInfo = MissingFeatures;
1211
0
  return Match_MissingFeature;
1212
0
}
1213
1214
namespace {
1215
  struct OperandMatchEntry {
1216
    uint8_t RequiredFeatures;
1217
    uint8_t Mnemonic;
1218
    uint8_t Class;
1219
    uint8_t OperandMask;
1220
1221
8.19k
    StringRef getMnemonic() const {
1222
8.19k
      return StringRef(MnemonicTable + Mnemonic + 1,
1223
8.19k
                       MnemonicTable[Mnemonic]);
1224
8.19k
    }
1225
  };
1226
1227
  // Predicate for searching for an opcode.
1228
  struct LessOpcodeOperand {
1229
4.64k
    bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
1230
4.64k
      return LHS.getMnemonic()  < RHS;
1231
4.64k
    }
1232
3.55k
    bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
1233
3.55k
      return LHS < RHS.getMnemonic();
1234
3.55k
    }
1235
0
    bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
1236
0
      return LHS.getMnemonic() < RHS.getMnemonic();
1237
0
    }
1238
  };
1239
} // end anonymous namespace.
1240
1241
static const OperandMatchEntry OperandMatchTable[20] = {
1242
  /* Operand List Mask, Mnemonic, Operand Class, Features */
1243
  { 0, 84 /* ld */, MCK_MemImm, 1 /* 0 */ },
1244
  { 0, 84 /* ld */, MCK_MemRegImm, 1 /* 0 */ },
1245
  { 0, 84 /* ld */, MCK_MemRegReg, 1 /* 0 */ },
1246
  { 0, 87 /* ld.b */, MCK_MemRegReg, 1 /* 0 */ },
1247
  { 0, 87 /* ld.b */, MCK_MemSpls, 1 /* 0 */ },
1248
  { 0, 92 /* ld.h */, MCK_MemRegReg, 1 /* 0 */ },
1249
  { 0, 92 /* ld.h */, MCK_MemSpls, 1 /* 0 */ },
1250
  { 0, 179 /* st */, MCK_MemImm, 2 /* 1 */ },
1251
  { 0, 179 /* st */, MCK_MemRegImm, 2 /* 1 */ },
1252
  { 0, 179 /* st */, MCK_MemRegReg, 2 /* 1 */ },
1253
  { 0, 182 /* st.b */, MCK_MemRegReg, 2 /* 1 */ },
1254
  { 0, 182 /* st.b */, MCK_MemSpls, 2 /* 1 */ },
1255
  { 0, 187 /* st.h */, MCK_MemRegReg, 2 /* 1 */ },
1256
  { 0, 187 /* st.h */, MCK_MemSpls, 2 /* 1 */ },
1257
  { 0, 221 /* uld */, MCK_MemRegImm, 1 /* 0 */ },
1258
  { 0, 221 /* uld */, MCK_MemRegReg, 1 /* 0 */ },
1259
  { 0, 225 /* uld.b */, MCK_MemRegReg, 1 /* 0 */ },
1260
  { 0, 225 /* uld.b */, MCK_MemSpls, 1 /* 0 */ },
1261
  { 0, 231 /* uld.h */, MCK_MemRegReg, 1 /* 0 */ },
1262
  { 0, 231 /* uld.h */, MCK_MemSpls, 1 /* 0 */ },
1263
};
1264
1265
OperandMatchResultTy LanaiAsmParser::
1266
tryCustomParseOperand(OperandVector &Operands,
1267
299
                      unsigned MCK) {
1268
299
1269
299
  switch(MCK) {
1270
299
  case MCK_MemImm:
1271
119
    return parseMemoryOperand(Operands);
1272
299
  case MCK_MemRegImm:
1273
18
    return parseMemoryOperand(Operands);
1274
299
  case MCK_MemRegReg:
1275
162
    return parseMemoryOperand(Operands);
1276
299
  case MCK_MemSpls:
1277
0
    return parseMemoryOperand(Operands);
1278
299
  default:
1279
0
    return MatchOperand_NoMatch;
1280
0
  }
1281
0
  return MatchOperand_NoMatch;
1282
0
}
1283
1284
OperandMatchResultTy LanaiAsmParser::
1285
MatchOperandParserImpl(OperandVector &Operands,
1286
                       StringRef Mnemonic,
1287
984
                       bool ParseForAllFeatures) {
1288
984
  // Get the current feature set.
1289
984
  uint64_t AvailableFeatures = getAvailableFeatures();
1290
984
1291
984
  // Get the next operand index.
1292
984
  unsigned NextOpNum = Operands.size() - 1;
1293
984
  // Search the table.
1294
984
  auto MnemonicRange =
1295
984
    std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
1296
984
                     Mnemonic, LessOpcodeOperand());
1297
984
1298
984
  if (MnemonicRange.first == MnemonicRange.second)
1299
385
    return MatchOperand_NoMatch;
1300
599
1301
599
  for (const OperandMatchEntry *it = MnemonicRange.first,
1302
1.31k
       *ie = MnemonicRange.second; it != ie; 
++it720
) {
1303
1.01k
    // equal_range guarantees that instruction mnemonic matches.
1304
1.01k
    assert(Mnemonic == it->getMnemonic());
1305
1.01k
1306
1.01k
    // check if the available features match
1307
1.01k
    if (!ParseForAllFeatures && (AvailableFeatures & it->RequiredFeatures) != it->RequiredFeatures)
1308
0
        continue;
1309
1.01k
1310
1.01k
    // check if the operand in question has a custom parser.
1311
1.01k
    if (!(it->OperandMask & (1 << NextOpNum)))
1312
720
      continue;
1313
299
1314
299
    // call custom parse method to handle the operand
1315
299
    OperandMatchResultTy Result = tryCustomParseOperand(Operands, it->Class);
1316
299
    if (Result != MatchOperand_NoMatch)
1317
299
      return Result;
1318
299
  }
1319
599
1320
599
  // Okay, we had no match.
1321
599
  
return MatchOperand_NoMatch300
;
1322
599
}
1323
1324
#endif // GET_MATCHER_IMPLEMENTATION
1325
1326
1327
#ifdef GET_MNEMONIC_SPELL_CHECKER
1328
#undef GET_MNEMONIC_SPELL_CHECKER
1329
1330
static std::string LanaiMnemonicSpellCheck(StringRef S, uint64_t FBS, unsigned VariantID) {
1331
  const unsigned MaxEditDist = 2;
1332
  std::vector<StringRef> Candidates;
1333
  StringRef Prev = "";
1334
1335
  // Find the appropriate table for this asm variant.
1336
  const MatchEntry *Start, *End;
1337
  switch (VariantID) {
1338
  default: llvm_unreachable("invalid variant!");
1339
  case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
1340
  }
1341
1342
  for (auto I = Start; I < End; I++) {
1343
    // Ignore unsupported instructions.
1344
    if ((FBS & I->RequiredFeatures) != I->RequiredFeatures)
1345
      continue;
1346
1347
    StringRef T = I->getMnemonic();
1348
    // Avoid recomputing the edit distance for the same string.
1349
    if (T.equals(Prev))
1350
      continue;
1351
1352
    Prev = T;
1353
    unsigned Dist = S.edit_distance(T, false, MaxEditDist);
1354
    if (Dist <= MaxEditDist)
1355
      Candidates.push_back(T);
1356
  }
1357
1358
  if (Candidates.empty())
1359
    return "";
1360
1361
  std::string Res = ", did you mean: ";
1362
  unsigned i = 0;
1363
  for( ; i < Candidates.size() - 1; i++)
1364
    Res += Candidates[i].str() + ", ";
1365
  return Res + Candidates[i].str() + "?";
1366
}
1367
1368
#endif // GET_MNEMONIC_SPELL_CHECKER
1369