Coverage Report

Created: 2018-07-12 09:57

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Lanai/LanaiGenCallingConv.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Calling Convention Implementation Fragment                                 *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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static bool CC_Lanai32(unsigned ValNo, MVT ValVT,
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                       MVT LocVT, CCValAssign::LocInfo LocInfo,
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                       ISD::ArgFlagsTy ArgFlags, CCState &State);
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static bool CC_Lanai32_Fast(unsigned ValNo, MVT ValVT,
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                            MVT LocVT, CCValAssign::LocInfo LocInfo,
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                            ISD::ArgFlagsTy ArgFlags, CCState &State);
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static bool RetCC_Lanai32(unsigned ValNo, MVT ValVT,
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                          MVT LocVT, CCValAssign::LocInfo LocInfo,
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                          ISD::ArgFlagsTy ArgFlags, CCState &State);
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static bool CC_Lanai32(unsigned ValNo, MVT ValVT,
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                       MVT LocVT, CCValAssign::LocInfo LocInfo,
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                       ISD::ArgFlagsTy ArgFlags, CCState &State) {
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  if (LocVT == MVT::i8 ||
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      LocVT == MVT::i16) {
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    LocVT = MVT::i32;
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    if (ArgFlags.isSExt())
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        LocInfo = CCValAssign::SExt;
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    else if (ArgFlags.isZExt())
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        LocInfo = CCValAssign::ZExt;
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    else
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        LocInfo = CCValAssign::AExt;
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  }
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  if (!State.isVarArg()) {
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    if (ArgFlags.isInReg()) {
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      if (LocVT == MVT::i32) {
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        static const MCPhysReg RegList1[] = {
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          Lanai::R6, Lanai::R7, Lanai::R18, Lanai::R19
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        };
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        if (unsigned Reg = State.AllocateReg(RegList1)) {
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          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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          return false;
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        }
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      }
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    }
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  }
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  unsigned Offset2 = State.AllocateStack(4, 4);
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  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
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  return false;
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return true0
; // CC didn't match.
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}
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static bool CC_Lanai32_Fast(unsigned ValNo, MVT ValVT,
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                            MVT LocVT, CCValAssign::LocInfo LocInfo,
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                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
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  if (LocVT == MVT::i8 ||
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      LocVT == MVT::i16) {
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    LocVT = MVT::i32;
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    if (ArgFlags.isSExt())
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        LocInfo = CCValAssign::SExt;
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    else if (ArgFlags.isZExt())
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        LocInfo = CCValAssign::ZExt;
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    else
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        LocInfo = CCValAssign::AExt;
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  }
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  if (!State.isVarArg()) {
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    if (LocVT == MVT::i32) {
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      static const MCPhysReg RegList1[] = {
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        Lanai::R6, Lanai::R7, Lanai::R18, Lanai::R19
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      };
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      if (unsigned Reg = State.AllocateReg(RegList1)) {
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        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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        return false;
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      }
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    }
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  }
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  unsigned Offset2 = State.AllocateStack(4, 4);
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  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
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  return false;
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  return true;  // CC didn't match.
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}
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static bool RetCC_Lanai32(unsigned ValNo, MVT ValVT,
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                          MVT LocVT, CCValAssign::LocInfo LocInfo,
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                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
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  if (LocVT == MVT::i32) {
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    static const MCPhysReg RegList1[] = {
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      Lanai::RV, Lanai::R9
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    };
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    if (unsigned Reg = State.AllocateReg(RegList1)) {
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      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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      return false;
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    }
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  }
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  return true;  // CC didn't match.
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}