Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Lanai/LanaiGenInstrInfo.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Target Instruction Enum Values and Descriptors                             *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_INSTRINFO_ENUM
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#undef GET_INSTRINFO_ENUM
11
namespace llvm {
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13
namespace Lanai {
14
  enum {
15
    PHI = 0,
16
    INLINEASM = 1,
17
    INLINEASM_BR  = 2,
18
    CFI_INSTRUCTION = 3,
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    EH_LABEL  = 4,
20
    GC_LABEL  = 5,
21
    ANNOTATION_LABEL  = 6,
22
    KILL  = 7,
23
    EXTRACT_SUBREG  = 8,
24
    INSERT_SUBREG = 9,
25
    IMPLICIT_DEF  = 10,
26
    SUBREG_TO_REG = 11,
27
    COPY_TO_REGCLASS  = 12,
28
    DBG_VALUE = 13,
29
    DBG_LABEL = 14,
30
    REG_SEQUENCE  = 15,
31
    COPY  = 16,
32
    BUNDLE  = 17,
33
    LIFETIME_START  = 18,
34
    LIFETIME_END  = 19,
35
    STACKMAP  = 20,
36
    FENTRY_CALL = 21,
37
    PATCHPOINT  = 22,
38
    LOAD_STACK_GUARD  = 23,
39
    STATEPOINT  = 24,
40
    LOCAL_ESCAPE  = 25,
41
    FAULTING_OP = 26,
42
    PATCHABLE_OP  = 27,
43
    PATCHABLE_FUNCTION_ENTER  = 28,
44
    PATCHABLE_RET = 29,
45
    PATCHABLE_FUNCTION_EXIT = 30,
46
    PATCHABLE_TAIL_CALL = 31,
47
    PATCHABLE_EVENT_CALL  = 32,
48
    PATCHABLE_TYPED_EVENT_CALL  = 33,
49
    ICALL_BRANCH_FUNNEL = 34,
50
    G_ADD = 35,
51
    G_SUB = 36,
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    G_MUL = 37,
53
    G_SDIV  = 38,
54
    G_UDIV  = 39,
55
    G_SREM  = 40,
56
    G_UREM  = 41,
57
    G_AND = 42,
58
    G_OR  = 43,
59
    G_XOR = 44,
60
    G_IMPLICIT_DEF  = 45,
61
    G_PHI = 46,
62
    G_FRAME_INDEX = 47,
63
    G_GLOBAL_VALUE  = 48,
64
    G_EXTRACT = 49,
65
    G_UNMERGE_VALUES  = 50,
66
    G_INSERT  = 51,
67
    G_MERGE_VALUES  = 52,
68
    G_BUILD_VECTOR  = 53,
69
    G_BUILD_VECTOR_TRUNC  = 54,
70
    G_CONCAT_VECTORS  = 55,
71
    G_PTRTOINT  = 56,
72
    G_INTTOPTR  = 57,
73
    G_BITCAST = 58,
74
    G_INTRINSIC_TRUNC = 59,
75
    G_INTRINSIC_ROUND = 60,
76
    G_LOAD  = 61,
77
    G_SEXTLOAD  = 62,
78
    G_ZEXTLOAD  = 63,
79
    G_STORE = 64,
80
    G_ATOMIC_CMPXCHG_WITH_SUCCESS = 65,
81
    G_ATOMIC_CMPXCHG  = 66,
82
    G_ATOMICRMW_XCHG  = 67,
83
    G_ATOMICRMW_ADD = 68,
84
    G_ATOMICRMW_SUB = 69,
85
    G_ATOMICRMW_AND = 70,
86
    G_ATOMICRMW_NAND  = 71,
87
    G_ATOMICRMW_OR  = 72,
88
    G_ATOMICRMW_XOR = 73,
89
    G_ATOMICRMW_MAX = 74,
90
    G_ATOMICRMW_MIN = 75,
91
    G_ATOMICRMW_UMAX  = 76,
92
    G_ATOMICRMW_UMIN  = 77,
93
    G_FENCE = 78,
94
    G_BRCOND  = 79,
95
    G_BRINDIRECT  = 80,
96
    G_INTRINSIC = 81,
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    G_INTRINSIC_W_SIDE_EFFECTS  = 82,
98
    G_ANYEXT  = 83,
99
    G_TRUNC = 84,
100
    G_CONSTANT  = 85,
101
    G_FCONSTANT = 86,
102
    G_VASTART = 87,
103
    G_VAARG = 88,
104
    G_SEXT  = 89,
105
    G_ZEXT  = 90,
106
    G_SHL = 91,
107
    G_LSHR  = 92,
108
    G_ASHR  = 93,
109
    G_ICMP  = 94,
110
    G_FCMP  = 95,
111
    G_SELECT  = 96,
112
    G_UADDO = 97,
113
    G_UADDE = 98,
114
    G_USUBO = 99,
115
    G_USUBE = 100,
116
    G_SADDO = 101,
117
    G_SADDE = 102,
118
    G_SSUBO = 103,
119
    G_SSUBE = 104,
120
    G_UMULO = 105,
121
    G_SMULO = 106,
122
    G_UMULH = 107,
123
    G_SMULH = 108,
124
    G_FADD  = 109,
125
    G_FSUB  = 110,
126
    G_FMUL  = 111,
127
    G_FMA = 112,
128
    G_FDIV  = 113,
129
    G_FREM  = 114,
130
    G_FPOW  = 115,
131
    G_FEXP  = 116,
132
    G_FEXP2 = 117,
133
    G_FLOG  = 118,
134
    G_FLOG2 = 119,
135
    G_FLOG10  = 120,
136
    G_FNEG  = 121,
137
    G_FPEXT = 122,
138
    G_FPTRUNC = 123,
139
    G_FPTOSI  = 124,
140
    G_FPTOUI  = 125,
141
    G_SITOFP  = 126,
142
    G_UITOFP  = 127,
143
    G_FABS  = 128,
144
    G_FCOPYSIGN = 129,
145
    G_FCANONICALIZE = 130,
146
    G_FMINNUM = 131,
147
    G_FMAXNUM = 132,
148
    G_FMINNUM_IEEE  = 133,
149
    G_FMAXNUM_IEEE  = 134,
150
    G_FMINIMUM  = 135,
151
    G_FMAXIMUM  = 136,
152
    G_GEP = 137,
153
    G_PTR_MASK  = 138,
154
    G_SMIN  = 139,
155
    G_SMAX  = 140,
156
    G_UMIN  = 141,
157
    G_UMAX  = 142,
158
    G_BR  = 143,
159
    G_BRJT  = 144,
160
    G_INSERT_VECTOR_ELT = 145,
161
    G_EXTRACT_VECTOR_ELT  = 146,
162
    G_SHUFFLE_VECTOR  = 147,
163
    G_CTTZ  = 148,
164
    G_CTTZ_ZERO_UNDEF = 149,
165
    G_CTLZ  = 150,
166
    G_CTLZ_ZERO_UNDEF = 151,
167
    G_CTPOP = 152,
168
    G_BSWAP = 153,
169
    G_FCEIL = 154,
170
    G_FCOS  = 155,
171
    G_FSIN  = 156,
172
    G_FSQRT = 157,
173
    G_FFLOOR  = 158,
174
    G_FRINT = 159,
175
    G_FNEARBYINT  = 160,
176
    G_ADDRSPACE_CAST  = 161,
177
    G_BLOCK_ADDR  = 162,
178
    G_JUMP_TABLE  = 163,
179
    ADJCALLSTACKDOWN  = 164,
180
    ADJCALLSTACKUP  = 165,
181
    ADJDYNALLOC = 166,
182
    CALL  = 167,
183
    CALLR = 168,
184
    ADDC_F_I_HI = 169,
185
    ADDC_F_I_LO = 170,
186
    ADDC_F_R  = 171,
187
    ADDC_I_HI = 172,
188
    ADDC_I_LO = 173,
189
    ADDC_R  = 174,
190
    ADD_F_I_HI  = 175,
191
    ADD_F_I_LO  = 176,
192
    ADD_F_R = 177,
193
    ADD_I_HI  = 178,
194
    ADD_I_LO  = 179,
195
    ADD_R = 180,
196
    AND_F_I_HI  = 181,
197
    AND_F_I_LO  = 182,
198
    AND_F_R = 183,
199
    AND_I_HI  = 184,
200
    AND_I_LO  = 185,
201
    AND_R = 186,
202
    BRCC  = 187,
203
    BRIND_CC  = 188,
204
    BRIND_CCA = 189,
205
    BRR = 190,
206
    BT  = 191,
207
    JR  = 192,
208
    LDADDR  = 193,
209
    LDBs_RI = 194,
210
    LDBs_RR = 195,
211
    LDBz_RI = 196,
212
    LDBz_RR = 197,
213
    LDHs_RI = 198,
214
    LDHs_RR = 199,
215
    LDHz_RI = 200,
216
    LDHz_RR = 201,
217
    LDW_RI  = 202,
218
    LDW_RR  = 203,
219
    LDWz_RR = 204,
220
    LEADZ = 205,
221
    LOG0  = 206,
222
    LOG1  = 207,
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    LOG2  = 208,
224
    LOG3  = 209,
225
    LOG4  = 210,
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    MOVHI = 211,
227
    NOP = 212,
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    OR_F_I_HI = 213,
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    OR_F_I_LO = 214,
230
    OR_F_R  = 215,
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    OR_I_HI = 216,
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    OR_I_LO = 217,
233
    OR_R  = 218,
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    POPC  = 219,
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    RET = 220,
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    SA_F_I  = 221,
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    SA_I  = 222,
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    SCC = 223,
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    SELECT  = 224,
240
    SFSUB_F_RI_HI = 225,
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    SFSUB_F_RI_LO = 226,
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    SFSUB_F_RR  = 227,
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    SHL_F_R = 228,
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    SHL_R = 229,
245
    SLI = 230,
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    SL_F_I  = 231,
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    SL_I  = 232,
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    SRA_F_R = 233,
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    SRA_R = 234,
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    SRL_F_R = 235,
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    SRL_R = 236,
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    STADDR  = 237,
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    STB_RI  = 238,
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    STB_RR  = 239,
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    STH_RI  = 240,
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    STH_RR  = 241,
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    SUBB_F_I_HI = 242,
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    SUBB_F_I_LO = 243,
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    SUBB_F_R  = 244,
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    SUBB_I_HI = 245,
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    SUBB_I_LO = 246,
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    SUBB_R  = 247,
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    SUB_F_I_HI  = 248,
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    SUB_F_I_LO  = 249,
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    SUB_F_R = 250,
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    SUB_I_HI  = 251,
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    SUB_I_LO  = 252,
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    SUB_R = 253,
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    SW_RI = 254,
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    SW_RR = 255,
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    TRAILZ  = 256,
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    XOR_F_I_HI  = 257,
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    XOR_F_I_LO  = 258,
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    XOR_F_R = 259,
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    XOR_I_HI  = 260,
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    XOR_I_LO  = 261,
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    XOR_R = 262,
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    INSTRUCTION_LIST_END = 263
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  };
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} // end Lanai namespace
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} // end llvm namespace
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#endif // GET_INSTRINFO_ENUM
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#ifdef GET_INSTRINFO_SCHED_ENUM
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#undef GET_INSTRINFO_SCHED_ENUM
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namespace llvm {
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namespace Lanai {
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namespace Sched {
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  enum {
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    NoInstrModel  = 0,
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    IIC_ALU_WriteALU  = 1,
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    IIC_ALU = 2,
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    IIC_LD_WriteLD  = 3,
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    IIC_LDSW_WriteLDSW  = 4,
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    WriteLD = 5,
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    IIC_ST_WriteST  = 6,
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    IIC_STSW_WriteSTSW  = 7,
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    SCHED_LIST_END = 8
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  };
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} // end Sched namespace
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} // end Lanai namespace
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} // end llvm namespace
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#endif // GET_INSTRINFO_SCHED_ENUM
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#ifdef GET_INSTRINFO_MC_DESC
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#undef GET_INSTRINFO_MC_DESC
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namespace llvm {
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static const MCPhysReg ImplicitList1[] = { Lanai::SP, 0 };
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static const MCPhysReg ImplicitList2[] = { Lanai::RCA, 0 };
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static const MCPhysReg ImplicitList3[] = { Lanai::SR, 0 };
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static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
320
static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
323
static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
325
static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
326
static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
327
static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
328
static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
329
static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
330
static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
331
static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
332
static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
333
static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
334
static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
335
static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
336
static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
337
static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
338
static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
339
static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
340
static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
341
static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
342
static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
343
static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
344
static const MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
345
static const MCOperandInfo OperandInfo32[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
346
static const MCOperandInfo OperandInfo33[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
347
static const MCOperandInfo OperandInfo34[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
348
static const MCOperandInfo OperandInfo35[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
349
static const MCOperandInfo OperandInfo36[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
350
static const MCOperandInfo OperandInfo37[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
351
static const MCOperandInfo OperandInfo38[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
352
static const MCOperandInfo OperandInfo39[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
353
static const MCOperandInfo OperandInfo40[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
354
355
extern const MCInstrDesc LanaiInsts[] = {
356
  { 0,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
357
  { 1,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
358
  { 2,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2 = INLINEASM_BR
359
  { 3,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = CFI_INSTRUCTION
360
  { 4,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = EH_LABEL
361
  { 5,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = GC_LABEL
362
  { 6,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #6 = ANNOTATION_LABEL
363
  { 7,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #7 = KILL
364
  { 8,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #8 = EXTRACT_SUBREG
365
  { 9,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #9 = INSERT_SUBREG
366
  { 10, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #10 = IMPLICIT_DEF
367
  { 11, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #11 = SUBREG_TO_REG
368
  { 12, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #12 = COPY_TO_REGCLASS
369
  { 13, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #13 = DBG_VALUE
370
  { 14, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #14 = DBG_LABEL
371
  { 15, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #15 = REG_SEQUENCE
372
  { 16, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #16 = COPY
373
  { 17, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #17 = BUNDLE
374
  { 18, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #18 = LIFETIME_START
375
  { 19, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #19 = LIFETIME_END
376
  { 20, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #20 = STACKMAP
377
  { 21, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #21 = FENTRY_CALL
378
  { 22, 6,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #22 = PATCHPOINT
379
  { 23, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #23 = LOAD_STACK_GUARD
380
  { 24, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #24 = STATEPOINT
381
  { 25, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #25 = LOCAL_ESCAPE
382
  { 26, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #26 = FAULTING_OP
383
  { 27, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #27 = PATCHABLE_OP
384
  { 28, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #28 = PATCHABLE_FUNCTION_ENTER
385
  { 29, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #29 = PATCHABLE_RET
386
  { 30, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #30 = PATCHABLE_FUNCTION_EXIT
387
  { 31, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #31 = PATCHABLE_TAIL_CALL
388
  { 32, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #32 = PATCHABLE_EVENT_CALL
389
  { 33, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
390
  { 34, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #34 = ICALL_BRANCH_FUNNEL
391
  { 35, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #35 = G_ADD
392
  { 36, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #36 = G_SUB
393
  { 37, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #37 = G_MUL
394
  { 38, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #38 = G_SDIV
395
  { 39, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #39 = G_UDIV
396
  { 40, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #40 = G_SREM
397
  { 41, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_UREM
398
  { 42, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_AND
399
  { 43, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #43 = G_OR
400
  { 44, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #44 = G_XOR
401
  { 45, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #45 = G_IMPLICIT_DEF
402
  { 46, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #46 = G_PHI
403
  { 47, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #47 = G_FRAME_INDEX
404
  { 48, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #48 = G_GLOBAL_VALUE
405
  { 49, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #49 = G_EXTRACT
406
  { 50, 2,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #50 = G_UNMERGE_VALUES
407
  { 51, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #51 = G_INSERT
408
  { 52, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #52 = G_MERGE_VALUES
409
  { 53, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = G_BUILD_VECTOR
410
  { 54, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #54 = G_BUILD_VECTOR_TRUNC
411
  { 55, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #55 = G_CONCAT_VECTORS
412
  { 56, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #56 = G_PTRTOINT
413
  { 57, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #57 = G_INTTOPTR
414
  { 58, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #58 = G_BITCAST
415
  { 59, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #59 = G_INTRINSIC_TRUNC
416
  { 60, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #60 = G_INTRINSIC_ROUND
417
  { 61, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #61 = G_LOAD
418
  { 62, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #62 = G_SEXTLOAD
419
  { 63, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #63 = G_ZEXTLOAD
420
  { 64, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #64 = G_STORE
421
  { 65, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #65 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
422
  { 66, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #66 = G_ATOMIC_CMPXCHG
423
  { 67, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #67 = G_ATOMICRMW_XCHG
424
  { 68, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #68 = G_ATOMICRMW_ADD
425
  { 69, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #69 = G_ATOMICRMW_SUB
426
  { 70, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #70 = G_ATOMICRMW_AND
427
  { 71, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #71 = G_ATOMICRMW_NAND
428
  { 72, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #72 = G_ATOMICRMW_OR
429
  { 73, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #73 = G_ATOMICRMW_XOR
430
  { 74, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #74 = G_ATOMICRMW_MAX
431
  { 75, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #75 = G_ATOMICRMW_MIN
432
  { 76, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #76 = G_ATOMICRMW_UMAX
433
  { 77, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #77 = G_ATOMICRMW_UMIN
434
  { 78, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #78 = G_FENCE
435
  { 79, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #79 = G_BRCOND
436
  { 80, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #80 = G_BRINDIRECT
437
  { 81, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #81 = G_INTRINSIC
438
  { 82, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #82 = G_INTRINSIC_W_SIDE_EFFECTS
439
  { 83, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #83 = G_ANYEXT
440
  { 84, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #84 = G_TRUNC
441
  { 85, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #85 = G_CONSTANT
442
  { 86, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #86 = G_FCONSTANT
443
  { 87, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #87 = G_VASTART
444
  { 88, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #88 = G_VAARG
445
  { 89, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #89 = G_SEXT
446
  { 90, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #90 = G_ZEXT
447
  { 91, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #91 = G_SHL
448
  { 92, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #92 = G_LSHR
449
  { 93, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #93 = G_ASHR
450
  { 94, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #94 = G_ICMP
451
  { 95, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #95 = G_FCMP
452
  { 96, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #96 = G_SELECT
453
  { 97, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #97 = G_UADDO
454
  { 98, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #98 = G_UADDE
455
  { 99, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #99 = G_USUBO
456
  { 100,  5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #100 = G_USUBE
457
  { 101,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #101 = G_SADDO
458
  { 102,  5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #102 = G_SADDE
459
  { 103,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #103 = G_SSUBO
460
  { 104,  5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #104 = G_SSUBE
461
  { 105,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #105 = G_UMULO
462
  { 106,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #106 = G_SMULO
463
  { 107,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #107 = G_UMULH
464
  { 108,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #108 = G_SMULH
465
  { 109,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #109 = G_FADD
466
  { 110,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #110 = G_FSUB
467
  { 111,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #111 = G_FMUL
468
  { 112,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #112 = G_FMA
469
  { 113,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #113 = G_FDIV
470
  { 114,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #114 = G_FREM
471
  { 115,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #115 = G_FPOW
472
  { 116,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #116 = G_FEXP
473
  { 117,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #117 = G_FEXP2
474
  { 118,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #118 = G_FLOG
475
  { 119,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #119 = G_FLOG2
476
  { 120,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #120 = G_FLOG10
477
  { 121,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #121 = G_FNEG
478
  { 122,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #122 = G_FPEXT
479
  { 123,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #123 = G_FPTRUNC
480
  { 124,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #124 = G_FPTOSI
481
  { 125,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #125 = G_FPTOUI
482
  { 126,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #126 = G_SITOFP
483
  { 127,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #127 = G_UITOFP
484
  { 128,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #128 = G_FABS
485
  { 129,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #129 = G_FCOPYSIGN
486
  { 130,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #130 = G_FCANONICALIZE
487
  { 131,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #131 = G_FMINNUM
488
  { 132,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #132 = G_FMAXNUM
489
  { 133,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #133 = G_FMINNUM_IEEE
490
  { 134,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #134 = G_FMAXNUM_IEEE
491
  { 135,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #135 = G_FMINIMUM
492
  { 136,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #136 = G_FMAXIMUM
493
  { 137,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #137 = G_GEP
494
  { 138,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #138 = G_PTR_MASK
495
  { 139,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #139 = G_SMIN
496
  { 140,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #140 = G_SMAX
497
  { 141,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #141 = G_UMIN
498
  { 142,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #142 = G_UMAX
499
  { 143,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #143 = G_BR
500
  { 144,  3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #144 = G_BRJT
501
  { 145,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #145 = G_INSERT_VECTOR_ELT
502
  { 146,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #146 = G_EXTRACT_VECTOR_ELT
503
  { 147,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #147 = G_SHUFFLE_VECTOR
504
  { 148,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #148 = G_CTTZ
505
  { 149,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #149 = G_CTTZ_ZERO_UNDEF
506
  { 150,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #150 = G_CTLZ
507
  { 151,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #151 = G_CTLZ_ZERO_UNDEF
508
  { 152,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #152 = G_CTPOP
509
  { 153,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #153 = G_BSWAP
510
  { 154,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #154 = G_FCEIL
511
  { 155,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #155 = G_FCOS
512
  { 156,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #156 = G_FSIN
513
  { 157,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #157 = G_FSQRT
514
  { 158,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #158 = G_FFLOOR
515
  { 159,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #159 = G_FRINT
516
  { 160,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #160 = G_FNEARBYINT
517
  { 161,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #161 = G_ADDRSPACE_CAST
518
  { 162,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #162 = G_BLOCK_ADDR
519
  { 163,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #163 = G_JUMP_TABLE
520
  { 164,  2,  0,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr },  // Inst #164 = ADJCALLSTACKDOWN
521
  { 165,  2,  0,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr },  // Inst #165 = ADJCALLSTACKUP
522
  { 166,  2,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #166 = ADJDYNALLOC
523
  { 167,  1,  0,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo2, -1 ,nullptr },  // Inst #167 = CALL
524
  { 168,  1,  0,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo33, -1 ,nullptr },  // Inst #168 = CALLR
525
  { 169,  3,  1,  4,  1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #169 = ADDC_F_I_HI
526
  { 170,  3,  1,  4,  1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #170 = ADDC_F_I_LO
527
  { 171,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo35, -1 ,nullptr },  // Inst #171 = ADDC_F_R
528
  { 172,  3,  1,  4,  1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #172 = ADDC_I_HI
529
  { 173,  3,  1,  4,  1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #173 = ADDC_I_LO
530
  { 174,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #174 = ADDC_R
531
  { 175,  3,  1,  4,  1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #175 = ADD_F_I_HI
532
  { 176,  3,  1,  4,  1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #176 = ADD_F_I_LO
533
  { 177,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo35, -1 ,nullptr },  // Inst #177 = ADD_F_R
534
  { 178,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #178 = ADD_I_HI
535
  { 179,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #179 = ADD_I_LO
536
  { 180,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #180 = ADD_R
537
  { 181,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #181 = AND_F_I_HI
538
  { 182,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #182 = AND_F_I_LO
539
  { 183,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo35, -1 ,nullptr },  // Inst #183 = AND_F_R
540
  { 184,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #184 = AND_I_HI
541
  { 185,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #185 = AND_I_LO
542
  { 186,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #186 = AND_R
543
  { 187,  2,  0,  4,  2,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #187 = BRCC
544
  { 188,  2,  0,  4,  1,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #188 = BRIND_CC
545
  { 189,  3,  0,  4,  1,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #189 = BRIND_CCA
546
  { 190,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #190 = BRR
547
  { 191,  1,  0,  4,  2,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #191 = BT
548
  { 192,  1,  0,  4,  1,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #192 = JR
549
  { 193,  2,  1,  4,  3,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #193 = LDADDR
550
  { 194,  4,  1,  4,  4,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #194 = LDBs_RI
551
  { 195,  4,  1,  4,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #195 = LDBs_RR
552
  { 196,  4,  1,  4,  4,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #196 = LDBz_RI
553
  { 197,  4,  1,  4,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #197 = LDBz_RR
554
  { 198,  4,  1,  4,  4,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #198 = LDHs_RI
555
  { 199,  4,  1,  4,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #199 = LDHs_RR
556
  { 200,  4,  1,  4,  4,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #200 = LDHz_RI
557
  { 201,  4,  1,  4,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #201 = LDHz_RR
558
  { 202,  4,  1,  4,  3,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #202 = LDW_RI
559
  { 203,  4,  1,  4,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #203 = LDW_RR
560
  { 204,  4,  1,  4,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #204 = LDWz_RR
561
  { 205,  2,  1,  4,  1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #205 = LEADZ
562
  { 206,  0,  0,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #206 = LOG0
563
  { 207,  0,  0,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #207 = LOG1
564
  { 208,  0,  0,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #208 = LOG2
565
  { 209,  0,  0,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #209 = LOG3
566
  { 210,  0,  0,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #210 = LOG4
567
  { 211,  2,  1,  4,  1,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #211 = MOVHI
568
  { 212,  0,  0,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #212 = NOP
569
  { 213,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #213 = OR_F_I_HI
570
  { 214,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #214 = OR_F_I_LO
571
  { 215,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo35, -1 ,nullptr },  // Inst #215 = OR_F_R
572
  { 216,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #216 = OR_I_HI
573
  { 217,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #217 = OR_I_LO
574
  { 218,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #218 = OR_R
575
  { 219,  2,  1,  4,  1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #219 = POPC
576
  { 220,  0,  0,  4,  0,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, nullptr, nullptr, -1 ,nullptr },  // Inst #220 = RET
577
  { 221,  3,  1,  4,  1,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #221 = SA_F_I
578
  { 222,  3,  1,  4,  1,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #222 = SA_I
579
  { 223,  2,  1,  4,  2,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #223 = SCC
580
  { 224,  4,  1,  4,  1,  0|(1ULL<<MCID::Select)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #224 = SELECT
581
  { 225,  2,  0,  4,  1,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo36, -1 ,nullptr },  // Inst #225 = SFSUB_F_RI_HI
582
  { 226,  2,  0,  4,  1,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo36, -1 ,nullptr },  // Inst #226 = SFSUB_F_RI_LO
583
  { 227,  2,  0,  4,  1,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo32, -1 ,nullptr },  // Inst #227 = SFSUB_F_RR
584
  { 228,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo35, -1 ,nullptr },  // Inst #228 = SHL_F_R
585
  { 229,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #229 = SHL_R
586
  { 230,  2,  1,  4,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #230 = SLI
587
  { 231,  3,  1,  4,  1,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #231 = SL_F_I
588
  { 232,  3,  1,  4,  1,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #232 = SL_I
589
  { 233,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo35, -1 ,nullptr },  // Inst #233 = SRA_F_R
590
  { 234,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #234 = SRA_R
591
  { 235,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo35, -1 ,nullptr },  // Inst #235 = SRL_F_R
592
  { 236,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #236 = SRL_R
593
  { 237,  2,  0,  4,  6,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #237 = STADDR
594
  { 238,  4,  0,  4,  7,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #238 = STB_RI
595
  { 239,  4,  0,  4,  6,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #239 = STB_RR
596
  { 240,  4,  0,  4,  7,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #240 = STH_RI
597
  { 241,  4,  0,  4,  6,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #241 = STH_RR
598
  { 242,  3,  1,  4,  1,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #242 = SUBB_F_I_HI
599
  { 243,  3,  1,  4,  1,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #243 = SUBB_F_I_LO
600
  { 244,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo35, -1 ,nullptr },  // Inst #244 = SUBB_F_R
601
  { 245,  3,  1,  4,  1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #245 = SUBB_I_HI
602
  { 246,  3,  1,  4,  1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #246 = SUBB_I_LO
603
  { 247,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #247 = SUBB_R
604
  { 248,  3,  1,  4,  1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #248 = SUB_F_I_HI
605
  { 249,  3,  1,  4,  1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #249 = SUB_F_I_LO
606
  { 250,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo35, -1 ,nullptr },  // Inst #250 = SUB_F_R
607
  { 251,  3,  1,  4,  1,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #251 = SUB_I_HI
608
  { 252,  3,  1,  4,  1,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #252 = SUB_I_LO
609
  { 253,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #253 = SUB_R
610
  { 254,  4,  0,  4,  6,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #254 = SW_RI
611
  { 255,  4,  0,  4,  6,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #255 = SW_RR
612
  { 256,  2,  1,  4,  1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #256 = TRAILZ
613
  { 257,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #257 = XOR_F_I_HI
614
  { 258,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #258 = XOR_F_I_LO
615
  { 259,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo35, -1 ,nullptr },  // Inst #259 = XOR_F_R
616
  { 260,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #260 = XOR_I_HI
617
  { 261,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #261 = XOR_I_LO
618
  { 262,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #262 = XOR_R
619
};
620
621
extern const char LanaiInstrNameData[] = {
622
  /* 0 */ 'G', '_', 'F', 'L', 'O', 'G', '1', '0', 0,
623
  /* 9 */ 'L', 'O', 'G', '0', 0,
624
  /* 14 */ 'L', 'O', 'G', '1', 0,
625
  /* 19 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0,
626
  /* 27 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0,
627
  /* 35 */ 'L', 'O', 'G', '3', 0,
628
  /* 40 */ 'L', 'O', 'G', '4', 0,
629
  /* 45 */ 'B', 'R', 'I', 'N', 'D', '_', 'C', 'C', 'A', 0,
630
  /* 55 */ 'G', '_', 'F', 'M', 'A', 0,
631
  /* 61 */ 'G', '_', 'F', 'S', 'U', 'B', 0,
632
  /* 68 */ 'G', '_', 'S', 'U', 'B', 0,
633
  /* 74 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'S', 'U', 'B', 0,
634
  /* 90 */ 'B', 'R', 'C', 'C', 0,
635
  /* 95 */ 'S', 'C', 'C', 0,
636
  /* 99 */ 'B', 'R', 'I', 'N', 'D', '_', 'C', 'C', 0,
637
  /* 108 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', 0,
638
  /* 120 */ 'G', '_', 'F', 'P', 'T', 'R', 'U', 'N', 'C', 0,
639
  /* 130 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'T', 'R', 'U', 'N', 'C', 0,
640
  /* 148 */ 'G', '_', 'T', 'R', 'U', 'N', 'C', 0,
641
  /* 156 */ 'G', '_', 'B', 'U', 'I', 'L', 'D', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'T', 'R', 'U', 'N', 'C', 0,
642
  /* 177 */ 'A', 'D', 'J', 'D', 'Y', 'N', 'A', 'L', 'L', 'O', 'C', 0,
643
  /* 189 */ 'P', 'O', 'P', 'C', 0,
644
  /* 194 */ 'G', '_', 'S', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
645
  /* 205 */ 'G', '_', 'Z', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
646
  /* 216 */ 'G', '_', 'L', 'O', 'A', 'D', 0,
647
  /* 223 */ 'G', '_', 'F', 'A', 'D', 'D', 0,
648
  /* 230 */ 'G', '_', 'A', 'D', 'D', 0,
649
  /* 236 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'D', 'D', 0,
650
  /* 252 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'N', 'A', 'N', 'D', 0,
651
  /* 269 */ 'G', '_', 'A', 'N', 'D', 0,
652
  /* 275 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'N', 'D', 0,
653
  /* 291 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
654
  /* 304 */ 'G', '_', 'B', 'R', 'C', 'O', 'N', 'D', 0,
655
  /* 313 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'R', 'O', 'U', 'N', 'D', 0,
656
  /* 331 */ 'L', 'O', 'A', 'D', '_', 'S', 'T', 'A', 'C', 'K', '_', 'G', 'U', 'A', 'R', 'D', 0,
657
  /* 348 */ 'G', '_', 'S', 'S', 'U', 'B', 'E', 0,
658
  /* 356 */ 'G', '_', 'U', 'S', 'U', 'B', 'E', 0,
659
  /* 364 */ 'G', '_', 'F', 'E', 'N', 'C', 'E', 0,
660
  /* 372 */ 'R', 'E', 'G', '_', 'S', 'E', 'Q', 'U', 'E', 'N', 'C', 'E', 0,
661
  /* 385 */ 'G', '_', 'S', 'A', 'D', 'D', 'E', 0,
662
  /* 393 */ 'G', '_', 'U', 'A', 'D', 'D', 'E', 0,
663
  /* 401 */ 'G', '_', 'F', 'M', 'I', 'N', 'N', 'U', 'M', '_', 'I', 'E', 'E', 'E', 0,
664
  /* 416 */ 'G', '_', 'F', 'M', 'A', 'X', 'N', 'U', 'M', '_', 'I', 'E', 'E', 'E', 0,
665
  /* 431 */ 'G', '_', 'J', 'U', 'M', 'P', '_', 'T', 'A', 'B', 'L', 'E', 0,
666
  /* 444 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
667
  /* 451 */ 'L', 'O', 'C', 'A', 'L', '_', 'E', 'S', 'C', 'A', 'P', 'E', 0,
668
  /* 464 */ 'G', '_', 'S', 'T', 'O', 'R', 'E', 0,
669
  /* 472 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
670
  /* 482 */ 'G', '_', 'G', 'L', 'O', 'B', 'A', 'L', '_', 'V', 'A', 'L', 'U', 'E', 0,
671
  /* 497 */ 'G', '_', 'F', 'C', 'A', 'N', 'O', 'N', 'I', 'C', 'A', 'L', 'I', 'Z', 'E', 0,
672
  /* 513 */ 'G', '_', 'C', 'T', 'L', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
673
  /* 531 */ 'G', '_', 'C', 'T', 'T', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
674
  /* 549 */ 'G', '_', 'I', 'M', 'P', 'L', 'I', 'C', 'I', 'T', '_', 'D', 'E', 'F', 0,
675
  /* 564 */ 'G', '_', 'F', 'N', 'E', 'G', 0,
676
  /* 571 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
677
  /* 586 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
678
  /* 600 */ 'S', 'U', 'B', 'R', 'E', 'G', '_', 'T', 'O', '_', 'R', 'E', 'G', 0,
679
  /* 614 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', 0,
680
  /* 631 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'C', 'H', 'G', 0,
681
  /* 648 */ 'G', '_', 'F', 'L', 'O', 'G', 0,
682
  /* 655 */ 'G', '_', 'V', 'A', 'A', 'R', 'G', 0,
683
  /* 663 */ 'G', '_', 'S', 'M', 'U', 'L', 'H', 0,
684
  /* 671 */ 'G', '_', 'U', 'M', 'U', 'L', 'H', 0,
685
  /* 679 */ 'G', '_', 'P', 'H', 'I', 0,
686
  /* 685 */ 'M', 'O', 'V', 'H', 'I', 0,
687
  /* 691 */ 'S', 'F', 'S', 'U', 'B', '_', 'F', '_', 'R', 'I', '_', 'H', 'I', 0,
688
  /* 705 */ 'S', 'U', 'B', 'B', '_', 'I', '_', 'H', 'I', 0,
689
  /* 715 */ 'S', 'U', 'B', '_', 'I', '_', 'H', 'I', 0,
690
  /* 724 */ 'A', 'D', 'D', 'C', '_', 'I', '_', 'H', 'I', 0,
691
  /* 734 */ 'A', 'D', 'D', '_', 'I', '_', 'H', 'I', 0,
692
  /* 743 */ 'A', 'N', 'D', '_', 'I', '_', 'H', 'I', 0,
693
  /* 752 */ 'S', 'U', 'B', 'B', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
694
  /* 764 */ 'S', 'U', 'B', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
695
  /* 775 */ 'A', 'D', 'D', 'C', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
696
  /* 787 */ 'A', 'D', 'D', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
697
  /* 798 */ 'A', 'N', 'D', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
698
  /* 809 */ 'X', 'O', 'R', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
699
  /* 820 */ 'X', 'O', 'R', '_', 'I', '_', 'H', 'I', 0,
700
  /* 829 */ 'S', 'L', 'I', 0,
701
  /* 833 */ 'S', 'T', 'B', '_', 'R', 'I', 0,
702
  /* 840 */ 'S', 'T', 'H', '_', 'R', 'I', 0,
703
  /* 847 */ 'L', 'D', 'W', '_', 'R', 'I', 0,
704
  /* 854 */ 'S', 'W', '_', 'R', 'I', 0,
705
  /* 860 */ 'L', 'D', 'B', 's', '_', 'R', 'I', 0,
706
  /* 868 */ 'L', 'D', 'H', 's', '_', 'R', 'I', 0,
707
  /* 876 */ 'L', 'D', 'B', 'z', '_', 'R', 'I', 0,
708
  /* 884 */ 'L', 'D', 'H', 'z', '_', 'R', 'I', 0,
709
  /* 892 */ 'G', '_', 'F', 'P', 'T', 'O', 'S', 'I', 0,
710
  /* 901 */ 'G', '_', 'F', 'P', 'T', 'O', 'U', 'I', 0,
711
  /* 910 */ 'S', 'A', '_', 'I', 0,
712
  /* 915 */ 'S', 'A', '_', 'F', '_', 'I', 0,
713
  /* 922 */ 'S', 'L', '_', 'F', '_', 'I', 0,
714
  /* 929 */ 'S', 'L', '_', 'I', 0,
715
  /* 934 */ 'G', '_', 'P', 'T', 'R', '_', 'M', 'A', 'S', 'K', 0,
716
  /* 945 */ 'G', 'C', '_', 'L', 'A', 'B', 'E', 'L', 0,
717
  /* 954 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0,
718
  /* 964 */ 'E', 'H', '_', 'L', 'A', 'B', 'E', 'L', 0,
719
  /* 973 */ 'A', 'N', 'N', 'O', 'T', 'A', 'T', 'I', 'O', 'N', '_', 'L', 'A', 'B', 'E', 'L', 0,
720
  /* 990 */ 'I', 'C', 'A', 'L', 'L', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'F', 'U', 'N', 'N', 'E', 'L', 0,
721
  /* 1010 */ 'G', '_', 'S', 'H', 'L', 0,
722
  /* 1016 */ 'G', '_', 'F', 'C', 'E', 'I', 'L', 0,
723
  /* 1024 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'A', 'I', 'L', '_', 'C', 'A', 'L', 'L', 0,
724
  /* 1044 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
725
  /* 1071 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
726
  /* 1092 */ 'F', 'E', 'N', 'T', 'R', 'Y', '_', 'C', 'A', 'L', 'L', 0,
727
  /* 1104 */ 'K', 'I', 'L', 'L', 0,
728
  /* 1109 */ 'G', '_', 'F', 'M', 'U', 'L', 0,
729
  /* 1116 */ 'G', '_', 'M', 'U', 'L', 0,
730
  /* 1122 */ 'G', '_', 'F', 'R', 'E', 'M', 0,
731
  /* 1129 */ 'G', '_', 'S', 'R', 'E', 'M', 0,
732
  /* 1136 */ 'G', '_', 'U', 'R', 'E', 'M', 0,
733
  /* 1143 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', 0,
734
  /* 1153 */ 'G', '_', 'F', 'M', 'I', 'N', 'I', 'M', 'U', 'M', 0,
735
  /* 1164 */ 'G', '_', 'F', 'M', 'A', 'X', 'I', 'M', 'U', 'M', 0,
736
  /* 1175 */ 'G', '_', 'F', 'M', 'I', 'N', 'N', 'U', 'M', 0,
737
  /* 1185 */ 'G', '_', 'F', 'M', 'A', 'X', 'N', 'U', 'M', 0,
738
  /* 1195 */ 'G', '_', 'F', 'C', 'O', 'P', 'Y', 'S', 'I', 'G', 'N', 0,
739
  /* 1207 */ 'G', '_', 'S', 'M', 'I', 'N', 0,
740
  /* 1214 */ 'G', '_', 'U', 'M', 'I', 'N', 0,
741
  /* 1221 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'I', 'N', 0,
742
  /* 1238 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'I', 'N', 0,
743
  /* 1254 */ 'G', '_', 'F', 'S', 'I', 'N', 0,
744
  /* 1261 */ 'C', 'F', 'I', '_', 'I', 'N', 'S', 'T', 'R', 'U', 'C', 'T', 'I', 'O', 'N', 0,
745
  /* 1277 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 0,
746
  /* 1294 */ 'G', '_', 'S', 'S', 'U', 'B', 'O', 0,
747
  /* 1302 */ 'G', '_', 'U', 'S', 'U', 'B', 'O', 0,
748
  /* 1310 */ 'G', '_', 'S', 'A', 'D', 'D', 'O', 0,
749
  /* 1318 */ 'G', '_', 'U', 'A', 'D', 'D', 'O', 0,
750
  /* 1326 */ 'G', '_', 'S', 'M', 'U', 'L', 'O', 0,
751
  /* 1334 */ 'G', '_', 'U', 'M', 'U', 'L', 'O', 0,
752
  /* 1342 */ 'S', 'F', 'S', 'U', 'B', '_', 'F', '_', 'R', 'I', '_', 'L', 'O', 0,
753
  /* 1356 */ 'S', 'U', 'B', 'B', '_', 'I', '_', 'L', 'O', 0,
754
  /* 1366 */ 'S', 'U', 'B', '_', 'I', '_', 'L', 'O', 0,
755
  /* 1375 */ 'A', 'D', 'D', 'C', '_', 'I', '_', 'L', 'O', 0,
756
  /* 1385 */ 'A', 'D', 'D', '_', 'I', '_', 'L', 'O', 0,
757
  /* 1394 */ 'A', 'N', 'D', '_', 'I', '_', 'L', 'O', 0,
758
  /* 1403 */ 'S', 'U', 'B', 'B', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
759
  /* 1415 */ 'S', 'U', 'B', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
760
  /* 1426 */ 'A', 'D', 'D', 'C', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
761
  /* 1438 */ 'A', 'D', 'D', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
762
  /* 1449 */ 'A', 'N', 'D', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
763
  /* 1460 */ 'X', 'O', 'R', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
764
  /* 1471 */ 'X', 'O', 'R', '_', 'I', '_', 'L', 'O', 0,
765
  /* 1480 */ 'S', 'T', 'A', 'C', 'K', 'M', 'A', 'P', 0,
766
  /* 1489 */ 'G', '_', 'B', 'S', 'W', 'A', 'P', 0,
767
  /* 1497 */ 'G', '_', 'G', 'E', 'P', 0,
768
  /* 1503 */ 'G', '_', 'S', 'I', 'T', 'O', 'F', 'P', 0,
769
  /* 1512 */ 'G', '_', 'U', 'I', 'T', 'O', 'F', 'P', 0,
770
  /* 1521 */ 'G', '_', 'F', 'C', 'M', 'P', 0,
771
  /* 1528 */ 'G', '_', 'I', 'C', 'M', 'P', 0,
772
  /* 1535 */ 'N', 'O', 'P', 0,
773
  /* 1539 */ 'G', '_', 'C', 'T', 'P', 'O', 'P', 0,
774
  /* 1547 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'O', 'P', 0,
775
  /* 1560 */ 'F', 'A', 'U', 'L', 'T', 'I', 'N', 'G', '_', 'O', 'P', 0,
776
  /* 1572 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 0,
777
  /* 1587 */ 'G', '_', 'F', 'E', 'X', 'P', 0,
778
  /* 1594 */ 'G', '_', 'B', 'R', 0,
779
  /* 1599 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', '_', 'B', 'R', 0,
780
  /* 1612 */ 'L', 'D', 'A', 'D', 'D', 'R', 0,
781
  /* 1619 */ 'S', 'T', 'A', 'D', 'D', 'R', 0,
782
  /* 1626 */ 'G', '_', 'B', 'L', 'O', 'C', 'K', '_', 'A', 'D', 'D', 'R', 0,
783
  /* 1639 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'N', 'T', 'E', 'R', 0,
784
  /* 1664 */ 'G', '_', 'A', 'S', 'H', 'R', 0,
785
  /* 1671 */ 'G', '_', 'L', 'S', 'H', 'R', 0,
786
  /* 1678 */ 'J', 'R', 0,
787
  /* 1681 */ 'C', 'A', 'L', 'L', 'R', 0,
788
  /* 1687 */ 'G', '_', 'F', 'F', 'L', 'O', 'O', 'R', 0,
789
  /* 1696 */ 'G', '_', 'B', 'U', 'I', 'L', 'D', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
790
  /* 1711 */ 'G', '_', 'S', 'H', 'U', 'F', 'F', 'L', 'E', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
791
  /* 1728 */ 'G', '_', 'X', 'O', 'R', 0,
792
  /* 1734 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'O', 'R', 0,
793
  /* 1750 */ 'G', '_', 'O', 'R', 0,
794
  /* 1755 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'O', 'R', 0,
795
  /* 1770 */ 'B', 'R', 'R', 0,
796
  /* 1774 */ 'S', 'T', 'B', '_', 'R', 'R', 0,
797
  /* 1781 */ 'S', 'F', 'S', 'U', 'B', '_', 'F', '_', 'R', 'R', 0,
798
  /* 1792 */ 'S', 'T', 'H', '_', 'R', 'R', 0,
799
  /* 1799 */ 'L', 'D', 'W', '_', 'R', 'R', 0,
800
  /* 1806 */ 'S', 'W', '_', 'R', 'R', 0,
801
  /* 1812 */ 'L', 'D', 'B', 's', '_', 'R', 'R', 0,
802
  /* 1820 */ 'L', 'D', 'H', 's', '_', 'R', 'R', 0,
803
  /* 1828 */ 'L', 'D', 'B', 'z', '_', 'R', 'R', 0,
804
  /* 1836 */ 'L', 'D', 'H', 'z', '_', 'R', 'R', 0,
805
  /* 1844 */ 'L', 'D', 'W', 'z', '_', 'R', 'R', 0,
806
  /* 1852 */ 'G', '_', 'I', 'N', 'T', 'T', 'O', 'P', 'T', 'R', 0,
807
  /* 1863 */ 'S', 'R', 'A', '_', 'R', 0,
808
  /* 1869 */ 'S', 'U', 'B', 'B', '_', 'R', 0,
809
  /* 1876 */ 'S', 'U', 'B', '_', 'R', 0,
810
  /* 1882 */ 'A', 'D', 'D', 'C', '_', 'R', 0,
811
  /* 1889 */ 'A', 'D', 'D', '_', 'R', 0,
812
  /* 1895 */ 'A', 'N', 'D', '_', 'R', 0,
813
  /* 1901 */ 'S', 'R', 'A', '_', 'F', '_', 'R', 0,
814
  /* 1909 */ 'S', 'U', 'B', 'B', '_', 'F', '_', 'R', 0,
815
  /* 1918 */ 'S', 'U', 'B', '_', 'F', '_', 'R', 0,
816
  /* 1926 */ 'A', 'D', 'D', 'C', '_', 'F', '_', 'R', 0,
817
  /* 1935 */ 'A', 'D', 'D', '_', 'F', '_', 'R', 0,
818
  /* 1943 */ 'A', 'N', 'D', '_', 'F', '_', 'R', 0,
819
  /* 1951 */ 'S', 'H', 'L', '_', 'F', '_', 'R', 0,
820
  /* 1959 */ 'S', 'R', 'L', '_', 'F', '_', 'R', 0,
821
  /* 1967 */ 'X', 'O', 'R', '_', 'F', '_', 'R', 0,
822
  /* 1975 */ 'S', 'H', 'L', '_', 'R', 0,
823
  /* 1981 */ 'S', 'R', 'L', '_', 'R', 0,
824
  /* 1987 */ 'X', 'O', 'R', '_', 'R', 0,
825
  /* 1993 */ 'G', '_', 'F', 'A', 'B', 'S', 0,
826
  /* 2000 */ 'G', '_', 'U', 'N', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
827
  /* 2017 */ 'G', '_', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
828
  /* 2032 */ 'G', '_', 'F', 'C', 'O', 'S', 0,
829
  /* 2039 */ 'G', '_', 'C', 'O', 'N', 'C', 'A', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', 'S', 0,
830
  /* 2056 */ 'C', 'O', 'P', 'Y', '_', 'T', 'O', '_', 'R', 'E', 'G', 'C', 'L', 'A', 'S', 'S', 0,
831
  /* 2073 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'W', 'I', 'T', 'H', '_', 'S', 'U', 'C', 'C', 'E', 'S', 'S', 0,
832
  /* 2103 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'W', '_', 'S', 'I', 'D', 'E', '_', 'E', 'F', 'F', 'E', 'C', 'T', 'S', 0,
833
  /* 2130 */ 'B', 'T', 0,
834
  /* 2133 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', 0,
835
  /* 2143 */ 'G', '_', 'S', 'E', 'L', 'E', 'C', 'T', 0,
836
  /* 2152 */ 'G', '_', 'B', 'R', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', 0,
837
  /* 2165 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'R', 'E', 'T', 0,
838
  /* 2179 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'X', 'I', 'T', 0,
839
  /* 2203 */ 'G', '_', 'B', 'R', 'J', 'T', 0,
840
  /* 2210 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
841
  /* 2231 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
842
  /* 2251 */ 'G', '_', 'F', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
843
  /* 2263 */ 'G', '_', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
844
  /* 2274 */ 'S', 'T', 'A', 'T', 'E', 'P', 'O', 'I', 'N', 'T', 0,
845
  /* 2285 */ 'P', 'A', 'T', 'C', 'H', 'P', 'O', 'I', 'N', 'T', 0,
846
  /* 2296 */ 'G', '_', 'P', 'T', 'R', 'T', 'O', 'I', 'N', 'T', 0,
847
  /* 2307 */ 'G', '_', 'F', 'R', 'I', 'N', 'T', 0,
848
  /* 2315 */ 'G', '_', 'F', 'N', 'E', 'A', 'R', 'B', 'Y', 'I', 'N', 'T', 0,
849
  /* 2328 */ 'G', '_', 'V', 'A', 'S', 'T', 'A', 'R', 'T', 0,
850
  /* 2338 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
851
  /* 2353 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', 0,
852
  /* 2362 */ 'G', '_', 'F', 'S', 'Q', 'R', 'T', 0,
853
  /* 2370 */ 'G', '_', 'B', 'I', 'T', 'C', 'A', 'S', 'T', 0,
854
  /* 2380 */ 'G', '_', 'A', 'D', 'D', 'R', 'S', 'P', 'A', 'C', 'E', '_', 'C', 'A', 'S', 'T', 0,
855
  /* 2397 */ 'G', '_', 'F', 'P', 'E', 'X', 'T', 0,
856
  /* 2405 */ 'G', '_', 'S', 'E', 'X', 'T', 0,
857
  /* 2412 */ 'G', '_', 'A', 'N', 'Y', 'E', 'X', 'T', 0,
858
  /* 2421 */ 'G', '_', 'Z', 'E', 'X', 'T', 0,
859
  /* 2428 */ 'G', '_', 'F', 'D', 'I', 'V', 0,
860
  /* 2435 */ 'G', '_', 'S', 'D', 'I', 'V', 0,
861
  /* 2442 */ 'G', '_', 'U', 'D', 'I', 'V', 0,
862
  /* 2449 */ 'G', '_', 'F', 'P', 'O', 'W', 0,
863
  /* 2456 */ 'G', '_', 'S', 'M', 'A', 'X', 0,
864
  /* 2463 */ 'G', '_', 'U', 'M', 'A', 'X', 0,
865
  /* 2470 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'A', 'X', 0,
866
  /* 2487 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'A', 'X', 0,
867
  /* 2503 */ 'G', '_', 'F', 'R', 'A', 'M', 'E', '_', 'I', 'N', 'D', 'E', 'X', 0,
868
  /* 2517 */ 'C', 'O', 'P', 'Y', 0,
869
  /* 2522 */ 'L', 'E', 'A', 'D', 'Z', 0,
870
  /* 2528 */ 'T', 'R', 'A', 'I', 'L', 'Z', 0,
871
  /* 2535 */ 'G', '_', 'C', 'T', 'L', 'Z', 0,
872
  /* 2542 */ 'G', '_', 'C', 'T', 'T', 'Z', 0,
873
};
874
875
extern const unsigned LanaiInstrNameIndices[] = {
876
    681U, 1143U, 1599U, 1261U, 964U, 945U, 973U, 1104U, 
877
    571U, 586U, 551U, 600U, 2056U, 472U, 954U, 372U, 
878
    2517U, 444U, 2338U, 291U, 1480U, 1092U, 2285U, 331U, 
879
    2274U, 451U, 1560U, 1547U, 1639U, 2165U, 2179U, 1024U, 
880
    1071U, 1044U, 990U, 230U, 68U, 1116U, 2435U, 2442U, 
881
    1129U, 1136U, 269U, 1750U, 1728U, 549U, 679U, 2503U, 
882
    482U, 2133U, 2000U, 2353U, 2017U, 1696U, 156U, 2039U, 
883
    2296U, 1852U, 2370U, 130U, 313U, 216U, 194U, 205U, 
884
    464U, 2073U, 614U, 631U, 236U, 74U, 275U, 252U, 
885
    1755U, 1734U, 2487U, 1238U, 2470U, 1221U, 364U, 304U, 
886
    2152U, 108U, 2103U, 2412U, 148U, 2263U, 2251U, 2328U, 
887
    655U, 2405U, 2421U, 1010U, 1671U, 1664U, 1528U, 1521U, 
888
    2143U, 1318U, 393U, 1302U, 356U, 1310U, 385U, 1294U, 
889
    348U, 1334U, 1326U, 671U, 663U, 223U, 61U, 1109U, 
890
    55U, 2428U, 1122U, 2449U, 1587U, 27U, 648U, 19U, 
891
    0U, 564U, 2397U, 120U, 892U, 901U, 1503U, 1512U, 
892
    1993U, 1195U, 497U, 1175U, 1185U, 401U, 416U, 1153U, 
893
    1164U, 1497U, 934U, 1207U, 2456U, 1214U, 2463U, 1594U, 
894
    2203U, 2231U, 2210U, 1711U, 2542U, 531U, 2535U, 513U, 
895
    1539U, 1489U, 1016U, 2032U, 1254U, 2362U, 1687U, 2307U, 
896
    2315U, 2380U, 1626U, 431U, 1277U, 1572U, 177U, 1039U, 
897
    1681U, 775U, 1426U, 1926U, 724U, 1375U, 1882U, 787U, 
898
    1438U, 1935U, 734U, 1385U, 1889U, 798U, 1449U, 1943U, 
899
    743U, 1394U, 1895U, 90U, 99U, 45U, 1770U, 2130U, 
900
    1678U, 1612U, 860U, 1812U, 876U, 1828U, 868U, 1820U, 
901
    884U, 1836U, 847U, 1799U, 1844U, 2522U, 9U, 14U, 
902
    22U, 35U, 40U, 685U, 1535U, 810U, 1461U, 1968U, 
903
    821U, 1472U, 1988U, 189U, 2175U, 915U, 910U, 95U, 
904
    2145U, 691U, 1342U, 1781U, 1951U, 1975U, 829U, 922U, 
905
    929U, 1901U, 1863U, 1959U, 1981U, 1619U, 833U, 1774U, 
906
    840U, 1792U, 752U, 1403U, 1909U, 705U, 1356U, 1869U, 
907
    764U, 1415U, 1918U, 715U, 1366U, 1876U, 854U, 1806U, 
908
    2528U, 809U, 1460U, 1967U, 820U, 1471U, 1987U, 
909
};
910
911
35
static inline void InitLanaiMCInstrInfo(MCInstrInfo *II) {
912
35
  II->InitMCInstrInfo(LanaiInsts, LanaiInstrNameIndices, LanaiInstrNameData, 263);
913
35
}
914
915
} // end llvm namespace
916
#endif // GET_INSTRINFO_MC_DESC
917
918
#ifdef GET_INSTRINFO_HEADER
919
#undef GET_INSTRINFO_HEADER
920
namespace llvm {
921
struct LanaiGenInstrInfo : public TargetInstrInfo {
922
  explicit LanaiGenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);
923
26
  ~LanaiGenInstrInfo() override = default;
924
925
};
926
} // end llvm namespace
927
#endif // GET_INSTRINFO_HEADER
928
929
#ifdef GET_INSTRINFO_HELPER_DECLS
930
#undef GET_INSTRINFO_HELPER_DECLS
931
932
933
#endif // GET_INSTRINFO_HELPER_DECLS
934
935
#ifdef GET_INSTRINFO_HELPERS
936
#undef GET_INSTRINFO_HELPERS
937
938
#endif // GET_INSTRINFO_HELPERS
939
940
#ifdef GET_INSTRINFO_CTOR_DTOR
941
#undef GET_INSTRINFO_CTOR_DTOR
942
namespace llvm {
943
extern const MCInstrDesc LanaiInsts[];
944
extern const unsigned LanaiInstrNameIndices[];
945
extern const char LanaiInstrNameData[];
946
LanaiGenInstrInfo::LanaiGenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)
947
27
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
948
27
  InitMCInstrInfo(LanaiInsts, LanaiInstrNameIndices, LanaiInstrNameData, 263);
949
27
}
950
} // end llvm namespace
951
#endif // GET_INSTRINFO_CTOR_DTOR
952
953
#ifdef GET_INSTRINFO_OPERAND_ENUM
954
#undef GET_INSTRINFO_OPERAND_ENUM
955
namespace llvm {
956
namespace Lanai {
957
namespace OpName {
958
enum {
959
OPERAND_LAST
960
};
961
} // end namespace OpName
962
} // end namespace Lanai
963
} // end namespace llvm
964
#endif //GET_INSTRINFO_OPERAND_ENUM
965
966
#ifdef GET_INSTRINFO_NAMED_OPS
967
#undef GET_INSTRINFO_NAMED_OPS
968
namespace llvm {
969
namespace Lanai {
970
LLVM_READONLY
971
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
972
  return -1;
973
}
974
} // end namespace Lanai
975
} // end namespace llvm
976
#endif //GET_INSTRINFO_NAMED_OPS
977
978
#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
979
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
980
namespace llvm {
981
namespace Lanai {
982
namespace OpTypes {
983
enum OperandType {
984
  AluOp = 0,
985
  BrTarget = 1,
986
  CCOp = 2,
987
  CallTarget = 3,
988
  MEMi = 4,
989
  MEMri = 5,
990
  MEMrr = 6,
991
  MEMspls = 7,
992
  f32imm = 8,
993
  f64imm = 9,
994
  i16imm = 10,
995
  i1imm = 11,
996
  i32hi16 = 12,
997
  i32hi16and = 13,
998
  i32imm = 14,
999
  i32lo16and = 15,
1000
  i32lo16s = 16,
1001
  i32lo16z = 17,
1002
  i32lo21 = 18,
1003
  i32neg16 = 19,
1004
  i64imm = 20,
1005
  i8imm = 21,
1006
  imm10 = 22,
1007
  immShift = 23,
1008
  pred = 24,
1009
  ptype0 = 25,
1010
  ptype1 = 26,
1011
  ptype2 = 27,
1012
  ptype3 = 28,
1013
  ptype4 = 29,
1014
  ptype5 = 30,
1015
  type0 = 31,
1016
  type1 = 32,
1017
  type2 = 33,
1018
  type3 = 34,
1019
  type4 = 35,
1020
  type5 = 36,
1021
  OPERAND_TYPE_LIST_END
1022
};
1023
} // end namespace OpTypes
1024
} // end namespace Lanai
1025
} // end namespace llvm
1026
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
1027
1028
#ifdef GET_INSTRINFO_OPERAND_TYPE
1029
#undef GET_INSTRINFO_OPERAND_TYPE
1030
namespace llvm {
1031
namespace Lanai {
1032
LLVM_READONLY
1033
int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
1034
  const int Offsets[] = {
1035
    0,
1036
    1,
1037
    1,
1038
    1,
1039
    2,
1040
    3,
1041
    4,
1042
    5,
1043
    5,
1044
    8,
1045
    12,
1046
    13,
1047
    17,
1048
    20,
1049
    20,
1050
    21,
1051
    23,
1052
    25,
1053
    25,
1054
    26,
1055
    27,
1056
    29,
1057
    29,
1058
    35,
1059
    36,
1060
    36,
1061
    38,
1062
    39,
1063
    39,
1064
    39,
1065
    39,
1066
    39,
1067
    39,
1068
    41,
1069
    44,
1070
    44,
1071
    47,
1072
    50,
1073
    53,
1074
    56,
1075
    59,
1076
    62,
1077
    65,
1078
    68,
1079
    71,
1080
    74,
1081
    75,
1082
    76,
1083
    78,
1084
    80,
1085
    83,
1086
    85,
1087
    89,
1088
    91,
1089
    93,
1090
    95,
1091
    97,
1092
    99,
1093
    101,
1094
    103,
1095
    105,
1096
    107,
1097
    109,
1098
    111,
1099
    113,
1100
    115,
1101
    120,
1102
    124,
1103
    127,
1104
    130,
1105
    133,
1106
    136,
1107
    139,
1108
    142,
1109
    145,
1110
    148,
1111
    151,
1112
    154,
1113
    157,
1114
    159,
1115
    161,
1116
    162,
1117
    163,
1118
    164,
1119
    166,
1120
    168,
1121
    170,
1122
    172,
1123
    173,
1124
    176,
1125
    178,
1126
    180,
1127
    183,
1128
    186,
1129
    189,
1130
    193,
1131
    197,
1132
    201,
1133
    205,
1134
    210,
1135
    214,
1136
    219,
1137
    223,
1138
    228,
1139
    232,
1140
    237,
1141
    241,
1142
    245,
1143
    248,
1144
    251,
1145
    254,
1146
    257,
1147
    260,
1148
    264,
1149
    267,
1150
    270,
1151
    273,
1152
    275,
1153
    277,
1154
    279,
1155
    281,
1156
    283,
1157
    285,
1158
    287,
1159
    289,
1160
    291,
1161
    293,
1162
    295,
1163
    297,
1164
    299,
1165
    302,
1166
    304,
1167
    307,
1168
    310,
1169
    313,
1170
    316,
1171
    319,
1172
    322,
1173
    325,
1174
    328,
1175
    331,
1176
    334,
1177
    337,
1178
    340,
1179
    341,
1180
    344,
1181
    348,
1182
    351,
1183
    355,
1184
    357,
1185
    359,
1186
    361,
1187
    363,
1188
    365,
1189
    367,
1190
    369,
1191
    371,
1192
    373,
1193
    375,
1194
    377,
1195
    379,
1196
    381,
1197
    383,
1198
    385,
1199
    387,
1200
    389,
1201
    391,
1202
    393,
1203
    394,
1204
    395,
1205
    398,
1206
    401,
1207
    405,
1208
    408,
1209
    411,
1210
    415,
1211
    418,
1212
    421,
1213
    425,
1214
    428,
1215
    431,
1216
    435,
1217
    438,
1218
    441,
1219
    445,
1220
    448,
1221
    451,
1222
    455,
1223
    457,
1224
    459,
1225
    462,
1226
    464,
1227
    465,
1228
    466,
1229
    468,
1230
    472,
1231
    476,
1232
    480,
1233
    484,
1234
    488,
1235
    492,
1236
    496,
1237
    500,
1238
    504,
1239
    508,
1240
    512,
1241
    514,
1242
    514,
1243
    514,
1244
    514,
1245
    514,
1246
    514,
1247
    516,
1248
    516,
1249
    519,
1250
    522,
1251
    526,
1252
    529,
1253
    532,
1254
    536,
1255
    538,
1256
    538,
1257
    541,
1258
    544,
1259
    546,
1260
    550,
1261
    552,
1262
    554,
1263
    556,
1264
    560,
1265
    564,
1266
    566,
1267
    569,
1268
    572,
1269
    576,
1270
    580,
1271
    584,
1272
    588,
1273
    590,
1274
    594,
1275
    598,
1276
    602,
1277
    606,
1278
    609,
1279
    612,
1280
    616,
1281
    619,
1282
    622,
1283
    626,
1284
    629,
1285
    632,
1286
    636,
1287
    639,
1288
    642,
1289
    646,
1290
    650,
1291
    654,
1292
    656,
1293
    659,
1294
    662,
1295
    666,
1296
    669,
1297
    672,
1298
  };
1299
  const int OpcodeOperandTypes[] = {
1300
    -1, 
1301
    /**/
1302
    /**/
1303
    OpTypes::i32imm, 
1304
    OpTypes::i32imm, 
1305
    OpTypes::i32imm, 
1306
    OpTypes::i32imm, 
1307
    /**/
1308
    -1, -1, OpTypes::i32imm, 
1309
    -1, -1, -1, OpTypes::i32imm, 
1310
    -1, 
1311
    -1, -1, -1, OpTypes::i32imm, 
1312
    -1, -1, OpTypes::i32imm, 
1313
    /**/
1314
    -1, 
1315
    -1, -1, 
1316
    -1, -1, 
1317
    /**/
1318
    OpTypes::i32imm, 
1319
    OpTypes::i32imm, 
1320
    OpTypes::i64imm, OpTypes::i32imm, 
1321
    /**/
1322
    -1, OpTypes::i64imm, OpTypes::i32imm, -1, OpTypes::i32imm, OpTypes::i32imm, 
1323
    -1, 
1324
    /**/
1325
    -1, OpTypes::i32imm, 
1326
    -1, 
1327
    /**/
1328
    /**/
1329
    /**/
1330
    /**/
1331
    /**/
1332
    -1, OpTypes::i8imm, 
1333
    OpTypes::i16imm, -1, OpTypes::i32imm, 
1334
    /**/
1335
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1336
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1337
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1338
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1339
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1340
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1341
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1342
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1343
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1344
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1345
    OpTypes::type0, 
1346
    OpTypes::type0, 
1347
    OpTypes::type0, -1, 
1348
    OpTypes::type0, -1, 
1349
    OpTypes::type0, OpTypes::type1, -1, 
1350
    OpTypes::type0, OpTypes::type1, 
1351
    OpTypes::type0, OpTypes::type0, OpTypes::type1, -1, 
1352
    OpTypes::type0, OpTypes::type1, 
1353
    OpTypes::type0, OpTypes::type1, 
1354
    OpTypes::type0, OpTypes::type1, 
1355
    OpTypes::type0, OpTypes::type1, 
1356
    OpTypes::type0, OpTypes::type1, 
1357
    OpTypes::type0, OpTypes::type1, 
1358
    OpTypes::type0, OpTypes::type1, 
1359
    OpTypes::type0, OpTypes::type0, 
1360
    OpTypes::type0, OpTypes::type0, 
1361
    OpTypes::type0, OpTypes::ptype1, 
1362
    OpTypes::type0, OpTypes::ptype1, 
1363
    OpTypes::type0, OpTypes::ptype1, 
1364
    OpTypes::type0, OpTypes::ptype1, 
1365
    OpTypes::type0, OpTypes::type1, OpTypes::type2, OpTypes::type0, OpTypes::type0, 
1366
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, OpTypes::type0, 
1367
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
1368
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
1369
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
1370
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
1371
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
1372
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
1373
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
1374
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
1375
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
1376
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
1377
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
1378
    OpTypes::i32imm, OpTypes::i32imm, 
1379
    OpTypes::type0, -1, 
1380
    OpTypes::type0, 
1381
    -1, 
1382
    -1, 
1383
    OpTypes::type0, OpTypes::type1, 
1384
    OpTypes::type0, OpTypes::type1, 
1385
    OpTypes::type0, -1, 
1386
    OpTypes::type0, -1, 
1387
    OpTypes::type0, 
1388
    OpTypes::type0, OpTypes::type1, -1, 
1389
    OpTypes::type0, OpTypes::type1, 
1390
    OpTypes::type0, OpTypes::type1, 
1391
    OpTypes::type0, OpTypes::type0, OpTypes::type1, 
1392
    OpTypes::type0, OpTypes::type0, OpTypes::type1, 
1393
    OpTypes::type0, OpTypes::type0, OpTypes::type1, 
1394
    OpTypes::type0, -1, OpTypes::type1, OpTypes::type1, 
1395
    OpTypes::type0, -1, OpTypes::type1, OpTypes::type1, 
1396
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
1397
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
1398
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, 
1399
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
1400
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, 
1401
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
1402
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, 
1403
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
1404
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, 
1405
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
1406
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
1407
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1408
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1409
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1410
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1411
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1412
    OpTypes::type0, OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1413
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1414
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1415
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1416
    OpTypes::type0, OpTypes::type0, 
1417
    OpTypes::type0, OpTypes::type0, 
1418
    OpTypes::type0, OpTypes::type0, 
1419
    OpTypes::type0, OpTypes::type0, 
1420
    OpTypes::type0, OpTypes::type0, 
1421
    OpTypes::type0, OpTypes::type0, 
1422
    OpTypes::type0, OpTypes::type1, 
1423
    OpTypes::type0, OpTypes::type1, 
1424
    OpTypes::type0, OpTypes::type1, 
1425
    OpTypes::type0, OpTypes::type1, 
1426
    OpTypes::type0, OpTypes::type1, 
1427
    OpTypes::type0, OpTypes::type1, 
1428
    OpTypes::type0, OpTypes::type0, 
1429
    OpTypes::type0, OpTypes::type0, OpTypes::type1, 
1430
    OpTypes::type0, OpTypes::type0, 
1431
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1432
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1433
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1434
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1435
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1436
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1437
    OpTypes::type0, OpTypes::type0, OpTypes::type1, 
1438
    OpTypes::type0, OpTypes::type0, -1, 
1439
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1440
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1441
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1442
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
1443
    -1, 
1444
    OpTypes::ptype0, -1, OpTypes::type1, 
1445
    OpTypes::type0, OpTypes::type0, OpTypes::type1, OpTypes::type2, 
1446
    OpTypes::type0, OpTypes::type1, OpTypes::type2, 
1447
    OpTypes::type0, OpTypes::type1, OpTypes::type1, OpTypes::type2, 
1448
    OpTypes::type0, OpTypes::type1, 
1449
    OpTypes::type0, OpTypes::type1, 
1450
    OpTypes::type0, OpTypes::type1, 
1451
    OpTypes::type0, OpTypes::type1, 
1452
    OpTypes::type0, OpTypes::type1, 
1453
    OpTypes::type0, OpTypes::type0, 
1454
    OpTypes::type0, OpTypes::type0, 
1455
    OpTypes::type0, OpTypes::type0, 
1456
    OpTypes::type0, OpTypes::type0, 
1457
    OpTypes::type0, OpTypes::type0, 
1458
    OpTypes::type0, OpTypes::type0, 
1459
    OpTypes::type0, OpTypes::type0, 
1460
    OpTypes::type0, OpTypes::type0, 
1461
    OpTypes::type0, OpTypes::type1, 
1462
    OpTypes::type0, -1, 
1463
    OpTypes::type0, -1, 
1464
    OpTypes::i32imm, OpTypes::i32imm, 
1465
    OpTypes::i32imm, OpTypes::i32imm, 
1466
    -1, -1, 
1467
    OpTypes::CallTarget, 
1468
    -1, 
1469
    -1, -1, OpTypes::i32hi16, 
1470
    -1, -1, OpTypes::i32lo16z, 
1471
    -1, -1, -1, OpTypes::i32imm, 
1472
    -1, -1, OpTypes::i32hi16, 
1473
    -1, -1, OpTypes::i32lo16z, 
1474
    -1, -1, -1, OpTypes::i32imm, 
1475
    -1, -1, OpTypes::i32hi16, 
1476
    -1, -1, OpTypes::i32lo16z, 
1477
    -1, -1, -1, OpTypes::i32imm, 
1478
    -1, -1, OpTypes::i32hi16, 
1479
    -1, -1, OpTypes::i32lo16z, 
1480
    -1, -1, -1, OpTypes::i32imm, 
1481
    -1, -1, OpTypes::i32hi16and, 
1482
    -1, -1, OpTypes::i32lo16and, 
1483
    -1, -1, -1, OpTypes::i32imm, 
1484
    -1, -1, OpTypes::i32hi16and, 
1485
    -1, -1, OpTypes::i32lo16and, 
1486
    -1, -1, -1, OpTypes::i32imm, 
1487
    OpTypes::BrTarget, OpTypes::CCOp, 
1488
    -1, OpTypes::CCOp, 
1489
    -1, -1, OpTypes::CCOp, 
1490
    OpTypes::i16imm, OpTypes::CCOp, 
1491
    OpTypes::BrTarget, 
1492
    -1, 
1493
    -1, OpTypes::i32lo21, 
1494
    -1, -1, OpTypes::imm10, OpTypes::AluOp, 
1495
    -1, -1, -1, OpTypes::AluOp, 
1496
    -1, -1, OpTypes::imm10, OpTypes::AluOp, 
1497
    -1, -1, -1, OpTypes::AluOp, 
1498
    -1, -1, OpTypes::imm10, OpTypes::AluOp, 
1499
    -1, -1, -1, OpTypes::AluOp, 
1500
    -1, -1, OpTypes::imm10, OpTypes::AluOp, 
1501
    -1, -1, -1, OpTypes::AluOp, 
1502
    -1, -1, OpTypes::i32lo16s, OpTypes::AluOp, 
1503
    -1, -1, -1, OpTypes::AluOp, 
1504
    -1, -1, -1, OpTypes::AluOp, 
1505
    -1, -1, 
1506
    /**/
1507
    /**/
1508
    /**/
1509
    /**/
1510
    /**/
1511
    -1, OpTypes::i32hi16, 
1512
    /**/
1513
    -1, -1, OpTypes::i32hi16, 
1514
    -1, -1, OpTypes::i32lo16z, 
1515
    -1, -1, -1, OpTypes::i32imm, 
1516
    -1, -1, OpTypes::i32hi16, 
1517
    -1, -1, OpTypes::i32lo16z, 
1518
    -1, -1, -1, OpTypes::i32imm, 
1519
    -1, -1, 
1520
    /**/
1521
    -1, -1, OpTypes::immShift, 
1522
    -1, -1, OpTypes::immShift, 
1523
    -1, OpTypes::CCOp, 
1524
    -1, -1, -1, OpTypes::CCOp, 
1525
    -1, OpTypes::i32hi16, 
1526
    -1, OpTypes::i32lo16z, 
1527
    -1, -1, 
1528
    -1, -1, -1, OpTypes::i32imm, 
1529
    -1, -1, -1, OpTypes::i32imm, 
1530
    -1, OpTypes::i32lo21, 
1531
    -1, -1, OpTypes::immShift, 
1532
    -1, -1, OpTypes::immShift, 
1533
    -1, -1, -1, OpTypes::i32imm, 
1534
    -1, -1, -1, OpTypes::i32imm, 
1535
    -1, -1, -1, OpTypes::i32imm, 
1536
    -1, -1, -1, OpTypes::i32imm, 
1537
    -1, OpTypes::i32lo21, 
1538
    -1, -1, OpTypes::imm10, OpTypes::AluOp, 
1539
    -1, -1, -1, OpTypes::AluOp, 
1540
    -1, -1, OpTypes::imm10, OpTypes::AluOp, 
1541
    -1, -1, -1, OpTypes::AluOp, 
1542
    -1, -1, OpTypes::i32hi16, 
1543
    -1, -1, OpTypes::i32lo16z, 
1544
    -1, -1, -1, OpTypes::i32imm, 
1545
    -1, -1, OpTypes::i32hi16, 
1546
    -1, -1, OpTypes::i32lo16z, 
1547
    -1, -1, -1, OpTypes::i32imm, 
1548
    -1, -1, OpTypes::i32hi16, 
1549
    -1, -1, OpTypes::i32lo16z, 
1550
    -1, -1, -1, OpTypes::i32imm, 
1551
    -1, -1, OpTypes::i32hi16, 
1552
    -1, -1, OpTypes::i32lo16z, 
1553
    -1, -1, -1, OpTypes::i32imm, 
1554
    -1, -1, OpTypes::i32lo16s, OpTypes::AluOp, 
1555
    -1, -1, -1, OpTypes::AluOp, 
1556
    -1, -1, 
1557
    -1, -1, OpTypes::i32hi16, 
1558
    -1, -1, OpTypes::i32lo16z, 
1559
    -1, -1, -1, OpTypes::i32imm, 
1560
    -1, -1, OpTypes::i32hi16, 
1561
    -1, -1, OpTypes::i32lo16z, 
1562
    -1, -1, -1, OpTypes::i32imm, 
1563
  };
1564
  return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
1565
}
1566
} // end namespace Lanai
1567
} // end namespace llvm
1568
#endif //GET_INSTRINFO_OPERAND_TYPE
1569
1570
#ifdef GET_INSTRMAP_INFO
1571
#undef GET_INSTRMAP_INFO
1572
namespace llvm {
1573
1574
namespace Lanai {
1575
1576
enum PostEncoderMethod {
1577
  PostEncoderMethod_adjustPqBitsSpls
1578
};
1579
1580
// splsIdempotent
1581
LLVM_READONLY
1582
128
int splsIdempotent(uint16_t Opcode) {
1583
128
static const uint16_t splsIdempotentTable[][2] = {
1584
128
  { Lanai::LDBs_RI, Lanai::LDBs_RI },
1585
128
  { Lanai::LDBz_RI, Lanai::LDBz_RI },
1586
128
  { Lanai::LDHs_RI, Lanai::LDHs_RI },
1587
128
  { Lanai::LDHz_RI, Lanai::LDHz_RI },
1588
128
  { Lanai::STB_RI, Lanai::STB_RI },
1589
128
  { Lanai::STH_RI, Lanai::STH_RI },
1590
128
}; // End of splsIdempotentTable
1591
128
1592
128
  unsigned mid;
1593
128
  unsigned start = 0;
1594
128
  unsigned end = 6;
1595
488
  while (start < end) {
1596
368
    mid = start + (end - start)/2;
1597
368
    if (Opcode == splsIdempotentTable[mid][0]) {
1598
8
      break;
1599
8
    }
1600
360
    if (Opcode < splsIdempotentTable[mid][0])
1601
232
      end = mid;
1602
128
    else
1603
128
      start = mid + 1;
1604
360
  }
1605
128
  if (start == end)
1606
120
    return -1; // Instruction doesn't exist in this table.
1607
8
1608
8
  return splsIdempotentTable[mid][1];
1609
8
}
1610
1611
} // End Lanai namespace
1612
} // End llvm namespace
1613
#endif // GET_INSTRMAP_INFO
1614