Coverage Report

Created: 2019-05-22 02:55

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Lanai/LanaiGenInstrInfo.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Target Instruction Enum Values and Descriptors                             *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_INSTRINFO_ENUM
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#undef GET_INSTRINFO_ENUM
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namespace llvm {
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namespace Lanai {
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  enum {
15
    PHI = 0,
16
    INLINEASM = 1,
17
    INLINEASM_BR  = 2,
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    CFI_INSTRUCTION = 3,
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    EH_LABEL  = 4,
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    GC_LABEL  = 5,
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    ANNOTATION_LABEL  = 6,
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    KILL  = 7,
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    EXTRACT_SUBREG  = 8,
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    INSERT_SUBREG = 9,
25
    IMPLICIT_DEF  = 10,
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    SUBREG_TO_REG = 11,
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    COPY_TO_REGCLASS  = 12,
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    DBG_VALUE = 13,
29
    DBG_LABEL = 14,
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    REG_SEQUENCE  = 15,
31
    COPY  = 16,
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    BUNDLE  = 17,
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    LIFETIME_START  = 18,
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    LIFETIME_END  = 19,
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    STACKMAP  = 20,
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    FENTRY_CALL = 21,
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    PATCHPOINT  = 22,
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    LOAD_STACK_GUARD  = 23,
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    STATEPOINT  = 24,
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    LOCAL_ESCAPE  = 25,
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    FAULTING_OP = 26,
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    PATCHABLE_OP  = 27,
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    PATCHABLE_FUNCTION_ENTER  = 28,
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    PATCHABLE_RET = 29,
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    PATCHABLE_FUNCTION_EXIT = 30,
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    PATCHABLE_TAIL_CALL = 31,
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    PATCHABLE_EVENT_CALL  = 32,
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    PATCHABLE_TYPED_EVENT_CALL  = 33,
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    ICALL_BRANCH_FUNNEL = 34,
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    G_ADD = 35,
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    G_SUB = 36,
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    G_MUL = 37,
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    G_SDIV  = 38,
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    G_UDIV  = 39,
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    G_SREM  = 40,
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    G_UREM  = 41,
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    G_AND = 42,
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    G_OR  = 43,
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    G_XOR = 44,
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    G_IMPLICIT_DEF  = 45,
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    G_PHI = 46,
62
    G_FRAME_INDEX = 47,
63
    G_GLOBAL_VALUE  = 48,
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    G_EXTRACT = 49,
65
    G_UNMERGE_VALUES  = 50,
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    G_INSERT  = 51,
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    G_MERGE_VALUES  = 52,
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    G_BUILD_VECTOR  = 53,
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    G_BUILD_VECTOR_TRUNC  = 54,
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    G_CONCAT_VECTORS  = 55,
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    G_PTRTOINT  = 56,
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    G_INTTOPTR  = 57,
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    G_BITCAST = 58,
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    G_INTRINSIC_TRUNC = 59,
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    G_INTRINSIC_ROUND = 60,
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    G_LOAD  = 61,
77
    G_SEXTLOAD  = 62,
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    G_ZEXTLOAD  = 63,
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    G_STORE = 64,
80
    G_ATOMIC_CMPXCHG_WITH_SUCCESS = 65,
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    G_ATOMIC_CMPXCHG  = 66,
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    G_ATOMICRMW_XCHG  = 67,
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    G_ATOMICRMW_ADD = 68,
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    G_ATOMICRMW_SUB = 69,
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    G_ATOMICRMW_AND = 70,
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    G_ATOMICRMW_NAND  = 71,
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    G_ATOMICRMW_OR  = 72,
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    G_ATOMICRMW_XOR = 73,
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    G_ATOMICRMW_MAX = 74,
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    G_ATOMICRMW_MIN = 75,
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    G_ATOMICRMW_UMAX  = 76,
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    G_ATOMICRMW_UMIN  = 77,
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    G_BRCOND  = 78,
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    G_BRINDIRECT  = 79,
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    G_INTRINSIC = 80,
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    G_INTRINSIC_W_SIDE_EFFECTS  = 81,
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    G_ANYEXT  = 82,
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    G_TRUNC = 83,
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    G_CONSTANT  = 84,
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    G_FCONSTANT = 85,
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    G_VASTART = 86,
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    G_VAARG = 87,
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    G_SEXT  = 88,
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    G_ZEXT  = 89,
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    G_SHL = 90,
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    G_LSHR  = 91,
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    G_ASHR  = 92,
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    G_ICMP  = 93,
109
    G_FCMP  = 94,
110
    G_SELECT  = 95,
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    G_UADDO = 96,
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    G_UADDE = 97,
113
    G_USUBO = 98,
114
    G_USUBE = 99,
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    G_SADDO = 100,
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    G_SADDE = 101,
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    G_SSUBO = 102,
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    G_SSUBE = 103,
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    G_UMULO = 104,
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    G_SMULO = 105,
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    G_UMULH = 106,
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    G_SMULH = 107,
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    G_FADD  = 108,
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    G_FSUB  = 109,
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    G_FMUL  = 110,
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    G_FMA = 111,
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    G_FDIV  = 112,
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    G_FREM  = 113,
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    G_FPOW  = 114,
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    G_FEXP  = 115,
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    G_FEXP2 = 116,
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    G_FLOG  = 117,
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    G_FLOG2 = 118,
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    G_FLOG10  = 119,
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    G_FNEG  = 120,
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    G_FPEXT = 121,
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    G_FPTRUNC = 122,
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    G_FPTOSI  = 123,
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    G_FPTOUI  = 124,
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    G_SITOFP  = 125,
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    G_UITOFP  = 126,
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    G_FABS  = 127,
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    G_FCOPYSIGN = 128,
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    G_FCANONICALIZE = 129,
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    G_GEP = 130,
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    G_PTR_MASK  = 131,
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    G_SMIN  = 132,
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    G_SMAX  = 133,
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    G_UMIN  = 134,
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    G_UMAX  = 135,
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    G_BR  = 136,
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    G_INSERT_VECTOR_ELT = 137,
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    G_EXTRACT_VECTOR_ELT  = 138,
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    G_SHUFFLE_VECTOR  = 139,
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    G_CTTZ  = 140,
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    G_CTTZ_ZERO_UNDEF = 141,
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    G_CTLZ  = 142,
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    G_CTLZ_ZERO_UNDEF = 143,
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    G_CTPOP = 144,
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    G_BSWAP = 145,
161
    G_FCEIL = 146,
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    G_FCOS  = 147,
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    G_FSIN  = 148,
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    G_FSQRT = 149,
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    G_FFLOOR  = 150,
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    G_FRINT = 151,
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    G_FNEARBYINT  = 152,
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    G_ADDRSPACE_CAST  = 153,
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    G_BLOCK_ADDR  = 154,
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    ADJCALLSTACKDOWN  = 155,
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    ADJCALLSTACKUP  = 156,
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    ADJDYNALLOC = 157,
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    CALL  = 158,
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    CALLR = 159,
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    ADDC_F_I_HI = 160,
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    ADDC_F_I_LO = 161,
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    ADDC_F_R  = 162,
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    ADDC_I_HI = 163,
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    ADDC_I_LO = 164,
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    ADDC_R  = 165,
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    ADD_F_I_HI  = 166,
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    ADD_F_I_LO  = 167,
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    ADD_F_R = 168,
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    ADD_I_HI  = 169,
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    ADD_I_LO  = 170,
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    ADD_R = 171,
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    AND_F_I_HI  = 172,
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    AND_F_I_LO  = 173,
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    AND_F_R = 174,
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    AND_I_HI  = 175,
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    AND_I_LO  = 176,
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    AND_R = 177,
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    BRCC  = 178,
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    BRIND_CC  = 179,
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    BRIND_CCA = 180,
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    BRR = 181,
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    BT  = 182,
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    JR  = 183,
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    LDADDR  = 184,
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    LDBs_RI = 185,
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    LDBs_RR = 186,
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    LDBz_RI = 187,
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    LDBz_RR = 188,
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    LDHs_RI = 189,
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    LDHs_RR = 190,
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    LDHz_RI = 191,
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    LDHz_RR = 192,
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    LDW_RI  = 193,
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    LDW_RR  = 194,
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    LDWz_RR = 195,
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    LEADZ = 196,
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    LOG0  = 197,
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    LOG1  = 198,
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    LOG2  = 199,
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    LOG3  = 200,
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    LOG4  = 201,
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    MOVHI = 202,
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    NOP = 203,
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    OR_F_I_HI = 204,
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    OR_F_I_LO = 205,
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    OR_F_R  = 206,
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    OR_I_HI = 207,
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    OR_I_LO = 208,
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    OR_R  = 209,
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    POPC  = 210,
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    RET = 211,
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    SA_F_I  = 212,
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    SA_I  = 213,
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    SCC = 214,
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    SELECT  = 215,
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    SFSUB_F_RI_HI = 216,
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    SFSUB_F_RI_LO = 217,
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    SFSUB_F_RR  = 218,
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    SHL_F_R = 219,
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    SHL_R = 220,
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    SLI = 221,
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    SL_F_I  = 222,
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    SL_I  = 223,
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    SRA_F_R = 224,
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    SRA_R = 225,
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    SRL_F_R = 226,
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    SRL_R = 227,
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    STADDR  = 228,
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    STB_RI  = 229,
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    STB_RR  = 230,
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    STH_RI  = 231,
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    STH_RR  = 232,
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    SUBB_F_I_HI = 233,
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    SUBB_F_I_LO = 234,
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    SUBB_F_R  = 235,
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    SUBB_I_HI = 236,
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    SUBB_I_LO = 237,
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    SUBB_R  = 238,
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    SUB_F_I_HI  = 239,
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    SUB_F_I_LO  = 240,
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    SUB_F_R = 241,
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    SUB_I_HI  = 242,
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    SUB_I_LO  = 243,
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    SUB_R = 244,
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    SW_RI = 245,
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    SW_RR = 246,
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    TRAILZ  = 247,
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    XOR_F_I_HI  = 248,
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    XOR_F_I_LO  = 249,
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    XOR_F_R = 250,
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    XOR_I_HI  = 251,
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    XOR_I_LO  = 252,
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    XOR_R = 253,
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    INSTRUCTION_LIST_END = 254
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  };
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} // end Lanai namespace
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} // end llvm namespace
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#endif // GET_INSTRINFO_ENUM
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#ifdef GET_INSTRINFO_SCHED_ENUM
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#undef GET_INSTRINFO_SCHED_ENUM
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namespace llvm {
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namespace Lanai {
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namespace Sched {
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  enum {
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    NoInstrModel  = 0,
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    IIC_ALU_WriteALU  = 1,
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    IIC_ALU = 2,
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    IIC_LD_WriteLD  = 3,
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    IIC_LDSW_WriteLDSW  = 4,
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    WriteLD = 5,
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    IIC_ST_WriteST  = 6,
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    IIC_STSW_WriteSTSW  = 7,
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    SCHED_LIST_END = 8
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  };
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} // end Sched namespace
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} // end Lanai namespace
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} // end llvm namespace
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#endif // GET_INSTRINFO_SCHED_ENUM
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#ifdef GET_INSTRINFO_MC_DESC
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#undef GET_INSTRINFO_MC_DESC
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namespace llvm {
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static const MCPhysReg ImplicitList1[] = { Lanai::SP, 0 };
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static const MCPhysReg ImplicitList2[] = { Lanai::RCA, 0 };
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static const MCPhysReg ImplicitList3[] = { Lanai::SR, 0 };
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static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
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static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
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static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
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static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
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static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
325
static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
326
static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
327
static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
328
static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
329
static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
330
static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
331
static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
332
static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
333
static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
334
static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
335
static const MCOperandInfo OperandInfo31[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
336
static const MCOperandInfo OperandInfo32[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
337
static const MCOperandInfo OperandInfo33[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
338
static const MCOperandInfo OperandInfo34[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
339
static const MCOperandInfo OperandInfo35[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
340
static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
341
static const MCOperandInfo OperandInfo37[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
342
static const MCOperandInfo OperandInfo38[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
343
static const MCOperandInfo OperandInfo39[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
344
345
extern const MCInstrDesc LanaiInsts[] = {
346
  { 0,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
347
  { 1,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
348
  { 2,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2 = INLINEASM_BR
349
  { 3,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = CFI_INSTRUCTION
350
  { 4,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = EH_LABEL
351
  { 5,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = GC_LABEL
352
  { 6,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #6 = ANNOTATION_LABEL
353
  { 7,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #7 = KILL
354
  { 8,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #8 = EXTRACT_SUBREG
355
  { 9,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #9 = INSERT_SUBREG
356
  { 10, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #10 = IMPLICIT_DEF
357
  { 11, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #11 = SUBREG_TO_REG
358
  { 12, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #12 = COPY_TO_REGCLASS
359
  { 13, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #13 = DBG_VALUE
360
  { 14, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #14 = DBG_LABEL
361
  { 15, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #15 = REG_SEQUENCE
362
  { 16, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #16 = COPY
363
  { 17, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #17 = BUNDLE
364
  { 18, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #18 = LIFETIME_START
365
  { 19, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #19 = LIFETIME_END
366
  { 20, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #20 = STACKMAP
367
  { 21, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #21 = FENTRY_CALL
368
  { 22, 6,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #22 = PATCHPOINT
369
  { 23, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #23 = LOAD_STACK_GUARD
370
  { 24, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #24 = STATEPOINT
371
  { 25, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #25 = LOCAL_ESCAPE
372
  { 26, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #26 = FAULTING_OP
373
  { 27, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #27 = PATCHABLE_OP
374
  { 28, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #28 = PATCHABLE_FUNCTION_ENTER
375
  { 29, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #29 = PATCHABLE_RET
376
  { 30, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #30 = PATCHABLE_FUNCTION_EXIT
377
  { 31, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #31 = PATCHABLE_TAIL_CALL
378
  { 32, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #32 = PATCHABLE_EVENT_CALL
379
  { 33, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
380
  { 34, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #34 = ICALL_BRANCH_FUNNEL
381
  { 35, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #35 = G_ADD
382
  { 36, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #36 = G_SUB
383
  { 37, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #37 = G_MUL
384
  { 38, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #38 = G_SDIV
385
  { 39, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #39 = G_UDIV
386
  { 40, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #40 = G_SREM
387
  { 41, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_UREM
388
  { 42, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_AND
389
  { 43, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #43 = G_OR
390
  { 44, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #44 = G_XOR
391
  { 45, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #45 = G_IMPLICIT_DEF
392
  { 46, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #46 = G_PHI
393
  { 47, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #47 = G_FRAME_INDEX
394
  { 48, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #48 = G_GLOBAL_VALUE
395
  { 49, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #49 = G_EXTRACT
396
  { 50, 2,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #50 = G_UNMERGE_VALUES
397
  { 51, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #51 = G_INSERT
398
  { 52, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #52 = G_MERGE_VALUES
399
  { 53, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = G_BUILD_VECTOR
400
  { 54, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #54 = G_BUILD_VECTOR_TRUNC
401
  { 55, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #55 = G_CONCAT_VECTORS
402
  { 56, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #56 = G_PTRTOINT
403
  { 57, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #57 = G_INTTOPTR
404
  { 58, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #58 = G_BITCAST
405
  { 59, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #59 = G_INTRINSIC_TRUNC
406
  { 60, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #60 = G_INTRINSIC_ROUND
407
  { 61, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #61 = G_LOAD
408
  { 62, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #62 = G_SEXTLOAD
409
  { 63, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #63 = G_ZEXTLOAD
410
  { 64, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #64 = G_STORE
411
  { 65, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #65 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
412
  { 66, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #66 = G_ATOMIC_CMPXCHG
413
  { 67, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #67 = G_ATOMICRMW_XCHG
414
  { 68, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #68 = G_ATOMICRMW_ADD
415
  { 69, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #69 = G_ATOMICRMW_SUB
416
  { 70, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #70 = G_ATOMICRMW_AND
417
  { 71, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #71 = G_ATOMICRMW_NAND
418
  { 72, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #72 = G_ATOMICRMW_OR
419
  { 73, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #73 = G_ATOMICRMW_XOR
420
  { 74, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #74 = G_ATOMICRMW_MAX
421
  { 75, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #75 = G_ATOMICRMW_MIN
422
  { 76, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #76 = G_ATOMICRMW_UMAX
423
  { 77, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #77 = G_ATOMICRMW_UMIN
424
  { 78, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #78 = G_BRCOND
425
  { 79, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #79 = G_BRINDIRECT
426
  { 80, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #80 = G_INTRINSIC
427
  { 81, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #81 = G_INTRINSIC_W_SIDE_EFFECTS
428
  { 82, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #82 = G_ANYEXT
429
  { 83, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #83 = G_TRUNC
430
  { 84, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #84 = G_CONSTANT
431
  { 85, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #85 = G_FCONSTANT
432
  { 86, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #86 = G_VASTART
433
  { 87, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #87 = G_VAARG
434
  { 88, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #88 = G_SEXT
435
  { 89, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #89 = G_ZEXT
436
  { 90, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #90 = G_SHL
437
  { 91, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #91 = G_LSHR
438
  { 92, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #92 = G_ASHR
439
  { 93, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #93 = G_ICMP
440
  { 94, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #94 = G_FCMP
441
  { 95, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #95 = G_SELECT
442
  { 96, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #96 = G_UADDO
443
  { 97, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #97 = G_UADDE
444
  { 98, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #98 = G_USUBO
445
  { 99, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #99 = G_USUBE
446
  { 100,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #100 = G_SADDO
447
  { 101,  5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #101 = G_SADDE
448
  { 102,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #102 = G_SSUBO
449
  { 103,  5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #103 = G_SSUBE
450
  { 104,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #104 = G_UMULO
451
  { 105,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #105 = G_SMULO
452
  { 106,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #106 = G_UMULH
453
  { 107,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #107 = G_SMULH
454
  { 108,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #108 = G_FADD
455
  { 109,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #109 = G_FSUB
456
  { 110,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #110 = G_FMUL
457
  { 111,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #111 = G_FMA
458
  { 112,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #112 = G_FDIV
459
  { 113,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #113 = G_FREM
460
  { 114,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #114 = G_FPOW
461
  { 115,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #115 = G_FEXP
462
  { 116,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #116 = G_FEXP2
463
  { 117,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #117 = G_FLOG
464
  { 118,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #118 = G_FLOG2
465
  { 119,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #119 = G_FLOG10
466
  { 120,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #120 = G_FNEG
467
  { 121,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #121 = G_FPEXT
468
  { 122,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #122 = G_FPTRUNC
469
  { 123,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #123 = G_FPTOSI
470
  { 124,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #124 = G_FPTOUI
471
  { 125,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #125 = G_SITOFP
472
  { 126,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #126 = G_UITOFP
473
  { 127,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #127 = G_FABS
474
  { 128,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #128 = G_FCOPYSIGN
475
  { 129,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #129 = G_FCANONICALIZE
476
  { 130,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #130 = G_GEP
477
  { 131,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #131 = G_PTR_MASK
478
  { 132,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #132 = G_SMIN
479
  { 133,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #133 = G_SMAX
480
  { 134,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #134 = G_UMIN
481
  { 135,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #135 = G_UMAX
482
  { 136,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #136 = G_BR
483
  { 137,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #137 = G_INSERT_VECTOR_ELT
484
  { 138,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #138 = G_EXTRACT_VECTOR_ELT
485
  { 139,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #139 = G_SHUFFLE_VECTOR
486
  { 140,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #140 = G_CTTZ
487
  { 141,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #141 = G_CTTZ_ZERO_UNDEF
488
  { 142,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #142 = G_CTLZ
489
  { 143,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #143 = G_CTLZ_ZERO_UNDEF
490
  { 144,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #144 = G_CTPOP
491
  { 145,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #145 = G_BSWAP
492
  { 146,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #146 = G_FCEIL
493
  { 147,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #147 = G_FCOS
494
  { 148,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #148 = G_FSIN
495
  { 149,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #149 = G_FSQRT
496
  { 150,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #150 = G_FFLOOR
497
  { 151,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #151 = G_FRINT
498
  { 152,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #152 = G_FNEARBYINT
499
  { 153,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #153 = G_ADDRSPACE_CAST
500
  { 154,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #154 = G_BLOCK_ADDR
501
  { 155,  2,  0,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr },  // Inst #155 = ADJCALLSTACKDOWN
502
  { 156,  2,  0,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr },  // Inst #156 = ADJCALLSTACKUP
503
  { 157,  2,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #157 = ADJDYNALLOC
504
  { 158,  1,  0,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo2, -1 ,nullptr },  // Inst #158 = CALL
505
  { 159,  1,  0,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo32, -1 ,nullptr },  // Inst #159 = CALLR
506
  { 160,  3,  1,  4,  1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #160 = ADDC_F_I_HI
507
  { 161,  3,  1,  4,  1,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #161 = ADDC_F_I_LO
508
  { 162,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #162 = ADDC_F_R
509
  { 163,  3,  1,  4,  1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #163 = ADDC_I_HI
510
  { 164,  3,  1,  4,  1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #164 = ADDC_I_LO
511
  { 165,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #165 = ADDC_R
512
  { 166,  3,  1,  4,  1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #166 = ADD_F_I_HI
513
  { 167,  3,  1,  4,  1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #167 = ADD_F_I_LO
514
  { 168,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #168 = ADD_F_R
515
  { 169,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #169 = ADD_I_HI
516
  { 170,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #170 = ADD_I_LO
517
  { 171,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #171 = ADD_R
518
  { 172,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #172 = AND_F_I_HI
519
  { 173,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #173 = AND_F_I_LO
520
  { 174,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #174 = AND_F_R
521
  { 175,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #175 = AND_I_HI
522
  { 176,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #176 = AND_I_LO
523
  { 177,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #177 = AND_R
524
  { 178,  2,  0,  4,  2,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #178 = BRCC
525
  { 179,  2,  0,  4,  1,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #179 = BRIND_CC
526
  { 180,  3,  0,  4,  1,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #180 = BRIND_CCA
527
  { 181,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #181 = BRR
528
  { 182,  1,  0,  4,  2,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #182 = BT
529
  { 183,  1,  0,  4,  1,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #183 = JR
530
  { 184,  2,  1,  4,  3,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #184 = LDADDR
531
  { 185,  4,  1,  4,  4,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #185 = LDBs_RI
532
  { 186,  4,  1,  4,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #186 = LDBs_RR
533
  { 187,  4,  1,  4,  4,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #187 = LDBz_RI
534
  { 188,  4,  1,  4,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #188 = LDBz_RR
535
  { 189,  4,  1,  4,  4,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #189 = LDHs_RI
536
  { 190,  4,  1,  4,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #190 = LDHs_RR
537
  { 191,  4,  1,  4,  4,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #191 = LDHz_RI
538
  { 192,  4,  1,  4,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #192 = LDHz_RR
539
  { 193,  4,  1,  4,  3,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #193 = LDW_RI
540
  { 194,  4,  1,  4,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #194 = LDW_RR
541
  { 195,  4,  1,  4,  5,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #195 = LDWz_RR
542
  { 196,  2,  1,  4,  1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #196 = LEADZ
543
  { 197,  0,  0,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #197 = LOG0
544
  { 198,  0,  0,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #198 = LOG1
545
  { 199,  0,  0,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #199 = LOG2
546
  { 200,  0,  0,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #200 = LOG3
547
  { 201,  0,  0,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #201 = LOG4
548
  { 202,  2,  1,  4,  1,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #202 = MOVHI
549
  { 203,  0,  0,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #203 = NOP
550
  { 204,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #204 = OR_F_I_HI
551
  { 205,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #205 = OR_F_I_LO
552
  { 206,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #206 = OR_F_R
553
  { 207,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #207 = OR_I_HI
554
  { 208,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #208 = OR_I_LO
555
  { 209,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #209 = OR_R
556
  { 210,  2,  1,  4,  1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #210 = POPC
557
  { 211,  0,  0,  4,  0,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, nullptr, nullptr, -1 ,nullptr },  // Inst #211 = RET
558
  { 212,  3,  1,  4,  1,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #212 = SA_F_I
559
  { 213,  3,  1,  4,  1,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #213 = SA_I
560
  { 214,  2,  1,  4,  2,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #214 = SCC
561
  { 215,  4,  1,  4,  1,  0|(1ULL<<MCID::Select)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #215 = SELECT
562
  { 216,  2,  0,  4,  1,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo35, -1 ,nullptr },  // Inst #216 = SFSUB_F_RI_HI
563
  { 217,  2,  0,  4,  1,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo35, -1 ,nullptr },  // Inst #217 = SFSUB_F_RI_LO
564
  { 218,  2,  0,  4,  1,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo31, -1 ,nullptr },  // Inst #218 = SFSUB_F_RR
565
  { 219,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #219 = SHL_F_R
566
  { 220,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #220 = SHL_R
567
  { 221,  2,  1,  4,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #221 = SLI
568
  { 222,  3,  1,  4,  1,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #222 = SL_F_I
569
  { 223,  3,  1,  4,  1,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #223 = SL_I
570
  { 224,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #224 = SRA_F_R
571
  { 225,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #225 = SRA_R
572
  { 226,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #226 = SRL_F_R
573
  { 227,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #227 = SRL_R
574
  { 228,  2,  0,  4,  6,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #228 = STADDR
575
  { 229,  4,  0,  4,  7,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #229 = STB_RI
576
  { 230,  4,  0,  4,  6,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #230 = STB_RR
577
  { 231,  4,  0,  4,  7,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #231 = STH_RI
578
  { 232,  4,  0,  4,  6,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #232 = STH_RR
579
  { 233,  3,  1,  4,  1,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #233 = SUBB_F_I_HI
580
  { 234,  3,  1,  4,  1,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #234 = SUBB_F_I_LO
581
  { 235,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #235 = SUBB_F_R
582
  { 236,  3,  1,  4,  1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #236 = SUBB_I_HI
583
  { 237,  3,  1,  4,  1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #237 = SUBB_I_LO
584
  { 238,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #238 = SUBB_R
585
  { 239,  3,  1,  4,  1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #239 = SUB_F_I_HI
586
  { 240,  3,  1,  4,  1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #240 = SUB_F_I_LO
587
  { 241,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #241 = SUB_F_R
588
  { 242,  3,  1,  4,  1,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #242 = SUB_I_HI
589
  { 243,  3,  1,  4,  1,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #243 = SUB_I_LO
590
  { 244,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #244 = SUB_R
591
  { 245,  4,  0,  4,  6,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #245 = SW_RI
592
  { 246,  4,  0,  4,  6,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #246 = SW_RR
593
  { 247,  2,  1,  4,  1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #247 = TRAILZ
594
  { 248,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #248 = XOR_F_I_HI
595
  { 249,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr },  // Inst #249 = XOR_F_I_LO
596
  { 250,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr },  // Inst #250 = XOR_F_R
597
  { 251,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #251 = XOR_I_HI
598
  { 252,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #252 = XOR_I_LO
599
  { 253,  4,  1,  4,  1,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #253 = XOR_R
600
};
601
602
extern const char LanaiInstrNameData[] = {
603
  /* 0 */ 'G', '_', 'F', 'L', 'O', 'G', '1', '0', 0,
604
  /* 9 */ 'L', 'O', 'G', '0', 0,
605
  /* 14 */ 'L', 'O', 'G', '1', 0,
606
  /* 19 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0,
607
  /* 27 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0,
608
  /* 35 */ 'L', 'O', 'G', '3', 0,
609
  /* 40 */ 'L', 'O', 'G', '4', 0,
610
  /* 45 */ 'B', 'R', 'I', 'N', 'D', '_', 'C', 'C', 'A', 0,
611
  /* 55 */ 'G', '_', 'F', 'M', 'A', 0,
612
  /* 61 */ 'G', '_', 'F', 'S', 'U', 'B', 0,
613
  /* 68 */ 'G', '_', 'S', 'U', 'B', 0,
614
  /* 74 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'S', 'U', 'B', 0,
615
  /* 90 */ 'B', 'R', 'C', 'C', 0,
616
  /* 95 */ 'S', 'C', 'C', 0,
617
  /* 99 */ 'B', 'R', 'I', 'N', 'D', '_', 'C', 'C', 0,
618
  /* 108 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', 0,
619
  /* 120 */ 'G', '_', 'F', 'P', 'T', 'R', 'U', 'N', 'C', 0,
620
  /* 130 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'T', 'R', 'U', 'N', 'C', 0,
621
  /* 148 */ 'G', '_', 'T', 'R', 'U', 'N', 'C', 0,
622
  /* 156 */ 'G', '_', 'B', 'U', 'I', 'L', 'D', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'T', 'R', 'U', 'N', 'C', 0,
623
  /* 177 */ 'A', 'D', 'J', 'D', 'Y', 'N', 'A', 'L', 'L', 'O', 'C', 0,
624
  /* 189 */ 'P', 'O', 'P', 'C', 0,
625
  /* 194 */ 'G', '_', 'S', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
626
  /* 205 */ 'G', '_', 'Z', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
627
  /* 216 */ 'G', '_', 'L', 'O', 'A', 'D', 0,
628
  /* 223 */ 'G', '_', 'F', 'A', 'D', 'D', 0,
629
  /* 230 */ 'G', '_', 'A', 'D', 'D', 0,
630
  /* 236 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'D', 'D', 0,
631
  /* 252 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'N', 'A', 'N', 'D', 0,
632
  /* 269 */ 'G', '_', 'A', 'N', 'D', 0,
633
  /* 275 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'N', 'D', 0,
634
  /* 291 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
635
  /* 304 */ 'G', '_', 'B', 'R', 'C', 'O', 'N', 'D', 0,
636
  /* 313 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'R', 'O', 'U', 'N', 'D', 0,
637
  /* 331 */ 'L', 'O', 'A', 'D', '_', 'S', 'T', 'A', 'C', 'K', '_', 'G', 'U', 'A', 'R', 'D', 0,
638
  /* 348 */ 'G', '_', 'S', 'S', 'U', 'B', 'E', 0,
639
  /* 356 */ 'G', '_', 'U', 'S', 'U', 'B', 'E', 0,
640
  /* 364 */ 'R', 'E', 'G', '_', 'S', 'E', 'Q', 'U', 'E', 'N', 'C', 'E', 0,
641
  /* 377 */ 'G', '_', 'S', 'A', 'D', 'D', 'E', 0,
642
  /* 385 */ 'G', '_', 'U', 'A', 'D', 'D', 'E', 0,
643
  /* 393 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
644
  /* 400 */ 'L', 'O', 'C', 'A', 'L', '_', 'E', 'S', 'C', 'A', 'P', 'E', 0,
645
  /* 413 */ 'G', '_', 'S', 'T', 'O', 'R', 'E', 0,
646
  /* 421 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
647
  /* 431 */ 'G', '_', 'G', 'L', 'O', 'B', 'A', 'L', '_', 'V', 'A', 'L', 'U', 'E', 0,
648
  /* 446 */ 'G', '_', 'F', 'C', 'A', 'N', 'O', 'N', 'I', 'C', 'A', 'L', 'I', 'Z', 'E', 0,
649
  /* 462 */ 'G', '_', 'C', 'T', 'L', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
650
  /* 480 */ 'G', '_', 'C', 'T', 'T', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
651
  /* 498 */ 'G', '_', 'I', 'M', 'P', 'L', 'I', 'C', 'I', 'T', '_', 'D', 'E', 'F', 0,
652
  /* 513 */ 'G', '_', 'F', 'N', 'E', 'G', 0,
653
  /* 520 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
654
  /* 535 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
655
  /* 549 */ 'S', 'U', 'B', 'R', 'E', 'G', '_', 'T', 'O', '_', 'R', 'E', 'G', 0,
656
  /* 563 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', 0,
657
  /* 580 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'C', 'H', 'G', 0,
658
  /* 597 */ 'G', '_', 'F', 'L', 'O', 'G', 0,
659
  /* 604 */ 'G', '_', 'V', 'A', 'A', 'R', 'G', 0,
660
  /* 612 */ 'G', '_', 'S', 'M', 'U', 'L', 'H', 0,
661
  /* 620 */ 'G', '_', 'U', 'M', 'U', 'L', 'H', 0,
662
  /* 628 */ 'G', '_', 'P', 'H', 'I', 0,
663
  /* 634 */ 'M', 'O', 'V', 'H', 'I', 0,
664
  /* 640 */ 'S', 'F', 'S', 'U', 'B', '_', 'F', '_', 'R', 'I', '_', 'H', 'I', 0,
665
  /* 654 */ 'S', 'U', 'B', 'B', '_', 'I', '_', 'H', 'I', 0,
666
  /* 664 */ 'S', 'U', 'B', '_', 'I', '_', 'H', 'I', 0,
667
  /* 673 */ 'A', 'D', 'D', 'C', '_', 'I', '_', 'H', 'I', 0,
668
  /* 683 */ 'A', 'D', 'D', '_', 'I', '_', 'H', 'I', 0,
669
  /* 692 */ 'A', 'N', 'D', '_', 'I', '_', 'H', 'I', 0,
670
  /* 701 */ 'S', 'U', 'B', 'B', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
671
  /* 713 */ 'S', 'U', 'B', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
672
  /* 724 */ 'A', 'D', 'D', 'C', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
673
  /* 736 */ 'A', 'D', 'D', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
674
  /* 747 */ 'A', 'N', 'D', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
675
  /* 758 */ 'X', 'O', 'R', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
676
  /* 769 */ 'X', 'O', 'R', '_', 'I', '_', 'H', 'I', 0,
677
  /* 778 */ 'S', 'L', 'I', 0,
678
  /* 782 */ 'S', 'T', 'B', '_', 'R', 'I', 0,
679
  /* 789 */ 'S', 'T', 'H', '_', 'R', 'I', 0,
680
  /* 796 */ 'L', 'D', 'W', '_', 'R', 'I', 0,
681
  /* 803 */ 'S', 'W', '_', 'R', 'I', 0,
682
  /* 809 */ 'L', 'D', 'B', 's', '_', 'R', 'I', 0,
683
  /* 817 */ 'L', 'D', 'H', 's', '_', 'R', 'I', 0,
684
  /* 825 */ 'L', 'D', 'B', 'z', '_', 'R', 'I', 0,
685
  /* 833 */ 'L', 'D', 'H', 'z', '_', 'R', 'I', 0,
686
  /* 841 */ 'G', '_', 'F', 'P', 'T', 'O', 'S', 'I', 0,
687
  /* 850 */ 'G', '_', 'F', 'P', 'T', 'O', 'U', 'I', 0,
688
  /* 859 */ 'S', 'A', '_', 'I', 0,
689
  /* 864 */ 'S', 'A', '_', 'F', '_', 'I', 0,
690
  /* 871 */ 'S', 'L', '_', 'F', '_', 'I', 0,
691
  /* 878 */ 'S', 'L', '_', 'I', 0,
692
  /* 883 */ 'G', '_', 'P', 'T', 'R', '_', 'M', 'A', 'S', 'K', 0,
693
  /* 894 */ 'G', 'C', '_', 'L', 'A', 'B', 'E', 'L', 0,
694
  /* 903 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0,
695
  /* 913 */ 'E', 'H', '_', 'L', 'A', 'B', 'E', 'L', 0,
696
  /* 922 */ 'A', 'N', 'N', 'O', 'T', 'A', 'T', 'I', 'O', 'N', '_', 'L', 'A', 'B', 'E', 'L', 0,
697
  /* 939 */ 'I', 'C', 'A', 'L', 'L', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'F', 'U', 'N', 'N', 'E', 'L', 0,
698
  /* 959 */ 'G', '_', 'S', 'H', 'L', 0,
699
  /* 965 */ 'G', '_', 'F', 'C', 'E', 'I', 'L', 0,
700
  /* 973 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'A', 'I', 'L', '_', 'C', 'A', 'L', 'L', 0,
701
  /* 993 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
702
  /* 1020 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
703
  /* 1041 */ 'F', 'E', 'N', 'T', 'R', 'Y', '_', 'C', 'A', 'L', 'L', 0,
704
  /* 1053 */ 'K', 'I', 'L', 'L', 0,
705
  /* 1058 */ 'G', '_', 'F', 'M', 'U', 'L', 0,
706
  /* 1065 */ 'G', '_', 'M', 'U', 'L', 0,
707
  /* 1071 */ 'G', '_', 'F', 'R', 'E', 'M', 0,
708
  /* 1078 */ 'G', '_', 'S', 'R', 'E', 'M', 0,
709
  /* 1085 */ 'G', '_', 'U', 'R', 'E', 'M', 0,
710
  /* 1092 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', 0,
711
  /* 1102 */ 'G', '_', 'F', 'C', 'O', 'P', 'Y', 'S', 'I', 'G', 'N', 0,
712
  /* 1114 */ 'G', '_', 'S', 'M', 'I', 'N', 0,
713
  /* 1121 */ 'G', '_', 'U', 'M', 'I', 'N', 0,
714
  /* 1128 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'I', 'N', 0,
715
  /* 1145 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'I', 'N', 0,
716
  /* 1161 */ 'G', '_', 'F', 'S', 'I', 'N', 0,
717
  /* 1168 */ 'C', 'F', 'I', '_', 'I', 'N', 'S', 'T', 'R', 'U', 'C', 'T', 'I', 'O', 'N', 0,
718
  /* 1184 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 0,
719
  /* 1201 */ 'G', '_', 'S', 'S', 'U', 'B', 'O', 0,
720
  /* 1209 */ 'G', '_', 'U', 'S', 'U', 'B', 'O', 0,
721
  /* 1217 */ 'G', '_', 'S', 'A', 'D', 'D', 'O', 0,
722
  /* 1225 */ 'G', '_', 'U', 'A', 'D', 'D', 'O', 0,
723
  /* 1233 */ 'G', '_', 'S', 'M', 'U', 'L', 'O', 0,
724
  /* 1241 */ 'G', '_', 'U', 'M', 'U', 'L', 'O', 0,
725
  /* 1249 */ 'S', 'F', 'S', 'U', 'B', '_', 'F', '_', 'R', 'I', '_', 'L', 'O', 0,
726
  /* 1263 */ 'S', 'U', 'B', 'B', '_', 'I', '_', 'L', 'O', 0,
727
  /* 1273 */ 'S', 'U', 'B', '_', 'I', '_', 'L', 'O', 0,
728
  /* 1282 */ 'A', 'D', 'D', 'C', '_', 'I', '_', 'L', 'O', 0,
729
  /* 1292 */ 'A', 'D', 'D', '_', 'I', '_', 'L', 'O', 0,
730
  /* 1301 */ 'A', 'N', 'D', '_', 'I', '_', 'L', 'O', 0,
731
  /* 1310 */ 'S', 'U', 'B', 'B', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
732
  /* 1322 */ 'S', 'U', 'B', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
733
  /* 1333 */ 'A', 'D', 'D', 'C', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
734
  /* 1345 */ 'A', 'D', 'D', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
735
  /* 1356 */ 'A', 'N', 'D', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
736
  /* 1367 */ 'X', 'O', 'R', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
737
  /* 1378 */ 'X', 'O', 'R', '_', 'I', '_', 'L', 'O', 0,
738
  /* 1387 */ 'S', 'T', 'A', 'C', 'K', 'M', 'A', 'P', 0,
739
  /* 1396 */ 'G', '_', 'B', 'S', 'W', 'A', 'P', 0,
740
  /* 1404 */ 'G', '_', 'G', 'E', 'P', 0,
741
  /* 1410 */ 'G', '_', 'S', 'I', 'T', 'O', 'F', 'P', 0,
742
  /* 1419 */ 'G', '_', 'U', 'I', 'T', 'O', 'F', 'P', 0,
743
  /* 1428 */ 'G', '_', 'F', 'C', 'M', 'P', 0,
744
  /* 1435 */ 'G', '_', 'I', 'C', 'M', 'P', 0,
745
  /* 1442 */ 'N', 'O', 'P', 0,
746
  /* 1446 */ 'G', '_', 'C', 'T', 'P', 'O', 'P', 0,
747
  /* 1454 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'O', 'P', 0,
748
  /* 1467 */ 'F', 'A', 'U', 'L', 'T', 'I', 'N', 'G', '_', 'O', 'P', 0,
749
  /* 1479 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 0,
750
  /* 1494 */ 'G', '_', 'F', 'E', 'X', 'P', 0,
751
  /* 1501 */ 'G', '_', 'B', 'R', 0,
752
  /* 1506 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', '_', 'B', 'R', 0,
753
  /* 1519 */ 'L', 'D', 'A', 'D', 'D', 'R', 0,
754
  /* 1526 */ 'S', 'T', 'A', 'D', 'D', 'R', 0,
755
  /* 1533 */ 'G', '_', 'B', 'L', 'O', 'C', 'K', '_', 'A', 'D', 'D', 'R', 0,
756
  /* 1546 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'N', 'T', 'E', 'R', 0,
757
  /* 1571 */ 'G', '_', 'A', 'S', 'H', 'R', 0,
758
  /* 1578 */ 'G', '_', 'L', 'S', 'H', 'R', 0,
759
  /* 1585 */ 'J', 'R', 0,
760
  /* 1588 */ 'C', 'A', 'L', 'L', 'R', 0,
761
  /* 1594 */ 'G', '_', 'F', 'F', 'L', 'O', 'O', 'R', 0,
762
  /* 1603 */ 'G', '_', 'B', 'U', 'I', 'L', 'D', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
763
  /* 1618 */ 'G', '_', 'S', 'H', 'U', 'F', 'F', 'L', 'E', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
764
  /* 1635 */ 'G', '_', 'X', 'O', 'R', 0,
765
  /* 1641 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'O', 'R', 0,
766
  /* 1657 */ 'G', '_', 'O', 'R', 0,
767
  /* 1662 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'O', 'R', 0,
768
  /* 1677 */ 'B', 'R', 'R', 0,
769
  /* 1681 */ 'S', 'T', 'B', '_', 'R', 'R', 0,
770
  /* 1688 */ 'S', 'F', 'S', 'U', 'B', '_', 'F', '_', 'R', 'R', 0,
771
  /* 1699 */ 'S', 'T', 'H', '_', 'R', 'R', 0,
772
  /* 1706 */ 'L', 'D', 'W', '_', 'R', 'R', 0,
773
  /* 1713 */ 'S', 'W', '_', 'R', 'R', 0,
774
  /* 1719 */ 'L', 'D', 'B', 's', '_', 'R', 'R', 0,
775
  /* 1727 */ 'L', 'D', 'H', 's', '_', 'R', 'R', 0,
776
  /* 1735 */ 'L', 'D', 'B', 'z', '_', 'R', 'R', 0,
777
  /* 1743 */ 'L', 'D', 'H', 'z', '_', 'R', 'R', 0,
778
  /* 1751 */ 'L', 'D', 'W', 'z', '_', 'R', 'R', 0,
779
  /* 1759 */ 'G', '_', 'I', 'N', 'T', 'T', 'O', 'P', 'T', 'R', 0,
780
  /* 1770 */ 'S', 'R', 'A', '_', 'R', 0,
781
  /* 1776 */ 'S', 'U', 'B', 'B', '_', 'R', 0,
782
  /* 1783 */ 'S', 'U', 'B', '_', 'R', 0,
783
  /* 1789 */ 'A', 'D', 'D', 'C', '_', 'R', 0,
784
  /* 1796 */ 'A', 'D', 'D', '_', 'R', 0,
785
  /* 1802 */ 'A', 'N', 'D', '_', 'R', 0,
786
  /* 1808 */ 'S', 'R', 'A', '_', 'F', '_', 'R', 0,
787
  /* 1816 */ 'S', 'U', 'B', 'B', '_', 'F', '_', 'R', 0,
788
  /* 1825 */ 'S', 'U', 'B', '_', 'F', '_', 'R', 0,
789
  /* 1833 */ 'A', 'D', 'D', 'C', '_', 'F', '_', 'R', 0,
790
  /* 1842 */ 'A', 'D', 'D', '_', 'F', '_', 'R', 0,
791
  /* 1850 */ 'A', 'N', 'D', '_', 'F', '_', 'R', 0,
792
  /* 1858 */ 'S', 'H', 'L', '_', 'F', '_', 'R', 0,
793
  /* 1866 */ 'S', 'R', 'L', '_', 'F', '_', 'R', 0,
794
  /* 1874 */ 'X', 'O', 'R', '_', 'F', '_', 'R', 0,
795
  /* 1882 */ 'S', 'H', 'L', '_', 'R', 0,
796
  /* 1888 */ 'S', 'R', 'L', '_', 'R', 0,
797
  /* 1894 */ 'X', 'O', 'R', '_', 'R', 0,
798
  /* 1900 */ 'G', '_', 'F', 'A', 'B', 'S', 0,
799
  /* 1907 */ 'G', '_', 'U', 'N', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
800
  /* 1924 */ 'G', '_', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
801
  /* 1939 */ 'G', '_', 'F', 'C', 'O', 'S', 0,
802
  /* 1946 */ 'G', '_', 'C', 'O', 'N', 'C', 'A', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', 'S', 0,
803
  /* 1963 */ 'C', 'O', 'P', 'Y', '_', 'T', 'O', '_', 'R', 'E', 'G', 'C', 'L', 'A', 'S', 'S', 0,
804
  /* 1980 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'W', 'I', 'T', 'H', '_', 'S', 'U', 'C', 'C', 'E', 'S', 'S', 0,
805
  /* 2010 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'W', '_', 'S', 'I', 'D', 'E', '_', 'E', 'F', 'F', 'E', 'C', 'T', 'S', 0,
806
  /* 2037 */ 'B', 'T', 0,
807
  /* 2040 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', 0,
808
  /* 2050 */ 'G', '_', 'S', 'E', 'L', 'E', 'C', 'T', 0,
809
  /* 2059 */ 'G', '_', 'B', 'R', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', 0,
810
  /* 2072 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'R', 'E', 'T', 0,
811
  /* 2086 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'X', 'I', 'T', 0,
812
  /* 2110 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
813
  /* 2131 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
814
  /* 2151 */ 'G', '_', 'F', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
815
  /* 2163 */ 'G', '_', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
816
  /* 2174 */ 'S', 'T', 'A', 'T', 'E', 'P', 'O', 'I', 'N', 'T', 0,
817
  /* 2185 */ 'P', 'A', 'T', 'C', 'H', 'P', 'O', 'I', 'N', 'T', 0,
818
  /* 2196 */ 'G', '_', 'P', 'T', 'R', 'T', 'O', 'I', 'N', 'T', 0,
819
  /* 2207 */ 'G', '_', 'F', 'R', 'I', 'N', 'T', 0,
820
  /* 2215 */ 'G', '_', 'F', 'N', 'E', 'A', 'R', 'B', 'Y', 'I', 'N', 'T', 0,
821
  /* 2228 */ 'G', '_', 'V', 'A', 'S', 'T', 'A', 'R', 'T', 0,
822
  /* 2238 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
823
  /* 2253 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', 0,
824
  /* 2262 */ 'G', '_', 'F', 'S', 'Q', 'R', 'T', 0,
825
  /* 2270 */ 'G', '_', 'B', 'I', 'T', 'C', 'A', 'S', 'T', 0,
826
  /* 2280 */ 'G', '_', 'A', 'D', 'D', 'R', 'S', 'P', 'A', 'C', 'E', '_', 'C', 'A', 'S', 'T', 0,
827
  /* 2297 */ 'G', '_', 'F', 'P', 'E', 'X', 'T', 0,
828
  /* 2305 */ 'G', '_', 'S', 'E', 'X', 'T', 0,
829
  /* 2312 */ 'G', '_', 'A', 'N', 'Y', 'E', 'X', 'T', 0,
830
  /* 2321 */ 'G', '_', 'Z', 'E', 'X', 'T', 0,
831
  /* 2328 */ 'G', '_', 'F', 'D', 'I', 'V', 0,
832
  /* 2335 */ 'G', '_', 'S', 'D', 'I', 'V', 0,
833
  /* 2342 */ 'G', '_', 'U', 'D', 'I', 'V', 0,
834
  /* 2349 */ 'G', '_', 'F', 'P', 'O', 'W', 0,
835
  /* 2356 */ 'G', '_', 'S', 'M', 'A', 'X', 0,
836
  /* 2363 */ 'G', '_', 'U', 'M', 'A', 'X', 0,
837
  /* 2370 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'A', 'X', 0,
838
  /* 2387 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'A', 'X', 0,
839
  /* 2403 */ 'G', '_', 'F', 'R', 'A', 'M', 'E', '_', 'I', 'N', 'D', 'E', 'X', 0,
840
  /* 2417 */ 'C', 'O', 'P', 'Y', 0,
841
  /* 2422 */ 'L', 'E', 'A', 'D', 'Z', 0,
842
  /* 2428 */ 'T', 'R', 'A', 'I', 'L', 'Z', 0,
843
  /* 2435 */ 'G', '_', 'C', 'T', 'L', 'Z', 0,
844
  /* 2442 */ 'G', '_', 'C', 'T', 'T', 'Z', 0,
845
};
846
847
extern const unsigned LanaiInstrNameIndices[] = {
848
    630U, 1092U, 1506U, 1168U, 913U, 894U, 922U, 1053U, 
849
    520U, 535U, 500U, 549U, 1963U, 421U, 903U, 364U, 
850
    2417U, 393U, 2238U, 291U, 1387U, 1041U, 2185U, 331U, 
851
    2174U, 400U, 1467U, 1454U, 1546U, 2072U, 2086U, 973U, 
852
    1020U, 993U, 939U, 230U, 68U, 1065U, 2335U, 2342U, 
853
    1078U, 1085U, 269U, 1657U, 1635U, 498U, 628U, 2403U, 
854
    431U, 2040U, 1907U, 2253U, 1924U, 1603U, 156U, 1946U, 
855
    2196U, 1759U, 2270U, 130U, 313U, 216U, 194U, 205U, 
856
    413U, 1980U, 563U, 580U, 236U, 74U, 275U, 252U, 
857
    1662U, 1641U, 2387U, 1145U, 2370U, 1128U, 304U, 2059U, 
858
    108U, 2010U, 2312U, 148U, 2163U, 2151U, 2228U, 604U, 
859
    2305U, 2321U, 959U, 1578U, 1571U, 1435U, 1428U, 2050U, 
860
    1225U, 385U, 1209U, 356U, 1217U, 377U, 1201U, 348U, 
861
    1241U, 1233U, 620U, 612U, 223U, 61U, 1058U, 55U, 
862
    2328U, 1071U, 2349U, 1494U, 27U, 597U, 19U, 0U, 
863
    513U, 2297U, 120U, 841U, 850U, 1410U, 1419U, 1900U, 
864
    1102U, 446U, 1404U, 883U, 1114U, 2356U, 1121U, 2363U, 
865
    1501U, 2131U, 2110U, 1618U, 2442U, 480U, 2435U, 462U, 
866
    1446U, 1396U, 965U, 1939U, 1161U, 2262U, 1594U, 2207U, 
867
    2215U, 2280U, 1533U, 1184U, 1479U, 177U, 988U, 1588U, 
868
    724U, 1333U, 1833U, 673U, 1282U, 1789U, 736U, 1345U, 
869
    1842U, 683U, 1292U, 1796U, 747U, 1356U, 1850U, 692U, 
870
    1301U, 1802U, 90U, 99U, 45U, 1677U, 2037U, 1585U, 
871
    1519U, 809U, 1719U, 825U, 1735U, 817U, 1727U, 833U, 
872
    1743U, 796U, 1706U, 1751U, 2422U, 9U, 14U, 22U, 
873
    35U, 40U, 634U, 1442U, 759U, 1368U, 1875U, 770U, 
874
    1379U, 1895U, 189U, 2082U, 864U, 859U, 95U, 2052U, 
875
    640U, 1249U, 1688U, 1858U, 1882U, 778U, 871U, 878U, 
876
    1808U, 1770U, 1866U, 1888U, 1526U, 782U, 1681U, 789U, 
877
    1699U, 701U, 1310U, 1816U, 654U, 1263U, 1776U, 713U, 
878
    1322U, 1825U, 664U, 1273U, 1783U, 803U, 1713U, 2428U, 
879
    758U, 1367U, 1874U, 769U, 1378U, 1894U, 
880
};
881
882
16
static inline void InitLanaiMCInstrInfo(MCInstrInfo *II) {
883
16
  II->InitMCInstrInfo(LanaiInsts, LanaiInstrNameIndices, LanaiInstrNameData, 254);
884
16
}
885
886
} // end llvm namespace
887
#endif // GET_INSTRINFO_MC_DESC
888
889
#ifdef GET_INSTRINFO_HEADER
890
#undef GET_INSTRINFO_HEADER
891
namespace llvm {
892
struct LanaiGenInstrInfo : public TargetInstrInfo {
893
  explicit LanaiGenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);
894
12
  ~LanaiGenInstrInfo() override = default;
895
896
};
897
} // end llvm namespace
898
#endif // GET_INSTRINFO_HEADER
899
900
#ifdef GET_INSTRINFO_HELPER_DECLS
901
#undef GET_INSTRINFO_HELPER_DECLS
902
903
904
#endif // GET_INSTRINFO_HELPER_DECLS
905
906
#ifdef GET_INSTRINFO_HELPERS
907
#undef GET_INSTRINFO_HELPERS
908
909
#endif // GET_INSTRINFO_HELPERS
910
911
#ifdef GET_INSTRINFO_CTOR_DTOR
912
#undef GET_INSTRINFO_CTOR_DTOR
913
namespace llvm {
914
extern const MCInstrDesc LanaiInsts[];
915
extern const unsigned LanaiInstrNameIndices[];
916
extern const char LanaiInstrNameData[];
917
LanaiGenInstrInfo::LanaiGenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)
918
12
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
919
12
  InitMCInstrInfo(LanaiInsts, LanaiInstrNameIndices, LanaiInstrNameData, 254);
920
12
}
921
} // end llvm namespace
922
#endif // GET_INSTRINFO_CTOR_DTOR
923
924
#ifdef GET_INSTRINFO_OPERAND_ENUM
925
#undef GET_INSTRINFO_OPERAND_ENUM
926
namespace llvm {
927
namespace Lanai {
928
namespace OpName {
929
enum {
930
OPERAND_LAST
931
};
932
} // end namespace OpName
933
} // end namespace Lanai
934
} // end namespace llvm
935
#endif //GET_INSTRINFO_OPERAND_ENUM
936
937
#ifdef GET_INSTRINFO_NAMED_OPS
938
#undef GET_INSTRINFO_NAMED_OPS
939
namespace llvm {
940
namespace Lanai {
941
LLVM_READONLY
942
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
943
  return -1;
944
}
945
} // end namespace Lanai
946
} // end namespace llvm
947
#endif //GET_INSTRINFO_NAMED_OPS
948
949
#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
950
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
951
namespace llvm {
952
namespace Lanai {
953
namespace OpTypes {
954
enum OperandType {
955
  AluOp = 0,
956
  BrTarget = 1,
957
  CCOp = 2,
958
  CallTarget = 3,
959
  MEMi = 4,
960
  MEMri = 5,
961
  MEMrr = 6,
962
  MEMspls = 7,
963
  f32imm = 8,
964
  f64imm = 9,
965
  i16imm = 10,
966
  i1imm = 11,
967
  i32hi16 = 12,
968
  i32hi16and = 13,
969
  i32imm = 14,
970
  i32lo16and = 15,
971
  i32lo16s = 16,
972
  i32lo16z = 17,
973
  i32lo21 = 18,
974
  i32neg16 = 19,
975
  i64imm = 20,
976
  i8imm = 21,
977
  imm10 = 22,
978
  immShift = 23,
979
  pred = 24,
980
  ptype0 = 25,
981
  ptype1 = 26,
982
  ptype2 = 27,
983
  ptype3 = 28,
984
  ptype4 = 29,
985
  ptype5 = 30,
986
  type0 = 31,
987
  type1 = 32,
988
  type2 = 33,
989
  type3 = 34,
990
  type4 = 35,
991
  type5 = 36,
992
  OPERAND_TYPE_LIST_END
993
};
994
} // end namespace OpTypes
995
} // end namespace Lanai
996
} // end namespace llvm
997
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
998
999
#ifdef GET_INSTRMAP_INFO
1000
#undef GET_INSTRMAP_INFO
1001
namespace llvm {
1002
1003
namespace Lanai {
1004
1005
enum PostEncoderMethod {
1006
  PostEncoderMethod_adjustPqBitsSpls
1007
};
1008
1009
// splsIdempotent
1010
LLVM_READONLY
1011
112
int splsIdempotent(uint16_t Opcode) {
1012
112
static const uint16_t splsIdempotentTable[][2] = {
1013
112
  { Lanai::LDBs_RI, Lanai::LDBs_RI },
1014
112
  { Lanai::LDBz_RI, Lanai::LDBz_RI },
1015
112
  { Lanai::LDHs_RI, Lanai::LDHs_RI },
1016
112
  { Lanai::LDHz_RI, Lanai::LDHz_RI },
1017
112
  { Lanai::STB_RI, Lanai::STB_RI },
1018
112
  { Lanai::STH_RI, Lanai::STH_RI },
1019
112
}; // End of splsIdempotentTable
1020
112
1021
112
  unsigned mid;
1022
112
  unsigned start = 0;
1023
112
  unsigned end = 6;
1024
444
  while (start < end) {
1025
332
    mid = start + (end - start)/2;
1026
332
    if (Opcode == splsIdempotentTable[mid][0]) {
1027
0
      break;
1028
0
    }
1029
332
    if (Opcode < splsIdempotentTable[mid][0])
1030
216
      end = mid;
1031
116
    else
1032
116
      start = mid + 1;
1033
332
  }
1034
112
  if (start == end)
1035
112
    return -1; // Instruction doesn't exist in this table.
1036
0
1037
0
  return splsIdempotentTable[mid][1];
1038
0
}
1039
1040
} // End Lanai namespace
1041
} // End llvm namespace
1042
#endif // GET_INSTRMAP_INFO
1043