Coverage Report

Created: 2018-07-19 03:59

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Lanai/LanaiGenMCCodeEmitter.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Machine Code Emitter                                                       *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
uint64_t LanaiMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
10
    SmallVectorImpl<MCFixup> &Fixups,
11
481
    const MCSubtargetInfo &STI) const {
12
481
  static const uint64_t InstBits[] = {
13
481
    UINT64_C(0),
14
481
    UINT64_C(0),
15
481
    UINT64_C(0),
16
481
    UINT64_C(0),
17
481
    UINT64_C(0),
18
481
    UINT64_C(0),
19
481
    UINT64_C(0),
20
481
    UINT64_C(0),
21
481
    UINT64_C(0),
22
481
    UINT64_C(0),
23
481
    UINT64_C(0),
24
481
    UINT64_C(0),
25
481
    UINT64_C(0),
26
481
    UINT64_C(0),
27
481
    UINT64_C(0),
28
481
    UINT64_C(0),
29
481
    UINT64_C(0),
30
481
    UINT64_C(0),
31
481
    UINT64_C(0),
32
481
    UINT64_C(0),
33
481
    UINT64_C(0),
34
481
    UINT64_C(0),
35
481
    UINT64_C(0),
36
481
    UINT64_C(0),
37
481
    UINT64_C(0),
38
481
    UINT64_C(0),
39
481
    UINT64_C(0),
40
481
    UINT64_C(0),
41
481
    UINT64_C(0),
42
481
    UINT64_C(0),
43
481
    UINT64_C(0),
44
481
    UINT64_C(0),
45
481
    UINT64_C(0),
46
481
    UINT64_C(0),
47
481
    UINT64_C(0),
48
481
    UINT64_C(0),
49
481
    UINT64_C(0),
50
481
    UINT64_C(0),
51
481
    UINT64_C(0),
52
481
    UINT64_C(0),
53
481
    UINT64_C(0),
54
481
    UINT64_C(0),
55
481
    UINT64_C(0),
56
481
    UINT64_C(0),
57
481
    UINT64_C(0),
58
481
    UINT64_C(0),
59
481
    UINT64_C(0),
60
481
    UINT64_C(0),
61
481
    UINT64_C(0),
62
481
    UINT64_C(0),
63
481
    UINT64_C(0),
64
481
    UINT64_C(0),
65
481
    UINT64_C(0),
66
481
    UINT64_C(0),
67
481
    UINT64_C(0),
68
481
    UINT64_C(0),
69
481
    UINT64_C(0),
70
481
    UINT64_C(0),
71
481
    UINT64_C(0),
72
481
    UINT64_C(0),
73
481
    UINT64_C(0),
74
481
    UINT64_C(0),
75
481
    UINT64_C(0),
76
481
    UINT64_C(0),
77
481
    UINT64_C(0),
78
481
    UINT64_C(0),
79
481
    UINT64_C(0),
80
481
    UINT64_C(0),
81
481
    UINT64_C(0),
82
481
    UINT64_C(0),
83
481
    UINT64_C(0),
84
481
    UINT64_C(0),
85
481
    UINT64_C(0),
86
481
    UINT64_C(0),
87
481
    UINT64_C(0),
88
481
    UINT64_C(0),
89
481
    UINT64_C(0),
90
481
    UINT64_C(0),
91
481
    UINT64_C(0),
92
481
    UINT64_C(0),
93
481
    UINT64_C(0),
94
481
    UINT64_C(0),
95
481
    UINT64_C(0),
96
481
    UINT64_C(0),
97
481
    UINT64_C(0),
98
481
    UINT64_C(0),
99
481
    UINT64_C(0),
100
481
    UINT64_C(0),
101
481
    UINT64_C(0),
102
481
    UINT64_C(0),
103
481
    UINT64_C(0),
104
481
    UINT64_C(0),
105
481
    UINT64_C(0),
106
481
    UINT64_C(0),
107
481
    UINT64_C(0),
108
481
    UINT64_C(0),
109
481
    UINT64_C(0),
110
481
    UINT64_C(0),
111
481
    UINT64_C(0),
112
481
    UINT64_C(0),
113
481
    UINT64_C(0),
114
481
    UINT64_C(0),
115
481
    UINT64_C(0),
116
481
    UINT64_C(0),
117
481
    UINT64_C(0),
118
481
    UINT64_C(0),
119
481
    UINT64_C(0),
120
481
    UINT64_C(0),
121
481
    UINT64_C(0),
122
481
    UINT64_C(0),
123
481
    UINT64_C(0),
124
481
    UINT64_C(0),
125
481
    UINT64_C(0),
126
481
    UINT64_C(0),
127
481
    UINT64_C(0),
128
481
    UINT64_C(0),
129
481
    UINT64_C(0),
130
481
    UINT64_C(0),
131
481
    UINT64_C(0),
132
481
    UINT64_C(0),
133
481
    UINT64_C(0),
134
481
    UINT64_C(0),
135
481
    UINT64_C(0),
136
481
    UINT64_C(0),
137
481
    UINT64_C(0),
138
481
    UINT64_C(0),
139
481
    UINT64_C(0),
140
481
    UINT64_C(0),
141
481
    UINT64_C(0),
142
481
    UINT64_C(0),
143
481
    UINT64_C(268632064),  // ADDC_F_I_HI
144
481
    UINT64_C(268566528),  // ADDC_F_I_LO
145
481
    UINT64_C(3221356800), // ADDC_F_R
146
481
    UINT64_C(268500992),  // ADDC_I_HI
147
481
    UINT64_C(268435456),  // ADDC_I_LO
148
481
    UINT64_C(3221225728), // ADDC_R
149
481
    UINT64_C(196608), // ADD_F_I_HI
150
481
    UINT64_C(131072), // ADD_F_I_LO
151
481
    UINT64_C(3221356544), // ADD_F_R
152
481
    UINT64_C(65536),  // ADD_I_HI
153
481
    UINT64_C(0),  // ADD_I_LO
154
481
    UINT64_C(3221225472), // ADD_R
155
481
    UINT64_C(1073938432), // AND_F_I_HI
156
481
    UINT64_C(1073872896), // AND_F_I_LO
157
481
    UINT64_C(3221357568), // AND_F_R
158
481
    UINT64_C(1073807360), // AND_I_HI
159
481
    UINT64_C(1073741824), // AND_I_LO
160
481
    UINT64_C(3221226496), // AND_R
161
481
    UINT64_C(3758096384), // BRCC
162
481
    UINT64_C(3238003968), // BRIND_CC
163
481
    UINT64_C(3238003968), // BRIND_CCA
164
481
    UINT64_C(3774873602), // BRR
165
481
    UINT64_C(3758096384), // BT
166
481
    UINT64_C(3238003968), // JR
167
481
    UINT64_C(4026531840), // LDADDR
168
481
    UINT64_C(4026744832), // LDBs_RI
169
481
    UINT64_C(2684354564), // LDBs_RR
170
481
    UINT64_C(4026748928), // LDBz_RI
171
481
    UINT64_C(2684354565), // LDBz_RR
172
481
    UINT64_C(4026728448), // LDHs_RI
173
481
    UINT64_C(2684354560), // LDHs_RR
174
481
    UINT64_C(4026732544), // LDHz_RI
175
481
    UINT64_C(2684354561), // LDHz_RR
176
481
    UINT64_C(2147483648), // LDW_RI
177
481
    UINT64_C(2684354562), // LDW_RR
178
481
    UINT64_C(2684354563), // LDWz_RR
179
481
    UINT64_C(3489660930), // LEADZ
180
481
    UINT64_C(2),  // LOG0
181
481
    UINT64_C(3),  // LOG1
182
481
    UINT64_C(4),  // LOG2
183
481
    UINT64_C(5),  // LOG3
184
481
    UINT64_C(6),  // LOG4
185
481
    UINT64_C(65536),  // MOVHI
186
481
    UINT64_C(1),  // NOP
187
481
    UINT64_C(1342373888), // OR_F_I_HI
188
481
    UINT64_C(1342308352), // OR_F_I_LO
189
481
    UINT64_C(3221357824), // OR_F_R
190
481
    UINT64_C(1342242816), // OR_I_HI
191
481
    UINT64_C(1342177280), // OR_I_LO
192
481
    UINT64_C(3221226752), // OR_R
193
481
    UINT64_C(3489660929), // POPC
194
481
    UINT64_C(2165768188), // RET
195
481
    UINT64_C(1879244800), // SA_F_I
196
481
    UINT64_C(1879113728), // SA_I
197
481
    UINT64_C(3758096386), // SCC
198
481
    UINT64_C(3221227264), // SELECT
199
481
    UINT64_C(537067520),  // SFSUB_F_RI_HI
200
481
    UINT64_C(537001984),  // SFSUB_F_RI_LO
201
481
    UINT64_C(3221357056), // SFSUB_F_RR
202
481
    UINT64_C(3221358464), // SHL_F_R
203
481
    UINT64_C(3221227392), // SHL_R
204
481
    UINT64_C(4026662912), // SLI
205
481
    UINT64_C(1879179264), // SL_F_I
206
481
    UINT64_C(1879048192), // SL_I
207
481
    UINT64_C(3221358528), // SRA_F_R
208
481
    UINT64_C(3221227456), // SRA_R
209
481
    UINT64_C(3221358464), // SRL_F_R
210
481
    UINT64_C(3221227392), // SRL_R
211
481
    UINT64_C(4026597376), // STADDR
212
481
    UINT64_C(4026753024), // STB_RI
213
481
    UINT64_C(2952790020), // STB_RR
214
481
    UINT64_C(4026736640), // STH_RI
215
481
    UINT64_C(2952790016), // STH_RR
216
481
    UINT64_C(805502976),  // SUBB_F_I_HI
217
481
    UINT64_C(805437440),  // SUBB_F_I_LO
218
481
    UINT64_C(3221357312), // SUBB_F_R
219
481
    UINT64_C(805371904),  // SUBB_I_HI
220
481
    UINT64_C(805306368),  // SUBB_I_LO
221
481
    UINT64_C(3221226240), // SUBB_R
222
481
    UINT64_C(537067520),  // SUB_F_I_HI
223
481
    UINT64_C(537001984),  // SUB_F_I_LO
224
481
    UINT64_C(3221357056), // SUB_F_R
225
481
    UINT64_C(536936448),  // SUB_I_HI
226
481
    UINT64_C(536870912),  // SUB_I_LO
227
481
    UINT64_C(3221225984), // SUB_R
228
481
    UINT64_C(2415919104), // SW_RI
229
481
    UINT64_C(2952790018), // SW_RR
230
481
    UINT64_C(3489660931), // TRAILZ
231
481
    UINT64_C(1610809344), // XOR_F_I_HI
232
481
    UINT64_C(1610743808), // XOR_F_I_LO
233
481
    UINT64_C(3221358080), // XOR_F_R
234
481
    UINT64_C(1610678272), // XOR_I_HI
235
481
    UINT64_C(1610612736), // XOR_I_LO
236
481
    UINT64_C(3221227008), // XOR_R
237
481
    UINT64_C(0)
238
481
  };
239
481
  const unsigned opcode = MI.getOpcode();
240
481
  uint64_t Value = InstBits[opcode];
241
481
  uint64_t op = 0;
242
481
  (void)op;  // suppress warning
243
481
  switch (opcode) {
244
481
    case Lanai::LOG0:
245
3
    case Lanai::LOG1:
246
3
    case Lanai::LOG2:
247
3
    case Lanai::LOG3:
248
3
    case Lanai::LOG4:
249
3
    case Lanai::NOP:
250
3
    case Lanai::RET: {
251
3
      break;
252
3
    }
253
20
    case Lanai::BRR: {
254
20
      // op: DDDI
255
20
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
256
20
      Value |= (op & UINT64_C(14)) << 24;
257
20
      Value |= op & UINT64_C(1);
258
20
      // op: imm16
259
20
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
260
20
      Value |= op & UINT64_C(65532);
261
20
      break;
262
3
    }
263
37
    case Lanai::STB_RI:
264
37
    case Lanai::STH_RI: {
265
37
      // op: Rd
266
37
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
267
37
      Value |= (op & UINT64_C(31)) << 23;
268
37
      // op: P
269
37
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
270
37
      Value |= (op & UINT64_C(1)) << 11;
271
37
      // op: Q
272
37
      op = getSplsOpValue(MI, 1, Fixups, STI);
273
37
      Value |= (op & UINT64_C(1)) << 10;
274
37
      // op: dst
275
37
      op = getSplsOpValue(MI, 1, Fixups, STI);
276
37
      Value |= (op & UINT64_C(126976)) << 6;
277
37
      Value |= op & UINT64_C(1023);
278
37
      Value = adjustPqBitsSpls(MI, Value, STI);
279
37
      break;
280
37
    }
281
65
    case Lanai::LDBs_RI:
282
65
    case Lanai::LDBz_RI:
283
65
    case Lanai::LDHs_RI:
284
65
    case Lanai::LDHz_RI: {
285
65
      // op: Rd
286
65
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
287
65
      Value |= (op & UINT64_C(31)) << 23;
288
65
      // op: P
289
65
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
290
65
      Value |= (op & UINT64_C(1)) << 11;
291
65
      // op: Q
292
65
      op = getSplsOpValue(MI, 1, Fixups, STI);
293
65
      Value |= (op & UINT64_C(1)) << 10;
294
65
      // op: src
295
65
      op = getSplsOpValue(MI, 1, Fixups, STI);
296
65
      Value |= (op & UINT64_C(126976)) << 6;
297
65
      Value |= op & UINT64_C(1023);
298
65
      Value = adjustPqBitsSpls(MI, Value, STI);
299
65
      break;
300
65
    }
301
65
    case Lanai::SW_RI: {
302
21
      // op: Rd
303
21
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
304
21
      Value |= (op & UINT64_C(31)) << 23;
305
21
      // op: P
306
21
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
307
21
      Value |= (op & UINT64_C(1)) << 17;
308
21
      // op: Q
309
21
      op = getRiMemoryOpValue(MI, 1, Fixups, STI);
310
21
      Value |= (op & UINT64_C(1)) << 16;
311
21
      // op: dst
312
21
      op = getRiMemoryOpValue(MI, 1, Fixups, STI);
313
21
      Value |= op & UINT64_C(8126464);
314
21
      Value |= op & UINT64_C(65535);
315
21
      Value = adjustPqBitsRmAndRrm(MI, Value, STI);
316
21
      break;
317
65
    }
318
65
    case Lanai::LDW_RI: {
319
44
      // op: Rd
320
44
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
321
44
      Value |= (op & UINT64_C(31)) << 23;
322
44
      // op: P
323
44
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
324
44
      Value |= (op & UINT64_C(1)) << 17;
325
44
      // op: Q
326
44
      op = getRiMemoryOpValue(MI, 1, Fixups, STI);
327
44
      Value |= (op & UINT64_C(1)) << 16;
328
44
      // op: src
329
44
      op = getRiMemoryOpValue(MI, 1, Fixups, STI);
330
44
      Value |= op & UINT64_C(8126464);
331
44
      Value |= op & UINT64_C(65535);
332
44
      Value = adjustPqBitsRmAndRrm(MI, Value, STI);
333
44
      break;
334
65
    }
335
88
    case Lanai::STB_RR:
336
88
    case Lanai::STH_RR:
337
88
    case Lanai::SW_RR: {
338
88
      // op: Rd
339
88
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
340
88
      Value |= (op & UINT64_C(31)) << 23;
341
88
      // op: P
342
88
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
343
88
      Value |= (op & UINT64_C(1)) << 17;
344
88
      // op: Q
345
88
      op = getRrMemoryOpValue(MI, 1, Fixups, STI);
346
88
      Value |= (op & UINT64_C(1)) << 16;
347
88
      // op: dst
348
88
      op = getRrMemoryOpValue(MI, 1, Fixups, STI);
349
88
      Value |= (op & UINT64_C(1015808)) << 3;
350
88
      Value |= (op & UINT64_C(31744)) << 1;
351
88
      Value |= (op & UINT64_C(255)) << 3;
352
88
      Value = adjustPqBitsRmAndRrm(MI, Value, STI);
353
88
      break;
354
88
    }
355
88
    case Lanai::LDBs_RR:
356
39
    case Lanai::LDBz_RR:
357
39
    case Lanai::LDHs_RR:
358
39
    case Lanai::LDHz_RR:
359
39
    case Lanai::LDW_RR:
360
39
    case Lanai::LDWz_RR: {
361
39
      // op: Rd
362
39
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
363
39
      Value |= (op & UINT64_C(31)) << 23;
364
39
      // op: P
365
39
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
366
39
      Value |= (op & UINT64_C(1)) << 17;
367
39
      // op: Q
368
39
      op = getRrMemoryOpValue(MI, 1, Fixups, STI);
369
39
      Value |= (op & UINT64_C(1)) << 16;
370
39
      // op: src
371
39
      op = getRrMemoryOpValue(MI, 1, Fixups, STI);
372
39
      Value |= (op & UINT64_C(1015808)) << 3;
373
39
      Value |= (op & UINT64_C(31744)) << 1;
374
39
      Value |= (op & UINT64_C(255)) << 3;
375
39
      Value = adjustPqBitsRmAndRrm(MI, Value, STI);
376
39
      break;
377
39
    }
378
39
    case Lanai::LEADZ:
379
3
    case Lanai::POPC:
380
3
    case Lanai::TRAILZ: {
381
3
      // op: Rd
382
3
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
383
3
      Value |= (op & UINT64_C(31)) << 23;
384
3
      // op: Rs1
385
3
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
386
3
      Value |= (op & UINT64_C(31)) << 18;
387
3
      break;
388
3
    }
389
42
    case Lanai::ADDC_F_R:
390
42
    case Lanai::ADDC_R:
391
42
    case Lanai::ADD_F_R:
392
42
    case Lanai::ADD_R:
393
42
    case Lanai::AND_F_R:
394
42
    case Lanai::AND_R:
395
42
    case Lanai::OR_F_R:
396
42
    case Lanai::OR_R:
397
42
    case Lanai::SELECT:
398
42
    case Lanai::SHL_F_R:
399
42
    case Lanai::SHL_R:
400
42
    case Lanai::SRA_F_R:
401
42
    case Lanai::SRA_R:
402
42
    case Lanai::SRL_F_R:
403
42
    case Lanai::SRL_R:
404
42
    case Lanai::SUBB_F_R:
405
42
    case Lanai::SUBB_R:
406
42
    case Lanai::SUB_F_R:
407
42
    case Lanai::SUB_R:
408
42
    case Lanai::XOR_F_R:
409
42
    case Lanai::XOR_R: {
410
42
      // op: Rd
411
42
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
412
42
      Value |= (op & UINT64_C(31)) << 23;
413
42
      // op: Rs1
414
42
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
415
42
      Value |= (op & UINT64_C(31)) << 18;
416
42
      // op: Rs2
417
42
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
418
42
      Value |= (op & UINT64_C(31)) << 11;
419
42
      // op: DDDI
420
42
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
421
42
      Value |= (op & UINT64_C(1)) << 16;
422
42
      Value |= (op & UINT64_C(14)) >> 1;
423
42
      break;
424
42
    }
425
64
    case Lanai::ADDC_F_I_HI:
426
64
    case Lanai::ADDC_F_I_LO:
427
64
    case Lanai::ADDC_I_HI:
428
64
    case Lanai::ADDC_I_LO:
429
64
    case Lanai::ADD_F_I_HI:
430
64
    case Lanai::ADD_F_I_LO:
431
64
    case Lanai::ADD_I_HI:
432
64
    case Lanai::ADD_I_LO:
433
64
    case Lanai::AND_F_I_HI:
434
64
    case Lanai::AND_F_I_LO:
435
64
    case Lanai::AND_I_HI:
436
64
    case Lanai::AND_I_LO:
437
64
    case Lanai::OR_F_I_HI:
438
64
    case Lanai::OR_F_I_LO:
439
64
    case Lanai::OR_I_HI:
440
64
    case Lanai::OR_I_LO:
441
64
    case Lanai::SA_F_I:
442
64
    case Lanai::SA_I:
443
64
    case Lanai::SL_F_I:
444
64
    case Lanai::SL_I:
445
64
    case Lanai::SUBB_F_I_HI:
446
64
    case Lanai::SUBB_F_I_LO:
447
64
    case Lanai::SUBB_I_HI:
448
64
    case Lanai::SUBB_I_LO:
449
64
    case Lanai::SUB_F_I_HI:
450
64
    case Lanai::SUB_F_I_LO:
451
64
    case Lanai::SUB_I_HI:
452
64
    case Lanai::SUB_I_LO:
453
64
    case Lanai::XOR_F_I_HI:
454
64
    case Lanai::XOR_F_I_LO:
455
64
    case Lanai::XOR_I_HI:
456
64
    case Lanai::XOR_I_LO: {
457
64
      // op: Rd
458
64
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
459
64
      Value |= (op & UINT64_C(31)) << 23;
460
64
      // op: Rs1
461
64
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
462
64
      Value |= (op & UINT64_C(31)) << 18;
463
64
      // op: imm16
464
64
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
465
64
      Value |= op & UINT64_C(65535);
466
64
      break;
467
64
    }
468
64
    case Lanai::STADDR: {
469
2
      // op: Rd
470
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
471
2
      Value |= (op & UINT64_C(31)) << 23;
472
2
      // op: dst
473
2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
474
2
      Value |= (op & UINT64_C(2031616)) << 2;
475
2
      Value |= op & UINT64_C(65535);
476
2
      break;
477
64
    }
478
64
    case Lanai::SLI: {
479
1
      // op: Rd
480
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
481
1
      Value |= (op & UINT64_C(31)) << 23;
482
1
      // op: imm
483
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
484
1
      Value |= (op & UINT64_C(2031616)) << 2;
485
1
      Value |= op & UINT64_C(65535);
486
1
      break;
487
64
    }
488
64
    case Lanai::MOVHI: {
489
0
      // op: Rd
490
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
491
0
      Value |= (op & UINT64_C(31)) << 23;
492
0
      // op: imm16
493
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
494
0
      Value |= op & UINT64_C(65535);
495
0
      break;
496
64
    }
497
64
    case Lanai::LDADDR: {
498
3
      // op: Rd
499
3
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
500
3
      Value |= (op & UINT64_C(31)) << 23;
501
3
      // op: src
502
3
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
503
3
      Value |= (op & UINT64_C(2031616)) << 2;
504
3
      Value |= op & UINT64_C(65535);
505
3
      break;
506
64
    }
507
64
    case Lanai::BRIND_CC: {
508
0
      // op: Rs1
509
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
510
0
      Value |= (op & UINT64_C(31)) << 18;
511
0
      // op: DDDI
512
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
513
0
      Value |= (op & UINT64_C(1)) << 16;
514
0
      Value |= (op & UINT64_C(14)) >> 1;
515
0
      break;
516
64
    }
517
64
    case Lanai::SCC: {
518
20
      // op: Rs1
519
20
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
520
20
      Value |= (op & UINT64_C(31)) << 18;
521
20
      // op: DDDI
522
20
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
523
20
      Value |= (op & UINT64_C(14)) << 24;
524
20
      Value |= op & UINT64_C(1);
525
20
      break;
526
64
    }
527
64
    case Lanai::SFSUB_F_RR: {
528
0
      // op: Rs1
529
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
530
0
      Value |= (op & UINT64_C(31)) << 18;
531
0
      // op: Rs2
532
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
533
0
      Value |= (op & UINT64_C(31)) << 11;
534
0
      break;
535
64
    }
536
64
    case Lanai::BRIND_CCA: {
537
0
      // op: Rs1
538
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
539
0
      Value |= (op & UINT64_C(31)) << 18;
540
0
      // op: Rs2
541
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
542
0
      Value |= (op & UINT64_C(31)) << 11;
543
0
      // op: DDDI
544
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
545
0
      Value |= (op & UINT64_C(1)) << 16;
546
0
      Value |= (op & UINT64_C(14)) >> 1;
547
0
      break;
548
64
    }
549
64
    case Lanai::SFSUB_F_RI_HI:
550
0
    case Lanai::SFSUB_F_RI_LO: {
551
0
      // op: Rs1
552
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
553
0
      Value |= (op & UINT64_C(31)) << 18;
554
0
      // op: imm16
555
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
556
0
      Value |= op & UINT64_C(65535);
557
0
      break;
558
0
    }
559
2
    case Lanai::JR: {
560
2
      // op: Rs2
561
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
562
2
      Value |= (op & UINT64_C(31)) << 11;
563
2
      break;
564
0
    }
565
6
    case Lanai::BT: {
566
6
      // op: addr
567
6
      op = getBranchTargetOpValue(MI, 0, Fixups, STI);
568
6
      Value |= op & UINT64_C(33554428);
569
6
      break;
570
0
    }
571
21
    case Lanai::BRCC: {
572
21
      // op: addr
573
21
      op = getBranchTargetOpValue(MI, 0, Fixups, STI);
574
21
      Value |= op & UINT64_C(33554428);
575
21
      // op: DDDI
576
21
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
577
21
      Value |= (op & UINT64_C(14)) << 24;
578
21
      Value |= op & UINT64_C(1);
579
21
      break;
580
0
    }
581
0
  default:
582
0
    std::string msg;
583
0
    raw_string_ostream Msg(msg);
584
0
    Msg << "Not supported instr: " << MI;
585
0
    report_fatal_error(Msg.str());
586
481
  }
587
481
  return Value;
588
481
}
589
590
#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
591
#undef ENABLE_INSTR_PREDICATE_VERIFIER
592
#include <sstream>
593
594
// Flags for subtarget features that participate in instruction matching.
595
enum SubtargetFeatureFlag : uint8_t {
596
  Feature_None = 0
597
};
598
599
#ifndef NDEBUG
600
static const char *SubtargetFeatureNames[] = {
601
  nullptr
602
};
603
604
#endif // NDEBUG
605
uint64_t LanaiMCCodeEmitter::
606
computeAvailableFeatures(const FeatureBitset& FB) const {
607
  uint64_t Features = 0;
608
  return Features;
609
}
610
611
void LanaiMCCodeEmitter::verifyInstructionPredicates(
612
    const MCInst &Inst, uint64_t AvailableFeatures) const {
613
#ifndef NDEBUG
614
  static uint64_t RequiredFeatures[] = {
615
    0, // PHI = 0
616
    0, // INLINEASM = 1
617
    0, // CFI_INSTRUCTION = 2
618
    0, // EH_LABEL = 3
619
    0, // GC_LABEL = 4
620
    0, // ANNOTATION_LABEL = 5
621
    0, // KILL = 6
622
    0, // EXTRACT_SUBREG = 7
623
    0, // INSERT_SUBREG = 8
624
    0, // IMPLICIT_DEF = 9
625
    0, // SUBREG_TO_REG = 10
626
    0, // COPY_TO_REGCLASS = 11
627
    0, // DBG_VALUE = 12
628
    0, // DBG_LABEL = 13
629
    0, // REG_SEQUENCE = 14
630
    0, // COPY = 15
631
    0, // BUNDLE = 16
632
    0, // LIFETIME_START = 17
633
    0, // LIFETIME_END = 18
634
    0, // STACKMAP = 19
635
    0, // FENTRY_CALL = 20
636
    0, // PATCHPOINT = 21
637
    0, // LOAD_STACK_GUARD = 22
638
    0, // STATEPOINT = 23
639
    0, // LOCAL_ESCAPE = 24
640
    0, // FAULTING_OP = 25
641
    0, // PATCHABLE_OP = 26
642
    0, // PATCHABLE_FUNCTION_ENTER = 27
643
    0, // PATCHABLE_RET = 28
644
    0, // PATCHABLE_FUNCTION_EXIT = 29
645
    0, // PATCHABLE_TAIL_CALL = 30
646
    0, // PATCHABLE_EVENT_CALL = 31
647
    0, // PATCHABLE_TYPED_EVENT_CALL = 32
648
    0, // ICALL_BRANCH_FUNNEL = 33
649
    0, // G_ADD = 34
650
    0, // G_SUB = 35
651
    0, // G_MUL = 36
652
    0, // G_SDIV = 37
653
    0, // G_UDIV = 38
654
    0, // G_SREM = 39
655
    0, // G_UREM = 40
656
    0, // G_AND = 41
657
    0, // G_OR = 42
658
    0, // G_XOR = 43
659
    0, // G_IMPLICIT_DEF = 44
660
    0, // G_PHI = 45
661
    0, // G_FRAME_INDEX = 46
662
    0, // G_GLOBAL_VALUE = 47
663
    0, // G_EXTRACT = 48
664
    0, // G_UNMERGE_VALUES = 49
665
    0, // G_INSERT = 50
666
    0, // G_MERGE_VALUES = 51
667
    0, // G_PTRTOINT = 52
668
    0, // G_INTTOPTR = 53
669
    0, // G_BITCAST = 54
670
    0, // G_LOAD = 55
671
    0, // G_SEXTLOAD = 56
672
    0, // G_ZEXTLOAD = 57
673
    0, // G_STORE = 58
674
    0, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 59
675
    0, // G_ATOMIC_CMPXCHG = 60
676
    0, // G_ATOMICRMW_XCHG = 61
677
    0, // G_ATOMICRMW_ADD = 62
678
    0, // G_ATOMICRMW_SUB = 63
679
    0, // G_ATOMICRMW_AND = 64
680
    0, // G_ATOMICRMW_NAND = 65
681
    0, // G_ATOMICRMW_OR = 66
682
    0, // G_ATOMICRMW_XOR = 67
683
    0, // G_ATOMICRMW_MAX = 68
684
    0, // G_ATOMICRMW_MIN = 69
685
    0, // G_ATOMICRMW_UMAX = 70
686
    0, // G_ATOMICRMW_UMIN = 71
687
    0, // G_BRCOND = 72
688
    0, // G_BRINDIRECT = 73
689
    0, // G_INTRINSIC = 74
690
    0, // G_INTRINSIC_W_SIDE_EFFECTS = 75
691
    0, // G_ANYEXT = 76
692
    0, // G_TRUNC = 77
693
    0, // G_CONSTANT = 78
694
    0, // G_FCONSTANT = 79
695
    0, // G_VASTART = 80
696
    0, // G_VAARG = 81
697
    0, // G_SEXT = 82
698
    0, // G_ZEXT = 83
699
    0, // G_SHL = 84
700
    0, // G_LSHR = 85
701
    0, // G_ASHR = 86
702
    0, // G_ICMP = 87
703
    0, // G_FCMP = 88
704
    0, // G_SELECT = 89
705
    0, // G_UADDE = 90
706
    0, // G_USUBE = 91
707
    0, // G_SADDO = 92
708
    0, // G_SSUBO = 93
709
    0, // G_UMULO = 94
710
    0, // G_SMULO = 95
711
    0, // G_UMULH = 96
712
    0, // G_SMULH = 97
713
    0, // G_FADD = 98
714
    0, // G_FSUB = 99
715
    0, // G_FMUL = 100
716
    0, // G_FMA = 101
717
    0, // G_FDIV = 102
718
    0, // G_FREM = 103
719
    0, // G_FPOW = 104
720
    0, // G_FEXP = 105
721
    0, // G_FEXP2 = 106
722
    0, // G_FLOG = 107
723
    0, // G_FLOG2 = 108
724
    0, // G_FNEG = 109
725
    0, // G_FPEXT = 110
726
    0, // G_FPTRUNC = 111
727
    0, // G_FPTOSI = 112
728
    0, // G_FPTOUI = 113
729
    0, // G_SITOFP = 114
730
    0, // G_UITOFP = 115
731
    0, // G_FABS = 116
732
    0, // G_GEP = 117
733
    0, // G_PTR_MASK = 118
734
    0, // G_BR = 119
735
    0, // G_INSERT_VECTOR_ELT = 120
736
    0, // G_EXTRACT_VECTOR_ELT = 121
737
    0, // G_SHUFFLE_VECTOR = 122
738
    0, // G_BSWAP = 123
739
    0, // G_ADDRSPACE_CAST = 124
740
    0, // ADJCALLSTACKDOWN = 125
741
    0, // ADJCALLSTACKUP = 126
742
    0, // ADJDYNALLOC = 127
743
    0, // CALL = 128
744
    0, // CALLR = 129
745
    0, // ADDC_F_I_HI = 130
746
    0, // ADDC_F_I_LO = 131
747
    0, // ADDC_F_R = 132
748
    0, // ADDC_I_HI = 133
749
    0, // ADDC_I_LO = 134
750
    0, // ADDC_R = 135
751
    0, // ADD_F_I_HI = 136
752
    0, // ADD_F_I_LO = 137
753
    0, // ADD_F_R = 138
754
    0, // ADD_I_HI = 139
755
    0, // ADD_I_LO = 140
756
    0, // ADD_R = 141
757
    0, // AND_F_I_HI = 142
758
    0, // AND_F_I_LO = 143
759
    0, // AND_F_R = 144
760
    0, // AND_I_HI = 145
761
    0, // AND_I_LO = 146
762
    0, // AND_R = 147
763
    0, // BRCC = 148
764
    0, // BRIND_CC = 149
765
    0, // BRIND_CCA = 150
766
    0, // BRR = 151
767
    0, // BT = 152
768
    0, // JR = 153
769
    0, // LDADDR = 154
770
    0, // LDBs_RI = 155
771
    0, // LDBs_RR = 156
772
    0, // LDBz_RI = 157
773
    0, // LDBz_RR = 158
774
    0, // LDHs_RI = 159
775
    0, // LDHs_RR = 160
776
    0, // LDHz_RI = 161
777
    0, // LDHz_RR = 162
778
    0, // LDW_RI = 163
779
    0, // LDW_RR = 164
780
    0, // LDWz_RR = 165
781
    0, // LEADZ = 166
782
    0, // LOG0 = 167
783
    0, // LOG1 = 168
784
    0, // LOG2 = 169
785
    0, // LOG3 = 170
786
    0, // LOG4 = 171
787
    0, // MOVHI = 172
788
    0, // NOP = 173
789
    0, // OR_F_I_HI = 174
790
    0, // OR_F_I_LO = 175
791
    0, // OR_F_R = 176
792
    0, // OR_I_HI = 177
793
    0, // OR_I_LO = 178
794
    0, // OR_R = 179
795
    0, // POPC = 180
796
    0, // RET = 181
797
    0, // SA_F_I = 182
798
    0, // SA_I = 183
799
    0, // SCC = 184
800
    0, // SELECT = 185
801
    0, // SFSUB_F_RI_HI = 186
802
    0, // SFSUB_F_RI_LO = 187
803
    0, // SFSUB_F_RR = 188
804
    0, // SHL_F_R = 189
805
    0, // SHL_R = 190
806
    0, // SLI = 191
807
    0, // SL_F_I = 192
808
    0, // SL_I = 193
809
    0, // SRA_F_R = 194
810
    0, // SRA_R = 195
811
    0, // SRL_F_R = 196
812
    0, // SRL_R = 197
813
    0, // STADDR = 198
814
    0, // STB_RI = 199
815
    0, // STB_RR = 200
816
    0, // STH_RI = 201
817
    0, // STH_RR = 202
818
    0, // SUBB_F_I_HI = 203
819
    0, // SUBB_F_I_LO = 204
820
    0, // SUBB_F_R = 205
821
    0, // SUBB_I_HI = 206
822
    0, // SUBB_I_LO = 207
823
    0, // SUBB_R = 208
824
    0, // SUB_F_I_HI = 209
825
    0, // SUB_F_I_LO = 210
826
    0, // SUB_F_R = 211
827
    0, // SUB_I_HI = 212
828
    0, // SUB_I_LO = 213
829
    0, // SUB_R = 214
830
    0, // SW_RI = 215
831
    0, // SW_RR = 216
832
    0, // TRAILZ = 217
833
    0, // XOR_F_I_HI = 218
834
    0, // XOR_F_I_LO = 219
835
    0, // XOR_F_R = 220
836
    0, // XOR_I_HI = 221
837
    0, // XOR_I_LO = 222
838
    0, // XOR_R = 223
839
  };
840
841
  assert(Inst.getOpcode() < 224);
842
  uint64_t MissingFeatures =
843
      (AvailableFeatures & RequiredFeatures[Inst.getOpcode()]) ^
844
      RequiredFeatures[Inst.getOpcode()];
845
  if (MissingFeatures) {
846
    std::ostringstream Msg;
847
    Msg << "Attempting to emit " << MCII.getName(Inst.getOpcode()).str()
848
        << " instruction but the ";
849
    for (unsigned i = 0; i < 8 * sizeof(MissingFeatures); ++i)
850
      if (MissingFeatures & (1ULL << i))
851
        Msg << SubtargetFeatureNames[i] << " ";
852
    Msg << "predicate(s) are not met";
853
    report_fatal_error(Msg.str());
854
  }
855
#else
856
// Silence unused variable warning on targets that don't use MCII for other purposes (e.g. BPF).
857
(void)MCII;
858
#endif // NDEBUG
859
}
860
#endif