Coverage Report

Created: 2018-11-16 02:38

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Lanai/LanaiGenMCCodeEmitter.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Machine Code Emitter                                                       *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
uint64_t LanaiMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
10
    SmallVectorImpl<MCFixup> &Fixups,
11
481
    const MCSubtargetInfo &STI) const {
12
481
  static const uint64_t InstBits[] = {
13
481
    UINT64_C(0),
14
481
    UINT64_C(0),
15
481
    UINT64_C(0),
16
481
    UINT64_C(0),
17
481
    UINT64_C(0),
18
481
    UINT64_C(0),
19
481
    UINT64_C(0),
20
481
    UINT64_C(0),
21
481
    UINT64_C(0),
22
481
    UINT64_C(0),
23
481
    UINT64_C(0),
24
481
    UINT64_C(0),
25
481
    UINT64_C(0),
26
481
    UINT64_C(0),
27
481
    UINT64_C(0),
28
481
    UINT64_C(0),
29
481
    UINT64_C(0),
30
481
    UINT64_C(0),
31
481
    UINT64_C(0),
32
481
    UINT64_C(0),
33
481
    UINT64_C(0),
34
481
    UINT64_C(0),
35
481
    UINT64_C(0),
36
481
    UINT64_C(0),
37
481
    UINT64_C(0),
38
481
    UINT64_C(0),
39
481
    UINT64_C(0),
40
481
    UINT64_C(0),
41
481
    UINT64_C(0),
42
481
    UINT64_C(0),
43
481
    UINT64_C(0),
44
481
    UINT64_C(0),
45
481
    UINT64_C(0),
46
481
    UINT64_C(0),
47
481
    UINT64_C(0),
48
481
    UINT64_C(0),
49
481
    UINT64_C(0),
50
481
    UINT64_C(0),
51
481
    UINT64_C(0),
52
481
    UINT64_C(0),
53
481
    UINT64_C(0),
54
481
    UINT64_C(0),
55
481
    UINT64_C(0),
56
481
    UINT64_C(0),
57
481
    UINT64_C(0),
58
481
    UINT64_C(0),
59
481
    UINT64_C(0),
60
481
    UINT64_C(0),
61
481
    UINT64_C(0),
62
481
    UINT64_C(0),
63
481
    UINT64_C(0),
64
481
    UINT64_C(0),
65
481
    UINT64_C(0),
66
481
    UINT64_C(0),
67
481
    UINT64_C(0),
68
481
    UINT64_C(0),
69
481
    UINT64_C(0),
70
481
    UINT64_C(0),
71
481
    UINT64_C(0),
72
481
    UINT64_C(0),
73
481
    UINT64_C(0),
74
481
    UINT64_C(0),
75
481
    UINT64_C(0),
76
481
    UINT64_C(0),
77
481
    UINT64_C(0),
78
481
    UINT64_C(0),
79
481
    UINT64_C(0),
80
481
    UINT64_C(0),
81
481
    UINT64_C(0),
82
481
    UINT64_C(0),
83
481
    UINT64_C(0),
84
481
    UINT64_C(0),
85
481
    UINT64_C(0),
86
481
    UINT64_C(0),
87
481
    UINT64_C(0),
88
481
    UINT64_C(0),
89
481
    UINT64_C(0),
90
481
    UINT64_C(0),
91
481
    UINT64_C(0),
92
481
    UINT64_C(0),
93
481
    UINT64_C(0),
94
481
    UINT64_C(0),
95
481
    UINT64_C(0),
96
481
    UINT64_C(0),
97
481
    UINT64_C(0),
98
481
    UINT64_C(0),
99
481
    UINT64_C(0),
100
481
    UINT64_C(0),
101
481
    UINT64_C(0),
102
481
    UINT64_C(0),
103
481
    UINT64_C(0),
104
481
    UINT64_C(0),
105
481
    UINT64_C(0),
106
481
    UINT64_C(0),
107
481
    UINT64_C(0),
108
481
    UINT64_C(0),
109
481
    UINT64_C(0),
110
481
    UINT64_C(0),
111
481
    UINT64_C(0),
112
481
    UINT64_C(0),
113
481
    UINT64_C(0),
114
481
    UINT64_C(0),
115
481
    UINT64_C(0),
116
481
    UINT64_C(0),
117
481
    UINT64_C(0),
118
481
    UINT64_C(0),
119
481
    UINT64_C(0),
120
481
    UINT64_C(0),
121
481
    UINT64_C(0),
122
481
    UINT64_C(0),
123
481
    UINT64_C(0),
124
481
    UINT64_C(0),
125
481
    UINT64_C(0),
126
481
    UINT64_C(0),
127
481
    UINT64_C(0),
128
481
    UINT64_C(0),
129
481
    UINT64_C(0),
130
481
    UINT64_C(0),
131
481
    UINT64_C(0),
132
481
    UINT64_C(0),
133
481
    UINT64_C(0),
134
481
    UINT64_C(0),
135
481
    UINT64_C(0),
136
481
    UINT64_C(0),
137
481
    UINT64_C(0),
138
481
    UINT64_C(0),
139
481
    UINT64_C(0),
140
481
    UINT64_C(0),
141
481
    UINT64_C(0),
142
481
    UINT64_C(0),
143
481
    UINT64_C(0),
144
481
    UINT64_C(0),
145
481
    UINT64_C(0),
146
481
    UINT64_C(0),
147
481
    UINT64_C(0),
148
481
    UINT64_C(0),
149
481
    UINT64_C(0),
150
481
    UINT64_C(0),
151
481
    UINT64_C(0),
152
481
    UINT64_C(0),
153
481
    UINT64_C(0),
154
481
    UINT64_C(0),
155
481
    UINT64_C(268632064),  // ADDC_F_I_HI
156
481
    UINT64_C(268566528),  // ADDC_F_I_LO
157
481
    UINT64_C(3221356800), // ADDC_F_R
158
481
    UINT64_C(268500992),  // ADDC_I_HI
159
481
    UINT64_C(268435456),  // ADDC_I_LO
160
481
    UINT64_C(3221225728), // ADDC_R
161
481
    UINT64_C(196608), // ADD_F_I_HI
162
481
    UINT64_C(131072), // ADD_F_I_LO
163
481
    UINT64_C(3221356544), // ADD_F_R
164
481
    UINT64_C(65536),  // ADD_I_HI
165
481
    UINT64_C(0),  // ADD_I_LO
166
481
    UINT64_C(3221225472), // ADD_R
167
481
    UINT64_C(1073938432), // AND_F_I_HI
168
481
    UINT64_C(1073872896), // AND_F_I_LO
169
481
    UINT64_C(3221357568), // AND_F_R
170
481
    UINT64_C(1073807360), // AND_I_HI
171
481
    UINT64_C(1073741824), // AND_I_LO
172
481
    UINT64_C(3221226496), // AND_R
173
481
    UINT64_C(3758096384), // BRCC
174
481
    UINT64_C(3238003968), // BRIND_CC
175
481
    UINT64_C(3238003968), // BRIND_CCA
176
481
    UINT64_C(3774873602), // BRR
177
481
    UINT64_C(3758096384), // BT
178
481
    UINT64_C(3238003968), // JR
179
481
    UINT64_C(4026531840), // LDADDR
180
481
    UINT64_C(4026744832), // LDBs_RI
181
481
    UINT64_C(2684354564), // LDBs_RR
182
481
    UINT64_C(4026748928), // LDBz_RI
183
481
    UINT64_C(2684354565), // LDBz_RR
184
481
    UINT64_C(4026728448), // LDHs_RI
185
481
    UINT64_C(2684354560), // LDHs_RR
186
481
    UINT64_C(4026732544), // LDHz_RI
187
481
    UINT64_C(2684354561), // LDHz_RR
188
481
    UINT64_C(2147483648), // LDW_RI
189
481
    UINT64_C(2684354562), // LDW_RR
190
481
    UINT64_C(2684354563), // LDWz_RR
191
481
    UINT64_C(3489660930), // LEADZ
192
481
    UINT64_C(2),  // LOG0
193
481
    UINT64_C(3),  // LOG1
194
481
    UINT64_C(4),  // LOG2
195
481
    UINT64_C(5),  // LOG3
196
481
    UINT64_C(6),  // LOG4
197
481
    UINT64_C(65536),  // MOVHI
198
481
    UINT64_C(1),  // NOP
199
481
    UINT64_C(1342373888), // OR_F_I_HI
200
481
    UINT64_C(1342308352), // OR_F_I_LO
201
481
    UINT64_C(3221357824), // OR_F_R
202
481
    UINT64_C(1342242816), // OR_I_HI
203
481
    UINT64_C(1342177280), // OR_I_LO
204
481
    UINT64_C(3221226752), // OR_R
205
481
    UINT64_C(3489660929), // POPC
206
481
    UINT64_C(2165768188), // RET
207
481
    UINT64_C(1879244800), // SA_F_I
208
481
    UINT64_C(1879113728), // SA_I
209
481
    UINT64_C(3758096386), // SCC
210
481
    UINT64_C(3221227264), // SELECT
211
481
    UINT64_C(537067520),  // SFSUB_F_RI_HI
212
481
    UINT64_C(537001984),  // SFSUB_F_RI_LO
213
481
    UINT64_C(3221357056), // SFSUB_F_RR
214
481
    UINT64_C(3221358464), // SHL_F_R
215
481
    UINT64_C(3221227392), // SHL_R
216
481
    UINT64_C(4026662912), // SLI
217
481
    UINT64_C(1879179264), // SL_F_I
218
481
    UINT64_C(1879048192), // SL_I
219
481
    UINT64_C(3221358528), // SRA_F_R
220
481
    UINT64_C(3221227456), // SRA_R
221
481
    UINT64_C(3221358464), // SRL_F_R
222
481
    UINT64_C(3221227392), // SRL_R
223
481
    UINT64_C(4026597376), // STADDR
224
481
    UINT64_C(4026753024), // STB_RI
225
481
    UINT64_C(2952790020), // STB_RR
226
481
    UINT64_C(4026736640), // STH_RI
227
481
    UINT64_C(2952790016), // STH_RR
228
481
    UINT64_C(805502976),  // SUBB_F_I_HI
229
481
    UINT64_C(805437440),  // SUBB_F_I_LO
230
481
    UINT64_C(3221357312), // SUBB_F_R
231
481
    UINT64_C(805371904),  // SUBB_I_HI
232
481
    UINT64_C(805306368),  // SUBB_I_LO
233
481
    UINT64_C(3221226240), // SUBB_R
234
481
    UINT64_C(537067520),  // SUB_F_I_HI
235
481
    UINT64_C(537001984),  // SUB_F_I_LO
236
481
    UINT64_C(3221357056), // SUB_F_R
237
481
    UINT64_C(536936448),  // SUB_I_HI
238
481
    UINT64_C(536870912),  // SUB_I_LO
239
481
    UINT64_C(3221225984), // SUB_R
240
481
    UINT64_C(2415919104), // SW_RI
241
481
    UINT64_C(2952790018), // SW_RR
242
481
    UINT64_C(3489660931), // TRAILZ
243
481
    UINT64_C(1610809344), // XOR_F_I_HI
244
481
    UINT64_C(1610743808), // XOR_F_I_LO
245
481
    UINT64_C(3221358080), // XOR_F_R
246
481
    UINT64_C(1610678272), // XOR_I_HI
247
481
    UINT64_C(1610612736), // XOR_I_LO
248
481
    UINT64_C(3221227008), // XOR_R
249
481
    UINT64_C(0)
250
481
  };
251
481
  const unsigned opcode = MI.getOpcode();
252
481
  uint64_t Value = InstBits[opcode];
253
481
  uint64_t op = 0;
254
481
  (void)op;  // suppress warning
255
481
  switch (opcode) {
256
481
    case Lanai::LOG0:
257
3
    case Lanai::LOG1:
258
3
    case Lanai::LOG2:
259
3
    case Lanai::LOG3:
260
3
    case Lanai::LOG4:
261
3
    case Lanai::NOP:
262
3
    case Lanai::RET: {
263
3
      break;
264
3
    }
265
20
    case Lanai::BRR: {
266
20
      // op: DDDI
267
20
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
268
20
      Value |= (op & UINT64_C(14)) << 24;
269
20
      Value |= op & UINT64_C(1);
270
20
      // op: imm16
271
20
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
272
20
      Value |= op & UINT64_C(65532);
273
20
      break;
274
3
    }
275
37
    case Lanai::STB_RI:
276
37
    case Lanai::STH_RI: {
277
37
      // op: Rd
278
37
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
279
37
      Value |= (op & UINT64_C(31)) << 23;
280
37
      // op: P
281
37
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
282
37
      Value |= (op & UINT64_C(1)) << 11;
283
37
      // op: Q
284
37
      op = getSplsOpValue(MI, 1, Fixups, STI);
285
37
      Value |= (op & UINT64_C(1)) << 10;
286
37
      // op: dst
287
37
      op = getSplsOpValue(MI, 1, Fixups, STI);
288
37
      Value |= (op & UINT64_C(126976)) << 6;
289
37
      Value |= op & UINT64_C(1023);
290
37
      Value = adjustPqBitsSpls(MI, Value, STI);
291
37
      break;
292
37
    }
293
65
    case Lanai::LDBs_RI:
294
65
    case Lanai::LDBz_RI:
295
65
    case Lanai::LDHs_RI:
296
65
    case Lanai::LDHz_RI: {
297
65
      // op: Rd
298
65
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
299
65
      Value |= (op & UINT64_C(31)) << 23;
300
65
      // op: P
301
65
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
302
65
      Value |= (op & UINT64_C(1)) << 11;
303
65
      // op: Q
304
65
      op = getSplsOpValue(MI, 1, Fixups, STI);
305
65
      Value |= (op & UINT64_C(1)) << 10;
306
65
      // op: src
307
65
      op = getSplsOpValue(MI, 1, Fixups, STI);
308
65
      Value |= (op & UINT64_C(126976)) << 6;
309
65
      Value |= op & UINT64_C(1023);
310
65
      Value = adjustPqBitsSpls(MI, Value, STI);
311
65
      break;
312
65
    }
313
65
    case Lanai::SW_RI: {
314
21
      // op: Rd
315
21
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
316
21
      Value |= (op & UINT64_C(31)) << 23;
317
21
      // op: P
318
21
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
319
21
      Value |= (op & UINT64_C(1)) << 17;
320
21
      // op: Q
321
21
      op = getRiMemoryOpValue(MI, 1, Fixups, STI);
322
21
      Value |= (op & UINT64_C(1)) << 16;
323
21
      // op: dst
324
21
      op = getRiMemoryOpValue(MI, 1, Fixups, STI);
325
21
      Value |= op & UINT64_C(8126464);
326
21
      Value |= op & UINT64_C(65535);
327
21
      Value = adjustPqBitsRmAndRrm(MI, Value, STI);
328
21
      break;
329
65
    }
330
65
    case Lanai::LDW_RI: {
331
44
      // op: Rd
332
44
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
333
44
      Value |= (op & UINT64_C(31)) << 23;
334
44
      // op: P
335
44
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
336
44
      Value |= (op & UINT64_C(1)) << 17;
337
44
      // op: Q
338
44
      op = getRiMemoryOpValue(MI, 1, Fixups, STI);
339
44
      Value |= (op & UINT64_C(1)) << 16;
340
44
      // op: src
341
44
      op = getRiMemoryOpValue(MI, 1, Fixups, STI);
342
44
      Value |= op & UINT64_C(8126464);
343
44
      Value |= op & UINT64_C(65535);
344
44
      Value = adjustPqBitsRmAndRrm(MI, Value, STI);
345
44
      break;
346
65
    }
347
88
    case Lanai::STB_RR:
348
88
    case Lanai::STH_RR:
349
88
    case Lanai::SW_RR: {
350
88
      // op: Rd
351
88
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
352
88
      Value |= (op & UINT64_C(31)) << 23;
353
88
      // op: P
354
88
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
355
88
      Value |= (op & UINT64_C(1)) << 17;
356
88
      // op: Q
357
88
      op = getRrMemoryOpValue(MI, 1, Fixups, STI);
358
88
      Value |= (op & UINT64_C(1)) << 16;
359
88
      // op: dst
360
88
      op = getRrMemoryOpValue(MI, 1, Fixups, STI);
361
88
      Value |= (op & UINT64_C(1015808)) << 3;
362
88
      Value |= (op & UINT64_C(31744)) << 1;
363
88
      Value |= (op & UINT64_C(255)) << 3;
364
88
      Value = adjustPqBitsRmAndRrm(MI, Value, STI);
365
88
      break;
366
88
    }
367
88
    case Lanai::LDBs_RR:
368
39
    case Lanai::LDBz_RR:
369
39
    case Lanai::LDHs_RR:
370
39
    case Lanai::LDHz_RR:
371
39
    case Lanai::LDW_RR:
372
39
    case Lanai::LDWz_RR: {
373
39
      // op: Rd
374
39
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
375
39
      Value |= (op & UINT64_C(31)) << 23;
376
39
      // op: P
377
39
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
378
39
      Value |= (op & UINT64_C(1)) << 17;
379
39
      // op: Q
380
39
      op = getRrMemoryOpValue(MI, 1, Fixups, STI);
381
39
      Value |= (op & UINT64_C(1)) << 16;
382
39
      // op: src
383
39
      op = getRrMemoryOpValue(MI, 1, Fixups, STI);
384
39
      Value |= (op & UINT64_C(1015808)) << 3;
385
39
      Value |= (op & UINT64_C(31744)) << 1;
386
39
      Value |= (op & UINT64_C(255)) << 3;
387
39
      Value = adjustPqBitsRmAndRrm(MI, Value, STI);
388
39
      break;
389
39
    }
390
39
    case Lanai::LEADZ:
391
3
    case Lanai::POPC:
392
3
    case Lanai::TRAILZ: {
393
3
      // op: Rd
394
3
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
395
3
      Value |= (op & UINT64_C(31)) << 23;
396
3
      // op: Rs1
397
3
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
398
3
      Value |= (op & UINT64_C(31)) << 18;
399
3
      break;
400
3
    }
401
42
    case Lanai::ADDC_F_R:
402
42
    case Lanai::ADDC_R:
403
42
    case Lanai::ADD_F_R:
404
42
    case Lanai::ADD_R:
405
42
    case Lanai::AND_F_R:
406
42
    case Lanai::AND_R:
407
42
    case Lanai::OR_F_R:
408
42
    case Lanai::OR_R:
409
42
    case Lanai::SELECT:
410
42
    case Lanai::SHL_F_R:
411
42
    case Lanai::SHL_R:
412
42
    case Lanai::SRA_F_R:
413
42
    case Lanai::SRA_R:
414
42
    case Lanai::SRL_F_R:
415
42
    case Lanai::SRL_R:
416
42
    case Lanai::SUBB_F_R:
417
42
    case Lanai::SUBB_R:
418
42
    case Lanai::SUB_F_R:
419
42
    case Lanai::SUB_R:
420
42
    case Lanai::XOR_F_R:
421
42
    case Lanai::XOR_R: {
422
42
      // op: Rd
423
42
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
424
42
      Value |= (op & UINT64_C(31)) << 23;
425
42
      // op: Rs1
426
42
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
427
42
      Value |= (op & UINT64_C(31)) << 18;
428
42
      // op: Rs2
429
42
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
430
42
      Value |= (op & UINT64_C(31)) << 11;
431
42
      // op: DDDI
432
42
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
433
42
      Value |= (op & UINT64_C(1)) << 16;
434
42
      Value |= (op & UINT64_C(14)) >> 1;
435
42
      break;
436
42
    }
437
64
    case Lanai::ADDC_F_I_HI:
438
64
    case Lanai::ADDC_F_I_LO:
439
64
    case Lanai::ADDC_I_HI:
440
64
    case Lanai::ADDC_I_LO:
441
64
    case Lanai::ADD_F_I_HI:
442
64
    case Lanai::ADD_F_I_LO:
443
64
    case Lanai::ADD_I_HI:
444
64
    case Lanai::ADD_I_LO:
445
64
    case Lanai::AND_F_I_HI:
446
64
    case Lanai::AND_F_I_LO:
447
64
    case Lanai::AND_I_HI:
448
64
    case Lanai::AND_I_LO:
449
64
    case Lanai::OR_F_I_HI:
450
64
    case Lanai::OR_F_I_LO:
451
64
    case Lanai::OR_I_HI:
452
64
    case Lanai::OR_I_LO:
453
64
    case Lanai::SA_F_I:
454
64
    case Lanai::SA_I:
455
64
    case Lanai::SL_F_I:
456
64
    case Lanai::SL_I:
457
64
    case Lanai::SUBB_F_I_HI:
458
64
    case Lanai::SUBB_F_I_LO:
459
64
    case Lanai::SUBB_I_HI:
460
64
    case Lanai::SUBB_I_LO:
461
64
    case Lanai::SUB_F_I_HI:
462
64
    case Lanai::SUB_F_I_LO:
463
64
    case Lanai::SUB_I_HI:
464
64
    case Lanai::SUB_I_LO:
465
64
    case Lanai::XOR_F_I_HI:
466
64
    case Lanai::XOR_F_I_LO:
467
64
    case Lanai::XOR_I_HI:
468
64
    case Lanai::XOR_I_LO: {
469
64
      // op: Rd
470
64
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
471
64
      Value |= (op & UINT64_C(31)) << 23;
472
64
      // op: Rs1
473
64
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
474
64
      Value |= (op & UINT64_C(31)) << 18;
475
64
      // op: imm16
476
64
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
477
64
      Value |= op & UINT64_C(65535);
478
64
      break;
479
64
    }
480
64
    case Lanai::STADDR: {
481
2
      // op: Rd
482
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
483
2
      Value |= (op & UINT64_C(31)) << 23;
484
2
      // op: dst
485
2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
486
2
      Value |= (op & UINT64_C(2031616)) << 2;
487
2
      Value |= op & UINT64_C(65535);
488
2
      break;
489
64
    }
490
64
    case Lanai::SLI: {
491
1
      // op: Rd
492
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
493
1
      Value |= (op & UINT64_C(31)) << 23;
494
1
      // op: imm
495
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
496
1
      Value |= (op & UINT64_C(2031616)) << 2;
497
1
      Value |= op & UINT64_C(65535);
498
1
      break;
499
64
    }
500
64
    case Lanai::MOVHI: {
501
0
      // op: Rd
502
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
503
0
      Value |= (op & UINT64_C(31)) << 23;
504
0
      // op: imm16
505
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
506
0
      Value |= op & UINT64_C(65535);
507
0
      break;
508
64
    }
509
64
    case Lanai::LDADDR: {
510
3
      // op: Rd
511
3
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
512
3
      Value |= (op & UINT64_C(31)) << 23;
513
3
      // op: src
514
3
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
515
3
      Value |= (op & UINT64_C(2031616)) << 2;
516
3
      Value |= op & UINT64_C(65535);
517
3
      break;
518
64
    }
519
64
    case Lanai::BRIND_CC: {
520
0
      // op: Rs1
521
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
522
0
      Value |= (op & UINT64_C(31)) << 18;
523
0
      // op: DDDI
524
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
525
0
      Value |= (op & UINT64_C(1)) << 16;
526
0
      Value |= (op & UINT64_C(14)) >> 1;
527
0
      break;
528
64
    }
529
64
    case Lanai::SCC: {
530
20
      // op: Rs1
531
20
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
532
20
      Value |= (op & UINT64_C(31)) << 18;
533
20
      // op: DDDI
534
20
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
535
20
      Value |= (op & UINT64_C(14)) << 24;
536
20
      Value |= op & UINT64_C(1);
537
20
      break;
538
64
    }
539
64
    case Lanai::SFSUB_F_RR: {
540
0
      // op: Rs1
541
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
542
0
      Value |= (op & UINT64_C(31)) << 18;
543
0
      // op: Rs2
544
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
545
0
      Value |= (op & UINT64_C(31)) << 11;
546
0
      break;
547
64
    }
548
64
    case Lanai::BRIND_CCA: {
549
0
      // op: Rs1
550
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
551
0
      Value |= (op & UINT64_C(31)) << 18;
552
0
      // op: Rs2
553
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
554
0
      Value |= (op & UINT64_C(31)) << 11;
555
0
      // op: DDDI
556
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
557
0
      Value |= (op & UINT64_C(1)) << 16;
558
0
      Value |= (op & UINT64_C(14)) >> 1;
559
0
      break;
560
64
    }
561
64
    case Lanai::SFSUB_F_RI_HI:
562
0
    case Lanai::SFSUB_F_RI_LO: {
563
0
      // op: Rs1
564
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
565
0
      Value |= (op & UINT64_C(31)) << 18;
566
0
      // op: imm16
567
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
568
0
      Value |= op & UINT64_C(65535);
569
0
      break;
570
0
    }
571
2
    case Lanai::JR: {
572
2
      // op: Rs2
573
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
574
2
      Value |= (op & UINT64_C(31)) << 11;
575
2
      break;
576
0
    }
577
6
    case Lanai::BT: {
578
6
      // op: addr
579
6
      op = getBranchTargetOpValue(MI, 0, Fixups, STI);
580
6
      Value |= op & UINT64_C(33554428);
581
6
      break;
582
0
    }
583
21
    case Lanai::BRCC: {
584
21
      // op: addr
585
21
      op = getBranchTargetOpValue(MI, 0, Fixups, STI);
586
21
      Value |= op & UINT64_C(33554428);
587
21
      // op: DDDI
588
21
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
589
21
      Value |= (op & UINT64_C(14)) << 24;
590
21
      Value |= op & UINT64_C(1);
591
21
      break;
592
0
    }
593
0
  default:
594
0
    std::string msg;
595
0
    raw_string_ostream Msg(msg);
596
0
    Msg << "Not supported instr: " << MI;
597
0
    report_fatal_error(Msg.str());
598
481
  }
599
481
  return Value;
600
481
}
601
602
#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
603
#undef ENABLE_INSTR_PREDICATE_VERIFIER
604
#include <sstream>
605
606
// Flags for subtarget features that participate in instruction matching.
607
enum SubtargetFeatureFlag : uint8_t {
608
  Feature_None = 0
609
};
610
611
#ifndef NDEBUG
612
static const char *SubtargetFeatureNames[] = {
613
  nullptr
614
};
615
616
#endif // NDEBUG
617
uint64_t LanaiMCCodeEmitter::
618
computeAvailableFeatures(const FeatureBitset& FB) const {
619
  uint64_t Features = 0;
620
  return Features;
621
}
622
623
void LanaiMCCodeEmitter::verifyInstructionPredicates(
624
    const MCInst &Inst, uint64_t AvailableFeatures) const {
625
#ifndef NDEBUG
626
  static uint64_t RequiredFeatures[] = {
627
    0, // PHI = 0
628
    0, // INLINEASM = 1
629
    0, // CFI_INSTRUCTION = 2
630
    0, // EH_LABEL = 3
631
    0, // GC_LABEL = 4
632
    0, // ANNOTATION_LABEL = 5
633
    0, // KILL = 6
634
    0, // EXTRACT_SUBREG = 7
635
    0, // INSERT_SUBREG = 8
636
    0, // IMPLICIT_DEF = 9
637
    0, // SUBREG_TO_REG = 10
638
    0, // COPY_TO_REGCLASS = 11
639
    0, // DBG_VALUE = 12
640
    0, // DBG_LABEL = 13
641
    0, // REG_SEQUENCE = 14
642
    0, // COPY = 15
643
    0, // BUNDLE = 16
644
    0, // LIFETIME_START = 17
645
    0, // LIFETIME_END = 18
646
    0, // STACKMAP = 19
647
    0, // FENTRY_CALL = 20
648
    0, // PATCHPOINT = 21
649
    0, // LOAD_STACK_GUARD = 22
650
    0, // STATEPOINT = 23
651
    0, // LOCAL_ESCAPE = 24
652
    0, // FAULTING_OP = 25
653
    0, // PATCHABLE_OP = 26
654
    0, // PATCHABLE_FUNCTION_ENTER = 27
655
    0, // PATCHABLE_RET = 28
656
    0, // PATCHABLE_FUNCTION_EXIT = 29
657
    0, // PATCHABLE_TAIL_CALL = 30
658
    0, // PATCHABLE_EVENT_CALL = 31
659
    0, // PATCHABLE_TYPED_EVENT_CALL = 32
660
    0, // ICALL_BRANCH_FUNNEL = 33
661
    0, // G_ADD = 34
662
    0, // G_SUB = 35
663
    0, // G_MUL = 36
664
    0, // G_SDIV = 37
665
    0, // G_UDIV = 38
666
    0, // G_SREM = 39
667
    0, // G_UREM = 40
668
    0, // G_AND = 41
669
    0, // G_OR = 42
670
    0, // G_XOR = 43
671
    0, // G_IMPLICIT_DEF = 44
672
    0, // G_PHI = 45
673
    0, // G_FRAME_INDEX = 46
674
    0, // G_GLOBAL_VALUE = 47
675
    0, // G_EXTRACT = 48
676
    0, // G_UNMERGE_VALUES = 49
677
    0, // G_INSERT = 50
678
    0, // G_MERGE_VALUES = 51
679
    0, // G_PTRTOINT = 52
680
    0, // G_INTTOPTR = 53
681
    0, // G_BITCAST = 54
682
    0, // G_INTRINSIC_TRUNC = 55
683
    0, // G_INTRINSIC_ROUND = 56
684
    0, // G_LOAD = 57
685
    0, // G_SEXTLOAD = 58
686
    0, // G_ZEXTLOAD = 59
687
    0, // G_STORE = 60
688
    0, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 61
689
    0, // G_ATOMIC_CMPXCHG = 62
690
    0, // G_ATOMICRMW_XCHG = 63
691
    0, // G_ATOMICRMW_ADD = 64
692
    0, // G_ATOMICRMW_SUB = 65
693
    0, // G_ATOMICRMW_AND = 66
694
    0, // G_ATOMICRMW_NAND = 67
695
    0, // G_ATOMICRMW_OR = 68
696
    0, // G_ATOMICRMW_XOR = 69
697
    0, // G_ATOMICRMW_MAX = 70
698
    0, // G_ATOMICRMW_MIN = 71
699
    0, // G_ATOMICRMW_UMAX = 72
700
    0, // G_ATOMICRMW_UMIN = 73
701
    0, // G_BRCOND = 74
702
    0, // G_BRINDIRECT = 75
703
    0, // G_INTRINSIC = 76
704
    0, // G_INTRINSIC_W_SIDE_EFFECTS = 77
705
    0, // G_ANYEXT = 78
706
    0, // G_TRUNC = 79
707
    0, // G_CONSTANT = 80
708
    0, // G_FCONSTANT = 81
709
    0, // G_VASTART = 82
710
    0, // G_VAARG = 83
711
    0, // G_SEXT = 84
712
    0, // G_ZEXT = 85
713
    0, // G_SHL = 86
714
    0, // G_LSHR = 87
715
    0, // G_ASHR = 88
716
    0, // G_ICMP = 89
717
    0, // G_FCMP = 90
718
    0, // G_SELECT = 91
719
    0, // G_UADDO = 92
720
    0, // G_UADDE = 93
721
    0, // G_USUBO = 94
722
    0, // G_USUBE = 95
723
    0, // G_SADDO = 96
724
    0, // G_SADDE = 97
725
    0, // G_SSUBO = 98
726
    0, // G_SSUBE = 99
727
    0, // G_UMULO = 100
728
    0, // G_SMULO = 101
729
    0, // G_UMULH = 102
730
    0, // G_SMULH = 103
731
    0, // G_FADD = 104
732
    0, // G_FSUB = 105
733
    0, // G_FMUL = 106
734
    0, // G_FMA = 107
735
    0, // G_FDIV = 108
736
    0, // G_FREM = 109
737
    0, // G_FPOW = 110
738
    0, // G_FEXP = 111
739
    0, // G_FEXP2 = 112
740
    0, // G_FLOG = 113
741
    0, // G_FLOG2 = 114
742
    0, // G_FNEG = 115
743
    0, // G_FPEXT = 116
744
    0, // G_FPTRUNC = 117
745
    0, // G_FPTOSI = 118
746
    0, // G_FPTOUI = 119
747
    0, // G_SITOFP = 120
748
    0, // G_UITOFP = 121
749
    0, // G_FABS = 122
750
    0, // G_GEP = 123
751
    0, // G_PTR_MASK = 124
752
    0, // G_BR = 125
753
    0, // G_INSERT_VECTOR_ELT = 126
754
    0, // G_EXTRACT_VECTOR_ELT = 127
755
    0, // G_SHUFFLE_VECTOR = 128
756
    0, // G_CTTZ = 129
757
    0, // G_CTTZ_ZERO_UNDEF = 130
758
    0, // G_CTLZ = 131
759
    0, // G_CTLZ_ZERO_UNDEF = 132
760
    0, // G_CTPOP = 133
761
    0, // G_BSWAP = 134
762
    0, // G_ADDRSPACE_CAST = 135
763
    0, // G_BLOCK_ADDR = 136
764
    0, // ADJCALLSTACKDOWN = 137
765
    0, // ADJCALLSTACKUP = 138
766
    0, // ADJDYNALLOC = 139
767
    0, // CALL = 140
768
    0, // CALLR = 141
769
    0, // ADDC_F_I_HI = 142
770
    0, // ADDC_F_I_LO = 143
771
    0, // ADDC_F_R = 144
772
    0, // ADDC_I_HI = 145
773
    0, // ADDC_I_LO = 146
774
    0, // ADDC_R = 147
775
    0, // ADD_F_I_HI = 148
776
    0, // ADD_F_I_LO = 149
777
    0, // ADD_F_R = 150
778
    0, // ADD_I_HI = 151
779
    0, // ADD_I_LO = 152
780
    0, // ADD_R = 153
781
    0, // AND_F_I_HI = 154
782
    0, // AND_F_I_LO = 155
783
    0, // AND_F_R = 156
784
    0, // AND_I_HI = 157
785
    0, // AND_I_LO = 158
786
    0, // AND_R = 159
787
    0, // BRCC = 160
788
    0, // BRIND_CC = 161
789
    0, // BRIND_CCA = 162
790
    0, // BRR = 163
791
    0, // BT = 164
792
    0, // JR = 165
793
    0, // LDADDR = 166
794
    0, // LDBs_RI = 167
795
    0, // LDBs_RR = 168
796
    0, // LDBz_RI = 169
797
    0, // LDBz_RR = 170
798
    0, // LDHs_RI = 171
799
    0, // LDHs_RR = 172
800
    0, // LDHz_RI = 173
801
    0, // LDHz_RR = 174
802
    0, // LDW_RI = 175
803
    0, // LDW_RR = 176
804
    0, // LDWz_RR = 177
805
    0, // LEADZ = 178
806
    0, // LOG0 = 179
807
    0, // LOG1 = 180
808
    0, // LOG2 = 181
809
    0, // LOG3 = 182
810
    0, // LOG4 = 183
811
    0, // MOVHI = 184
812
    0, // NOP = 185
813
    0, // OR_F_I_HI = 186
814
    0, // OR_F_I_LO = 187
815
    0, // OR_F_R = 188
816
    0, // OR_I_HI = 189
817
    0, // OR_I_LO = 190
818
    0, // OR_R = 191
819
    0, // POPC = 192
820
    0, // RET = 193
821
    0, // SA_F_I = 194
822
    0, // SA_I = 195
823
    0, // SCC = 196
824
    0, // SELECT = 197
825
    0, // SFSUB_F_RI_HI = 198
826
    0, // SFSUB_F_RI_LO = 199
827
    0, // SFSUB_F_RR = 200
828
    0, // SHL_F_R = 201
829
    0, // SHL_R = 202
830
    0, // SLI = 203
831
    0, // SL_F_I = 204
832
    0, // SL_I = 205
833
    0, // SRA_F_R = 206
834
    0, // SRA_R = 207
835
    0, // SRL_F_R = 208
836
    0, // SRL_R = 209
837
    0, // STADDR = 210
838
    0, // STB_RI = 211
839
    0, // STB_RR = 212
840
    0, // STH_RI = 213
841
    0, // STH_RR = 214
842
    0, // SUBB_F_I_HI = 215
843
    0, // SUBB_F_I_LO = 216
844
    0, // SUBB_F_R = 217
845
    0, // SUBB_I_HI = 218
846
    0, // SUBB_I_LO = 219
847
    0, // SUBB_R = 220
848
    0, // SUB_F_I_HI = 221
849
    0, // SUB_F_I_LO = 222
850
    0, // SUB_F_R = 223
851
    0, // SUB_I_HI = 224
852
    0, // SUB_I_LO = 225
853
    0, // SUB_R = 226
854
    0, // SW_RI = 227
855
    0, // SW_RR = 228
856
    0, // TRAILZ = 229
857
    0, // XOR_F_I_HI = 230
858
    0, // XOR_F_I_LO = 231
859
    0, // XOR_F_R = 232
860
    0, // XOR_I_HI = 233
861
    0, // XOR_I_LO = 234
862
    0, // XOR_R = 235
863
  };
864
865
  assert(Inst.getOpcode() < 236);
866
  uint64_t MissingFeatures =
867
      (AvailableFeatures & RequiredFeatures[Inst.getOpcode()]) ^
868
      RequiredFeatures[Inst.getOpcode()];
869
  if (MissingFeatures) {
870
    std::ostringstream Msg;
871
    Msg << "Attempting to emit " << MCII.getName(Inst.getOpcode()).str()
872
        << " instruction but the ";
873
    for (unsigned i = 0; i < 8 * sizeof(MissingFeatures); ++i)
874
      if (MissingFeatures & (1ULL << i))
875
        Msg << SubtargetFeatureNames[i] << " ";
876
    Msg << "predicate(s) are not met";
877
    report_fatal_error(Msg.str());
878
  }
879
#else
880
// Silence unused variable warning on targets that don't use MCII for other purposes (e.g. BPF).
881
(void)MCII;
882
#endif // NDEBUG
883
}
884
#endif