Coverage Report

Created: 2018-12-11 00:00

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Lanai/LanaiGenRegisterInfo.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
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|* Target Register Enum Values                                                *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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9
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#ifdef GET_REGINFO_ENUM
11
#undef GET_REGINFO_ENUM
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13
namespace llvm {
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15
class MCRegisterClass;
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extern const MCRegisterClass LanaiMCRegisterClasses[];
17
18
namespace Lanai {
19
enum {
20
  NoRegister,
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  FP = 1,
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  PC = 2,
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  RCA = 3,
24
  RV = 4,
25
  SP = 5,
26
  SR = 6,
27
  R0 = 7,
28
  R1 = 8,
29
  R2 = 9,
30
  R3 = 10,
31
  R4 = 11,
32
  R5 = 12,
33
  R6 = 13,
34
  R7 = 14,
35
  R8 = 15,
36
  R9 = 16,
37
  R10 = 17,
38
  R11 = 18,
39
  R12 = 19,
40
  R13 = 20,
41
  R14 = 21,
42
  R15 = 22,
43
  R16 = 23,
44
  R17 = 24,
45
  R18 = 25,
46
  R19 = 26,
47
  R20 = 27,
48
  R21 = 28,
49
  R22 = 29,
50
  R23 = 30,
51
  R24 = 31,
52
  R25 = 32,
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  R26 = 33,
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  R27 = 34,
55
  R28 = 35,
56
  R29 = 36,
57
  R30 = 37,
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  R31 = 38,
59
  RR1 = 39,
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  RR2 = 40,
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  NUM_TARGET_REGS   // 41
62
};
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} // end namespace Lanai
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// Register classes
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namespace Lanai {
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enum {
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  GPRRegClassID = 0,
70
  GPR_with_sub_32RegClassID = 1,
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  CCRRegClassID = 2,
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73
  };
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} // end namespace Lanai
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// Subregister indices
78
79
namespace Lanai {
80
enum {
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  NoSubRegister,
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  sub_32, // 1
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  NUM_TARGET_SUBREGS
84
};
85
} // end namespace Lanai
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87
} // end namespace llvm
88
89
#endif // GET_REGINFO_ENUM
90
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
92
|*                                                                            *|
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|* MC Register Information                                                    *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
97
\*===----------------------------------------------------------------------===*/
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#ifdef GET_REGINFO_MC_DESC
101
#undef GET_REGINFO_MC_DESC
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103
namespace llvm {
104
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extern const MCPhysReg LanaiRegDiffLists[] = {
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  /* 0 */ 4, 0,
107
  /* 2 */ 6, 0,
108
  /* 4 */ 7, 0,
109
  /* 6 */ 11, 0,
110
  /* 8 */ 19, 0,
111
  /* 10 */ 22, 0,
112
  /* 12 */ 65208, 0,
113
  /* 14 */ 65419, 0,
114
  /* 16 */ 65428, 0,
115
  /* 18 */ 65474, 0,
116
  /* 20 */ 65509, 0,
117
  /* 22 */ 65514, 0,
118
  /* 24 */ 65517, 0,
119
  /* 26 */ 65525, 0,
120
  /* 28 */ 65529, 0,
121
  /* 30 */ 65530, 0,
122
  /* 32 */ 65531, 0,
123
  /* 34 */ 65532, 0,
124
  /* 36 */ 65535, 0,
125
};
126
127
extern const LaneBitmask LanaiLaneMaskLists[] = {
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  /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
129
  /* 2 */ LaneBitmask(0x00000001), LaneBitmask::getAll(),
130
};
131
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extern const uint16_t LanaiSubRegIdxLists[] = {
133
  /* 0 */ 1, 0,
134
};
135
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extern const MCRegisterInfo::SubRegCoveredBits LanaiSubRegIdxRanges[] = {
137
  { 65535, 65535 },
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  { 0, 32 },  // sub_32
139
};
140
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extern const char LanaiRegStrings[] = {
142
  /* 0 */ 'R', '1', '0', 0,
143
  /* 4 */ 'R', '2', '0', 0,
144
  /* 8 */ 'R', '3', '0', 0,
145
  /* 12 */ 'R', '0', 0,
146
  /* 15 */ 'R', '1', '1', 0,
147
  /* 19 */ 'R', '2', '1', 0,
148
  /* 23 */ 'R', '3', '1', 0,
149
  /* 27 */ 'R', 'R', '1', 0,
150
  /* 31 */ 'R', '1', '2', 0,
151
  /* 35 */ 'R', '2', '2', 0,
152
  /* 39 */ 'R', 'R', '2', 0,
153
  /* 43 */ 'R', '1', '3', 0,
154
  /* 47 */ 'R', '2', '3', 0,
155
  /* 51 */ 'R', '3', 0,
156
  /* 54 */ 'R', '1', '4', 0,
157
  /* 58 */ 'R', '2', '4', 0,
158
  /* 62 */ 'R', '4', 0,
159
  /* 65 */ 'R', '1', '5', 0,
160
  /* 69 */ 'R', '2', '5', 0,
161
  /* 73 */ 'R', '5', 0,
162
  /* 76 */ 'R', '1', '6', 0,
163
  /* 80 */ 'R', '2', '6', 0,
164
  /* 84 */ 'R', '6', 0,
165
  /* 87 */ 'R', '1', '7', 0,
166
  /* 91 */ 'R', '2', '7', 0,
167
  /* 95 */ 'R', '7', 0,
168
  /* 98 */ 'R', '1', '8', 0,
169
  /* 102 */ 'R', '2', '8', 0,
170
  /* 106 */ 'R', '8', 0,
171
  /* 109 */ 'R', '1', '9', 0,
172
  /* 113 */ 'R', '2', '9', 0,
173
  /* 117 */ 'R', '9', 0,
174
  /* 120 */ 'R', 'C', 'A', 0,
175
  /* 124 */ 'P', 'C', 0,
176
  /* 127 */ 'F', 'P', 0,
177
  /* 130 */ 'S', 'P', 0,
178
  /* 133 */ 'S', 'R', 0,
179
  /* 136 */ 'R', 'V', 0,
180
};
181
182
extern const MCRegisterDesc LanaiRegDesc[] = { // Descriptors
183
  { 3, 0, 0, 0, 0, 0 },
184
  { 127, 6, 1, 0, 577, 2 },
185
  { 124, 4, 1, 0, 577, 2 },
186
  { 120, 8, 1, 0, 577, 2 },
187
  { 136, 6, 1, 0, 577, 2 },
188
  { 130, 2, 1, 0, 577, 2 },
189
  { 133, 1, 1, 1, 577, 0 },
190
  { 12, 1, 1, 1, 577, 0 },
191
  { 28, 1, 1, 1, 577, 0 },
192
  { 40, 1, 28, 1, 295, 0 },
193
  { 51, 1, 1, 1, 295, 0 },
194
  { 62, 1, 30, 1, 0, 0 },
195
  { 73, 1, 26, 1, 265, 0 },
196
  { 84, 1, 1, 1, 545, 0 },
197
  { 95, 1, 1, 1, 545, 0 },
198
  { 106, 1, 26, 1, 232, 0 },
199
  { 117, 1, 1, 1, 513, 0 },
200
  { 0, 1, 10, 1, 513, 0 },
201
  { 15, 1, 10, 1, 513, 0 },
202
  { 31, 1, 1, 1, 513, 0 },
203
  { 43, 1, 1, 1, 513, 0 },
204
  { 54, 1, 1, 1, 513, 0 },
205
  { 65, 1, 24, 1, 207, 0 },
206
  { 76, 1, 1, 1, 481, 0 },
207
  { 87, 1, 1, 1, 481, 0 },
208
  { 98, 1, 1, 1, 481, 0 },
209
  { 109, 1, 1, 1, 481, 0 },
210
  { 4, 1, 1, 1, 481, 0 },
211
  { 19, 1, 1, 1, 481, 0 },
212
  { 35, 1, 1, 1, 481, 0 },
213
  { 47, 1, 1, 1, 481, 0 },
214
  { 58, 1, 1, 1, 481, 0 },
215
  { 69, 1, 1, 1, 481, 0 },
216
  { 80, 1, 1, 1, 481, 0 },
217
  { 91, 1, 1, 1, 481, 0 },
218
  { 102, 1, 1, 1, 481, 0 },
219
  { 113, 1, 1, 1, 481, 0 },
220
  { 8, 1, 1, 1, 481, 0 },
221
  { 23, 1, 1, 1, 481, 0 },
222
  { 27, 22, 1, 0, 321, 2 },
223
  { 39, 22, 1, 0, 321, 2 },
224
};
225
226
extern const MCPhysReg LanaiRegUnitRoots[][2] = {
227
  { Lanai::R5 },
228
  { Lanai::R2 },
229
  { Lanai::R15 },
230
  { Lanai::R8 },
231
  { Lanai::R4 },
232
  { Lanai::SR },
233
  { Lanai::R0 },
234
  { Lanai::R1 },
235
  { Lanai::R3 },
236
  { Lanai::R6 },
237
  { Lanai::R7 },
238
  { Lanai::R9 },
239
  { Lanai::R10 },
240
  { Lanai::R11 },
241
  { Lanai::R12 },
242
  { Lanai::R13 },
243
  { Lanai::R14 },
244
  { Lanai::R16 },
245
  { Lanai::R17 },
246
  { Lanai::R18 },
247
  { Lanai::R19 },
248
  { Lanai::R20 },
249
  { Lanai::R21 },
250
  { Lanai::R22 },
251
  { Lanai::R23 },
252
  { Lanai::R24 },
253
  { Lanai::R25 },
254
  { Lanai::R26 },
255
  { Lanai::R27 },
256
  { Lanai::R28 },
257
  { Lanai::R29 },
258
  { Lanai::R30 },
259
  { Lanai::R31 },
260
};
261
262
namespace {     // Register classes...
263
  // GPR Register Class...
264
  const MCPhysReg GPR[] = {
265
    Lanai::R3, Lanai::R9, Lanai::R12, Lanai::R13, Lanai::R14, Lanai::R16, Lanai::R17, Lanai::R20, Lanai::R21, Lanai::R22, Lanai::R23, Lanai::R24, Lanai::R25, Lanai::R26, Lanai::R27, Lanai::R28, Lanai::R29, Lanai::R30, Lanai::R31, Lanai::R6, Lanai::R7, Lanai::R18, Lanai::R19, Lanai::R15, Lanai::RCA, Lanai::R10, Lanai::RR1, Lanai::R11, Lanai::RR2, Lanai::R8, Lanai::RV, Lanai::R5, Lanai::FP, Lanai::R4, Lanai::SP, Lanai::R2, Lanai::PC, Lanai::R1, Lanai::R0, 
266
  };
267
268
  // GPR Bit set.
269
  const uint8_t GPRBits[] = {
270
    0xbe, 0xff, 0xff, 0xff, 0xff, 0x01, 
271
  };
272
273
  // GPR_with_sub_32 Register Class...
274
  const MCPhysReg GPR_with_sub_32[] = {
275
    Lanai::RCA, Lanai::RR1, Lanai::RR2, Lanai::RV, Lanai::FP, Lanai::SP, Lanai::PC, 
276
  };
277
278
  // GPR_with_sub_32 Bit set.
279
  const uint8_t GPR_with_sub_32Bits[] = {
280
    0x3e, 0x00, 0x00, 0x00, 0x80, 0x01, 
281
  };
282
283
  // CCR Register Class...
284
  const MCPhysReg CCR[] = {
285
    Lanai::SR, 
286
  };
287
288
  // CCR Bit set.
289
  const uint8_t CCRBits[] = {
290
    0x40, 
291
  };
292
293
} // end anonymous namespace
294
295
extern const char LanaiRegClassStrings[] = {
296
  /* 0 */ 'G', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 0,
297
  /* 16 */ 'C', 'C', 'R', 0,
298
  /* 20 */ 'G', 'P', 'R', 0,
299
};
300
301
extern const MCRegisterClass LanaiMCRegisterClasses[] = {
302
  { GPR, GPRBits, 20, 39, sizeof(GPRBits), Lanai::GPRRegClassID, 1, true },
303
  { GPR_with_sub_32, GPR_with_sub_32Bits, 0, 7, sizeof(GPR_with_sub_32Bits), Lanai::GPR_with_sub_32RegClassID, 1, true },
304
  { CCR, CCRBits, 16, 1, sizeof(CCRBits), Lanai::CCRRegClassID, -1, false },
305
};
306
307
// Lanai Dwarf<->LLVM register mappings.
308
extern const MCRegisterInfo::DwarfLLVMRegPair LanaiDwarfFlavour0Dwarf2L[] = {
309
  { 0U, Lanai::R0 },
310
  { 1U, Lanai::R1 },
311
  { 2U, Lanai::R2 },
312
  { 3U, Lanai::R3 },
313
  { 4U, Lanai::R4 },
314
  { 5U, Lanai::R5 },
315
  { 6U, Lanai::R6 },
316
  { 7U, Lanai::R7 },
317
  { 8U, Lanai::R8 },
318
  { 9U, Lanai::R9 },
319
  { 10U, Lanai::R10 },
320
  { 11U, Lanai::R11 },
321
  { 12U, Lanai::R12 },
322
  { 13U, Lanai::R13 },
323
  { 14U, Lanai::R14 },
324
  { 15U, Lanai::R15 },
325
  { 16U, Lanai::R16 },
326
  { 17U, Lanai::R17 },
327
  { 18U, Lanai::R18 },
328
  { 19U, Lanai::R19 },
329
  { 20U, Lanai::R20 },
330
  { 21U, Lanai::R21 },
331
  { 22U, Lanai::R22 },
332
  { 23U, Lanai::R23 },
333
  { 24U, Lanai::R24 },
334
  { 25U, Lanai::R25 },
335
  { 26U, Lanai::R26 },
336
  { 27U, Lanai::R27 },
337
  { 28U, Lanai::R28 },
338
  { 29U, Lanai::R29 },
339
  { 30U, Lanai::R30 },
340
  { 31U, Lanai::R31 },
341
};
342
extern const unsigned LanaiDwarfFlavour0Dwarf2LSize = array_lengthof(LanaiDwarfFlavour0Dwarf2L);
343
344
extern const MCRegisterInfo::DwarfLLVMRegPair LanaiEHFlavour0Dwarf2L[] = {
345
  { 0U, Lanai::R0 },
346
  { 1U, Lanai::R1 },
347
  { 2U, Lanai::R2 },
348
  { 3U, Lanai::R3 },
349
  { 4U, Lanai::R4 },
350
  { 5U, Lanai::R5 },
351
  { 6U, Lanai::R6 },
352
  { 7U, Lanai::R7 },
353
  { 8U, Lanai::R8 },
354
  { 9U, Lanai::R9 },
355
  { 10U, Lanai::R10 },
356
  { 11U, Lanai::R11 },
357
  { 12U, Lanai::R12 },
358
  { 13U, Lanai::R13 },
359
  { 14U, Lanai::R14 },
360
  { 15U, Lanai::R15 },
361
  { 16U, Lanai::R16 },
362
  { 17U, Lanai::R17 },
363
  { 18U, Lanai::R18 },
364
  { 19U, Lanai::R19 },
365
  { 20U, Lanai::R20 },
366
  { 21U, Lanai::R21 },
367
  { 22U, Lanai::R22 },
368
  { 23U, Lanai::R23 },
369
  { 24U, Lanai::R24 },
370
  { 25U, Lanai::R25 },
371
  { 26U, Lanai::R26 },
372
  { 27U, Lanai::R27 },
373
  { 28U, Lanai::R28 },
374
  { 29U, Lanai::R29 },
375
  { 30U, Lanai::R30 },
376
  { 31U, Lanai::R31 },
377
};
378
extern const unsigned LanaiEHFlavour0Dwarf2LSize = array_lengthof(LanaiEHFlavour0Dwarf2L);
379
380
extern const MCRegisterInfo::DwarfLLVMRegPair LanaiDwarfFlavour0L2Dwarf[] = {
381
  { Lanai::FP, 5U },
382
  { Lanai::PC, 2U },
383
  { Lanai::RCA, 15U },
384
  { Lanai::RV, 8U },
385
  { Lanai::SP, 4U },
386
  { Lanai::R0, 0U },
387
  { Lanai::R1, 1U },
388
  { Lanai::R2, 2U },
389
  { Lanai::R3, 3U },
390
  { Lanai::R4, 4U },
391
  { Lanai::R5, 5U },
392
  { Lanai::R6, 6U },
393
  { Lanai::R7, 7U },
394
  { Lanai::R8, 8U },
395
  { Lanai::R9, 9U },
396
  { Lanai::R10, 10U },
397
  { Lanai::R11, 11U },
398
  { Lanai::R12, 12U },
399
  { Lanai::R13, 13U },
400
  { Lanai::R14, 14U },
401
  { Lanai::R15, 15U },
402
  { Lanai::R16, 16U },
403
  { Lanai::R17, 17U },
404
  { Lanai::R18, 18U },
405
  { Lanai::R19, 19U },
406
  { Lanai::R20, 20U },
407
  { Lanai::R21, 21U },
408
  { Lanai::R22, 22U },
409
  { Lanai::R23, 23U },
410
  { Lanai::R24, 24U },
411
  { Lanai::R25, 25U },
412
  { Lanai::R26, 26U },
413
  { Lanai::R27, 27U },
414
  { Lanai::R28, 28U },
415
  { Lanai::R29, 29U },
416
  { Lanai::R30, 30U },
417
  { Lanai::R31, 31U },
418
  { Lanai::RR1, 10U },
419
  { Lanai::RR2, 11U },
420
};
421
extern const unsigned LanaiDwarfFlavour0L2DwarfSize = array_lengthof(LanaiDwarfFlavour0L2Dwarf);
422
423
extern const MCRegisterInfo::DwarfLLVMRegPair LanaiEHFlavour0L2Dwarf[] = {
424
  { Lanai::FP, 5U },
425
  { Lanai::PC, 2U },
426
  { Lanai::RCA, 15U },
427
  { Lanai::RV, 8U },
428
  { Lanai::SP, 4U },
429
  { Lanai::R0, 0U },
430
  { Lanai::R1, 1U },
431
  { Lanai::R2, 2U },
432
  { Lanai::R3, 3U },
433
  { Lanai::R4, 4U },
434
  { Lanai::R5, 5U },
435
  { Lanai::R6, 6U },
436
  { Lanai::R7, 7U },
437
  { Lanai::R8, 8U },
438
  { Lanai::R9, 9U },
439
  { Lanai::R10, 10U },
440
  { Lanai::R11, 11U },
441
  { Lanai::R12, 12U },
442
  { Lanai::R13, 13U },
443
  { Lanai::R14, 14U },
444
  { Lanai::R15, 15U },
445
  { Lanai::R16, 16U },
446
  { Lanai::R17, 17U },
447
  { Lanai::R18, 18U },
448
  { Lanai::R19, 19U },
449
  { Lanai::R20, 20U },
450
  { Lanai::R21, 21U },
451
  { Lanai::R22, 22U },
452
  { Lanai::R23, 23U },
453
  { Lanai::R24, 24U },
454
  { Lanai::R25, 25U },
455
  { Lanai::R26, 26U },
456
  { Lanai::R27, 27U },
457
  { Lanai::R28, 28U },
458
  { Lanai::R29, 29U },
459
  { Lanai::R30, 30U },
460
  { Lanai::R31, 31U },
461
  { Lanai::RR1, 10U },
462
  { Lanai::RR2, 11U },
463
};
464
extern const unsigned LanaiEHFlavour0L2DwarfSize = array_lengthof(LanaiEHFlavour0L2Dwarf);
465
466
extern const uint16_t LanaiRegEncodingTable[] = {
467
  0,
468
  0,
469
  0,
470
  0,
471
  0,
472
  0,
473
  0,
474
  0,
475
  0,
476
  0,
477
  0,
478
  0,
479
  0,
480
  0,
481
  0,
482
  0,
483
  0,
484
  0,
485
  0,
486
  0,
487
  0,
488
  0,
489
  0,
490
  0,
491
  0,
492
  0,
493
  0,
494
  0,
495
  0,
496
  0,
497
  0,
498
  0,
499
  0,
500
  0,
501
  0,
502
  0,
503
  0,
504
  0,
505
  0,
506
  0,
507
  0,
508
};
509
33
static inline void InitLanaiMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
510
33
  RI->InitMCRegisterInfo(LanaiRegDesc, 41, RA, PC, LanaiMCRegisterClasses, 3, LanaiRegUnitRoots, 33, LanaiRegDiffLists, LanaiLaneMaskLists, LanaiRegStrings, LanaiRegClassStrings, LanaiSubRegIdxLists, 2,
511
33
LanaiSubRegIdxRanges, LanaiRegEncodingTable);
512
33
513
33
  switch (DwarfFlavour) {
514
33
  default:
515
0
    llvm_unreachable("Unknown DWARF flavour");
516
33
  case 0:
517
33
    RI->mapDwarfRegsToLLVMRegs(LanaiDwarfFlavour0Dwarf2L, LanaiDwarfFlavour0Dwarf2LSize, false);
518
33
    break;
519
33
  }
520
33
  switch (EHFlavour) {
521
33
  default:
522
0
    llvm_unreachable("Unknown DWARF flavour");
523
33
  case 0:
524
33
    RI->mapDwarfRegsToLLVMRegs(LanaiEHFlavour0Dwarf2L, LanaiEHFlavour0Dwarf2LSize, true);
525
33
    break;
526
33
  }
527
33
  switch (DwarfFlavour) {
528
33
  default:
529
0
    llvm_unreachable("Unknown DWARF flavour");
530
33
  case 0:
531
33
    RI->mapLLVMRegsToDwarfRegs(LanaiDwarfFlavour0L2Dwarf, LanaiDwarfFlavour0L2DwarfSize, false);
532
33
    break;
533
33
  }
534
33
  switch (EHFlavour) {
535
33
  default:
536
0
    llvm_unreachable("Unknown DWARF flavour");
537
33
  case 0:
538
33
    RI->mapLLVMRegsToDwarfRegs(LanaiEHFlavour0L2Dwarf, LanaiEHFlavour0L2DwarfSize, true);
539
33
    break;
540
33
  }
541
33
}
542
543
} // end namespace llvm
544
545
#endif // GET_REGINFO_MC_DESC
546
547
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
548
|*                                                                            *|
549
|* Register Information Header Fragment                                       *|
550
|*                                                                            *|
551
|* Automatically generated file, do not edit!                                 *|
552
|*                                                                            *|
553
\*===----------------------------------------------------------------------===*/
554
555
556
#ifdef GET_REGINFO_HEADER
557
#undef GET_REGINFO_HEADER
558
559
#include "llvm/CodeGen/TargetRegisterInfo.h"
560
561
namespace llvm {
562
563
class LanaiFrameLowering;
564
565
struct LanaiGenRegisterInfo : public TargetRegisterInfo {
566
  explicit LanaiGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
567
      unsigned PC = 0, unsigned HwMode = 0);
568
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
569
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
570
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
571
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
572
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
573
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
574
  unsigned getNumRegPressureSets() const override;
575
  const char *getRegPressureSetName(unsigned Idx) const override;
576
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
577
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
578
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
579
  ArrayRef<const char *> getRegMaskNames() const override;
580
  ArrayRef<const uint32_t *> getRegMasks() const override;
581
  /// Devirtualized TargetFrameLowering.
582
  static const LanaiFrameLowering *getFrameLowering(
583
      const MachineFunction &MF);
584
};
585
586
namespace Lanai { // Register classes
587
  extern const TargetRegisterClass GPRRegClass;
588
  extern const TargetRegisterClass GPR_with_sub_32RegClass;
589
  extern const TargetRegisterClass CCRRegClass;
590
} // end namespace Lanai
591
592
} // end namespace llvm
593
594
#endif // GET_REGINFO_HEADER
595
596
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
597
|*                                                                            *|
598
|* Target Register and Register Classes Information                           *|
599
|*                                                                            *|
600
|* Automatically generated file, do not edit!                                 *|
601
|*                                                                            *|
602
\*===----------------------------------------------------------------------===*/
603
604
605
#ifdef GET_REGINFO_TARGET_DESC
606
#undef GET_REGINFO_TARGET_DESC
607
608
namespace llvm {
609
610
extern const MCRegisterClass LanaiMCRegisterClasses[];
611
612
static const MVT::SimpleValueType VTLists[] = {
613
  /* 0 */ MVT::i32, MVT::Other,
614
};
615
616
static const char *const SubRegIndexNameTable[] = { "sub_32", "" };
617
618
619
static const LaneBitmask SubRegIndexLaneMaskTable[] = {
620
  LaneBitmask::getAll(),
621
  LaneBitmask(0x00000001), // sub_32
622
 };
623
624
625
626
static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
627
  // Mode = 0 (Default)
628
  { 32, 32, 32, VTLists+0 },    // GPR
629
  { 32, 32, 32, VTLists+0 },    // GPR_with_sub_32
630
  { 32, 32, 32, VTLists+0 },    // CCR
631
};
632
633
static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
634
635
static const uint32_t GPRSubClassMask[] = {
636
  0x00000003, 
637
  0x00000002, // sub_32
638
};
639
640
static const uint32_t GPR_with_sub_32SubClassMask[] = {
641
  0x00000002, 
642
};
643
644
static const uint32_t CCRSubClassMask[] = {
645
  0x00000004, 
646
};
647
648
static const uint16_t SuperRegIdxSeqs[] = {
649
  /* 0 */ 1, 0,
650
};
651
652
static const TargetRegisterClass *const GPR_with_sub_32Superclasses[] = {
653
  &Lanai::GPRRegClass,
654
  nullptr
655
};
656
657
658
namespace Lanai {   // Register class instances
659
  extern const TargetRegisterClass GPRRegClass = {
660
    &LanaiMCRegisterClasses[GPRRegClassID],
661
    GPRSubClassMask,
662
    SuperRegIdxSeqs + 0,
663
    LaneBitmask(0x00000001),
664
    0,
665
    false, /* HasDisjunctSubRegs */
666
    false, /* CoveredBySubRegs */
667
    NullRegClasses,
668
    nullptr
669
  };
670
671
  extern const TargetRegisterClass GPR_with_sub_32RegClass = {
672
    &LanaiMCRegisterClasses[GPR_with_sub_32RegClassID],
673
    GPR_with_sub_32SubClassMask,
674
    SuperRegIdxSeqs + 1,
675
    LaneBitmask(0x00000001),
676
    0,
677
    false, /* HasDisjunctSubRegs */
678
    false, /* CoveredBySubRegs */
679
    GPR_with_sub_32Superclasses,
680
    nullptr
681
  };
682
683
  extern const TargetRegisterClass CCRRegClass = {
684
    &LanaiMCRegisterClasses[CCRRegClassID],
685
    CCRSubClassMask,
686
    SuperRegIdxSeqs + 1,
687
    LaneBitmask(0x00000001),
688
    0,
689
    false, /* HasDisjunctSubRegs */
690
    false, /* CoveredBySubRegs */
691
    NullRegClasses,
692
    nullptr
693
  };
694
695
} // end namespace Lanai
696
697
namespace {
698
  const TargetRegisterClass* const RegisterClasses[] = {
699
    &Lanai::GPRRegClass,
700
    &Lanai::GPR_with_sub_32RegClass,
701
    &Lanai::CCRRegClass,
702
  };
703
} // end anonymous namespace
704
705
static const TargetRegisterInfoDesc LanaiRegInfoDesc[] = { // Extra Descriptors
706
  { 0, false },
707
  { 0, true },
708
  { 0, true },
709
  { 0, true },
710
  { 0, true },
711
  { 0, true },
712
  { 0, false },
713
  { 0, true },
714
  { 0, true },
715
  { 0, true },
716
  { 0, true },
717
  { 0, true },
718
  { 0, true },
719
  { 0, true },
720
  { 0, true },
721
  { 0, true },
722
  { 0, true },
723
  { 0, true },
724
  { 0, true },
725
  { 0, true },
726
  { 0, true },
727
  { 0, true },
728
  { 0, true },
729
  { 0, true },
730
  { 0, true },
731
  { 0, true },
732
  { 0, true },
733
  { 0, true },
734
  { 0, true },
735
  { 0, true },
736
  { 0, true },
737
  { 0, true },
738
  { 0, true },
739
  { 0, true },
740
  { 0, true },
741
  { 0, true },
742
  { 0, true },
743
  { 0, true },
744
  { 0, true },
745
  { 0, true },
746
  { 0, true },
747
};
748
0
unsigned LanaiGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
749
0
  static const uint8_t Rows[1][1] = {
750
0
    { 0, },
751
0
  };
752
0
753
0
  --IdxA; assert(IdxA < 1);
754
0
  --IdxB; assert(IdxB < 1);
755
0
  return Rows[0][IdxB];
756
0
}
757
758
  struct MaskRolOp {
759
    LaneBitmask Mask;
760
    uint8_t  RotateLeft;
761
  };
762
  static const MaskRolOp LaneMaskComposeSequences[] = {
763
    { LaneBitmask(0xFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 }  // Sequence 0
764
  };
765
  static const MaskRolOp *const CompositeSequences[] = {
766
    &LaneMaskComposeSequences[0] // to sub_32
767
  };
768
769
0
LaneBitmask LanaiGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
770
0
  --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
771
0
  LaneBitmask Result;
772
0
  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
773
0
    LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
774
0
    if (unsigned S = Ops->RotateLeft)
775
0
      Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
776
0
    else
777
0
      Result |= LaneBitmask(M);
778
0
  }
779
0
  return Result;
780
0
}
781
782
0
LaneBitmask LanaiGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
783
0
  LaneMask &= getSubRegIndexLaneMask(IdxA);
784
0
  --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
785
0
  LaneBitmask Result;
786
0
  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
787
0
    LaneBitmask::Type M = LaneMask.getAsInteger();
788
0
    if (unsigned S = Ops->RotateLeft)
789
0
      Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
790
0
    else
791
0
      Result |= LaneBitmask(M);
792
0
  }
793
0
  return Result;
794
0
}
795
796
0
const TargetRegisterClass *LanaiGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
797
0
  static const uint8_t Table[3][1] = {
798
0
    { // GPR
799
0
      2,  // sub_32 -> GPR_with_sub_32
800
0
    },
801
0
    { // GPR_with_sub_32
802
0
      2,  // sub_32 -> GPR_with_sub_32
803
0
    },
804
0
    { // CCR
805
0
      0,  // sub_32
806
0
    },
807
0
  };
808
0
  assert(RC && "Missing regclass");
809
0
  if (!Idx) return RC;
810
0
  --Idx;
811
0
  assert(Idx < 1 && "Bad subreg");
812
0
  unsigned TV = Table[RC->getID()][Idx];
813
0
  return TV ? getRegClass(TV - 1) : nullptr;
814
0
}
815
816
/// Get the weight in units of pressure for this register class.
817
const RegClassWeight &LanaiGenRegisterInfo::
818
282
getRegClassWeight(const TargetRegisterClass *RC) const {
819
282
  static const RegClassWeight RCWeightTable[] = {
820
282
    {1, 32},    // GPR
821
282
    {1, 7},   // GPR_with_sub_32
822
282
    {0, 0},   // CCR
823
282
  };
824
282
  return RCWeightTable[RC->getID()];
825
282
}
826
827
/// Get the weight in units of pressure for this register unit.
828
unsigned LanaiGenRegisterInfo::
829
44
getRegUnitWeight(unsigned RegUnit) const {
830
44
  assert(RegUnit < 33 && "invalid register unit");
831
44
  // All register units have unit weight.
832
44
  return 1;
833
44
}
834
835
836
// Get the number of dimensions of register pressure.
837
197
unsigned LanaiGenRegisterInfo::getNumRegPressureSets() const {
838
197
  return 2;
839
197
}
840
841
// Get the name of this register unit pressure set.
842
const char *LanaiGenRegisterInfo::
843
0
getRegPressureSetName(unsigned Idx) const {
844
0
  static const char *const PressureNameTable[] = {
845
0
    "GPR_with_sub_32",
846
0
    "GPR",
847
0
  };
848
0
  return PressureNameTable[Idx];
849
0
}
850
851
// Get the register unit pressure limit for this dimension.
852
// This limit must be adjusted dynamically for reserved registers.
853
unsigned LanaiGenRegisterInfo::
854
182
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
855
182
  static const uint8_t PressureLimitTable[] = {
856
182
    7,    // 0: GPR_with_sub_32
857
182
    32,   // 1: GPR
858
182
  };
859
182
  return PressureLimitTable[Idx];
860
182
}
861
862
/// Table of pressure sets per register class or unit.
863
static const int RCSetsTable[] = {
864
  /* 0 */ 0, 1, -1,
865
};
866
867
/// Get the dimensions of register pressure impacted by this register class.
868
/// Returns a -1 terminated array of pressure set IDs
869
const int* LanaiGenRegisterInfo::
870
272
getRegClassPressureSets(const TargetRegisterClass *RC) const {
871
272
  static const uint8_t RCSetStartTable[] = {
872
272
    1,0,2,};
873
272
  return &RCSetsTable[RCSetStartTable[RC->getID()]];
874
272
}
875
876
/// Get the dimensions of register pressure impacted by this register unit.
877
/// Returns a -1 terminated array of pressure set IDs
878
const int* LanaiGenRegisterInfo::
879
44
getRegUnitPressureSets(unsigned RegUnit) const {
880
44
  assert(RegUnit < 33 && "invalid register unit");
881
44
  static const uint8_t RUSetStartTable[] = {
882
44
    0,0,0,0,0,2,1,1,1,1,1,1,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,};
883
44
  return &RCSetsTable[RUSetStartTable[RegUnit]];
884
44
}
885
886
extern const MCRegisterDesc LanaiRegDesc[];
887
extern const MCPhysReg LanaiRegDiffLists[];
888
extern const LaneBitmask LanaiLaneMaskLists[];
889
extern const char LanaiRegStrings[];
890
extern const char LanaiRegClassStrings[];
891
extern const MCPhysReg LanaiRegUnitRoots[][2];
892
extern const uint16_t LanaiSubRegIdxLists[];
893
extern const MCRegisterInfo::SubRegCoveredBits LanaiSubRegIdxRanges[];
894
extern const uint16_t LanaiRegEncodingTable[];
895
// Lanai Dwarf<->LLVM register mappings.
896
extern const MCRegisterInfo::DwarfLLVMRegPair LanaiDwarfFlavour0Dwarf2L[];
897
extern const unsigned LanaiDwarfFlavour0Dwarf2LSize;
898
899
extern const MCRegisterInfo::DwarfLLVMRegPair LanaiEHFlavour0Dwarf2L[];
900
extern const unsigned LanaiEHFlavour0Dwarf2LSize;
901
902
extern const MCRegisterInfo::DwarfLLVMRegPair LanaiDwarfFlavour0L2Dwarf[];
903
extern const unsigned LanaiDwarfFlavour0L2DwarfSize;
904
905
extern const MCRegisterInfo::DwarfLLVMRegPair LanaiEHFlavour0L2Dwarf[];
906
extern const unsigned LanaiEHFlavour0L2DwarfSize;
907
908
LanaiGenRegisterInfo::
909
LanaiGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
910
      unsigned PC, unsigned HwMode)
911
  : TargetRegisterInfo(LanaiRegInfoDesc, RegisterClasses, RegisterClasses+3,
912
             SubRegIndexNameTable, SubRegIndexLaneMaskTable,
913
26
             LaneBitmask(0xFFFFFFFE), RegClassInfos, HwMode) {
914
26
  InitMCRegisterInfo(LanaiRegDesc, 41, RA, PC,
915
26
                     LanaiMCRegisterClasses, 3,
916
26
                     LanaiRegUnitRoots,
917
26
                     33,
918
26
                     LanaiRegDiffLists,
919
26
                     LanaiLaneMaskLists,
920
26
                     LanaiRegStrings,
921
26
                     LanaiRegClassStrings,
922
26
                     LanaiSubRegIdxLists,
923
26
                     2,
924
26
                     LanaiSubRegIdxRanges,
925
26
                     LanaiRegEncodingTable);
926
26
927
26
  switch (DwarfFlavour) {
928
26
  default:
929
0
    llvm_unreachable("Unknown DWARF flavour");
930
26
  case 0:
931
26
    mapDwarfRegsToLLVMRegs(LanaiDwarfFlavour0Dwarf2L, LanaiDwarfFlavour0Dwarf2LSize, false);
932
26
    break;
933
26
  }
934
26
  switch (EHFlavour) {
935
26
  default:
936
0
    llvm_unreachable("Unknown DWARF flavour");
937
26
  case 0:
938
26
    mapDwarfRegsToLLVMRegs(LanaiEHFlavour0Dwarf2L, LanaiEHFlavour0Dwarf2LSize, true);
939
26
    break;
940
26
  }
941
26
  switch (DwarfFlavour) {
942
26
  default:
943
0
    llvm_unreachable("Unknown DWARF flavour");
944
26
  case 0:
945
26
    mapLLVMRegsToDwarfRegs(LanaiDwarfFlavour0L2Dwarf, LanaiDwarfFlavour0L2DwarfSize, false);
946
26
    break;
947
26
  }
948
26
  switch (EHFlavour) {
949
26
  default:
950
0
    llvm_unreachable("Unknown DWARF flavour");
951
26
  case 0:
952
26
    mapLLVMRegsToDwarfRegs(LanaiEHFlavour0L2Dwarf, LanaiEHFlavour0L2DwarfSize, true);
953
26
    break;
954
26
  }
955
26
}
956
957
static const MCPhysReg CSR_SaveList[] = { 0 };
958
static const uint32_t CSR_RegMask[] = { 0x00000000, 0x00000000, };
959
960
961
10
ArrayRef<const uint32_t *> LanaiGenRegisterInfo::getRegMasks() const {
962
10
  static const uint32_t *const Masks[] = {
963
10
    CSR_RegMask,
964
10
  };
965
10
  return makeArrayRef(Masks);
966
10
}
967
968
3
ArrayRef<const char *> LanaiGenRegisterInfo::getRegMaskNames() const {
969
3
  static const char *const Names[] = {
970
3
    "CSR",
971
3
  };
972
3
  return makeArrayRef(Names);
973
3
}
974
975
const LanaiFrameLowering *
976
0
LanaiGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
977
0
  return static_cast<const LanaiFrameLowering *>(
978
0
      MF.getSubtarget().getFrameLowering());
979
0
}
980
981
} // end namespace llvm
982
983
#endif // GET_REGINFO_TARGET_DESC
984