Coverage Report

Created: 2018-12-14 11:24

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Lanai/LanaiGenSubtargetInfo.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Subtarget Enumeration Source Fragment                                      *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_SUBTARGETINFO_ENUM
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#undef GET_SUBTARGETINFO_ENUM
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namespace llvm {
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} // end namespace llvm
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#endif // GET_SUBTARGETINFO_ENUM
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#ifdef GET_SUBTARGETINFO_MC_DESC
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#undef GET_SUBTARGETINFO_MC_DESC
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namespace llvm {
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// Sorted (by key) array of values for CPU subtype.
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extern const llvm::SubtargetFeatureKV LanaiSubTypeKV[] = {
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  { "generic", "Select the generic processor", { }, { } },
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  { "v11", "Select the v11 processor", { }, { } },
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};
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#ifdef DBGFIELD
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#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
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#endif
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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#define DBGFIELD(x) x,
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#else
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#define DBGFIELD(x)
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#endif
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// Functional units for "LanaiItinerary"
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namespace LanaiItineraryFU {
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  const unsigned ALU_FU = 1 << 0;
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  const unsigned LDST_FU = 1 << 1;
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} // end namespace LanaiItineraryFU
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extern const llvm::InstrStage LanaiStages[] = {
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  { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
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  { 1, LanaiItineraryFU::ALU_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
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  { 1, LanaiItineraryFU::LDST_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
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  { 2, LanaiItineraryFU::LDST_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
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  { 0, 0, 0, llvm::InstrStage::Required } // End stages
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};
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extern const unsigned LanaiOperandCycles[] = {
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  0, // No itinerary
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  0 // End operand cycles
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};
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extern const unsigned LanaiForwardingPaths[] = {
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 0, // No itinerary
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 0 // End bypass tables
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};
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static const llvm::InstrItinerary LanaiItinerary[] = {
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  { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
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  { 1, 1, 2, 0, 0 }, // 1 IIC_ALU_WriteALU
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  { 1, 1, 2, 0, 0 }, // 2 IIC_ALU
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  { 1, 2, 3, 0, 0 }, // 3 IIC_LD_WriteLD
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  { 1, 3, 4, 0, 0 }, // 4 IIC_LDSW_WriteLDSW
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  { 0, 0, 0, 0, 0 }, // 5 WriteLD
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  { 1, 2, 3, 0, 0 }, // 6 IIC_ST_WriteST
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  { 1, 3, 4, 0, 0 }, // 7 IIC_STSW_WriteSTSW
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  { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
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};
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// ===============================================================
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// Data tables for the new per-operand machine model.
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// {ProcResourceIdx, Cycles}
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extern const llvm::MCWriteProcResEntry LanaiWriteProcResTable[] = {
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  { 0,  0}, // Invalid
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  { 1,  1}, // #1
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  { 2,  1} // #2
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}; // LanaiWriteProcResTable
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// {Cycles, WriteResourceID}
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extern const llvm::MCWriteLatencyEntry LanaiWriteLatencyTable[] = {
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  { 0,  0}, // Invalid
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  { 1,  0}, // #1 WriteALU
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  { 2,  0}, // #2 WriteLD_WriteLDSW_WriteST
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  { 4,  0} // #3 WriteSTSW
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}; // LanaiWriteLatencyTable
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// {UseIdx, WriteResourceID, Cycles}
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extern const llvm::MCReadAdvanceEntry LanaiReadAdvanceTable[] = {
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  {0,  0,  0}, // Invalid
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}; // LanaiReadAdvanceTable
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// {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
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static const llvm::MCSchedClassDesc LanaiSchedModelSchedClasses[] = {
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  {DBGFIELD("InvalidSchedClass")  16383, false, false,  0, 0,  0, 0,  0, 0},
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  {DBGFIELD("IIC_ALU_WriteALU")   1, false, false,  1, 1,  1, 1,  0, 0}, // #1
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  {DBGFIELD("IIC_ALU")            0, false, false,  0, 0,  0, 0,  0, 0}, // #2
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  {DBGFIELD("IIC_LD_WriteLD")     1, false, false,  2, 1,  2, 1,  0, 0}, // #3
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  {DBGFIELD("IIC_LDSW_WriteLDSW") 1, false, false,  2, 1,  2, 1,  0, 0}, // #4
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  {DBGFIELD("WriteLD")            1, false, false,  2, 1,  2, 1,  0, 0}, // #5
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  {DBGFIELD("IIC_ST_WriteST")     1, false, false,  2, 1,  2, 1,  0, 0}, // #6
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  {DBGFIELD("IIC_STSW_WriteSTSW") 1, false, false,  2, 1,  3, 1,  0, 0}, // #7
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}; // LanaiSchedModelSchedClasses
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static const llvm::MCSchedModel NoSchedModel = {
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  MCSchedModel::DefaultIssueWidth,
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  MCSchedModel::DefaultMicroOpBufferSize,
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  MCSchedModel::DefaultLoopMicroOpBufferSize,
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  MCSchedModel::DefaultLoadLatency,
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  MCSchedModel::DefaultHighLatency,
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  MCSchedModel::DefaultMispredictPenalty,
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  false, // PostRAScheduler
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  false, // CompleteModel
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  0, // Processor ID
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  nullptr, nullptr, 0, 0, // No instruction-level machine model.
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  nullptr, // No Itinerary
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  nullptr // No extra processor descriptor
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};
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static const unsigned LanaiSchedModelProcResourceSubUnits[] = {
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  0,  // Invalid
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};
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// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
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static const llvm::MCProcResourceDesc LanaiSchedModelProcResources[] = {
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  {"InvalidUnit", 0, 0, 0, 0},
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  {"ALU",             1, 0, 0, nullptr}, // #1
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  {"LdSt",            1, 0, 0, nullptr}, // #2
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};
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static const llvm::MCSchedModel LanaiSchedModel = {
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  1, // IssueWidth
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  0, // MicroOpBufferSize
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  0, // LoopMicroOpBufferSize
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  2, // LoadLatency
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  MCSchedModel::DefaultHighLatency,
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  10, // MispredictPenalty
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  false, // PostRAScheduler
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  false, // CompleteModel
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  1, // Processor ID
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  LanaiSchedModelProcResources,
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  LanaiSchedModelSchedClasses,
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  3,
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  8,
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  LanaiItinerary,
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  nullptr // No extra processor descriptor
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};
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// Sorted (by key) array of sched model for CPU subtype.
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extern const llvm::SubtargetInfoKV LanaiProcSchedKV[] = {
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  { "generic", (const void *)&LanaiSchedModel },
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  { "v11", (const void *)&LanaiSchedModel },
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};
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#undef DBGFIELD
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namespace Lanai_MC {
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unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
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    const MCInst *MI, unsigned CPUID) {
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  // Don't know how to resolve this scheduling class.
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  return 0;
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}
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} // end of namespace Lanai_MC
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struct LanaiGenMCSubtargetInfo : public MCSubtargetInfo {
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  LanaiGenMCSubtargetInfo(const Triple &TT, 
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    StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
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    ArrayRef<SubtargetFeatureKV> PD,
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    const SubtargetInfoKV *ProcSched,
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    const MCWriteProcResEntry *WPR,
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    const MCWriteLatencyEntry *WL,
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    const MCReadAdvanceEntry *RA, const InstrStage *IS,
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    const unsigned *OC, const unsigned *FP) :
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      MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched,
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                      WPR, WL, RA, IS, OC, FP) { }
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  unsigned resolveVariantSchedClass(unsigned SchedClass,
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      const MCInst *MI, unsigned CPUID) const override {
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    return Lanai_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID); 
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  }
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};
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static inline MCSubtargetInfo *createLanaiMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) {
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  return new LanaiGenMCSubtargetInfo(TT, CPU, FS, None, LanaiSubTypeKV, 
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                      LanaiProcSchedKV, LanaiWriteProcResTable, LanaiWriteLatencyTable, LanaiReadAdvanceTable, 
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                      LanaiStages, LanaiOperandCycles, LanaiForwardingPaths);
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}
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} // end namespace llvm
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#endif // GET_SUBTARGETINFO_MC_DESC
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#ifdef GET_SUBTARGETINFO_TARGET_DESC
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#undef GET_SUBTARGETINFO_TARGET_DESC
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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// ParseSubtargetFeatures - Parses features string setting specified
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// subtarget options.
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void llvm::LanaiSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {
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  LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
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  LLVM_DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n");
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}
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#endif // GET_SUBTARGETINFO_TARGET_DESC
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#ifdef GET_SUBTARGETINFO_HEADER
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#undef GET_SUBTARGETINFO_HEADER
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namespace llvm {
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class DFAPacketizer;
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namespace Lanai_MC {
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unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
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}
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struct LanaiGenSubtargetInfo : public TargetSubtargetInfo {
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  explicit LanaiGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS);
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public:
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  unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
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  unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
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  DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
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};
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} // end namespace llvm
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#endif // GET_SUBTARGETINFO_HEADER
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#ifdef GET_SUBTARGETINFO_CTOR
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#undef GET_SUBTARGETINFO_CTOR
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#include "llvm/CodeGen/TargetSchedule.h"
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namespace llvm {
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extern const llvm::SubtargetFeatureKV LanaiFeatureKV[];
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extern const llvm::SubtargetFeatureKV LanaiSubTypeKV[];
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extern const llvm::SubtargetInfoKV LanaiProcSchedKV[];
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extern const llvm::MCWriteProcResEntry LanaiWriteProcResTable[];
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extern const llvm::MCWriteLatencyEntry LanaiWriteLatencyTable[];
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extern const llvm::MCReadAdvanceEntry LanaiReadAdvanceTable[];
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extern const llvm::InstrStage LanaiStages[];
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extern const unsigned LanaiOperandCycles[];
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extern const unsigned LanaiForwardingPaths[];
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LanaiGenSubtargetInfo::LanaiGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
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  : TargetSubtargetInfo(TT, CPU, FS, None, makeArrayRef(LanaiSubTypeKV, 2), 
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                        LanaiProcSchedKV, LanaiWriteProcResTable, LanaiWriteLatencyTable, LanaiReadAdvanceTable, 
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                        LanaiStages, LanaiOperandCycles, LanaiForwardingPaths) {}
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unsigned LanaiGenSubtargetInfo
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::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
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  report_fatal_error("Expected a variant SchedClass");
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} // LanaiGenSubtargetInfo::resolveSchedClass
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unsigned LanaiGenSubtargetInfo
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::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
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  return Lanai_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
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} // LanaiGenSubtargetInfo::resolveVariantSchedClass
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} // end namespace llvm
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#endif // GET_SUBTARGETINFO_CTOR
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#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
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#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
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#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
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#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
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#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
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#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
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