Coverage Report

Created: 2018-11-16 02:38

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/MSP430/MSP430GenInstrInfo.inc
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1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Instruction Enum Values and Descriptors                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_INSTRINFO_ENUM
10
#undef GET_INSTRINFO_ENUM
11
namespace llvm {
12
13
namespace MSP430 {
14
  enum {
15
    PHI = 0,
16
    INLINEASM = 1,
17
    CFI_INSTRUCTION = 2,
18
    EH_LABEL  = 3,
19
    GC_LABEL  = 4,
20
    ANNOTATION_LABEL  = 5,
21
    KILL  = 6,
22
    EXTRACT_SUBREG  = 7,
23
    INSERT_SUBREG = 8,
24
    IMPLICIT_DEF  = 9,
25
    SUBREG_TO_REG = 10,
26
    COPY_TO_REGCLASS  = 11,
27
    DBG_VALUE = 12,
28
    DBG_LABEL = 13,
29
    REG_SEQUENCE  = 14,
30
    COPY  = 15,
31
    BUNDLE  = 16,
32
    LIFETIME_START  = 17,
33
    LIFETIME_END  = 18,
34
    STACKMAP  = 19,
35
    FENTRY_CALL = 20,
36
    PATCHPOINT  = 21,
37
    LOAD_STACK_GUARD  = 22,
38
    STATEPOINT  = 23,
39
    LOCAL_ESCAPE  = 24,
40
    FAULTING_OP = 25,
41
    PATCHABLE_OP  = 26,
42
    PATCHABLE_FUNCTION_ENTER  = 27,
43
    PATCHABLE_RET = 28,
44
    PATCHABLE_FUNCTION_EXIT = 29,
45
    PATCHABLE_TAIL_CALL = 30,
46
    PATCHABLE_EVENT_CALL  = 31,
47
    PATCHABLE_TYPED_EVENT_CALL  = 32,
48
    ICALL_BRANCH_FUNNEL = 33,
49
    G_ADD = 34,
50
    G_SUB = 35,
51
    G_MUL = 36,
52
    G_SDIV  = 37,
53
    G_UDIV  = 38,
54
    G_SREM  = 39,
55
    G_UREM  = 40,
56
    G_AND = 41,
57
    G_OR  = 42,
58
    G_XOR = 43,
59
    G_IMPLICIT_DEF  = 44,
60
    G_PHI = 45,
61
    G_FRAME_INDEX = 46,
62
    G_GLOBAL_VALUE  = 47,
63
    G_EXTRACT = 48,
64
    G_UNMERGE_VALUES  = 49,
65
    G_INSERT  = 50,
66
    G_MERGE_VALUES  = 51,
67
    G_PTRTOINT  = 52,
68
    G_INTTOPTR  = 53,
69
    G_BITCAST = 54,
70
    G_INTRINSIC_TRUNC = 55,
71
    G_INTRINSIC_ROUND = 56,
72
    G_LOAD  = 57,
73
    G_SEXTLOAD  = 58,
74
    G_ZEXTLOAD  = 59,
75
    G_STORE = 60,
76
    G_ATOMIC_CMPXCHG_WITH_SUCCESS = 61,
77
    G_ATOMIC_CMPXCHG  = 62,
78
    G_ATOMICRMW_XCHG  = 63,
79
    G_ATOMICRMW_ADD = 64,
80
    G_ATOMICRMW_SUB = 65,
81
    G_ATOMICRMW_AND = 66,
82
    G_ATOMICRMW_NAND  = 67,
83
    G_ATOMICRMW_OR  = 68,
84
    G_ATOMICRMW_XOR = 69,
85
    G_ATOMICRMW_MAX = 70,
86
    G_ATOMICRMW_MIN = 71,
87
    G_ATOMICRMW_UMAX  = 72,
88
    G_ATOMICRMW_UMIN  = 73,
89
    G_BRCOND  = 74,
90
    G_BRINDIRECT  = 75,
91
    G_INTRINSIC = 76,
92
    G_INTRINSIC_W_SIDE_EFFECTS  = 77,
93
    G_ANYEXT  = 78,
94
    G_TRUNC = 79,
95
    G_CONSTANT  = 80,
96
    G_FCONSTANT = 81,
97
    G_VASTART = 82,
98
    G_VAARG = 83,
99
    G_SEXT  = 84,
100
    G_ZEXT  = 85,
101
    G_SHL = 86,
102
    G_LSHR  = 87,
103
    G_ASHR  = 88,
104
    G_ICMP  = 89,
105
    G_FCMP  = 90,
106
    G_SELECT  = 91,
107
    G_UADDO = 92,
108
    G_UADDE = 93,
109
    G_USUBO = 94,
110
    G_USUBE = 95,
111
    G_SADDO = 96,
112
    G_SADDE = 97,
113
    G_SSUBO = 98,
114
    G_SSUBE = 99,
115
    G_UMULO = 100,
116
    G_SMULO = 101,
117
    G_UMULH = 102,
118
    G_SMULH = 103,
119
    G_FADD  = 104,
120
    G_FSUB  = 105,
121
    G_FMUL  = 106,
122
    G_FMA = 107,
123
    G_FDIV  = 108,
124
    G_FREM  = 109,
125
    G_FPOW  = 110,
126
    G_FEXP  = 111,
127
    G_FEXP2 = 112,
128
    G_FLOG  = 113,
129
    G_FLOG2 = 114,
130
    G_FNEG  = 115,
131
    G_FPEXT = 116,
132
    G_FPTRUNC = 117,
133
    G_FPTOSI  = 118,
134
    G_FPTOUI  = 119,
135
    G_SITOFP  = 120,
136
    G_UITOFP  = 121,
137
    G_FABS  = 122,
138
    G_GEP = 123,
139
    G_PTR_MASK  = 124,
140
    G_BR  = 125,
141
    G_INSERT_VECTOR_ELT = 126,
142
    G_EXTRACT_VECTOR_ELT  = 127,
143
    G_SHUFFLE_VECTOR  = 128,
144
    G_CTTZ  = 129,
145
    G_CTTZ_ZERO_UNDEF = 130,
146
    G_CTLZ  = 131,
147
    G_CTLZ_ZERO_UNDEF = 132,
148
    G_CTPOP = 133,
149
    G_BSWAP = 134,
150
    G_ADDRSPACE_CAST  = 135,
151
    G_BLOCK_ADDR  = 136,
152
    ADD16mc = 137,
153
    ADD16mi = 138,
154
    ADD16mm = 139,
155
    ADD16mn = 140,
156
    ADD16mp = 141,
157
    ADD16mr = 142,
158
    ADD16rc = 143,
159
    ADD16ri = 144,
160
    ADD16rm = 145,
161
    ADD16rn = 146,
162
    ADD16rp = 147,
163
    ADD16rr = 148,
164
    ADD8mc  = 149,
165
    ADD8mi  = 150,
166
    ADD8mm  = 151,
167
    ADD8mn  = 152,
168
    ADD8mp  = 153,
169
    ADD8mr  = 154,
170
    ADD8rc  = 155,
171
    ADD8ri  = 156,
172
    ADD8rm  = 157,
173
    ADD8rn  = 158,
174
    ADD8rp  = 159,
175
    ADD8rr  = 160,
176
    ADDC16mc  = 161,
177
    ADDC16mi  = 162,
178
    ADDC16mm  = 163,
179
    ADDC16mn  = 164,
180
    ADDC16mp  = 165,
181
    ADDC16mr  = 166,
182
    ADDC16rc  = 167,
183
    ADDC16ri  = 168,
184
    ADDC16rm  = 169,
185
    ADDC16rn  = 170,
186
    ADDC16rp  = 171,
187
    ADDC16rr  = 172,
188
    ADDC8mc = 173,
189
    ADDC8mi = 174,
190
    ADDC8mm = 175,
191
    ADDC8mn = 176,
192
    ADDC8mp = 177,
193
    ADDC8mr = 178,
194
    ADDC8rc = 179,
195
    ADDC8ri = 180,
196
    ADDC8rm = 181,
197
    ADDC8rn = 182,
198
    ADDC8rp = 183,
199
    ADDC8rr = 184,
200
    ADDframe  = 185,
201
    ADJCALLSTACKDOWN  = 186,
202
    ADJCALLSTACKUP  = 187,
203
    AND16mc = 188,
204
    AND16mi = 189,
205
    AND16mm = 190,
206
    AND16mn = 191,
207
    AND16mp = 192,
208
    AND16mr = 193,
209
    AND16rc = 194,
210
    AND16ri = 195,
211
    AND16rm = 196,
212
    AND16rn = 197,
213
    AND16rp = 198,
214
    AND16rr = 199,
215
    AND8mc  = 200,
216
    AND8mi  = 201,
217
    AND8mm  = 202,
218
    AND8mn  = 203,
219
    AND8mp  = 204,
220
    AND8mr  = 205,
221
    AND8rc  = 206,
222
    AND8ri  = 207,
223
    AND8rm  = 208,
224
    AND8rn  = 209,
225
    AND8rp  = 210,
226
    AND8rr  = 211,
227
    BIC16mc = 212,
228
    BIC16mi = 213,
229
    BIC16mm = 214,
230
    BIC16mn = 215,
231
    BIC16mp = 216,
232
    BIC16mr = 217,
233
    BIC16rc = 218,
234
    BIC16ri = 219,
235
    BIC16rm = 220,
236
    BIC16rn = 221,
237
    BIC16rp = 222,
238
    BIC16rr = 223,
239
    BIC8mc  = 224,
240
    BIC8mi  = 225,
241
    BIC8mm  = 226,
242
    BIC8mn  = 227,
243
    BIC8mp  = 228,
244
    BIC8mr  = 229,
245
    BIC8rc  = 230,
246
    BIC8ri  = 231,
247
    BIC8rm  = 232,
248
    BIC8rn  = 233,
249
    BIC8rp  = 234,
250
    BIC8rr  = 235,
251
    BIS16mc = 236,
252
    BIS16mi = 237,
253
    BIS16mm = 238,
254
    BIS16mn = 239,
255
    BIS16mp = 240,
256
    BIS16mr = 241,
257
    BIS16rc = 242,
258
    BIS16ri = 243,
259
    BIS16rm = 244,
260
    BIS16rn = 245,
261
    BIS16rp = 246,
262
    BIS16rr = 247,
263
    BIS8mc  = 248,
264
    BIS8mi  = 249,
265
    BIS8mm  = 250,
266
    BIS8mn  = 251,
267
    BIS8mp  = 252,
268
    BIS8mr  = 253,
269
    BIS8rc  = 254,
270
    BIS8ri  = 255,
271
    BIS8rm  = 256,
272
    BIS8rn  = 257,
273
    BIS8rp  = 258,
274
    BIS8rr  = 259,
275
    BIT16mc = 260,
276
    BIT16mi = 261,
277
    BIT16mm = 262,
278
    BIT16mr = 263,
279
    BIT16rc = 264,
280
    BIT16ri = 265,
281
    BIT16rm = 266,
282
    BIT16rr = 267,
283
    BIT8mc  = 268,
284
    BIT8mi  = 269,
285
    BIT8mm  = 270,
286
    BIT8mr  = 271,
287
    BIT8rc  = 272,
288
    BIT8ri  = 273,
289
    BIT8rm  = 274,
290
    BIT8rr  = 275,
291
    Bi  = 276,
292
    Bm  = 277,
293
    Br  = 278,
294
    CALLi = 279,
295
    CALLm = 280,
296
    CALLr = 281,
297
    CMP16mc = 282,
298
    CMP16mi = 283,
299
    CMP16mr = 284,
300
    CMP16rc = 285,
301
    CMP16ri = 286,
302
    CMP16rm = 287,
303
    CMP16rr = 288,
304
    CMP8mc  = 289,
305
    CMP8mi  = 290,
306
    CMP8mr  = 291,
307
    CMP8rc  = 292,
308
    CMP8ri  = 293,
309
    CMP8rm  = 294,
310
    CMP8rr  = 295,
311
    DADD16mc  = 296,
312
    DADD16mi  = 297,
313
    DADD16mm  = 298,
314
    DADD16mn  = 299,
315
    DADD16mp  = 300,
316
    DADD16mr  = 301,
317
    DADD16rc  = 302,
318
    DADD16ri  = 303,
319
    DADD16rm  = 304,
320
    DADD16rn  = 305,
321
    DADD16rp  = 306,
322
    DADD16rr  = 307,
323
    DADD8mc = 308,
324
    DADD8mi = 309,
325
    DADD8mm = 310,
326
    DADD8mn = 311,
327
    DADD8mp = 312,
328
    DADD8mr = 313,
329
    DADD8rc = 314,
330
    DADD8ri = 315,
331
    DADD8rm = 316,
332
    DADD8rn = 317,
333
    DADD8rp = 318,
334
    DADD8rr = 319,
335
    JCC = 320,
336
    JMP = 321,
337
    MOV16mc = 322,
338
    MOV16mi = 323,
339
    MOV16mm = 324,
340
    MOV16mr = 325,
341
    MOV16rc = 326,
342
    MOV16ri = 327,
343
    MOV16rm = 328,
344
    MOV16rn = 329,
345
    MOV16rp = 330,
346
    MOV16rr = 331,
347
    MOV8mc  = 332,
348
    MOV8mi  = 333,
349
    MOV8mm  = 334,
350
    MOV8mr  = 335,
351
    MOV8rc  = 336,
352
    MOV8ri  = 337,
353
    MOV8rm  = 338,
354
    MOV8rn  = 339,
355
    MOV8rp  = 340,
356
    MOV8rr  = 341,
357
    MOVZX16rm8  = 342,
358
    MOVZX16rr8  = 343,
359
    POP16r  = 344,
360
    PUSH16c = 345,
361
    PUSH16i = 346,
362
    PUSH16r = 347,
363
    PUSH8r  = 348,
364
    RET = 349,
365
    RETI  = 350,
366
    RRA16r  = 351,
367
    RRA8r = 352,
368
    RRC16r  = 353,
369
    RRC8r = 354,
370
    Rrcl16  = 355,
371
    Rrcl8 = 356,
372
    SEXT16r = 357,
373
    SUB16mc = 358,
374
    SUB16mi = 359,
375
    SUB16mm = 360,
376
    SUB16mn = 361,
377
    SUB16mp = 362,
378
    SUB16mr = 363,
379
    SUB16rc = 364,
380
    SUB16ri = 365,
381
    SUB16rm = 366,
382
    SUB16rn = 367,
383
    SUB16rp = 368,
384
    SUB16rr = 369,
385
    SUB8mc  = 370,
386
    SUB8mi  = 371,
387
    SUB8mm  = 372,
388
    SUB8mn  = 373,
389
    SUB8mp  = 374,
390
    SUB8mr  = 375,
391
    SUB8rc  = 376,
392
    SUB8ri  = 377,
393
    SUB8rm  = 378,
394
    SUB8rn  = 379,
395
    SUB8rp  = 380,
396
    SUB8rr  = 381,
397
    SUBC16mc  = 382,
398
    SUBC16mi  = 383,
399
    SUBC16mm  = 384,
400
    SUBC16mn  = 385,
401
    SUBC16mp  = 386,
402
    SUBC16mr  = 387,
403
    SUBC16rc  = 388,
404
    SUBC16ri  = 389,
405
    SUBC16rm  = 390,
406
    SUBC16rn  = 391,
407
    SUBC16rp  = 392,
408
    SUBC16rr  = 393,
409
    SUBC8mc = 394,
410
    SUBC8mi = 395,
411
    SUBC8mm = 396,
412
    SUBC8mn = 397,
413
    SUBC8mp = 398,
414
    SUBC8mr = 399,
415
    SUBC8rc = 400,
416
    SUBC8ri = 401,
417
    SUBC8rm = 402,
418
    SUBC8rn = 403,
419
    SUBC8rp = 404,
420
    SUBC8rr = 405,
421
    SWPB16r = 406,
422
    Select16  = 407,
423
    Select8 = 408,
424
    Shl16 = 409,
425
    Shl8  = 410,
426
    Sra16 = 411,
427
    Sra8  = 412,
428
    Srl16 = 413,
429
    Srl8  = 414,
430
    XOR16mc = 415,
431
    XOR16mi = 416,
432
    XOR16mm = 417,
433
    XOR16mn = 418,
434
    XOR16mp = 419,
435
    XOR16mr = 420,
436
    XOR16rc = 421,
437
    XOR16ri = 422,
438
    XOR16rm = 423,
439
    XOR16rn = 424,
440
    XOR16rp = 425,
441
    XOR16rr = 426,
442
    XOR8mc  = 427,
443
    XOR8mi  = 428,
444
    XOR8mm  = 429,
445
    XOR8mn  = 430,
446
    XOR8mp  = 431,
447
    XOR8mr  = 432,
448
    XOR8rc  = 433,
449
    XOR8ri  = 434,
450
    XOR8rm  = 435,
451
    XOR8rn  = 436,
452
    XOR8rp  = 437,
453
    XOR8rr  = 438,
454
    ZEXT16r = 439,
455
    INSTRUCTION_LIST_END = 440
456
  };
457
458
} // end MSP430 namespace
459
} // end llvm namespace
460
#endif // GET_INSTRINFO_ENUM
461
462
#ifdef GET_INSTRINFO_SCHED_ENUM
463
#undef GET_INSTRINFO_SCHED_ENUM
464
namespace llvm {
465
466
namespace MSP430 {
467
namespace Sched {
468
  enum {
469
    NoInstrModel  = 0,
470
    SCHED_LIST_END = 1
471
  };
472
} // end Sched namespace
473
} // end MSP430 namespace
474
} // end llvm namespace
475
#endif // GET_INSTRINFO_SCHED_ENUM
476
477
#ifdef GET_INSTRINFO_MC_DESC
478
#undef GET_INSTRINFO_MC_DESC
479
namespace llvm {
480
481
static const MCPhysReg ImplicitList1[] = { MSP430::SR, 0 };
482
static const MCPhysReg ImplicitList2[] = { MSP430::SP, 0 };
483
static const MCPhysReg ImplicitList3[] = { MSP430::SP, MSP430::SR, 0 };
484
static const MCPhysReg ImplicitList4[] = { MSP430::R11, MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, MSP430::SR, 0 };
485
486
static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
487
static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
488
static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
489
static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
490
static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
491
static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
492
static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
493
static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
494
static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
495
static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
496
static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
497
static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
498
static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
499
static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
500
static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
501
static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
502
static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
503
static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
504
static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
505
static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
506
static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
507
static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
508
static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
509
static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
510
static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
511
static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
512
static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
513
static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
514
static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
515
static const MCOperandInfo OperandInfo31[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
516
static const MCOperandInfo OperandInfo32[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
517
static const MCOperandInfo OperandInfo33[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
518
static const MCOperandInfo OperandInfo34[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
519
static const MCOperandInfo OperandInfo35[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
520
static const MCOperandInfo OperandInfo36[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
521
static const MCOperandInfo OperandInfo37[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
522
static const MCOperandInfo OperandInfo38[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
523
static const MCOperandInfo OperandInfo39[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
524
static const MCOperandInfo OperandInfo40[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
525
static const MCOperandInfo OperandInfo41[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
526
static const MCOperandInfo OperandInfo42[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
527
static const MCOperandInfo OperandInfo43[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
528
static const MCOperandInfo OperandInfo44[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
529
static const MCOperandInfo OperandInfo45[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
530
static const MCOperandInfo OperandInfo46[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
531
static const MCOperandInfo OperandInfo47[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
532
static const MCOperandInfo OperandInfo48[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
533
static const MCOperandInfo OperandInfo49[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
534
static const MCOperandInfo OperandInfo50[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
535
static const MCOperandInfo OperandInfo51[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
536
static const MCOperandInfo OperandInfo52[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
537
static const MCOperandInfo OperandInfo53[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
538
static const MCOperandInfo OperandInfo54[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
539
static const MCOperandInfo OperandInfo55[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
540
static const MCOperandInfo OperandInfo56[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
541
static const MCOperandInfo OperandInfo57[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
542
static const MCOperandInfo OperandInfo58[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
543
static const MCOperandInfo OperandInfo59[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
544
static const MCOperandInfo OperandInfo60[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
545
static const MCOperandInfo OperandInfo61[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
546
static const MCOperandInfo OperandInfo62[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
547
static const MCOperandInfo OperandInfo63[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
548
static const MCOperandInfo OperandInfo64[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
549
static const MCOperandInfo OperandInfo65[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
550
static const MCOperandInfo OperandInfo66[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
551
static const MCOperandInfo OperandInfo67[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
552
static const MCOperandInfo OperandInfo68[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
553
static const MCOperandInfo OperandInfo69[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
554
static const MCOperandInfo OperandInfo70[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
555
static const MCOperandInfo OperandInfo71[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
556
557
extern const MCInstrDesc MSP430Insts[] = {
558
  { 0,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
559
  { 1,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
560
  { 2,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #2 = CFI_INSTRUCTION
561
  { 3,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = EH_LABEL
562
  { 4,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = GC_LABEL
563
  { 5,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = ANNOTATION_LABEL
564
  { 6,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #6 = KILL
565
  { 7,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #7 = EXTRACT_SUBREG
566
  { 8,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #8 = INSERT_SUBREG
567
  { 9,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #9 = IMPLICIT_DEF
568
  { 10, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #10 = SUBREG_TO_REG
569
  { 11, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #11 = COPY_TO_REGCLASS
570
  { 12, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #12 = DBG_VALUE
571
  { 13, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #13 = DBG_LABEL
572
  { 14, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #14 = REG_SEQUENCE
573
  { 15, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #15 = COPY
574
  { 16, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #16 = BUNDLE
575
  { 17, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #17 = LIFETIME_START
576
  { 18, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #18 = LIFETIME_END
577
  { 19, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #19 = STACKMAP
578
  { 20, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #20 = FENTRY_CALL
579
  { 21, 6,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #21 = PATCHPOINT
580
  { 22, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #22 = LOAD_STACK_GUARD
581
  { 23, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #23 = STATEPOINT
582
  { 24, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #24 = LOCAL_ESCAPE
583
  { 25, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #25 = FAULTING_OP
584
  { 26, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #26 = PATCHABLE_OP
585
  { 27, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #27 = PATCHABLE_FUNCTION_ENTER
586
  { 28, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #28 = PATCHABLE_RET
587
  { 29, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #29 = PATCHABLE_FUNCTION_EXIT
588
  { 30, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #30 = PATCHABLE_TAIL_CALL
589
  { 31, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #31 = PATCHABLE_EVENT_CALL
590
  { 32, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #32 = PATCHABLE_TYPED_EVENT_CALL
591
  { 33, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #33 = ICALL_BRANCH_FUNNEL
592
  { 34, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #34 = G_ADD
593
  { 35, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #35 = G_SUB
594
  { 36, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #36 = G_MUL
595
  { 37, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #37 = G_SDIV
596
  { 38, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #38 = G_UDIV
597
  { 39, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #39 = G_SREM
598
  { 40, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #40 = G_UREM
599
  { 41, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_AND
600
  { 42, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_OR
601
  { 43, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #43 = G_XOR
602
  { 44, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #44 = G_IMPLICIT_DEF
603
  { 45, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #45 = G_PHI
604
  { 46, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #46 = G_FRAME_INDEX
605
  { 47, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #47 = G_GLOBAL_VALUE
606
  { 48, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #48 = G_EXTRACT
607
  { 49, 2,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #49 = G_UNMERGE_VALUES
608
  { 50, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #50 = G_INSERT
609
  { 51, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #51 = G_MERGE_VALUES
610
  { 52, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #52 = G_PTRTOINT
611
  { 53, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = G_INTTOPTR
612
  { 54, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #54 = G_BITCAST
613
  { 55, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #55 = G_INTRINSIC_TRUNC
614
  { 56, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #56 = G_INTRINSIC_ROUND
615
  { 57, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #57 = G_LOAD
616
  { 58, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #58 = G_SEXTLOAD
617
  { 59, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #59 = G_ZEXTLOAD
618
  { 60, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #60 = G_STORE
619
  { 61, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #61 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
620
  { 62, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #62 = G_ATOMIC_CMPXCHG
621
  { 63, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #63 = G_ATOMICRMW_XCHG
622
  { 64, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #64 = G_ATOMICRMW_ADD
623
  { 65, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #65 = G_ATOMICRMW_SUB
624
  { 66, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #66 = G_ATOMICRMW_AND
625
  { 67, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #67 = G_ATOMICRMW_NAND
626
  { 68, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #68 = G_ATOMICRMW_OR
627
  { 69, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #69 = G_ATOMICRMW_XOR
628
  { 70, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #70 = G_ATOMICRMW_MAX
629
  { 71, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #71 = G_ATOMICRMW_MIN
630
  { 72, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #72 = G_ATOMICRMW_UMAX
631
  { 73, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #73 = G_ATOMICRMW_UMIN
632
  { 74, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #74 = G_BRCOND
633
  { 75, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #75 = G_BRINDIRECT
634
  { 76, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #76 = G_INTRINSIC
635
  { 77, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #77 = G_INTRINSIC_W_SIDE_EFFECTS
636
  { 78, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #78 = G_ANYEXT
637
  { 79, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #79 = G_TRUNC
638
  { 80, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #80 = G_CONSTANT
639
  { 81, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #81 = G_FCONSTANT
640
  { 82, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #82 = G_VASTART
641
  { 83, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #83 = G_VAARG
642
  { 84, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #84 = G_SEXT
643
  { 85, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #85 = G_ZEXT
644
  { 86, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #86 = G_SHL
645
  { 87, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #87 = G_LSHR
646
  { 88, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #88 = G_ASHR
647
  { 89, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #89 = G_ICMP
648
  { 90, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #90 = G_FCMP
649
  { 91, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #91 = G_SELECT
650
  { 92, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #92 = G_UADDO
651
  { 93, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #93 = G_UADDE
652
  { 94, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #94 = G_USUBO
653
  { 95, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #95 = G_USUBE
654
  { 96, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #96 = G_SADDO
655
  { 97, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #97 = G_SADDE
656
  { 98, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #98 = G_SSUBO
657
  { 99, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #99 = G_SSUBE
658
  { 100,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #100 = G_UMULO
659
  { 101,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #101 = G_SMULO
660
  { 102,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #102 = G_UMULH
661
  { 103,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #103 = G_SMULH
662
  { 104,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #104 = G_FADD
663
  { 105,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #105 = G_FSUB
664
  { 106,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #106 = G_FMUL
665
  { 107,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #107 = G_FMA
666
  { 108,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #108 = G_FDIV
667
  { 109,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #109 = G_FREM
668
  { 110,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #110 = G_FPOW
669
  { 111,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #111 = G_FEXP
670
  { 112,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #112 = G_FEXP2
671
  { 113,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #113 = G_FLOG
672
  { 114,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #114 = G_FLOG2
673
  { 115,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #115 = G_FNEG
674
  { 116,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #116 = G_FPEXT
675
  { 117,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #117 = G_FPTRUNC
676
  { 118,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #118 = G_FPTOSI
677
  { 119,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #119 = G_FPTOUI
678
  { 120,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #120 = G_SITOFP
679
  { 121,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #121 = G_UITOFP
680
  { 122,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #122 = G_FABS
681
  { 123,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #123 = G_GEP
682
  { 124,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #124 = G_PTR_MASK
683
  { 125,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #125 = G_BR
684
  { 126,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #126 = G_INSERT_VECTOR_ELT
685
  { 127,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #127 = G_EXTRACT_VECTOR_ELT
686
  { 128,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #128 = G_SHUFFLE_VECTOR
687
  { 129,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #129 = G_CTTZ
688
  { 130,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #130 = G_CTTZ_ZERO_UNDEF
689
  { 131,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #131 = G_CTLZ
690
  { 132,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #132 = G_CTLZ_ZERO_UNDEF
691
  { 133,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #133 = G_CTPOP
692
  { 134,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #134 = G_BSWAP
693
  { 135,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #135 = G_ADDRSPACE_CAST
694
  { 136,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #136 = G_BLOCK_ADDR
695
  { 137,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #137 = ADD16mc
696
  { 138,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #138 = ADD16mi
697
  { 139,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #139 = ADD16mm
698
  { 140,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #140 = ADD16mn
699
  { 141,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #141 = ADD16mp
700
  { 142,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #142 = ADD16mr
701
  { 143,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #143 = ADD16rc
702
  { 144,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #144 = ADD16ri
703
  { 145,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #145 = ADD16rm
704
  { 146,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #146 = ADD16rn
705
  { 147,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #147 = ADD16rp
706
  { 148,  3,  1,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #148 = ADD16rr
707
  { 149,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #149 = ADD8mc
708
  { 150,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #150 = ADD8mi
709
  { 151,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #151 = ADD8mm
710
  { 152,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #152 = ADD8mn
711
  { 153,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #153 = ADD8mp
712
  { 154,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #154 = ADD8mr
713
  { 155,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #155 = ADD8rc
714
  { 156,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #156 = ADD8ri
715
  { 157,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #157 = ADD8rm
716
  { 158,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #158 = ADD8rn
717
  { 159,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #159 = ADD8rp
718
  { 160,  3,  1,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #160 = ADD8rr
719
  { 161,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #161 = ADDC16mc
720
  { 162,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #162 = ADDC16mi
721
  { 163,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #163 = ADDC16mm
722
  { 164,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #164 = ADDC16mn
723
  { 165,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #165 = ADDC16mp
724
  { 166,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #166 = ADDC16mr
725
  { 167,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #167 = ADDC16rc
726
  { 168,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #168 = ADDC16ri
727
  { 169,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #169 = ADDC16rm
728
  { 170,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #170 = ADDC16rn
729
  { 171,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #171 = ADDC16rp
730
  { 172,  3,  1,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #172 = ADDC16rr
731
  { 173,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #173 = ADDC8mc
732
  { 174,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #174 = ADDC8mi
733
  { 175,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #175 = ADDC8mm
734
  { 176,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #176 = ADDC8mn
735
  { 177,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #177 = ADDC8mp
736
  { 178,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #178 = ADDC8mr
737
  { 179,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #179 = ADDC8rc
738
  { 180,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #180 = ADDC8ri
739
  { 181,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #181 = ADDC8rm
740
  { 182,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #182 = ADDC8rn
741
  { 183,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #183 = ADDC8rp
742
  { 184,  3,  1,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #184 = ADDC8rr
743
  { 185,  3,  1,  0,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo49, -1 ,nullptr },  // Inst #185 = ADDframe
744
  { 186,  2,  0,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo8, -1 ,nullptr },  // Inst #186 = ADJCALLSTACKDOWN
745
  { 187,  2,  0,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo8, -1 ,nullptr },  // Inst #187 = ADJCALLSTACKUP
746
  { 188,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #188 = AND16mc
747
  { 189,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #189 = AND16mi
748
  { 190,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #190 = AND16mm
749
  { 191,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #191 = AND16mn
750
  { 192,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #192 = AND16mp
751
  { 193,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #193 = AND16mr
752
  { 194,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #194 = AND16rc
753
  { 195,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #195 = AND16ri
754
  { 196,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #196 = AND16rm
755
  { 197,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #197 = AND16rn
756
  { 198,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #198 = AND16rp
757
  { 199,  3,  1,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #199 = AND16rr
758
  { 200,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #200 = AND8mc
759
  { 201,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #201 = AND8mi
760
  { 202,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #202 = AND8mm
761
  { 203,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #203 = AND8mn
762
  { 204,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #204 = AND8mp
763
  { 205,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #205 = AND8mr
764
  { 206,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #206 = AND8rc
765
  { 207,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #207 = AND8ri
766
  { 208,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #208 = AND8rm
767
  { 209,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #209 = AND8rn
768
  { 210,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #210 = AND8rp
769
  { 211,  3,  1,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #211 = AND8rr
770
  { 212,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #212 = BIC16mc
771
  { 213,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #213 = BIC16mi
772
  { 214,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #214 = BIC16mm
773
  { 215,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #215 = BIC16mn
774
  { 216,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #216 = BIC16mp
775
  { 217,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #217 = BIC16mr
776
  { 218,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #218 = BIC16rc
777
  { 219,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #219 = BIC16ri
778
  { 220,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #220 = BIC16rm
779
  { 221,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #221 = BIC16rn
780
  { 222,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #222 = BIC16rp
781
  { 223,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #223 = BIC16rr
782
  { 224,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #224 = BIC8mc
783
  { 225,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #225 = BIC8mi
784
  { 226,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #226 = BIC8mm
785
  { 227,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #227 = BIC8mn
786
  { 228,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #228 = BIC8mp
787
  { 229,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #229 = BIC8mr
788
  { 230,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #230 = BIC8rc
789
  { 231,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #231 = BIC8ri
790
  { 232,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #232 = BIC8rm
791
  { 233,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #233 = BIC8rn
792
  { 234,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #234 = BIC8rp
793
  { 235,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #235 = BIC8rr
794
  { 236,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #236 = BIS16mc
795
  { 237,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #237 = BIS16mi
796
  { 238,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #238 = BIS16mm
797
  { 239,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #239 = BIS16mn
798
  { 240,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #240 = BIS16mp
799
  { 241,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #241 = BIS16mr
800
  { 242,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #242 = BIS16rc
801
  { 243,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #243 = BIS16ri
802
  { 244,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #244 = BIS16rm
803
  { 245,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #245 = BIS16rn
804
  { 246,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #246 = BIS16rp
805
  { 247,  3,  1,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #247 = BIS16rr
806
  { 248,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #248 = BIS8mc
807
  { 249,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #249 = BIS8mi
808
  { 250,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #250 = BIS8mm
809
  { 251,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #251 = BIS8mn
810
  { 252,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #252 = BIS8mp
811
  { 253,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #253 = BIS8mr
812
  { 254,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #254 = BIS8rc
813
  { 255,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #255 = BIS8ri
814
  { 256,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #256 = BIS8rm
815
  { 257,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #257 = BIS8rn
816
  { 258,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #258 = BIS8rp
817
  { 259,  3,  1,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #259 = BIS8rr
818
  { 260,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #260 = BIT16mc
819
  { 261,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #261 = BIT16mi
820
  { 262,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #262 = BIT16mm
821
  { 263,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #263 = BIT16mr
822
  { 264,  2,  0,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr },  // Inst #264 = BIT16rc
823
  { 265,  2,  0,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr },  // Inst #265 = BIT16ri
824
  { 266,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr },  // Inst #266 = BIT16rm
825
  { 267,  2,  0,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #267 = BIT16rr
826
  { 268,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #268 = BIT8mc
827
  { 269,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #269 = BIT8mi
828
  { 270,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #270 = BIT8mm
829
  { 271,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #271 = BIT8mr
830
  { 272,  2,  0,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo54, -1 ,nullptr },  // Inst #272 = BIT8rc
831
  { 273,  2,  0,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #273 = BIT8ri
832
  { 274,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #274 = BIT8rm
833
  { 275,  2,  0,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo57, -1 ,nullptr },  // Inst #275 = BIT8rr
834
  { 276,  1,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #276 = Bi
835
  { 277,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #277 = Bm
836
  { 278,  1,  0,  2,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #278 = Br
837
  { 279,  1,  0,  4,  0,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList4, OperandInfo3, -1 ,nullptr },  // Inst #279 = CALLi
838
  { 280,  2,  0,  4,  0,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList4, OperandInfo58, -1 ,nullptr },  // Inst #280 = CALLm
839
  { 281,  1,  0,  2,  0,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList4, OperandInfo59, -1 ,nullptr },  // Inst #281 = CALLr
840
  { 282,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #282 = CMP16mc
841
  { 283,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #283 = CMP16mi
842
  { 284,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #284 = CMP16mr
843
  { 285,  2,  0,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr },  // Inst #285 = CMP16rc
844
  { 286,  2,  0,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr },  // Inst #286 = CMP16ri
845
  { 287,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr },  // Inst #287 = CMP16rm
846
  { 288,  2,  0,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #288 = CMP16rr
847
  { 289,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #289 = CMP8mc
848
  { 290,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #290 = CMP8mi
849
  { 291,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #291 = CMP8mr
850
  { 292,  2,  0,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo54, -1 ,nullptr },  // Inst #292 = CMP8rc
851
  { 293,  2,  0,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #293 = CMP8ri
852
  { 294,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #294 = CMP8rm
853
  { 295,  2,  0,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo57, -1 ,nullptr },  // Inst #295 = CMP8rr
854
  { 296,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #296 = DADD16mc
855
  { 297,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #297 = DADD16mi
856
  { 298,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #298 = DADD16mm
857
  { 299,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #299 = DADD16mn
858
  { 300,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #300 = DADD16mp
859
  { 301,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #301 = DADD16mr
860
  { 302,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #302 = DADD16rc
861
  { 303,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #303 = DADD16ri
862
  { 304,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #304 = DADD16rm
863
  { 305,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #305 = DADD16rn
864
  { 306,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #306 = DADD16rp
865
  { 307,  3,  1,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #307 = DADD16rr
866
  { 308,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #308 = DADD8mc
867
  { 309,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #309 = DADD8mi
868
  { 310,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #310 = DADD8mm
869
  { 311,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #311 = DADD8mn
870
  { 312,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #312 = DADD8mp
871
  { 313,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #313 = DADD8mr
872
  { 314,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #314 = DADD8rc
873
  { 315,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #315 = DADD8ri
874
  { 316,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #316 = DADD8rm
875
  { 317,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #317 = DADD8rn
876
  { 318,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #318 = DADD8rp
877
  { 319,  3,  1,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #319 = DADD8rr
878
  { 320,  2,  0,  2,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #320 = JCC
879
  { 321,  1,  0,  2,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #321 = JMP
880
  { 322,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #322 = MOV16mc
881
  { 323,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #323 = MOV16mi
882
  { 324,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #324 = MOV16mm
883
  { 325,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #325 = MOV16mr
884
  { 326,  2,  1,  2,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #326 = MOV16rc
885
  { 327,  2,  1,  4,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #327 = MOV16ri
886
  { 328,  3,  1,  4,  0,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #328 = MOV16rm
887
  { 329,  2,  1,  2,  0,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #329 = MOV16rn
888
  { 330,  3,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #330 = MOV16rp
889
  { 331,  2,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #331 = MOV16rr
890
  { 332,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #332 = MOV8mc
891
  { 333,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #333 = MOV8mi
892
  { 334,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #334 = MOV8mm
893
  { 335,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #335 = MOV8mr
894
  { 336,  2,  1,  2,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #336 = MOV8rc
895
  { 337,  2,  1,  4,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #337 = MOV8ri
896
  { 338,  3,  1,  4,  0,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #338 = MOV8rm
897
  { 339,  2,  1,  2,  0,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #339 = MOV8rn
898
  { 340,  3,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #340 = MOV8rp
899
  { 341,  2,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #341 = MOV8rr
900
  { 342,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #342 = MOVZX16rm8
901
  { 343,  2,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr },  // Inst #343 = MOVZX16rr8
902
  { 344,  1,  1,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo59, -1 ,nullptr },  // Inst #344 = POP16r
903
  { 345,  1,  0,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo2, -1 ,nullptr },  // Inst #345 = PUSH16c
904
  { 346,  1,  0,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo3, -1 ,nullptr },  // Inst #346 = PUSH16i
905
  { 347,  1,  0,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo59, -1 ,nullptr },  // Inst #347 = PUSH16r
906
  { 348,  1,  0,  2,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo65, -1 ,nullptr },  // Inst #348 = PUSH8r
907
  { 349,  0,  0,  2,  0,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #349 = RET
908
  { 350,  0,  0,  2,  0,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #350 = RETI
909
  { 351,  2,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr },  // Inst #351 = RRA16r
910
  { 352,  2,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #352 = RRA8r
911
  { 353,  2,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo66, -1 ,nullptr },  // Inst #353 = RRC16r
912
  { 354,  2,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #354 = RRC8r
913
  { 355,  2,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #355 = Rrcl16
914
  { 356,  2,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo57, -1 ,nullptr },  // Inst #356 = Rrcl8
915
  { 357,  2,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr },  // Inst #357 = SEXT16r
916
  { 358,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #358 = SUB16mc
917
  { 359,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #359 = SUB16mi
918
  { 360,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #360 = SUB16mm
919
  { 361,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #361 = SUB16mn
920
  { 362,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #362 = SUB16mp
921
  { 363,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #363 = SUB16mr
922
  { 364,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #364 = SUB16rc
923
  { 365,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #365 = SUB16ri
924
  { 366,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #366 = SUB16rm
925
  { 367,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #367 = SUB16rn
926
  { 368,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #368 = SUB16rp
927
  { 369,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #369 = SUB16rr
928
  { 370,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #370 = SUB8mc
929
  { 371,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #371 = SUB8mi
930
  { 372,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #372 = SUB8mm
931
  { 373,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #373 = SUB8mn
932
  { 374,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #374 = SUB8mp
933
  { 375,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #375 = SUB8mr
934
  { 376,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #376 = SUB8rc
935
  { 377,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #377 = SUB8ri
936
  { 378,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #378 = SUB8rm
937
  { 379,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #379 = SUB8rn
938
  { 380,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #380 = SUB8rp
939
  { 381,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #381 = SUB8rr
940
  { 382,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #382 = SUBC16mc
941
  { 383,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #383 = SUBC16mi
942
  { 384,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #384 = SUBC16mm
943
  { 385,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #385 = SUBC16mn
944
  { 386,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #386 = SUBC16mp
945
  { 387,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #387 = SUBC16mr
946
  { 388,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #388 = SUBC16rc
947
  { 389,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #389 = SUBC16ri
948
  { 390,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #390 = SUBC16rm
949
  { 391,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #391 = SUBC16rn
950
  { 392,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #392 = SUBC16rp
951
  { 393,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #393 = SUBC16rr
952
  { 394,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #394 = SUBC8mc
953
  { 395,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #395 = SUBC8mi
954
  { 396,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #396 = SUBC8mm
955
  { 397,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #397 = SUBC8mn
956
  { 398,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #398 = SUBC8mp
957
  { 399,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #399 = SUBC8mr
958
  { 400,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #400 = SUBC8rc
959
  { 401,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #401 = SUBC8ri
960
  { 402,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #402 = SUBC8rm
961
  { 403,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #403 = SUBC8rn
962
  { 404,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #404 = SUBC8rp
963
  { 405,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #405 = SUBC8rr
964
  { 406,  2,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #406 = SWPB16r
965
  { 407,  4,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #407 = Select16
966
  { 408,  4,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #408 = Select8
967
  { 409,  3,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo70, -1 ,nullptr },  // Inst #409 = Shl16
968
  { 410,  3,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr },  // Inst #410 = Shl8
969
  { 411,  3,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo70, -1 ,nullptr },  // Inst #411 = Sra16
970
  { 412,  3,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr },  // Inst #412 = Sra8
971
  { 413,  3,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo70, -1 ,nullptr },  // Inst #413 = Srl16
972
  { 414,  3,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr },  // Inst #414 = Srl8
973
  { 415,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #415 = XOR16mc
974
  { 416,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #416 = XOR16mi
975
  { 417,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #417 = XOR16mm
976
  { 418,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #418 = XOR16mn
977
  { 419,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #419 = XOR16mp
978
  { 420,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #420 = XOR16mr
979
  { 421,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #421 = XOR16rc
980
  { 422,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #422 = XOR16ri
981
  { 423,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #423 = XOR16rm
982
  { 424,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #424 = XOR16rn
983
  { 425,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #425 = XOR16rp
984
  { 426,  3,  1,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #426 = XOR16rr
985
  { 427,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #427 = XOR8mc
986
  { 428,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #428 = XOR8mi
987
  { 429,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #429 = XOR8mm
988
  { 430,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #430 = XOR8mn
989
  { 431,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #431 = XOR8mp
990
  { 432,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #432 = XOR8mr
991
  { 433,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #433 = XOR8rc
992
  { 434,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #434 = XOR8ri
993
  { 435,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #435 = XOR8rm
994
  { 436,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #436 = XOR8rn
995
  { 437,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #437 = XOR8rp
996
  { 438,  3,  1,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #438 = XOR8rr
997
  { 439,  2,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #439 = ZEXT16r
998
};
999
1000
extern const char MSP430InstrNameData[] = {
1001
  /* 0 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0,
1002
  /* 8 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0,
1003
  /* 16 */ 'S', 'r', 'a', '1', '6', 0,
1004
  /* 22 */ 'R', 'r', 'c', 'l', '1', '6', 0,
1005
  /* 29 */ 'S', 'h', 'l', '1', '6', 0,
1006
  /* 35 */ 'S', 'r', 'l', '1', '6', 0,
1007
  /* 41 */ 'S', 'e', 'l', 'e', 'c', 't', '1', '6', 0,
1008
  /* 50 */ 'S', 'r', 'a', '8', 0,
1009
  /* 55 */ 'R', 'r', 'c', 'l', '8', 0,
1010
  /* 61 */ 'S', 'h', 'l', '8', 0,
1011
  /* 66 */ 'S', 'r', 'l', '8', 0,
1012
  /* 71 */ 'M', 'O', 'V', 'Z', 'X', '1', '6', 'r', 'm', '8', 0,
1013
  /* 82 */ 'M', 'O', 'V', 'Z', 'X', '1', '6', 'r', 'r', '8', 0,
1014
  /* 93 */ 'S', 'e', 'l', 'e', 'c', 't', '8', 0,
1015
  /* 101 */ 'G', '_', 'F', 'M', 'A', 0,
1016
  /* 107 */ 'G', '_', 'F', 'S', 'U', 'B', 0,
1017
  /* 114 */ 'G', '_', 'S', 'U', 'B', 0,
1018
  /* 120 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'S', 'U', 'B', 0,
1019
  /* 136 */ 'J', 'C', 'C', 0,
1020
  /* 140 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', 0,
1021
  /* 152 */ 'G', '_', 'F', 'P', 'T', 'R', 'U', 'N', 'C', 0,
1022
  /* 162 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'T', 'R', 'U', 'N', 'C', 0,
1023
  /* 180 */ 'G', '_', 'T', 'R', 'U', 'N', 'C', 0,
1024
  /* 188 */ 'G', '_', 'S', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
1025
  /* 199 */ 'G', '_', 'Z', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
1026
  /* 210 */ 'G', '_', 'L', 'O', 'A', 'D', 0,
1027
  /* 217 */ 'G', '_', 'F', 'A', 'D', 'D', 0,
1028
  /* 224 */ 'G', '_', 'A', 'D', 'D', 0,
1029
  /* 230 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'D', 'D', 0,
1030
  /* 246 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'N', 'A', 'N', 'D', 0,
1031
  /* 263 */ 'G', '_', 'A', 'N', 'D', 0,
1032
  /* 269 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'N', 'D', 0,
1033
  /* 285 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
1034
  /* 298 */ 'G', '_', 'B', 'R', 'C', 'O', 'N', 'D', 0,
1035
  /* 307 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'R', 'O', 'U', 'N', 'D', 0,
1036
  /* 325 */ 'L', 'O', 'A', 'D', '_', 'S', 'T', 'A', 'C', 'K', '_', 'G', 'U', 'A', 'R', 'D', 0,
1037
  /* 342 */ 'G', '_', 'S', 'S', 'U', 'B', 'E', 0,
1038
  /* 350 */ 'G', '_', 'U', 'S', 'U', 'B', 'E', 0,
1039
  /* 358 */ 'R', 'E', 'G', '_', 'S', 'E', 'Q', 'U', 'E', 'N', 'C', 'E', 0,
1040
  /* 371 */ 'G', '_', 'S', 'A', 'D', 'D', 'E', 0,
1041
  /* 379 */ 'G', '_', 'U', 'A', 'D', 'D', 'E', 0,
1042
  /* 387 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
1043
  /* 394 */ 'L', 'O', 'C', 'A', 'L', '_', 'E', 'S', 'C', 'A', 'P', 'E', 0,
1044
  /* 407 */ 'G', '_', 'S', 'T', 'O', 'R', 'E', 0,
1045
  /* 415 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
1046
  /* 425 */ 'G', '_', 'G', 'L', 'O', 'B', 'A', 'L', '_', 'V', 'A', 'L', 'U', 'E', 0,
1047
  /* 440 */ 'G', '_', 'C', 'T', 'L', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
1048
  /* 458 */ 'G', '_', 'C', 'T', 'T', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
1049
  /* 476 */ 'G', '_', 'I', 'M', 'P', 'L', 'I', 'C', 'I', 'T', '_', 'D', 'E', 'F', 0,
1050
  /* 491 */ 'G', '_', 'F', 'N', 'E', 'G', 0,
1051
  /* 498 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
1052
  /* 513 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
1053
  /* 527 */ 'S', 'U', 'B', 'R', 'E', 'G', '_', 'T', 'O', '_', 'R', 'E', 'G', 0,
1054
  /* 541 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', 0,
1055
  /* 558 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'C', 'H', 'G', 0,
1056
  /* 575 */ 'G', '_', 'F', 'L', 'O', 'G', 0,
1057
  /* 582 */ 'G', '_', 'V', 'A', 'A', 'R', 'G', 0,
1058
  /* 590 */ 'G', '_', 'S', 'M', 'U', 'L', 'H', 0,
1059
  /* 598 */ 'G', '_', 'U', 'M', 'U', 'L', 'H', 0,
1060
  /* 606 */ 'G', '_', 'P', 'H', 'I', 0,
1061
  /* 612 */ 'G', '_', 'F', 'P', 'T', 'O', 'S', 'I', 0,
1062
  /* 621 */ 'R', 'E', 'T', 'I', 0,
1063
  /* 626 */ 'G', '_', 'F', 'P', 'T', 'O', 'U', 'I', 0,
1064
  /* 635 */ 'G', '_', 'P', 'T', 'R', '_', 'M', 'A', 'S', 'K', 0,
1065
  /* 646 */ 'G', 'C', '_', 'L', 'A', 'B', 'E', 'L', 0,
1066
  /* 655 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0,
1067
  /* 665 */ 'E', 'H', '_', 'L', 'A', 'B', 'E', 'L', 0,
1068
  /* 674 */ 'A', 'N', 'N', 'O', 'T', 'A', 'T', 'I', 'O', 'N', '_', 'L', 'A', 'B', 'E', 'L', 0,
1069
  /* 691 */ 'I', 'C', 'A', 'L', 'L', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'F', 'U', 'N', 'N', 'E', 'L', 0,
1070
  /* 711 */ 'G', '_', 'S', 'H', 'L', 0,
1071
  /* 717 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'A', 'I', 'L', '_', 'C', 'A', 'L', 'L', 0,
1072
  /* 737 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
1073
  /* 764 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
1074
  /* 785 */ 'F', 'E', 'N', 'T', 'R', 'Y', '_', 'C', 'A', 'L', 'L', 0,
1075
  /* 797 */ 'K', 'I', 'L', 'L', 0,
1076
  /* 802 */ 'G', '_', 'F', 'M', 'U', 'L', 0,
1077
  /* 809 */ 'G', '_', 'M', 'U', 'L', 0,
1078
  /* 815 */ 'G', '_', 'F', 'R', 'E', 'M', 0,
1079
  /* 822 */ 'G', '_', 'S', 'R', 'E', 'M', 0,
1080
  /* 829 */ 'G', '_', 'U', 'R', 'E', 'M', 0,
1081
  /* 836 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', 0,
1082
  /* 846 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'I', 'N', 0,
1083
  /* 863 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'I', 'N', 0,
1084
  /* 879 */ 'C', 'F', 'I', '_', 'I', 'N', 'S', 'T', 'R', 'U', 'C', 'T', 'I', 'O', 'N', 0,
1085
  /* 895 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 0,
1086
  /* 912 */ 'G', '_', 'S', 'S', 'U', 'B', 'O', 0,
1087
  /* 920 */ 'G', '_', 'U', 'S', 'U', 'B', 'O', 0,
1088
  /* 928 */ 'G', '_', 'S', 'A', 'D', 'D', 'O', 0,
1089
  /* 936 */ 'G', '_', 'U', 'A', 'D', 'D', 'O', 0,
1090
  /* 944 */ 'G', '_', 'S', 'M', 'U', 'L', 'O', 0,
1091
  /* 952 */ 'G', '_', 'U', 'M', 'U', 'L', 'O', 0,
1092
  /* 960 */ 'S', 'T', 'A', 'C', 'K', 'M', 'A', 'P', 0,
1093
  /* 969 */ 'G', '_', 'B', 'S', 'W', 'A', 'P', 0,
1094
  /* 977 */ 'G', '_', 'G', 'E', 'P', 0,
1095
  /* 983 */ 'G', '_', 'S', 'I', 'T', 'O', 'F', 'P', 0,
1096
  /* 992 */ 'G', '_', 'U', 'I', 'T', 'O', 'F', 'P', 0,
1097
  /* 1001 */ 'G', '_', 'F', 'C', 'M', 'P', 0,
1098
  /* 1008 */ 'G', '_', 'I', 'C', 'M', 'P', 0,
1099
  /* 1015 */ 'J', 'M', 'P', 0,
1100
  /* 1019 */ 'G', '_', 'C', 'T', 'P', 'O', 'P', 0,
1101
  /* 1027 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'O', 'P', 0,
1102
  /* 1040 */ 'F', 'A', 'U', 'L', 'T', 'I', 'N', 'G', '_', 'O', 'P', 0,
1103
  /* 1052 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 0,
1104
  /* 1067 */ 'G', '_', 'F', 'E', 'X', 'P', 0,
1105
  /* 1074 */ 'G', '_', 'B', 'R', 0,
1106
  /* 1079 */ 'G', '_', 'B', 'L', 'O', 'C', 'K', '_', 'A', 'D', 'D', 'R', 0,
1107
  /* 1092 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'N', 'T', 'E', 'R', 0,
1108
  /* 1117 */ 'G', '_', 'A', 'S', 'H', 'R', 0,
1109
  /* 1124 */ 'G', '_', 'L', 'S', 'H', 'R', 0,
1110
  /* 1131 */ 'G', '_', 'S', 'H', 'U', 'F', 'F', 'L', 'E', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
1111
  /* 1148 */ 'G', '_', 'X', 'O', 'R', 0,
1112
  /* 1154 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'O', 'R', 0,
1113
  /* 1170 */ 'G', '_', 'O', 'R', 0,
1114
  /* 1175 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'O', 'R', 0,
1115
  /* 1190 */ 'G', '_', 'I', 'N', 'T', 'T', 'O', 'P', 'T', 'R', 0,
1116
  /* 1201 */ 'G', '_', 'F', 'A', 'B', 'S', 0,
1117
  /* 1208 */ 'G', '_', 'U', 'N', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
1118
  /* 1225 */ 'G', '_', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
1119
  /* 1240 */ 'C', 'O', 'P', 'Y', '_', 'T', 'O', '_', 'R', 'E', 'G', 'C', 'L', 'A', 'S', 'S', 0,
1120
  /* 1257 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'W', 'I', 'T', 'H', '_', 'S', 'U', 'C', 'C', 'E', 'S', 'S', 0,
1121
  /* 1287 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'W', '_', 'S', 'I', 'D', 'E', '_', 'E', 'F', 'F', 'E', 'C', 'T', 'S', 0,
1122
  /* 1314 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', 0,
1123
  /* 1324 */ 'G', '_', 'S', 'E', 'L', 'E', 'C', 'T', 0,
1124
  /* 1333 */ 'G', '_', 'B', 'R', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', 0,
1125
  /* 1346 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'R', 'E', 'T', 0,
1126
  /* 1360 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'X', 'I', 'T', 0,
1127
  /* 1384 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
1128
  /* 1405 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
1129
  /* 1425 */ 'G', '_', 'F', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
1130
  /* 1437 */ 'G', '_', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
1131
  /* 1448 */ 'S', 'T', 'A', 'T', 'E', 'P', 'O', 'I', 'N', 'T', 0,
1132
  /* 1459 */ 'P', 'A', 'T', 'C', 'H', 'P', 'O', 'I', 'N', 'T', 0,
1133
  /* 1470 */ 'G', '_', 'P', 'T', 'R', 'T', 'O', 'I', 'N', 'T', 0,
1134
  /* 1481 */ 'G', '_', 'V', 'A', 'S', 'T', 'A', 'R', 'T', 0,
1135
  /* 1491 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
1136
  /* 1506 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', 0,
1137
  /* 1515 */ 'G', '_', 'B', 'I', 'T', 'C', 'A', 'S', 'T', 0,
1138
  /* 1525 */ 'G', '_', 'A', 'D', 'D', 'R', 'S', 'P', 'A', 'C', 'E', '_', 'C', 'A', 'S', 'T', 0,
1139
  /* 1542 */ 'G', '_', 'F', 'P', 'E', 'X', 'T', 0,
1140
  /* 1550 */ 'G', '_', 'S', 'E', 'X', 'T', 0,
1141
  /* 1557 */ 'G', '_', 'A', 'N', 'Y', 'E', 'X', 'T', 0,
1142
  /* 1566 */ 'G', '_', 'Z', 'E', 'X', 'T', 0,
1143
  /* 1573 */ 'G', '_', 'F', 'D', 'I', 'V', 0,
1144
  /* 1580 */ 'G', '_', 'S', 'D', 'I', 'V', 0,
1145
  /* 1587 */ 'G', '_', 'U', 'D', 'I', 'V', 0,
1146
  /* 1594 */ 'G', '_', 'F', 'P', 'O', 'W', 0,
1147
  /* 1601 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'A', 'X', 0,
1148
  /* 1618 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'A', 'X', 0,
1149
  /* 1634 */ 'G', '_', 'F', 'R', 'A', 'M', 'E', '_', 'I', 'N', 'D', 'E', 'X', 0,
1150
  /* 1648 */ 'C', 'O', 'P', 'Y', 0,
1151
  /* 1653 */ 'G', '_', 'C', 'T', 'L', 'Z', 0,
1152
  /* 1660 */ 'G', '_', 'C', 'T', 'T', 'Z', 0,
1153
  /* 1667 */ 'P', 'U', 'S', 'H', '1', '6', 'c', 0,
1154
  /* 1675 */ 'S', 'U', 'B', '1', '6', 'm', 'c', 0,
1155
  /* 1683 */ 'S', 'U', 'B', 'C', '1', '6', 'm', 'c', 0,
1156
  /* 1692 */ 'A', 'D', 'D', 'C', '1', '6', 'm', 'c', 0,
1157
  /* 1701 */ 'B', 'I', 'C', '1', '6', 'm', 'c', 0,
1158
  /* 1709 */ 'D', 'A', 'D', 'D', '1', '6', 'm', 'c', 0,
1159
  /* 1718 */ 'A', 'N', 'D', '1', '6', 'm', 'c', 0,
1160
  /* 1726 */ 'C', 'M', 'P', '1', '6', 'm', 'c', 0,
1161
  /* 1734 */ 'X', 'O', 'R', '1', '6', 'm', 'c', 0,
1162
  /* 1742 */ 'B', 'I', 'S', '1', '6', 'm', 'c', 0,
1163
  /* 1750 */ 'B', 'I', 'T', '1', '6', 'm', 'c', 0,
1164
  /* 1758 */ 'M', 'O', 'V', '1', '6', 'm', 'c', 0,
1165
  /* 1766 */ 'S', 'U', 'B', '8', 'm', 'c', 0,
1166
  /* 1773 */ 'S', 'U', 'B', 'C', '8', 'm', 'c', 0,
1167
  /* 1781 */ 'A', 'D', 'D', 'C', '8', 'm', 'c', 0,
1168
  /* 1789 */ 'B', 'I', 'C', '8', 'm', 'c', 0,
1169
  /* 1796 */ 'D', 'A', 'D', 'D', '8', 'm', 'c', 0,
1170
  /* 1804 */ 'A', 'N', 'D', '8', 'm', 'c', 0,
1171
  /* 1811 */ 'C', 'M', 'P', '8', 'm', 'c', 0,
1172
  /* 1818 */ 'X', 'O', 'R', '8', 'm', 'c', 0,
1173
  /* 1825 */ 'B', 'I', 'S', '8', 'm', 'c', 0,
1174
  /* 1832 */ 'B', 'I', 'T', '8', 'm', 'c', 0,
1175
  /* 1839 */ 'M', 'O', 'V', '8', 'm', 'c', 0,
1176
  /* 1846 */ 'S', 'U', 'B', '1', '6', 'r', 'c', 0,
1177
  /* 1854 */ 'S', 'U', 'B', 'C', '1', '6', 'r', 'c', 0,
1178
  /* 1863 */ 'A', 'D', 'D', 'C', '1', '6', 'r', 'c', 0,
1179
  /* 1872 */ 'B', 'I', 'C', '1', '6', 'r', 'c', 0,
1180
  /* 1880 */ 'D', 'A', 'D', 'D', '1', '6', 'r', 'c', 0,
1181
  /* 1889 */ 'A', 'N', 'D', '1', '6', 'r', 'c', 0,
1182
  /* 1897 */ 'C', 'M', 'P', '1', '6', 'r', 'c', 0,
1183
  /* 1905 */ 'X', 'O', 'R', '1', '6', 'r', 'c', 0,
1184
  /* 1913 */ 'B', 'I', 'S', '1', '6', 'r', 'c', 0,
1185
  /* 1921 */ 'B', 'I', 'T', '1', '6', 'r', 'c', 0,
1186
  /* 1929 */ 'M', 'O', 'V', '1', '6', 'r', 'c', 0,
1187
  /* 1937 */ 'S', 'U', 'B', '8', 'r', 'c', 0,
1188
  /* 1944 */ 'S', 'U', 'B', 'C', '8', 'r', 'c', 0,
1189
  /* 1952 */ 'A', 'D', 'D', 'C', '8', 'r', 'c', 0,
1190
  /* 1960 */ 'B', 'I', 'C', '8', 'r', 'c', 0,
1191
  /* 1967 */ 'D', 'A', 'D', 'D', '8', 'r', 'c', 0,
1192
  /* 1975 */ 'A', 'N', 'D', '8', 'r', 'c', 0,
1193
  /* 1982 */ 'C', 'M', 'P', '8', 'r', 'c', 0,
1194
  /* 1989 */ 'X', 'O', 'R', '8', 'r', 'c', 0,
1195
  /* 1996 */ 'B', 'I', 'S', '8', 'r', 'c', 0,
1196
  /* 2003 */ 'B', 'I', 'T', '8', 'r', 'c', 0,
1197
  /* 2010 */ 'M', 'O', 'V', '8', 'r', 'c', 0,
1198
  /* 2017 */ 'A', 'D', 'D', 'f', 'r', 'a', 'm', 'e', 0,
1199
  /* 2026 */ 'P', 'U', 'S', 'H', '1', '6', 'i', 0,
1200
  /* 2034 */ 'B', 'i', 0,
1201
  /* 2037 */ 'C', 'A', 'L', 'L', 'i', 0,
1202
  /* 2043 */ 'S', 'U', 'B', '1', '6', 'm', 'i', 0,
1203
  /* 2051 */ 'S', 'U', 'B', 'C', '1', '6', 'm', 'i', 0,
1204
  /* 2060 */ 'A', 'D', 'D', 'C', '1', '6', 'm', 'i', 0,
1205
  /* 2069 */ 'B', 'I', 'C', '1', '6', 'm', 'i', 0,
1206
  /* 2077 */ 'D', 'A', 'D', 'D', '1', '6', 'm', 'i', 0,
1207
  /* 2086 */ 'A', 'N', 'D', '1', '6', 'm', 'i', 0,
1208
  /* 2094 */ 'C', 'M', 'P', '1', '6', 'm', 'i', 0,
1209
  /* 2102 */ 'X', 'O', 'R', '1', '6', 'm', 'i', 0,
1210
  /* 2110 */ 'B', 'I', 'S', '1', '6', 'm', 'i', 0,
1211
  /* 2118 */ 'B', 'I', 'T', '1', '6', 'm', 'i', 0,
1212
  /* 2126 */ 'M', 'O', 'V', '1', '6', 'm', 'i', 0,
1213
  /* 2134 */ 'S', 'U', 'B', '8', 'm', 'i', 0,
1214
  /* 2141 */ 'S', 'U', 'B', 'C', '8', 'm', 'i', 0,
1215
  /* 2149 */ 'A', 'D', 'D', 'C', '8', 'm', 'i', 0,
1216
  /* 2157 */ 'B', 'I', 'C', '8', 'm', 'i', 0,
1217
  /* 2164 */ 'D', 'A', 'D', 'D', '8', 'm', 'i', 0,
1218
  /* 2172 */ 'A', 'N', 'D', '8', 'm', 'i', 0,
1219
  /* 2179 */ 'C', 'M', 'P', '8', 'm', 'i', 0,
1220
  /* 2186 */ 'X', 'O', 'R', '8', 'm', 'i', 0,
1221
  /* 2193 */ 'B', 'I', 'S', '8', 'm', 'i', 0,
1222
  /* 2200 */ 'B', 'I', 'T', '8', 'm', 'i', 0,
1223
  /* 2207 */ 'M', 'O', 'V', '8', 'm', 'i', 0,
1224
  /* 2214 */ 'S', 'U', 'B', '1', '6', 'r', 'i', 0,
1225
  /* 2222 */ 'S', 'U', 'B', 'C', '1', '6', 'r', 'i', 0,
1226
  /* 2231 */ 'A', 'D', 'D', 'C', '1', '6', 'r', 'i', 0,
1227
  /* 2240 */ 'B', 'I', 'C', '1', '6', 'r', 'i', 0,
1228
  /* 2248 */ 'D', 'A', 'D', 'D', '1', '6', 'r', 'i', 0,
1229
  /* 2257 */ 'A', 'N', 'D', '1', '6', 'r', 'i', 0,
1230
  /* 2265 */ 'C', 'M', 'P', '1', '6', 'r', 'i', 0,
1231
  /* 2273 */ 'X', 'O', 'R', '1', '6', 'r', 'i', 0,
1232
  /* 2281 */ 'B', 'I', 'S', '1', '6', 'r', 'i', 0,
1233
  /* 2289 */ 'B', 'I', 'T', '1', '6', 'r', 'i', 0,
1234
  /* 2297 */ 'M', 'O', 'V', '1', '6', 'r', 'i', 0,
1235
  /* 2305 */ 'S', 'U', 'B', '8', 'r', 'i', 0,
1236
  /* 2312 */ 'S', 'U', 'B', 'C', '8', 'r', 'i', 0,
1237
  /* 2320 */ 'A', 'D', 'D', 'C', '8', 'r', 'i', 0,
1238
  /* 2328 */ 'B', 'I', 'C', '8', 'r', 'i', 0,
1239
  /* 2335 */ 'D', 'A', 'D', 'D', '8', 'r', 'i', 0,
1240
  /* 2343 */ 'A', 'N', 'D', '8', 'r', 'i', 0,
1241
  /* 2350 */ 'C', 'M', 'P', '8', 'r', 'i', 0,
1242
  /* 2357 */ 'X', 'O', 'R', '8', 'r', 'i', 0,
1243
  /* 2364 */ 'B', 'I', 'S', '8', 'r', 'i', 0,
1244
  /* 2371 */ 'B', 'I', 'T', '8', 'r', 'i', 0,
1245
  /* 2378 */ 'M', 'O', 'V', '8', 'r', 'i', 0,
1246
  /* 2385 */ 'B', 'm', 0,
1247
  /* 2388 */ 'C', 'A', 'L', 'L', 'm', 0,
1248
  /* 2394 */ 'S', 'U', 'B', '1', '6', 'm', 'm', 0,
1249
  /* 2402 */ 'S', 'U', 'B', 'C', '1', '6', 'm', 'm', 0,
1250
  /* 2411 */ 'A', 'D', 'D', 'C', '1', '6', 'm', 'm', 0,
1251
  /* 2420 */ 'B', 'I', 'C', '1', '6', 'm', 'm', 0,
1252
  /* 2428 */ 'D', 'A', 'D', 'D', '1', '6', 'm', 'm', 0,
1253
  /* 2437 */ 'A', 'N', 'D', '1', '6', 'm', 'm', 0,
1254
  /* 2445 */ 'X', 'O', 'R', '1', '6', 'm', 'm', 0,
1255
  /* 2453 */ 'B', 'I', 'S', '1', '6', 'm', 'm', 0,
1256
  /* 2461 */ 'B', 'I', 'T', '1', '6', 'm', 'm', 0,
1257
  /* 2469 */ 'M', 'O', 'V', '1', '6', 'm', 'm', 0,
1258
  /* 2477 */ 'S', 'U', 'B', '8', 'm', 'm', 0,
1259
  /* 2484 */ 'S', 'U', 'B', 'C', '8', 'm', 'm', 0,
1260
  /* 2492 */ 'A', 'D', 'D', 'C', '8', 'm', 'm', 0,
1261
  /* 2500 */ 'B', 'I', 'C', '8', 'm', 'm', 0,
1262
  /* 2507 */ 'D', 'A', 'D', 'D', '8', 'm', 'm', 0,
1263
  /* 2515 */ 'A', 'N', 'D', '8', 'm', 'm', 0,
1264
  /* 2522 */ 'X', 'O', 'R', '8', 'm', 'm', 0,
1265
  /* 2529 */ 'B', 'I', 'S', '8', 'm', 'm', 0,
1266
  /* 2536 */ 'B', 'I', 'T', '8', 'm', 'm', 0,
1267
  /* 2543 */ 'M', 'O', 'V', '8', 'm', 'm', 0,
1268
  /* 2550 */ 'S', 'U', 'B', '1', '6', 'r', 'm', 0,
1269
  /* 2558 */ 'S', 'U', 'B', 'C', '1', '6', 'r', 'm', 0,
1270
  /* 2567 */ 'A', 'D', 'D', 'C', '1', '6', 'r', 'm', 0,
1271
  /* 2576 */ 'B', 'I', 'C', '1', '6', 'r', 'm', 0,
1272
  /* 2584 */ 'D', 'A', 'D', 'D', '1', '6', 'r', 'm', 0,
1273
  /* 2593 */ 'A', 'N', 'D', '1', '6', 'r', 'm', 0,
1274
  /* 2601 */ 'C', 'M', 'P', '1', '6', 'r', 'm', 0,
1275
  /* 2609 */ 'X', 'O', 'R', '1', '6', 'r', 'm', 0,
1276
  /* 2617 */ 'B', 'I', 'S', '1', '6', 'r', 'm', 0,
1277
  /* 2625 */ 'B', 'I', 'T', '1', '6', 'r', 'm', 0,
1278
  /* 2633 */ 'M', 'O', 'V', '1', '6', 'r', 'm', 0,
1279
  /* 2641 */ 'S', 'U', 'B', '8', 'r', 'm', 0,
1280
  /* 2648 */ 'S', 'U', 'B', 'C', '8', 'r', 'm', 0,
1281
  /* 2656 */ 'A', 'D', 'D', 'C', '8', 'r', 'm', 0,
1282
  /* 2664 */ 'B', 'I', 'C', '8', 'r', 'm', 0,
1283
  /* 2671 */ 'D', 'A', 'D', 'D', '8', 'r', 'm', 0,
1284
  /* 2679 */ 'A', 'N', 'D', '8', 'r', 'm', 0,
1285
  /* 2686 */ 'C', 'M', 'P', '8', 'r', 'm', 0,
1286
  /* 2693 */ 'X', 'O', 'R', '8', 'r', 'm', 0,
1287
  /* 2700 */ 'B', 'I', 'S', '8', 'r', 'm', 0,
1288
  /* 2707 */ 'B', 'I', 'T', '8', 'r', 'm', 0,
1289
  /* 2714 */ 'M', 'O', 'V', '8', 'r', 'm', 0,
1290
  /* 2721 */ 'S', 'U', 'B', '1', '6', 'm', 'n', 0,
1291
  /* 2729 */ 'S', 'U', 'B', 'C', '1', '6', 'm', 'n', 0,
1292
  /* 2738 */ 'A', 'D', 'D', 'C', '1', '6', 'm', 'n', 0,
1293
  /* 2747 */ 'B', 'I', 'C', '1', '6', 'm', 'n', 0,
1294
  /* 2755 */ 'D', 'A', 'D', 'D', '1', '6', 'm', 'n', 0,
1295
  /* 2764 */ 'A', 'N', 'D', '1', '6', 'm', 'n', 0,
1296
  /* 2772 */ 'X', 'O', 'R', '1', '6', 'm', 'n', 0,
1297
  /* 2780 */ 'B', 'I', 'S', '1', '6', 'm', 'n', 0,
1298
  /* 2788 */ 'S', 'U', 'B', '8', 'm', 'n', 0,
1299
  /* 2795 */ 'S', 'U', 'B', 'C', '8', 'm', 'n', 0,
1300
  /* 2803 */ 'A', 'D', 'D', 'C', '8', 'm', 'n', 0,
1301
  /* 2811 */ 'B', 'I', 'C', '8', 'm', 'n', 0,
1302
  /* 2818 */ 'D', 'A', 'D', 'D', '8', 'm', 'n', 0,
1303
  /* 2826 */ 'A', 'N', 'D', '8', 'm', 'n', 0,
1304
  /* 2833 */ 'X', 'O', 'R', '8', 'm', 'n', 0,
1305
  /* 2840 */ 'B', 'I', 'S', '8', 'm', 'n', 0,
1306
  /* 2847 */ 'S', 'U', 'B', '1', '6', 'r', 'n', 0,
1307
  /* 2855 */ 'S', 'U', 'B', 'C', '1', '6', 'r', 'n', 0,
1308
  /* 2864 */ 'A', 'D', 'D', 'C', '1', '6', 'r', 'n', 0,
1309
  /* 2873 */ 'B', 'I', 'C', '1', '6', 'r', 'n', 0,
1310
  /* 2881 */ 'D', 'A', 'D', 'D', '1', '6', 'r', 'n', 0,
1311
  /* 2890 */ 'A', 'N', 'D', '1', '6', 'r', 'n', 0,
1312
  /* 2898 */ 'X', 'O', 'R', '1', '6', 'r', 'n', 0,
1313
  /* 2906 */ 'B', 'I', 'S', '1', '6', 'r', 'n', 0,
1314
  /* 2914 */ 'M', 'O', 'V', '1', '6', 'r', 'n', 0,
1315
  /* 2922 */ 'S', 'U', 'B', '8', 'r', 'n', 0,
1316
  /* 2929 */ 'S', 'U', 'B', 'C', '8', 'r', 'n', 0,
1317
  /* 2937 */ 'A', 'D', 'D', 'C', '8', 'r', 'n', 0,
1318
  /* 2945 */ 'B', 'I', 'C', '8', 'r', 'n', 0,
1319
  /* 2952 */ 'D', 'A', 'D', 'D', '8', 'r', 'n', 0,
1320
  /* 2960 */ 'A', 'N', 'D', '8', 'r', 'n', 0,
1321
  /* 2967 */ 'X', 'O', 'R', '8', 'r', 'n', 0,
1322
  /* 2974 */ 'B', 'I', 'S', '8', 'r', 'n', 0,
1323
  /* 2981 */ 'M', 'O', 'V', '8', 'r', 'n', 0,
1324
  /* 2988 */ 'S', 'U', 'B', '1', '6', 'm', 'p', 0,
1325
  /* 2996 */ 'S', 'U', 'B', 'C', '1', '6', 'm', 'p', 0,
1326
  /* 3005 */ 'A', 'D', 'D', 'C', '1', '6', 'm', 'p', 0,
1327
  /* 3014 */ 'B', 'I', 'C', '1', '6', 'm', 'p', 0,
1328
  /* 3022 */ 'D', 'A', 'D', 'D', '1', '6', 'm', 'p', 0,
1329
  /* 3031 */ 'A', 'N', 'D', '1', '6', 'm', 'p', 0,
1330
  /* 3039 */ 'X', 'O', 'R', '1', '6', 'm', 'p', 0,
1331
  /* 3047 */ 'B', 'I', 'S', '1', '6', 'm', 'p', 0,
1332
  /* 3055 */ 'S', 'U', 'B', '8', 'm', 'p', 0,
1333
  /* 3062 */ 'S', 'U', 'B', 'C', '8', 'm', 'p', 0,
1334
  /* 3070 */ 'A', 'D', 'D', 'C', '8', 'm', 'p', 0,
1335
  /* 3078 */ 'B', 'I', 'C', '8', 'm', 'p', 0,
1336
  /* 3085 */ 'D', 'A', 'D', 'D', '8', 'm', 'p', 0,
1337
  /* 3093 */ 'A', 'N', 'D', '8', 'm', 'p', 0,
1338
  /* 3100 */ 'X', 'O', 'R', '8', 'm', 'p', 0,
1339
  /* 3107 */ 'B', 'I', 'S', '8', 'm', 'p', 0,
1340
  /* 3114 */ 'S', 'U', 'B', '1', '6', 'r', 'p', 0,
1341
  /* 3122 */ 'S', 'U', 'B', 'C', '1', '6', 'r', 'p', 0,
1342
  /* 3131 */ 'A', 'D', 'D', 'C', '1', '6', 'r', 'p', 0,
1343
  /* 3140 */ 'B', 'I', 'C', '1', '6', 'r', 'p', 0,
1344
  /* 3148 */ 'D', 'A', 'D', 'D', '1', '6', 'r', 'p', 0,
1345
  /* 3157 */ 'A', 'N', 'D', '1', '6', 'r', 'p', 0,
1346
  /* 3165 */ 'X', 'O', 'R', '1', '6', 'r', 'p', 0,
1347
  /* 3173 */ 'B', 'I', 'S', '1', '6', 'r', 'p', 0,
1348
  /* 3181 */ 'M', 'O', 'V', '1', '6', 'r', 'p', 0,
1349
  /* 3189 */ 'S', 'U', 'B', '8', 'r', 'p', 0,
1350
  /* 3196 */ 'S', 'U', 'B', 'C', '8', 'r', 'p', 0,
1351
  /* 3204 */ 'A', 'D', 'D', 'C', '8', 'r', 'p', 0,
1352
  /* 3212 */ 'B', 'I', 'C', '8', 'r', 'p', 0,
1353
  /* 3219 */ 'D', 'A', 'D', 'D', '8', 'r', 'p', 0,
1354
  /* 3227 */ 'A', 'N', 'D', '8', 'r', 'p', 0,
1355
  /* 3234 */ 'X', 'O', 'R', '8', 'r', 'p', 0,
1356
  /* 3241 */ 'B', 'I', 'S', '8', 'r', 'p', 0,
1357
  /* 3248 */ 'M', 'O', 'V', '8', 'r', 'p', 0,
1358
  /* 3255 */ 'R', 'R', 'A', '1', '6', 'r', 0,
1359
  /* 3262 */ 'S', 'W', 'P', 'B', '1', '6', 'r', 0,
1360
  /* 3270 */ 'R', 'R', 'C', '1', '6', 'r', 0,
1361
  /* 3277 */ 'P', 'U', 'S', 'H', '1', '6', 'r', 0,
1362
  /* 3285 */ 'P', 'O', 'P', '1', '6', 'r', 0,
1363
  /* 3292 */ 'S', 'E', 'X', 'T', '1', '6', 'r', 0,
1364
  /* 3300 */ 'Z', 'E', 'X', 'T', '1', '6', 'r', 0,
1365
  /* 3308 */ 'R', 'R', 'A', '8', 'r', 0,
1366
  /* 3314 */ 'R', 'R', 'C', '8', 'r', 0,
1367
  /* 3320 */ 'P', 'U', 'S', 'H', '8', 'r', 0,
1368
  /* 3327 */ 'B', 'r', 0,
1369
  /* 3330 */ 'C', 'A', 'L', 'L', 'r', 0,
1370
  /* 3336 */ 'S', 'U', 'B', '1', '6', 'm', 'r', 0,
1371
  /* 3344 */ 'S', 'U', 'B', 'C', '1', '6', 'm', 'r', 0,
1372
  /* 3353 */ 'A', 'D', 'D', 'C', '1', '6', 'm', 'r', 0,
1373
  /* 3362 */ 'B', 'I', 'C', '1', '6', 'm', 'r', 0,
1374
  /* 3370 */ 'D', 'A', 'D', 'D', '1', '6', 'm', 'r', 0,
1375
  /* 3379 */ 'A', 'N', 'D', '1', '6', 'm', 'r', 0,
1376
  /* 3387 */ 'C', 'M', 'P', '1', '6', 'm', 'r', 0,
1377
  /* 3395 */ 'X', 'O', 'R', '1', '6', 'm', 'r', 0,
1378
  /* 3403 */ 'B', 'I', 'S', '1', '6', 'm', 'r', 0,
1379
  /* 3411 */ 'B', 'I', 'T', '1', '6', 'm', 'r', 0,
1380
  /* 3419 */ 'M', 'O', 'V', '1', '6', 'm', 'r', 0,
1381
  /* 3427 */ 'S', 'U', 'B', '8', 'm', 'r', 0,
1382
  /* 3434 */ 'S', 'U', 'B', 'C', '8', 'm', 'r', 0,
1383
  /* 3442 */ 'A', 'D', 'D', 'C', '8', 'm', 'r', 0,
1384
  /* 3450 */ 'B', 'I', 'C', '8', 'm', 'r', 0,
1385
  /* 3457 */ 'D', 'A', 'D', 'D', '8', 'm', 'r', 0,
1386
  /* 3465 */ 'A', 'N', 'D', '8', 'm', 'r', 0,
1387
  /* 3472 */ 'C', 'M', 'P', '8', 'm', 'r', 0,
1388
  /* 3479 */ 'X', 'O', 'R', '8', 'm', 'r', 0,
1389
  /* 3486 */ 'B', 'I', 'S', '8', 'm', 'r', 0,
1390
  /* 3493 */ 'B', 'I', 'T', '8', 'm', 'r', 0,
1391
  /* 3500 */ 'M', 'O', 'V', '8', 'm', 'r', 0,
1392
  /* 3507 */ 'S', 'U', 'B', '1', '6', 'r', 'r', 0,
1393
  /* 3515 */ 'S', 'U', 'B', 'C', '1', '6', 'r', 'r', 0,
1394
  /* 3524 */ 'A', 'D', 'D', 'C', '1', '6', 'r', 'r', 0,
1395
  /* 3533 */ 'B', 'I', 'C', '1', '6', 'r', 'r', 0,
1396
  /* 3541 */ 'D', 'A', 'D', 'D', '1', '6', 'r', 'r', 0,
1397
  /* 3550 */ 'A', 'N', 'D', '1', '6', 'r', 'r', 0,
1398
  /* 3558 */ 'C', 'M', 'P', '1', '6', 'r', 'r', 0,
1399
  /* 3566 */ 'X', 'O', 'R', '1', '6', 'r', 'r', 0,
1400
  /* 3574 */ 'B', 'I', 'S', '1', '6', 'r', 'r', 0,
1401
  /* 3582 */ 'B', 'I', 'T', '1', '6', 'r', 'r', 0,
1402
  /* 3590 */ 'M', 'O', 'V', '1', '6', 'r', 'r', 0,
1403
  /* 3598 */ 'S', 'U', 'B', '8', 'r', 'r', 0,
1404
  /* 3605 */ 'S', 'U', 'B', 'C', '8', 'r', 'r', 0,
1405
  /* 3613 */ 'A', 'D', 'D', 'C', '8', 'r', 'r', 0,
1406
  /* 3621 */ 'B', 'I', 'C', '8', 'r', 'r', 0,
1407
  /* 3628 */ 'D', 'A', 'D', 'D', '8', 'r', 'r', 0,
1408
  /* 3636 */ 'A', 'N', 'D', '8', 'r', 'r', 0,
1409
  /* 3643 */ 'C', 'M', 'P', '8', 'r', 'r', 0,
1410
  /* 3650 */ 'X', 'O', 'R', '8', 'r', 'r', 0,
1411
  /* 3657 */ 'B', 'I', 'S', '8', 'r', 'r', 0,
1412
  /* 3664 */ 'B', 'I', 'T', '8', 'r', 'r', 0,
1413
  /* 3671 */ 'M', 'O', 'V', '8', 'r', 'r', 0,
1414
};
1415
1416
extern const unsigned MSP430InstrNameIndices[] = {
1417
    608U, 836U, 879U, 665U, 646U, 674U, 797U, 498U, 
1418
    513U, 478U, 527U, 1240U, 415U, 655U, 358U, 1648U, 
1419
    387U, 1491U, 285U, 960U, 785U, 1459U, 325U, 1448U, 
1420
    394U, 1040U, 1027U, 1092U, 1346U, 1360U, 717U, 764U, 
1421
    737U, 691U, 224U, 114U, 809U, 1580U, 1587U, 822U, 
1422
    829U, 263U, 1170U, 1148U, 476U, 606U, 1634U, 425U, 
1423
    1314U, 1208U, 1506U, 1225U, 1470U, 1190U, 1515U, 162U, 
1424
    307U, 210U, 188U, 199U, 407U, 1257U, 541U, 558U, 
1425
    230U, 120U, 269U, 246U, 1175U, 1154U, 1618U, 863U, 
1426
    1601U, 846U, 298U, 1333U, 140U, 1287U, 1557U, 180U, 
1427
    1437U, 1425U, 1481U, 582U, 1550U, 1566U, 711U, 1124U, 
1428
    1117U, 1008U, 1001U, 1324U, 936U, 379U, 920U, 350U, 
1429
    928U, 371U, 912U, 342U, 952U, 944U, 598U, 590U, 
1430
    217U, 107U, 802U, 101U, 1573U, 815U, 1594U, 1067U, 
1431
    8U, 575U, 0U, 491U, 1542U, 152U, 612U, 626U, 
1432
    983U, 992U, 1201U, 977U, 635U, 1074U, 1405U, 1384U, 
1433
    1131U, 1660U, 458U, 1653U, 440U, 1019U, 969U, 1525U, 
1434
    1079U, 1710U, 2078U, 2429U, 2756U, 3023U, 3371U, 1881U, 
1435
    2249U, 2585U, 2882U, 3149U, 3542U, 1797U, 2165U, 2508U, 
1436
    2819U, 3086U, 3458U, 1968U, 2336U, 2672U, 2953U, 3220U, 
1437
    3629U, 1692U, 2060U, 2411U, 2738U, 3005U, 3353U, 1863U, 
1438
    2231U, 2567U, 2864U, 3131U, 3524U, 1781U, 2149U, 2492U, 
1439
    2803U, 3070U, 3442U, 1952U, 2320U, 2656U, 2937U, 3204U, 
1440
    3613U, 2017U, 895U, 1052U, 1718U, 2086U, 2437U, 2764U, 
1441
    3031U, 3379U, 1889U, 2257U, 2593U, 2890U, 3157U, 3550U, 
1442
    1804U, 2172U, 2515U, 2826U, 3093U, 3465U, 1975U, 2343U, 
1443
    2679U, 2960U, 3227U, 3636U, 1701U, 2069U, 2420U, 2747U, 
1444
    3014U, 3362U, 1872U, 2240U, 2576U, 2873U, 3140U, 3533U, 
1445
    1789U, 2157U, 2500U, 2811U, 3078U, 3450U, 1960U, 2328U, 
1446
    2664U, 2945U, 3212U, 3621U, 1742U, 2110U, 2453U, 2780U, 
1447
    3047U, 3403U, 1913U, 2281U, 2617U, 2906U, 3173U, 3574U, 
1448
    1825U, 2193U, 2529U, 2840U, 3107U, 3486U, 1996U, 2364U, 
1449
    2700U, 2974U, 3241U, 3657U, 1750U, 2118U, 2461U, 3411U, 
1450
    1921U, 2289U, 2625U, 3582U, 1832U, 2200U, 2536U, 3493U, 
1451
    2003U, 2371U, 2707U, 3664U, 2034U, 2385U, 3327U, 2037U, 
1452
    2388U, 3330U, 1726U, 2094U, 3387U, 1897U, 2265U, 2601U, 
1453
    3558U, 1811U, 2179U, 3472U, 1982U, 2350U, 2686U, 3643U, 
1454
    1709U, 2077U, 2428U, 2755U, 3022U, 3370U, 1880U, 2248U, 
1455
    2584U, 2881U, 3148U, 3541U, 1796U, 2164U, 2507U, 2818U, 
1456
    3085U, 3457U, 1967U, 2335U, 2671U, 2952U, 3219U, 3628U, 
1457
    136U, 1015U, 1758U, 2126U, 2469U, 3419U, 1929U, 2297U, 
1458
    2633U, 2914U, 3181U, 3590U, 1839U, 2207U, 2543U, 3500U, 
1459
    2010U, 2378U, 2714U, 2981U, 3248U, 3671U, 71U, 82U, 
1460
    3285U, 1667U, 2026U, 3277U, 3320U, 1356U, 621U, 3255U, 
1461
    3308U, 3270U, 3314U, 22U, 55U, 3292U, 1675U, 2043U, 
1462
    2394U, 2721U, 2988U, 3336U, 1846U, 2214U, 2550U, 2847U, 
1463
    3114U, 3507U, 1766U, 2134U, 2477U, 2788U, 3055U, 3427U, 
1464
    1937U, 2305U, 2641U, 2922U, 3189U, 3598U, 1683U, 2051U, 
1465
    2402U, 2729U, 2996U, 3344U, 1854U, 2222U, 2558U, 2855U, 
1466
    3122U, 3515U, 1773U, 2141U, 2484U, 2795U, 3062U, 3434U, 
1467
    1944U, 2312U, 2648U, 2929U, 3196U, 3605U, 3262U, 41U, 
1468
    93U, 29U, 61U, 16U, 50U, 35U, 66U, 1734U, 
1469
    2102U, 2445U, 2772U, 3039U, 3395U, 1905U, 2273U, 2609U, 
1470
    2898U, 3165U, 3566U, 1818U, 2186U, 2522U, 2833U, 3100U, 
1471
    3479U, 1989U, 2357U, 2693U, 2967U, 3234U, 3650U, 3300U, 
1472
};
1473
1474
73
static inline void InitMSP430MCInstrInfo(MCInstrInfo *II) {
1475
73
  II->InitMCInstrInfo(MSP430Insts, MSP430InstrNameIndices, MSP430InstrNameData, 440);
1476
73
}
1477
1478
} // end llvm namespace
1479
#endif // GET_INSTRINFO_MC_DESC
1480
1481
#ifdef GET_INSTRINFO_HEADER
1482
#undef GET_INSTRINFO_HEADER
1483
namespace llvm {
1484
struct MSP430GenInstrInfo : public TargetInstrInfo {
1485
  explicit MSP430GenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);
1486
64
  ~MSP430GenInstrInfo() override = default;
1487
1488
};
1489
} // end llvm namespace
1490
#endif // GET_INSTRINFO_HEADER
1491
1492
#ifdef GET_TII_HELPER_DECLS
1493
#undef GET_TII_HELPER_DECLS
1494
#endif // GET_TII_HELPER_DECLS
1495
1496
#ifdef GET_TII_HELPERS
1497
#undef GET_TII_HELPERS
1498
#endif // GET_TTI_HELPERS
1499
1500
#ifdef GET_INSTRINFO_CTOR_DTOR
1501
#undef GET_INSTRINFO_CTOR_DTOR
1502
namespace llvm {
1503
extern const MCInstrDesc MSP430Insts[];
1504
extern const unsigned MSP430InstrNameIndices[];
1505
extern const char MSP430InstrNameData[];
1506
MSP430GenInstrInfo::MSP430GenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)
1507
64
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1508
64
  InitMCInstrInfo(MSP430Insts, MSP430InstrNameIndices, MSP430InstrNameData, 440);
1509
64
}
1510
} // end llvm namespace
1511
#endif // GET_INSTRINFO_CTOR_DTOR
1512
1513
#ifdef GET_INSTRINFO_OPERAND_ENUM
1514
#undef GET_INSTRINFO_OPERAND_ENUM
1515
namespace llvm {
1516
namespace MSP430 {
1517
namespace OpName {
1518
enum {
1519
OPERAND_LAST
1520
};
1521
} // end namespace OpName
1522
} // end namespace MSP430
1523
} // end namespace llvm
1524
#endif //GET_INSTRINFO_OPERAND_ENUM
1525
1526
#ifdef GET_INSTRINFO_NAMED_OPS
1527
#undef GET_INSTRINFO_NAMED_OPS
1528
namespace llvm {
1529
namespace MSP430 {
1530
LLVM_READONLY
1531
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
1532
  return -1;
1533
}
1534
} // end namespace MSP430
1535
} // end namespace llvm
1536
#endif //GET_INSTRINFO_NAMED_OPS
1537
1538
#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
1539
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
1540
namespace llvm {
1541
namespace MSP430 {
1542
namespace OpTypes {
1543
enum OperandType {
1544
  cc = 0,
1545
  cg16imm = 1,
1546
  cg8imm = 2,
1547
  f32imm = 3,
1548
  f64imm = 4,
1549
  i16imm = 5,
1550
  i1imm = 6,
1551
  i32imm = 7,
1552
  i64imm = 8,
1553
  i8imm = 9,
1554
  indreg = 10,
1555
  jmptarget = 11,
1556
  memdst = 12,
1557
  memsrc = 13,
1558
  postreg = 14,
1559
  ptype0 = 15,
1560
  ptype1 = 16,
1561
  ptype2 = 17,
1562
  ptype3 = 18,
1563
  ptype4 = 19,
1564
  ptype5 = 20,
1565
  type0 = 21,
1566
  type1 = 22,
1567
  type2 = 23,
1568
  type3 = 24,
1569
  type4 = 25,
1570
  type5 = 26,
1571
  OPERAND_TYPE_LIST_END
1572
};
1573
} // end namespace OpTypes
1574
} // end namespace MSP430
1575
} // end namespace llvm
1576
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
1577