Coverage Report

Created: 2019-02-15 18:59

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/MSP430/MSP430GenInstrInfo.inc
Line
Count
Source
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Instruction Enum Values and Descriptors                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_INSTRINFO_ENUM
10
#undef GET_INSTRINFO_ENUM
11
namespace llvm {
12
13
namespace MSP430 {
14
  enum {
15
    PHI = 0,
16
    INLINEASM = 1,
17
    INLINEASM_BR  = 2,
18
    CFI_INSTRUCTION = 3,
19
    EH_LABEL  = 4,
20
    GC_LABEL  = 5,
21
    ANNOTATION_LABEL  = 6,
22
    KILL  = 7,
23
    EXTRACT_SUBREG  = 8,
24
    INSERT_SUBREG = 9,
25
    IMPLICIT_DEF  = 10,
26
    SUBREG_TO_REG = 11,
27
    COPY_TO_REGCLASS  = 12,
28
    DBG_VALUE = 13,
29
    DBG_LABEL = 14,
30
    REG_SEQUENCE  = 15,
31
    COPY  = 16,
32
    BUNDLE  = 17,
33
    LIFETIME_START  = 18,
34
    LIFETIME_END  = 19,
35
    STACKMAP  = 20,
36
    FENTRY_CALL = 21,
37
    PATCHPOINT  = 22,
38
    LOAD_STACK_GUARD  = 23,
39
    STATEPOINT  = 24,
40
    LOCAL_ESCAPE  = 25,
41
    FAULTING_OP = 26,
42
    PATCHABLE_OP  = 27,
43
    PATCHABLE_FUNCTION_ENTER  = 28,
44
    PATCHABLE_RET = 29,
45
    PATCHABLE_FUNCTION_EXIT = 30,
46
    PATCHABLE_TAIL_CALL = 31,
47
    PATCHABLE_EVENT_CALL  = 32,
48
    PATCHABLE_TYPED_EVENT_CALL  = 33,
49
    ICALL_BRANCH_FUNNEL = 34,
50
    G_ADD = 35,
51
    G_SUB = 36,
52
    G_MUL = 37,
53
    G_SDIV  = 38,
54
    G_UDIV  = 39,
55
    G_SREM  = 40,
56
    G_UREM  = 41,
57
    G_AND = 42,
58
    G_OR  = 43,
59
    G_XOR = 44,
60
    G_IMPLICIT_DEF  = 45,
61
    G_PHI = 46,
62
    G_FRAME_INDEX = 47,
63
    G_GLOBAL_VALUE  = 48,
64
    G_EXTRACT = 49,
65
    G_UNMERGE_VALUES  = 50,
66
    G_INSERT  = 51,
67
    G_MERGE_VALUES  = 52,
68
    G_BUILD_VECTOR  = 53,
69
    G_BUILD_VECTOR_TRUNC  = 54,
70
    G_CONCAT_VECTORS  = 55,
71
    G_PTRTOINT  = 56,
72
    G_INTTOPTR  = 57,
73
    G_BITCAST = 58,
74
    G_INTRINSIC_TRUNC = 59,
75
    G_INTRINSIC_ROUND = 60,
76
    G_LOAD  = 61,
77
    G_SEXTLOAD  = 62,
78
    G_ZEXTLOAD  = 63,
79
    G_STORE = 64,
80
    G_ATOMIC_CMPXCHG_WITH_SUCCESS = 65,
81
    G_ATOMIC_CMPXCHG  = 66,
82
    G_ATOMICRMW_XCHG  = 67,
83
    G_ATOMICRMW_ADD = 68,
84
    G_ATOMICRMW_SUB = 69,
85
    G_ATOMICRMW_AND = 70,
86
    G_ATOMICRMW_NAND  = 71,
87
    G_ATOMICRMW_OR  = 72,
88
    G_ATOMICRMW_XOR = 73,
89
    G_ATOMICRMW_MAX = 74,
90
    G_ATOMICRMW_MIN = 75,
91
    G_ATOMICRMW_UMAX  = 76,
92
    G_ATOMICRMW_UMIN  = 77,
93
    G_BRCOND  = 78,
94
    G_BRINDIRECT  = 79,
95
    G_INTRINSIC = 80,
96
    G_INTRINSIC_W_SIDE_EFFECTS  = 81,
97
    G_ANYEXT  = 82,
98
    G_TRUNC = 83,
99
    G_CONSTANT  = 84,
100
    G_FCONSTANT = 85,
101
    G_VASTART = 86,
102
    G_VAARG = 87,
103
    G_SEXT  = 88,
104
    G_ZEXT  = 89,
105
    G_SHL = 90,
106
    G_LSHR  = 91,
107
    G_ASHR  = 92,
108
    G_ICMP  = 93,
109
    G_FCMP  = 94,
110
    G_SELECT  = 95,
111
    G_UADDO = 96,
112
    G_UADDE = 97,
113
    G_USUBO = 98,
114
    G_USUBE = 99,
115
    G_SADDO = 100,
116
    G_SADDE = 101,
117
    G_SSUBO = 102,
118
    G_SSUBE = 103,
119
    G_UMULO = 104,
120
    G_SMULO = 105,
121
    G_UMULH = 106,
122
    G_SMULH = 107,
123
    G_FADD  = 108,
124
    G_FSUB  = 109,
125
    G_FMUL  = 110,
126
    G_FMA = 111,
127
    G_FDIV  = 112,
128
    G_FREM  = 113,
129
    G_FPOW  = 114,
130
    G_FEXP  = 115,
131
    G_FEXP2 = 116,
132
    G_FLOG  = 117,
133
    G_FLOG2 = 118,
134
    G_FLOG10  = 119,
135
    G_FNEG  = 120,
136
    G_FPEXT = 121,
137
    G_FPTRUNC = 122,
138
    G_FPTOSI  = 123,
139
    G_FPTOUI  = 124,
140
    G_SITOFP  = 125,
141
    G_UITOFP  = 126,
142
    G_FABS  = 127,
143
    G_FCANONICALIZE = 128,
144
    G_GEP = 129,
145
    G_PTR_MASK  = 130,
146
    G_BR  = 131,
147
    G_INSERT_VECTOR_ELT = 132,
148
    G_EXTRACT_VECTOR_ELT  = 133,
149
    G_SHUFFLE_VECTOR  = 134,
150
    G_CTTZ  = 135,
151
    G_CTTZ_ZERO_UNDEF = 136,
152
    G_CTLZ  = 137,
153
    G_CTLZ_ZERO_UNDEF = 138,
154
    G_CTPOP = 139,
155
    G_BSWAP = 140,
156
    G_FCEIL = 141,
157
    G_FCOS  = 142,
158
    G_FSIN  = 143,
159
    G_FSQRT = 144,
160
    G_FFLOOR  = 145,
161
    G_ADDRSPACE_CAST  = 146,
162
    G_BLOCK_ADDR  = 147,
163
    ADD16mc = 148,
164
    ADD16mi = 149,
165
    ADD16mm = 150,
166
    ADD16mn = 151,
167
    ADD16mp = 152,
168
    ADD16mr = 153,
169
    ADD16rc = 154,
170
    ADD16ri = 155,
171
    ADD16rm = 156,
172
    ADD16rn = 157,
173
    ADD16rp = 158,
174
    ADD16rr = 159,
175
    ADD8mc  = 160,
176
    ADD8mi  = 161,
177
    ADD8mm  = 162,
178
    ADD8mn  = 163,
179
    ADD8mp  = 164,
180
    ADD8mr  = 165,
181
    ADD8rc  = 166,
182
    ADD8ri  = 167,
183
    ADD8rm  = 168,
184
    ADD8rn  = 169,
185
    ADD8rp  = 170,
186
    ADD8rr  = 171,
187
    ADDC16mc  = 172,
188
    ADDC16mi  = 173,
189
    ADDC16mm  = 174,
190
    ADDC16mn  = 175,
191
    ADDC16mp  = 176,
192
    ADDC16mr  = 177,
193
    ADDC16rc  = 178,
194
    ADDC16ri  = 179,
195
    ADDC16rm  = 180,
196
    ADDC16rn  = 181,
197
    ADDC16rp  = 182,
198
    ADDC16rr  = 183,
199
    ADDC8mc = 184,
200
    ADDC8mi = 185,
201
    ADDC8mm = 186,
202
    ADDC8mn = 187,
203
    ADDC8mp = 188,
204
    ADDC8mr = 189,
205
    ADDC8rc = 190,
206
    ADDC8ri = 191,
207
    ADDC8rm = 192,
208
    ADDC8rn = 193,
209
    ADDC8rp = 194,
210
    ADDC8rr = 195,
211
    ADDframe  = 196,
212
    ADJCALLSTACKDOWN  = 197,
213
    ADJCALLSTACKUP  = 198,
214
    AND16mc = 199,
215
    AND16mi = 200,
216
    AND16mm = 201,
217
    AND16mn = 202,
218
    AND16mp = 203,
219
    AND16mr = 204,
220
    AND16rc = 205,
221
    AND16ri = 206,
222
    AND16rm = 207,
223
    AND16rn = 208,
224
    AND16rp = 209,
225
    AND16rr = 210,
226
    AND8mc  = 211,
227
    AND8mi  = 212,
228
    AND8mm  = 213,
229
    AND8mn  = 214,
230
    AND8mp  = 215,
231
    AND8mr  = 216,
232
    AND8rc  = 217,
233
    AND8ri  = 218,
234
    AND8rm  = 219,
235
    AND8rn  = 220,
236
    AND8rp  = 221,
237
    AND8rr  = 222,
238
    BIC16mc = 223,
239
    BIC16mi = 224,
240
    BIC16mm = 225,
241
    BIC16mn = 226,
242
    BIC16mp = 227,
243
    BIC16mr = 228,
244
    BIC16rc = 229,
245
    BIC16ri = 230,
246
    BIC16rm = 231,
247
    BIC16rn = 232,
248
    BIC16rp = 233,
249
    BIC16rr = 234,
250
    BIC8mc  = 235,
251
    BIC8mi  = 236,
252
    BIC8mm  = 237,
253
    BIC8mn  = 238,
254
    BIC8mp  = 239,
255
    BIC8mr  = 240,
256
    BIC8rc  = 241,
257
    BIC8ri  = 242,
258
    BIC8rm  = 243,
259
    BIC8rn  = 244,
260
    BIC8rp  = 245,
261
    BIC8rr  = 246,
262
    BIS16mc = 247,
263
    BIS16mi = 248,
264
    BIS16mm = 249,
265
    BIS16mn = 250,
266
    BIS16mp = 251,
267
    BIS16mr = 252,
268
    BIS16rc = 253,
269
    BIS16ri = 254,
270
    BIS16rm = 255,
271
    BIS16rn = 256,
272
    BIS16rp = 257,
273
    BIS16rr = 258,
274
    BIS8mc  = 259,
275
    BIS8mi  = 260,
276
    BIS8mm  = 261,
277
    BIS8mn  = 262,
278
    BIS8mp  = 263,
279
    BIS8mr  = 264,
280
    BIS8rc  = 265,
281
    BIS8ri  = 266,
282
    BIS8rm  = 267,
283
    BIS8rn  = 268,
284
    BIS8rp  = 269,
285
    BIS8rr  = 270,
286
    BIT16mc = 271,
287
    BIT16mi = 272,
288
    BIT16mm = 273,
289
    BIT16mn = 274,
290
    BIT16mp = 275,
291
    BIT16mr = 276,
292
    BIT16rc = 277,
293
    BIT16ri = 278,
294
    BIT16rm = 279,
295
    BIT16rn = 280,
296
    BIT16rp = 281,
297
    BIT16rr = 282,
298
    BIT8mc  = 283,
299
    BIT8mi  = 284,
300
    BIT8mm  = 285,
301
    BIT8mn  = 286,
302
    BIT8mp  = 287,
303
    BIT8mr  = 288,
304
    BIT8rc  = 289,
305
    BIT8ri  = 290,
306
    BIT8rm  = 291,
307
    BIT8rn  = 292,
308
    BIT8rp  = 293,
309
    BIT8rr  = 294,
310
    Bi  = 295,
311
    Bm  = 296,
312
    Br  = 297,
313
    CALLi = 298,
314
    CALLm = 299,
315
    CALLn = 300,
316
    CALLp = 301,
317
    CALLr = 302,
318
    CMP16mc = 303,
319
    CMP16mi = 304,
320
    CMP16mm = 305,
321
    CMP16mn = 306,
322
    CMP16mp = 307,
323
    CMP16mr = 308,
324
    CMP16rc = 309,
325
    CMP16ri = 310,
326
    CMP16rm = 311,
327
    CMP16rn = 312,
328
    CMP16rp = 313,
329
    CMP16rr = 314,
330
    CMP8mc  = 315,
331
    CMP8mi  = 316,
332
    CMP8mm  = 317,
333
    CMP8mn  = 318,
334
    CMP8mp  = 319,
335
    CMP8mr  = 320,
336
    CMP8rc  = 321,
337
    CMP8ri  = 322,
338
    CMP8rm  = 323,
339
    CMP8rn  = 324,
340
    CMP8rp  = 325,
341
    CMP8rr  = 326,
342
    DADD16mc  = 327,
343
    DADD16mi  = 328,
344
    DADD16mm  = 329,
345
    DADD16mn  = 330,
346
    DADD16mp  = 331,
347
    DADD16mr  = 332,
348
    DADD16rc  = 333,
349
    DADD16ri  = 334,
350
    DADD16rm  = 335,
351
    DADD16rn  = 336,
352
    DADD16rp  = 337,
353
    DADD16rr  = 338,
354
    DADD8mc = 339,
355
    DADD8mi = 340,
356
    DADD8mm = 341,
357
    DADD8mn = 342,
358
    DADD8mp = 343,
359
    DADD8mr = 344,
360
    DADD8rc = 345,
361
    DADD8ri = 346,
362
    DADD8rm = 347,
363
    DADD8rn = 348,
364
    DADD8rp = 349,
365
    DADD8rr = 350,
366
    JCC = 351,
367
    JMP = 352,
368
    MOV16mc = 353,
369
    MOV16mi = 354,
370
    MOV16mm = 355,
371
    MOV16mn = 356,
372
    MOV16mr = 357,
373
    MOV16rc = 358,
374
    MOV16ri = 359,
375
    MOV16rm = 360,
376
    MOV16rn = 361,
377
    MOV16rp = 362,
378
    MOV16rr = 363,
379
    MOV8mc  = 364,
380
    MOV8mi  = 365,
381
    MOV8mm  = 366,
382
    MOV8mn  = 367,
383
    MOV8mr  = 368,
384
    MOV8rc  = 369,
385
    MOV8ri  = 370,
386
    MOV8rm  = 371,
387
    MOV8rn  = 372,
388
    MOV8rp  = 373,
389
    MOV8rr  = 374,
390
    MOVZX16rm8  = 375,
391
    MOVZX16rr8  = 376,
392
    POP16r  = 377,
393
    PUSH16c = 378,
394
    PUSH16i = 379,
395
    PUSH16r = 380,
396
    PUSH8r  = 381,
397
    RET = 382,
398
    RETI  = 383,
399
    RRA16m  = 384,
400
    RRA16n  = 385,
401
    RRA16p  = 386,
402
    RRA16r  = 387,
403
    RRA8m = 388,
404
    RRA8n = 389,
405
    RRA8p = 390,
406
    RRA8r = 391,
407
    RRC16m  = 392,
408
    RRC16n  = 393,
409
    RRC16p  = 394,
410
    RRC16r  = 395,
411
    RRC8m = 396,
412
    RRC8n = 397,
413
    RRC8p = 398,
414
    RRC8r = 399,
415
    Rrcl16  = 400,
416
    Rrcl8 = 401,
417
    SEXT16m = 402,
418
    SEXT16n = 403,
419
    SEXT16p = 404,
420
    SEXT16r = 405,
421
    SUB16mc = 406,
422
    SUB16mi = 407,
423
    SUB16mm = 408,
424
    SUB16mn = 409,
425
    SUB16mp = 410,
426
    SUB16mr = 411,
427
    SUB16rc = 412,
428
    SUB16ri = 413,
429
    SUB16rm = 414,
430
    SUB16rn = 415,
431
    SUB16rp = 416,
432
    SUB16rr = 417,
433
    SUB8mc  = 418,
434
    SUB8mi  = 419,
435
    SUB8mm  = 420,
436
    SUB8mn  = 421,
437
    SUB8mp  = 422,
438
    SUB8mr  = 423,
439
    SUB8rc  = 424,
440
    SUB8ri  = 425,
441
    SUB8rm  = 426,
442
    SUB8rn  = 427,
443
    SUB8rp  = 428,
444
    SUB8rr  = 429,
445
    SUBC16mc  = 430,
446
    SUBC16mi  = 431,
447
    SUBC16mm  = 432,
448
    SUBC16mn  = 433,
449
    SUBC16mp  = 434,
450
    SUBC16mr  = 435,
451
    SUBC16rc  = 436,
452
    SUBC16ri  = 437,
453
    SUBC16rm  = 438,
454
    SUBC16rn  = 439,
455
    SUBC16rp  = 440,
456
    SUBC16rr  = 441,
457
    SUBC8mc = 442,
458
    SUBC8mi = 443,
459
    SUBC8mm = 444,
460
    SUBC8mn = 445,
461
    SUBC8mp = 446,
462
    SUBC8mr = 447,
463
    SUBC8rc = 448,
464
    SUBC8ri = 449,
465
    SUBC8rm = 450,
466
    SUBC8rn = 451,
467
    SUBC8rp = 452,
468
    SUBC8rr = 453,
469
    SWPB16m = 454,
470
    SWPB16n = 455,
471
    SWPB16p = 456,
472
    SWPB16r = 457,
473
    Select16  = 458,
474
    Select8 = 459,
475
    Shl16 = 460,
476
    Shl8  = 461,
477
    Sra16 = 462,
478
    Sra8  = 463,
479
    Srl16 = 464,
480
    Srl8  = 465,
481
    XOR16mc = 466,
482
    XOR16mi = 467,
483
    XOR16mm = 468,
484
    XOR16mn = 469,
485
    XOR16mp = 470,
486
    XOR16mr = 471,
487
    XOR16rc = 472,
488
    XOR16ri = 473,
489
    XOR16rm = 474,
490
    XOR16rn = 475,
491
    XOR16rp = 476,
492
    XOR16rr = 477,
493
    XOR8mc  = 478,
494
    XOR8mi  = 479,
495
    XOR8mm  = 480,
496
    XOR8mn  = 481,
497
    XOR8mp  = 482,
498
    XOR8mr  = 483,
499
    XOR8rc  = 484,
500
    XOR8ri  = 485,
501
    XOR8rm  = 486,
502
    XOR8rn  = 487,
503
    XOR8rp  = 488,
504
    XOR8rr  = 489,
505
    ZEXT16r = 490,
506
    INSTRUCTION_LIST_END = 491
507
  };
508
509
} // end MSP430 namespace
510
} // end llvm namespace
511
#endif // GET_INSTRINFO_ENUM
512
513
#ifdef GET_INSTRINFO_SCHED_ENUM
514
#undef GET_INSTRINFO_SCHED_ENUM
515
namespace llvm {
516
517
namespace MSP430 {
518
namespace Sched {
519
  enum {
520
    NoInstrModel  = 0,
521
    SCHED_LIST_END = 1
522
  };
523
} // end Sched namespace
524
} // end MSP430 namespace
525
} // end llvm namespace
526
#endif // GET_INSTRINFO_SCHED_ENUM
527
528
#ifdef GET_INSTRINFO_MC_DESC
529
#undef GET_INSTRINFO_MC_DESC
530
namespace llvm {
531
532
static const MCPhysReg ImplicitList1[] = { MSP430::SR, 0 };
533
static const MCPhysReg ImplicitList2[] = { MSP430::SP, 0 };
534
static const MCPhysReg ImplicitList3[] = { MSP430::SP, MSP430::SR, 0 };
535
static const MCPhysReg ImplicitList4[] = { MSP430::R11, MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, MSP430::SR, 0 };
536
537
static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
538
static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
539
static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
540
static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
541
static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
542
static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
543
static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
544
static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
545
static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
546
static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
547
static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
548
static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
549
static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
550
static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
551
static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
552
static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
553
static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
554
static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
555
static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
556
static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
557
static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
558
static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
559
static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
560
static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
561
static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
562
static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
563
static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
564
static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
565
static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
566
static const MCOperandInfo OperandInfo31[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
567
static const MCOperandInfo OperandInfo32[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
568
static const MCOperandInfo OperandInfo33[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
569
static const MCOperandInfo OperandInfo34[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
570
static const MCOperandInfo OperandInfo35[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
571
static const MCOperandInfo OperandInfo36[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
572
static const MCOperandInfo OperandInfo37[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
573
static const MCOperandInfo OperandInfo38[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
574
static const MCOperandInfo OperandInfo39[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
575
static const MCOperandInfo OperandInfo40[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
576
static const MCOperandInfo OperandInfo41[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
577
static const MCOperandInfo OperandInfo42[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
578
static const MCOperandInfo OperandInfo43[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
579
static const MCOperandInfo OperandInfo44[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
580
static const MCOperandInfo OperandInfo45[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
581
static const MCOperandInfo OperandInfo46[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
582
static const MCOperandInfo OperandInfo47[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
583
static const MCOperandInfo OperandInfo48[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
584
static const MCOperandInfo OperandInfo49[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
585
static const MCOperandInfo OperandInfo50[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
586
static const MCOperandInfo OperandInfo51[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
587
static const MCOperandInfo OperandInfo52[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
588
static const MCOperandInfo OperandInfo53[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
589
static const MCOperandInfo OperandInfo54[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
590
static const MCOperandInfo OperandInfo55[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
591
static const MCOperandInfo OperandInfo56[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
592
static const MCOperandInfo OperandInfo57[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
593
static const MCOperandInfo OperandInfo58[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
594
static const MCOperandInfo OperandInfo59[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
595
static const MCOperandInfo OperandInfo60[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
596
static const MCOperandInfo OperandInfo61[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
597
static const MCOperandInfo OperandInfo62[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
598
static const MCOperandInfo OperandInfo63[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
599
static const MCOperandInfo OperandInfo64[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
600
static const MCOperandInfo OperandInfo65[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
601
static const MCOperandInfo OperandInfo66[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
602
static const MCOperandInfo OperandInfo67[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
603
static const MCOperandInfo OperandInfo68[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
604
static const MCOperandInfo OperandInfo69[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
605
static const MCOperandInfo OperandInfo70[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
606
static const MCOperandInfo OperandInfo71[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
607
static const MCOperandInfo OperandInfo72[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
608
609
extern const MCInstrDesc MSP430Insts[] = {
610
  { 0,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
611
  { 1,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
612
  { 2,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2 = INLINEASM_BR
613
  { 3,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = CFI_INSTRUCTION
614
  { 4,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = EH_LABEL
615
  { 5,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = GC_LABEL
616
  { 6,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #6 = ANNOTATION_LABEL
617
  { 7,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #7 = KILL
618
  { 8,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #8 = EXTRACT_SUBREG
619
  { 9,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #9 = INSERT_SUBREG
620
  { 10, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #10 = IMPLICIT_DEF
621
  { 11, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #11 = SUBREG_TO_REG
622
  { 12, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #12 = COPY_TO_REGCLASS
623
  { 13, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #13 = DBG_VALUE
624
  { 14, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #14 = DBG_LABEL
625
  { 15, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #15 = REG_SEQUENCE
626
  { 16, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #16 = COPY
627
  { 17, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #17 = BUNDLE
628
  { 18, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #18 = LIFETIME_START
629
  { 19, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #19 = LIFETIME_END
630
  { 20, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #20 = STACKMAP
631
  { 21, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #21 = FENTRY_CALL
632
  { 22, 6,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #22 = PATCHPOINT
633
  { 23, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #23 = LOAD_STACK_GUARD
634
  { 24, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #24 = STATEPOINT
635
  { 25, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #25 = LOCAL_ESCAPE
636
  { 26, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #26 = FAULTING_OP
637
  { 27, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #27 = PATCHABLE_OP
638
  { 28, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #28 = PATCHABLE_FUNCTION_ENTER
639
  { 29, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #29 = PATCHABLE_RET
640
  { 30, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #30 = PATCHABLE_FUNCTION_EXIT
641
  { 31, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #31 = PATCHABLE_TAIL_CALL
642
  { 32, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #32 = PATCHABLE_EVENT_CALL
643
  { 33, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
644
  { 34, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #34 = ICALL_BRANCH_FUNNEL
645
  { 35, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #35 = G_ADD
646
  { 36, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #36 = G_SUB
647
  { 37, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #37 = G_MUL
648
  { 38, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #38 = G_SDIV
649
  { 39, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #39 = G_UDIV
650
  { 40, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #40 = G_SREM
651
  { 41, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_UREM
652
  { 42, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_AND
653
  { 43, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #43 = G_OR
654
  { 44, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #44 = G_XOR
655
  { 45, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #45 = G_IMPLICIT_DEF
656
  { 46, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #46 = G_PHI
657
  { 47, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #47 = G_FRAME_INDEX
658
  { 48, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #48 = G_GLOBAL_VALUE
659
  { 49, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #49 = G_EXTRACT
660
  { 50, 2,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #50 = G_UNMERGE_VALUES
661
  { 51, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #51 = G_INSERT
662
  { 52, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #52 = G_MERGE_VALUES
663
  { 53, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = G_BUILD_VECTOR
664
  { 54, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #54 = G_BUILD_VECTOR_TRUNC
665
  { 55, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #55 = G_CONCAT_VECTORS
666
  { 56, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #56 = G_PTRTOINT
667
  { 57, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #57 = G_INTTOPTR
668
  { 58, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #58 = G_BITCAST
669
  { 59, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #59 = G_INTRINSIC_TRUNC
670
  { 60, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #60 = G_INTRINSIC_ROUND
671
  { 61, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #61 = G_LOAD
672
  { 62, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #62 = G_SEXTLOAD
673
  { 63, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #63 = G_ZEXTLOAD
674
  { 64, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #64 = G_STORE
675
  { 65, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #65 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
676
  { 66, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #66 = G_ATOMIC_CMPXCHG
677
  { 67, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #67 = G_ATOMICRMW_XCHG
678
  { 68, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #68 = G_ATOMICRMW_ADD
679
  { 69, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #69 = G_ATOMICRMW_SUB
680
  { 70, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #70 = G_ATOMICRMW_AND
681
  { 71, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #71 = G_ATOMICRMW_NAND
682
  { 72, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #72 = G_ATOMICRMW_OR
683
  { 73, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #73 = G_ATOMICRMW_XOR
684
  { 74, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #74 = G_ATOMICRMW_MAX
685
  { 75, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #75 = G_ATOMICRMW_MIN
686
  { 76, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #76 = G_ATOMICRMW_UMAX
687
  { 77, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #77 = G_ATOMICRMW_UMIN
688
  { 78, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #78 = G_BRCOND
689
  { 79, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #79 = G_BRINDIRECT
690
  { 80, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #80 = G_INTRINSIC
691
  { 81, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #81 = G_INTRINSIC_W_SIDE_EFFECTS
692
  { 82, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #82 = G_ANYEXT
693
  { 83, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #83 = G_TRUNC
694
  { 84, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #84 = G_CONSTANT
695
  { 85, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #85 = G_FCONSTANT
696
  { 86, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #86 = G_VASTART
697
  { 87, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #87 = G_VAARG
698
  { 88, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #88 = G_SEXT
699
  { 89, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #89 = G_ZEXT
700
  { 90, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #90 = G_SHL
701
  { 91, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #91 = G_LSHR
702
  { 92, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #92 = G_ASHR
703
  { 93, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #93 = G_ICMP
704
  { 94, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #94 = G_FCMP
705
  { 95, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #95 = G_SELECT
706
  { 96, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #96 = G_UADDO
707
  { 97, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #97 = G_UADDE
708
  { 98, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #98 = G_USUBO
709
  { 99, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #99 = G_USUBE
710
  { 100,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #100 = G_SADDO
711
  { 101,  5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #101 = G_SADDE
712
  { 102,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #102 = G_SSUBO
713
  { 103,  5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #103 = G_SSUBE
714
  { 104,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #104 = G_UMULO
715
  { 105,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #105 = G_SMULO
716
  { 106,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #106 = G_UMULH
717
  { 107,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #107 = G_SMULH
718
  { 108,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #108 = G_FADD
719
  { 109,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #109 = G_FSUB
720
  { 110,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #110 = G_FMUL
721
  { 111,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #111 = G_FMA
722
  { 112,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #112 = G_FDIV
723
  { 113,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #113 = G_FREM
724
  { 114,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #114 = G_FPOW
725
  { 115,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #115 = G_FEXP
726
  { 116,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #116 = G_FEXP2
727
  { 117,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #117 = G_FLOG
728
  { 118,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #118 = G_FLOG2
729
  { 119,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #119 = G_FLOG10
730
  { 120,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #120 = G_FNEG
731
  { 121,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #121 = G_FPEXT
732
  { 122,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #122 = G_FPTRUNC
733
  { 123,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #123 = G_FPTOSI
734
  { 124,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #124 = G_FPTOUI
735
  { 125,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #125 = G_SITOFP
736
  { 126,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #126 = G_UITOFP
737
  { 127,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #127 = G_FABS
738
  { 128,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #128 = G_FCANONICALIZE
739
  { 129,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #129 = G_GEP
740
  { 130,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #130 = G_PTR_MASK
741
  { 131,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #131 = G_BR
742
  { 132,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #132 = G_INSERT_VECTOR_ELT
743
  { 133,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #133 = G_EXTRACT_VECTOR_ELT
744
  { 134,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #134 = G_SHUFFLE_VECTOR
745
  { 135,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #135 = G_CTTZ
746
  { 136,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #136 = G_CTTZ_ZERO_UNDEF
747
  { 137,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #137 = G_CTLZ
748
  { 138,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #138 = G_CTLZ_ZERO_UNDEF
749
  { 139,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #139 = G_CTPOP
750
  { 140,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #140 = G_BSWAP
751
  { 141,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #141 = G_FCEIL
752
  { 142,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #142 = G_FCOS
753
  { 143,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #143 = G_FSIN
754
  { 144,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #144 = G_FSQRT
755
  { 145,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #145 = G_FFLOOR
756
  { 146,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #146 = G_ADDRSPACE_CAST
757
  { 147,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #147 = G_BLOCK_ADDR
758
  { 148,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #148 = ADD16mc
759
  { 149,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #149 = ADD16mi
760
  { 150,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #150 = ADD16mm
761
  { 151,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #151 = ADD16mn
762
  { 152,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #152 = ADD16mp
763
  { 153,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #153 = ADD16mr
764
  { 154,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #154 = ADD16rc
765
  { 155,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #155 = ADD16ri
766
  { 156,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #156 = ADD16rm
767
  { 157,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #157 = ADD16rn
768
  { 158,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #158 = ADD16rp
769
  { 159,  3,  1,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #159 = ADD16rr
770
  { 160,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #160 = ADD8mc
771
  { 161,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #161 = ADD8mi
772
  { 162,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #162 = ADD8mm
773
  { 163,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #163 = ADD8mn
774
  { 164,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #164 = ADD8mp
775
  { 165,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #165 = ADD8mr
776
  { 166,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #166 = ADD8rc
777
  { 167,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #167 = ADD8ri
778
  { 168,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #168 = ADD8rm
779
  { 169,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #169 = ADD8rn
780
  { 170,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #170 = ADD8rp
781
  { 171,  3,  1,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #171 = ADD8rr
782
  { 172,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #172 = ADDC16mc
783
  { 173,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #173 = ADDC16mi
784
  { 174,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #174 = ADDC16mm
785
  { 175,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #175 = ADDC16mn
786
  { 176,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #176 = ADDC16mp
787
  { 177,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #177 = ADDC16mr
788
  { 178,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #178 = ADDC16rc
789
  { 179,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #179 = ADDC16ri
790
  { 180,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #180 = ADDC16rm
791
  { 181,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #181 = ADDC16rn
792
  { 182,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #182 = ADDC16rp
793
  { 183,  3,  1,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #183 = ADDC16rr
794
  { 184,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #184 = ADDC8mc
795
  { 185,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #185 = ADDC8mi
796
  { 186,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #186 = ADDC8mm
797
  { 187,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #187 = ADDC8mn
798
  { 188,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #188 = ADDC8mp
799
  { 189,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #189 = ADDC8mr
800
  { 190,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #190 = ADDC8rc
801
  { 191,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #191 = ADDC8ri
802
  { 192,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #192 = ADDC8rm
803
  { 193,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #193 = ADDC8rn
804
  { 194,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #194 = ADDC8rp
805
  { 195,  3,  1,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #195 = ADDC8rr
806
  { 196,  3,  1,  0,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo49, -1 ,nullptr },  // Inst #196 = ADDframe
807
  { 197,  2,  0,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo8, -1 ,nullptr },  // Inst #197 = ADJCALLSTACKDOWN
808
  { 198,  2,  0,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo8, -1 ,nullptr },  // Inst #198 = ADJCALLSTACKUP
809
  { 199,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #199 = AND16mc
810
  { 200,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #200 = AND16mi
811
  { 201,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #201 = AND16mm
812
  { 202,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #202 = AND16mn
813
  { 203,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #203 = AND16mp
814
  { 204,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #204 = AND16mr
815
  { 205,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #205 = AND16rc
816
  { 206,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #206 = AND16ri
817
  { 207,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #207 = AND16rm
818
  { 208,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #208 = AND16rn
819
  { 209,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #209 = AND16rp
820
  { 210,  3,  1,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #210 = AND16rr
821
  { 211,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #211 = AND8mc
822
  { 212,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #212 = AND8mi
823
  { 213,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #213 = AND8mm
824
  { 214,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #214 = AND8mn
825
  { 215,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #215 = AND8mp
826
  { 216,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #216 = AND8mr
827
  { 217,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #217 = AND8rc
828
  { 218,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #218 = AND8ri
829
  { 219,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #219 = AND8rm
830
  { 220,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #220 = AND8rn
831
  { 221,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #221 = AND8rp
832
  { 222,  3,  1,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #222 = AND8rr
833
  { 223,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #223 = BIC16mc
834
  { 224,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #224 = BIC16mi
835
  { 225,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #225 = BIC16mm
836
  { 226,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #226 = BIC16mn
837
  { 227,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #227 = BIC16mp
838
  { 228,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #228 = BIC16mr
839
  { 229,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #229 = BIC16rc
840
  { 230,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #230 = BIC16ri
841
  { 231,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #231 = BIC16rm
842
  { 232,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #232 = BIC16rn
843
  { 233,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #233 = BIC16rp
844
  { 234,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #234 = BIC16rr
845
  { 235,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #235 = BIC8mc
846
  { 236,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #236 = BIC8mi
847
  { 237,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #237 = BIC8mm
848
  { 238,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #238 = BIC8mn
849
  { 239,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #239 = BIC8mp
850
  { 240,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #240 = BIC8mr
851
  { 241,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #241 = BIC8rc
852
  { 242,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #242 = BIC8ri
853
  { 243,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #243 = BIC8rm
854
  { 244,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #244 = BIC8rn
855
  { 245,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #245 = BIC8rp
856
  { 246,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #246 = BIC8rr
857
  { 247,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #247 = BIS16mc
858
  { 248,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #248 = BIS16mi
859
  { 249,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #249 = BIS16mm
860
  { 250,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #250 = BIS16mn
861
  { 251,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #251 = BIS16mp
862
  { 252,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #252 = BIS16mr
863
  { 253,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #253 = BIS16rc
864
  { 254,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #254 = BIS16ri
865
  { 255,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #255 = BIS16rm
866
  { 256,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #256 = BIS16rn
867
  { 257,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #257 = BIS16rp
868
  { 258,  3,  1,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #258 = BIS16rr
869
  { 259,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #259 = BIS8mc
870
  { 260,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #260 = BIS8mi
871
  { 261,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #261 = BIS8mm
872
  { 262,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #262 = BIS8mn
873
  { 263,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #263 = BIS8mp
874
  { 264,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #264 = BIS8mr
875
  { 265,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #265 = BIS8rc
876
  { 266,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #266 = BIS8ri
877
  { 267,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #267 = BIS8rm
878
  { 268,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #268 = BIS8rn
879
  { 269,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #269 = BIS8rp
880
  { 270,  3,  1,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #270 = BIS8rr
881
  { 271,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #271 = BIT16mc
882
  { 272,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #272 = BIT16mi
883
  { 273,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #273 = BIT16mm
884
  { 274,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #274 = BIT16mn
885
  { 275,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #275 = BIT16mp
886
  { 276,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #276 = BIT16mr
887
  { 277,  2,  0,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr },  // Inst #277 = BIT16rc
888
  { 278,  2,  0,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr },  // Inst #278 = BIT16ri
889
  { 279,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr },  // Inst #279 = BIT16rm
890
  { 280,  2,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #280 = BIT16rn
891
  { 281,  2,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #281 = BIT16rp
892
  { 282,  2,  0,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo54, -1 ,nullptr },  // Inst #282 = BIT16rr
893
  { 283,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #283 = BIT8mc
894
  { 284,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #284 = BIT8mi
895
  { 285,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #285 = BIT8mm
896
  { 286,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #286 = BIT8mn
897
  { 287,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #287 = BIT8mp
898
  { 288,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #288 = BIT8mr
899
  { 289,  2,  0,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #289 = BIT8rc
900
  { 290,  2,  0,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #290 = BIT8ri
901
  { 291,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo57, -1 ,nullptr },  // Inst #291 = BIT8rm
902
  { 292,  2,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo58, -1 ,nullptr },  // Inst #292 = BIT8rn
903
  { 293,  2,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo58, -1 ,nullptr },  // Inst #293 = BIT8rp
904
  { 294,  2,  0,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #294 = BIT8rr
905
  { 295,  1,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #295 = Bi
906
  { 296,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #296 = Bm
907
  { 297,  1,  0,  2,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #297 = Br
908
  { 298,  1,  0,  4,  0,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList4, OperandInfo3, -1 ,nullptr },  // Inst #298 = CALLi
909
  { 299,  2,  0,  4,  0,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList4, OperandInfo60, -1 ,nullptr },  // Inst #299 = CALLm
910
  { 300,  1,  0,  2,  0,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList4, OperandInfo62, -1 ,nullptr },  // Inst #300 = CALLn
911
  { 301,  1,  0,  2,  0,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList4, OperandInfo62, -1 ,nullptr },  // Inst #301 = CALLp
912
  { 302,  1,  0,  2,  0,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList4, OperandInfo61, -1 ,nullptr },  // Inst #302 = CALLr
913
  { 303,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #303 = CMP16mc
914
  { 304,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #304 = CMP16mi
915
  { 305,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #305 = CMP16mm
916
  { 306,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #306 = CMP16mn
917
  { 307,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #307 = CMP16mp
918
  { 308,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #308 = CMP16mr
919
  { 309,  2,  0,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr },  // Inst #309 = CMP16rc
920
  { 310,  2,  0,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr },  // Inst #310 = CMP16ri
921
  { 311,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr },  // Inst #311 = CMP16rm
922
  { 312,  2,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #312 = CMP16rn
923
  { 313,  2,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #313 = CMP16rp
924
  { 314,  2,  0,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo54, -1 ,nullptr },  // Inst #314 = CMP16rr
925
  { 315,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #315 = CMP8mc
926
  { 316,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #316 = CMP8mi
927
  { 317,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #317 = CMP8mm
928
  { 318,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #318 = CMP8mn
929
  { 319,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #319 = CMP8mp
930
  { 320,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #320 = CMP8mr
931
  { 321,  2,  0,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #321 = CMP8rc
932
  { 322,  2,  0,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #322 = CMP8ri
933
  { 323,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo57, -1 ,nullptr },  // Inst #323 = CMP8rm
934
  { 324,  2,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo58, -1 ,nullptr },  // Inst #324 = CMP8rn
935
  { 325,  2,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo58, -1 ,nullptr },  // Inst #325 = CMP8rp
936
  { 326,  2,  0,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #326 = CMP8rr
937
  { 327,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #327 = DADD16mc
938
  { 328,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #328 = DADD16mi
939
  { 329,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #329 = DADD16mm
940
  { 330,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #330 = DADD16mn
941
  { 331,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #331 = DADD16mp
942
  { 332,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #332 = DADD16mr
943
  { 333,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #333 = DADD16rc
944
  { 334,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #334 = DADD16ri
945
  { 335,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #335 = DADD16rm
946
  { 336,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #336 = DADD16rn
947
  { 337,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #337 = DADD16rp
948
  { 338,  3,  1,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #338 = DADD16rr
949
  { 339,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #339 = DADD8mc
950
  { 340,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #340 = DADD8mi
951
  { 341,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #341 = DADD8mm
952
  { 342,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #342 = DADD8mn
953
  { 343,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #343 = DADD8mp
954
  { 344,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #344 = DADD8mr
955
  { 345,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #345 = DADD8rc
956
  { 346,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #346 = DADD8ri
957
  { 347,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #347 = DADD8rm
958
  { 348,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #348 = DADD8rn
959
  { 349,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #349 = DADD8rp
960
  { 350,  3,  1,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #350 = DADD8rr
961
  { 351,  2,  0,  2,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #351 = JCC
962
  { 352,  1,  0,  2,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #352 = JMP
963
  { 353,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #353 = MOV16mc
964
  { 354,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #354 = MOV16mi
965
  { 355,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #355 = MOV16mm
966
  { 356,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #356 = MOV16mn
967
  { 357,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #357 = MOV16mr
968
  { 358,  2,  1,  2,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #358 = MOV16rc
969
  { 359,  2,  1,  4,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #359 = MOV16ri
970
  { 360,  3,  1,  4,  0,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #360 = MOV16rm
971
  { 361,  2,  1,  2,  0,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #361 = MOV16rn
972
  { 362,  3,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #362 = MOV16rp
973
  { 363,  2,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #363 = MOV16rr
974
  { 364,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #364 = MOV8mc
975
  { 365,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #365 = MOV8mi
976
  { 366,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #366 = MOV8mm
977
  { 367,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #367 = MOV8mn
978
  { 368,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #368 = MOV8mr
979
  { 369,  2,  1,  2,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #369 = MOV8rc
980
  { 370,  2,  1,  4,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #370 = MOV8ri
981
  { 371,  3,  1,  4,  0,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #371 = MOV8rm
982
  { 372,  2,  1,  2,  0,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #372 = MOV8rn
983
  { 373,  3,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr },  // Inst #373 = MOV8rp
984
  { 374,  2,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #374 = MOV8rr
985
  { 375,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #375 = MOVZX16rm8
986
  { 376,  2,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr },  // Inst #376 = MOVZX16rr8
987
  { 377,  1,  1,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo61, -1 ,nullptr },  // Inst #377 = POP16r
988
  { 378,  1,  0,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo2, -1 ,nullptr },  // Inst #378 = PUSH16c
989
  { 379,  1,  0,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo3, -1 ,nullptr },  // Inst #379 = PUSH16i
990
  { 380,  1,  0,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo61, -1 ,nullptr },  // Inst #380 = PUSH16r
991
  { 381,  1,  0,  2,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo66, -1 ,nullptr },  // Inst #381 = PUSH8r
992
  { 382,  0,  0,  2,  0,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #382 = RET
993
  { 383,  0,  0,  2,  0,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #383 = RETI
994
  { 384,  2,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo60, -1 ,nullptr },  // Inst #384 = RRA16m
995
  { 385,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo62, -1 ,nullptr },  // Inst #385 = RRA16n
996
  { 386,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo62, -1 ,nullptr },  // Inst #386 = RRA16p
997
  { 387,  2,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #387 = RRA16r
998
  { 388,  2,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo60, -1 ,nullptr },  // Inst #388 = RRA8m
999
  { 389,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo62, -1 ,nullptr },  // Inst #389 = RRA8n
1000
  { 390,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo62, -1 ,nullptr },  // Inst #390 = RRA8p
1001
  { 391,  2,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo68, -1 ,nullptr },  // Inst #391 = RRA8r
1002
  { 392,  2,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo60, -1 ,nullptr },  // Inst #392 = RRC16m
1003
  { 393,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo62, -1 ,nullptr },  // Inst #393 = RRC16n
1004
  { 394,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo62, -1 ,nullptr },  // Inst #394 = RRC16p
1005
  { 395,  2,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #395 = RRC16r
1006
  { 396,  2,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo60, -1 ,nullptr },  // Inst #396 = RRC8m
1007
  { 397,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo62, -1 ,nullptr },  // Inst #397 = RRC8n
1008
  { 398,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo62, -1 ,nullptr },  // Inst #398 = RRC8p
1009
  { 399,  2,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo68, -1 ,nullptr },  // Inst #399 = RRC8r
1010
  { 400,  2,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo54, -1 ,nullptr },  // Inst #400 = Rrcl16
1011
  { 401,  2,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #401 = Rrcl8
1012
  { 402,  2,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo60, -1 ,nullptr },  // Inst #402 = SEXT16m
1013
  { 403,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo62, -1 ,nullptr },  // Inst #403 = SEXT16n
1014
  { 404,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo62, -1 ,nullptr },  // Inst #404 = SEXT16p
1015
  { 405,  2,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #405 = SEXT16r
1016
  { 406,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #406 = SUB16mc
1017
  { 407,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #407 = SUB16mi
1018
  { 408,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #408 = SUB16mm
1019
  { 409,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #409 = SUB16mn
1020
  { 410,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #410 = SUB16mp
1021
  { 411,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #411 = SUB16mr
1022
  { 412,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #412 = SUB16rc
1023
  { 413,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #413 = SUB16ri
1024
  { 414,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #414 = SUB16rm
1025
  { 415,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #415 = SUB16rn
1026
  { 416,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #416 = SUB16rp
1027
  { 417,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #417 = SUB16rr
1028
  { 418,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #418 = SUB8mc
1029
  { 419,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #419 = SUB8mi
1030
  { 420,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #420 = SUB8mm
1031
  { 421,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #421 = SUB8mn
1032
  { 422,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #422 = SUB8mp
1033
  { 423,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #423 = SUB8mr
1034
  { 424,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #424 = SUB8rc
1035
  { 425,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #425 = SUB8ri
1036
  { 426,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #426 = SUB8rm
1037
  { 427,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #427 = SUB8rn
1038
  { 428,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #428 = SUB8rp
1039
  { 429,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #429 = SUB8rr
1040
  { 430,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #430 = SUBC16mc
1041
  { 431,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #431 = SUBC16mi
1042
  { 432,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #432 = SUBC16mm
1043
  { 433,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #433 = SUBC16mn
1044
  { 434,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #434 = SUBC16mp
1045
  { 435,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #435 = SUBC16mr
1046
  { 436,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #436 = SUBC16rc
1047
  { 437,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #437 = SUBC16ri
1048
  { 438,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #438 = SUBC16rm
1049
  { 439,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #439 = SUBC16rn
1050
  { 440,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #440 = SUBC16rp
1051
  { 441,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #441 = SUBC16rr
1052
  { 442,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #442 = SUBC8mc
1053
  { 443,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #443 = SUBC8mi
1054
  { 444,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #444 = SUBC8mm
1055
  { 445,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #445 = SUBC8mn
1056
  { 446,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #446 = SUBC8mp
1057
  { 447,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #447 = SUBC8mr
1058
  { 448,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #448 = SUBC8rc
1059
  { 449,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #449 = SUBC8ri
1060
  { 450,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #450 = SUBC8rm
1061
  { 451,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #451 = SUBC8rn
1062
  { 452,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #452 = SUBC8rp
1063
  { 453,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #453 = SUBC8rr
1064
  { 454,  2,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #454 = SWPB16m
1065
  { 455,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #455 = SWPB16n
1066
  { 456,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #456 = SWPB16p
1067
  { 457,  2,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #457 = SWPB16r
1068
  { 458,  4,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #458 = Select16
1069
  { 459,  4,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #459 = Select8
1070
  { 460,  3,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr },  // Inst #460 = Shl16
1071
  { 461,  3,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr },  // Inst #461 = Shl8
1072
  { 462,  3,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr },  // Inst #462 = Sra16
1073
  { 463,  3,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr },  // Inst #463 = Sra8
1074
  { 464,  3,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr },  // Inst #464 = Srl16
1075
  { 465,  3,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr },  // Inst #465 = Srl8
1076
  { 466,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #466 = XOR16mc
1077
  { 467,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #467 = XOR16mi
1078
  { 468,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #468 = XOR16mm
1079
  { 469,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #469 = XOR16mn
1080
  { 470,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #470 = XOR16mp
1081
  { 471,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #471 = XOR16mr
1082
  { 472,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #472 = XOR16rc
1083
  { 473,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #473 = XOR16ri
1084
  { 474,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #474 = XOR16rm
1085
  { 475,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #475 = XOR16rn
1086
  { 476,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #476 = XOR16rp
1087
  { 477,  3,  1,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #477 = XOR16rr
1088
  { 478,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #478 = XOR8mc
1089
  { 479,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #479 = XOR8mi
1090
  { 480,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #480 = XOR8mm
1091
  { 481,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #481 = XOR8mn
1092
  { 482,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #482 = XOR8mp
1093
  { 483,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #483 = XOR8mr
1094
  { 484,  3,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #484 = XOR8rc
1095
  { 485,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #485 = XOR8ri
1096
  { 486,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #486 = XOR8rm
1097
  { 487,  3,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #487 = XOR8rn
1098
  { 488,  4,  2,  2,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #488 = XOR8rp
1099
  { 489,  3,  1,  2,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #489 = XOR8rr
1100
  { 490,  2,  1,  2,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #490 = ZEXT16r
1101
};
1102
1103
extern const char MSP430InstrNameData[] = {
1104
  /* 0 */ 'G', '_', 'F', 'L', 'O', 'G', '1', '0', 0,
1105
  /* 9 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0,
1106
  /* 17 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0,
1107
  /* 25 */ 'S', 'r', 'a', '1', '6', 0,
1108
  /* 31 */ 'R', 'r', 'c', 'l', '1', '6', 0,
1109
  /* 38 */ 'S', 'h', 'l', '1', '6', 0,
1110
  /* 44 */ 'S', 'r', 'l', '1', '6', 0,
1111
  /* 50 */ 'S', 'e', 'l', 'e', 'c', 't', '1', '6', 0,
1112
  /* 59 */ 'S', 'r', 'a', '8', 0,
1113
  /* 64 */ 'R', 'r', 'c', 'l', '8', 0,
1114
  /* 70 */ 'S', 'h', 'l', '8', 0,
1115
  /* 75 */ 'S', 'r', 'l', '8', 0,
1116
  /* 80 */ 'M', 'O', 'V', 'Z', 'X', '1', '6', 'r', 'm', '8', 0,
1117
  /* 91 */ 'M', 'O', 'V', 'Z', 'X', '1', '6', 'r', 'r', '8', 0,
1118
  /* 102 */ 'S', 'e', 'l', 'e', 'c', 't', '8', 0,
1119
  /* 110 */ 'G', '_', 'F', 'M', 'A', 0,
1120
  /* 116 */ 'G', '_', 'F', 'S', 'U', 'B', 0,
1121
  /* 123 */ 'G', '_', 'S', 'U', 'B', 0,
1122
  /* 129 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'S', 'U', 'B', 0,
1123
  /* 145 */ 'J', 'C', 'C', 0,
1124
  /* 149 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', 0,
1125
  /* 161 */ 'G', '_', 'F', 'P', 'T', 'R', 'U', 'N', 'C', 0,
1126
  /* 171 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'T', 'R', 'U', 'N', 'C', 0,
1127
  /* 189 */ 'G', '_', 'T', 'R', 'U', 'N', 'C', 0,
1128
  /* 197 */ 'G', '_', 'B', 'U', 'I', 'L', 'D', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'T', 'R', 'U', 'N', 'C', 0,
1129
  /* 218 */ 'G', '_', 'S', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
1130
  /* 229 */ 'G', '_', 'Z', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
1131
  /* 240 */ 'G', '_', 'L', 'O', 'A', 'D', 0,
1132
  /* 247 */ 'G', '_', 'F', 'A', 'D', 'D', 0,
1133
  /* 254 */ 'G', '_', 'A', 'D', 'D', 0,
1134
  /* 260 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'D', 'D', 0,
1135
  /* 276 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'N', 'A', 'N', 'D', 0,
1136
  /* 293 */ 'G', '_', 'A', 'N', 'D', 0,
1137
  /* 299 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'N', 'D', 0,
1138
  /* 315 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
1139
  /* 328 */ 'G', '_', 'B', 'R', 'C', 'O', 'N', 'D', 0,
1140
  /* 337 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'R', 'O', 'U', 'N', 'D', 0,
1141
  /* 355 */ 'L', 'O', 'A', 'D', '_', 'S', 'T', 'A', 'C', 'K', '_', 'G', 'U', 'A', 'R', 'D', 0,
1142
  /* 372 */ 'G', '_', 'S', 'S', 'U', 'B', 'E', 0,
1143
  /* 380 */ 'G', '_', 'U', 'S', 'U', 'B', 'E', 0,
1144
  /* 388 */ 'R', 'E', 'G', '_', 'S', 'E', 'Q', 'U', 'E', 'N', 'C', 'E', 0,
1145
  /* 401 */ 'G', '_', 'S', 'A', 'D', 'D', 'E', 0,
1146
  /* 409 */ 'G', '_', 'U', 'A', 'D', 'D', 'E', 0,
1147
  /* 417 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
1148
  /* 424 */ 'L', 'O', 'C', 'A', 'L', '_', 'E', 'S', 'C', 'A', 'P', 'E', 0,
1149
  /* 437 */ 'G', '_', 'S', 'T', 'O', 'R', 'E', 0,
1150
  /* 445 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
1151
  /* 455 */ 'G', '_', 'G', 'L', 'O', 'B', 'A', 'L', '_', 'V', 'A', 'L', 'U', 'E', 0,
1152
  /* 470 */ 'G', '_', 'F', 'C', 'A', 'N', 'O', 'N', 'I', 'C', 'A', 'L', 'I', 'Z', 'E', 0,
1153
  /* 486 */ 'G', '_', 'C', 'T', 'L', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
1154
  /* 504 */ 'G', '_', 'C', 'T', 'T', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
1155
  /* 522 */ 'G', '_', 'I', 'M', 'P', 'L', 'I', 'C', 'I', 'T', '_', 'D', 'E', 'F', 0,
1156
  /* 537 */ 'G', '_', 'F', 'N', 'E', 'G', 0,
1157
  /* 544 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
1158
  /* 559 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
1159
  /* 573 */ 'S', 'U', 'B', 'R', 'E', 'G', '_', 'T', 'O', '_', 'R', 'E', 'G', 0,
1160
  /* 587 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', 0,
1161
  /* 604 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'C', 'H', 'G', 0,
1162
  /* 621 */ 'G', '_', 'F', 'L', 'O', 'G', 0,
1163
  /* 628 */ 'G', '_', 'V', 'A', 'A', 'R', 'G', 0,
1164
  /* 636 */ 'G', '_', 'S', 'M', 'U', 'L', 'H', 0,
1165
  /* 644 */ 'G', '_', 'U', 'M', 'U', 'L', 'H', 0,
1166
  /* 652 */ 'G', '_', 'P', 'H', 'I', 0,
1167
  /* 658 */ 'G', '_', 'F', 'P', 'T', 'O', 'S', 'I', 0,
1168
  /* 667 */ 'R', 'E', 'T', 'I', 0,
1169
  /* 672 */ 'G', '_', 'F', 'P', 'T', 'O', 'U', 'I', 0,
1170
  /* 681 */ 'G', '_', 'P', 'T', 'R', '_', 'M', 'A', 'S', 'K', 0,
1171
  /* 692 */ 'G', 'C', '_', 'L', 'A', 'B', 'E', 'L', 0,
1172
  /* 701 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0,
1173
  /* 711 */ 'E', 'H', '_', 'L', 'A', 'B', 'E', 'L', 0,
1174
  /* 720 */ 'A', 'N', 'N', 'O', 'T', 'A', 'T', 'I', 'O', 'N', '_', 'L', 'A', 'B', 'E', 'L', 0,
1175
  /* 737 */ 'I', 'C', 'A', 'L', 'L', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'F', 'U', 'N', 'N', 'E', 'L', 0,
1176
  /* 757 */ 'G', '_', 'S', 'H', 'L', 0,
1177
  /* 763 */ 'G', '_', 'F', 'C', 'E', 'I', 'L', 0,
1178
  /* 771 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'A', 'I', 'L', '_', 'C', 'A', 'L', 'L', 0,
1179
  /* 791 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
1180
  /* 818 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
1181
  /* 839 */ 'F', 'E', 'N', 'T', 'R', 'Y', '_', 'C', 'A', 'L', 'L', 0,
1182
  /* 851 */ 'K', 'I', 'L', 'L', 0,
1183
  /* 856 */ 'G', '_', 'F', 'M', 'U', 'L', 0,
1184
  /* 863 */ 'G', '_', 'M', 'U', 'L', 0,
1185
  /* 869 */ 'G', '_', 'F', 'R', 'E', 'M', 0,
1186
  /* 876 */ 'G', '_', 'S', 'R', 'E', 'M', 0,
1187
  /* 883 */ 'G', '_', 'U', 'R', 'E', 'M', 0,
1188
  /* 890 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', 0,
1189
  /* 900 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'I', 'N', 0,
1190
  /* 917 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'I', 'N', 0,
1191
  /* 933 */ 'G', '_', 'F', 'S', 'I', 'N', 0,
1192
  /* 940 */ 'C', 'F', 'I', '_', 'I', 'N', 'S', 'T', 'R', 'U', 'C', 'T', 'I', 'O', 'N', 0,
1193
  /* 956 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 0,
1194
  /* 973 */ 'G', '_', 'S', 'S', 'U', 'B', 'O', 0,
1195
  /* 981 */ 'G', '_', 'U', 'S', 'U', 'B', 'O', 0,
1196
  /* 989 */ 'G', '_', 'S', 'A', 'D', 'D', 'O', 0,
1197
  /* 997 */ 'G', '_', 'U', 'A', 'D', 'D', 'O', 0,
1198
  /* 1005 */ 'G', '_', 'S', 'M', 'U', 'L', 'O', 0,
1199
  /* 1013 */ 'G', '_', 'U', 'M', 'U', 'L', 'O', 0,
1200
  /* 1021 */ 'S', 'T', 'A', 'C', 'K', 'M', 'A', 'P', 0,
1201
  /* 1030 */ 'G', '_', 'B', 'S', 'W', 'A', 'P', 0,
1202
  /* 1038 */ 'G', '_', 'G', 'E', 'P', 0,
1203
  /* 1044 */ 'G', '_', 'S', 'I', 'T', 'O', 'F', 'P', 0,
1204
  /* 1053 */ 'G', '_', 'U', 'I', 'T', 'O', 'F', 'P', 0,
1205
  /* 1062 */ 'G', '_', 'F', 'C', 'M', 'P', 0,
1206
  /* 1069 */ 'G', '_', 'I', 'C', 'M', 'P', 0,
1207
  /* 1076 */ 'J', 'M', 'P', 0,
1208
  /* 1080 */ 'G', '_', 'C', 'T', 'P', 'O', 'P', 0,
1209
  /* 1088 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'O', 'P', 0,
1210
  /* 1101 */ 'F', 'A', 'U', 'L', 'T', 'I', 'N', 'G', '_', 'O', 'P', 0,
1211
  /* 1113 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 0,
1212
  /* 1128 */ 'G', '_', 'F', 'E', 'X', 'P', 0,
1213
  /* 1135 */ 'G', '_', 'B', 'R', 0,
1214
  /* 1140 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', '_', 'B', 'R', 0,
1215
  /* 1153 */ 'G', '_', 'B', 'L', 'O', 'C', 'K', '_', 'A', 'D', 'D', 'R', 0,
1216
  /* 1166 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'N', 'T', 'E', 'R', 0,
1217
  /* 1191 */ 'G', '_', 'A', 'S', 'H', 'R', 0,
1218
  /* 1198 */ 'G', '_', 'L', 'S', 'H', 'R', 0,
1219
  /* 1205 */ 'G', '_', 'F', 'F', 'L', 'O', 'O', 'R', 0,
1220
  /* 1214 */ 'G', '_', 'B', 'U', 'I', 'L', 'D', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
1221
  /* 1229 */ 'G', '_', 'S', 'H', 'U', 'F', 'F', 'L', 'E', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
1222
  /* 1246 */ 'G', '_', 'X', 'O', 'R', 0,
1223
  /* 1252 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'O', 'R', 0,
1224
  /* 1268 */ 'G', '_', 'O', 'R', 0,
1225
  /* 1273 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'O', 'R', 0,
1226
  /* 1288 */ 'G', '_', 'I', 'N', 'T', 'T', 'O', 'P', 'T', 'R', 0,
1227
  /* 1299 */ 'G', '_', 'F', 'A', 'B', 'S', 0,
1228
  /* 1306 */ 'G', '_', 'U', 'N', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
1229
  /* 1323 */ 'G', '_', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
1230
  /* 1338 */ 'G', '_', 'F', 'C', 'O', 'S', 0,
1231
  /* 1345 */ 'G', '_', 'C', 'O', 'N', 'C', 'A', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', 'S', 0,
1232
  /* 1362 */ 'C', 'O', 'P', 'Y', '_', 'T', 'O', '_', 'R', 'E', 'G', 'C', 'L', 'A', 'S', 'S', 0,
1233
  /* 1379 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'W', 'I', 'T', 'H', '_', 'S', 'U', 'C', 'C', 'E', 'S', 'S', 0,
1234
  /* 1409 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'W', '_', 'S', 'I', 'D', 'E', '_', 'E', 'F', 'F', 'E', 'C', 'T', 'S', 0,
1235
  /* 1436 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', 0,
1236
  /* 1446 */ 'G', '_', 'S', 'E', 'L', 'E', 'C', 'T', 0,
1237
  /* 1455 */ 'G', '_', 'B', 'R', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', 0,
1238
  /* 1468 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'R', 'E', 'T', 0,
1239
  /* 1482 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'X', 'I', 'T', 0,
1240
  /* 1506 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
1241
  /* 1527 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
1242
  /* 1547 */ 'G', '_', 'F', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
1243
  /* 1559 */ 'G', '_', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
1244
  /* 1570 */ 'S', 'T', 'A', 'T', 'E', 'P', 'O', 'I', 'N', 'T', 0,
1245
  /* 1581 */ 'P', 'A', 'T', 'C', 'H', 'P', 'O', 'I', 'N', 'T', 0,
1246
  /* 1592 */ 'G', '_', 'P', 'T', 'R', 'T', 'O', 'I', 'N', 'T', 0,
1247
  /* 1603 */ 'G', '_', 'V', 'A', 'S', 'T', 'A', 'R', 'T', 0,
1248
  /* 1613 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
1249
  /* 1628 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', 0,
1250
  /* 1637 */ 'G', '_', 'F', 'S', 'Q', 'R', 'T', 0,
1251
  /* 1645 */ 'G', '_', 'B', 'I', 'T', 'C', 'A', 'S', 'T', 0,
1252
  /* 1655 */ 'G', '_', 'A', 'D', 'D', 'R', 'S', 'P', 'A', 'C', 'E', '_', 'C', 'A', 'S', 'T', 0,
1253
  /* 1672 */ 'G', '_', 'F', 'P', 'E', 'X', 'T', 0,
1254
  /* 1680 */ 'G', '_', 'S', 'E', 'X', 'T', 0,
1255
  /* 1687 */ 'G', '_', 'A', 'N', 'Y', 'E', 'X', 'T', 0,
1256
  /* 1696 */ 'G', '_', 'Z', 'E', 'X', 'T', 0,
1257
  /* 1703 */ 'G', '_', 'F', 'D', 'I', 'V', 0,
1258
  /* 1710 */ 'G', '_', 'S', 'D', 'I', 'V', 0,
1259
  /* 1717 */ 'G', '_', 'U', 'D', 'I', 'V', 0,
1260
  /* 1724 */ 'G', '_', 'F', 'P', 'O', 'W', 0,
1261
  /* 1731 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'A', 'X', 0,
1262
  /* 1748 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'A', 'X', 0,
1263
  /* 1764 */ 'G', '_', 'F', 'R', 'A', 'M', 'E', '_', 'I', 'N', 'D', 'E', 'X', 0,
1264
  /* 1778 */ 'C', 'O', 'P', 'Y', 0,
1265
  /* 1783 */ 'G', '_', 'C', 'T', 'L', 'Z', 0,
1266
  /* 1790 */ 'G', '_', 'C', 'T', 'T', 'Z', 0,
1267
  /* 1797 */ 'P', 'U', 'S', 'H', '1', '6', 'c', 0,
1268
  /* 1805 */ 'S', 'U', 'B', '1', '6', 'm', 'c', 0,
1269
  /* 1813 */ 'S', 'U', 'B', 'C', '1', '6', 'm', 'c', 0,
1270
  /* 1822 */ 'A', 'D', 'D', 'C', '1', '6', 'm', 'c', 0,
1271
  /* 1831 */ 'B', 'I', 'C', '1', '6', 'm', 'c', 0,
1272
  /* 1839 */ 'D', 'A', 'D', 'D', '1', '6', 'm', 'c', 0,
1273
  /* 1848 */ 'A', 'N', 'D', '1', '6', 'm', 'c', 0,
1274
  /* 1856 */ 'C', 'M', 'P', '1', '6', 'm', 'c', 0,
1275
  /* 1864 */ 'X', 'O', 'R', '1', '6', 'm', 'c', 0,
1276
  /* 1872 */ 'B', 'I', 'S', '1', '6', 'm', 'c', 0,
1277
  /* 1880 */ 'B', 'I', 'T', '1', '6', 'm', 'c', 0,
1278
  /* 1888 */ 'M', 'O', 'V', '1', '6', 'm', 'c', 0,
1279
  /* 1896 */ 'S', 'U', 'B', '8', 'm', 'c', 0,
1280
  /* 1903 */ 'S', 'U', 'B', 'C', '8', 'm', 'c', 0,
1281
  /* 1911 */ 'A', 'D', 'D', 'C', '8', 'm', 'c', 0,
1282
  /* 1919 */ 'B', 'I', 'C', '8', 'm', 'c', 0,
1283
  /* 1926 */ 'D', 'A', 'D', 'D', '8', 'm', 'c', 0,
1284
  /* 1934 */ 'A', 'N', 'D', '8', 'm', 'c', 0,
1285
  /* 1941 */ 'C', 'M', 'P', '8', 'm', 'c', 0,
1286
  /* 1948 */ 'X', 'O', 'R', '8', 'm', 'c', 0,
1287
  /* 1955 */ 'B', 'I', 'S', '8', 'm', 'c', 0,
1288
  /* 1962 */ 'B', 'I', 'T', '8', 'm', 'c', 0,
1289
  /* 1969 */ 'M', 'O', 'V', '8', 'm', 'c', 0,
1290
  /* 1976 */ 'S', 'U', 'B', '1', '6', 'r', 'c', 0,
1291
  /* 1984 */ 'S', 'U', 'B', 'C', '1', '6', 'r', 'c', 0,
1292
  /* 1993 */ 'A', 'D', 'D', 'C', '1', '6', 'r', 'c', 0,
1293
  /* 2002 */ 'B', 'I', 'C', '1', '6', 'r', 'c', 0,
1294
  /* 2010 */ 'D', 'A', 'D', 'D', '1', '6', 'r', 'c', 0,
1295
  /* 2019 */ 'A', 'N', 'D', '1', '6', 'r', 'c', 0,
1296
  /* 2027 */ 'C', 'M', 'P', '1', '6', 'r', 'c', 0,
1297
  /* 2035 */ 'X', 'O', 'R', '1', '6', 'r', 'c', 0,
1298
  /* 2043 */ 'B', 'I', 'S', '1', '6', 'r', 'c', 0,
1299
  /* 2051 */ 'B', 'I', 'T', '1', '6', 'r', 'c', 0,
1300
  /* 2059 */ 'M', 'O', 'V', '1', '6', 'r', 'c', 0,
1301
  /* 2067 */ 'S', 'U', 'B', '8', 'r', 'c', 0,
1302
  /* 2074 */ 'S', 'U', 'B', 'C', '8', 'r', 'c', 0,
1303
  /* 2082 */ 'A', 'D', 'D', 'C', '8', 'r', 'c', 0,
1304
  /* 2090 */ 'B', 'I', 'C', '8', 'r', 'c', 0,
1305
  /* 2097 */ 'D', 'A', 'D', 'D', '8', 'r', 'c', 0,
1306
  /* 2105 */ 'A', 'N', 'D', '8', 'r', 'c', 0,
1307
  /* 2112 */ 'C', 'M', 'P', '8', 'r', 'c', 0,
1308
  /* 2119 */ 'X', 'O', 'R', '8', 'r', 'c', 0,
1309
  /* 2126 */ 'B', 'I', 'S', '8', 'r', 'c', 0,
1310
  /* 2133 */ 'B', 'I', 'T', '8', 'r', 'c', 0,
1311
  /* 2140 */ 'M', 'O', 'V', '8', 'r', 'c', 0,
1312
  /* 2147 */ 'A', 'D', 'D', 'f', 'r', 'a', 'm', 'e', 0,
1313
  /* 2156 */ 'P', 'U', 'S', 'H', '1', '6', 'i', 0,
1314
  /* 2164 */ 'B', 'i', 0,
1315
  /* 2167 */ 'C', 'A', 'L', 'L', 'i', 0,
1316
  /* 2173 */ 'S', 'U', 'B', '1', '6', 'm', 'i', 0,
1317
  /* 2181 */ 'S', 'U', 'B', 'C', '1', '6', 'm', 'i', 0,
1318
  /* 2190 */ 'A', 'D', 'D', 'C', '1', '6', 'm', 'i', 0,
1319
  /* 2199 */ 'B', 'I', 'C', '1', '6', 'm', 'i', 0,
1320
  /* 2207 */ 'D', 'A', 'D', 'D', '1', '6', 'm', 'i', 0,
1321
  /* 2216 */ 'A', 'N', 'D', '1', '6', 'm', 'i', 0,
1322
  /* 2224 */ 'C', 'M', 'P', '1', '6', 'm', 'i', 0,
1323
  /* 2232 */ 'X', 'O', 'R', '1', '6', 'm', 'i', 0,
1324
  /* 2240 */ 'B', 'I', 'S', '1', '6', 'm', 'i', 0,
1325
  /* 2248 */ 'B', 'I', 'T', '1', '6', 'm', 'i', 0,
1326
  /* 2256 */ 'M', 'O', 'V', '1', '6', 'm', 'i', 0,
1327
  /* 2264 */ 'S', 'U', 'B', '8', 'm', 'i', 0,
1328
  /* 2271 */ 'S', 'U', 'B', 'C', '8', 'm', 'i', 0,
1329
  /* 2279 */ 'A', 'D', 'D', 'C', '8', 'm', 'i', 0,
1330
  /* 2287 */ 'B', 'I', 'C', '8', 'm', 'i', 0,
1331
  /* 2294 */ 'D', 'A', 'D', 'D', '8', 'm', 'i', 0,
1332
  /* 2302 */ 'A', 'N', 'D', '8', 'm', 'i', 0,
1333
  /* 2309 */ 'C', 'M', 'P', '8', 'm', 'i', 0,
1334
  /* 2316 */ 'X', 'O', 'R', '8', 'm', 'i', 0,
1335
  /* 2323 */ 'B', 'I', 'S', '8', 'm', 'i', 0,
1336
  /* 2330 */ 'B', 'I', 'T', '8', 'm', 'i', 0,
1337
  /* 2337 */ 'M', 'O', 'V', '8', 'm', 'i', 0,
1338
  /* 2344 */ 'S', 'U', 'B', '1', '6', 'r', 'i', 0,
1339
  /* 2352 */ 'S', 'U', 'B', 'C', '1', '6', 'r', 'i', 0,
1340
  /* 2361 */ 'A', 'D', 'D', 'C', '1', '6', 'r', 'i', 0,
1341
  /* 2370 */ 'B', 'I', 'C', '1', '6', 'r', 'i', 0,
1342
  /* 2378 */ 'D', 'A', 'D', 'D', '1', '6', 'r', 'i', 0,
1343
  /* 2387 */ 'A', 'N', 'D', '1', '6', 'r', 'i', 0,
1344
  /* 2395 */ 'C', 'M', 'P', '1', '6', 'r', 'i', 0,
1345
  /* 2403 */ 'X', 'O', 'R', '1', '6', 'r', 'i', 0,
1346
  /* 2411 */ 'B', 'I', 'S', '1', '6', 'r', 'i', 0,
1347
  /* 2419 */ 'B', 'I', 'T', '1', '6', 'r', 'i', 0,
1348
  /* 2427 */ 'M', 'O', 'V', '1', '6', 'r', 'i', 0,
1349
  /* 2435 */ 'S', 'U', 'B', '8', 'r', 'i', 0,
1350
  /* 2442 */ 'S', 'U', 'B', 'C', '8', 'r', 'i', 0,
1351
  /* 2450 */ 'A', 'D', 'D', 'C', '8', 'r', 'i', 0,
1352
  /* 2458 */ 'B', 'I', 'C', '8', 'r', 'i', 0,
1353
  /* 2465 */ 'D', 'A', 'D', 'D', '8', 'r', 'i', 0,
1354
  /* 2473 */ 'A', 'N', 'D', '8', 'r', 'i', 0,
1355
  /* 2480 */ 'C', 'M', 'P', '8', 'r', 'i', 0,
1356
  /* 2487 */ 'X', 'O', 'R', '8', 'r', 'i', 0,
1357
  /* 2494 */ 'B', 'I', 'S', '8', 'r', 'i', 0,
1358
  /* 2501 */ 'B', 'I', 'T', '8', 'r', 'i', 0,
1359
  /* 2508 */ 'M', 'O', 'V', '8', 'r', 'i', 0,
1360
  /* 2515 */ 'R', 'R', 'A', '1', '6', 'm', 0,
1361
  /* 2522 */ 'S', 'W', 'P', 'B', '1', '6', 'm', 0,
1362
  /* 2530 */ 'R', 'R', 'C', '1', '6', 'm', 0,
1363
  /* 2537 */ 'S', 'E', 'X', 'T', '1', '6', 'm', 0,
1364
  /* 2545 */ 'R', 'R', 'A', '8', 'm', 0,
1365
  /* 2551 */ 'R', 'R', 'C', '8', 'm', 0,
1366
  /* 2557 */ 'B', 'm', 0,
1367
  /* 2560 */ 'C', 'A', 'L', 'L', 'm', 0,
1368
  /* 2566 */ 'S', 'U', 'B', '1', '6', 'm', 'm', 0,
1369
  /* 2574 */ 'S', 'U', 'B', 'C', '1', '6', 'm', 'm', 0,
1370
  /* 2583 */ 'A', 'D', 'D', 'C', '1', '6', 'm', 'm', 0,
1371
  /* 2592 */ 'B', 'I', 'C', '1', '6', 'm', 'm', 0,
1372
  /* 2600 */ 'D', 'A', 'D', 'D', '1', '6', 'm', 'm', 0,
1373
  /* 2609 */ 'A', 'N', 'D', '1', '6', 'm', 'm', 0,
1374
  /* 2617 */ 'C', 'M', 'P', '1', '6', 'm', 'm', 0,
1375
  /* 2625 */ 'X', 'O', 'R', '1', '6', 'm', 'm', 0,
1376
  /* 2633 */ 'B', 'I', 'S', '1', '6', 'm', 'm', 0,
1377
  /* 2641 */ 'B', 'I', 'T', '1', '6', 'm', 'm', 0,
1378
  /* 2649 */ 'M', 'O', 'V', '1', '6', 'm', 'm', 0,
1379
  /* 2657 */ 'S', 'U', 'B', '8', 'm', 'm', 0,
1380
  /* 2664 */ 'S', 'U', 'B', 'C', '8', 'm', 'm', 0,
1381
  /* 2672 */ 'A', 'D', 'D', 'C', '8', 'm', 'm', 0,
1382
  /* 2680 */ 'B', 'I', 'C', '8', 'm', 'm', 0,
1383
  /* 2687 */ 'D', 'A', 'D', 'D', '8', 'm', 'm', 0,
1384
  /* 2695 */ 'A', 'N', 'D', '8', 'm', 'm', 0,
1385
  /* 2702 */ 'C', 'M', 'P', '8', 'm', 'm', 0,
1386
  /* 2709 */ 'X', 'O', 'R', '8', 'm', 'm', 0,
1387
  /* 2716 */ 'B', 'I', 'S', '8', 'm', 'm', 0,
1388
  /* 2723 */ 'B', 'I', 'T', '8', 'm', 'm', 0,
1389
  /* 2730 */ 'M', 'O', 'V', '8', 'm', 'm', 0,
1390
  /* 2737 */ 'S', 'U', 'B', '1', '6', 'r', 'm', 0,
1391
  /* 2745 */ 'S', 'U', 'B', 'C', '1', '6', 'r', 'm', 0,
1392
  /* 2754 */ 'A', 'D', 'D', 'C', '1', '6', 'r', 'm', 0,
1393
  /* 2763 */ 'B', 'I', 'C', '1', '6', 'r', 'm', 0,
1394
  /* 2771 */ 'D', 'A', 'D', 'D', '1', '6', 'r', 'm', 0,
1395
  /* 2780 */ 'A', 'N', 'D', '1', '6', 'r', 'm', 0,
1396
  /* 2788 */ 'C', 'M', 'P', '1', '6', 'r', 'm', 0,
1397
  /* 2796 */ 'X', 'O', 'R', '1', '6', 'r', 'm', 0,
1398
  /* 2804 */ 'B', 'I', 'S', '1', '6', 'r', 'm', 0,
1399
  /* 2812 */ 'B', 'I', 'T', '1', '6', 'r', 'm', 0,
1400
  /* 2820 */ 'M', 'O', 'V', '1', '6', 'r', 'm', 0,
1401
  /* 2828 */ 'S', 'U', 'B', '8', 'r', 'm', 0,
1402
  /* 2835 */ 'S', 'U', 'B', 'C', '8', 'r', 'm', 0,
1403
  /* 2843 */ 'A', 'D', 'D', 'C', '8', 'r', 'm', 0,
1404
  /* 2851 */ 'B', 'I', 'C', '8', 'r', 'm', 0,
1405
  /* 2858 */ 'D', 'A', 'D', 'D', '8', 'r', 'm', 0,
1406
  /* 2866 */ 'A', 'N', 'D', '8', 'r', 'm', 0,
1407
  /* 2873 */ 'C', 'M', 'P', '8', 'r', 'm', 0,
1408
  /* 2880 */ 'X', 'O', 'R', '8', 'r', 'm', 0,
1409
  /* 2887 */ 'B', 'I', 'S', '8', 'r', 'm', 0,
1410
  /* 2894 */ 'B', 'I', 'T', '8', 'r', 'm', 0,
1411
  /* 2901 */ 'M', 'O', 'V', '8', 'r', 'm', 0,
1412
  /* 2908 */ 'R', 'R', 'A', '1', '6', 'n', 0,
1413
  /* 2915 */ 'S', 'W', 'P', 'B', '1', '6', 'n', 0,
1414
  /* 2923 */ 'R', 'R', 'C', '1', '6', 'n', 0,
1415
  /* 2930 */ 'S', 'E', 'X', 'T', '1', '6', 'n', 0,
1416
  /* 2938 */ 'R', 'R', 'A', '8', 'n', 0,
1417
  /* 2944 */ 'R', 'R', 'C', '8', 'n', 0,
1418
  /* 2950 */ 'C', 'A', 'L', 'L', 'n', 0,
1419
  /* 2956 */ 'S', 'U', 'B', '1', '6', 'm', 'n', 0,
1420
  /* 2964 */ 'S', 'U', 'B', 'C', '1', '6', 'm', 'n', 0,
1421
  /* 2973 */ 'A', 'D', 'D', 'C', '1', '6', 'm', 'n', 0,
1422
  /* 2982 */ 'B', 'I', 'C', '1', '6', 'm', 'n', 0,
1423
  /* 2990 */ 'D', 'A', 'D', 'D', '1', '6', 'm', 'n', 0,
1424
  /* 2999 */ 'A', 'N', 'D', '1', '6', 'm', 'n', 0,
1425
  /* 3007 */ 'C', 'M', 'P', '1', '6', 'm', 'n', 0,
1426
  /* 3015 */ 'X', 'O', 'R', '1', '6', 'm', 'n', 0,
1427
  /* 3023 */ 'B', 'I', 'S', '1', '6', 'm', 'n', 0,
1428
  /* 3031 */ 'B', 'I', 'T', '1', '6', 'm', 'n', 0,
1429
  /* 3039 */ 'M', 'O', 'V', '1', '6', 'm', 'n', 0,
1430
  /* 3047 */ 'S', 'U', 'B', '8', 'm', 'n', 0,
1431
  /* 3054 */ 'S', 'U', 'B', 'C', '8', 'm', 'n', 0,
1432
  /* 3062 */ 'A', 'D', 'D', 'C', '8', 'm', 'n', 0,
1433
  /* 3070 */ 'B', 'I', 'C', '8', 'm', 'n', 0,
1434
  /* 3077 */ 'D', 'A', 'D', 'D', '8', 'm', 'n', 0,
1435
  /* 3085 */ 'A', 'N', 'D', '8', 'm', 'n', 0,
1436
  /* 3092 */ 'C', 'M', 'P', '8', 'm', 'n', 0,
1437
  /* 3099 */ 'X', 'O', 'R', '8', 'm', 'n', 0,
1438
  /* 3106 */ 'B', 'I', 'S', '8', 'm', 'n', 0,
1439
  /* 3113 */ 'B', 'I', 'T', '8', 'm', 'n', 0,
1440
  /* 3120 */ 'M', 'O', 'V', '8', 'm', 'n', 0,
1441
  /* 3127 */ 'S', 'U', 'B', '1', '6', 'r', 'n', 0,
1442
  /* 3135 */ 'S', 'U', 'B', 'C', '1', '6', 'r', 'n', 0,
1443
  /* 3144 */ 'A', 'D', 'D', 'C', '1', '6', 'r', 'n', 0,
1444
  /* 3153 */ 'B', 'I', 'C', '1', '6', 'r', 'n', 0,
1445
  /* 3161 */ 'D', 'A', 'D', 'D', '1', '6', 'r', 'n', 0,
1446
  /* 3170 */ 'A', 'N', 'D', '1', '6', 'r', 'n', 0,
1447
  /* 3178 */ 'C', 'M', 'P', '1', '6', 'r', 'n', 0,
1448
  /* 3186 */ 'X', 'O', 'R', '1', '6', 'r', 'n', 0,
1449
  /* 3194 */ 'B', 'I', 'S', '1', '6', 'r', 'n', 0,
1450
  /* 3202 */ 'B', 'I', 'T', '1', '6', 'r', 'n', 0,
1451
  /* 3210 */ 'M', 'O', 'V', '1', '6', 'r', 'n', 0,
1452
  /* 3218 */ 'S', 'U', 'B', '8', 'r', 'n', 0,
1453
  /* 3225 */ 'S', 'U', 'B', 'C', '8', 'r', 'n', 0,
1454
  /* 3233 */ 'A', 'D', 'D', 'C', '8', 'r', 'n', 0,
1455
  /* 3241 */ 'B', 'I', 'C', '8', 'r', 'n', 0,
1456
  /* 3248 */ 'D', 'A', 'D', 'D', '8', 'r', 'n', 0,
1457
  /* 3256 */ 'A', 'N', 'D', '8', 'r', 'n', 0,
1458
  /* 3263 */ 'C', 'M', 'P', '8', 'r', 'n', 0,
1459
  /* 3270 */ 'X', 'O', 'R', '8', 'r', 'n', 0,
1460
  /* 3277 */ 'B', 'I', 'S', '8', 'r', 'n', 0,
1461
  /* 3284 */ 'B', 'I', 'T', '8', 'r', 'n', 0,
1462
  /* 3291 */ 'M', 'O', 'V', '8', 'r', 'n', 0,
1463
  /* 3298 */ 'R', 'R', 'A', '1', '6', 'p', 0,
1464
  /* 3305 */ 'S', 'W', 'P', 'B', '1', '6', 'p', 0,
1465
  /* 3313 */ 'R', 'R', 'C', '1', '6', 'p', 0,
1466
  /* 3320 */ 'S', 'E', 'X', 'T', '1', '6', 'p', 0,
1467
  /* 3328 */ 'R', 'R', 'A', '8', 'p', 0,
1468
  /* 3334 */ 'R', 'R', 'C', '8', 'p', 0,
1469
  /* 3340 */ 'C', 'A', 'L', 'L', 'p', 0,
1470
  /* 3346 */ 'S', 'U', 'B', '1', '6', 'm', 'p', 0,
1471
  /* 3354 */ 'S', 'U', 'B', 'C', '1', '6', 'm', 'p', 0,
1472
  /* 3363 */ 'A', 'D', 'D', 'C', '1', '6', 'm', 'p', 0,
1473
  /* 3372 */ 'B', 'I', 'C', '1', '6', 'm', 'p', 0,
1474
  /* 3380 */ 'D', 'A', 'D', 'D', '1', '6', 'm', 'p', 0,
1475
  /* 3389 */ 'A', 'N', 'D', '1', '6', 'm', 'p', 0,
1476
  /* 3397 */ 'C', 'M', 'P', '1', '6', 'm', 'p', 0,
1477
  /* 3405 */ 'X', 'O', 'R', '1', '6', 'm', 'p', 0,
1478
  /* 3413 */ 'B', 'I', 'S', '1', '6', 'm', 'p', 0,
1479
  /* 3421 */ 'B', 'I', 'T', '1', '6', 'm', 'p', 0,
1480
  /* 3429 */ 'S', 'U', 'B', '8', 'm', 'p', 0,
1481
  /* 3436 */ 'S', 'U', 'B', 'C', '8', 'm', 'p', 0,
1482
  /* 3444 */ 'A', 'D', 'D', 'C', '8', 'm', 'p', 0,
1483
  /* 3452 */ 'B', 'I', 'C', '8', 'm', 'p', 0,
1484
  /* 3459 */ 'D', 'A', 'D', 'D', '8', 'm', 'p', 0,
1485
  /* 3467 */ 'A', 'N', 'D', '8', 'm', 'p', 0,
1486
  /* 3474 */ 'C', 'M', 'P', '8', 'm', 'p', 0,
1487
  /* 3481 */ 'X', 'O', 'R', '8', 'm', 'p', 0,
1488
  /* 3488 */ 'B', 'I', 'S', '8', 'm', 'p', 0,
1489
  /* 3495 */ 'B', 'I', 'T', '8', 'm', 'p', 0,
1490
  /* 3502 */ 'S', 'U', 'B', '1', '6', 'r', 'p', 0,
1491
  /* 3510 */ 'S', 'U', 'B', 'C', '1', '6', 'r', 'p', 0,
1492
  /* 3519 */ 'A', 'D', 'D', 'C', '1', '6', 'r', 'p', 0,
1493
  /* 3528 */ 'B', 'I', 'C', '1', '6', 'r', 'p', 0,
1494
  /* 3536 */ 'D', 'A', 'D', 'D', '1', '6', 'r', 'p', 0,
1495
  /* 3545 */ 'A', 'N', 'D', '1', '6', 'r', 'p', 0,
1496
  /* 3553 */ 'C', 'M', 'P', '1', '6', 'r', 'p', 0,
1497
  /* 3561 */ 'X', 'O', 'R', '1', '6', 'r', 'p', 0,
1498
  /* 3569 */ 'B', 'I', 'S', '1', '6', 'r', 'p', 0,
1499
  /* 3577 */ 'B', 'I', 'T', '1', '6', 'r', 'p', 0,
1500
  /* 3585 */ 'M', 'O', 'V', '1', '6', 'r', 'p', 0,
1501
  /* 3593 */ 'S', 'U', 'B', '8', 'r', 'p', 0,
1502
  /* 3600 */ 'S', 'U', 'B', 'C', '8', 'r', 'p', 0,
1503
  /* 3608 */ 'A', 'D', 'D', 'C', '8', 'r', 'p', 0,
1504
  /* 3616 */ 'B', 'I', 'C', '8', 'r', 'p', 0,
1505
  /* 3623 */ 'D', 'A', 'D', 'D', '8', 'r', 'p', 0,
1506
  /* 3631 */ 'A', 'N', 'D', '8', 'r', 'p', 0,
1507
  /* 3638 */ 'C', 'M', 'P', '8', 'r', 'p', 0,
1508
  /* 3645 */ 'X', 'O', 'R', '8', 'r', 'p', 0,
1509
  /* 3652 */ 'B', 'I', 'S', '8', 'r', 'p', 0,
1510
  /* 3659 */ 'B', 'I', 'T', '8', 'r', 'p', 0,
1511
  /* 3666 */ 'M', 'O', 'V', '8', 'r', 'p', 0,
1512
  /* 3673 */ 'R', 'R', 'A', '1', '6', 'r', 0,
1513
  /* 3680 */ 'S', 'W', 'P', 'B', '1', '6', 'r', 0,
1514
  /* 3688 */ 'R', 'R', 'C', '1', '6', 'r', 0,
1515
  /* 3695 */ 'P', 'U', 'S', 'H', '1', '6', 'r', 0,
1516
  /* 3703 */ 'P', 'O', 'P', '1', '6', 'r', 0,
1517
  /* 3710 */ 'S', 'E', 'X', 'T', '1', '6', 'r', 0,
1518
  /* 3718 */ 'Z', 'E', 'X', 'T', '1', '6', 'r', 0,
1519
  /* 3726 */ 'R', 'R', 'A', '8', 'r', 0,
1520
  /* 3732 */ 'R', 'R', 'C', '8', 'r', 0,
1521
  /* 3738 */ 'P', 'U', 'S', 'H', '8', 'r', 0,
1522
  /* 3745 */ 'B', 'r', 0,
1523
  /* 3748 */ 'C', 'A', 'L', 'L', 'r', 0,
1524
  /* 3754 */ 'S', 'U', 'B', '1', '6', 'm', 'r', 0,
1525
  /* 3762 */ 'S', 'U', 'B', 'C', '1', '6', 'm', 'r', 0,
1526
  /* 3771 */ 'A', 'D', 'D', 'C', '1', '6', 'm', 'r', 0,
1527
  /* 3780 */ 'B', 'I', 'C', '1', '6', 'm', 'r', 0,
1528
  /* 3788 */ 'D', 'A', 'D', 'D', '1', '6', 'm', 'r', 0,
1529
  /* 3797 */ 'A', 'N', 'D', '1', '6', 'm', 'r', 0,
1530
  /* 3805 */ 'C', 'M', 'P', '1', '6', 'm', 'r', 0,
1531
  /* 3813 */ 'X', 'O', 'R', '1', '6', 'm', 'r', 0,
1532
  /* 3821 */ 'B', 'I', 'S', '1', '6', 'm', 'r', 0,
1533
  /* 3829 */ 'B', 'I', 'T', '1', '6', 'm', 'r', 0,
1534
  /* 3837 */ 'M', 'O', 'V', '1', '6', 'm', 'r', 0,
1535
  /* 3845 */ 'S', 'U', 'B', '8', 'm', 'r', 0,
1536
  /* 3852 */ 'S', 'U', 'B', 'C', '8', 'm', 'r', 0,
1537
  /* 3860 */ 'A', 'D', 'D', 'C', '8', 'm', 'r', 0,
1538
  /* 3868 */ 'B', 'I', 'C', '8', 'm', 'r', 0,
1539
  /* 3875 */ 'D', 'A', 'D', 'D', '8', 'm', 'r', 0,
1540
  /* 3883 */ 'A', 'N', 'D', '8', 'm', 'r', 0,
1541
  /* 3890 */ 'C', 'M', 'P', '8', 'm', 'r', 0,
1542
  /* 3897 */ 'X', 'O', 'R', '8', 'm', 'r', 0,
1543
  /* 3904 */ 'B', 'I', 'S', '8', 'm', 'r', 0,
1544
  /* 3911 */ 'B', 'I', 'T', '8', 'm', 'r', 0,
1545
  /* 3918 */ 'M', 'O', 'V', '8', 'm', 'r', 0,
1546
  /* 3925 */ 'S', 'U', 'B', '1', '6', 'r', 'r', 0,
1547
  /* 3933 */ 'S', 'U', 'B', 'C', '1', '6', 'r', 'r', 0,
1548
  /* 3942 */ 'A', 'D', 'D', 'C', '1', '6', 'r', 'r', 0,
1549
  /* 3951 */ 'B', 'I', 'C', '1', '6', 'r', 'r', 0,
1550
  /* 3959 */ 'D', 'A', 'D', 'D', '1', '6', 'r', 'r', 0,
1551
  /* 3968 */ 'A', 'N', 'D', '1', '6', 'r', 'r', 0,
1552
  /* 3976 */ 'C', 'M', 'P', '1', '6', 'r', 'r', 0,
1553
  /* 3984 */ 'X', 'O', 'R', '1', '6', 'r', 'r', 0,
1554
  /* 3992 */ 'B', 'I', 'S', '1', '6', 'r', 'r', 0,
1555
  /* 4000 */ 'B', 'I', 'T', '1', '6', 'r', 'r', 0,
1556
  /* 4008 */ 'M', 'O', 'V', '1', '6', 'r', 'r', 0,
1557
  /* 4016 */ 'S', 'U', 'B', '8', 'r', 'r', 0,
1558
  /* 4023 */ 'S', 'U', 'B', 'C', '8', 'r', 'r', 0,
1559
  /* 4031 */ 'A', 'D', 'D', 'C', '8', 'r', 'r', 0,
1560
  /* 4039 */ 'B', 'I', 'C', '8', 'r', 'r', 0,
1561
  /* 4046 */ 'D', 'A', 'D', 'D', '8', 'r', 'r', 0,
1562
  /* 4054 */ 'A', 'N', 'D', '8', 'r', 'r', 0,
1563
  /* 4061 */ 'C', 'M', 'P', '8', 'r', 'r', 0,
1564
  /* 4068 */ 'X', 'O', 'R', '8', 'r', 'r', 0,
1565
  /* 4075 */ 'B', 'I', 'S', '8', 'r', 'r', 0,
1566
  /* 4082 */ 'B', 'I', 'T', '8', 'r', 'r', 0,
1567
  /* 4089 */ 'M', 'O', 'V', '8', 'r', 'r', 0,
1568
};
1569
1570
extern const unsigned MSP430InstrNameIndices[] = {
1571
    654U, 890U, 1140U, 940U, 711U, 692U, 720U, 851U, 
1572
    544U, 559U, 524U, 573U, 1362U, 445U, 701U, 388U, 
1573
    1778U, 417U, 1613U, 315U, 1021U, 839U, 1581U, 355U, 
1574
    1570U, 424U, 1101U, 1088U, 1166U, 1468U, 1482U, 771U, 
1575
    818U, 791U, 737U, 254U, 123U, 863U, 1710U, 1717U, 
1576
    876U, 883U, 293U, 1268U, 1246U, 522U, 652U, 1764U, 
1577
    455U, 1436U, 1306U, 1628U, 1323U, 1214U, 197U, 1345U, 
1578
    1592U, 1288U, 1645U, 171U, 337U, 240U, 218U, 229U, 
1579
    437U, 1379U, 587U, 604U, 260U, 129U, 299U, 276U, 
1580
    1273U, 1252U, 1748U, 917U, 1731U, 900U, 328U, 1455U, 
1581
    149U, 1409U, 1687U, 189U, 1559U, 1547U, 1603U, 628U, 
1582
    1680U, 1696U, 757U, 1198U, 1191U, 1069U, 1062U, 1446U, 
1583
    997U, 409U, 981U, 380U, 989U, 401U, 973U, 372U, 
1584
    1013U, 1005U, 644U, 636U, 247U, 116U, 856U, 110U, 
1585
    1703U, 869U, 1724U, 1128U, 17U, 621U, 9U, 0U, 
1586
    537U, 1672U, 161U, 658U, 672U, 1044U, 1053U, 1299U, 
1587
    470U, 1038U, 681U, 1135U, 1527U, 1506U, 1229U, 1790U, 
1588
    504U, 1783U, 486U, 1080U, 1030U, 763U, 1338U, 933U, 
1589
    1637U, 1205U, 1655U, 1153U, 1840U, 2208U, 2601U, 2991U, 
1590
    3381U, 3789U, 2011U, 2379U, 2772U, 3162U, 3537U, 3960U, 
1591
    1927U, 2295U, 2688U, 3078U, 3460U, 3876U, 2098U, 2466U, 
1592
    2859U, 3249U, 3624U, 4047U, 1822U, 2190U, 2583U, 2973U, 
1593
    3363U, 3771U, 1993U, 2361U, 2754U, 3144U, 3519U, 3942U, 
1594
    1911U, 2279U, 2672U, 3062U, 3444U, 3860U, 2082U, 2450U, 
1595
    2843U, 3233U, 3608U, 4031U, 2147U, 956U, 1113U, 1848U, 
1596
    2216U, 2609U, 2999U, 3389U, 3797U, 2019U, 2387U, 2780U, 
1597
    3170U, 3545U, 3968U, 1934U, 2302U, 2695U, 3085U, 3467U, 
1598
    3883U, 2105U, 2473U, 2866U, 3256U, 3631U, 4054U, 1831U, 
1599
    2199U, 2592U, 2982U, 3372U, 3780U, 2002U, 2370U, 2763U, 
1600
    3153U, 3528U, 3951U, 1919U, 2287U, 2680U, 3070U, 3452U, 
1601
    3868U, 2090U, 2458U, 2851U, 3241U, 3616U, 4039U, 1872U, 
1602
    2240U, 2633U, 3023U, 3413U, 3821U, 2043U, 2411U, 2804U, 
1603
    3194U, 3569U, 3992U, 1955U, 2323U, 2716U, 3106U, 3488U, 
1604
    3904U, 2126U, 2494U, 2887U, 3277U, 3652U, 4075U, 1880U, 
1605
    2248U, 2641U, 3031U, 3421U, 3829U, 2051U, 2419U, 2812U, 
1606
    3202U, 3577U, 4000U, 1962U, 2330U, 2723U, 3113U, 3495U, 
1607
    3911U, 2133U, 2501U, 2894U, 3284U, 3659U, 4082U, 2164U, 
1608
    2557U, 3745U, 2167U, 2560U, 2950U, 3340U, 3748U, 1856U, 
1609
    2224U, 2617U, 3007U, 3397U, 3805U, 2027U, 2395U, 2788U, 
1610
    3178U, 3553U, 3976U, 1941U, 2309U, 2702U, 3092U, 3474U, 
1611
    3890U, 2112U, 2480U, 2873U, 3263U, 3638U, 4061U, 1839U, 
1612
    2207U, 2600U, 2990U, 3380U, 3788U, 2010U, 2378U, 2771U, 
1613
    3161U, 3536U, 3959U, 1926U, 2294U, 2687U, 3077U, 3459U, 
1614
    3875U, 2097U, 2465U, 2858U, 3248U, 3623U, 4046U, 145U, 
1615
    1076U, 1888U, 2256U, 2649U, 3039U, 3837U, 2059U, 2427U, 
1616
    2820U, 3210U, 3585U, 4008U, 1969U, 2337U, 2730U, 3120U, 
1617
    3918U, 2140U, 2508U, 2901U, 3291U, 3666U, 4089U, 80U, 
1618
    91U, 3703U, 1797U, 2156U, 3695U, 3738U, 1478U, 667U, 
1619
    2515U, 2908U, 3298U, 3673U, 2545U, 2938U, 3328U, 3726U, 
1620
    2530U, 2923U, 3313U, 3688U, 2551U, 2944U, 3334U, 3732U, 
1621
    31U, 64U, 2537U, 2930U, 3320U, 3710U, 1805U, 2173U, 
1622
    2566U, 2956U, 3346U, 3754U, 1976U, 2344U, 2737U, 3127U, 
1623
    3502U, 3925U, 1896U, 2264U, 2657U, 3047U, 3429U, 3845U, 
1624
    2067U, 2435U, 2828U, 3218U, 3593U, 4016U, 1813U, 2181U, 
1625
    2574U, 2964U, 3354U, 3762U, 1984U, 2352U, 2745U, 3135U, 
1626
    3510U, 3933U, 1903U, 2271U, 2664U, 3054U, 3436U, 3852U, 
1627
    2074U, 2442U, 2835U, 3225U, 3600U, 4023U, 2522U, 2915U, 
1628
    3305U, 3680U, 50U, 102U, 38U, 70U, 25U, 59U, 
1629
    44U, 75U, 1864U, 2232U, 2625U, 3015U, 3405U, 3813U, 
1630
    2035U, 2403U, 2796U, 3186U, 3561U, 3984U, 1948U, 2316U, 
1631
    2709U, 3099U, 3481U, 3897U, 2119U, 2487U, 2880U, 3270U, 
1632
    3645U, 4068U, 3718U, 
1633
};
1634
1635
100
static inline void InitMSP430MCInstrInfo(MCInstrInfo *II) {
1636
100
  II->InitMCInstrInfo(MSP430Insts, MSP430InstrNameIndices, MSP430InstrNameData, 491);
1637
100
}
1638
1639
} // end llvm namespace
1640
#endif // GET_INSTRINFO_MC_DESC
1641
1642
#ifdef GET_INSTRINFO_HEADER
1643
#undef GET_INSTRINFO_HEADER
1644
namespace llvm {
1645
struct MSP430GenInstrInfo : public TargetInstrInfo {
1646
  explicit MSP430GenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);
1647
75
  ~MSP430GenInstrInfo() override = default;
1648
1649
};
1650
} // end llvm namespace
1651
#endif // GET_INSTRINFO_HEADER
1652
1653
#ifdef GET_INSTRINFO_HELPER_DECLS
1654
#undef GET_INSTRINFO_HELPER_DECLS
1655
1656
1657
#endif // GET_INSTRINFO_HELPER_DECLS
1658
1659
#ifdef GET_INSTRINFO_HELPERS
1660
#undef GET_INSTRINFO_HELPERS
1661
1662
#endif // GET_INSTRINFO_HELPERS
1663
1664
#ifdef GET_INSTRINFO_CTOR_DTOR
1665
#undef GET_INSTRINFO_CTOR_DTOR
1666
namespace llvm {
1667
extern const MCInstrDesc MSP430Insts[];
1668
extern const unsigned MSP430InstrNameIndices[];
1669
extern const char MSP430InstrNameData[];
1670
MSP430GenInstrInfo::MSP430GenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)
1671
76
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1672
76
  InitMCInstrInfo(MSP430Insts, MSP430InstrNameIndices, MSP430InstrNameData, 491);
1673
76
}
1674
} // end llvm namespace
1675
#endif // GET_INSTRINFO_CTOR_DTOR
1676
1677
#ifdef GET_INSTRINFO_OPERAND_ENUM
1678
#undef GET_INSTRINFO_OPERAND_ENUM
1679
namespace llvm {
1680
namespace MSP430 {
1681
namespace OpName {
1682
enum {
1683
OPERAND_LAST
1684
};
1685
} // end namespace OpName
1686
} // end namespace MSP430
1687
} // end namespace llvm
1688
#endif //GET_INSTRINFO_OPERAND_ENUM
1689
1690
#ifdef GET_INSTRINFO_NAMED_OPS
1691
#undef GET_INSTRINFO_NAMED_OPS
1692
namespace llvm {
1693
namespace MSP430 {
1694
LLVM_READONLY
1695
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
1696
  return -1;
1697
}
1698
} // end namespace MSP430
1699
} // end namespace llvm
1700
#endif //GET_INSTRINFO_NAMED_OPS
1701
1702
#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
1703
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
1704
namespace llvm {
1705
namespace MSP430 {
1706
namespace OpTypes {
1707
enum OperandType {
1708
  cc = 0,
1709
  cg16imm = 1,
1710
  cg8imm = 2,
1711
  f32imm = 3,
1712
  f64imm = 4,
1713
  i16imm = 5,
1714
  i1imm = 6,
1715
  i32imm = 7,
1716
  i64imm = 8,
1717
  i8imm = 9,
1718
  indreg = 10,
1719
  jmptarget = 11,
1720
  memdst = 12,
1721
  memsrc = 13,
1722
  postreg = 14,
1723
  ptype0 = 15,
1724
  ptype1 = 16,
1725
  ptype2 = 17,
1726
  ptype3 = 18,
1727
  ptype4 = 19,
1728
  ptype5 = 20,
1729
  type0 = 21,
1730
  type1 = 22,
1731
  type2 = 23,
1732
  type3 = 24,
1733
  type4 = 25,
1734
  type5 = 26,
1735
  OPERAND_TYPE_LIST_END
1736
};
1737
} // end namespace OpTypes
1738
} // end namespace MSP430
1739
} // end namespace llvm
1740
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
1741