Coverage Report

Created: 2018-07-19 03:59

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/MSP430/MSP430GenInstrInfo.inc
Line
Count
Source
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Instruction Enum Values and Descriptors                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_INSTRINFO_ENUM
10
#undef GET_INSTRINFO_ENUM
11
namespace llvm {
12
13
namespace MSP430 {
14
  enum {
15
    PHI = 0,
16
    INLINEASM = 1,
17
    CFI_INSTRUCTION = 2,
18
    EH_LABEL  = 3,
19
    GC_LABEL  = 4,
20
    ANNOTATION_LABEL  = 5,
21
    KILL  = 6,
22
    EXTRACT_SUBREG  = 7,
23
    INSERT_SUBREG = 8,
24
    IMPLICIT_DEF  = 9,
25
    SUBREG_TO_REG = 10,
26
    COPY_TO_REGCLASS  = 11,
27
    DBG_VALUE = 12,
28
    DBG_LABEL = 13,
29
    REG_SEQUENCE  = 14,
30
    COPY  = 15,
31
    BUNDLE  = 16,
32
    LIFETIME_START  = 17,
33
    LIFETIME_END  = 18,
34
    STACKMAP  = 19,
35
    FENTRY_CALL = 20,
36
    PATCHPOINT  = 21,
37
    LOAD_STACK_GUARD  = 22,
38
    STATEPOINT  = 23,
39
    LOCAL_ESCAPE  = 24,
40
    FAULTING_OP = 25,
41
    PATCHABLE_OP  = 26,
42
    PATCHABLE_FUNCTION_ENTER  = 27,
43
    PATCHABLE_RET = 28,
44
    PATCHABLE_FUNCTION_EXIT = 29,
45
    PATCHABLE_TAIL_CALL = 30,
46
    PATCHABLE_EVENT_CALL  = 31,
47
    PATCHABLE_TYPED_EVENT_CALL  = 32,
48
    ICALL_BRANCH_FUNNEL = 33,
49
    G_ADD = 34,
50
    G_SUB = 35,
51
    G_MUL = 36,
52
    G_SDIV  = 37,
53
    G_UDIV  = 38,
54
    G_SREM  = 39,
55
    G_UREM  = 40,
56
    G_AND = 41,
57
    G_OR  = 42,
58
    G_XOR = 43,
59
    G_IMPLICIT_DEF  = 44,
60
    G_PHI = 45,
61
    G_FRAME_INDEX = 46,
62
    G_GLOBAL_VALUE  = 47,
63
    G_EXTRACT = 48,
64
    G_UNMERGE_VALUES  = 49,
65
    G_INSERT  = 50,
66
    G_MERGE_VALUES  = 51,
67
    G_PTRTOINT  = 52,
68
    G_INTTOPTR  = 53,
69
    G_BITCAST = 54,
70
    G_LOAD  = 55,
71
    G_SEXTLOAD  = 56,
72
    G_ZEXTLOAD  = 57,
73
    G_STORE = 58,
74
    G_ATOMIC_CMPXCHG_WITH_SUCCESS = 59,
75
    G_ATOMIC_CMPXCHG  = 60,
76
    G_ATOMICRMW_XCHG  = 61,
77
    G_ATOMICRMW_ADD = 62,
78
    G_ATOMICRMW_SUB = 63,
79
    G_ATOMICRMW_AND = 64,
80
    G_ATOMICRMW_NAND  = 65,
81
    G_ATOMICRMW_OR  = 66,
82
    G_ATOMICRMW_XOR = 67,
83
    G_ATOMICRMW_MAX = 68,
84
    G_ATOMICRMW_MIN = 69,
85
    G_ATOMICRMW_UMAX  = 70,
86
    G_ATOMICRMW_UMIN  = 71,
87
    G_BRCOND  = 72,
88
    G_BRINDIRECT  = 73,
89
    G_INTRINSIC = 74,
90
    G_INTRINSIC_W_SIDE_EFFECTS  = 75,
91
    G_ANYEXT  = 76,
92
    G_TRUNC = 77,
93
    G_CONSTANT  = 78,
94
    G_FCONSTANT = 79,
95
    G_VASTART = 80,
96
    G_VAARG = 81,
97
    G_SEXT  = 82,
98
    G_ZEXT  = 83,
99
    G_SHL = 84,
100
    G_LSHR  = 85,
101
    G_ASHR  = 86,
102
    G_ICMP  = 87,
103
    G_FCMP  = 88,
104
    G_SELECT  = 89,
105
    G_UADDE = 90,
106
    G_USUBE = 91,
107
    G_SADDO = 92,
108
    G_SSUBO = 93,
109
    G_UMULO = 94,
110
    G_SMULO = 95,
111
    G_UMULH = 96,
112
    G_SMULH = 97,
113
    G_FADD  = 98,
114
    G_FSUB  = 99,
115
    G_FMUL  = 100,
116
    G_FMA = 101,
117
    G_FDIV  = 102,
118
    G_FREM  = 103,
119
    G_FPOW  = 104,
120
    G_FEXP  = 105,
121
    G_FEXP2 = 106,
122
    G_FLOG  = 107,
123
    G_FLOG2 = 108,
124
    G_FNEG  = 109,
125
    G_FPEXT = 110,
126
    G_FPTRUNC = 111,
127
    G_FPTOSI  = 112,
128
    G_FPTOUI  = 113,
129
    G_SITOFP  = 114,
130
    G_UITOFP  = 115,
131
    G_FABS  = 116,
132
    G_GEP = 117,
133
    G_PTR_MASK  = 118,
134
    G_BR  = 119,
135
    G_INSERT_VECTOR_ELT = 120,
136
    G_EXTRACT_VECTOR_ELT  = 121,
137
    G_SHUFFLE_VECTOR  = 122,
138
    G_BSWAP = 123,
139
    G_ADDRSPACE_CAST  = 124,
140
    ADC16mi = 125,
141
    ADC16mm = 126,
142
    ADC16mr = 127,
143
    ADC16ri = 128,
144
    ADC16rm = 129,
145
    ADC16rr = 130,
146
    ADC8mi  = 131,
147
    ADC8mm  = 132,
148
    ADC8mr  = 133,
149
    ADC8ri  = 134,
150
    ADC8rm  = 135,
151
    ADC8rr  = 136,
152
    ADD16mi = 137,
153
    ADD16mm = 138,
154
    ADD16mr = 139,
155
    ADD16ri = 140,
156
    ADD16rm = 141,
157
    ADD16rm_POST  = 142,
158
    ADD16rr = 143,
159
    ADD8mi  = 144,
160
    ADD8mm  = 145,
161
    ADD8mr  = 146,
162
    ADD8ri  = 147,
163
    ADD8rm  = 148,
164
    ADD8rm_POST = 149,
165
    ADD8rr  = 150,
166
    ADDframe  = 151,
167
    ADJCALLSTACKDOWN  = 152,
168
    ADJCALLSTACKUP  = 153,
169
    AND16mi = 154,
170
    AND16mm = 155,
171
    AND16mr = 156,
172
    AND16ri = 157,
173
    AND16rm = 158,
174
    AND16rm_POST  = 159,
175
    AND16rr = 160,
176
    AND8mi  = 161,
177
    AND8mm  = 162,
178
    AND8mr  = 163,
179
    AND8ri  = 164,
180
    AND8rm  = 165,
181
    AND8rm_POST = 166,
182
    AND8rr  = 167,
183
    BIC16mm = 168,
184
    BIC16mr = 169,
185
    BIC16rm = 170,
186
    BIC16rr = 171,
187
    BIC8mm  = 172,
188
    BIC8mr  = 173,
189
    BIC8rm  = 174,
190
    BIC8rr  = 175,
191
    BIT16mi = 176,
192
    BIT16mm = 177,
193
    BIT16mr = 178,
194
    BIT16ri = 179,
195
    BIT16rm = 180,
196
    BIT16rr = 181,
197
    BIT8mi  = 182,
198
    BIT8mm  = 183,
199
    BIT8mr  = 184,
200
    BIT8ri  = 185,
201
    BIT8rm  = 186,
202
    BIT8rr  = 187,
203
    Bi  = 188,
204
    Bm  = 189,
205
    Br  = 190,
206
    CALLi = 191,
207
    CALLm = 192,
208
    CALLr = 193,
209
    CMP16mi = 194,
210
    CMP16mr = 195,
211
    CMP16ri = 196,
212
    CMP16rm = 197,
213
    CMP16rr = 198,
214
    CMP8mi  = 199,
215
    CMP8mr  = 200,
216
    CMP8ri  = 201,
217
    CMP8rm  = 202,
218
    CMP8rr  = 203,
219
    JCC = 204,
220
    JMP = 205,
221
    MOV16mi = 206,
222
    MOV16mm = 207,
223
    MOV16mr = 208,
224
    MOV16ri = 209,
225
    MOV16rm = 210,
226
    MOV16rm_POST  = 211,
227
    MOV16rr = 212,
228
    MOV8mi  = 213,
229
    MOV8mm  = 214,
230
    MOV8mr  = 215,
231
    MOV8ri  = 216,
232
    MOV8rm  = 217,
233
    MOV8rm_POST = 218,
234
    MOV8rr  = 219,
235
    MOVZX16rm8  = 220,
236
    MOVZX16rr8  = 221,
237
    NOP = 222,
238
    OR16mi  = 223,
239
    OR16mm  = 224,
240
    OR16mr  = 225,
241
    OR16ri  = 226,
242
    OR16rm  = 227,
243
    OR16rm_POST = 228,
244
    OR16rr  = 229,
245
    OR8mi = 230,
246
    OR8mm = 231,
247
    OR8mr = 232,
248
    OR8ri = 233,
249
    OR8rm = 234,
250
    OR8rm_POST  = 235,
251
    OR8rr = 236,
252
    POP16r  = 237,
253
    PUSH16r = 238,
254
    RET = 239,
255
    RETI  = 240,
256
    SAR16r1 = 241,
257
    SAR16r1c  = 242,
258
    SAR8r1  = 243,
259
    SAR8r1c = 244,
260
    SBC16mi = 245,
261
    SBC16mm = 246,
262
    SBC16mr = 247,
263
    SBC16ri = 248,
264
    SBC16rm = 249,
265
    SBC16rr = 250,
266
    SBC8mi  = 251,
267
    SBC8mm  = 252,
268
    SBC8mr  = 253,
269
    SBC8ri  = 254,
270
    SBC8rm  = 255,
271
    SBC8rr  = 256,
272
    SEXT16r = 257,
273
    SHL16r1 = 258,
274
    SHL8r1  = 259,
275
    SUB16mi = 260,
276
    SUB16mm = 261,
277
    SUB16mr = 262,
278
    SUB16ri = 263,
279
    SUB16rm = 264,
280
    SUB16rm_POST  = 265,
281
    SUB16rr = 266,
282
    SUB8mi  = 267,
283
    SUB8mm  = 268,
284
    SUB8mr  = 269,
285
    SUB8ri  = 270,
286
    SUB8rm  = 271,
287
    SUB8rm_POST = 272,
288
    SUB8rr  = 273,
289
    SWPB16r = 274,
290
    Select16  = 275,
291
    Select8 = 276,
292
    Shl16 = 277,
293
    Shl8  = 278,
294
    Sra16 = 279,
295
    Sra8  = 280,
296
    Srl16 = 281,
297
    Srl8  = 282,
298
    XOR16mi = 283,
299
    XOR16mm = 284,
300
    XOR16mr = 285,
301
    XOR16ri = 286,
302
    XOR16rm = 287,
303
    XOR16rm_POST  = 288,
304
    XOR16rr = 289,
305
    XOR8mi  = 290,
306
    XOR8mm  = 291,
307
    XOR8mr  = 292,
308
    XOR8ri  = 293,
309
    XOR8rm  = 294,
310
    XOR8rm_POST = 295,
311
    XOR8rr  = 296,
312
    ZEXT16r = 297,
313
    INSTRUCTION_LIST_END = 298
314
  };
315
316
} // end MSP430 namespace
317
} // end llvm namespace
318
#endif // GET_INSTRINFO_ENUM
319
320
#ifdef GET_INSTRINFO_SCHED_ENUM
321
#undef GET_INSTRINFO_SCHED_ENUM
322
namespace llvm {
323
324
namespace MSP430 {
325
namespace Sched {
326
  enum {
327
    NoInstrModel  = 0,
328
    SCHED_LIST_END = 1
329
  };
330
} // end Sched namespace
331
} // end MSP430 namespace
332
} // end llvm namespace
333
#endif // GET_INSTRINFO_SCHED_ENUM
334
335
#ifdef GET_INSTRINFO_MC_DESC
336
#undef GET_INSTRINFO_MC_DESC
337
namespace llvm {
338
339
static const MCPhysReg ImplicitList1[] = { MSP430::SR, 0 };
340
static const MCPhysReg ImplicitList2[] = { MSP430::SP, 0 };
341
static const MCPhysReg ImplicitList3[] = { MSP430::SP, MSP430::SR, 0 };
342
static const MCPhysReg ImplicitList4[] = { MSP430::R11, MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, MSP430::SR, 0 };
343
344
static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
345
static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
346
static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
347
static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
348
static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
349
static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
350
static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
351
static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
352
static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
353
static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
354
static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
355
static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
356
static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
357
static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
358
static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
359
static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
360
static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
361
static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
362
static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
363
static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
364
static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
365
static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
366
static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
367
static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
368
static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
369
static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
370
static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
371
static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
372
static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
373
static const MCOperandInfo OperandInfo31[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
374
static const MCOperandInfo OperandInfo32[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
375
static const MCOperandInfo OperandInfo33[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
376
static const MCOperandInfo OperandInfo34[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
377
static const MCOperandInfo OperandInfo35[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
378
static const MCOperandInfo OperandInfo36[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
379
static const MCOperandInfo OperandInfo37[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
380
static const MCOperandInfo OperandInfo38[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
381
static const MCOperandInfo OperandInfo39[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
382
static const MCOperandInfo OperandInfo40[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
383
static const MCOperandInfo OperandInfo41[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
384
static const MCOperandInfo OperandInfo42[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
385
static const MCOperandInfo OperandInfo43[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
386
static const MCOperandInfo OperandInfo44[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
387
static const MCOperandInfo OperandInfo45[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
388
static const MCOperandInfo OperandInfo46[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
389
static const MCOperandInfo OperandInfo47[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
390
static const MCOperandInfo OperandInfo48[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
391
static const MCOperandInfo OperandInfo49[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
392
static const MCOperandInfo OperandInfo50[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
393
static const MCOperandInfo OperandInfo51[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
394
static const MCOperandInfo OperandInfo52[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
395
static const MCOperandInfo OperandInfo53[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
396
static const MCOperandInfo OperandInfo54[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
397
static const MCOperandInfo OperandInfo55[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
398
static const MCOperandInfo OperandInfo56[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
399
static const MCOperandInfo OperandInfo57[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
400
static const MCOperandInfo OperandInfo58[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
401
static const MCOperandInfo OperandInfo59[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
402
static const MCOperandInfo OperandInfo60[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
403
404
extern const MCInstrDesc MSP430Insts[] = {
405
  { 0,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
406
  { 1,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
407
  { 2,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #2 = CFI_INSTRUCTION
408
  { 3,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = EH_LABEL
409
  { 4,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = GC_LABEL
410
  { 5,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = ANNOTATION_LABEL
411
  { 6,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #6 = KILL
412
  { 7,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #7 = EXTRACT_SUBREG
413
  { 8,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #8 = INSERT_SUBREG
414
  { 9,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #9 = IMPLICIT_DEF
415
  { 10, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #10 = SUBREG_TO_REG
416
  { 11, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #11 = COPY_TO_REGCLASS
417
  { 12, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #12 = DBG_VALUE
418
  { 13, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #13 = DBG_LABEL
419
  { 14, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #14 = REG_SEQUENCE
420
  { 15, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #15 = COPY
421
  { 16, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #16 = BUNDLE
422
  { 17, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #17 = LIFETIME_START
423
  { 18, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #18 = LIFETIME_END
424
  { 19, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #19 = STACKMAP
425
  { 20, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #20 = FENTRY_CALL
426
  { 21, 6,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #21 = PATCHPOINT
427
  { 22, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #22 = LOAD_STACK_GUARD
428
  { 23, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #23 = STATEPOINT
429
  { 24, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #24 = LOCAL_ESCAPE
430
  { 25, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #25 = FAULTING_OP
431
  { 26, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #26 = PATCHABLE_OP
432
  { 27, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #27 = PATCHABLE_FUNCTION_ENTER
433
  { 28, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #28 = PATCHABLE_RET
434
  { 29, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #29 = PATCHABLE_FUNCTION_EXIT
435
  { 30, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #30 = PATCHABLE_TAIL_CALL
436
  { 31, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #31 = PATCHABLE_EVENT_CALL
437
  { 32, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #32 = PATCHABLE_TYPED_EVENT_CALL
438
  { 33, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #33 = ICALL_BRANCH_FUNNEL
439
  { 34, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #34 = G_ADD
440
  { 35, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #35 = G_SUB
441
  { 36, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #36 = G_MUL
442
  { 37, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #37 = G_SDIV
443
  { 38, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #38 = G_UDIV
444
  { 39, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #39 = G_SREM
445
  { 40, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #40 = G_UREM
446
  { 41, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_AND
447
  { 42, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_OR
448
  { 43, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #43 = G_XOR
449
  { 44, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #44 = G_IMPLICIT_DEF
450
  { 45, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #45 = G_PHI
451
  { 46, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #46 = G_FRAME_INDEX
452
  { 47, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #47 = G_GLOBAL_VALUE
453
  { 48, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #48 = G_EXTRACT
454
  { 49, 2,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #49 = G_UNMERGE_VALUES
455
  { 50, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #50 = G_INSERT
456
  { 51, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #51 = G_MERGE_VALUES
457
  { 52, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #52 = G_PTRTOINT
458
  { 53, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = G_INTTOPTR
459
  { 54, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #54 = G_BITCAST
460
  { 55, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #55 = G_LOAD
461
  { 56, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #56 = G_SEXTLOAD
462
  { 57, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #57 = G_ZEXTLOAD
463
  { 58, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #58 = G_STORE
464
  { 59, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #59 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
465
  { 60, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #60 = G_ATOMIC_CMPXCHG
466
  { 61, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #61 = G_ATOMICRMW_XCHG
467
  { 62, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #62 = G_ATOMICRMW_ADD
468
  { 63, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #63 = G_ATOMICRMW_SUB
469
  { 64, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #64 = G_ATOMICRMW_AND
470
  { 65, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #65 = G_ATOMICRMW_NAND
471
  { 66, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #66 = G_ATOMICRMW_OR
472
  { 67, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #67 = G_ATOMICRMW_XOR
473
  { 68, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #68 = G_ATOMICRMW_MAX
474
  { 69, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #69 = G_ATOMICRMW_MIN
475
  { 70, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #70 = G_ATOMICRMW_UMAX
476
  { 71, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #71 = G_ATOMICRMW_UMIN
477
  { 72, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #72 = G_BRCOND
478
  { 73, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #73 = G_BRINDIRECT
479
  { 74, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #74 = G_INTRINSIC
480
  { 75, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #75 = G_INTRINSIC_W_SIDE_EFFECTS
481
  { 76, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #76 = G_ANYEXT
482
  { 77, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #77 = G_TRUNC
483
  { 78, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #78 = G_CONSTANT
484
  { 79, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #79 = G_FCONSTANT
485
  { 80, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #80 = G_VASTART
486
  { 81, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #81 = G_VAARG
487
  { 82, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #82 = G_SEXT
488
  { 83, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #83 = G_ZEXT
489
  { 84, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #84 = G_SHL
490
  { 85, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #85 = G_LSHR
491
  { 86, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #86 = G_ASHR
492
  { 87, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #87 = G_ICMP
493
  { 88, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #88 = G_FCMP
494
  { 89, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #89 = G_SELECT
495
  { 90, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #90 = G_UADDE
496
  { 91, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #91 = G_USUBE
497
  { 92, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #92 = G_SADDO
498
  { 93, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #93 = G_SSUBO
499
  { 94, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #94 = G_UMULO
500
  { 95, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #95 = G_SMULO
501
  { 96, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #96 = G_UMULH
502
  { 97, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #97 = G_SMULH
503
  { 98, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #98 = G_FADD
504
  { 99, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #99 = G_FSUB
505
  { 100,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #100 = G_FMUL
506
  { 101,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #101 = G_FMA
507
  { 102,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #102 = G_FDIV
508
  { 103,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #103 = G_FREM
509
  { 104,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #104 = G_FPOW
510
  { 105,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #105 = G_FEXP
511
  { 106,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #106 = G_FEXP2
512
  { 107,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #107 = G_FLOG
513
  { 108,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #108 = G_FLOG2
514
  { 109,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #109 = G_FNEG
515
  { 110,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #110 = G_FPEXT
516
  { 111,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #111 = G_FPTRUNC
517
  { 112,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #112 = G_FPTOSI
518
  { 113,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #113 = G_FPTOUI
519
  { 114,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #114 = G_SITOFP
520
  { 115,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #115 = G_UITOFP
521
  { 116,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #116 = G_FABS
522
  { 117,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #117 = G_GEP
523
  { 118,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #118 = G_PTR_MASK
524
  { 119,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #119 = G_BR
525
  { 120,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #120 = G_INSERT_VECTOR_ELT
526
  { 121,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #121 = G_EXTRACT_VECTOR_ELT
527
  { 122,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #122 = G_SHUFFLE_VECTOR
528
  { 123,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #123 = G_BSWAP
529
  { 124,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #124 = G_ADDRSPACE_CAST
530
  { 125,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #125 = ADC16mi
531
  { 126,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, ImplicitList1, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #126 = ADC16mm
532
  { 127,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #127 = ADC16mr
533
  { 128,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #128 = ADC16ri
534
  { 129,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #129 = ADC16rm
535
  { 130,  3,  1,  0,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #130 = ADC16rr
536
  { 131,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #131 = ADC8mi
537
  { 132,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, ImplicitList1, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #132 = ADC8mm
538
  { 133,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #133 = ADC8mr
539
  { 134,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #134 = ADC8ri
540
  { 135,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #135 = ADC8rm
541
  { 136,  3,  1,  0,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #136 = ADC8rr
542
  { 137,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #137 = ADD16mi
543
  { 138,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #138 = ADD16mm
544
  { 139,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #139 = ADD16mr
545
  { 140,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #140 = ADD16ri
546
  { 141,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #141 = ADD16rm
547
  { 142,  4,  2,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #142 = ADD16rm_POST
548
  { 143,  3,  1,  0,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #143 = ADD16rr
549
  { 144,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #144 = ADD8mi
550
  { 145,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #145 = ADD8mm
551
  { 146,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #146 = ADD8mr
552
  { 147,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #147 = ADD8ri
553
  { 148,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #148 = ADD8rm
554
  { 149,  4,  2,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #149 = ADD8rm_POST
555
  { 150,  3,  1,  0,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #150 = ADD8rr
556
  { 151,  3,  1,  0,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, ImplicitList2, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #151 = ADDframe
557
  { 152,  2,  0,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, ImplicitList2, ImplicitList3, OperandInfo8, -1 ,nullptr },  // Inst #152 = ADJCALLSTACKDOWN
558
  { 153,  2,  0,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, ImplicitList2, ImplicitList3, OperandInfo8, -1 ,nullptr },  // Inst #153 = ADJCALLSTACKUP
559
  { 154,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #154 = AND16mi
560
  { 155,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #155 = AND16mm
561
  { 156,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #156 = AND16mr
562
  { 157,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #157 = AND16ri
563
  { 158,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #158 = AND16rm
564
  { 159,  4,  2,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #159 = AND16rm_POST
565
  { 160,  3,  1,  0,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #160 = AND16rr
566
  { 161,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #161 = AND8mi
567
  { 162,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #162 = AND8mm
568
  { 163,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #163 = AND8mr
569
  { 164,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #164 = AND8ri
570
  { 165,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #165 = AND8rm
571
  { 166,  4,  2,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #166 = AND8rm_POST
572
  { 167,  3,  1,  0,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #167 = AND8rr
573
  { 168,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #168 = BIC16mm
574
  { 169,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #169 = BIC16mr
575
  { 170,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #170 = BIC16rm
576
  { 171,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #171 = BIC16rr
577
  { 172,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #172 = BIC8mm
578
  { 173,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #173 = BIC8mr
579
  { 174,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #174 = BIC8rm
580
  { 175,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #175 = BIC8rr
581
  { 176,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #176 = BIT16mi
582
  { 177,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #177 = BIT16mm
583
  { 178,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #178 = BIT16mr
584
  { 179,  2,  0,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #179 = BIT16ri
585
  { 180,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #180 = BIT16rm
586
  { 181,  2,  0,  0,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #181 = BIT16rr
587
  { 182,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #182 = BIT8mi
588
  { 183,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #183 = BIT8mm
589
  { 184,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #184 = BIT8mr
590
  { 185,  2,  0,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #185 = BIT8ri
591
  { 186,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #186 = BIT8rm
592
  { 187,  2,  0,  0,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo49, -1 ,nullptr },  // Inst #187 = BIT8rr
593
  { 188,  1,  0,  0,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #188 = Bi
594
  { 189,  2,  0,  0,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #189 = Bm
595
  { 190,  1,  0,  0,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #190 = Br
596
  { 191,  1,  0,  0,  0,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xdULL, ImplicitList2, ImplicitList4, OperandInfo3, -1 ,nullptr },  // Inst #191 = CALLi
597
  { 192,  2,  0,  0,  0,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xdULL, ImplicitList2, ImplicitList4, OperandInfo50, -1 ,nullptr },  // Inst #192 = CALLm
598
  { 193,  1,  0,  0,  0,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x9ULL, ImplicitList2, ImplicitList4, OperandInfo51, -1 ,nullptr },  // Inst #193 = CALLr
599
  { 194,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #194 = CMP16mi
600
  { 195,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #195 = CMP16mr
601
  { 196,  2,  0,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #196 = CMP16ri
602
  { 197,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #197 = CMP16rm
603
  { 198,  2,  0,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #198 = CMP16rr
604
  { 199,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #199 = CMP8mi
605
  { 200,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #200 = CMP8mr
606
  { 201,  2,  0,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #201 = CMP8ri
607
  { 202,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #202 = CMP8rm
608
  { 203,  2,  0,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo49, -1 ,nullptr },  // Inst #203 = CMP8rr
609
  { 204,  2,  0,  0,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xbULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #204 = JCC
610
  { 205,  1,  0,  0,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xbULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #205 = JMP
611
  { 206,  3,  0,  0,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #206 = MOV16mi
612
  { 207,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #207 = MOV16mm
613
  { 208,  3,  0,  0,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #208 = MOV16mr
614
  { 209,  2,  1,  0,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #209 = MOV16ri
615
  { 210,  3,  1,  0,  0,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #210 = MOV16rm
616
  { 211,  3,  2,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #211 = MOV16rm_POST
617
  { 212,  2,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #212 = MOV16rr
618
  { 213,  3,  0,  0,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #213 = MOV8mi
619
  { 214,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #214 = MOV8mm
620
  { 215,  3,  0,  0,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #215 = MOV8mr
621
  { 216,  2,  1,  0,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #216 = MOV8ri
622
  { 217,  3,  1,  0,  0,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #217 = MOV8rm
623
  { 218,  3,  2,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #218 = MOV8rm_POST
624
  { 219,  2,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #219 = MOV8rr
625
  { 220,  3,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #220 = MOVZX16rm8
626
  { 221,  2,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #221 = MOVZX16rr8
627
  { 222,  0,  0,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #222 = NOP
628
  { 223,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #223 = OR16mi
629
  { 224,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #224 = OR16mm
630
  { 225,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #225 = OR16mr
631
  { 226,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #226 = OR16ri
632
  { 227,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #227 = OR16rm
633
  { 228,  4,  2,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #228 = OR16rm_POST
634
  { 229,  3,  1,  0,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #229 = OR16rr
635
  { 230,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #230 = OR8mi
636
  { 231,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #231 = OR8mm
637
  { 232,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #232 = OR8mr
638
  { 233,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #233 = OR8ri
639
  { 234,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #234 = OR8rm
640
  { 235,  4,  2,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #235 = OR8rm_POST
641
  { 236,  3,  1,  0,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #236 = OR8rr
642
  { 237,  1,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, ImplicitList2, ImplicitList2, OperandInfo51, -1 ,nullptr },  // Inst #237 = POP16r
643
  { 238,  1,  0,  0,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x9ULL, ImplicitList2, ImplicitList2, OperandInfo51, -1 ,nullptr },  // Inst #238 = PUSH16r
644
  { 239,  0,  0,  0,  0,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #239 = RET
645
  { 240,  0,  0,  0,  0,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x9ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #240 = RETI
646
  { 241,  2,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x9ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #241 = SAR16r1
647
  { 242,  2,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #242 = SAR16r1c
648
  { 243,  2,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x9ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #243 = SAR8r1
649
  { 244,  2,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #244 = SAR8r1c
650
  { 245,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #245 = SBC16mi
651
  { 246,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, ImplicitList1, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #246 = SBC16mm
652
  { 247,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #247 = SBC16mr
653
  { 248,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #248 = SBC16ri
654
  { 249,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #249 = SBC16rm
655
  { 250,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #250 = SBC16rr
656
  { 251,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #251 = SBC8mi
657
  { 252,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, ImplicitList1, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #252 = SBC8mm
658
  { 253,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #253 = SBC8mr
659
  { 254,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #254 = SBC8ri
660
  { 255,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #255 = SBC8rm
661
  { 256,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #256 = SBC8rr
662
  { 257,  2,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x9ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #257 = SEXT16r
663
  { 258,  2,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #258 = SHL16r1
664
  { 259,  2,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #259 = SHL8r1
665
  { 260,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #260 = SUB16mi
666
  { 261,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #261 = SUB16mm
667
  { 262,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #262 = SUB16mr
668
  { 263,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #263 = SUB16ri
669
  { 264,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #264 = SUB16rm
670
  { 265,  4,  2,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #265 = SUB16rm_POST
671
  { 266,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #266 = SUB16rr
672
  { 267,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #267 = SUB8mi
673
  { 268,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #268 = SUB8mm
674
  { 269,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #269 = SUB8mr
675
  { 270,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #270 = SUB8ri
676
  { 271,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #271 = SUB8rm
677
  { 272,  4,  2,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #272 = SUB8rm_POST
678
  { 273,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #273 = SUB8rr
679
  { 274,  2,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x9ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #274 = SWPB16r
680
  { 275,  4,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, ImplicitList1, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #275 = Select16
681
  { 276,  4,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #276 = Select8
682
  { 277,  3,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #277 = Shl16
683
  { 278,  3,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, nullptr, ImplicitList1, OperandInfo60, -1 ,nullptr },  // Inst #278 = Shl8
684
  { 279,  3,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #279 = Sra16
685
  { 280,  3,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, nullptr, ImplicitList1, OperandInfo60, -1 ,nullptr },  // Inst #280 = Sra8
686
  { 281,  3,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #281 = Srl16
687
  { 282,  3,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, nullptr, ImplicitList1, OperandInfo60, -1 ,nullptr },  // Inst #282 = Srl8
688
  { 283,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #283 = XOR16mi
689
  { 284,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #284 = XOR16mm
690
  { 285,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #285 = XOR16mr
691
  { 286,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #286 = XOR16ri
692
  { 287,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #287 = XOR16rm
693
  { 288,  4,  2,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #288 = XOR16rm_POST
694
  { 289,  3,  1,  0,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #289 = XOR16rr
695
  { 290,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #290 = XOR8mi
696
  { 291,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #291 = XOR8mm
697
  { 292,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #292 = XOR8mr
698
  { 293,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #293 = XOR8ri
699
  { 294,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #294 = XOR8rm
700
  { 295,  4,  2,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #295 = XOR8rm_POST
701
  { 296,  3,  1,  0,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #296 = XOR8rr
702
  { 297,  2,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #297 = ZEXT16r
703
};
704
705
extern const char MSP430InstrNameData[] = {
706
  /* 0 */ 'S', 'H', 'L', '1', '6', 'r', '1', 0,
707
  /* 8 */ 'S', 'A', 'R', '1', '6', 'r', '1', 0,
708
  /* 16 */ 'S', 'H', 'L', '8', 'r', '1', 0,
709
  /* 23 */ 'S', 'A', 'R', '8', 'r', '1', 0,
710
  /* 30 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0,
711
  /* 38 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0,
712
  /* 46 */ 'S', 'r', 'a', '1', '6', 0,
713
  /* 52 */ 'S', 'h', 'l', '1', '6', 0,
714
  /* 58 */ 'S', 'r', 'l', '1', '6', 0,
715
  /* 64 */ 'S', 'e', 'l', 'e', 'c', 't', '1', '6', 0,
716
  /* 73 */ 'S', 'r', 'a', '8', 0,
717
  /* 78 */ 'S', 'h', 'l', '8', 0,
718
  /* 83 */ 'S', 'r', 'l', '8', 0,
719
  /* 88 */ 'M', 'O', 'V', 'Z', 'X', '1', '6', 'r', 'm', '8', 0,
720
  /* 99 */ 'M', 'O', 'V', 'Z', 'X', '1', '6', 'r', 'r', '8', 0,
721
  /* 110 */ 'S', 'e', 'l', 'e', 'c', 't', '8', 0,
722
  /* 118 */ 'G', '_', 'F', 'M', 'A', 0,
723
  /* 124 */ 'G', '_', 'F', 'S', 'U', 'B', 0,
724
  /* 131 */ 'G', '_', 'S', 'U', 'B', 0,
725
  /* 137 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'S', 'U', 'B', 0,
726
  /* 153 */ 'J', 'C', 'C', 0,
727
  /* 157 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', 0,
728
  /* 169 */ 'G', '_', 'F', 'P', 'T', 'R', 'U', 'N', 'C', 0,
729
  /* 179 */ 'G', '_', 'T', 'R', 'U', 'N', 'C', 0,
730
  /* 187 */ 'G', '_', 'S', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
731
  /* 198 */ 'G', '_', 'Z', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
732
  /* 209 */ 'G', '_', 'L', 'O', 'A', 'D', 0,
733
  /* 216 */ 'G', '_', 'F', 'A', 'D', 'D', 0,
734
  /* 223 */ 'G', '_', 'A', 'D', 'D', 0,
735
  /* 229 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'D', 'D', 0,
736
  /* 245 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'N', 'A', 'N', 'D', 0,
737
  /* 262 */ 'G', '_', 'A', 'N', 'D', 0,
738
  /* 268 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'N', 'D', 0,
739
  /* 284 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
740
  /* 297 */ 'G', '_', 'B', 'R', 'C', 'O', 'N', 'D', 0,
741
  /* 306 */ 'L', 'O', 'A', 'D', '_', 'S', 'T', 'A', 'C', 'K', '_', 'G', 'U', 'A', 'R', 'D', 0,
742
  /* 323 */ 'G', '_', 'U', 'S', 'U', 'B', 'E', 0,
743
  /* 331 */ 'R', 'E', 'G', '_', 'S', 'E', 'Q', 'U', 'E', 'N', 'C', 'E', 0,
744
  /* 344 */ 'G', '_', 'U', 'A', 'D', 'D', 'E', 0,
745
  /* 352 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
746
  /* 359 */ 'L', 'O', 'C', 'A', 'L', '_', 'E', 'S', 'C', 'A', 'P', 'E', 0,
747
  /* 372 */ 'G', '_', 'S', 'T', 'O', 'R', 'E', 0,
748
  /* 380 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
749
  /* 390 */ 'G', '_', 'G', 'L', 'O', 'B', 'A', 'L', '_', 'V', 'A', 'L', 'U', 'E', 0,
750
  /* 405 */ 'G', '_', 'I', 'M', 'P', 'L', 'I', 'C', 'I', 'T', '_', 'D', 'E', 'F', 0,
751
  /* 420 */ 'G', '_', 'F', 'N', 'E', 'G', 0,
752
  /* 427 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
753
  /* 442 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
754
  /* 456 */ 'S', 'U', 'B', 'R', 'E', 'G', '_', 'T', 'O', '_', 'R', 'E', 'G', 0,
755
  /* 470 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', 0,
756
  /* 487 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'C', 'H', 'G', 0,
757
  /* 504 */ 'G', '_', 'F', 'L', 'O', 'G', 0,
758
  /* 511 */ 'G', '_', 'V', 'A', 'A', 'R', 'G', 0,
759
  /* 519 */ 'G', '_', 'S', 'M', 'U', 'L', 'H', 0,
760
  /* 527 */ 'G', '_', 'U', 'M', 'U', 'L', 'H', 0,
761
  /* 535 */ 'G', '_', 'P', 'H', 'I', 0,
762
  /* 541 */ 'G', '_', 'F', 'P', 'T', 'O', 'S', 'I', 0,
763
  /* 550 */ 'R', 'E', 'T', 'I', 0,
764
  /* 555 */ 'G', '_', 'F', 'P', 'T', 'O', 'U', 'I', 0,
765
  /* 564 */ 'G', '_', 'P', 'T', 'R', '_', 'M', 'A', 'S', 'K', 0,
766
  /* 575 */ 'G', 'C', '_', 'L', 'A', 'B', 'E', 'L', 0,
767
  /* 584 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0,
768
  /* 594 */ 'E', 'H', '_', 'L', 'A', 'B', 'E', 'L', 0,
769
  /* 603 */ 'A', 'N', 'N', 'O', 'T', 'A', 'T', 'I', 'O', 'N', '_', 'L', 'A', 'B', 'E', 'L', 0,
770
  /* 620 */ 'I', 'C', 'A', 'L', 'L', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'F', 'U', 'N', 'N', 'E', 'L', 0,
771
  /* 640 */ 'G', '_', 'S', 'H', 'L', 0,
772
  /* 646 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'A', 'I', 'L', '_', 'C', 'A', 'L', 'L', 0,
773
  /* 666 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
774
  /* 693 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
775
  /* 714 */ 'F', 'E', 'N', 'T', 'R', 'Y', '_', 'C', 'A', 'L', 'L', 0,
776
  /* 726 */ 'K', 'I', 'L', 'L', 0,
777
  /* 731 */ 'G', '_', 'F', 'M', 'U', 'L', 0,
778
  /* 738 */ 'G', '_', 'M', 'U', 'L', 0,
779
  /* 744 */ 'G', '_', 'F', 'R', 'E', 'M', 0,
780
  /* 751 */ 'G', '_', 'S', 'R', 'E', 'M', 0,
781
  /* 758 */ 'G', '_', 'U', 'R', 'E', 'M', 0,
782
  /* 765 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', 0,
783
  /* 775 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'I', 'N', 0,
784
  /* 792 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'I', 'N', 0,
785
  /* 808 */ 'C', 'F', 'I', '_', 'I', 'N', 'S', 'T', 'R', 'U', 'C', 'T', 'I', 'O', 'N', 0,
786
  /* 824 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 0,
787
  /* 841 */ 'G', '_', 'S', 'S', 'U', 'B', 'O', 0,
788
  /* 849 */ 'G', '_', 'S', 'A', 'D', 'D', 'O', 0,
789
  /* 857 */ 'G', '_', 'S', 'M', 'U', 'L', 'O', 0,
790
  /* 865 */ 'G', '_', 'U', 'M', 'U', 'L', 'O', 0,
791
  /* 873 */ 'S', 'T', 'A', 'C', 'K', 'M', 'A', 'P', 0,
792
  /* 882 */ 'G', '_', 'B', 'S', 'W', 'A', 'P', 0,
793
  /* 890 */ 'G', '_', 'G', 'E', 'P', 0,
794
  /* 896 */ 'G', '_', 'S', 'I', 'T', 'O', 'F', 'P', 0,
795
  /* 905 */ 'G', '_', 'U', 'I', 'T', 'O', 'F', 'P', 0,
796
  /* 914 */ 'G', '_', 'F', 'C', 'M', 'P', 0,
797
  /* 921 */ 'G', '_', 'I', 'C', 'M', 'P', 0,
798
  /* 928 */ 'J', 'M', 'P', 0,
799
  /* 932 */ 'N', 'O', 'P', 0,
800
  /* 936 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'O', 'P', 0,
801
  /* 949 */ 'F', 'A', 'U', 'L', 'T', 'I', 'N', 'G', '_', 'O', 'P', 0,
802
  /* 961 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 0,
803
  /* 976 */ 'G', '_', 'F', 'E', 'X', 'P', 0,
804
  /* 983 */ 'G', '_', 'B', 'R', 0,
805
  /* 988 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'N', 'T', 'E', 'R', 0,
806
  /* 1013 */ 'G', '_', 'A', 'S', 'H', 'R', 0,
807
  /* 1020 */ 'G', '_', 'L', 'S', 'H', 'R', 0,
808
  /* 1027 */ 'G', '_', 'S', 'H', 'U', 'F', 'F', 'L', 'E', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
809
  /* 1044 */ 'G', '_', 'X', 'O', 'R', 0,
810
  /* 1050 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'O', 'R', 0,
811
  /* 1066 */ 'G', '_', 'O', 'R', 0,
812
  /* 1071 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'O', 'R', 0,
813
  /* 1086 */ 'G', '_', 'I', 'N', 'T', 'T', 'O', 'P', 'T', 'R', 0,
814
  /* 1097 */ 'G', '_', 'F', 'A', 'B', 'S', 0,
815
  /* 1104 */ 'G', '_', 'U', 'N', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
816
  /* 1121 */ 'G', '_', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
817
  /* 1136 */ 'C', 'O', 'P', 'Y', '_', 'T', 'O', '_', 'R', 'E', 'G', 'C', 'L', 'A', 'S', 'S', 0,
818
  /* 1153 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'W', 'I', 'T', 'H', '_', 'S', 'U', 'C', 'C', 'E', 'S', 'S', 0,
819
  /* 1183 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'W', '_', 'S', 'I', 'D', 'E', '_', 'E', 'F', 'F', 'E', 'C', 'T', 'S', 0,
820
  /* 1210 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', 0,
821
  /* 1220 */ 'G', '_', 'S', 'E', 'L', 'E', 'C', 'T', 0,
822
  /* 1229 */ 'G', '_', 'B', 'R', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', 0,
823
  /* 1242 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'R', 'E', 'T', 0,
824
  /* 1256 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'X', 'I', 'T', 0,
825
  /* 1280 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
826
  /* 1301 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
827
  /* 1321 */ 'G', '_', 'F', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
828
  /* 1333 */ 'G', '_', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
829
  /* 1344 */ 'S', 'T', 'A', 'T', 'E', 'P', 'O', 'I', 'N', 'T', 0,
830
  /* 1355 */ 'P', 'A', 'T', 'C', 'H', 'P', 'O', 'I', 'N', 'T', 0,
831
  /* 1366 */ 'G', '_', 'P', 'T', 'R', 'T', 'O', 'I', 'N', 'T', 0,
832
  /* 1377 */ 'G', '_', 'V', 'A', 'S', 'T', 'A', 'R', 'T', 0,
833
  /* 1387 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
834
  /* 1402 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', 0,
835
  /* 1411 */ 'G', '_', 'B', 'I', 'T', 'C', 'A', 'S', 'T', 0,
836
  /* 1421 */ 'G', '_', 'A', 'D', 'D', 'R', 'S', 'P', 'A', 'C', 'E', '_', 'C', 'A', 'S', 'T', 0,
837
  /* 1438 */ 'S', 'U', 'B', '1', '6', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
838
  /* 1451 */ 'A', 'D', 'D', '1', '6', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
839
  /* 1464 */ 'A', 'N', 'D', '1', '6', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
840
  /* 1477 */ 'X', 'O', 'R', '1', '6', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
841
  /* 1490 */ 'M', 'O', 'V', '1', '6', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
842
  /* 1503 */ 'S', 'U', 'B', '8', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
843
  /* 1515 */ 'A', 'D', 'D', '8', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
844
  /* 1527 */ 'A', 'N', 'D', '8', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
845
  /* 1539 */ 'X', 'O', 'R', '8', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
846
  /* 1551 */ 'M', 'O', 'V', '8', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
847
  /* 1563 */ 'G', '_', 'F', 'P', 'E', 'X', 'T', 0,
848
  /* 1571 */ 'G', '_', 'S', 'E', 'X', 'T', 0,
849
  /* 1578 */ 'G', '_', 'A', 'N', 'Y', 'E', 'X', 'T', 0,
850
  /* 1587 */ 'G', '_', 'Z', 'E', 'X', 'T', 0,
851
  /* 1594 */ 'G', '_', 'F', 'D', 'I', 'V', 0,
852
  /* 1601 */ 'G', '_', 'S', 'D', 'I', 'V', 0,
853
  /* 1608 */ 'G', '_', 'U', 'D', 'I', 'V', 0,
854
  /* 1615 */ 'G', '_', 'F', 'P', 'O', 'W', 0,
855
  /* 1622 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'A', 'X', 0,
856
  /* 1639 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'A', 'X', 0,
857
  /* 1655 */ 'G', '_', 'F', 'R', 'A', 'M', 'E', '_', 'I', 'N', 'D', 'E', 'X', 0,
858
  /* 1669 */ 'C', 'O', 'P', 'Y', 0,
859
  /* 1674 */ 'S', 'A', 'R', '1', '6', 'r', '1', 'c', 0,
860
  /* 1683 */ 'S', 'A', 'R', '8', 'r', '1', 'c', 0,
861
  /* 1691 */ 'A', 'D', 'D', 'f', 'r', 'a', 'm', 'e', 0,
862
  /* 1700 */ 'B', 'i', 0,
863
  /* 1703 */ 'C', 'A', 'L', 'L', 'i', 0,
864
  /* 1709 */ 'S', 'U', 'B', '1', '6', 'm', 'i', 0,
865
  /* 1717 */ 'S', 'B', 'C', '1', '6', 'm', 'i', 0,
866
  /* 1725 */ 'A', 'D', 'C', '1', '6', 'm', 'i', 0,
867
  /* 1733 */ 'A', 'D', 'D', '1', '6', 'm', 'i', 0,
868
  /* 1741 */ 'A', 'N', 'D', '1', '6', 'm', 'i', 0,
869
  /* 1749 */ 'C', 'M', 'P', '1', '6', 'm', 'i', 0,
870
  /* 1757 */ 'X', 'O', 'R', '1', '6', 'm', 'i', 0,
871
  /* 1765 */ 'B', 'I', 'T', '1', '6', 'm', 'i', 0,
872
  /* 1773 */ 'M', 'O', 'V', '1', '6', 'm', 'i', 0,
873
  /* 1781 */ 'S', 'U', 'B', '8', 'm', 'i', 0,
874
  /* 1788 */ 'S', 'B', 'C', '8', 'm', 'i', 0,
875
  /* 1795 */ 'A', 'D', 'C', '8', 'm', 'i', 0,
876
  /* 1802 */ 'A', 'D', 'D', '8', 'm', 'i', 0,
877
  /* 1809 */ 'A', 'N', 'D', '8', 'm', 'i', 0,
878
  /* 1816 */ 'C', 'M', 'P', '8', 'm', 'i', 0,
879
  /* 1823 */ 'X', 'O', 'R', '8', 'm', 'i', 0,
880
  /* 1830 */ 'B', 'I', 'T', '8', 'm', 'i', 0,
881
  /* 1837 */ 'M', 'O', 'V', '8', 'm', 'i', 0,
882
  /* 1844 */ 'S', 'U', 'B', '1', '6', 'r', 'i', 0,
883
  /* 1852 */ 'S', 'B', 'C', '1', '6', 'r', 'i', 0,
884
  /* 1860 */ 'A', 'D', 'C', '1', '6', 'r', 'i', 0,
885
  /* 1868 */ 'A', 'D', 'D', '1', '6', 'r', 'i', 0,
886
  /* 1876 */ 'A', 'N', 'D', '1', '6', 'r', 'i', 0,
887
  /* 1884 */ 'C', 'M', 'P', '1', '6', 'r', 'i', 0,
888
  /* 1892 */ 'X', 'O', 'R', '1', '6', 'r', 'i', 0,
889
  /* 1900 */ 'B', 'I', 'T', '1', '6', 'r', 'i', 0,
890
  /* 1908 */ 'M', 'O', 'V', '1', '6', 'r', 'i', 0,
891
  /* 1916 */ 'S', 'U', 'B', '8', 'r', 'i', 0,
892
  /* 1923 */ 'S', 'B', 'C', '8', 'r', 'i', 0,
893
  /* 1930 */ 'A', 'D', 'C', '8', 'r', 'i', 0,
894
  /* 1937 */ 'A', 'D', 'D', '8', 'r', 'i', 0,
895
  /* 1944 */ 'A', 'N', 'D', '8', 'r', 'i', 0,
896
  /* 1951 */ 'C', 'M', 'P', '8', 'r', 'i', 0,
897
  /* 1958 */ 'X', 'O', 'R', '8', 'r', 'i', 0,
898
  /* 1965 */ 'B', 'I', 'T', '8', 'r', 'i', 0,
899
  /* 1972 */ 'M', 'O', 'V', '8', 'r', 'i', 0,
900
  /* 1979 */ 'B', 'm', 0,
901
  /* 1982 */ 'C', 'A', 'L', 'L', 'm', 0,
902
  /* 1988 */ 'S', 'U', 'B', '1', '6', 'm', 'm', 0,
903
  /* 1996 */ 'S', 'B', 'C', '1', '6', 'm', 'm', 0,
904
  /* 2004 */ 'A', 'D', 'C', '1', '6', 'm', 'm', 0,
905
  /* 2012 */ 'B', 'I', 'C', '1', '6', 'm', 'm', 0,
906
  /* 2020 */ 'A', 'D', 'D', '1', '6', 'm', 'm', 0,
907
  /* 2028 */ 'A', 'N', 'D', '1', '6', 'm', 'm', 0,
908
  /* 2036 */ 'X', 'O', 'R', '1', '6', 'm', 'm', 0,
909
  /* 2044 */ 'B', 'I', 'T', '1', '6', 'm', 'm', 0,
910
  /* 2052 */ 'M', 'O', 'V', '1', '6', 'm', 'm', 0,
911
  /* 2060 */ 'S', 'U', 'B', '8', 'm', 'm', 0,
912
  /* 2067 */ 'S', 'B', 'C', '8', 'm', 'm', 0,
913
  /* 2074 */ 'A', 'D', 'C', '8', 'm', 'm', 0,
914
  /* 2081 */ 'B', 'I', 'C', '8', 'm', 'm', 0,
915
  /* 2088 */ 'A', 'D', 'D', '8', 'm', 'm', 0,
916
  /* 2095 */ 'A', 'N', 'D', '8', 'm', 'm', 0,
917
  /* 2102 */ 'X', 'O', 'R', '8', 'm', 'm', 0,
918
  /* 2109 */ 'B', 'I', 'T', '8', 'm', 'm', 0,
919
  /* 2116 */ 'M', 'O', 'V', '8', 'm', 'm', 0,
920
  /* 2123 */ 'S', 'U', 'B', '1', '6', 'r', 'm', 0,
921
  /* 2131 */ 'S', 'B', 'C', '1', '6', 'r', 'm', 0,
922
  /* 2139 */ 'A', 'D', 'C', '1', '6', 'r', 'm', 0,
923
  /* 2147 */ 'B', 'I', 'C', '1', '6', 'r', 'm', 0,
924
  /* 2155 */ 'A', 'D', 'D', '1', '6', 'r', 'm', 0,
925
  /* 2163 */ 'A', 'N', 'D', '1', '6', 'r', 'm', 0,
926
  /* 2171 */ 'C', 'M', 'P', '1', '6', 'r', 'm', 0,
927
  /* 2179 */ 'X', 'O', 'R', '1', '6', 'r', 'm', 0,
928
  /* 2187 */ 'B', 'I', 'T', '1', '6', 'r', 'm', 0,
929
  /* 2195 */ 'M', 'O', 'V', '1', '6', 'r', 'm', 0,
930
  /* 2203 */ 'S', 'U', 'B', '8', 'r', 'm', 0,
931
  /* 2210 */ 'S', 'B', 'C', '8', 'r', 'm', 0,
932
  /* 2217 */ 'A', 'D', 'C', '8', 'r', 'm', 0,
933
  /* 2224 */ 'B', 'I', 'C', '8', 'r', 'm', 0,
934
  /* 2231 */ 'A', 'D', 'D', '8', 'r', 'm', 0,
935
  /* 2238 */ 'A', 'N', 'D', '8', 'r', 'm', 0,
936
  /* 2245 */ 'C', 'M', 'P', '8', 'r', 'm', 0,
937
  /* 2252 */ 'X', 'O', 'R', '8', 'r', 'm', 0,
938
  /* 2259 */ 'B', 'I', 'T', '8', 'r', 'm', 0,
939
  /* 2266 */ 'M', 'O', 'V', '8', 'r', 'm', 0,
940
  /* 2273 */ 'S', 'W', 'P', 'B', '1', '6', 'r', 0,
941
  /* 2281 */ 'P', 'U', 'S', 'H', '1', '6', 'r', 0,
942
  /* 2289 */ 'P', 'O', 'P', '1', '6', 'r', 0,
943
  /* 2296 */ 'S', 'E', 'X', 'T', '1', '6', 'r', 0,
944
  /* 2304 */ 'Z', 'E', 'X', 'T', '1', '6', 'r', 0,
945
  /* 2312 */ 'B', 'r', 0,
946
  /* 2315 */ 'C', 'A', 'L', 'L', 'r', 0,
947
  /* 2321 */ 'S', 'U', 'B', '1', '6', 'm', 'r', 0,
948
  /* 2329 */ 'S', 'B', 'C', '1', '6', 'm', 'r', 0,
949
  /* 2337 */ 'A', 'D', 'C', '1', '6', 'm', 'r', 0,
950
  /* 2345 */ 'B', 'I', 'C', '1', '6', 'm', 'r', 0,
951
  /* 2353 */ 'A', 'D', 'D', '1', '6', 'm', 'r', 0,
952
  /* 2361 */ 'A', 'N', 'D', '1', '6', 'm', 'r', 0,
953
  /* 2369 */ 'C', 'M', 'P', '1', '6', 'm', 'r', 0,
954
  /* 2377 */ 'X', 'O', 'R', '1', '6', 'm', 'r', 0,
955
  /* 2385 */ 'B', 'I', 'T', '1', '6', 'm', 'r', 0,
956
  /* 2393 */ 'M', 'O', 'V', '1', '6', 'm', 'r', 0,
957
  /* 2401 */ 'S', 'U', 'B', '8', 'm', 'r', 0,
958
  /* 2408 */ 'S', 'B', 'C', '8', 'm', 'r', 0,
959
  /* 2415 */ 'A', 'D', 'C', '8', 'm', 'r', 0,
960
  /* 2422 */ 'B', 'I', 'C', '8', 'm', 'r', 0,
961
  /* 2429 */ 'A', 'D', 'D', '8', 'm', 'r', 0,
962
  /* 2436 */ 'A', 'N', 'D', '8', 'm', 'r', 0,
963
  /* 2443 */ 'C', 'M', 'P', '8', 'm', 'r', 0,
964
  /* 2450 */ 'X', 'O', 'R', '8', 'm', 'r', 0,
965
  /* 2457 */ 'B', 'I', 'T', '8', 'm', 'r', 0,
966
  /* 2464 */ 'M', 'O', 'V', '8', 'm', 'r', 0,
967
  /* 2471 */ 'S', 'U', 'B', '1', '6', 'r', 'r', 0,
968
  /* 2479 */ 'S', 'B', 'C', '1', '6', 'r', 'r', 0,
969
  /* 2487 */ 'A', 'D', 'C', '1', '6', 'r', 'r', 0,
970
  /* 2495 */ 'B', 'I', 'C', '1', '6', 'r', 'r', 0,
971
  /* 2503 */ 'A', 'D', 'D', '1', '6', 'r', 'r', 0,
972
  /* 2511 */ 'A', 'N', 'D', '1', '6', 'r', 'r', 0,
973
  /* 2519 */ 'C', 'M', 'P', '1', '6', 'r', 'r', 0,
974
  /* 2527 */ 'X', 'O', 'R', '1', '6', 'r', 'r', 0,
975
  /* 2535 */ 'B', 'I', 'T', '1', '6', 'r', 'r', 0,
976
  /* 2543 */ 'M', 'O', 'V', '1', '6', 'r', 'r', 0,
977
  /* 2551 */ 'S', 'U', 'B', '8', 'r', 'r', 0,
978
  /* 2558 */ 'S', 'B', 'C', '8', 'r', 'r', 0,
979
  /* 2565 */ 'A', 'D', 'C', '8', 'r', 'r', 0,
980
  /* 2572 */ 'B', 'I', 'C', '8', 'r', 'r', 0,
981
  /* 2579 */ 'A', 'D', 'D', '8', 'r', 'r', 0,
982
  /* 2586 */ 'A', 'N', 'D', '8', 'r', 'r', 0,
983
  /* 2593 */ 'C', 'M', 'P', '8', 'r', 'r', 0,
984
  /* 2600 */ 'X', 'O', 'R', '8', 'r', 'r', 0,
985
  /* 2607 */ 'B', 'I', 'T', '8', 'r', 'r', 0,
986
  /* 2614 */ 'M', 'O', 'V', '8', 'r', 'r', 0,
987
};
988
989
extern const unsigned MSP430InstrNameIndices[] = {
990
    537U, 765U, 808U, 594U, 575U, 603U, 726U, 427U, 
991
    442U, 407U, 456U, 1136U, 380U, 584U, 331U, 1669U, 
992
    352U, 1387U, 284U, 873U, 714U, 1355U, 306U, 1344U, 
993
    359U, 949U, 936U, 988U, 1242U, 1256U, 646U, 693U, 
994
    666U, 620U, 223U, 131U, 738U, 1601U, 1608U, 751U, 
995
    758U, 262U, 1066U, 1044U, 405U, 535U, 1655U, 390U, 
996
    1210U, 1104U, 1402U, 1121U, 1366U, 1086U, 1411U, 209U, 
997
    187U, 198U, 372U, 1153U, 470U, 487U, 229U, 137U, 
998
    268U, 245U, 1071U, 1050U, 1639U, 792U, 1622U, 775U, 
999
    297U, 1229U, 157U, 1183U, 1578U, 179U, 1333U, 1321U, 
1000
    1377U, 511U, 1571U, 1587U, 640U, 1020U, 1013U, 921U, 
1001
    914U, 1220U, 344U, 323U, 849U, 841U, 865U, 857U, 
1002
    527U, 519U, 216U, 124U, 731U, 118U, 1594U, 744U, 
1003
    1615U, 976U, 38U, 504U, 30U, 420U, 1563U, 169U, 
1004
    541U, 555U, 896U, 905U, 1097U, 890U, 564U, 983U, 
1005
    1301U, 1280U, 1027U, 882U, 1421U, 1725U, 2004U, 2337U, 
1006
    1860U, 2139U, 2487U, 1795U, 2074U, 2415U, 1930U, 2217U, 
1007
    2565U, 1733U, 2020U, 2353U, 1868U, 2155U, 1451U, 2503U, 
1008
    1802U, 2088U, 2429U, 1937U, 2231U, 1515U, 2579U, 1691U, 
1009
    824U, 961U, 1741U, 2028U, 2361U, 1876U, 2163U, 1464U, 
1010
    2511U, 1809U, 2095U, 2436U, 1944U, 2238U, 1527U, 2586U, 
1011
    2012U, 2345U, 2147U, 2495U, 2081U, 2422U, 2224U, 2572U, 
1012
    1765U, 2044U, 2385U, 1900U, 2187U, 2535U, 1830U, 2109U, 
1013
    2457U, 1965U, 2259U, 2607U, 1700U, 1979U, 2312U, 1703U, 
1014
    1982U, 2315U, 1749U, 2369U, 1884U, 2171U, 2519U, 1816U, 
1015
    2443U, 1951U, 2245U, 2593U, 153U, 928U, 1773U, 2052U, 
1016
    2393U, 1908U, 2195U, 1490U, 2543U, 1837U, 2116U, 2464U, 
1017
    1972U, 2266U, 1551U, 2614U, 88U, 99U, 932U, 1758U, 
1018
    2037U, 2378U, 1893U, 2180U, 1478U, 2528U, 1824U, 2103U, 
1019
    2451U, 1959U, 2253U, 1540U, 2601U, 2289U, 2281U, 1252U, 
1020
    550U, 8U, 1674U, 23U, 1683U, 1717U, 1996U, 2329U, 
1021
    1852U, 2131U, 2479U, 1788U, 2067U, 2408U, 1923U, 2210U, 
1022
    2558U, 2296U, 0U, 16U, 1709U, 1988U, 2321U, 1844U, 
1023
    2123U, 1438U, 2471U, 1781U, 2060U, 2401U, 1916U, 2203U, 
1024
    1503U, 2551U, 2273U, 64U, 110U, 52U, 78U, 46U, 
1025
    73U, 58U, 83U, 1757U, 2036U, 2377U, 1892U, 2179U, 
1026
    1477U, 2527U, 1823U, 2102U, 2450U, 1958U, 2252U, 1539U, 
1027
    2600U, 2304U, 
1028
};
1029
1030
64
static inline void InitMSP430MCInstrInfo(MCInstrInfo *II) {
1031
64
  II->InitMCInstrInfo(MSP430Insts, MSP430InstrNameIndices, MSP430InstrNameData, 298);
1032
64
}
1033
1034
} // end llvm namespace
1035
#endif // GET_INSTRINFO_MC_DESC
1036
1037
#ifdef GET_INSTRINFO_HEADER
1038
#undef GET_INSTRINFO_HEADER
1039
namespace llvm {
1040
struct MSP430GenInstrInfo : public TargetInstrInfo {
1041
  explicit MSP430GenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);
1042
64
  ~MSP430GenInstrInfo() override = default;
1043
1044
};
1045
} // end llvm namespace
1046
#endif // GET_INSTRINFO_HEADER
1047
1048
#ifdef GET_INSTRINFO_CTOR_DTOR
1049
#undef GET_INSTRINFO_CTOR_DTOR
1050
namespace llvm {
1051
extern const MCInstrDesc MSP430Insts[];
1052
extern const unsigned MSP430InstrNameIndices[];
1053
extern const char MSP430InstrNameData[];
1054
MSP430GenInstrInfo::MSP430GenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)
1055
64
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1056
64
  InitMCInstrInfo(MSP430Insts, MSP430InstrNameIndices, MSP430InstrNameData, 298);
1057
64
}
1058
} // end llvm namespace
1059
#endif // GET_INSTRINFO_CTOR_DTOR
1060
1061
#ifdef GET_INSTRINFO_OPERAND_ENUM
1062
#undef GET_INSTRINFO_OPERAND_ENUM
1063
namespace llvm {
1064
namespace MSP430 {
1065
namespace OpName {
1066
enum {
1067
OPERAND_LAST
1068
};
1069
} // end namespace OpName
1070
} // end namespace MSP430
1071
} // end namespace llvm
1072
#endif //GET_INSTRINFO_OPERAND_ENUM
1073
1074
#ifdef GET_INSTRINFO_NAMED_OPS
1075
#undef GET_INSTRINFO_NAMED_OPS
1076
namespace llvm {
1077
namespace MSP430 {
1078
LLVM_READONLY
1079
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
1080
  return -1;
1081
}
1082
} // end namespace MSP430
1083
} // end namespace llvm
1084
#endif //GET_INSTRINFO_NAMED_OPS
1085
1086
#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
1087
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
1088
namespace llvm {
1089
namespace MSP430 {
1090
namespace OpTypes {
1091
enum OperandType {
1092
  cc = 0,
1093
  f32imm = 1,
1094
  f64imm = 2,
1095
  i16imm = 3,
1096
  i1imm = 4,
1097
  i32imm = 5,
1098
  i64imm = 6,
1099
  i8imm = 7,
1100
  jmptarget = 8,
1101
  memdst = 9,
1102
  memsrc = 10,
1103
  ptype0 = 11,
1104
  ptype1 = 12,
1105
  ptype2 = 13,
1106
  ptype3 = 14,
1107
  ptype4 = 15,
1108
  ptype5 = 16,
1109
  type0 = 17,
1110
  type1 = 18,
1111
  type2 = 19,
1112
  type3 = 20,
1113
  type4 = 21,
1114
  type5 = 22,
1115
  OPERAND_TYPE_LIST_END
1116
};
1117
} // end namespace OpTypes
1118
} // end namespace MSP430
1119
} // end namespace llvm
1120
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
1121