Coverage Report

Created: 2018-09-19 20:53

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/MSP430/MSP430GenInstrInfo.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Target Instruction Enum Values and Descriptors                             *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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9
#ifdef GET_INSTRINFO_ENUM
10
#undef GET_INSTRINFO_ENUM
11
namespace llvm {
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namespace MSP430 {
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  enum {
15
    PHI = 0,
16
    INLINEASM = 1,
17
    CFI_INSTRUCTION = 2,
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    EH_LABEL  = 3,
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    GC_LABEL  = 4,
20
    ANNOTATION_LABEL  = 5,
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    KILL  = 6,
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    EXTRACT_SUBREG  = 7,
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    INSERT_SUBREG = 8,
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    IMPLICIT_DEF  = 9,
25
    SUBREG_TO_REG = 10,
26
    COPY_TO_REGCLASS  = 11,
27
    DBG_VALUE = 12,
28
    DBG_LABEL = 13,
29
    REG_SEQUENCE  = 14,
30
    COPY  = 15,
31
    BUNDLE  = 16,
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    LIFETIME_START  = 17,
33
    LIFETIME_END  = 18,
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    STACKMAP  = 19,
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    FENTRY_CALL = 20,
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    PATCHPOINT  = 21,
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    LOAD_STACK_GUARD  = 22,
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    STATEPOINT  = 23,
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    LOCAL_ESCAPE  = 24,
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    FAULTING_OP = 25,
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    PATCHABLE_OP  = 26,
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    PATCHABLE_FUNCTION_ENTER  = 27,
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    PATCHABLE_RET = 28,
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    PATCHABLE_FUNCTION_EXIT = 29,
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    PATCHABLE_TAIL_CALL = 30,
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    PATCHABLE_EVENT_CALL  = 31,
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    PATCHABLE_TYPED_EVENT_CALL  = 32,
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    ICALL_BRANCH_FUNNEL = 33,
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    G_ADD = 34,
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    G_SUB = 35,
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    G_MUL = 36,
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    G_SDIV  = 37,
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    G_UDIV  = 38,
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    G_SREM  = 39,
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    G_UREM  = 40,
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    G_AND = 41,
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    G_OR  = 42,
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    G_XOR = 43,
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    G_IMPLICIT_DEF  = 44,
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    G_PHI = 45,
61
    G_FRAME_INDEX = 46,
62
    G_GLOBAL_VALUE  = 47,
63
    G_EXTRACT = 48,
64
    G_UNMERGE_VALUES  = 49,
65
    G_INSERT  = 50,
66
    G_MERGE_VALUES  = 51,
67
    G_PTRTOINT  = 52,
68
    G_INTTOPTR  = 53,
69
    G_BITCAST = 54,
70
    G_INTRINSIC_TRUNC = 55,
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    G_INTRINSIC_ROUND = 56,
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    G_LOAD  = 57,
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    G_SEXTLOAD  = 58,
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    G_ZEXTLOAD  = 59,
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    G_STORE = 60,
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    G_ATOMIC_CMPXCHG_WITH_SUCCESS = 61,
77
    G_ATOMIC_CMPXCHG  = 62,
78
    G_ATOMICRMW_XCHG  = 63,
79
    G_ATOMICRMW_ADD = 64,
80
    G_ATOMICRMW_SUB = 65,
81
    G_ATOMICRMW_AND = 66,
82
    G_ATOMICRMW_NAND  = 67,
83
    G_ATOMICRMW_OR  = 68,
84
    G_ATOMICRMW_XOR = 69,
85
    G_ATOMICRMW_MAX = 70,
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    G_ATOMICRMW_MIN = 71,
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    G_ATOMICRMW_UMAX  = 72,
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    G_ATOMICRMW_UMIN  = 73,
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    G_BRCOND  = 74,
90
    G_BRINDIRECT  = 75,
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    G_INTRINSIC = 76,
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    G_INTRINSIC_W_SIDE_EFFECTS  = 77,
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    G_ANYEXT  = 78,
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    G_TRUNC = 79,
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    G_CONSTANT  = 80,
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    G_FCONSTANT = 81,
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    G_VASTART = 82,
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    G_VAARG = 83,
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    G_SEXT  = 84,
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    G_ZEXT  = 85,
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    G_SHL = 86,
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    G_LSHR  = 87,
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    G_ASHR  = 88,
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    G_ICMP  = 89,
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    G_FCMP  = 90,
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    G_SELECT  = 91,
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    G_UADDO = 92,
108
    G_UADDE = 93,
109
    G_USUBO = 94,
110
    G_USUBE = 95,
111
    G_SADDO = 96,
112
    G_SADDE = 97,
113
    G_SSUBO = 98,
114
    G_SSUBE = 99,
115
    G_UMULO = 100,
116
    G_SMULO = 101,
117
    G_UMULH = 102,
118
    G_SMULH = 103,
119
    G_FADD  = 104,
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    G_FSUB  = 105,
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    G_FMUL  = 106,
122
    G_FMA = 107,
123
    G_FDIV  = 108,
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    G_FREM  = 109,
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    G_FPOW  = 110,
126
    G_FEXP  = 111,
127
    G_FEXP2 = 112,
128
    G_FLOG  = 113,
129
    G_FLOG2 = 114,
130
    G_FNEG  = 115,
131
    G_FPEXT = 116,
132
    G_FPTRUNC = 117,
133
    G_FPTOSI  = 118,
134
    G_FPTOUI  = 119,
135
    G_SITOFP  = 120,
136
    G_UITOFP  = 121,
137
    G_FABS  = 122,
138
    G_GEP = 123,
139
    G_PTR_MASK  = 124,
140
    G_BR  = 125,
141
    G_INSERT_VECTOR_ELT = 126,
142
    G_EXTRACT_VECTOR_ELT  = 127,
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    G_SHUFFLE_VECTOR  = 128,
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    G_CTTZ  = 129,
145
    G_CTTZ_ZERO_UNDEF = 130,
146
    G_CTLZ  = 131,
147
    G_CTLZ_ZERO_UNDEF = 132,
148
    G_CTPOP = 133,
149
    G_BSWAP = 134,
150
    G_ADDRSPACE_CAST  = 135,
151
    G_BLOCK_ADDR  = 136,
152
    ADC16mi = 137,
153
    ADC16mm = 138,
154
    ADC16mr = 139,
155
    ADC16ri = 140,
156
    ADC16rm = 141,
157
    ADC16rr = 142,
158
    ADC8mi  = 143,
159
    ADC8mm  = 144,
160
    ADC8mr  = 145,
161
    ADC8ri  = 146,
162
    ADC8rm  = 147,
163
    ADC8rr  = 148,
164
    ADD16mi = 149,
165
    ADD16mm = 150,
166
    ADD16mr = 151,
167
    ADD16ri = 152,
168
    ADD16rm = 153,
169
    ADD16rm_POST  = 154,
170
    ADD16rr = 155,
171
    ADD8mi  = 156,
172
    ADD8mm  = 157,
173
    ADD8mr  = 158,
174
    ADD8ri  = 159,
175
    ADD8rm  = 160,
176
    ADD8rm_POST = 161,
177
    ADD8rr  = 162,
178
    ADDframe  = 163,
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    ADJCALLSTACKDOWN  = 164,
180
    ADJCALLSTACKUP  = 165,
181
    AND16mi = 166,
182
    AND16mm = 167,
183
    AND16mr = 168,
184
    AND16ri = 169,
185
    AND16rm = 170,
186
    AND16rm_POST  = 171,
187
    AND16rr = 172,
188
    AND8mi  = 173,
189
    AND8mm  = 174,
190
    AND8mr  = 175,
191
    AND8ri  = 176,
192
    AND8rm  = 177,
193
    AND8rm_POST = 178,
194
    AND8rr  = 179,
195
    BIC16mm = 180,
196
    BIC16mr = 181,
197
    BIC16rm = 182,
198
    BIC16rr = 183,
199
    BIC8mm  = 184,
200
    BIC8mr  = 185,
201
    BIC8rm  = 186,
202
    BIC8rr  = 187,
203
    BIT16mi = 188,
204
    BIT16mm = 189,
205
    BIT16mr = 190,
206
    BIT16ri = 191,
207
    BIT16rm = 192,
208
    BIT16rr = 193,
209
    BIT8mi  = 194,
210
    BIT8mm  = 195,
211
    BIT8mr  = 196,
212
    BIT8ri  = 197,
213
    BIT8rm  = 198,
214
    BIT8rr  = 199,
215
    Bi  = 200,
216
    Bm  = 201,
217
    Br  = 202,
218
    CALLi = 203,
219
    CALLm = 204,
220
    CALLr = 205,
221
    CMP16mi = 206,
222
    CMP16mr = 207,
223
    CMP16ri = 208,
224
    CMP16rm = 209,
225
    CMP16rr = 210,
226
    CMP8mi  = 211,
227
    CMP8mr  = 212,
228
    CMP8ri  = 213,
229
    CMP8rm  = 214,
230
    CMP8rr  = 215,
231
    JCC = 216,
232
    JMP = 217,
233
    MOV16mi = 218,
234
    MOV16mm = 219,
235
    MOV16mr = 220,
236
    MOV16ri = 221,
237
    MOV16rm = 222,
238
    MOV16rm_POST  = 223,
239
    MOV16rr = 224,
240
    MOV8mi  = 225,
241
    MOV8mm  = 226,
242
    MOV8mr  = 227,
243
    MOV8ri  = 228,
244
    MOV8rm  = 229,
245
    MOV8rm_POST = 230,
246
    MOV8rr  = 231,
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    MOVZX16rm8  = 232,
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    MOVZX16rr8  = 233,
249
    NOP = 234,
250
    OR16mi  = 235,
251
    OR16mm  = 236,
252
    OR16mr  = 237,
253
    OR16ri  = 238,
254
    OR16rm  = 239,
255
    OR16rm_POST = 240,
256
    OR16rr  = 241,
257
    OR8mi = 242,
258
    OR8mm = 243,
259
    OR8mr = 244,
260
    OR8ri = 245,
261
    OR8rm = 246,
262
    OR8rm_POST  = 247,
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    OR8rr = 248,
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    POP16r  = 249,
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    PUSH16r = 250,
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    RET = 251,
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    RETI  = 252,
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    SAR16r1 = 253,
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    SAR16r1c  = 254,
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    SAR8r1  = 255,
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    SAR8r1c = 256,
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    SBC16mi = 257,
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    SBC16mm = 258,
274
    SBC16mr = 259,
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    SBC16ri = 260,
276
    SBC16rm = 261,
277
    SBC16rr = 262,
278
    SBC8mi  = 263,
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    SBC8mm  = 264,
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    SBC8mr  = 265,
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    SBC8ri  = 266,
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    SBC8rm  = 267,
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    SBC8rr  = 268,
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    SEXT16r = 269,
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    SHL16r1 = 270,
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    SHL8r1  = 271,
287
    SUB16mi = 272,
288
    SUB16mm = 273,
289
    SUB16mr = 274,
290
    SUB16ri = 275,
291
    SUB16rm = 276,
292
    SUB16rm_POST  = 277,
293
    SUB16rr = 278,
294
    SUB8mi  = 279,
295
    SUB8mm  = 280,
296
    SUB8mr  = 281,
297
    SUB8ri  = 282,
298
    SUB8rm  = 283,
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    SUB8rm_POST = 284,
300
    SUB8rr  = 285,
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    SWPB16r = 286,
302
    Select16  = 287,
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    Select8 = 288,
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    Shl16 = 289,
305
    Shl8  = 290,
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    Sra16 = 291,
307
    Sra8  = 292,
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    Srl16 = 293,
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    Srl8  = 294,
310
    XOR16mi = 295,
311
    XOR16mm = 296,
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    XOR16mr = 297,
313
    XOR16ri = 298,
314
    XOR16rm = 299,
315
    XOR16rm_POST  = 300,
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    XOR16rr = 301,
317
    XOR8mi  = 302,
318
    XOR8mm  = 303,
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    XOR8mr  = 304,
320
    XOR8ri  = 305,
321
    XOR8rm  = 306,
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    XOR8rm_POST = 307,
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    XOR8rr  = 308,
324
    ZEXT16r = 309,
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    INSTRUCTION_LIST_END = 310
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  };
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} // end MSP430 namespace
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} // end llvm namespace
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#endif // GET_INSTRINFO_ENUM
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#ifdef GET_INSTRINFO_SCHED_ENUM
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#undef GET_INSTRINFO_SCHED_ENUM
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namespace llvm {
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namespace MSP430 {
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namespace Sched {
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  enum {
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    NoInstrModel  = 0,
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    SCHED_LIST_END = 1
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  };
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} // end Sched namespace
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} // end MSP430 namespace
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} // end llvm namespace
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#endif // GET_INSTRINFO_SCHED_ENUM
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#ifdef GET_INSTRINFO_MC_DESC
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#undef GET_INSTRINFO_MC_DESC
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namespace llvm {
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static const MCPhysReg ImplicitList1[] = { MSP430::SR, 0 };
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static const MCPhysReg ImplicitList2[] = { MSP430::SP, 0 };
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static const MCPhysReg ImplicitList3[] = { MSP430::SP, MSP430::SR, 0 };
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static const MCPhysReg ImplicitList4[] = { MSP430::R11, MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, MSP430::SR, 0 };
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static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
357
static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
358
static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
359
static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
360
static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
361
static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
362
static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
363
static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
364
static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
365
static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
366
static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
367
static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
368
static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
369
static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
370
static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
371
static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
372
static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
373
static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
374
static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
375
static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
376
static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
377
static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
378
static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
379
static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
380
static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
381
static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
382
static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
383
static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
384
static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
385
static const MCOperandInfo OperandInfo31[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
386
static const MCOperandInfo OperandInfo32[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
387
static const MCOperandInfo OperandInfo33[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
388
static const MCOperandInfo OperandInfo34[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
389
static const MCOperandInfo OperandInfo35[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
390
static const MCOperandInfo OperandInfo36[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
391
static const MCOperandInfo OperandInfo37[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
392
static const MCOperandInfo OperandInfo38[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
393
static const MCOperandInfo OperandInfo39[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
394
static const MCOperandInfo OperandInfo40[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
395
static const MCOperandInfo OperandInfo41[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
396
static const MCOperandInfo OperandInfo42[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
397
static const MCOperandInfo OperandInfo43[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
398
static const MCOperandInfo OperandInfo44[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
399
static const MCOperandInfo OperandInfo45[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
400
static const MCOperandInfo OperandInfo46[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
401
static const MCOperandInfo OperandInfo47[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
402
static const MCOperandInfo OperandInfo48[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
403
static const MCOperandInfo OperandInfo49[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
404
static const MCOperandInfo OperandInfo50[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
405
static const MCOperandInfo OperandInfo51[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
406
static const MCOperandInfo OperandInfo52[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
407
static const MCOperandInfo OperandInfo53[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
408
static const MCOperandInfo OperandInfo54[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
409
static const MCOperandInfo OperandInfo55[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
410
static const MCOperandInfo OperandInfo56[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
411
static const MCOperandInfo OperandInfo57[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
412
static const MCOperandInfo OperandInfo58[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
413
static const MCOperandInfo OperandInfo59[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
414
static const MCOperandInfo OperandInfo60[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
415
416
extern const MCInstrDesc MSP430Insts[] = {
417
  { 0,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
418
  { 1,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
419
  { 2,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #2 = CFI_INSTRUCTION
420
  { 3,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = EH_LABEL
421
  { 4,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = GC_LABEL
422
  { 5,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = ANNOTATION_LABEL
423
  { 6,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #6 = KILL
424
  { 7,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #7 = EXTRACT_SUBREG
425
  { 8,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #8 = INSERT_SUBREG
426
  { 9,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #9 = IMPLICIT_DEF
427
  { 10, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #10 = SUBREG_TO_REG
428
  { 11, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #11 = COPY_TO_REGCLASS
429
  { 12, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #12 = DBG_VALUE
430
  { 13, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #13 = DBG_LABEL
431
  { 14, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #14 = REG_SEQUENCE
432
  { 15, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #15 = COPY
433
  { 16, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #16 = BUNDLE
434
  { 17, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #17 = LIFETIME_START
435
  { 18, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #18 = LIFETIME_END
436
  { 19, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #19 = STACKMAP
437
  { 20, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #20 = FENTRY_CALL
438
  { 21, 6,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #21 = PATCHPOINT
439
  { 22, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #22 = LOAD_STACK_GUARD
440
  { 23, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #23 = STATEPOINT
441
  { 24, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #24 = LOCAL_ESCAPE
442
  { 25, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #25 = FAULTING_OP
443
  { 26, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #26 = PATCHABLE_OP
444
  { 27, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #27 = PATCHABLE_FUNCTION_ENTER
445
  { 28, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #28 = PATCHABLE_RET
446
  { 29, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #29 = PATCHABLE_FUNCTION_EXIT
447
  { 30, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #30 = PATCHABLE_TAIL_CALL
448
  { 31, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #31 = PATCHABLE_EVENT_CALL
449
  { 32, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #32 = PATCHABLE_TYPED_EVENT_CALL
450
  { 33, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #33 = ICALL_BRANCH_FUNNEL
451
  { 34, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #34 = G_ADD
452
  { 35, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #35 = G_SUB
453
  { 36, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #36 = G_MUL
454
  { 37, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #37 = G_SDIV
455
  { 38, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #38 = G_UDIV
456
  { 39, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #39 = G_SREM
457
  { 40, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #40 = G_UREM
458
  { 41, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_AND
459
  { 42, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_OR
460
  { 43, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #43 = G_XOR
461
  { 44, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #44 = G_IMPLICIT_DEF
462
  { 45, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #45 = G_PHI
463
  { 46, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #46 = G_FRAME_INDEX
464
  { 47, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #47 = G_GLOBAL_VALUE
465
  { 48, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #48 = G_EXTRACT
466
  { 49, 2,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #49 = G_UNMERGE_VALUES
467
  { 50, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #50 = G_INSERT
468
  { 51, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #51 = G_MERGE_VALUES
469
  { 52, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #52 = G_PTRTOINT
470
  { 53, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = G_INTTOPTR
471
  { 54, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #54 = G_BITCAST
472
  { 55, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #55 = G_INTRINSIC_TRUNC
473
  { 56, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #56 = G_INTRINSIC_ROUND
474
  { 57, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #57 = G_LOAD
475
  { 58, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #58 = G_SEXTLOAD
476
  { 59, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #59 = G_ZEXTLOAD
477
  { 60, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #60 = G_STORE
478
  { 61, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #61 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
479
  { 62, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #62 = G_ATOMIC_CMPXCHG
480
  { 63, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #63 = G_ATOMICRMW_XCHG
481
  { 64, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #64 = G_ATOMICRMW_ADD
482
  { 65, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #65 = G_ATOMICRMW_SUB
483
  { 66, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #66 = G_ATOMICRMW_AND
484
  { 67, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #67 = G_ATOMICRMW_NAND
485
  { 68, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #68 = G_ATOMICRMW_OR
486
  { 69, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #69 = G_ATOMICRMW_XOR
487
  { 70, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #70 = G_ATOMICRMW_MAX
488
  { 71, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #71 = G_ATOMICRMW_MIN
489
  { 72, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #72 = G_ATOMICRMW_UMAX
490
  { 73, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #73 = G_ATOMICRMW_UMIN
491
  { 74, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #74 = G_BRCOND
492
  { 75, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #75 = G_BRINDIRECT
493
  { 76, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #76 = G_INTRINSIC
494
  { 77, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #77 = G_INTRINSIC_W_SIDE_EFFECTS
495
  { 78, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #78 = G_ANYEXT
496
  { 79, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #79 = G_TRUNC
497
  { 80, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #80 = G_CONSTANT
498
  { 81, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #81 = G_FCONSTANT
499
  { 82, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #82 = G_VASTART
500
  { 83, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #83 = G_VAARG
501
  { 84, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #84 = G_SEXT
502
  { 85, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #85 = G_ZEXT
503
  { 86, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #86 = G_SHL
504
  { 87, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #87 = G_LSHR
505
  { 88, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #88 = G_ASHR
506
  { 89, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #89 = G_ICMP
507
  { 90, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #90 = G_FCMP
508
  { 91, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #91 = G_SELECT
509
  { 92, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #92 = G_UADDO
510
  { 93, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #93 = G_UADDE
511
  { 94, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #94 = G_USUBO
512
  { 95, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #95 = G_USUBE
513
  { 96, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #96 = G_SADDO
514
  { 97, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #97 = G_SADDE
515
  { 98, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #98 = G_SSUBO
516
  { 99, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #99 = G_SSUBE
517
  { 100,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #100 = G_UMULO
518
  { 101,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #101 = G_SMULO
519
  { 102,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #102 = G_UMULH
520
  { 103,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #103 = G_SMULH
521
  { 104,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #104 = G_FADD
522
  { 105,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #105 = G_FSUB
523
  { 106,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #106 = G_FMUL
524
  { 107,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #107 = G_FMA
525
  { 108,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #108 = G_FDIV
526
  { 109,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #109 = G_FREM
527
  { 110,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #110 = G_FPOW
528
  { 111,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #111 = G_FEXP
529
  { 112,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #112 = G_FEXP2
530
  { 113,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #113 = G_FLOG
531
  { 114,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #114 = G_FLOG2
532
  { 115,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #115 = G_FNEG
533
  { 116,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #116 = G_FPEXT
534
  { 117,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #117 = G_FPTRUNC
535
  { 118,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #118 = G_FPTOSI
536
  { 119,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #119 = G_FPTOUI
537
  { 120,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #120 = G_SITOFP
538
  { 121,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #121 = G_UITOFP
539
  { 122,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #122 = G_FABS
540
  { 123,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #123 = G_GEP
541
  { 124,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #124 = G_PTR_MASK
542
  { 125,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #125 = G_BR
543
  { 126,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #126 = G_INSERT_VECTOR_ELT
544
  { 127,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #127 = G_EXTRACT_VECTOR_ELT
545
  { 128,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #128 = G_SHUFFLE_VECTOR
546
  { 129,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #129 = G_CTTZ
547
  { 130,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #130 = G_CTTZ_ZERO_UNDEF
548
  { 131,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #131 = G_CTLZ
549
  { 132,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #132 = G_CTLZ_ZERO_UNDEF
550
  { 133,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #133 = G_CTPOP
551
  { 134,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #134 = G_BSWAP
552
  { 135,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #135 = G_ADDRSPACE_CAST
553
  { 136,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #136 = G_BLOCK_ADDR
554
  { 137,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #137 = ADC16mi
555
  { 138,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, ImplicitList1, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #138 = ADC16mm
556
  { 139,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #139 = ADC16mr
557
  { 140,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #140 = ADC16ri
558
  { 141,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #141 = ADC16rm
559
  { 142,  3,  1,  0,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #142 = ADC16rr
560
  { 143,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #143 = ADC8mi
561
  { 144,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, ImplicitList1, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #144 = ADC8mm
562
  { 145,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #145 = ADC8mr
563
  { 146,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #146 = ADC8ri
564
  { 147,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #147 = ADC8rm
565
  { 148,  3,  1,  0,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #148 = ADC8rr
566
  { 149,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #149 = ADD16mi
567
  { 150,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #150 = ADD16mm
568
  { 151,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #151 = ADD16mr
569
  { 152,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #152 = ADD16ri
570
  { 153,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #153 = ADD16rm
571
  { 154,  4,  2,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #154 = ADD16rm_POST
572
  { 155,  3,  1,  0,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #155 = ADD16rr
573
  { 156,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #156 = ADD8mi
574
  { 157,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #157 = ADD8mm
575
  { 158,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #158 = ADD8mr
576
  { 159,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #159 = ADD8ri
577
  { 160,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #160 = ADD8rm
578
  { 161,  4,  2,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #161 = ADD8rm_POST
579
  { 162,  3,  1,  0,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #162 = ADD8rr
580
  { 163,  3,  1,  0,  0,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, ImplicitList2, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #163 = ADDframe
581
  { 164,  2,  0,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, ImplicitList2, ImplicitList3, OperandInfo8, -1 ,nullptr },  // Inst #164 = ADJCALLSTACKDOWN
582
  { 165,  2,  0,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, ImplicitList2, ImplicitList3, OperandInfo8, -1 ,nullptr },  // Inst #165 = ADJCALLSTACKUP
583
  { 166,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #166 = AND16mi
584
  { 167,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #167 = AND16mm
585
  { 168,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #168 = AND16mr
586
  { 169,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #169 = AND16ri
587
  { 170,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #170 = AND16rm
588
  { 171,  4,  2,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #171 = AND16rm_POST
589
  { 172,  3,  1,  0,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #172 = AND16rr
590
  { 173,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #173 = AND8mi
591
  { 174,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #174 = AND8mm
592
  { 175,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #175 = AND8mr
593
  { 176,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #176 = AND8ri
594
  { 177,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #177 = AND8rm
595
  { 178,  4,  2,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #178 = AND8rm_POST
596
  { 179,  3,  1,  0,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #179 = AND8rr
597
  { 180,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #180 = BIC16mm
598
  { 181,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #181 = BIC16mr
599
  { 182,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #182 = BIC16rm
600
  { 183,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #183 = BIC16rr
601
  { 184,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #184 = BIC8mm
602
  { 185,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #185 = BIC8mr
603
  { 186,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #186 = BIC8rm
604
  { 187,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #187 = BIC8rr
605
  { 188,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #188 = BIT16mi
606
  { 189,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #189 = BIT16mm
607
  { 190,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #190 = BIT16mr
608
  { 191,  2,  0,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #191 = BIT16ri
609
  { 192,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #192 = BIT16rm
610
  { 193,  2,  0,  0,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #193 = BIT16rr
611
  { 194,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #194 = BIT8mi
612
  { 195,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #195 = BIT8mm
613
  { 196,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #196 = BIT8mr
614
  { 197,  2,  0,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #197 = BIT8ri
615
  { 198,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #198 = BIT8rm
616
  { 199,  2,  0,  0,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo49, -1 ,nullptr },  // Inst #199 = BIT8rr
617
  { 200,  1,  0,  0,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #200 = Bi
618
  { 201,  2,  0,  0,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #201 = Bm
619
  { 202,  1,  0,  0,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #202 = Br
620
  { 203,  1,  0,  0,  0,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xdULL, ImplicitList2, ImplicitList4, OperandInfo3, -1 ,nullptr },  // Inst #203 = CALLi
621
  { 204,  2,  0,  0,  0,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xdULL, ImplicitList2, ImplicitList4, OperandInfo50, -1 ,nullptr },  // Inst #204 = CALLm
622
  { 205,  1,  0,  0,  0,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x9ULL, ImplicitList2, ImplicitList4, OperandInfo51, -1 ,nullptr },  // Inst #205 = CALLr
623
  { 206,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #206 = CMP16mi
624
  { 207,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #207 = CMP16mr
625
  { 208,  2,  0,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #208 = CMP16ri
626
  { 209,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #209 = CMP16rm
627
  { 210,  2,  0,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #210 = CMP16rr
628
  { 211,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #211 = CMP8mi
629
  { 212,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #212 = CMP8mr
630
  { 213,  2,  0,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #213 = CMP8ri
631
  { 214,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #214 = CMP8rm
632
  { 215,  2,  0,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo49, -1 ,nullptr },  // Inst #215 = CMP8rr
633
  { 216,  2,  0,  0,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xbULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #216 = JCC
634
  { 217,  1,  0,  0,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xbULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #217 = JMP
635
  { 218,  3,  0,  0,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #218 = MOV16mi
636
  { 219,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #219 = MOV16mm
637
  { 220,  3,  0,  0,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #220 = MOV16mr
638
  { 221,  2,  1,  0,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #221 = MOV16ri
639
  { 222,  3,  1,  0,  0,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #222 = MOV16rm
640
  { 223,  3,  2,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #223 = MOV16rm_POST
641
  { 224,  2,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #224 = MOV16rr
642
  { 225,  3,  0,  0,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #225 = MOV8mi
643
  { 226,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #226 = MOV8mm
644
  { 227,  3,  0,  0,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #227 = MOV8mr
645
  { 228,  2,  1,  0,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #228 = MOV8ri
646
  { 229,  3,  1,  0,  0,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #229 = MOV8rm
647
  { 230,  3,  2,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #230 = MOV8rm_POST
648
  { 231,  2,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #231 = MOV8rr
649
  { 232,  3,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #232 = MOVZX16rm8
650
  { 233,  2,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #233 = MOVZX16rr8
651
  { 234,  0,  0,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #234 = NOP
652
  { 235,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #235 = OR16mi
653
  { 236,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #236 = OR16mm
654
  { 237,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #237 = OR16mr
655
  { 238,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #238 = OR16ri
656
  { 239,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #239 = OR16rm
657
  { 240,  4,  2,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #240 = OR16rm_POST
658
  { 241,  3,  1,  0,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #241 = OR16rr
659
  { 242,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #242 = OR8mi
660
  { 243,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #243 = OR8mm
661
  { 244,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #244 = OR8mr
662
  { 245,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #245 = OR8ri
663
  { 246,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #246 = OR8rm
664
  { 247,  4,  2,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #247 = OR8rm_POST
665
  { 248,  3,  1,  0,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #248 = OR8rr
666
  { 249,  1,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, ImplicitList2, ImplicitList2, OperandInfo51, -1 ,nullptr },  // Inst #249 = POP16r
667
  { 250,  1,  0,  0,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x9ULL, ImplicitList2, ImplicitList2, OperandInfo51, -1 ,nullptr },  // Inst #250 = PUSH16r
668
  { 251,  0,  0,  0,  0,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #251 = RET
669
  { 252,  0,  0,  0,  0,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x9ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #252 = RETI
670
  { 253,  2,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x9ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #253 = SAR16r1
671
  { 254,  2,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #254 = SAR16r1c
672
  { 255,  2,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x9ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #255 = SAR8r1
673
  { 256,  2,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #256 = SAR8r1c
674
  { 257,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #257 = SBC16mi
675
  { 258,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, ImplicitList1, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #258 = SBC16mm
676
  { 259,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #259 = SBC16mr
677
  { 260,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #260 = SBC16ri
678
  { 261,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #261 = SBC16rm
679
  { 262,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #262 = SBC16rr
680
  { 263,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #263 = SBC8mi
681
  { 264,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, ImplicitList1, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #264 = SBC8mm
682
  { 265,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #265 = SBC8mr
683
  { 266,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #266 = SBC8ri
684
  { 267,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #267 = SBC8rm
685
  { 268,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #268 = SBC8rr
686
  { 269,  2,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x9ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #269 = SEXT16r
687
  { 270,  2,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #270 = SHL16r1
688
  { 271,  2,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #271 = SHL8r1
689
  { 272,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #272 = SUB16mi
690
  { 273,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #273 = SUB16mm
691
  { 274,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #274 = SUB16mr
692
  { 275,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #275 = SUB16ri
693
  { 276,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #276 = SUB16rm
694
  { 277,  4,  2,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #277 = SUB16rm_POST
695
  { 278,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #278 = SUB16rr
696
  { 279,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #279 = SUB8mi
697
  { 280,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #280 = SUB8mm
698
  { 281,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #281 = SUB8mr
699
  { 282,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #282 = SUB8ri
700
  { 283,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #283 = SUB8rm
701
  { 284,  4,  2,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #284 = SUB8rm_POST
702
  { 285,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #285 = SUB8rr
703
  { 286,  2,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x9ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #286 = SWPB16r
704
  { 287,  4,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, ImplicitList1, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #287 = Select16
705
  { 288,  4,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #288 = Select8
706
  { 289,  3,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #289 = Shl16
707
  { 290,  3,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, nullptr, ImplicitList1, OperandInfo60, -1 ,nullptr },  // Inst #290 = Shl8
708
  { 291,  3,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #291 = Sra16
709
  { 292,  3,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, nullptr, ImplicitList1, OperandInfo60, -1 ,nullptr },  // Inst #292 = Sra8
710
  { 293,  3,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #293 = Srl16
711
  { 294,  3,  1,  0,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x4ULL, nullptr, ImplicitList1, OperandInfo60, -1 ,nullptr },  // Inst #294 = Srl8
712
  { 295,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #295 = XOR16mi
713
  { 296,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #296 = XOR16mm
714
  { 297,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #297 = XOR16mr
715
  { 298,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #298 = XOR16ri
716
  { 299,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #299 = XOR16rm
717
  { 300,  4,  2,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #300 = XOR16rm_POST
718
  { 301,  3,  1,  0,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #301 = XOR16rr
719
  { 302,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #302 = XOR8mi
720
  { 303,  4,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x12ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #303 = XOR8mm
721
  { 304,  3,  0,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #304 = XOR8mr
722
  { 305,  3,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #305 = XOR8ri
723
  { 306,  4,  1,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xeULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #306 = XOR8rm
724
  { 307,  4,  2,  0,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #307 = XOR8rm_POST
725
  { 308,  3,  1,  0,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #308 = XOR8rr
726
  { 309,  2,  1,  0,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xaULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #309 = ZEXT16r
727
};
728
729
extern const char MSP430InstrNameData[] = {
730
  /* 0 */ 'S', 'H', 'L', '1', '6', 'r', '1', 0,
731
  /* 8 */ 'S', 'A', 'R', '1', '6', 'r', '1', 0,
732
  /* 16 */ 'S', 'H', 'L', '8', 'r', '1', 0,
733
  /* 23 */ 'S', 'A', 'R', '8', 'r', '1', 0,
734
  /* 30 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0,
735
  /* 38 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0,
736
  /* 46 */ 'S', 'r', 'a', '1', '6', 0,
737
  /* 52 */ 'S', 'h', 'l', '1', '6', 0,
738
  /* 58 */ 'S', 'r', 'l', '1', '6', 0,
739
  /* 64 */ 'S', 'e', 'l', 'e', 'c', 't', '1', '6', 0,
740
  /* 73 */ 'S', 'r', 'a', '8', 0,
741
  /* 78 */ 'S', 'h', 'l', '8', 0,
742
  /* 83 */ 'S', 'r', 'l', '8', 0,
743
  /* 88 */ 'M', 'O', 'V', 'Z', 'X', '1', '6', 'r', 'm', '8', 0,
744
  /* 99 */ 'M', 'O', 'V', 'Z', 'X', '1', '6', 'r', 'r', '8', 0,
745
  /* 110 */ 'S', 'e', 'l', 'e', 'c', 't', '8', 0,
746
  /* 118 */ 'G', '_', 'F', 'M', 'A', 0,
747
  /* 124 */ 'G', '_', 'F', 'S', 'U', 'B', 0,
748
  /* 131 */ 'G', '_', 'S', 'U', 'B', 0,
749
  /* 137 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'S', 'U', 'B', 0,
750
  /* 153 */ 'J', 'C', 'C', 0,
751
  /* 157 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', 0,
752
  /* 169 */ 'G', '_', 'F', 'P', 'T', 'R', 'U', 'N', 'C', 0,
753
  /* 179 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'T', 'R', 'U', 'N', 'C', 0,
754
  /* 197 */ 'G', '_', 'T', 'R', 'U', 'N', 'C', 0,
755
  /* 205 */ 'G', '_', 'S', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
756
  /* 216 */ 'G', '_', 'Z', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
757
  /* 227 */ 'G', '_', 'L', 'O', 'A', 'D', 0,
758
  /* 234 */ 'G', '_', 'F', 'A', 'D', 'D', 0,
759
  /* 241 */ 'G', '_', 'A', 'D', 'D', 0,
760
  /* 247 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'D', 'D', 0,
761
  /* 263 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'N', 'A', 'N', 'D', 0,
762
  /* 280 */ 'G', '_', 'A', 'N', 'D', 0,
763
  /* 286 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'N', 'D', 0,
764
  /* 302 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
765
  /* 315 */ 'G', '_', 'B', 'R', 'C', 'O', 'N', 'D', 0,
766
  /* 324 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'R', 'O', 'U', 'N', 'D', 0,
767
  /* 342 */ 'L', 'O', 'A', 'D', '_', 'S', 'T', 'A', 'C', 'K', '_', 'G', 'U', 'A', 'R', 'D', 0,
768
  /* 359 */ 'G', '_', 'S', 'S', 'U', 'B', 'E', 0,
769
  /* 367 */ 'G', '_', 'U', 'S', 'U', 'B', 'E', 0,
770
  /* 375 */ 'R', 'E', 'G', '_', 'S', 'E', 'Q', 'U', 'E', 'N', 'C', 'E', 0,
771
  /* 388 */ 'G', '_', 'S', 'A', 'D', 'D', 'E', 0,
772
  /* 396 */ 'G', '_', 'U', 'A', 'D', 'D', 'E', 0,
773
  /* 404 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
774
  /* 411 */ 'L', 'O', 'C', 'A', 'L', '_', 'E', 'S', 'C', 'A', 'P', 'E', 0,
775
  /* 424 */ 'G', '_', 'S', 'T', 'O', 'R', 'E', 0,
776
  /* 432 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
777
  /* 442 */ 'G', '_', 'G', 'L', 'O', 'B', 'A', 'L', '_', 'V', 'A', 'L', 'U', 'E', 0,
778
  /* 457 */ 'G', '_', 'C', 'T', 'L', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
779
  /* 475 */ 'G', '_', 'C', 'T', 'T', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
780
  /* 493 */ 'G', '_', 'I', 'M', 'P', 'L', 'I', 'C', 'I', 'T', '_', 'D', 'E', 'F', 0,
781
  /* 508 */ 'G', '_', 'F', 'N', 'E', 'G', 0,
782
  /* 515 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
783
  /* 530 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
784
  /* 544 */ 'S', 'U', 'B', 'R', 'E', 'G', '_', 'T', 'O', '_', 'R', 'E', 'G', 0,
785
  /* 558 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', 0,
786
  /* 575 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'C', 'H', 'G', 0,
787
  /* 592 */ 'G', '_', 'F', 'L', 'O', 'G', 0,
788
  /* 599 */ 'G', '_', 'V', 'A', 'A', 'R', 'G', 0,
789
  /* 607 */ 'G', '_', 'S', 'M', 'U', 'L', 'H', 0,
790
  /* 615 */ 'G', '_', 'U', 'M', 'U', 'L', 'H', 0,
791
  /* 623 */ 'G', '_', 'P', 'H', 'I', 0,
792
  /* 629 */ 'G', '_', 'F', 'P', 'T', 'O', 'S', 'I', 0,
793
  /* 638 */ 'R', 'E', 'T', 'I', 0,
794
  /* 643 */ 'G', '_', 'F', 'P', 'T', 'O', 'U', 'I', 0,
795
  /* 652 */ 'G', '_', 'P', 'T', 'R', '_', 'M', 'A', 'S', 'K', 0,
796
  /* 663 */ 'G', 'C', '_', 'L', 'A', 'B', 'E', 'L', 0,
797
  /* 672 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0,
798
  /* 682 */ 'E', 'H', '_', 'L', 'A', 'B', 'E', 'L', 0,
799
  /* 691 */ 'A', 'N', 'N', 'O', 'T', 'A', 'T', 'I', 'O', 'N', '_', 'L', 'A', 'B', 'E', 'L', 0,
800
  /* 708 */ 'I', 'C', 'A', 'L', 'L', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'F', 'U', 'N', 'N', 'E', 'L', 0,
801
  /* 728 */ 'G', '_', 'S', 'H', 'L', 0,
802
  /* 734 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'A', 'I', 'L', '_', 'C', 'A', 'L', 'L', 0,
803
  /* 754 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
804
  /* 781 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
805
  /* 802 */ 'F', 'E', 'N', 'T', 'R', 'Y', '_', 'C', 'A', 'L', 'L', 0,
806
  /* 814 */ 'K', 'I', 'L', 'L', 0,
807
  /* 819 */ 'G', '_', 'F', 'M', 'U', 'L', 0,
808
  /* 826 */ 'G', '_', 'M', 'U', 'L', 0,
809
  /* 832 */ 'G', '_', 'F', 'R', 'E', 'M', 0,
810
  /* 839 */ 'G', '_', 'S', 'R', 'E', 'M', 0,
811
  /* 846 */ 'G', '_', 'U', 'R', 'E', 'M', 0,
812
  /* 853 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', 0,
813
  /* 863 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'I', 'N', 0,
814
  /* 880 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'I', 'N', 0,
815
  /* 896 */ 'C', 'F', 'I', '_', 'I', 'N', 'S', 'T', 'R', 'U', 'C', 'T', 'I', 'O', 'N', 0,
816
  /* 912 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 0,
817
  /* 929 */ 'G', '_', 'S', 'S', 'U', 'B', 'O', 0,
818
  /* 937 */ 'G', '_', 'U', 'S', 'U', 'B', 'O', 0,
819
  /* 945 */ 'G', '_', 'S', 'A', 'D', 'D', 'O', 0,
820
  /* 953 */ 'G', '_', 'U', 'A', 'D', 'D', 'O', 0,
821
  /* 961 */ 'G', '_', 'S', 'M', 'U', 'L', 'O', 0,
822
  /* 969 */ 'G', '_', 'U', 'M', 'U', 'L', 'O', 0,
823
  /* 977 */ 'S', 'T', 'A', 'C', 'K', 'M', 'A', 'P', 0,
824
  /* 986 */ 'G', '_', 'B', 'S', 'W', 'A', 'P', 0,
825
  /* 994 */ 'G', '_', 'G', 'E', 'P', 0,
826
  /* 1000 */ 'G', '_', 'S', 'I', 'T', 'O', 'F', 'P', 0,
827
  /* 1009 */ 'G', '_', 'U', 'I', 'T', 'O', 'F', 'P', 0,
828
  /* 1018 */ 'G', '_', 'F', 'C', 'M', 'P', 0,
829
  /* 1025 */ 'G', '_', 'I', 'C', 'M', 'P', 0,
830
  /* 1032 */ 'J', 'M', 'P', 0,
831
  /* 1036 */ 'N', 'O', 'P', 0,
832
  /* 1040 */ 'G', '_', 'C', 'T', 'P', 'O', 'P', 0,
833
  /* 1048 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'O', 'P', 0,
834
  /* 1061 */ 'F', 'A', 'U', 'L', 'T', 'I', 'N', 'G', '_', 'O', 'P', 0,
835
  /* 1073 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 0,
836
  /* 1088 */ 'G', '_', 'F', 'E', 'X', 'P', 0,
837
  /* 1095 */ 'G', '_', 'B', 'R', 0,
838
  /* 1100 */ 'G', '_', 'B', 'L', 'O', 'C', 'K', '_', 'A', 'D', 'D', 'R', 0,
839
  /* 1113 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'N', 'T', 'E', 'R', 0,
840
  /* 1138 */ 'G', '_', 'A', 'S', 'H', 'R', 0,
841
  /* 1145 */ 'G', '_', 'L', 'S', 'H', 'R', 0,
842
  /* 1152 */ 'G', '_', 'S', 'H', 'U', 'F', 'F', 'L', 'E', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
843
  /* 1169 */ 'G', '_', 'X', 'O', 'R', 0,
844
  /* 1175 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'O', 'R', 0,
845
  /* 1191 */ 'G', '_', 'O', 'R', 0,
846
  /* 1196 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'O', 'R', 0,
847
  /* 1211 */ 'G', '_', 'I', 'N', 'T', 'T', 'O', 'P', 'T', 'R', 0,
848
  /* 1222 */ 'G', '_', 'F', 'A', 'B', 'S', 0,
849
  /* 1229 */ 'G', '_', 'U', 'N', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
850
  /* 1246 */ 'G', '_', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
851
  /* 1261 */ 'C', 'O', 'P', 'Y', '_', 'T', 'O', '_', 'R', 'E', 'G', 'C', 'L', 'A', 'S', 'S', 0,
852
  /* 1278 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'W', 'I', 'T', 'H', '_', 'S', 'U', 'C', 'C', 'E', 'S', 'S', 0,
853
  /* 1308 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'W', '_', 'S', 'I', 'D', 'E', '_', 'E', 'F', 'F', 'E', 'C', 'T', 'S', 0,
854
  /* 1335 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', 0,
855
  /* 1345 */ 'G', '_', 'S', 'E', 'L', 'E', 'C', 'T', 0,
856
  /* 1354 */ 'G', '_', 'B', 'R', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', 0,
857
  /* 1367 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'R', 'E', 'T', 0,
858
  /* 1381 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'X', 'I', 'T', 0,
859
  /* 1405 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
860
  /* 1426 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
861
  /* 1446 */ 'G', '_', 'F', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
862
  /* 1458 */ 'G', '_', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
863
  /* 1469 */ 'S', 'T', 'A', 'T', 'E', 'P', 'O', 'I', 'N', 'T', 0,
864
  /* 1480 */ 'P', 'A', 'T', 'C', 'H', 'P', 'O', 'I', 'N', 'T', 0,
865
  /* 1491 */ 'G', '_', 'P', 'T', 'R', 'T', 'O', 'I', 'N', 'T', 0,
866
  /* 1502 */ 'G', '_', 'V', 'A', 'S', 'T', 'A', 'R', 'T', 0,
867
  /* 1512 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
868
  /* 1527 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', 0,
869
  /* 1536 */ 'G', '_', 'B', 'I', 'T', 'C', 'A', 'S', 'T', 0,
870
  /* 1546 */ 'G', '_', 'A', 'D', 'D', 'R', 'S', 'P', 'A', 'C', 'E', '_', 'C', 'A', 'S', 'T', 0,
871
  /* 1563 */ 'S', 'U', 'B', '1', '6', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
872
  /* 1576 */ 'A', 'D', 'D', '1', '6', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
873
  /* 1589 */ 'A', 'N', 'D', '1', '6', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
874
  /* 1602 */ 'X', 'O', 'R', '1', '6', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
875
  /* 1615 */ 'M', 'O', 'V', '1', '6', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
876
  /* 1628 */ 'S', 'U', 'B', '8', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
877
  /* 1640 */ 'A', 'D', 'D', '8', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
878
  /* 1652 */ 'A', 'N', 'D', '8', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
879
  /* 1664 */ 'X', 'O', 'R', '8', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
880
  /* 1676 */ 'M', 'O', 'V', '8', 'r', 'm', '_', 'P', 'O', 'S', 'T', 0,
881
  /* 1688 */ 'G', '_', 'F', 'P', 'E', 'X', 'T', 0,
882
  /* 1696 */ 'G', '_', 'S', 'E', 'X', 'T', 0,
883
  /* 1703 */ 'G', '_', 'A', 'N', 'Y', 'E', 'X', 'T', 0,
884
  /* 1712 */ 'G', '_', 'Z', 'E', 'X', 'T', 0,
885
  /* 1719 */ 'G', '_', 'F', 'D', 'I', 'V', 0,
886
  /* 1726 */ 'G', '_', 'S', 'D', 'I', 'V', 0,
887
  /* 1733 */ 'G', '_', 'U', 'D', 'I', 'V', 0,
888
  /* 1740 */ 'G', '_', 'F', 'P', 'O', 'W', 0,
889
  /* 1747 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'A', 'X', 0,
890
  /* 1764 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'A', 'X', 0,
891
  /* 1780 */ 'G', '_', 'F', 'R', 'A', 'M', 'E', '_', 'I', 'N', 'D', 'E', 'X', 0,
892
  /* 1794 */ 'C', 'O', 'P', 'Y', 0,
893
  /* 1799 */ 'G', '_', 'C', 'T', 'L', 'Z', 0,
894
  /* 1806 */ 'G', '_', 'C', 'T', 'T', 'Z', 0,
895
  /* 1813 */ 'S', 'A', 'R', '1', '6', 'r', '1', 'c', 0,
896
  /* 1822 */ 'S', 'A', 'R', '8', 'r', '1', 'c', 0,
897
  /* 1830 */ 'A', 'D', 'D', 'f', 'r', 'a', 'm', 'e', 0,
898
  /* 1839 */ 'B', 'i', 0,
899
  /* 1842 */ 'C', 'A', 'L', 'L', 'i', 0,
900
  /* 1848 */ 'S', 'U', 'B', '1', '6', 'm', 'i', 0,
901
  /* 1856 */ 'S', 'B', 'C', '1', '6', 'm', 'i', 0,
902
  /* 1864 */ 'A', 'D', 'C', '1', '6', 'm', 'i', 0,
903
  /* 1872 */ 'A', 'D', 'D', '1', '6', 'm', 'i', 0,
904
  /* 1880 */ 'A', 'N', 'D', '1', '6', 'm', 'i', 0,
905
  /* 1888 */ 'C', 'M', 'P', '1', '6', 'm', 'i', 0,
906
  /* 1896 */ 'X', 'O', 'R', '1', '6', 'm', 'i', 0,
907
  /* 1904 */ 'B', 'I', 'T', '1', '6', 'm', 'i', 0,
908
  /* 1912 */ 'M', 'O', 'V', '1', '6', 'm', 'i', 0,
909
  /* 1920 */ 'S', 'U', 'B', '8', 'm', 'i', 0,
910
  /* 1927 */ 'S', 'B', 'C', '8', 'm', 'i', 0,
911
  /* 1934 */ 'A', 'D', 'C', '8', 'm', 'i', 0,
912
  /* 1941 */ 'A', 'D', 'D', '8', 'm', 'i', 0,
913
  /* 1948 */ 'A', 'N', 'D', '8', 'm', 'i', 0,
914
  /* 1955 */ 'C', 'M', 'P', '8', 'm', 'i', 0,
915
  /* 1962 */ 'X', 'O', 'R', '8', 'm', 'i', 0,
916
  /* 1969 */ 'B', 'I', 'T', '8', 'm', 'i', 0,
917
  /* 1976 */ 'M', 'O', 'V', '8', 'm', 'i', 0,
918
  /* 1983 */ 'S', 'U', 'B', '1', '6', 'r', 'i', 0,
919
  /* 1991 */ 'S', 'B', 'C', '1', '6', 'r', 'i', 0,
920
  /* 1999 */ 'A', 'D', 'C', '1', '6', 'r', 'i', 0,
921
  /* 2007 */ 'A', 'D', 'D', '1', '6', 'r', 'i', 0,
922
  /* 2015 */ 'A', 'N', 'D', '1', '6', 'r', 'i', 0,
923
  /* 2023 */ 'C', 'M', 'P', '1', '6', 'r', 'i', 0,
924
  /* 2031 */ 'X', 'O', 'R', '1', '6', 'r', 'i', 0,
925
  /* 2039 */ 'B', 'I', 'T', '1', '6', 'r', 'i', 0,
926
  /* 2047 */ 'M', 'O', 'V', '1', '6', 'r', 'i', 0,
927
  /* 2055 */ 'S', 'U', 'B', '8', 'r', 'i', 0,
928
  /* 2062 */ 'S', 'B', 'C', '8', 'r', 'i', 0,
929
  /* 2069 */ 'A', 'D', 'C', '8', 'r', 'i', 0,
930
  /* 2076 */ 'A', 'D', 'D', '8', 'r', 'i', 0,
931
  /* 2083 */ 'A', 'N', 'D', '8', 'r', 'i', 0,
932
  /* 2090 */ 'C', 'M', 'P', '8', 'r', 'i', 0,
933
  /* 2097 */ 'X', 'O', 'R', '8', 'r', 'i', 0,
934
  /* 2104 */ 'B', 'I', 'T', '8', 'r', 'i', 0,
935
  /* 2111 */ 'M', 'O', 'V', '8', 'r', 'i', 0,
936
  /* 2118 */ 'B', 'm', 0,
937
  /* 2121 */ 'C', 'A', 'L', 'L', 'm', 0,
938
  /* 2127 */ 'S', 'U', 'B', '1', '6', 'm', 'm', 0,
939
  /* 2135 */ 'S', 'B', 'C', '1', '6', 'm', 'm', 0,
940
  /* 2143 */ 'A', 'D', 'C', '1', '6', 'm', 'm', 0,
941
  /* 2151 */ 'B', 'I', 'C', '1', '6', 'm', 'm', 0,
942
  /* 2159 */ 'A', 'D', 'D', '1', '6', 'm', 'm', 0,
943
  /* 2167 */ 'A', 'N', 'D', '1', '6', 'm', 'm', 0,
944
  /* 2175 */ 'X', 'O', 'R', '1', '6', 'm', 'm', 0,
945
  /* 2183 */ 'B', 'I', 'T', '1', '6', 'm', 'm', 0,
946
  /* 2191 */ 'M', 'O', 'V', '1', '6', 'm', 'm', 0,
947
  /* 2199 */ 'S', 'U', 'B', '8', 'm', 'm', 0,
948
  /* 2206 */ 'S', 'B', 'C', '8', 'm', 'm', 0,
949
  /* 2213 */ 'A', 'D', 'C', '8', 'm', 'm', 0,
950
  /* 2220 */ 'B', 'I', 'C', '8', 'm', 'm', 0,
951
  /* 2227 */ 'A', 'D', 'D', '8', 'm', 'm', 0,
952
  /* 2234 */ 'A', 'N', 'D', '8', 'm', 'm', 0,
953
  /* 2241 */ 'X', 'O', 'R', '8', 'm', 'm', 0,
954
  /* 2248 */ 'B', 'I', 'T', '8', 'm', 'm', 0,
955
  /* 2255 */ 'M', 'O', 'V', '8', 'm', 'm', 0,
956
  /* 2262 */ 'S', 'U', 'B', '1', '6', 'r', 'm', 0,
957
  /* 2270 */ 'S', 'B', 'C', '1', '6', 'r', 'm', 0,
958
  /* 2278 */ 'A', 'D', 'C', '1', '6', 'r', 'm', 0,
959
  /* 2286 */ 'B', 'I', 'C', '1', '6', 'r', 'm', 0,
960
  /* 2294 */ 'A', 'D', 'D', '1', '6', 'r', 'm', 0,
961
  /* 2302 */ 'A', 'N', 'D', '1', '6', 'r', 'm', 0,
962
  /* 2310 */ 'C', 'M', 'P', '1', '6', 'r', 'm', 0,
963
  /* 2318 */ 'X', 'O', 'R', '1', '6', 'r', 'm', 0,
964
  /* 2326 */ 'B', 'I', 'T', '1', '6', 'r', 'm', 0,
965
  /* 2334 */ 'M', 'O', 'V', '1', '6', 'r', 'm', 0,
966
  /* 2342 */ 'S', 'U', 'B', '8', 'r', 'm', 0,
967
  /* 2349 */ 'S', 'B', 'C', '8', 'r', 'm', 0,
968
  /* 2356 */ 'A', 'D', 'C', '8', 'r', 'm', 0,
969
  /* 2363 */ 'B', 'I', 'C', '8', 'r', 'm', 0,
970
  /* 2370 */ 'A', 'D', 'D', '8', 'r', 'm', 0,
971
  /* 2377 */ 'A', 'N', 'D', '8', 'r', 'm', 0,
972
  /* 2384 */ 'C', 'M', 'P', '8', 'r', 'm', 0,
973
  /* 2391 */ 'X', 'O', 'R', '8', 'r', 'm', 0,
974
  /* 2398 */ 'B', 'I', 'T', '8', 'r', 'm', 0,
975
  /* 2405 */ 'M', 'O', 'V', '8', 'r', 'm', 0,
976
  /* 2412 */ 'S', 'W', 'P', 'B', '1', '6', 'r', 0,
977
  /* 2420 */ 'P', 'U', 'S', 'H', '1', '6', 'r', 0,
978
  /* 2428 */ 'P', 'O', 'P', '1', '6', 'r', 0,
979
  /* 2435 */ 'S', 'E', 'X', 'T', '1', '6', 'r', 0,
980
  /* 2443 */ 'Z', 'E', 'X', 'T', '1', '6', 'r', 0,
981
  /* 2451 */ 'B', 'r', 0,
982
  /* 2454 */ 'C', 'A', 'L', 'L', 'r', 0,
983
  /* 2460 */ 'S', 'U', 'B', '1', '6', 'm', 'r', 0,
984
  /* 2468 */ 'S', 'B', 'C', '1', '6', 'm', 'r', 0,
985
  /* 2476 */ 'A', 'D', 'C', '1', '6', 'm', 'r', 0,
986
  /* 2484 */ 'B', 'I', 'C', '1', '6', 'm', 'r', 0,
987
  /* 2492 */ 'A', 'D', 'D', '1', '6', 'm', 'r', 0,
988
  /* 2500 */ 'A', 'N', 'D', '1', '6', 'm', 'r', 0,
989
  /* 2508 */ 'C', 'M', 'P', '1', '6', 'm', 'r', 0,
990
  /* 2516 */ 'X', 'O', 'R', '1', '6', 'm', 'r', 0,
991
  /* 2524 */ 'B', 'I', 'T', '1', '6', 'm', 'r', 0,
992
  /* 2532 */ 'M', 'O', 'V', '1', '6', 'm', 'r', 0,
993
  /* 2540 */ 'S', 'U', 'B', '8', 'm', 'r', 0,
994
  /* 2547 */ 'S', 'B', 'C', '8', 'm', 'r', 0,
995
  /* 2554 */ 'A', 'D', 'C', '8', 'm', 'r', 0,
996
  /* 2561 */ 'B', 'I', 'C', '8', 'm', 'r', 0,
997
  /* 2568 */ 'A', 'D', 'D', '8', 'm', 'r', 0,
998
  /* 2575 */ 'A', 'N', 'D', '8', 'm', 'r', 0,
999
  /* 2582 */ 'C', 'M', 'P', '8', 'm', 'r', 0,
1000
  /* 2589 */ 'X', 'O', 'R', '8', 'm', 'r', 0,
1001
  /* 2596 */ 'B', 'I', 'T', '8', 'm', 'r', 0,
1002
  /* 2603 */ 'M', 'O', 'V', '8', 'm', 'r', 0,
1003
  /* 2610 */ 'S', 'U', 'B', '1', '6', 'r', 'r', 0,
1004
  /* 2618 */ 'S', 'B', 'C', '1', '6', 'r', 'r', 0,
1005
  /* 2626 */ 'A', 'D', 'C', '1', '6', 'r', 'r', 0,
1006
  /* 2634 */ 'B', 'I', 'C', '1', '6', 'r', 'r', 0,
1007
  /* 2642 */ 'A', 'D', 'D', '1', '6', 'r', 'r', 0,
1008
  /* 2650 */ 'A', 'N', 'D', '1', '6', 'r', 'r', 0,
1009
  /* 2658 */ 'C', 'M', 'P', '1', '6', 'r', 'r', 0,
1010
  /* 2666 */ 'X', 'O', 'R', '1', '6', 'r', 'r', 0,
1011
  /* 2674 */ 'B', 'I', 'T', '1', '6', 'r', 'r', 0,
1012
  /* 2682 */ 'M', 'O', 'V', '1', '6', 'r', 'r', 0,
1013
  /* 2690 */ 'S', 'U', 'B', '8', 'r', 'r', 0,
1014
  /* 2697 */ 'S', 'B', 'C', '8', 'r', 'r', 0,
1015
  /* 2704 */ 'A', 'D', 'C', '8', 'r', 'r', 0,
1016
  /* 2711 */ 'B', 'I', 'C', '8', 'r', 'r', 0,
1017
  /* 2718 */ 'A', 'D', 'D', '8', 'r', 'r', 0,
1018
  /* 2725 */ 'A', 'N', 'D', '8', 'r', 'r', 0,
1019
  /* 2732 */ 'C', 'M', 'P', '8', 'r', 'r', 0,
1020
  /* 2739 */ 'X', 'O', 'R', '8', 'r', 'r', 0,
1021
  /* 2746 */ 'B', 'I', 'T', '8', 'r', 'r', 0,
1022
  /* 2753 */ 'M', 'O', 'V', '8', 'r', 'r', 0,
1023
};
1024
1025
extern const unsigned MSP430InstrNameIndices[] = {
1026
    625U, 853U, 896U, 682U, 663U, 691U, 814U, 515U, 
1027
    530U, 495U, 544U, 1261U, 432U, 672U, 375U, 1794U, 
1028
    404U, 1512U, 302U, 977U, 802U, 1480U, 342U, 1469U, 
1029
    411U, 1061U, 1048U, 1113U, 1367U, 1381U, 734U, 781U, 
1030
    754U, 708U, 241U, 131U, 826U, 1726U, 1733U, 839U, 
1031
    846U, 280U, 1191U, 1169U, 493U, 623U, 1780U, 442U, 
1032
    1335U, 1229U, 1527U, 1246U, 1491U, 1211U, 1536U, 179U, 
1033
    324U, 227U, 205U, 216U, 424U, 1278U, 558U, 575U, 
1034
    247U, 137U, 286U, 263U, 1196U, 1175U, 1764U, 880U, 
1035
    1747U, 863U, 315U, 1354U, 157U, 1308U, 1703U, 197U, 
1036
    1458U, 1446U, 1502U, 599U, 1696U, 1712U, 728U, 1145U, 
1037
    1138U, 1025U, 1018U, 1345U, 953U, 396U, 937U, 367U, 
1038
    945U, 388U, 929U, 359U, 969U, 961U, 615U, 607U, 
1039
    234U, 124U, 819U, 118U, 1719U, 832U, 1740U, 1088U, 
1040
    38U, 592U, 30U, 508U, 1688U, 169U, 629U, 643U, 
1041
    1000U, 1009U, 1222U, 994U, 652U, 1095U, 1426U, 1405U, 
1042
    1152U, 1806U, 475U, 1799U, 457U, 1040U, 986U, 1546U, 
1043
    1100U, 1864U, 2143U, 2476U, 1999U, 2278U, 2626U, 1934U, 
1044
    2213U, 2554U, 2069U, 2356U, 2704U, 1872U, 2159U, 2492U, 
1045
    2007U, 2294U, 1576U, 2642U, 1941U, 2227U, 2568U, 2076U, 
1046
    2370U, 1640U, 2718U, 1830U, 912U, 1073U, 1880U, 2167U, 
1047
    2500U, 2015U, 2302U, 1589U, 2650U, 1948U, 2234U, 2575U, 
1048
    2083U, 2377U, 1652U, 2725U, 2151U, 2484U, 2286U, 2634U, 
1049
    2220U, 2561U, 2363U, 2711U, 1904U, 2183U, 2524U, 2039U, 
1050
    2326U, 2674U, 1969U, 2248U, 2596U, 2104U, 2398U, 2746U, 
1051
    1839U, 2118U, 2451U, 1842U, 2121U, 2454U, 1888U, 2508U, 
1052
    2023U, 2310U, 2658U, 1955U, 2582U, 2090U, 2384U, 2732U, 
1053
    153U, 1032U, 1912U, 2191U, 2532U, 2047U, 2334U, 1615U, 
1054
    2682U, 1976U, 2255U, 2603U, 2111U, 2405U, 1676U, 2753U, 
1055
    88U, 99U, 1036U, 1897U, 2176U, 2517U, 2032U, 2319U, 
1056
    1603U, 2667U, 1963U, 2242U, 2590U, 2098U, 2392U, 1665U, 
1057
    2740U, 2428U, 2420U, 1377U, 638U, 8U, 1813U, 23U, 
1058
    1822U, 1856U, 2135U, 2468U, 1991U, 2270U, 2618U, 1927U, 
1059
    2206U, 2547U, 2062U, 2349U, 2697U, 2435U, 0U, 16U, 
1060
    1848U, 2127U, 2460U, 1983U, 2262U, 1563U, 2610U, 1920U, 
1061
    2199U, 2540U, 2055U, 2342U, 1628U, 2690U, 2412U, 64U, 
1062
    110U, 52U, 78U, 46U, 73U, 58U, 83U, 1896U, 
1063
    2175U, 2516U, 2031U, 2318U, 1602U, 2666U, 1962U, 2241U, 
1064
    2589U, 2097U, 2391U, 1664U, 2739U, 2443U, 
1065
};
1066
1067
0
static inline void InitMSP430MCInstrInfo(MCInstrInfo *II) {
1068
0
  II->InitMCInstrInfo(MSP430Insts, MSP430InstrNameIndices, MSP430InstrNameData, 310);
1069
0
}
1070
1071
} // end llvm namespace
1072
#endif // GET_INSTRINFO_MC_DESC
1073
1074
#ifdef GET_INSTRINFO_HEADER
1075
#undef GET_INSTRINFO_HEADER
1076
namespace llvm {
1077
struct MSP430GenInstrInfo : public TargetInstrInfo {
1078
  explicit MSP430GenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);
1079
0
  ~MSP430GenInstrInfo() override = default;
1080
1081
};
1082
} // end llvm namespace
1083
#endif // GET_INSTRINFO_HEADER
1084
1085
#ifdef GET_INSTRINFO_CTOR_DTOR
1086
#undef GET_INSTRINFO_CTOR_DTOR
1087
namespace llvm {
1088
extern const MCInstrDesc MSP430Insts[];
1089
extern const unsigned MSP430InstrNameIndices[];
1090
extern const char MSP430InstrNameData[];
1091
MSP430GenInstrInfo::MSP430GenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)
1092
0
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1093
0
  InitMCInstrInfo(MSP430Insts, MSP430InstrNameIndices, MSP430InstrNameData, 310);
1094
0
}
1095
} // end llvm namespace
1096
#endif // GET_INSTRINFO_CTOR_DTOR
1097
1098
#ifdef GET_INSTRINFO_OPERAND_ENUM
1099
#undef GET_INSTRINFO_OPERAND_ENUM
1100
namespace llvm {
1101
namespace MSP430 {
1102
namespace OpName {
1103
enum {
1104
OPERAND_LAST
1105
};
1106
} // end namespace OpName
1107
} // end namespace MSP430
1108
} // end namespace llvm
1109
#endif //GET_INSTRINFO_OPERAND_ENUM
1110
1111
#ifdef GET_INSTRINFO_NAMED_OPS
1112
#undef GET_INSTRINFO_NAMED_OPS
1113
namespace llvm {
1114
namespace MSP430 {
1115
LLVM_READONLY
1116
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
1117
  return -1;
1118
}
1119
} // end namespace MSP430
1120
} // end namespace llvm
1121
#endif //GET_INSTRINFO_NAMED_OPS
1122
1123
#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
1124
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
1125
namespace llvm {
1126
namespace MSP430 {
1127
namespace OpTypes {
1128
enum OperandType {
1129
  cc = 0,
1130
  f32imm = 1,
1131
  f64imm = 2,
1132
  i16imm = 3,
1133
  i1imm = 4,
1134
  i32imm = 5,
1135
  i64imm = 6,
1136
  i8imm = 7,
1137
  jmptarget = 8,
1138
  memdst = 9,
1139
  memsrc = 10,
1140
  ptype0 = 11,
1141
  ptype1 = 12,
1142
  ptype2 = 13,
1143
  ptype3 = 14,
1144
  ptype4 = 15,
1145
  ptype5 = 16,
1146
  type0 = 17,
1147
  type1 = 18,
1148
  type2 = 19,
1149
  type3 = 20,
1150
  type4 = 21,
1151
  type5 = 22,
1152
  OPERAND_TYPE_LIST_END
1153
};
1154
} // end namespace OpTypes
1155
} // end namespace MSP430
1156
} // end namespace llvm
1157
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
1158