Coverage Report

Created: 2018-07-19 03:59

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/MSP430/MSP430GenRegisterInfo.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
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|* Target Register Enum Values                                                *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
8
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#ifdef GET_REGINFO_ENUM
11
#undef GET_REGINFO_ENUM
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13
namespace llvm {
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class MCRegisterClass;
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extern const MCRegisterClass MSP430MCRegisterClasses[];
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namespace MSP430 {
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enum {
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  NoRegister,
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  CG = 1,
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  CGB = 2,
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  FP = 3,
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  FPB = 4,
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  PC = 5,
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  PCB = 6,
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  SP = 7,
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  SPB = 8,
29
  SR = 9,
30
  SRB = 10,
31
  R5 = 11,
32
  R6 = 12,
33
  R7 = 13,
34
  R8 = 14,
35
  R9 = 15,
36
  R10 = 16,
37
  R11 = 17,
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  R12 = 18,
39
  R13 = 19,
40
  R14 = 20,
41
  R15 = 21,
42
  R5B = 22,
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  R6B = 23,
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  R7B = 24,
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  R8B = 25,
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  R9B = 26,
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  R10B = 27,
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  R11B = 28,
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  R12B = 29,
50
  R13B = 30,
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  R14B = 31,
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  R15B = 32,
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  NUM_TARGET_REGS   // 33
54
};
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} // end namespace MSP430
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// Register classes
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namespace MSP430 {
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enum {
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  GR8RegClassID = 0,
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  GR16RegClassID = 1,
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64
  };
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} // end namespace MSP430
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// Subregister indices
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namespace MSP430 {
71
enum {
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  NoSubRegister,
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  subreg_8bit,  // 1
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  NUM_TARGET_SUBREGS
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};
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} // end namespace MSP430
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} // end namespace llvm
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#endif // GET_REGINFO_ENUM
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
83
|*                                                                            *|
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|* MC Register Information                                                    *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_REGINFO_MC_DESC
92
#undef GET_REGINFO_MC_DESC
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namespace llvm {
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extern const MCPhysReg MSP430RegDiffLists[] = {
97
  /* 0 */ 0, 0,
98
  /* 2 */ 1, 0,
99
  /* 4 */ 2, 0,
100
  /* 6 */ 3, 0,
101
  /* 8 */ 4, 0,
102
  /* 10 */ 11, 0,
103
  /* 12 */ 65519, 0,
104
  /* 14 */ 65525, 0,
105
  /* 16 */ 65530, 0,
106
  /* 18 */ 65535, 0,
107
};
108
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extern const LaneBitmask MSP430LaneMaskLists[] = {
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  /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
111
  /* 2 */ LaneBitmask(0x00000001), LaneBitmask::getAll(),
112
};
113
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extern const uint16_t MSP430SubRegIdxLists[] = {
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  /* 0 */ 1, 0,
116
};
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118
extern const MCRegisterInfo::SubRegCoveredBits MSP430SubRegIdxRanges[] = {
119
  { 65535, 65535 },
120
  { 0, 8 }, // subreg_8bit
121
};
122
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extern const char MSP430RegStrings[] = {
124
  /* 0 */ 'R', '1', '0', 0,
125
  /* 4 */ 'R', '1', '1', 0,
126
  /* 8 */ 'R', '1', '2', 0,
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  /* 12 */ 'R', '1', '3', 0,
128
  /* 16 */ 'R', '1', '4', 0,
129
  /* 20 */ 'R', '1', '5', 0,
130
  /* 24 */ 'R', '5', 0,
131
  /* 27 */ 'R', '6', 0,
132
  /* 30 */ 'R', '7', 0,
133
  /* 33 */ 'R', '8', 0,
134
  /* 36 */ 'R', '9', 0,
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  /* 39 */ 'R', '1', '0', 'B', 0,
136
  /* 44 */ 'R', '1', '1', 'B', 0,
137
  /* 49 */ 'R', '1', '2', 'B', 0,
138
  /* 54 */ 'R', '1', '3', 'B', 0,
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  /* 59 */ 'R', '1', '4', 'B', 0,
140
  /* 64 */ 'R', '1', '5', 'B', 0,
141
  /* 69 */ 'R', '5', 'B', 0,
142
  /* 73 */ 'R', '6', 'B', 0,
143
  /* 77 */ 'R', '7', 'B', 0,
144
  /* 81 */ 'R', '8', 'B', 0,
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  /* 85 */ 'R', '9', 'B', 0,
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  /* 89 */ 'P', 'C', 'B', 0,
147
  /* 93 */ 'C', 'G', 'B', 0,
148
  /* 97 */ 'F', 'P', 'B', 0,
149
  /* 101 */ 'S', 'P', 'B', 0,
150
  /* 105 */ 'S', 'R', 'B', 0,
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  /* 109 */ 'P', 'C', 0,
152
  /* 112 */ 'C', 'G', 0,
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  /* 115 */ 'F', 'P', 0,
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  /* 118 */ 'S', 'P', 0,
155
  /* 121 */ 'S', 'R', 0,
156
};
157
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extern const MCRegisterDesc MSP430RegDesc[] = { // Descriptors
159
  { 3, 0, 0, 0, 0, 0 },
160
  { 112, 2, 1, 0, 0, 2 },
161
  { 93, 1, 18, 1, 0, 0 },
162
  { 115, 2, 1, 0, 32, 2 },
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  { 97, 1, 18, 1, 32, 0 },
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  { 109, 2, 1, 0, 64, 2 },
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  { 89, 1, 18, 1, 64, 0 },
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  { 118, 2, 1, 0, 96, 2 },
167
  { 101, 1, 18, 1, 96, 0 },
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  { 121, 2, 1, 0, 128, 2 },
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  { 105, 1, 18, 1, 128, 0 },
170
  { 24, 10, 1, 0, 257, 2 },
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  { 27, 10, 1, 0, 257, 2 },
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  { 30, 10, 1, 0, 257, 2 },
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  { 33, 10, 1, 0, 257, 2 },
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  { 36, 10, 1, 0, 257, 2 },
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  { 0, 10, 1, 0, 257, 2 },
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  { 4, 10, 1, 0, 257, 2 },
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  { 8, 10, 1, 0, 257, 2 },
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  { 12, 10, 1, 0, 257, 2 },
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  { 16, 10, 1, 0, 257, 2 },
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  { 20, 10, 1, 0, 257, 2 },
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  { 69, 1, 14, 1, 193, 0 },
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  { 73, 1, 14, 1, 193, 0 },
183
  { 77, 1, 14, 1, 193, 0 },
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  { 81, 1, 14, 1, 193, 0 },
185
  { 85, 1, 14, 1, 193, 0 },
186
  { 39, 1, 14, 1, 193, 0 },
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  { 44, 1, 14, 1, 193, 0 },
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  { 49, 1, 14, 1, 193, 0 },
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  { 54, 1, 14, 1, 193, 0 },
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  { 59, 1, 14, 1, 193, 0 },
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  { 64, 1, 14, 1, 193, 0 },
192
};
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extern const MCPhysReg MSP430RegUnitRoots[][2] = {
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  { MSP430::CGB },
196
  { MSP430::FPB },
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  { MSP430::PCB },
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  { MSP430::SPB },
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  { MSP430::SRB },
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  { MSP430::R5B },
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  { MSP430::R6B },
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  { MSP430::R7B },
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  { MSP430::R8B },
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  { MSP430::R9B },
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  { MSP430::R10B },
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  { MSP430::R11B },
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  { MSP430::R12B },
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  { MSP430::R13B },
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  { MSP430::R14B },
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  { MSP430::R15B },
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};
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namespace {     // Register classes...
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  // GR8 Register Class...
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  const MCPhysReg GR8[] = {
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    MSP430::R12B, MSP430::R13B, MSP430::R14B, MSP430::R15B, MSP430::R11B, MSP430::R10B, MSP430::R9B, MSP430::R8B, MSP430::R7B, MSP430::R6B, MSP430::R5B, MSP430::FPB, MSP430::PCB, MSP430::SPB, MSP430::SRB, MSP430::CGB, 
217
  };
218
219
  // GR8 Bit set.
220
  const uint8_t GR8Bits[] = {
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    0x54, 0x05, 0xc0, 0xff, 0x01, 
222
  };
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  // GR16 Register Class...
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  const MCPhysReg GR16[] = {
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    MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, MSP430::R11, MSP430::R10, MSP430::R9, MSP430::R8, MSP430::R7, MSP430::R6, MSP430::R5, MSP430::FP, MSP430::PC, MSP430::SP, MSP430::SR, MSP430::CG, 
227
  };
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  // GR16 Bit set.
230
  const uint8_t GR16Bits[] = {
231
    0xaa, 0xfa, 0x3f, 
232
  };
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} // end anonymous namespace
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extern const char MSP430RegClassStrings[] = {
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  /* 0 */ 'G', 'R', '1', '6', 0,
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  /* 5 */ 'G', 'R', '8', 0,
239
};
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extern const MCRegisterClass MSP430MCRegisterClasses[] = {
242
  { GR8, GR8Bits, 5, 16, sizeof(GR8Bits), MSP430::GR8RegClassID, 1, 1, true },
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  { GR16, GR16Bits, 0, 16, sizeof(GR16Bits), MSP430::GR16RegClassID, 2, 1, true },
244
};
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extern const uint16_t MSP430RegEncodingTable[] = {
247
  0,
248
  0,
249
  0,
250
  0,
251
  0,
252
  0,
253
  0,
254
  0,
255
  0,
256
  0,
257
  0,
258
  0,
259
  0,
260
  0,
261
  0,
262
  0,
263
  0,
264
  0,
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  0,
266
  0,
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  0,
268
  0,
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  0,
270
  0,
271
  0,
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  0,
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  0,
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  0,
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  0,
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  0,
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  0,
278
  0,
279
  0,
280
};
281
64
static inline void InitMSP430MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
282
64
  RI->InitMCRegisterInfo(MSP430RegDesc, 33, RA, PC, MSP430MCRegisterClasses, 2, MSP430RegUnitRoots, 16, MSP430RegDiffLists, MSP430LaneMaskLists, MSP430RegStrings, MSP430RegClassStrings, MSP430SubRegIdxLists, 2,
283
64
MSP430SubRegIdxRanges, MSP430RegEncodingTable);
284
64
285
64
}
286
287
} // end namespace llvm
288
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#endif // GET_REGINFO_MC_DESC
290
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
292
|*                                                                            *|
293
|* Register Information Header Fragment                                       *|
294
|*                                                                            *|
295
|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
298
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#ifdef GET_REGINFO_HEADER
301
#undef GET_REGINFO_HEADER
302
303
#include "llvm/CodeGen/TargetRegisterInfo.h"
304
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namespace llvm {
306
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class MSP430FrameLowering;
308
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struct MSP430GenRegisterInfo : public TargetRegisterInfo {
310
  explicit MSP430GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
311
      unsigned PC = 0, unsigned HwMode = 0);
312
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
313
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
314
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
315
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
316
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
317
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
318
  unsigned getNumRegPressureSets() const override;
319
  const char *getRegPressureSetName(unsigned Idx) const override;
320
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
321
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
322
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
323
  ArrayRef<const char *> getRegMaskNames() const override;
324
  ArrayRef<const uint32_t *> getRegMasks() const override;
325
  /// Devirtualized TargetFrameLowering.
326
  static const MSP430FrameLowering *getFrameLowering(
327
      const MachineFunction &MF);
328
};
329
330
namespace MSP430 { // Register classes
331
  extern const TargetRegisterClass GR8RegClass;
332
  extern const TargetRegisterClass GR16RegClass;
333
} // end namespace MSP430
334
335
} // end namespace llvm
336
337
#endif // GET_REGINFO_HEADER
338
339
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
340
|*                                                                            *|
341
|* Target Register and Register Classes Information                           *|
342
|*                                                                            *|
343
|* Automatically generated file, do not edit!                                 *|
344
|*                                                                            *|
345
\*===----------------------------------------------------------------------===*/
346
347
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#ifdef GET_REGINFO_TARGET_DESC
349
#undef GET_REGINFO_TARGET_DESC
350
351
namespace llvm {
352
353
extern const MCRegisterClass MSP430MCRegisterClasses[];
354
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static const MVT::SimpleValueType VTLists[] = {
356
  /* 0 */ MVT::i8, MVT::Other,
357
  /* 2 */ MVT::i16, MVT::Other,
358
};
359
360
static const char *const SubRegIndexNameTable[] = { "subreg_8bit", "" };
361
362
363
static const LaneBitmask SubRegIndexLaneMaskTable[] = {
364
  LaneBitmask::getAll(),
365
  LaneBitmask(0x00000001), // subreg_8bit
366
 };
367
368
369
370
static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
371
  // Mode = 0 (Default)
372
  { 8, 8, 8, VTLists+0 },    // GR8
373
  { 16, 16, 16, VTLists+2 },    // GR16
374
};
375
376
static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
377
378
static const uint32_t GR8SubClassMask[] = {
379
  0x00000001, 
380
  0x00000002, // subreg_8bit
381
};
382
383
static const uint32_t GR16SubClassMask[] = {
384
  0x00000002, 
385
};
386
387
static const uint16_t SuperRegIdxSeqs[] = {
388
  /* 0 */ 1, 0,
389
};
390
391
392
namespace MSP430 {   // Register class instances
393
  extern const TargetRegisterClass GR8RegClass = {
394
    &MSP430MCRegisterClasses[GR8RegClassID],
395
    GR8SubClassMask,
396
    SuperRegIdxSeqs + 0,
397
    LaneBitmask(0x00000001),
398
    0,
399
    false, /* HasDisjunctSubRegs */
400
    false, /* CoveredBySubRegs */
401
    NullRegClasses,
402
    nullptr
403
  };
404
405
  extern const TargetRegisterClass GR16RegClass = {
406
    &MSP430MCRegisterClasses[GR16RegClassID],
407
    GR16SubClassMask,
408
    SuperRegIdxSeqs + 1,
409
    LaneBitmask(0x00000001),
410
    0,
411
    false, /* HasDisjunctSubRegs */
412
    false, /* CoveredBySubRegs */
413
    NullRegClasses,
414
    nullptr
415
  };
416
417
} // end namespace MSP430
418
419
namespace {
420
  const TargetRegisterClass* const RegisterClasses[] = {
421
    &MSP430::GR8RegClass,
422
    &MSP430::GR16RegClass,
423
  };
424
} // end anonymous namespace
425
426
static const TargetRegisterInfoDesc MSP430RegInfoDesc[] = { // Extra Descriptors
427
  { 0, false },
428
  { 0, true },
429
  { 0, true },
430
  { 0, true },
431
  { 0, true },
432
  { 0, true },
433
  { 0, true },
434
  { 0, true },
435
  { 0, true },
436
  { 0, true },
437
  { 0, true },
438
  { 0, true },
439
  { 0, true },
440
  { 0, true },
441
  { 0, true },
442
  { 0, true },
443
  { 0, true },
444
  { 0, true },
445
  { 0, true },
446
  { 0, true },
447
  { 0, true },
448
  { 0, true },
449
  { 0, true },
450
  { 0, true },
451
  { 0, true },
452
  { 0, true },
453
  { 0, true },
454
  { 0, true },
455
  { 0, true },
456
  { 0, true },
457
  { 0, true },
458
  { 0, true },
459
  { 0, true },
460
};
461
0
unsigned MSP430GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
462
0
  static const uint8_t Rows[1][1] = {
463
0
    { 0, },
464
0
  };
465
0
466
0
  --IdxA; assert(IdxA < 1);
467
0
  --IdxB; assert(IdxB < 1);
468
0
  return Rows[0][IdxB];
469
0
}
470
471
  struct MaskRolOp {
472
    LaneBitmask Mask;
473
    uint8_t  RotateLeft;
474
  };
475
  static const MaskRolOp LaneMaskComposeSequences[] = {
476
    { LaneBitmask(0xFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 }  // Sequence 0
477
  };
478
  static const MaskRolOp *const CompositeSequences[] = {
479
    &LaneMaskComposeSequences[0] // to subreg_8bit
480
  };
481
482
0
LaneBitmask MSP430GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
483
0
  --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
484
0
  LaneBitmask Result;
485
0
  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
486
0
    LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
487
0
    if (unsigned S = Ops->RotateLeft)
488
0
      Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
489
0
    else
490
0
      Result |= LaneBitmask(M);
491
0
  }
492
0
  return Result;
493
0
}
494
495
0
LaneBitmask MSP430GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
496
0
  LaneMask &= getSubRegIndexLaneMask(IdxA);
497
0
  --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
498
0
  LaneBitmask Result;
499
0
  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
500
0
    LaneBitmask::Type M = LaneMask.getAsInteger();
501
0
    if (unsigned S = Ops->RotateLeft)
502
0
      Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
503
0
    else
504
0
      Result |= LaneBitmask(M);
505
0
  }
506
0
  return Result;
507
0
}
508
509
68
const TargetRegisterClass *MSP430GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
510
68
  static const uint8_t Table[2][1] = {
511
68
    { // GR8
512
68
      0,  // subreg_8bit
513
68
    },
514
68
    { // GR16
515
68
      2,  // subreg_8bit -> GR16
516
68
    },
517
68
  };
518
68
  assert(RC && "Missing regclass");
519
68
  if (!Idx) 
return RC0
;
520
68
  --Idx;
521
68
  assert(Idx < 1 && "Bad subreg");
522
68
  unsigned TV = Table[RC->getID()][Idx];
523
68
  return TV ? getRegClass(TV - 1) : 
nullptr0
;
524
68
}
525
526
/// Get the weight in units of pressure for this register class.
527
const RegClassWeight &MSP430GenRegisterInfo::
528
156
getRegClassWeight(const TargetRegisterClass *RC) const {
529
156
  static const RegClassWeight RCWeightTable[] = {
530
156
    {1, 16},    // GR8
531
156
    {1, 16},    // GR16
532
156
  };
533
156
  return RCWeightTable[RC->getID()];
534
156
}
535
536
/// Get the weight in units of pressure for this register unit.
537
unsigned MSP430GenRegisterInfo::
538
0
getRegUnitWeight(unsigned RegUnit) const {
539
0
  assert(RegUnit < 16 && "invalid register unit");
540
0
  // All register units have unit weight.
541
0
  return 1;
542
0
}
543
544
545
// Get the number of dimensions of register pressure.
546
445
unsigned MSP430GenRegisterInfo::getNumRegPressureSets() const {
547
445
  return 1;
548
445
}
549
550
// Get the name of this register unit pressure set.
551
const char *MSP430GenRegisterInfo::
552
0
getRegPressureSetName(unsigned Idx) const {
553
0
  static const char *const PressureNameTable[] = {
554
0
    "GR8",
555
0
  };
556
0
  return PressureNameTable[Idx];
557
0
}
558
559
// Get the register unit pressure limit for this dimension.
560
// This limit must be adjusted dynamically for reserved registers.
561
unsigned MSP430GenRegisterInfo::
562
214
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
563
214
  static const uint8_t PressureLimitTable[] = {
564
214
    16,   // 0: GR8
565
214
  };
566
214
  return PressureLimitTable[Idx];
567
214
}
568
569
/// Table of pressure sets per register class or unit.
570
static const int RCSetsTable[] = {
571
  /* 0 */ 0, -1,
572
};
573
574
/// Get the dimensions of register pressure impacted by this register class.
575
/// Returns a -1 terminated array of pressure set IDs
576
const int* MSP430GenRegisterInfo::
577
137
getRegClassPressureSets(const TargetRegisterClass *RC) const {
578
137
  static const uint8_t RCSetStartTable[] = {
579
137
    0,0,};
580
137
  return &RCSetsTable[RCSetStartTable[RC->getID()]];
581
137
}
582
583
/// Get the dimensions of register pressure impacted by this register unit.
584
/// Returns a -1 terminated array of pressure set IDs
585
const int* MSP430GenRegisterInfo::
586
0
getRegUnitPressureSets(unsigned RegUnit) const {
587
0
  assert(RegUnit < 16 && "invalid register unit");
588
0
  static const uint8_t RUSetStartTable[] = {
589
0
    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,};
590
0
  return &RCSetsTable[RUSetStartTable[RegUnit]];
591
0
}
592
593
extern const MCRegisterDesc MSP430RegDesc[];
594
extern const MCPhysReg MSP430RegDiffLists[];
595
extern const LaneBitmask MSP430LaneMaskLists[];
596
extern const char MSP430RegStrings[];
597
extern const char MSP430RegClassStrings[];
598
extern const MCPhysReg MSP430RegUnitRoots[][2];
599
extern const uint16_t MSP430SubRegIdxLists[];
600
extern const MCRegisterInfo::SubRegCoveredBits MSP430SubRegIdxRanges[];
601
extern const uint16_t MSP430RegEncodingTable[];
602
MSP430GenRegisterInfo::
603
MSP430GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
604
      unsigned PC, unsigned HwMode)
605
  : TargetRegisterInfo(MSP430RegInfoDesc, RegisterClasses, RegisterClasses+2,
606
             SubRegIndexNameTable, SubRegIndexLaneMaskTable,
607
64
             LaneBitmask(0xFFFFFFFE), RegClassInfos, HwMode) {
608
64
  InitMCRegisterInfo(MSP430RegDesc, 33, RA, PC,
609
64
                     MSP430MCRegisterClasses, 2,
610
64
                     MSP430RegUnitRoots,
611
64
                     16,
612
64
                     MSP430RegDiffLists,
613
64
                     MSP430LaneMaskLists,
614
64
                     MSP430RegStrings,
615
64
                     MSP430RegClassStrings,
616
64
                     MSP430SubRegIdxLists,
617
64
                     2,
618
64
                     MSP430SubRegIdxRanges,
619
64
                     MSP430RegEncodingTable);
620
64
621
64
}
622
623
624
625
1
ArrayRef<const uint32_t *> MSP430GenRegisterInfo::getRegMasks() const {
626
1
  return None;
627
1
}
628
629
0
ArrayRef<const char *> MSP430GenRegisterInfo::getRegMaskNames() const {
630
0
  return None;
631
0
}
632
633
const MSP430FrameLowering *
634
2.46k
MSP430GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
635
2.46k
  return static_cast<const MSP430FrameLowering *>(
636
2.46k
      MF.getSubtarget().getFrameLowering());
637
2.46k
}
638
639
} // end namespace llvm
640
641
#endif // GET_REGINFO_TARGET_DESC
642