Coverage Report

Created: 2019-03-24 22:13

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/MSP430/MSP430GenSubtargetInfo.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Subtarget Enumeration Source Fragment                                      *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_SUBTARGETINFO_ENUM
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#undef GET_SUBTARGETINFO_ENUM
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namespace llvm {
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namespace MSP430 {
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enum {
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  FeatureHWMult16 = 0,
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  FeatureHWMult32 = 1,
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  FeatureHWMultF5 = 2,
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  FeatureX = 3,
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};
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} // end namespace MSP430
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} // end namespace llvm
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#endif // GET_SUBTARGETINFO_ENUM
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#ifdef GET_SUBTARGETINFO_MC_DESC
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#undef GET_SUBTARGETINFO_MC_DESC
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namespace llvm {
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// Sorted (by key) array of values for CPU features.
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extern const llvm::SubtargetFeatureKV MSP430FeatureKV[] = {
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  { "ext", "Enable MSP430-X extensions", MSP430::FeatureX, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
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  { "hwmult16", "Enable 16-bit hardware multiplier", MSP430::FeatureHWMult16, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
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  { "hwmult32", "Enable 32-bit hardware multiplier", MSP430::FeatureHWMult32, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
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  { "hwmultf5", "Enable F5 series hardware multiplier", MSP430::FeatureHWMultF5, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
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};
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#ifdef DBGFIELD
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#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
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#endif
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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#define DBGFIELD(x) x,
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#else
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#define DBGFIELD(x)
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#endif
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// ===============================================================
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// Data tables for the new per-operand machine model.
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// {ProcResourceIdx, Cycles}
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extern const llvm::MCWriteProcResEntry MSP430WriteProcResTable[] = {
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  { 0,  0}, // Invalid
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}; // MSP430WriteProcResTable
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// {Cycles, WriteResourceID}
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extern const llvm::MCWriteLatencyEntry MSP430WriteLatencyTable[] = {
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  { 0,  0}, // Invalid
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}; // MSP430WriteLatencyTable
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// {UseIdx, WriteResourceID, Cycles}
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extern const llvm::MCReadAdvanceEntry MSP430ReadAdvanceTable[] = {
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  {0,  0,  0}, // Invalid
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}; // MSP430ReadAdvanceTable
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#undef DBGFIELD
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static const llvm::MCSchedModel NoSchedModel = {
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  MCSchedModel::DefaultIssueWidth,
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  MCSchedModel::DefaultMicroOpBufferSize,
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  MCSchedModel::DefaultLoopMicroOpBufferSize,
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  MCSchedModel::DefaultLoadLatency,
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  MCSchedModel::DefaultHighLatency,
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  MCSchedModel::DefaultMispredictPenalty,
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  false, // PostRAScheduler
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  false, // CompleteModel
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  0, // Processor ID
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  nullptr, nullptr, 0, 0, // No instruction-level machine model.
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  nullptr, // No Itinerary
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  nullptr // No extra processor descriptor
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};
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// Sorted (by key) array of values for CPU subtype.
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extern const llvm::SubtargetSubTypeKV MSP430SubTypeKV[] = {
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 { "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
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 { "msp430", { { { 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
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 { "msp430x", { { { 0x8ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
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};
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namespace MSP430_MC {
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unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
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    const MCInst *MI, unsigned CPUID) {
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  // Don't know how to resolve this scheduling class.
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  return 0;
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}
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} // end of namespace MSP430_MC
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struct MSP430GenMCSubtargetInfo : public MCSubtargetInfo {
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  MSP430GenMCSubtargetInfo(const Triple &TT, 
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    StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
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    ArrayRef<SubtargetSubTypeKV> PD,
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    const MCWriteProcResEntry *WPR,
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    const MCWriteLatencyEntry *WL,
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    const MCReadAdvanceEntry *RA, const InstrStage *IS,
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    const unsigned *OC, const unsigned *FP) :
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      MCSubtargetInfo(TT, CPU, FS, PF, PD,
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                      WPR, WL, RA, IS, OC, FP) { }
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  unsigned resolveVariantSchedClass(unsigned SchedClass,
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      const MCInst *MI, unsigned CPUID) const override {
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    return MSP430_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID); 
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  }
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};
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static inline MCSubtargetInfo *createMSP430MCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) {
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  return new MSP430GenMCSubtargetInfo(TT, CPU, FS, MSP430FeatureKV, MSP430SubTypeKV, 
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                      MSP430WriteProcResTable, MSP430WriteLatencyTable, MSP430ReadAdvanceTable, 
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                      nullptr, nullptr, nullptr);
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}
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} // end namespace llvm
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#endif // GET_SUBTARGETINFO_MC_DESC
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#ifdef GET_SUBTARGETINFO_TARGET_DESC
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#undef GET_SUBTARGETINFO_TARGET_DESC
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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// ParseSubtargetFeatures - Parses features string setting specified
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// subtarget options.
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void llvm::MSP430Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {
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  LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
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  LLVM_DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n");
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  InitMCProcessorInfo(CPU, FS);
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  const FeatureBitset& Bits = getFeatureBits();
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  if (Bits[MSP430::FeatureHWMult16] && 
HWMultMode < HWMult161
)
HWMultMode = HWMult161
;
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  if (Bits[MSP430::FeatureHWMult32] && 
HWMultMode < HWMult321
)
HWMultMode = HWMult321
;
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  if (Bits[MSP430::FeatureHWMultF5] && 
HWMultMode < HWMultF51
)
HWMultMode = HWMultF51
;
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  if (Bits[MSP430::FeatureX]) 
ExtendedInsts = true0
;
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}
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#endif // GET_SUBTARGETINFO_TARGET_DESC
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#ifdef GET_SUBTARGETINFO_HEADER
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#undef GET_SUBTARGETINFO_HEADER
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namespace llvm {
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class DFAPacketizer;
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namespace MSP430_MC {
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unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
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}
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struct MSP430GenSubtargetInfo : public TargetSubtargetInfo {
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  explicit MSP430GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS);
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public:
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  unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
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  unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
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  DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
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};
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} // end namespace llvm
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#endif // GET_SUBTARGETINFO_HEADER
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#ifdef GET_SUBTARGETINFO_CTOR
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#undef GET_SUBTARGETINFO_CTOR
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#include "llvm/CodeGen/TargetSchedule.h"
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namespace llvm {
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extern const llvm::SubtargetFeatureKV MSP430FeatureKV[];
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extern const llvm::SubtargetSubTypeKV MSP430SubTypeKV[];
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extern const llvm::MCWriteProcResEntry MSP430WriteProcResTable[];
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extern const llvm::MCWriteLatencyEntry MSP430WriteLatencyTable[];
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extern const llvm::MCReadAdvanceEntry MSP430ReadAdvanceTable[];
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MSP430GenSubtargetInfo::MSP430GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
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  : TargetSubtargetInfo(TT, CPU, FS, makeArrayRef(MSP430FeatureKV, 4), makeArrayRef(MSP430SubTypeKV, 3), 
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                        MSP430WriteProcResTable, MSP430WriteLatencyTable, MSP430ReadAdvanceTable, 
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                        nullptr, nullptr, nullptr) {}
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unsigned MSP430GenSubtargetInfo
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0
::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
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  report_fatal_error("Expected a variant SchedClass");
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} // MSP430GenSubtargetInfo::resolveSchedClass
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unsigned MSP430GenSubtargetInfo
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::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
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  return MSP430_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
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} // MSP430GenSubtargetInfo::resolveVariantSchedClass
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} // end namespace llvm
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#endif // GET_SUBTARGETINFO_CTOR
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#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
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#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
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#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
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#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
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#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
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#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
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