Coverage Report

Created: 2018-07-12 09:57

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Mips/MipsGenAsmMatcher.inc
Line
Count
Source (jump to first uncovered line)
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Assembly Matcher Source Fragment                                           *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_ASSEMBLER_HEADER
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#undef GET_ASSEMBLER_HEADER
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  // This should be included into the middle of the declaration of
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  // your subclasses implementation of MCTargetAsmParser.
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  uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;
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  void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
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                       const OperandVector &Operands);
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  void convertToMapAndConstraints(unsigned Kind,
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                           const OperandVector &Operands) override;
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  unsigned MatchInstructionImpl(const OperandVector &Operands,
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                                MCInst &Inst,
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                                uint64_t &ErrorInfo,
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                                bool matchingInlineAsm,
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                                unsigned VariantID = 0);
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  OperandMatchResultTy MatchOperandParserImpl(
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    OperandVector &Operands,
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    StringRef Mnemonic,
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    bool ParseForAllFeatures = false);
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  OperandMatchResultTy tryCustomParseOperand(
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    OperandVector &Operands,
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    unsigned MCK);
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#endif // GET_ASSEMBLER_HEADER_INFO
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#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
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#undef GET_OPERAND_DIAGNOSTIC_TYPES
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  Match_Immz,
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  Match_MemSImm10,
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  Match_MemSImm10Lsl1,
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  Match_MemSImm10Lsl2,
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  Match_MemSImm10Lsl3,
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  Match_MemSImm11,
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  Match_MemSImm12,
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  Match_MemSImm16,
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  Match_MemSImm9,
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  Match_MemSImmPtr,
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  Match_SImm10_0,
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  Match_SImm10_Lsl1,
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  Match_SImm10_Lsl2,
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  Match_SImm10_Lsl3,
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  Match_SImm11_0,
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  Match_SImm16,
54
  Match_SImm16_Relaxed,
55
  Match_SImm19_Lsl2,
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  Match_SImm32,
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  Match_SImm32_Relaxed,
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  Match_SImm4_0,
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  Match_SImm5_0,
60
  Match_SImm6_0,
61
  Match_SImm7_Lsl2,
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  Match_SImm9_0,
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  Match_UImm10_0,
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  Match_UImm16,
65
  Match_UImm16_AltRelaxed,
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  Match_UImm16_Relaxed,
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  Match_UImm1_0,
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  Match_UImm20_0,
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  Match_UImm26_0,
70
  Match_UImm2_0,
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  Match_UImm2_1,
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  Match_UImm32_Coerced,
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  Match_UImm3_0,
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  Match_UImm4_0,
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  Match_UImm5_0,
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  Match_UImm5_0_Report_UImm6,
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  Match_UImm5_1,
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  Match_UImm5_32,
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  Match_UImm5_33,
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  Match_UImm5_Lsl2,
81
  Match_UImm6_0,
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  Match_UImm6_Lsl2,
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  Match_UImm7_0,
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  Match_UImm7_N1,
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  Match_UImm8_0,
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  Match_UImmRange2_64,
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  END_OPERAND_DIAGNOSTIC_TYPES
88
#endif // GET_OPERAND_DIAGNOSTIC_TYPES
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#ifdef GET_REGISTER_MATCHER
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#undef GET_REGISTER_MATCHER
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// Flags for subtarget features that participate in instruction matching.
95
enum SubtargetFeatureFlag : uint64_t {
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  Feature_HasMips2 = (1ULL << 10),
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  Feature_HasMips3_32 = (1ULL << 16),
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  Feature_HasMips3_32r2 = (1ULL << 17),
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  Feature_HasMips3 = (1ULL << 11),
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  Feature_NotMips3 = (1ULL << 44),
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  Feature_HasMips4_32 = (1ULL << 18),
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  Feature_NotMips4_32 = (1ULL << 46),
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  Feature_HasMips4_32r2 = (1ULL << 19),
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  Feature_HasMips5_32r2 = (1ULL << 20),
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  Feature_HasMips32 = (1ULL << 12),
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  Feature_HasMips32r2 = (1ULL << 13),
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  Feature_HasMips32r5 = (1ULL << 14),
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  Feature_HasMips32r6 = (1ULL << 15),
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  Feature_NotMips32r6 = (1ULL << 45),
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  Feature_IsGP64bit = (1ULL << 31),
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  Feature_IsGP32bit = (1ULL << 30),
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  Feature_IsPTR64bit = (1ULL << 35),
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  Feature_IsPTR32bit = (1ULL << 34),
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  Feature_HasMips64 = (1ULL << 21),
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  Feature_NotMips64 = (1ULL << 47),
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  Feature_HasMips64r2 = (1ULL << 22),
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  Feature_HasMips64r5 = (1ULL << 23),
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  Feature_HasMips64r6 = (1ULL << 24),
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  Feature_NotMips64r6 = (1ULL << 48),
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  Feature_InMips16Mode = (1ULL << 28),
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  Feature_NotInMips16Mode = (1ULL << 43),
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  Feature_HasCnMips = (1ULL << 1),
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  Feature_NotCnMips = (1ULL << 40),
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  Feature_IsSym32 = (1ULL << 37),
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  Feature_IsSym64 = (1ULL << 38),
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  Feature_HasStdEnc = (1ULL << 25),
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  Feature_InMicroMips = (1ULL << 27),
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  Feature_NotInMicroMips = (1ULL << 42),
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  Feature_HasEVA = (1ULL << 5),
130
  Feature_HasMSA = (1ULL << 7),
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  Feature_HasMadd4 = (1ULL << 9),
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  Feature_HasMT = (1ULL << 8),
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  Feature_UseIndirectJumpsHazard = (1ULL << 49),
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  Feature_NoIndirectJumpGuards = (1ULL << 39),
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  Feature_HasCRC = (1ULL << 0),
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  Feature_HasVirt = (1ULL << 26),
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  Feature_HasGINV = (1ULL << 6),
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  Feature_IsFP64bit = (1ULL << 29),
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  Feature_NotFP64bit = (1ULL << 41),
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  Feature_IsSingleFloat = (1ULL << 36),
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  Feature_IsNotSingleFloat = (1ULL << 32),
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  Feature_IsNotSoftFloat = (1ULL << 33),
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  Feature_HasDSP = (1ULL << 2),
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  Feature_HasDSPR2 = (1ULL << 3),
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  Feature_HasDSPR3 = (1ULL << 4),
146
  Feature_None = 0
147
};
148
149
#endif // GET_REGISTER_MATCHER
150
151
152
#ifdef GET_SUBTARGET_FEATURE_NAME
153
#undef GET_SUBTARGET_FEATURE_NAME
154
155
// User-level names for subtarget features that participate in
156
// instruction matching.
157
static const char *getSubtargetFeatureName(uint64_t Val) {
158
  switch(Val) {
159
  case Feature_HasMips2: return "";
160
  case Feature_HasMips3_32: return "";
161
  case Feature_HasMips3_32r2: return "";
162
  case Feature_HasMips3: return "";
163
  case Feature_NotMips3: return "";
164
  case Feature_HasMips4_32: return "";
165
  case Feature_NotMips4_32: return "";
166
  case Feature_HasMips4_32r2: return "";
167
  case Feature_HasMips5_32r2: return "";
168
  case Feature_HasMips32: return "";
169
  case Feature_HasMips32r2: return "";
170
  case Feature_HasMips32r5: return "";
171
  case Feature_HasMips32r6: return "";
172
  case Feature_NotMips32r6: return "";
173
  case Feature_IsGP64bit: return "";
174
  case Feature_IsGP32bit: return "";
175
  case Feature_IsPTR64bit: return "";
176
  case Feature_IsPTR32bit: return "";
177
  case Feature_HasMips64: return "";
178
  case Feature_NotMips64: return "";
179
  case Feature_HasMips64r2: return "";
180
  case Feature_HasMips64r5: return "";
181
  case Feature_HasMips64r6: return "";
182
  case Feature_NotMips64r6: return "";
183
  case Feature_InMips16Mode: return "";
184
  case Feature_NotInMips16Mode: return "";
185
  case Feature_HasCnMips: return "";
186
  case Feature_NotCnMips: return "";
187
  case Feature_IsSym32: return "";
188
  case Feature_IsSym64: return "";
189
  case Feature_HasStdEnc: return "";
190
  case Feature_InMicroMips: return "";
191
  case Feature_NotInMicroMips: return "";
192
  case Feature_HasEVA: return "";
193
  case Feature_HasMSA: return "";
194
  case Feature_HasMadd4: return "";
195
  case Feature_HasMT: return "";
196
  case Feature_UseIndirectJumpsHazard: return "";
197
  case Feature_NoIndirectJumpGuards: return "";
198
  case Feature_HasCRC: return "";
199
  case Feature_HasVirt: return "";
200
  case Feature_HasGINV: return "";
201
  case Feature_IsFP64bit: return "";
202
  case Feature_NotFP64bit: return "";
203
  case Feature_IsSingleFloat: return "";
204
  case Feature_IsNotSingleFloat: return "";
205
  case Feature_IsNotSoftFloat: return "";
206
  case Feature_HasDSP: return "";
207
  case Feature_HasDSPR2: return "";
208
  case Feature_HasDSPR3: return "";
209
  default: return "(unknown)";
210
  }
211
}
212
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#endif // GET_SUBTARGET_FEATURE_NAME
214
215
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#ifdef GET_MATCHER_IMPLEMENTATION
217
#undef GET_MATCHER_IMPLEMENTATION
218
219
enum {
220
  Tie0_1_1,
221
  Tie0_1_2,
222
};
223
224
static const uint8_t TiedAsmOperandTable[][3] = {
225
  /* Tie0_1_1 */ { 0, 1, 1 },
226
  /* Tie0_1_2 */ { 0, 1, 2 },
227
};
228
229
namespace {
230
enum OperatorConversionKind {
231
  CVT_Done,
232
  CVT_Reg,
233
  CVT_Tied,
234
  CVT_95_addGPR32AsmRegOperands,
235
  CVT_95_addAFGR64AsmRegOperands,
236
  CVT_95_addFGR64AsmRegOperands,
237
  CVT_95_addFGR32AsmRegOperands,
238
  CVT_95_addSImmOperands_LT_32_GT_,
239
  CVT_95_addMSA128AsmRegOperands,
240
  CVT_95_addSImmOperands_LT_16_GT_,
241
  CVT_95_Reg,
242
  CVT_95_addImmOperands,
243
  CVT_95_addGPRMM16AsmRegOperands,
244
  CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_,
245
  CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_,
246
  CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_,
247
  CVT_95_addUImmOperands_LT_16_GT_,
248
  CVT_95_addGPR64AsmRegOperands,
249
  CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_,
250
  CVT_regZERO,
251
  CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_,
252
  CVT_regFCC0,
253
  CVT_95_addFCCAsmRegOperands,
254
  CVT_95_addCOP2AsmRegOperands,
255
  CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_,
256
  CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_,
257
  CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_,
258
  CVT_imm_95_0,
259
  CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_,
260
  CVT_95_addMemOperands,
261
  CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_,
262
  CVT_95_addCCRAsmRegOperands,
263
  CVT_95_addMSACtrlAsmRegOperands,
264
  CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_,
265
  CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_,
266
  CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_,
267
  CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_,
268
  CVT_95_addGPR32NonZeroAsmRegOperands,
269
  CVT_95_addGPR32ZeroAsmRegOperands,
270
  CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_,
271
  CVT_95_addCOP0AsmRegOperands,
272
  CVT_regZERO_64,
273
  CVT_95_addACC64DSPAsmRegOperands,
274
  CVT_95_addConstantUImmOperands_LT_1_GT_,
275
  CVT_regRA,
276
  CVT_regRA_64,
277
  CVT_95_addMicroMipsMemOperands,
278
  CVT_95_addCOP3AsmRegOperands,
279
  CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_,
280
  CVT_95_addConstantUImmOperands_LT_32_GT_,
281
  CVT_95_addStrictlyAFGR64AsmRegOperands,
282
  CVT_95_addStrictlyFGR64AsmRegOperands,
283
  CVT_95_addStrictlyFGR32AsmRegOperands,
284
  CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_,
285
  CVT_95_addRegListOperands,
286
  CVT_ConvertXWPOperands,
287
  CVT_regAC0,
288
  CVT_95_addMovePRegPairOperands,
289
  CVT_95_addGPRMM16AsmRegMovePOperands,
290
  CVT_95_addHI32DSPAsmRegOperands,
291
  CVT_95_addLO32DSPAsmRegOperands,
292
  CVT_regS0,
293
  CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_,
294
  CVT_95_addHWRegsAsmRegOperands,
295
  CVT_95_addGPRMM16AsmRegZeroOperands,
296
  CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_,
297
  CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_,
298
  CVT_imm_95_2,
299
  CVT_imm_95_6,
300
  CVT_imm_95_4,
301
  CVT_imm_95_5,
302
  CVT_imm_95_31,
303
  CVT_NUM_CONVERTERS
304
};
305
306
enum InstructionConversionKind {
307
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1,
308
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1,
309
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1,
310
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1,
311
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1,
312
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1,
313
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
314
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2,
315
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2,
316
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
317
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
318
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1,
319
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2,
320
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1,
321
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1,
322
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2,
323
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2,
324
  Convert__SImm161_1,
325
  Convert__Reg1_0__SImm161_1,
326
  Convert__Reg1_0__SImm161_2,
327
  Convert__Reg1_0__Reg1_1__SImm161_2,
328
  Convert__Reg1_0__Tie0_1_1__SImm161_1,
329
  Convert__GPR32AsmReg1_0__Simm19_Lsl21_1,
330
  Convert__GPRMM16AsmReg1_0__Imm1_1,
331
  Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1,
332
  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2,
333
  Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1,
334
  Convert__Imm1_0,
335
  Convert__Reg1_0__Reg1_1__Reg1_2,
336
  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2,
337
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2,
338
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3,
339
  Convert__GPR32AsmReg1_0__SImm161_1,
340
  Convert__Reg1_0__Tie0_1_1__Reg1_1,
341
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1,
342
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1,
343
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2,
344
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2,
345
  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1,
346
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2,
347
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1,
348
  Convert__regZERO__regZERO__JumpTarget1_0,
349
  Convert__JumpTarget1_0,
350
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1,
351
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2,
352
  Convert__regZERO__JumpTarget1_0,
353
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1,
354
  Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2,
355
  Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2,
356
  Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2,
357
  Convert__FGR64AsmReg1_0__JumpTarget1_1,
358
  Convert__regFCC0__JumpTarget1_0,
359
  Convert__FCCAsmReg1_0__JumpTarget1_1,
360
  Convert__COP2AsmReg1_0__JumpTarget1_1,
361
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2,
362
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2,
363
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2,
364
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2,
365
  Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2,
366
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2,
367
  Convert__Reg1_0__JumpTarget1_1,
368
  Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1,
369
  Convert__GPRMM16AsmReg1_0__JumpTarget1_1,
370
  Convert__GPR32AsmReg1_0__JumpTarget1_1,
371
  Convert__GPR64AsmReg1_0__JumpTarget1_1,
372
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2,
373
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2,
374
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2,
375
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2,
376
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2,
377
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2,
378
  Convert__MSA128AsmReg1_0__JumpTarget1_1,
379
  Convert__imm_95_0__imm_95_0,
380
  Convert_NoOperands,
381
  Convert__ConstantUImm10_01_0__imm_95_0,
382
  Convert__ConstantUImm10_01_0__ConstantUImm10_01_1,
383
  Convert__ConstantUImm4_01_0,
384
  Convert__SImm161_0,
385
  Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1,
386
  Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1,
387
  Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2,
388
  Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
389
  Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1,
390
  Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
391
  Convert__MemOffsetSimm92_1__ConstantUImm5_01_0,
392
  Convert__Mem2_1__ConstantUImm5_01_0,
393
  Convert__FGR64AsmReg1_0__FGR32AsmReg1_1,
394
  Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1,
395
  Convert__FGR32AsmReg1_0__FGR64AsmReg1_1,
396
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2,
397
  Convert__GPR32AsmReg1_0__CCRAsmReg1_1,
398
  Convert__GPR32AsmReg1_0__COP2AsmReg1_1,
399
  Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1,
400
  Convert__GPR32AsmReg1_0__FGR32AsmReg1_1,
401
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2,
402
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2,
403
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3,
404
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3,
405
  Convert__Reg1_0__Reg1_1,
406
  Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
407
  Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3,
408
  Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3,
409
  Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3,
410
  Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3,
411
  Convert__CCRAsmReg1_1__GPR32AsmReg1_0,
412
  Convert__COP2AsmReg1_1__GPR32AsmReg1_0,
413
  Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1,
414
  Convert__FGR32AsmReg1_1__GPR32AsmReg1_0,
415
  Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1,
416
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1,
417
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2,
418
  Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2,
419
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3,
420
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2,
421
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1,
422
  Convert__GPR64AsmReg1_1__GPR64AsmReg1_2,
423
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3,
424
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3,
425
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3,
426
  Convert__regZERO,
427
  Convert__GPR32AsmReg1_0,
428
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1,
429
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1,
430
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1,
431
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1,
432
  Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1,
433
  Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1,
434
  Convert__Reg1_1__Reg1_2,
435
  Convert__GPR32AsmReg1_1__GPR32AsmReg1_2,
436
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2,
437
  Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
438
  Convert__GPR64AsmReg1_0__Imm1_1,
439
  Convert__GPR64AsmReg1_0__Mem2_1,
440
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3,
441
  Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0,
442
  Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2,
443
  Convert__GPR64AsmReg1_0__FGR64AsmReg1_1,
444
  Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0,
445
  Convert__GPR64AsmReg1_0__UImm161_1,
446
  Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2,
447
  Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0,
448
  Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2,
449
  Convert__FGR64AsmReg1_1__GPR64AsmReg1_0,
450
  Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0,
451
  Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2,
452
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2,
453
  Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0,
454
  Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1,
455
  Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
456
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0,
457
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1,
458
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1,
459
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2,
460
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1,
461
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2,
462
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2,
463
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1,
464
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1,
465
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2,
466
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3,
467
  Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2,
468
  Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2,
469
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1,
470
  Convert__MSA128AsmReg1_0__GPR32AsmReg1_1,
471
  Convert__MSA128AsmReg1_0__GPR64AsmReg1_1,
472
  Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2,
473
  Convert__GPR32AsmReg1_0__ConstantUImm2_01_1,
474
  Convert__imm_95_0,
475
  Convert__ConstantUImm10_01_0,
476
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1,
477
  Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2,
478
  Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2,
479
  Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2,
480
  Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2,
481
  Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1,
482
  Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
483
  Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
484
  Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
485
  Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
486
  Convert__regRA__GPR32AsmReg1_0,
487
  Convert__regRA_64__GPR64AsmReg1_0,
488
  Convert__Reg1_0,
489
  Convert__GPR32AsmReg1_0__imm_95_0,
490
  Convert__GPR64AsmReg1_0__imm_95_0,
491
  Convert__regZERO__GPR32AsmReg1_0,
492
  Convert__GPR64AsmReg1_0,
493
  Convert__regZERO_64__GPR64AsmReg1_0,
494
  Convert__UImm5Lsl21_0,
495
  Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1,
496
  Convert__FGR64AsmReg1_0__MemOffsetSimm162_1,
497
  Convert__FGR32AsmReg1_0__MemOffsetSimm162_1,
498
  Convert__GPR32AsmReg1_0__Imm1_1,
499
  Convert__GPR32AsmReg1_0__Mem2_1,
500
  Convert__GPR32AsmReg1_0__MemOffsetSimm162_1,
501
  Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1,
502
  Convert__GPR32AsmReg1_0__MemOffsetSimm92_1,
503
  Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1,
504
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
505
  Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1,
506
  Convert__MSA128AsmReg1_0__MemOffsetSimm102_1,
507
  Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1,
508
  Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1,
509
  Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1,
510
  Convert__COP2AsmReg1_0__MemOffsetSimm112_1,
511
  Convert__COP2AsmReg1_0__MemOffsetSimm162_1,
512
  Convert__COP3AsmReg1_0__Mem2_1,
513
  Convert__MSA128AsmReg1_0__ConstantSImm10_01_1,
514
  Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1,
515
  Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
516
  Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
517
  Convert__GPR32AsmReg1_0__UImm32_Coerced1_1,
518
  Convert__StrictlyAFGR64AsmReg1_0__Imm1_1,
519
  Convert__StrictlyFGR64AsmReg1_0__Imm1_1,
520
  Convert__StrictlyFGR32AsmReg1_0__Imm1_1,
521
  Convert__GPRMM16AsmReg1_0__UImm7_N11_1,
522
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3,
523
  Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3,
524
  Convert__GPR32AsmReg1_0__UImm161_1,
525
  Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1,
526
  Convert__Reg1_0__Imm1_1__imm_95_0,
527
  Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1,
528
  Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1,
529
  Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1,
530
  Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1,
531
  Convert__RegList1_0__Mem2_1,
532
  Convert__RegList161_0__MemOffsetUimm42_1,
533
  ConvertCustom_ConvertXWPOperands,
534
  Convert__GPR32AsmReg1_0__MemOffsetSimm122_1,
535
  Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
536
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3,
537
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3,
538
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3,
539
  Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2,
540
  Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2,
541
  Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0,
542
  Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2,
543
  Convert__GPR32AsmReg1_0__FGR64AsmReg1_1,
544
  Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0,
545
  Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2,
546
  Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1,
547
  Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1,
548
  Convert__GPR32AsmReg1_0__regAC0,
549
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0,
550
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4,
551
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO,
552
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64,
553
  Convert__MovePRegPair2_0__GPRMM16AsmRegMoveP1_1__GPRMM16AsmRegMoveP1_2,
554
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
555
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
556
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
557
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
558
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
559
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
560
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
561
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
562
  Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0,
563
  Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2,
564
  Convert__FGR64AsmReg1_1__GPR32AsmReg1_0,
565
  Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0,
566
  Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2,
567
  Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0,
568
  Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0,
569
  Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0,
570
  Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1,
571
  Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0,
572
  Convert__regAC0__GPR32AsmReg1_0,
573
  Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0,
574
  Convert__GPR32AsmReg1_1__GPR32AsmReg1_0,
575
  Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4,
576
  Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
577
  Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0,
578
  Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1,
579
  Convert__regZERO__regZERO__imm_95_0,
580
  Convert__regZERO__regS0,
581
  Convert__regZERO__regZERO,
582
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO,
583
  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1,
584
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0,
585
  Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0,
586
  Convert__GPR32AsmReg1_0__ConstantUImm7_01_1,
587
  Convert__GPR32AsmReg1_0__ConstantUImm10_01_1,
588
  Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0,
589
  Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2,
590
  Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2,
591
  Convert__GPR32AsmReg1_0__ConstantSImm10_01_1,
592
  Convert__GPR32AsmReg1_0__ConstantUImm8_01_1,
593
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1,
594
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2,
595
  Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1,
596
  Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1,
597
  Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1,
598
  Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1,
599
  Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1,
600
  Convert__ConstantUImm20_01_0,
601
  Convert__Reg1_0__Tie0_1_1,
602
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1,
603
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2,
604
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0,
605
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1,
606
  Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1,
607
  Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1,
608
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2,
609
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2,
610
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3,
611
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3,
612
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3,
613
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3,
614
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3,
615
  Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2,
616
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3,
617
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3,
618
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3,
619
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3,
620
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3,
621
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1,
622
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2,
623
  Convert__ConstantUImm5_01_0,
624
  Convert__MemOffsetSimm162_0,
625
  Convert__imm_95_2,
626
  Convert__imm_95_6,
627
  Convert__imm_95_4,
628
  Convert__imm_95_5,
629
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2,
630
  Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2,
631
  Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2,
632
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2,
633
  Convert__GPR32AsmReg1_0__imm_95_31,
634
  CVT_NUM_SIGNATURES
635
};
636
637
} // end anonymous namespace
638
639
static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][11] = {
640
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1
641
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
642
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1
643
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
644
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1
645
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
646
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1
647
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
648
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1
649
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
650
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1
651
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
652
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
653
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
654
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2
655
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
656
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2
657
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done },
658
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
659
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
660
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
661
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
662
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1
663
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
664
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2
665
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done },
666
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1
667
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
668
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1
669
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
670
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2
671
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
672
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2
673
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
674
  // Convert__SImm161_1
675
  { CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
676
  // Convert__Reg1_0__SImm161_1
677
  { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
678
  // Convert__Reg1_0__SImm161_2
679
  { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
680
  // Convert__Reg1_0__Reg1_1__SImm161_2
681
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
682
  // Convert__Reg1_0__Tie0_1_1__SImm161_1
683
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
684
  // Convert__GPR32AsmReg1_0__Simm19_Lsl21_1
685
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
686
  // Convert__GPRMM16AsmReg1_0__Imm1_1
687
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
688
  // Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1
689
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
690
  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2
691
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
692
  // Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1
693
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_, 2, CVT_Done },
694
  // Convert__Imm1_0
695
  { CVT_95_addImmOperands, 1, CVT_Done },
696
  // Convert__Reg1_0__Reg1_1__Reg1_2
697
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
698
  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2
699
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addGPRMM16AsmRegOperands, 3, CVT_Done },
700
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2
701
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
702
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3
703
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
704
  // Convert__GPR32AsmReg1_0__SImm161_1
705
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
706
  // Convert__Reg1_0__Tie0_1_1__Reg1_1
707
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
708
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1
709
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
710
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1
711
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
712
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2
713
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
714
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2
715
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
716
  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1
717
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
718
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2
719
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
720
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1
721
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done },
722
  // Convert__regZERO__regZERO__JumpTarget1_0
723
  { CVT_regZERO, 0, CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done },
724
  // Convert__JumpTarget1_0
725
  { CVT_95_addImmOperands, 1, CVT_Done },
726
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1
727
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
728
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2
729
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },
730
  // Convert__regZERO__JumpTarget1_0
731
  { CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done },
732
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1
733
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done },
734
  // Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2
735
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
736
  // Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2
737
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
738
  // Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2
739
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
740
  // Convert__FGR64AsmReg1_0__JumpTarget1_1
741
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
742
  // Convert__regFCC0__JumpTarget1_0
743
  { CVT_regFCC0, 0, CVT_95_addImmOperands, 1, CVT_Done },
744
  // Convert__FCCAsmReg1_0__JumpTarget1_1
745
  { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
746
  // Convert__COP2AsmReg1_0__JumpTarget1_1
747
  { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
748
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2
749
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
750
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2
751
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
752
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2
753
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
754
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2
755
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
756
  // Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2
757
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
758
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2
759
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
760
  // Convert__Reg1_0__JumpTarget1_1
761
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
762
  // Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1
763
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addImmOperands, 2, CVT_Done },
764
  // Convert__GPRMM16AsmReg1_0__JumpTarget1_1
765
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
766
  // Convert__GPR32AsmReg1_0__JumpTarget1_1
767
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
768
  // Convert__GPR64AsmReg1_0__JumpTarget1_1
769
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
770
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2
771
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done },
772
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2
773
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
774
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2
775
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
776
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2
777
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
778
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2
779
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
780
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2
781
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
782
  // Convert__MSA128AsmReg1_0__JumpTarget1_1
783
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
784
  // Convert__imm_95_0__imm_95_0
785
  { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
786
  // Convert_NoOperands
787
  { CVT_Done },
788
  // Convert__ConstantUImm10_01_0__imm_95_0
789
  { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_imm_95_0, 0, CVT_Done },
790
  // Convert__ConstantUImm10_01_0__ConstantUImm10_01_1
791
  { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
792
  // Convert__ConstantUImm4_01_0
793
  { CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 1, CVT_Done },
794
  // Convert__SImm161_0
795
  { CVT_95_addSImmOperands_LT_16_GT_, 1, CVT_Done },
796
  // Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1
797
  { CVT_regFCC0, 0, CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
798
  // Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1
799
  { CVT_regFCC0, 0, CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
800
  // Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2
801
  { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done },
802
  // Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
803
  { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
804
  // Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1
805
  { CVT_regFCC0, 0, CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
806
  // Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
807
  { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
808
  // Convert__MemOffsetSimm92_1__ConstantUImm5_01_0
809
  { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
810
  // Convert__Mem2_1__ConstantUImm5_01_0
811
  { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
812
  // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1
813
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
814
  // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1
815
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
816
  // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1
817
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
818
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2
819
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
820
  // Convert__GPR32AsmReg1_0__CCRAsmReg1_1
821
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCCRAsmRegOperands, 2, CVT_Done },
822
  // Convert__GPR32AsmReg1_0__COP2AsmReg1_1
823
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_Done },
824
  // Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1
825
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSACtrlAsmRegOperands, 2, CVT_Done },
826
  // Convert__GPR32AsmReg1_0__FGR32AsmReg1_1
827
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
828
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2
829
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
830
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2
831
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
832
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3
833
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done },
834
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3
835
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done },
836
  // Convert__Reg1_0__Reg1_1
837
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
838
  // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
839
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
840
  // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3
841
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
842
  // Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3
843
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
844
  // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3
845
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
846
  // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3
847
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
848
  // Convert__CCRAsmReg1_1__GPR32AsmReg1_0
849
  { CVT_95_addCCRAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
850
  // Convert__COP2AsmReg1_1__GPR32AsmReg1_0
851
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
852
  // Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1
853
  { CVT_95_addMSACtrlAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
854
  // Convert__FGR32AsmReg1_1__GPR32AsmReg1_0
855
  { CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
856
  // Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1
857
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
858
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1
859
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
860
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2
861
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
862
  // Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2
863
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
864
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3
865
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
866
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2
867
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
868
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1
869
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
870
  // Convert__GPR64AsmReg1_1__GPR64AsmReg1_2
871
  { CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },
872
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3
873
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_, 4, CVT_Done },
874
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3
875
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
876
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3
877
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
878
  // Convert__regZERO
879
  { CVT_regZERO, 0, CVT_Done },
880
  // Convert__GPR32AsmReg1_0
881
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
882
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1
883
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addImmOperands, 4, CVT_Tied, Tie0_1_1, CVT_Done },
884
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1
885
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
886
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1
887
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
888
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1
889
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
890
  // Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1
891
  { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
892
  // Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1
893
  { CVT_95_addGPR32ZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
894
  // Convert__Reg1_1__Reg1_2
895
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
896
  // Convert__GPR32AsmReg1_1__GPR32AsmReg1_2
897
  { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
898
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2
899
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
900
  // Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
901
  { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
902
  // Convert__GPR64AsmReg1_0__Imm1_1
903
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
904
  // Convert__GPR64AsmReg1_0__Mem2_1
905
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
906
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3
907
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
908
  // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0
909
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
910
  // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2
911
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
912
  // Convert__GPR64AsmReg1_0__FGR64AsmReg1_1
913
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
914
  // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0
915
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
916
  // Convert__GPR64AsmReg1_0__UImm161_1
917
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
918
  // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2
919
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
920
  // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0
921
  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
922
  // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2
923
  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
924
  // Convert__FGR64AsmReg1_1__GPR64AsmReg1_0
925
  { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
926
  // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0
927
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
928
  // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2
929
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
930
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2
931
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
932
  // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0
933
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
934
  // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1
935
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
936
  // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
937
  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
938
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0
939
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
940
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1
941
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
942
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1
943
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 2, CVT_Done },
944
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2
945
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
946
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1
947
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done },
948
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2
949
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
950
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2
951
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
952
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1
953
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
954
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1
955
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
956
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2
957
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
958
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3
959
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
960
  // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2
961
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
962
  // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2
963
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
964
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1
965
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_Done },
966
  // Convert__MSA128AsmReg1_0__GPR32AsmReg1_1
967
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
968
  // Convert__MSA128AsmReg1_0__GPR64AsmReg1_1
969
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
970
  // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2
971
  { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
972
  // Convert__GPR32AsmReg1_0__ConstantUImm2_01_1
973
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 2, CVT_Done },
974
  // Convert__imm_95_0
975
  { CVT_imm_95_0, 0, CVT_Done },
976
  // Convert__ConstantUImm10_01_0
977
  { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_Done },
978
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1
979
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
980
  // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2
981
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
982
  // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2
983
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR64AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_Done },
984
  // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2
985
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
986
  // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2
987
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Done },
988
  // Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1
989
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
990
  // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6
991
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
992
  // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6
993
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
994
  // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6
995
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
996
  // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6
997
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
998
  // Convert__regRA__GPR32AsmReg1_0
999
  { CVT_regRA, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1000
  // Convert__regRA_64__GPR64AsmReg1_0
1001
  { CVT_regRA_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1002
  // Convert__Reg1_0
1003
  { CVT_95_Reg, 1, CVT_Done },
1004
  // Convert__GPR32AsmReg1_0__imm_95_0
1005
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1006
  // Convert__GPR64AsmReg1_0__imm_95_0
1007
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1008
  // Convert__regZERO__GPR32AsmReg1_0
1009
  { CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1010
  // Convert__GPR64AsmReg1_0
1011
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1012
  // Convert__regZERO_64__GPR64AsmReg1_0
1013
  { CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1014
  // Convert__UImm5Lsl21_0
1015
  { CVT_95_addImmOperands, 1, CVT_Done },
1016
  // Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1
1017
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1018
  // Convert__FGR64AsmReg1_0__MemOffsetSimm162_1
1019
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1020
  // Convert__FGR32AsmReg1_0__MemOffsetSimm162_1
1021
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1022
  // Convert__GPR32AsmReg1_0__Imm1_1
1023
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1024
  // Convert__GPR32AsmReg1_0__Mem2_1
1025
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1026
  // Convert__GPR32AsmReg1_0__MemOffsetSimm162_1
1027
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1028
  // Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1
1029
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1030
  // Convert__GPR32AsmReg1_0__MemOffsetSimm92_1
1031
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1032
  // Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1
1033
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done },
1034
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1035
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1036
  // Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1
1037
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1038
  // Convert__MSA128AsmReg1_0__MemOffsetSimm102_1
1039
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1040
  // Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1
1041
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1042
  // Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1
1043
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1044
  // Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1
1045
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1046
  // Convert__COP2AsmReg1_0__MemOffsetSimm112_1
1047
  { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1048
  // Convert__COP2AsmReg1_0__MemOffsetSimm162_1
1049
  { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1050
  // Convert__COP3AsmReg1_0__Mem2_1
1051
  { CVT_95_addCOP3AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1052
  // Convert__MSA128AsmReg1_0__ConstantSImm10_01_1
1053
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1054
  // Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1
1055
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1056
  // Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1057
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1058
  // Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1059
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1060
  // Convert__GPR32AsmReg1_0__UImm32_Coerced1_1
1061
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_32_GT_, 2, CVT_Done },
1062
  // Convert__StrictlyAFGR64AsmReg1_0__Imm1_1
1063
  { CVT_95_addStrictlyAFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1064
  // Convert__StrictlyFGR64AsmReg1_0__Imm1_1
1065
  { CVT_95_addStrictlyFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1066
  // Convert__StrictlyFGR32AsmReg1_0__Imm1_1
1067
  { CVT_95_addStrictlyFGR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1068
  // Convert__GPRMM16AsmReg1_0__UImm7_N11_1
1069
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_, 2, CVT_Done },
1070
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3
1071
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
1072
  // Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3
1073
  { CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
1074
  // Convert__GPR32AsmReg1_0__UImm161_1
1075
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
1076
  // Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1
1077
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
1078
  // Convert__Reg1_0__Imm1_1__imm_95_0
1079
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1080
  // Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1
1081
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1082
  // Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1
1083
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1084
  // Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1
1085
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1086
  // Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1
1087
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1088
  // Convert__RegList1_0__Mem2_1
1089
  { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1090
  // Convert__RegList161_0__MemOffsetUimm42_1
1091
  { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1092
  // ConvertCustom_ConvertXWPOperands
1093
  { CVT_ConvertXWPOperands, 0, CVT_Done },
1094
  // Convert__GPR32AsmReg1_0__MemOffsetSimm122_1
1095
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1096
  // Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1097
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1098
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3
1099
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_95_addAFGR64AsmRegOperands, 4, CVT_Done },
1100
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3
1101
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_95_addFGR64AsmRegOperands, 4, CVT_Done },
1102
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3
1103
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 4, CVT_Done },
1104
  // Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2
1105
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
1106
  // Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2
1107
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
1108
  // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0
1109
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1110
  // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2
1111
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1112
  // Convert__GPR32AsmReg1_0__FGR64AsmReg1_1
1113
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
1114
  // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0
1115
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1116
  // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2
1117
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1118
  // Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1
1119
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
1120
  // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1
1121
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_Done },
1122
  // Convert__GPR32AsmReg1_0__regAC0
1123
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regAC0, 0, CVT_Done },
1124
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0
1125
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1126
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4
1127
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done },
1128
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO
1129
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_regZERO, 0, CVT_Done },
1130
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64
1131
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_regZERO_64, 0, CVT_Done },
1132
  // Convert__MovePRegPair2_0__GPRMM16AsmRegMoveP1_1__GPRMM16AsmRegMoveP1_2
1133
  { CVT_95_addMovePRegPairOperands, 1, CVT_95_addGPRMM16AsmRegMovePOperands, 2, CVT_95_addGPRMM16AsmRegMovePOperands, 3, CVT_Done },
1134
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1135
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1136
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1137
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1138
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1139
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1140
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1141
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1142
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1143
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1144
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1145
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1146
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1147
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1148
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1149
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1150
  // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0
1151
  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1152
  // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2
1153
  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1154
  // Convert__FGR64AsmReg1_1__GPR32AsmReg1_0
1155
  { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1156
  // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0
1157
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1158
  // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2
1159
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1160
  // Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0
1161
  { CVT_95_addAFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1162
  // Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0
1163
  { CVT_95_addFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1164
  // Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0
1165
  { CVT_95_addHI32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1166
  // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1
1167
  { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_Done },
1168
  // Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0
1169
  { CVT_95_addLO32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1170
  // Convert__regAC0__GPR32AsmReg1_0
1171
  { CVT_regAC0, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1172
  // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0
1173
  { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1174
  // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0
1175
  { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1176
  // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4
1177
  { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done },
1178
  // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
1179
  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1180
  // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0
1181
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1182
  // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1
1183
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1184
  // Convert__regZERO__regZERO__imm_95_0
1185
  { CVT_regZERO, 0, CVT_regZERO, 0, CVT_imm_95_0, 0, CVT_Done },
1186
  // Convert__regZERO__regS0
1187
  { CVT_regZERO, 0, CVT_regS0, 0, CVT_Done },
1188
  // Convert__regZERO__regZERO
1189
  { CVT_regZERO, 0, CVT_regZERO, 0, CVT_Done },
1190
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO
1191
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_Done },
1192
  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1
1193
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Done },
1194
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0
1195
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1196
  // Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0
1197
  { CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
1198
  // Convert__GPR32AsmReg1_0__ConstantUImm7_01_1
1199
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_, 2, CVT_Done },
1200
  // Convert__GPR32AsmReg1_0__ConstantUImm10_01_1
1201
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1202
  // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0
1203
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1204
  // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2
1205
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1206
  // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2
1207
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
1208
  // Convert__GPR32AsmReg1_0__ConstantSImm10_01_1
1209
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1210
  // Convert__GPR32AsmReg1_0__ConstantUImm8_01_1
1211
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 2, CVT_Done },
1212
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1
1213
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done },
1214
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2
1215
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
1216
  // Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1
1217
  { CVT_95_addGPRMM16AsmRegZeroOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done },
1218
  // Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1
1219
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
1220
  // Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1
1221
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
1222
  // Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1
1223
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
1224
  // Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1
1225
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
1226
  // Convert__ConstantUImm20_01_0
1227
  { CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_, 1, CVT_Done },
1228
  // Convert__Reg1_0__Tie0_1_1
1229
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done },
1230
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1
1231
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1232
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2
1233
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done },
1234
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0
1235
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1236
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1
1237
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1238
  // Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1
1239
  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1240
  // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1
1241
  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1242
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2
1243
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
1244
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2
1245
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1246
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3
1247
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done },
1248
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3
1249
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
1250
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3
1251
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
1252
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3
1253
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
1254
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3
1255
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
1256
  // Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2
1257
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
1258
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3
1259
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done },
1260
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3
1261
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
1262
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3
1263
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
1264
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3
1265
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
1266
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3
1267
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
1268
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1
1269
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1270
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2
1271
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1272
  // Convert__ConstantUImm5_01_0
1273
  { CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
1274
  // Convert__MemOffsetSimm162_0
1275
  { CVT_95_addMemOperands, 1, CVT_Done },
1276
  // Convert__imm_95_2
1277
  { CVT_imm_95_2, 0, CVT_Done },
1278
  // Convert__imm_95_6
1279
  { CVT_imm_95_6, 0, CVT_Done },
1280
  // Convert__imm_95_4
1281
  { CVT_imm_95_4, 0, CVT_Done },
1282
  // Convert__imm_95_5
1283
  { CVT_imm_95_5, 0, CVT_Done },
1284
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2
1285
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done },
1286
  // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2
1287
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1288
  // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2
1289
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1290
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2
1291
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1292
  // Convert__GPR32AsmReg1_0__imm_95_31
1293
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_31, 0, CVT_Done },
1294
};
1295
1296
void MipsAsmParser::
1297
convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
1298
36.0k
                const OperandVector &Operands) {
1299
36.0k
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
1300
36.0k
  const uint8_t *Converter = ConversionTable[Kind];
1301
36.0k
  unsigned OpIdx;
1302
36.0k
  Inst.setOpcode(Opcode);
1303
125k
  for (const uint8_t *p = Converter; *p; 
p+= 289.6k
) {
1304
89.6k
    OpIdx = *(p + 1);
1305
89.6k
    switch (*p) {
1306
89.6k
    
default: 0
llvm_unreachable0
("invalid conversion entry!");
1307
89.6k
    case CVT_Reg:
1308
0
      static_cast<MipsOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
1309
0
      break;
1310
89.6k
    case CVT_Tied: {
1311
627
      assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
1312
627
                          std::begin(TiedAsmOperandTable)) &&
1313
627
             "Tied operand not found");
1314
627
      unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];
1315
627
      if (TiedResOpnd != (uint8_t) -1)
1316
627
        Inst.addOperand(Inst.getOperand(TiedResOpnd));
1317
627
      break;
1318
89.6k
    }
1319
89.6k
    case CVT_95_addGPR32AsmRegOperands:
1320
24.1k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32AsmRegOperands(Inst, 1);
1321
24.1k
      break;
1322
89.6k
    case CVT_95_addAFGR64AsmRegOperands:
1323
925
      static_cast<MipsOperand&>(*Operands[OpIdx]).addAFGR64AsmRegOperands(Inst, 1);
1324
925
      break;
1325
89.6k
    case CVT_95_addFGR64AsmRegOperands:
1326
1.27k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addFGR64AsmRegOperands(Inst, 1);
1327
1.27k
      break;
1328
89.6k
    case CVT_95_addFGR32AsmRegOperands:
1329
2.54k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addFGR32AsmRegOperands(Inst, 1);
1330
2.54k
      break;
1331
89.6k
    case CVT_95_addSImmOperands_LT_32_GT_:
1332
636
      static_cast<MipsOperand&>(*Operands[OpIdx]).addSImmOperands<32>(Inst, 1);
1333
636
      break;
1334
89.6k
    case CVT_95_addMSA128AsmRegOperands:
1335
1.40k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addMSA128AsmRegOperands(Inst, 1);
1336
1.40k
      break;
1337
89.6k
    case CVT_95_addSImmOperands_LT_16_GT_:
1338
1.27k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addSImmOperands<16>(Inst, 1);
1339
1.27k
      break;
1340
89.6k
    case CVT_95_Reg:
1341
0
      static_cast<MipsOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
1342
0
      break;
1343
89.6k
    case CVT_95_addImmOperands:
1344
3.56k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
1345
3.56k
      break;
1346
89.6k
    case CVT_95_addGPRMM16AsmRegOperands:
1347
178
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegOperands(Inst, 1);
1348
178
      break;
1349
89.6k
    case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_:
1350
4
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<4, 0>(Inst, 1);
1351
4
      break;
1352
89.6k
    case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_:
1353
475
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 0>(Inst, 1);
1354
475
      break;
1355
89.6k
    case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_:
1356
14
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<2, 0>(Inst, 1);
1357
14
      break;
1358
89.6k
    case CVT_95_addUImmOperands_LT_16_GT_:
1359
231
      static_cast<MipsOperand&>(*Operands[OpIdx]).addUImmOperands<16>(Inst, 1);
1360
231
      break;
1361
89.6k
    case CVT_95_addGPR64AsmRegOperands:
1362
3.95k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR64AsmRegOperands(Inst, 1);
1363
3.95k
      break;
1364
89.6k
    case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_:
1365
15
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<8, 0>(Inst, 1);
1366
15
      break;
1367
89.6k
    case CVT_regZERO:
1368
21.7k
      Inst.addOperand(MCOperand::createReg(Mips::ZERO));
1369
21.7k
      break;
1370
89.6k
    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_:
1371
6
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 32, -32>(Inst, 1);
1372
6
      break;
1373
89.6k
    case CVT_regFCC0:
1374
282
      Inst.addOperand(MCOperand::createReg(Mips::FCC0));
1375
282
      break;
1376
89.6k
    case CVT_95_addFCCAsmRegOperands:
1377
734
      static_cast<MipsOperand&>(*Operands[OpIdx]).addFCCAsmRegOperands(Inst, 1);
1378
734
      break;
1379
89.6k
    case CVT_95_addCOP2AsmRegOperands:
1380
122
      static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP2AsmRegOperands(Inst, 1);
1381
122
      break;
1382
89.6k
    case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_:
1383
155
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<3, 0>(Inst, 1);
1384
155
      break;
1385
89.6k
    case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_:
1386
76
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<6, 0>(Inst, 1);
1387
76
      break;
1388
89.6k
    case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_:
1389
62
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<4, 0>(Inst, 1);
1390
62
      break;
1391
89.6k
    case CVT_imm_95_0:
1392
11.0k
      Inst.addOperand(MCOperand::createImm(0));
1393
11.0k
      break;
1394
89.6k
    case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_:
1395
132
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<10, 0>(Inst, 1);
1396
132
      break;
1397
89.6k
    case CVT_95_addMemOperands:
1398
12.6k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addMemOperands(Inst, 2);
1399
12.6k
      break;
1400
89.6k
    case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_:
1401
20
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<5, 0>(Inst, 1);
1402
20
      break;
1403
89.6k
    case CVT_95_addCCRAsmRegOperands:
1404
38
      static_cast<MipsOperand&>(*Operands[OpIdx]).addCCRAsmRegOperands(Inst, 1);
1405
38
      break;
1406
89.6k
    case CVT_95_addMSACtrlAsmRegOperands:
1407
32
      static_cast<MipsOperand&>(*Operands[OpIdx]).addMSACtrlAsmRegOperands(Inst, 1);
1408
32
      break;
1409
89.6k
    case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_:
1410
53
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<1, 0>(Inst, 1);
1411
53
      break;
1412
89.6k
    case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_:
1413
10
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 33>(Inst, 1);
1414
10
      break;
1415
89.6k
    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_:
1416
20
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 32>(Inst, 1);
1417
20
      break;
1418
89.6k
    case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_:
1419
42
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 1>(Inst, 1);
1420
42
      break;
1421
89.6k
    case CVT_95_addGPR32NonZeroAsmRegOperands:
1422
50
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32NonZeroAsmRegOperands(Inst, 1);
1423
50
      break;
1424
89.6k
    case CVT_95_addGPR32ZeroAsmRegOperands:
1425
16
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32ZeroAsmRegOperands(Inst, 1);
1426
16
      break;
1427
89.6k
    case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_:
1428
12
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<2, 1>(Inst, 1);
1429
12
      break;
1430
89.6k
    case CVT_95_addCOP0AsmRegOperands:
1431
116
      static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP0AsmRegOperands(Inst, 1);
1432
116
      break;
1433
89.6k
    case CVT_regZERO_64:
1434
87
      Inst.addOperand(MCOperand::createReg(Mips::ZERO_64));
1435
87
      break;
1436
89.6k
    case CVT_95_addACC64DSPAsmRegOperands:
1437
180
      static_cast<MipsOperand&>(*Operands[OpIdx]).addACC64DSPAsmRegOperands(Inst, 1);
1438
180
      break;
1439
89.6k
    case CVT_95_addConstantUImmOperands_LT_1_GT_:
1440
4
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<1>(Inst, 1);
1441
4
      break;
1442
89.6k
    case CVT_regRA:
1443
40
      Inst.addOperand(MCOperand::createReg(Mips::RA));
1444
40
      break;
1445
89.6k
    case CVT_regRA_64:
1446
5
      Inst.addOperand(MCOperand::createReg(Mips::RA_64));
1447
5
      break;
1448
89.6k
    case CVT_95_addMicroMipsMemOperands:
1449
50
      static_cast<MipsOperand&>(*Operands[OpIdx]).addMicroMipsMemOperands(Inst, 2);
1450
50
      break;
1451
89.6k
    case CVT_95_addCOP3AsmRegOperands:
1452
6
      static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP3AsmRegOperands(Inst, 1);
1453
6
      break;
1454
89.6k
    case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_:
1455
12
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<10, 0>(Inst, 1);
1456
12
      break;
1457
89.6k
    case CVT_95_addConstantUImmOperands_LT_32_GT_:
1458
206
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<32>(Inst, 1);
1459
206
      break;
1460
89.6k
    case CVT_95_addStrictlyAFGR64AsmRegOperands:
1461
39
      static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyAFGR64AsmRegOperands(Inst, 1);
1462
39
      break;
1463
89.6k
    case CVT_95_addStrictlyFGR64AsmRegOperands:
1464
52
      static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyFGR64AsmRegOperands(Inst, 1);
1465
52
      break;
1466
89.6k
    case CVT_95_addStrictlyFGR32AsmRegOperands:
1467
66
      static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyFGR32AsmRegOperands(Inst, 1);
1468
66
      break;
1469
89.6k
    case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_:
1470
7
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<7, -1>(Inst, 1);
1471
7
      break;
1472
89.6k
    case CVT_95_addRegListOperands:
1473
63
      static_cast<MipsOperand&>(*Operands[OpIdx]).addRegListOperands(Inst, 1);
1474
63
      break;
1475
89.6k
    case CVT_ConvertXWPOperands:
1476
14
      ConvertXWPOperands(Inst, Operands);
1477
14
      break;
1478
89.6k
    case CVT_regAC0:
1479
4
      Inst.addOperand(MCOperand::createReg(Mips::AC0));
1480
4
      break;
1481
89.6k
    case CVT_95_addMovePRegPairOperands:
1482
4
      static_cast<MipsOperand&>(*Operands[OpIdx]).addMovePRegPairOperands(Inst, 2);
1483
4
      break;
1484
89.6k
    case CVT_95_addGPRMM16AsmRegMovePOperands:
1485
8
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegMovePOperands(Inst, 1);
1486
8
      break;
1487
89.6k
    case CVT_95_addHI32DSPAsmRegOperands:
1488
3
      static_cast<MipsOperand&>(*Operands[OpIdx]).addHI32DSPAsmRegOperands(Inst, 1);
1489
3
      break;
1490
89.6k
    case CVT_95_addLO32DSPAsmRegOperands:
1491
3
      static_cast<MipsOperand&>(*Operands[OpIdx]).addLO32DSPAsmRegOperands(Inst, 1);
1492
3
      break;
1493
89.6k
    case CVT_regS0:
1494
2
      Inst.addOperand(MCOperand::createReg(Mips::S0));
1495
2
      break;
1496
89.6k
    case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_:
1497
5
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<7, 0>(Inst, 1);
1498
5
      break;
1499
89.6k
    case CVT_95_addHWRegsAsmRegOperands:
1500
60
      static_cast<MipsOperand&>(*Operands[OpIdx]).addHWRegsAsmRegOperands(Inst, 1);
1501
60
      break;
1502
89.6k
    case CVT_95_addGPRMM16AsmRegZeroOperands:
1503
22
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegZeroOperands(Inst, 1);
1504
22
      break;
1505
89.6k
    case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_:
1506
25
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<20, 0>(Inst, 1);
1507
25
      break;
1508
89.6k
    case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_:
1509
6
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<6, 0>(Inst, 1);
1510
6
      break;
1511
89.6k
    case CVT_imm_95_2:
1512
1
      Inst.addOperand(MCOperand::createImm(2));
1513
1
      break;
1514
89.6k
    case CVT_imm_95_6:
1515
1
      Inst.addOperand(MCOperand::createImm(6));
1516
1
      break;
1517
89.6k
    case CVT_imm_95_4:
1518
1
      Inst.addOperand(MCOperand::createImm(4));
1519
1
      break;
1520
89.6k
    case CVT_imm_95_5:
1521
1
      Inst.addOperand(MCOperand::createImm(5));
1522
1
      break;
1523
89.6k
    case CVT_imm_95_31:
1524
4
      Inst.addOperand(MCOperand::createImm(31));
1525
4
      break;
1526
89.6k
    }
1527
89.6k
  }
1528
36.0k
}
1529
1530
void MipsAsmParser::
1531
convertToMapAndConstraints(unsigned Kind,
1532
0
                           const OperandVector &Operands) {
1533
0
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
1534
0
  unsigned NumMCOperands = 0;
1535
0
  const uint8_t *Converter = ConversionTable[Kind];
1536
0
  for (const uint8_t *p = Converter; *p; p+= 2) {
1537
0
    switch (*p) {
1538
0
    default: llvm_unreachable("invalid conversion entry!");
1539
0
    case CVT_Reg:
1540
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1541
0
      Operands[*(p + 1)]->setConstraint("r");
1542
0
      ++NumMCOperands;
1543
0
      break;
1544
0
    case CVT_Tied:
1545
0
      ++NumMCOperands;
1546
0
      break;
1547
0
    case CVT_95_addGPR32AsmRegOperands:
1548
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1549
0
      Operands[*(p + 1)]->setConstraint("m");
1550
0
      NumMCOperands += 1;
1551
0
      break;
1552
0
    case CVT_95_addAFGR64AsmRegOperands:
1553
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1554
0
      Operands[*(p + 1)]->setConstraint("m");
1555
0
      NumMCOperands += 1;
1556
0
      break;
1557
0
    case CVT_95_addFGR64AsmRegOperands:
1558
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1559
0
      Operands[*(p + 1)]->setConstraint("m");
1560
0
      NumMCOperands += 1;
1561
0
      break;
1562
0
    case CVT_95_addFGR32AsmRegOperands:
1563
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1564
0
      Operands[*(p + 1)]->setConstraint("m");
1565
0
      NumMCOperands += 1;
1566
0
      break;
1567
0
    case CVT_95_addSImmOperands_LT_32_GT_:
1568
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1569
0
      Operands[*(p + 1)]->setConstraint("m");
1570
0
      NumMCOperands += 1;
1571
0
      break;
1572
0
    case CVT_95_addMSA128AsmRegOperands:
1573
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1574
0
      Operands[*(p + 1)]->setConstraint("m");
1575
0
      NumMCOperands += 1;
1576
0
      break;
1577
0
    case CVT_95_addSImmOperands_LT_16_GT_:
1578
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1579
0
      Operands[*(p + 1)]->setConstraint("m");
1580
0
      NumMCOperands += 1;
1581
0
      break;
1582
0
    case CVT_95_Reg:
1583
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1584
0
      Operands[*(p + 1)]->setConstraint("r");
1585
0
      NumMCOperands += 1;
1586
0
      break;
1587
0
    case CVT_95_addImmOperands:
1588
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1589
0
      Operands[*(p + 1)]->setConstraint("m");
1590
0
      NumMCOperands += 1;
1591
0
      break;
1592
0
    case CVT_95_addGPRMM16AsmRegOperands:
1593
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1594
0
      Operands[*(p + 1)]->setConstraint("m");
1595
0
      NumMCOperands += 1;
1596
0
      break;
1597
0
    case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_:
1598
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1599
0
      Operands[*(p + 1)]->setConstraint("m");
1600
0
      NumMCOperands += 1;
1601
0
      break;
1602
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_:
1603
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1604
0
      Operands[*(p + 1)]->setConstraint("m");
1605
0
      NumMCOperands += 1;
1606
0
      break;
1607
0
    case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_:
1608
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1609
0
      Operands[*(p + 1)]->setConstraint("m");
1610
0
      NumMCOperands += 1;
1611
0
      break;
1612
0
    case CVT_95_addUImmOperands_LT_16_GT_:
1613
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1614
0
      Operands[*(p + 1)]->setConstraint("m");
1615
0
      NumMCOperands += 1;
1616
0
      break;
1617
0
    case CVT_95_addGPR64AsmRegOperands:
1618
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1619
0
      Operands[*(p + 1)]->setConstraint("m");
1620
0
      NumMCOperands += 1;
1621
0
      break;
1622
0
    case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_:
1623
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1624
0
      Operands[*(p + 1)]->setConstraint("m");
1625
0
      NumMCOperands += 1;
1626
0
      break;
1627
0
    case CVT_regZERO:
1628
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1629
0
      Operands[*(p + 1)]->setConstraint("m");
1630
0
      ++NumMCOperands;
1631
0
      break;
1632
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_:
1633
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1634
0
      Operands[*(p + 1)]->setConstraint("m");
1635
0
      NumMCOperands += 1;
1636
0
      break;
1637
0
    case CVT_regFCC0:
1638
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1639
0
      Operands[*(p + 1)]->setConstraint("m");
1640
0
      ++NumMCOperands;
1641
0
      break;
1642
0
    case CVT_95_addFCCAsmRegOperands:
1643
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1644
0
      Operands[*(p + 1)]->setConstraint("m");
1645
0
      NumMCOperands += 1;
1646
0
      break;
1647
0
    case CVT_95_addCOP2AsmRegOperands:
1648
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1649
0
      Operands[*(p + 1)]->setConstraint("m");
1650
0
      NumMCOperands += 1;
1651
0
      break;
1652
0
    case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_:
1653
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1654
0
      Operands[*(p + 1)]->setConstraint("m");
1655
0
      NumMCOperands += 1;
1656
0
      break;
1657
0
    case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_:
1658
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1659
0
      Operands[*(p + 1)]->setConstraint("m");
1660
0
      NumMCOperands += 1;
1661
0
      break;
1662
0
    case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_:
1663
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1664
0
      Operands[*(p + 1)]->setConstraint("m");
1665
0
      NumMCOperands += 1;
1666
0
      break;
1667
0
    case CVT_imm_95_0:
1668
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1669
0
      Operands[*(p + 1)]->setConstraint("");
1670
0
      ++NumMCOperands;
1671
0
      break;
1672
0
    case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_:
1673
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1674
0
      Operands[*(p + 1)]->setConstraint("m");
1675
0
      NumMCOperands += 1;
1676
0
      break;
1677
0
    case CVT_95_addMemOperands:
1678
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1679
0
      Operands[*(p + 1)]->setConstraint("m");
1680
0
      NumMCOperands += 2;
1681
0
      break;
1682
0
    case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_:
1683
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1684
0
      Operands[*(p + 1)]->setConstraint("m");
1685
0
      NumMCOperands += 1;
1686
0
      break;
1687
0
    case CVT_95_addCCRAsmRegOperands:
1688
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1689
0
      Operands[*(p + 1)]->setConstraint("m");
1690
0
      NumMCOperands += 1;
1691
0
      break;
1692
0
    case CVT_95_addMSACtrlAsmRegOperands:
1693
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1694
0
      Operands[*(p + 1)]->setConstraint("m");
1695
0
      NumMCOperands += 1;
1696
0
      break;
1697
0
    case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_:
1698
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1699
0
      Operands[*(p + 1)]->setConstraint("m");
1700
0
      NumMCOperands += 1;
1701
0
      break;
1702
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_:
1703
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1704
0
      Operands[*(p + 1)]->setConstraint("m");
1705
0
      NumMCOperands += 1;
1706
0
      break;
1707
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_:
1708
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1709
0
      Operands[*(p + 1)]->setConstraint("m");
1710
0
      NumMCOperands += 1;
1711
0
      break;
1712
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_:
1713
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1714
0
      Operands[*(p + 1)]->setConstraint("m");
1715
0
      NumMCOperands += 1;
1716
0
      break;
1717
0
    case CVT_95_addGPR32NonZeroAsmRegOperands:
1718
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1719
0
      Operands[*(p + 1)]->setConstraint("m");
1720
0
      NumMCOperands += 1;
1721
0
      break;
1722
0
    case CVT_95_addGPR32ZeroAsmRegOperands:
1723
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1724
0
      Operands[*(p + 1)]->setConstraint("m");
1725
0
      NumMCOperands += 1;
1726
0
      break;
1727
0
    case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_:
1728
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1729
0
      Operands[*(p + 1)]->setConstraint("m");
1730
0
      NumMCOperands += 1;
1731
0
      break;
1732
0
    case CVT_95_addCOP0AsmRegOperands:
1733
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1734
0
      Operands[*(p + 1)]->setConstraint("m");
1735
0
      NumMCOperands += 1;
1736
0
      break;
1737
0
    case CVT_regZERO_64:
1738
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1739
0
      Operands[*(p + 1)]->setConstraint("m");
1740
0
      ++NumMCOperands;
1741
0
      break;
1742
0
    case CVT_95_addACC64DSPAsmRegOperands:
1743
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1744
0
      Operands[*(p + 1)]->setConstraint("m");
1745
0
      NumMCOperands += 1;
1746
0
      break;
1747
0
    case CVT_95_addConstantUImmOperands_LT_1_GT_:
1748
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1749
0
      Operands[*(p + 1)]->setConstraint("m");
1750
0
      NumMCOperands += 1;
1751
0
      break;
1752
0
    case CVT_regRA:
1753
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1754
0
      Operands[*(p + 1)]->setConstraint("m");
1755
0
      ++NumMCOperands;
1756
0
      break;
1757
0
    case CVT_regRA_64:
1758
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1759
0
      Operands[*(p + 1)]->setConstraint("m");
1760
0
      ++NumMCOperands;
1761
0
      break;
1762
0
    case CVT_95_addMicroMipsMemOperands:
1763
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1764
0
      Operands[*(p + 1)]->setConstraint("m");
1765
0
      NumMCOperands += 2;
1766
0
      break;
1767
0
    case CVT_95_addCOP3AsmRegOperands:
1768
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1769
0
      Operands[*(p + 1)]->setConstraint("m");
1770
0
      NumMCOperands += 1;
1771
0
      break;
1772
0
    case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_:
1773
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1774
0
      Operands[*(p + 1)]->setConstraint("m");
1775
0
      NumMCOperands += 1;
1776
0
      break;
1777
0
    case CVT_95_addConstantUImmOperands_LT_32_GT_:
1778
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1779
0
      Operands[*(p + 1)]->setConstraint("m");
1780
0
      NumMCOperands += 1;
1781
0
      break;
1782
0
    case CVT_95_addStrictlyAFGR64AsmRegOperands:
1783
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1784
0
      Operands[*(p + 1)]->setConstraint("m");
1785
0
      NumMCOperands += 1;
1786
0
      break;
1787
0
    case CVT_95_addStrictlyFGR64AsmRegOperands:
1788
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1789
0
      Operands[*(p + 1)]->setConstraint("m");
1790
0
      NumMCOperands += 1;
1791
0
      break;
1792
0
    case CVT_95_addStrictlyFGR32AsmRegOperands:
1793
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1794
0
      Operands[*(p + 1)]->setConstraint("m");
1795
0
      NumMCOperands += 1;
1796
0
      break;
1797
0
    case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_:
1798
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1799
0
      Operands[*(p + 1)]->setConstraint("m");
1800
0
      NumMCOperands += 1;
1801
0
      break;
1802
0
    case CVT_95_addRegListOperands:
1803
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1804
0
      Operands[*(p + 1)]->setConstraint("m");
1805
0
      NumMCOperands += 1;
1806
0
      break;
1807
0
    case CVT_regAC0:
1808
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1809
0
      Operands[*(p + 1)]->setConstraint("m");
1810
0
      ++NumMCOperands;
1811
0
      break;
1812
0
    case CVT_95_addMovePRegPairOperands:
1813
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1814
0
      Operands[*(p + 1)]->setConstraint("m");
1815
0
      NumMCOperands += 2;
1816
0
      break;
1817
0
    case CVT_95_addGPRMM16AsmRegMovePOperands:
1818
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1819
0
      Operands[*(p + 1)]->setConstraint("m");
1820
0
      NumMCOperands += 1;
1821
0
      break;
1822
0
    case CVT_95_addHI32DSPAsmRegOperands:
1823
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1824
0
      Operands[*(p + 1)]->setConstraint("m");
1825
0
      NumMCOperands += 1;
1826
0
      break;
1827
0
    case CVT_95_addLO32DSPAsmRegOperands:
1828
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1829
0
      Operands[*(p + 1)]->setConstraint("m");
1830
0
      NumMCOperands += 1;
1831
0
      break;
1832
0
    case CVT_regS0:
1833
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1834
0
      Operands[*(p + 1)]->setConstraint("m");
1835
0
      ++NumMCOperands;
1836
0
      break;
1837
0
    case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_:
1838
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1839
0
      Operands[*(p + 1)]->setConstraint("m");
1840
0
      NumMCOperands += 1;
1841
0
      break;
1842
0
    case CVT_95_addHWRegsAsmRegOperands:
1843
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1844
0
      Operands[*(p + 1)]->setConstraint("m");
1845
0
      NumMCOperands += 1;
1846
0
      break;
1847
0
    case CVT_95_addGPRMM16AsmRegZeroOperands:
1848
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1849
0
      Operands[*(p + 1)]->setConstraint("m");
1850
0
      NumMCOperands += 1;
1851
0
      break;
1852
0
    case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_:
1853
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1854
0
      Operands[*(p + 1)]->setConstraint("m");
1855
0
      NumMCOperands += 1;
1856
0
      break;
1857
0
    case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_:
1858
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1859
0
      Operands[*(p + 1)]->setConstraint("m");
1860
0
      NumMCOperands += 1;
1861
0
      break;
1862
0
    case CVT_imm_95_2:
1863
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1864
0
      Operands[*(p + 1)]->setConstraint("");
1865
0
      ++NumMCOperands;
1866
0
      break;
1867
0
    case CVT_imm_95_6:
1868
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1869
0
      Operands[*(p + 1)]->setConstraint("");
1870
0
      ++NumMCOperands;
1871
0
      break;
1872
0
    case CVT_imm_95_4:
1873
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1874
0
      Operands[*(p + 1)]->setConstraint("");
1875
0
      ++NumMCOperands;
1876
0
      break;
1877
0
    case CVT_imm_95_5:
1878
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1879
0
      Operands[*(p + 1)]->setConstraint("");
1880
0
      ++NumMCOperands;
1881
0
      break;
1882
0
    case CVT_imm_95_31:
1883
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1884
0
      Operands[*(p + 1)]->setConstraint("");
1885
0
      ++NumMCOperands;
1886
0
      break;
1887
0
    }
1888
0
  }
1889
0
}
1890
1891
namespace {
1892
1893
/// MatchClassKind - The kinds of classes which participate in
1894
/// instruction matching.
1895
enum MatchClassKind {
1896
  InvalidMatchClass = 0,
1897
  OptionalMatchClass = 1,
1898
  MCK__35_, // '#'
1899
  MCK__40_, // '('
1900
  MCK__41_, // ')'
1901
  MCK_0, // '0'
1902
  MCK_16, // '16'
1903
  MCK__91_, // '['
1904
  MCK__93_, // ']'
1905
  MCK_bit, // 'bit'
1906
  MCK_inst, // 'inst'
1907
  MCK_LAST_TOKEN = MCK_inst,
1908
  MCK_Reg29, // derived register class
1909
  MCK_Reg15, // derived register class
1910
  MCK_ACC128, // register class 'ACC128'
1911
  MCK_ACC64, // register class 'ACC64'
1912
  MCK_CPURAReg, // register class 'CPURAReg,RA'
1913
  MCK_CPUSPReg, // register class 'CPUSPReg,SP32,SP'
1914
  MCK_DSPCC, // register class 'DSPCC'
1915
  MCK_GP32, // register class 'GP32'
1916
  MCK_GP64, // register class 'GP64'
1917
  MCK_GPR32ZERO, // register class 'GPR32ZERO,ZERO'
1918
  MCK_HI32, // register class 'HI32'
1919
  MCK_HI64, // register class 'HI64'
1920
  MCK_LO32, // register class 'LO32'
1921
  MCK_LO64, // register class 'LO64'
1922
  MCK_PC, // register class 'PC'
1923
  MCK_SP64, // register class 'SP64'
1924
  MCK_Reg26, // derived register class
1925
  MCK_Reg11, // derived register class
1926
  MCK_OCTEON_MPL, // register class 'OCTEON_MPL'
1927
  MCK_OCTEON_P, // register class 'OCTEON_P'
1928
  MCK_Reg24, // derived register class
1929
  MCK_Reg19, // derived register class
1930
  MCK_Reg9, // derived register class
1931
  MCK_Reg4, // derived register class
1932
  MCK_ACC64DSP, // register class 'ACC64DSP'
1933
  MCK_HI32DSP, // register class 'HI32DSP'
1934
  MCK_LO32DSP, // register class 'LO32DSP'
1935
  MCK_Reg25, // derived register class
1936
  MCK_Reg23, // derived register class
1937
  MCK_Reg10, // derived register class
1938
  MCK_Reg8, // derived register class
1939
  MCK_Reg36, // derived register class
1940
  MCK_Reg21, // derived register class
1941
  MCK_Reg18, // derived register class
1942
  MCK_Reg17, // derived register class
1943
  MCK_CPU16Regs, // register class 'CPU16Regs,GPRMM16'
1944
  MCK_FCC, // register class 'FCC'
1945
  MCK_GPRMM16MoveP, // register class 'GPRMM16MoveP'
1946
  MCK_GPRMM16Zero, // register class 'GPRMM16Zero'
1947
  MCK_MSACtrl, // register class 'MSACtrl'
1948
  MCK_Reg22, // derived register class
1949
  MCK_CPU16RegsPlusSP, // register class 'CPU16RegsPlusSP'
1950
  MCK_Reg42, // derived register class
1951
  MCK_Reg39, // derived register class
1952
  MCK_Reg34, // derived register class
1953
  MCK_Reg31, // derived register class
1954
  MCK_AFGR64, // register class 'AFGR64'
1955
  MCK_MSA128WEvens, // register class 'MSA128WEvens'
1956
  MCK_Reg37, // derived register class
1957
  MCK_Reg20, // derived register class
1958
  MCK_GPR32NONZERO, // register class 'GPR32NONZERO'
1959
  MCK_CCR, // register class 'CCR'
1960
  MCK_COP0, // register class 'COP0'
1961
  MCK_COP2, // register class 'COP2'
1962
  MCK_COP3, // register class 'COP3'
1963
  MCK_DSPR, // register class 'DSPR,GPR32'
1964
  MCK_FGR32, // register class 'FGR32,FGRCC'
1965
  MCK_FGR64, // register class 'FGR64'
1966
  MCK_FGRH32, // register class 'FGRH32'
1967
  MCK_GPR64, // register class 'GPR64'
1968
  MCK_HWRegs, // register class 'HWRegs'
1969
  MCK_MSA128F16, // register class 'MSA128F16,MSA128B,MSA128D,MSA128H,MSA128W'
1970
  MCK_OddSP, // register class 'OddSP'
1971
  MCK_LAST_REGISTER = MCK_OddSP,
1972
  MCK_ACC64DSPAsmReg, // user defined class 'ACC64DSPAsmOperand'
1973
  MCK_AFGR64AsmReg, // user defined class 'AFGR64AsmOperand'
1974
  MCK_CCRAsmReg, // user defined class 'CCRAsmOperand'
1975
  MCK_COP0AsmReg, // user defined class 'COP0AsmOperand'
1976
  MCK_COP2AsmReg, // user defined class 'COP2AsmOperand'
1977
  MCK_COP3AsmReg, // user defined class 'COP3AsmOperand'
1978
  MCK_FCCAsmReg, // user defined class 'FCCRegsAsmOperand'
1979
  MCK_FGR32AsmReg, // user defined class 'FGR32AsmOperand'
1980
  MCK_FGR64AsmReg, // user defined class 'FGR64AsmOperand'
1981
  MCK_FGRH32AsmReg, // user defined class 'FGRH32AsmOperand'
1982
  MCK_GPR32AsmReg, // user defined class 'GPR32AsmOperand'
1983
  MCK_GPR32NonZeroAsmReg, // user defined class 'GPR32NonZeroAsmOperand'
1984
  MCK_GPR32ZeroAsmReg, // user defined class 'GPR32ZeroAsmOperand'
1985
  MCK_GPR64AsmReg, // user defined class 'GPR64AsmOperand'
1986
  MCK_GPRMM16AsmReg, // user defined class 'GPRMM16AsmOperand'
1987
  MCK_GPRMM16AsmRegMoveP, // user defined class 'GPRMM16AsmOperandMoveP'
1988
  MCK_GPRMM16AsmRegZero, // user defined class 'GPRMM16AsmOperandZero'
1989
  MCK_HI32DSPAsmReg, // user defined class 'HI32DSPAsmOperand'
1990
  MCK_HWRegsAsmReg, // user defined class 'HWRegsAsmOperand'
1991
  MCK_Imm, // user defined class 'ImmAsmOperand'
1992
  MCK_LO32DSPAsmReg, // user defined class 'LO32DSPAsmOperand'
1993
  MCK_MSA128AsmReg, // user defined class 'MSA128AsmOperand'
1994
  MCK_MSACtrlAsmReg, // user defined class 'MSACtrlAsmOperand'
1995
  MCK_MicroMipsMemGP, // user defined class 'MicroMipsMemGPAsmOperand'
1996
  MCK_MicroMipsMem, // user defined class 'MicroMipsMemGPRMM16AsmOperand'
1997
  MCK_MicroMipsMemSP, // user defined class 'MicroMipsMemSPAsmOperand'
1998
  MCK_InvNum, // user defined class 'MipsInvertedImmoperand'
1999
  MCK_JumpTarget, // user defined class 'MipsJumpTargetAsmOperand'
2000
  MCK_MemOffsetSimm10, // user defined class 'MipsMemSimm10AsmOperand'
2001
  MCK_MemOffsetSimm10_1, // user defined class 'MipsMemSimm10Lsl1AsmOperand'
2002
  MCK_MemOffsetSimm10_2, // user defined class 'MipsMemSimm10Lsl2AsmOperand'
2003
  MCK_MemOffsetSimm10_3, // user defined class 'MipsMemSimm10Lsl3AsmOperand'
2004
  MCK_MemOffsetSimm11, // user defined class 'MipsMemSimm11AsmOperand'
2005
  MCK_MemOffsetSimm12, // user defined class 'MipsMemSimm12AsmOperand'
2006
  MCK_MemOffsetSimm16, // user defined class 'MipsMemSimm16AsmOperand'
2007
  MCK_MemOffsetSimm9, // user defined class 'MipsMemSimm9AsmOperand'
2008
  MCK_MemOffsetSimmPtr, // user defined class 'MipsMemSimmPtrAsmOperand'
2009
  MCK_MemOffsetUimm4, // user defined class 'MipsMemUimm4AsmOperand'
2010
  MCK_Mem, // user defined class 'MipsMemAsmOperand'
2011
  MCK_MovePRegPair, // user defined class 'MovePRegPairAsmOperand'
2012
  MCK_RegList16, // user defined class 'RegList16AsmOperand'
2013
  MCK_RegList, // user defined class 'RegListAsmOperand'
2014
  MCK_Simm19_Lsl2, // user defined class 'Simm19Lsl2AsmOperand'
2015
  MCK_StrictlyAFGR64AsmReg, // user defined class 'StrictlyAFGR64AsmOperand'
2016
  MCK_StrictlyFGR32AsmReg, // user defined class 'StrictlyFGR32AsmOperand'
2017
  MCK_StrictlyFGR64AsmReg, // user defined class 'StrictlyFGR64AsmOperand'
2018
  MCK_ConstantImmz, // user defined class 'ConstantImmzAsmOperandClass'
2019
  MCK_ConstantUImm1_0, // user defined class 'ConstantUImm1AsmOperandClass'
2020
  MCK_ConstantUImm2_0, // user defined class 'ConstantUImm2AsmOperandClass'
2021
  MCK_ConstantUImm2_1, // user defined class 'ConstantUImm2Plus1AsmOperandClass'
2022
  MCK_ConstantUImm3_0, // user defined class 'ConstantUImm3AsmOperandClass'
2023
  MCK_ConstantSImm4_0, // user defined class 'ConstantSImm4AsmOperandClass'
2024
  MCK_ConstantUImm4_0, // user defined class 'ConstantUImm4AsmOperandClass'
2025
  MCK_ConstantSImm5_0, // user defined class 'ConstantSImm5AsmOperandClass'
2026
  MCK_ConstantUImm5_0, // user defined class 'ConstantUImm5AsmOperandClass'
2027
  MCK_ConstantUImm5_1, // user defined class 'ConstantUImm5Plus1AsmOperandClass'
2028
  MCK_ConstantUImm5_Plus1_Report_UImm6, // user defined class 'ConstantUImm5Plus1ReportUImm6AsmOperandClass'
2029
  MCK_ConstantUImm5_32_Norm, // user defined class 'ConstantUImm5Plus32NormalizeAsmOperandClass'
2030
  MCK_ConstantUImm5_32, // user defined class 'ConstantUImm5Plus32AsmOperandClass'
2031
  MCK_ConstantUImm5_0_Report_UImm6, // user defined class 'ConstantUImm5ReportUImm6AsmOperandClass'
2032
  MCK_ConstantUImm5_33, // user defined class 'ConstantUImm5Plus33AsmOperandClass'
2033
  MCK_ConstantUImmRange2_64, // user defined class 'ConstantUImm5_Range2_64AsmOperandClass'
2034
  MCK_UImm5Lsl2, // user defined class 'ConstantUImm5Lsl2AsmOperandClass'
2035
  MCK_ConstantSImm6_0, // user defined class 'ConstantSImm6AsmOperandClass'
2036
  MCK_ConstantUImm6_0, // user defined class 'ConstantUImm6AsmOperandClass'
2037
  MCK_UImm6Lsl2, // user defined class 'ConstantUImm6Lsl2AsmOperandClass'
2038
  MCK_ConstantUImm7_0, // user defined class 'ConstantUImm7AsmOperandClass'
2039
  MCK_UImm7_N1, // user defined class 'ConstantUImm7Sub1AsmOperandClass'
2040
  MCK_ConstantUImm8_0, // user defined class 'ConstantUImm8AsmOperandClass'
2041
  MCK_SImm7Lsl2, // user defined class 'ConstantSImm7Lsl2AsmOperandClass'
2042
  MCK_ConstantSImm9_0, // user defined class 'ConstantSImm9AsmOperandClass'
2043
  MCK_ConstantSImm10_0, // user defined class 'ConstantSImm10AsmOperandClass'
2044
  MCK_ConstantUImm10_0, // user defined class 'ConstantUImm10AsmOperandClass'
2045
  MCK_SImm10Lsl1, // user defined class 'ConstantSImm10Lsl1AsmOperandClass'
2046
  MCK_ConstantSImm11_0, // user defined class 'ConstantSImm11AsmOperandClass'
2047
  MCK_SImm10Lsl2, // user defined class 'ConstantSImm10Lsl2AsmOperandClass'
2048
  MCK_SImm10Lsl3, // user defined class 'ConstantSImm10Lsl3AsmOperandClass'
2049
  MCK_SImm16, // user defined class 'SImm16AsmOperandClass'
2050
  MCK_SImm16_Relaxed, // user defined class 'SImm16RelaxedAsmOperandClass'
2051
  MCK_UImm16_AltRelaxed, // user defined class 'UImm16AltRelaxedAsmOperandClass'
2052
  MCK_UImm16, // user defined class 'UImm16AsmOperandClass'
2053
  MCK_SImm19Lsl2, // user defined class 'ConstantSImm19Lsl2AsmOperandClass'
2054
  MCK_UImm16_Relaxed, // user defined class 'UImm16RelaxedAsmOperandClass'
2055
  MCK_ConstantUImm20_0, // user defined class 'ConstantUImm20AsmOperandClass'
2056
  MCK_ConstantUImm26_0, // user defined class 'ConstantUImm26AsmOperandClass'
2057
  MCK_SImm32, // user defined class 'SImm32AsmOperandClass'
2058
  MCK_SImm32_Relaxed, // user defined class 'SImm32RelaxedAsmOperandClass'
2059
  MCK_UImm32_Coerced, // user defined class 'UImm32CoercedAsmOperandClass'
2060
  NumMatchClassKinds
2061
};
2062
2063
}
2064
2065
14.4k
static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
2066
14.4k
  return MCTargetAsmParser::Match_InvalidOperand;
2067
14.4k
}
2068
2069
880
static MatchClassKind matchTokenString(StringRef Name) {
2070
880
  switch (Name.size()) {
2071
880
  
default: break0
;
2072
880
  case 1:  // 6 strings to match.
2073
880
    switch (Name[0]) {
2074
880
    
default: break0
;
2075
880
    case '#':  // 1 string to match.
2076
0
      return MCK__35_;  // "#"
2077
880
    case '(':  // 1 string to match.
2078
363
      return MCK__40_;  // "("
2079
880
    case ')':  // 1 string to match.
2080
363
      return MCK__41_;  // ")"
2081
880
    case '0':  // 1 string to match.
2082
0
      return MCK_0;  // "0"
2083
880
    case '[':  // 1 string to match.
2084
112
      return MCK__91_;  // "["
2085
880
    case ']':  // 1 string to match.
2086
42
      return MCK__93_;  // "]"
2087
0
    }
2088
0
    break;
2089
0
  case 2:  // 1 string to match.
2090
0
    if (memcmp(Name.data()+0, "16", 2) != 0)
2091
0
      break;
2092
0
    return MCK_16;   // "16"
2093
0
  case 3:  // 1 string to match.
2094
0
    if (memcmp(Name.data()+0, "bit", 3) != 0)
2095
0
      break;
2096
0
    return MCK_bit;  // "bit"
2097
0
  case 4:  // 1 string to match.
2098
0
    if (memcmp(Name.data()+0, "inst", 4) != 0)
2099
0
      break;
2100
0
    return MCK_inst;  // "inst"
2101
0
  }
2102
0
  return InvalidMatchClass;
2103
0
}
2104
2105
/// isSubclass - Compute whether \p A is a subclass of \p B.
2106
39.6k
static bool isSubclass(MatchClassKind A, MatchClassKind B) {
2107
39.6k
  if (A == B)
2108
1.00k
    return true;
2109
38.6k
2110
38.6k
  switch (A) {
2111
38.6k
  default:
2112
24.2k
    return false;
2113
38.6k
2114
38.6k
  case MCK_Reg29:
2115
0
    switch (B) {
2116
0
    default: return false;
2117
0
    case MCK_Reg20: return true;
2118
0
    case MCK_GPR64: return true;
2119
0
    }
2120
0
2121
0
  case MCK_Reg15:
2122
0
    switch (B) {
2123
0
    default: return false;
2124
0
    case MCK_Reg19: return true;
2125
0
    case MCK_Reg18: return true;
2126
0
    case MCK_Reg17: return true;
2127
0
    case MCK_GPR64: return true;
2128
0
    }
2129
0
2130
0
  case MCK_ACC64:
2131
0
    return B == MCK_ACC64DSP;
2132
0
2133
133
  case MCK_CPURAReg:
2134
133
    switch (B) {
2135
133
    default: return false;
2136
133
    
case MCK_GPR32NONZERO: return true0
;
2137
133
    
case MCK_DSPR: return true0
;
2138
0
    }
2139
0
2140
546
  case MCK_CPUSPReg:
2141
546
    switch (B) {
2142
546
    default: return false;
2143
546
    
case MCK_CPU16RegsPlusSP: return true0
;
2144
546
    
case MCK_GPR32NONZERO: return true0
;
2145
546
    
case MCK_DSPR: return true0
;
2146
0
    }
2147
0
2148
0
  case MCK_GP32:
2149
0
    switch (B) {
2150
0
    default: return false;
2151
0
    case MCK_GPR32NONZERO: return true;
2152
0
    case MCK_DSPR: return true;
2153
0
    }
2154
0
2155
0
  case MCK_GP64:
2156
0
    switch (B) {
2157
0
    default: return false;
2158
0
    case MCK_Reg20: return true;
2159
0
    case MCK_GPR64: return true;
2160
0
    }
2161
0
2162
351
  case MCK_GPR32ZERO:
2163
351
    switch (B) {
2164
351
    default: return false;
2165
351
    
case MCK_Reg4: return true0
;
2166
351
    
case MCK_GPRMM16MoveP: return true0
;
2167
351
    
case MCK_GPRMM16Zero: return true0
;
2168
351
    
case MCK_DSPR: return true0
;
2169
0
    }
2170
0
2171
0
  case MCK_HI32:
2172
0
    return B == MCK_HI32DSP;
2173
0
2174
0
  case MCK_LO32:
2175
0
    return B == MCK_LO32DSP;
2176
0
2177
0
  case MCK_SP64:
2178
0
    switch (B) {
2179
0
    default: return false;
2180
0
    case MCK_Reg22: return true;
2181
0
    case MCK_Reg20: return true;
2182
0
    case MCK_GPR64: return true;
2183
0
    }
2184
0
2185
0
  case MCK_Reg26:
2186
0
    switch (B) {
2187
0
    default: return false;
2188
0
    case MCK_Reg24: return true;
2189
0
    case MCK_Reg19: return true;
2190
0
    case MCK_Reg25: return true;
2191
0
    case MCK_Reg23: return true;
2192
0
    case MCK_Reg21: return true;
2193
0
    case MCK_Reg18: return true;
2194
0
    case MCK_Reg17: return true;
2195
0
    case MCK_Reg22: return true;
2196
0
    case MCK_Reg20: return true;
2197
0
    case MCK_GPR64: return true;
2198
0
    }
2199
0
2200
0
  case MCK_Reg11:
2201
0
    switch (B) {
2202
0
    default: return false;
2203
0
    case MCK_Reg9: return true;
2204
0
    case MCK_Reg4: return true;
2205
0
    case MCK_Reg10: return true;
2206
0
    case MCK_Reg8: return true;
2207
0
    case MCK_CPU16Regs: return true;
2208
0
    case MCK_GPRMM16MoveP: return true;
2209
0
    case MCK_GPRMM16Zero: return true;
2210
0
    case MCK_CPU16RegsPlusSP: return true;
2211
0
    case MCK_GPR32NONZERO: return true;
2212
0
    case MCK_DSPR: return true;
2213
0
    }
2214
0
2215
0
  case MCK_Reg24:
2216
0
    switch (B) {
2217
0
    default: return false;
2218
0
    case MCK_Reg25: return true;
2219
0
    case MCK_Reg21: return true;
2220
0
    case MCK_Reg18: return true;
2221
0
    case MCK_Reg22: return true;
2222
0
    case MCK_Reg20: return true;
2223
0
    case MCK_GPR64: return true;
2224
0
    }
2225
0
2226
0
  case MCK_Reg19:
2227
0
    switch (B) {
2228
0
    default: return false;
2229
0
    case MCK_Reg18: return true;
2230
0
    case MCK_Reg17: return true;
2231
0
    case MCK_GPR64: return true;
2232
0
    }
2233
0
2234
0
  case MCK_Reg9:
2235
0
    switch (B) {
2236
0
    default: return false;
2237
0
    case MCK_Reg10: return true;
2238
0
    case MCK_CPU16Regs: return true;
2239
0
    case MCK_GPRMM16MoveP: return true;
2240
0
    case MCK_CPU16RegsPlusSP: return true;
2241
0
    case MCK_GPR32NONZERO: return true;
2242
0
    case MCK_DSPR: return true;
2243
0
    }
2244
0
2245
0
  case MCK_Reg4:
2246
0
    switch (B) {
2247
0
    default: return false;
2248
0
    case MCK_GPRMM16MoveP: return true;
2249
0
    case MCK_GPRMM16Zero: return true;
2250
0
    case MCK_DSPR: return true;
2251
0
    }
2252
0
2253
0
  case MCK_Reg25:
2254
0
    switch (B) {
2255
0
    default: return false;
2256
0
    case MCK_Reg18: return true;
2257
0
    case MCK_Reg20: return true;
2258
0
    case MCK_GPR64: return true;
2259
0
    }
2260
0
2261
0
  case MCK_Reg23:
2262
0
    switch (B) {
2263
0
    default: return false;
2264
0
    case MCK_Reg21: return true;
2265
0
    case MCK_Reg17: return true;
2266
0
    case MCK_Reg22: return true;
2267
0
    case MCK_Reg20: return true;
2268
0
    case MCK_GPR64: return true;
2269
0
    }
2270
0
2271
0
  case MCK_Reg10:
2272
0
    switch (B) {
2273
0
    default: return false;
2274
0
    case MCK_GPRMM16MoveP: return true;
2275
0
    case MCK_GPR32NONZERO: return true;
2276
0
    case MCK_DSPR: return true;
2277
0
    }
2278
0
2279
0
  case MCK_Reg8:
2280
0
    switch (B) {
2281
0
    default: return false;
2282
0
    case MCK_CPU16Regs: return true;
2283
0
    case MCK_GPRMM16Zero: return true;
2284
0
    case MCK_CPU16RegsPlusSP: return true;
2285
0
    case MCK_GPR32NONZERO: return true;
2286
0
    case MCK_DSPR: return true;
2287
0
    }
2288
0
2289
0
  case MCK_Reg36:
2290
0
    switch (B) {
2291
0
    default: return false;
2292
0
    case MCK_AFGR64: return true;
2293
0
    case MCK_Reg37: return true;
2294
0
    case MCK_OddSP: return true;
2295
0
    }
2296
0
2297
0
  case MCK_Reg21:
2298
0
    switch (B) {
2299
0
    default: return false;
2300
0
    case MCK_Reg22: return true;
2301
0
    case MCK_Reg20: return true;
2302
0
    case MCK_GPR64: return true;
2303
0
    }
2304
0
2305
0
  case MCK_Reg18:
2306
0
    return B == MCK_GPR64;
2307
0
2308
0
  case MCK_Reg17:
2309
0
    return B == MCK_GPR64;
2310
0
2311
13.3k
  case MCK_CPU16Regs:
2312
13.3k
    switch (B) {
2313
13.3k
    default: return false;
2314
13.3k
    
case MCK_CPU16RegsPlusSP: return true0
;
2315
13.3k
    
case MCK_GPR32NONZERO: return true0
;
2316
13.3k
    
case MCK_DSPR: return true0
;
2317
0
    }
2318
0
2319
0
  case MCK_GPRMM16MoveP:
2320
0
    return B == MCK_DSPR;
2321
0
2322
0
  case MCK_GPRMM16Zero:
2323
0
    return B == MCK_DSPR;
2324
0
2325
0
  case MCK_Reg22:
2326
0
    switch (B) {
2327
0
    default: return false;
2328
0
    case MCK_Reg20: return true;
2329
0
    case MCK_GPR64: return true;
2330
0
    }
2331
0
2332
0
  case MCK_CPU16RegsPlusSP:
2333
0
    switch (B) {
2334
0
    default: return false;
2335
0
    case MCK_GPR32NONZERO: return true;
2336
0
    case MCK_DSPR: return true;
2337
0
    }
2338
0
2339
0
  case MCK_Reg42:
2340
0
    return B == MCK_MSA128F16;
2341
0
2342
0
  case MCK_Reg39:
2343
0
    switch (B) {
2344
0
    default: return false;
2345
0
    case MCK_Reg37: return true;
2346
0
    case MCK_FGR64: return true;
2347
0
    case MCK_OddSP: return true;
2348
0
    }
2349
0
2350
0
  case MCK_Reg34:
2351
0
    switch (B) {
2352
0
    default: return false;
2353
0
    case MCK_FGRH32: return true;
2354
0
    case MCK_OddSP: return true;
2355
0
    }
2356
0
2357
0
  case MCK_Reg31:
2358
0
    switch (B) {
2359
0
    default: return false;
2360
0
    case MCK_FGR32: return true;
2361
0
    case MCK_OddSP: return true;
2362
0
    }
2363
0
2364
0
  case MCK_MSA128WEvens:
2365
0
    return B == MCK_MSA128F16;
2366
0
2367
0
  case MCK_Reg37:
2368
0
    return B == MCK_OddSP;
2369
0
2370
0
  case MCK_Reg20:
2371
0
    return B == MCK_GPR64;
2372
0
2373
0
  case MCK_GPR32NONZERO:
2374
0
    return B == MCK_DSPR;
2375
0
2376
0
  case MCK_MemOffsetSimm10:
2377
0
    return B == MCK_Mem;
2378
0
2379
0
  case MCK_MemOffsetSimm10_1:
2380
0
    return B == MCK_Mem;
2381
0
2382
0
  case MCK_MemOffsetSimm10_2:
2383
0
    return B == MCK_Mem;
2384
0
2385
0
  case MCK_MemOffsetSimm10_3:
2386
0
    return B == MCK_Mem;
2387
0
2388
0
  case MCK_MemOffsetSimm11:
2389
0
    return B == MCK_Mem;
2390
0
2391
0
  case MCK_MemOffsetSimm12:
2392
0
    return B == MCK_Mem;
2393
0
2394
0
  case MCK_MemOffsetSimm16:
2395
0
    return B == MCK_Mem;
2396
0
2397
0
  case MCK_MemOffsetSimm9:
2398
0
    return B == MCK_Mem;
2399
0
2400
0
  case MCK_MemOffsetSimmPtr:
2401
0
    return B == MCK_Mem;
2402
0
2403
8
  case MCK_MemOffsetUimm4:
2404
8
    return B == MCK_Mem;
2405
0
2406
0
  case MCK_ConstantImmz:
2407
0
    switch (B) {
2408
0
    default: return false;
2409
0
    case MCK_ConstantUImm1_0: return true;
2410
0
    case MCK_ConstantUImm2_0: return true;
2411
0
    case MCK_ConstantUImm3_0: return true;
2412
0
    case MCK_ConstantSImm4_0: return true;
2413
0
    case MCK_ConstantUImm4_0: return true;
2414
0
    case MCK_ConstantSImm5_0: return true;
2415
0
    case MCK_ConstantUImm5_0: return true;
2416
0
    case MCK_ConstantUImm5_1: return true;
2417
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2418
0
    case MCK_ConstantUImm5_32_Norm: return true;
2419
0
    case MCK_ConstantUImm5_32: return true;
2420
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2421
0
    case MCK_ConstantUImm5_33: return true;
2422
0
    case MCK_ConstantUImmRange2_64: return true;
2423
0
    case MCK_UImm5Lsl2: return true;
2424
0
    case MCK_ConstantSImm6_0: return true;
2425
0
    case MCK_ConstantUImm6_0: return true;
2426
0
    case MCK_UImm6Lsl2: return true;
2427
0
    case MCK_ConstantUImm7_0: return true;
2428
0
    case MCK_UImm7_N1: return true;
2429
0
    case MCK_ConstantUImm8_0: return true;
2430
0
    case MCK_SImm7Lsl2: return true;
2431
0
    case MCK_ConstantSImm9_0: return true;
2432
0
    case MCK_ConstantSImm10_0: return true;
2433
0
    case MCK_ConstantUImm10_0: return true;
2434
0
    case MCK_SImm10Lsl1: return true;
2435
0
    case MCK_ConstantSImm11_0: return true;
2436
0
    case MCK_SImm10Lsl2: return true;
2437
0
    case MCK_SImm10Lsl3: return true;
2438
0
    case MCK_SImm16: return true;
2439
0
    case MCK_SImm16_Relaxed: return true;
2440
0
    case MCK_UImm16_Relaxed: return true;
2441
0
    case MCK_ConstantUImm20_0: return true;
2442
0
    case MCK_ConstantUImm26_0: return true;
2443
0
    case MCK_SImm32: return true;
2444
0
    case MCK_SImm32_Relaxed: return true;
2445
0
    case MCK_UImm32_Coerced: return true;
2446
0
    }
2447
0
2448
0
  case MCK_ConstantUImm1_0:
2449
0
    switch (B) {
2450
0
    default: return false;
2451
0
    case MCK_ConstantUImm2_0: return true;
2452
0
    case MCK_ConstantUImm3_0: return true;
2453
0
    case MCK_ConstantSImm4_0: return true;
2454
0
    case MCK_ConstantUImm4_0: return true;
2455
0
    case MCK_ConstantSImm5_0: return true;
2456
0
    case MCK_ConstantUImm5_0: return true;
2457
0
    case MCK_ConstantUImm5_1: return true;
2458
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2459
0
    case MCK_ConstantUImm5_32_Norm: return true;
2460
0
    case MCK_ConstantUImm5_32: return true;
2461
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2462
0
    case MCK_ConstantUImm5_33: return true;
2463
0
    case MCK_ConstantUImmRange2_64: return true;
2464
0
    case MCK_UImm5Lsl2: return true;
2465
0
    case MCK_ConstantSImm6_0: return true;
2466
0
    case MCK_ConstantUImm6_0: return true;
2467
0
    case MCK_UImm6Lsl2: return true;
2468
0
    case MCK_ConstantUImm7_0: return true;
2469
0
    case MCK_UImm7_N1: return true;
2470
0
    case MCK_ConstantUImm8_0: return true;
2471
0
    case MCK_SImm7Lsl2: return true;
2472
0
    case MCK_ConstantSImm9_0: return true;
2473
0
    case MCK_ConstantSImm10_0: return true;
2474
0
    case MCK_ConstantUImm10_0: return true;
2475
0
    case MCK_SImm10Lsl1: return true;
2476
0
    case MCK_ConstantSImm11_0: return true;
2477
0
    case MCK_SImm10Lsl2: return true;
2478
0
    case MCK_SImm10Lsl3: return true;
2479
0
    case MCK_SImm16: return true;
2480
0
    case MCK_SImm16_Relaxed: return true;
2481
0
    case MCK_UImm16_Relaxed: return true;
2482
0
    case MCK_ConstantUImm20_0: return true;
2483
0
    case MCK_ConstantUImm26_0: return true;
2484
0
    case MCK_SImm32: return true;
2485
0
    case MCK_SImm32_Relaxed: return true;
2486
0
    case MCK_UImm32_Coerced: return true;
2487
0
    }
2488
0
2489
6
  case MCK_ConstantUImm2_0:
2490
6
    switch (B) {
2491
6
    default: return false;
2492
6
    
case MCK_ConstantUImm3_0: return true0
;
2493
6
    
case MCK_ConstantSImm4_0: return true0
;
2494
6
    
case MCK_ConstantUImm4_0: return true0
;
2495
6
    
case MCK_ConstantSImm5_0: return true0
;
2496
6
    
case MCK_ConstantUImm5_0: return true0
;
2497
6
    
case MCK_ConstantUImm5_1: return true0
;
2498
6
    
case MCK_ConstantUImm5_Plus1_Report_UImm6: return true0
;
2499
6
    
case MCK_ConstantUImm5_32_Norm: return true0
;
2500
6
    
case MCK_ConstantUImm5_32: return true0
;
2501
6
    
case MCK_ConstantUImm5_0_Report_UImm6: return true0
;
2502
6
    
case MCK_ConstantUImm5_33: return true0
;
2503
6
    
case MCK_ConstantUImmRange2_64: return true0
;
2504
6
    
case MCK_UImm5Lsl2: return true0
;
2505
6
    
case MCK_ConstantSImm6_0: return true0
;
2506
6
    
case MCK_ConstantUImm6_0: return true0
;
2507
6
    
case MCK_UImm6Lsl2: return true0
;
2508
6
    
case MCK_ConstantUImm7_0: return true0
;
2509
6
    
case MCK_UImm7_N1: return true0
;
2510
6
    
case MCK_ConstantUImm8_0: return true0
;
2511
6
    
case MCK_SImm7Lsl2: return true0
;
2512
6
    
case MCK_ConstantSImm9_0: return true0
;
2513
6
    
case MCK_ConstantSImm10_0: return true0
;
2514
6
    
case MCK_ConstantUImm10_0: return true0
;
2515
6
    
case MCK_SImm10Lsl1: return true0
;
2516
6
    
case MCK_ConstantSImm11_0: return true0
;
2517
6
    
case MCK_SImm10Lsl2: return true0
;
2518
6
    
case MCK_SImm10Lsl3: return true0
;
2519
6
    
case MCK_SImm16: return true0
;
2520
6
    
case MCK_SImm16_Relaxed: return true0
;
2521
6
    
case MCK_UImm16_Relaxed: return true0
;
2522
6
    
case MCK_ConstantUImm20_0: return true0
;
2523
6
    
case MCK_ConstantUImm26_0: return true0
;
2524
6
    
case MCK_SImm32: return true0
;
2525
6
    
case MCK_SImm32_Relaxed: return true0
;
2526
6
    
case MCK_UImm32_Coerced: return true0
;
2527
0
    }
2528
0
2529
0
  case MCK_ConstantUImm2_1:
2530
0
    switch (B) {
2531
0
    default: return false;
2532
0
    case MCK_ConstantUImm3_0: return true;
2533
0
    case MCK_ConstantSImm4_0: return true;
2534
0
    case MCK_ConstantUImm4_0: return true;
2535
0
    case MCK_ConstantSImm5_0: return true;
2536
0
    case MCK_ConstantUImm5_0: return true;
2537
0
    case MCK_ConstantUImm5_1: return true;
2538
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2539
0
    case MCK_ConstantUImm5_32_Norm: return true;
2540
0
    case MCK_ConstantUImm5_32: return true;
2541
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2542
0
    case MCK_ConstantUImm5_33: return true;
2543
0
    case MCK_ConstantUImmRange2_64: return true;
2544
0
    case MCK_UImm5Lsl2: return true;
2545
0
    case MCK_ConstantSImm6_0: return true;
2546
0
    case MCK_ConstantUImm6_0: return true;
2547
0
    case MCK_UImm6Lsl2: return true;
2548
0
    case MCK_ConstantUImm7_0: return true;
2549
0
    case MCK_UImm7_N1: return true;
2550
0
    case MCK_ConstantUImm8_0: return true;
2551
0
    case MCK_SImm7Lsl2: return true;
2552
0
    case MCK_ConstantSImm9_0: return true;
2553
0
    case MCK_ConstantSImm10_0: return true;
2554
0
    case MCK_ConstantUImm10_0: return true;
2555
0
    case MCK_SImm10Lsl1: return true;
2556
0
    case MCK_ConstantSImm11_0: return true;
2557
0
    case MCK_SImm10Lsl2: return true;
2558
0
    case MCK_SImm10Lsl3: return true;
2559
0
    case MCK_SImm16: return true;
2560
0
    case MCK_SImm16_Relaxed: return true;
2561
0
    case MCK_UImm16_Relaxed: return true;
2562
0
    case MCK_ConstantUImm20_0: return true;
2563
0
    case MCK_ConstantUImm26_0: return true;
2564
0
    case MCK_SImm32: return true;
2565
0
    case MCK_SImm32_Relaxed: return true;
2566
0
    case MCK_UImm32_Coerced: return true;
2567
0
    }
2568
0
2569
0
  case MCK_ConstantUImm3_0:
2570
0
    switch (B) {
2571
0
    default: return false;
2572
0
    case MCK_ConstantSImm4_0: return true;
2573
0
    case MCK_ConstantUImm4_0: return true;
2574
0
    case MCK_ConstantSImm5_0: return true;
2575
0
    case MCK_ConstantUImm5_0: return true;
2576
0
    case MCK_ConstantUImm5_1: return true;
2577
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2578
0
    case MCK_ConstantUImm5_32_Norm: return true;
2579
0
    case MCK_ConstantUImm5_32: return true;
2580
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2581
0
    case MCK_ConstantUImm5_33: return true;
2582
0
    case MCK_ConstantUImmRange2_64: return true;
2583
0
    case MCK_UImm5Lsl2: return true;
2584
0
    case MCK_ConstantSImm6_0: return true;
2585
0
    case MCK_ConstantUImm6_0: return true;
2586
0
    case MCK_UImm6Lsl2: return true;
2587
0
    case MCK_ConstantUImm7_0: return true;
2588
0
    case MCK_UImm7_N1: return true;
2589
0
    case MCK_ConstantUImm8_0: return true;
2590
0
    case MCK_SImm7Lsl2: return true;
2591
0
    case MCK_ConstantSImm9_0: return true;
2592
0
    case MCK_ConstantSImm10_0: return true;
2593
0
    case MCK_ConstantUImm10_0: return true;
2594
0
    case MCK_SImm10Lsl1: return true;
2595
0
    case MCK_ConstantSImm11_0: return true;
2596
0
    case MCK_SImm10Lsl2: return true;
2597
0
    case MCK_SImm10Lsl3: return true;
2598
0
    case MCK_SImm16: return true;
2599
0
    case MCK_SImm16_Relaxed: return true;
2600
0
    case MCK_UImm16_Relaxed: return true;
2601
0
    case MCK_ConstantUImm20_0: return true;
2602
0
    case MCK_ConstantUImm26_0: return true;
2603
0
    case MCK_SImm32: return true;
2604
0
    case MCK_SImm32_Relaxed: return true;
2605
0
    case MCK_UImm32_Coerced: return true;
2606
0
    }
2607
0
2608
0
  case MCK_ConstantSImm4_0:
2609
0
    switch (B) {
2610
0
    default: return false;
2611
0
    case MCK_ConstantUImm4_0: return true;
2612
0
    case MCK_ConstantSImm5_0: return true;
2613
0
    case MCK_ConstantUImm5_0: return true;
2614
0
    case MCK_ConstantUImm5_1: return true;
2615
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2616
0
    case MCK_ConstantUImm5_32_Norm: return true;
2617
0
    case MCK_ConstantUImm5_32: return true;
2618
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2619
0
    case MCK_ConstantUImm5_33: return true;
2620
0
    case MCK_ConstantUImmRange2_64: return true;
2621
0
    case MCK_UImm5Lsl2: return true;
2622
0
    case MCK_ConstantSImm6_0: return true;
2623
0
    case MCK_ConstantUImm6_0: return true;
2624
0
    case MCK_UImm6Lsl2: return true;
2625
0
    case MCK_ConstantUImm7_0: return true;
2626
0
    case MCK_UImm7_N1: return true;
2627
0
    case MCK_ConstantUImm8_0: return true;
2628
0
    case MCK_SImm7Lsl2: return true;
2629
0
    case MCK_ConstantSImm9_0: return true;
2630
0
    case MCK_ConstantSImm10_0: return true;
2631
0
    case MCK_ConstantUImm10_0: return true;
2632
0
    case MCK_SImm10Lsl1: return true;
2633
0
    case MCK_ConstantSImm11_0: return true;
2634
0
    case MCK_SImm10Lsl2: return true;
2635
0
    case MCK_SImm10Lsl3: return true;
2636
0
    case MCK_SImm16: return true;
2637
0
    case MCK_SImm16_Relaxed: return true;
2638
0
    case MCK_UImm16_Relaxed: return true;
2639
0
    case MCK_ConstantUImm20_0: return true;
2640
0
    case MCK_ConstantUImm26_0: return true;
2641
0
    case MCK_SImm32: return true;
2642
0
    case MCK_SImm32_Relaxed: return true;
2643
0
    case MCK_UImm32_Coerced: return true;
2644
0
    }
2645
0
2646
6
  case MCK_ConstantUImm4_0:
2647
6
    switch (B) {
2648
6
    default: return false;
2649
6
    
case MCK_ConstantSImm5_0: return true0
;
2650
6
    
case MCK_ConstantUImm5_0: return true0
;
2651
6
    
case MCK_ConstantUImm5_1: return true0
;
2652
6
    
case MCK_ConstantUImm5_Plus1_Report_UImm6: return true0
;
2653
6
    
case MCK_ConstantUImm5_32_Norm: return true0
;
2654
6
    
case MCK_ConstantUImm5_32: return true0
;
2655
6
    
case MCK_ConstantUImm5_0_Report_UImm6: return true0
;
2656
6
    
case MCK_ConstantUImm5_33: return true0
;
2657
6
    
case MCK_ConstantUImmRange2_64: return true0
;
2658
6
    
case MCK_UImm5Lsl2: return true0
;
2659
6
    
case MCK_ConstantSImm6_0: return true0
;
2660
6
    
case MCK_ConstantUImm6_0: return true0
;
2661
6
    
case MCK_UImm6Lsl2: return true0
;
2662
6
    
case MCK_ConstantUImm7_0: return true0
;
2663
6
    
case MCK_UImm7_N1: return true0
;
2664
6
    
case MCK_ConstantUImm8_0: return true0
;
2665
6
    
case MCK_SImm7Lsl2: return true0
;
2666
6
    
case MCK_ConstantSImm9_0: return true0
;
2667
6
    
case MCK_ConstantSImm10_0: return true0
;
2668
6
    
case MCK_ConstantUImm10_0: return true0
;
2669
6
    
case MCK_SImm10Lsl1: return true0
;
2670
6
    
case MCK_ConstantSImm11_0: return true0
;
2671
6
    
case MCK_SImm10Lsl2: return true0
;
2672
6
    
case MCK_SImm10Lsl3: return true0
;
2673
6
    
case MCK_SImm16: return true0
;
2674
6
    
case MCK_SImm16_Relaxed: return true0
;
2675
6
    
case MCK_UImm16_Relaxed: return true0
;
2676
6
    
case MCK_ConstantUImm20_0: return true0
;
2677
6
    
case MCK_ConstantUImm26_0: return true0
;
2678
6
    
case MCK_SImm32: return true0
;
2679
6
    
case MCK_SImm32_Relaxed: return true0
;
2680
6
    
case MCK_UImm32_Coerced: return true0
;
2681
0
    }
2682
0
2683
0
  case MCK_ConstantSImm5_0:
2684
0
    switch (B) {
2685
0
    default: return false;
2686
0
    case MCK_ConstantUImm5_0: return true;
2687
0
    case MCK_ConstantUImm5_1: return true;
2688
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2689
0
    case MCK_ConstantUImm5_32_Norm: return true;
2690
0
    case MCK_ConstantUImm5_32: return true;
2691
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2692
0
    case MCK_ConstantUImm5_33: return true;
2693
0
    case MCK_ConstantUImmRange2_64: return true;
2694
0
    case MCK_UImm5Lsl2: return true;
2695
0
    case MCK_ConstantSImm6_0: return true;
2696
0
    case MCK_ConstantUImm6_0: return true;
2697
0
    case MCK_UImm6Lsl2: return true;
2698
0
    case MCK_ConstantUImm7_0: return true;
2699
0
    case MCK_UImm7_N1: return true;
2700
0
    case MCK_ConstantUImm8_0: return true;
2701
0
    case MCK_SImm7Lsl2: return true;
2702
0
    case MCK_ConstantSImm9_0: return true;
2703
0
    case MCK_ConstantSImm10_0: return true;
2704
0
    case MCK_ConstantUImm10_0: return true;
2705
0
    case MCK_SImm10Lsl1: return true;
2706
0
    case MCK_ConstantSImm11_0: return true;
2707
0
    case MCK_SImm10Lsl2: return true;
2708
0
    case MCK_SImm10Lsl3: return true;
2709
0
    case MCK_SImm16: return true;
2710
0
    case MCK_SImm16_Relaxed: return true;
2711
0
    case MCK_UImm16_Relaxed: return true;
2712
0
    case MCK_ConstantUImm20_0: return true;
2713
0
    case MCK_ConstantUImm26_0: return true;
2714
0
    case MCK_SImm32: return true;
2715
0
    case MCK_SImm32_Relaxed: return true;
2716
0
    case MCK_UImm32_Coerced: return true;
2717
0
    }
2718
0
2719
3
  case MCK_ConstantUImm5_0:
2720
3
    switch (B) {
2721
3
    default: return false;
2722
3
    
case MCK_ConstantUImm5_1: return true0
;
2723
3
    
case MCK_ConstantUImm5_Plus1_Report_UImm6: return true0
;
2724
3
    
case MCK_ConstantUImm5_32_Norm: return true0
;
2725
3
    
case MCK_ConstantUImm5_32: return true0
;
2726
3
    
case MCK_ConstantUImm5_0_Report_UImm6: return true0
;
2727
3
    
case MCK_ConstantUImm5_33: return true0
;
2728
3
    
case MCK_ConstantUImmRange2_64: return true0
;
2729
3
    
case MCK_UImm5Lsl2: return true0
;
2730
3
    
case MCK_ConstantSImm6_0: return true0
;
2731
3
    
case MCK_ConstantUImm6_0: return true0
;
2732
3
    
case MCK_UImm6Lsl2: return true0
;
2733
3
    
case MCK_ConstantUImm7_0: return true0
;
2734
3
    
case MCK_UImm7_N1: return true0
;
2735
3
    
case MCK_ConstantUImm8_0: return true0
;
2736
3
    
case MCK_SImm7Lsl2: return true0
;
2737
3
    
case MCK_ConstantSImm9_0: return true0
;
2738
3
    
case MCK_ConstantSImm10_0: return true0
;
2739
3
    
case MCK_ConstantUImm10_0: return true0
;
2740
3
    
case MCK_SImm10Lsl1: return true0
;
2741
3
    
case MCK_ConstantSImm11_0: return true0
;
2742
3
    
case MCK_SImm10Lsl2: return true0
;
2743
3
    
case MCK_SImm10Lsl3: return true0
;
2744
3
    
case MCK_SImm16: return true0
;
2745
3
    
case MCK_SImm16_Relaxed: return true0
;
2746
3
    
case MCK_UImm16_Relaxed: return true0
;
2747
3
    
case MCK_ConstantUImm20_0: return true0
;
2748
3
    
case MCK_ConstantUImm26_0: return true0
;
2749
3
    
case MCK_SImm32: return true0
;
2750
3
    
case MCK_SImm32_Relaxed: return true0
;
2751
3
    
case MCK_UImm32_Coerced: return true0
;
2752
0
    }
2753
0
2754
0
  case MCK_ConstantUImm5_1:
2755
0
    switch (B) {
2756
0
    default: return false;
2757
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2758
0
    case MCK_ConstantUImm5_32_Norm: return true;
2759
0
    case MCK_ConstantUImm5_32: return true;
2760
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2761
0
    case MCK_ConstantUImm5_33: return true;
2762
0
    case MCK_ConstantUImmRange2_64: return true;
2763
0
    case MCK_UImm5Lsl2: return true;
2764
0
    case MCK_ConstantSImm6_0: return true;
2765
0
    case MCK_ConstantUImm6_0: return true;
2766
0
    case MCK_UImm6Lsl2: return true;
2767
0
    case MCK_ConstantUImm7_0: return true;
2768
0
    case MCK_UImm7_N1: return true;
2769
0
    case MCK_ConstantUImm8_0: return true;
2770
0
    case MCK_SImm7Lsl2: return true;
2771
0
    case MCK_ConstantSImm9_0: return true;
2772
0
    case MCK_ConstantSImm10_0: return true;
2773
0
    case MCK_ConstantUImm10_0: return true;
2774
0
    case MCK_SImm10Lsl1: return true;
2775
0
    case MCK_ConstantSImm11_0: return true;
2776
0
    case MCK_SImm10Lsl2: return true;
2777
0
    case MCK_SImm10Lsl3: return true;
2778
0
    case MCK_SImm16: return true;
2779
0
    case MCK_SImm16_Relaxed: return true;
2780
0
    case MCK_UImm16_Relaxed: return true;
2781
0
    case MCK_ConstantUImm20_0: return true;
2782
0
    case MCK_ConstantUImm26_0: return true;
2783
0
    case MCK_SImm32: return true;
2784
0
    case MCK_SImm32_Relaxed: return true;
2785
0
    case MCK_UImm32_Coerced: return true;
2786
0
    }
2787
0
2788
0
  case MCK_ConstantUImm5_Plus1_Report_UImm6:
2789
0
    switch (B) {
2790
0
    default: return false;
2791
0
    case MCK_ConstantUImm5_32_Norm: return true;
2792
0
    case MCK_ConstantUImm5_32: return true;
2793
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2794
0
    case MCK_ConstantUImm5_33: return true;
2795
0
    case MCK_ConstantUImmRange2_64: return true;
2796
0
    case MCK_UImm5Lsl2: return true;
2797
0
    case MCK_ConstantSImm6_0: return true;
2798
0
    case MCK_ConstantUImm6_0: return true;
2799
0
    case MCK_UImm6Lsl2: return true;
2800
0
    case MCK_ConstantUImm7_0: return true;
2801
0
    case MCK_UImm7_N1: return true;
2802
0
    case MCK_ConstantUImm8_0: return true;
2803
0
    case MCK_SImm7Lsl2: return true;
2804
0
    case MCK_ConstantSImm9_0: return true;
2805
0
    case MCK_ConstantSImm10_0: return true;
2806
0
    case MCK_ConstantUImm10_0: return true;
2807
0
    case MCK_SImm10Lsl1: return true;
2808
0
    case MCK_ConstantSImm11_0: return true;
2809
0
    case MCK_SImm10Lsl2: return true;
2810
0
    case MCK_SImm10Lsl3: return true;
2811
0
    case MCK_SImm16: return true;
2812
0
    case MCK_SImm16_Relaxed: return true;
2813
0
    case MCK_UImm16_Relaxed: return true;
2814
0
    case MCK_ConstantUImm20_0: return true;
2815
0
    case MCK_ConstantUImm26_0: return true;
2816
0
    case MCK_SImm32: return true;
2817
0
    case MCK_SImm32_Relaxed: return true;
2818
0
    case MCK_UImm32_Coerced: return true;
2819
0
    }
2820
0
2821
0
  case MCK_ConstantUImm5_32_Norm:
2822
0
    switch (B) {
2823
0
    default: return false;
2824
0
    case MCK_ConstantUImm5_32: return true;
2825
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2826
0
    case MCK_ConstantUImm5_33: return true;
2827
0
    case MCK_ConstantUImmRange2_64: return true;
2828
0
    case MCK_UImm5Lsl2: return true;
2829
0
    case MCK_ConstantSImm6_0: return true;
2830
0
    case MCK_ConstantUImm6_0: return true;
2831
0
    case MCK_UImm6Lsl2: return true;
2832
0
    case MCK_ConstantUImm7_0: return true;
2833
0
    case MCK_UImm7_N1: return true;
2834
0
    case MCK_ConstantUImm8_0: return true;
2835
0
    case MCK_SImm7Lsl2: return true;
2836
0
    case MCK_ConstantSImm9_0: return true;
2837
0
    case MCK_ConstantSImm10_0: return true;
2838
0
    case MCK_ConstantUImm10_0: return true;
2839
0
    case MCK_SImm10Lsl1: return true;
2840
0
    case MCK_ConstantSImm11_0: return true;
2841
0
    case MCK_SImm10Lsl2: return true;
2842
0
    case MCK_SImm10Lsl3: return true;
2843
0
    case MCK_SImm16: return true;
2844
0
    case MCK_SImm16_Relaxed: return true;
2845
0
    case MCK_UImm16_Relaxed: return true;
2846
0
    case MCK_ConstantUImm20_0: return true;
2847
0
    case MCK_ConstantUImm26_0: return true;
2848
0
    case MCK_SImm32: return true;
2849
0
    case MCK_SImm32_Relaxed: return true;
2850
0
    case MCK_UImm32_Coerced: return true;
2851
0
    }
2852
0
2853
0
  case MCK_ConstantUImm5_32:
2854
0
    switch (B) {
2855
0
    default: return false;
2856
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2857
0
    case MCK_ConstantUImm5_33: return true;
2858
0
    case MCK_ConstantUImmRange2_64: return true;
2859
0
    case MCK_UImm5Lsl2: return true;
2860
0
    case MCK_ConstantSImm6_0: return true;
2861
0
    case MCK_ConstantUImm6_0: return true;
2862
0
    case MCK_UImm6Lsl2: return true;
2863
0
    case MCK_ConstantUImm7_0: return true;
2864
0
    case MCK_UImm7_N1: return true;
2865
0
    case MCK_ConstantUImm8_0: return true;
2866
0
    case MCK_SImm7Lsl2: return true;
2867
0
    case MCK_ConstantSImm9_0: return true;
2868
0
    case MCK_ConstantSImm10_0: return true;
2869
0
    case MCK_ConstantUImm10_0: return true;
2870
0
    case MCK_SImm10Lsl1: return true;
2871
0
    case MCK_ConstantSImm11_0: return true;
2872
0
    case MCK_SImm10Lsl2: return true;
2873
0
    case MCK_SImm10Lsl3: return true;
2874
0
    case MCK_SImm16: return true;
2875
0
    case MCK_SImm16_Relaxed: return true;
2876
0
    case MCK_UImm16_Relaxed: return true;
2877
0
    case MCK_ConstantUImm20_0: return true;
2878
0
    case MCK_ConstantUImm26_0: return true;
2879
0
    case MCK_SImm32: return true;
2880
0
    case MCK_SImm32_Relaxed: return true;
2881
0
    case MCK_UImm32_Coerced: return true;
2882
0
    }
2883
0
2884
0
  case MCK_ConstantUImm5_0_Report_UImm6:
2885
0
    switch (B) {
2886
0
    default: return false;
2887
0
    case MCK_ConstantUImm5_33: return true;
2888
0
    case MCK_ConstantUImmRange2_64: return true;
2889
0
    case MCK_UImm5Lsl2: return true;
2890
0
    case MCK_ConstantSImm6_0: return true;
2891
0
    case MCK_ConstantUImm6_0: return true;
2892
0
    case MCK_UImm6Lsl2: return true;
2893
0
    case MCK_ConstantUImm7_0: return true;
2894
0
    case MCK_UImm7_N1: return true;
2895
0
    case MCK_ConstantUImm8_0: return true;
2896
0
    case MCK_SImm7Lsl2: return true;
2897
0
    case MCK_ConstantSImm9_0: return true;
2898
0
    case MCK_ConstantSImm10_0: return true;
2899
0
    case MCK_ConstantUImm10_0: return true;
2900
0
    case MCK_SImm10Lsl1: return true;
2901
0
    case MCK_ConstantSImm11_0: return true;
2902
0
    case MCK_SImm10Lsl2: return true;
2903
0
    case MCK_SImm10Lsl3: return true;
2904
0
    case MCK_SImm16: return true;
2905
0
    case MCK_SImm16_Relaxed: return true;
2906
0
    case MCK_UImm16_Relaxed: return true;
2907
0
    case MCK_ConstantUImm20_0: return true;
2908
0
    case MCK_ConstantUImm26_0: return true;
2909
0
    case MCK_SImm32: return true;
2910
0
    case MCK_SImm32_Relaxed: return true;
2911
0
    case MCK_UImm32_Coerced: return true;
2912
0
    }
2913
0
2914
0
  case MCK_ConstantUImm5_33:
2915
0
    switch (B) {
2916
0
    default: return false;
2917
0
    case MCK_ConstantUImmRange2_64: return true;
2918
0
    case MCK_UImm5Lsl2: return true;
2919
0
    case MCK_ConstantSImm6_0: return true;
2920
0
    case MCK_ConstantUImm6_0: return true;
2921
0
    case MCK_UImm6Lsl2: return true;
2922
0
    case MCK_ConstantUImm7_0: return true;
2923
0
    case MCK_UImm7_N1: return true;
2924
0
    case MCK_ConstantUImm8_0: return true;
2925
0
    case MCK_SImm7Lsl2: return true;
2926
0
    case MCK_ConstantSImm9_0: return true;
2927
0
    case MCK_ConstantSImm10_0: return true;
2928
0
    case MCK_ConstantUImm10_0: return true;
2929
0
    case MCK_SImm10Lsl1: return true;
2930
0
    case MCK_ConstantSImm11_0: return true;
2931
0
    case MCK_SImm10Lsl2: return true;
2932
0
    case MCK_SImm10Lsl3: return true;
2933
0
    case MCK_SImm16: return true;
2934
0
    case MCK_SImm16_Relaxed: return true;
2935
0
    case MCK_UImm16_Relaxed: return true;
2936
0
    case MCK_ConstantUImm20_0: return true;
2937
0
    case MCK_ConstantUImm26_0: return true;
2938
0
    case MCK_SImm32: return true;
2939
0
    case MCK_SImm32_Relaxed: return true;
2940
0
    case MCK_UImm32_Coerced: return true;
2941
0
    }
2942
0
2943
0
  case MCK_ConstantUImmRange2_64:
2944
0
    switch (B) {
2945
0
    default: return false;
2946
0
    case MCK_UImm5Lsl2: return true;
2947
0
    case MCK_ConstantSImm6_0: return true;
2948
0
    case MCK_ConstantUImm6_0: return true;
2949
0
    case MCK_UImm6Lsl2: return true;
2950
0
    case MCK_ConstantUImm7_0: return true;
2951
0
    case MCK_UImm7_N1: return true;
2952
0
    case MCK_ConstantUImm8_0: return true;
2953
0
    case MCK_SImm7Lsl2: return true;
2954
0
    case MCK_ConstantSImm9_0: return true;
2955
0
    case MCK_ConstantSImm10_0: return true;
2956
0
    case MCK_ConstantUImm10_0: return true;
2957
0
    case MCK_SImm10Lsl1: return true;
2958
0
    case MCK_ConstantSImm11_0: return true;
2959
0
    case MCK_SImm10Lsl2: return true;
2960
0
    case MCK_SImm10Lsl3: return true;
2961
0
    case MCK_SImm16: return true;
2962
0
    case MCK_SImm16_Relaxed: return true;
2963
0
    case MCK_UImm16_Relaxed: return true;
2964
0
    case MCK_ConstantUImm20_0: return true;
2965
0
    case MCK_ConstantUImm26_0: return true;
2966
0
    case MCK_SImm32: return true;
2967
0
    case MCK_SImm32_Relaxed: return true;
2968
0
    case MCK_UImm32_Coerced: return true;
2969
0
    }
2970
0
2971
0
  case MCK_UImm5Lsl2:
2972
0
    switch (B) {
2973
0
    default: return false;
2974
0
    case MCK_ConstantSImm6_0: return true;
2975
0
    case MCK_ConstantUImm6_0: return true;
2976
0
    case MCK_UImm6Lsl2: return true;
2977
0
    case MCK_ConstantUImm7_0: return true;
2978
0
    case MCK_UImm7_N1: return true;
2979
0
    case MCK_ConstantUImm8_0: return true;
2980
0
    case MCK_SImm7Lsl2: return true;
2981
0
    case MCK_ConstantSImm9_0: return true;
2982
0
    case MCK_ConstantSImm10_0: return true;
2983
0
    case MCK_ConstantUImm10_0: return true;
2984
0
    case MCK_SImm10Lsl1: return true;
2985
0
    case MCK_ConstantSImm11_0: return true;
2986
0
    case MCK_SImm10Lsl2: return true;
2987
0
    case MCK_SImm10Lsl3: return true;
2988
0
    case MCK_SImm16: return true;
2989
0
    case MCK_SImm16_Relaxed: return true;
2990
0
    case MCK_UImm16_Relaxed: return true;
2991
0
    case MCK_ConstantUImm20_0: return true;
2992
0
    case MCK_ConstantUImm26_0: return true;
2993
0
    case MCK_SImm32: return true;
2994
0
    case MCK_SImm32_Relaxed: return true;
2995
0
    case MCK_UImm32_Coerced: return true;
2996
0
    }
2997
0
2998
0
  case MCK_ConstantSImm6_0:
2999
0
    switch (B) {
3000
0
    default: return false;
3001
0
    case MCK_ConstantUImm6_0: return true;
3002
0
    case MCK_UImm6Lsl2: return true;
3003
0
    case MCK_ConstantUImm7_0: return true;
3004
0
    case MCK_UImm7_N1: return true;
3005
0
    case MCK_ConstantUImm8_0: return true;
3006
0
    case MCK_SImm7Lsl2: return true;
3007
0
    case MCK_ConstantSImm9_0: return true;
3008
0
    case MCK_ConstantSImm10_0: return true;
3009
0
    case MCK_ConstantUImm10_0: return true;
3010
0
    case MCK_SImm10Lsl1: return true;
3011
0
    case MCK_ConstantSImm11_0: return true;
3012
0
    case MCK_SImm10Lsl2: return true;
3013
0
    case MCK_SImm10Lsl3: return true;
3014
0
    case MCK_SImm16: return true;
3015
0
    case MCK_SImm16_Relaxed: return true;
3016
0
    case MCK_UImm16_Relaxed: return true;
3017
0
    case MCK_ConstantUImm20_0: return true;
3018
0
    case MCK_ConstantUImm26_0: return true;
3019
0
    case MCK_SImm32: return true;
3020
0
    case MCK_SImm32_Relaxed: return true;
3021
0
    case MCK_UImm32_Coerced: return true;
3022
0
    }
3023
0
3024
0
  case MCK_ConstantUImm6_0:
3025
0
    switch (B) {
3026
0
    default: return false;
3027
0
    case MCK_UImm6Lsl2: return true;
3028
0
    case MCK_ConstantUImm7_0: return true;
3029
0
    case MCK_UImm7_N1: return true;
3030
0
    case MCK_ConstantUImm8_0: return true;
3031
0
    case MCK_SImm7Lsl2: return true;
3032
0
    case MCK_ConstantSImm9_0: return true;
3033
0
    case MCK_ConstantSImm10_0: return true;
3034
0
    case MCK_ConstantUImm10_0: return true;
3035
0
    case MCK_SImm10Lsl1: return true;
3036
0
    case MCK_ConstantSImm11_0: return true;
3037
0
    case MCK_SImm10Lsl2: return true;
3038
0
    case MCK_SImm10Lsl3: return true;
3039
0
    case MCK_SImm16: return true;
3040
0
    case MCK_SImm16_Relaxed: return true;
3041
0
    case MCK_UImm16_Relaxed: return true;
3042
0
    case MCK_ConstantUImm20_0: return true;
3043
0
    case MCK_ConstantUImm26_0: return true;
3044
0
    case MCK_SImm32: return true;
3045
0
    case MCK_SImm32_Relaxed: return true;
3046
0
    case MCK_UImm32_Coerced: return true;
3047
0
    }
3048
0
3049
0
  case MCK_UImm6Lsl2:
3050
0
    switch (B) {
3051
0
    default: return false;
3052
0
    case MCK_ConstantUImm7_0: return true;
3053
0
    case MCK_UImm7_N1: return true;
3054
0
    case MCK_ConstantUImm8_0: return true;
3055
0
    case MCK_SImm7Lsl2: return true;
3056
0
    case MCK_ConstantSImm9_0: return true;
3057
0
    case MCK_ConstantSImm10_0: return true;
3058
0
    case MCK_ConstantUImm10_0: return true;
3059
0
    case MCK_SImm10Lsl1: return true;
3060
0
    case MCK_ConstantSImm11_0: return true;
3061
0
    case MCK_SImm10Lsl2: return true;
3062
0
    case MCK_SImm10Lsl3: return true;
3063
0
    case MCK_SImm16: return true;
3064
0
    case MCK_SImm16_Relaxed: return true;
3065
0
    case MCK_UImm16_Relaxed: return true;
3066
0
    case MCK_ConstantUImm20_0: return true;
3067
0
    case MCK_ConstantUImm26_0: return true;
3068
0
    case MCK_SImm32: return true;
3069
0
    case MCK_SImm32_Relaxed: return true;
3070
0
    case MCK_UImm32_Coerced: return true;
3071
0
    }
3072
0
3073
0
  case MCK_ConstantUImm7_0:
3074
0
    switch (B) {
3075
0
    default: return false;
3076
0
    case MCK_UImm7_N1: return true;
3077
0
    case MCK_ConstantUImm8_0: return true;
3078
0
    case MCK_SImm7Lsl2: return true;
3079
0
    case MCK_ConstantSImm9_0: return true;
3080
0
    case MCK_ConstantSImm10_0: return true;
3081
0
    case MCK_ConstantUImm10_0: return true;
3082
0
    case MCK_SImm10Lsl1: return true;
3083
0
    case MCK_ConstantSImm11_0: return true;
3084
0
    case MCK_SImm10Lsl2: return true;
3085
0
    case MCK_SImm10Lsl3: return true;
3086
0
    case MCK_SImm16: return true;
3087
0
    case MCK_SImm16_Relaxed: return true;
3088
0
    case MCK_UImm16_Relaxed: return true;
3089
0
    case MCK_ConstantUImm20_0: return true;
3090
0
    case MCK_ConstantUImm26_0: return true;
3091
0
    case MCK_SImm32: return true;
3092
0
    case MCK_SImm32_Relaxed: return true;
3093
0
    case MCK_UImm32_Coerced: return true;
3094
0
    }
3095
0
3096
0
  case MCK_UImm7_N1:
3097
0
    switch (B) {
3098
0
    default: return false;
3099
0
    case MCK_ConstantUImm8_0: return true;
3100
0
    case MCK_SImm7Lsl2: return true;
3101
0
    case MCK_ConstantSImm9_0: return true;
3102
0
    case MCK_ConstantSImm10_0: return true;
3103
0
    case MCK_ConstantUImm10_0: return true;
3104
0
    case MCK_SImm10Lsl1: return true;
3105
0
    case MCK_ConstantSImm11_0: return true;
3106
0
    case MCK_SImm10Lsl2: return true;
3107
0
    case MCK_SImm10Lsl3: return true;
3108
0
    case MCK_SImm16: return true;
3109
0
    case MCK_SImm16_Relaxed: return true;
3110
0
    case MCK_UImm16_Relaxed: return true;
3111
0
    case MCK_ConstantUImm20_0: return true;
3112
0
    case MCK_ConstantUImm26_0: return true;
3113
0
    case MCK_SImm32: return true;
3114
0
    case MCK_SImm32_Relaxed: return true;
3115
0
    case MCK_UImm32_Coerced: return true;
3116
0
    }
3117
0
3118
0
  case MCK_ConstantUImm8_0:
3119
0
    switch (B) {
3120
0
    default: return false;
3121
0
    case MCK_SImm7Lsl2: return true;
3122
0
    case MCK_ConstantSImm9_0: return true;
3123
0
    case MCK_ConstantSImm10_0: return true;
3124
0
    case MCK_ConstantUImm10_0: return true;
3125
0
    case MCK_SImm10Lsl1: return true;
3126
0
    case MCK_ConstantSImm11_0: return true;
3127
0
    case MCK_SImm10Lsl2: return true;
3128
0
    case MCK_SImm10Lsl3: return true;
3129
0
    case MCK_SImm16: return true;
3130
0
    case MCK_SImm16_Relaxed: return true;
3131
0
    case MCK_UImm16_Relaxed: return true;
3132
0
    case MCK_ConstantUImm20_0: return true;
3133
0
    case MCK_ConstantUImm26_0: return true;
3134
0
    case MCK_SImm32: return true;
3135
0
    case MCK_SImm32_Relaxed: return true;
3136
0
    case MCK_UImm32_Coerced: return true;
3137
0
    }
3138
0
3139
0
  case MCK_SImm7Lsl2:
3140
0
    switch (B) {
3141
0
    default: return false;
3142
0
    case MCK_ConstantSImm9_0: return true;
3143
0
    case MCK_ConstantSImm10_0: return true;
3144
0
    case MCK_ConstantUImm10_0: return true;
3145
0
    case MCK_SImm10Lsl1: return true;
3146
0
    case MCK_ConstantSImm11_0: return true;
3147
0
    case MCK_SImm10Lsl2: return true;
3148
0
    case MCK_SImm10Lsl3: return true;
3149
0
    case MCK_SImm16: return true;
3150
0
    case MCK_SImm16_Relaxed: return true;
3151
0
    case MCK_UImm16_Relaxed: return true;
3152
0
    case MCK_ConstantUImm20_0: return true;
3153
0
    case MCK_ConstantUImm26_0: return true;
3154
0
    case MCK_SImm32: return true;
3155
0
    case MCK_SImm32_Relaxed: return true;
3156
0
    case MCK_UImm32_Coerced: return true;
3157
0
    }
3158
0
3159
0
  case MCK_ConstantSImm9_0:
3160
0
    switch (B) {
3161
0
    default: return false;
3162
0
    case MCK_ConstantSImm10_0: return true;
3163
0
    case MCK_ConstantUImm10_0: return true;
3164
0
    case MCK_SImm10Lsl1: return true;
3165
0
    case MCK_ConstantSImm11_0: return true;
3166
0
    case MCK_SImm10Lsl2: return true;
3167
0
    case MCK_SImm10Lsl3: return true;
3168
0
    case MCK_SImm16: return true;
3169
0
    case MCK_SImm16_Relaxed: return true;
3170
0
    case MCK_UImm16_Relaxed: return true;
3171
0
    case MCK_ConstantUImm20_0: return true;
3172
0
    case MCK_ConstantUImm26_0: return true;
3173
0
    case MCK_SImm32: return true;
3174
0
    case MCK_SImm32_Relaxed: return true;
3175
0
    case MCK_UImm32_Coerced: return true;
3176
0
    }
3177
0
3178
0
  case MCK_ConstantSImm10_0:
3179
0
    switch (B) {
3180
0
    default: return false;
3181
0
    case MCK_ConstantUImm10_0: return true;
3182
0
    case MCK_SImm10Lsl1: return true;
3183
0
    case MCK_ConstantSImm11_0: return true;
3184
0
    case MCK_SImm10Lsl2: return true;
3185
0
    case MCK_SImm10Lsl3: return true;
3186
0
    case MCK_SImm16: return true;
3187
0
    case MCK_SImm16_Relaxed: return true;
3188
0
    case MCK_UImm16_Relaxed: return true;
3189
0
    case MCK_ConstantUImm20_0: return true;
3190
0
    case MCK_ConstantUImm26_0: return true;
3191
0
    case MCK_SImm32: return true;
3192
0
    case MCK_SImm32_Relaxed: return true;
3193
0
    case MCK_UImm32_Coerced: return true;
3194
0
    }
3195
0
3196
10
  case MCK_ConstantUImm10_0:
3197
10
    switch (B) {
3198
10
    default: return false;
3199
10
    
case MCK_SImm10Lsl1: return true0
;
3200
10
    
case MCK_ConstantSImm11_0: return true0
;
3201
10
    
case MCK_SImm10Lsl2: return true0
;
3202
10
    
case MCK_SImm10Lsl3: return true0
;
3203
10
    
case MCK_SImm16: return true0
;
3204
10
    
case MCK_SImm16_Relaxed: return true0
;
3205
10
    
case MCK_UImm16_Relaxed: return true0
;
3206
10
    
case MCK_ConstantUImm20_0: return true0
;
3207
10
    
case MCK_ConstantUImm26_0: return true0
;
3208
10
    
case MCK_SImm32: return true0
;
3209
10
    
case MCK_SImm32_Relaxed: return true0
;
3210
10
    
case MCK_UImm32_Coerced: return true0
;
3211
0
    }
3212
0
3213
0
  case MCK_SImm10Lsl1:
3214
0
    switch (B) {
3215
0
    default: return false;
3216
0
    case MCK_ConstantSImm11_0: return true;
3217
0
    case MCK_SImm10Lsl2: return true;
3218
0
    case MCK_SImm10Lsl3: return true;
3219
0
    case MCK_SImm16: return true;
3220
0
    case MCK_SImm16_Relaxed: return true;
3221
0
    case MCK_UImm16_Relaxed: return true;
3222
0
    case MCK_ConstantUImm20_0: return true;
3223
0
    case MCK_ConstantUImm26_0: return true;
3224
0
    case MCK_SImm32: return true;
3225
0
    case MCK_SImm32_Relaxed: return true;
3226
0
    case MCK_UImm32_Coerced: return true;
3227
0
    }
3228
0
3229
0
  case MCK_ConstantSImm11_0:
3230
0
    switch (B) {
3231
0
    default: return false;
3232
0
    case MCK_SImm10Lsl2: return true;
3233
0
    case MCK_SImm10Lsl3: return true;
3234
0
    case MCK_SImm16: return true;
3235
0
    case MCK_SImm16_Relaxed: return true;
3236
0
    case MCK_UImm16_Relaxed: return true;
3237
0
    case MCK_ConstantUImm20_0: return true;
3238
0
    case MCK_ConstantUImm26_0: return true;
3239
0
    case MCK_SImm32: return true;
3240
0
    case MCK_SImm32_Relaxed: return true;
3241
0
    case MCK_UImm32_Coerced: return true;
3242
0
    }
3243
0
3244
0
  case MCK_SImm10Lsl2:
3245
0
    switch (B) {
3246
0
    default: return false;
3247
0
    case MCK_SImm10Lsl3: return true;
3248
0
    case MCK_SImm16: return true;
3249
0
    case MCK_SImm16_Relaxed: return true;
3250
0
    case MCK_UImm16_Relaxed: return true;
3251
0
    case MCK_ConstantUImm20_0: return true;
3252
0
    case MCK_ConstantUImm26_0: return true;
3253
0
    case MCK_SImm32: return true;
3254
0
    case MCK_SImm32_Relaxed: return true;
3255
0
    case MCK_UImm32_Coerced: return true;
3256
0
    }
3257
0
3258
0
  case MCK_SImm10Lsl3:
3259
0
    switch (B) {
3260
0
    default: return false;
3261
0
    case MCK_SImm16: return true;
3262
0
    case MCK_SImm16_Relaxed: return true;
3263
0
    case MCK_UImm16_Relaxed: return true;
3264
0
    case MCK_ConstantUImm20_0: return true;
3265
0
    case MCK_ConstantUImm26_0: return true;
3266
0
    case MCK_SImm32: return true;
3267
0
    case MCK_SImm32_Relaxed: return true;
3268
0
    case MCK_UImm32_Coerced: return true;
3269
0
    }
3270
0
3271
10
  case MCK_SImm16:
3272
10
    switch (B) {
3273
10
    default: return false;
3274
10
    
case MCK_SImm16_Relaxed: return true0
;
3275
10
    
case MCK_UImm16_Relaxed: return true0
;
3276
10
    
case MCK_ConstantUImm20_0: return true0
;
3277
10
    
case MCK_ConstantUImm26_0: return true0
;
3278
10
    
case MCK_SImm32: return true0
;
3279
10
    
case MCK_SImm32_Relaxed: return true0
;
3280
10
    
case MCK_UImm32_Coerced: return true0
;
3281
0
    }
3282
0
3283
0
  case MCK_SImm16_Relaxed:
3284
0
    switch (B) {
3285
0
    default: return false;
3286
0
    case MCK_UImm16_Relaxed: return true;
3287
0
    case MCK_ConstantUImm20_0: return true;
3288
0
    case MCK_ConstantUImm26_0: return true;
3289
0
    case MCK_SImm32: return true;
3290
0
    case MCK_SImm32_Relaxed: return true;
3291
0
    case MCK_UImm32_Coerced: return true;
3292
0
    }
3293
0
3294
0
  case MCK_UImm16_AltRelaxed:
3295
0
    switch (B) {
3296
0
    default: return false;
3297
0
    case MCK_UImm16_Relaxed: return true;
3298
0
    case MCK_ConstantUImm20_0: return true;
3299
0
    case MCK_ConstantUImm26_0: return true;
3300
0
    case MCK_SImm32: return true;
3301
0
    case MCK_SImm32_Relaxed: return true;
3302
0
    case MCK_UImm32_Coerced: return true;
3303
0
    }
3304
0
3305
0
  case MCK_UImm16:
3306
0
    switch (B) {
3307
0
    default: return false;
3308
0
    case MCK_UImm16_Relaxed: return true;
3309
0
    case MCK_ConstantUImm20_0: return true;
3310
0
    case MCK_ConstantUImm26_0: return true;
3311
0
    case MCK_SImm32: return true;
3312
0
    case MCK_SImm32_Relaxed: return true;
3313
0
    case MCK_UImm32_Coerced: return true;
3314
0
    }
3315
0
3316
0
  case MCK_SImm19Lsl2:
3317
0
    switch (B) {
3318
0
    default: return false;
3319
0
    case MCK_ConstantUImm20_0: return true;
3320
0
    case MCK_ConstantUImm26_0: return true;
3321
0
    case MCK_SImm32: return true;
3322
0
    case MCK_SImm32_Relaxed: return true;
3323
0
    case MCK_UImm32_Coerced: return true;
3324
0
    }
3325
0
3326
0
  case MCK_UImm16_Relaxed:
3327
0
    switch (B) {
3328
0
    default: return false;
3329
0
    case MCK_ConstantUImm20_0: return true;
3330
0
    case MCK_ConstantUImm26_0: return true;
3331
0
    case MCK_SImm32: return true;
3332
0
    case MCK_SImm32_Relaxed: return true;
3333
0
    case MCK_UImm32_Coerced: return true;
3334
0
    }
3335
0
3336
0
  case MCK_ConstantUImm20_0:
3337
0
    switch (B) {
3338
0
    default: return false;
3339
0
    case MCK_ConstantUImm26_0: return true;
3340
0
    case MCK_SImm32: return true;
3341
0
    case MCK_SImm32_Relaxed: return true;
3342
0
    case MCK_UImm32_Coerced: return true;
3343
0
    }
3344
0
3345
0
  case MCK_ConstantUImm26_0:
3346
0
    switch (B) {
3347
0
    default: return false;
3348
0
    case MCK_SImm32: return true;
3349
0
    case MCK_SImm32_Relaxed: return true;
3350
0
    case MCK_UImm32_Coerced: return true;
3351
0
    }
3352
0
3353
0
  case MCK_SImm32:
3354
0
    switch (B) {
3355
0
    default: return false;
3356
0
    case MCK_SImm32_Relaxed: return true;
3357
0
    case MCK_UImm32_Coerced: return true;
3358
0
    }
3359
0
3360
0
  case MCK_SImm32_Relaxed:
3361
0
    return B == MCK_UImm32_Coerced;
3362
38.6k
  }
3363
38.6k
}
3364
3365
162k
static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
3366
162k
  MipsOperand &Operand = (MipsOperand&)GOp;
3367
162k
  if (Kind == InvalidMatchClass)
3368
5.06k
    return MCTargetAsmParser::Match_InvalidOperand;
3369
157k
3370
157k
  if (Operand.isToken() && 
Kind <= MCK_LAST_TOKEN880
)
3371
880
    return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
3372
880
             MCTargetAsmParser::Match_Success :
3373
880
             
MCTargetAsmParser::Match_InvalidOperand0
;
3374
156k
3375
156k
  switch (Kind) {
3376
156k
  
default: break14.5k
;
3377
156k
  // 'ACC64DSPAsmReg' class
3378
156k
  case MCK_ACC64DSPAsmReg: {
3379
571
    DiagnosticPredicate DP(Operand.isACCAsmReg());
3380
571
    if (DP.isMatch())
3381
420
      return MCTargetAsmParser::Match_Success;
3382
151
    break;
3383
151
    }
3384
151
  // 'AFGR64AsmReg' class
3385
4.71k
  case MCK_AFGR64AsmReg: {
3386
4.71k
    DiagnosticPredicate DP(Operand.isFGRAsmReg());
3387
4.71k
    if (DP.isMatch())
3388
4.21k
      return MCTargetAsmParser::Match_Success;
3389
498
    break;
3390
498
    }
3391
498
  // 'CCRAsmReg' class
3392
498
  case MCK_CCRAsmReg: {
3393
46
    DiagnosticPredicate DP(Operand.isCCRAsmReg());
3394
46
    if (DP.isMatch())
3395
46
      return MCTargetAsmParser::Match_Success;
3396
0
    break;
3397
0
    }
3398
0
  // 'COP0AsmReg' class
3399
680
  case MCK_COP0AsmReg: {
3400
680
    DiagnosticPredicate DP(Operand.isCOP0AsmReg());
3401
680
    if (DP.isMatch())
3402
548
      return MCTargetAsmParser::Match_Success;
3403
132
    break;
3404
132
    }
3405
132
  // 'COP2AsmReg' class
3406
566
  case MCK_COP2AsmReg: {
3407
566
    DiagnosticPredicate DP(Operand.isCOP2AsmReg());
3408
566
    if (DP.isMatch())
3409
564
      return MCTargetAsmParser::Match_Success;
3410
2
    break;
3411
2
    }
3412
2
  // 'COP3AsmReg' class
3413
16
  case MCK_COP3AsmReg: {
3414
16
    DiagnosticPredicate DP(Operand.isCOP3AsmReg());
3415
16
    if (DP.isMatch())
3416
16
      return MCTargetAsmParser::Match_Success;
3417
0
    break;
3418
0
    }
3419
0
  // 'FCCAsmReg' class
3420
2.07k
  case MCK_FCCAsmReg: {
3421
2.07k
    DiagnosticPredicate DP(Operand.isFCCAsmReg());
3422
2.07k
    if (DP.isMatch())
3423
1.65k
      return MCTargetAsmParser::Match_Success;
3424
418
    break;
3425
418
    }
3426
418
  // 'FGR32AsmReg' class
3427
6.73k
  case MCK_FGR32AsmReg: {
3428
6.73k
    DiagnosticPredicate DP(Operand.isFGRAsmReg());
3429
6.73k
    if (DP.isMatch())
3430
6.18k
      return MCTargetAsmParser::Match_Success;
3431
545
    break;
3432
545
    }
3433
545
  // 'FGR64AsmReg' class
3434
4.21k
  case MCK_FGR64AsmReg: {
3435
4.21k
    DiagnosticPredicate DP(Operand.isFGRAsmReg());
3436
4.21k
    if (DP.isMatch())
3437
3.71k
      return MCTargetAsmParser::Match_Success;
3438
500
    break;
3439
500
    }
3440
500
  // 'FGRH32AsmReg' class
3441
500
  case MCK_FGRH32AsmReg: {
3442
0
    DiagnosticPredicate DP(Operand.isFGRAsmReg());
3443
0
    if (DP.isMatch())
3444
0
      return MCTargetAsmParser::Match_Success;
3445
0
    break;
3446
0
    }
3447
0
  // 'GPR32AsmReg' class
3448
66.0k
  case MCK_GPR32AsmReg: {
3449
66.0k
    DiagnosticPredicate DP(Operand.isGPRAsmReg());
3450
66.0k
    if (DP.isMatch())
3451
62.3k
      return MCTargetAsmParser::Match_Success;
3452
3.71k
    break;
3453
3.71k
    }
3454
3.71k
  // 'GPR32NonZeroAsmReg' class
3455
3.71k
  case MCK_GPR32NonZeroAsmReg: {
3456
130
    DiagnosticPredicate DP(Operand.isGPRNonZeroAsmReg());
3457
130
    if (DP.isMatch())
3458
76
      return MCTargetAsmParser::Match_Success;
3459
54
    break;
3460
54
    }
3461
54
  // 'GPR32ZeroAsmReg' class
3462
100
  case MCK_GPR32ZeroAsmReg: {
3463
100
    DiagnosticPredicate DP(Operand.isGPRZeroAsmReg());
3464
100
    if (DP.isMatch())
3465
54
      return MCTargetAsmParser::Match_Success;
3466
46
    break;
3467
46
    }
3468
46
  // 'GPR64AsmReg' class
3469
8.32k
  case MCK_GPR64AsmReg: {
3470
8.32k
    DiagnosticPredicate DP(Operand.isGPRAsmReg());
3471
8.32k
    if (DP.isMatch())
3472
7.86k
      return MCTargetAsmParser::Match_Success;
3473
461
    break;
3474
461
    }
3475
461
  // 'GPRMM16AsmReg' class
3476
461
  case MCK_GPRMM16AsmReg: {
3477
269
    DiagnosticPredicate DP(Operand.isMM16AsmReg());
3478
269
    if (DP.isMatch())
3479
234
      return MCTargetAsmParser::Match_Success;
3480
35
    break;
3481
35
    }
3482
35
  // 'GPRMM16AsmRegMoveP' class
3483
35
  case MCK_GPRMM16AsmRegMoveP: {
3484
22
    DiagnosticPredicate DP(Operand.isMM16AsmRegMoveP());
3485
22
    if (DP.isMatch())
3486
14
      return MCTargetAsmParser::Match_Success;
3487
8
    break;
3488
8
    }
3489
8
  // 'GPRMM16AsmRegZero' class
3490
65
  case MCK_GPRMM16AsmRegZero: {
3491
65
    DiagnosticPredicate DP(Operand.isMM16AsmRegZero());
3492
65
    if (DP.isMatch())
3493
41
      return MCTargetAsmParser::Match_Success;
3494
24
    break;
3495
24
    }
3496
24
  // 'HI32DSPAsmReg' class
3497
24
  case MCK_HI32DSPAsmReg: {
3498
9
    DiagnosticPredicate DP(Operand.isACCAsmReg());
3499
9
    if (DP.isMatch())
3500
9
      return MCTargetAsmParser::Match_Success;
3501
0
    break;
3502
0
    }
3503
0
  // 'HWRegsAsmReg' class
3504
81
  case MCK_HWRegsAsmReg: {
3505
81
    DiagnosticPredicate DP(Operand.isHWRegsAsmReg());
3506
81
    if (DP.isMatch())
3507
81
      return MCTargetAsmParser::Match_Success;
3508
0
    break;
3509
0
    }
3510
0
  // 'Imm' class
3511
2.97k
  case MCK_Imm: {
3512
2.97k
    DiagnosticPredicate DP(Operand.isImm());
3513
2.97k
    if (DP.isMatch())
3514
1.95k
      return MCTargetAsmParser::Match_Success;
3515
1.02k
    break;
3516
1.02k
    }
3517
1.02k
  // 'LO32DSPAsmReg' class
3518
1.02k
  case MCK_LO32DSPAsmReg: {
3519
9
    DiagnosticPredicate DP(Operand.isACCAsmReg());
3520
9
    if (DP.isMatch())
3521
9
      return MCTargetAsmParser::Match_Success;
3522
0
    break;
3523
0
    }
3524
0
  // 'MSA128AsmReg' class
3525
2.13k
  case MCK_MSA128AsmReg: {
3526
2.13k
    DiagnosticPredicate DP(Operand.isMSA128AsmReg());
3527
2.13k
    if (DP.isMatch())
3528
2.13k
      return MCTargetAsmParser::Match_Success;
3529
0
    break;
3530
0
    }
3531
0
  // 'MSACtrlAsmReg' class
3532
38
  case MCK_MSACtrlAsmReg: {
3533
38
    DiagnosticPredicate DP(Operand.isMSACtrlAsmReg());
3534
38
    if (DP.isMatch())
3535
32
      return MCTargetAsmParser::Match_Success;
3536
6
    break;
3537
6
    }
3538
6
  // 'MicroMipsMemGP' class
3539
6
  case MCK_MicroMipsMemGP: {
3540
0
    DiagnosticPredicate DP(Operand.isMemWithSimmWordAlignedOffsetGP<9>());
3541
0
    if (DP.isMatch())
3542
0
      return MCTargetAsmParser::Match_Success;
3543
0
    break;
3544
0
    }
3545
0
  // 'MicroMipsMem' class
3546
75
  case MCK_MicroMipsMem: {
3547
75
    DiagnosticPredicate DP(Operand.isMemWithGRPMM16Base());
3548
75
    if (DP.isMatch())
3549
57
      return MCTargetAsmParser::Match_Success;
3550
18
    break;
3551
18
    }
3552
18
  // 'MicroMipsMemSP' class
3553
10.4k
  case MCK_MicroMipsMemSP: {
3554
10.4k
    DiagnosticPredicate DP(Operand.isMemWithUimmWordAlignedOffsetSP<7>());
3555
10.4k
    if (DP.isMatch())
3556
57
      return MCTargetAsmParser::Match_Success;
3557
10.4k
    break;
3558
10.4k
    }
3559
10.4k
  // 'InvNum' class
3560
10.4k
  case MCK_InvNum: {
3561
245
    DiagnosticPredicate DP(Operand.isInvNum());
3562
245
    if (DP.isMatch())
3563
106
      return MCTargetAsmParser::Match_Success;
3564
139
    break;
3565
139
    }
3566
139
  // 'JumpTarget' class
3567
2.58k
  case MCK_JumpTarget: {
3568
2.58k
    DiagnosticPredicate DP(Operand.isImm());
3569
2.58k
    if (DP.isMatch())
3570
2.26k
      return MCTargetAsmParser::Match_Success;
3571
322
    break;
3572
322
    }
3573
322
  // 'MemOffsetSimm10' class
3574
322
  case MCK_MemOffsetSimm10: {
3575
7
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10>());
3576
7
    if (DP.isMatch())
3577
3
      return MCTargetAsmParser::Match_Success;
3578
4
    if (DP.isNearMatch())
3579
4
      return MipsAsmParser::Match_MemSImm10;
3580
0
    break;
3581
0
    }
3582
0
  // 'MemOffsetSimm10_1' class
3583
9
  case MCK_MemOffsetSimm10_1: {
3584
9
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 1>());
3585
9
    if (DP.isMatch())
3586
5
      return MCTargetAsmParser::Match_Success;
3587
4
    if (DP.isNearMatch())
3588
4
      return MipsAsmParser::Match_MemSImm10Lsl1;
3589
0
    break;
3590
0
    }
3591
0
  // 'MemOffsetSimm10_2' class
3592
10
  case MCK_MemOffsetSimm10_2: {
3593
10
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 2>());
3594
10
    if (DP.isMatch())
3595
6
      return MCTargetAsmParser::Match_Success;
3596
4
    if (DP.isNearMatch())
3597
4
      return MipsAsmParser::Match_MemSImm10Lsl2;
3598
0
    break;
3599
0
    }
3600
0
  // 'MemOffsetSimm10_3' class
3601
13
  case MCK_MemOffsetSimm10_3: {
3602
13
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 3>());
3603
13
    if (DP.isMatch())
3604
9
      return MCTargetAsmParser::Match_Success;
3605
4
    if (DP.isNearMatch())
3606
4
      return MipsAsmParser::Match_MemSImm10Lsl3;
3607
0
    break;
3608
0
    }
3609
0
  // 'MemOffsetSimm11' class
3610
304
  case MCK_MemOffsetSimm11: {
3611
304
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<11>());
3612
304
    if (DP.isMatch())
3613
58
      return MCTargetAsmParser::Match_Success;
3614
246
    if (DP.isNearMatch())
3615
246
      return MipsAsmParser::Match_MemSImm11;
3616
0
    break;
3617
0
    }
3618
0
  // 'MemOffsetSimm12' class
3619
40
  case MCK_MemOffsetSimm12: {
3620
40
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<12>());
3621
40
    if (DP.isMatch())
3622
25
      return MCTargetAsmParser::Match_Success;
3623
15
    if (DP.isNearMatch())
3624
15
      return MipsAsmParser::Match_MemSImm12;
3625
0
    break;
3626
0
    }
3627
0
  // 'MemOffsetSimm16' class
3628
975
  case MCK_MemOffsetSimm16: {
3629
975
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<16>());
3630
975
    if (DP.isMatch())
3631
688
      return MCTargetAsmParser::Match_Success;
3632
287
    if (DP.isNearMatch())
3633
287
      return MipsAsmParser::Match_MemSImm16;
3634
0
    break;
3635
0
    }
3636
0
  // 'MemOffsetSimm9' class
3637
1.83k
  case MCK_MemOffsetSimm9: {
3638
1.83k
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<9>());
3639
1.83k
    if (DP.isMatch())
3640
586
      return MCTargetAsmParser::Match_Success;
3641
1.25k
    if (DP.isNearMatch())
3642
1.25k
      return MipsAsmParser::Match_MemSImm9;
3643
0
    break;
3644
0
    }
3645
0
  // 'MemOffsetSimmPtr' class
3646
379
  case MCK_MemOffsetSimmPtr: {
3647
379
    DiagnosticPredicate DP(Operand.isMemWithPtrSizeOffset());
3648
379
    if (DP.isMatch())
3649
333
      return MCTargetAsmParser::Match_Success;
3650
46
    if (DP.isNearMatch())
3651
46
      return MipsAsmParser::Match_MemSImmPtr;
3652
0
    break;
3653
0
    }
3654
0
  // 'MemOffsetUimm4' class
3655
18
  case MCK_MemOffsetUimm4: {
3656
18
    DiagnosticPredicate DP(Operand.isMemWithUimmOffsetSP<6>());
3657
18
    if (DP.isMatch())
3658
10
      return MCTargetAsmParser::Match_Success;
3659
8
    break;
3660
8
    }
3661
8
  // 'Mem' class
3662
12.0k
  case MCK_Mem: {
3663
12.0k
    DiagnosticPredicate DP(Operand.isMem());
3664
12.0k
    if (DP.isMatch())
3665
11.8k
      return MCTargetAsmParser::Match_Success;
3666
148
    break;
3667
148
    }
3668
148
  // 'MovePRegPair' class
3669
148
  case MCK_MovePRegPair: {
3670
21
    DiagnosticPredicate DP(Operand.isMovePRegPair());
3671
21
    if (DP.isMatch())
3672
13
      return MCTargetAsmParser::Match_Success;
3673
8
    break;
3674
8
    }
3675
8
  // 'RegList16' class
3676
36
  case MCK_RegList16: {
3677
36
    DiagnosticPredicate DP(Operand.isRegList16());
3678
36
    if (DP.isMatch())
3679
18
      return MCTargetAsmParser::Match_Success;
3680
18
    break;
3681
18
    }
3682
18
  // 'RegList' class
3683
55
  case MCK_RegList: {
3684
55
    DiagnosticPredicate DP(Operand.isRegList());
3685
55
    if (DP.isMatch())
3686
55
      return MCTargetAsmParser::Match_Success;
3687
0
    break;
3688
0
    }
3689
0
  // 'Simm19_Lsl2' class
3690
94
  case MCK_Simm19_Lsl2: {
3691
94
    DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>());
3692
94
    if (DP.isMatch())
3693
52
      return MCTargetAsmParser::Match_Success;
3694
42
    if (DP.isNearMatch())
3695
42
      return MipsAsmParser::Match_SImm19_Lsl2;
3696
0
    break;
3697
0
    }
3698
0
  // 'StrictlyAFGR64AsmReg' class
3699
91
  case MCK_StrictlyAFGR64AsmReg: {
3700
91
    DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
3701
91
    if (DP.isMatch())
3702
91
      return MCTargetAsmParser::Match_Success;
3703
0
    break;
3704
0
    }
3705
0
  // 'StrictlyFGR32AsmReg' class
3706
66
  case MCK_StrictlyFGR32AsmReg: {
3707
66
    DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
3708
66
    if (DP.isMatch())
3709
66
      return MCTargetAsmParser::Match_Success;
3710
0
    break;
3711
0
    }
3712
0
  // 'StrictlyFGR64AsmReg' class
3713
52
  case MCK_StrictlyFGR64AsmReg: {
3714
52
    DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
3715
52
    if (DP.isMatch())
3716
52
      return MCTargetAsmParser::Match_Success;
3717
0
    break;
3718
0
    }
3719
0
  // 'ConstantImmz' class
3720
12
  case MCK_ConstantImmz: {
3721
12
    DiagnosticPredicate DP(Operand.isConstantImmz());
3722
12
    if (DP.isMatch())
3723
4
      return MCTargetAsmParser::Match_Success;
3724
8
    if (DP.isNearMatch())
3725
8
      return MipsAsmParser::Match_Immz;
3726
0
    break;
3727
0
    }
3728
0
  // 'ConstantUImm1_0' class
3729
69
  case MCK_ConstantUImm1_0: {
3730
69
    DiagnosticPredicate DP(Operand.isConstantUImm<1, 0>());
3731
69
    if (DP.isMatch())
3732
55
      return MCTargetAsmParser::Match_Success;
3733
14
    if (DP.isNearMatch())
3734
14
      return MipsAsmParser::Match_UImm1_0;
3735
0
    break;
3736
0
    }
3737
0
  // 'ConstantUImm2_0' class
3738
85
  case MCK_ConstantUImm2_0: {
3739
85
    DiagnosticPredicate DP(Operand.isConstantUImm<2, 0>());
3740
85
    if (DP.isMatch())
3741
31
      return MCTargetAsmParser::Match_Success;
3742
54
    if (DP.isNearMatch())
3743
54
      return MipsAsmParser::Match_UImm2_0;
3744
0
    break;
3745
0
    }
3746
0
  // 'ConstantUImm2_1' class
3747
56
  case MCK_ConstantUImm2_1: {
3748
56
    DiagnosticPredicate DP(Operand.isConstantUImm<2, 1>());
3749
56
    if (DP.isMatch())
3750
18
      return MCTargetAsmParser::Match_Success;
3751
38
    if (DP.isNearMatch())
3752
38
      return MipsAsmParser::Match_UImm2_1;
3753
0
    break;
3754
0
    }
3755
0
  // 'ConstantUImm3_0' class
3756
410
  case MCK_ConstantUImm3_0: {
3757
410
    DiagnosticPredicate DP(Operand.isConstantUImm<3, 0>());
3758
410
    if (DP.isMatch())
3759
229
      return MCTargetAsmParser::Match_Success;
3760
181
    if (DP.isNearMatch())
3761
181
      return MipsAsmParser::Match_UImm3_0;
3762
0
    break;
3763
0
    }
3764
0
  // 'ConstantSImm4_0' class
3765
8
  case MCK_ConstantSImm4_0: {
3766
8
    DiagnosticPredicate DP(Operand.isConstantSImm<4, 0>());
3767
8
    if (DP.isMatch())
3768
4
      return MCTargetAsmParser::Match_Success;
3769
4
    if (DP.isNearMatch())
3770
4
      return MipsAsmParser::Match_SImm4_0;
3771
0
    break;
3772
0
    }
3773
0
  // 'ConstantUImm4_0' class
3774
291
  case MCK_ConstantUImm4_0: {
3775
291
    DiagnosticPredicate DP(Operand.isConstantUImm<4, 0>());
3776
291
    if (DP.isMatch())
3777
81
      return MCTargetAsmParser::Match_Success;
3778
210
    if (DP.isNearMatch())
3779
210
      return MipsAsmParser::Match_UImm4_0;
3780
0
    break;
3781
0
    }
3782
0
  // 'ConstantSImm5_0' class
3783
60
  case MCK_ConstantSImm5_0: {
3784
60
    DiagnosticPredicate DP(Operand.isConstantSImm<5, 0>());
3785
60
    if (DP.isMatch())
3786
20
      return MCTargetAsmParser::Match_Success;
3787
40
    if (DP.isNearMatch())
3788
40
      return MipsAsmParser::Match_SImm5_0;
3789
0
    break;
3790
0
    }
3791
0
  // 'ConstantUImm5_0' class
3792
2.09k
  case MCK_ConstantUImm5_0: {
3793
2.09k
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>());
3794
2.09k
    if (DP.isMatch())
3795
869
      return MCTargetAsmParser::Match_Success;
3796
1.22k
    if (DP.isNearMatch())
3797
1.22k
      return MipsAsmParser::Match_UImm5_0;
3798
0
    break;
3799
0
    }
3800
0
  // 'ConstantUImm5_1' class
3801
129
  case MCK_ConstantUImm5_1: {
3802
129
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>());
3803
129
    if (DP.isMatch())
3804
79
      return MCTargetAsmParser::Match_Success;
3805
50
    if (DP.isNearMatch())
3806
50
      return MipsAsmParser::Match_UImm5_1;
3807
0
    break;
3808
0
    }
3809
0
  // 'ConstantUImm5_Plus1_Report_UImm6' class
3810
11
  case MCK_ConstantUImm5_Plus1_Report_UImm6: {
3811
11
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>());
3812
11
    if (DP.isMatch())
3813
9
      return MCTargetAsmParser::Match_Success;
3814
2
    if (DP.isNearMatch())
3815
2
      return MipsAsmParser::Match_UImm5_1;
3816
0
    break;
3817
0
    }
3818
0
  // 'ConstantUImm5_32_Norm' class
3819
16
  case MCK_ConstantUImm5_32_Norm: {
3820
16
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>());
3821
16
    if (DP.isMatch())
3822
6
      return MCTargetAsmParser::Match_Success;
3823
10
    if (DP.isNearMatch())
3824
10
      return MipsAsmParser::Match_UImm5_32;
3825
0
    break;
3826
0
    }
3827
0
  // 'ConstantUImm5_32' class
3828
76
  case MCK_ConstantUImm5_32: {
3829
76
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>());
3830
76
    if (DP.isMatch())
3831
34
      return MCTargetAsmParser::Match_Success;
3832
42
    if (DP.isNearMatch())
3833
42
      return MipsAsmParser::Match_UImm5_32;
3834
0
    break;
3835
0
    }
3836
0
  // 'ConstantUImm5_0_Report_UImm6' class
3837
23
  case MCK_ConstantUImm5_0_Report_UImm6: {
3838
23
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>());
3839
23
    if (DP.isMatch())
3840
13
      return MCTargetAsmParser::Match_Success;
3841
10
    if (DP.isNearMatch())
3842
10
      return MipsAsmParser::Match_UImm5_0_Report_UImm6;
3843
0
    break;
3844
0
    }
3845
0
  // 'ConstantUImm5_33' class
3846
26
  case MCK_ConstantUImm5_33: {
3847
26
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 33>());
3848
26
    if (DP.isMatch())
3849
11
      return MCTargetAsmParser::Match_Success;
3850
15
    if (DP.isNearMatch())
3851
15
      return MipsAsmParser::Match_UImm5_33;
3852
0
    break;
3853
0
    }
3854
0
  // 'ConstantUImmRange2_64' class
3855
28
  case MCK_ConstantUImmRange2_64: {
3856
28
    DiagnosticPredicate DP(Operand.isConstantUImmRange<2, 64>());
3857
28
    if (DP.isMatch())
3858
18
      return MCTargetAsmParser::Match_Success;
3859
10
    if (DP.isNearMatch())
3860
10
      return MipsAsmParser::Match_UImmRange2_64;
3861
0
    break;
3862
0
    }
3863
0
  // 'UImm5Lsl2' class
3864
26
  case MCK_UImm5Lsl2: {
3865
26
    DiagnosticPredicate DP(Operand.isScaledUImm<5, 2>());
3866
26
    if (DP.isMatch())
3867
4
      return MCTargetAsmParser::Match_Success;
3868
22
    if (DP.isNearMatch())
3869
22
      return MipsAsmParser::Match_UImm5_Lsl2;
3870
0
    break;
3871
0
    }
3872
0
  // 'ConstantSImm6_0' class
3873
22
  case MCK_ConstantSImm6_0: {
3874
22
    DiagnosticPredicate DP(Operand.isConstantSImm<6, 0>());
3875
22
    if (DP.isMatch())
3876
14
      return MCTargetAsmParser::Match_Success;
3877
8
    if (DP.isNearMatch())
3878
8
      return MipsAsmParser::Match_SImm6_0;
3879
0
    break;
3880
0
    }
3881
0
  // 'ConstantUImm6_0' class
3882
302
  case MCK_ConstantUImm6_0: {
3883
302
    DiagnosticPredicate DP(Operand.isConstantUImm<6, 0>());
3884
302
    if (DP.isMatch())
3885
119
      return MCTargetAsmParser::Match_Success;
3886
183
    if (DP.isNearMatch())
3887
183
      return MipsAsmParser::Match_UImm6_0;
3888
0
    break;
3889
0
    }
3890
0
  // 'UImm6Lsl2' class
3891
10
  case MCK_UImm6Lsl2: {
3892
10
    DiagnosticPredicate DP(Operand.isScaledUImm<6, 2>());
3893
10
    if (DP.isMatch())
3894
4
      return MCTargetAsmParser::Match_Success;
3895
6
    if (DP.isNearMatch())
3896
6
      return MipsAsmParser::Match_UImm6_Lsl2;
3897
0
    break;
3898
0
    }
3899
0
  // 'ConstantUImm7_0' class
3900
19
  case MCK_ConstantUImm7_0: {
3901
19
    DiagnosticPredicate DP(Operand.isConstantUImm<7, 0>());
3902
19
    if (DP.isMatch())
3903
11
      return MCTargetAsmParser::Match_Success;
3904
8
    if (DP.isNearMatch())
3905
8
      return MipsAsmParser::Match_UImm7_0;
3906
0
    break;
3907
0
    }
3908
0
  // 'UImm7_N1' class
3909
16
  case MCK_UImm7_N1: {
3910
16
    DiagnosticPredicate DP(Operand.isConstantUImm<7, -1>());
3911
16
    if (DP.isMatch())
3912
8
      return MCTargetAsmParser::Match_Success;
3913
8
    if (DP.isNearMatch())
3914
8
      return MipsAsmParser::Match_UImm7_N1;
3915
0
    break;
3916
0
    }
3917
0
  // 'ConstantUImm8_0' class
3918
46
  case MCK_ConstantUImm8_0: {
3919
46
    DiagnosticPredicate DP(Operand.isConstantUImm<8, 0>());
3920
46
    if (DP.isMatch())
3921
19
      return MCTargetAsmParser::Match_Success;
3922
27
    if (DP.isNearMatch())
3923
27
      return MipsAsmParser::Match_UImm8_0;
3924
0
    break;
3925
0
    }
3926
0
  // 'SImm7Lsl2' class
3927
0
  case MCK_SImm7Lsl2: {
3928
0
    DiagnosticPredicate DP(Operand.isScaledSImm<7, 2>());
3929
0
    if (DP.isMatch())
3930
0
      return MCTargetAsmParser::Match_Success;
3931
0
    if (DP.isNearMatch())
3932
0
      return MipsAsmParser::Match_SImm7_Lsl2;
3933
0
    break;
3934
0
    }
3935
0
  // 'ConstantSImm9_0' class
3936
0
  case MCK_ConstantSImm9_0: {
3937
0
    DiagnosticPredicate DP(Operand.isConstantSImm<9, 0>());
3938
0
    if (DP.isMatch())
3939
0
      return MCTargetAsmParser::Match_Success;
3940
0
    if (DP.isNearMatch())
3941
0
      return MipsAsmParser::Match_SImm9_0;
3942
0
    break;
3943
0
    }
3944
0
  // 'ConstantSImm10_0' class
3945
44
  case MCK_ConstantSImm10_0: {
3946
44
    DiagnosticPredicate DP(Operand.isConstantSImm<10, 0>());
3947
44
    if (DP.isMatch())
3948
18
      return MCTargetAsmParser::Match_Success;
3949
26
    if (DP.isNearMatch())
3950
26
      return MipsAsmParser::Match_SImm10_0;
3951
0
    break;
3952
0
    }
3953
0
  // 'ConstantUImm10_0' class
3954
470
  case MCK_ConstantUImm10_0: {
3955
470
    DiagnosticPredicate DP(Operand.isConstantUImm<10, 0>());
3956
470
    if (DP.isMatch())
3957
258
      return MCTargetAsmParser::Match_Success;
3958
212
    if (DP.isNearMatch())
3959
212
      return MipsAsmParser::Match_UImm10_0;
3960
0
    break;
3961
0
    }
3962
0
  // 'SImm10Lsl1' class
3963
0
  case MCK_SImm10Lsl1: {
3964
0
    DiagnosticPredicate DP(Operand.isScaledSImm<10, 1>());
3965
0
    if (DP.isMatch())
3966
0
      return MCTargetAsmParser::Match_Success;
3967
0
    if (DP.isNearMatch())
3968
0
      return MipsAsmParser::Match_SImm10_Lsl1;
3969
0
    break;
3970
0
    }
3971
0
  // 'ConstantSImm11_0' class
3972
0
  case MCK_ConstantSImm11_0: {
3973
0
    DiagnosticPredicate DP(Operand.isConstantSImm<11, 0>());
3974
0
    if (DP.isMatch())
3975
0
      return MCTargetAsmParser::Match_Success;
3976
0
    if (DP.isNearMatch())
3977
0
      return MipsAsmParser::Match_SImm11_0;
3978
0
    break;
3979
0
    }
3980
0
  // 'SImm10Lsl2' class
3981
0
  case MCK_SImm10Lsl2: {
3982
0
    DiagnosticPredicate DP(Operand.isScaledSImm<10, 2>());
3983
0
    if (DP.isMatch())
3984
0
      return MCTargetAsmParser::Match_Success;
3985
0
    if (DP.isNearMatch())
3986
0
      return MipsAsmParser::Match_SImm10_Lsl2;
3987
0
    break;
3988
0
    }
3989
0
  // 'SImm10Lsl3' class
3990
0
  case MCK_SImm10Lsl3: {
3991
0
    DiagnosticPredicate DP(Operand.isScaledSImm<10, 3>());
3992
0
    if (DP.isMatch())
3993
0
      return MCTargetAsmParser::Match_Success;
3994
0
    if (DP.isNearMatch())
3995
0
      return MipsAsmParser::Match_SImm10_Lsl3;
3996
0
    break;
3997
0
    }
3998
0
  // 'SImm16' class
3999
3.67k
  case MCK_SImm16: {
4000
3.67k
    DiagnosticPredicate DP(Operand.isSImm<16>());
4001
3.67k
    if (DP.isMatch())
4002
1.98k
      return MCTargetAsmParser::Match_Success;
4003
1.68k
    if (DP.isNearMatch())
4004
1.68k
      return MipsAsmParser::Match_SImm16;
4005
0
    break;
4006
0
    }
4007
0
  // 'SImm16_Relaxed' class
4008
1.13k
  case MCK_SImm16_Relaxed: {
4009
1.13k
    DiagnosticPredicate DP(Operand.isAnyImm<16>());
4010
1.13k
    if (DP.isMatch())
4011
514
      return MCTargetAsmParser::Match_Success;
4012
617
    if (DP.isNearMatch())
4013
617
      return MipsAsmParser::Match_SImm16_Relaxed;
4014
0
    break;
4015
0
    }
4016
0
  // 'UImm16_AltRelaxed' class
4017
11
  case MCK_UImm16_AltRelaxed: {
4018
11
    DiagnosticPredicate DP(Operand.isUImm<16>());
4019
11
    if (DP.isMatch())
4020
6
      return MCTargetAsmParser::Match_Success;
4021
5
    if (DP.isNearMatch())
4022
5
      return MipsAsmParser::Match_UImm16_AltRelaxed;
4023
0
    break;
4024
0
    }
4025
0
  // 'UImm16' class
4026
911
  case MCK_UImm16: {
4027
911
    DiagnosticPredicate DP(Operand.isUImm<16>());
4028
911
    if (DP.isMatch())
4029
355
      return MCTargetAsmParser::Match_Success;
4030
556
    if (DP.isNearMatch())
4031
556
      return MipsAsmParser::Match_UImm16;
4032
0
    break;
4033
0
    }
4034
0
  // 'SImm19Lsl2' class
4035
0
  case MCK_SImm19Lsl2: {
4036
0
    DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>());
4037
0
    if (DP.isMatch())
4038
0
      return MCTargetAsmParser::Match_Success;
4039
0
    if (DP.isNearMatch())
4040
0
      return MipsAsmParser::Match_SImm19_Lsl2;
4041
0
    break;
4042
0
    }
4043
0
  // 'UImm16_Relaxed' class
4044
223
  case MCK_UImm16_Relaxed: {
4045
223
    DiagnosticPredicate DP(Operand.isAnyImm<16>());
4046
223
    if (DP.isMatch())
4047
223
      return MCTargetAsmParser::Match_Success;
4048
0
    if (DP.isNearMatch())
4049
0
      return MipsAsmParser::Match_UImm16_Relaxed;
4050
0
    break;
4051
0
    }
4052
0
  // 'ConstantUImm20_0' class
4053
47
  case MCK_ConstantUImm20_0: {
4054
47
    DiagnosticPredicate DP(Operand.isConstantUImm<20, 0>());
4055
47
    if (DP.isMatch())
4056
32
      return MCTargetAsmParser::Match_Success;
4057
15
    if (DP.isNearMatch())
4058
15
      return MipsAsmParser::Match_UImm20_0;
4059
0
    break;
4060
0
    }
4061
0
  // 'ConstantUImm26_0' class
4062
0
  case MCK_ConstantUImm26_0: {
4063
0
    DiagnosticPredicate DP(Operand.isConstantUImm<26, 0>());
4064
0
    if (DP.isMatch())
4065
0
      return MCTargetAsmParser::Match_Success;
4066
0
    if (DP.isNearMatch())
4067
0
      return MipsAsmParser::Match_UImm26_0;
4068
0
    break;
4069
0
    }
4070
0
  // 'SImm32' class
4071
198
  case MCK_SImm32: {
4072
198
    DiagnosticPredicate DP(Operand.isSImm<32>());
4073
198
    if (DP.isMatch())
4074
50
      return MCTargetAsmParser::Match_Success;
4075
148
    if (DP.isNearMatch())
4076
148
      return MipsAsmParser::Match_SImm32;
4077
0
    break;
4078
0
    }
4079
0
  // 'SImm32_Relaxed' class
4080
2.24k
  case MCK_SImm32_Relaxed: {
4081
2.24k
    DiagnosticPredicate DP(Operand.isAnyImm<33>());
4082
2.24k
    if (DP.isMatch())
4083
1.02k
      return MCTargetAsmParser::Match_Success;
4084
1.21k
    if (DP.isNearMatch())
4085
1.21k
      return MipsAsmParser::Match_SImm32_Relaxed;
4086
0
    break;
4087
0
    }
4088
0
  // 'UImm32_Coerced' class
4089
209
  case MCK_UImm32_Coerced: {
4090
209
    DiagnosticPredicate DP(Operand.isSImm<33>());
4091
209
    if (DP.isMatch())
4092
206
      return MCTargetAsmParser::Match_Success;
4093
3
    if (DP.isNearMatch())
4094
3
      return MipsAsmParser::Match_UImm32_Coerced;
4095
0
    break;
4096
0
    }
4097
33.1k
  } // end switch (Kind)
4098
33.1k
4099
33.1k
  if (Operand.isReg()) {
4100
251
    MatchClassKind OpKind;
4101
251
    switch (Operand.getReg()) {
4102
251
    
default: OpKind = InvalidMatchClass; break0
;
4103
251
    case Mips::ZERO: OpKind = MCK_GPR32ZERO; break;
4104
251
    
case Mips::AT: OpKind = MCK_GPR32NONZERO; break0
;
4105
251
    
case Mips::V0: OpKind = MCK_Reg11; break0
;
4106
251
    
case Mips::V1: OpKind = MCK_Reg11; break0
;
4107
251
    
case Mips::A0: OpKind = MCK_Reg8; break0
;
4108
251
    
case Mips::A1: OpKind = MCK_Reg8; break0
;
4109
251
    
case Mips::A2: OpKind = MCK_Reg8; break0
;
4110
251
    
case Mips::A3: OpKind = MCK_Reg8; break0
;
4111
251
    
case Mips::T0: OpKind = MCK_GPR32NONZERO; break0
;
4112
251
    
case Mips::T1: OpKind = MCK_GPR32NONZERO; break0
;
4113
251
    
case Mips::T2: OpKind = MCK_GPR32NONZERO; break0
;
4114
251
    
case Mips::T3: OpKind = MCK_GPR32NONZERO; break0
;
4115
251
    
case Mips::T4: OpKind = MCK_GPR32NONZERO; break0
;
4116
251
    
case Mips::T5: OpKind = MCK_GPR32NONZERO; break0
;
4117
251
    
case Mips::T6: OpKind = MCK_GPR32NONZERO; break0
;
4118
251
    
case Mips::T7: OpKind = MCK_GPR32NONZERO; break0
;
4119
251
    
case Mips::S0: OpKind = MCK_Reg9; break0
;
4120
251
    
case Mips::S1: OpKind = MCK_Reg11; break0
;
4121
251
    
case Mips::S2: OpKind = MCK_Reg10; break0
;
4122
251
    
case Mips::S3: OpKind = MCK_Reg10; break0
;
4123
251
    
case Mips::S4: OpKind = MCK_Reg10; break0
;
4124
251
    
case Mips::S5: OpKind = MCK_GPR32NONZERO; break0
;
4125
251
    
case Mips::S6: OpKind = MCK_GPR32NONZERO; break0
;
4126
251
    
case Mips::S7: OpKind = MCK_GPR32NONZERO; break0
;
4127
251
    
case Mips::T8: OpKind = MCK_GPR32NONZERO; break0
;
4128
251
    
case Mips::T9: OpKind = MCK_GPR32NONZERO; break0
;
4129
251
    
case Mips::K0: OpKind = MCK_GPR32NONZERO; break0
;
4130
251
    
case Mips::K1: OpKind = MCK_GPR32NONZERO; break0
;
4131
251
    
case Mips::GP: OpKind = MCK_GP32; break0
;
4132
251
    
case Mips::SP: OpKind = MCK_CPUSPReg; break0
;
4133
251
    
case Mips::FP: OpKind = MCK_GPR32NONZERO; break0
;
4134
251
    
case Mips::RA: OpKind = MCK_CPURAReg; break0
;
4135
251
    
case Mips::ZERO_64: OpKind = MCK_Reg15; break0
;
4136
251
    
case Mips::AT_64: OpKind = MCK_Reg20; break0
;
4137
251
    
case Mips::V0_64: OpKind = MCK_Reg26; break0
;
4138
251
    
case Mips::V1_64: OpKind = MCK_Reg26; break0
;
4139
251
    
case Mips::A0_64: OpKind = MCK_Reg23; break0
;
4140
251
    
case Mips::A1_64: OpKind = MCK_Reg23; break0
;
4141
251
    
case Mips::A2_64: OpKind = MCK_Reg23; break0
;
4142
251
    
case Mips::A3_64: OpKind = MCK_Reg23; break0
;
4143
251
    
case Mips::T0_64: OpKind = MCK_Reg20; break0
;
4144
251
    
case Mips::T1_64: OpKind = MCK_Reg20; break0
;
4145
251
    
case Mips::T2_64: OpKind = MCK_Reg20; break0
;
4146
251
    
case Mips::T3_64: OpKind = MCK_Reg20; break0
;
4147
251
    
case Mips::T4_64: OpKind = MCK_Reg20; break0
;
4148
251
    
case Mips::T5_64: OpKind = MCK_Reg20; break0
;
4149
251
    
case Mips::T6_64: OpKind = MCK_Reg20; break0
;
4150
251
    
case Mips::T7_64: OpKind = MCK_Reg20; break0
;
4151
251
    
case Mips::S0_64: OpKind = MCK_Reg24; break0
;
4152
251
    
case Mips::S1_64: OpKind = MCK_Reg26; break0
;
4153
251
    
case Mips::S2_64: OpKind = MCK_Reg25; break0
;
4154
251
    
case Mips::S3_64: OpKind = MCK_Reg25; break0
;
4155
251
    
case Mips::S4_64: OpKind = MCK_Reg25; break0
;
4156
251
    
case Mips::S5_64: OpKind = MCK_Reg20; break0
;
4157
251
    
case Mips::S6_64: OpKind = MCK_Reg20; break0
;
4158
251
    
case Mips::S7_64: OpKind = MCK_Reg20; break0
;
4159
251
    
case Mips::T8_64: OpKind = MCK_Reg20; break0
;
4160
251
    
case Mips::T9_64: OpKind = MCK_Reg20; break0
;
4161
251
    
case Mips::K0_64: OpKind = MCK_Reg20; break0
;
4162
251
    
case Mips::K1_64: OpKind = MCK_Reg20; break0
;
4163
251
    
case Mips::GP_64: OpKind = MCK_GP64; break0
;
4164
251
    
case Mips::SP_64: OpKind = MCK_SP64; break0
;
4165
251
    
case Mips::FP_64: OpKind = MCK_Reg20; break0
;
4166
251
    
case Mips::RA_64: OpKind = MCK_Reg29; break0
;
4167
251
    
case Mips::F0: OpKind = MCK_FGR32; break0
;
4168
251
    
case Mips::F1: OpKind = MCK_Reg31; break0
;
4169
251
    
case Mips::F2: OpKind = MCK_FGR32; break0
;
4170
251
    
case Mips::F3: OpKind = MCK_Reg31; break0
;
4171
251
    
case Mips::F4: OpKind = MCK_FGR32; break0
;
4172
251
    
case Mips::F5: OpKind = MCK_Reg31; break0
;
4173
251
    
case Mips::F6: OpKind = MCK_FGR32; break0
;
4174
251
    
case Mips::F7: OpKind = MCK_Reg31; break0
;
4175
251
    
case Mips::F8: OpKind = MCK_FGR32; break0
;
4176
251
    
case Mips::F9: OpKind = MCK_Reg31; break0
;
4177
251
    
case Mips::F10: OpKind = MCK_FGR32; break0
;
4178
251
    
case Mips::F11: OpKind = MCK_Reg31; break0
;
4179
251
    
case Mips::F12: OpKind = MCK_FGR32; break0
;
4180
251
    
case Mips::F13: OpKind = MCK_Reg31; break0
;
4181
251
    
case Mips::F14: OpKind = MCK_FGR32; break0
;
4182
251
    
case Mips::F15: OpKind = MCK_Reg31; break0
;
4183
251
    
case Mips::F16: OpKind = MCK_FGR32; break0
;
4184
251
    
case Mips::F17: OpKind = MCK_Reg31; break0
;
4185
251
    
case Mips::F18: OpKind = MCK_FGR32; break0
;
4186
251
    
case Mips::F19: OpKind = MCK_Reg31; break0
;
4187
251
    
case Mips::F20: OpKind = MCK_FGR32; break0
;
4188
251
    
case Mips::F21: OpKind = MCK_Reg31; break0
;
4189
251
    
case Mips::F22: OpKind = MCK_FGR32; break0
;
4190
251
    
case Mips::F23: OpKind = MCK_Reg31; break0
;
4191
251
    
case Mips::F24: OpKind = MCK_FGR32; break0
;
4192
251
    
case Mips::F25: OpKind = MCK_Reg31; break0
;
4193
251
    
case Mips::F26: OpKind = MCK_FGR32; break0
;
4194
251
    
case Mips::F27: OpKind = MCK_Reg31; break0
;
4195
251
    
case Mips::F28: OpKind = MCK_FGR32; break0
;
4196
251
    
case Mips::F29: OpKind = MCK_Reg31; break0
;
4197
251
    
case Mips::F30: OpKind = MCK_FGR32; break0
;
4198
251
    
case Mips::F31: OpKind = MCK_Reg31; break0
;
4199
251
    
case Mips::F_HI0: OpKind = MCK_FGRH32; break0
;
4200
251
    
case Mips::F_HI1: OpKind = MCK_Reg34; break0
;
4201
251
    
case Mips::F_HI2: OpKind = MCK_FGRH32; break0
;
4202
251
    
case Mips::F_HI3: OpKind = MCK_Reg34; break0
;
4203
251
    
case Mips::F_HI4: OpKind = MCK_FGRH32; break0
;
4204
251
    
case Mips::F_HI5: OpKind = MCK_Reg34; break0
;
4205
251
    
case Mips::F_HI6: OpKind = MCK_FGRH32; break0
;
4206
251
    
case Mips::F_HI7: OpKind = MCK_Reg34; break0
;
4207
251
    
case Mips::F_HI8: OpKind = MCK_FGRH32; break0
;
4208
251
    
case Mips::F_HI9: OpKind = MCK_Reg34; break0
;
4209
251
    
case Mips::F_HI10: OpKind = MCK_FGRH32; break0
;
4210
251
    
case Mips::F_HI11: OpKind = MCK_Reg34; break0
;
4211
251
    
case Mips::F_HI12: OpKind = MCK_FGRH32; break0
;
4212
251
    
case Mips::F_HI13: OpKind = MCK_Reg34; break0
;
4213
251
    
case Mips::F_HI14: OpKind = MCK_FGRH32; break0
;
4214
251
    
case Mips::F_HI15: OpKind = MCK_Reg34; break0
;
4215
251
    
case Mips::F_HI16: OpKind = MCK_FGRH32; break0
;
4216
251
    
case Mips::F_HI17: OpKind = MCK_Reg34; break0
;
4217
251
    
case Mips::F_HI18: OpKind = MCK_FGRH32; break0
;
4218
251
    
case Mips::F_HI19: OpKind = MCK_Reg34; break0
;
4219
251
    
case Mips::F_HI20: OpKind = MCK_FGRH32; break0
;
4220
251
    
case Mips::F_HI21: OpKind = MCK_Reg34; break0
;
4221
251
    
case Mips::F_HI22: OpKind = MCK_FGRH32; break0
;
4222
251
    
case Mips::F_HI23: OpKind = MCK_Reg34; break0
;
4223
251
    
case Mips::F_HI24: OpKind = MCK_FGRH32; break0
;
4224
251
    
case Mips::F_HI25: OpKind = MCK_Reg34; break0
;
4225
251
    
case Mips::F_HI26: OpKind = MCK_FGRH32; break0
;
4226
251
    
case Mips::F_HI27: OpKind = MCK_Reg34; break0
;
4227
251
    
case Mips::F_HI28: OpKind = MCK_FGRH32; break0
;
4228
251
    
case Mips::F_HI29: OpKind = MCK_Reg34; break0
;
4229
251
    
case Mips::F_HI30: OpKind = MCK_FGRH32; break0
;
4230
251
    
case Mips::F_HI31: OpKind = MCK_Reg34; break0
;
4231
251
    
case Mips::D0: OpKind = MCK_AFGR64; break0
;
4232
251
    
case Mips::D1: OpKind = MCK_Reg36; break0
;
4233
251
    
case Mips::D2: OpKind = MCK_AFGR64; break0
;
4234
251
    
case Mips::D3: OpKind = MCK_Reg36; break0
;
4235
251
    
case Mips::D4: OpKind = MCK_AFGR64; break0
;
4236
251
    
case Mips::D5: OpKind = MCK_Reg36; break0
;
4237
251
    
case Mips::D6: OpKind = MCK_AFGR64; break0
;
4238
251
    
case Mips::D7: OpKind = MCK_Reg36; break0
;
4239
251
    
case Mips::D8: OpKind = MCK_AFGR64; break0
;
4240
251
    
case Mips::D9: OpKind = MCK_Reg36; break0
;
4241
251
    
case Mips::D10: OpKind = MCK_AFGR64; break0
;
4242
251
    
case Mips::D11: OpKind = MCK_Reg36; break0
;
4243
251
    
case Mips::D12: OpKind = MCK_AFGR64; break0
;
4244
251
    
case Mips::D13: OpKind = MCK_Reg36; break0
;
4245
251
    
case Mips::D14: OpKind = MCK_AFGR64; break0
;
4246
251
    
case Mips::D15: OpKind = MCK_Reg36; break0
;
4247
251
    
case Mips::D0_64: OpKind = MCK_FGR64; break0
;
4248
251
    
case Mips::D1_64: OpKind = MCK_Reg39; break0
;
4249
251
    
case Mips::D2_64: OpKind = MCK_FGR64; break0
;
4250
251
    
case Mips::D3_64: OpKind = MCK_Reg39; break0
;
4251
251
    
case Mips::D4_64: OpKind = MCK_FGR64; break0
;
4252
251
    
case Mips::D5_64: OpKind = MCK_Reg39; break0
;
4253
251
    
case Mips::D6_64: OpKind = MCK_FGR64; break0
;
4254
251
    
case Mips::D7_64: OpKind = MCK_Reg39; break0
;
4255
251
    
case Mips::D8_64: OpKind = MCK_FGR64; break0
;
4256
251
    
case Mips::D9_64: OpKind = MCK_Reg39; break0
;
4257
251
    
case Mips::D10_64: OpKind = MCK_FGR64; break0
;
4258
251
    
case Mips::D11_64: OpKind = MCK_Reg39; break0
;
4259
251
    
case Mips::D12_64: OpKind = MCK_FGR64; break0
;
4260
251
    
case Mips::D13_64: OpKind = MCK_Reg39; break0
;
4261
251
    
case Mips::D14_64: OpKind = MCK_FGR64; break0
;
4262
251
    
case Mips::D15_64: OpKind = MCK_Reg39; break0
;
4263
251
    
case Mips::D16_64: OpKind = MCK_FGR64; break0
;
4264
251
    
case Mips::D17_64: OpKind = MCK_Reg39; break0
;
4265
251
    
case Mips::D18_64: OpKind = MCK_FGR64; break0
;
4266
251
    
case Mips::D19_64: OpKind = MCK_Reg39; break0
;
4267
251
    
case Mips::D20_64: OpKind = MCK_FGR64; break0
;
4268
251
    
case Mips::D21_64: OpKind = MCK_Reg39; break0
;
4269
251
    
case Mips::D22_64: OpKind = MCK_FGR64; break0
;
4270
251
    
case Mips::D23_64: OpKind = MCK_Reg39; break0
;
4271
251
    
case Mips::D24_64: OpKind = MCK_FGR64; break0
;
4272
251
    
case Mips::D25_64: OpKind = MCK_Reg39; break0
;
4273
251
    
case Mips::D26_64: OpKind = MCK_FGR64; break0
;
4274
251
    
case Mips::D27_64: OpKind = MCK_Reg39; break0
;
4275
251
    
case Mips::D28_64: OpKind = MCK_FGR64; break0
;
4276
251
    
case Mips::D29_64: OpKind = MCK_Reg39; break0
;
4277
251
    
case Mips::D30_64: OpKind = MCK_FGR64; break0
;
4278
251
    
case Mips::D31_64: OpKind = MCK_Reg39; break0
;
4279
251
    
case Mips::W0: OpKind = MCK_MSA128WEvens; break0
;
4280
251
    
case Mips::W1: OpKind = MCK_Reg42; break0
;
4281
251
    
case Mips::W2: OpKind = MCK_MSA128WEvens; break0
;
4282
251
    
case Mips::W3: OpKind = MCK_Reg42; break0
;
4283
251
    
case Mips::W4: OpKind = MCK_MSA128WEvens; break0
;
4284
251
    
case Mips::W5: OpKind = MCK_Reg42; break0
;
4285
251
    
case Mips::W6: OpKind = MCK_MSA128WEvens; break0
;
4286
251
    
case Mips::W7: OpKind = MCK_Reg42; break0
;
4287
251
    
case Mips::W8: OpKind = MCK_MSA128WEvens; break0
;
4288
251
    
case Mips::W9: OpKind = MCK_Reg42; break0
;
4289
251
    
case Mips::W10: OpKind = MCK_MSA128WEvens; break0
;
4290
251
    
case Mips::W11: OpKind = MCK_Reg42; break0
;
4291
251
    
case Mips::W12: OpKind = MCK_MSA128WEvens; break0
;
4292
251
    
case Mips::W13: OpKind = MCK_Reg42; break0
;
4293
251
    
case Mips::W14: OpKind = MCK_MSA128WEvens; break0
;
4294
251
    
case Mips::W15: OpKind = MCK_Reg42; break0
;
4295
251
    
case Mips::W16: OpKind = MCK_MSA128WEvens; break0
;
4296
251
    
case Mips::W17: OpKind = MCK_Reg42; break0
;
4297
251
    
case Mips::W18: OpKind = MCK_MSA128WEvens; break0
;
4298
251
    
case Mips::W19: OpKind = MCK_Reg42; break0
;
4299
251
    
case Mips::W20: OpKind = MCK_MSA128WEvens; break0
;
4300
251
    
case Mips::W21: OpKind = MCK_Reg42; break0
;
4301
251
    
case Mips::W22: OpKind = MCK_MSA128WEvens; break0
;
4302
251
    
case Mips::W23: OpKind = MCK_Reg42; break0
;
4303
251
    
case Mips::W24: OpKind = MCK_MSA128WEvens; break0
;
4304
251
    
case Mips::W25: OpKind = MCK_Reg42; break0
;
4305
251
    
case Mips::W26: OpKind = MCK_MSA128WEvens; break0
;
4306
251
    
case Mips::W27: OpKind = MCK_Reg42; break0
;
4307
251
    
case Mips::W28: OpKind = MCK_MSA128WEvens; break0
;
4308
251
    
case Mips::W29: OpKind = MCK_Reg42; break0
;
4309
251
    
case Mips::W30: OpKind = MCK_MSA128WEvens; break0
;
4310
251
    
case Mips::W31: OpKind = MCK_Reg42; break0
;
4311
251
    
case Mips::HI0: OpKind = MCK_HI32; break0
;
4312
251
    
case Mips::HI1: OpKind = MCK_HI32DSP; break0
;
4313
251
    
case Mips::HI2: OpKind = MCK_HI32DSP; break0
;
4314
251
    
case Mips::HI3: OpKind = MCK_HI32DSP; break0
;
4315
251
    
case Mips::LO0: OpKind = MCK_LO32; break0
;
4316
251
    
case Mips::LO1: OpKind = MCK_LO32DSP; break0
;
4317
251
    
case Mips::LO2: OpKind = MCK_LO32DSP; break0
;
4318
251
    
case Mips::LO3: OpKind = MCK_LO32DSP; break0
;
4319
251
    
case Mips::HI0_64: OpKind = MCK_HI64; break0
;
4320
251
    
case Mips::LO0_64: OpKind = MCK_LO64; break0
;
4321
251
    
case Mips::FCR0: OpKind = MCK_CCR; break0
;
4322
251
    
case Mips::FCR1: OpKind = MCK_CCR; break0
;
4323
251
    
case Mips::FCR2: OpKind = MCK_CCR; break0
;
4324
251
    
case Mips::FCR3: OpKind = MCK_CCR; break0
;
4325
251
    
case Mips::FCR4: OpKind = MCK_CCR; break0
;
4326
251
    
case Mips::FCR5: OpKind = MCK_CCR; break0
;
4327
251
    
case Mips::FCR6: OpKind = MCK_CCR; break0
;
4328
251
    
case Mips::FCR7: OpKind = MCK_CCR; break0
;
4329
251
    
case Mips::FCR8: OpKind = MCK_CCR; break0
;
4330
251
    
case Mips::FCR9: OpKind = MCK_CCR; break0
;
4331
251
    
case Mips::FCR10: OpKind = MCK_CCR; break0
;
4332
251
    
case Mips::FCR11: OpKind = MCK_CCR; break0
;
4333
251
    
case Mips::FCR12: OpKind = MCK_CCR; break0
;
4334
251
    
case Mips::FCR13: OpKind = MCK_CCR; break0
;
4335
251
    
case Mips::FCR14: OpKind = MCK_CCR; break0
;
4336
251
    
case Mips::FCR15: OpKind = MCK_CCR; break0
;
4337
251
    
case Mips::FCR16: OpKind = MCK_CCR; break0
;
4338
251
    
case Mips::FCR17: OpKind = MCK_CCR; break0
;
4339
251
    
case Mips::FCR18: OpKind = MCK_CCR; break0
;
4340
251
    
case Mips::FCR19: OpKind = MCK_CCR; break0
;
4341
251
    
case Mips::FCR20: OpKind = MCK_CCR; break0
;
4342
251
    
case Mips::FCR21: OpKind = MCK_CCR; break0
;
4343
251
    
case Mips::FCR22: OpKind = MCK_CCR; break0
;
4344
251
    
case Mips::FCR23: OpKind = MCK_CCR; break0
;
4345
251
    
case Mips::FCR24: OpKind = MCK_CCR; break0
;
4346
251
    
case Mips::FCR25: OpKind = MCK_CCR; break0
;
4347
251
    
case Mips::FCR26: OpKind = MCK_CCR; break0
;
4348
251
    
case Mips::FCR27: OpKind = MCK_CCR; break0
;
4349
251
    
case Mips::FCR28: OpKind = MCK_CCR; break0
;
4350
251
    
case Mips::FCR29: OpKind = MCK_CCR; break0
;
4351
251
    
case Mips::FCR30: OpKind = MCK_CCR; break0
;
4352
251
    
case Mips::FCR31: OpKind = MCK_CCR; break0
;
4353
251
    
case Mips::FCC0: OpKind = MCK_FCC; break0
;
4354
251
    
case Mips::FCC1: OpKind = MCK_FCC; break0
;
4355
251
    
case Mips::FCC2: OpKind = MCK_FCC; break0
;
4356
251
    
case Mips::FCC3: OpKind = MCK_FCC; break0
;
4357
251
    
case Mips::FCC4: OpKind = MCK_FCC; break0
;
4358
251
    
case Mips::FCC5: OpKind = MCK_FCC; break0
;
4359
251
    
case Mips::FCC6: OpKind = MCK_FCC; break0
;
4360
251
    
case Mips::FCC7: OpKind = MCK_FCC; break0
;
4361
251
    
case Mips::COP00: OpKind = MCK_COP0; break0
;
4362
251
    
case Mips::COP01: OpKind = MCK_COP0; break0
;
4363
251
    
case Mips::COP02: OpKind = MCK_COP0; break0
;
4364
251
    
case Mips::COP03: OpKind = MCK_COP0; break0
;
4365
251
    
case Mips::COP04: OpKind = MCK_COP0; break0
;
4366
251
    
case Mips::COP05: OpKind = MCK_COP0; break0
;
4367
251
    
case Mips::COP06: OpKind = MCK_COP0; break0
;
4368
251
    
case Mips::COP07: OpKind = MCK_COP0; break0
;
4369
251
    
case Mips::COP08: OpKind = MCK_COP0; break0
;
4370
251
    
case Mips::COP09: OpKind = MCK_COP0; break0
;
4371
251
    
case Mips::COP010: OpKind = MCK_COP0; break0
;
4372
251
    
case Mips::COP011: OpKind = MCK_COP0; break0
;
4373
251
    
case Mips::COP012: OpKind = MCK_COP0; break0
;
4374
251
    
case Mips::COP013: OpKind = MCK_COP0; break0
;
4375
251
    
case Mips::COP014: OpKind = MCK_COP0; break0
;
4376
251
    
case Mips::COP015: OpKind = MCK_COP0; break0
;
4377
251
    
case Mips::COP016: OpKind = MCK_COP0; break0
;
4378
251
    
case Mips::COP017: OpKind = MCK_COP0; break0
;
4379
251
    
case Mips::COP018: OpKind = MCK_COP0; break0
;
4380
251
    
case Mips::COP019: OpKind = MCK_COP0; break0
;
4381
251
    
case Mips::COP020: OpKind = MCK_COP0; break0
;
4382
251
    
case Mips::COP021: OpKind = MCK_COP0; break0
;
4383
251
    
case Mips::COP022: OpKind = MCK_COP0; break0
;
4384
251
    
case Mips::COP023: OpKind = MCK_COP0; break0
;
4385
251
    
case Mips::COP024: OpKind = MCK_COP0; break0
;
4386
251
    
case Mips::COP025: OpKind = MCK_COP0; break0
;
4387
251
    
case Mips::COP026: OpKind = MCK_COP0; break0
;
4388
251
    
case Mips::COP027: OpKind = MCK_COP0; break0
;
4389
251
    
case Mips::COP028: OpKind = MCK_COP0; break0
;
4390
251
    
case Mips::COP029: OpKind = MCK_COP0; break0
;
4391
251
    
case Mips::COP030: OpKind = MCK_COP0; break0
;
4392
251
    
case Mips::COP031: OpKind = MCK_COP0; break0
;
4393
251
    
case Mips::COP20: OpKind = MCK_COP2; break0
;
4394
251
    
case Mips::COP21: OpKind = MCK_COP2; break0
;
4395
251
    
case Mips::COP22: OpKind = MCK_COP2; break0
;
4396
251
    
case Mips::COP23: OpKind = MCK_COP2; break0
;
4397
251
    
case Mips::COP24: OpKind = MCK_COP2; break0
;
4398
251
    
case Mips::COP25: OpKind = MCK_COP2; break0
;
4399
251
    
case Mips::COP26: OpKind = MCK_COP2; break0
;
4400
251
    
case Mips::COP27: OpKind = MCK_COP2; break0
;
4401
251
    
case Mips::COP28: OpKind = MCK_COP2; break0
;
4402
251
    
case Mips::COP29: OpKind = MCK_COP2; break0
;
4403
251
    
case Mips::COP210: OpKind = MCK_COP2; break0
;
4404
251
    
case Mips::COP211: OpKind = MCK_COP2; break0
;
4405
251
    
case Mips::COP212: OpKind = MCK_COP2; break0
;
4406
251
    
case Mips::COP213: OpKind = MCK_COP2; break0
;
4407
251
    
case Mips::COP214: OpKind = MCK_COP2; break0
;
4408
251
    
case Mips::COP215: OpKind = MCK_COP2; break0
;
4409
251
    
case Mips::COP216: OpKind = MCK_COP2; break0
;
4410
251
    
case Mips::COP217: OpKind = MCK_COP2; break0
;
4411
251
    
case Mips::COP218: OpKind = MCK_COP2; break0
;
4412
251
    
case Mips::COP219: OpKind = MCK_COP2; break0
;
4413
251
    
case Mips::COP220: OpKind = MCK_COP2; break0
;
4414
251
    
case Mips::COP221: OpKind = MCK_COP2; break0
;
4415
251
    
case Mips::COP222: OpKind = MCK_COP2; break0
;
4416
251
    
case Mips::COP223: OpKind = MCK_COP2; break0
;
4417
251
    
case Mips::COP224: OpKind = MCK_COP2; break0
;
4418
251
    
case Mips::COP225: OpKind = MCK_COP2; break0
;
4419
251
    
case Mips::COP226: OpKind = MCK_COP2; break0
;
4420
251
    
case Mips::COP227: OpKind = MCK_COP2; break0
;
4421
251
    
case Mips::COP228: OpKind = MCK_COP2; break0
;
4422
251
    
case Mips::COP229: OpKind = MCK_COP2; break0
;
4423
251
    
case Mips::COP230: OpKind = MCK_COP2; break0
;
4424
251
    
case Mips::COP231: OpKind = MCK_COP2; break0
;
4425
251
    
case Mips::COP30: OpKind = MCK_COP3; break0
;
4426
251
    
case Mips::COP31: OpKind = MCK_COP3; break0
;
4427
251
    
case Mips::COP32: OpKind = MCK_COP3; break0
;
4428
251
    
case Mips::COP33: OpKind = MCK_COP3; break0
;
4429
251
    
case Mips::COP34: OpKind = MCK_COP3; break0
;
4430
251
    
case Mips::COP35: OpKind = MCK_COP3; break0
;
4431
251
    
case Mips::COP36: OpKind = MCK_COP3; break0
;
4432
251
    
case Mips::COP37: OpKind = MCK_COP3; break0
;
4433
251
    
case Mips::COP38: OpKind = MCK_COP3; break0
;
4434
251
    
case Mips::COP39: OpKind = MCK_COP3; break0
;
4435
251
    
case Mips::COP310: OpKind = MCK_COP3; break0
;
4436
251
    
case Mips::COP311: OpKind = MCK_COP3; break0
;
4437
251
    
case Mips::COP312: OpKind = MCK_COP3; break0
;
4438
251
    
case Mips::COP313: OpKind = MCK_COP3; break0
;
4439
251
    
case Mips::COP314: OpKind = MCK_COP3; break0
;
4440
251
    
case Mips::COP315: OpKind = MCK_COP3; break0
;
4441
251
    
case Mips::COP316: OpKind = MCK_COP3; break0
;
4442
251
    
case Mips::COP317: OpKind = MCK_COP3; break0
;
4443
251
    
case Mips::COP318: OpKind = MCK_COP3; break0
;
4444
251
    
case Mips::COP319: OpKind = MCK_COP3; break0
;
4445
251
    
case Mips::COP320: OpKind = MCK_COP3; break0
;
4446
251
    
case Mips::COP321: OpKind = MCK_COP3; break0
;
4447
251
    
case Mips::COP322: OpKind = MCK_COP3; break0
;
4448
251
    
case Mips::COP323: OpKind = MCK_COP3; break0
;
4449
251
    
case Mips::COP324: OpKind = MCK_COP3; break0
;
4450
251
    
case Mips::COP325: OpKind = MCK_COP3; break0
;
4451
251
    
case Mips::COP326: OpKind = MCK_COP3; break0
;
4452
251
    
case Mips::COP327: OpKind = MCK_COP3; break0
;
4453
251
    
case Mips::COP328: OpKind = MCK_COP3; break0
;
4454
251
    
case Mips::COP329: OpKind = MCK_COP3; break0
;
4455
251
    
case Mips::COP330: OpKind = MCK_COP3; break0
;
4456
251
    
case Mips::COP331: OpKind = MCK_COP3; break0
;
4457
251
    
case Mips::PC: OpKind = MCK_PC; break0
;
4458
251
    
case Mips::HWR0: OpKind = MCK_HWRegs; break0
;
4459
251
    
case Mips::HWR1: OpKind = MCK_HWRegs; break0
;
4460
251
    
case Mips::HWR2: OpKind = MCK_HWRegs; break0
;
4461
251
    
case Mips::HWR3: OpKind = MCK_HWRegs; break0
;
4462
251
    
case Mips::HWR4: OpKind = MCK_HWRegs; break0
;
4463
251
    
case Mips::HWR5: OpKind = MCK_HWRegs; break0
;
4464
251
    
case Mips::HWR6: OpKind = MCK_HWRegs; break0
;
4465
251
    
case Mips::HWR7: OpKind = MCK_HWRegs; break0
;
4466
251
    
case Mips::HWR8: OpKind = MCK_HWRegs; break0
;
4467
251
    
case Mips::HWR9: OpKind = MCK_HWRegs; break0
;
4468
251
    
case Mips::HWR10: OpKind = MCK_HWRegs; break0
;
4469
251
    
case Mips::HWR11: OpKind = MCK_HWRegs; break0
;
4470
251
    
case Mips::HWR12: OpKind = MCK_HWRegs; break0
;
4471
251
    
case Mips::HWR13: OpKind = MCK_HWRegs; break0
;
4472
251
    
case Mips::HWR14: OpKind = MCK_HWRegs; break0
;
4473
251
    
case Mips::HWR15: OpKind = MCK_HWRegs; break0
;
4474
251
    
case Mips::HWR16: OpKind = MCK_HWRegs; break0
;
4475
251
    
case Mips::HWR17: OpKind = MCK_HWRegs; break0
;
4476
251
    
case Mips::HWR18: OpKind = MCK_HWRegs; break0
;
4477
251
    
case Mips::HWR19: OpKind = MCK_HWRegs; break0
;
4478
251
    
case Mips::HWR20: OpKind = MCK_HWRegs; break0
;
4479
251
    
case Mips::HWR21: OpKind = MCK_HWRegs; break0
;
4480
251
    
case Mips::HWR22: OpKind = MCK_HWRegs; break0
;
4481
251
    
case Mips::HWR23: OpKind = MCK_HWRegs; break0
;
4482
251
    
case Mips::HWR24: OpKind = MCK_HWRegs; break0
;
4483
251
    
case Mips::HWR25: OpKind = MCK_HWRegs; break0
;
4484
251
    
case Mips::HWR26: OpKind = MCK_HWRegs; break0
;
4485
251
    
case Mips::HWR27: OpKind = MCK_HWRegs; break0
;
4486
251
    
case Mips::HWR28: OpKind = MCK_HWRegs; break0
;
4487
251
    
case Mips::HWR29: OpKind = MCK_HWRegs; break0
;
4488
251
    
case Mips::HWR30: OpKind = MCK_HWRegs; break0
;
4489
251
    
case Mips::HWR31: OpKind = MCK_HWRegs; break0
;
4490
251
    
case Mips::AC0: OpKind = MCK_ACC64; break0
;