Coverage Report

Created: 2019-03-24 22:13

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Mips/MipsGenAsmMatcher.inc
Line
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Source (jump to first uncovered line)
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Assembly Matcher Source Fragment                                           *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_ASSEMBLER_HEADER
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#undef GET_ASSEMBLER_HEADER
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  // This should be included into the middle of the declaration of
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  // your subclasses implementation of MCTargetAsmParser.
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  FeatureBitset ComputeAvailableFeatures(const FeatureBitset& FB) const;
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  void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
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                       const OperandVector &Operands);
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  void convertToMapAndConstraints(unsigned Kind,
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                           const OperandVector &Operands) override;
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  unsigned MatchInstructionImpl(const OperandVector &Operands,
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                                MCInst &Inst,
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                                uint64_t &ErrorInfo,
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                                FeatureBitset &MissingFeatures,
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                                bool matchingInlineAsm,
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                                unsigned VariantID = 0);
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  unsigned MatchInstructionImpl(const OperandVector &Operands,
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                                MCInst &Inst,
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                                uint64_t &ErrorInfo,
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                                bool matchingInlineAsm,
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40.8k
                                unsigned VariantID = 0) {
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40.8k
    FeatureBitset MissingFeatures;
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40.8k
    return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
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40.8k
                                matchingInlineAsm, VariantID);
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40.8k
  }
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  OperandMatchResultTy MatchOperandParserImpl(
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    OperandVector &Operands,
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    StringRef Mnemonic,
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    bool ParseForAllFeatures = false);
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  OperandMatchResultTy tryCustomParseOperand(
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    OperandVector &Operands,
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    unsigned MCK);
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#endif // GET_ASSEMBLER_HEADER_INFO
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#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
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#undef GET_OPERAND_DIAGNOSTIC_TYPES
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49
  Match_Immz,
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  Match_MemSImm10,
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  Match_MemSImm10Lsl1,
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  Match_MemSImm10Lsl2,
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  Match_MemSImm10Lsl3,
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  Match_MemSImm11,
55
  Match_MemSImm12,
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  Match_MemSImm16,
57
  Match_MemSImm9,
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  Match_MemSImmPtr,
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  Match_SImm10_0,
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  Match_SImm10_Lsl1,
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  Match_SImm10_Lsl2,
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  Match_SImm10_Lsl3,
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  Match_SImm11_0,
64
  Match_SImm16,
65
  Match_SImm16_Relaxed,
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  Match_SImm19_Lsl2,
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  Match_SImm32,
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  Match_SImm32_Relaxed,
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  Match_SImm4_0,
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  Match_SImm5_0,
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  Match_SImm6_0,
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  Match_SImm7_Lsl2,
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  Match_SImm9_0,
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  Match_UImm10_0,
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  Match_UImm16,
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  Match_UImm16_AltRelaxed,
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  Match_UImm16_Relaxed,
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  Match_UImm1_0,
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  Match_UImm20_0,
80
  Match_UImm26_0,
81
  Match_UImm2_0,
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  Match_UImm2_1,
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  Match_UImm32_Coerced,
84
  Match_UImm3_0,
85
  Match_UImm4_0,
86
  Match_UImm5_0,
87
  Match_UImm5_0_Report_UImm6,
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  Match_UImm5_1,
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  Match_UImm5_32,
90
  Match_UImm5_33,
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  Match_UImm5_Lsl2,
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  Match_UImm6_0,
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  Match_UImm6_Lsl2,
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  Match_UImm7_0,
95
  Match_UImm7_N1,
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  Match_UImm8_0,
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  Match_UImmRange2_64,
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  END_OPERAND_DIAGNOSTIC_TYPES
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#endif // GET_OPERAND_DIAGNOSTIC_TYPES
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#ifdef GET_REGISTER_MATCHER
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#undef GET_REGISTER_MATCHER
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// Bits for subtarget features that participate in instruction matching.
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enum SubtargetFeatureBits : uint8_t {
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  Feature_HasMips2Bit = 10,
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  Feature_HasMips3_32Bit = 16,
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  Feature_HasMips3_32r2Bit = 17,
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  Feature_HasMips3Bit = 11,
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  Feature_NotMips3Bit = 44,
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  Feature_HasMips4_32Bit = 18,
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  Feature_NotMips4_32Bit = 46,
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  Feature_HasMips4_32r2Bit = 19,
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  Feature_HasMips5_32r2Bit = 20,
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  Feature_HasMips32Bit = 12,
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  Feature_HasMips32r2Bit = 13,
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  Feature_HasMips32r5Bit = 14,
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  Feature_HasMips32r6Bit = 15,
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  Feature_NotMips32r6Bit = 45,
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  Feature_IsGP64bitBit = 31,
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  Feature_IsGP32bitBit = 30,
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  Feature_IsPTR64bitBit = 35,
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  Feature_IsPTR32bitBit = 34,
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  Feature_HasMips64Bit = 21,
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  Feature_NotMips64Bit = 47,
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  Feature_HasMips64r2Bit = 22,
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  Feature_HasMips64r5Bit = 23,
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  Feature_HasMips64r6Bit = 24,
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  Feature_NotMips64r6Bit = 48,
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  Feature_InMips16ModeBit = 28,
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  Feature_NotInMips16ModeBit = 43,
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  Feature_HasCnMipsBit = 1,
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  Feature_NotCnMipsBit = 40,
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  Feature_IsSym32Bit = 37,
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  Feature_IsSym64Bit = 38,
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  Feature_HasStdEncBit = 25,
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  Feature_InMicroMipsBit = 27,
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  Feature_NotInMicroMipsBit = 42,
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  Feature_HasEVABit = 5,
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  Feature_HasMSABit = 7,
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  Feature_HasMadd4Bit = 9,
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  Feature_HasMTBit = 8,
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  Feature_UseIndirectJumpsHazardBit = 49,
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  Feature_NoIndirectJumpGuardsBit = 39,
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  Feature_HasCRCBit = 0,
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  Feature_HasVirtBit = 26,
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  Feature_HasGINVBit = 6,
149
  Feature_IsFP64bitBit = 29,
150
  Feature_NotFP64bitBit = 41,
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  Feature_IsSingleFloatBit = 36,
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  Feature_IsNotSingleFloatBit = 32,
153
  Feature_IsNotSoftFloatBit = 33,
154
  Feature_HasDSPBit = 2,
155
  Feature_HasDSPR2Bit = 3,
156
  Feature_HasDSPR3Bit = 4,
157
};
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159
#endif // GET_REGISTER_MATCHER
160
161
162
#ifdef GET_SUBTARGET_FEATURE_NAME
163
#undef GET_SUBTARGET_FEATURE_NAME
164
165
// User-level names for subtarget features that participate in
166
// instruction matching.
167
static const char *getSubtargetFeatureName(uint64_t Val) {
168
  switch(Val) {
169
  case Feature_HasMips2Bit: return "";
170
  case Feature_HasMips3_32Bit: return "";
171
  case Feature_HasMips3_32r2Bit: return "";
172
  case Feature_HasMips3Bit: return "";
173
  case Feature_NotMips3Bit: return "";
174
  case Feature_HasMips4_32Bit: return "";
175
  case Feature_NotMips4_32Bit: return "";
176
  case Feature_HasMips4_32r2Bit: return "";
177
  case Feature_HasMips5_32r2Bit: return "";
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  case Feature_HasMips32Bit: return "";
179
  case Feature_HasMips32r2Bit: return "";
180
  case Feature_HasMips32r5Bit: return "";
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  case Feature_HasMips32r6Bit: return "";
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  case Feature_NotMips32r6Bit: return "";
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  case Feature_IsGP64bitBit: return "";
184
  case Feature_IsGP32bitBit: return "";
185
  case Feature_IsPTR64bitBit: return "";
186
  case Feature_IsPTR32bitBit: return "";
187
  case Feature_HasMips64Bit: return "";
188
  case Feature_NotMips64Bit: return "";
189
  case Feature_HasMips64r2Bit: return "";
190
  case Feature_HasMips64r5Bit: return "";
191
  case Feature_HasMips64r6Bit: return "";
192
  case Feature_NotMips64r6Bit: return "";
193
  case Feature_InMips16ModeBit: return "";
194
  case Feature_NotInMips16ModeBit: return "";
195
  case Feature_HasCnMipsBit: return "";
196
  case Feature_NotCnMipsBit: return "";
197
  case Feature_IsSym32Bit: return "";
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  case Feature_IsSym64Bit: return "";
199
  case Feature_HasStdEncBit: return "";
200
  case Feature_InMicroMipsBit: return "";
201
  case Feature_NotInMicroMipsBit: return "";
202
  case Feature_HasEVABit: return "";
203
  case Feature_HasMSABit: return "";
204
  case Feature_HasMadd4Bit: return "";
205
  case Feature_HasMTBit: return "";
206
  case Feature_UseIndirectJumpsHazardBit: return "";
207
  case Feature_NoIndirectJumpGuardsBit: return "";
208
  case Feature_HasCRCBit: return "";
209
  case Feature_HasVirtBit: return "";
210
  case Feature_HasGINVBit: return "";
211
  case Feature_IsFP64bitBit: return "";
212
  case Feature_NotFP64bitBit: return "";
213
  case Feature_IsSingleFloatBit: return "";
214
  case Feature_IsNotSingleFloatBit: return "";
215
  case Feature_IsNotSoftFloatBit: return "";
216
  case Feature_HasDSPBit: return "";
217
  case Feature_HasDSPR2Bit: return "";
218
  case Feature_HasDSPR3Bit: return "";
219
  default: return "(unknown)";
220
  }
221
}
222
223
#endif // GET_SUBTARGET_FEATURE_NAME
224
225
226
#ifdef GET_MATCHER_IMPLEMENTATION
227
#undef GET_MATCHER_IMPLEMENTATION
228
229
enum {
230
  Tie0_1_1,
231
  Tie0_1_2,
232
};
233
234
static const uint8_t TiedAsmOperandTable[][3] = {
235
  /* Tie0_1_1 */ { 0, 1, 1 },
236
  /* Tie0_1_2 */ { 0, 1, 2 },
237
};
238
239
namespace {
240
enum OperatorConversionKind {
241
  CVT_Done,
242
  CVT_Reg,
243
  CVT_Tied,
244
  CVT_95_addGPR32AsmRegOperands,
245
  CVT_95_addAFGR64AsmRegOperands,
246
  CVT_95_addFGR64AsmRegOperands,
247
  CVT_95_addFGR32AsmRegOperands,
248
  CVT_95_addSImmOperands_LT_32_GT_,
249
  CVT_95_addMSA128AsmRegOperands,
250
  CVT_95_addSImmOperands_LT_16_GT_,
251
  CVT_95_Reg,
252
  CVT_95_addImmOperands,
253
  CVT_95_addGPRMM16AsmRegOperands,
254
  CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_,
255
  CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_,
256
  CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_,
257
  CVT_95_addUImmOperands_LT_16_GT_,
258
  CVT_95_addGPR64AsmRegOperands,
259
  CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_,
260
  CVT_regZERO,
261
  CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_,
262
  CVT_regFCC0,
263
  CVT_95_addFCCAsmRegOperands,
264
  CVT_95_addCOP2AsmRegOperands,
265
  CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_,
266
  CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_,
267
  CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_,
268
  CVT_imm_95_0,
269
  CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_,
270
  CVT_95_addMemOperands,
271
  CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_,
272
  CVT_95_addCCRAsmRegOperands,
273
  CVT_95_addMSACtrlAsmRegOperands,
274
  CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_,
275
  CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_,
276
  CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_,
277
  CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_,
278
  CVT_95_addGPR32NonZeroAsmRegOperands,
279
  CVT_95_addGPR32ZeroAsmRegOperands,
280
  CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_,
281
  CVT_95_addCOP0AsmRegOperands,
282
  CVT_regZERO_64,
283
  CVT_95_addACC64DSPAsmRegOperands,
284
  CVT_95_addConstantUImmOperands_LT_1_GT_,
285
  CVT_regRA,
286
  CVT_regRA_64,
287
  CVT_95_addMicroMipsMemOperands,
288
  CVT_95_addCOP3AsmRegOperands,
289
  CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_,
290
  CVT_95_addConstantUImmOperands_LT_32_GT_,
291
  CVT_95_addStrictlyAFGR64AsmRegOperands,
292
  CVT_95_addStrictlyFGR64AsmRegOperands,
293
  CVT_95_addStrictlyFGR32AsmRegOperands,
294
  CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_,
295
  CVT_95_addRegListOperands,
296
  CVT_ConvertXWPOperands,
297
  CVT_regAC0,
298
  CVT_95_addGPRMM16AsmRegMovePPairFirstOperands,
299
  CVT_95_addGPRMM16AsmRegMovePPairSecondOperands,
300
  CVT_95_addGPRMM16AsmRegMovePOperands,
301
  CVT_95_addHI32DSPAsmRegOperands,
302
  CVT_95_addLO32DSPAsmRegOperands,
303
  CVT_regS0,
304
  CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_,
305
  CVT_95_addHWRegsAsmRegOperands,
306
  CVT_95_addGPRMM16AsmRegZeroOperands,
307
  CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_,
308
  CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_,
309
  CVT_imm_95_2,
310
  CVT_imm_95_6,
311
  CVT_imm_95_4,
312
  CVT_imm_95_5,
313
  CVT_imm_95_31,
314
  CVT_NUM_CONVERTERS
315
};
316
317
enum InstructionConversionKind {
318
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1,
319
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1,
320
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1,
321
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1,
322
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1,
323
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1,
324
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
325
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2,
326
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2,
327
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
328
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
329
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1,
330
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2,
331
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1,
332
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1,
333
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2,
334
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2,
335
  Convert__SImm161_1,
336
  Convert__Reg1_0__SImm161_1,
337
  Convert__Reg1_0__SImm161_2,
338
  Convert__Reg1_0__Reg1_1__SImm161_2,
339
  Convert__Reg1_0__Tie0_1_1__SImm161_1,
340
  Convert__GPR32AsmReg1_0__Simm19_Lsl21_1,
341
  Convert__GPRMM16AsmReg1_0__Imm1_1,
342
  Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1,
343
  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2,
344
  Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1,
345
  Convert__Imm1_0,
346
  Convert__Reg1_0__Reg1_1__Reg1_2,
347
  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2,
348
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2,
349
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3,
350
  Convert__GPR32AsmReg1_0__SImm161_1,
351
  Convert__Reg1_0__Tie0_1_1__Reg1_1,
352
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1,
353
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1,
354
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2,
355
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2,
356
  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1,
357
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2,
358
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1,
359
  Convert__regZERO__regZERO__JumpTarget1_0,
360
  Convert__JumpTarget1_0,
361
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1,
362
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2,
363
  Convert__regZERO__JumpTarget1_0,
364
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1,
365
  Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2,
366
  Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2,
367
  Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2,
368
  Convert__FGR64AsmReg1_0__JumpTarget1_1,
369
  Convert__regFCC0__JumpTarget1_0,
370
  Convert__FCCAsmReg1_0__JumpTarget1_1,
371
  Convert__COP2AsmReg1_0__JumpTarget1_1,
372
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2,
373
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2,
374
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2,
375
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2,
376
  Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2,
377
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2,
378
  Convert__Reg1_0__JumpTarget1_1,
379
  Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1,
380
  Convert__GPRMM16AsmReg1_0__JumpTarget1_1,
381
  Convert__GPR32AsmReg1_0__JumpTarget1_1,
382
  Convert__GPR64AsmReg1_0__JumpTarget1_1,
383
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2,
384
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2,
385
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2,
386
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2,
387
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2,
388
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2,
389
  Convert__MSA128AsmReg1_0__JumpTarget1_1,
390
  Convert__imm_95_0__imm_95_0,
391
  Convert_NoOperands,
392
  Convert__ConstantUImm10_01_0__imm_95_0,
393
  Convert__ConstantUImm10_01_0__ConstantUImm10_01_1,
394
  Convert__ConstantUImm4_01_0,
395
  Convert__SImm161_0,
396
  Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1,
397
  Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1,
398
  Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2,
399
  Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
400
  Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1,
401
  Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
402
  Convert__MemOffsetSimm92_1__ConstantUImm5_01_0,
403
  Convert__Mem2_1__ConstantUImm5_01_0,
404
  Convert__FGR64AsmReg1_0__FGR32AsmReg1_1,
405
  Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1,
406
  Convert__FGR32AsmReg1_0__FGR64AsmReg1_1,
407
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2,
408
  Convert__GPR32AsmReg1_0__CCRAsmReg1_1,
409
  Convert__GPR32AsmReg1_0__COP2AsmReg1_1,
410
  Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1,
411
  Convert__GPR32AsmReg1_0__FGR32AsmReg1_1,
412
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2,
413
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2,
414
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3,
415
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3,
416
  Convert__Reg1_0__Reg1_1,
417
  Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
418
  Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3,
419
  Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3,
420
  Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3,
421
  Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3,
422
  Convert__CCRAsmReg1_1__GPR32AsmReg1_0,
423
  Convert__COP2AsmReg1_1__GPR32AsmReg1_0,
424
  Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1,
425
  Convert__FGR32AsmReg1_1__GPR32AsmReg1_0,
426
  Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1,
427
  Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
428
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1,
429
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2,
430
  Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2,
431
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3,
432
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2,
433
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1,
434
  Convert__GPR64AsmReg1_1__GPR64AsmReg1_2,
435
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3,
436
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3,
437
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3,
438
  Convert__regZERO,
439
  Convert__GPR32AsmReg1_0,
440
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1,
441
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1,
442
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1,
443
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1,
444
  Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1,
445
  Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1,
446
  Convert__Reg1_1__Reg1_2,
447
  Convert__GPR32AsmReg1_1__GPR32AsmReg1_2,
448
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2,
449
  Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
450
  Convert__GPR64AsmReg1_0__Imm1_1,
451
  Convert__GPR64AsmReg1_0__Mem2_1,
452
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3,
453
  Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0,
454
  Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2,
455
  Convert__GPR64AsmReg1_0__FGR64AsmReg1_1,
456
  Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0,
457
  Convert__GPR64AsmReg1_0__UImm161_1,
458
  Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2,
459
  Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0,
460
  Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2,
461
  Convert__FGR64AsmReg1_1__GPR64AsmReg1_0,
462
  Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0,
463
  Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2,
464
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2,
465
  Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0,
466
  Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1,
467
  Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
468
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0,
469
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1,
470
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1,
471
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2,
472
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1,
473
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2,
474
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2,
475
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1,
476
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1,
477
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2,
478
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3,
479
  Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2,
480
  Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2,
481
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1,
482
  Convert__MSA128AsmReg1_0__GPR32AsmReg1_1,
483
  Convert__MSA128AsmReg1_0__GPR64AsmReg1_1,
484
  Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2,
485
  Convert__GPR32AsmReg1_0__ConstantUImm2_01_1,
486
  Convert__imm_95_0,
487
  Convert__ConstantUImm10_01_0,
488
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1,
489
  Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2,
490
  Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2,
491
  Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2,
492
  Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2,
493
  Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1,
494
  Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
495
  Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
496
  Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
497
  Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
498
  Convert__regRA__GPR32AsmReg1_0,
499
  Convert__regRA_64__GPR64AsmReg1_0,
500
  Convert__Reg1_0,
501
  Convert__GPR32AsmReg1_0__imm_95_0,
502
  Convert__GPR64AsmReg1_0__imm_95_0,
503
  Convert__regZERO__GPR32AsmReg1_0,
504
  Convert__GPR64AsmReg1_0,
505
  Convert__regZERO_64__GPR64AsmReg1_0,
506
  Convert__UImm5Lsl21_0,
507
  Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1,
508
  Convert__FGR64AsmReg1_0__MemOffsetSimm162_1,
509
  Convert__FGR32AsmReg1_0__MemOffsetSimm162_1,
510
  Convert__GPR32AsmReg1_0__Imm1_1,
511
  Convert__GPR32AsmReg1_0__Mem2_1,
512
  Convert__GPR32AsmReg1_0__MemOffsetSimm162_1,
513
  Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1,
514
  Convert__GPR32AsmReg1_0__MemOffsetSimm92_1,
515
  Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1,
516
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
517
  Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1,
518
  Convert__MSA128AsmReg1_0__MemOffsetSimm102_1,
519
  Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1,
520
  Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1,
521
  Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1,
522
  Convert__COP2AsmReg1_0__MemOffsetSimm112_1,
523
  Convert__COP2AsmReg1_0__MemOffsetSimm162_1,
524
  Convert__COP3AsmReg1_0__Mem2_1,
525
  Convert__MSA128AsmReg1_0__ConstantSImm10_01_1,
526
  Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1,
527
  Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
528
  Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
529
  Convert__GPR32AsmReg1_0__UImm32_Coerced1_1,
530
  Convert__StrictlyAFGR64AsmReg1_0__Imm1_1,
531
  Convert__StrictlyFGR64AsmReg1_0__Imm1_1,
532
  Convert__StrictlyFGR32AsmReg1_0__Imm1_1,
533
  Convert__GPRMM16AsmReg1_0__UImm7_N11_1,
534
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3,
535
  Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3,
536
  Convert__GPR32AsmReg1_0__UImm161_1,
537
  Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1,
538
  Convert__Reg1_0__Imm1_1__imm_95_0,
539
  Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1,
540
  Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1,
541
  Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1,
542
  Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1,
543
  Convert__RegList1_0__Mem2_1,
544
  Convert__RegList161_0__MemOffsetUimm42_1,
545
  ConvertCustom_ConvertXWPOperands,
546
  Convert__GPR32AsmReg1_0__MemOffsetSimm122_1,
547
  Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
548
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3,
549
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3,
550
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3,
551
  Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2,
552
  Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2,
553
  Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0,
554
  Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2,
555
  Convert__GPR32AsmReg1_0__FGR64AsmReg1_1,
556
  Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0,
557
  Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2,
558
  Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1,
559
  Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1,
560
  Convert__GPR32AsmReg1_0__regAC0,
561
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0,
562
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4,
563
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO,
564
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64,
565
  Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3,
566
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
567
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
568
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
569
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
570
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
571
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
572
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
573
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
574
  Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0,
575
  Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2,
576
  Convert__FGR64AsmReg1_1__GPR32AsmReg1_0,
577
  Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0,
578
  Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2,
579
  Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0,
580
  Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0,
581
  Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0,
582
  Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1,
583
  Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0,
584
  Convert__regAC0__GPR32AsmReg1_0,
585
  Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0,
586
  Convert__GPR32AsmReg1_1__GPR32AsmReg1_0,
587
  Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4,
588
  Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
589
  Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0,
590
  Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1,
591
  Convert__regZERO__regZERO__imm_95_0,
592
  Convert__regZERO__regS0,
593
  Convert__regZERO__regZERO,
594
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO,
595
  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1,
596
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0,
597
  Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0,
598
  Convert__GPR32AsmReg1_0__ConstantUImm7_01_1,
599
  Convert__GPR32AsmReg1_0__ConstantUImm10_01_1,
600
  Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0,
601
  Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0,
602
  Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2,
603
  Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2,
604
  Convert__GPR32AsmReg1_0__ConstantSImm10_01_1,
605
  Convert__GPR32AsmReg1_0__ConstantUImm8_01_1,
606
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1,
607
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2,
608
  Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1,
609
  Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1,
610
  Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1,
611
  Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1,
612
  Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1,
613
  Convert__ConstantUImm20_01_0,
614
  Convert__Reg1_0__Tie0_1_1,
615
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1,
616
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2,
617
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0,
618
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1,
619
  Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1,
620
  Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1,
621
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2,
622
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2,
623
  Convert__UImm161_0,
624
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3,
625
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3,
626
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3,
627
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3,
628
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3,
629
  Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2,
630
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3,
631
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3,
632
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3,
633
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3,
634
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3,
635
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1,
636
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2,
637
  Convert__ConstantUImm5_01_0,
638
  Convert__MemOffsetSimm162_0,
639
  Convert__imm_95_2,
640
  Convert__imm_95_6,
641
  Convert__imm_95_4,
642
  Convert__imm_95_5,
643
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2,
644
  Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2,
645
  Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2,
646
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2,
647
  Convert__GPR32AsmReg1_0__imm_95_31,
648
  CVT_NUM_SIGNATURES
649
};
650
651
} // end anonymous namespace
652
653
static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][11] = {
654
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1
655
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
656
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1
657
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
658
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1
659
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
660
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1
661
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
662
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1
663
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
664
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1
665
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
666
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
667
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
668
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2
669
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
670
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2
671
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done },
672
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
673
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
674
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
675
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
676
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1
677
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
678
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2
679
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done },
680
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1
681
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
682
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1
683
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
684
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2
685
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
686
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2
687
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
688
  // Convert__SImm161_1
689
  { CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
690
  // Convert__Reg1_0__SImm161_1
691
  { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
692
  // Convert__Reg1_0__SImm161_2
693
  { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
694
  // Convert__Reg1_0__Reg1_1__SImm161_2
695
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
696
  // Convert__Reg1_0__Tie0_1_1__SImm161_1
697
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
698
  // Convert__GPR32AsmReg1_0__Simm19_Lsl21_1
699
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
700
  // Convert__GPRMM16AsmReg1_0__Imm1_1
701
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
702
  // Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1
703
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
704
  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2
705
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
706
  // Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1
707
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_, 2, CVT_Done },
708
  // Convert__Imm1_0
709
  { CVT_95_addImmOperands, 1, CVT_Done },
710
  // Convert__Reg1_0__Reg1_1__Reg1_2
711
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
712
  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2
713
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addGPRMM16AsmRegOperands, 3, CVT_Done },
714
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2
715
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
716
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3
717
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
718
  // Convert__GPR32AsmReg1_0__SImm161_1
719
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
720
  // Convert__Reg1_0__Tie0_1_1__Reg1_1
721
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
722
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1
723
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
724
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1
725
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
726
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2
727
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
728
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2
729
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
730
  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1
731
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
732
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2
733
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
734
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1
735
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done },
736
  // Convert__regZERO__regZERO__JumpTarget1_0
737
  { CVT_regZERO, 0, CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done },
738
  // Convert__JumpTarget1_0
739
  { CVT_95_addImmOperands, 1, CVT_Done },
740
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1
741
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
742
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2
743
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },
744
  // Convert__regZERO__JumpTarget1_0
745
  { CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done },
746
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1
747
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done },
748
  // Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2
749
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
750
  // Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2
751
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
752
  // Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2
753
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
754
  // Convert__FGR64AsmReg1_0__JumpTarget1_1
755
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
756
  // Convert__regFCC0__JumpTarget1_0
757
  { CVT_regFCC0, 0, CVT_95_addImmOperands, 1, CVT_Done },
758
  // Convert__FCCAsmReg1_0__JumpTarget1_1
759
  { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
760
  // Convert__COP2AsmReg1_0__JumpTarget1_1
761
  { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
762
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2
763
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
764
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2
765
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
766
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2
767
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
768
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2
769
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
770
  // Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2
771
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
772
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2
773
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
774
  // Convert__Reg1_0__JumpTarget1_1
775
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
776
  // Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1
777
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addImmOperands, 2, CVT_Done },
778
  // Convert__GPRMM16AsmReg1_0__JumpTarget1_1
779
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
780
  // Convert__GPR32AsmReg1_0__JumpTarget1_1
781
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
782
  // Convert__GPR64AsmReg1_0__JumpTarget1_1
783
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
784
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2
785
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done },
786
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2
787
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
788
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2
789
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
790
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2
791
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
792
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2
793
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
794
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2
795
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
796
  // Convert__MSA128AsmReg1_0__JumpTarget1_1
797
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
798
  // Convert__imm_95_0__imm_95_0
799
  { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
800
  // Convert_NoOperands
801
  { CVT_Done },
802
  // Convert__ConstantUImm10_01_0__imm_95_0
803
  { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_imm_95_0, 0, CVT_Done },
804
  // Convert__ConstantUImm10_01_0__ConstantUImm10_01_1
805
  { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
806
  // Convert__ConstantUImm4_01_0
807
  { CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 1, CVT_Done },
808
  // Convert__SImm161_0
809
  { CVT_95_addSImmOperands_LT_16_GT_, 1, CVT_Done },
810
  // Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1
811
  { CVT_regFCC0, 0, CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
812
  // Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1
813
  { CVT_regFCC0, 0, CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
814
  // Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2
815
  { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done },
816
  // Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
817
  { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
818
  // Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1
819
  { CVT_regFCC0, 0, CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
820
  // Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
821
  { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
822
  // Convert__MemOffsetSimm92_1__ConstantUImm5_01_0
823
  { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
824
  // Convert__Mem2_1__ConstantUImm5_01_0
825
  { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
826
  // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1
827
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
828
  // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1
829
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
830
  // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1
831
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
832
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2
833
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
834
  // Convert__GPR32AsmReg1_0__CCRAsmReg1_1
835
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCCRAsmRegOperands, 2, CVT_Done },
836
  // Convert__GPR32AsmReg1_0__COP2AsmReg1_1
837
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_Done },
838
  // Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1
839
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSACtrlAsmRegOperands, 2, CVT_Done },
840
  // Convert__GPR32AsmReg1_0__FGR32AsmReg1_1
841
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
842
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2
843
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
844
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2
845
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
846
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3
847
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done },
848
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3
849
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done },
850
  // Convert__Reg1_0__Reg1_1
851
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
852
  // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
853
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
854
  // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3
855
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
856
  // Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3
857
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
858
  // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3
859
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
860
  // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3
861
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
862
  // Convert__CCRAsmReg1_1__GPR32AsmReg1_0
863
  { CVT_95_addCCRAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
864
  // Convert__COP2AsmReg1_1__GPR32AsmReg1_0
865
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
866
  // Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1
867
  { CVT_95_addMSACtrlAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
868
  // Convert__FGR32AsmReg1_1__GPR32AsmReg1_0
869
  { CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
870
  // Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1
871
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
872
  // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
873
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
874
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1
875
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
876
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2
877
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
878
  // Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2
879
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
880
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3
881
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
882
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2
883
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
884
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1
885
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
886
  // Convert__GPR64AsmReg1_1__GPR64AsmReg1_2
887
  { CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },
888
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3
889
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_, 4, CVT_Done },
890
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3
891
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
892
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3
893
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
894
  // Convert__regZERO
895
  { CVT_regZERO, 0, CVT_Done },
896
  // Convert__GPR32AsmReg1_0
897
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
898
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1
899
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addImmOperands, 4, CVT_Tied, Tie0_1_1, CVT_Done },
900
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1
901
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
902
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1
903
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
904
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1
905
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
906
  // Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1
907
  { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
908
  // Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1
909
  { CVT_95_addGPR32ZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
910
  // Convert__Reg1_1__Reg1_2
911
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
912
  // Convert__GPR32AsmReg1_1__GPR32AsmReg1_2
913
  { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
914
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2
915
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
916
  // Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
917
  { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
918
  // Convert__GPR64AsmReg1_0__Imm1_1
919
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
920
  // Convert__GPR64AsmReg1_0__Mem2_1
921
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
922
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3
923
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
924
  // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0
925
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
926
  // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2
927
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
928
  // Convert__GPR64AsmReg1_0__FGR64AsmReg1_1
929
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
930
  // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0
931
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
932
  // Convert__GPR64AsmReg1_0__UImm161_1
933
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
934
  // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2
935
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
936
  // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0
937
  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
938
  // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2
939
  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
940
  // Convert__FGR64AsmReg1_1__GPR64AsmReg1_0
941
  { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
942
  // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0
943
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
944
  // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2
945
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
946
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2
947
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
948
  // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0
949
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
950
  // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1
951
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
952
  // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
953
  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
954
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0
955
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
956
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1
957
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
958
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1
959
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 2, CVT_Done },
960
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2
961
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
962
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1
963
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done },
964
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2
965
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
966
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2
967
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
968
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1
969
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
970
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1
971
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
972
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2
973
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
974
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3
975
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
976
  // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2
977
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
978
  // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2
979
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
980
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1
981
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_Done },
982
  // Convert__MSA128AsmReg1_0__GPR32AsmReg1_1
983
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
984
  // Convert__MSA128AsmReg1_0__GPR64AsmReg1_1
985
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
986
  // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2
987
  { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
988
  // Convert__GPR32AsmReg1_0__ConstantUImm2_01_1
989
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 2, CVT_Done },
990
  // Convert__imm_95_0
991
  { CVT_imm_95_0, 0, CVT_Done },
992
  // Convert__ConstantUImm10_01_0
993
  { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_Done },
994
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1
995
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
996
  // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2
997
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
998
  // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2
999
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR64AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_Done },
1000
  // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2
1001
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1002
  // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2
1003
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Done },
1004
  // Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1
1005
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1006
  // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6
1007
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
1008
  // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6
1009
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
1010
  // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6
1011
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
1012
  // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6
1013
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
1014
  // Convert__regRA__GPR32AsmReg1_0
1015
  { CVT_regRA, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1016
  // Convert__regRA_64__GPR64AsmReg1_0
1017
  { CVT_regRA_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1018
  // Convert__Reg1_0
1019
  { CVT_95_Reg, 1, CVT_Done },
1020
  // Convert__GPR32AsmReg1_0__imm_95_0
1021
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1022
  // Convert__GPR64AsmReg1_0__imm_95_0
1023
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1024
  // Convert__regZERO__GPR32AsmReg1_0
1025
  { CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1026
  // Convert__GPR64AsmReg1_0
1027
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1028
  // Convert__regZERO_64__GPR64AsmReg1_0
1029
  { CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1030
  // Convert__UImm5Lsl21_0
1031
  { CVT_95_addImmOperands, 1, CVT_Done },
1032
  // Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1
1033
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1034
  // Convert__FGR64AsmReg1_0__MemOffsetSimm162_1
1035
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1036
  // Convert__FGR32AsmReg1_0__MemOffsetSimm162_1
1037
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1038
  // Convert__GPR32AsmReg1_0__Imm1_1
1039
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1040
  // Convert__GPR32AsmReg1_0__Mem2_1
1041
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1042
  // Convert__GPR32AsmReg1_0__MemOffsetSimm162_1
1043
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1044
  // Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1
1045
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1046
  // Convert__GPR32AsmReg1_0__MemOffsetSimm92_1
1047
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1048
  // Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1
1049
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done },
1050
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1051
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1052
  // Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1
1053
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1054
  // Convert__MSA128AsmReg1_0__MemOffsetSimm102_1
1055
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1056
  // Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1
1057
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1058
  // Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1
1059
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1060
  // Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1
1061
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1062
  // Convert__COP2AsmReg1_0__MemOffsetSimm112_1
1063
  { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1064
  // Convert__COP2AsmReg1_0__MemOffsetSimm162_1
1065
  { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1066
  // Convert__COP3AsmReg1_0__Mem2_1
1067
  { CVT_95_addCOP3AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1068
  // Convert__MSA128AsmReg1_0__ConstantSImm10_01_1
1069
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1070
  // Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1
1071
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1072
  // Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1073
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1074
  // Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1075
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1076
  // Convert__GPR32AsmReg1_0__UImm32_Coerced1_1
1077
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_32_GT_, 2, CVT_Done },
1078
  // Convert__StrictlyAFGR64AsmReg1_0__Imm1_1
1079
  { CVT_95_addStrictlyAFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1080
  // Convert__StrictlyFGR64AsmReg1_0__Imm1_1
1081
  { CVT_95_addStrictlyFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1082
  // Convert__StrictlyFGR32AsmReg1_0__Imm1_1
1083
  { CVT_95_addStrictlyFGR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1084
  // Convert__GPRMM16AsmReg1_0__UImm7_N11_1
1085
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_, 2, CVT_Done },
1086
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3
1087
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
1088
  // Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3
1089
  { CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
1090
  // Convert__GPR32AsmReg1_0__UImm161_1
1091
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
1092
  // Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1
1093
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
1094
  // Convert__Reg1_0__Imm1_1__imm_95_0
1095
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1096
  // Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1
1097
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1098
  // Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1
1099
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1100
  // Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1
1101
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1102
  // Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1
1103
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1104
  // Convert__RegList1_0__Mem2_1
1105
  { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1106
  // Convert__RegList161_0__MemOffsetUimm42_1
1107
  { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1108
  // ConvertCustom_ConvertXWPOperands
1109
  { CVT_ConvertXWPOperands, 0, CVT_Done },
1110
  // Convert__GPR32AsmReg1_0__MemOffsetSimm122_1
1111
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1112
  // Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1113
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1114
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3
1115
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_95_addAFGR64AsmRegOperands, 4, CVT_Done },
1116
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3
1117
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_95_addFGR64AsmRegOperands, 4, CVT_Done },
1118
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3
1119
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 4, CVT_Done },
1120
  // Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2
1121
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
1122
  // Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2
1123
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
1124
  // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0
1125
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1126
  // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2
1127
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1128
  // Convert__GPR32AsmReg1_0__FGR64AsmReg1_1
1129
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
1130
  // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0
1131
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1132
  // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2
1133
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1134
  // Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1
1135
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
1136
  // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1
1137
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_Done },
1138
  // Convert__GPR32AsmReg1_0__regAC0
1139
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regAC0, 0, CVT_Done },
1140
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0
1141
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1142
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4
1143
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done },
1144
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO
1145
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_regZERO, 0, CVT_Done },
1146
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64
1147
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_regZERO_64, 0, CVT_Done },
1148
  // Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3
1149
  { CVT_95_addGPRMM16AsmRegMovePPairFirstOperands, 1, CVT_95_addGPRMM16AsmRegMovePPairSecondOperands, 2, CVT_95_addGPRMM16AsmRegMovePOperands, 3, CVT_95_addGPRMM16AsmRegMovePOperands, 4, CVT_Done },
1150
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1151
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1152
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1153
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1154
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1155
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1156
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1157
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1158
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1159
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1160
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1161
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1162
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1163
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1164
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1165
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1166
  // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0
1167
  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1168
  // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2
1169
  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1170
  // Convert__FGR64AsmReg1_1__GPR32AsmReg1_0
1171
  { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1172
  // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0
1173
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1174
  // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2
1175
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1176
  // Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0
1177
  { CVT_95_addAFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1178
  // Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0
1179
  { CVT_95_addFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1180
  // Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0
1181
  { CVT_95_addHI32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1182
  // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1
1183
  { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_Done },
1184
  // Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0
1185
  { CVT_95_addLO32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1186
  // Convert__regAC0__GPR32AsmReg1_0
1187
  { CVT_regAC0, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1188
  // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0
1189
  { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1190
  // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0
1191
  { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1192
  // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4
1193
  { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done },
1194
  // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
1195
  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1196
  // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0
1197
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1198
  // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1
1199
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1200
  // Convert__regZERO__regZERO__imm_95_0
1201
  { CVT_regZERO, 0, CVT_regZERO, 0, CVT_imm_95_0, 0, CVT_Done },
1202
  // Convert__regZERO__regS0
1203
  { CVT_regZERO, 0, CVT_regS0, 0, CVT_Done },
1204
  // Convert__regZERO__regZERO
1205
  { CVT_regZERO, 0, CVT_regZERO, 0, CVT_Done },
1206
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO
1207
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_Done },
1208
  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1
1209
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Done },
1210
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0
1211
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1212
  // Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0
1213
  { CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
1214
  // Convert__GPR32AsmReg1_0__ConstantUImm7_01_1
1215
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_, 2, CVT_Done },
1216
  // Convert__GPR32AsmReg1_0__ConstantUImm10_01_1
1217
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1218
  // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0
1219
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1220
  // Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0
1221
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1222
  // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2
1223
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1224
  // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2
1225
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
1226
  // Convert__GPR32AsmReg1_0__ConstantSImm10_01_1
1227
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1228
  // Convert__GPR32AsmReg1_0__ConstantUImm8_01_1
1229
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 2, CVT_Done },
1230
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1
1231
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done },
1232
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2
1233
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
1234
  // Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1
1235
  { CVT_95_addGPRMM16AsmRegZeroOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done },
1236
  // Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1
1237
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
1238
  // Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1
1239
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
1240
  // Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1
1241
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
1242
  // Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1
1243
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
1244
  // Convert__ConstantUImm20_01_0
1245
  { CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_, 1, CVT_Done },
1246
  // Convert__Reg1_0__Tie0_1_1
1247
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done },
1248
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1
1249
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1250
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2
1251
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done },
1252
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0
1253
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1254
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1
1255
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1256
  // Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1
1257
  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1258
  // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1
1259
  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1260
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2
1261
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
1262
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2
1263
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1264
  // Convert__UImm161_0
1265
  { CVT_95_addUImmOperands_LT_16_GT_, 1, CVT_Done },
1266
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3
1267
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done },
1268
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3
1269
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
1270
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3
1271
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
1272
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3
1273
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
1274
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3
1275
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
1276
  // Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2
1277
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
1278
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3
1279
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done },
1280
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3
1281
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
1282
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3
1283
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
1284
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3
1285
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
1286
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3
1287
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
1288
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1
1289
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1290
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2
1291
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1292
  // Convert__ConstantUImm5_01_0
1293
  { CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
1294
  // Convert__MemOffsetSimm162_0
1295
  { CVT_95_addMemOperands, 1, CVT_Done },
1296
  // Convert__imm_95_2
1297
  { CVT_imm_95_2, 0, CVT_Done },
1298
  // Convert__imm_95_6
1299
  { CVT_imm_95_6, 0, CVT_Done },
1300
  // Convert__imm_95_4
1301
  { CVT_imm_95_4, 0, CVT_Done },
1302
  // Convert__imm_95_5
1303
  { CVT_imm_95_5, 0, CVT_Done },
1304
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2
1305
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done },
1306
  // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2
1307
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1308
  // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2
1309
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1310
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2
1311
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1312
  // Convert__GPR32AsmReg1_0__imm_95_31
1313
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_31, 0, CVT_Done },
1314
};
1315
1316
void MipsAsmParser::
1317
convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
1318
36.3k
                const OperandVector &Operands) {
1319
36.3k
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
1320
36.3k
  const uint8_t *Converter = ConversionTable[Kind];
1321
36.3k
  unsigned OpIdx;
1322
36.3k
  Inst.setOpcode(Opcode);
1323
126k
  for (const uint8_t *p = Converter; *p; 
p+= 290.2k
) {
1324
90.2k
    OpIdx = *(p + 1);
1325
90.2k
    switch (*p) {
1326
90.2k
    
default: 0
llvm_unreachable0
("invalid conversion entry!");
1327
90.2k
    case CVT_Reg:
1328
0
      static_cast<MipsOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
1329
0
      break;
1330
90.2k
    case CVT_Tied: {
1331
627
      assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
1332
627
                          std::begin(TiedAsmOperandTable)) &&
1333
627
             "Tied operand not found");
1334
627
      unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];
1335
627
      if (TiedResOpnd != (uint8_t) -1)
1336
627
        Inst.addOperand(Inst.getOperand(TiedResOpnd));
1337
627
      break;
1338
90.2k
    }
1339
90.2k
    case CVT_95_addGPR32AsmRegOperands:
1340
24.2k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32AsmRegOperands(Inst, 1);
1341
24.2k
      break;
1342
90.2k
    case CVT_95_addAFGR64AsmRegOperands:
1343
924
      static_cast<MipsOperand&>(*Operands[OpIdx]).addAFGR64AsmRegOperands(Inst, 1);
1344
924
      break;
1345
90.2k
    case CVT_95_addFGR64AsmRegOperands:
1346
1.31k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addFGR64AsmRegOperands(Inst, 1);
1347
1.31k
      break;
1348
90.2k
    case CVT_95_addFGR32AsmRegOperands:
1349
2.55k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addFGR32AsmRegOperands(Inst, 1);
1350
2.55k
      break;
1351
90.2k
    case CVT_95_addSImmOperands_LT_32_GT_:
1352
636
      static_cast<MipsOperand&>(*Operands[OpIdx]).addSImmOperands<32>(Inst, 1);
1353
636
      break;
1354
90.2k
    case CVT_95_addMSA128AsmRegOperands:
1355
1.40k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addMSA128AsmRegOperands(Inst, 1);
1356
1.40k
      break;
1357
90.2k
    case CVT_95_addSImmOperands_LT_16_GT_:
1358
1.34k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addSImmOperands<16>(Inst, 1);
1359
1.34k
      break;
1360
90.2k
    case CVT_95_Reg:
1361
0
      static_cast<MipsOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
1362
0
      break;
1363
90.2k
    case CVT_95_addImmOperands:
1364
3.57k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
1365
3.57k
      break;
1366
90.2k
    case CVT_95_addGPRMM16AsmRegOperands:
1367
178
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegOperands(Inst, 1);
1368
178
      break;
1369
90.2k
    case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_:
1370
4
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<4, 0>(Inst, 1);
1371
4
      break;
1372
90.2k
    case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_:
1373
475
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 0>(Inst, 1);
1374
475
      break;
1375
90.2k
    case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_:
1376
14
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<2, 0>(Inst, 1);
1377
14
      break;
1378
90.2k
    case CVT_95_addUImmOperands_LT_16_GT_:
1379
236
      static_cast<MipsOperand&>(*Operands[OpIdx]).addUImmOperands<16>(Inst, 1);
1380
236
      break;
1381
90.2k
    case CVT_95_addGPR64AsmRegOperands:
1382
3.96k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR64AsmRegOperands(Inst, 1);
1383
3.96k
      break;
1384
90.2k
    case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_:
1385
15
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<8, 0>(Inst, 1);
1386
15
      break;
1387
90.2k
    case CVT_regZERO:
1388
22.0k
      Inst.addOperand(MCOperand::createReg(Mips::ZERO));
1389
22.0k
      break;
1390
90.2k
    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_:
1391
6
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 32, -32>(Inst, 1);
1392
6
      break;
1393
90.2k
    case CVT_regFCC0:
1394
282
      Inst.addOperand(MCOperand::createReg(Mips::FCC0));
1395
282
      break;
1396
90.2k
    case CVT_95_addFCCAsmRegOperands:
1397
734
      static_cast<MipsOperand&>(*Operands[OpIdx]).addFCCAsmRegOperands(Inst, 1);
1398
734
      break;
1399
90.2k
    case CVT_95_addCOP2AsmRegOperands:
1400
122
      static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP2AsmRegOperands(Inst, 1);
1401
122
      break;
1402
90.2k
    case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_:
1403
155
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<3, 0>(Inst, 1);
1404
155
      break;
1405
90.2k
    case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_:
1406
76
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<6, 0>(Inst, 1);
1407
76
      break;
1408
90.2k
    case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_:
1409
62
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<4, 0>(Inst, 1);
1410
62
      break;
1411
90.2k
    case CVT_imm_95_0:
1412
11.1k
      Inst.addOperand(MCOperand::createImm(0));
1413
11.1k
      break;
1414
90.2k
    case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_:
1415
132
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<10, 0>(Inst, 1);
1416
132
      break;
1417
90.2k
    case CVT_95_addMemOperands:
1418
12.6k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addMemOperands(Inst, 2);
1419
12.6k
      break;
1420
90.2k
    case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_:
1421
20
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<5, 0>(Inst, 1);
1422
20
      break;
1423
90.2k
    case CVT_95_addCCRAsmRegOperands:
1424
38
      static_cast<MipsOperand&>(*Operands[OpIdx]).addCCRAsmRegOperands(Inst, 1);
1425
38
      break;
1426
90.2k
    case CVT_95_addMSACtrlAsmRegOperands:
1427
32
      static_cast<MipsOperand&>(*Operands[OpIdx]).addMSACtrlAsmRegOperands(Inst, 1);
1428
32
      break;
1429
90.2k
    case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_:
1430
53
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<1, 0>(Inst, 1);
1431
53
      break;
1432
90.2k
    case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_:
1433
10
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 33>(Inst, 1);
1434
10
      break;
1435
90.2k
    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_:
1436
20
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 32>(Inst, 1);
1437
20
      break;
1438
90.2k
    case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_:
1439
42
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 1>(Inst, 1);
1440
42
      break;
1441
90.2k
    case CVT_95_addGPR32NonZeroAsmRegOperands:
1442
50
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32NonZeroAsmRegOperands(Inst, 1);
1443
50
      break;
1444
90.2k
    case CVT_95_addGPR32ZeroAsmRegOperands:
1445
16
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32ZeroAsmRegOperands(Inst, 1);
1446
16
      break;
1447
90.2k
    case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_:
1448
12
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<2, 1>(Inst, 1);
1449
12
      break;
1450
90.2k
    case CVT_95_addCOP0AsmRegOperands:
1451
116
      static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP0AsmRegOperands(Inst, 1);
1452
116
      break;
1453
90.2k
    case CVT_regZERO_64:
1454
87
      Inst.addOperand(MCOperand::createReg(Mips::ZERO_64));
1455
87
      break;
1456
90.2k
    case CVT_95_addACC64DSPAsmRegOperands:
1457
180
      static_cast<MipsOperand&>(*Operands[OpIdx]).addACC64DSPAsmRegOperands(Inst, 1);
1458
180
      break;
1459
90.2k
    case CVT_95_addConstantUImmOperands_LT_1_GT_:
1460
4
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<1>(Inst, 1);
1461
4
      break;
1462
90.2k
    case CVT_regRA:
1463
40
      Inst.addOperand(MCOperand::createReg(Mips::RA));
1464
40
      break;
1465
90.2k
    case CVT_regRA_64:
1466
5
      Inst.addOperand(MCOperand::createReg(Mips::RA_64));
1467
5
      break;
1468
90.2k
    case CVT_95_addMicroMipsMemOperands:
1469
50
      static_cast<MipsOperand&>(*Operands[OpIdx]).addMicroMipsMemOperands(Inst, 2);
1470
50
      break;
1471
90.2k
    case CVT_95_addCOP3AsmRegOperands:
1472
6
      static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP3AsmRegOperands(Inst, 1);
1473
6
      break;
1474
90.2k
    case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_:
1475
12
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<10, 0>(Inst, 1);
1476
12
      break;
1477
90.2k
    case CVT_95_addConstantUImmOperands_LT_32_GT_:
1478
206
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<32>(Inst, 1);
1479
206
      break;
1480
90.2k
    case CVT_95_addStrictlyAFGR64AsmRegOperands:
1481
39
      static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyAFGR64AsmRegOperands(Inst, 1);
1482
39
      break;
1483
90.2k
    case CVT_95_addStrictlyFGR64AsmRegOperands:
1484
52
      static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyFGR64AsmRegOperands(Inst, 1);
1485
52
      break;
1486
90.2k
    case CVT_95_addStrictlyFGR32AsmRegOperands:
1487
66
      static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyFGR32AsmRegOperands(Inst, 1);
1488
66
      break;
1489
90.2k
    case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_:
1490
7
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<7, -1>(Inst, 1);
1491
7
      break;
1492
90.2k
    case CVT_95_addRegListOperands:
1493
63
      static_cast<MipsOperand&>(*Operands[OpIdx]).addRegListOperands(Inst, 1);
1494
63
      break;
1495
90.2k
    case CVT_ConvertXWPOperands:
1496
14
      ConvertXWPOperands(Inst, Operands);
1497
14
      break;
1498
90.2k
    case CVT_regAC0:
1499
4
      Inst.addOperand(MCOperand::createReg(Mips::AC0));
1500
4
      break;
1501
90.2k
    case CVT_95_addGPRMM16AsmRegMovePPairFirstOperands:
1502
6
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegMovePPairFirstOperands(Inst, 1);
1503
6
      break;
1504
90.2k
    case CVT_95_addGPRMM16AsmRegMovePPairSecondOperands:
1505
6
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegMovePPairSecondOperands(Inst, 1);
1506
6
      break;
1507
90.2k
    case CVT_95_addGPRMM16AsmRegMovePOperands:
1508
12
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegMovePOperands(Inst, 1);
1509
12
      break;
1510
90.2k
    case CVT_95_addHI32DSPAsmRegOperands:
1511
3
      static_cast<MipsOperand&>(*Operands[OpIdx]).addHI32DSPAsmRegOperands(Inst, 1);
1512
3
      break;
1513
90.2k
    case CVT_95_addLO32DSPAsmRegOperands:
1514
3
      static_cast<MipsOperand&>(*Operands[OpIdx]).addLO32DSPAsmRegOperands(Inst, 1);
1515
3
      break;
1516
90.2k
    case CVT_regS0:
1517
2
      Inst.addOperand(MCOperand::createReg(Mips::S0));
1518
2
      break;
1519
90.2k
    case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_:
1520
5
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<7, 0>(Inst, 1);
1521
5
      break;
1522
90.2k
    case CVT_95_addHWRegsAsmRegOperands:
1523
60
      static_cast<MipsOperand&>(*Operands[OpIdx]).addHWRegsAsmRegOperands(Inst, 1);
1524
60
      break;
1525
90.2k
    case CVT_95_addGPRMM16AsmRegZeroOperands:
1526
22
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegZeroOperands(Inst, 1);
1527
22
      break;
1528
90.2k
    case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_:
1529
25
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<20, 0>(Inst, 1);
1530
25
      break;
1531
90.2k
    case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_:
1532
6
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<6, 0>(Inst, 1);
1533
6
      break;
1534
90.2k
    case CVT_imm_95_2:
1535
1
      Inst.addOperand(MCOperand::createImm(2));
1536
1
      break;
1537
90.2k
    case CVT_imm_95_6:
1538
1
      Inst.addOperand(MCOperand::createImm(6));
1539
1
      break;
1540
90.2k
    case CVT_imm_95_4:
1541
1
      Inst.addOperand(MCOperand::createImm(4));
1542
1
      break;
1543
90.2k
    case CVT_imm_95_5:
1544
1
      Inst.addOperand(MCOperand::createImm(5));
1545
1
      break;
1546
90.2k
    case CVT_imm_95_31:
1547
4
      Inst.addOperand(MCOperand::createImm(31));
1548
4
      break;
1549
90.2k
    }
1550
90.2k
  }
1551
36.3k
}
1552
1553
void MipsAsmParser::
1554
convertToMapAndConstraints(unsigned Kind,
1555
0
                           const OperandVector &Operands) {
1556
0
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
1557
0
  unsigned NumMCOperands = 0;
1558
0
  const uint8_t *Converter = ConversionTable[Kind];
1559
0
  for (const uint8_t *p = Converter; *p; p+= 2) {
1560
0
    switch (*p) {
1561
0
    default: llvm_unreachable("invalid conversion entry!");
1562
0
    case CVT_Reg:
1563
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1564
0
      Operands[*(p + 1)]->setConstraint("r");
1565
0
      ++NumMCOperands;
1566
0
      break;
1567
0
    case CVT_Tied:
1568
0
      ++NumMCOperands;
1569
0
      break;
1570
0
    case CVT_95_addGPR32AsmRegOperands:
1571
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1572
0
      Operands[*(p + 1)]->setConstraint("m");
1573
0
      NumMCOperands += 1;
1574
0
      break;
1575
0
    case CVT_95_addAFGR64AsmRegOperands:
1576
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1577
0
      Operands[*(p + 1)]->setConstraint("m");
1578
0
      NumMCOperands += 1;
1579
0
      break;
1580
0
    case CVT_95_addFGR64AsmRegOperands:
1581
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1582
0
      Operands[*(p + 1)]->setConstraint("m");
1583
0
      NumMCOperands += 1;
1584
0
      break;
1585
0
    case CVT_95_addFGR32AsmRegOperands:
1586
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1587
0
      Operands[*(p + 1)]->setConstraint("m");
1588
0
      NumMCOperands += 1;
1589
0
      break;
1590
0
    case CVT_95_addSImmOperands_LT_32_GT_:
1591
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1592
0
      Operands[*(p + 1)]->setConstraint("m");
1593
0
      NumMCOperands += 1;
1594
0
      break;
1595
0
    case CVT_95_addMSA128AsmRegOperands:
1596
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1597
0
      Operands[*(p + 1)]->setConstraint("m");
1598
0
      NumMCOperands += 1;
1599
0
      break;
1600
0
    case CVT_95_addSImmOperands_LT_16_GT_:
1601
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1602
0
      Operands[*(p + 1)]->setConstraint("m");
1603
0
      NumMCOperands += 1;
1604
0
      break;
1605
0
    case CVT_95_Reg:
1606
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1607
0
      Operands[*(p + 1)]->setConstraint("r");
1608
0
      NumMCOperands += 1;
1609
0
      break;
1610
0
    case CVT_95_addImmOperands:
1611
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1612
0
      Operands[*(p + 1)]->setConstraint("m");
1613
0
      NumMCOperands += 1;
1614
0
      break;
1615
0
    case CVT_95_addGPRMM16AsmRegOperands:
1616
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1617
0
      Operands[*(p + 1)]->setConstraint("m");
1618
0
      NumMCOperands += 1;
1619
0
      break;
1620
0
    case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_:
1621
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1622
0
      Operands[*(p + 1)]->setConstraint("m");
1623
0
      NumMCOperands += 1;
1624
0
      break;
1625
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_:
1626
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1627
0
      Operands[*(p + 1)]->setConstraint("m");
1628
0
      NumMCOperands += 1;
1629
0
      break;
1630
0
    case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_:
1631
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1632
0
      Operands[*(p + 1)]->setConstraint("m");
1633
0
      NumMCOperands += 1;
1634
0
      break;
1635
0
    case CVT_95_addUImmOperands_LT_16_GT_:
1636
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1637
0
      Operands[*(p + 1)]->setConstraint("m");
1638
0
      NumMCOperands += 1;
1639
0
      break;
1640
0
    case CVT_95_addGPR64AsmRegOperands:
1641
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1642
0
      Operands[*(p + 1)]->setConstraint("m");
1643
0
      NumMCOperands += 1;
1644
0
      break;
1645
0
    case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_:
1646
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1647
0
      Operands[*(p + 1)]->setConstraint("m");
1648
0
      NumMCOperands += 1;
1649
0
      break;
1650
0
    case CVT_regZERO:
1651
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1652
0
      Operands[*(p + 1)]->setConstraint("m");
1653
0
      ++NumMCOperands;
1654
0
      break;
1655
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_:
1656
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1657
0
      Operands[*(p + 1)]->setConstraint("m");
1658
0
      NumMCOperands += 1;
1659
0
      break;
1660
0
    case CVT_regFCC0:
1661
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1662
0
      Operands[*(p + 1)]->setConstraint("m");
1663
0
      ++NumMCOperands;
1664
0
      break;
1665
0
    case CVT_95_addFCCAsmRegOperands:
1666
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1667
0
      Operands[*(p + 1)]->setConstraint("m");
1668
0
      NumMCOperands += 1;
1669
0
      break;
1670
0
    case CVT_95_addCOP2AsmRegOperands:
1671
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1672
0
      Operands[*(p + 1)]->setConstraint("m");
1673
0
      NumMCOperands += 1;
1674
0
      break;
1675
0
    case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_:
1676
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1677
0
      Operands[*(p + 1)]->setConstraint("m");
1678
0
      NumMCOperands += 1;
1679
0
      break;
1680
0
    case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_:
1681
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1682
0
      Operands[*(p + 1)]->setConstraint("m");
1683
0
      NumMCOperands += 1;
1684
0
      break;
1685
0
    case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_:
1686
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1687
0
      Operands[*(p + 1)]->setConstraint("m");
1688
0
      NumMCOperands += 1;
1689
0
      break;
1690
0
    case CVT_imm_95_0:
1691
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1692
0
      Operands[*(p + 1)]->setConstraint("");
1693
0
      ++NumMCOperands;
1694
0
      break;
1695
0
    case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_:
1696
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1697
0
      Operands[*(p + 1)]->setConstraint("m");
1698
0
      NumMCOperands += 1;
1699
0
      break;
1700
0
    case CVT_95_addMemOperands:
1701
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1702
0
      Operands[*(p + 1)]->setConstraint("m");
1703
0
      NumMCOperands += 2;
1704
0
      break;
1705
0
    case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_:
1706
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1707
0
      Operands[*(p + 1)]->setConstraint("m");
1708
0
      NumMCOperands += 1;
1709
0
      break;
1710
0
    case CVT_95_addCCRAsmRegOperands:
1711
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1712
0
      Operands[*(p + 1)]->setConstraint("m");
1713
0
      NumMCOperands += 1;
1714
0
      break;
1715
0
    case CVT_95_addMSACtrlAsmRegOperands:
1716
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1717
0
      Operands[*(p + 1)]->setConstraint("m");
1718
0
      NumMCOperands += 1;
1719
0
      break;
1720
0
    case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_:
1721
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1722
0
      Operands[*(p + 1)]->setConstraint("m");
1723
0
      NumMCOperands += 1;
1724
0
      break;
1725
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_:
1726
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1727
0
      Operands[*(p + 1)]->setConstraint("m");
1728
0
      NumMCOperands += 1;
1729
0
      break;
1730
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_:
1731
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1732
0
      Operands[*(p + 1)]->setConstraint("m");
1733
0
      NumMCOperands += 1;
1734
0
      break;
1735
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_:
1736
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1737
0
      Operands[*(p + 1)]->setConstraint("m");
1738
0
      NumMCOperands += 1;
1739
0
      break;
1740
0
    case CVT_95_addGPR32NonZeroAsmRegOperands:
1741
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1742
0
      Operands[*(p + 1)]->setConstraint("m");
1743
0
      NumMCOperands += 1;
1744
0
      break;
1745
0
    case CVT_95_addGPR32ZeroAsmRegOperands:
1746
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1747
0
      Operands[*(p + 1)]->setConstraint("m");
1748
0
      NumMCOperands += 1;
1749
0
      break;
1750
0
    case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_:
1751
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1752
0
      Operands[*(p + 1)]->setConstraint("m");
1753
0
      NumMCOperands += 1;
1754
0
      break;
1755
0
    case CVT_95_addCOP0AsmRegOperands:
1756
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1757
0
      Operands[*(p + 1)]->setConstraint("m");
1758
0
      NumMCOperands += 1;
1759
0
      break;
1760
0
    case CVT_regZERO_64:
1761
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1762
0
      Operands[*(p + 1)]->setConstraint("m");
1763
0
      ++NumMCOperands;
1764
0
      break;
1765
0
    case CVT_95_addACC64DSPAsmRegOperands:
1766
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1767
0
      Operands[*(p + 1)]->setConstraint("m");
1768
0
      NumMCOperands += 1;
1769
0
      break;
1770
0
    case CVT_95_addConstantUImmOperands_LT_1_GT_:
1771
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1772
0
      Operands[*(p + 1)]->setConstraint("m");
1773
0
      NumMCOperands += 1;
1774
0
      break;
1775
0
    case CVT_regRA:
1776
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1777
0
      Operands[*(p + 1)]->setConstraint("m");
1778
0
      ++NumMCOperands;
1779
0
      break;
1780
0
    case CVT_regRA_64:
1781
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1782
0
      Operands[*(p + 1)]->setConstraint("m");
1783
0
      ++NumMCOperands;
1784
0
      break;
1785
0
    case CVT_95_addMicroMipsMemOperands:
1786
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1787
0
      Operands[*(p + 1)]->setConstraint("m");
1788
0
      NumMCOperands += 2;
1789
0
      break;
1790
0
    case CVT_95_addCOP3AsmRegOperands:
1791
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1792
0
      Operands[*(p + 1)]->setConstraint("m");
1793
0
      NumMCOperands += 1;
1794
0
      break;
1795
0
    case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_:
1796
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1797
0
      Operands[*(p + 1)]->setConstraint("m");
1798
0
      NumMCOperands += 1;
1799
0
      break;
1800
0
    case CVT_95_addConstantUImmOperands_LT_32_GT_:
1801
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1802
0
      Operands[*(p + 1)]->setConstraint("m");
1803
0
      NumMCOperands += 1;
1804
0
      break;
1805
0
    case CVT_95_addStrictlyAFGR64AsmRegOperands:
1806
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1807
0
      Operands[*(p + 1)]->setConstraint("m");
1808
0
      NumMCOperands += 1;
1809
0
      break;
1810
0
    case CVT_95_addStrictlyFGR64AsmRegOperands:
1811
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1812
0
      Operands[*(p + 1)]->setConstraint("m");
1813
0
      NumMCOperands += 1;
1814
0
      break;
1815
0
    case CVT_95_addStrictlyFGR32AsmRegOperands:
1816
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1817
0
      Operands[*(p + 1)]->setConstraint("m");
1818
0
      NumMCOperands += 1;
1819
0
      break;
1820
0
    case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_:
1821
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1822
0
      Operands[*(p + 1)]->setConstraint("m");
1823
0
      NumMCOperands += 1;
1824
0
      break;
1825
0
    case CVT_95_addRegListOperands:
1826
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1827
0
      Operands[*(p + 1)]->setConstraint("m");
1828
0
      NumMCOperands += 1;
1829
0
      break;
1830
0
    case CVT_regAC0:
1831
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1832
0
      Operands[*(p + 1)]->setConstraint("m");
1833
0
      ++NumMCOperands;
1834
0
      break;
1835
0
    case CVT_95_addGPRMM16AsmRegMovePPairFirstOperands:
1836
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1837
0
      Operands[*(p + 1)]->setConstraint("m");
1838
0
      NumMCOperands += 1;
1839
0
      break;
1840
0
    case CVT_95_addGPRMM16AsmRegMovePPairSecondOperands:
1841
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1842
0
      Operands[*(p + 1)]->setConstraint("m");
1843
0
      NumMCOperands += 1;
1844
0
      break;
1845
0
    case CVT_95_addGPRMM16AsmRegMovePOperands:
1846
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1847
0
      Operands[*(p + 1)]->setConstraint("m");
1848
0
      NumMCOperands += 1;
1849
0
      break;
1850
0
    case CVT_95_addHI32DSPAsmRegOperands:
1851
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1852
0
      Operands[*(p + 1)]->setConstraint("m");
1853
0
      NumMCOperands += 1;
1854
0
      break;
1855
0
    case CVT_95_addLO32DSPAsmRegOperands:
1856
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1857
0
      Operands[*(p + 1)]->setConstraint("m");
1858
0
      NumMCOperands += 1;
1859
0
      break;
1860
0
    case CVT_regS0:
1861
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1862
0
      Operands[*(p + 1)]->setConstraint("m");
1863
0
      ++NumMCOperands;
1864
0
      break;
1865
0
    case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_:
1866
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1867
0
      Operands[*(p + 1)]->setConstraint("m");
1868
0
      NumMCOperands += 1;
1869
0
      break;
1870
0
    case CVT_95_addHWRegsAsmRegOperands:
1871
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1872
0
      Operands[*(p + 1)]->setConstraint("m");
1873
0
      NumMCOperands += 1;
1874
0
      break;
1875
0
    case CVT_95_addGPRMM16AsmRegZeroOperands:
1876
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1877
0
      Operands[*(p + 1)]->setConstraint("m");
1878
0
      NumMCOperands += 1;
1879
0
      break;
1880
0
    case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_:
1881
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1882
0
      Operands[*(p + 1)]->setConstraint("m");
1883
0
      NumMCOperands += 1;
1884
0
      break;
1885
0
    case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_:
1886
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1887
0
      Operands[*(p + 1)]->setConstraint("m");
1888
0
      NumMCOperands += 1;
1889
0
      break;
1890
0
    case CVT_imm_95_2:
1891
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1892
0
      Operands[*(p + 1)]->setConstraint("");
1893
0
      ++NumMCOperands;
1894
0
      break;
1895
0
    case CVT_imm_95_6:
1896
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1897
0
      Operands[*(p + 1)]->setConstraint("");
1898
0
      ++NumMCOperands;
1899
0
      break;
1900
0
    case CVT_imm_95_4:
1901
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1902
0
      Operands[*(p + 1)]->setConstraint("");
1903
0
      ++NumMCOperands;
1904
0
      break;
1905
0
    case CVT_imm_95_5:
1906
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1907
0
      Operands[*(p + 1)]->setConstraint("");
1908
0
      ++NumMCOperands;
1909
0
      break;
1910
0
    case CVT_imm_95_31:
1911
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1912
0
      Operands[*(p + 1)]->setConstraint("");
1913
0
      ++NumMCOperands;
1914
0
      break;
1915
0
    }
1916
0
  }
1917
0
}
1918
1919
namespace {
1920
1921
/// MatchClassKind - The kinds of classes which participate in
1922
/// instruction matching.
1923
enum MatchClassKind {
1924
  InvalidMatchClass = 0,
1925
  OptionalMatchClass = 1,
1926
  MCK__35_, // '#'
1927
  MCK__40_, // '('
1928
  MCK__41_, // ')'
1929
  MCK_0, // '0'
1930
  MCK_16, // '16'
1931
  MCK__91_, // '['
1932
  MCK__93_, // ']'
1933
  MCK_bit, // 'bit'
1934
  MCK_inst, // 'inst'
1935
  MCK_LAST_TOKEN = MCK_inst,
1936
  MCK_Reg37, // derived register class
1937
  MCK_Reg19, // derived register class
1938
  MCK_ACC128, // register class 'ACC128'
1939
  MCK_ACC64, // register class 'ACC64'
1940
  MCK_CPURAReg, // register class 'CPURAReg,RA'
1941
  MCK_CPUSPReg, // register class 'CPUSPReg,SP32,SP'
1942
  MCK_DSPCC, // register class 'DSPCC'
1943
  MCK_GP32, // register class 'GP32'
1944
  MCK_GP64, // register class 'GP64'
1945
  MCK_GPR32ZERO, // register class 'GPR32ZERO,ZERO'
1946
  MCK_HI32, // register class 'HI32'
1947
  MCK_HI64, // register class 'HI64'
1948
  MCK_LO32, // register class 'LO32'
1949
  MCK_LO64, // register class 'LO64'
1950
  MCK_PC, // register class 'PC'
1951
  MCK_SP64, // register class 'SP64'
1952
  MCK_Reg32, // derived register class
1953
  MCK_Reg13, // derived register class
1954
  MCK_Reg33, // derived register class
1955
  MCK_Reg31, // derived register class
1956
  MCK_Reg30, // derived register class
1957
  MCK_Reg14, // derived register class
1958
  MCK_Reg11, // derived register class
1959
  MCK_GPRMM16MovePPairFirst, // register class 'GPRMM16MovePPairFirst'
1960
  MCK_OCTEON_MPL, // register class 'OCTEON_MPL'
1961
  MCK_OCTEON_P, // register class 'OCTEON_P'
1962
  MCK_Reg28, // derived register class
1963
  MCK_Reg23, // derived register class
1964
  MCK_Reg9, // derived register class
1965
  MCK_Reg4, // derived register class
1966
  MCK_ACC64DSP, // register class 'ACC64DSP'
1967
  MCK_HI32DSP, // register class 'HI32DSP'
1968
  MCK_LO32DSP, // register class 'LO32DSP'
1969
  MCK_Reg34, // derived register class
1970
  MCK_GPRMM16MovePPairSecond, // register class 'GPRMM16MovePPairSecond'
1971
  MCK_Reg29, // derived register class
1972
  MCK_Reg27, // derived register class
1973
  MCK_Reg10, // derived register class
1974
  MCK_Reg8, // derived register class
1975
  MCK_Reg44, // derived register class
1976
  MCK_Reg25, // derived register class
1977
  MCK_Reg22, // derived register class
1978
  MCK_Reg21, // derived register class
1979
  MCK_CPU16Regs, // register class 'CPU16Regs,GPRMM16'
1980
  MCK_FCC, // register class 'FCC'
1981
  MCK_GPRMM16MoveP, // register class 'GPRMM16MoveP'
1982
  MCK_GPRMM16Zero, // register class 'GPRMM16Zero'
1983
  MCK_MSACtrl, // register class 'MSACtrl'
1984
  MCK_Reg26, // derived register class
1985
  MCK_CPU16RegsPlusSP, // register class 'CPU16RegsPlusSP'
1986
  MCK_Reg50, // derived register class
1987
  MCK_Reg47, // derived register class
1988
  MCK_Reg42, // derived register class
1989
  MCK_Reg39, // derived register class
1990
  MCK_AFGR64, // register class 'AFGR64'
1991
  MCK_MSA128WEvens, // register class 'MSA128WEvens'
1992
  MCK_Reg45, // derived register class
1993
  MCK_Reg24, // derived register class
1994
  MCK_GPR32NONZERO, // register class 'GPR32NONZERO'
1995
  MCK_CCR, // register class 'CCR'
1996
  MCK_COP0, // register class 'COP0'
1997
  MCK_COP2, // register class 'COP2'
1998
  MCK_COP3, // register class 'COP3'
1999
  MCK_DSPR, // register class 'DSPR,GPR32'
2000
  MCK_FGR32, // register class 'FGR32,FGRCC'
2001
  MCK_FGR64, // register class 'FGR64'
2002
  MCK_FGRH32, // register class 'FGRH32'
2003
  MCK_GPR64, // register class 'GPR64'
2004
  MCK_HWRegs, // register class 'HWRegs'
2005
  MCK_MSA128F16, // register class 'MSA128F16,MSA128B,MSA128D,MSA128H,MSA128W'
2006
  MCK_OddSP, // register class 'OddSP'
2007
  MCK_LAST_REGISTER = MCK_OddSP,
2008
  MCK_ACC64DSPAsmReg, // user defined class 'ACC64DSPAsmOperand'
2009
  MCK_AFGR64AsmReg, // user defined class 'AFGR64AsmOperand'
2010
  MCK_CCRAsmReg, // user defined class 'CCRAsmOperand'
2011
  MCK_COP0AsmReg, // user defined class 'COP0AsmOperand'
2012
  MCK_COP2AsmReg, // user defined class 'COP2AsmOperand'
2013
  MCK_COP3AsmReg, // user defined class 'COP3AsmOperand'
2014
  MCK_FCCAsmReg, // user defined class 'FCCRegsAsmOperand'
2015
  MCK_FGR32AsmReg, // user defined class 'FGR32AsmOperand'
2016
  MCK_FGR64AsmReg, // user defined class 'FGR64AsmOperand'
2017
  MCK_FGRH32AsmReg, // user defined class 'FGRH32AsmOperand'
2018
  MCK_GPR32AsmReg, // user defined class 'GPR32AsmOperand'
2019
  MCK_GPR32NonZeroAsmReg, // user defined class 'GPR32NonZeroAsmOperand'
2020
  MCK_GPR32ZeroAsmReg, // user defined class 'GPR32ZeroAsmOperand'
2021
  MCK_GPR64AsmReg, // user defined class 'GPR64AsmOperand'
2022
  MCK_GPRMM16AsmReg, // user defined class 'GPRMM16AsmOperand'
2023
  MCK_GPRMM16AsmRegMoveP, // user defined class 'GPRMM16AsmOperandMoveP'
2024
  MCK_GPRMM16AsmRegMovePPairFirst, // user defined class 'GPRMM16AsmOperandMovePPairFirst'
2025
  MCK_GPRMM16AsmRegMovePPairSecond, // user defined class 'GPRMM16AsmOperandMovePPairSecond'
2026
  MCK_GPRMM16AsmRegZero, // user defined class 'GPRMM16AsmOperandZero'
2027
  MCK_HI32DSPAsmReg, // user defined class 'HI32DSPAsmOperand'
2028
  MCK_HWRegsAsmReg, // user defined class 'HWRegsAsmOperand'
2029
  MCK_Imm, // user defined class 'ImmAsmOperand'
2030
  MCK_LO32DSPAsmReg, // user defined class 'LO32DSPAsmOperand'
2031
  MCK_MSA128AsmReg, // user defined class 'MSA128AsmOperand'
2032
  MCK_MSACtrlAsmReg, // user defined class 'MSACtrlAsmOperand'
2033
  MCK_MicroMipsMemGP, // user defined class 'MicroMipsMemGPAsmOperand'
2034
  MCK_MicroMipsMem, // user defined class 'MicroMipsMemGPRMM16AsmOperand'
2035
  MCK_MicroMipsMemSP, // user defined class 'MicroMipsMemSPAsmOperand'
2036
  MCK_InvNum, // user defined class 'MipsInvertedImmoperand'
2037
  MCK_JumpTarget, // user defined class 'MipsJumpTargetAsmOperand'
2038
  MCK_MemOffsetSimm10, // user defined class 'MipsMemSimm10AsmOperand'
2039
  MCK_MemOffsetSimm10_1, // user defined class 'MipsMemSimm10Lsl1AsmOperand'
2040
  MCK_MemOffsetSimm10_2, // user defined class 'MipsMemSimm10Lsl2AsmOperand'
2041
  MCK_MemOffsetSimm10_3, // user defined class 'MipsMemSimm10Lsl3AsmOperand'
2042
  MCK_MemOffsetSimm11, // user defined class 'MipsMemSimm11AsmOperand'
2043
  MCK_MemOffsetSimm12, // user defined class 'MipsMemSimm12AsmOperand'
2044
  MCK_MemOffsetSimm16, // user defined class 'MipsMemSimm16AsmOperand'
2045
  MCK_MemOffsetSimm9, // user defined class 'MipsMemSimm9AsmOperand'
2046
  MCK_MemOffsetSimmPtr, // user defined class 'MipsMemSimmPtrAsmOperand'
2047
  MCK_MemOffsetUimm4, // user defined class 'MipsMemUimm4AsmOperand'
2048
  MCK_Mem, // user defined class 'MipsMemAsmOperand'
2049
  MCK_RegList16, // user defined class 'RegList16AsmOperand'
2050
  MCK_RegList, // user defined class 'RegListAsmOperand'
2051
  MCK_Simm19_Lsl2, // user defined class 'Simm19Lsl2AsmOperand'
2052
  MCK_StrictlyAFGR64AsmReg, // user defined class 'StrictlyAFGR64AsmOperand'
2053
  MCK_StrictlyFGR32AsmReg, // user defined class 'StrictlyFGR32AsmOperand'
2054
  MCK_StrictlyFGR64AsmReg, // user defined class 'StrictlyFGR64AsmOperand'
2055
  MCK_ConstantImmz, // user defined class 'ConstantImmzAsmOperandClass'
2056
  MCK_ConstantUImm1_0, // user defined class 'ConstantUImm1AsmOperandClass'
2057
  MCK_ConstantUImm2_0, // user defined class 'ConstantUImm2AsmOperandClass'
2058
  MCK_ConstantUImm2_1, // user defined class 'ConstantUImm2Plus1AsmOperandClass'
2059
  MCK_ConstantUImm3_0, // user defined class 'ConstantUImm3AsmOperandClass'
2060
  MCK_ConstantSImm4_0, // user defined class 'ConstantSImm4AsmOperandClass'
2061
  MCK_ConstantUImm4_0, // user defined class 'ConstantUImm4AsmOperandClass'
2062
  MCK_ConstantSImm5_0, // user defined class 'ConstantSImm5AsmOperandClass'
2063
  MCK_ConstantUImm5_0, // user defined class 'ConstantUImm5AsmOperandClass'
2064
  MCK_ConstantUImm5_1, // user defined class 'ConstantUImm5Plus1AsmOperandClass'
2065
  MCK_ConstantUImm5_Plus1_Report_UImm6, // user defined class 'ConstantUImm5Plus1ReportUImm6AsmOperandClass'
2066
  MCK_ConstantUImm5_32_Norm, // user defined class 'ConstantUImm5Plus32NormalizeAsmOperandClass'
2067
  MCK_ConstantUImm5_32, // user defined class 'ConstantUImm5Plus32AsmOperandClass'
2068
  MCK_ConstantUImm5_0_Report_UImm6, // user defined class 'ConstantUImm5ReportUImm6AsmOperandClass'
2069
  MCK_ConstantUImm5_33, // user defined class 'ConstantUImm5Plus33AsmOperandClass'
2070
  MCK_ConstantUImmRange2_64, // user defined class 'ConstantUImm5_Range2_64AsmOperandClass'
2071
  MCK_UImm5Lsl2, // user defined class 'ConstantUImm5Lsl2AsmOperandClass'
2072
  MCK_ConstantSImm6_0, // user defined class 'ConstantSImm6AsmOperandClass'
2073
  MCK_ConstantUImm6_0, // user defined class 'ConstantUImm6AsmOperandClass'
2074
  MCK_UImm6Lsl2, // user defined class 'ConstantUImm6Lsl2AsmOperandClass'
2075
  MCK_ConstantUImm7_0, // user defined class 'ConstantUImm7AsmOperandClass'
2076
  MCK_UImm7_N1, // user defined class 'ConstantUImm7Sub1AsmOperandClass'
2077
  MCK_ConstantUImm8_0, // user defined class 'ConstantUImm8AsmOperandClass'
2078
  MCK_SImm7Lsl2, // user defined class 'ConstantSImm7Lsl2AsmOperandClass'
2079
  MCK_ConstantSImm9_0, // user defined class 'ConstantSImm9AsmOperandClass'
2080
  MCK_ConstantSImm10_0, // user defined class 'ConstantSImm10AsmOperandClass'
2081
  MCK_ConstantUImm10_0, // user defined class 'ConstantUImm10AsmOperandClass'
2082
  MCK_SImm10Lsl1, // user defined class 'ConstantSImm10Lsl1AsmOperandClass'
2083
  MCK_ConstantSImm11_0, // user defined class 'ConstantSImm11AsmOperandClass'
2084
  MCK_SImm10Lsl2, // user defined class 'ConstantSImm10Lsl2AsmOperandClass'
2085
  MCK_SImm10Lsl3, // user defined class 'ConstantSImm10Lsl3AsmOperandClass'
2086
  MCK_SImm16, // user defined class 'SImm16AsmOperandClass'
2087
  MCK_SImm16_Relaxed, // user defined class 'SImm16RelaxedAsmOperandClass'
2088
  MCK_UImm16_AltRelaxed, // user defined class 'UImm16AltRelaxedAsmOperandClass'
2089
  MCK_UImm16, // user defined class 'UImm16AsmOperandClass'
2090
  MCK_SImm19Lsl2, // user defined class 'ConstantSImm19Lsl2AsmOperandClass'
2091
  MCK_UImm16_Relaxed, // user defined class 'UImm16RelaxedAsmOperandClass'
2092
  MCK_ConstantUImm20_0, // user defined class 'ConstantUImm20AsmOperandClass'
2093
  MCK_ConstantUImm26_0, // user defined class 'ConstantUImm26AsmOperandClass'
2094
  MCK_SImm32, // user defined class 'SImm32AsmOperandClass'
2095
  MCK_SImm32_Relaxed, // user defined class 'SImm32RelaxedAsmOperandClass'
2096
  MCK_UImm32_Coerced, // user defined class 'UImm32CoercedAsmOperandClass'
2097
  NumMatchClassKinds
2098
};
2099
2100
}
2101
2102
14.4k
static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
2103
14.4k
  return MCTargetAsmParser::Match_InvalidOperand;
2104
14.4k
}
2105
2106
880
static MatchClassKind matchTokenString(StringRef Name) {
2107
880
  switch (Name.size()) {
2108
880
  
default: break0
;
2109
880
  case 1:  // 6 strings to match.
2110
880
    switch (Name[0]) {
2111
880
    
default: break0
;
2112
880
    case '#':  // 1 string to match.
2113
0
      return MCK__35_;  // "#"
2114
880
    case '(':  // 1 string to match.
2115
363
      return MCK__40_;  // "("
2116
880
    case ')':  // 1 string to match.
2117
363
      return MCK__41_;  // ")"
2118
880
    case '0':  // 1 string to match.
2119
0
      return MCK_0;  // "0"
2120
880
    case '[':  // 1 string to match.
2121
112
      return MCK__91_;  // "["
2122
880
    case ']':  // 1 string to match.
2123
42
      return MCK__93_;  // "]"
2124
0
    }
2125
0
    break;
2126
0
  case 2:  // 1 string to match.
2127
0
    if (memcmp(Name.data()+0, "16", 2) != 0)
2128
0
      break;
2129
0
    return MCK_16;   // "16"
2130
0
  case 3:  // 1 string to match.
2131
0
    if (memcmp(Name.data()+0, "bit", 3) != 0)
2132
0
      break;
2133
0
    return MCK_bit;  // "bit"
2134
0
  case 4:  // 1 string to match.
2135
0
    if (memcmp(Name.data()+0, "inst", 4) != 0)
2136
0
      break;
2137
0
    return MCK_inst;  // "inst"
2138
0
  }
2139
0
  return InvalidMatchClass;
2140
0
}
2141
2142
/// isSubclass - Compute whether \p A is a subclass of \p B.
2143
39.7k
static bool isSubclass(MatchClassKind A, MatchClassKind B) {
2144
39.7k
  if (A == B)
2145
1.00k
    return true;
2146
38.7k
2147
38.7k
  switch (A) {
2148
38.7k
  default:
2149
24.2k
    return false;
2150
38.7k
2151
38.7k
  case MCK_Reg37:
2152
0
    switch (B) {
2153
0
    default: return false;
2154
0
    case MCK_Reg24: return true;
2155
0
    case MCK_GPR64: return true;
2156
0
    }
2157
0
2158
0
  case MCK_Reg19:
2159
0
    switch (B) {
2160
0
    default: return false;
2161
0
    case MCK_Reg23: return true;
2162
0
    case MCK_Reg22: return true;
2163
0
    case MCK_Reg21: return true;
2164
0
    case MCK_GPR64: return true;
2165
0
    }
2166
0
2167
0
  case MCK_ACC64:
2168
0
    return B == MCK_ACC64DSP;
2169
0
2170
133
  case MCK_CPURAReg:
2171
133
    switch (B) {
2172
133
    default: return false;
2173
133
    
case MCK_GPR32NONZERO: return true0
;
2174
133
    
case MCK_DSPR: return true0
;
2175
0
    }
2176
0
2177
551
  case MCK_CPUSPReg:
2178
551
    switch (B) {
2179
551
    default: return false;
2180
551
    
case MCK_CPU16RegsPlusSP: return true0
;
2181
551
    
case MCK_GPR32NONZERO: return true0
;
2182
551
    
case MCK_DSPR: return true0
;
2183
0
    }
2184
0
2185
0
  case MCK_GP32:
2186
0
    switch (B) {
2187
0
    default: return false;
2188
0
    case MCK_GPR32NONZERO: return true;
2189
0
    case MCK_DSPR: return true;
2190
0
    }
2191
0
2192
0
  case MCK_GP64:
2193
0
    switch (B) {
2194
0
    default: return false;
2195
0
    case MCK_Reg24: return true;
2196
0
    case MCK_GPR64: return true;
2197
0
    }
2198
0
2199
351
  case MCK_GPR32ZERO:
2200
351
    switch (B) {
2201
351
    default: return false;
2202
351
    
case MCK_Reg4: return true0
;
2203
351
    
case MCK_GPRMM16MoveP: return true0
;
2204
351
    
case MCK_GPRMM16Zero: return true0
;
2205
351
    
case MCK_DSPR: return true0
;
2206
0
    }
2207
0
2208
0
  case MCK_HI32:
2209
0
    return B == MCK_HI32DSP;
2210
0
2211
0
  case MCK_LO32:
2212
0
    return B == MCK_LO32DSP;
2213
0
2214
0
  case MCK_SP64:
2215
0
    switch (B) {
2216
0
    default: return false;
2217
0
    case MCK_Reg26: return true;
2218
0
    case MCK_Reg24: return true;
2219
0
    case MCK_GPR64: return true;
2220
0
    }
2221
0
2222
0
  case MCK_Reg32:
2223
0
    switch (B) {
2224
0
    default: return false;
2225
0
    case MCK_Reg33: return true;
2226
0
    case MCK_Reg31: return true;
2227
0
    case MCK_Reg34: return true;
2228
0
    case MCK_Reg27: return true;
2229
0
    case MCK_Reg25: return true;
2230
0
    case MCK_Reg21: return true;
2231
0
    case MCK_Reg26: return true;
2232
0
    case MCK_Reg24: return true;
2233
0
    case MCK_GPR64: return true;
2234
0
    }
2235
0
2236
0
  case MCK_Reg13:
2237
0
    switch (B) {
2238
0
    default: return false;
2239
0
    case MCK_Reg14: return true;
2240
0
    case MCK_GPRMM16MovePPairFirst: return true;
2241
0
    case MCK_GPRMM16MovePPairSecond: return true;
2242
0
    case MCK_Reg8: return true;
2243
0
    case MCK_CPU16Regs: return true;
2244
0
    case MCK_GPRMM16Zero: return true;
2245
0
    case MCK_CPU16RegsPlusSP: return true;
2246
0
    case MCK_GPR32NONZERO: return true;
2247
0
    case MCK_DSPR: return true;
2248
0
    }
2249
0
2250
0
  case MCK_Reg33:
2251
0
    switch (B) {
2252
0
    default: return false;
2253
0
    case MCK_Reg34: return true;
2254
0
    case MCK_Reg27: return true;
2255
0
    case MCK_Reg25: return true;
2256
0
    case MCK_Reg21: return true;
2257
0
    case MCK_Reg26: return true;
2258
0
    case MCK_Reg24: return true;
2259
0
    case MCK_GPR64: return true;
2260
0
    }
2261
0
2262
0
  case MCK_Reg31:
2263
0
    switch (B) {
2264
0
    default: return false;
2265
0
    case MCK_Reg27: return true;
2266
0
    case MCK_Reg25: return true;
2267
0
    case MCK_Reg21: return true;
2268
0
    case MCK_Reg26: return true;
2269
0
    case MCK_Reg24: return true;
2270
0
    case MCK_GPR64: return true;
2271
0
    }
2272
0
2273
0
  case MCK_Reg30:
2274
0
    switch (B) {
2275
0
    default: return false;
2276
0
    case MCK_Reg28: return true;
2277
0
    case MCK_Reg23: return true;
2278
0
    case MCK_Reg29: return true;
2279
0
    case MCK_Reg27: return true;
2280
0
    case MCK_Reg25: return true;
2281
0
    case MCK_Reg22: return true;
2282
0
    case MCK_Reg21: return true;
2283
0
    case MCK_Reg26: return true;
2284
0
    case MCK_Reg24: return true;
2285
0
    case MCK_GPR64: return true;
2286
0
    }
2287
0
2288
0
  case MCK_Reg14:
2289
0
    switch (B) {
2290
0
    default: return false;
2291
0
    case MCK_GPRMM16MovePPairSecond: return true;
2292
0
    case MCK_Reg8: return true;
2293
0
    case MCK_CPU16Regs: return true;
2294
0
    case MCK_GPRMM16Zero: return true;
2295
0
    case MCK_CPU16RegsPlusSP: return true;
2296
0
    case MCK_GPR32NONZERO: return true;
2297
0
    case MCK_DSPR: return true;
2298
0
    }
2299
0
2300
0
  case MCK_Reg11:
2301
0
    switch (B) {
2302
0
    default: return false;
2303
0
    case MCK_Reg9: return true;
2304
0
    case MCK_Reg4: return true;
2305
0
    case MCK_Reg10: return true;
2306
0
    case MCK_Reg8: return true;
2307
0
    case MCK_CPU16Regs: return true;
2308
0
    case MCK_GPRMM16MoveP: return true;
2309
0
    case MCK_GPRMM16Zero: return true;
2310
0
    case MCK_CPU16RegsPlusSP: return true;
2311
0
    case MCK_GPR32NONZERO: return true;
2312
0
    case MCK_DSPR: return true;
2313
0
    }
2314
0
2315
0
  case MCK_GPRMM16MovePPairFirst:
2316
0
    switch (B) {
2317
0
    default: return false;
2318
0
    case MCK_Reg8: return true;
2319
0
    case MCK_CPU16Regs: return true;
2320
0
    case MCK_GPRMM16Zero: return true;
2321
0
    case MCK_CPU16RegsPlusSP: return true;
2322
0
    case MCK_GPR32NONZERO: return true;
2323
0
    case MCK_DSPR: return true;
2324
0
    }
2325
0
2326
0
  case MCK_Reg28:
2327
0
    switch (B) {
2328
0
    default: return false;
2329
0
    case MCK_Reg29: return true;
2330
0
    case MCK_Reg25: return true;
2331
0
    case MCK_Reg22: return true;
2332
0
    case MCK_Reg26: return true;
2333
0
    case MCK_Reg24: return true;
2334
0
    case MCK_GPR64: return true;
2335
0
    }
2336
0
2337
0
  case MCK_Reg23:
2338
0
    switch (B) {
2339
0
    default: return false;
2340
0
    case MCK_Reg22: return true;
2341
0
    case MCK_Reg21: return true;
2342
0
    case MCK_GPR64: return true;
2343
0
    }
2344
0
2345
0
  case MCK_Reg9:
2346
0
    switch (B) {
2347
0
    default: return false;
2348
0
    case MCK_Reg10: return true;
2349
0
    case MCK_CPU16Regs: return true;
2350
0
    case MCK_GPRMM16MoveP: return true;
2351
0
    case MCK_CPU16RegsPlusSP: return true;
2352
0
    case MCK_GPR32NONZERO: return true;
2353
0
    case MCK_DSPR: return true;
2354
0
    }
2355
0
2356
0
  case MCK_Reg4:
2357
0
    switch (B) {
2358
0
    default: return false;
2359
0
    case MCK_GPRMM16MoveP: return true;
2360
0
    case MCK_GPRMM16Zero: return true;
2361
0
    case MCK_DSPR: return true;
2362
0
    }
2363
0
2364
0
  case MCK_Reg34:
2365
0
    switch (B) {
2366
0
    default: return false;
2367
0
    case MCK_Reg24: return true;
2368
0
    case MCK_GPR64: return true;
2369
0
    }
2370
0
2371
0
  case MCK_GPRMM16MovePPairSecond:
2372
0
    switch (B) {
2373
0
    default: return false;
2374
0
    case MCK_GPR32NONZERO: return true;
2375
0
    case MCK_DSPR: return true;
2376
0
    }
2377
0
2378
0
  case MCK_Reg29:
2379
0
    switch (B) {
2380
0
    default: return false;
2381
0
    case MCK_Reg22: return true;
2382
0
    case MCK_Reg24: return true;
2383
0
    case MCK_GPR64: return true;
2384
0
    }
2385
0
2386
0
  case MCK_Reg27:
2387
0
    switch (B) {
2388
0
    default: return false;
2389
0
    case MCK_Reg25: return true;
2390
0
    case MCK_Reg21: return true;
2391
0
    case MCK_Reg26: return true;
2392
0
    case MCK_Reg24: return true;
2393
0
    case MCK_GPR64: return true;
2394
0
    }
2395
0
2396
0
  case MCK_Reg10:
2397
0
    switch (B) {
2398
0
    default: return false;
2399
0
    case MCK_GPRMM16MoveP: return true;
2400
0
    case MCK_GPR32NONZERO: return true;
2401
0
    case MCK_DSPR: return true;
2402
0
    }
2403
0
2404
0
  case MCK_Reg8:
2405
0
    switch (B) {
2406
0
    default: return false;
2407
0
    case MCK_CPU16Regs: return true;
2408
0
    case MCK_GPRMM16Zero: return true;
2409
0
    case MCK_CPU16RegsPlusSP: return true;
2410
0
    case MCK_GPR32NONZERO: return true;
2411
0
    case MCK_DSPR: return true;
2412
0
    }
2413
0
2414
0
  case MCK_Reg44:
2415
0
    switch (B) {
2416
0
    default: return false;
2417
0
    case MCK_AFGR64: return true;
2418
0
    case MCK_Reg45: return true;
2419
0
    case MCK_OddSP: return true;
2420
0
    }
2421
0
2422
0
  case MCK_Reg25:
2423
0
    switch (B) {
2424
0
    default: return false;
2425
0
    case MCK_Reg26: return true;
2426
0
    case MCK_Reg24: return true;
2427
0
    case MCK_GPR64: return true;
2428
0
    }
2429
0
2430
0
  case MCK_Reg22:
2431
0
    return B == MCK_GPR64;
2432
0
2433
0
  case MCK_Reg21:
2434
0
    return B == MCK_GPR64;
2435
0
2436
13.3k
  case MCK_CPU16Regs:
2437
13.3k
    switch (B) {
2438
13.3k
    default: return false;
2439
13.3k
    
case MCK_CPU16RegsPlusSP: return true0
;
2440
13.3k
    
case MCK_GPR32NONZERO: return true0
;
2441
13.3k
    
case MCK_DSPR: return true0
;
2442
0
    }
2443
0
2444
0
  case MCK_GPRMM16MoveP:
2445
0
    return B == MCK_DSPR;
2446
0
2447
0
  case MCK_GPRMM16Zero:
2448
0
    return B == MCK_DSPR;
2449
0
2450
0
  case MCK_Reg26:
2451
0
    switch (B) {
2452
0
    default: return false;
2453
0
    case MCK_Reg24: return true;
2454
0
    case MCK_GPR64: return true;
2455
0
    }
2456
0
2457
0
  case MCK_CPU16RegsPlusSP:
2458
0
    switch (B) {
2459
0
    default: return false;
2460
0
    case MCK_GPR32NONZERO: return true;
2461
0
    case MCK_DSPR: return true;
2462
0
    }
2463
0
2464
0
  case MCK_Reg50:
2465
0
    return B == MCK_MSA128F16;
2466
0
2467
0
  case MCK_Reg47:
2468
0
    switch (B) {
2469
0
    default: return false;
2470
0
    case MCK_Reg45: return true;
2471
0
    case MCK_FGR64: return true;
2472
0
    case MCK_OddSP: return true;
2473
0
    }
2474
0
2475
0
  case MCK_Reg42:
2476
0
    switch (B) {
2477
0
    default: return false;
2478
0
    case MCK_FGRH32: return true;
2479
0
    case MCK_OddSP: return true;
2480
0
    }
2481
0
2482
0
  case MCK_Reg39:
2483
0
    switch (B) {
2484
0
    default: return false;
2485
0
    case MCK_FGR32: return true;
2486
0
    case MCK_OddSP: return true;
2487
0
    }
2488
0
2489
0
  case MCK_MSA128WEvens:
2490
0
    return B == MCK_MSA128F16;
2491
0
2492
0
  case MCK_Reg45:
2493
0
    return B == MCK_OddSP;
2494
0
2495
0
  case MCK_Reg24:
2496
0
    return B == MCK_GPR64;
2497
0
2498
0
  case MCK_GPR32NONZERO:
2499
0
    return B == MCK_DSPR;
2500
0
2501
0
  case MCK_MemOffsetSimm10:
2502
0
    return B == MCK_Mem;
2503
0
2504
0
  case MCK_MemOffsetSimm10_1:
2505
0
    return B == MCK_Mem;
2506
0
2507
0
  case MCK_MemOffsetSimm10_2:
2508
0
    return B == MCK_Mem;
2509
0
2510
0
  case MCK_MemOffsetSimm10_3:
2511
0
    return B == MCK_Mem;
2512
0
2513
0
  case MCK_MemOffsetSimm11:
2514
0
    return B == MCK_Mem;
2515
0
2516
0
  case MCK_MemOffsetSimm12:
2517
0
    return B == MCK_Mem;
2518
0
2519
0
  case MCK_MemOffsetSimm16:
2520
0
    return B == MCK_Mem;
2521
0
2522
0
  case MCK_MemOffsetSimm9:
2523
0
    return B == MCK_Mem;
2524
0
2525
0
  case MCK_MemOffsetSimmPtr:
2526
0
    return B == MCK_Mem;
2527
0
2528
8
  case MCK_MemOffsetUimm4:
2529
8
    return B == MCK_Mem;
2530
0
2531
0
  case MCK_ConstantImmz:
2532
0
    switch (B) {
2533
0
    default: return false;
2534
0
    case MCK_ConstantUImm1_0: return true;
2535
0
    case MCK_ConstantUImm2_0: return true;
2536
0
    case MCK_ConstantUImm3_0: return true;
2537
0
    case MCK_ConstantSImm4_0: return true;
2538
0
    case MCK_ConstantUImm4_0: return true;
2539
0
    case MCK_ConstantSImm5_0: return true;
2540
0
    case MCK_ConstantUImm5_0: return true;
2541
0
    case MCK_ConstantUImm5_1: return true;
2542
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2543
0
    case MCK_ConstantUImm5_32_Norm: return true;
2544
0
    case MCK_ConstantUImm5_32: return true;
2545
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2546
0
    case MCK_ConstantUImm5_33: return true;
2547
0
    case MCK_ConstantUImmRange2_64: return true;
2548
0
    case MCK_UImm5Lsl2: return true;
2549
0
    case MCK_ConstantSImm6_0: return true;
2550
0
    case MCK_ConstantUImm6_0: return true;
2551
0
    case MCK_UImm6Lsl2: return true;
2552
0
    case MCK_ConstantUImm7_0: return true;
2553
0
    case MCK_UImm7_N1: return true;
2554
0
    case MCK_ConstantUImm8_0: return true;
2555
0
    case MCK_SImm7Lsl2: return true;
2556
0
    case MCK_ConstantSImm9_0: return true;
2557
0
    case MCK_ConstantSImm10_0: return true;
2558
0
    case MCK_ConstantUImm10_0: return true;
2559
0
    case MCK_SImm10Lsl1: return true;
2560
0
    case MCK_ConstantSImm11_0: return true;
2561
0
    case MCK_SImm10Lsl2: return true;
2562
0
    case MCK_SImm10Lsl3: return true;
2563
0
    case MCK_SImm16: return true;
2564
0
    case MCK_SImm16_Relaxed: return true;
2565
0
    case MCK_UImm16_Relaxed: return true;
2566
0
    case MCK_ConstantUImm20_0: return true;
2567
0
    case MCK_ConstantUImm26_0: return true;
2568
0
    case MCK_SImm32: return true;
2569
0
    case MCK_SImm32_Relaxed: return true;
2570
0
    case MCK_UImm32_Coerced: return true;
2571
0
    }
2572
0
2573
0
  case MCK_ConstantUImm1_0:
2574
0
    switch (B) {
2575
0
    default: return false;
2576
0
    case MCK_ConstantUImm2_0: return true;
2577
0
    case MCK_ConstantUImm3_0: return true;
2578
0
    case MCK_ConstantSImm4_0: return true;
2579
0
    case MCK_ConstantUImm4_0: return true;
2580
0
    case MCK_ConstantSImm5_0: return true;
2581
0
    case MCK_ConstantUImm5_0: return true;
2582
0
    case MCK_ConstantUImm5_1: return true;
2583
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2584
0
    case MCK_ConstantUImm5_32_Norm: return true;
2585
0
    case MCK_ConstantUImm5_32: return true;
2586
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2587
0
    case MCK_ConstantUImm5_33: return true;
2588
0
    case MCK_ConstantUImmRange2_64: return true;
2589
0
    case MCK_UImm5Lsl2: return true;
2590
0
    case MCK_ConstantSImm6_0: return true;
2591
0
    case MCK_ConstantUImm6_0: return true;
2592
0
    case MCK_UImm6Lsl2: return true;
2593
0
    case MCK_ConstantUImm7_0: return true;
2594
0
    case MCK_UImm7_N1: return true;
2595
0
    case MCK_ConstantUImm8_0: return true;
2596
0
    case MCK_SImm7Lsl2: return true;
2597
0
    case MCK_ConstantSImm9_0: return true;
2598
0
    case MCK_ConstantSImm10_0: return true;
2599
0
    case MCK_ConstantUImm10_0: return true;
2600
0
    case MCK_SImm10Lsl1: return true;
2601
0
    case MCK_ConstantSImm11_0: return true;
2602
0
    case MCK_SImm10Lsl2: return true;
2603
0
    case MCK_SImm10Lsl3: return true;
2604
0
    case MCK_SImm16: return true;
2605
0
    case MCK_SImm16_Relaxed: return true;
2606
0
    case MCK_UImm16_Relaxed: return true;
2607
0
    case MCK_ConstantUImm20_0: return true;
2608
0
    case MCK_ConstantUImm26_0: return true;
2609
0
    case MCK_SImm32: return true;
2610
0
    case MCK_SImm32_Relaxed: return true;
2611
0
    case MCK_UImm32_Coerced: return true;
2612
0
    }
2613
0
2614
6
  case MCK_ConstantUImm2_0:
2615
6
    switch (B) {
2616
6
    default: return false;
2617
6
    
case MCK_ConstantUImm3_0: return true0
;
2618
6
    
case MCK_ConstantSImm4_0: return true0
;
2619
6
    
case MCK_ConstantUImm4_0: return true0
;
2620
6
    
case MCK_ConstantSImm5_0: return true0
;
2621
6
    
case MCK_ConstantUImm5_0: return true0
;
2622
6
    
case MCK_ConstantUImm5_1: return true0
;
2623
6
    
case MCK_ConstantUImm5_Plus1_Report_UImm6: return true0
;
2624
6
    
case MCK_ConstantUImm5_32_Norm: return true0
;
2625
6
    
case MCK_ConstantUImm5_32: return true0
;
2626
6
    
case MCK_ConstantUImm5_0_Report_UImm6: return true0
;
2627
6
    
case MCK_ConstantUImm5_33: return true0
;
2628
6
    
case MCK_ConstantUImmRange2_64: return true0
;
2629
6
    
case MCK_UImm5Lsl2: return true0
;
2630
6
    
case MCK_ConstantSImm6_0: return true0
;
2631
6
    
case MCK_ConstantUImm6_0: return true0
;
2632
6
    
case MCK_UImm6Lsl2: return true0
;
2633
6
    
case MCK_ConstantUImm7_0: return true0
;
2634
6
    
case MCK_UImm7_N1: return true0
;
2635
6
    
case MCK_ConstantUImm8_0: return true0
;
2636
6
    
case MCK_SImm7Lsl2: return true0
;
2637
6
    
case MCK_ConstantSImm9_0: return true0
;
2638
6
    
case MCK_ConstantSImm10_0: return true0
;
2639
6
    
case MCK_ConstantUImm10_0: return true0
;
2640
6
    
case MCK_SImm10Lsl1: return true0
;
2641
6
    
case MCK_ConstantSImm11_0: return true0
;
2642
6
    
case MCK_SImm10Lsl2: return true0
;
2643
6
    
case MCK_SImm10Lsl3: return true0
;
2644
6
    
case MCK_SImm16: return true0
;
2645
6
    
case MCK_SImm16_Relaxed: return true0
;
2646
6
    
case MCK_UImm16_Relaxed: return true0
;
2647
6
    
case MCK_ConstantUImm20_0: return true0
;
2648
6
    
case MCK_ConstantUImm26_0: return true0
;
2649
6
    
case MCK_SImm32: return true0
;
2650
6
    
case MCK_SImm32_Relaxed: return true0
;
2651
6
    
case MCK_UImm32_Coerced: return true0
;
2652
0
    }
2653
0
2654
0
  case MCK_ConstantUImm2_1:
2655
0
    switch (B) {
2656
0
    default: return false;
2657
0
    case MCK_ConstantUImm3_0: return true;
2658
0
    case MCK_ConstantSImm4_0: return true;
2659
0
    case MCK_ConstantUImm4_0: return true;
2660
0
    case MCK_ConstantSImm5_0: return true;
2661
0
    case MCK_ConstantUImm5_0: return true;
2662
0
    case MCK_ConstantUImm5_1: return true;
2663
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2664
0
    case MCK_ConstantUImm5_32_Norm: return true;
2665
0
    case MCK_ConstantUImm5_32: return true;
2666
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2667
0
    case MCK_ConstantUImm5_33: return true;
2668
0
    case MCK_ConstantUImmRange2_64: return true;
2669
0
    case MCK_UImm5Lsl2: return true;
2670
0
    case MCK_ConstantSImm6_0: return true;
2671
0
    case MCK_ConstantUImm6_0: return true;
2672
0
    case MCK_UImm6Lsl2: return true;
2673
0
    case MCK_ConstantUImm7_0: return true;
2674
0
    case MCK_UImm7_N1: return true;
2675
0
    case MCK_ConstantUImm8_0: return true;
2676
0
    case MCK_SImm7Lsl2: return true;
2677
0
    case MCK_ConstantSImm9_0: return true;
2678
0
    case MCK_ConstantSImm10_0: return true;
2679
0
    case MCK_ConstantUImm10_0: return true;
2680
0
    case MCK_SImm10Lsl1: return true;
2681
0
    case MCK_ConstantSImm11_0: return true;
2682
0
    case MCK_SImm10Lsl2: return true;
2683
0
    case MCK_SImm10Lsl3: return true;
2684
0
    case MCK_SImm16: return true;
2685
0
    case MCK_SImm16_Relaxed: return true;
2686
0
    case MCK_UImm16_Relaxed: return true;
2687
0
    case MCK_ConstantUImm20_0: return true;
2688
0
    case MCK_ConstantUImm26_0: return true;
2689
0
    case MCK_SImm32: return true;
2690
0
    case MCK_SImm32_Relaxed: return true;
2691
0
    case MCK_UImm32_Coerced: return true;
2692
0
    }
2693
0
2694
0
  case MCK_ConstantUImm3_0:
2695
0
    switch (B) {
2696
0
    default: return false;
2697
0
    case MCK_ConstantSImm4_0: return true;
2698
0
    case MCK_ConstantUImm4_0: return true;
2699
0
    case MCK_ConstantSImm5_0: return true;
2700
0
    case MCK_ConstantUImm5_0: return true;
2701
0
    case MCK_ConstantUImm5_1: return true;
2702
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2703
0
    case MCK_ConstantUImm5_32_Norm: return true;
2704
0
    case MCK_ConstantUImm5_32: return true;
2705
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2706
0
    case MCK_ConstantUImm5_33: return true;
2707
0
    case MCK_ConstantUImmRange2_64: return true;
2708
0
    case MCK_UImm5Lsl2: return true;
2709
0
    case MCK_ConstantSImm6_0: return true;
2710
0
    case MCK_ConstantUImm6_0: return true;
2711
0
    case MCK_UImm6Lsl2: return true;
2712
0
    case MCK_ConstantUImm7_0: return true;
2713
0
    case MCK_UImm7_N1: return true;
2714
0
    case MCK_ConstantUImm8_0: return true;
2715
0
    case MCK_SImm7Lsl2: return true;
2716
0
    case MCK_ConstantSImm9_0: return true;
2717
0
    case MCK_ConstantSImm10_0: return true;
2718
0
    case MCK_ConstantUImm10_0: return true;
2719
0
    case MCK_SImm10Lsl1: return true;
2720
0
    case MCK_ConstantSImm11_0: return true;
2721
0
    case MCK_SImm10Lsl2: return true;
2722
0
    case MCK_SImm10Lsl3: return true;
2723
0
    case MCK_SImm16: return true;
2724
0
    case MCK_SImm16_Relaxed: return true;
2725
0
    case MCK_UImm16_Relaxed: return true;
2726
0
    case MCK_ConstantUImm20_0: return true;
2727
0
    case MCK_ConstantUImm26_0: return true;
2728
0
    case MCK_SImm32: return true;
2729
0
    case MCK_SImm32_Relaxed: return true;
2730
0
    case MCK_UImm32_Coerced: return true;
2731
0
    }
2732
0
2733
0
  case MCK_ConstantSImm4_0:
2734
0
    switch (B) {
2735
0
    default: return false;
2736
0
    case MCK_ConstantUImm4_0: return true;
2737
0
    case MCK_ConstantSImm5_0: return true;
2738
0
    case MCK_ConstantUImm5_0: return true;
2739
0
    case MCK_ConstantUImm5_1: return true;
2740
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2741
0
    case MCK_ConstantUImm5_32_Norm: return true;
2742
0
    case MCK_ConstantUImm5_32: return true;
2743
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2744
0
    case MCK_ConstantUImm5_33: return true;
2745
0
    case MCK_ConstantUImmRange2_64: return true;
2746
0
    case MCK_UImm5Lsl2: return true;
2747
0
    case MCK_ConstantSImm6_0: return true;
2748
0
    case MCK_ConstantUImm6_0: return true;
2749
0
    case MCK_UImm6Lsl2: return true;
2750
0
    case MCK_ConstantUImm7_0: return true;
2751
0
    case MCK_UImm7_N1: return true;
2752
0
    case MCK_ConstantUImm8_0: return true;
2753
0
    case MCK_SImm7Lsl2: return true;
2754
0
    case MCK_ConstantSImm9_0: return true;
2755
0
    case MCK_ConstantSImm10_0: return true;
2756
0
    case MCK_ConstantUImm10_0: return true;
2757
0
    case MCK_SImm10Lsl1: return true;
2758
0
    case MCK_ConstantSImm11_0: return true;
2759
0
    case MCK_SImm10Lsl2: return true;
2760
0
    case MCK_SImm10Lsl3: return true;
2761
0
    case MCK_SImm16: return true;
2762
0
    case MCK_SImm16_Relaxed: return true;
2763
0
    case MCK_UImm16_Relaxed: return true;
2764
0
    case MCK_ConstantUImm20_0: return true;
2765
0
    case MCK_ConstantUImm26_0: return true;
2766
0
    case MCK_SImm32: return true;
2767
0
    case MCK_SImm32_Relaxed: return true;
2768
0
    case MCK_UImm32_Coerced: return true;
2769
0
    }
2770
0
2771
6
  case MCK_ConstantUImm4_0:
2772
6
    switch (B) {
2773
6
    default: return false;
2774
6
    
case MCK_ConstantSImm5_0: return true0
;
2775
6
    
case MCK_ConstantUImm5_0: return true0
;
2776
6
    
case MCK_ConstantUImm5_1: return true0
;
2777
6
    
case MCK_ConstantUImm5_Plus1_Report_UImm6: return true0
;
2778
6
    
case MCK_ConstantUImm5_32_Norm: return true0
;
2779
6
    
case MCK_ConstantUImm5_32: return true0
;
2780
6
    
case MCK_ConstantUImm5_0_Report_UImm6: return true0
;
2781
6
    
case MCK_ConstantUImm5_33: return true0
;
2782
6
    
case MCK_ConstantUImmRange2_64: return true0
;
2783
6
    
case MCK_UImm5Lsl2: return true0
;
2784
6
    
case MCK_ConstantSImm6_0: return true0
;
2785
6
    
case MCK_ConstantUImm6_0: return true0
;
2786
6
    
case MCK_UImm6Lsl2: return true0
;
2787
6
    
case MCK_ConstantUImm7_0: return true0
;
2788
6
    
case MCK_UImm7_N1: return true0
;
2789
6
    
case MCK_ConstantUImm8_0: return true0
;
2790
6
    
case MCK_SImm7Lsl2: return true0
;
2791
6
    
case MCK_ConstantSImm9_0: return true0
;
2792
6
    
case MCK_ConstantSImm10_0: return true0
;
2793
6
    
case MCK_ConstantUImm10_0: return true0
;
2794
6
    
case MCK_SImm10Lsl1: return true0
;
2795
6
    
case MCK_ConstantSImm11_0: return true0
;
2796
6
    
case MCK_SImm10Lsl2: return true0
;
2797
6
    
case MCK_SImm10Lsl3: return true0
;
2798
6
    
case MCK_SImm16: return true0
;
2799
6
    
case MCK_SImm16_Relaxed: return true0
;
2800
6
    
case MCK_UImm16_Relaxed: return true0
;
2801
6
    
case MCK_ConstantUImm20_0: return true0
;
2802
6
    
case MCK_ConstantUImm26_0: return true0
;
2803
6
    
case MCK_SImm32: return true0
;
2804
6
    
case MCK_SImm32_Relaxed: return true0
;
2805
6
    
case MCK_UImm32_Coerced: return true0
;
2806
0
    }
2807
0
2808
0
  case MCK_ConstantSImm5_0:
2809
0
    switch (B) {
2810
0
    default: return false;
2811
0
    case MCK_ConstantUImm5_0: return true;
2812
0
    case MCK_ConstantUImm5_1: return true;
2813
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2814
0
    case MCK_ConstantUImm5_32_Norm: return true;
2815
0
    case MCK_ConstantUImm5_32: return true;
2816
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2817
0
    case MCK_ConstantUImm5_33: return true;
2818
0
    case MCK_ConstantUImmRange2_64: return true;
2819
0
    case MCK_UImm5Lsl2: return true;
2820
0
    case MCK_ConstantSImm6_0: return true;
2821
0
    case MCK_ConstantUImm6_0: return true;
2822
0
    case MCK_UImm6Lsl2: return true;
2823
0
    case MCK_ConstantUImm7_0: return true;
2824
0
    case MCK_UImm7_N1: return true;
2825
0
    case MCK_ConstantUImm8_0: return true;
2826
0
    case MCK_SImm7Lsl2: return true;
2827
0
    case MCK_ConstantSImm9_0: return true;
2828
0
    case MCK_ConstantSImm10_0: return true;
2829
0
    case MCK_ConstantUImm10_0: return true;
2830
0
    case MCK_SImm10Lsl1: return true;
2831
0
    case MCK_ConstantSImm11_0: return true;
2832
0
    case MCK_SImm10Lsl2: return true;
2833
0
    case MCK_SImm10Lsl3: return true;
2834
0
    case MCK_SImm16: return true;
2835
0
    case MCK_SImm16_Relaxed: return true;
2836
0
    case MCK_UImm16_Relaxed: return true;
2837
0
    case MCK_ConstantUImm20_0: return true;
2838
0
    case MCK_ConstantUImm26_0: return true;
2839
0
    case MCK_SImm32: return true;
2840
0
    case MCK_SImm32_Relaxed: return true;
2841
0
    case MCK_UImm32_Coerced: return true;
2842
0
    }
2843
0
2844
3
  case MCK_ConstantUImm5_0:
2845
3
    switch (B) {
2846
3
    default: return false;
2847
3
    
case MCK_ConstantUImm5_1: return true0
;
2848
3
    
case MCK_ConstantUImm5_Plus1_Report_UImm6: return true0
;
2849
3
    
case MCK_ConstantUImm5_32_Norm: return true0
;
2850
3
    
case MCK_ConstantUImm5_32: return true0
;
2851
3
    
case MCK_ConstantUImm5_0_Report_UImm6: return true0
;
2852
3
    
case MCK_ConstantUImm5_33: return true0
;
2853
3
    
case MCK_ConstantUImmRange2_64: return true0
;
2854
3
    
case MCK_UImm5Lsl2: return true0
;
2855
3
    
case MCK_ConstantSImm6_0: return true0
;
2856
3
    
case MCK_ConstantUImm6_0: return true0
;
2857
3
    
case MCK_UImm6Lsl2: return true0
;
2858
3
    
case MCK_ConstantUImm7_0: return true0
;
2859
3
    
case MCK_UImm7_N1: return true0
;
2860
3
    
case MCK_ConstantUImm8_0: return true0
;
2861
3
    
case MCK_SImm7Lsl2: return true0
;
2862
3
    
case MCK_ConstantSImm9_0: return true0
;
2863
3
    
case MCK_ConstantSImm10_0: return true0
;
2864
3
    
case MCK_ConstantUImm10_0: return true0
;
2865
3
    
case MCK_SImm10Lsl1: return true0
;
2866
3
    
case MCK_ConstantSImm11_0: return true0
;
2867
3
    
case MCK_SImm10Lsl2: return true0
;
2868
3
    
case MCK_SImm10Lsl3: return true0
;
2869
3
    
case MCK_SImm16: return true0
;
2870
3
    
case MCK_SImm16_Relaxed: return true0
;
2871
3
    
case MCK_UImm16_Relaxed: return true0
;
2872
3
    
case MCK_ConstantUImm20_0: return true0
;
2873
3
    
case MCK_ConstantUImm26_0: return true0
;
2874
3
    
case MCK_SImm32: return true0
;
2875
3
    
case MCK_SImm32_Relaxed: return true0
;
2876
3
    
case MCK_UImm32_Coerced: return true0
;
2877
0
    }
2878
0
2879
0
  case MCK_ConstantUImm5_1:
2880
0
    switch (B) {
2881
0
    default: return false;
2882
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2883
0
    case MCK_ConstantUImm5_32_Norm: return true;
2884
0
    case MCK_ConstantUImm5_32: return true;
2885
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2886
0
    case MCK_ConstantUImm5_33: return true;
2887
0
    case MCK_ConstantUImmRange2_64: return true;
2888
0
    case MCK_UImm5Lsl2: return true;
2889
0
    case MCK_ConstantSImm6_0: return true;
2890
0
    case MCK_ConstantUImm6_0: return true;
2891
0
    case MCK_UImm6Lsl2: return true;
2892
0
    case MCK_ConstantUImm7_0: return true;
2893
0
    case MCK_UImm7_N1: return true;
2894
0
    case MCK_ConstantUImm8_0: return true;
2895
0
    case MCK_SImm7Lsl2: return true;
2896
0
    case MCK_ConstantSImm9_0: return true;
2897
0
    case MCK_ConstantSImm10_0: return true;
2898
0
    case MCK_ConstantUImm10_0: return true;
2899
0
    case MCK_SImm10Lsl1: return true;
2900
0
    case MCK_ConstantSImm11_0: return true;
2901
0
    case MCK_SImm10Lsl2: return true;
2902
0
    case MCK_SImm10Lsl3: return true;
2903
0
    case MCK_SImm16: return true;
2904
0
    case MCK_SImm16_Relaxed: return true;
2905
0
    case MCK_UImm16_Relaxed: return true;
2906
0
    case MCK_ConstantUImm20_0: return true;
2907
0
    case MCK_ConstantUImm26_0: return true;
2908
0
    case MCK_SImm32: return true;
2909
0
    case MCK_SImm32_Relaxed: return true;
2910
0
    case MCK_UImm32_Coerced: return true;
2911
0
    }
2912
0
2913
0
  case MCK_ConstantUImm5_Plus1_Report_UImm6:
2914
0
    switch (B) {
2915
0
    default: return false;
2916
0
    case MCK_ConstantUImm5_32_Norm: return true;
2917
0
    case MCK_ConstantUImm5_32: return true;
2918
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2919
0
    case MCK_ConstantUImm5_33: return true;
2920
0
    case MCK_ConstantUImmRange2_64: return true;
2921
0
    case MCK_UImm5Lsl2: return true;
2922
0
    case MCK_ConstantSImm6_0: return true;
2923
0
    case MCK_ConstantUImm6_0: return true;
2924
0
    case MCK_UImm6Lsl2: return true;
2925
0
    case MCK_ConstantUImm7_0: return true;
2926
0
    case MCK_UImm7_N1: return true;
2927
0
    case MCK_ConstantUImm8_0: return true;
2928
0
    case MCK_SImm7Lsl2: return true;
2929
0
    case MCK_ConstantSImm9_0: return true;
2930
0
    case MCK_ConstantSImm10_0: return true;
2931
0
    case MCK_ConstantUImm10_0: return true;
2932
0
    case MCK_SImm10Lsl1: return true;
2933
0
    case MCK_ConstantSImm11_0: return true;
2934
0
    case MCK_SImm10Lsl2: return true;
2935
0
    case MCK_SImm10Lsl3: return true;
2936
0
    case MCK_SImm16: return true;
2937
0
    case MCK_SImm16_Relaxed: return true;
2938
0
    case MCK_UImm16_Relaxed: return true;
2939
0
    case MCK_ConstantUImm20_0: return true;
2940
0
    case MCK_ConstantUImm26_0: return true;
2941
0
    case MCK_SImm32: return true;
2942
0
    case MCK_SImm32_Relaxed: return true;
2943
0
    case MCK_UImm32_Coerced: return true;
2944
0
    }
2945
0
2946
0
  case MCK_ConstantUImm5_32_Norm:
2947
0
    switch (B) {
2948
0
    default: return false;
2949
0
    case MCK_ConstantUImm5_32: return true;
2950
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2951
0
    case MCK_ConstantUImm5_33: return true;
2952
0
    case MCK_ConstantUImmRange2_64: return true;
2953
0
    case MCK_UImm5Lsl2: return true;
2954
0
    case MCK_ConstantSImm6_0: return true;
2955
0
    case MCK_ConstantUImm6_0: return true;
2956
0
    case MCK_UImm6Lsl2: return true;
2957
0
    case MCK_ConstantUImm7_0: return true;
2958
0
    case MCK_UImm7_N1: return true;
2959
0
    case MCK_ConstantUImm8_0: return true;
2960
0
    case MCK_SImm7Lsl2: return true;
2961
0
    case MCK_ConstantSImm9_0: return true;
2962
0
    case MCK_ConstantSImm10_0: return true;
2963
0
    case MCK_ConstantUImm10_0: return true;
2964
0
    case MCK_SImm10Lsl1: return true;
2965
0
    case MCK_ConstantSImm11_0: return true;
2966
0
    case MCK_SImm10Lsl2: return true;
2967
0
    case MCK_SImm10Lsl3: return true;
2968
0
    case MCK_SImm16: return true;
2969
0
    case MCK_SImm16_Relaxed: return true;
2970
0
    case MCK_UImm16_Relaxed: return true;
2971
0
    case MCK_ConstantUImm20_0: return true;
2972
0
    case MCK_ConstantUImm26_0: return true;
2973
0
    case MCK_SImm32: return true;
2974
0
    case MCK_SImm32_Relaxed: return true;
2975
0
    case MCK_UImm32_Coerced: return true;
2976
0
    }
2977
0
2978
0
  case MCK_ConstantUImm5_32:
2979
0
    switch (B) {
2980
0
    default: return false;
2981
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2982
0
    case MCK_ConstantUImm5_33: return true;
2983
0
    case MCK_ConstantUImmRange2_64: return true;
2984
0
    case MCK_UImm5Lsl2: return true;
2985
0
    case MCK_ConstantSImm6_0: return true;
2986
0
    case MCK_ConstantUImm6_0: return true;
2987
0
    case MCK_UImm6Lsl2: return true;
2988
0
    case MCK_ConstantUImm7_0: return true;
2989
0
    case MCK_UImm7_N1: return true;
2990
0
    case MCK_ConstantUImm8_0: return true;
2991
0
    case MCK_SImm7Lsl2: return true;
2992
0
    case MCK_ConstantSImm9_0: return true;
2993
0
    case MCK_ConstantSImm10_0: return true;
2994
0
    case MCK_ConstantUImm10_0: return true;
2995
0
    case MCK_SImm10Lsl1: return true;
2996
0
    case MCK_ConstantSImm11_0: return true;
2997
0
    case MCK_SImm10Lsl2: return true;
2998
0
    case MCK_SImm10Lsl3: return true;
2999
0
    case MCK_SImm16: return true;
3000
0
    case MCK_SImm16_Relaxed: return true;
3001
0
    case MCK_UImm16_Relaxed: return true;
3002
0
    case MCK_ConstantUImm20_0: return true;
3003
0
    case MCK_ConstantUImm26_0: return true;
3004
0
    case MCK_SImm32: return true;
3005
0
    case MCK_SImm32_Relaxed: return true;
3006
0
    case MCK_UImm32_Coerced: return true;
3007
0
    }
3008
0
3009
0
  case MCK_ConstantUImm5_0_Report_UImm6:
3010
0
    switch (B) {
3011
0
    default: return false;
3012
0
    case MCK_ConstantUImm5_33: return true;
3013
0
    case MCK_ConstantUImmRange2_64: return true;
3014
0
    case MCK_UImm5Lsl2: return true;
3015
0
    case MCK_ConstantSImm6_0: return true;
3016
0
    case MCK_ConstantUImm6_0: return true;
3017
0
    case MCK_UImm6Lsl2: return true;
3018
0
    case MCK_ConstantUImm7_0: return true;
3019
0
    case MCK_UImm7_N1: return true;
3020
0
    case MCK_ConstantUImm8_0: return true;
3021
0
    case MCK_SImm7Lsl2: return true;
3022
0
    case MCK_ConstantSImm9_0: return true;
3023
0
    case MCK_ConstantSImm10_0: return true;
3024
0
    case MCK_ConstantUImm10_0: return true;
3025
0
    case MCK_SImm10Lsl1: return true;
3026
0
    case MCK_ConstantSImm11_0: return true;
3027
0
    case MCK_SImm10Lsl2: return true;
3028
0
    case MCK_SImm10Lsl3: return true;
3029
0
    case MCK_SImm16: return true;
3030
0
    case MCK_SImm16_Relaxed: return true;
3031
0
    case MCK_UImm16_Relaxed: return true;
3032
0
    case MCK_ConstantUImm20_0: return true;
3033
0
    case MCK_ConstantUImm26_0: return true;
3034
0
    case MCK_SImm32: return true;
3035
0
    case MCK_SImm32_Relaxed: return true;
3036
0
    case MCK_UImm32_Coerced: return true;
3037
0
    }
3038
0
3039
0
  case MCK_ConstantUImm5_33:
3040
0
    switch (B) {
3041
0
    default: return false;
3042
0
    case MCK_ConstantUImmRange2_64: return true;
3043
0
    case MCK_UImm5Lsl2: return true;
3044
0
    case MCK_ConstantSImm6_0: return true;
3045
0
    case MCK_ConstantUImm6_0: return true;
3046
0
    case MCK_UImm6Lsl2: return true;
3047
0
    case MCK_ConstantUImm7_0: return true;
3048
0
    case MCK_UImm7_N1: return true;
3049
0
    case MCK_ConstantUImm8_0: return true;
3050
0
    case MCK_SImm7Lsl2: return true;
3051
0
    case MCK_ConstantSImm9_0: return true;
3052
0
    case MCK_ConstantSImm10_0: return true;
3053
0
    case MCK_ConstantUImm10_0: return true;
3054
0
    case MCK_SImm10Lsl1: return true;
3055
0
    case MCK_ConstantSImm11_0: return true;
3056
0
    case MCK_SImm10Lsl2: return true;
3057
0
    case MCK_SImm10Lsl3: return true;
3058
0
    case MCK_SImm16: return true;
3059
0
    case MCK_SImm16_Relaxed: return true;
3060
0
    case MCK_UImm16_Relaxed: return true;
3061
0
    case MCK_ConstantUImm20_0: return true;
3062
0
    case MCK_ConstantUImm26_0: return true;
3063
0
    case MCK_SImm32: return true;
3064
0
    case MCK_SImm32_Relaxed: return true;
3065
0
    case MCK_UImm32_Coerced: return true;
3066
0
    }
3067
0
3068
0
  case MCK_ConstantUImmRange2_64:
3069
0
    switch (B) {
3070
0
    default: return false;
3071
0
    case MCK_UImm5Lsl2: return true;
3072
0
    case MCK_ConstantSImm6_0: return true;
3073
0
    case MCK_ConstantUImm6_0: return true;
3074
0
    case MCK_UImm6Lsl2: return true;
3075
0
    case MCK_ConstantUImm7_0: return true;
3076
0
    case MCK_UImm7_N1: return true;
3077
0
    case MCK_ConstantUImm8_0: return true;
3078
0
    case MCK_SImm7Lsl2: return true;
3079
0
    case MCK_ConstantSImm9_0: return true;
3080
0
    case MCK_ConstantSImm10_0: return true;
3081
0
    case MCK_ConstantUImm10_0: return true;
3082
0
    case MCK_SImm10Lsl1: return true;
3083
0
    case MCK_ConstantSImm11_0: return true;
3084
0
    case MCK_SImm10Lsl2: return true;
3085
0
    case MCK_SImm10Lsl3: return true;
3086
0
    case MCK_SImm16: return true;
3087
0
    case MCK_SImm16_Relaxed: return true;
3088
0
    case MCK_UImm16_Relaxed: return true;
3089
0
    case MCK_ConstantUImm20_0: return true;
3090
0
    case MCK_ConstantUImm26_0: return true;
3091
0
    case MCK_SImm32: return true;
3092
0
    case MCK_SImm32_Relaxed: return true;
3093
0
    case MCK_UImm32_Coerced: return true;
3094
0
    }
3095
0
3096
0
  case MCK_UImm5Lsl2:
3097
0
    switch (B) {
3098
0
    default: return false;
3099
0
    case MCK_ConstantSImm6_0: return true;
3100
0
    case MCK_ConstantUImm6_0: return true;
3101
0
    case MCK_UImm6Lsl2: return true;
3102
0
    case MCK_ConstantUImm7_0: return true;
3103
0
    case MCK_UImm7_N1: return true;
3104
0
    case MCK_ConstantUImm8_0: return true;
3105
0
    case MCK_SImm7Lsl2: return true;
3106
0
    case MCK_ConstantSImm9_0: return true;
3107
0
    case MCK_ConstantSImm10_0: return true;
3108
0
    case MCK_ConstantUImm10_0: return true;
3109
0
    case MCK_SImm10Lsl1: return true;
3110
0
    case MCK_ConstantSImm11_0: return true;
3111
0
    case MCK_SImm10Lsl2: return true;
3112
0
    case MCK_SImm10Lsl3: return true;
3113
0
    case MCK_SImm16: return true;
3114
0
    case MCK_SImm16_Relaxed: return true;
3115
0
    case MCK_UImm16_Relaxed: return true;
3116
0
    case MCK_ConstantUImm20_0: return true;
3117
0
    case MCK_ConstantUImm26_0: return true;
3118
0
    case MCK_SImm32: return true;
3119
0
    case MCK_SImm32_Relaxed: return true;
3120
0
    case MCK_UImm32_Coerced: return true;
3121
0
    }
3122
0
3123
0
  case MCK_ConstantSImm6_0:
3124
0
    switch (B) {
3125
0
    default: return false;
3126
0
    case MCK_ConstantUImm6_0: return true;
3127
0
    case MCK_UImm6Lsl2: return true;
3128
0
    case MCK_ConstantUImm7_0: return true;
3129
0
    case MCK_UImm7_N1: return true;
3130
0
    case MCK_ConstantUImm8_0: return true;
3131
0
    case MCK_SImm7Lsl2: return true;
3132
0
    case MCK_ConstantSImm9_0: return true;
3133
0
    case MCK_ConstantSImm10_0: return true;
3134
0
    case MCK_ConstantUImm10_0: return true;
3135
0
    case MCK_SImm10Lsl1: return true;
3136
0
    case MCK_ConstantSImm11_0: return true;
3137
0
    case MCK_SImm10Lsl2: return true;
3138
0
    case MCK_SImm10Lsl3: return true;
3139
0
    case MCK_SImm16: return true;
3140
0
    case MCK_SImm16_Relaxed: return true;
3141
0
    case MCK_UImm16_Relaxed: return true;
3142
0
    case MCK_ConstantUImm20_0: return true;
3143
0
    case MCK_ConstantUImm26_0: return true;
3144
0
    case MCK_SImm32: return true;
3145
0
    case MCK_SImm32_Relaxed: return true;
3146
0
    case MCK_UImm32_Coerced: return true;
3147
0
    }
3148
0
3149
0
  case MCK_ConstantUImm6_0:
3150
0
    switch (B) {
3151
0
    default: return false;
3152
0
    case MCK_UImm6Lsl2: return true;
3153
0
    case MCK_ConstantUImm7_0: return true;
3154
0
    case MCK_UImm7_N1: return true;
3155
0
    case MCK_ConstantUImm8_0: return true;
3156
0
    case MCK_SImm7Lsl2: return true;
3157
0
    case MCK_ConstantSImm9_0: return true;
3158
0
    case MCK_ConstantSImm10_0: return true;
3159
0
    case MCK_ConstantUImm10_0: return true;
3160
0
    case MCK_SImm10Lsl1: return true;
3161
0
    case MCK_ConstantSImm11_0: return true;
3162
0
    case MCK_SImm10Lsl2: return true;
3163
0
    case MCK_SImm10Lsl3: return true;
3164
0
    case MCK_SImm16: return true;
3165
0
    case MCK_SImm16_Relaxed: return true;
3166
0
    case MCK_UImm16_Relaxed: return true;
3167
0
    case MCK_ConstantUImm20_0: return true;
3168
0
    case MCK_ConstantUImm26_0: return true;
3169
0
    case MCK_SImm32: return true;
3170
0
    case MCK_SImm32_Relaxed: return true;
3171
0
    case MCK_UImm32_Coerced: return true;
3172
0
    }
3173
0
3174
0
  case MCK_UImm6Lsl2:
3175
0
    switch (B) {
3176
0
    default: return false;
3177
0
    case MCK_ConstantUImm7_0: return true;
3178
0
    case MCK_UImm7_N1: return true;
3179
0
    case MCK_ConstantUImm8_0: return true;
3180
0
    case MCK_SImm7Lsl2: return true;
3181
0
    case MCK_ConstantSImm9_0: return true;
3182
0
    case MCK_ConstantSImm10_0: return true;
3183
0
    case MCK_ConstantUImm10_0: return true;
3184
0
    case MCK_SImm10Lsl1: return true;
3185
0
    case MCK_ConstantSImm11_0: return true;
3186
0
    case MCK_SImm10Lsl2: return true;
3187
0
    case MCK_SImm10Lsl3: return true;
3188
0
    case MCK_SImm16: return true;
3189
0
    case MCK_SImm16_Relaxed: return true;
3190
0
    case MCK_UImm16_Relaxed: return true;
3191
0
    case MCK_ConstantUImm20_0: return true;
3192
0
    case MCK_ConstantUImm26_0: return true;
3193
0
    case MCK_SImm32: return true;
3194
0
    case MCK_SImm32_Relaxed: return true;
3195
0
    case MCK_UImm32_Coerced: return true;
3196
0
    }
3197
0
3198
0
  case MCK_ConstantUImm7_0:
3199
0
    switch (B) {
3200
0
    default: return false;
3201
0
    case MCK_UImm7_N1: return true;
3202
0
    case MCK_ConstantUImm8_0: return true;
3203
0
    case MCK_SImm7Lsl2: return true;
3204
0
    case MCK_ConstantSImm9_0: return true;
3205
0
    case MCK_ConstantSImm10_0: return true;
3206
0
    case MCK_ConstantUImm10_0: return true;
3207
0
    case MCK_SImm10Lsl1: return true;
3208
0
    case MCK_ConstantSImm11_0: return true;
3209
0
    case MCK_SImm10Lsl2: return true;
3210
0
    case MCK_SImm10Lsl3: return true;
3211
0
    case MCK_SImm16: return true;
3212
0
    case MCK_SImm16_Relaxed: return true;
3213
0
    case MCK_UImm16_Relaxed: return true;
3214
0
    case MCK_ConstantUImm20_0: return true;
3215
0
    case MCK_ConstantUImm26_0: return true;
3216
0
    case MCK_SImm32: return true;
3217
0
    case MCK_SImm32_Relaxed: return true;
3218
0
    case MCK_UImm32_Coerced: return true;
3219
0
    }
3220
0
3221
0
  case MCK_UImm7_N1:
3222
0
    switch (B) {
3223
0
    default: return false;
3224
0
    case MCK_ConstantUImm8_0: return true;
3225
0
    case MCK_SImm7Lsl2: return true;
3226
0
    case MCK_ConstantSImm9_0: return true;
3227
0
    case MCK_ConstantSImm10_0: return true;
3228
0
    case MCK_ConstantUImm10_0: return true;
3229
0
    case MCK_SImm10Lsl1: return true;
3230
0
    case MCK_ConstantSImm11_0: return true;
3231
0
    case MCK_SImm10Lsl2: return true;
3232
0
    case MCK_SImm10Lsl3: return true;
3233
0
    case MCK_SImm16: return true;
3234
0
    case MCK_SImm16_Relaxed: return true;
3235
0
    case MCK_UImm16_Relaxed: return true;
3236
0
    case MCK_ConstantUImm20_0: return true;
3237
0
    case MCK_ConstantUImm26_0: return true;
3238
0
    case MCK_SImm32: return true;
3239
0
    case MCK_SImm32_Relaxed: return true;
3240
0
    case MCK_UImm32_Coerced: return true;
3241
0
    }
3242
0
3243
0
  case MCK_ConstantUImm8_0:
3244
0
    switch (B) {
3245
0
    default: return false;
3246
0
    case MCK_SImm7Lsl2: return true;
3247
0
    case MCK_ConstantSImm9_0: return true;
3248
0
    case MCK_ConstantSImm10_0: return true;
3249
0
    case MCK_ConstantUImm10_0: return true;
3250
0
    case MCK_SImm10Lsl1: return true;
3251
0
    case MCK_ConstantSImm11_0: return true;
3252
0
    case MCK_SImm10Lsl2: return true;
3253
0
    case MCK_SImm10Lsl3: return true;
3254
0
    case MCK_SImm16: return true;
3255
0
    case MCK_SImm16_Relaxed: return true;
3256
0
    case MCK_UImm16_Relaxed: return true;
3257
0
    case MCK_ConstantUImm20_0: return true;
3258
0
    case MCK_ConstantUImm26_0: return true;
3259
0
    case MCK_SImm32: return true;
3260
0
    case MCK_SImm32_Relaxed: return true;
3261
0
    case MCK_UImm32_Coerced: return true;
3262
0
    }
3263
0
3264
0
  case MCK_SImm7Lsl2:
3265
0
    switch (B) {
3266
0
    default: return false;
3267
0
    case MCK_ConstantSImm9_0: return true;
3268
0
    case MCK_ConstantSImm10_0: return true;
3269
0
    case MCK_ConstantUImm10_0: return true;
3270
0
    case MCK_SImm10Lsl1: return true;
3271
0
    case MCK_ConstantSImm11_0: return true;
3272
0
    case MCK_SImm10Lsl2: return true;
3273
0
    case MCK_SImm10Lsl3: return true;
3274
0
    case MCK_SImm16: return true;
3275
0
    case MCK_SImm16_Relaxed: return true;
3276
0
    case MCK_UImm16_Relaxed: return true;
3277
0
    case MCK_ConstantUImm20_0: return true;
3278
0
    case MCK_ConstantUImm26_0: return true;
3279
0
    case MCK_SImm32: return true;
3280
0
    case MCK_SImm32_Relaxed: return true;
3281
0
    case MCK_UImm32_Coerced: return true;
3282
0
    }
3283
0
3284
0
  case MCK_ConstantSImm9_0:
3285
0
    switch (B) {
3286
0
    default: return false;
3287
0
    case MCK_ConstantSImm10_0: return true;
3288
0
    case MCK_ConstantUImm10_0: return true;
3289
0
    case MCK_SImm10Lsl1: return true;
3290
0
    case MCK_ConstantSImm11_0: return true;
3291
0
    case MCK_SImm10Lsl2: return true;
3292
0
    case MCK_SImm10Lsl3: return true;
3293
0
    case MCK_SImm16: return true;
3294
0
    case MCK_SImm16_Relaxed: return true;
3295
0
    case MCK_UImm16_Relaxed: return true;
3296
0
    case MCK_ConstantUImm20_0: return true;
3297
0
    case MCK_ConstantUImm26_0: return true;
3298
0
    case MCK_SImm32: return true;
3299
0
    case MCK_SImm32_Relaxed: return true;
3300
0
    case MCK_UImm32_Coerced: return true;
3301
0
    }
3302
0
3303
0
  case MCK_ConstantSImm10_0:
3304
0
    switch (B) {
3305
0
    default: return false;
3306
0
    case MCK_ConstantUImm10_0: return true;
3307
0
    case MCK_SImm10Lsl1: return true;
3308
0
    case MCK_ConstantSImm11_0: return true;
3309
0
    case MCK_SImm10Lsl2: return true;
3310
0
    case MCK_SImm10Lsl3: return true;
3311
0
    case MCK_SImm16: return true;
3312
0
    case MCK_SImm16_Relaxed: return true;
3313
0
    case MCK_UImm16_Relaxed: return true;
3314
0
    case MCK_ConstantUImm20_0: return true;
3315
0
    case MCK_ConstantUImm26_0: return true;
3316
0
    case MCK_SImm32: return true;
3317
0
    case MCK_SImm32_Relaxed: return true;
3318
0
    case MCK_UImm32_Coerced: return true;
3319
0
    }
3320
0
3321
10
  case MCK_ConstantUImm10_0:
3322
10
    switch (B) {
3323
10
    default: return false;
3324
10
    
case MCK_SImm10Lsl1: return true0
;
3325
10
    
case MCK_ConstantSImm11_0: return true0
;
3326
10
    
case MCK_SImm10Lsl2: return true0
;
3327
10
    
case MCK_SImm10Lsl3: return true0
;
3328
10
    
case MCK_SImm16: return true0
;
3329
10
    
case MCK_SImm16_Relaxed: return true0
;
3330
10
    
case MCK_UImm16_Relaxed: return true0
;
3331
10
    
case MCK_ConstantUImm20_0: return true0
;
3332
10
    
case MCK_ConstantUImm26_0: return true0
;
3333
10
    
case MCK_SImm32: return true0
;
3334
10
    
case MCK_SImm32_Relaxed: return true0
;
3335
10
    
case MCK_UImm32_Coerced: return true0
;
3336
0
    }
3337
0
3338
0
  case MCK_SImm10Lsl1:
3339
0
    switch (B) {
3340
0
    default: return false;
3341
0
    case MCK_ConstantSImm11_0: return true;
3342
0
    case MCK_SImm10Lsl2: return true;
3343
0
    case MCK_SImm10Lsl3: return true;
3344
0
    case MCK_SImm16: return true;
3345
0
    case MCK_SImm16_Relaxed: return true;
3346
0
    case MCK_UImm16_Relaxed: return true;
3347
0
    case MCK_ConstantUImm20_0: return true;
3348
0
    case MCK_ConstantUImm26_0: return true;
3349
0
    case MCK_SImm32: return true;
3350
0
    case MCK_SImm32_Relaxed: return true;
3351
0
    case MCK_UImm32_Coerced: return true;
3352
0
    }
3353
0
3354
0
  case MCK_ConstantSImm11_0:
3355
0
    switch (B) {
3356
0
    default: return false;
3357
0
    case MCK_SImm10Lsl2: return true;
3358
0
    case MCK_SImm10Lsl3: return true;
3359
0
    case MCK_SImm16: return true;
3360
0
    case MCK_SImm16_Relaxed: return true;
3361
0
    case MCK_UImm16_Relaxed: return true;
3362
0
    case MCK_ConstantUImm20_0: return true;
3363
0
    case MCK_ConstantUImm26_0: return true;
3364
0
    case MCK_SImm32: return true;
3365
0
    case MCK_SImm32_Relaxed: return true;
3366
0
    case MCK_UImm32_Coerced: return true;
3367
0
    }
3368
0
3369
0
  case MCK_SImm10Lsl2:
3370
0
    switch (B) {
3371
0
    default: return false;
3372
0
    case MCK_SImm10Lsl3: return true;
3373
0
    case MCK_SImm16: return true;
3374
0
    case MCK_SImm16_Relaxed: return true;
3375
0
    case MCK_UImm16_Relaxed: return true;
3376
0
    case MCK_ConstantUImm20_0: return true;
3377
0
    case MCK_ConstantUImm26_0: return true;
3378
0
    case MCK_SImm32: return true;
3379
0
    case MCK_SImm32_Relaxed: return true;
3380
0
    case MCK_UImm32_Coerced: return true;
3381
0
    }
3382
0
3383
0
  case MCK_SImm10Lsl3:
3384
0
    switch (B) {
3385
0
    default: return false;
3386
0
    case MCK_SImm16: return true;
3387
0
    case MCK_SImm16_Relaxed: return true;
3388
0
    case MCK_UImm16_Relaxed: return true;
3389
0
    case MCK_ConstantUImm20_0: return true;
3390
0
    case MCK_ConstantUImm26_0: return true;
3391
0
    case MCK_SImm32: return true;
3392
0
    case MCK_SImm32_Relaxed: return true;
3393
0
    case MCK_UImm32_Coerced: return true;
3394
0
    }
3395
0
3396
10
  case MCK_SImm16:
3397
10
    switch (B) {
3398
10
    default: return false;
3399
10
    
case MCK_SImm16_Relaxed: return true0
;
3400
10
    
case MCK_UImm16_Relaxed: return true0
;
3401
10
    
case MCK_ConstantUImm20_0: return true0
;
3402
10
    
case MCK_ConstantUImm26_0: return true0
;
3403
10
    
case MCK_SImm32: return true0
;
3404
10
    
case MCK_SImm32_Relaxed: return true0
;
3405
10
    
case MCK_UImm32_Coerced: return true0
;
3406
0
    }
3407
0
3408
0
  case MCK_SImm16_Relaxed:
3409
0
    switch (B) {
3410
0
    default: return false;
3411
0
    case MCK_UImm16_Relaxed: return true;
3412
0
    case MCK_ConstantUImm20_0: return true;
3413
0
    case MCK_ConstantUImm26_0: return true;
3414
0
    case MCK_SImm32: return true;
3415
0
    case MCK_SImm32_Relaxed: return true;
3416
0
    case MCK_UImm32_Coerced: return true;
3417
0
    }
3418
0
3419
0
  case MCK_UImm16_AltRelaxed:
3420
0
    switch (B) {
3421
0
    default: return false;
3422
0
    case MCK_UImm16_Relaxed: return true;
3423
0
    case MCK_ConstantUImm20_0: return true;
3424
0
    case MCK_ConstantUImm26_0: return true;
3425
0
    case MCK_SImm32: return true;
3426
0
    case MCK_SImm32_Relaxed: return true;
3427
0
    case MCK_UImm32_Coerced: return true;
3428
0
    }
3429
0
3430
0
  case MCK_UImm16:
3431
0
    switch (B) {
3432
0
    default: return false;
3433
0
    case MCK_UImm16_Relaxed: return true;
3434
0
    case MCK_ConstantUImm20_0: return true;
3435
0
    case MCK_ConstantUImm26_0: return true;
3436
0
    case MCK_SImm32: return true;
3437
0
    case MCK_SImm32_Relaxed: return true;
3438
0
    case MCK_UImm32_Coerced: return true;
3439
0
    }
3440
0
3441
0
  case MCK_SImm19Lsl2:
3442
0
    switch (B) {
3443
0
    default: return false;
3444
0
    case MCK_ConstantUImm20_0: return true;
3445
0
    case MCK_ConstantUImm26_0: return true;
3446
0
    case MCK_SImm32: return true;
3447
0
    case MCK_SImm32_Relaxed: return true;
3448
0
    case MCK_UImm32_Coerced: return true;
3449
0
    }
3450
0
3451
0
  case MCK_UImm16_Relaxed:
3452
0
    switch (B) {
3453
0
    default: return false;
3454
0
    case MCK_ConstantUImm20_0: return true;
3455
0
    case MCK_ConstantUImm26_0: return true;
3456
0
    case MCK_SImm32: return true;
3457
0
    case MCK_SImm32_Relaxed: return true;
3458
0
    case MCK_UImm32_Coerced: return true;
3459
0
    }
3460
0
3461
0
  case MCK_ConstantUImm20_0:
3462
0
    switch (B) {
3463
0
    default: return false;
3464
0
    case MCK_ConstantUImm26_0: return true;
3465
0
    case MCK_SImm32: return true;
3466
0
    case MCK_SImm32_Relaxed: return true;
3467
0
    case MCK_UImm32_Coerced: return true;
3468
0
    }
3469
0
3470
0
  case MCK_ConstantUImm26_0:
3471
0
    switch (B) {
3472
0
    default: return false;
3473
0
    case MCK_SImm32: return true;
3474
0
    case MCK_SImm32_Relaxed: return true;
3475
0
    case MCK_UImm32_Coerced: return true;
3476
0
    }
3477
0
3478
0
  case MCK_SImm32:
3479
0
    switch (B) {
3480
0
    default: return false;
3481
0
    case MCK_SImm32_Relaxed: return true;
3482
0
    case MCK_UImm32_Coerced: return true;
3483
0
    }
3484
0
3485
0
  case MCK_SImm32_Relaxed:
3486
0
    return B == MCK_UImm32_Coerced;
3487
38.7k
  }
3488
38.7k
}
3489
3490
163k
static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
3491
163k
  MipsOperand &Operand = (MipsOperand&)GOp;
3492
163k
  if (Kind == InvalidMatchClass)
3493
5.07k
    return MCTargetAsmParser::Match_InvalidOperand;
3494
158k
3495
158k
  if (Operand.isToken() && 
Kind <= MCK_LAST_TOKEN880
)
3496
880
    return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
3497
880
             MCTargetAsmParser::Match_Success :
3498
880
             
MCTargetAsmParser::Match_InvalidOperand0
;
3499
157k
3500
157k
  switch (Kind) {
3501
157k
  
default: break14.5k
;
3502
157k
  // 'ACC64DSPAsmReg' class
3503
157k
  case MCK_ACC64DSPAsmReg: {
3504
571
    DiagnosticPredicate DP(Operand.isACCAsmReg());
3505
571
    if (DP.isMatch())
3506
420
      return MCTargetAsmParser::Match_Success;
3507
151
    break;
3508
151
    }
3509
151
  // 'AFGR64AsmReg' class
3510
4.69k
  case MCK_AFGR64AsmReg: {
3511
4.69k
    DiagnosticPredicate DP(Operand.isFGRAsmReg());
3512
4.69k
    if (DP.isMatch())
3513
4.19k
      return MCTargetAsmParser::Match_Success;
3514
498
    break;
3515
498
    }
3516
498
  // 'CCRAsmReg' class
3517
498
  case MCK_CCRAsmReg: {
3518
46
    DiagnosticPredicate DP(Operand.isCCRAsmReg());
3519
46
    if (DP.isMatch())
3520
46
      return MCTargetAsmParser::Match_Success;
3521
0
    break;
3522
0
    }
3523
0
  // 'COP0AsmReg' class
3524
680
  case MCK_COP0AsmReg: {
3525
680
    DiagnosticPredicate DP(Operand.isCOP0AsmReg());
3526
680
    if (DP.isMatch())
3527
548
      return MCTargetAsmParser::Match_Success;
3528
132
    break;
3529
132
    }
3530
132
  // 'COP2AsmReg' class
3531
566
  case MCK_COP2AsmReg: {
3532
566
    DiagnosticPredicate DP(Operand.isCOP2AsmReg());
3533
566
    if (DP.isMatch())
3534
564
      return MCTargetAsmParser::Match_Success;
3535
2
    break;
3536
2
    }
3537
2
  // 'COP3AsmReg' class
3538
16
  case MCK_COP3AsmReg: {
3539
16
    DiagnosticPredicate DP(Operand.isCOP3AsmReg());
3540
16
    if (DP.isMatch())
3541
16
      return MCTargetAsmParser::Match_Success;
3542
0
    break;
3543
0
    }
3544
0
  // 'FCCAsmReg' class
3545
2.07k
  case MCK_FCCAsmReg: {
3546
2.07k
    DiagnosticPredicate DP(Operand.isFCCAsmReg());
3547
2.07k
    if (DP.isMatch())
3548
1.65k
      return MCTargetAsmParser::Match_Success;
3549
418
    break;
3550
418
    }
3551
418
  // 'FGR32AsmReg' class
3552
6.77k
  case MCK_FGR32AsmReg: {
3553
6.77k
    DiagnosticPredicate DP(Operand.isFGRAsmReg());
3554
6.77k
    if (DP.isMatch())
3555
6.23k
      return MCTargetAsmParser::Match_Success;
3556
545
    break;
3557
545
    }
3558
545
  // 'FGR64AsmReg' class
3559
4.35k
  case MCK_FGR64AsmReg: {
3560
4.35k
    DiagnosticPredicate DP(Operand.isFGRAsmReg());
3561
4.35k
    if (DP.isMatch())
3562
3.85k
      return MCTargetAsmParser::Match_Success;
3563
500
    break;
3564
500
    }
3565
500
  // 'FGRH32AsmReg' class
3566
500
  case MCK_FGRH32AsmReg: {
3567
0
    DiagnosticPredicate DP(Operand.isFGRAsmReg());
3568
0
    if (DP.isMatch())
3569
0
      return MCTargetAsmParser::Match_Success;
3570
0
    break;
3571
0
    }
3572
0
  // 'GPR32AsmReg' class
3573
66.2k
  case MCK_GPR32AsmReg: {
3574
66.2k
    DiagnosticPredicate DP(Operand.isGPRAsmReg());
3575
66.2k
    if (DP.isMatch())
3576
62.5k
      return MCTargetAsmParser::Match_Success;
3577
3.72k
    break;
3578
3.72k
    }
3579
3.72k
  // 'GPR32NonZeroAsmReg' class
3580
3.72k
  case MCK_GPR32NonZeroAsmReg: {
3581
130
    DiagnosticPredicate DP(Operand.isGPRNonZeroAsmReg());
3582
130
    if (DP.isMatch())
3583
76
      return MCTargetAsmParser::Match_Success;
3584
54
    break;
3585
54
    }
3586
54
  // 'GPR32ZeroAsmReg' class
3587
100
  case MCK_GPR32ZeroAsmReg: {
3588
100
    DiagnosticPredicate DP(Operand.isGPRZeroAsmReg());
3589
100
    if (DP.isMatch())
3590
54
      return MCTargetAsmParser::Match_Success;
3591
46
    break;
3592
46
    }
3593
46
  // 'GPR64AsmReg' class
3594
8.34k
  case MCK_GPR64AsmReg: {
3595
8.34k
    DiagnosticPredicate DP(Operand.isGPRAsmReg());
3596
8.34k
    if (DP.isMatch())
3597
7.88k
      return MCTargetAsmParser::Match_Success;
3598
461
    break;
3599
461
    }
3600
461
  // 'GPRMM16AsmReg' class
3601
461
  case MCK_GPRMM16AsmReg: {
3602
269
    DiagnosticPredicate DP(Operand.isMM16AsmReg());
3603
269
    if (DP.isMatch())
3604
234
      return MCTargetAsmParser::Match_Success;
3605
35
    break;
3606
35
    }
3607
35
  // 'GPRMM16AsmRegMoveP' class
3608
35
  case MCK_GPRMM16AsmRegMoveP: {
3609
28
    DiagnosticPredicate DP(Operand.isMM16AsmRegMoveP());
3610
28
    if (DP.isMatch())
3611
20
      return MCTargetAsmParser::Match_Success;
3612
8
    break;
3613
8
    }
3614
8
  // 'GPRMM16AsmRegMovePPairFirst' class
3615
20
  case MCK_GPRMM16AsmRegMovePPairFirst: {
3616
20
    DiagnosticPredicate DP(Operand.isMM16AsmRegMovePPairFirst());
3617
20
    if (DP.isMatch())
3618
16
      return MCTargetAsmParser::Match_Success;
3619
4
    break;
3620
4
    }
3621
4
  // 'GPRMM16AsmRegMovePPairSecond' class
3622
16
  case MCK_GPRMM16AsmRegMovePPairSecond: {
3623
16
    DiagnosticPredicate DP(Operand.isMM16AsmRegMovePPairSecond());
3624
16
    if (DP.isMatch())
3625
16
      return MCTargetAsmParser::Match_Success;
3626
0
    break;
3627
0
    }
3628
0
  // 'GPRMM16AsmRegZero' class
3629
65
  case MCK_GPRMM16AsmRegZero: {
3630
65
    DiagnosticPredicate DP(Operand.isMM16AsmRegZero());
3631
65
    if (DP.isMatch())
3632
41
      return MCTargetAsmParser::Match_Success;
3633
24
    break;
3634
24
    }
3635
24
  // 'HI32DSPAsmReg' class
3636
24
  case MCK_HI32DSPAsmReg: {
3637
9
    DiagnosticPredicate DP(Operand.isACCAsmReg());
3638
9
    if (DP.isMatch())
3639
9
      return MCTargetAsmParser::Match_Success;
3640
0
    break;
3641
0
    }
3642
0
  // 'HWRegsAsmReg' class
3643
85
  case MCK_HWRegsAsmReg: {
3644
85
    DiagnosticPredicate DP(Operand.isHWRegsAsmReg());
3645
85
    if (DP.isMatch())
3646
85
      return MCTargetAsmParser::Match_Success;
3647
0
    break;
3648
0
    }
3649
0
  // 'Imm' class
3650
2.98k
  case MCK_Imm: {
3651
2.98k
    DiagnosticPredicate DP(Operand.isImm());
3652
2.98k
    if (DP.isMatch())
3653
1.96k
      return MCTargetAsmParser::Match_Success;
3654
1.02k
    break;
3655
1.02k
    }
3656
1.02k
  // 'LO32DSPAsmReg' class
3657
1.02k
  case MCK_LO32DSPAsmReg: {
3658
9
    DiagnosticPredicate DP(Operand.isACCAsmReg());
3659
9
    if (DP.isMatch())
3660
9
      return MCTargetAsmParser::Match_Success;
3661
0
    break;
3662
0
    }
3663
0
  // 'MSA128AsmReg' class
3664
2.13k
  case MCK_MSA128AsmReg: {
3665
2.13k
    DiagnosticPredicate DP(Operand.isMSA128AsmReg());
3666
2.13k
    if (DP.isMatch())
3667
2.13k
      return MCTargetAsmParser::Match_Success;
3668
0
    break;
3669
0
    }
3670
0
  // 'MSACtrlAsmReg' class
3671
38
  case MCK_MSACtrlAsmReg: {
3672
38
    DiagnosticPredicate DP(Operand.isMSACtrlAsmReg());
3673
38
    if (DP.isMatch())
3674
32
      return MCTargetAsmParser::Match_Success;
3675
6
    break;
3676
6
    }
3677
6
  // 'MicroMipsMemGP' class
3678
6
  case MCK_MicroMipsMemGP: {
3679
0
    DiagnosticPredicate DP(Operand.isMemWithSimmWordAlignedOffsetGP<9>());
3680
0
    if (DP.isMatch())
3681
0
      return MCTargetAsmParser::Match_Success;
3682
0
    break;
3683
0
    }
3684
0
  // 'MicroMipsMem' class
3685
75
  case MCK_MicroMipsMem: {
3686
75
    DiagnosticPredicate DP(Operand.isMemWithGRPMM16Base());
3687
75
    if (DP.isMatch())
3688
57
      return MCTargetAsmParser::Match_Success;
3689
18
    break;
3690
18
    }
3691
18
  // 'MicroMipsMemSP' class
3692
10.4k
  case MCK_MicroMipsMemSP: {
3693
10.4k
    DiagnosticPredicate DP(Operand.isMemWithUimmWordAlignedOffsetSP<7>());
3694
10.4k
    if (DP.isMatch())
3695
59
      return MCTargetAsmParser::Match_Success;
3696
10.4k
    break;
3697
10.4k
    }
3698
10.4k
  // 'InvNum' class
3699
10.4k
  case MCK_InvNum: {
3700
245
    DiagnosticPredicate DP(Operand.isInvNum());
3701
245
    if (DP.isMatch())
3702
106
      return MCTargetAsmParser::Match_Success;
3703
139
    break;
3704
139
    }
3705
139
  // 'JumpTarget' class
3706
2.59k
  case MCK_JumpTarget: {
3707
2.59k
    DiagnosticPredicate DP(Operand.isImm());
3708
2.59k
    if (DP.isMatch())
3709
2.27k
      return MCTargetAsmParser::Match_Success;
3710
322
    break;
3711
322
    }
3712
322
  // 'MemOffsetSimm10' class
3713
322
  case MCK_MemOffsetSimm10: {
3714
7
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10>());
3715
7
    if (DP.isMatch())
3716
3
      return MCTargetAsmParser::Match_Success;
3717
4
    if (DP.isNearMatch())
3718
4
      return MipsAsmParser::Match_MemSImm10;
3719
0
    break;
3720
0
    }
3721
0
  // 'MemOffsetSimm10_1' class
3722
9
  case MCK_MemOffsetSimm10_1: {
3723
9
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 1>());
3724
9
    if (DP.isMatch())
3725
5
      return MCTargetAsmParser::Match_Success;
3726
4
    if (DP.isNearMatch())
3727
4
      return MipsAsmParser::Match_MemSImm10Lsl1;
3728
0
    break;
3729
0
    }
3730
0
  // 'MemOffsetSimm10_2' class
3731
10
  case MCK_MemOffsetSimm10_2: {
3732
10
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 2>());
3733
10
    if (DP.isMatch())
3734
6
      return MCTargetAsmParser::Match_Success;
3735
4
    if (DP.isNearMatch())
3736
4
      return MipsAsmParser::Match_MemSImm10Lsl2;
3737
0
    break;
3738
0
    }
3739
0
  // 'MemOffsetSimm10_3' class
3740
13
  case MCK_MemOffsetSimm10_3: {
3741
13
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 3>());
3742
13
    if (DP.isMatch())
3743
9
      return MCTargetAsmParser::Match_Success;
3744
4
    if (DP.isNearMatch())
3745
4
      return MipsAsmParser::Match_MemSImm10Lsl3;
3746
0
    break;
3747
0
    }
3748
0
  // 'MemOffsetSimm11' class
3749
304
  case MCK_MemOffsetSimm11: {
3750
304
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<11>());
3751
304
    if (DP.isMatch())
3752
58
      return MCTargetAsmParser::Match_Success;
3753
246
    if (DP.isNearMatch())
3754
246
      return MipsAsmParser::Match_MemSImm11;
3755
0
    break;
3756
0
    }
3757
0
  // 'MemOffsetSimm12' class
3758
40
  case MCK_MemOffsetSimm12: {
3759
40
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<12>());
3760
40
    if (DP.isMatch())
3761
25
      return MCTargetAsmParser::Match_Success;
3762
15
    if (DP.isNearMatch())
3763
15
      return MipsAsmParser::Match_MemSImm12;
3764
0
    break;
3765
0
    }
3766
0
  // 'MemOffsetSimm16' class
3767
985
  case MCK_MemOffsetSimm16: {
3768
985
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<16>());
3769
985
    if (DP.isMatch())
3770
698
      return MCTargetAsmParser::Match_Success;
3771
287
    if (DP.isNearMatch())
3772
287
      return MipsAsmParser::Match_MemSImm16;
3773
0
    break;
3774
0
    }
3775
0
  // 'MemOffsetSimm9' class
3776
1.83k
  case MCK_MemOffsetSimm9: {
3777
1.83k
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<9>());
3778
1.83k
    if (DP.isMatch())
3779
586
      return MCTargetAsmParser::Match_Success;
3780
1.25k
    if (DP.isNearMatch())
3781
1.25k
      return MipsAsmParser::Match_MemSImm9;
3782
0
    break;
3783
0
    }
3784
0
  // 'MemOffsetSimmPtr' class
3785
381
  case MCK_MemOffsetSimmPtr: {
3786
381
    DiagnosticPredicate DP(Operand.isMemWithPtrSizeOffset());
3787
381
    if (DP.isMatch())
3788
335
      return MCTargetAsmParser::Match_Success;
3789
46
    if (DP.isNearMatch())
3790
46
      return MipsAsmParser::Match_MemSImmPtr;
3791
0
    break;
3792
0
    }
3793
0
  // 'MemOffsetUimm4' class
3794
18
  case MCK_MemOffsetUimm4: {
3795
18
    DiagnosticPredicate DP(Operand.isMemWithUimmOffsetSP<6>());
3796
18
    if (DP.isMatch())
3797
10
      return MCTargetAsmParser::Match_Success;
3798
8
    break;
3799
8
    }
3800
8
  // 'Mem' class
3801
12.0k
  case MCK_Mem: {
3802
12.0k
    DiagnosticPredicate DP(Operand.isMem());
3803
12.0k
    if (DP.isMatch())
3804
11.8k
      return MCTargetAsmParser::Match_Success;
3805
148
    break;
3806
148
    }
3807
148
  // 'RegList16' class
3808
148
  case MCK_RegList16: {
3809
36
    DiagnosticPredicate DP(Operand.isRegList16());
3810
36
    if (DP.isMatch())
3811
18
      return MCTargetAsmParser::Match_Success;
3812
18
    break;
3813
18
    }
3814
18
  // 'RegList' class
3815
55
  case MCK_RegList: {
3816
55
    DiagnosticPredicate DP(Operand.isRegList());
3817
55
    if (DP.isMatch())
3818
55
      return MCTargetAsmParser::Match_Success;
3819
0
    break;
3820
0
    }
3821
0
  // 'Simm19_Lsl2' class
3822
94
  case MCK_Simm19_Lsl2: {
3823
94
    DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>());
3824
94
    if (DP.isMatch())
3825
52
      return MCTargetAsmParser::Match_Success;
3826
42
    if (DP.isNearMatch())
3827
42
      return MipsAsmParser::Match_SImm19_Lsl2;
3828
0
    break;
3829
0
    }
3830
0
  // 'StrictlyAFGR64AsmReg' class
3831
91
  case MCK_StrictlyAFGR64AsmReg: {
3832
91
    DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
3833
91
    if (DP.isMatch())
3834
91
      return MCTargetAsmParser::Match_Success;
3835
0
    break;
3836
0
    }
3837
0
  // 'StrictlyFGR32AsmReg' class
3838
66
  case MCK_StrictlyFGR32AsmReg: {
3839
66
    DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
3840
66
    if (DP.isMatch())
3841
66
      return MCTargetAsmParser::Match_Success;
3842
0
    break;
3843
0
    }
3844
0
  // 'StrictlyFGR64AsmReg' class
3845
52
  case MCK_StrictlyFGR64AsmReg: {
3846
52
    DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
3847
52
    if (DP.isMatch())
3848
52
      return MCTargetAsmParser::Match_Success;
3849
0
    break;
3850
0
    }
3851
0
  // 'ConstantImmz' class
3852
12
  case MCK_ConstantImmz: {
3853
12
    DiagnosticPredicate DP(Operand.isConstantImmz());
3854
12
    if (DP.isMatch())
3855
4
      return MCTargetAsmParser::Match_Success;
3856
8
    if (DP.isNearMatch())
3857
8
      return MipsAsmParser::Match_Immz;
3858
0
    break;
3859
0
    }
3860
0
  // 'ConstantUImm1_0' class
3861
69
  case MCK_ConstantUImm1_0: {
3862
69
    DiagnosticPredicate DP(Operand.isConstantUImm<1, 0>());
3863
69
    if (DP.isMatch())
3864
55
      return MCTargetAsmParser::Match_Success;
3865
14
    if (DP.isNearMatch())
3866
14
      return MipsAsmParser::Match_UImm1_0;
3867
0
    break;
3868
0
    }
3869
0
  // 'ConstantUImm2_0' class
3870
85
  case MCK_ConstantUImm2_0: {
3871
85
    DiagnosticPredicate DP(Operand.isConstantUImm<2, 0>());
3872
85
    if (DP.isMatch())
3873
31
      return MCTargetAsmParser::Match_Success;
3874
54
    if (DP.isNearMatch())
3875
54
      return MipsAsmParser::Match_UImm2_0;
3876
0
    break;
3877
0
    }
3878
0
  // 'ConstantUImm2_1' class
3879
56
  case MCK_ConstantUImm2_1: {
3880
56
    DiagnosticPredicate DP(Operand.isConstantUImm<2, 1>());
3881
56
    if (DP.isMatch())
3882
18
      return MCTargetAsmParser::Match_Success;
3883
38
    if (DP.isNearMatch())
3884
38
      return MipsAsmParser::Match_UImm2_1;
3885
0
    break;
3886
0
    }
3887
0
  // 'ConstantUImm3_0' class
3888
410
  case MCK_ConstantUImm3_0: {
3889
410
    DiagnosticPredicate DP(Operand.isConstantUImm<3, 0>());
3890
410
    if (DP.isMatch())
3891
229
      return MCTargetAsmParser::Match_Success;
3892
181
    if (DP.isNearMatch())
3893
181
      return MipsAsmParser::Match_UImm3_0;
3894
0
    break;
3895
0
    }
3896
0
  // 'ConstantSImm4_0' class
3897
8
  case MCK_ConstantSImm4_0: {
3898
8
    DiagnosticPredicate DP(Operand.isConstantSImm<4, 0>());
3899
8
    if (DP.isMatch())
3900
4
      return MCTargetAsmParser::Match_Success;
3901
4
    if (DP.isNearMatch())
3902
4
      return MipsAsmParser::Match_SImm4_0;
3903
0
    break;
3904
0
    }
3905
0
  // 'ConstantUImm4_0' class
3906
291
  case MCK_ConstantUImm4_0: {
3907
291
    DiagnosticPredicate DP(Operand.isConstantUImm<4, 0>());
3908
291
    if (DP.isMatch())
3909
81
      return MCTargetAsmParser::Match_Success;
3910
210
    if (DP.isNearMatch())
3911
210
      return MipsAsmParser::Match_UImm4_0;
3912
0
    break;
3913
0
    }
3914
0
  // 'ConstantSImm5_0' class
3915
60
  case MCK_ConstantSImm5_0: {
3916
60
    DiagnosticPredicate DP(Operand.isConstantSImm<5, 0>());
3917
60
    if (DP.isMatch())
3918
20
      return MCTargetAsmParser::Match_Success;
3919
40
    if (DP.isNearMatch())
3920
40
      return MipsAsmParser::Match_SImm5_0;
3921
0
    break;
3922
0
    }
3923
0
  // 'ConstantUImm5_0' class
3924
2.09k
  case MCK_ConstantUImm5_0: {
3925
2.09k
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>());
3926
2.09k
    if (DP.isMatch())
3927
869
      return MCTargetAsmParser::Match_Success;
3928
1.22k
    if (DP.isNearMatch())
3929
1.22k
      return MipsAsmParser::Match_UImm5_0;
3930
0
    break;
3931
0
    }
3932
0
  // 'ConstantUImm5_1' class
3933
129
  case MCK_ConstantUImm5_1: {
3934
129
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>());
3935
129
    if (DP.isMatch())
3936
79
      return MCTargetAsmParser::Match_Success;
3937
50
    if (DP.isNearMatch())
3938
50
      return MipsAsmParser::Match_UImm5_1;
3939
0
    break;
3940
0
    }
3941
0
  // 'ConstantUImm5_Plus1_Report_UImm6' class
3942
11
  case MCK_ConstantUImm5_Plus1_Report_UImm6: {
3943
11
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>());
3944
11
    if (DP.isMatch())
3945
9
      return MCTargetAsmParser::Match_Success;
3946
2
    if (DP.isNearMatch())
3947
2
      return MipsAsmParser::Match_UImm5_1;
3948
0
    break;
3949
0
    }
3950
0
  // 'ConstantUImm5_32_Norm' class
3951
16
  case MCK_ConstantUImm5_32_Norm: {
3952
16
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>());
3953
16
    if (DP.isMatch())
3954
6
      return MCTargetAsmParser::Match_Success;
3955
10
    if (DP.isNearMatch())
3956
10
      return MipsAsmParser::Match_UImm5_32;
3957
0
    break;
3958
0
    }
3959
0
  // 'ConstantUImm5_32' class
3960
76
  case MCK_ConstantUImm5_32: {
3961
76
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>());
3962
76
    if (DP.isMatch())
3963
34
      return MCTargetAsmParser::Match_Success;
3964
42
    if (DP.isNearMatch())
3965
42
      return MipsAsmParser::Match_UImm5_32;
3966
0
    break;
3967
0
    }
3968
0
  // 'ConstantUImm5_0_Report_UImm6' class
3969
23
  case MCK_ConstantUImm5_0_Report_UImm6: {
3970
23
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>());
3971
23
    if (DP.isMatch())
3972
13
      return MCTargetAsmParser::Match_Success;
3973
10
    if (DP.isNearMatch())
3974
10
      return MipsAsmParser::Match_UImm5_0_Report_UImm6;
3975
0
    break;
3976
0
    }
3977
0
  // 'ConstantUImm5_33' class
3978
26
  case MCK_ConstantUImm5_33: {
3979
26
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 33>());
3980
26
    if (DP.isMatch())
3981
11
      return MCTargetAsmParser::Match_Success;
3982
15
    if (DP.isNearMatch())
3983
15
      return MipsAsmParser::Match_UImm5_33;
3984
0
    break;
3985
0
    }
3986
0
  // 'ConstantUImmRange2_64' class
3987
28
  case MCK_ConstantUImmRange2_64: {
3988
28
    DiagnosticPredicate DP(Operand.isConstantUImmRange<2, 64>());
3989
28
    if (DP.isMatch())
3990
18
      return MCTargetAsmParser::Match_Success;
3991
10
    if (DP.isNearMatch())
3992
10
      return MipsAsmParser::Match_UImmRange2_64;
3993
0
    break;
3994
0
    }
3995
0
  // 'UImm5Lsl2' class
3996
26
  case MCK_UImm5Lsl2: {
3997
26
    DiagnosticPredicate DP(Operand.isScaledUImm<5, 2>());
3998
26
    if (DP.isMatch())
3999
4
      return MCTargetAsmParser::Match_Success;
4000
22
    if (DP.isNearMatch())
4001
22
      return MipsAsmParser::Match_UImm5_Lsl2;
4002
0
    break;
4003
0
    }
4004
0
  // 'ConstantSImm6_0' class
4005
22
  case MCK_ConstantSImm6_0: {
4006
22
    DiagnosticPredicate DP(Operand.isConstantSImm<6, 0>());
4007
22
    if (DP.isMatch())
4008
14
      return MCTargetAsmParser::Match_Success;
4009
8
    if (DP.isNearMatch())
4010
8
      return MipsAsmParser::Match_SImm6_0;
4011
0
    break;
4012
0
    }
4013
0
  // 'ConstantUImm6_0' class
4014
302
  case MCK_ConstantUImm6_0: {
4015
302
    DiagnosticPredicate DP(Operand.isConstantUImm<6, 0>());
4016
302
    if (DP.isMatch())
4017
119
      return MCTargetAsmParser::Match_Success;
4018
183
    if (DP.isNearMatch())
4019
183
      return MipsAsmParser::Match_UImm6_0;
4020
0
    break;
4021
0
    }
4022
0
  // 'UImm6Lsl2' class
4023
10
  case MCK_UImm6Lsl2: {
4024
10
    DiagnosticPredicate DP(Operand.isScaledUImm<6, 2>());
4025
10
    if (DP.isMatch())
4026
4
      return MCTargetAsmParser::Match_Success;
4027
6
    if (DP.isNearMatch())
4028
6
      return MipsAsmParser::Match_UImm6_Lsl2;
4029
0
    break;
4030
0
    }
4031
0
  // 'ConstantUImm7_0' class
4032
19
  case MCK_ConstantUImm7_0: {
4033
19
    DiagnosticPredicate DP(Operand.isConstantUImm<7, 0>());
4034
19
    if (DP.isMatch())
4035
11
      return MCTargetAsmParser::Match_Success;
4036
8
    if (DP.isNearMatch())
4037
8
      return MipsAsmParser::Match_UImm7_0;
4038
0
    break;
4039
0
    }
4040
0
  // 'UImm7_N1' class
4041
16
  case MCK_UImm7_N1: {
4042
16
    DiagnosticPredicate DP(Operand.isConstantUImm<7, -1>());
4043
16
    if (DP.isMatch())
4044
8
      return MCTargetAsmParser::Match_Success;
4045
8
    if (DP.isNearMatch())
4046
8
      return MipsAsmParser::Match_UImm7_N1;
4047
0
    break;
4048
0
    }
4049
0
  // 'ConstantUImm8_0' class
4050
46
  case MCK_ConstantUImm8_0: {
4051
46
    DiagnosticPredicate DP(Operand.isConstantUImm<8, 0>());
4052
46
    if (DP.isMatch())
4053
19
      return MCTargetAsmParser::Match_Success;
4054
27
    if (DP.isNearMatch())
4055
27
      return MipsAsmParser::Match_UImm8_0;
4056
0
    break;
4057
0
    }
4058
0
  // 'SImm7Lsl2' class
4059
0
  case MCK_SImm7Lsl2: {
4060
0
    DiagnosticPredicate DP(Operand.isScaledSImm<7, 2>());
4061
0
    if (DP.isMatch())
4062
0
      return MCTargetAsmParser::Match_Success;
4063
0
    if (DP.isNearMatch())
4064
0
      return MipsAsmParser::Match_SImm7_Lsl2;
4065
0
    break;
4066
0
    }
4067
0
  // 'ConstantSImm9_0' class
4068
0
  case MCK_ConstantSImm9_0: {
4069
0
    DiagnosticPredicate DP(Operand.isConstantSImm<9, 0>());
4070
0
    if (DP.isMatch())
4071
0
      return MCTargetAsmParser::Match_Success;
4072
0
    if (DP.isNearMatch())
4073
0
      return MipsAsmParser::Match_SImm9_0;
4074
0
    break;
4075
0
    }
4076
0
  // 'ConstantSImm10_0' class
4077
44
  case MCK_ConstantSImm10_0: {
4078
44
    DiagnosticPredicate DP(Operand.isConstantSImm<10, 0>());
4079
44
    if (DP.isMatch())
4080
18
      return MCTargetAsmParser::Match_Success;
4081
26
    if (DP.isNearMatch())
4082
26
      return MipsAsmParser::Match_SImm10_0;
4083
0
    break;
4084
0
    }
4085
0
  // 'ConstantUImm10_0' class
4086
470
  case MCK_ConstantUImm10_0: {
4087
470
    DiagnosticPredicate DP(Operand.isConstantUImm<10, 0>());
4088
470
    if (DP.isMatch())
4089
258
      return MCTargetAsmParser::Match_Success;
4090
212
    if (DP.isNearMatch())
4091
212
      return MipsAsmParser::Match_UImm10_0;
4092
0
    break;
4093
0
    }
4094
0
  // 'SImm10Lsl1' class
4095
0
  case MCK_SImm10Lsl1: {
4096
0
    DiagnosticPredicate DP(Operand.isScaledSImm<10, 1>());
4097
0
    if (DP.isMatch())
4098
0
      return MCTargetAsmParser::Match_Success;
4099
0
    if (DP.isNearMatch())
4100
0
      return MipsAsmParser::Match_SImm10_Lsl1;
4101
0
    break;
4102
0
    }
4103
0
  // 'ConstantSImm11_0' class
4104
0
  case MCK_ConstantSImm11_0: {
4105
0
    DiagnosticPredicate DP(Operand.isConstantSImm<11, 0>());
4106
0
    if (DP.isMatch())
4107
0
      return MCTargetAsmParser::Match_Success;
4108
0
    if (DP.isNearMatch())
4109
0
      return MipsAsmParser::Match_SImm11_0;
4110
0
    break;
4111
0
    }
4112
0
  // 'SImm10Lsl2' class
4113
0
  case MCK_SImm10Lsl2: {
4114
0
    DiagnosticPredicate DP(Operand.isScaledSImm<10, 2>());
4115
0
    if (DP.isMatch())
4116
0
      return MCTargetAsmParser::Match_Success;
4117
0
    if (DP.isNearMatch())
4118
0
      return MipsAsmParser::Match_SImm10_Lsl2;
4119
0
    break;
4120
0
    }
4121
0
  // 'SImm10Lsl3' class
4122
0
  case MCK_SImm10Lsl3: {
4123
0
    DiagnosticPredicate DP(Operand.isScaledSImm<10, 3>());
4124
0
    if (DP.isMatch())
4125
0
      return MCTargetAsmParser::Match_Success;
4126
0
    if (DP.isNearMatch())
4127
0
      return MipsAsmParser::Match_SImm10_Lsl3;
4128
0
    break;
4129
0
    }
4130
0
  // 'SImm16' class
4131
3.76k
  case MCK_SImm16: {
4132
3.76k
    DiagnosticPredicate DP(Operand.isSImm<16>());
4133
3.76k
    if (DP.isMatch())
4134
2.06k
      return MCTargetAsmParser::Match_Success;
4135
1.69k
    if (DP.isNearMatch())
4136
1.69k
      return MipsAsmParser::Match_SImm16;
4137
0
    break;
4138
0
    }
4139
0
  // 'SImm16_Relaxed' class
4140
1.14k
  case MCK_SImm16_Relaxed: {
4141
1.14k
    DiagnosticPredicate DP(Operand.isAnyImm<16>());
4142
1.14k
    if (DP.isMatch())
4143
519
      return MCTargetAsmParser::Match_Success;
4144
622
    if (DP.isNearMatch())
4145
622
      return MipsAsmParser::Match_SImm16_Relaxed;
4146
0
    break;
4147
0
    }
4148
0
  // 'UImm16_AltRelaxed' class
4149
11
  case MCK_UImm16_AltRelaxed: {
4150
11
    DiagnosticPredicate DP(Operand.isUImm<16>());
4151
11
    if (DP.isMatch())
4152
6
      return MCTargetAsmParser::Match_Success;
4153
5
    if (DP.isNearMatch())
4154
5
      return MipsAsmParser::Match_UImm16_AltRelaxed;
4155
0
    break;
4156
0
    }
4157
0
  // 'UImm16' class
4158
917
  case MCK_UImm16: {
4159
917
    DiagnosticPredicate DP(Operand.isUImm<16>());
4160
917
    if (DP.isMatch())
4161
361
      return MCTargetAsmParser::Match_Success;
4162
556
    if (DP.isNearMatch())
4163
556
      return MipsAsmParser::Match_UImm16;
4164
0
    break;
4165
0
    }
4166
0
  // 'SImm19Lsl2' class
4167
0
  case MCK_SImm19Lsl2: {
4168
0
    DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>());
4169
0
    if (DP.isMatch())
4170
0
      return MCTargetAsmParser::Match_Success;
4171
0
    if (DP.isNearMatch())
4172
0
      return MipsAsmParser::Match_SImm19_Lsl2;
4173
0
    break;
4174
0
    }
4175
0
  // 'UImm16_Relaxed' class
4176
225
  case MCK_UImm16_Relaxed: {
4177
225
    DiagnosticPredicate DP(Operand.isAnyImm<16>());
4178
225
    if (DP.isMatch())
4179
225
      return MCTargetAsmParser::Match_Success;
4180
0
    if (DP.isNearMatch())
4181
0
      return MipsAsmParser::Match_UImm16_Relaxed;
4182
0
    break;
4183
0
    }
4184
0
  // 'ConstantUImm20_0' class
4185
47
  case MCK_ConstantUImm20_0: {
4186
47
    DiagnosticPredicate DP(Operand.isConstantUImm<20, 0>());
4187
47
    if (DP.isMatch())
4188
32
      return MCTargetAsmParser::Match_Success;
4189
15
    if (DP.isNearMatch())
4190
15
      return MipsAsmParser::Match_UImm20_0;
4191
0
    break;
4192
0
    }
4193
0
  // 'ConstantUImm26_0' class
4194
0
  case MCK_ConstantUImm26_0: {
4195
0
    DiagnosticPredicate DP(Operand.isConstantUImm<26, 0>());
4196
0
    if (DP.isMatch())
4197
0
      return MCTargetAsmParser::Match_Success;
4198
0
    if (DP.isNearMatch())
4199
0
      return MipsAsmParser::Match_UImm26_0;
4200
0
    break;
4201
0
    }
4202
0
  // 'SImm32' class
4203
198
  case MCK_SImm32: {
4204
198
    DiagnosticPredicate DP(Operand.isSImm<32>());
4205
198
    if (DP.isMatch())
4206
50
      return MCTargetAsmParser::Match_Success;
4207
148
    if (DP.isNearMatch())
4208
148
      return MipsAsmParser::Match_SImm32;
4209
0
    break;
4210
0
    }
4211
0
  // 'SImm32_Relaxed' class
4212
2.24k
  case MCK_SImm32_Relaxed: {
4213
2.24k
    DiagnosticPredicate DP(Operand.isAnyImm<33>());
4214
2.24k
    if (DP.isMatch())
4215
1.02k
      return MCTargetAsmParser::Match_Success;
4216
1.21k
    if (DP.isNearMatch())
4217
1.21k
      return MipsAsmParser::Match_SImm32_Relaxed;
4218
0
    break;
4219
0
    }
4220
0
  // 'UImm32_Coerced' class
4221
209
  case MCK_UImm32_Coerced: {
4222
209
    DiagnosticPredicate DP(Operand.isSImm<33>());
4223
209
    if (DP.isMatch())
4224
206
      return MCTargetAsmParser::Match_Success;
4225
3
    if (DP.isNearMatch())
4226
3
      return MipsAsmParser::Match_UImm32_Coerced;
4227
0
    break;
4228
0
    }
4229
33.2k
  } // end switch (Kind)
4230
33.2k
4231
33.2k
  if (Operand.isReg()) {
4232
251
    MatchClassKind OpKind;
4233
251
    switch (Operand.getReg()) {
4234
251
    
default: OpKind = InvalidMatchClass; break0
;
4235
251
    case Mips::ZERO: OpKind = MCK_GPR32ZERO; break;
4236
251
    
case Mips::AT: OpKind = MCK_GPR32NONZERO; break0
;
4237
251
    
case Mips::V0: OpKind = MCK_Reg11; break0
;
4238
251
    
case Mips::V1: OpKind = MCK_Reg11; break0
;
4239
251
    
case Mips::A0: OpKind = MCK_GPRMM16MovePPairFirst; break0
;
4240
251
    
case Mips::A1: OpKind = MCK_Reg13; break0
;
4241
251
    
case Mips::A2: OpKind = MCK_Reg13; break0
;
4242
251
    
case Mips::A3: OpKind = MCK_Reg14; break0
;
4243
251
    
case Mips::T0: OpKind = MCK_GPR32NONZERO; break0
;
4244
251
    
case Mips::T1: OpKind = MCK_GPR32NONZERO; break0
;
4245
251
    
case Mips::T2: OpKind = MCK_GPR32NONZERO; break0
;
4246
251
    
case Mips::T3: OpKind = MCK_GPR32NONZERO; break0
;
4247
251
    
case Mips::T4: OpKind = MCK_GPR32NONZERO; break0
;
4248
251
    
case Mips::T5: OpKind = MCK_GPR32NONZERO; break0
;
4249
251
    
case Mips::T6: OpKind = MCK_GPR32NONZERO; break0
;
4250
251
    
case Mips::T7: OpKind = MCK_GPR32NONZERO; break0
;
4251
251
    
case Mips::S0: OpKind = MCK_Reg9; break0
;
4252
251
    
case Mips::S1: OpKind = MCK_Reg11; break0
;
4253
251
    
case Mips::S2: OpKind = MCK_Reg10; break0
;
4254
251
    
case Mips::S3: OpKind = MCK_Reg10; break0
;
4255
251
    
case Mips::S4: OpKind = MCK_Reg10; break0
;
4256
251
    
case Mips::S5: OpKind = MCK_GPRMM16MovePPairSecond; break0
;
4257
251
    
case Mips::S6: OpKind = MCK_GPRMM16MovePPairSecond; break0
;
4258
251
    
case Mips::S7: OpKind = MCK_GPR32NONZERO; break0
;
4259
251
    
case Mips::T8: OpKind = MCK_GPR32NONZERO; break0
;
4260
251
    
case Mips::T9: OpKind = MCK_GPR32NONZERO; break0
;
4261
251
    
case Mips::K0: OpKind = MCK_GPR32NONZERO; break0
;
4262
251
    
case Mips::K1: OpKind = MCK_GPR32NONZERO; break0
;
4263
251
    
case Mips::GP: OpKind = MCK_GP32; break0
;
4264
251
    
case Mips::SP: OpKind = MCK_CPUSPReg; break0
;
4265
251
    
case Mips::FP: OpKind = MCK_GPR32NONZERO; break0
;
4266
251
    
case Mips::RA: OpKind = MCK_CPURAReg; break0
;
4267
251
    
case Mips::ZERO_64: OpKind = MCK_Reg19; break0
;
4268
251
    
case Mips::AT_64: OpKind = MCK_Reg24; break0
;
4269
251
    
case Mips::V0_64: OpKind = MCK_Reg30; break0
;
4270
251
    
case Mips::V1_64: OpKind = MCK_Reg30; break0
;
4271
251
    
case Mips::A0_64: OpKind = MCK_Reg31; break0
;
4272
251
    
case Mips::A1_64: OpKind = MCK_Reg32; break0
;
4273
251
    
case Mips::A2_64: OpKind = MCK_Reg32; break0
;
4274
251
    
case Mips::A3_64: OpKind = MCK_Reg33; break0
;
4275
251
    
case Mips::T0_64: OpKind = MCK_Reg24; break0
;
4276
251
    
case Mips::T1_64: OpKind = MCK_Reg24; break0
;
4277
251
    
case Mips::T2_64: OpKind = MCK_Reg24; break0
;
4278
251
    
case Mips::T3_64: OpKind = MCK_Reg24; break0
;
4279
251
    
case Mips::T4_64: OpKind = MCK_Reg24; break0
;
4280
251
    
case Mips::T5_64: OpKind = MCK_Reg24; break0
;
4281
251
    
case Mips::T6_64: OpKind = MCK_Reg24; break0
;
4282
251
    
case Mips::T7_64: OpKind = MCK_Reg24; break0
;
4283
251
    
case Mips::S0_64: OpKind = MCK_Reg28; break0
;
4284
251
    
case Mips::S1_64: OpKind = MCK_Reg30; break0
;
4285
251
    
case Mips::S2_64: OpKind = MCK_Reg29; break0
;
4286
251
    
case Mips::S3_64: OpKind = MCK_Reg29; break0
;
4287
251
    
case Mips::S4_64: OpKind = MCK_Reg29; break0
;
4288
251
    
case Mips::S5_64: OpKind = MCK_Reg34; break0
;
4289
251
    
case Mips::S6_64: OpKind = MCK_Reg34; break0
;
4290
251
    
case Mips::S7_64: OpKind = MCK_Reg24; break0
;
4291
251
    
case Mips::T8_64: OpKind = MCK_Reg24; break0
;
4292
251
    
case Mips::T9_64: OpKind = MCK_Reg24; break0
;
4293
251
    
case Mips::K0_64: OpKind = MCK_Reg24; break0
;
4294
251
    
case Mips::K1_64: OpKind = MCK_Reg24; break0
;
4295
251
    
case Mips::GP_64: OpKind = MCK_GP64; break0
;
4296
251
    
case Mips::SP_64: OpKind = MCK_SP64; break0
;
4297
251
    
case Mips::FP_64: OpKind = MCK_Reg24; break0
;
4298
251
    
case Mips::RA_64: OpKind = MCK_Reg37; break0
;
4299
251
    
case Mips::F0: OpKind = MCK_FGR32; break0
;
4300
251
    
case Mips::F1: OpKind = MCK_Reg39; break0
;
4301
251
    
case Mips::F2: OpKind = MCK_FGR32; break0
;
4302
251
    
case Mips::F3: OpKind = MCK_Reg39; break0
;
4303
251
    
case Mips::F4: OpKind = MCK_FGR32; break0
;
4304
251
    
case Mips::F5: OpKind = MCK_Reg39; break0
;
4305
251
    
case Mips::F6: OpKind = MCK_FGR32; break0
;
4306
251
    
case Mips::F7: OpKind = MCK_Reg39; break0
;
4307
251
    
case Mips::F8: OpKind = MCK_FGR32; break0
;
4308
251
    
case Mips::F9: OpKind = MCK_Reg39; break0
;
4309
251
    
case Mips::F10: OpKind = MCK_FGR32; break0
;
4310
251
    
case Mips::F11: OpKind = MCK_Reg39; break0
;
4311
251
    
case Mips::F12: OpKind = MCK_FGR32; break0
;
4312
251
    
case Mips::F13: OpKind = MCK_Reg39; break0
;
4313
251
    
case Mips::F14: OpKind = MCK_FGR32; break0
;
4314
251
    
case Mips::F15: OpKind = MCK_Reg39; break0
;
4315
251
    
case Mips::F16: OpKind = MCK_FGR32; break0
;
4316
251
    
case Mips::F17: OpKind = MCK_Reg39; break0
;
4317
251
    
case Mips::F18: OpKind = MCK_FGR32; break0
;
4318
251
    
case Mips::F19: OpKind = MCK_Reg39; break0
;
4319
251
    
case Mips::F20: OpKind = MCK_FGR32; break0
;
4320
251
    
case Mips::F21: OpKind = MCK_Reg39; break0
;
4321
251
    
case Mips::F22: OpKind = MCK_FGR32; break0
;
4322
251
    
case Mips::F23: OpKind = MCK_Reg39; break0
;
4323
251
    
case Mips::F24: OpKind = MCK_FGR32; break0
;
4324
251
    
case Mips::F25: OpKind = MCK_Reg39; break0
;
4325
251
    
case Mips::F26: OpKind = MCK_FGR32; break0
;
4326
251
    
case Mips::F27: OpKind = MCK_Reg39; break0
;
4327
251
    
case Mips::F28: OpKind = MCK_FGR32; break0
;
4328
251
    
case Mips::F29: OpKind = MCK_Reg39; break0
;
4329
251
    
case Mips::F30: OpKind = MCK_FGR32; break0
;
4330
251
    
case Mips::F31: OpKind = MCK_Reg39; break0
;
4331
251
    
case Mips::F_HI0: OpKind = MCK_FGRH32; break0
;
4332
251
    
case Mips::F_HI1: OpKind = MCK_Reg42; break0
;
4333
251
    
case Mips::F_HI2: OpKind = MCK_FGRH32; break0
;
4334
251
    
case Mips::F_HI3: OpKind = MCK_Reg42; break0
;
4335
251
    
case Mips::F_HI4: OpKind = MCK_FGRH32; break0
;
4336
251
    
case Mips::F_HI5: OpKind = MCK_Reg42; break0
;
4337
251
    
case Mips::F_HI6: OpKind = MCK_FGRH32; break0
;
4338
251
    
case Mips::F_HI7: OpKind = MCK_Reg42; break0
;
4339
251
    
case Mips::F_HI8: OpKind = MCK_FGRH32; break0
;
4340
251
    
case Mips::F_HI9: OpKind = MCK_Reg42; break0
;
4341
251
    
case Mips::F_HI10: OpKind = MCK_FGRH32; break0
;
4342
251
    
case Mips::F_HI11: OpKind = MCK_Reg42; break0
;
4343
251
    
case Mips::F_HI12: OpKind = MCK_FGRH32; break0
;
4344
251
    
case Mips::F_HI13: OpKind = MCK_Reg42; break0
;
4345
251
    
case Mips::F_HI14: OpKind = MCK_FGRH32; break0
;
4346
251
    
case Mips::F_HI15: OpKind = MCK_Reg42; break0
;
4347
251
    
case Mips::F_HI16: OpKind = MCK_FGRH32; break0
;
4348
251
    
case Mips::F_HI17: OpKind = MCK_Reg42; break0
;
4349
251
    
case Mips::F_HI18: OpKind = MCK_FGRH32; break0
;
4350
251
    
case Mips::F_HI19: OpKind = MCK_Reg42; break0
;
4351
251
    
case Mips::F_HI20: OpKind = MCK_FGRH32; break0
;
4352
251
    
case Mips::F_HI21: OpKind = MCK_Reg42; break0
;
4353
251
    
case Mips::F_HI22: OpKind = MCK_FGRH32; break0
;
4354
251
    
case Mips::F_HI23: OpKind = MCK_Reg42; break0
;
4355
251
    
case Mips::F_HI24: OpKind = MCK_FGRH32; break0
;
4356
251
    
case Mips::F_HI25: OpKind = MCK_Reg42; break0
;
4357
251
    
case Mips::F_HI26: OpKind = MCK_FGRH32; break0
;
4358
251
    
case Mips::F_HI27: OpKind = MCK_Reg42; break0
;
4359
251
    
case Mips::F_HI28: OpKind = MCK_FGRH32; break0
;
4360
251
    
case Mips::F_HI29: OpKind = MCK_Reg42; break0
;
4361
251
    
case Mips::F_HI30: OpKind = MCK_FGRH32; break0
;
4362
251
    
case Mips::F_HI31: OpKind = MCK_Reg42; break0
;
4363
251
    
case Mips::D0: OpKind = MCK_AFGR64; break0
;
4364
251
    
case Mips::D1: OpKind = MCK_Reg44; break0
;
4365
251
    
case Mips::D2: OpKind = MCK_AFGR64; break0
;
4366
251
    
case Mips::D3: OpKind = MCK_Reg44; break0
;
4367
251
    
case Mips::D4: OpKind = MCK_AFGR64; break0
;
4368
251
    
case Mips::D5: OpKind = MCK_Reg44; break0
;
4369
251
    
case Mips::D6: OpKind = MCK_AFGR64; break0
;
4370
251
    
case Mips::D7: OpKind = MCK_Reg44; break0
;
4371
251
    
case Mips::D8: OpKind = MCK_AFGR64; break0
;
4372
251
    
case Mips::D9: OpKind = MCK_Reg44; break0
;
4373
251
    
case Mips::D10: OpKind = MCK_AFGR64; break0
;
4374
251
    
case Mips::D11: OpKind = MCK_Reg44; break0
;
4375
251
    
case Mips::D12: OpKind = MCK_AFGR64; break0
;
4376
251
    
case Mips::D13: OpKind = MCK_Reg44; break0
;
4377
251
    
case Mips::D14: OpKind = MCK_AFGR64; break0
;
4378
251
    
case Mips::D15: OpKind = MCK_Reg44; break0
;
4379
251
    
case Mips::D0_64: OpKind = MCK_FGR64; break0
;
4380
251
    
case Mips::D1_64: OpKind = MCK_Reg47; break0
;
4381
251
    
case Mips::D2_64: OpKind = MCK_FGR64; break0
;
4382
251
    
case Mips::D3_64: OpKind = MCK_Reg47; break0
;
4383
251
    
case Mips::D4_64: OpKind = MCK_FGR64; break0
;
4384
251
    
case Mips::D5_64: OpKind = MCK_Reg47; break0
;
4385
251
    
case Mips::D6_64: OpKind = MCK_FGR64; break0
;
4386
251
    
case Mips::D7_64: OpKind = MCK_Reg47; break0
;
4387
251
    
case Mips::D8_64: OpKind = MCK_FGR64; break0
;
4388
251
    
case Mips::D9_64: OpKind = MCK_Reg47; break0
;
4389
251
    
case Mips::D10_64: OpKind = MCK_FGR64; break0
;
4390
251
    
case Mips::D11_64: OpKind = MCK_Reg47; break0
;
4391
251
    
case Mips::D12_64: OpKind = MCK_FGR64; break0
;
4392
251
    
case Mips::D13_64: OpKind = MCK_Reg47; break0
;
4393
251
    
case Mips::D14_64: OpKind = MCK_FGR64; break0
;
4394
251
    
case Mips::D15_64: OpKind = MCK_Reg47; break0
;
4395
251
    
case Mips::D16_64: OpKind = MCK_FGR64; break0
;
4396
251
    
case Mips::D17_64: OpKind = MCK_Reg47; break0
;
4397
251
    
case Mips::D18_64: OpKind = MCK_FGR64; break0
;
4398
251
    
case Mips::D19_64: OpKind = MCK_Reg47; break0
;
4399
251
    
case Mips::D20_64: OpKind = MCK_FGR64; break0
;
4400
251
    
case Mips::D21_64: OpKind = MCK_Reg47; break0
;
4401
251
    
case Mips::D22_64: OpKind = MCK_FGR64; break0
;
4402
251
    
case Mips::D23_64: OpKind = MCK_Reg47; break0
;
4403
251
    
case Mips::D24_64: OpKind = MCK_FGR64; break0
;
4404
251
    
case Mips::D25_64: OpKind = MCK_Reg47; break0
;
4405
251
    
case Mips::D26_64: OpKind = MCK_FGR64; break0
;
4406
251
    
case Mips::D27_64: OpKind = MCK_Reg47; break0
;
4407
251
    
case Mips::D28_64: OpKind = MCK_FGR64; break0
;
4408
251
    
case Mips::D29_64: OpKind = MCK_Reg47; break0
;
4409
251
    
case Mips::D30_64: OpKind = MCK_FGR64; break0
;
4410
251
    
case Mips::D31_64: OpKind = MCK_Reg47; break0
;
4411
251
    
case Mips::W0: OpKind = MCK_MSA128WEvens; break0
;
4412
251
    
case Mips::W1: OpKind = MCK_Reg50; break0
;
4413
251
    
case Mips::W2: OpKind = MCK_MSA128WEvens; break0
;
4414
251
    
case Mips::W3: OpKind = MCK_Reg50; break0
;
4415
251
    
case Mips::W4: OpKind = MCK_MSA128WEvens; break0
;
4416
251
    
case Mips::W5: OpKind = MCK_Reg50; break0
;
4417
251
    
case Mips::W6: OpKind = MCK_MSA128WEvens; break0
;
4418
251
    
case Mips::W7: OpKind = MCK_Reg50; break0
;
4419
251
    
case Mips::W8: OpKind = MCK_MSA128WEvens; break0
;
4420
251
    
case Mips::W9: OpKind = MCK_Reg50; break0
;
4421
251
    
case Mips::W10: OpKind = MCK_MSA128WEvens; break0
;
4422
251
    
case Mips::W11: OpKind = MCK_Reg50; break0
;
4423
251
    
case Mips::W12: OpKind = MCK_MSA128WEvens; break0
;
4424
251
    
case Mips::W13: OpKind = MCK_Reg50; break0
;
4425
251
    
case Mips::W14: OpKind = MCK_MSA128WEvens; break0
;
4426
251
    
case Mips::W15: OpKind = MCK_Reg50; break0
;
4427
251
    
case Mips::W16: OpKind = MCK_MSA128WEvens; break0
;
4428
251
    
case Mips::W17: OpKind = MCK_Reg50; break0
;
4429
251
    
case Mips::W18: OpKind = MCK_MSA128WEvens; break0
;
4430
251
    
case Mips::W19: OpKind = MCK_Reg50; break0
;
4431
251
    
case Mips::W20: OpKind = MCK_MSA128WEvens; break0
;
4432
251
    
case Mips::W21: OpKind = MCK_Reg50; break0
;
4433
251
    
case Mips::W22: OpKind = MCK_MSA128WEvens; break0
;
4434
251
    
case Mips::W23: OpKind = MCK_Reg50; break0
;
4435
251
    
case Mips::W24: OpKind = MCK_MSA128WEvens; break0
;
4436
251
    
case Mips::W25: OpKind = MCK_Reg50; break0
;
4437
251
    
case Mips::W26: OpKind = MCK_MSA128WEvens; break0
;
4438
251
    
case Mips::W27: OpKind = MCK_Reg50; break0
;
4439
251
    
case Mips::W28: OpKind = MCK_MSA128WEvens; break0
;
4440
251
    
case Mips::W29: OpKind = MCK_Reg50; break0
;
4441
251
    
case Mips::W30: OpKind = MCK_MSA128WEvens; break0
;
4442
251
    
case Mips::W31: OpKind = MCK_Reg50; break0
;
4443
251
    
case Mips::HI0: OpKind = MCK_HI32; break0
;
4444
251
    
case Mips::HI1: OpKind = MCK_HI32DSP; break0
;
4445
251
    
case Mips::HI2: OpKind = MCK_HI32DSP; break0
;
4446
251
    
case Mips::HI3: OpKind = MCK_HI32DSP; break0
;
4447
251
    
case Mips::LO0: OpKind = MCK_LO32; break0
;
4448
251
    
case Mips::LO1: OpKind = MCK_LO32DSP; break0
;
4449
251
    
case Mips::LO2: OpKind = MCK_LO32DSP; break0
;
4450
251
    
case Mips::LO3: OpKind = MCK_LO32DSP; break0
;
4451
251
    
case Mips::HI0_64: OpKind = MCK_HI64; break0
;
4452
251
    
case Mips::LO0_64: OpKind = MCK_LO64; break0
;
4453
251
    
case Mips::FCR0: OpKind = MCK_CCR; break0
;
4454
251
    
case Mips::FCR1: OpKind = MCK_CCR; break0
;
4455
251
    
case Mips::FCR2: OpKind = MCK_CCR; break0
;
4456
251
    
case Mips::FCR3: OpKind = MCK_CCR; break0
;
4457
251
    
case Mips::FCR4: OpKind = MCK_CCR; break0
;
4458
251
    
case Mips::FCR5: OpKind = MCK_CCR; break0
;
4459
251
    
case Mips::FCR6: OpKind = MCK_CCR; break0
;
4460
251
    
case Mips::FCR7: OpKind = MCK_CCR; break0
;
4461
251
    
case Mips::FCR8: OpKind = MCK_CCR; break0
;
4462
251
    
case Mips::FCR9: OpKind = MCK_CCR; break0
;
4463
251
    
case Mips::FCR10: OpKind = MCK_CCR; break0
;
4464
251
    
case Mips::FCR11: OpKind = MCK_CCR; break0
;
4465
251
    
case Mips::FCR12: OpKind = MCK_CCR; break0
;
4466
251
    
case Mips::FCR13: OpKind = MCK_CCR; break0
;
4467
251
    
case Mips::FCR14: OpKind = MCK_CCR; break0
;
4468
251
    
case Mips::FCR15: OpKind = MCK_CCR; break0
;
4469
251
    
case Mips::FCR16: OpKind = MCK_CCR; break0
;
4470
251
    
case Mips::FCR17: OpKind = MCK_CCR; break0
;
4471
251
    
case Mips::FCR18: OpKind = MCK_CCR; break0
;
4472
251
    
case Mips::FCR19: OpKind = MCK_CCR; break0
;
4473
251
    
case Mips::FCR20: OpKind = MCK_CCR; break0
;
4474
251
    
case Mips::FCR21: OpKind = MCK_CCR; break0
;
4475
251
    
case Mips::FCR22: OpKind = MCK_CCR; break0
;
4476
251
    
case Mips::FCR23: OpKind = MCK_CCR; break0
;
4477
251
    
case Mips::FCR24: OpKind = MCK_CCR; break0
;
4478
251
    
case Mips::FCR25: OpKind = MCK_CCR; break0
;
4479
251
    
case Mips::FCR26: OpKind = MCK_CCR; break0
;
4480
251
    
case Mips::FCR27: OpKind = MCK_CCR; break0
;
4481
251
    
case Mips::FCR28: OpKind = MCK_CCR; break0
;
4482
251
    
case Mips::FCR29: OpKind = MCK_CCR; break0
;
4483
251
    
case Mips::FCR30: OpKind = MCK_CCR; break0
;
4484
251
    
case Mips::FCR31: OpKind = MCK_CCR; break0
;
4485
251
    
case Mips::FCC0: OpKind = MCK_FCC; break0
;
4486
251
    
case Mips::FCC1: OpKind = MCK_FCC; break0
;
4487
251
    
case Mips::FCC2: OpKind = MCK_FCC; break0
;
4488
251
    
case Mips::FCC3: OpKind = MCK_FCC; break0
;
4489
251
    
case Mips::FCC4: OpKind = MCK_FCC; break0
;
4490
251
    
case Mips::FCC5: OpKind = MCK_FCC; break0
;
4491
251
    
case Mips::FCC6: OpKind = MCK_FCC; break0
;
4492
251
    
case Mips::FCC7: OpKind = MCK_FCC; break0
;
4493
251
    
case Mips::COP00: OpKind = MCK_COP0; break0
;
4494
251
    
case Mips::COP01: OpKind = MCK_COP0; break0
;
4495
251
    
case Mips::COP02: OpKind = MCK_COP0; break0
;
4496
251
    
case Mips::COP03: OpKind = MCK_COP0; break0
;
4497
251
    
case Mips::COP04: OpKind = MCK_COP0; break0
;
4498
251
    
case Mips::COP05: OpKind = MCK_COP0; break0
;
4499
251
    
case Mips::COP06: OpKind = MCK_COP0; break0
;
4500
251
    
case Mips::COP07: OpKind = MCK_COP0; break0
;
4501
251
    
case Mips::COP08: OpKind = MCK_COP0; break0
;
4502
251
    
case Mips::COP09: OpKind = MCK_COP0; break0
;
4503
251
    
case Mips::COP010: OpKind = MCK_COP0; break0
;
4504
251
    
case Mips::COP011: OpKind = MCK_COP0; break0
;
4505
251
    
case Mips::COP012: OpKind = MCK_COP0; break0
;
4506
251
    
case Mips::COP013: OpKind = MCK_COP0; break0
;
4507
251
    
case Mips::COP014: OpKind = MCK_COP0; break0
;
4508
251
    
case Mips::COP015: OpKind = MCK_COP0; break0
;
4509
251
    
case Mips::COP016: OpKind = MCK_COP0; break0
;
4510
251
    
case Mips::COP017: OpKind = MCK_COP0; break0
;
4511
251
    
case Mips::COP018: OpKind = MCK_COP0; break0
;
4512
251
    
case Mips::COP019: OpKind = MCK_COP0; break0
;
4513
251
    
case Mips::COP020: OpKind = MCK_COP0; break0
;
4514
251
    
case Mips::COP021: OpKind = MCK_COP0; break0
;
4515
251
    
case Mips::COP022: OpKind = MCK_COP0; break0
;
4516
251
    
case Mips::COP023: OpKind = MCK_COP0; break0
;
4517
251
    
case Mips::COP024: OpKind = MCK_COP0; break0
;
4518
251
    
case Mips::COP025: OpKind = MCK_COP0; break0
;
4519
251
    
case Mips::COP026: OpKind = MCK_COP0; break0
;
4520
251
    
case Mips::COP027: OpKind = MCK_COP0; break0
;
4521
251
    
case Mips::COP028: OpKind = MCK_COP0; break0
;