Coverage Report

Created: 2018-09-25 17:16

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Mips/MipsGenAsmMatcher.inc
Line
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Source (jump to first uncovered line)
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Assembly Matcher Source Fragment                                           *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_ASSEMBLER_HEADER
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#undef GET_ASSEMBLER_HEADER
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  // This should be included into the middle of the declaration of
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  // your subclasses implementation of MCTargetAsmParser.
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  uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;
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  void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
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                       const OperandVector &Operands);
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  void convertToMapAndConstraints(unsigned Kind,
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                           const OperandVector &Operands) override;
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  unsigned MatchInstructionImpl(const OperandVector &Operands,
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                                MCInst &Inst,
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                                uint64_t &ErrorInfo,
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                                bool matchingInlineAsm,
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                                unsigned VariantID = 0);
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  OperandMatchResultTy MatchOperandParserImpl(
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    OperandVector &Operands,
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    StringRef Mnemonic,
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    bool ParseForAllFeatures = false);
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  OperandMatchResultTy tryCustomParseOperand(
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    OperandVector &Operands,
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    unsigned MCK);
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#endif // GET_ASSEMBLER_HEADER_INFO
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#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
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#undef GET_OPERAND_DIAGNOSTIC_TYPES
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  Match_Immz,
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  Match_MemSImm10,
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  Match_MemSImm10Lsl1,
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  Match_MemSImm10Lsl2,
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  Match_MemSImm10Lsl3,
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  Match_MemSImm11,
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  Match_MemSImm12,
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  Match_MemSImm16,
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  Match_MemSImm9,
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  Match_MemSImmPtr,
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  Match_SImm10_0,
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  Match_SImm10_Lsl1,
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  Match_SImm10_Lsl2,
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  Match_SImm10_Lsl3,
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  Match_SImm11_0,
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  Match_SImm16,
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  Match_SImm16_Relaxed,
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  Match_SImm19_Lsl2,
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  Match_SImm32,
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  Match_SImm32_Relaxed,
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  Match_SImm4_0,
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  Match_SImm5_0,
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  Match_SImm6_0,
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  Match_SImm7_Lsl2,
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  Match_SImm9_0,
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  Match_UImm10_0,
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  Match_UImm16,
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  Match_UImm16_AltRelaxed,
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  Match_UImm16_Relaxed,
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  Match_UImm1_0,
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  Match_UImm20_0,
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  Match_UImm26_0,
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  Match_UImm2_0,
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  Match_UImm2_1,
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  Match_UImm32_Coerced,
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  Match_UImm3_0,
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  Match_UImm4_0,
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  Match_UImm5_0,
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  Match_UImm5_0_Report_UImm6,
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  Match_UImm5_1,
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  Match_UImm5_32,
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  Match_UImm5_33,
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  Match_UImm5_Lsl2,
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  Match_UImm6_0,
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  Match_UImm6_Lsl2,
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  Match_UImm7_0,
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  Match_UImm7_N1,
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  Match_UImm8_0,
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  Match_UImmRange2_64,
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  END_OPERAND_DIAGNOSTIC_TYPES
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#endif // GET_OPERAND_DIAGNOSTIC_TYPES
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#ifdef GET_REGISTER_MATCHER
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#undef GET_REGISTER_MATCHER
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// Flags for subtarget features that participate in instruction matching.
95
enum SubtargetFeatureFlag : uint64_t {
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  Feature_HasMips2 = (1ULL << 10),
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  Feature_HasMips3_32 = (1ULL << 16),
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  Feature_HasMips3_32r2 = (1ULL << 17),
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  Feature_HasMips3 = (1ULL << 11),
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  Feature_NotMips3 = (1ULL << 44),
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  Feature_HasMips4_32 = (1ULL << 18),
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  Feature_NotMips4_32 = (1ULL << 46),
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  Feature_HasMips4_32r2 = (1ULL << 19),
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  Feature_HasMips5_32r2 = (1ULL << 20),
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  Feature_HasMips32 = (1ULL << 12),
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  Feature_HasMips32r2 = (1ULL << 13),
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  Feature_HasMips32r5 = (1ULL << 14),
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  Feature_HasMips32r6 = (1ULL << 15),
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  Feature_NotMips32r6 = (1ULL << 45),
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  Feature_IsGP64bit = (1ULL << 31),
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  Feature_IsGP32bit = (1ULL << 30),
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  Feature_IsPTR64bit = (1ULL << 35),
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  Feature_IsPTR32bit = (1ULL << 34),
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  Feature_HasMips64 = (1ULL << 21),
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  Feature_NotMips64 = (1ULL << 47),
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  Feature_HasMips64r2 = (1ULL << 22),
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  Feature_HasMips64r5 = (1ULL << 23),
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  Feature_HasMips64r6 = (1ULL << 24),
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  Feature_NotMips64r6 = (1ULL << 48),
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  Feature_InMips16Mode = (1ULL << 28),
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  Feature_NotInMips16Mode = (1ULL << 43),
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  Feature_HasCnMips = (1ULL << 1),
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  Feature_NotCnMips = (1ULL << 40),
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  Feature_IsSym32 = (1ULL << 37),
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  Feature_IsSym64 = (1ULL << 38),
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  Feature_HasStdEnc = (1ULL << 25),
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  Feature_InMicroMips = (1ULL << 27),
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  Feature_NotInMicroMips = (1ULL << 42),
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  Feature_HasEVA = (1ULL << 5),
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  Feature_HasMSA = (1ULL << 7),
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  Feature_HasMadd4 = (1ULL << 9),
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  Feature_HasMT = (1ULL << 8),
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  Feature_UseIndirectJumpsHazard = (1ULL << 49),
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  Feature_NoIndirectJumpGuards = (1ULL << 39),
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  Feature_HasCRC = (1ULL << 0),
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  Feature_HasVirt = (1ULL << 26),
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  Feature_HasGINV = (1ULL << 6),
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  Feature_IsFP64bit = (1ULL << 29),
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  Feature_NotFP64bit = (1ULL << 41),
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  Feature_IsSingleFloat = (1ULL << 36),
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  Feature_IsNotSingleFloat = (1ULL << 32),
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  Feature_IsNotSoftFloat = (1ULL << 33),
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  Feature_HasDSP = (1ULL << 2),
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  Feature_HasDSPR2 = (1ULL << 3),
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  Feature_HasDSPR3 = (1ULL << 4),
146
  Feature_None = 0
147
};
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149
#endif // GET_REGISTER_MATCHER
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152
#ifdef GET_SUBTARGET_FEATURE_NAME
153
#undef GET_SUBTARGET_FEATURE_NAME
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155
// User-level names for subtarget features that participate in
156
// instruction matching.
157
static const char *getSubtargetFeatureName(uint64_t Val) {
158
  switch(Val) {
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  case Feature_HasMips2: return "";
160
  case Feature_HasMips3_32: return "";
161
  case Feature_HasMips3_32r2: return "";
162
  case Feature_HasMips3: return "";
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  case Feature_NotMips3: return "";
164
  case Feature_HasMips4_32: return "";
165
  case Feature_NotMips4_32: return "";
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  case Feature_HasMips4_32r2: return "";
167
  case Feature_HasMips5_32r2: return "";
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  case Feature_HasMips32: return "";
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  case Feature_HasMips32r2: return "";
170
  case Feature_HasMips32r5: return "";
171
  case Feature_HasMips32r6: return "";
172
  case Feature_NotMips32r6: return "";
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  case Feature_IsGP64bit: return "";
174
  case Feature_IsGP32bit: return "";
175
  case Feature_IsPTR64bit: return "";
176
  case Feature_IsPTR32bit: return "";
177
  case Feature_HasMips64: return "";
178
  case Feature_NotMips64: return "";
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  case Feature_HasMips64r2: return "";
180
  case Feature_HasMips64r5: return "";
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  case Feature_HasMips64r6: return "";
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  case Feature_NotMips64r6: return "";
183
  case Feature_InMips16Mode: return "";
184
  case Feature_NotInMips16Mode: return "";
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  case Feature_HasCnMips: return "";
186
  case Feature_NotCnMips: return "";
187
  case Feature_IsSym32: return "";
188
  case Feature_IsSym64: return "";
189
  case Feature_HasStdEnc: return "";
190
  case Feature_InMicroMips: return "";
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  case Feature_NotInMicroMips: return "";
192
  case Feature_HasEVA: return "";
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  case Feature_HasMSA: return "";
194
  case Feature_HasMadd4: return "";
195
  case Feature_HasMT: return "";
196
  case Feature_UseIndirectJumpsHazard: return "";
197
  case Feature_NoIndirectJumpGuards: return "";
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  case Feature_HasCRC: return "";
199
  case Feature_HasVirt: return "";
200
  case Feature_HasGINV: return "";
201
  case Feature_IsFP64bit: return "";
202
  case Feature_NotFP64bit: return "";
203
  case Feature_IsSingleFloat: return "";
204
  case Feature_IsNotSingleFloat: return "";
205
  case Feature_IsNotSoftFloat: return "";
206
  case Feature_HasDSP: return "";
207
  case Feature_HasDSPR2: return "";
208
  case Feature_HasDSPR3: return "";
209
  default: return "(unknown)";
210
  }
211
}
212
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#endif // GET_SUBTARGET_FEATURE_NAME
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#ifdef GET_MATCHER_IMPLEMENTATION
217
#undef GET_MATCHER_IMPLEMENTATION
218
219
enum {
220
  Tie0_1_1,
221
  Tie0_1_2,
222
};
223
224
static const uint8_t TiedAsmOperandTable[][3] = {
225
  /* Tie0_1_1 */ { 0, 1, 1 },
226
  /* Tie0_1_2 */ { 0, 1, 2 },
227
};
228
229
namespace {
230
enum OperatorConversionKind {
231
  CVT_Done,
232
  CVT_Reg,
233
  CVT_Tied,
234
  CVT_95_addGPR32AsmRegOperands,
235
  CVT_95_addAFGR64AsmRegOperands,
236
  CVT_95_addFGR64AsmRegOperands,
237
  CVT_95_addFGR32AsmRegOperands,
238
  CVT_95_addSImmOperands_LT_32_GT_,
239
  CVT_95_addMSA128AsmRegOperands,
240
  CVT_95_addSImmOperands_LT_16_GT_,
241
  CVT_95_Reg,
242
  CVT_95_addImmOperands,
243
  CVT_95_addGPRMM16AsmRegOperands,
244
  CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_,
245
  CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_,
246
  CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_,
247
  CVT_95_addUImmOperands_LT_16_GT_,
248
  CVT_95_addGPR64AsmRegOperands,
249
  CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_,
250
  CVT_regZERO,
251
  CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_,
252
  CVT_regFCC0,
253
  CVT_95_addFCCAsmRegOperands,
254
  CVT_95_addCOP2AsmRegOperands,
255
  CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_,
256
  CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_,
257
  CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_,
258
  CVT_imm_95_0,
259
  CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_,
260
  CVT_95_addMemOperands,
261
  CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_,
262
  CVT_95_addCCRAsmRegOperands,
263
  CVT_95_addMSACtrlAsmRegOperands,
264
  CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_,
265
  CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_,
266
  CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_,
267
  CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_,
268
  CVT_95_addGPR32NonZeroAsmRegOperands,
269
  CVT_95_addGPR32ZeroAsmRegOperands,
270
  CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_,
271
  CVT_95_addCOP0AsmRegOperands,
272
  CVT_regZERO_64,
273
  CVT_95_addACC64DSPAsmRegOperands,
274
  CVT_95_addConstantUImmOperands_LT_1_GT_,
275
  CVT_regRA,
276
  CVT_regRA_64,
277
  CVT_95_addMicroMipsMemOperands,
278
  CVT_95_addCOP3AsmRegOperands,
279
  CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_,
280
  CVT_95_addConstantUImmOperands_LT_32_GT_,
281
  CVT_95_addStrictlyAFGR64AsmRegOperands,
282
  CVT_95_addStrictlyFGR64AsmRegOperands,
283
  CVT_95_addStrictlyFGR32AsmRegOperands,
284
  CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_,
285
  CVT_95_addRegListOperands,
286
  CVT_ConvertXWPOperands,
287
  CVT_regAC0,
288
  CVT_95_addGPRMM16AsmRegMovePPairFirstOperands,
289
  CVT_95_addGPRMM16AsmRegMovePPairSecondOperands,
290
  CVT_95_addGPRMM16AsmRegMovePOperands,
291
  CVT_95_addHI32DSPAsmRegOperands,
292
  CVT_95_addLO32DSPAsmRegOperands,
293
  CVT_regS0,
294
  CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_,
295
  CVT_95_addHWRegsAsmRegOperands,
296
  CVT_95_addGPRMM16AsmRegZeroOperands,
297
  CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_,
298
  CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_,
299
  CVT_imm_95_2,
300
  CVT_imm_95_6,
301
  CVT_imm_95_4,
302
  CVT_imm_95_5,
303
  CVT_imm_95_31,
304
  CVT_NUM_CONVERTERS
305
};
306
307
enum InstructionConversionKind {
308
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1,
309
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1,
310
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1,
311
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1,
312
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1,
313
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1,
314
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
315
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2,
316
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2,
317
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
318
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
319
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1,
320
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2,
321
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1,
322
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1,
323
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2,
324
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2,
325
  Convert__SImm161_1,
326
  Convert__Reg1_0__SImm161_1,
327
  Convert__Reg1_0__SImm161_2,
328
  Convert__Reg1_0__Reg1_1__SImm161_2,
329
  Convert__Reg1_0__Tie0_1_1__SImm161_1,
330
  Convert__GPR32AsmReg1_0__Simm19_Lsl21_1,
331
  Convert__GPRMM16AsmReg1_0__Imm1_1,
332
  Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1,
333
  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2,
334
  Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1,
335
  Convert__Imm1_0,
336
  Convert__Reg1_0__Reg1_1__Reg1_2,
337
  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2,
338
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2,
339
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3,
340
  Convert__GPR32AsmReg1_0__SImm161_1,
341
  Convert__Reg1_0__Tie0_1_1__Reg1_1,
342
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1,
343
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1,
344
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2,
345
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2,
346
  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1,
347
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2,
348
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1,
349
  Convert__regZERO__regZERO__JumpTarget1_0,
350
  Convert__JumpTarget1_0,
351
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1,
352
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2,
353
  Convert__regZERO__JumpTarget1_0,
354
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1,
355
  Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2,
356
  Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2,
357
  Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2,
358
  Convert__FGR64AsmReg1_0__JumpTarget1_1,
359
  Convert__regFCC0__JumpTarget1_0,
360
  Convert__FCCAsmReg1_0__JumpTarget1_1,
361
  Convert__COP2AsmReg1_0__JumpTarget1_1,
362
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2,
363
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2,
364
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2,
365
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2,
366
  Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2,
367
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2,
368
  Convert__Reg1_0__JumpTarget1_1,
369
  Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1,
370
  Convert__GPRMM16AsmReg1_0__JumpTarget1_1,
371
  Convert__GPR32AsmReg1_0__JumpTarget1_1,
372
  Convert__GPR64AsmReg1_0__JumpTarget1_1,
373
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2,
374
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2,
375
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2,
376
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2,
377
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2,
378
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2,
379
  Convert__MSA128AsmReg1_0__JumpTarget1_1,
380
  Convert__imm_95_0__imm_95_0,
381
  Convert_NoOperands,
382
  Convert__ConstantUImm10_01_0__imm_95_0,
383
  Convert__ConstantUImm10_01_0__ConstantUImm10_01_1,
384
  Convert__ConstantUImm4_01_0,
385
  Convert__SImm161_0,
386
  Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1,
387
  Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1,
388
  Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2,
389
  Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
390
  Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1,
391
  Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
392
  Convert__MemOffsetSimm92_1__ConstantUImm5_01_0,
393
  Convert__Mem2_1__ConstantUImm5_01_0,
394
  Convert__FGR64AsmReg1_0__FGR32AsmReg1_1,
395
  Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1,
396
  Convert__FGR32AsmReg1_0__FGR64AsmReg1_1,
397
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2,
398
  Convert__GPR32AsmReg1_0__CCRAsmReg1_1,
399
  Convert__GPR32AsmReg1_0__COP2AsmReg1_1,
400
  Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1,
401
  Convert__GPR32AsmReg1_0__FGR32AsmReg1_1,
402
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2,
403
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2,
404
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3,
405
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3,
406
  Convert__Reg1_0__Reg1_1,
407
  Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
408
  Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3,
409
  Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3,
410
  Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3,
411
  Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3,
412
  Convert__CCRAsmReg1_1__GPR32AsmReg1_0,
413
  Convert__COP2AsmReg1_1__GPR32AsmReg1_0,
414
  Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1,
415
  Convert__FGR32AsmReg1_1__GPR32AsmReg1_0,
416
  Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1,
417
  Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
418
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1,
419
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2,
420
  Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2,
421
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3,
422
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2,
423
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1,
424
  Convert__GPR64AsmReg1_1__GPR64AsmReg1_2,
425
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3,
426
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3,
427
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3,
428
  Convert__regZERO,
429
  Convert__GPR32AsmReg1_0,
430
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1,
431
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1,
432
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1,
433
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1,
434
  Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1,
435
  Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1,
436
  Convert__Reg1_1__Reg1_2,
437
  Convert__GPR32AsmReg1_1__GPR32AsmReg1_2,
438
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2,
439
  Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
440
  Convert__GPR64AsmReg1_0__Imm1_1,
441
  Convert__GPR64AsmReg1_0__Mem2_1,
442
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3,
443
  Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0,
444
  Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2,
445
  Convert__GPR64AsmReg1_0__FGR64AsmReg1_1,
446
  Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0,
447
  Convert__GPR64AsmReg1_0__UImm161_1,
448
  Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2,
449
  Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0,
450
  Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2,
451
  Convert__FGR64AsmReg1_1__GPR64AsmReg1_0,
452
  Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0,
453
  Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2,
454
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2,
455
  Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0,
456
  Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1,
457
  Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
458
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0,
459
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1,
460
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1,
461
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2,
462
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1,
463
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2,
464
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2,
465
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1,
466
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1,
467
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2,
468
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3,
469
  Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2,
470
  Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2,
471
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1,
472
  Convert__MSA128AsmReg1_0__GPR32AsmReg1_1,
473
  Convert__MSA128AsmReg1_0__GPR64AsmReg1_1,
474
  Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2,
475
  Convert__GPR32AsmReg1_0__ConstantUImm2_01_1,
476
  Convert__imm_95_0,
477
  Convert__ConstantUImm10_01_0,
478
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1,
479
  Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2,
480
  Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2,
481
  Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2,
482
  Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2,
483
  Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1,
484
  Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
485
  Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
486
  Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
487
  Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
488
  Convert__regRA__GPR32AsmReg1_0,
489
  Convert__regRA_64__GPR64AsmReg1_0,
490
  Convert__Reg1_0,
491
  Convert__GPR32AsmReg1_0__imm_95_0,
492
  Convert__GPR64AsmReg1_0__imm_95_0,
493
  Convert__regZERO__GPR32AsmReg1_0,
494
  Convert__GPR64AsmReg1_0,
495
  Convert__regZERO_64__GPR64AsmReg1_0,
496
  Convert__UImm5Lsl21_0,
497
  Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1,
498
  Convert__FGR64AsmReg1_0__MemOffsetSimm162_1,
499
  Convert__FGR32AsmReg1_0__MemOffsetSimm162_1,
500
  Convert__GPR32AsmReg1_0__Imm1_1,
501
  Convert__GPR32AsmReg1_0__Mem2_1,
502
  Convert__GPR32AsmReg1_0__MemOffsetSimm162_1,
503
  Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1,
504
  Convert__GPR32AsmReg1_0__MemOffsetSimm92_1,
505
  Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1,
506
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
507
  Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1,
508
  Convert__MSA128AsmReg1_0__MemOffsetSimm102_1,
509
  Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1,
510
  Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1,
511
  Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1,
512
  Convert__COP2AsmReg1_0__MemOffsetSimm112_1,
513
  Convert__COP2AsmReg1_0__MemOffsetSimm162_1,
514
  Convert__COP3AsmReg1_0__Mem2_1,
515
  Convert__MSA128AsmReg1_0__ConstantSImm10_01_1,
516
  Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1,
517
  Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
518
  Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
519
  Convert__GPR32AsmReg1_0__UImm32_Coerced1_1,
520
  Convert__StrictlyAFGR64AsmReg1_0__Imm1_1,
521
  Convert__StrictlyFGR64AsmReg1_0__Imm1_1,
522
  Convert__StrictlyFGR32AsmReg1_0__Imm1_1,
523
  Convert__GPRMM16AsmReg1_0__UImm7_N11_1,
524
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3,
525
  Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3,
526
  Convert__GPR32AsmReg1_0__UImm161_1,
527
  Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1,
528
  Convert__Reg1_0__Imm1_1__imm_95_0,
529
  Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1,
530
  Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1,
531
  Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1,
532
  Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1,
533
  Convert__RegList1_0__Mem2_1,
534
  Convert__RegList161_0__MemOffsetUimm42_1,
535
  ConvertCustom_ConvertXWPOperands,
536
  Convert__GPR32AsmReg1_0__MemOffsetSimm122_1,
537
  Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
538
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3,
539
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3,
540
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3,
541
  Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2,
542
  Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2,
543
  Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0,
544
  Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2,
545
  Convert__GPR32AsmReg1_0__FGR64AsmReg1_1,
546
  Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0,
547
  Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2,
548
  Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1,
549
  Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1,
550
  Convert__GPR32AsmReg1_0__regAC0,
551
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0,
552
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4,
553
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO,
554
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64,
555
  Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3,
556
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
557
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
558
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
559
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
560
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
561
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
562
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
563
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
564
  Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0,
565
  Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2,
566
  Convert__FGR64AsmReg1_1__GPR32AsmReg1_0,
567
  Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0,
568
  Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2,
569
  Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0,
570
  Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0,
571
  Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0,
572
  Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1,
573
  Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0,
574
  Convert__regAC0__GPR32AsmReg1_0,
575
  Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0,
576
  Convert__GPR32AsmReg1_1__GPR32AsmReg1_0,
577
  Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4,
578
  Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
579
  Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0,
580
  Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1,
581
  Convert__regZERO__regZERO__imm_95_0,
582
  Convert__regZERO__regS0,
583
  Convert__regZERO__regZERO,
584
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO,
585
  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1,
586
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0,
587
  Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0,
588
  Convert__GPR32AsmReg1_0__ConstantUImm7_01_1,
589
  Convert__GPR32AsmReg1_0__ConstantUImm10_01_1,
590
  Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0,
591
  Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0,
592
  Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2,
593
  Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2,
594
  Convert__GPR32AsmReg1_0__ConstantSImm10_01_1,
595
  Convert__GPR32AsmReg1_0__ConstantUImm8_01_1,
596
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1,
597
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2,
598
  Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1,
599
  Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1,
600
  Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1,
601
  Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1,
602
  Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1,
603
  Convert__ConstantUImm20_01_0,
604
  Convert__Reg1_0__Tie0_1_1,
605
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1,
606
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2,
607
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0,
608
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1,
609
  Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1,
610
  Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1,
611
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2,
612
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2,
613
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3,
614
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3,
615
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3,
616
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3,
617
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3,
618
  Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2,
619
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3,
620
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3,
621
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3,
622
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3,
623
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3,
624
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1,
625
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2,
626
  Convert__ConstantUImm5_01_0,
627
  Convert__MemOffsetSimm162_0,
628
  Convert__imm_95_2,
629
  Convert__imm_95_6,
630
  Convert__imm_95_4,
631
  Convert__imm_95_5,
632
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2,
633
  Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2,
634
  Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2,
635
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2,
636
  Convert__GPR32AsmReg1_0__imm_95_31,
637
  CVT_NUM_SIGNATURES
638
};
639
640
} // end anonymous namespace
641
642
static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][11] = {
643
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1
644
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
645
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1
646
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
647
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1
648
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
649
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1
650
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
651
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1
652
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
653
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1
654
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
655
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
656
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
657
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2
658
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
659
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2
660
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done },
661
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
662
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
663
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
664
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
665
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1
666
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
667
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2
668
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done },
669
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1
670
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
671
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1
672
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
673
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2
674
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
675
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2
676
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
677
  // Convert__SImm161_1
678
  { CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
679
  // Convert__Reg1_0__SImm161_1
680
  { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
681
  // Convert__Reg1_0__SImm161_2
682
  { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
683
  // Convert__Reg1_0__Reg1_1__SImm161_2
684
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
685
  // Convert__Reg1_0__Tie0_1_1__SImm161_1
686
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
687
  // Convert__GPR32AsmReg1_0__Simm19_Lsl21_1
688
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
689
  // Convert__GPRMM16AsmReg1_0__Imm1_1
690
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
691
  // Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1
692
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
693
  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2
694
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
695
  // Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1
696
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_, 2, CVT_Done },
697
  // Convert__Imm1_0
698
  { CVT_95_addImmOperands, 1, CVT_Done },
699
  // Convert__Reg1_0__Reg1_1__Reg1_2
700
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
701
  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2
702
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addGPRMM16AsmRegOperands, 3, CVT_Done },
703
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2
704
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
705
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3
706
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
707
  // Convert__GPR32AsmReg1_0__SImm161_1
708
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
709
  // Convert__Reg1_0__Tie0_1_1__Reg1_1
710
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
711
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1
712
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
713
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1
714
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
715
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2
716
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
717
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2
718
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
719
  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1
720
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
721
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2
722
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
723
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1
724
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done },
725
  // Convert__regZERO__regZERO__JumpTarget1_0
726
  { CVT_regZERO, 0, CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done },
727
  // Convert__JumpTarget1_0
728
  { CVT_95_addImmOperands, 1, CVT_Done },
729
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1
730
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
731
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2
732
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },
733
  // Convert__regZERO__JumpTarget1_0
734
  { CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done },
735
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1
736
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done },
737
  // Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2
738
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
739
  // Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2
740
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
741
  // Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2
742
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
743
  // Convert__FGR64AsmReg1_0__JumpTarget1_1
744
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
745
  // Convert__regFCC0__JumpTarget1_0
746
  { CVT_regFCC0, 0, CVT_95_addImmOperands, 1, CVT_Done },
747
  // Convert__FCCAsmReg1_0__JumpTarget1_1
748
  { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
749
  // Convert__COP2AsmReg1_0__JumpTarget1_1
750
  { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
751
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2
752
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
753
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2
754
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
755
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2
756
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
757
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2
758
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
759
  // Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2
760
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
761
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2
762
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
763
  // Convert__Reg1_0__JumpTarget1_1
764
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
765
  // Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1
766
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addImmOperands, 2, CVT_Done },
767
  // Convert__GPRMM16AsmReg1_0__JumpTarget1_1
768
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
769
  // Convert__GPR32AsmReg1_0__JumpTarget1_1
770
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
771
  // Convert__GPR64AsmReg1_0__JumpTarget1_1
772
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
773
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2
774
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done },
775
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2
776
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
777
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2
778
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
779
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2
780
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
781
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2
782
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
783
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2
784
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
785
  // Convert__MSA128AsmReg1_0__JumpTarget1_1
786
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
787
  // Convert__imm_95_0__imm_95_0
788
  { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
789
  // Convert_NoOperands
790
  { CVT_Done },
791
  // Convert__ConstantUImm10_01_0__imm_95_0
792
  { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_imm_95_0, 0, CVT_Done },
793
  // Convert__ConstantUImm10_01_0__ConstantUImm10_01_1
794
  { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
795
  // Convert__ConstantUImm4_01_0
796
  { CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 1, CVT_Done },
797
  // Convert__SImm161_0
798
  { CVT_95_addSImmOperands_LT_16_GT_, 1, CVT_Done },
799
  // Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1
800
  { CVT_regFCC0, 0, CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
801
  // Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1
802
  { CVT_regFCC0, 0, CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
803
  // Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2
804
  { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done },
805
  // Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
806
  { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
807
  // Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1
808
  { CVT_regFCC0, 0, CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
809
  // Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
810
  { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
811
  // Convert__MemOffsetSimm92_1__ConstantUImm5_01_0
812
  { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
813
  // Convert__Mem2_1__ConstantUImm5_01_0
814
  { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
815
  // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1
816
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
817
  // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1
818
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
819
  // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1
820
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
821
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2
822
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
823
  // Convert__GPR32AsmReg1_0__CCRAsmReg1_1
824
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCCRAsmRegOperands, 2, CVT_Done },
825
  // Convert__GPR32AsmReg1_0__COP2AsmReg1_1
826
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_Done },
827
  // Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1
828
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSACtrlAsmRegOperands, 2, CVT_Done },
829
  // Convert__GPR32AsmReg1_0__FGR32AsmReg1_1
830
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
831
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2
832
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
833
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2
834
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
835
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3
836
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done },
837
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3
838
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done },
839
  // Convert__Reg1_0__Reg1_1
840
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
841
  // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
842
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
843
  // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3
844
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
845
  // Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3
846
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
847
  // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3
848
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
849
  // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3
850
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
851
  // Convert__CCRAsmReg1_1__GPR32AsmReg1_0
852
  { CVT_95_addCCRAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
853
  // Convert__COP2AsmReg1_1__GPR32AsmReg1_0
854
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
855
  // Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1
856
  { CVT_95_addMSACtrlAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
857
  // Convert__FGR32AsmReg1_1__GPR32AsmReg1_0
858
  { CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
859
  // Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1
860
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
861
  // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
862
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
863
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1
864
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
865
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2
866
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
867
  // Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2
868
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
869
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3
870
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
871
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2
872
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
873
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1
874
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
875
  // Convert__GPR64AsmReg1_1__GPR64AsmReg1_2
876
  { CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },
877
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3
878
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_, 4, CVT_Done },
879
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3
880
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
881
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3
882
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
883
  // Convert__regZERO
884
  { CVT_regZERO, 0, CVT_Done },
885
  // Convert__GPR32AsmReg1_0
886
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
887
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1
888
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addImmOperands, 4, CVT_Tied, Tie0_1_1, CVT_Done },
889
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1
890
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
891
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1
892
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
893
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1
894
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
895
  // Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1
896
  { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
897
  // Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1
898
  { CVT_95_addGPR32ZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
899
  // Convert__Reg1_1__Reg1_2
900
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
901
  // Convert__GPR32AsmReg1_1__GPR32AsmReg1_2
902
  { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
903
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2
904
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
905
  // Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
906
  { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
907
  // Convert__GPR64AsmReg1_0__Imm1_1
908
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
909
  // Convert__GPR64AsmReg1_0__Mem2_1
910
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
911
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3
912
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
913
  // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0
914
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
915
  // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2
916
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
917
  // Convert__GPR64AsmReg1_0__FGR64AsmReg1_1
918
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
919
  // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0
920
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
921
  // Convert__GPR64AsmReg1_0__UImm161_1
922
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
923
  // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2
924
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
925
  // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0
926
  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
927
  // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2
928
  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
929
  // Convert__FGR64AsmReg1_1__GPR64AsmReg1_0
930
  { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
931
  // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0
932
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
933
  // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2
934
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
935
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2
936
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
937
  // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0
938
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
939
  // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1
940
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
941
  // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
942
  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
943
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0
944
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
945
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1
946
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
947
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1
948
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 2, CVT_Done },
949
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2
950
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
951
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1
952
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done },
953
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2
954
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
955
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2
956
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
957
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1
958
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
959
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1
960
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
961
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2
962
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
963
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3
964
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
965
  // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2
966
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
967
  // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2
968
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
969
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1
970
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_Done },
971
  // Convert__MSA128AsmReg1_0__GPR32AsmReg1_1
972
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
973
  // Convert__MSA128AsmReg1_0__GPR64AsmReg1_1
974
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
975
  // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2
976
  { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
977
  // Convert__GPR32AsmReg1_0__ConstantUImm2_01_1
978
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 2, CVT_Done },
979
  // Convert__imm_95_0
980
  { CVT_imm_95_0, 0, CVT_Done },
981
  // Convert__ConstantUImm10_01_0
982
  { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_Done },
983
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1
984
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
985
  // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2
986
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
987
  // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2
988
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR64AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_Done },
989
  // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2
990
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
991
  // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2
992
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Done },
993
  // Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1
994
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
995
  // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6
996
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
997
  // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6
998
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
999
  // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6
1000
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
1001
  // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6
1002
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
1003
  // Convert__regRA__GPR32AsmReg1_0
1004
  { CVT_regRA, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1005
  // Convert__regRA_64__GPR64AsmReg1_0
1006
  { CVT_regRA_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1007
  // Convert__Reg1_0
1008
  { CVT_95_Reg, 1, CVT_Done },
1009
  // Convert__GPR32AsmReg1_0__imm_95_0
1010
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1011
  // Convert__GPR64AsmReg1_0__imm_95_0
1012
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1013
  // Convert__regZERO__GPR32AsmReg1_0
1014
  { CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1015
  // Convert__GPR64AsmReg1_0
1016
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1017
  // Convert__regZERO_64__GPR64AsmReg1_0
1018
  { CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1019
  // Convert__UImm5Lsl21_0
1020
  { CVT_95_addImmOperands, 1, CVT_Done },
1021
  // Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1
1022
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1023
  // Convert__FGR64AsmReg1_0__MemOffsetSimm162_1
1024
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1025
  // Convert__FGR32AsmReg1_0__MemOffsetSimm162_1
1026
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1027
  // Convert__GPR32AsmReg1_0__Imm1_1
1028
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1029
  // Convert__GPR32AsmReg1_0__Mem2_1
1030
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1031
  // Convert__GPR32AsmReg1_0__MemOffsetSimm162_1
1032
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1033
  // Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1
1034
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1035
  // Convert__GPR32AsmReg1_0__MemOffsetSimm92_1
1036
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1037
  // Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1
1038
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done },
1039
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1040
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1041
  // Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1
1042
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1043
  // Convert__MSA128AsmReg1_0__MemOffsetSimm102_1
1044
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1045
  // Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1
1046
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1047
  // Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1
1048
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1049
  // Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1
1050
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1051
  // Convert__COP2AsmReg1_0__MemOffsetSimm112_1
1052
  { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1053
  // Convert__COP2AsmReg1_0__MemOffsetSimm162_1
1054
  { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1055
  // Convert__COP3AsmReg1_0__Mem2_1
1056
  { CVT_95_addCOP3AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1057
  // Convert__MSA128AsmReg1_0__ConstantSImm10_01_1
1058
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1059
  // Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1
1060
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1061
  // Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1062
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1063
  // Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1064
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1065
  // Convert__GPR32AsmReg1_0__UImm32_Coerced1_1
1066
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_32_GT_, 2, CVT_Done },
1067
  // Convert__StrictlyAFGR64AsmReg1_0__Imm1_1
1068
  { CVT_95_addStrictlyAFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1069
  // Convert__StrictlyFGR64AsmReg1_0__Imm1_1
1070
  { CVT_95_addStrictlyFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1071
  // Convert__StrictlyFGR32AsmReg1_0__Imm1_1
1072
  { CVT_95_addStrictlyFGR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1073
  // Convert__GPRMM16AsmReg1_0__UImm7_N11_1
1074
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_, 2, CVT_Done },
1075
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3
1076
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
1077
  // Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3
1078
  { CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
1079
  // Convert__GPR32AsmReg1_0__UImm161_1
1080
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
1081
  // Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1
1082
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
1083
  // Convert__Reg1_0__Imm1_1__imm_95_0
1084
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1085
  // Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1
1086
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1087
  // Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1
1088
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1089
  // Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1
1090
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1091
  // Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1
1092
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1093
  // Convert__RegList1_0__Mem2_1
1094
  { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1095
  // Convert__RegList161_0__MemOffsetUimm42_1
1096
  { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1097
  // ConvertCustom_ConvertXWPOperands
1098
  { CVT_ConvertXWPOperands, 0, CVT_Done },
1099
  // Convert__GPR32AsmReg1_0__MemOffsetSimm122_1
1100
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1101
  // Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1102
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1103
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3
1104
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_95_addAFGR64AsmRegOperands, 4, CVT_Done },
1105
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3
1106
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_95_addFGR64AsmRegOperands, 4, CVT_Done },
1107
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3
1108
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 4, CVT_Done },
1109
  // Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2
1110
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
1111
  // Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2
1112
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
1113
  // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0
1114
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1115
  // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2
1116
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1117
  // Convert__GPR32AsmReg1_0__FGR64AsmReg1_1
1118
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
1119
  // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0
1120
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1121
  // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2
1122
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1123
  // Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1
1124
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
1125
  // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1
1126
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_Done },
1127
  // Convert__GPR32AsmReg1_0__regAC0
1128
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regAC0, 0, CVT_Done },
1129
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0
1130
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1131
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4
1132
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done },
1133
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO
1134
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_regZERO, 0, CVT_Done },
1135
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64
1136
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_regZERO_64, 0, CVT_Done },
1137
  // Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3
1138
  { CVT_95_addGPRMM16AsmRegMovePPairFirstOperands, 1, CVT_95_addGPRMM16AsmRegMovePPairSecondOperands, 2, CVT_95_addGPRMM16AsmRegMovePOperands, 3, CVT_95_addGPRMM16AsmRegMovePOperands, 4, CVT_Done },
1139
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1140
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1141
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1142
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1143
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1144
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1145
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1146
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1147
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1148
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1149
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1150
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1151
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1152
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1153
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1154
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1155
  // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0
1156
  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1157
  // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2
1158
  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1159
  // Convert__FGR64AsmReg1_1__GPR32AsmReg1_0
1160
  { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1161
  // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0
1162
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1163
  // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2
1164
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1165
  // Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0
1166
  { CVT_95_addAFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1167
  // Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0
1168
  { CVT_95_addFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1169
  // Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0
1170
  { CVT_95_addHI32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1171
  // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1
1172
  { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_Done },
1173
  // Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0
1174
  { CVT_95_addLO32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1175
  // Convert__regAC0__GPR32AsmReg1_0
1176
  { CVT_regAC0, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1177
  // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0
1178
  { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1179
  // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0
1180
  { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1181
  // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4
1182
  { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done },
1183
  // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
1184
  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1185
  // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0
1186
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1187
  // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1
1188
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1189
  // Convert__regZERO__regZERO__imm_95_0
1190
  { CVT_regZERO, 0, CVT_regZERO, 0, CVT_imm_95_0, 0, CVT_Done },
1191
  // Convert__regZERO__regS0
1192
  { CVT_regZERO, 0, CVT_regS0, 0, CVT_Done },
1193
  // Convert__regZERO__regZERO
1194
  { CVT_regZERO, 0, CVT_regZERO, 0, CVT_Done },
1195
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO
1196
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_Done },
1197
  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1
1198
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Done },
1199
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0
1200
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1201
  // Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0
1202
  { CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
1203
  // Convert__GPR32AsmReg1_0__ConstantUImm7_01_1
1204
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_, 2, CVT_Done },
1205
  // Convert__GPR32AsmReg1_0__ConstantUImm10_01_1
1206
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1207
  // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0
1208
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1209
  // Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0
1210
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1211
  // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2
1212
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1213
  // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2
1214
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
1215
  // Convert__GPR32AsmReg1_0__ConstantSImm10_01_1
1216
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1217
  // Convert__GPR32AsmReg1_0__ConstantUImm8_01_1
1218
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 2, CVT_Done },
1219
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1
1220
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done },
1221
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2
1222
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
1223
  // Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1
1224
  { CVT_95_addGPRMM16AsmRegZeroOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done },
1225
  // Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1
1226
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
1227
  // Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1
1228
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
1229
  // Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1
1230
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
1231
  // Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1
1232
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
1233
  // Convert__ConstantUImm20_01_0
1234
  { CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_, 1, CVT_Done },
1235
  // Convert__Reg1_0__Tie0_1_1
1236
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done },
1237
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1
1238
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1239
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2
1240
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done },
1241
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0
1242
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1243
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1
1244
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1245
  // Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1
1246
  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1247
  // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1
1248
  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1249
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2
1250
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
1251
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2
1252
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1253
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3
1254
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done },
1255
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3
1256
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
1257
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3
1258
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
1259
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3
1260
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
1261
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3
1262
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
1263
  // Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2
1264
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
1265
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3
1266
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done },
1267
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3
1268
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
1269
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3
1270
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
1271
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3
1272
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
1273
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3
1274
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
1275
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1
1276
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1277
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2
1278
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1279
  // Convert__ConstantUImm5_01_0
1280
  { CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
1281
  // Convert__MemOffsetSimm162_0
1282
  { CVT_95_addMemOperands, 1, CVT_Done },
1283
  // Convert__imm_95_2
1284
  { CVT_imm_95_2, 0, CVT_Done },
1285
  // Convert__imm_95_6
1286
  { CVT_imm_95_6, 0, CVT_Done },
1287
  // Convert__imm_95_4
1288
  { CVT_imm_95_4, 0, CVT_Done },
1289
  // Convert__imm_95_5
1290
  { CVT_imm_95_5, 0, CVT_Done },
1291
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2
1292
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done },
1293
  // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2
1294
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1295
  // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2
1296
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1297
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2
1298
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1299
  // Convert__GPR32AsmReg1_0__imm_95_31
1300
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_31, 0, CVT_Done },
1301
};
1302
1303
void MipsAsmParser::
1304
convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
1305
36.1k
                const OperandVector &Operands) {
1306
36.1k
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
1307
36.1k
  const uint8_t *Converter = ConversionTable[Kind];
1308
36.1k
  unsigned OpIdx;
1309
36.1k
  Inst.setOpcode(Opcode);
1310
125k
  for (const uint8_t *p = Converter; *p; 
p+= 289.7k
) {
1311
89.7k
    OpIdx = *(p + 1);
1312
89.7k
    switch (*p) {
1313
89.7k
    
default: 0
llvm_unreachable0
("invalid conversion entry!");
1314
89.7k
    case CVT_Reg:
1315
0
      static_cast<MipsOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
1316
0
      break;
1317
89.7k
    case CVT_Tied: {
1318
627
      assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
1319
627
                          std::begin(TiedAsmOperandTable)) &&
1320
627
             "Tied operand not found");
1321
627
      unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];
1322
627
      if (TiedResOpnd != (uint8_t) -1)
1323
627
        Inst.addOperand(Inst.getOperand(TiedResOpnd));
1324
627
      break;
1325
89.7k
    }
1326
89.7k
    case CVT_95_addGPR32AsmRegOperands:
1327
24.1k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32AsmRegOperands(Inst, 1);
1328
24.1k
      break;
1329
89.7k
    case CVT_95_addAFGR64AsmRegOperands:
1330
925
      static_cast<MipsOperand&>(*Operands[OpIdx]).addAFGR64AsmRegOperands(Inst, 1);
1331
925
      break;
1332
89.7k
    case CVT_95_addFGR64AsmRegOperands:
1333
1.30k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addFGR64AsmRegOperands(Inst, 1);
1334
1.30k
      break;
1335
89.7k
    case CVT_95_addFGR32AsmRegOperands:
1336
2.55k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addFGR32AsmRegOperands(Inst, 1);
1337
2.55k
      break;
1338
89.7k
    case CVT_95_addSImmOperands_LT_32_GT_:
1339
636
      static_cast<MipsOperand&>(*Operands[OpIdx]).addSImmOperands<32>(Inst, 1);
1340
636
      break;
1341
89.7k
    case CVT_95_addMSA128AsmRegOperands:
1342
1.40k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addMSA128AsmRegOperands(Inst, 1);
1343
1.40k
      break;
1344
89.7k
    case CVT_95_addSImmOperands_LT_16_GT_:
1345
1.27k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addSImmOperands<16>(Inst, 1);
1346
1.27k
      break;
1347
89.7k
    case CVT_95_Reg:
1348
0
      static_cast<MipsOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
1349
0
      break;
1350
89.7k
    case CVT_95_addImmOperands:
1351
3.56k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
1352
3.56k
      break;
1353
89.7k
    case CVT_95_addGPRMM16AsmRegOperands:
1354
178
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegOperands(Inst, 1);
1355
178
      break;
1356
89.7k
    case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_:
1357
4
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<4, 0>(Inst, 1);
1358
4
      break;
1359
89.7k
    case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_:
1360
475
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 0>(Inst, 1);
1361
475
      break;
1362
89.7k
    case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_:
1363
14
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<2, 0>(Inst, 1);
1364
14
      break;
1365
89.7k
    case CVT_95_addUImmOperands_LT_16_GT_:
1366
233
      static_cast<MipsOperand&>(*Operands[OpIdx]).addUImmOperands<16>(Inst, 1);
1367
233
      break;
1368
89.7k
    case CVT_95_addGPR64AsmRegOperands:
1369
3.96k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR64AsmRegOperands(Inst, 1);
1370
3.96k
      break;
1371
89.7k
    case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_:
1372
15
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<8, 0>(Inst, 1);
1373
15
      break;
1374
89.7k
    case CVT_regZERO:
1375
21.7k
      Inst.addOperand(MCOperand::createReg(Mips::ZERO));
1376
21.7k
      break;
1377
89.7k
    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_:
1378
6
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 32, -32>(Inst, 1);
1379
6
      break;
1380
89.7k
    case CVT_regFCC0:
1381
282
      Inst.addOperand(MCOperand::createReg(Mips::FCC0));
1382
282
      break;
1383
89.7k
    case CVT_95_addFCCAsmRegOperands:
1384
734
      static_cast<MipsOperand&>(*Operands[OpIdx]).addFCCAsmRegOperands(Inst, 1);
1385
734
      break;
1386
89.7k
    case CVT_95_addCOP2AsmRegOperands:
1387
122
      static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP2AsmRegOperands(Inst, 1);
1388
122
      break;
1389
89.7k
    case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_:
1390
155
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<3, 0>(Inst, 1);
1391
155
      break;
1392
89.7k
    case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_:
1393
76
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<6, 0>(Inst, 1);
1394
76
      break;
1395
89.7k
    case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_:
1396
62
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<4, 0>(Inst, 1);
1397
62
      break;
1398
89.7k
    case CVT_imm_95_0:
1399
11.0k
      Inst.addOperand(MCOperand::createImm(0));
1400
11.0k
      break;
1401
89.7k
    case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_:
1402
132
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<10, 0>(Inst, 1);
1403
132
      break;
1404
89.7k
    case CVT_95_addMemOperands:
1405
12.6k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addMemOperands(Inst, 2);
1406
12.6k
      break;
1407
89.7k
    case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_:
1408
20
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<5, 0>(Inst, 1);
1409
20
      break;
1410
89.7k
    case CVT_95_addCCRAsmRegOperands:
1411
38
      static_cast<MipsOperand&>(*Operands[OpIdx]).addCCRAsmRegOperands(Inst, 1);
1412
38
      break;
1413
89.7k
    case CVT_95_addMSACtrlAsmRegOperands:
1414
32
      static_cast<MipsOperand&>(*Operands[OpIdx]).addMSACtrlAsmRegOperands(Inst, 1);
1415
32
      break;
1416
89.7k
    case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_:
1417
53
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<1, 0>(Inst, 1);
1418
53
      break;
1419
89.7k
    case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_:
1420
10
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 33>(Inst, 1);
1421
10
      break;
1422
89.7k
    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_:
1423
20
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 32>(Inst, 1);
1424
20
      break;
1425
89.7k
    case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_:
1426
42
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 1>(Inst, 1);
1427
42
      break;
1428
89.7k
    case CVT_95_addGPR32NonZeroAsmRegOperands:
1429
50
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32NonZeroAsmRegOperands(Inst, 1);
1430
50
      break;
1431
89.7k
    case CVT_95_addGPR32ZeroAsmRegOperands:
1432
16
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32ZeroAsmRegOperands(Inst, 1);
1433
16
      break;
1434
89.7k
    case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_:
1435
12
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<2, 1>(Inst, 1);
1436
12
      break;
1437
89.7k
    case CVT_95_addCOP0AsmRegOperands:
1438
116
      static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP0AsmRegOperands(Inst, 1);
1439
116
      break;
1440
89.7k
    case CVT_regZERO_64:
1441
87
      Inst.addOperand(MCOperand::createReg(Mips::ZERO_64));
1442
87
      break;
1443
89.7k
    case CVT_95_addACC64DSPAsmRegOperands:
1444
180
      static_cast<MipsOperand&>(*Operands[OpIdx]).addACC64DSPAsmRegOperands(Inst, 1);
1445
180
      break;
1446
89.7k
    case CVT_95_addConstantUImmOperands_LT_1_GT_:
1447
4
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<1>(Inst, 1);
1448
4
      break;
1449
89.7k
    case CVT_regRA:
1450
40
      Inst.addOperand(MCOperand::createReg(Mips::RA));
1451
40
      break;
1452
89.7k
    case CVT_regRA_64:
1453
5
      Inst.addOperand(MCOperand::createReg(Mips::RA_64));
1454
5
      break;
1455
89.7k
    case CVT_95_addMicroMipsMemOperands:
1456
50
      static_cast<MipsOperand&>(*Operands[OpIdx]).addMicroMipsMemOperands(Inst, 2);
1457
50
      break;
1458
89.7k
    case CVT_95_addCOP3AsmRegOperands:
1459
6
      static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP3AsmRegOperands(Inst, 1);
1460
6
      break;
1461
89.7k
    case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_:
1462
12
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<10, 0>(Inst, 1);
1463
12
      break;
1464
89.7k
    case CVT_95_addConstantUImmOperands_LT_32_GT_:
1465
206
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<32>(Inst, 1);
1466
206
      break;
1467
89.7k
    case CVT_95_addStrictlyAFGR64AsmRegOperands:
1468
39
      static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyAFGR64AsmRegOperands(Inst, 1);
1469
39
      break;
1470
89.7k
    case CVT_95_addStrictlyFGR64AsmRegOperands:
1471
52
      static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyFGR64AsmRegOperands(Inst, 1);
1472
52
      break;
1473
89.7k
    case CVT_95_addStrictlyFGR32AsmRegOperands:
1474
66
      static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyFGR32AsmRegOperands(Inst, 1);
1475
66
      break;
1476
89.7k
    case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_:
1477
7
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<7, -1>(Inst, 1);
1478
7
      break;
1479
89.7k
    case CVT_95_addRegListOperands:
1480
63
      static_cast<MipsOperand&>(*Operands[OpIdx]).addRegListOperands(Inst, 1);
1481
63
      break;
1482
89.7k
    case CVT_ConvertXWPOperands:
1483
14
      ConvertXWPOperands(Inst, Operands);
1484
14
      break;
1485
89.7k
    case CVT_regAC0:
1486
4
      Inst.addOperand(MCOperand::createReg(Mips::AC0));
1487
4
      break;
1488
89.7k
    case CVT_95_addGPRMM16AsmRegMovePPairFirstOperands:
1489
6
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegMovePPairFirstOperands(Inst, 1);
1490
6
      break;
1491
89.7k
    case CVT_95_addGPRMM16AsmRegMovePPairSecondOperands:
1492
6
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegMovePPairSecondOperands(Inst, 1);
1493
6
      break;
1494
89.7k
    case CVT_95_addGPRMM16AsmRegMovePOperands:
1495
12
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegMovePOperands(Inst, 1);
1496
12
      break;
1497
89.7k
    case CVT_95_addHI32DSPAsmRegOperands:
1498
3
      static_cast<MipsOperand&>(*Operands[OpIdx]).addHI32DSPAsmRegOperands(Inst, 1);
1499
3
      break;
1500
89.7k
    case CVT_95_addLO32DSPAsmRegOperands:
1501
3
      static_cast<MipsOperand&>(*Operands[OpIdx]).addLO32DSPAsmRegOperands(Inst, 1);
1502
3
      break;
1503
89.7k
    case CVT_regS0:
1504
2
      Inst.addOperand(MCOperand::createReg(Mips::S0));
1505
2
      break;
1506
89.7k
    case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_:
1507
5
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<7, 0>(Inst, 1);
1508
5
      break;
1509
89.7k
    case CVT_95_addHWRegsAsmRegOperands:
1510
60
      static_cast<MipsOperand&>(*Operands[OpIdx]).addHWRegsAsmRegOperands(Inst, 1);
1511
60
      break;
1512
89.7k
    case CVT_95_addGPRMM16AsmRegZeroOperands:
1513
22
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegZeroOperands(Inst, 1);
1514
22
      break;
1515
89.7k
    case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_:
1516
25
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<20, 0>(Inst, 1);
1517
25
      break;
1518
89.7k
    case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_:
1519
6
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<6, 0>(Inst, 1);
1520
6
      break;
1521
89.7k
    case CVT_imm_95_2:
1522
1
      Inst.addOperand(MCOperand::createImm(2));
1523
1
      break;
1524
89.7k
    case CVT_imm_95_6:
1525
1
      Inst.addOperand(MCOperand::createImm(6));
1526
1
      break;
1527
89.7k
    case CVT_imm_95_4:
1528
1
      Inst.addOperand(MCOperand::createImm(4));
1529
1
      break;
1530
89.7k
    case CVT_imm_95_5:
1531
1
      Inst.addOperand(MCOperand::createImm(5));
1532
1
      break;
1533
89.7k
    case CVT_imm_95_31:
1534
4
      Inst.addOperand(MCOperand::createImm(31));
1535
4
      break;
1536
89.7k
    }
1537
89.7k
  }
1538
36.1k
}
1539
1540
void MipsAsmParser::
1541
convertToMapAndConstraints(unsigned Kind,
1542
0
                           const OperandVector &Operands) {
1543
0
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
1544
0
  unsigned NumMCOperands = 0;
1545
0
  const uint8_t *Converter = ConversionTable[Kind];
1546
0
  for (const uint8_t *p = Converter; *p; p+= 2) {
1547
0
    switch (*p) {
1548
0
    default: llvm_unreachable("invalid conversion entry!");
1549
0
    case CVT_Reg:
1550
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1551
0
      Operands[*(p + 1)]->setConstraint("r");
1552
0
      ++NumMCOperands;
1553
0
      break;
1554
0
    case CVT_Tied:
1555
0
      ++NumMCOperands;
1556
0
      break;
1557
0
    case CVT_95_addGPR32AsmRegOperands:
1558
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1559
0
      Operands[*(p + 1)]->setConstraint("m");
1560
0
      NumMCOperands += 1;
1561
0
      break;
1562
0
    case CVT_95_addAFGR64AsmRegOperands:
1563
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1564
0
      Operands[*(p + 1)]->setConstraint("m");
1565
0
      NumMCOperands += 1;
1566
0
      break;
1567
0
    case CVT_95_addFGR64AsmRegOperands:
1568
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1569
0
      Operands[*(p + 1)]->setConstraint("m");
1570
0
      NumMCOperands += 1;
1571
0
      break;
1572
0
    case CVT_95_addFGR32AsmRegOperands:
1573
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1574
0
      Operands[*(p + 1)]->setConstraint("m");
1575
0
      NumMCOperands += 1;
1576
0
      break;
1577
0
    case CVT_95_addSImmOperands_LT_32_GT_:
1578
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1579
0
      Operands[*(p + 1)]->setConstraint("m");
1580
0
      NumMCOperands += 1;
1581
0
      break;
1582
0
    case CVT_95_addMSA128AsmRegOperands:
1583
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1584
0
      Operands[*(p + 1)]->setConstraint("m");
1585
0
      NumMCOperands += 1;
1586
0
      break;
1587
0
    case CVT_95_addSImmOperands_LT_16_GT_:
1588
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1589
0
      Operands[*(p + 1)]->setConstraint("m");
1590
0
      NumMCOperands += 1;
1591
0
      break;
1592
0
    case CVT_95_Reg:
1593
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1594
0
      Operands[*(p + 1)]->setConstraint("r");
1595
0
      NumMCOperands += 1;
1596
0
      break;
1597
0
    case CVT_95_addImmOperands:
1598
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1599
0
      Operands[*(p + 1)]->setConstraint("m");
1600
0
      NumMCOperands += 1;
1601
0
      break;
1602
0
    case CVT_95_addGPRMM16AsmRegOperands:
1603
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1604
0
      Operands[*(p + 1)]->setConstraint("m");
1605
0
      NumMCOperands += 1;
1606
0
      break;
1607
0
    case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_:
1608
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1609
0
      Operands[*(p + 1)]->setConstraint("m");
1610
0
      NumMCOperands += 1;
1611
0
      break;
1612
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_:
1613
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1614
0
      Operands[*(p + 1)]->setConstraint("m");
1615
0
      NumMCOperands += 1;
1616
0
      break;
1617
0
    case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_:
1618
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1619
0
      Operands[*(p + 1)]->setConstraint("m");
1620
0
      NumMCOperands += 1;
1621
0
      break;
1622
0
    case CVT_95_addUImmOperands_LT_16_GT_:
1623
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1624
0
      Operands[*(p + 1)]->setConstraint("m");
1625
0
      NumMCOperands += 1;
1626
0
      break;
1627
0
    case CVT_95_addGPR64AsmRegOperands:
1628
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1629
0
      Operands[*(p + 1)]->setConstraint("m");
1630
0
      NumMCOperands += 1;
1631
0
      break;
1632
0
    case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_:
1633
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1634
0
      Operands[*(p + 1)]->setConstraint("m");
1635
0
      NumMCOperands += 1;
1636
0
      break;
1637
0
    case CVT_regZERO:
1638
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1639
0
      Operands[*(p + 1)]->setConstraint("m");
1640
0
      ++NumMCOperands;
1641
0
      break;
1642
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_:
1643
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1644
0
      Operands[*(p + 1)]->setConstraint("m");
1645
0
      NumMCOperands += 1;
1646
0
      break;
1647
0
    case CVT_regFCC0:
1648
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1649
0
      Operands[*(p + 1)]->setConstraint("m");
1650
0
      ++NumMCOperands;
1651
0
      break;
1652
0
    case CVT_95_addFCCAsmRegOperands:
1653
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1654
0
      Operands[*(p + 1)]->setConstraint("m");
1655
0
      NumMCOperands += 1;
1656
0
      break;
1657
0
    case CVT_95_addCOP2AsmRegOperands:
1658
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1659
0
      Operands[*(p + 1)]->setConstraint("m");
1660
0
      NumMCOperands += 1;
1661
0
      break;
1662
0
    case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_:
1663
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1664
0
      Operands[*(p + 1)]->setConstraint("m");
1665
0
      NumMCOperands += 1;
1666
0
      break;
1667
0
    case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_:
1668
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1669
0
      Operands[*(p + 1)]->setConstraint("m");
1670
0
      NumMCOperands += 1;
1671
0
      break;
1672
0
    case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_:
1673
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1674
0
      Operands[*(p + 1)]->setConstraint("m");
1675
0
      NumMCOperands += 1;
1676
0
      break;
1677
0
    case CVT_imm_95_0:
1678
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1679
0
      Operands[*(p + 1)]->setConstraint("");
1680
0
      ++NumMCOperands;
1681
0
      break;
1682
0
    case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_:
1683
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1684
0
      Operands[*(p + 1)]->setConstraint("m");
1685
0
      NumMCOperands += 1;
1686
0
      break;
1687
0
    case CVT_95_addMemOperands:
1688
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1689
0
      Operands[*(p + 1)]->setConstraint("m");
1690
0
      NumMCOperands += 2;
1691
0
      break;
1692
0
    case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_:
1693
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1694
0
      Operands[*(p + 1)]->setConstraint("m");
1695
0
      NumMCOperands += 1;
1696
0
      break;
1697
0
    case CVT_95_addCCRAsmRegOperands:
1698
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1699
0
      Operands[*(p + 1)]->setConstraint("m");
1700
0
      NumMCOperands += 1;
1701
0
      break;
1702
0
    case CVT_95_addMSACtrlAsmRegOperands:
1703
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1704
0
      Operands[*(p + 1)]->setConstraint("m");
1705
0
      NumMCOperands += 1;
1706
0
      break;
1707
0
    case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_:
1708
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1709
0
      Operands[*(p + 1)]->setConstraint("m");
1710
0
      NumMCOperands += 1;
1711
0
      break;
1712
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_:
1713
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1714
0
      Operands[*(p + 1)]->setConstraint("m");
1715
0
      NumMCOperands += 1;
1716
0
      break;
1717
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_:
1718
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1719
0
      Operands[*(p + 1)]->setConstraint("m");
1720
0
      NumMCOperands += 1;
1721
0
      break;
1722
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_:
1723
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1724
0
      Operands[*(p + 1)]->setConstraint("m");
1725
0
      NumMCOperands += 1;
1726
0
      break;
1727
0
    case CVT_95_addGPR32NonZeroAsmRegOperands:
1728
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1729
0
      Operands[*(p + 1)]->setConstraint("m");
1730
0
      NumMCOperands += 1;
1731
0
      break;
1732
0
    case CVT_95_addGPR32ZeroAsmRegOperands:
1733
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1734
0
      Operands[*(p + 1)]->setConstraint("m");
1735
0
      NumMCOperands += 1;
1736
0
      break;
1737
0
    case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_:
1738
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1739
0
      Operands[*(p + 1)]->setConstraint("m");
1740
0
      NumMCOperands += 1;
1741
0
      break;
1742
0
    case CVT_95_addCOP0AsmRegOperands:
1743
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1744
0
      Operands[*(p + 1)]->setConstraint("m");
1745
0
      NumMCOperands += 1;
1746
0
      break;
1747
0
    case CVT_regZERO_64:
1748
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1749
0
      Operands[*(p + 1)]->setConstraint("m");
1750
0
      ++NumMCOperands;
1751
0
      break;
1752
0
    case CVT_95_addACC64DSPAsmRegOperands:
1753
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1754
0
      Operands[*(p + 1)]->setConstraint("m");
1755
0
      NumMCOperands += 1;
1756
0
      break;
1757
0
    case CVT_95_addConstantUImmOperands_LT_1_GT_:
1758
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1759
0
      Operands[*(p + 1)]->setConstraint("m");
1760
0
      NumMCOperands += 1;
1761
0
      break;
1762
0
    case CVT_regRA:
1763
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1764
0
      Operands[*(p + 1)]->setConstraint("m");
1765
0
      ++NumMCOperands;
1766
0
      break;
1767
0
    case CVT_regRA_64:
1768
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1769
0
      Operands[*(p + 1)]->setConstraint("m");
1770
0
      ++NumMCOperands;
1771
0
      break;
1772
0
    case CVT_95_addMicroMipsMemOperands:
1773
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1774
0
      Operands[*(p + 1)]->setConstraint("m");
1775
0
      NumMCOperands += 2;
1776
0
      break;
1777
0
    case CVT_95_addCOP3AsmRegOperands:
1778
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1779
0
      Operands[*(p + 1)]->setConstraint("m");
1780
0
      NumMCOperands += 1;
1781
0
      break;
1782
0
    case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_:
1783
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1784
0
      Operands[*(p + 1)]->setConstraint("m");
1785
0
      NumMCOperands += 1;
1786
0
      break;
1787
0
    case CVT_95_addConstantUImmOperands_LT_32_GT_:
1788
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1789
0
      Operands[*(p + 1)]->setConstraint("m");
1790
0
      NumMCOperands += 1;
1791
0
      break;
1792
0
    case CVT_95_addStrictlyAFGR64AsmRegOperands:
1793
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1794
0
      Operands[*(p + 1)]->setConstraint("m");
1795
0
      NumMCOperands += 1;
1796
0
      break;
1797
0
    case CVT_95_addStrictlyFGR64AsmRegOperands:
1798
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1799
0
      Operands[*(p + 1)]->setConstraint("m");
1800
0
      NumMCOperands += 1;
1801
0
      break;
1802
0
    case CVT_95_addStrictlyFGR32AsmRegOperands:
1803
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1804
0
      Operands[*(p + 1)]->setConstraint("m");
1805
0
      NumMCOperands += 1;
1806
0
      break;
1807
0
    case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_:
1808
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1809
0
      Operands[*(p + 1)]->setConstraint("m");
1810
0
      NumMCOperands += 1;
1811
0
      break;
1812
0
    case CVT_95_addRegListOperands:
1813
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1814
0
      Operands[*(p + 1)]->setConstraint("m");
1815
0
      NumMCOperands += 1;
1816
0
      break;
1817
0
    case CVT_regAC0:
1818
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1819
0
      Operands[*(p + 1)]->setConstraint("m");
1820
0
      ++NumMCOperands;
1821
0
      break;
1822
0
    case CVT_95_addGPRMM16AsmRegMovePPairFirstOperands:
1823
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1824
0
      Operands[*(p + 1)]->setConstraint("m");
1825
0
      NumMCOperands += 1;
1826
0
      break;
1827
0
    case CVT_95_addGPRMM16AsmRegMovePPairSecondOperands:
1828
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1829
0
      Operands[*(p + 1)]->setConstraint("m");
1830
0
      NumMCOperands += 1;
1831
0
      break;
1832
0
    case CVT_95_addGPRMM16AsmRegMovePOperands:
1833
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1834
0
      Operands[*(p + 1)]->setConstraint("m");
1835
0
      NumMCOperands += 1;
1836
0
      break;
1837
0
    case CVT_95_addHI32DSPAsmRegOperands:
1838
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1839
0
      Operands[*(p + 1)]->setConstraint("m");
1840
0
      NumMCOperands += 1;
1841
0
      break;
1842
0
    case CVT_95_addLO32DSPAsmRegOperands:
1843
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1844
0
      Operands[*(p + 1)]->setConstraint("m");
1845
0
      NumMCOperands += 1;
1846
0
      break;
1847
0
    case CVT_regS0:
1848
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1849
0
      Operands[*(p + 1)]->setConstraint("m");
1850
0
      ++NumMCOperands;
1851
0
      break;
1852
0
    case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_:
1853
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1854
0
      Operands[*(p + 1)]->setConstraint("m");
1855
0
      NumMCOperands += 1;
1856
0
      break;
1857
0
    case CVT_95_addHWRegsAsmRegOperands:
1858
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1859
0
      Operands[*(p + 1)]->setConstraint("m");
1860
0
      NumMCOperands += 1;
1861
0
      break;
1862
0
    case CVT_95_addGPRMM16AsmRegZeroOperands:
1863
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1864
0
      Operands[*(p + 1)]->setConstraint("m");
1865
0
      NumMCOperands += 1;
1866
0
      break;
1867
0
    case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_:
1868
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1869
0
      Operands[*(p + 1)]->setConstraint("m");
1870
0
      NumMCOperands += 1;
1871
0
      break;
1872
0
    case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_:
1873
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1874
0
      Operands[*(p + 1)]->setConstraint("m");
1875
0
      NumMCOperands += 1;
1876
0
      break;
1877
0
    case CVT_imm_95_2:
1878
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1879
0
      Operands[*(p + 1)]->setConstraint("");
1880
0
      ++NumMCOperands;
1881
0
      break;
1882
0
    case CVT_imm_95_6:
1883
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1884
0
      Operands[*(p + 1)]->setConstraint("");
1885
0
      ++NumMCOperands;
1886
0
      break;
1887
0
    case CVT_imm_95_4:
1888
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1889
0
      Operands[*(p + 1)]->setConstraint("");
1890
0
      ++NumMCOperands;
1891
0
      break;
1892
0
    case CVT_imm_95_5:
1893
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1894
0
      Operands[*(p + 1)]->setConstraint("");
1895
0
      ++NumMCOperands;
1896
0
      break;
1897
0
    case CVT_imm_95_31:
1898
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1899
0
      Operands[*(p + 1)]->setConstraint("");
1900
0
      ++NumMCOperands;
1901
0
      break;
1902
0
    }
1903
0
  }
1904
0
}
1905
1906
namespace {
1907
1908
/// MatchClassKind - The kinds of classes which participate in
1909
/// instruction matching.
1910
enum MatchClassKind {
1911
  InvalidMatchClass = 0,
1912
  OptionalMatchClass = 1,
1913
  MCK__35_, // '#'
1914
  MCK__40_, // '('
1915
  MCK__41_, // ')'
1916
  MCK_0, // '0'
1917
  MCK_16, // '16'
1918
  MCK__91_, // '['
1919
  MCK__93_, // ']'
1920
  MCK_bit, // 'bit'
1921
  MCK_inst, // 'inst'
1922
  MCK_LAST_TOKEN = MCK_inst,
1923
  MCK_Reg37, // derived register class
1924
  MCK_Reg19, // derived register class
1925
  MCK_ACC128, // register class 'ACC128'
1926
  MCK_ACC64, // register class 'ACC64'
1927
  MCK_CPURAReg, // register class 'CPURAReg,RA'
1928
  MCK_CPUSPReg, // register class 'CPUSPReg,SP32,SP'
1929
  MCK_DSPCC, // register class 'DSPCC'
1930
  MCK_GP32, // register class 'GP32'
1931
  MCK_GP64, // register class 'GP64'
1932
  MCK_GPR32ZERO, // register class 'GPR32ZERO,ZERO'
1933
  MCK_HI32, // register class 'HI32'
1934
  MCK_HI64, // register class 'HI64'
1935
  MCK_LO32, // register class 'LO32'
1936
  MCK_LO64, // register class 'LO64'
1937
  MCK_PC, // register class 'PC'
1938
  MCK_SP64, // register class 'SP64'
1939
  MCK_Reg32, // derived register class
1940
  MCK_Reg13, // derived register class
1941
  MCK_Reg33, // derived register class
1942
  MCK_Reg31, // derived register class
1943
  MCK_Reg30, // derived register class
1944
  MCK_Reg14, // derived register class
1945
  MCK_Reg11, // derived register class
1946
  MCK_GPRMM16MovePPairFirst, // register class 'GPRMM16MovePPairFirst'
1947
  MCK_OCTEON_MPL, // register class 'OCTEON_MPL'
1948
  MCK_OCTEON_P, // register class 'OCTEON_P'
1949
  MCK_Reg28, // derived register class
1950
  MCK_Reg23, // derived register class
1951
  MCK_Reg9, // derived register class
1952
  MCK_Reg4, // derived register class
1953
  MCK_ACC64DSP, // register class 'ACC64DSP'
1954
  MCK_HI32DSP, // register class 'HI32DSP'
1955
  MCK_LO32DSP, // register class 'LO32DSP'
1956
  MCK_Reg34, // derived register class
1957
  MCK_GPRMM16MovePPairSecond, // register class 'GPRMM16MovePPairSecond'
1958
  MCK_Reg29, // derived register class
1959
  MCK_Reg27, // derived register class
1960
  MCK_Reg10, // derived register class
1961
  MCK_Reg8, // derived register class
1962
  MCK_Reg44, // derived register class
1963
  MCK_Reg25, // derived register class
1964
  MCK_Reg22, // derived register class
1965
  MCK_Reg21, // derived register class
1966
  MCK_CPU16Regs, // register class 'CPU16Regs,GPRMM16'
1967
  MCK_FCC, // register class 'FCC'
1968
  MCK_GPRMM16MoveP, // register class 'GPRMM16MoveP'
1969
  MCK_GPRMM16Zero, // register class 'GPRMM16Zero'
1970
  MCK_MSACtrl, // register class 'MSACtrl'
1971
  MCK_Reg26, // derived register class
1972
  MCK_CPU16RegsPlusSP, // register class 'CPU16RegsPlusSP'
1973
  MCK_Reg50, // derived register class
1974
  MCK_Reg47, // derived register class
1975
  MCK_Reg42, // derived register class
1976
  MCK_Reg39, // derived register class
1977
  MCK_AFGR64, // register class 'AFGR64'
1978
  MCK_MSA128WEvens, // register class 'MSA128WEvens'
1979
  MCK_Reg45, // derived register class
1980
  MCK_Reg24, // derived register class
1981
  MCK_GPR32NONZERO, // register class 'GPR32NONZERO'
1982
  MCK_CCR, // register class 'CCR'
1983
  MCK_COP0, // register class 'COP0'
1984
  MCK_COP2, // register class 'COP2'
1985
  MCK_COP3, // register class 'COP3'
1986
  MCK_DSPR, // register class 'DSPR,GPR32'
1987
  MCK_FGR32, // register class 'FGR32,FGRCC'
1988
  MCK_FGR64, // register class 'FGR64'
1989
  MCK_FGRH32, // register class 'FGRH32'
1990
  MCK_GPR64, // register class 'GPR64'
1991
  MCK_HWRegs, // register class 'HWRegs'
1992
  MCK_MSA128F16, // register class 'MSA128F16,MSA128B,MSA128D,MSA128H,MSA128W'
1993
  MCK_OddSP, // register class 'OddSP'
1994
  MCK_LAST_REGISTER = MCK_OddSP,
1995
  MCK_ACC64DSPAsmReg, // user defined class 'ACC64DSPAsmOperand'
1996
  MCK_AFGR64AsmReg, // user defined class 'AFGR64AsmOperand'
1997
  MCK_CCRAsmReg, // user defined class 'CCRAsmOperand'
1998
  MCK_COP0AsmReg, // user defined class 'COP0AsmOperand'
1999
  MCK_COP2AsmReg, // user defined class 'COP2AsmOperand'
2000
  MCK_COP3AsmReg, // user defined class 'COP3AsmOperand'
2001
  MCK_FCCAsmReg, // user defined class 'FCCRegsAsmOperand'
2002
  MCK_FGR32AsmReg, // user defined class 'FGR32AsmOperand'
2003
  MCK_FGR64AsmReg, // user defined class 'FGR64AsmOperand'
2004
  MCK_FGRH32AsmReg, // user defined class 'FGRH32AsmOperand'
2005
  MCK_GPR32AsmReg, // user defined class 'GPR32AsmOperand'
2006
  MCK_GPR32NonZeroAsmReg, // user defined class 'GPR32NonZeroAsmOperand'
2007
  MCK_GPR32ZeroAsmReg, // user defined class 'GPR32ZeroAsmOperand'
2008
  MCK_GPR64AsmReg, // user defined class 'GPR64AsmOperand'
2009
  MCK_GPRMM16AsmReg, // user defined class 'GPRMM16AsmOperand'
2010
  MCK_GPRMM16AsmRegMoveP, // user defined class 'GPRMM16AsmOperandMoveP'
2011
  MCK_GPRMM16AsmRegMovePPairFirst, // user defined class 'GPRMM16AsmOperandMovePPairFirst'
2012
  MCK_GPRMM16AsmRegMovePPairSecond, // user defined class 'GPRMM16AsmOperandMovePPairSecond'
2013
  MCK_GPRMM16AsmRegZero, // user defined class 'GPRMM16AsmOperandZero'
2014
  MCK_HI32DSPAsmReg, // user defined class 'HI32DSPAsmOperand'
2015
  MCK_HWRegsAsmReg, // user defined class 'HWRegsAsmOperand'
2016
  MCK_Imm, // user defined class 'ImmAsmOperand'
2017
  MCK_LO32DSPAsmReg, // user defined class 'LO32DSPAsmOperand'
2018
  MCK_MSA128AsmReg, // user defined class 'MSA128AsmOperand'
2019
  MCK_MSACtrlAsmReg, // user defined class 'MSACtrlAsmOperand'
2020
  MCK_MicroMipsMemGP, // user defined class 'MicroMipsMemGPAsmOperand'
2021
  MCK_MicroMipsMem, // user defined class 'MicroMipsMemGPRMM16AsmOperand'
2022
  MCK_MicroMipsMemSP, // user defined class 'MicroMipsMemSPAsmOperand'
2023
  MCK_InvNum, // user defined class 'MipsInvertedImmoperand'
2024
  MCK_JumpTarget, // user defined class 'MipsJumpTargetAsmOperand'
2025
  MCK_MemOffsetSimm10, // user defined class 'MipsMemSimm10AsmOperand'
2026
  MCK_MemOffsetSimm10_1, // user defined class 'MipsMemSimm10Lsl1AsmOperand'
2027
  MCK_MemOffsetSimm10_2, // user defined class 'MipsMemSimm10Lsl2AsmOperand'
2028
  MCK_MemOffsetSimm10_3, // user defined class 'MipsMemSimm10Lsl3AsmOperand'
2029
  MCK_MemOffsetSimm11, // user defined class 'MipsMemSimm11AsmOperand'
2030
  MCK_MemOffsetSimm12, // user defined class 'MipsMemSimm12AsmOperand'
2031
  MCK_MemOffsetSimm16, // user defined class 'MipsMemSimm16AsmOperand'
2032
  MCK_MemOffsetSimm9, // user defined class 'MipsMemSimm9AsmOperand'
2033
  MCK_MemOffsetSimmPtr, // user defined class 'MipsMemSimmPtrAsmOperand'
2034
  MCK_MemOffsetUimm4, // user defined class 'MipsMemUimm4AsmOperand'
2035
  MCK_Mem, // user defined class 'MipsMemAsmOperand'
2036
  MCK_RegList16, // user defined class 'RegList16AsmOperand'
2037
  MCK_RegList, // user defined class 'RegListAsmOperand'
2038
  MCK_Simm19_Lsl2, // user defined class 'Simm19Lsl2AsmOperand'
2039
  MCK_StrictlyAFGR64AsmReg, // user defined class 'StrictlyAFGR64AsmOperand'
2040
  MCK_StrictlyFGR32AsmReg, // user defined class 'StrictlyFGR32AsmOperand'
2041
  MCK_StrictlyFGR64AsmReg, // user defined class 'StrictlyFGR64AsmOperand'
2042
  MCK_ConstantImmz, // user defined class 'ConstantImmzAsmOperandClass'
2043
  MCK_ConstantUImm1_0, // user defined class 'ConstantUImm1AsmOperandClass'
2044
  MCK_ConstantUImm2_0, // user defined class 'ConstantUImm2AsmOperandClass'
2045
  MCK_ConstantUImm2_1, // user defined class 'ConstantUImm2Plus1AsmOperandClass'
2046
  MCK_ConstantUImm3_0, // user defined class 'ConstantUImm3AsmOperandClass'
2047
  MCK_ConstantSImm4_0, // user defined class 'ConstantSImm4AsmOperandClass'
2048
  MCK_ConstantUImm4_0, // user defined class 'ConstantUImm4AsmOperandClass'
2049
  MCK_ConstantSImm5_0, // user defined class 'ConstantSImm5AsmOperandClass'
2050
  MCK_ConstantUImm5_0, // user defined class 'ConstantUImm5AsmOperandClass'
2051
  MCK_ConstantUImm5_1, // user defined class 'ConstantUImm5Plus1AsmOperandClass'
2052
  MCK_ConstantUImm5_Plus1_Report_UImm6, // user defined class 'ConstantUImm5Plus1ReportUImm6AsmOperandClass'
2053
  MCK_ConstantUImm5_32_Norm, // user defined class 'ConstantUImm5Plus32NormalizeAsmOperandClass'
2054
  MCK_ConstantUImm5_32, // user defined class 'ConstantUImm5Plus32AsmOperandClass'
2055
  MCK_ConstantUImm5_0_Report_UImm6, // user defined class 'ConstantUImm5ReportUImm6AsmOperandClass'
2056
  MCK_ConstantUImm5_33, // user defined class 'ConstantUImm5Plus33AsmOperandClass'
2057
  MCK_ConstantUImmRange2_64, // user defined class 'ConstantUImm5_Range2_64AsmOperandClass'
2058
  MCK_UImm5Lsl2, // user defined class 'ConstantUImm5Lsl2AsmOperandClass'
2059
  MCK_ConstantSImm6_0, // user defined class 'ConstantSImm6AsmOperandClass'
2060
  MCK_ConstantUImm6_0, // user defined class 'ConstantUImm6AsmOperandClass'
2061
  MCK_UImm6Lsl2, // user defined class 'ConstantUImm6Lsl2AsmOperandClass'
2062
  MCK_ConstantUImm7_0, // user defined class 'ConstantUImm7AsmOperandClass'
2063
  MCK_UImm7_N1, // user defined class 'ConstantUImm7Sub1AsmOperandClass'
2064
  MCK_ConstantUImm8_0, // user defined class 'ConstantUImm8AsmOperandClass'
2065
  MCK_SImm7Lsl2, // user defined class 'ConstantSImm7Lsl2AsmOperandClass'
2066
  MCK_ConstantSImm9_0, // user defined class 'ConstantSImm9AsmOperandClass'
2067
  MCK_ConstantSImm10_0, // user defined class 'ConstantSImm10AsmOperandClass'
2068
  MCK_ConstantUImm10_0, // user defined class 'ConstantUImm10AsmOperandClass'
2069
  MCK_SImm10Lsl1, // user defined class 'ConstantSImm10Lsl1AsmOperandClass'
2070
  MCK_ConstantSImm11_0, // user defined class 'ConstantSImm11AsmOperandClass'
2071
  MCK_SImm10Lsl2, // user defined class 'ConstantSImm10Lsl2AsmOperandClass'
2072
  MCK_SImm10Lsl3, // user defined class 'ConstantSImm10Lsl3AsmOperandClass'
2073
  MCK_SImm16, // user defined class 'SImm16AsmOperandClass'
2074
  MCK_SImm16_Relaxed, // user defined class 'SImm16RelaxedAsmOperandClass'
2075
  MCK_UImm16_AltRelaxed, // user defined class 'UImm16AltRelaxedAsmOperandClass'
2076
  MCK_UImm16, // user defined class 'UImm16AsmOperandClass'
2077
  MCK_SImm19Lsl2, // user defined class 'ConstantSImm19Lsl2AsmOperandClass'
2078
  MCK_UImm16_Relaxed, // user defined class 'UImm16RelaxedAsmOperandClass'
2079
  MCK_ConstantUImm20_0, // user defined class 'ConstantUImm20AsmOperandClass'
2080
  MCK_ConstantUImm26_0, // user defined class 'ConstantUImm26AsmOperandClass'
2081
  MCK_SImm32, // user defined class 'SImm32AsmOperandClass'
2082
  MCK_SImm32_Relaxed, // user defined class 'SImm32RelaxedAsmOperandClass'
2083
  MCK_UImm32_Coerced, // user defined class 'UImm32CoercedAsmOperandClass'
2084
  NumMatchClassKinds
2085
};
2086
2087
}
2088
2089
14.4k
static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
2090
14.4k
  return MCTargetAsmParser::Match_InvalidOperand;
2091
14.4k
}
2092
2093
880
static MatchClassKind matchTokenString(StringRef Name) {
2094
880
  switch (Name.size()) {
2095
880
  
default: break0
;
2096
880
  case 1:  // 6 strings to match.
2097
880
    switch (Name[0]) {
2098
880
    
default: break0
;
2099
880
    case '#':  // 1 string to match.
2100
0
      return MCK__35_;  // "#"
2101
880
    case '(':  // 1 string to match.
2102
363
      return MCK__40_;  // "("
2103
880
    case ')':  // 1 string to match.
2104
363
      return MCK__41_;  // ")"
2105
880
    case '0':  // 1 string to match.
2106
0
      return MCK_0;  // "0"
2107
880
    case '[':  // 1 string to match.
2108
112
      return MCK__91_;  // "["
2109
880
    case ']':  // 1 string to match.
2110
42
      return MCK__93_;  // "]"
2111
0
    }
2112
0
    break;
2113
0
  case 2:  // 1 string to match.
2114
0
    if (memcmp(Name.data()+0, "16", 2) != 0)
2115
0
      break;
2116
0
    return MCK_16;   // "16"
2117
0
  case 3:  // 1 string to match.
2118
0
    if (memcmp(Name.data()+0, "bit", 3) != 0)
2119
0
      break;
2120
0
    return MCK_bit;  // "bit"
2121
0
  case 4:  // 1 string to match.
2122
0
    if (memcmp(Name.data()+0, "inst", 4) != 0)
2123
0
      break;
2124
0
    return MCK_inst;  // "inst"
2125
0
  }
2126
0
  return InvalidMatchClass;
2127
0
}
2128
2129
/// isSubclass - Compute whether \p A is a subclass of \p B.
2130
39.6k
static bool isSubclass(MatchClassKind A, MatchClassKind B) {
2131
39.6k
  if (A == B)
2132
1.00k
    return true;
2133
38.6k
2134
38.6k
  switch (A) {
2135
38.6k
  default:
2136
24.2k
    return false;
2137
38.6k
2138
38.6k
  case MCK_Reg37:
2139
0
    switch (B) {
2140
0
    default: return false;
2141
0
    case MCK_Reg24: return true;
2142
0
    case MCK_GPR64: return true;
2143
0
    }
2144
0
2145
0
  case MCK_Reg19:
2146
0
    switch (B) {
2147
0
    default: return false;
2148
0
    case MCK_Reg23: return true;
2149
0
    case MCK_Reg22: return true;
2150
0
    case MCK_Reg21: return true;
2151
0
    case MCK_GPR64: return true;
2152
0
    }
2153
0
2154
0
  case MCK_ACC64:
2155
0
    return B == MCK_ACC64DSP;
2156
0
2157
133
  case MCK_CPURAReg:
2158
133
    switch (B) {
2159
133
    default: return false;
2160
133
    
case MCK_GPR32NONZERO: return true0
;
2161
133
    
case MCK_DSPR: return true0
;
2162
0
    }
2163
0
2164
548
  case MCK_CPUSPReg:
2165
548
    switch (B) {
2166
548
    default: return false;
2167
548
    
case MCK_CPU16RegsPlusSP: return true0
;
2168
548
    
case MCK_GPR32NONZERO: return true0
;
2169
548
    
case MCK_DSPR: return true0
;
2170
0
    }
2171
0
2172
0
  case MCK_GP32:
2173
0
    switch (B) {
2174
0
    default: return false;
2175
0
    case MCK_GPR32NONZERO: return true;
2176
0
    case MCK_DSPR: return true;
2177
0
    }
2178
0
2179
0
  case MCK_GP64:
2180
0
    switch (B) {
2181
0
    default: return false;
2182
0
    case MCK_Reg24: return true;
2183
0
    case MCK_GPR64: return true;
2184
0
    }
2185
0
2186
351
  case MCK_GPR32ZERO:
2187
351
    switch (B) {
2188
351
    default: return false;
2189
351
    
case MCK_Reg4: return true0
;
2190
351
    
case MCK_GPRMM16MoveP: return true0
;
2191
351
    
case MCK_GPRMM16Zero: return true0
;
2192
351
    
case MCK_DSPR: return true0
;
2193
0
    }
2194
0
2195
0
  case MCK_HI32:
2196
0
    return B == MCK_HI32DSP;
2197
0
2198
0
  case MCK_LO32:
2199
0
    return B == MCK_LO32DSP;
2200
0
2201
0
  case MCK_SP64:
2202
0
    switch (B) {
2203
0
    default: return false;
2204
0
    case MCK_Reg26: return true;
2205
0
    case MCK_Reg24: return true;
2206
0
    case MCK_GPR64: return true;
2207
0
    }
2208
0
2209
0
  case MCK_Reg32:
2210
0
    switch (B) {
2211
0
    default: return false;
2212
0
    case MCK_Reg33: return true;
2213
0
    case MCK_Reg31: return true;
2214
0
    case MCK_Reg34: return true;
2215
0
    case MCK_Reg27: return true;
2216
0
    case MCK_Reg25: return true;
2217
0
    case MCK_Reg21: return true;
2218
0
    case MCK_Reg26: return true;
2219
0
    case MCK_Reg24: return true;
2220
0
    case MCK_GPR64: return true;
2221
0
    }
2222
0
2223
0
  case MCK_Reg13:
2224
0
    switch (B) {
2225
0
    default: return false;
2226
0
    case MCK_Reg14: return true;
2227
0
    case MCK_GPRMM16MovePPairFirst: return true;
2228
0
    case MCK_GPRMM16MovePPairSecond: return true;
2229
0
    case MCK_Reg8: return true;
2230
0
    case MCK_CPU16Regs: return true;
2231
0
    case MCK_GPRMM16Zero: return true;
2232
0
    case MCK_CPU16RegsPlusSP: return true;
2233
0
    case MCK_GPR32NONZERO: return true;
2234
0
    case MCK_DSPR: return true;
2235
0
    }
2236
0
2237
0
  case MCK_Reg33:
2238
0
    switch (B) {
2239
0
    default: return false;
2240
0
    case MCK_Reg34: return true;
2241
0
    case MCK_Reg27: return true;
2242
0
    case MCK_Reg25: return true;
2243
0
    case MCK_Reg21: return true;
2244
0
    case MCK_Reg26: return true;
2245
0
    case MCK_Reg24: return true;
2246
0
    case MCK_GPR64: return true;
2247
0
    }
2248
0
2249
0
  case MCK_Reg31:
2250
0
    switch (B) {
2251
0
    default: return false;
2252
0
    case MCK_Reg27: return true;
2253
0
    case MCK_Reg25: return true;
2254
0
    case MCK_Reg21: return true;
2255
0
    case MCK_Reg26: return true;
2256
0
    case MCK_Reg24: return true;
2257
0
    case MCK_GPR64: return true;
2258
0
    }
2259
0
2260
0
  case MCK_Reg30:
2261
0
    switch (B) {
2262
0
    default: return false;
2263
0
    case MCK_Reg28: return true;
2264
0
    case MCK_Reg23: return true;
2265
0
    case MCK_Reg29: return true;
2266
0
    case MCK_Reg27: return true;
2267
0
    case MCK_Reg25: return true;
2268
0
    case MCK_Reg22: return true;
2269
0
    case MCK_Reg21: return true;
2270
0
    case MCK_Reg26: return true;
2271
0
    case MCK_Reg24: return true;
2272
0
    case MCK_GPR64: return true;
2273
0
    }
2274
0
2275
0
  case MCK_Reg14:
2276
0
    switch (B) {
2277
0
    default: return false;
2278
0
    case MCK_GPRMM16MovePPairSecond: return true;
2279
0
    case MCK_Reg8: return true;
2280
0
    case MCK_CPU16Regs: return true;
2281
0
    case MCK_GPRMM16Zero: return true;
2282
0
    case MCK_CPU16RegsPlusSP: return true;
2283
0
    case MCK_GPR32NONZERO: return true;
2284
0
    case MCK_DSPR: return true;
2285
0
    }
2286
0
2287
0
  case MCK_Reg11:
2288
0
    switch (B) {
2289
0
    default: return false;
2290
0
    case MCK_Reg9: return true;
2291
0
    case MCK_Reg4: return true;
2292
0
    case MCK_Reg10: return true;
2293
0
    case MCK_Reg8: return true;
2294
0
    case MCK_CPU16Regs: return true;
2295
0
    case MCK_GPRMM16MoveP: return true;
2296
0
    case MCK_GPRMM16Zero: return true;
2297
0
    case MCK_CPU16RegsPlusSP: return true;
2298
0
    case MCK_GPR32NONZERO: return true;
2299
0
    case MCK_DSPR: return true;
2300
0
    }
2301
0
2302
0
  case MCK_GPRMM16MovePPairFirst:
2303
0
    switch (B) {
2304
0
    default: return false;
2305
0
    case MCK_Reg8: return true;
2306
0
    case MCK_CPU16Regs: return true;
2307
0
    case MCK_GPRMM16Zero: return true;
2308
0
    case MCK_CPU16RegsPlusSP: return true;
2309
0
    case MCK_GPR32NONZERO: return true;
2310
0
    case MCK_DSPR: return true;
2311
0
    }
2312
0
2313
0
  case MCK_Reg28:
2314
0
    switch (B) {
2315
0
    default: return false;
2316
0
    case MCK_Reg29: return true;
2317
0
    case MCK_Reg25: return true;
2318
0
    case MCK_Reg22: return true;
2319
0
    case MCK_Reg26: return true;
2320
0
    case MCK_Reg24: return true;
2321
0
    case MCK_GPR64: return true;
2322
0
    }
2323
0
2324
0
  case MCK_Reg23:
2325
0
    switch (B) {
2326
0
    default: return false;
2327
0
    case MCK_Reg22: return true;
2328
0
    case MCK_Reg21: return true;
2329
0
    case MCK_GPR64: return true;
2330
0
    }
2331
0
2332
0
  case MCK_Reg9:
2333
0
    switch (B) {
2334
0
    default: return false;
2335
0
    case MCK_Reg10: return true;
2336
0
    case MCK_CPU16Regs: return true;
2337
0
    case MCK_GPRMM16MoveP: return true;
2338
0
    case MCK_CPU16RegsPlusSP: return true;
2339
0
    case MCK_GPR32NONZERO: return true;
2340
0
    case MCK_DSPR: return true;
2341
0
    }
2342
0
2343
0
  case MCK_Reg4:
2344
0
    switch (B) {
2345
0
    default: return false;
2346
0
    case MCK_GPRMM16MoveP: return true;
2347
0
    case MCK_GPRMM16Zero: return true;
2348
0
    case MCK_DSPR: return true;
2349
0
    }
2350
0
2351
0
  case MCK_Reg34:
2352
0
    switch (B) {
2353
0
    default: return false;
2354
0
    case MCK_Reg24: return true;
2355
0
    case MCK_GPR64: return true;
2356
0
    }
2357
0
2358
0
  case MCK_GPRMM16MovePPairSecond:
2359
0
    switch (B) {
2360
0
    default: return false;
2361
0
    case MCK_GPR32NONZERO: return true;
2362
0
    case MCK_DSPR: return true;
2363
0
    }
2364
0
2365
0
  case MCK_Reg29:
2366
0
    switch (B) {
2367
0
    default: return false;
2368
0
    case MCK_Reg22: return true;
2369
0
    case MCK_Reg24: return true;
2370
0
    case MCK_GPR64: return true;
2371
0
    }
2372
0
2373
0
  case MCK_Reg27:
2374
0
    switch (B) {
2375
0
    default: return false;
2376
0
    case MCK_Reg25: return true;
2377
0
    case MCK_Reg21: return true;
2378
0
    case MCK_Reg26: return true;
2379
0
    case MCK_Reg24: return true;
2380
0
    case MCK_GPR64: return true;
2381
0
    }
2382
0
2383
0
  case MCK_Reg10:
2384
0
    switch (B) {
2385
0
    default: return false;
2386
0
    case MCK_GPRMM16MoveP: return true;
2387
0
    case MCK_GPR32NONZERO: return true;
2388
0
    case MCK_DSPR: return true;
2389
0
    }
2390
0
2391
0
  case MCK_Reg8:
2392
0
    switch (B) {
2393
0
    default: return false;
2394
0
    case MCK_CPU16Regs: return true;
2395
0
    case MCK_GPRMM16Zero: return true;
2396
0
    case MCK_CPU16RegsPlusSP: return true;
2397
0
    case MCK_GPR32NONZERO: return true;
2398
0
    case MCK_DSPR: return true;
2399
0
    }
2400
0
2401
0
  case MCK_Reg44:
2402
0
    switch (B) {
2403
0
    default: return false;
2404
0
    case MCK_AFGR64: return true;
2405
0
    case MCK_Reg45: return true;
2406
0
    case MCK_OddSP: return true;
2407
0
    }
2408
0
2409
0
  case MCK_Reg25:
2410
0
    switch (B) {
2411
0
    default: return false;
2412
0
    case MCK_Reg26: return true;
2413
0
    case MCK_Reg24: return true;
2414
0
    case MCK_GPR64: return true;
2415
0
    }
2416
0
2417
0
  case MCK_Reg22:
2418
0
    return B == MCK_GPR64;
2419
0
2420
0
  case MCK_Reg21:
2421
0
    return B == MCK_GPR64;
2422
0
2423
13.3k
  case MCK_CPU16Regs:
2424
13.3k
    switch (B) {
2425
13.3k
    default: return false;
2426
13.3k
    
case MCK_CPU16RegsPlusSP: return true0
;
2427
13.3k
    
case MCK_GPR32NONZERO: return true0
;
2428
13.3k
    
case MCK_DSPR: return true0
;
2429
0
    }
2430
0
2431
0
  case MCK_GPRMM16MoveP:
2432
0
    return B == MCK_DSPR;
2433
0
2434
0
  case MCK_GPRMM16Zero:
2435
0
    return B == MCK_DSPR;
2436
0
2437
0
  case MCK_Reg26:
2438
0
    switch (B) {
2439
0
    default: return false;
2440
0
    case MCK_Reg24: return true;
2441
0
    case MCK_GPR64: return true;
2442
0
    }
2443
0
2444
0
  case MCK_CPU16RegsPlusSP:
2445
0
    switch (B) {
2446
0
    default: return false;
2447
0
    case MCK_GPR32NONZERO: return true;
2448
0
    case MCK_DSPR: return true;
2449
0
    }
2450
0
2451
0
  case MCK_Reg50:
2452
0
    return B == MCK_MSA128F16;
2453
0
2454
0
  case MCK_Reg47:
2455
0
    switch (B) {
2456
0
    default: return false;
2457
0
    case MCK_Reg45: return true;
2458
0
    case MCK_FGR64: return true;
2459
0
    case MCK_OddSP: return true;
2460
0
    }
2461
0
2462
0
  case MCK_Reg42:
2463
0
    switch (B) {
2464
0
    default: return false;
2465
0
    case MCK_FGRH32: return true;
2466
0
    case MCK_OddSP: return true;
2467
0
    }
2468
0
2469
0
  case MCK_Reg39:
2470
0
    switch (B) {
2471
0
    default: return false;
2472
0
    case MCK_FGR32: return true;
2473
0
    case MCK_OddSP: return true;
2474
0
    }
2475
0
2476
0
  case MCK_MSA128WEvens:
2477
0
    return B == MCK_MSA128F16;
2478
0
2479
0
  case MCK_Reg45:
2480
0
    return B == MCK_OddSP;
2481
0
2482
0
  case MCK_Reg24:
2483
0
    return B == MCK_GPR64;
2484
0
2485
0
  case MCK_GPR32NONZERO:
2486
0
    return B == MCK_DSPR;
2487
0
2488
0
  case MCK_MemOffsetSimm10:
2489
0
    return B == MCK_Mem;
2490
0
2491
0
  case MCK_MemOffsetSimm10_1:
2492
0
    return B == MCK_Mem;
2493
0
2494
0
  case MCK_MemOffsetSimm10_2:
2495
0
    return B == MCK_Mem;
2496
0
2497
0
  case MCK_MemOffsetSimm10_3:
2498
0
    return B == MCK_Mem;
2499
0
2500
0
  case MCK_MemOffsetSimm11:
2501
0
    return B == MCK_Mem;
2502
0
2503
0
  case MCK_MemOffsetSimm12:
2504
0
    return B == MCK_Mem;
2505
0
2506
0
  case MCK_MemOffsetSimm16:
2507
0
    return B == MCK_Mem;
2508
0
2509
0
  case MCK_MemOffsetSimm9:
2510
0
    return B == MCK_Mem;
2511
0
2512
0
  case MCK_MemOffsetSimmPtr:
2513
0
    return B == MCK_Mem;
2514
0
2515
8
  case MCK_MemOffsetUimm4:
2516
8
    return B == MCK_Mem;
2517
0
2518
0
  case MCK_ConstantImmz:
2519
0
    switch (B) {
2520
0
    default: return false;
2521
0
    case MCK_ConstantUImm1_0: return true;
2522
0
    case MCK_ConstantUImm2_0: return true;
2523
0
    case MCK_ConstantUImm3_0: return true;
2524
0
    case MCK_ConstantSImm4_0: return true;
2525
0
    case MCK_ConstantUImm4_0: return true;
2526
0
    case MCK_ConstantSImm5_0: return true;
2527
0
    case MCK_ConstantUImm5_0: return true;
2528
0
    case MCK_ConstantUImm5_1: return true;
2529
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2530
0
    case MCK_ConstantUImm5_32_Norm: return true;
2531
0
    case MCK_ConstantUImm5_32: return true;
2532
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2533
0
    case MCK_ConstantUImm5_33: return true;
2534
0
    case MCK_ConstantUImmRange2_64: return true;
2535
0
    case MCK_UImm5Lsl2: return true;
2536
0
    case MCK_ConstantSImm6_0: return true;
2537
0
    case MCK_ConstantUImm6_0: return true;
2538
0
    case MCK_UImm6Lsl2: return true;
2539
0
    case MCK_ConstantUImm7_0: return true;
2540
0
    case MCK_UImm7_N1: return true;
2541
0
    case MCK_ConstantUImm8_0: return true;
2542
0
    case MCK_SImm7Lsl2: return true;
2543
0
    case MCK_ConstantSImm9_0: return true;
2544
0
    case MCK_ConstantSImm10_0: return true;
2545
0
    case MCK_ConstantUImm10_0: return true;
2546
0
    case MCK_SImm10Lsl1: return true;
2547
0
    case MCK_ConstantSImm11_0: return true;
2548
0
    case MCK_SImm10Lsl2: return true;
2549
0
    case MCK_SImm10Lsl3: return true;
2550
0
    case MCK_SImm16: return true;
2551
0
    case MCK_SImm16_Relaxed: return true;
2552
0
    case MCK_UImm16_Relaxed: return true;
2553
0
    case MCK_ConstantUImm20_0: return true;
2554
0
    case MCK_ConstantUImm26_0: return true;
2555
0
    case MCK_SImm32: return true;
2556
0
    case MCK_SImm32_Relaxed: return true;
2557
0
    case MCK_UImm32_Coerced: return true;
2558
0
    }
2559
0
2560
0
  case MCK_ConstantUImm1_0:
2561
0
    switch (B) {
2562
0
    default: return false;
2563
0
    case MCK_ConstantUImm2_0: return true;
2564
0
    case MCK_ConstantUImm3_0: return true;
2565
0
    case MCK_ConstantSImm4_0: return true;
2566
0
    case MCK_ConstantUImm4_0: return true;
2567
0
    case MCK_ConstantSImm5_0: return true;
2568
0
    case MCK_ConstantUImm5_0: return true;
2569
0
    case MCK_ConstantUImm5_1: return true;
2570
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2571
0
    case MCK_ConstantUImm5_32_Norm: return true;
2572
0
    case MCK_ConstantUImm5_32: return true;
2573
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2574
0
    case MCK_ConstantUImm5_33: return true;
2575
0
    case MCK_ConstantUImmRange2_64: return true;
2576
0
    case MCK_UImm5Lsl2: return true;
2577
0
    case MCK_ConstantSImm6_0: return true;
2578
0
    case MCK_ConstantUImm6_0: return true;
2579
0
    case MCK_UImm6Lsl2: return true;
2580
0
    case MCK_ConstantUImm7_0: return true;
2581
0
    case MCK_UImm7_N1: return true;
2582
0
    case MCK_ConstantUImm8_0: return true;
2583
0
    case MCK_SImm7Lsl2: return true;
2584
0
    case MCK_ConstantSImm9_0: return true;
2585
0
    case MCK_ConstantSImm10_0: return true;
2586
0
    case MCK_ConstantUImm10_0: return true;
2587
0
    case MCK_SImm10Lsl1: return true;
2588
0
    case MCK_ConstantSImm11_0: return true;
2589
0
    case MCK_SImm10Lsl2: return true;
2590
0
    case MCK_SImm10Lsl3: return true;
2591
0
    case MCK_SImm16: return true;
2592
0
    case MCK_SImm16_Relaxed: return true;
2593
0
    case MCK_UImm16_Relaxed: return true;
2594
0
    case MCK_ConstantUImm20_0: return true;
2595
0
    case MCK_ConstantUImm26_0: return true;
2596
0
    case MCK_SImm32: return true;
2597
0
    case MCK_SImm32_Relaxed: return true;
2598
0
    case MCK_UImm32_Coerced: return true;
2599
0
    }
2600
0
2601
6
  case MCK_ConstantUImm2_0:
2602
6
    switch (B) {
2603
6
    default: return false;
2604
6
    
case MCK_ConstantUImm3_0: return true0
;
2605
6
    
case MCK_ConstantSImm4_0: return true0
;
2606
6
    
case MCK_ConstantUImm4_0: return true0
;
2607
6
    
case MCK_ConstantSImm5_0: return true0
;
2608
6
    
case MCK_ConstantUImm5_0: return true0
;
2609
6
    
case MCK_ConstantUImm5_1: return true0
;
2610
6
    
case MCK_ConstantUImm5_Plus1_Report_UImm6: return true0
;
2611
6
    
case MCK_ConstantUImm5_32_Norm: return true0
;
2612
6
    
case MCK_ConstantUImm5_32: return true0
;
2613
6
    
case MCK_ConstantUImm5_0_Report_UImm6: return true0
;
2614
6
    
case MCK_ConstantUImm5_33: return true0
;
2615
6
    
case MCK_ConstantUImmRange2_64: return true0
;
2616
6
    
case MCK_UImm5Lsl2: return true0
;
2617
6
    
case MCK_ConstantSImm6_0: return true0
;
2618
6
    
case MCK_ConstantUImm6_0: return true0
;
2619
6
    
case MCK_UImm6Lsl2: return true0
;
2620
6
    
case MCK_ConstantUImm7_0: return true0
;
2621
6
    
case MCK_UImm7_N1: return true0
;
2622
6
    
case MCK_ConstantUImm8_0: return true0
;
2623
6
    
case MCK_SImm7Lsl2: return true0
;
2624
6
    
case MCK_ConstantSImm9_0: return true0
;
2625
6
    
case MCK_ConstantSImm10_0: return true0
;
2626
6
    
case MCK_ConstantUImm10_0: return true0
;
2627
6
    
case MCK_SImm10Lsl1: return true0
;
2628
6
    
case MCK_ConstantSImm11_0: return true0
;
2629
6
    
case MCK_SImm10Lsl2: return true0
;
2630
6
    
case MCK_SImm10Lsl3: return true0
;
2631
6
    
case MCK_SImm16: return true0
;
2632
6
    
case MCK_SImm16_Relaxed: return true0
;
2633
6
    
case MCK_UImm16_Relaxed: return true0
;
2634
6
    
case MCK_ConstantUImm20_0: return true0
;
2635
6
    
case MCK_ConstantUImm26_0: return true0
;
2636
6
    
case MCK_SImm32: return true0
;
2637
6
    
case MCK_SImm32_Relaxed: return true0
;
2638
6
    
case MCK_UImm32_Coerced: return true0
;
2639
0
    }
2640
0
2641
0
  case MCK_ConstantUImm2_1:
2642
0
    switch (B) {
2643
0
    default: return false;
2644
0
    case MCK_ConstantUImm3_0: return true;
2645
0
    case MCK_ConstantSImm4_0: return true;
2646
0
    case MCK_ConstantUImm4_0: return true;
2647
0
    case MCK_ConstantSImm5_0: return true;
2648
0
    case MCK_ConstantUImm5_0: return true;
2649
0
    case MCK_ConstantUImm5_1: return true;
2650
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2651
0
    case MCK_ConstantUImm5_32_Norm: return true;
2652
0
    case MCK_ConstantUImm5_32: return true;
2653
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2654
0
    case MCK_ConstantUImm5_33: return true;
2655
0
    case MCK_ConstantUImmRange2_64: return true;
2656
0
    case MCK_UImm5Lsl2: return true;
2657
0
    case MCK_ConstantSImm6_0: return true;
2658
0
    case MCK_ConstantUImm6_0: return true;
2659
0
    case MCK_UImm6Lsl2: return true;
2660
0
    case MCK_ConstantUImm7_0: return true;
2661
0
    case MCK_UImm7_N1: return true;
2662
0
    case MCK_ConstantUImm8_0: return true;
2663
0
    case MCK_SImm7Lsl2: return true;
2664
0
    case MCK_ConstantSImm9_0: return true;
2665
0
    case MCK_ConstantSImm10_0: return true;
2666
0
    case MCK_ConstantUImm10_0: return true;
2667
0
    case MCK_SImm10Lsl1: return true;
2668
0
    case MCK_ConstantSImm11_0: return true;
2669
0
    case MCK_SImm10Lsl2: return true;
2670
0
    case MCK_SImm10Lsl3: return true;
2671
0
    case MCK_SImm16: return true;
2672
0
    case MCK_SImm16_Relaxed: return true;
2673
0
    case MCK_UImm16_Relaxed: return true;
2674
0
    case MCK_ConstantUImm20_0: return true;
2675
0
    case MCK_ConstantUImm26_0: return true;
2676
0
    case MCK_SImm32: return true;
2677
0
    case MCK_SImm32_Relaxed: return true;
2678
0
    case MCK_UImm32_Coerced: return true;
2679
0
    }
2680
0
2681
0
  case MCK_ConstantUImm3_0:
2682
0
    switch (B) {
2683
0
    default: return false;
2684
0
    case MCK_ConstantSImm4_0: return true;
2685
0
    case MCK_ConstantUImm4_0: return true;
2686
0
    case MCK_ConstantSImm5_0: return true;
2687
0
    case MCK_ConstantUImm5_0: return true;
2688
0
    case MCK_ConstantUImm5_1: return true;
2689
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2690
0
    case MCK_ConstantUImm5_32_Norm: return true;
2691
0
    case MCK_ConstantUImm5_32: return true;
2692
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2693
0
    case MCK_ConstantUImm5_33: return true;
2694
0
    case MCK_ConstantUImmRange2_64: return true;
2695
0
    case MCK_UImm5Lsl2: return true;
2696
0
    case MCK_ConstantSImm6_0: return true;
2697
0
    case MCK_ConstantUImm6_0: return true;
2698
0
    case MCK_UImm6Lsl2: return true;
2699
0
    case MCK_ConstantUImm7_0: return true;
2700
0
    case MCK_UImm7_N1: return true;
2701
0
    case MCK_ConstantUImm8_0: return true;
2702
0
    case MCK_SImm7Lsl2: return true;
2703
0
    case MCK_ConstantSImm9_0: return true;
2704
0
    case MCK_ConstantSImm10_0: return true;
2705
0
    case MCK_ConstantUImm10_0: return true;
2706
0
    case MCK_SImm10Lsl1: return true;
2707
0
    case MCK_ConstantSImm11_0: return true;
2708
0
    case MCK_SImm10Lsl2: return true;
2709
0
    case MCK_SImm10Lsl3: return true;
2710
0
    case MCK_SImm16: return true;
2711
0
    case MCK_SImm16_Relaxed: return true;
2712
0
    case MCK_UImm16_Relaxed: return true;
2713
0
    case MCK_ConstantUImm20_0: return true;
2714
0
    case MCK_ConstantUImm26_0: return true;
2715
0
    case MCK_SImm32: return true;
2716
0
    case MCK_SImm32_Relaxed: return true;
2717
0
    case MCK_UImm32_Coerced: return true;
2718
0
    }
2719
0
2720
0
  case MCK_ConstantSImm4_0:
2721
0
    switch (B) {
2722
0
    default: return false;
2723
0
    case MCK_ConstantUImm4_0: return true;
2724
0
    case MCK_ConstantSImm5_0: return true;
2725
0
    case MCK_ConstantUImm5_0: return true;
2726
0
    case MCK_ConstantUImm5_1: return true;
2727
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2728
0
    case MCK_ConstantUImm5_32_Norm: return true;
2729
0
    case MCK_ConstantUImm5_32: return true;
2730
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2731
0
    case MCK_ConstantUImm5_33: return true;
2732
0
    case MCK_ConstantUImmRange2_64: return true;
2733
0
    case MCK_UImm5Lsl2: return true;
2734
0
    case MCK_ConstantSImm6_0: return true;
2735
0
    case MCK_ConstantUImm6_0: return true;
2736
0
    case MCK_UImm6Lsl2: return true;
2737
0
    case MCK_ConstantUImm7_0: return true;
2738
0
    case MCK_UImm7_N1: return true;
2739
0
    case MCK_ConstantUImm8_0: return true;
2740
0
    case MCK_SImm7Lsl2: return true;
2741
0
    case MCK_ConstantSImm9_0: return true;
2742
0
    case MCK_ConstantSImm10_0: return true;
2743
0
    case MCK_ConstantUImm10_0: return true;
2744
0
    case MCK_SImm10Lsl1: return true;
2745
0
    case MCK_ConstantSImm11_0: return true;
2746
0
    case MCK_SImm10Lsl2: return true;
2747
0
    case MCK_SImm10Lsl3: return true;
2748
0
    case MCK_SImm16: return true;
2749
0
    case MCK_SImm16_Relaxed: return true;
2750
0
    case MCK_UImm16_Relaxed: return true;
2751
0
    case MCK_ConstantUImm20_0: return true;
2752
0
    case MCK_ConstantUImm26_0: return true;
2753
0
    case MCK_SImm32: return true;
2754
0
    case MCK_SImm32_Relaxed: return true;
2755
0
    case MCK_UImm32_Coerced: return true;
2756
0
    }
2757
0
2758
6
  case MCK_ConstantUImm4_0:
2759
6
    switch (B) {
2760
6
    default: return false;
2761
6
    
case MCK_ConstantSImm5_0: return true0
;
2762
6
    
case MCK_ConstantUImm5_0: return true0
;
2763
6
    
case MCK_ConstantUImm5_1: return true0
;
2764
6
    
case MCK_ConstantUImm5_Plus1_Report_UImm6: return true0
;
2765
6
    
case MCK_ConstantUImm5_32_Norm: return true0
;
2766
6
    
case MCK_ConstantUImm5_32: return true0
;
2767
6
    
case MCK_ConstantUImm5_0_Report_UImm6: return true0
;
2768
6
    
case MCK_ConstantUImm5_33: return true0
;
2769
6
    
case MCK_ConstantUImmRange2_64: return true0
;
2770
6
    
case MCK_UImm5Lsl2: return true0
;
2771
6
    
case MCK_ConstantSImm6_0: return true0
;
2772
6
    
case MCK_ConstantUImm6_0: return true0
;
2773
6
    
case MCK_UImm6Lsl2: return true0
;
2774
6
    
case MCK_ConstantUImm7_0: return true0
;
2775
6
    
case MCK_UImm7_N1: return true0
;
2776
6
    
case MCK_ConstantUImm8_0: return true0
;
2777
6
    
case MCK_SImm7Lsl2: return true0
;
2778
6
    
case MCK_ConstantSImm9_0: return true0
;
2779
6
    
case MCK_ConstantSImm10_0: return true0
;
2780
6
    
case MCK_ConstantUImm10_0: return true0
;
2781
6
    
case MCK_SImm10Lsl1: return true0
;
2782
6
    
case MCK_ConstantSImm11_0: return true0
;
2783
6
    
case MCK_SImm10Lsl2: return true0
;
2784
6
    
case MCK_SImm10Lsl3: return true0
;
2785
6
    
case MCK_SImm16: return true0
;
2786
6
    
case MCK_SImm16_Relaxed: return true0
;
2787
6
    
case MCK_UImm16_Relaxed: return true0
;
2788
6
    
case MCK_ConstantUImm20_0: return true0
;
2789
6
    
case MCK_ConstantUImm26_0: return true0
;
2790
6
    
case MCK_SImm32: return true0
;
2791
6
    
case MCK_SImm32_Relaxed: return true0
;
2792
6
    
case MCK_UImm32_Coerced: return true0
;
2793
0
    }
2794
0
2795
0
  case MCK_ConstantSImm5_0:
2796
0
    switch (B) {
2797
0
    default: return false;
2798
0
    case MCK_ConstantUImm5_0: return true;
2799
0
    case MCK_ConstantUImm5_1: return true;
2800
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2801
0
    case MCK_ConstantUImm5_32_Norm: return true;
2802
0
    case MCK_ConstantUImm5_32: return true;
2803
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2804
0
    case MCK_ConstantUImm5_33: return true;
2805
0
    case MCK_ConstantUImmRange2_64: return true;
2806
0
    case MCK_UImm5Lsl2: return true;
2807
0
    case MCK_ConstantSImm6_0: return true;
2808
0
    case MCK_ConstantUImm6_0: return true;
2809
0
    case MCK_UImm6Lsl2: return true;
2810
0
    case MCK_ConstantUImm7_0: return true;
2811
0
    case MCK_UImm7_N1: return true;
2812
0
    case MCK_ConstantUImm8_0: return true;
2813
0
    case MCK_SImm7Lsl2: return true;
2814
0
    case MCK_ConstantSImm9_0: return true;
2815
0
    case MCK_ConstantSImm10_0: return true;
2816
0
    case MCK_ConstantUImm10_0: return true;
2817
0
    case MCK_SImm10Lsl1: return true;
2818
0
    case MCK_ConstantSImm11_0: return true;
2819
0
    case MCK_SImm10Lsl2: return true;
2820
0
    case MCK_SImm10Lsl3: return true;
2821
0
    case MCK_SImm16: return true;
2822
0
    case MCK_SImm16_Relaxed: return true;
2823
0
    case MCK_UImm16_Relaxed: return true;
2824
0
    case MCK_ConstantUImm20_0: return true;
2825
0
    case MCK_ConstantUImm26_0: return true;
2826
0
    case MCK_SImm32: return true;
2827
0
    case MCK_SImm32_Relaxed: return true;
2828
0
    case MCK_UImm32_Coerced: return true;
2829
0
    }
2830
0
2831
3
  case MCK_ConstantUImm5_0:
2832
3
    switch (B) {
2833
3
    default: return false;
2834
3
    
case MCK_ConstantUImm5_1: return true0
;
2835
3
    
case MCK_ConstantUImm5_Plus1_Report_UImm6: return true0
;
2836
3
    
case MCK_ConstantUImm5_32_Norm: return true0
;
2837
3
    
case MCK_ConstantUImm5_32: return true0
;
2838
3
    
case MCK_ConstantUImm5_0_Report_UImm6: return true0
;
2839
3
    
case MCK_ConstantUImm5_33: return true0
;
2840
3
    
case MCK_ConstantUImmRange2_64: return true0
;
2841
3
    
case MCK_UImm5Lsl2: return true0
;
2842
3
    
case MCK_ConstantSImm6_0: return true0
;
2843
3
    
case MCK_ConstantUImm6_0: return true0
;
2844
3
    
case MCK_UImm6Lsl2: return true0
;
2845
3
    
case MCK_ConstantUImm7_0: return true0
;
2846
3
    
case MCK_UImm7_N1: return true0
;
2847
3
    
case MCK_ConstantUImm8_0: return true0
;
2848
3
    
case MCK_SImm7Lsl2: return true0
;
2849
3
    
case MCK_ConstantSImm9_0: return true0
;
2850
3
    
case MCK_ConstantSImm10_0: return true0
;
2851
3
    
case MCK_ConstantUImm10_0: return true0
;
2852
3
    
case MCK_SImm10Lsl1: return true0
;
2853
3
    
case MCK_ConstantSImm11_0: return true0
;
2854
3
    
case MCK_SImm10Lsl2: return true0
;
2855
3
    
case MCK_SImm10Lsl3: return true0
;
2856
3
    
case MCK_SImm16: return true0
;
2857
3
    
case MCK_SImm16_Relaxed: return true0
;
2858
3
    
case MCK_UImm16_Relaxed: return true0
;
2859
3
    
case MCK_ConstantUImm20_0: return true0
;
2860
3
    
case MCK_ConstantUImm26_0: return true0
;
2861
3
    
case MCK_SImm32: return true0
;
2862
3
    
case MCK_SImm32_Relaxed: return true0
;
2863
3
    
case MCK_UImm32_Coerced: return true0
;
2864
0
    }
2865
0
2866
0
  case MCK_ConstantUImm5_1:
2867
0
    switch (B) {
2868
0
    default: return false;
2869
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2870
0
    case MCK_ConstantUImm5_32_Norm: return true;
2871
0
    case MCK_ConstantUImm5_32: return true;
2872
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2873
0
    case MCK_ConstantUImm5_33: return true;
2874
0
    case MCK_ConstantUImmRange2_64: return true;
2875
0
    case MCK_UImm5Lsl2: return true;
2876
0
    case MCK_ConstantSImm6_0: return true;
2877
0
    case MCK_ConstantUImm6_0: return true;
2878
0
    case MCK_UImm6Lsl2: return true;
2879
0
    case MCK_ConstantUImm7_0: return true;
2880
0
    case MCK_UImm7_N1: return true;
2881
0
    case MCK_ConstantUImm8_0: return true;
2882
0
    case MCK_SImm7Lsl2: return true;
2883
0
    case MCK_ConstantSImm9_0: return true;
2884
0
    case MCK_ConstantSImm10_0: return true;
2885
0
    case MCK_ConstantUImm10_0: return true;
2886
0
    case MCK_SImm10Lsl1: return true;
2887
0
    case MCK_ConstantSImm11_0: return true;
2888
0
    case MCK_SImm10Lsl2: return true;
2889
0
    case MCK_SImm10Lsl3: return true;
2890
0
    case MCK_SImm16: return true;
2891
0
    case MCK_SImm16_Relaxed: return true;
2892
0
    case MCK_UImm16_Relaxed: return true;
2893
0
    case MCK_ConstantUImm20_0: return true;
2894
0
    case MCK_ConstantUImm26_0: return true;
2895
0
    case MCK_SImm32: return true;
2896
0
    case MCK_SImm32_Relaxed: return true;
2897
0
    case MCK_UImm32_Coerced: return true;
2898
0
    }
2899
0
2900
0
  case MCK_ConstantUImm5_Plus1_Report_UImm6:
2901
0
    switch (B) {
2902
0
    default: return false;
2903
0
    case MCK_ConstantUImm5_32_Norm: return true;
2904
0
    case MCK_ConstantUImm5_32: return true;
2905
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2906
0
    case MCK_ConstantUImm5_33: return true;
2907
0
    case MCK_ConstantUImmRange2_64: return true;
2908
0
    case MCK_UImm5Lsl2: return true;
2909
0
    case MCK_ConstantSImm6_0: return true;
2910
0
    case MCK_ConstantUImm6_0: return true;
2911
0
    case MCK_UImm6Lsl2: return true;
2912
0
    case MCK_ConstantUImm7_0: return true;
2913
0
    case MCK_UImm7_N1: return true;
2914
0
    case MCK_ConstantUImm8_0: return true;
2915
0
    case MCK_SImm7Lsl2: return true;
2916
0
    case MCK_ConstantSImm9_0: return true;
2917
0
    case MCK_ConstantSImm10_0: return true;
2918
0
    case MCK_ConstantUImm10_0: return true;
2919
0
    case MCK_SImm10Lsl1: return true;
2920
0
    case MCK_ConstantSImm11_0: return true;
2921
0
    case MCK_SImm10Lsl2: return true;
2922
0
    case MCK_SImm10Lsl3: return true;
2923
0
    case MCK_SImm16: return true;
2924
0
    case MCK_SImm16_Relaxed: return true;
2925
0
    case MCK_UImm16_Relaxed: return true;
2926
0
    case MCK_ConstantUImm20_0: return true;
2927
0
    case MCK_ConstantUImm26_0: return true;
2928
0
    case MCK_SImm32: return true;
2929
0
    case MCK_SImm32_Relaxed: return true;
2930
0
    case MCK_UImm32_Coerced: return true;
2931
0
    }
2932
0
2933
0
  case MCK_ConstantUImm5_32_Norm:
2934
0
    switch (B) {
2935
0
    default: return false;
2936
0
    case MCK_ConstantUImm5_32: return true;
2937
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2938
0
    case MCK_ConstantUImm5_33: return true;
2939
0
    case MCK_ConstantUImmRange2_64: return true;
2940
0
    case MCK_UImm5Lsl2: return true;
2941
0
    case MCK_ConstantSImm6_0: return true;
2942
0
    case MCK_ConstantUImm6_0: return true;
2943
0
    case MCK_UImm6Lsl2: return true;
2944
0
    case MCK_ConstantUImm7_0: return true;
2945
0
    case MCK_UImm7_N1: return true;
2946
0
    case MCK_ConstantUImm8_0: return true;
2947
0
    case MCK_SImm7Lsl2: return true;
2948
0
    case MCK_ConstantSImm9_0: return true;
2949
0
    case MCK_ConstantSImm10_0: return true;
2950
0
    case MCK_ConstantUImm10_0: return true;
2951
0
    case MCK_SImm10Lsl1: return true;
2952
0
    case MCK_ConstantSImm11_0: return true;
2953
0
    case MCK_SImm10Lsl2: return true;
2954
0
    case MCK_SImm10Lsl3: return true;
2955
0
    case MCK_SImm16: return true;
2956
0
    case MCK_SImm16_Relaxed: return true;
2957
0
    case MCK_UImm16_Relaxed: return true;
2958
0
    case MCK_ConstantUImm20_0: return true;
2959
0
    case MCK_ConstantUImm26_0: return true;
2960
0
    case MCK_SImm32: return true;
2961
0
    case MCK_SImm32_Relaxed: return true;
2962
0
    case MCK_UImm32_Coerced: return true;
2963
0
    }
2964
0
2965
0
  case MCK_ConstantUImm5_32:
2966
0
    switch (B) {
2967
0
    default: return false;
2968
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2969
0
    case MCK_ConstantUImm5_33: return true;
2970
0
    case MCK_ConstantUImmRange2_64: return true;
2971
0
    case MCK_UImm5Lsl2: return true;
2972
0
    case MCK_ConstantSImm6_0: return true;
2973
0
    case MCK_ConstantUImm6_0: return true;
2974
0
    case MCK_UImm6Lsl2: return true;
2975
0
    case MCK_ConstantUImm7_0: return true;
2976
0
    case MCK_UImm7_N1: return true;
2977
0
    case MCK_ConstantUImm8_0: return true;
2978
0
    case MCK_SImm7Lsl2: return true;
2979
0
    case MCK_ConstantSImm9_0: return true;
2980
0
    case MCK_ConstantSImm10_0: return true;
2981
0
    case MCK_ConstantUImm10_0: return true;
2982
0
    case MCK_SImm10Lsl1: return true;
2983
0
    case MCK_ConstantSImm11_0: return true;
2984
0
    case MCK_SImm10Lsl2: return true;
2985
0
    case MCK_SImm10Lsl3: return true;
2986
0
    case MCK_SImm16: return true;
2987
0
    case MCK_SImm16_Relaxed: return true;
2988
0
    case MCK_UImm16_Relaxed: return true;
2989
0
    case MCK_ConstantUImm20_0: return true;
2990
0
    case MCK_ConstantUImm26_0: return true;
2991
0
    case MCK_SImm32: return true;
2992
0
    case MCK_SImm32_Relaxed: return true;
2993
0
    case MCK_UImm32_Coerced: return true;
2994
0
    }
2995
0
2996
0
  case MCK_ConstantUImm5_0_Report_UImm6:
2997
0
    switch (B) {
2998
0
    default: return false;
2999
0
    case MCK_ConstantUImm5_33: return true;
3000
0
    case MCK_ConstantUImmRange2_64: return true;
3001
0
    case MCK_UImm5Lsl2: return true;
3002
0
    case MCK_ConstantSImm6_0: return true;
3003
0
    case MCK_ConstantUImm6_0: return true;
3004
0
    case MCK_UImm6Lsl2: return true;
3005
0
    case MCK_ConstantUImm7_0: return true;
3006
0
    case MCK_UImm7_N1: return true;
3007
0
    case MCK_ConstantUImm8_0: return true;
3008
0
    case MCK_SImm7Lsl2: return true;
3009
0
    case MCK_ConstantSImm9_0: return true;
3010
0
    case MCK_ConstantSImm10_0: return true;
3011
0
    case MCK_ConstantUImm10_0: return true;
3012
0
    case MCK_SImm10Lsl1: return true;
3013
0
    case MCK_ConstantSImm11_0: return true;
3014
0
    case MCK_SImm10Lsl2: return true;
3015
0
    case MCK_SImm10Lsl3: return true;
3016
0
    case MCK_SImm16: return true;
3017
0
    case MCK_SImm16_Relaxed: return true;
3018
0
    case MCK_UImm16_Relaxed: return true;
3019
0
    case MCK_ConstantUImm20_0: return true;
3020
0
    case MCK_ConstantUImm26_0: return true;
3021
0
    case MCK_SImm32: return true;
3022
0
    case MCK_SImm32_Relaxed: return true;
3023
0
    case MCK_UImm32_Coerced: return true;
3024
0
    }
3025
0
3026
0
  case MCK_ConstantUImm5_33:
3027
0
    switch (B) {
3028
0
    default: return false;
3029
0
    case MCK_ConstantUImmRange2_64: return true;
3030
0
    case MCK_UImm5Lsl2: return true;
3031
0
    case MCK_ConstantSImm6_0: return true;
3032
0
    case MCK_ConstantUImm6_0: return true;
3033
0
    case MCK_UImm6Lsl2: return true;
3034
0
    case MCK_ConstantUImm7_0: return true;
3035
0
    case MCK_UImm7_N1: return true;
3036
0
    case MCK_ConstantUImm8_0: return true;
3037
0
    case MCK_SImm7Lsl2: return true;
3038
0
    case MCK_ConstantSImm9_0: return true;
3039
0
    case MCK_ConstantSImm10_0: return true;
3040
0
    case MCK_ConstantUImm10_0: return true;
3041
0
    case MCK_SImm10Lsl1: return true;
3042
0
    case MCK_ConstantSImm11_0: return true;
3043
0
    case MCK_SImm10Lsl2: return true;
3044
0
    case MCK_SImm10Lsl3: return true;
3045
0
    case MCK_SImm16: return true;
3046
0
    case MCK_SImm16_Relaxed: return true;
3047
0
    case MCK_UImm16_Relaxed: return true;
3048
0
    case MCK_ConstantUImm20_0: return true;
3049
0
    case MCK_ConstantUImm26_0: return true;
3050
0
    case MCK_SImm32: return true;
3051
0
    case MCK_SImm32_Relaxed: return true;
3052
0
    case MCK_UImm32_Coerced: return true;
3053
0
    }
3054
0
3055
0
  case MCK_ConstantUImmRange2_64:
3056
0
    switch (B) {
3057
0
    default: return false;
3058
0
    case MCK_UImm5Lsl2: return true;
3059
0
    case MCK_ConstantSImm6_0: return true;
3060
0
    case MCK_ConstantUImm6_0: return true;
3061
0
    case MCK_UImm6Lsl2: return true;
3062
0
    case MCK_ConstantUImm7_0: return true;
3063
0
    case MCK_UImm7_N1: return true;
3064
0
    case MCK_ConstantUImm8_0: return true;
3065
0
    case MCK_SImm7Lsl2: return true;
3066
0
    case MCK_ConstantSImm9_0: return true;
3067
0
    case MCK_ConstantSImm10_0: return true;
3068
0
    case MCK_ConstantUImm10_0: return true;
3069
0
    case MCK_SImm10Lsl1: return true;
3070
0
    case MCK_ConstantSImm11_0: return true;
3071
0
    case MCK_SImm10Lsl2: return true;
3072
0
    case MCK_SImm10Lsl3: return true;
3073
0
    case MCK_SImm16: return true;
3074
0
    case MCK_SImm16_Relaxed: return true;
3075
0
    case MCK_UImm16_Relaxed: return true;
3076
0
    case MCK_ConstantUImm20_0: return true;
3077
0
    case MCK_ConstantUImm26_0: return true;
3078
0
    case MCK_SImm32: return true;
3079
0
    case MCK_SImm32_Relaxed: return true;
3080
0
    case MCK_UImm32_Coerced: return true;
3081
0
    }
3082
0
3083
0
  case MCK_UImm5Lsl2:
3084
0
    switch (B) {
3085
0
    default: return false;
3086
0
    case MCK_ConstantSImm6_0: return true;
3087
0
    case MCK_ConstantUImm6_0: return true;
3088
0
    case MCK_UImm6Lsl2: return true;
3089
0
    case MCK_ConstantUImm7_0: return true;
3090
0
    case MCK_UImm7_N1: return true;
3091
0
    case MCK_ConstantUImm8_0: return true;
3092
0
    case MCK_SImm7Lsl2: return true;
3093
0
    case MCK_ConstantSImm9_0: return true;
3094
0
    case MCK_ConstantSImm10_0: return true;
3095
0
    case MCK_ConstantUImm10_0: return true;
3096
0
    case MCK_SImm10Lsl1: return true;
3097
0
    case MCK_ConstantSImm11_0: return true;
3098
0
    case MCK_SImm10Lsl2: return true;
3099
0
    case MCK_SImm10Lsl3: return true;
3100
0
    case MCK_SImm16: return true;
3101
0
    case MCK_SImm16_Relaxed: return true;
3102
0
    case MCK_UImm16_Relaxed: return true;
3103
0
    case MCK_ConstantUImm20_0: return true;
3104
0
    case MCK_ConstantUImm26_0: return true;
3105
0
    case MCK_SImm32: return true;
3106
0
    case MCK_SImm32_Relaxed: return true;
3107
0
    case MCK_UImm32_Coerced: return true;
3108
0
    }
3109
0
3110
0
  case MCK_ConstantSImm6_0:
3111
0
    switch (B) {
3112
0
    default: return false;
3113
0
    case MCK_ConstantUImm6_0: return true;
3114
0
    case MCK_UImm6Lsl2: return true;
3115
0
    case MCK_ConstantUImm7_0: return true;
3116
0
    case MCK_UImm7_N1: return true;
3117
0
    case MCK_ConstantUImm8_0: return true;
3118
0
    case MCK_SImm7Lsl2: return true;
3119
0
    case MCK_ConstantSImm9_0: return true;
3120
0
    case MCK_ConstantSImm10_0: return true;
3121
0
    case MCK_ConstantUImm10_0: return true;
3122
0
    case MCK_SImm10Lsl1: return true;
3123
0
    case MCK_ConstantSImm11_0: return true;
3124
0
    case MCK_SImm10Lsl2: return true;
3125
0
    case MCK_SImm10Lsl3: return true;
3126
0
    case MCK_SImm16: return true;
3127
0
    case MCK_SImm16_Relaxed: return true;
3128
0
    case MCK_UImm16_Relaxed: return true;
3129
0
    case MCK_ConstantUImm20_0: return true;
3130
0
    case MCK_ConstantUImm26_0: return true;
3131
0
    case MCK_SImm32: return true;
3132
0
    case MCK_SImm32_Relaxed: return true;
3133
0
    case MCK_UImm32_Coerced: return true;
3134
0
    }
3135
0
3136
0
  case MCK_ConstantUImm6_0:
3137
0
    switch (B) {
3138
0
    default: return false;
3139
0
    case MCK_UImm6Lsl2: return true;
3140
0
    case MCK_ConstantUImm7_0: return true;
3141
0
    case MCK_UImm7_N1: return true;
3142
0
    case MCK_ConstantUImm8_0: return true;
3143
0
    case MCK_SImm7Lsl2: return true;
3144
0
    case MCK_ConstantSImm9_0: return true;
3145
0
    case MCK_ConstantSImm10_0: return true;
3146
0
    case MCK_ConstantUImm10_0: return true;
3147
0
    case MCK_SImm10Lsl1: return true;
3148
0
    case MCK_ConstantSImm11_0: return true;
3149
0
    case MCK_SImm10Lsl2: return true;
3150
0
    case MCK_SImm10Lsl3: return true;
3151
0
    case MCK_SImm16: return true;
3152
0
    case MCK_SImm16_Relaxed: return true;
3153
0
    case MCK_UImm16_Relaxed: return true;
3154
0
    case MCK_ConstantUImm20_0: return true;
3155
0
    case MCK_ConstantUImm26_0: return true;
3156
0
    case MCK_SImm32: return true;
3157
0
    case MCK_SImm32_Relaxed: return true;
3158
0
    case MCK_UImm32_Coerced: return true;
3159
0
    }
3160
0
3161
0
  case MCK_UImm6Lsl2:
3162
0
    switch (B) {
3163
0
    default: return false;
3164
0
    case MCK_ConstantUImm7_0: return true;
3165
0
    case MCK_UImm7_N1: return true;
3166
0
    case MCK_ConstantUImm8_0: return true;
3167
0
    case MCK_SImm7Lsl2: return true;
3168
0
    case MCK_ConstantSImm9_0: return true;
3169
0
    case MCK_ConstantSImm10_0: return true;
3170
0
    case MCK_ConstantUImm10_0: return true;
3171
0
    case MCK_SImm10Lsl1: return true;
3172
0
    case MCK_ConstantSImm11_0: return true;
3173
0
    case MCK_SImm10Lsl2: return true;
3174
0
    case MCK_SImm10Lsl3: return true;
3175
0
    case MCK_SImm16: return true;
3176
0
    case MCK_SImm16_Relaxed: return true;
3177
0
    case MCK_UImm16_Relaxed: return true;
3178
0
    case MCK_ConstantUImm20_0: return true;
3179
0
    case MCK_ConstantUImm26_0: return true;
3180
0
    case MCK_SImm32: return true;
3181
0
    case MCK_SImm32_Relaxed: return true;
3182
0
    case MCK_UImm32_Coerced: return true;
3183
0
    }
3184
0
3185
0
  case MCK_ConstantUImm7_0:
3186
0
    switch (B) {
3187
0
    default: return false;
3188
0
    case MCK_UImm7_N1: return true;
3189
0
    case MCK_ConstantUImm8_0: return true;
3190
0
    case MCK_SImm7Lsl2: return true;
3191
0
    case MCK_ConstantSImm9_0: return true;
3192
0
    case MCK_ConstantSImm10_0: return true;
3193
0
    case MCK_ConstantUImm10_0: return true;
3194
0
    case MCK_SImm10Lsl1: return true;
3195
0
    case MCK_ConstantSImm11_0: return true;
3196
0
    case MCK_SImm10Lsl2: return true;
3197
0
    case MCK_SImm10Lsl3: return true;
3198
0
    case MCK_SImm16: return true;
3199
0
    case MCK_SImm16_Relaxed: return true;
3200
0
    case MCK_UImm16_Relaxed: return true;
3201
0
    case MCK_ConstantUImm20_0: return true;
3202
0
    case MCK_ConstantUImm26_0: return true;
3203
0
    case MCK_SImm32: return true;
3204
0
    case MCK_SImm32_Relaxed: return true;
3205
0
    case MCK_UImm32_Coerced: return true;
3206
0
    }
3207
0
3208
0
  case MCK_UImm7_N1:
3209
0
    switch (B) {
3210
0
    default: return false;
3211
0
    case MCK_ConstantUImm8_0: return true;
3212
0
    case MCK_SImm7Lsl2: return true;
3213
0
    case MCK_ConstantSImm9_0: return true;
3214
0
    case MCK_ConstantSImm10_0: return true;
3215
0
    case MCK_ConstantUImm10_0: return true;
3216
0
    case MCK_SImm10Lsl1: return true;
3217
0
    case MCK_ConstantSImm11_0: return true;
3218
0
    case MCK_SImm10Lsl2: return true;
3219
0
    case MCK_SImm10Lsl3: return true;
3220
0
    case MCK_SImm16: return true;
3221
0
    case MCK_SImm16_Relaxed: return true;
3222
0
    case MCK_UImm16_Relaxed: return true;
3223
0
    case MCK_ConstantUImm20_0: return true;
3224
0
    case MCK_ConstantUImm26_0: return true;
3225
0
    case MCK_SImm32: return true;
3226
0
    case MCK_SImm32_Relaxed: return true;
3227
0
    case MCK_UImm32_Coerced: return true;
3228
0
    }
3229
0
3230
0
  case MCK_ConstantUImm8_0:
3231
0
    switch (B) {
3232
0
    default: return false;
3233
0
    case MCK_SImm7Lsl2: return true;
3234
0
    case MCK_ConstantSImm9_0: return true;
3235
0
    case MCK_ConstantSImm10_0: return true;
3236
0
    case MCK_ConstantUImm10_0: return true;
3237
0
    case MCK_SImm10Lsl1: return true;
3238
0
    case MCK_ConstantSImm11_0: return true;
3239
0
    case MCK_SImm10Lsl2: return true;
3240
0
    case MCK_SImm10Lsl3: return true;
3241
0
    case MCK_SImm16: return true;
3242
0
    case MCK_SImm16_Relaxed: return true;
3243
0
    case MCK_UImm16_Relaxed: return true;
3244
0
    case MCK_ConstantUImm20_0: return true;
3245
0
    case MCK_ConstantUImm26_0: return true;
3246
0
    case MCK_SImm32: return true;
3247
0
    case MCK_SImm32_Relaxed: return true;
3248
0
    case MCK_UImm32_Coerced: return true;
3249
0
    }
3250
0
3251
0
  case MCK_SImm7Lsl2:
3252
0
    switch (B) {
3253
0
    default: return false;
3254
0
    case MCK_ConstantSImm9_0: return true;
3255
0
    case MCK_ConstantSImm10_0: return true;
3256
0
    case MCK_ConstantUImm10_0: return true;
3257
0
    case MCK_SImm10Lsl1: return true;
3258
0
    case MCK_ConstantSImm11_0: return true;
3259
0
    case MCK_SImm10Lsl2: return true;
3260
0
    case MCK_SImm10Lsl3: return true;
3261
0
    case MCK_SImm16: return true;
3262
0
    case MCK_SImm16_Relaxed: return true;
3263
0
    case MCK_UImm16_Relaxed: return true;
3264
0
    case MCK_ConstantUImm20_0: return true;
3265
0
    case MCK_ConstantUImm26_0: return true;
3266
0
    case MCK_SImm32: return true;
3267
0
    case MCK_SImm32_Relaxed: return true;
3268
0
    case MCK_UImm32_Coerced: return true;
3269
0
    }
3270
0
3271
0
  case MCK_ConstantSImm9_0:
3272
0
    switch (B) {
3273
0
    default: return false;
3274
0
    case MCK_ConstantSImm10_0: return true;
3275
0
    case MCK_ConstantUImm10_0: return true;
3276
0
    case MCK_SImm10Lsl1: return true;
3277
0
    case MCK_ConstantSImm11_0: return true;
3278
0
    case MCK_SImm10Lsl2: return true;
3279
0
    case MCK_SImm10Lsl3: return true;
3280
0
    case MCK_SImm16: return true;
3281
0
    case MCK_SImm16_Relaxed: return true;
3282
0
    case MCK_UImm16_Relaxed: return true;
3283
0
    case MCK_ConstantUImm20_0: return true;
3284
0
    case MCK_ConstantUImm26_0: return true;
3285
0
    case MCK_SImm32: return true;
3286
0
    case MCK_SImm32_Relaxed: return true;
3287
0
    case MCK_UImm32_Coerced: return true;
3288
0
    }
3289
0
3290
0
  case MCK_ConstantSImm10_0:
3291
0
    switch (B) {
3292
0
    default: return false;
3293
0
    case MCK_ConstantUImm10_0: return true;
3294
0
    case MCK_SImm10Lsl1: return true;
3295
0
    case MCK_ConstantSImm11_0: return true;
3296
0
    case MCK_SImm10Lsl2: return true;
3297
0
    case MCK_SImm10Lsl3: return true;
3298
0
    case MCK_SImm16: return true;
3299
0
    case MCK_SImm16_Relaxed: return true;
3300
0
    case MCK_UImm16_Relaxed: return true;
3301
0
    case MCK_ConstantUImm20_0: return true;
3302
0
    case MCK_ConstantUImm26_0: return true;
3303
0
    case MCK_SImm32: return true;
3304
0
    case MCK_SImm32_Relaxed: return true;
3305
0
    case MCK_UImm32_Coerced: return true;
3306
0
    }
3307
0
3308
10
  case MCK_ConstantUImm10_0:
3309
10
    switch (B) {
3310
10
    default: return false;
3311
10
    
case MCK_SImm10Lsl1: return true0
;
3312
10
    
case MCK_ConstantSImm11_0: return true0
;
3313
10
    
case MCK_SImm10Lsl2: return true0
;
3314
10
    
case MCK_SImm10Lsl3: return true0
;
3315
10
    
case MCK_SImm16: return true0
;
3316
10
    
case MCK_SImm16_Relaxed: return true0
;
3317
10
    
case MCK_UImm16_Relaxed: return true0
;
3318
10
    
case MCK_ConstantUImm20_0: return true0
;
3319
10
    
case MCK_ConstantUImm26_0: return true0
;
3320
10
    
case MCK_SImm32: return true0
;
3321
10
    
case MCK_SImm32_Relaxed: return true0
;
3322
10
    
case MCK_UImm32_Coerced: return true0
;
3323
0
    }
3324
0
3325
0
  case MCK_SImm10Lsl1:
3326
0
    switch (B) {
3327
0
    default: return false;
3328
0
    case MCK_ConstantSImm11_0: return true;
3329
0
    case MCK_SImm10Lsl2: return true;
3330
0
    case MCK_SImm10Lsl3: return true;
3331
0
    case MCK_SImm16: return true;
3332
0
    case MCK_SImm16_Relaxed: return true;
3333
0
    case MCK_UImm16_Relaxed: return true;
3334
0
    case MCK_ConstantUImm20_0: return true;
3335
0
    case MCK_ConstantUImm26_0: return true;
3336
0
    case MCK_SImm32: return true;
3337
0
    case MCK_SImm32_Relaxed: return true;
3338
0
    case MCK_UImm32_Coerced: return true;
3339
0
    }
3340
0
3341
0
  case MCK_ConstantSImm11_0:
3342
0
    switch (B) {
3343
0
    default: return false;
3344
0
    case MCK_SImm10Lsl2: return true;
3345
0
    case MCK_SImm10Lsl3: return true;
3346
0
    case MCK_SImm16: return true;
3347
0
    case MCK_SImm16_Relaxed: return true;
3348
0
    case MCK_UImm16_Relaxed: return true;
3349
0
    case MCK_ConstantUImm20_0: return true;
3350
0
    case MCK_ConstantUImm26_0: return true;
3351
0
    case MCK_SImm32: return true;
3352
0
    case MCK_SImm32_Relaxed: return true;
3353
0
    case MCK_UImm32_Coerced: return true;
3354
0
    }
3355
0
3356
0
  case MCK_SImm10Lsl2:
3357
0
    switch (B) {
3358
0
    default: return false;
3359
0
    case MCK_SImm10Lsl3: return true;
3360
0
    case MCK_SImm16: return true;
3361
0
    case MCK_SImm16_Relaxed: return true;
3362
0
    case MCK_UImm16_Relaxed: return true;
3363
0
    case MCK_ConstantUImm20_0: return true;
3364
0
    case MCK_ConstantUImm26_0: return true;
3365
0
    case MCK_SImm32: return true;
3366
0
    case MCK_SImm32_Relaxed: return true;
3367
0
    case MCK_UImm32_Coerced: return true;
3368
0
    }
3369
0
3370
0
  case MCK_SImm10Lsl3:
3371
0
    switch (B) {
3372
0
    default: return false;
3373
0
    case MCK_SImm16: return true;
3374
0
    case MCK_SImm16_Relaxed: return true;
3375
0
    case MCK_UImm16_Relaxed: return true;
3376
0
    case MCK_ConstantUImm20_0: return true;
3377
0
    case MCK_ConstantUImm26_0: return true;
3378
0
    case MCK_SImm32: return true;
3379
0
    case MCK_SImm32_Relaxed: return true;
3380
0
    case MCK_UImm32_Coerced: return true;
3381
0
    }
3382
0
3383
10
  case MCK_SImm16:
3384
10
    switch (B) {
3385
10
    default: return false;
3386
10
    
case MCK_SImm16_Relaxed: return true0
;
3387
10
    
case MCK_UImm16_Relaxed: return true0
;
3388
10
    
case MCK_ConstantUImm20_0: return true0
;
3389
10
    
case MCK_ConstantUImm26_0: return true0
;
3390
10
    
case MCK_SImm32: return true0
;
3391
10
    
case MCK_SImm32_Relaxed: return true0
;
3392
10
    
case MCK_UImm32_Coerced: return true0
;
3393
0
    }
3394
0
3395
0
  case MCK_SImm16_Relaxed:
3396
0
    switch (B) {
3397
0
    default: return false;
3398
0
    case MCK_UImm16_Relaxed: return true;
3399
0
    case MCK_ConstantUImm20_0: return true;
3400
0
    case MCK_ConstantUImm26_0: return true;
3401
0
    case MCK_SImm32: return true;
3402
0
    case MCK_SImm32_Relaxed: return true;
3403
0
    case MCK_UImm32_Coerced: return true;
3404
0
    }
3405
0
3406
0
  case MCK_UImm16_AltRelaxed:
3407
0
    switch (B) {
3408
0
    default: return false;
3409
0
    case MCK_UImm16_Relaxed: return true;
3410
0
    case MCK_ConstantUImm20_0: return true;
3411
0
    case MCK_ConstantUImm26_0: return true;
3412
0
    case MCK_SImm32: return true;
3413
0
    case MCK_SImm32_Relaxed: return true;
3414
0
    case MCK_UImm32_Coerced: return true;
3415
0
    }
3416
0
3417
0
  case MCK_UImm16:
3418
0
    switch (B) {
3419
0
    default: return false;
3420
0
    case MCK_UImm16_Relaxed: return true;
3421
0
    case MCK_ConstantUImm20_0: return true;
3422
0
    case MCK_ConstantUImm26_0: return true;
3423
0
    case MCK_SImm32: return true;
3424
0
    case MCK_SImm32_Relaxed: return true;
3425
0
    case MCK_UImm32_Coerced: return true;
3426
0
    }
3427
0
3428
0
  case MCK_SImm19Lsl2:
3429
0
    switch (B) {
3430
0
    default: return false;
3431
0
    case MCK_ConstantUImm20_0: return true;
3432
0
    case MCK_ConstantUImm26_0: return true;
3433
0
    case MCK_SImm32: return true;
3434
0
    case MCK_SImm32_Relaxed: return true;
3435
0
    case MCK_UImm32_Coerced: return true;
3436
0
    }
3437
0
3438
0
  case MCK_UImm16_Relaxed:
3439
0
    switch (B) {
3440
0
    default: return false;
3441
0
    case MCK_ConstantUImm20_0: return true;
3442
0
    case MCK_ConstantUImm26_0: return true;
3443
0
    case MCK_SImm32: return true;
3444
0
    case MCK_SImm32_Relaxed: return true;
3445
0
    case MCK_UImm32_Coerced: return true;
3446
0
    }
3447
0
3448
0
  case MCK_ConstantUImm20_0:
3449
0
    switch (B) {
3450
0
    default: return false;
3451
0
    case MCK_ConstantUImm26_0: return true;
3452
0
    case MCK_SImm32: return true;
3453
0
    case MCK_SImm32_Relaxed: return true;
3454
0
    case MCK_UImm32_Coerced: return true;
3455
0
    }
3456
0
3457
0
  case MCK_ConstantUImm26_0:
3458
0
    switch (B) {
3459
0
    default: return false;
3460
0
    case MCK_SImm32: return true;
3461
0
    case MCK_SImm32_Relaxed: return true;
3462
0
    case MCK_UImm32_Coerced: return true;
3463
0
    }
3464
0
3465
0
  case MCK_SImm32:
3466
0
    switch (B) {
3467
0
    default: return false;
3468
0
    case MCK_SImm32_Relaxed: return true;
3469
0
    case MCK_UImm32_Coerced: return true;
3470
0
    }
3471
0
3472
0
  case MCK_SImm32_Relaxed:
3473
0
    return B == MCK_UImm32_Coerced;
3474
38.6k
  }
3475
38.6k
}
3476
3477
162k
static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
3478
162k
  MipsOperand &Operand = (MipsOperand&)GOp;
3479
162k
  if (Kind == InvalidMatchClass)
3480
5.06k
    return MCTargetAsmParser::Match_InvalidOperand;
3481
157k
3482
157k
  if (Operand.isToken() && 
Kind <= MCK_LAST_TOKEN880
)
3483
880
    return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
3484
880
             MCTargetAsmParser::Match_Success :
3485
880
             
MCTargetAsmParser::Match_InvalidOperand0
;
3486
156k
3487
156k
  switch (Kind) {
3488
156k
  
default: break14.5k
;
3489
156k
  // 'ACC64DSPAsmReg' class
3490
156k
  case MCK_ACC64DSPAsmReg: {
3491
571
    DiagnosticPredicate DP(Operand.isACCAsmReg());
3492
571
    if (DP.isMatch())
3493
420
      return MCTargetAsmParser::Match_Success;
3494
151
    break;
3495
151
    }
3496
151
  // 'AFGR64AsmReg' class
3497
4.71k
  case MCK_AFGR64AsmReg: {
3498
4.71k
    DiagnosticPredicate DP(Operand.isFGRAsmReg());
3499
4.71k
    if (DP.isMatch())
3500
4.21k
      return MCTargetAsmParser::Match_Success;
3501
498
    break;
3502
498
    }
3503
498
  // 'CCRAsmReg' class
3504
498
  case MCK_CCRAsmReg: {
3505
46
    DiagnosticPredicate DP(Operand.isCCRAsmReg());
3506
46
    if (DP.isMatch())
3507
46
      return MCTargetAsmParser::Match_Success;
3508
0
    break;
3509
0
    }
3510
0
  // 'COP0AsmReg' class
3511
680
  case MCK_COP0AsmReg: {
3512
680
    DiagnosticPredicate DP(Operand.isCOP0AsmReg());
3513
680
    if (DP.isMatch())
3514
548
      return MCTargetAsmParser::Match_Success;
3515
132
    break;
3516
132
    }
3517
132
  // 'COP2AsmReg' class
3518
566
  case MCK_COP2AsmReg: {
3519
566
    DiagnosticPredicate DP(Operand.isCOP2AsmReg());
3520
566
    if (DP.isMatch())
3521
564
      return MCTargetAsmParser::Match_Success;
3522
2
    break;
3523
2
    }
3524
2
  // 'COP3AsmReg' class
3525
16
  case MCK_COP3AsmReg: {
3526
16
    DiagnosticPredicate DP(Operand.isCOP3AsmReg());
3527
16
    if (DP.isMatch())
3528
16
      return MCTargetAsmParser::Match_Success;
3529
0
    break;
3530
0
    }
3531
0
  // 'FCCAsmReg' class
3532
2.07k
  case MCK_FCCAsmReg: {
3533
2.07k
    DiagnosticPredicate DP(Operand.isFCCAsmReg());
3534
2.07k
    if (DP.isMatch())
3535
1.65k
      return MCTargetAsmParser::Match_Success;
3536
418
    break;
3537
418
    }
3538
418
  // 'FGR32AsmReg' class
3539
6.77k
  case MCK_FGR32AsmReg: {
3540
6.77k
    DiagnosticPredicate DP(Operand.isFGRAsmReg());
3541
6.77k
    if (DP.isMatch())
3542
6.23k
      return MCTargetAsmParser::Match_Success;
3543
545
    break;
3544
545
    }
3545
545
  // 'FGR64AsmReg' class
3546
4.32k
  case MCK_FGR64AsmReg: {
3547
4.32k
    DiagnosticPredicate DP(Operand.isFGRAsmReg());
3548
4.32k
    if (DP.isMatch())
3549
3.82k
      return MCTargetAsmParser::Match_Success;
3550
500
    break;
3551
500
    }
3552
500
  // 'FGRH32AsmReg' class
3553
500
  case MCK_FGRH32AsmReg: {
3554
0
    DiagnosticPredicate DP(Operand.isFGRAsmReg());
3555
0
    if (DP.isMatch())
3556
0
      return MCTargetAsmParser::Match_Success;
3557
0
    break;
3558
0
    }
3559
0
  // 'GPR32AsmReg' class
3560
66.0k
  case MCK_GPR32AsmReg: {
3561
66.0k
    DiagnosticPredicate DP(Operand.isGPRAsmReg());
3562
66.0k
    if (DP.isMatch())
3563
62.3k
      return MCTargetAsmParser::Match_Success;
3564
3.71k
    break;
3565
3.71k
    }
3566
3.71k
  // 'GPR32NonZeroAsmReg' class
3567
3.71k
  case MCK_GPR32NonZeroAsmReg: {
3568
130
    DiagnosticPredicate DP(Operand.isGPRNonZeroAsmReg());
3569
130
    if (DP.isMatch())
3570
76
      return MCTargetAsmParser::Match_Success;
3571
54
    break;
3572
54
    }
3573
54
  // 'GPR32ZeroAsmReg' class
3574
100
  case MCK_GPR32ZeroAsmReg: {
3575
100
    DiagnosticPredicate DP(Operand.isGPRZeroAsmReg());
3576
100
    if (DP.isMatch())
3577
54
      return MCTargetAsmParser::Match_Success;
3578
46
    break;
3579
46
    }
3580
46
  // 'GPR64AsmReg' class
3581
8.34k
  case MCK_GPR64AsmReg: {
3582
8.34k
    DiagnosticPredicate DP(Operand.isGPRAsmReg());
3583
8.34k
    if (DP.isMatch())
3584
7.88k
      return MCTargetAsmParser::Match_Success;
3585
461
    break;
3586
461
    }
3587
461
  // 'GPRMM16AsmReg' class
3588
461
  case MCK_GPRMM16AsmReg: {
3589
269
    DiagnosticPredicate DP(Operand.isMM16AsmReg());
3590
269
    if (DP.isMatch())
3591
234
      return MCTargetAsmParser::Match_Success;
3592
35
    break;
3593
35
    }
3594
35
  // 'GPRMM16AsmRegMoveP' class
3595
35
  case MCK_GPRMM16AsmRegMoveP: {
3596
28
    DiagnosticPredicate DP(Operand.isMM16AsmRegMoveP());
3597
28
    if (DP.isMatch())
3598
20
      return MCTargetAsmParser::Match_Success;
3599
8
    break;
3600
8
    }
3601
8
  // 'GPRMM16AsmRegMovePPairFirst' class
3602
20
  case MCK_GPRMM16AsmRegMovePPairFirst: {
3603
20
    DiagnosticPredicate DP(Operand.isMM16AsmRegMovePPairFirst());
3604
20
    if (DP.isMatch())
3605
16
      return MCTargetAsmParser::Match_Success;
3606
4
    break;
3607
4
    }
3608
4
  // 'GPRMM16AsmRegMovePPairSecond' class
3609
16
  case MCK_GPRMM16AsmRegMovePPairSecond: {
3610
16
    DiagnosticPredicate DP(Operand.isMM16AsmRegMovePPairSecond());
3611
16
    if (DP.isMatch())
3612
16
      return MCTargetAsmParser::Match_Success;
3613
0
    break;
3614
0
    }
3615
0
  // 'GPRMM16AsmRegZero' class
3616
65
  case MCK_GPRMM16AsmRegZero: {
3617
65
    DiagnosticPredicate DP(Operand.isMM16AsmRegZero());
3618
65
    if (DP.isMatch())
3619
41
      return MCTargetAsmParser::Match_Success;
3620
24
    break;
3621
24
    }
3622
24
  // 'HI32DSPAsmReg' class
3623
24
  case MCK_HI32DSPAsmReg: {
3624
9
    DiagnosticPredicate DP(Operand.isACCAsmReg());
3625
9
    if (DP.isMatch())
3626
9
      return MCTargetAsmParser::Match_Success;
3627
0
    break;
3628
0
    }
3629
0
  // 'HWRegsAsmReg' class
3630
85
  case MCK_HWRegsAsmReg: {
3631
85
    DiagnosticPredicate DP(Operand.isHWRegsAsmReg());
3632
85
    if (DP.isMatch())
3633
85
      return MCTargetAsmParser::Match_Success;
3634
0
    break;
3635
0
    }
3636
0
  // 'Imm' class
3637
2.97k
  case MCK_Imm: {
3638
2.97k
    DiagnosticPredicate DP(Operand.isImm());
3639
2.97k
    if (DP.isMatch())
3640
1.95k
      return MCTargetAsmParser::Match_Success;
3641
1.02k
    break;
3642
1.02k
    }
3643
1.02k
  // 'LO32DSPAsmReg' class
3644
1.02k
  case MCK_LO32DSPAsmReg: {
3645
9
    DiagnosticPredicate DP(Operand.isACCAsmReg());
3646
9
    if (DP.isMatch())
3647
9
      return MCTargetAsmParser::Match_Success;
3648
0
    break;
3649
0
    }
3650
0
  // 'MSA128AsmReg' class
3651
2.13k
  case MCK_MSA128AsmReg: {
3652
2.13k
    DiagnosticPredicate DP(Operand.isMSA128AsmReg());
3653
2.13k
    if (DP.isMatch())
3654
2.13k
      return MCTargetAsmParser::Match_Success;
3655
0
    break;
3656
0
    }
3657
0
  // 'MSACtrlAsmReg' class
3658
38
  case MCK_MSACtrlAsmReg: {
3659
38
    DiagnosticPredicate DP(Operand.isMSACtrlAsmReg());
3660
38
    if (DP.isMatch())
3661
32
      return MCTargetAsmParser::Match_Success;
3662
6
    break;
3663
6
    }
3664
6
  // 'MicroMipsMemGP' class
3665
6
  case MCK_MicroMipsMemGP: {
3666
0
    DiagnosticPredicate DP(Operand.isMemWithSimmWordAlignedOffsetGP<9>());
3667
0
    if (DP.isMatch())
3668
0
      return MCTargetAsmParser::Match_Success;
3669
0
    break;
3670
0
    }
3671
0
  // 'MicroMipsMem' class
3672
75
  case MCK_MicroMipsMem: {
3673
75
    DiagnosticPredicate DP(Operand.isMemWithGRPMM16Base());
3674
75
    if (DP.isMatch())
3675
57
      return MCTargetAsmParser::Match_Success;
3676
18
    break;
3677
18
    }
3678
18
  // 'MicroMipsMemSP' class
3679
10.4k
  case MCK_MicroMipsMemSP: {
3680
10.4k
    DiagnosticPredicate DP(Operand.isMemWithUimmWordAlignedOffsetSP<7>());
3681
10.4k
    if (DP.isMatch())
3682
57
      return MCTargetAsmParser::Match_Success;
3683
10.4k
    break;
3684
10.4k
    }
3685
10.4k
  // 'InvNum' class
3686
10.4k
  case MCK_InvNum: {
3687
245
    DiagnosticPredicate DP(Operand.isInvNum());
3688
245
    if (DP.isMatch())
3689
106
      return MCTargetAsmParser::Match_Success;
3690
139
    break;
3691
139
    }
3692
139
  // 'JumpTarget' class
3693
2.58k
  case MCK_JumpTarget: {
3694
2.58k
    DiagnosticPredicate DP(Operand.isImm());
3695
2.58k
    if (DP.isMatch())
3696
2.26k
      return MCTargetAsmParser::Match_Success;
3697
322
    break;
3698
322
    }
3699
322
  // 'MemOffsetSimm10' class
3700
322
  case MCK_MemOffsetSimm10: {
3701
7
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10>());
3702
7
    if (DP.isMatch())
3703
3
      return MCTargetAsmParser::Match_Success;
3704
4
    if (DP.isNearMatch())
3705
4
      return MipsAsmParser::Match_MemSImm10;
3706
0
    break;
3707
0
    }
3708
0
  // 'MemOffsetSimm10_1' class
3709
9
  case MCK_MemOffsetSimm10_1: {
3710
9
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 1>());
3711
9
    if (DP.isMatch())
3712
5
      return MCTargetAsmParser::Match_Success;
3713
4
    if (DP.isNearMatch())
3714
4
      return MipsAsmParser::Match_MemSImm10Lsl1;
3715
0
    break;
3716
0
    }
3717
0
  // 'MemOffsetSimm10_2' class
3718
10
  case MCK_MemOffsetSimm10_2: {
3719
10
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 2>());
3720
10
    if (DP.isMatch())
3721
6
      return MCTargetAsmParser::Match_Success;
3722
4
    if (DP.isNearMatch())
3723
4
      return MipsAsmParser::Match_MemSImm10Lsl2;
3724
0
    break;
3725
0
    }
3726
0
  // 'MemOffsetSimm10_3' class
3727
13
  case MCK_MemOffsetSimm10_3: {
3728
13
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 3>());
3729
13
    if (DP.isMatch())
3730
9
      return MCTargetAsmParser::Match_Success;
3731
4
    if (DP.isNearMatch())
3732
4
      return MipsAsmParser::Match_MemSImm10Lsl3;
3733
0
    break;
3734
0
    }
3735
0
  // 'MemOffsetSimm11' class
3736
304
  case MCK_MemOffsetSimm11: {
3737
304
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<11>());
3738
304
    if (DP.isMatch())
3739
58
      return MCTargetAsmParser::Match_Success;
3740
246
    if (DP.isNearMatch())
3741
246
      return MipsAsmParser::Match_MemSImm11;
3742
0
    break;
3743
0
    }
3744
0
  // 'MemOffsetSimm12' class
3745
40
  case MCK_MemOffsetSimm12: {
3746
40
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<12>());
3747
40
    if (DP.isMatch())
3748
25
      return MCTargetAsmParser::Match_Success;
3749
15
    if (DP.isNearMatch())
3750
15
      return MipsAsmParser::Match_MemSImm12;
3751
0
    break;
3752
0
    }
3753
0
  // 'MemOffsetSimm16' class
3754
977
  case MCK_MemOffsetSimm16: {
3755
977
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<16>());
3756
977
    if (DP.isMatch())
3757
690
      return MCTargetAsmParser::Match_Success;
3758
287
    if (DP.isNearMatch())
3759
287
      return MipsAsmParser::Match_MemSImm16;
3760
0
    break;
3761
0
    }
3762
0
  // 'MemOffsetSimm9' class
3763
1.83k
  case MCK_MemOffsetSimm9: {
3764
1.83k
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<9>());
3765
1.83k
    if (DP.isMatch())
3766
586
      return MCTargetAsmParser::Match_Success;
3767
1.25k
    if (DP.isNearMatch())
3768
1.25k
      return MipsAsmParser::Match_MemSImm9;
3769
0
    break;
3770
0
    }
3771
0
  // 'MemOffsetSimmPtr' class
3772
381
  case MCK_MemOffsetSimmPtr: {
3773
381
    DiagnosticPredicate DP(Operand.isMemWithPtrSizeOffset());
3774
381
    if (DP.isMatch())
3775
335
      return MCTargetAsmParser::Match_Success;
3776
46
    if (DP.isNearMatch())
3777
46
      return MipsAsmParser::Match_MemSImmPtr;
3778
0
    break;
3779
0
    }
3780
0
  // 'MemOffsetUimm4' class
3781
18
  case MCK_MemOffsetUimm4: {
3782
18
    DiagnosticPredicate DP(Operand.isMemWithUimmOffsetSP<6>());
3783
18
    if (DP.isMatch())
3784
10
      return MCTargetAsmParser::Match_Success;
3785
8
    break;
3786
8
    }
3787
8
  // 'Mem' class
3788
12.0k
  case MCK_Mem: {
3789
12.0k
    DiagnosticPredicate DP(Operand.isMem());
3790
12.0k
    if (DP.isMatch())
3791
11.8k
      return MCTargetAsmParser::Match_Success;
3792
148
    break;
3793
148
    }
3794
148
  // 'RegList16' class
3795
148
  case MCK_RegList16: {
3796
36
    DiagnosticPredicate DP(Operand.isRegList16());
3797
36
    if (DP.isMatch())
3798
18
      return MCTargetAsmParser::Match_Success;
3799
18
    break;
3800
18
    }
3801
18
  // 'RegList' class
3802
55
  case MCK_RegList: {
3803
55
    DiagnosticPredicate DP(Operand.isRegList());
3804
55
    if (DP.isMatch())
3805
55
      return MCTargetAsmParser::Match_Success;
3806
0
    break;
3807
0
    }
3808
0
  // 'Simm19_Lsl2' class
3809
94
  case MCK_Simm19_Lsl2: {
3810
94
    DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>());
3811
94
    if (DP.isMatch())
3812
52
      return MCTargetAsmParser::Match_Success;
3813
42
    if (DP.isNearMatch())
3814
42
      return MipsAsmParser::Match_SImm19_Lsl2;
3815
0
    break;
3816
0
    }
3817
0
  // 'StrictlyAFGR64AsmReg' class
3818
91
  case MCK_StrictlyAFGR64AsmReg: {
3819
91
    DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
3820
91
    if (DP.isMatch())
3821
91
      return MCTargetAsmParser::Match_Success;
3822
0
    break;
3823
0
    }
3824
0
  // 'StrictlyFGR32AsmReg' class
3825
66
  case MCK_StrictlyFGR32AsmReg: {
3826
66
    DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
3827
66
    if (DP.isMatch())
3828
66
      return MCTargetAsmParser::Match_Success;
3829
0
    break;
3830
0
    }
3831
0
  // 'StrictlyFGR64AsmReg' class
3832
52
  case MCK_StrictlyFGR64AsmReg: {
3833
52
    DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
3834
52
    if (DP.isMatch())
3835
52
      return MCTargetAsmParser::Match_Success;
3836
0
    break;
3837
0
    }
3838
0
  // 'ConstantImmz' class
3839
12
  case MCK_ConstantImmz: {
3840
12
    DiagnosticPredicate DP(Operand.isConstantImmz());
3841
12
    if (DP.isMatch())
3842
4
      return MCTargetAsmParser::Match_Success;
3843
8
    if (DP.isNearMatch())
3844
8
      return MipsAsmParser::Match_Immz;
3845
0
    break;
3846
0
    }
3847
0
  // 'ConstantUImm1_0' class
3848
69
  case MCK_ConstantUImm1_0: {
3849
69
    DiagnosticPredicate DP(Operand.isConstantUImm<1, 0>());
3850
69
    if (DP.isMatch())
3851
55
      return MCTargetAsmParser::Match_Success;
3852
14
    if (DP.isNearMatch())
3853
14
      return MipsAsmParser::Match_UImm1_0;
3854
0
    break;
3855
0
    }
3856
0
  // 'ConstantUImm2_0' class
3857
85
  case MCK_ConstantUImm2_0: {
3858
85
    DiagnosticPredicate DP(Operand.isConstantUImm<2, 0>());
3859
85
    if (DP.isMatch())
3860
31
      return MCTargetAsmParser::Match_Success;
3861
54
    if (DP.isNearMatch())
3862
54
      return MipsAsmParser::Match_UImm2_0;
3863
0
    break;
3864
0
    }
3865
0
  // 'ConstantUImm2_1' class
3866
56
  case MCK_ConstantUImm2_1: {
3867
56
    DiagnosticPredicate DP(Operand.isConstantUImm<2, 1>());
3868
56
    if (DP.isMatch())
3869
18
      return MCTargetAsmParser::Match_Success;
3870
38
    if (DP.isNearMatch())
3871
38
      return MipsAsmParser::Match_UImm2_1;
3872
0
    break;
3873
0
    }
3874
0
  // 'ConstantUImm3_0' class
3875
410
  case MCK_ConstantUImm3_0: {
3876
410
    DiagnosticPredicate DP(Operand.isConstantUImm<3, 0>());
3877
410
    if (DP.isMatch())
3878
229
      return MCTargetAsmParser::Match_Success;
3879
181
    if (DP.isNearMatch())
3880
181
      return MipsAsmParser::Match_UImm3_0;
3881
0
    break;
3882
0
    }
3883
0
  // 'ConstantSImm4_0' class
3884
8
  case MCK_ConstantSImm4_0: {
3885
8
    DiagnosticPredicate DP(Operand.isConstantSImm<4, 0>());
3886
8
    if (DP.isMatch())
3887
4
      return MCTargetAsmParser::Match_Success;
3888
4
    if (DP.isNearMatch())
3889
4
      return MipsAsmParser::Match_SImm4_0;
3890
0
    break;
3891
0
    }
3892
0
  // 'ConstantUImm4_0' class
3893
291
  case MCK_ConstantUImm4_0: {
3894
291
    DiagnosticPredicate DP(Operand.isConstantUImm<4, 0>());
3895
291
    if (DP.isMatch())
3896
81
      return MCTargetAsmParser::Match_Success;
3897
210
    if (DP.isNearMatch())
3898
210
      return MipsAsmParser::Match_UImm4_0;
3899
0
    break;
3900
0
    }
3901
0
  // 'ConstantSImm5_0' class
3902
60
  case MCK_ConstantSImm5_0: {
3903
60
    DiagnosticPredicate DP(Operand.isConstantSImm<5, 0>());
3904
60
    if (DP.isMatch())
3905
20
      return MCTargetAsmParser::Match_Success;
3906
40
    if (DP.isNearMatch())
3907
40
      return MipsAsmParser::Match_SImm5_0;
3908
0
    break;
3909
0
    }
3910
0
  // 'ConstantUImm5_0' class
3911
2.09k
  case MCK_ConstantUImm5_0: {
3912
2.09k
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>());
3913
2.09k
    if (DP.isMatch())
3914
869
      return MCTargetAsmParser::Match_Success;
3915
1.22k
    if (DP.isNearMatch())
3916
1.22k
      return MipsAsmParser::Match_UImm5_0;
3917
0
    break;
3918
0
    }
3919
0
  // 'ConstantUImm5_1' class
3920
129
  case MCK_ConstantUImm5_1: {
3921
129
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>());
3922
129
    if (DP.isMatch())
3923
79
      return MCTargetAsmParser::Match_Success;
3924
50
    if (DP.isNearMatch())
3925
50
      return MipsAsmParser::Match_UImm5_1;
3926
0
    break;
3927
0
    }
3928
0
  // 'ConstantUImm5_Plus1_Report_UImm6' class
3929
11
  case MCK_ConstantUImm5_Plus1_Report_UImm6: {
3930
11
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>());
3931
11
    if (DP.isMatch())
3932
9
      return MCTargetAsmParser::Match_Success;
3933
2
    if (DP.isNearMatch())
3934
2
      return MipsAsmParser::Match_UImm5_1;
3935
0
    break;
3936
0
    }
3937
0
  // 'ConstantUImm5_32_Norm' class
3938
16
  case MCK_ConstantUImm5_32_Norm: {
3939
16
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>());
3940
16
    if (DP.isMatch())
3941
6
      return MCTargetAsmParser::Match_Success;
3942
10
    if (DP.isNearMatch())
3943
10
      return MipsAsmParser::Match_UImm5_32;
3944
0
    break;
3945
0
    }
3946
0
  // 'ConstantUImm5_32' class
3947
76
  case MCK_ConstantUImm5_32: {
3948
76
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>());
3949
76
    if (DP.isMatch())
3950
34
      return MCTargetAsmParser::Match_Success;
3951
42
    if (DP.isNearMatch())
3952
42
      return MipsAsmParser::Match_UImm5_32;
3953
0
    break;
3954
0
    }
3955
0
  // 'ConstantUImm5_0_Report_UImm6' class
3956
23
  case MCK_ConstantUImm5_0_Report_UImm6: {
3957
23
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>());
3958
23
    if (DP.isMatch())
3959
13
      return MCTargetAsmParser::Match_Success;
3960
10
    if (DP.isNearMatch())
3961
10
      return MipsAsmParser::Match_UImm5_0_Report_UImm6;
3962
0
    break;
3963
0
    }
3964
0
  // 'ConstantUImm5_33' class
3965
26
  case MCK_ConstantUImm5_33: {
3966
26
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 33>());
3967
26
    if (DP.isMatch())
3968
11
      return MCTargetAsmParser::Match_Success;
3969
15
    if (DP.isNearMatch())
3970
15
      return MipsAsmParser::Match_UImm5_33;
3971
0
    break;
3972
0
    }
3973
0
  // 'ConstantUImmRange2_64' class
3974
28
  case MCK_ConstantUImmRange2_64: {
3975
28
    DiagnosticPredicate DP(Operand.isConstantUImmRange<2, 64>());
3976
28
    if (DP.isMatch())
3977
18
      return MCTargetAsmParser::Match_Success;
3978
10
    if (DP.isNearMatch())
3979
10
      return MipsAsmParser::Match_UImmRange2_64;
3980
0
    break;
3981
0
    }
3982
0
  // 'UImm5Lsl2' class
3983
26
  case MCK_UImm5Lsl2: {
3984
26
    DiagnosticPredicate DP(Operand.isScaledUImm<5, 2>());
3985
26
    if (DP.isMatch())
3986
4
      return MCTargetAsmParser::Match_Success;
3987
22
    if (DP.isNearMatch())
3988
22
      return MipsAsmParser::Match_UImm5_Lsl2;
3989
0
    break;
3990
0
    }
3991
0
  // 'ConstantSImm6_0' class
3992
22
  case MCK_ConstantSImm6_0: {
3993
22
    DiagnosticPredicate DP(Operand.isConstantSImm<6, 0>());
3994
22
    if (DP.isMatch())
3995
14
      return MCTargetAsmParser::Match_Success;
3996
8
    if (DP.isNearMatch())
3997
8
      return MipsAsmParser::Match_SImm6_0;
3998
0
    break;
3999
0
    }
4000
0
  // 'ConstantUImm6_0' class
4001
302
  case MCK_ConstantUImm6_0: {
4002
302
    DiagnosticPredicate DP(Operand.isConstantUImm<6, 0>());
4003
302
    if (DP.isMatch())
4004
119
      return MCTargetAsmParser::Match_Success;
4005
183
    if (DP.isNearMatch())
4006
183
      return MipsAsmParser::Match_UImm6_0;
4007
0
    break;
4008
0
    }
4009
0
  // 'UImm6Lsl2' class
4010
10
  case MCK_UImm6Lsl2: {
4011
10
    DiagnosticPredicate DP(Operand.isScaledUImm<6, 2>());
4012
10
    if (DP.isMatch())
4013
4
      return MCTargetAsmParser::Match_Success;
4014
6
    if (DP.isNearMatch())
4015
6
      return MipsAsmParser::Match_UImm6_Lsl2;
4016
0
    break;
4017
0
    }
4018
0
  // 'ConstantUImm7_0' class
4019
19
  case MCK_ConstantUImm7_0: {
4020
19
    DiagnosticPredicate DP(Operand.isConstantUImm<7, 0>());
4021
19
    if (DP.isMatch())
4022
11
      return MCTargetAsmParser::Match_Success;
4023
8
    if (DP.isNearMatch())
4024
8
      return MipsAsmParser::Match_UImm7_0;
4025
0
    break;
4026
0
    }
4027
0
  // 'UImm7_N1' class
4028
16
  case MCK_UImm7_N1: {
4029
16
    DiagnosticPredicate DP(Operand.isConstantUImm<7, -1>());
4030
16
    if (DP.isMatch())
4031
8
      return MCTargetAsmParser::Match_Success;
4032
8
    if (DP.isNearMatch())
4033
8
      return MipsAsmParser::Match_UImm7_N1;
4034
0
    break;
4035
0
    }
4036
0
  // 'ConstantUImm8_0' class
4037
46
  case MCK_ConstantUImm8_0: {
4038
46
    DiagnosticPredicate DP(Operand.isConstantUImm<8, 0>());
4039
46
    if (DP.isMatch())
4040
19
      return MCTargetAsmParser::Match_Success;
4041
27
    if (DP.isNearMatch())
4042
27
      return MipsAsmParser::Match_UImm8_0;
4043
0
    break;
4044
0
    }
4045
0
  // 'SImm7Lsl2' class
4046
0
  case MCK_SImm7Lsl2: {
4047
0
    DiagnosticPredicate DP(Operand.isScaledSImm<7, 2>());
4048
0
    if (DP.isMatch())
4049
0
      return MCTargetAsmParser::Match_Success;
4050
0
    if (DP.isNearMatch())
4051
0
      return MipsAsmParser::Match_SImm7_Lsl2;
4052
0
    break;
4053
0
    }
4054
0
  // 'ConstantSImm9_0' class
4055
0
  case MCK_ConstantSImm9_0: {
4056
0
    DiagnosticPredicate DP(Operand.isConstantSImm<9, 0>());
4057
0
    if (DP.isMatch())
4058
0
      return MCTargetAsmParser::Match_Success;
4059
0
    if (DP.isNearMatch())
4060
0
      return MipsAsmParser::Match_SImm9_0;
4061
0
    break;
4062
0
    }
4063
0
  // 'ConstantSImm10_0' class
4064
44
  case MCK_ConstantSImm10_0: {
4065
44
    DiagnosticPredicate DP(Operand.isConstantSImm<10, 0>());
4066
44
    if (DP.isMatch())
4067
18
      return MCTargetAsmParser::Match_Success;
4068
26
    if (DP.isNearMatch())
4069
26
      return MipsAsmParser::Match_SImm10_0;
4070
0
    break;
4071
0
    }
4072
0
  // 'ConstantUImm10_0' class
4073
470
  case MCK_ConstantUImm10_0: {
4074
470
    DiagnosticPredicate DP(Operand.isConstantUImm<10, 0>());
4075
470
    if (DP.isMatch())
4076
258
      return MCTargetAsmParser::Match_Success;
4077
212
    if (DP.isNearMatch())
4078
212
      return MipsAsmParser::Match_UImm10_0;
4079
0
    break;
4080
0
    }
4081
0
  // 'SImm10Lsl1' class
4082
0
  case MCK_SImm10Lsl1: {
4083
0
    DiagnosticPredicate DP(Operand.isScaledSImm<10, 1>());
4084
0
    if (DP.isMatch())
4085
0
      return MCTargetAsmParser::Match_Success;
4086
0
    if (DP.isNearMatch())
4087
0
      return MipsAsmParser::Match_SImm10_Lsl1;
4088
0
    break;
4089
0
    }
4090
0
  // 'ConstantSImm11_0' class
4091
0
  case MCK_ConstantSImm11_0: {
4092
0
    DiagnosticPredicate DP(Operand.isConstantSImm<11, 0>());
4093
0
    if (DP.isMatch())
4094
0
      return MCTargetAsmParser::Match_Success;
4095
0
    if (DP.isNearMatch())
4096
0
      return MipsAsmParser::Match_SImm11_0;
4097
0
    break;
4098
0
    }
4099
0
  // 'SImm10Lsl2' class
4100
0
  case MCK_SImm10Lsl2: {
4101
0
    DiagnosticPredicate DP(Operand.isScaledSImm<10, 2>());
4102
0
    if (DP.isMatch())
4103
0
      return MCTargetAsmParser::Match_Success;
4104
0
    if (DP.isNearMatch())
4105
0
      return MipsAsmParser::Match_SImm10_Lsl2;
4106
0
    break;
4107
0
    }
4108
0
  // 'SImm10Lsl3' class
4109
0
  case MCK_SImm10Lsl3: {
4110
0
    DiagnosticPredicate DP(Operand.isScaledSImm<10, 3>());
4111
0
    if (DP.isMatch())
4112
0
      return MCTargetAsmParser::Match_Success;
4113
0
    if (DP.isNearMatch())
4114
0
      return MipsAsmParser::Match_SImm10_Lsl3;
4115
0
    break;
4116
0
    }
4117
0
  // 'SImm16' class
4118
3.68k
  case MCK_SImm16: {
4119
3.68k
    DiagnosticPredicate DP(Operand.isSImm<16>());
4120
3.68k
    if (DP.isMatch())
4121
1.98k
      return MCTargetAsmParser::Match_Success;
4122
1.69k
    if (DP.isNearMatch())
4123
1.69k
      return MipsAsmParser::Match_SImm16;
4124
0
    break;
4125
0
    }
4126
0
  // 'SImm16_Relaxed' class
4127
1.13k
  case MCK_SImm16_Relaxed: {
4128
1.13k
    DiagnosticPredicate DP(Operand.isAnyImm<16>());
4129
1.13k
    if (DP.isMatch())
4130
516
      return MCTargetAsmParser::Match_Success;
4131
619
    if (DP.isNearMatch())
4132
619
      return MipsAsmParser::Match_SImm16_Relaxed;
4133
0
    break;
4134
0
    }
4135
0
  // 'UImm16_AltRelaxed' class
4136
11
  case MCK_UImm16_AltRelaxed: {
4137
11
    DiagnosticPredicate DP(Operand.isUImm<16>());
4138
11
    if (DP.isMatch())
4139
6
      return MCTargetAsmParser::Match_Success;
4140
5
    if (DP.isNearMatch())
4141
5
      return MipsAsmParser::Match_UImm16_AltRelaxed;
4142
0
    break;
4143
0
    }
4144
0
  // 'UImm16' class
4145
913
  case MCK_UImm16: {
4146
913
    DiagnosticPredicate DP(Operand.isUImm<16>());
4147
913
    if (DP.isMatch())
4148
357
      return MCTargetAsmParser::Match_Success;
4149
556
    if (DP.isNearMatch())
4150
556
      return MipsAsmParser::Match_UImm16;
4151
0
    break;
4152
0
    }
4153
0
  // 'SImm19Lsl2' class
4154
0
  case MCK_SImm19Lsl2: {
4155
0
    DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>());
4156
0
    if (DP.isMatch())
4157
0
      return MCTargetAsmParser::Match_Success;
4158
0
    if (DP.isNearMatch())
4159
0
      return MipsAsmParser::Match_SImm19_Lsl2;
4160
0
    break;
4161
0
    }
4162
0
  // 'UImm16_Relaxed' class
4163
225
  case MCK_UImm16_Relaxed: {
4164
225
    DiagnosticPredicate DP(Operand.isAnyImm<16>());
4165
225
    if (DP.isMatch())
4166
225
      return MCTargetAsmParser::Match_Success;
4167
0
    if (DP.isNearMatch())
4168
0
      return MipsAsmParser::Match_UImm16_Relaxed;
4169
0
    break;
4170
0
    }
4171
0
  // 'ConstantUImm20_0' class
4172
47
  case MCK_ConstantUImm20_0: {
4173
47
    DiagnosticPredicate DP(Operand.isConstantUImm<20, 0>());
4174
47
    if (DP.isMatch())
4175
32
      return MCTargetAsmParser::Match_Success;
4176
15
    if (DP.isNearMatch())
4177
15
      return MipsAsmParser::Match_UImm20_0;
4178
0
    break;
4179
0
    }
4180
0
  // 'ConstantUImm26_0' class
4181
0
  case MCK_ConstantUImm26_0: {
4182
0
    DiagnosticPredicate DP(Operand.isConstantUImm<26, 0>());
4183
0
    if (DP.isMatch())
4184
0
      return MCTargetAsmParser::Match_Success;
4185
0
    if (DP.isNearMatch())
4186
0
      return MipsAsmParser::Match_UImm26_0;
4187
0
    break;
4188
0
    }
4189
0
  // 'SImm32' class
4190
198
  case MCK_SImm32: {
4191
198
    DiagnosticPredicate DP(Operand.isSImm<32>());
4192
198
    if (DP.isMatch())
4193
50
      return MCTargetAsmParser::Match_Success;
4194
148
    if (DP.isNearMatch())
4195
148
      return MipsAsmParser::Match_SImm32;
4196
0
    break;
4197
0
    }
4198
0
  // 'SImm32_Relaxed' class
4199
2.24k
  case MCK_SImm32_Relaxed: {
4200
2.24k
    DiagnosticPredicate DP(Operand.isAnyImm<33>());
4201
2.24k
    if (DP.isMatch())
4202
1.02k
      return MCTargetAsmParser::Match_Success;
4203
1.21k
    if (DP.isNearMatch())
4204
1.21k
      return MipsAsmParser::Match_SImm32_Relaxed;
4205
0
    break;
4206
0
    }
4207
0
  // 'UImm32_Coerced' class
4208
209
  case MCK_UImm32_Coerced: {
4209
209
    DiagnosticPredicate DP(Operand.isSImm<33>());
4210
209
    if (DP.isMatch())
4211
206
      return MCTargetAsmParser::Match_Success;
4212
3
    if (DP.isNearMatch())
4213
3
      return MipsAsmParser::Match_UImm32_Coerced;
4214
0
    break;
4215
0
    }
4216
33.1k
  } // end switch (Kind)
4217
33.1k
4218
33.1k
  if (Operand.isReg()) {
4219
251
    MatchClassKind OpKind;
4220
251
    switch (Operand.getReg()) {
4221
251
    
default: OpKind = InvalidMatchClass; break0
;
4222
251
    case Mips::ZERO: OpKind = MCK_GPR32ZERO; break;
4223
251
    
case Mips::AT: OpKind = MCK_GPR32NONZERO; break0
;
4224
251
    
case Mips::V0: OpKind = MCK_Reg11; break0
;
4225
251
    
case Mips::V1: OpKind = MCK_Reg11; break0
;
4226
251
    
case Mips::A0: OpKind = MCK_GPRMM16MovePPairFirst; break0
;
4227
251
    
case Mips::A1: OpKind = MCK_Reg13; break0
;
4228
251
    
case Mips::A2: OpKind = MCK_Reg13; break0
;
4229
251
    
case Mips::A3: OpKind = MCK_Reg14; break0
;
4230
251
    
case Mips::T0: OpKind = MCK_GPR32NONZERO; break0
;
4231
251
    
case Mips::T1: OpKind = MCK_GPR32NONZERO; break0
;
4232
251
    
case Mips::T2: OpKind = MCK_GPR32NONZERO; break0
;
4233
251
    
case Mips::T3: OpKind = MCK_GPR32NONZERO; break0
;
4234
251
    
case Mips::T4: OpKind = MCK_GPR32NONZERO; break0
;
4235
251
    
case Mips::T5: OpKind = MCK_GPR32NONZERO; break0
;
4236
251
    
case Mips::T6: OpKind = MCK_GPR32NONZERO; break0
;
4237
251
    
case Mips::T7: OpKind = MCK_GPR32NONZERO; break0
;
4238
251
    
case Mips::S0: OpKind = MCK_Reg9; break0
;
4239
251
    
case Mips::S1: OpKind = MCK_Reg11; break0
;
4240
251
    
case Mips::S2: OpKind = MCK_Reg10; break0
;
4241
251
    
case Mips::S3: OpKind = MCK_Reg10; break0
;
4242
251
    
case Mips::S4: OpKind = MCK_Reg10; break0
;
4243
251
    
case Mips::S5: OpKind = MCK_GPRMM16MovePPairSecond; break0
;
4244
251
    
case Mips::S6: OpKind = MCK_GPRMM16MovePPairSecond; break0
;
4245
251
    
case Mips::S7: OpKind = MCK_GPR32NONZERO; break0
;
4246
251
    
case Mips::T8: OpKind = MCK_GPR32NONZERO; break0
;
4247
251
    
case Mips::T9: OpKind = MCK_GPR32NONZERO; break0
;
4248
251
    
case Mips::K0: OpKind = MCK_GPR32NONZERO; break0
;
4249
251
    
case Mips::K1: OpKind = MCK_GPR32NONZERO; break0
;
4250
251
    
case Mips::GP: OpKind = MCK_GP32; break0
;
4251
251
    
case Mips::SP: OpKind = MCK_CPUSPReg; break0
;
4252
251
    
case Mips::FP: OpKind = MCK_GPR32NONZERO; break0
;
4253
251
    
case Mips::RA: OpKind = MCK_CPURAReg; break0
;
4254
251
    
case Mips::ZERO_64: OpKind = MCK_Reg19; break0
;
4255
251
    
case Mips::AT_64: OpKind = MCK_Reg24; break0
;
4256
251
    
case Mips::V0_64: OpKind = MCK_Reg30; break0
;
4257
251
    
case Mips::V1_64: OpKind = MCK_Reg30; break0
;
4258
251
    
case Mips::A0_64: OpKind = MCK_Reg31; break0
;
4259
251
    
case Mips::A1_64: OpKind = MCK_Reg32; break0
;
4260
251
    
case Mips::A2_64: OpKind = MCK_Reg32; break0
;
4261
251
    
case Mips::A3_64: OpKind = MCK_Reg33; break0
;
4262
251
    
case Mips::T0_64: OpKind = MCK_Reg24; break0
;
4263
251
    
case Mips::T1_64: OpKind = MCK_Reg24; break0
;
4264
251
    
case Mips::T2_64: OpKind = MCK_Reg24; break0
;
4265
251
    
case Mips::T3_64: OpKind = MCK_Reg24; break0
;
4266
251
    
case Mips::T4_64: OpKind = MCK_Reg24; break0
;
4267
251
    
case Mips::T5_64: OpKind = MCK_Reg24; break0
;
4268
251
    
case Mips::T6_64: OpKind = MCK_Reg24; break0
;
4269
251
    
case Mips::T7_64: OpKind = MCK_Reg24; break0
;
4270
251
    
case Mips::S0_64: OpKind = MCK_Reg28; break0
;
4271
251
    
case Mips::S1_64: OpKind = MCK_Reg30; break0
;
4272
251
    
case Mips::S2_64: OpKind = MCK_Reg29; break0
;
4273
251
    
case Mips::S3_64: OpKind = MCK_Reg29; break0
;
4274
251
    
case Mips::S4_64: OpKind = MCK_Reg29; break0
;
4275
251
    
case Mips::S5_64: OpKind = MCK_Reg34; break0
;
4276
251
    
case Mips::S6_64: OpKind = MCK_Reg34; break0
;
4277
251
    
case Mips::S7_64: OpKind = MCK_Reg24; break0
;
4278
251
    
case Mips::T8_64: OpKind = MCK_Reg24; break0
;
4279
251
    
case Mips::T9_64: OpKind = MCK_Reg24; break0
;
4280
251
    
case Mips::K0_64: OpKind = MCK_Reg24; break0
;
4281
251
    
case Mips::K1_64: OpKind = MCK_Reg24; break0
;
4282
251
    
case Mips::GP_64: OpKind = MCK_GP64; break0
;
4283
251
    
case Mips::SP_64: OpKind = MCK_SP64; break0
;
4284
251
    
case Mips::FP_64: OpKind = MCK_Reg24; break0
;
4285
251
    
case Mips::RA_64: OpKind = MCK_Reg37; break0
;
4286
251
    
case Mips::F0: OpKind = MCK_FGR32; break0
;
4287
251
    
case Mips::F1: OpKind = MCK_Reg39; break0
;
4288
251
    
case Mips::F2: OpKind = MCK_FGR32; break0
;
4289
251
    
case Mips::F3: OpKind = MCK_Reg39; break0
;
4290
251
    
case Mips::F4: OpKind = MCK_FGR32; break0
;
4291
251
    
case Mips::F5: OpKind = MCK_Reg39; break0
;
4292
251
    
case Mips::F6: OpKind = MCK_FGR32; break0
;
4293
251
    
case Mips::F7: OpKind = MCK_Reg39; break0
;
4294
251
    
case Mips::F8: OpKind = MCK_FGR32; break0
;
4295
251
    
case Mips::F9: OpKind = MCK_Reg39; break0
;
4296
251
    
case Mips::F10: OpKind = MCK_FGR32; break0
;
4297
251
    
case Mips::F11: OpKind = MCK_Reg39; break0
;
4298
251
    
case Mips::F12: OpKind = MCK_FGR32; break0
;
4299
251
    
case Mips::F13: OpKind = MCK_Reg39; break0
;
4300
251
    
case Mips::F14: OpKind = MCK_FGR32; break0
;
4301
251
    
case Mips::F15: OpKind = MCK_Reg39; break0
;
4302
251
    
case Mips::F16: OpKind = MCK_FGR32; break0
;
4303
251
    
case Mips::F17: OpKind = MCK_Reg39; break0
;
4304
251
    
case Mips::F18: OpKind = MCK_FGR32; break0
;
4305
251
    
case Mips::F19: OpKind = MCK_Reg39; break0
;
4306
251
    
case Mips::F20: OpKind = MCK_FGR32; break0
;
4307
251
    
case Mips::F21: OpKind = MCK_Reg39; break0
;
4308
251
    
case Mips::F22: OpKind = MCK_FGR32; break0
;
4309
251
    
case Mips::F23: OpKind = MCK_Reg39; break0
;
4310
251
    
case Mips::F24: OpKind = MCK_FGR32; break0
;
4311
251
    
case Mips::F25: OpKind = MCK_Reg39; break0
;
4312
251
    
case Mips::F26: OpKind = MCK_FGR32; break0
;
4313
251
    
case Mips::F27: OpKind = MCK_Reg39; break0
;
4314
251
    
case Mips::F28: OpKind = MCK_FGR32; break0
;
4315
251
    
case Mips::F29: OpKind = MCK_Reg39; break0
;
4316
251
    
case Mips::F30: OpKind = MCK_FGR32; break0
;
4317
251
    
case Mips::F31: OpKind = MCK_Reg39; break0
;
4318
251
    
case Mips::F_HI0: OpKind = MCK_FGRH32; break0
;
4319
251
    
case Mips::F_HI1: OpKind = MCK_Reg42; break0
;
4320
251
    
case Mips::F_HI2: OpKind = MCK_FGRH32; break0
;
4321
251
    
case Mips::F_HI3: OpKind = MCK_Reg42; break0
;
4322
251
    
case Mips::F_HI4: OpKind = MCK_FGRH32; break0
;
4323
251
    
case Mips::F_HI5: OpKind = MCK_Reg42; break0
;
4324
251
    
case Mips::F_HI6: OpKind = MCK_FGRH32; break0
;
4325
251
    
case Mips::F_HI7: OpKind = MCK_Reg42; break0
;
4326
251
    
case Mips::F_HI8: OpKind = MCK_FGRH32; break0
;
4327
251
    
case Mips::F_HI9: OpKind = MCK_Reg42; break0
;
4328
251
    
case Mips::F_HI10: OpKind = MCK_FGRH32; break0
;
4329
251
    
case Mips::F_HI11: OpKind = MCK_Reg42; break0
;
4330
251
    
case Mips::F_HI12: OpKind = MCK_FGRH32; break0
;
4331
251
    
case Mips::F_HI13: OpKind = MCK_Reg42; break0
;
4332
251
    
case Mips::F_HI14: OpKind = MCK_FGRH32; break0
;
4333
251
    
case Mips::F_HI15: OpKind = MCK_Reg42; break0
;
4334
251
    
case Mips::F_HI16: OpKind = MCK_FGRH32; break0
;
4335
251
    
case Mips::F_HI17: OpKind = MCK_Reg42; break0
;
4336
251
    
case Mips::F_HI18: OpKind = MCK_FGRH32; break0
;
4337
251
    
case Mips::F_HI19: OpKind = MCK_Reg42; break0
;
4338
251
    
case Mips::F_HI20: OpKind = MCK_FGRH32; break0
;
4339
251
    
case Mips::F_HI21: OpKind = MCK_Reg42; break0
;
4340
251
    
case Mips::F_HI22: OpKind = MCK_FGRH32; break0
;
4341
251
    
case Mips::F_HI23: OpKind = MCK_Reg42; break0
;
4342
251
    
case Mips::F_HI24: OpKind = MCK_FGRH32; break0
;
4343
251
    
case Mips::F_HI25: OpKind = MCK_Reg42; break0
;
4344
251
    
case Mips::F_HI26: OpKind = MCK_FGRH32; break0
;
4345
251
    
case Mips::F_HI27: OpKind = MCK_Reg42; break0
;
4346
251
    
case Mips::F_HI28: OpKind = MCK_FGRH32; break0
;
4347
251
    
case Mips::F_HI29: OpKind = MCK_Reg42; break0
;
4348
251
    
case Mips::F_HI30: OpKind = MCK_FGRH32; break0
;
4349
251
    
case Mips::F_HI31: OpKind = MCK_Reg42; break0
;
4350
251
    
case Mips::D0: OpKind = MCK_AFGR64; break0
;
4351
251
    
case Mips::D1: OpKind = MCK_Reg44; break0
;
4352
251
    
case Mips::D2: OpKind = MCK_AFGR64; break0
;
4353
251
    
case Mips::D3: OpKind = MCK_Reg44; break0
;
4354
251
    
case Mips::D4: OpKind = MCK_AFGR64; break0
;
4355
251
    
case Mips::D5: OpKind = MCK_Reg44; break0
;
4356
251
    
case Mips::D6: OpKind = MCK_AFGR64; break0
;
4357
251
    
case Mips::D7: OpKind = MCK_Reg44; break0
;
4358
251
    
case Mips::D8: OpKind = MCK_AFGR64; break0
;
4359
251
    
case Mips::D9: OpKind = MCK_Reg44; break0
;
4360
251
    
case Mips::D10: OpKind = MCK_AFGR64; break0
;
4361
251
    
case Mips::D11: OpKind = MCK_Reg44; break0
;
4362
251
    
case Mips::D12: OpKind = MCK_AFGR64; break0
;
4363
251
    
case Mips::D13: OpKind = MCK_Reg44; break0
;
4364
251
    
case Mips::D14: OpKind = MCK_AFGR64; break0
;
4365
251
    
case Mips::D15: OpKind = MCK_Reg44; break0
;
4366
251
    
case Mips::D0_64: OpKind = MCK_FGR64; break0
;
4367
251
    
case Mips::D1_64: OpKind = MCK_Reg47; break0
;
4368
251
    
case Mips::D2_64: OpKind = MCK_FGR64; break0
;
4369
251
    
case Mips::D3_64: OpKind = MCK_Reg47; break0
;
4370
251
    
case Mips::D4_64: OpKind = MCK_FGR64; break0
;
4371
251
    
case Mips::D5_64: OpKind = MCK_Reg47; break0
;
4372
251
    
case Mips::D6_64: OpKind = MCK_FGR64; break0
;
4373
251
    
case Mips::D7_64: OpKind = MCK_Reg47; break0
;
4374
251
    
case Mips::D8_64: OpKind = MCK_FGR64; break0
;
4375
251
    
case Mips::D9_64: OpKind = MCK_Reg47; break0
;
4376
251
    
case Mips::D10_64: OpKind = MCK_FGR64; break0
;
4377
251
    
case Mips::D11_64: OpKind = MCK_Reg47; break0
;
4378
251
    
case Mips::D12_64: OpKind = MCK_FGR64; break0
;
4379
251
    
case Mips::D13_64: OpKind = MCK_Reg47; break0
;
4380
251
    
case Mips::D14_64: OpKind = MCK_FGR64; break0
;
4381
251
    
case Mips::D15_64: OpKind = MCK_Reg47; break0
;
4382
251
    
case Mips::D16_64: OpKind = MCK_FGR64; break0
;
4383
251
    
case Mips::D17_64: OpKind = MCK_Reg47; break0
;
4384
251
    
case Mips::D18_64: OpKind = MCK_FGR64; break0
;
4385
251
    
case Mips::D19_64: OpKind = MCK_Reg47; break0
;
4386
251
    
case Mips::D20_64: OpKind = MCK_FGR64; break0
;
4387
251
    
case Mips::D21_64: OpKind = MCK_Reg47; break0
;
4388
251
    
case Mips::D22_64: OpKind = MCK_FGR64; break0
;
4389
251
    
case Mips::D23_64: OpKind = MCK_Reg47; break0
;
4390
251
    
case Mips::D24_64: OpKind = MCK_FGR64; break0
;
4391
251
    
case Mips::D25_64: OpKind = MCK_Reg47; break0
;
4392
251
    
case Mips::D26_64: OpKind = MCK_FGR64; break0
;
4393
251
    
case Mips::D27_64: OpKind = MCK_Reg47; break0
;
4394
251
    
case Mips::D28_64: OpKind = MCK_FGR64; break0
;
4395
251
    
case Mips::D29_64: OpKind = MCK_Reg47; break0
;
4396
251
    
case Mips::D30_64: OpKind = MCK_FGR64; break0
;
4397
251
    
case Mips::D31_64: OpKind = MCK_Reg47; break0
;
4398
251
    
case Mips::W0: OpKind = MCK_MSA128WEvens; break0
;
4399
251
    
case Mips::W1: OpKind = MCK_Reg50; break0
;
4400
251
    
case Mips::W2: OpKind = MCK_MSA128WEvens; break0
;
4401
251
    
case Mips::W3: OpKind = MCK_Reg50; break0
;
4402
251
    
case Mips::W4: OpKind = MCK_MSA128WEvens; break0
;
4403
251
    
case Mips::W5: OpKind = MCK_Reg50; break0
;
4404
251
    
case Mips::W6: OpKind = MCK_MSA128WEvens; break0
;
4405
251
    
case Mips::W7: OpKind = MCK_Reg50; break0
;
4406
251
    
case Mips::W8: OpKind = MCK_MSA128WEvens; break0
;
4407
251
    
case Mips::W9: OpKind = MCK_Reg50; break0
;
4408
251
    
case Mips::W10: OpKind = MCK_MSA128WEvens; break0
;
4409
251
    
case Mips::W11: OpKind = MCK_Reg50; break0
;
4410
251
    
case Mips::W12: OpKind = MCK_MSA128WEvens; break0
;
4411
251
    
case Mips::W13: OpKind = MCK_Reg50; break0
;
4412
251
    
case Mips::W14: OpKind = MCK_MSA128WEvens; break0
;
4413
251
    
case Mips::W15: OpKind = MCK_Reg50; break0
;
4414
251
    
case Mips::W16: OpKind = MCK_MSA128WEvens; break0
;
4415
251
    
case Mips::W17: OpKind = MCK_Reg50; break0
;
4416
251
    
case Mips::W18: OpKind = MCK_MSA128WEvens; break0
;
4417
251
    
case Mips::W19: OpKind = MCK_Reg50; break0
;
4418
251
    
case Mips::W20: OpKind = MCK_MSA128WEvens; break0
;
4419
251
    
case Mips::W21: OpKind = MCK_Reg50; break0
;
4420
251
    
case Mips::W22: OpKind = MCK_MSA128WEvens; break0
;
4421
251
    
case Mips::W23: OpKind = MCK_Reg50; break0
;
4422
251
    
case Mips::W24: OpKind = MCK_MSA128WEvens; break0
;
4423
251
    
case Mips::W25: OpKind = MCK_Reg50; break0
;
4424
251
    
case Mips::W26: OpKind = MCK_MSA128WEvens; break0
;
4425
251
    
case Mips::W27: OpKind = MCK_Reg50; break0
;
4426
251
    
case Mips::W28: OpKind = MCK_MSA128WEvens; break0
;
4427
251
    
case Mips::W29: OpKind = MCK_Reg50; break0
;
4428
251
    
case Mips::W30: OpKind = MCK_MSA128WEvens; break0
;
4429
251
    
case Mips::W31: OpKind = MCK_Reg50; break0
;
4430
251
    
case Mips::HI0: OpKind = MCK_HI32; break0
;
4431
251
    
case Mips::HI1: OpKind = MCK_HI32DSP; break0
;
4432
251
    
case Mips::HI2: OpKind = MCK_HI32DSP; break0
;
4433
251
    
case Mips::HI3: OpKind = MCK_HI32DSP; break0
;
4434
251
    
case Mips::LO0: OpKind = MCK_LO32; break0
;
4435
251
    
case Mips::LO1: OpKind = MCK_LO32DSP; break0
;
4436
251
    
case Mips::LO2: OpKind = MCK_LO32DSP; break0
;
4437
251
    
case Mips::LO3: OpKind = MCK_LO32DSP; break0
;
4438
251
    
case Mips::HI0_64: OpKind = MCK_HI64; break0
;
4439
251
    
case Mips::LO0_64: OpKind = MCK_LO64; break0
;
4440
251
    
case Mips::FCR0: OpKind = MCK_CCR; break0
;
4441
251
    
case Mips::FCR1: OpKind = MCK_CCR; break0
;
4442
251
    
case Mips::FCR2: OpKind = MCK_CCR; break0
;
4443
251
    
case Mips::FCR3: OpKind = MCK_CCR; break0
;
4444
251
    
case Mips::FCR4: OpKind = MCK_CCR; break0
;
4445
251
    
case Mips::FCR5: OpKind = MCK_CCR; break0
;
4446
251
    
case Mips::FCR6: OpKind = MCK_CCR; break0
;
4447
251
    
case Mips::FCR7: OpKind = MCK_CCR; break0
;
4448
251
    
case Mips::FCR8: OpKind = MCK_CCR; break0
;
4449
251
    
case Mips::FCR9: OpKind = MCK_CCR; break0
;
4450
251
    
case Mips::FCR10: OpKind = MCK_CCR; break0
;
4451
251
    
case Mips::FCR11: OpKind = MCK_CCR; break0
;
4452
251
    
case Mips::FCR12: OpKind = MCK_CCR; break0
;
4453
251
    
case Mips::FCR13: OpKind = MCK_CCR; break0
;
4454
251
    
case Mips::FCR14: OpKind = MCK_CCR; break0
;
4455
251
    
case Mips::FCR15: OpKind = MCK_CCR; break0
;
4456
251
    
case Mips::FCR16: OpKind = MCK_CCR; break0
;
4457
251
    
case Mips::FCR17: OpKind = MCK_CCR; break0
;
4458
251
    
case Mips::FCR18: OpKind = MCK_CCR; break0
;
4459
251
    
case Mips::FCR19: OpKind = MCK_CCR; break0
;
4460
251
    
case Mips::FCR20: OpKind = MCK_CCR; break0
;
4461
251
    
case Mips::FCR21: OpKind = MCK_CCR; break0
;
4462
251
    
case Mips::FCR22: OpKind = MCK_CCR; break0
;
4463
251
    
case Mips::FCR23: OpKind = MCK_CCR; break0
;
4464
251
    
case Mips::FCR24: OpKind = MCK_CCR; break0
;
4465
251
    
case Mips::FCR25: OpKind = MCK_CCR; break0
;
4466
251
    
case Mips::FCR26: OpKind = MCK_CCR; break0
;
4467
251
    
case Mips::FCR27: OpKind = MCK_CCR; break0
;
4468
251
    
case Mips::FCR28: OpKind = MCK_CCR; break0
;
4469
251
    
case Mips::FCR29: OpKind = MCK_CCR; break0
;
4470
251
    
case Mips::FCR30: OpKind = MCK_CCR; break0
;
4471
251
    
case Mips::FCR31: OpKind = MCK_CCR; break0
;
4472
251
    
case Mips::FCC0: OpKind = MCK_FCC; break0
;
4473
251
    
case Mips::FCC1: OpKind = MCK_FCC; break0
;
4474
251
    
case Mips::FCC2: OpKind = MCK_FCC; break0
;
4475
251
    
case Mips::FCC3: OpKind = MCK_FCC; break0
;
4476
251
    
case Mips::FCC4: OpKind = MCK_FCC; break0
;
4477
251
    
case Mips::FCC5: OpKind = MCK_FCC; break0
;
4478
251
    
case Mips::FCC6: OpKind = MCK_FCC; break0
;
4479
251
    
case Mips::FCC7: OpKind = MCK_FCC; break0
;
4480
251
    
case Mips::COP00: OpKind = MCK_COP0; break0
;
4481
251
    
case Mips::COP01: OpKind = MCK_COP0; break0
;
4482
251
    
case Mips::COP02: OpKind = MCK_COP0; break0
;
4483
251
    
case Mips::COP03: OpKind = MCK_COP0; break0
;
4484
251
    
case Mips::COP04: OpKind = MCK_COP0; break0
;
4485
251
    
case Mips::COP05: OpKind = MCK_COP0; break0
;
4486
251
    
case Mips::COP06: OpKind = MCK_COP0; break0
;
4487
251
    
case Mips::COP07: OpKind = MCK_COP0; break0
;
4488
251
    
case Mips::COP08: OpKind = MCK_COP0; break0
;
4489
251
    
case Mips::COP09: OpKind = MCK_COP0; break0
;
4490
251
    
case Mips::COP010: OpKind = MCK_COP0; break0
;
4491
251
    
case Mips::COP011: OpKind = MCK_COP0; break0
;
4492
251
    
case Mips::COP012: OpKind = MCK_COP0; break0
;
4493
251
    
case Mips::COP013: OpKind = MCK_COP0; break0
;
4494
251
    
case Mips::COP014: OpKind = MCK_COP0; break0
;
4495
251
    
case Mips::COP015: OpKind = MCK_COP0; break0
;
4496
251
    
case Mips::COP016: OpKind = MCK_COP0; break0
;
4497
251
    
case Mips::COP017: OpKind = MCK_COP0; break0
;
4498
251
    
case Mips::COP018: OpKind = MCK_COP0; break0
;
4499
251
    
case Mips::COP019: OpKind = MCK_COP0; break0
;
4500
251
    
case Mips::COP020: OpKind = MCK_COP0; break0
;
4501
251
    
case Mips::COP021: OpKind = MCK_COP0; break0
;
4502
251
    
case Mips::COP022: OpKind = MCK_COP0; break0
;
4503
251
    
case Mips::COP023: OpKind = MCK_COP0; break0
;
4504
251
    
case Mips::COP024: OpKind = MCK_COP0; break0
;
4505
251
    
case Mips::COP025: OpKind = MCK_COP0; break0
;
4506
251
    
case Mips::COP026: OpKind = MCK_COP0; break0
;
4507
251
    
case Mips::COP027: OpKind = MCK_COP0; break0
;
4508
251
    
case Mips::COP028: OpKind = MCK_COP0; break0
;
4509
251
    
case Mips::COP029: OpKind = MCK_COP0; break0
;
4510
251
    
case Mips::COP030: OpKind = MCK_COP0; break0
;
4511
251
    
case Mips::COP031: OpKind = MCK_COP0; break0
;
4512
251
    
case Mips::COP20: OpKind = MCK_COP2; break0
;
4513
251
    
case Mips::COP21: OpKind = MCK_COP2; break0
;
4514
251
    
case Mips::COP22: OpKind = MCK_COP2; break0
;
4515
251
    
case Mips::COP23: OpKind = MCK_COP2; break0
;