Coverage Report

Created: 2018-12-14 11:24

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Mips/MipsGenAsmMatcher.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Assembly Matcher Source Fragment                                           *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
#ifdef GET_ASSEMBLER_HEADER
11
#undef GET_ASSEMBLER_HEADER
12
  // This should be included into the middle of the declaration of
13
  // your subclasses implementation of MCTargetAsmParser.
14
  uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;
15
  void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
16
                       const OperandVector &Operands);
17
  void convertToMapAndConstraints(unsigned Kind,
18
                           const OperandVector &Operands) override;
19
  unsigned MatchInstructionImpl(const OperandVector &Operands,
20
                                MCInst &Inst,
21
                                uint64_t &ErrorInfo,
22
                                bool matchingInlineAsm,
23
                                unsigned VariantID = 0);
24
  OperandMatchResultTy MatchOperandParserImpl(
25
    OperandVector &Operands,
26
    StringRef Mnemonic,
27
    bool ParseForAllFeatures = false);
28
  OperandMatchResultTy tryCustomParseOperand(
29
    OperandVector &Operands,
30
    unsigned MCK);
31
32
#endif // GET_ASSEMBLER_HEADER_INFO
33
34
35
#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
36
#undef GET_OPERAND_DIAGNOSTIC_TYPES
37
38
  Match_Immz,
39
  Match_MemSImm10,
40
  Match_MemSImm10Lsl1,
41
  Match_MemSImm10Lsl2,
42
  Match_MemSImm10Lsl3,
43
  Match_MemSImm11,
44
  Match_MemSImm12,
45
  Match_MemSImm16,
46
  Match_MemSImm9,
47
  Match_MemSImmPtr,
48
  Match_SImm10_0,
49
  Match_SImm10_Lsl1,
50
  Match_SImm10_Lsl2,
51
  Match_SImm10_Lsl3,
52
  Match_SImm11_0,
53
  Match_SImm16,
54
  Match_SImm16_Relaxed,
55
  Match_SImm19_Lsl2,
56
  Match_SImm32,
57
  Match_SImm32_Relaxed,
58
  Match_SImm4_0,
59
  Match_SImm5_0,
60
  Match_SImm6_0,
61
  Match_SImm7_Lsl2,
62
  Match_SImm9_0,
63
  Match_UImm10_0,
64
  Match_UImm16,
65
  Match_UImm16_AltRelaxed,
66
  Match_UImm16_Relaxed,
67
  Match_UImm1_0,
68
  Match_UImm20_0,
69
  Match_UImm26_0,
70
  Match_UImm2_0,
71
  Match_UImm2_1,
72
  Match_UImm32_Coerced,
73
  Match_UImm3_0,
74
  Match_UImm4_0,
75
  Match_UImm5_0,
76
  Match_UImm5_0_Report_UImm6,
77
  Match_UImm5_1,
78
  Match_UImm5_32,
79
  Match_UImm5_33,
80
  Match_UImm5_Lsl2,
81
  Match_UImm6_0,
82
  Match_UImm6_Lsl2,
83
  Match_UImm7_0,
84
  Match_UImm7_N1,
85
  Match_UImm8_0,
86
  Match_UImmRange2_64,
87
  END_OPERAND_DIAGNOSTIC_TYPES
88
#endif // GET_OPERAND_DIAGNOSTIC_TYPES
89
90
91
#ifdef GET_REGISTER_MATCHER
92
#undef GET_REGISTER_MATCHER
93
94
// Flags for subtarget features that participate in instruction matching.
95
enum SubtargetFeatureFlag : uint64_t {
96
  Feature_HasMips2 = (1ULL << 10),
97
  Feature_HasMips3_32 = (1ULL << 16),
98
  Feature_HasMips3_32r2 = (1ULL << 17),
99
  Feature_HasMips3 = (1ULL << 11),
100
  Feature_NotMips3 = (1ULL << 44),
101
  Feature_HasMips4_32 = (1ULL << 18),
102
  Feature_NotMips4_32 = (1ULL << 46),
103
  Feature_HasMips4_32r2 = (1ULL << 19),
104
  Feature_HasMips5_32r2 = (1ULL << 20),
105
  Feature_HasMips32 = (1ULL << 12),
106
  Feature_HasMips32r2 = (1ULL << 13),
107
  Feature_HasMips32r5 = (1ULL << 14),
108
  Feature_HasMips32r6 = (1ULL << 15),
109
  Feature_NotMips32r6 = (1ULL << 45),
110
  Feature_IsGP64bit = (1ULL << 31),
111
  Feature_IsGP32bit = (1ULL << 30),
112
  Feature_IsPTR64bit = (1ULL << 35),
113
  Feature_IsPTR32bit = (1ULL << 34),
114
  Feature_HasMips64 = (1ULL << 21),
115
  Feature_NotMips64 = (1ULL << 47),
116
  Feature_HasMips64r2 = (1ULL << 22),
117
  Feature_HasMips64r5 = (1ULL << 23),
118
  Feature_HasMips64r6 = (1ULL << 24),
119
  Feature_NotMips64r6 = (1ULL << 48),
120
  Feature_InMips16Mode = (1ULL << 28),
121
  Feature_NotInMips16Mode = (1ULL << 43),
122
  Feature_HasCnMips = (1ULL << 1),
123
  Feature_NotCnMips = (1ULL << 40),
124
  Feature_IsSym32 = (1ULL << 37),
125
  Feature_IsSym64 = (1ULL << 38),
126
  Feature_HasStdEnc = (1ULL << 25),
127
  Feature_InMicroMips = (1ULL << 27),
128
  Feature_NotInMicroMips = (1ULL << 42),
129
  Feature_HasEVA = (1ULL << 5),
130
  Feature_HasMSA = (1ULL << 7),
131
  Feature_HasMadd4 = (1ULL << 9),
132
  Feature_HasMT = (1ULL << 8),
133
  Feature_UseIndirectJumpsHazard = (1ULL << 49),
134
  Feature_NoIndirectJumpGuards = (1ULL << 39),
135
  Feature_HasCRC = (1ULL << 0),
136
  Feature_HasVirt = (1ULL << 26),
137
  Feature_HasGINV = (1ULL << 6),
138
  Feature_IsFP64bit = (1ULL << 29),
139
  Feature_NotFP64bit = (1ULL << 41),
140
  Feature_IsSingleFloat = (1ULL << 36),
141
  Feature_IsNotSingleFloat = (1ULL << 32),
142
  Feature_IsNotSoftFloat = (1ULL << 33),
143
  Feature_HasDSP = (1ULL << 2),
144
  Feature_HasDSPR2 = (1ULL << 3),
145
  Feature_HasDSPR3 = (1ULL << 4),
146
  Feature_None = 0
147
};
148
149
#endif // GET_REGISTER_MATCHER
150
151
152
#ifdef GET_SUBTARGET_FEATURE_NAME
153
#undef GET_SUBTARGET_FEATURE_NAME
154
155
// User-level names for subtarget features that participate in
156
// instruction matching.
157
static const char *getSubtargetFeatureName(uint64_t Val) {
158
  switch(Val) {
159
  case Feature_HasMips2: return "";
160
  case Feature_HasMips3_32: return "";
161
  case Feature_HasMips3_32r2: return "";
162
  case Feature_HasMips3: return "";
163
  case Feature_NotMips3: return "";
164
  case Feature_HasMips4_32: return "";
165
  case Feature_NotMips4_32: return "";
166
  case Feature_HasMips4_32r2: return "";
167
  case Feature_HasMips5_32r2: return "";
168
  case Feature_HasMips32: return "";
169
  case Feature_HasMips32r2: return "";
170
  case Feature_HasMips32r5: return "";
171
  case Feature_HasMips32r6: return "";
172
  case Feature_NotMips32r6: return "";
173
  case Feature_IsGP64bit: return "";
174
  case Feature_IsGP32bit: return "";
175
  case Feature_IsPTR64bit: return "";
176
  case Feature_IsPTR32bit: return "";
177
  case Feature_HasMips64: return "";
178
  case Feature_NotMips64: return "";
179
  case Feature_HasMips64r2: return "";
180
  case Feature_HasMips64r5: return "";
181
  case Feature_HasMips64r6: return "";
182
  case Feature_NotMips64r6: return "";
183
  case Feature_InMips16Mode: return "";
184
  case Feature_NotInMips16Mode: return "";
185
  case Feature_HasCnMips: return "";
186
  case Feature_NotCnMips: return "";
187
  case Feature_IsSym32: return "";
188
  case Feature_IsSym64: return "";
189
  case Feature_HasStdEnc: return "";
190
  case Feature_InMicroMips: return "";
191
  case Feature_NotInMicroMips: return "";
192
  case Feature_HasEVA: return "";
193
  case Feature_HasMSA: return "";
194
  case Feature_HasMadd4: return "";
195
  case Feature_HasMT: return "";
196
  case Feature_UseIndirectJumpsHazard: return "";
197
  case Feature_NoIndirectJumpGuards: return "";
198
  case Feature_HasCRC: return "";
199
  case Feature_HasVirt: return "";
200
  case Feature_HasGINV: return "";
201
  case Feature_IsFP64bit: return "";
202
  case Feature_NotFP64bit: return "";
203
  case Feature_IsSingleFloat: return "";
204
  case Feature_IsNotSingleFloat: return "";
205
  case Feature_IsNotSoftFloat: return "";
206
  case Feature_HasDSP: return "";
207
  case Feature_HasDSPR2: return "";
208
  case Feature_HasDSPR3: return "";
209
  default: return "(unknown)";
210
  }
211
}
212
213
#endif // GET_SUBTARGET_FEATURE_NAME
214
215
216
#ifdef GET_MATCHER_IMPLEMENTATION
217
#undef GET_MATCHER_IMPLEMENTATION
218
219
enum {
220
  Tie0_1_1,
221
  Tie0_1_2,
222
};
223
224
static const uint8_t TiedAsmOperandTable[][3] = {
225
  /* Tie0_1_1 */ { 0, 1, 1 },
226
  /* Tie0_1_2 */ { 0, 1, 2 },
227
};
228
229
namespace {
230
enum OperatorConversionKind {
231
  CVT_Done,
232
  CVT_Reg,
233
  CVT_Tied,
234
  CVT_95_addGPR32AsmRegOperands,
235
  CVT_95_addAFGR64AsmRegOperands,
236
  CVT_95_addFGR64AsmRegOperands,
237
  CVT_95_addFGR32AsmRegOperands,
238
  CVT_95_addSImmOperands_LT_32_GT_,
239
  CVT_95_addMSA128AsmRegOperands,
240
  CVT_95_addSImmOperands_LT_16_GT_,
241
  CVT_95_Reg,
242
  CVT_95_addImmOperands,
243
  CVT_95_addGPRMM16AsmRegOperands,
244
  CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_,
245
  CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_,
246
  CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_,
247
  CVT_95_addUImmOperands_LT_16_GT_,
248
  CVT_95_addGPR64AsmRegOperands,
249
  CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_,
250
  CVT_regZERO,
251
  CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_,
252
  CVT_regFCC0,
253
  CVT_95_addFCCAsmRegOperands,
254
  CVT_95_addCOP2AsmRegOperands,
255
  CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_,
256
  CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_,
257
  CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_,
258
  CVT_imm_95_0,
259
  CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_,
260
  CVT_95_addMemOperands,
261
  CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_,
262
  CVT_95_addCCRAsmRegOperands,
263
  CVT_95_addMSACtrlAsmRegOperands,
264
  CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_,
265
  CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_,
266
  CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_,
267
  CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_,
268
  CVT_95_addGPR32NonZeroAsmRegOperands,
269
  CVT_95_addGPR32ZeroAsmRegOperands,
270
  CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_,
271
  CVT_95_addCOP0AsmRegOperands,
272
  CVT_regZERO_64,
273
  CVT_95_addACC64DSPAsmRegOperands,
274
  CVT_95_addConstantUImmOperands_LT_1_GT_,
275
  CVT_regRA,
276
  CVT_regRA_64,
277
  CVT_95_addMicroMipsMemOperands,
278
  CVT_95_addCOP3AsmRegOperands,
279
  CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_,
280
  CVT_95_addConstantUImmOperands_LT_32_GT_,
281
  CVT_95_addStrictlyAFGR64AsmRegOperands,
282
  CVT_95_addStrictlyFGR64AsmRegOperands,
283
  CVT_95_addStrictlyFGR32AsmRegOperands,
284
  CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_,
285
  CVT_95_addRegListOperands,
286
  CVT_ConvertXWPOperands,
287
  CVT_regAC0,
288
  CVT_95_addGPRMM16AsmRegMovePPairFirstOperands,
289
  CVT_95_addGPRMM16AsmRegMovePPairSecondOperands,
290
  CVT_95_addGPRMM16AsmRegMovePOperands,
291
  CVT_95_addHI32DSPAsmRegOperands,
292
  CVT_95_addLO32DSPAsmRegOperands,
293
  CVT_regS0,
294
  CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_,
295
  CVT_95_addHWRegsAsmRegOperands,
296
  CVT_95_addGPRMM16AsmRegZeroOperands,
297
  CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_,
298
  CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_,
299
  CVT_imm_95_2,
300
  CVT_imm_95_6,
301
  CVT_imm_95_4,
302
  CVT_imm_95_5,
303
  CVT_imm_95_31,
304
  CVT_NUM_CONVERTERS
305
};
306
307
enum InstructionConversionKind {
308
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1,
309
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1,
310
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1,
311
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1,
312
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1,
313
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1,
314
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
315
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2,
316
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2,
317
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
318
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
319
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1,
320
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2,
321
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1,
322
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1,
323
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2,
324
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2,
325
  Convert__SImm161_1,
326
  Convert__Reg1_0__SImm161_1,
327
  Convert__Reg1_0__SImm161_2,
328
  Convert__Reg1_0__Reg1_1__SImm161_2,
329
  Convert__Reg1_0__Tie0_1_1__SImm161_1,
330
  Convert__GPR32AsmReg1_0__Simm19_Lsl21_1,
331
  Convert__GPRMM16AsmReg1_0__Imm1_1,
332
  Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1,
333
  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2,
334
  Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1,
335
  Convert__Imm1_0,
336
  Convert__Reg1_0__Reg1_1__Reg1_2,
337
  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2,
338
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2,
339
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3,
340
  Convert__GPR32AsmReg1_0__SImm161_1,
341
  Convert__Reg1_0__Tie0_1_1__Reg1_1,
342
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1,
343
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1,
344
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2,
345
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2,
346
  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1,
347
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2,
348
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1,
349
  Convert__regZERO__regZERO__JumpTarget1_0,
350
  Convert__JumpTarget1_0,
351
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1,
352
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2,
353
  Convert__regZERO__JumpTarget1_0,
354
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1,
355
  Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2,
356
  Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2,
357
  Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2,
358
  Convert__FGR64AsmReg1_0__JumpTarget1_1,
359
  Convert__regFCC0__JumpTarget1_0,
360
  Convert__FCCAsmReg1_0__JumpTarget1_1,
361
  Convert__COP2AsmReg1_0__JumpTarget1_1,
362
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2,
363
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2,
364
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2,
365
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2,
366
  Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2,
367
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2,
368
  Convert__Reg1_0__JumpTarget1_1,
369
  Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1,
370
  Convert__GPRMM16AsmReg1_0__JumpTarget1_1,
371
  Convert__GPR32AsmReg1_0__JumpTarget1_1,
372
  Convert__GPR64AsmReg1_0__JumpTarget1_1,
373
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2,
374
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2,
375
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2,
376
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2,
377
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2,
378
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2,
379
  Convert__MSA128AsmReg1_0__JumpTarget1_1,
380
  Convert__imm_95_0__imm_95_0,
381
  Convert_NoOperands,
382
  Convert__ConstantUImm10_01_0__imm_95_0,
383
  Convert__ConstantUImm10_01_0__ConstantUImm10_01_1,
384
  Convert__ConstantUImm4_01_0,
385
  Convert__SImm161_0,
386
  Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1,
387
  Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1,
388
  Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2,
389
  Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
390
  Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1,
391
  Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
392
  Convert__MemOffsetSimm92_1__ConstantUImm5_01_0,
393
  Convert__Mem2_1__ConstantUImm5_01_0,
394
  Convert__FGR64AsmReg1_0__FGR32AsmReg1_1,
395
  Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1,
396
  Convert__FGR32AsmReg1_0__FGR64AsmReg1_1,
397
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2,
398
  Convert__GPR32AsmReg1_0__CCRAsmReg1_1,
399
  Convert__GPR32AsmReg1_0__COP2AsmReg1_1,
400
  Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1,
401
  Convert__GPR32AsmReg1_0__FGR32AsmReg1_1,
402
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2,
403
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2,
404
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3,
405
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3,
406
  Convert__Reg1_0__Reg1_1,
407
  Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
408
  Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3,
409
  Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3,
410
  Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3,
411
  Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3,
412
  Convert__CCRAsmReg1_1__GPR32AsmReg1_0,
413
  Convert__COP2AsmReg1_1__GPR32AsmReg1_0,
414
  Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1,
415
  Convert__FGR32AsmReg1_1__GPR32AsmReg1_0,
416
  Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1,
417
  Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
418
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1,
419
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2,
420
  Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2,
421
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3,
422
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2,
423
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1,
424
  Convert__GPR64AsmReg1_1__GPR64AsmReg1_2,
425
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3,
426
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3,
427
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3,
428
  Convert__regZERO,
429
  Convert__GPR32AsmReg1_0,
430
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1,
431
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1,
432
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1,
433
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1,
434
  Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1,
435
  Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1,
436
  Convert__Reg1_1__Reg1_2,
437
  Convert__GPR32AsmReg1_1__GPR32AsmReg1_2,
438
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2,
439
  Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
440
  Convert__GPR64AsmReg1_0__Imm1_1,
441
  Convert__GPR64AsmReg1_0__Mem2_1,
442
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3,
443
  Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0,
444
  Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2,
445
  Convert__GPR64AsmReg1_0__FGR64AsmReg1_1,
446
  Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0,
447
  Convert__GPR64AsmReg1_0__UImm161_1,
448
  Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2,
449
  Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0,
450
  Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2,
451
  Convert__FGR64AsmReg1_1__GPR64AsmReg1_0,
452
  Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0,
453
  Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2,
454
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2,
455
  Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0,
456
  Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1,
457
  Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
458
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0,
459
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1,
460
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1,
461
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2,
462
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1,
463
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2,
464
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2,
465
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1,
466
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1,
467
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2,
468
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3,
469
  Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2,
470
  Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2,
471
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1,
472
  Convert__MSA128AsmReg1_0__GPR32AsmReg1_1,
473
  Convert__MSA128AsmReg1_0__GPR64AsmReg1_1,
474
  Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2,
475
  Convert__GPR32AsmReg1_0__ConstantUImm2_01_1,
476
  Convert__imm_95_0,
477
  Convert__ConstantUImm10_01_0,
478
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1,
479
  Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2,
480
  Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2,
481
  Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2,
482
  Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2,
483
  Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1,
484
  Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
485
  Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
486
  Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
487
  Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
488
  Convert__regRA__GPR32AsmReg1_0,
489
  Convert__regRA_64__GPR64AsmReg1_0,
490
  Convert__Reg1_0,
491
  Convert__GPR32AsmReg1_0__imm_95_0,
492
  Convert__GPR64AsmReg1_0__imm_95_0,
493
  Convert__regZERO__GPR32AsmReg1_0,
494
  Convert__GPR64AsmReg1_0,
495
  Convert__regZERO_64__GPR64AsmReg1_0,
496
  Convert__UImm5Lsl21_0,
497
  Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1,
498
  Convert__FGR64AsmReg1_0__MemOffsetSimm162_1,
499
  Convert__FGR32AsmReg1_0__MemOffsetSimm162_1,
500
  Convert__GPR32AsmReg1_0__Imm1_1,
501
  Convert__GPR32AsmReg1_0__Mem2_1,
502
  Convert__GPR32AsmReg1_0__MemOffsetSimm162_1,
503
  Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1,
504
  Convert__GPR32AsmReg1_0__MemOffsetSimm92_1,
505
  Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1,
506
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
507
  Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1,
508
  Convert__MSA128AsmReg1_0__MemOffsetSimm102_1,
509
  Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1,
510
  Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1,
511
  Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1,
512
  Convert__COP2AsmReg1_0__MemOffsetSimm112_1,
513
  Convert__COP2AsmReg1_0__MemOffsetSimm162_1,
514
  Convert__COP3AsmReg1_0__Mem2_1,
515
  Convert__MSA128AsmReg1_0__ConstantSImm10_01_1,
516
  Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1,
517
  Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
518
  Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
519
  Convert__GPR32AsmReg1_0__UImm32_Coerced1_1,
520
  Convert__StrictlyAFGR64AsmReg1_0__Imm1_1,
521
  Convert__StrictlyFGR64AsmReg1_0__Imm1_1,
522
  Convert__StrictlyFGR32AsmReg1_0__Imm1_1,
523
  Convert__GPRMM16AsmReg1_0__UImm7_N11_1,
524
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3,
525
  Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3,
526
  Convert__GPR32AsmReg1_0__UImm161_1,
527
  Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1,
528
  Convert__Reg1_0__Imm1_1__imm_95_0,
529
  Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1,
530
  Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1,
531
  Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1,
532
  Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1,
533
  Convert__RegList1_0__Mem2_1,
534
  Convert__RegList161_0__MemOffsetUimm42_1,
535
  ConvertCustom_ConvertXWPOperands,
536
  Convert__GPR32AsmReg1_0__MemOffsetSimm122_1,
537
  Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
538
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3,
539
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3,
540
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3,
541
  Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2,
542
  Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2,
543
  Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0,
544
  Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2,
545
  Convert__GPR32AsmReg1_0__FGR64AsmReg1_1,
546
  Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0,
547
  Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2,
548
  Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1,
549
  Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1,
550
  Convert__GPR32AsmReg1_0__regAC0,
551
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0,
552
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4,
553
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO,
554
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64,
555
  Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3,
556
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
557
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
558
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
559
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
560
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
561
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
562
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
563
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
564
  Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0,
565
  Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2,
566
  Convert__FGR64AsmReg1_1__GPR32AsmReg1_0,
567
  Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0,
568
  Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2,
569
  Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0,
570
  Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0,
571
  Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0,
572
  Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1,
573
  Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0,
574
  Convert__regAC0__GPR32AsmReg1_0,
575
  Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0,
576
  Convert__GPR32AsmReg1_1__GPR32AsmReg1_0,
577
  Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4,
578
  Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
579
  Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0,
580
  Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1,
581
  Convert__regZERO__regZERO__imm_95_0,
582
  Convert__regZERO__regS0,
583
  Convert__regZERO__regZERO,
584
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO,
585
  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1,
586
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0,
587
  Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0,
588
  Convert__GPR32AsmReg1_0__ConstantUImm7_01_1,
589
  Convert__GPR32AsmReg1_0__ConstantUImm10_01_1,
590
  Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0,
591
  Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0,
592
  Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2,
593
  Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2,
594
  Convert__GPR32AsmReg1_0__ConstantSImm10_01_1,
595
  Convert__GPR32AsmReg1_0__ConstantUImm8_01_1,
596
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1,
597
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2,
598
  Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1,
599
  Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1,
600
  Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1,
601
  Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1,
602
  Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1,
603
  Convert__ConstantUImm20_01_0,
604
  Convert__Reg1_0__Tie0_1_1,
605
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1,
606
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2,
607
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0,
608
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1,
609
  Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1,
610
  Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1,
611
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2,
612
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2,
613
  Convert__UImm161_0,
614
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3,
615
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3,
616
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3,
617
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3,
618
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3,
619
  Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2,
620
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3,
621
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3,
622
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3,
623
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3,
624
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3,
625
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1,
626
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2,
627
  Convert__ConstantUImm5_01_0,
628
  Convert__MemOffsetSimm162_0,
629
  Convert__imm_95_2,
630
  Convert__imm_95_6,
631
  Convert__imm_95_4,
632
  Convert__imm_95_5,
633
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2,
634
  Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2,
635
  Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2,
636
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2,
637
  Convert__GPR32AsmReg1_0__imm_95_31,
638
  CVT_NUM_SIGNATURES
639
};
640
641
} // end anonymous namespace
642
643
static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][11] = {
644
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1
645
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
646
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1
647
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
648
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1
649
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
650
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1
651
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
652
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1
653
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
654
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1
655
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
656
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
657
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
658
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2
659
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
660
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2
661
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done },
662
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
663
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
664
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
665
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
666
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1
667
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
668
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2
669
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done },
670
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1
671
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
672
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1
673
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
674
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2
675
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
676
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2
677
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
678
  // Convert__SImm161_1
679
  { CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
680
  // Convert__Reg1_0__SImm161_1
681
  { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
682
  // Convert__Reg1_0__SImm161_2
683
  { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
684
  // Convert__Reg1_0__Reg1_1__SImm161_2
685
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
686
  // Convert__Reg1_0__Tie0_1_1__SImm161_1
687
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
688
  // Convert__GPR32AsmReg1_0__Simm19_Lsl21_1
689
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
690
  // Convert__GPRMM16AsmReg1_0__Imm1_1
691
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
692
  // Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1
693
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
694
  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2
695
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
696
  // Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1
697
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_, 2, CVT_Done },
698
  // Convert__Imm1_0
699
  { CVT_95_addImmOperands, 1, CVT_Done },
700
  // Convert__Reg1_0__Reg1_1__Reg1_2
701
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
702
  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2
703
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addGPRMM16AsmRegOperands, 3, CVT_Done },
704
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2
705
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
706
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3
707
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
708
  // Convert__GPR32AsmReg1_0__SImm161_1
709
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
710
  // Convert__Reg1_0__Tie0_1_1__Reg1_1
711
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
712
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1
713
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
714
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1
715
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
716
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2
717
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
718
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2
719
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
720
  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1
721
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
722
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2
723
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
724
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1
725
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done },
726
  // Convert__regZERO__regZERO__JumpTarget1_0
727
  { CVT_regZERO, 0, CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done },
728
  // Convert__JumpTarget1_0
729
  { CVT_95_addImmOperands, 1, CVT_Done },
730
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1
731
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
732
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2
733
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },
734
  // Convert__regZERO__JumpTarget1_0
735
  { CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done },
736
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1
737
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done },
738
  // Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2
739
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
740
  // Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2
741
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
742
  // Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2
743
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
744
  // Convert__FGR64AsmReg1_0__JumpTarget1_1
745
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
746
  // Convert__regFCC0__JumpTarget1_0
747
  { CVT_regFCC0, 0, CVT_95_addImmOperands, 1, CVT_Done },
748
  // Convert__FCCAsmReg1_0__JumpTarget1_1
749
  { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
750
  // Convert__COP2AsmReg1_0__JumpTarget1_1
751
  { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
752
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2
753
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
754
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2
755
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
756
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2
757
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
758
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2
759
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
760
  // Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2
761
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
762
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2
763
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
764
  // Convert__Reg1_0__JumpTarget1_1
765
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
766
  // Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1
767
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addImmOperands, 2, CVT_Done },
768
  // Convert__GPRMM16AsmReg1_0__JumpTarget1_1
769
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
770
  // Convert__GPR32AsmReg1_0__JumpTarget1_1
771
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
772
  // Convert__GPR64AsmReg1_0__JumpTarget1_1
773
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
774
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2
775
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done },
776
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2
777
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
778
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2
779
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
780
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2
781
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
782
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2
783
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
784
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2
785
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
786
  // Convert__MSA128AsmReg1_0__JumpTarget1_1
787
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
788
  // Convert__imm_95_0__imm_95_0
789
  { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
790
  // Convert_NoOperands
791
  { CVT_Done },
792
  // Convert__ConstantUImm10_01_0__imm_95_0
793
  { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_imm_95_0, 0, CVT_Done },
794
  // Convert__ConstantUImm10_01_0__ConstantUImm10_01_1
795
  { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
796
  // Convert__ConstantUImm4_01_0
797
  { CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 1, CVT_Done },
798
  // Convert__SImm161_0
799
  { CVT_95_addSImmOperands_LT_16_GT_, 1, CVT_Done },
800
  // Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1
801
  { CVT_regFCC0, 0, CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
802
  // Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1
803
  { CVT_regFCC0, 0, CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
804
  // Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2
805
  { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done },
806
  // Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
807
  { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
808
  // Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1
809
  { CVT_regFCC0, 0, CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
810
  // Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
811
  { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
812
  // Convert__MemOffsetSimm92_1__ConstantUImm5_01_0
813
  { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
814
  // Convert__Mem2_1__ConstantUImm5_01_0
815
  { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
816
  // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1
817
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
818
  // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1
819
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
820
  // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1
821
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
822
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2
823
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
824
  // Convert__GPR32AsmReg1_0__CCRAsmReg1_1
825
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCCRAsmRegOperands, 2, CVT_Done },
826
  // Convert__GPR32AsmReg1_0__COP2AsmReg1_1
827
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_Done },
828
  // Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1
829
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSACtrlAsmRegOperands, 2, CVT_Done },
830
  // Convert__GPR32AsmReg1_0__FGR32AsmReg1_1
831
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
832
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2
833
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
834
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2
835
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
836
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3
837
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done },
838
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3
839
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done },
840
  // Convert__Reg1_0__Reg1_1
841
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
842
  // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
843
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
844
  // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3
845
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
846
  // Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3
847
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
848
  // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3
849
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
850
  // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3
851
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
852
  // Convert__CCRAsmReg1_1__GPR32AsmReg1_0
853
  { CVT_95_addCCRAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
854
  // Convert__COP2AsmReg1_1__GPR32AsmReg1_0
855
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
856
  // Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1
857
  { CVT_95_addMSACtrlAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
858
  // Convert__FGR32AsmReg1_1__GPR32AsmReg1_0
859
  { CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
860
  // Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1
861
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
862
  // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
863
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
864
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1
865
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
866
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2
867
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
868
  // Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2
869
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
870
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3
871
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
872
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2
873
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
874
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1
875
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
876
  // Convert__GPR64AsmReg1_1__GPR64AsmReg1_2
877
  { CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },
878
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3
879
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_, 4, CVT_Done },
880
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3
881
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
882
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3
883
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
884
  // Convert__regZERO
885
  { CVT_regZERO, 0, CVT_Done },
886
  // Convert__GPR32AsmReg1_0
887
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
888
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1
889
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addImmOperands, 4, CVT_Tied, Tie0_1_1, CVT_Done },
890
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1
891
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
892
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1
893
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
894
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1
895
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
896
  // Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1
897
  { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
898
  // Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1
899
  { CVT_95_addGPR32ZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
900
  // Convert__Reg1_1__Reg1_2
901
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
902
  // Convert__GPR32AsmReg1_1__GPR32AsmReg1_2
903
  { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
904
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2
905
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
906
  // Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
907
  { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
908
  // Convert__GPR64AsmReg1_0__Imm1_1
909
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
910
  // Convert__GPR64AsmReg1_0__Mem2_1
911
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
912
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3
913
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
914
  // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0
915
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
916
  // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2
917
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
918
  // Convert__GPR64AsmReg1_0__FGR64AsmReg1_1
919
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
920
  // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0
921
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
922
  // Convert__GPR64AsmReg1_0__UImm161_1
923
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
924
  // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2
925
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
926
  // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0
927
  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
928
  // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2
929
  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
930
  // Convert__FGR64AsmReg1_1__GPR64AsmReg1_0
931
  { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
932
  // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0
933
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
934
  // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2
935
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
936
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2
937
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
938
  // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0
939
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
940
  // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1
941
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
942
  // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
943
  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
944
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0
945
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
946
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1
947
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
948
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1
949
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 2, CVT_Done },
950
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2
951
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
952
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1
953
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done },
954
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2
955
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
956
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2
957
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
958
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1
959
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
960
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1
961
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
962
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2
963
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
964
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3
965
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
966
  // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2
967
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
968
  // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2
969
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
970
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1
971
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_Done },
972
  // Convert__MSA128AsmReg1_0__GPR32AsmReg1_1
973
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
974
  // Convert__MSA128AsmReg1_0__GPR64AsmReg1_1
975
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
976
  // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2
977
  { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
978
  // Convert__GPR32AsmReg1_0__ConstantUImm2_01_1
979
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 2, CVT_Done },
980
  // Convert__imm_95_0
981
  { CVT_imm_95_0, 0, CVT_Done },
982
  // Convert__ConstantUImm10_01_0
983
  { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_Done },
984
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1
985
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
986
  // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2
987
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
988
  // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2
989
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR64AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_Done },
990
  // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2
991
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
992
  // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2
993
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Done },
994
  // Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1
995
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
996
  // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6
997
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
998
  // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6
999
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
1000
  // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6
1001
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
1002
  // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6
1003
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
1004
  // Convert__regRA__GPR32AsmReg1_0
1005
  { CVT_regRA, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1006
  // Convert__regRA_64__GPR64AsmReg1_0
1007
  { CVT_regRA_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1008
  // Convert__Reg1_0
1009
  { CVT_95_Reg, 1, CVT_Done },
1010
  // Convert__GPR32AsmReg1_0__imm_95_0
1011
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1012
  // Convert__GPR64AsmReg1_0__imm_95_0
1013
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1014
  // Convert__regZERO__GPR32AsmReg1_0
1015
  { CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1016
  // Convert__GPR64AsmReg1_0
1017
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1018
  // Convert__regZERO_64__GPR64AsmReg1_0
1019
  { CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1020
  // Convert__UImm5Lsl21_0
1021
  { CVT_95_addImmOperands, 1, CVT_Done },
1022
  // Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1
1023
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1024
  // Convert__FGR64AsmReg1_0__MemOffsetSimm162_1
1025
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1026
  // Convert__FGR32AsmReg1_0__MemOffsetSimm162_1
1027
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1028
  // Convert__GPR32AsmReg1_0__Imm1_1
1029
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1030
  // Convert__GPR32AsmReg1_0__Mem2_1
1031
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1032
  // Convert__GPR32AsmReg1_0__MemOffsetSimm162_1
1033
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1034
  // Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1
1035
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1036
  // Convert__GPR32AsmReg1_0__MemOffsetSimm92_1
1037
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1038
  // Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1
1039
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done },
1040
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1041
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1042
  // Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1
1043
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1044
  // Convert__MSA128AsmReg1_0__MemOffsetSimm102_1
1045
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1046
  // Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1
1047
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1048
  // Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1
1049
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1050
  // Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1
1051
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1052
  // Convert__COP2AsmReg1_0__MemOffsetSimm112_1
1053
  { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1054
  // Convert__COP2AsmReg1_0__MemOffsetSimm162_1
1055
  { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1056
  // Convert__COP3AsmReg1_0__Mem2_1
1057
  { CVT_95_addCOP3AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1058
  // Convert__MSA128AsmReg1_0__ConstantSImm10_01_1
1059
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1060
  // Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1
1061
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1062
  // Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1063
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1064
  // Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1065
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1066
  // Convert__GPR32AsmReg1_0__UImm32_Coerced1_1
1067
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_32_GT_, 2, CVT_Done },
1068
  // Convert__StrictlyAFGR64AsmReg1_0__Imm1_1
1069
  { CVT_95_addStrictlyAFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1070
  // Convert__StrictlyFGR64AsmReg1_0__Imm1_1
1071
  { CVT_95_addStrictlyFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1072
  // Convert__StrictlyFGR32AsmReg1_0__Imm1_1
1073
  { CVT_95_addStrictlyFGR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1074
  // Convert__GPRMM16AsmReg1_0__UImm7_N11_1
1075
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_, 2, CVT_Done },
1076
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3
1077
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
1078
  // Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3
1079
  { CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
1080
  // Convert__GPR32AsmReg1_0__UImm161_1
1081
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
1082
  // Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1
1083
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
1084
  // Convert__Reg1_0__Imm1_1__imm_95_0
1085
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1086
  // Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1
1087
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1088
  // Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1
1089
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1090
  // Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1
1091
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1092
  // Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1
1093
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1094
  // Convert__RegList1_0__Mem2_1
1095
  { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1096
  // Convert__RegList161_0__MemOffsetUimm42_1
1097
  { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1098
  // ConvertCustom_ConvertXWPOperands
1099
  { CVT_ConvertXWPOperands, 0, CVT_Done },
1100
  // Convert__GPR32AsmReg1_0__MemOffsetSimm122_1
1101
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1102
  // Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1103
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1104
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3
1105
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_95_addAFGR64AsmRegOperands, 4, CVT_Done },
1106
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3
1107
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_95_addFGR64AsmRegOperands, 4, CVT_Done },
1108
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3
1109
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 4, CVT_Done },
1110
  // Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2
1111
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
1112
  // Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2
1113
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
1114
  // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0
1115
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1116
  // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2
1117
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1118
  // Convert__GPR32AsmReg1_0__FGR64AsmReg1_1
1119
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
1120
  // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0
1121
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1122
  // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2
1123
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1124
  // Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1
1125
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
1126
  // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1
1127
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_Done },
1128
  // Convert__GPR32AsmReg1_0__regAC0
1129
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regAC0, 0, CVT_Done },
1130
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0
1131
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1132
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4
1133
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done },
1134
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO
1135
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_regZERO, 0, CVT_Done },
1136
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64
1137
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_regZERO_64, 0, CVT_Done },
1138
  // Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3
1139
  { CVT_95_addGPRMM16AsmRegMovePPairFirstOperands, 1, CVT_95_addGPRMM16AsmRegMovePPairSecondOperands, 2, CVT_95_addGPRMM16AsmRegMovePOperands, 3, CVT_95_addGPRMM16AsmRegMovePOperands, 4, CVT_Done },
1140
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1141
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1142
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1143
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1144
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1145
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1146
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1147
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1148
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1149
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1150
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1151
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1152
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1153
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1154
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1155
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1156
  // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0
1157
  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1158
  // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2
1159
  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1160
  // Convert__FGR64AsmReg1_1__GPR32AsmReg1_0
1161
  { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1162
  // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0
1163
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1164
  // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2
1165
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1166
  // Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0
1167
  { CVT_95_addAFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1168
  // Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0
1169
  { CVT_95_addFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1170
  // Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0
1171
  { CVT_95_addHI32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1172
  // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1
1173
  { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_Done },
1174
  // Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0
1175
  { CVT_95_addLO32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1176
  // Convert__regAC0__GPR32AsmReg1_0
1177
  { CVT_regAC0, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1178
  // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0
1179
  { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1180
  // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0
1181
  { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1182
  // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4
1183
  { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done },
1184
  // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
1185
  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1186
  // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0
1187
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1188
  // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1
1189
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1190
  // Convert__regZERO__regZERO__imm_95_0
1191
  { CVT_regZERO, 0, CVT_regZERO, 0, CVT_imm_95_0, 0, CVT_Done },
1192
  // Convert__regZERO__regS0
1193
  { CVT_regZERO, 0, CVT_regS0, 0, CVT_Done },
1194
  // Convert__regZERO__regZERO
1195
  { CVT_regZERO, 0, CVT_regZERO, 0, CVT_Done },
1196
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO
1197
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_Done },
1198
  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1
1199
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Done },
1200
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0
1201
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1202
  // Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0
1203
  { CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
1204
  // Convert__GPR32AsmReg1_0__ConstantUImm7_01_1
1205
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_, 2, CVT_Done },
1206
  // Convert__GPR32AsmReg1_0__ConstantUImm10_01_1
1207
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1208
  // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0
1209
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1210
  // Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0
1211
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1212
  // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2
1213
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1214
  // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2
1215
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
1216
  // Convert__GPR32AsmReg1_0__ConstantSImm10_01_1
1217
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1218
  // Convert__GPR32AsmReg1_0__ConstantUImm8_01_1
1219
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 2, CVT_Done },
1220
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1
1221
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done },
1222
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2
1223
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
1224
  // Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1
1225
  { CVT_95_addGPRMM16AsmRegZeroOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done },
1226
  // Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1
1227
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
1228
  // Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1
1229
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
1230
  // Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1
1231
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
1232
  // Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1
1233
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
1234
  // Convert__ConstantUImm20_01_0
1235
  { CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_, 1, CVT_Done },
1236
  // Convert__Reg1_0__Tie0_1_1
1237
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done },
1238
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1
1239
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1240
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2
1241
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done },
1242
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0
1243
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1244
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1
1245
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1246
  // Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1
1247
  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1248
  // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1
1249
  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1250
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2
1251
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
1252
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2
1253
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1254
  // Convert__UImm161_0
1255
  { CVT_95_addUImmOperands_LT_16_GT_, 1, CVT_Done },
1256
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3
1257
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done },
1258
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3
1259
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
1260
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3
1261
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
1262
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3
1263
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
1264
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3
1265
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
1266
  // Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2
1267
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
1268
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3
1269
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done },
1270
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3
1271
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
1272
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3
1273
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
1274
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3
1275
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
1276
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3
1277
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
1278
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1
1279
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1280
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2
1281
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1282
  // Convert__ConstantUImm5_01_0
1283
  { CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
1284
  // Convert__MemOffsetSimm162_0
1285
  { CVT_95_addMemOperands, 1, CVT_Done },
1286
  // Convert__imm_95_2
1287
  { CVT_imm_95_2, 0, CVT_Done },
1288
  // Convert__imm_95_6
1289
  { CVT_imm_95_6, 0, CVT_Done },
1290
  // Convert__imm_95_4
1291
  { CVT_imm_95_4, 0, CVT_Done },
1292
  // Convert__imm_95_5
1293
  { CVT_imm_95_5, 0, CVT_Done },
1294
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2
1295
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done },
1296
  // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2
1297
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1298
  // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2
1299
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1300
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2
1301
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1302
  // Convert__GPR32AsmReg1_0__imm_95_31
1303
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_31, 0, CVT_Done },
1304
};
1305
1306
void MipsAsmParser::
1307
convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
1308
36.2k
                const OperandVector &Operands) {
1309
36.2k
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
1310
36.2k
  const uint8_t *Converter = ConversionTable[Kind];
1311
36.2k
  unsigned OpIdx;
1312
36.2k
  Inst.setOpcode(Opcode);
1313
126k
  for (const uint8_t *p = Converter; *p; 
p+= 290.1k
) {
1314
90.1k
    OpIdx = *(p + 1);
1315
90.1k
    switch (*p) {
1316
90.1k
    
default: 0
llvm_unreachable0
("invalid conversion entry!");
1317
90.1k
    case CVT_Reg:
1318
0
      static_cast<MipsOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
1319
0
      break;
1320
90.1k
    case CVT_Tied: {
1321
627
      assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
1322
627
                          std::begin(TiedAsmOperandTable)) &&
1323
627
             "Tied operand not found");
1324
627
      unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];
1325
627
      if (TiedResOpnd != (uint8_t) -1)
1326
627
        Inst.addOperand(Inst.getOperand(TiedResOpnd));
1327
627
      break;
1328
90.1k
    }
1329
90.1k
    case CVT_95_addGPR32AsmRegOperands:
1330
24.1k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32AsmRegOperands(Inst, 1);
1331
24.1k
      break;
1332
90.1k
    case CVT_95_addAFGR64AsmRegOperands:
1333
925
      static_cast<MipsOperand&>(*Operands[OpIdx]).addAFGR64AsmRegOperands(Inst, 1);
1334
925
      break;
1335
90.1k
    case CVT_95_addFGR64AsmRegOperands:
1336
1.30k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addFGR64AsmRegOperands(Inst, 1);
1337
1.30k
      break;
1338
90.1k
    case CVT_95_addFGR32AsmRegOperands:
1339
2.55k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addFGR32AsmRegOperands(Inst, 1);
1340
2.55k
      break;
1341
90.1k
    case CVT_95_addSImmOperands_LT_32_GT_:
1342
636
      static_cast<MipsOperand&>(*Operands[OpIdx]).addSImmOperands<32>(Inst, 1);
1343
636
      break;
1344
90.1k
    case CVT_95_addMSA128AsmRegOperands:
1345
1.40k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addMSA128AsmRegOperands(Inst, 1);
1346
1.40k
      break;
1347
90.1k
    case CVT_95_addSImmOperands_LT_16_GT_:
1348
1.34k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addSImmOperands<16>(Inst, 1);
1349
1.34k
      break;
1350
90.1k
    case CVT_95_Reg:
1351
0
      static_cast<MipsOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
1352
0
      break;
1353
90.1k
    case CVT_95_addImmOperands:
1354
3.56k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
1355
3.56k
      break;
1356
90.1k
    case CVT_95_addGPRMM16AsmRegOperands:
1357
178
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegOperands(Inst, 1);
1358
178
      break;
1359
90.1k
    case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_:
1360
4
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<4, 0>(Inst, 1);
1361
4
      break;
1362
90.1k
    case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_:
1363
475
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 0>(Inst, 1);
1364
475
      break;
1365
90.1k
    case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_:
1366
14
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<2, 0>(Inst, 1);
1367
14
      break;
1368
90.1k
    case CVT_95_addUImmOperands_LT_16_GT_:
1369
236
      static_cast<MipsOperand&>(*Operands[OpIdx]).addUImmOperands<16>(Inst, 1);
1370
236
      break;
1371
90.1k
    case CVT_95_addGPR64AsmRegOperands:
1372
3.96k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR64AsmRegOperands(Inst, 1);
1373
3.96k
      break;
1374
90.1k
    case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_:
1375
15
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<8, 0>(Inst, 1);
1376
15
      break;
1377
90.1k
    case CVT_regZERO:
1378
21.9k
      Inst.addOperand(MCOperand::createReg(Mips::ZERO));
1379
21.9k
      break;
1380
90.1k
    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_:
1381
6
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 32, -32>(Inst, 1);
1382
6
      break;
1383
90.1k
    case CVT_regFCC0:
1384
282
      Inst.addOperand(MCOperand::createReg(Mips::FCC0));
1385
282
      break;
1386
90.1k
    case CVT_95_addFCCAsmRegOperands:
1387
734
      static_cast<MipsOperand&>(*Operands[OpIdx]).addFCCAsmRegOperands(Inst, 1);
1388
734
      break;
1389
90.1k
    case CVT_95_addCOP2AsmRegOperands:
1390
122
      static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP2AsmRegOperands(Inst, 1);
1391
122
      break;
1392
90.1k
    case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_:
1393
155
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<3, 0>(Inst, 1);
1394
155
      break;
1395
90.1k
    case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_:
1396
76
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<6, 0>(Inst, 1);
1397
76
      break;
1398
90.1k
    case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_:
1399
62
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<4, 0>(Inst, 1);
1400
62
      break;
1401
90.1k
    case CVT_imm_95_0:
1402
11.1k
      Inst.addOperand(MCOperand::createImm(0));
1403
11.1k
      break;
1404
90.1k
    case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_:
1405
132
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<10, 0>(Inst, 1);
1406
132
      break;
1407
90.1k
    case CVT_95_addMemOperands:
1408
12.6k
      static_cast<MipsOperand&>(*Operands[OpIdx]).addMemOperands(Inst, 2);
1409
12.6k
      break;
1410
90.1k
    case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_:
1411
20
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<5, 0>(Inst, 1);
1412
20
      break;
1413
90.1k
    case CVT_95_addCCRAsmRegOperands:
1414
38
      static_cast<MipsOperand&>(*Operands[OpIdx]).addCCRAsmRegOperands(Inst, 1);
1415
38
      break;
1416
90.1k
    case CVT_95_addMSACtrlAsmRegOperands:
1417
32
      static_cast<MipsOperand&>(*Operands[OpIdx]).addMSACtrlAsmRegOperands(Inst, 1);
1418
32
      break;
1419
90.1k
    case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_:
1420
53
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<1, 0>(Inst, 1);
1421
53
      break;
1422
90.1k
    case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_:
1423
10
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 33>(Inst, 1);
1424
10
      break;
1425
90.1k
    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_:
1426
20
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 32>(Inst, 1);
1427
20
      break;
1428
90.1k
    case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_:
1429
42
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 1>(Inst, 1);
1430
42
      break;
1431
90.1k
    case CVT_95_addGPR32NonZeroAsmRegOperands:
1432
50
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32NonZeroAsmRegOperands(Inst, 1);
1433
50
      break;
1434
90.1k
    case CVT_95_addGPR32ZeroAsmRegOperands:
1435
16
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32ZeroAsmRegOperands(Inst, 1);
1436
16
      break;
1437
90.1k
    case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_:
1438
12
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<2, 1>(Inst, 1);
1439
12
      break;
1440
90.1k
    case CVT_95_addCOP0AsmRegOperands:
1441
116
      static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP0AsmRegOperands(Inst, 1);
1442
116
      break;
1443
90.1k
    case CVT_regZERO_64:
1444
87
      Inst.addOperand(MCOperand::createReg(Mips::ZERO_64));
1445
87
      break;
1446
90.1k
    case CVT_95_addACC64DSPAsmRegOperands:
1447
180
      static_cast<MipsOperand&>(*Operands[OpIdx]).addACC64DSPAsmRegOperands(Inst, 1);
1448
180
      break;
1449
90.1k
    case CVT_95_addConstantUImmOperands_LT_1_GT_:
1450
4
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<1>(Inst, 1);
1451
4
      break;
1452
90.1k
    case CVT_regRA:
1453
40
      Inst.addOperand(MCOperand::createReg(Mips::RA));
1454
40
      break;
1455
90.1k
    case CVT_regRA_64:
1456
5
      Inst.addOperand(MCOperand::createReg(Mips::RA_64));
1457
5
      break;
1458
90.1k
    case CVT_95_addMicroMipsMemOperands:
1459
50
      static_cast<MipsOperand&>(*Operands[OpIdx]).addMicroMipsMemOperands(Inst, 2);
1460
50
      break;
1461
90.1k
    case CVT_95_addCOP3AsmRegOperands:
1462
6
      static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP3AsmRegOperands(Inst, 1);
1463
6
      break;
1464
90.1k
    case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_:
1465
12
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<10, 0>(Inst, 1);
1466
12
      break;
1467
90.1k
    case CVT_95_addConstantUImmOperands_LT_32_GT_:
1468
206
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<32>(Inst, 1);
1469
206
      break;
1470
90.1k
    case CVT_95_addStrictlyAFGR64AsmRegOperands:
1471
39
      static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyAFGR64AsmRegOperands(Inst, 1);
1472
39
      break;
1473
90.1k
    case CVT_95_addStrictlyFGR64AsmRegOperands:
1474
52
      static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyFGR64AsmRegOperands(Inst, 1);
1475
52
      break;
1476
90.1k
    case CVT_95_addStrictlyFGR32AsmRegOperands:
1477
66
      static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyFGR32AsmRegOperands(Inst, 1);
1478
66
      break;
1479
90.1k
    case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_:
1480
7
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<7, -1>(Inst, 1);
1481
7
      break;
1482
90.1k
    case CVT_95_addRegListOperands:
1483
63
      static_cast<MipsOperand&>(*Operands[OpIdx]).addRegListOperands(Inst, 1);
1484
63
      break;
1485
90.1k
    case CVT_ConvertXWPOperands:
1486
14
      ConvertXWPOperands(Inst, Operands);
1487
14
      break;
1488
90.1k
    case CVT_regAC0:
1489
4
      Inst.addOperand(MCOperand::createReg(Mips::AC0));
1490
4
      break;
1491
90.1k
    case CVT_95_addGPRMM16AsmRegMovePPairFirstOperands:
1492
6
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegMovePPairFirstOperands(Inst, 1);
1493
6
      break;
1494
90.1k
    case CVT_95_addGPRMM16AsmRegMovePPairSecondOperands:
1495
6
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegMovePPairSecondOperands(Inst, 1);
1496
6
      break;
1497
90.1k
    case CVT_95_addGPRMM16AsmRegMovePOperands:
1498
12
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegMovePOperands(Inst, 1);
1499
12
      break;
1500
90.1k
    case CVT_95_addHI32DSPAsmRegOperands:
1501
3
      static_cast<MipsOperand&>(*Operands[OpIdx]).addHI32DSPAsmRegOperands(Inst, 1);
1502
3
      break;
1503
90.1k
    case CVT_95_addLO32DSPAsmRegOperands:
1504
3
      static_cast<MipsOperand&>(*Operands[OpIdx]).addLO32DSPAsmRegOperands(Inst, 1);
1505
3
      break;
1506
90.1k
    case CVT_regS0:
1507
2
      Inst.addOperand(MCOperand::createReg(Mips::S0));
1508
2
      break;
1509
90.1k
    case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_:
1510
5
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<7, 0>(Inst, 1);
1511
5
      break;
1512
90.1k
    case CVT_95_addHWRegsAsmRegOperands:
1513
60
      static_cast<MipsOperand&>(*Operands[OpIdx]).addHWRegsAsmRegOperands(Inst, 1);
1514
60
      break;
1515
90.1k
    case CVT_95_addGPRMM16AsmRegZeroOperands:
1516
22
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegZeroOperands(Inst, 1);
1517
22
      break;
1518
90.1k
    case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_:
1519
25
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<20, 0>(Inst, 1);
1520
25
      break;
1521
90.1k
    case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_:
1522
6
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<6, 0>(Inst, 1);
1523
6
      break;
1524
90.1k
    case CVT_imm_95_2:
1525
1
      Inst.addOperand(MCOperand::createImm(2));
1526
1
      break;
1527
90.1k
    case CVT_imm_95_6:
1528
1
      Inst.addOperand(MCOperand::createImm(6));
1529
1
      break;
1530
90.1k
    case CVT_imm_95_4:
1531
1
      Inst.addOperand(MCOperand::createImm(4));
1532
1
      break;
1533
90.1k
    case CVT_imm_95_5:
1534
1
      Inst.addOperand(MCOperand::createImm(5));
1535
1
      break;
1536
90.1k
    case CVT_imm_95_31:
1537
4
      Inst.addOperand(MCOperand::createImm(31));
1538
4
      break;
1539
90.1k
    }
1540
90.1k
  }
1541
36.2k
}
1542
1543
void MipsAsmParser::
1544
convertToMapAndConstraints(unsigned Kind,
1545
0
                           const OperandVector &Operands) {
1546
0
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
1547
0
  unsigned NumMCOperands = 0;
1548
0
  const uint8_t *Converter = ConversionTable[Kind];
1549
0
  for (const uint8_t *p = Converter; *p; p+= 2) {
1550
0
    switch (*p) {
1551
0
    default: llvm_unreachable("invalid conversion entry!");
1552
0
    case CVT_Reg:
1553
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1554
0
      Operands[*(p + 1)]->setConstraint("r");
1555
0
      ++NumMCOperands;
1556
0
      break;
1557
0
    case CVT_Tied:
1558
0
      ++NumMCOperands;
1559
0
      break;
1560
0
    case CVT_95_addGPR32AsmRegOperands:
1561
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1562
0
      Operands[*(p + 1)]->setConstraint("m");
1563
0
      NumMCOperands += 1;
1564
0
      break;
1565
0
    case CVT_95_addAFGR64AsmRegOperands:
1566
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1567
0
      Operands[*(p + 1)]->setConstraint("m");
1568
0
      NumMCOperands += 1;
1569
0
      break;
1570
0
    case CVT_95_addFGR64AsmRegOperands:
1571
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1572
0
      Operands[*(p + 1)]->setConstraint("m");
1573
0
      NumMCOperands += 1;
1574
0
      break;
1575
0
    case CVT_95_addFGR32AsmRegOperands:
1576
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1577
0
      Operands[*(p + 1)]->setConstraint("m");
1578
0
      NumMCOperands += 1;
1579
0
      break;
1580
0
    case CVT_95_addSImmOperands_LT_32_GT_:
1581
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1582
0
      Operands[*(p + 1)]->setConstraint("m");
1583
0
      NumMCOperands += 1;
1584
0
      break;
1585
0
    case CVT_95_addMSA128AsmRegOperands:
1586
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1587
0
      Operands[*(p + 1)]->setConstraint("m");
1588
0
      NumMCOperands += 1;
1589
0
      break;
1590
0
    case CVT_95_addSImmOperands_LT_16_GT_:
1591
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1592
0
      Operands[*(p + 1)]->setConstraint("m");
1593
0
      NumMCOperands += 1;
1594
0
      break;
1595
0
    case CVT_95_Reg:
1596
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1597
0
      Operands[*(p + 1)]->setConstraint("r");
1598
0
      NumMCOperands += 1;
1599
0
      break;
1600
0
    case CVT_95_addImmOperands:
1601
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1602
0
      Operands[*(p + 1)]->setConstraint("m");
1603
0
      NumMCOperands += 1;
1604
0
      break;
1605
0
    case CVT_95_addGPRMM16AsmRegOperands:
1606
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1607
0
      Operands[*(p + 1)]->setConstraint("m");
1608
0
      NumMCOperands += 1;
1609
0
      break;
1610
0
    case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_:
1611
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1612
0
      Operands[*(p + 1)]->setConstraint("m");
1613
0
      NumMCOperands += 1;
1614
0
      break;
1615
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_:
1616
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1617
0
      Operands[*(p + 1)]->setConstraint("m");
1618
0
      NumMCOperands += 1;
1619
0
      break;
1620
0
    case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_:
1621
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1622
0
      Operands[*(p + 1)]->setConstraint("m");
1623
0
      NumMCOperands += 1;
1624
0
      break;
1625
0
    case CVT_95_addUImmOperands_LT_16_GT_:
1626
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1627
0
      Operands[*(p + 1)]->setConstraint("m");
1628
0
      NumMCOperands += 1;
1629
0
      break;
1630
0
    case CVT_95_addGPR64AsmRegOperands:
1631
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1632
0
      Operands[*(p + 1)]->setConstraint("m");
1633
0
      NumMCOperands += 1;
1634
0
      break;
1635
0
    case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_:
1636
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1637
0
      Operands[*(p + 1)]->setConstraint("m");
1638
0
      NumMCOperands += 1;
1639
0
      break;
1640
0
    case CVT_regZERO:
1641
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1642
0
      Operands[*(p + 1)]->setConstraint("m");
1643
0
      ++NumMCOperands;
1644
0
      break;
1645
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_:
1646
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1647
0
      Operands[*(p + 1)]->setConstraint("m");
1648
0
      NumMCOperands += 1;
1649
0
      break;
1650
0
    case CVT_regFCC0:
1651
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1652
0
      Operands[*(p + 1)]->setConstraint("m");
1653
0
      ++NumMCOperands;
1654
0
      break;
1655
0
    case CVT_95_addFCCAsmRegOperands:
1656
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1657
0
      Operands[*(p + 1)]->setConstraint("m");
1658
0
      NumMCOperands += 1;
1659
0
      break;
1660
0
    case CVT_95_addCOP2AsmRegOperands:
1661
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1662
0
      Operands[*(p + 1)]->setConstraint("m");
1663
0
      NumMCOperands += 1;
1664
0
      break;
1665
0
    case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_:
1666
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1667
0
      Operands[*(p + 1)]->setConstraint("m");
1668
0
      NumMCOperands += 1;
1669
0
      break;
1670
0
    case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_:
1671
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1672
0
      Operands[*(p + 1)]->setConstraint("m");
1673
0
      NumMCOperands += 1;
1674
0
      break;
1675
0
    case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_:
1676
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1677
0
      Operands[*(p + 1)]->setConstraint("m");
1678
0
      NumMCOperands += 1;
1679
0
      break;
1680
0
    case CVT_imm_95_0:
1681
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1682
0
      Operands[*(p + 1)]->setConstraint("");
1683
0
      ++NumMCOperands;
1684
0
      break;
1685
0
    case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_:
1686
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1687
0
      Operands[*(p + 1)]->setConstraint("m");
1688
0
      NumMCOperands += 1;
1689
0
      break;
1690
0
    case CVT_95_addMemOperands:
1691
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1692
0
      Operands[*(p + 1)]->setConstraint("m");
1693
0
      NumMCOperands += 2;
1694
0
      break;
1695
0
    case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_:
1696
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1697
0
      Operands[*(p + 1)]->setConstraint("m");
1698
0
      NumMCOperands += 1;
1699
0
      break;
1700
0
    case CVT_95_addCCRAsmRegOperands:
1701
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1702
0
      Operands[*(p + 1)]->setConstraint("m");
1703
0
      NumMCOperands += 1;
1704
0
      break;
1705
0
    case CVT_95_addMSACtrlAsmRegOperands:
1706
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1707
0
      Operands[*(p + 1)]->setConstraint("m");
1708
0
      NumMCOperands += 1;
1709
0
      break;
1710
0
    case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_:
1711
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1712
0
      Operands[*(p + 1)]->setConstraint("m");
1713
0
      NumMCOperands += 1;
1714
0
      break;
1715
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_:
1716
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1717
0
      Operands[*(p + 1)]->setConstraint("m");
1718
0
      NumMCOperands += 1;
1719
0
      break;
1720
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_:
1721
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1722
0
      Operands[*(p + 1)]->setConstraint("m");
1723
0
      NumMCOperands += 1;
1724
0
      break;
1725
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_:
1726
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1727
0
      Operands[*(p + 1)]->setConstraint("m");
1728
0
      NumMCOperands += 1;
1729
0
      break;
1730
0
    case CVT_95_addGPR32NonZeroAsmRegOperands:
1731
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1732
0
      Operands[*(p + 1)]->setConstraint("m");
1733
0
      NumMCOperands += 1;
1734
0
      break;
1735
0
    case CVT_95_addGPR32ZeroAsmRegOperands:
1736
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1737
0
      Operands[*(p + 1)]->setConstraint("m");
1738
0
      NumMCOperands += 1;
1739
0
      break;
1740
0
    case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_:
1741
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1742
0
      Operands[*(p + 1)]->setConstraint("m");
1743
0
      NumMCOperands += 1;
1744
0
      break;
1745
0
    case CVT_95_addCOP0AsmRegOperands:
1746
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1747
0
      Operands[*(p + 1)]->setConstraint("m");
1748
0
      NumMCOperands += 1;
1749
0
      break;
1750
0
    case CVT_regZERO_64:
1751
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1752
0
      Operands[*(p + 1)]->setConstraint("m");
1753
0
      ++NumMCOperands;
1754
0
      break;
1755
0
    case CVT_95_addACC64DSPAsmRegOperands:
1756
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1757
0
      Operands[*(p + 1)]->setConstraint("m");
1758
0
      NumMCOperands += 1;
1759
0
      break;
1760
0
    case CVT_95_addConstantUImmOperands_LT_1_GT_:
1761
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1762
0
      Operands[*(p + 1)]->setConstraint("m");
1763
0
      NumMCOperands += 1;
1764
0
      break;
1765
0
    case CVT_regRA:
1766
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1767
0
      Operands[*(p + 1)]->setConstraint("m");
1768
0
      ++NumMCOperands;
1769
0
      break;
1770
0
    case CVT_regRA_64:
1771
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1772
0
      Operands[*(p + 1)]->setConstraint("m");
1773
0
      ++NumMCOperands;
1774
0
      break;
1775
0
    case CVT_95_addMicroMipsMemOperands:
1776
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1777
0
      Operands[*(p + 1)]->setConstraint("m");
1778
0
      NumMCOperands += 2;
1779
0
      break;
1780
0
    case CVT_95_addCOP3AsmRegOperands:
1781
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1782
0
      Operands[*(p + 1)]->setConstraint("m");
1783
0
      NumMCOperands += 1;
1784
0
      break;
1785
0
    case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_:
1786
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1787
0
      Operands[*(p + 1)]->setConstraint("m");
1788
0
      NumMCOperands += 1;
1789
0
      break;
1790
0
    case CVT_95_addConstantUImmOperands_LT_32_GT_:
1791
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1792
0
      Operands[*(p + 1)]->setConstraint("m");
1793
0
      NumMCOperands += 1;
1794
0
      break;
1795
0
    case CVT_95_addStrictlyAFGR64AsmRegOperands:
1796
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1797
0
      Operands[*(p + 1)]->setConstraint("m");
1798
0
      NumMCOperands += 1;
1799
0
      break;
1800
0
    case CVT_95_addStrictlyFGR64AsmRegOperands:
1801
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1802
0
      Operands[*(p + 1)]->setConstraint("m");
1803
0
      NumMCOperands += 1;
1804
0
      break;
1805
0
    case CVT_95_addStrictlyFGR32AsmRegOperands:
1806
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1807
0
      Operands[*(p + 1)]->setConstraint("m");
1808
0
      NumMCOperands += 1;
1809
0
      break;
1810
0
    case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_:
1811
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1812
0
      Operands[*(p + 1)]->setConstraint("m");
1813
0
      NumMCOperands += 1;
1814
0
      break;
1815
0
    case CVT_95_addRegListOperands:
1816
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1817
0
      Operands[*(p + 1)]->setConstraint("m");
1818
0
      NumMCOperands += 1;
1819
0
      break;
1820
0
    case CVT_regAC0:
1821
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1822
0
      Operands[*(p + 1)]->setConstraint("m");
1823
0
      ++NumMCOperands;
1824
0
      break;
1825
0
    case CVT_95_addGPRMM16AsmRegMovePPairFirstOperands:
1826
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1827
0
      Operands[*(p + 1)]->setConstraint("m");
1828
0
      NumMCOperands += 1;
1829
0
      break;
1830
0
    case CVT_95_addGPRMM16AsmRegMovePPairSecondOperands:
1831
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1832
0
      Operands[*(p + 1)]->setConstraint("m");
1833
0
      NumMCOperands += 1;
1834
0
      break;
1835
0
    case CVT_95_addGPRMM16AsmRegMovePOperands:
1836
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1837
0
      Operands[*(p + 1)]->setConstraint("m");
1838
0
      NumMCOperands += 1;
1839
0
      break;
1840
0
    case CVT_95_addHI32DSPAsmRegOperands:
1841
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1842
0
      Operands[*(p + 1)]->setConstraint("m");
1843
0
      NumMCOperands += 1;
1844
0
      break;
1845
0
    case CVT_95_addLO32DSPAsmRegOperands:
1846
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1847
0
      Operands[*(p + 1)]->setConstraint("m");
1848
0
      NumMCOperands += 1;
1849
0
      break;
1850
0
    case CVT_regS0:
1851
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1852
0
      Operands[*(p + 1)]->setConstraint("m");
1853
0
      ++NumMCOperands;
1854
0
      break;
1855
0
    case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_:
1856
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1857
0
      Operands[*(p + 1)]->setConstraint("m");
1858
0
      NumMCOperands += 1;
1859
0
      break;
1860
0
    case CVT_95_addHWRegsAsmRegOperands:
1861
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1862
0
      Operands[*(p + 1)]->setConstraint("m");
1863
0
      NumMCOperands += 1;
1864
0
      break;
1865
0
    case CVT_95_addGPRMM16AsmRegZeroOperands:
1866
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1867
0
      Operands[*(p + 1)]->setConstraint("m");
1868
0
      NumMCOperands += 1;
1869
0
      break;
1870
0
    case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_:
1871
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1872
0
      Operands[*(p + 1)]->setConstraint("m");
1873
0
      NumMCOperands += 1;
1874
0
      break;
1875
0
    case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_:
1876
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1877
0
      Operands[*(p + 1)]->setConstraint("m");
1878
0
      NumMCOperands += 1;
1879
0
      break;
1880
0
    case CVT_imm_95_2:
1881
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1882
0
      Operands[*(p + 1)]->setConstraint("");
1883
0
      ++NumMCOperands;
1884
0
      break;
1885
0
    case CVT_imm_95_6:
1886
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1887
0
      Operands[*(p + 1)]->setConstraint("");
1888
0
      ++NumMCOperands;
1889
0
      break;
1890
0
    case CVT_imm_95_4:
1891
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1892
0
      Operands[*(p + 1)]->setConstraint("");
1893
0
      ++NumMCOperands;
1894
0
      break;
1895
0
    case CVT_imm_95_5:
1896
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1897
0
      Operands[*(p + 1)]->setConstraint("");
1898
0
      ++NumMCOperands;
1899
0
      break;
1900
0
    case CVT_imm_95_31:
1901
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1902
0
      Operands[*(p + 1)]->setConstraint("");
1903
0
      ++NumMCOperands;
1904
0
      break;
1905
0
    }
1906
0
  }
1907
0
}
1908
1909
namespace {
1910
1911
/// MatchClassKind - The kinds of classes which participate in
1912
/// instruction matching.
1913
enum MatchClassKind {
1914
  InvalidMatchClass = 0,
1915
  OptionalMatchClass = 1,
1916
  MCK__35_, // '#'
1917
  MCK__40_, // '('
1918
  MCK__41_, // ')'
1919
  MCK_0, // '0'
1920
  MCK_16, // '16'
1921
  MCK__91_, // '['
1922
  MCK__93_, // ']'
1923
  MCK_bit, // 'bit'
1924
  MCK_inst, // 'inst'
1925
  MCK_LAST_TOKEN = MCK_inst,
1926
  MCK_Reg37, // derived register class
1927
  MCK_Reg19, // derived register class
1928
  MCK_ACC128, // register class 'ACC128'
1929
  MCK_ACC64, // register class 'ACC64'
1930
  MCK_CPURAReg, // register class 'CPURAReg,RA'
1931
  MCK_CPUSPReg, // register class 'CPUSPReg,SP32,SP'
1932
  MCK_DSPCC, // register class 'DSPCC'
1933
  MCK_GP32, // register class 'GP32'
1934
  MCK_GP64, // register class 'GP64'
1935
  MCK_GPR32ZERO, // register class 'GPR32ZERO,ZERO'
1936
  MCK_HI32, // register class 'HI32'
1937
  MCK_HI64, // register class 'HI64'
1938
  MCK_LO32, // register class 'LO32'
1939
  MCK_LO64, // register class 'LO64'
1940
  MCK_PC, // register class 'PC'
1941
  MCK_SP64, // register class 'SP64'
1942
  MCK_Reg32, // derived register class
1943
  MCK_Reg13, // derived register class
1944
  MCK_Reg33, // derived register class
1945
  MCK_Reg31, // derived register class
1946
  MCK_Reg30, // derived register class
1947
  MCK_Reg14, // derived register class
1948
  MCK_Reg11, // derived register class
1949
  MCK_GPRMM16MovePPairFirst, // register class 'GPRMM16MovePPairFirst'
1950
  MCK_OCTEON_MPL, // register class 'OCTEON_MPL'
1951
  MCK_OCTEON_P, // register class 'OCTEON_P'
1952
  MCK_Reg28, // derived register class
1953
  MCK_Reg23, // derived register class
1954
  MCK_Reg9, // derived register class
1955
  MCK_Reg4, // derived register class
1956
  MCK_ACC64DSP, // register class 'ACC64DSP'
1957
  MCK_HI32DSP, // register class 'HI32DSP'
1958
  MCK_LO32DSP, // register class 'LO32DSP'
1959
  MCK_Reg34, // derived register class
1960
  MCK_GPRMM16MovePPairSecond, // register class 'GPRMM16MovePPairSecond'
1961
  MCK_Reg29, // derived register class
1962
  MCK_Reg27, // derived register class
1963
  MCK_Reg10, // derived register class
1964
  MCK_Reg8, // derived register class
1965
  MCK_Reg44, // derived register class
1966
  MCK_Reg25, // derived register class
1967
  MCK_Reg22, // derived register class
1968
  MCK_Reg21, // derived register class
1969
  MCK_CPU16Regs, // register class 'CPU16Regs,GPRMM16'
1970
  MCK_FCC, // register class 'FCC'
1971
  MCK_GPRMM16MoveP, // register class 'GPRMM16MoveP'
1972
  MCK_GPRMM16Zero, // register class 'GPRMM16Zero'
1973
  MCK_MSACtrl, // register class 'MSACtrl'
1974
  MCK_Reg26, // derived register class
1975
  MCK_CPU16RegsPlusSP, // register class 'CPU16RegsPlusSP'
1976
  MCK_Reg50, // derived register class
1977
  MCK_Reg47, // derived register class
1978
  MCK_Reg42, // derived register class
1979
  MCK_Reg39, // derived register class
1980
  MCK_AFGR64, // register class 'AFGR64'
1981
  MCK_MSA128WEvens, // register class 'MSA128WEvens'
1982
  MCK_Reg45, // derived register class
1983
  MCK_Reg24, // derived register class
1984
  MCK_GPR32NONZERO, // register class 'GPR32NONZERO'
1985
  MCK_CCR, // register class 'CCR'
1986
  MCK_COP0, // register class 'COP0'
1987
  MCK_COP2, // register class 'COP2'
1988
  MCK_COP3, // register class 'COP3'
1989
  MCK_DSPR, // register class 'DSPR,GPR32'
1990
  MCK_FGR32, // register class 'FGR32,FGRCC'
1991
  MCK_FGR64, // register class 'FGR64'
1992
  MCK_FGRH32, // register class 'FGRH32'
1993
  MCK_GPR64, // register class 'GPR64'
1994
  MCK_HWRegs, // register class 'HWRegs'
1995
  MCK_MSA128F16, // register class 'MSA128F16,MSA128B,MSA128D,MSA128H,MSA128W'
1996
  MCK_OddSP, // register class 'OddSP'
1997
  MCK_LAST_REGISTER = MCK_OddSP,
1998
  MCK_ACC64DSPAsmReg, // user defined class 'ACC64DSPAsmOperand'
1999
  MCK_AFGR64AsmReg, // user defined class 'AFGR64AsmOperand'
2000
  MCK_CCRAsmReg, // user defined class 'CCRAsmOperand'
2001
  MCK_COP0AsmReg, // user defined class 'COP0AsmOperand'
2002
  MCK_COP2AsmReg, // user defined class 'COP2AsmOperand'
2003
  MCK_COP3AsmReg, // user defined class 'COP3AsmOperand'
2004
  MCK_FCCAsmReg, // user defined class 'FCCRegsAsmOperand'
2005
  MCK_FGR32AsmReg, // user defined class 'FGR32AsmOperand'
2006
  MCK_FGR64AsmReg, // user defined class 'FGR64AsmOperand'
2007
  MCK_FGRH32AsmReg, // user defined class 'FGRH32AsmOperand'
2008
  MCK_GPR32AsmReg, // user defined class 'GPR32AsmOperand'
2009
  MCK_GPR32NonZeroAsmReg, // user defined class 'GPR32NonZeroAsmOperand'
2010
  MCK_GPR32ZeroAsmReg, // user defined class 'GPR32ZeroAsmOperand'
2011
  MCK_GPR64AsmReg, // user defined class 'GPR64AsmOperand'
2012
  MCK_GPRMM16AsmReg, // user defined class 'GPRMM16AsmOperand'
2013
  MCK_GPRMM16AsmRegMoveP, // user defined class 'GPRMM16AsmOperandMoveP'
2014
  MCK_GPRMM16AsmRegMovePPairFirst, // user defined class 'GPRMM16AsmOperandMovePPairFirst'
2015
  MCK_GPRMM16AsmRegMovePPairSecond, // user defined class 'GPRMM16AsmOperandMovePPairSecond'
2016
  MCK_GPRMM16AsmRegZero, // user defined class 'GPRMM16AsmOperandZero'
2017
  MCK_HI32DSPAsmReg, // user defined class 'HI32DSPAsmOperand'
2018
  MCK_HWRegsAsmReg, // user defined class 'HWRegsAsmOperand'
2019
  MCK_Imm, // user defined class 'ImmAsmOperand'
2020
  MCK_LO32DSPAsmReg, // user defined class 'LO32DSPAsmOperand'
2021
  MCK_MSA128AsmReg, // user defined class 'MSA128AsmOperand'
2022
  MCK_MSACtrlAsmReg, // user defined class 'MSACtrlAsmOperand'
2023
  MCK_MicroMipsMemGP, // user defined class 'MicroMipsMemGPAsmOperand'
2024
  MCK_MicroMipsMem, // user defined class 'MicroMipsMemGPRMM16AsmOperand'
2025
  MCK_MicroMipsMemSP, // user defined class 'MicroMipsMemSPAsmOperand'
2026
  MCK_InvNum, // user defined class 'MipsInvertedImmoperand'
2027
  MCK_JumpTarget, // user defined class 'MipsJumpTargetAsmOperand'
2028
  MCK_MemOffsetSimm10, // user defined class 'MipsMemSimm10AsmOperand'
2029
  MCK_MemOffsetSimm10_1, // user defined class 'MipsMemSimm10Lsl1AsmOperand'
2030
  MCK_MemOffsetSimm10_2, // user defined class 'MipsMemSimm10Lsl2AsmOperand'
2031
  MCK_MemOffsetSimm10_3, // user defined class 'MipsMemSimm10Lsl3AsmOperand'
2032
  MCK_MemOffsetSimm11, // user defined class 'MipsMemSimm11AsmOperand'
2033
  MCK_MemOffsetSimm12, // user defined class 'MipsMemSimm12AsmOperand'
2034
  MCK_MemOffsetSimm16, // user defined class 'MipsMemSimm16AsmOperand'
2035
  MCK_MemOffsetSimm9, // user defined class 'MipsMemSimm9AsmOperand'
2036
  MCK_MemOffsetSimmPtr, // user defined class 'MipsMemSimmPtrAsmOperand'
2037
  MCK_MemOffsetUimm4, // user defined class 'MipsMemUimm4AsmOperand'
2038
  MCK_Mem, // user defined class 'MipsMemAsmOperand'
2039
  MCK_RegList16, // user defined class 'RegList16AsmOperand'
2040
  MCK_RegList, // user defined class 'RegListAsmOperand'
2041
  MCK_Simm19_Lsl2, // user defined class 'Simm19Lsl2AsmOperand'
2042
  MCK_StrictlyAFGR64AsmReg, // user defined class 'StrictlyAFGR64AsmOperand'
2043
  MCK_StrictlyFGR32AsmReg, // user defined class 'StrictlyFGR32AsmOperand'
2044
  MCK_StrictlyFGR64AsmReg, // user defined class 'StrictlyFGR64AsmOperand'
2045
  MCK_ConstantImmz, // user defined class 'ConstantImmzAsmOperandClass'
2046
  MCK_ConstantUImm1_0, // user defined class 'ConstantUImm1AsmOperandClass'
2047
  MCK_ConstantUImm2_0, // user defined class 'ConstantUImm2AsmOperandClass'
2048
  MCK_ConstantUImm2_1, // user defined class 'ConstantUImm2Plus1AsmOperandClass'
2049
  MCK_ConstantUImm3_0, // user defined class 'ConstantUImm3AsmOperandClass'
2050
  MCK_ConstantSImm4_0, // user defined class 'ConstantSImm4AsmOperandClass'
2051
  MCK_ConstantUImm4_0, // user defined class 'ConstantUImm4AsmOperandClass'
2052
  MCK_ConstantSImm5_0, // user defined class 'ConstantSImm5AsmOperandClass'
2053
  MCK_ConstantUImm5_0, // user defined class 'ConstantUImm5AsmOperandClass'
2054
  MCK_ConstantUImm5_1, // user defined class 'ConstantUImm5Plus1AsmOperandClass'
2055
  MCK_ConstantUImm5_Plus1_Report_UImm6, // user defined class 'ConstantUImm5Plus1ReportUImm6AsmOperandClass'
2056
  MCK_ConstantUImm5_32_Norm, // user defined class 'ConstantUImm5Plus32NormalizeAsmOperandClass'
2057
  MCK_ConstantUImm5_32, // user defined class 'ConstantUImm5Plus32AsmOperandClass'
2058
  MCK_ConstantUImm5_0_Report_UImm6, // user defined class 'ConstantUImm5ReportUImm6AsmOperandClass'
2059
  MCK_ConstantUImm5_33, // user defined class 'ConstantUImm5Plus33AsmOperandClass'
2060
  MCK_ConstantUImmRange2_64, // user defined class 'ConstantUImm5_Range2_64AsmOperandClass'
2061
  MCK_UImm5Lsl2, // user defined class 'ConstantUImm5Lsl2AsmOperandClass'
2062
  MCK_ConstantSImm6_0, // user defined class 'ConstantSImm6AsmOperandClass'
2063
  MCK_ConstantUImm6_0, // user defined class 'ConstantUImm6AsmOperandClass'
2064
  MCK_UImm6Lsl2, // user defined class 'ConstantUImm6Lsl2AsmOperandClass'
2065
  MCK_ConstantUImm7_0, // user defined class 'ConstantUImm7AsmOperandClass'
2066
  MCK_UImm7_N1, // user defined class 'ConstantUImm7Sub1AsmOperandClass'
2067
  MCK_ConstantUImm8_0, // user defined class 'ConstantUImm8AsmOperandClass'
2068
  MCK_SImm7Lsl2, // user defined class 'ConstantSImm7Lsl2AsmOperandClass'
2069
  MCK_ConstantSImm9_0, // user defined class 'ConstantSImm9AsmOperandClass'
2070
  MCK_ConstantSImm10_0, // user defined class 'ConstantSImm10AsmOperandClass'
2071
  MCK_ConstantUImm10_0, // user defined class 'ConstantUImm10AsmOperandClass'
2072
  MCK_SImm10Lsl1, // user defined class 'ConstantSImm10Lsl1AsmOperandClass'
2073
  MCK_ConstantSImm11_0, // user defined class 'ConstantSImm11AsmOperandClass'
2074
  MCK_SImm10Lsl2, // user defined class 'ConstantSImm10Lsl2AsmOperandClass'
2075
  MCK_SImm10Lsl3, // user defined class 'ConstantSImm10Lsl3AsmOperandClass'
2076
  MCK_SImm16, // user defined class 'SImm16AsmOperandClass'
2077
  MCK_SImm16_Relaxed, // user defined class 'SImm16RelaxedAsmOperandClass'
2078
  MCK_UImm16_AltRelaxed, // user defined class 'UImm16AltRelaxedAsmOperandClass'
2079
  MCK_UImm16, // user defined class 'UImm16AsmOperandClass'
2080
  MCK_SImm19Lsl2, // user defined class 'ConstantSImm19Lsl2AsmOperandClass'
2081
  MCK_UImm16_Relaxed, // user defined class 'UImm16RelaxedAsmOperandClass'
2082
  MCK_ConstantUImm20_0, // user defined class 'ConstantUImm20AsmOperandClass'
2083
  MCK_ConstantUImm26_0, // user defined class 'ConstantUImm26AsmOperandClass'
2084
  MCK_SImm32, // user defined class 'SImm32AsmOperandClass'
2085
  MCK_SImm32_Relaxed, // user defined class 'SImm32RelaxedAsmOperandClass'
2086
  MCK_UImm32_Coerced, // user defined class 'UImm32CoercedAsmOperandClass'
2087
  NumMatchClassKinds
2088
};
2089
2090
}
2091
2092
14.4k
static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
2093
14.4k
  return MCTargetAsmParser::Match_InvalidOperand;
2094
14.4k
}
2095
2096
880
static MatchClassKind matchTokenString(StringRef Name) {
2097
880
  switch (Name.size()) {
2098
880
  
default: break0
;
2099
880
  case 1:  // 6 strings to match.
2100
880
    switch (Name[0]) {
2101
880
    
default: break0
;
2102
880
    case '#':  // 1 string to match.
2103
0
      return MCK__35_;  // "#"
2104
880
    case '(':  // 1 string to match.
2105
363
      return MCK__40_;  // "("
2106
880
    case ')':  // 1 string to match.
2107
363
      return MCK__41_;  // ")"
2108
880
    case '0':  // 1 string to match.
2109
0
      return MCK_0;  // "0"
2110
880
    case '[':  // 1 string to match.
2111
112
      return MCK__91_;  // "["
2112
880
    case ']':  // 1 string to match.
2113
42
      return MCK__93_;  // "]"
2114
0
    }
2115
0
    break;
2116
0
  case 2:  // 1 string to match.
2117
0
    if (memcmp(Name.data()+0, "16", 2) != 0)
2118
0
      break;
2119
0
    return MCK_16;   // "16"
2120
0
  case 3:  // 1 string to match.
2121
0
    if (memcmp(Name.data()+0, "bit", 3) != 0)
2122
0
      break;
2123
0
    return MCK_bit;  // "bit"
2124
0
  case 4:  // 1 string to match.
2125
0
    if (memcmp(Name.data()+0, "inst", 4) != 0)
2126
0
      break;
2127
0
    return MCK_inst;  // "inst"
2128
0
  }
2129
0
  return InvalidMatchClass;
2130
0
}
2131
2132
/// isSubclass - Compute whether \p A is a subclass of \p B.
2133
39.6k
static bool isSubclass(MatchClassKind A, MatchClassKind B) {
2134
39.6k
  if (A == B)
2135
1.00k
    return true;
2136
38.6k
2137
38.6k
  switch (A) {
2138
38.6k
  default:
2139
24.2k
    return false;
2140
38.6k
2141
38.6k
  case MCK_Reg37:
2142
0
    switch (B) {
2143
0
    default: return false;
2144
0
    case MCK_Reg24: return true;
2145
0
    case MCK_GPR64: return true;
2146
0
    }
2147
0
2148
0
  case MCK_Reg19:
2149
0
    switch (B) {
2150
0
    default: return false;
2151
0
    case MCK_Reg23: return true;
2152
0
    case MCK_Reg22: return true;
2153
0
    case MCK_Reg21: return true;
2154
0
    case MCK_GPR64: return true;
2155
0
    }
2156
0
2157
0
  case MCK_ACC64:
2158
0
    return B == MCK_ACC64DSP;
2159
0
2160
133
  case MCK_CPURAReg:
2161
133
    switch (B) {
2162
133
    default: return false;
2163
133
    
case MCK_GPR32NONZERO: return true0
;
2164
133
    
case MCK_DSPR: return true0
;
2165
0
    }
2166
0
2167
551
  case MCK_CPUSPReg:
2168
551
    switch (B) {
2169
551
    default: return false;
2170
551
    
case MCK_CPU16RegsPlusSP: return true0
;
2171
551
    
case MCK_GPR32NONZERO: return true0
;
2172
551
    
case MCK_DSPR: return true0
;
2173
0
    }
2174
0
2175
0
  case MCK_GP32:
2176
0
    switch (B) {
2177
0
    default: return false;
2178
0
    case MCK_GPR32NONZERO: return true;
2179
0
    case MCK_DSPR: return true;
2180
0
    }
2181
0
2182
0
  case MCK_GP64:
2183
0
    switch (B) {
2184
0
    default: return false;
2185
0
    case MCK_Reg24: return true;
2186
0
    case MCK_GPR64: return true;
2187
0
    }
2188
0
2189
351
  case MCK_GPR32ZERO:
2190
351
    switch (B) {
2191
351
    default: return false;
2192
351
    
case MCK_Reg4: return true0
;
2193
351
    
case MCK_GPRMM16MoveP: return true0
;
2194
351
    
case MCK_GPRMM16Zero: return true0
;
2195
351
    
case MCK_DSPR: return true0
;
2196
0
    }
2197
0
2198
0
  case MCK_HI32:
2199
0
    return B == MCK_HI32DSP;
2200
0
2201
0
  case MCK_LO32:
2202
0
    return B == MCK_LO32DSP;
2203
0
2204
0
  case MCK_SP64:
2205
0
    switch (B) {
2206
0
    default: return false;
2207
0
    case MCK_Reg26: return true;
2208
0
    case MCK_Reg24: return true;
2209
0
    case MCK_GPR64: return true;
2210
0
    }
2211
0
2212
0
  case MCK_Reg32:
2213
0
    switch (B) {
2214
0
    default: return false;
2215
0
    case MCK_Reg33: return true;
2216
0
    case MCK_Reg31: return true;
2217
0
    case MCK_Reg34: return true;
2218
0
    case MCK_Reg27: return true;
2219
0
    case MCK_Reg25: return true;
2220
0
    case MCK_Reg21: return true;
2221
0
    case MCK_Reg26: return true;
2222
0
    case MCK_Reg24: return true;
2223
0
    case MCK_GPR64: return true;
2224
0
    }
2225
0
2226
0
  case MCK_Reg13:
2227
0
    switch (B) {
2228
0
    default: return false;
2229
0
    case MCK_Reg14: return true;
2230
0
    case MCK_GPRMM16MovePPairFirst: return true;
2231
0
    case MCK_GPRMM16MovePPairSecond: return true;
2232
0
    case MCK_Reg8: return true;
2233
0
    case MCK_CPU16Regs: return true;
2234
0
    case MCK_GPRMM16Zero: return true;
2235
0
    case MCK_CPU16RegsPlusSP: return true;
2236
0
    case MCK_GPR32NONZERO: return true;
2237
0
    case MCK_DSPR: return true;
2238
0
    }
2239
0
2240
0
  case MCK_Reg33:
2241
0
    switch (B) {
2242
0
    default: return false;
2243
0
    case MCK_Reg34: return true;
2244
0
    case MCK_Reg27: return true;
2245
0
    case MCK_Reg25: return true;
2246
0
    case MCK_Reg21: return true;
2247
0
    case MCK_Reg26: return true;
2248
0
    case MCK_Reg24: return true;
2249
0
    case MCK_GPR64: return true;
2250
0
    }
2251
0
2252
0
  case MCK_Reg31:
2253
0
    switch (B) {
2254
0
    default: return false;
2255
0
    case MCK_Reg27: return true;
2256
0
    case MCK_Reg25: return true;
2257
0
    case MCK_Reg21: return true;
2258
0
    case MCK_Reg26: return true;
2259
0
    case MCK_Reg24: return true;
2260
0
    case MCK_GPR64: return true;
2261
0
    }
2262
0
2263
0
  case MCK_Reg30:
2264
0
    switch (B) {
2265
0
    default: return false;
2266
0
    case MCK_Reg28: return true;
2267
0
    case MCK_Reg23: return true;
2268
0
    case MCK_Reg29: return true;
2269
0
    case MCK_Reg27: return true;
2270
0
    case MCK_Reg25: return true;
2271
0
    case MCK_Reg22: return true;
2272
0
    case MCK_Reg21: return true;
2273
0
    case MCK_Reg26: return true;
2274
0
    case MCK_Reg24: return true;
2275
0
    case MCK_GPR64: return true;
2276
0
    }
2277
0
2278
0
  case MCK_Reg14:
2279
0
    switch (B) {
2280
0
    default: return false;
2281
0
    case MCK_GPRMM16MovePPairSecond: return true;
2282
0
    case MCK_Reg8: return true;
2283
0
    case MCK_CPU16Regs: return true;
2284
0
    case MCK_GPRMM16Zero: return true;
2285
0
    case MCK_CPU16RegsPlusSP: return true;
2286
0
    case MCK_GPR32NONZERO: return true;
2287
0
    case MCK_DSPR: return true;
2288
0
    }
2289
0
2290
0
  case MCK_Reg11:
2291
0
    switch (B) {
2292
0
    default: return false;
2293
0
    case MCK_Reg9: return true;
2294
0
    case MCK_Reg4: return true;
2295
0
    case MCK_Reg10: return true;
2296
0
    case MCK_Reg8: return true;
2297
0
    case MCK_CPU16Regs: return true;
2298
0
    case MCK_GPRMM16MoveP: return true;
2299
0
    case MCK_GPRMM16Zero: return true;
2300
0
    case MCK_CPU16RegsPlusSP: return true;
2301
0
    case MCK_GPR32NONZERO: return true;
2302
0
    case MCK_DSPR: return true;
2303
0
    }
2304
0
2305
0
  case MCK_GPRMM16MovePPairFirst:
2306
0
    switch (B) {
2307
0
    default: return false;
2308
0
    case MCK_Reg8: return true;
2309
0
    case MCK_CPU16Regs: return true;
2310
0
    case MCK_GPRMM16Zero: return true;
2311
0
    case MCK_CPU16RegsPlusSP: return true;
2312
0
    case MCK_GPR32NONZERO: return true;
2313
0
    case MCK_DSPR: return true;
2314
0
    }
2315
0
2316
0
  case MCK_Reg28:
2317
0
    switch (B) {
2318
0
    default: return false;
2319
0
    case MCK_Reg29: return true;
2320
0
    case MCK_Reg25: return true;
2321
0
    case MCK_Reg22: return true;
2322
0
    case MCK_Reg26: return true;
2323
0
    case MCK_Reg24: return true;
2324
0
    case MCK_GPR64: return true;
2325
0
    }
2326
0
2327
0
  case MCK_Reg23:
2328
0
    switch (B) {
2329
0
    default: return false;
2330
0
    case MCK_Reg22: return true;
2331
0
    case MCK_Reg21: return true;
2332
0
    case MCK_GPR64: return true;
2333
0
    }
2334
0
2335
0
  case MCK_Reg9:
2336
0
    switch (B) {
2337
0
    default: return false;
2338
0
    case MCK_Reg10: return true;
2339
0
    case MCK_CPU16Regs: return true;
2340
0
    case MCK_GPRMM16MoveP: return true;
2341
0
    case MCK_CPU16RegsPlusSP: return true;
2342
0
    case MCK_GPR32NONZERO: return true;
2343
0
    case MCK_DSPR: return true;
2344
0
    }
2345
0
2346
0
  case MCK_Reg4:
2347
0
    switch (B) {
2348
0
    default: return false;
2349
0
    case MCK_GPRMM16MoveP: return true;
2350
0
    case MCK_GPRMM16Zero: return true;
2351
0
    case MCK_DSPR: return true;
2352
0
    }
2353
0
2354
0
  case MCK_Reg34:
2355
0
    switch (B) {
2356
0
    default: return false;
2357
0
    case MCK_Reg24: return true;
2358
0
    case MCK_GPR64: return true;
2359
0
    }
2360
0
2361
0
  case MCK_GPRMM16MovePPairSecond:
2362
0
    switch (B) {
2363
0
    default: return false;
2364
0
    case MCK_GPR32NONZERO: return true;
2365
0
    case MCK_DSPR: return true;
2366
0
    }
2367
0
2368
0
  case MCK_Reg29:
2369
0
    switch (B) {
2370
0
    default: return false;
2371
0
    case MCK_Reg22: return true;
2372
0
    case MCK_Reg24: return true;
2373
0
    case MCK_GPR64: return true;
2374
0
    }
2375
0
2376
0
  case MCK_Reg27:
2377
0
    switch (B) {
2378
0
    default: return false;
2379
0
    case MCK_Reg25: return true;
2380
0
    case MCK_Reg21: return true;
2381
0
    case MCK_Reg26: return true;
2382
0
    case MCK_Reg24: return true;
2383
0
    case MCK_GPR64: return true;
2384
0
    }
2385
0
2386
0
  case MCK_Reg10:
2387
0
    switch (B) {
2388
0
    default: return false;
2389
0
    case MCK_GPRMM16MoveP: return true;
2390
0
    case MCK_GPR32NONZERO: return true;
2391
0
    case MCK_DSPR: return true;
2392
0
    }
2393
0
2394
0
  case MCK_Reg8:
2395
0
    switch (B) {
2396
0
    default: return false;
2397
0
    case MCK_CPU16Regs: return true;
2398
0
    case MCK_GPRMM16Zero: return true;
2399
0
    case MCK_CPU16RegsPlusSP: return true;
2400
0
    case MCK_GPR32NONZERO: return true;
2401
0
    case MCK_DSPR: return true;
2402
0
    }
2403
0
2404
0
  case MCK_Reg44:
2405
0
    switch (B) {
2406
0
    default: return false;
2407
0
    case MCK_AFGR64: return true;
2408
0
    case MCK_Reg45: return true;
2409
0
    case MCK_OddSP: return true;
2410
0
    }
2411
0
2412
0
  case MCK_Reg25:
2413
0
    switch (B) {
2414
0
    default: return false;
2415
0
    case MCK_Reg26: return true;
2416
0
    case MCK_Reg24: return true;
2417
0
    case MCK_GPR64: return true;
2418
0
    }
2419
0
2420
0
  case MCK_Reg22:
2421
0
    return B == MCK_GPR64;
2422
0
2423
0
  case MCK_Reg21:
2424
0
    return B == MCK_GPR64;
2425
0
2426
13.3k
  case MCK_CPU16Regs:
2427
13.3k
    switch (B) {
2428
13.3k
    default: return false;
2429
13.3k
    
case MCK_CPU16RegsPlusSP: return true0
;
2430
13.3k
    
case MCK_GPR32NONZERO: return true0
;
2431
13.3k
    
case MCK_DSPR: return true0
;
2432
0
    }
2433
0
2434
0
  case MCK_GPRMM16MoveP:
2435
0
    return B == MCK_DSPR;
2436
0
2437
0
  case MCK_GPRMM16Zero:
2438
0
    return B == MCK_DSPR;
2439
0
2440
0
  case MCK_Reg26:
2441
0
    switch (B) {
2442
0
    default: return false;
2443
0
    case MCK_Reg24: return true;
2444
0
    case MCK_GPR64: return true;
2445
0
    }
2446
0
2447
0
  case MCK_CPU16RegsPlusSP:
2448
0
    switch (B) {
2449
0
    default: return false;
2450
0
    case MCK_GPR32NONZERO: return true;
2451
0
    case MCK_DSPR: return true;
2452
0
    }
2453
0
2454
0
  case MCK_Reg50:
2455
0
    return B == MCK_MSA128F16;
2456
0
2457
0
  case MCK_Reg47:
2458
0
    switch (B) {
2459
0
    default: return false;
2460
0
    case MCK_Reg45: return true;
2461
0
    case MCK_FGR64: return true;
2462
0
    case MCK_OddSP: return true;
2463
0
    }
2464
0
2465
0
  case MCK_Reg42:
2466
0
    switch (B) {
2467
0
    default: return false;
2468
0
    case MCK_FGRH32: return true;
2469
0
    case MCK_OddSP: return true;
2470
0
    }
2471
0
2472
0
  case MCK_Reg39:
2473
0
    switch (B) {
2474
0
    default: return false;
2475
0
    case MCK_FGR32: return true;
2476
0
    case MCK_OddSP: return true;
2477
0
    }
2478
0
2479
0
  case MCK_MSA128WEvens:
2480
0
    return B == MCK_MSA128F16;
2481
0
2482
0
  case MCK_Reg45:
2483
0
    return B == MCK_OddSP;
2484
0
2485
0
  case MCK_Reg24:
2486
0
    return B == MCK_GPR64;
2487
0
2488
0
  case MCK_GPR32NONZERO:
2489
0
    return B == MCK_DSPR;
2490
0
2491
0
  case MCK_MemOffsetSimm10:
2492
0
    return B == MCK_Mem;
2493
0
2494
0
  case MCK_MemOffsetSimm10_1:
2495
0
    return B == MCK_Mem;
2496
0
2497
0
  case MCK_MemOffsetSimm10_2:
2498
0
    return B == MCK_Mem;
2499
0
2500
0
  case MCK_MemOffsetSimm10_3:
2501
0
    return B == MCK_Mem;
2502
0
2503
0
  case MCK_MemOffsetSimm11:
2504
0
    return B == MCK_Mem;
2505
0
2506
0
  case MCK_MemOffsetSimm12:
2507
0
    return B == MCK_Mem;
2508
0
2509
0
  case MCK_MemOffsetSimm16:
2510
0
    return B == MCK_Mem;
2511
0
2512
0
  case MCK_MemOffsetSimm9:
2513
0
    return B == MCK_Mem;
2514
0
2515
0
  case MCK_MemOffsetSimmPtr:
2516
0
    return B == MCK_Mem;
2517
0
2518
8
  case MCK_MemOffsetUimm4:
2519
8
    return B == MCK_Mem;
2520
0
2521
0
  case MCK_ConstantImmz:
2522
0
    switch (B) {
2523
0
    default: return false;
2524
0
    case MCK_ConstantUImm1_0: return true;
2525
0
    case MCK_ConstantUImm2_0: return true;
2526
0
    case MCK_ConstantUImm3_0: return true;
2527
0
    case MCK_ConstantSImm4_0: return true;
2528
0
    case MCK_ConstantUImm4_0: return true;
2529
0
    case MCK_ConstantSImm5_0: return true;
2530
0
    case MCK_ConstantUImm5_0: return true;
2531
0
    case MCK_ConstantUImm5_1: return true;
2532
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2533
0
    case MCK_ConstantUImm5_32_Norm: return true;
2534
0
    case MCK_ConstantUImm5_32: return true;
2535
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2536
0
    case MCK_ConstantUImm5_33: return true;
2537
0
    case MCK_ConstantUImmRange2_64: return true;
2538
0
    case MCK_UImm5Lsl2: return true;
2539
0
    case MCK_ConstantSImm6_0: return true;
2540
0
    case MCK_ConstantUImm6_0: return true;
2541
0
    case MCK_UImm6Lsl2: return true;
2542
0
    case MCK_ConstantUImm7_0: return true;
2543
0
    case MCK_UImm7_N1: return true;
2544
0
    case MCK_ConstantUImm8_0: return true;
2545
0
    case MCK_SImm7Lsl2: return true;
2546
0
    case MCK_ConstantSImm9_0: return true;
2547
0
    case MCK_ConstantSImm10_0: return true;
2548
0
    case MCK_ConstantUImm10_0: return true;
2549
0
    case MCK_SImm10Lsl1: return true;
2550
0
    case MCK_ConstantSImm11_0: return true;
2551
0
    case MCK_SImm10Lsl2: return true;
2552
0
    case MCK_SImm10Lsl3: return true;
2553
0
    case MCK_SImm16: return true;
2554
0
    case MCK_SImm16_Relaxed: return true;
2555
0
    case MCK_UImm16_Relaxed: return true;
2556
0
    case MCK_ConstantUImm20_0: return true;
2557
0
    case MCK_ConstantUImm26_0: return true;
2558
0
    case MCK_SImm32: return true;
2559
0
    case MCK_SImm32_Relaxed: return true;
2560
0
    case MCK_UImm32_Coerced: return true;
2561
0
    }
2562
0
2563
0
  case MCK_ConstantUImm1_0:
2564
0
    switch (B) {
2565
0
    default: return false;
2566
0
    case MCK_ConstantUImm2_0: return true;
2567
0
    case MCK_ConstantUImm3_0: return true;
2568
0
    case MCK_ConstantSImm4_0: return true;
2569
0
    case MCK_ConstantUImm4_0: return true;
2570
0
    case MCK_ConstantSImm5_0: return true;
2571
0
    case MCK_ConstantUImm5_0: return true;
2572
0
    case MCK_ConstantUImm5_1: return true;
2573
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2574
0
    case MCK_ConstantUImm5_32_Norm: return true;
2575
0
    case MCK_ConstantUImm5_32: return true;
2576
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2577
0
    case MCK_ConstantUImm5_33: return true;
2578
0
    case MCK_ConstantUImmRange2_64: return true;
2579
0
    case MCK_UImm5Lsl2: return true;
2580
0
    case MCK_ConstantSImm6_0: return true;
2581
0
    case MCK_ConstantUImm6_0: return true;
2582
0
    case MCK_UImm6Lsl2: return true;
2583
0
    case MCK_ConstantUImm7_0: return true;
2584
0
    case MCK_UImm7_N1: return true;
2585
0
    case MCK_ConstantUImm8_0: return true;
2586
0
    case MCK_SImm7Lsl2: return true;
2587
0
    case MCK_ConstantSImm9_0: return true;
2588
0
    case MCK_ConstantSImm10_0: return true;
2589
0
    case MCK_ConstantUImm10_0: return true;
2590
0
    case MCK_SImm10Lsl1: return true;
2591
0
    case MCK_ConstantSImm11_0: return true;
2592
0
    case MCK_SImm10Lsl2: return true;
2593
0
    case MCK_SImm10Lsl3: return true;
2594
0
    case MCK_SImm16: return true;
2595
0
    case MCK_SImm16_Relaxed: return true;
2596
0
    case MCK_UImm16_Relaxed: return true;
2597
0
    case MCK_ConstantUImm20_0: return true;
2598
0
    case MCK_ConstantUImm26_0: return true;
2599
0
    case MCK_SImm32: return true;
2600
0
    case MCK_SImm32_Relaxed: return true;
2601
0
    case MCK_UImm32_Coerced: return true;
2602
0
    }
2603
0
2604
6
  case MCK_ConstantUImm2_0:
2605
6
    switch (B) {
2606
6
    default: return false;
2607
6
    
case MCK_ConstantUImm3_0: return true0
;
2608
6
    
case MCK_ConstantSImm4_0: return true0
;
2609
6
    
case MCK_ConstantUImm4_0: return true0
;
2610
6
    
case MCK_ConstantSImm5_0: return true0
;
2611
6
    
case MCK_ConstantUImm5_0: return true0
;
2612
6
    
case MCK_ConstantUImm5_1: return true0
;
2613
6
    
case MCK_ConstantUImm5_Plus1_Report_UImm6: return true0
;
2614
6
    
case MCK_ConstantUImm5_32_Norm: return true0
;
2615
6
    
case MCK_ConstantUImm5_32: return true0
;
2616
6
    
case MCK_ConstantUImm5_0_Report_UImm6: return true0
;
2617
6
    
case MCK_ConstantUImm5_33: return true0
;
2618
6
    
case MCK_ConstantUImmRange2_64: return true0
;
2619
6
    
case MCK_UImm5Lsl2: return true0
;
2620
6
    
case MCK_ConstantSImm6_0: return true0
;
2621
6
    
case MCK_ConstantUImm6_0: return true0
;
2622
6
    
case MCK_UImm6Lsl2: return true0
;
2623
6
    
case MCK_ConstantUImm7_0: return true0
;
2624
6
    
case MCK_UImm7_N1: return true0
;
2625
6
    
case MCK_ConstantUImm8_0: return true0
;
2626
6
    
case MCK_SImm7Lsl2: return true0
;
2627
6
    
case MCK_ConstantSImm9_0: return true0
;
2628
6
    
case MCK_ConstantSImm10_0: return true0
;
2629
6
    
case MCK_ConstantUImm10_0: return true0
;
2630
6
    
case MCK_SImm10Lsl1: return true0
;
2631
6
    
case MCK_ConstantSImm11_0: return true0
;
2632
6
    
case MCK_SImm10Lsl2: return true0
;
2633
6
    
case MCK_SImm10Lsl3: return true0
;
2634
6
    
case MCK_SImm16: return true0
;
2635
6
    
case MCK_SImm16_Relaxed: return true0
;
2636
6
    
case MCK_UImm16_Relaxed: return true0
;
2637
6
    
case MCK_ConstantUImm20_0: return true0
;
2638
6
    
case MCK_ConstantUImm26_0: return true0
;
2639
6
    
case MCK_SImm32: return true0
;
2640
6
    
case MCK_SImm32_Relaxed: return true0
;
2641
6
    
case MCK_UImm32_Coerced: return true0
;
2642
0
    }
2643
0
2644
0
  case MCK_ConstantUImm2_1:
2645
0
    switch (B) {
2646
0
    default: return false;
2647
0
    case MCK_ConstantUImm3_0: return true;
2648
0
    case MCK_ConstantSImm4_0: return true;
2649
0
    case MCK_ConstantUImm4_0: return true;
2650
0
    case MCK_ConstantSImm5_0: return true;
2651
0
    case MCK_ConstantUImm5_0: return true;
2652
0
    case MCK_ConstantUImm5_1: return true;
2653
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2654
0
    case MCK_ConstantUImm5_32_Norm: return true;
2655
0
    case MCK_ConstantUImm5_32: return true;
2656
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2657
0
    case MCK_ConstantUImm5_33: return true;
2658
0
    case MCK_ConstantUImmRange2_64: return true;
2659
0
    case MCK_UImm5Lsl2: return true;
2660
0
    case MCK_ConstantSImm6_0: return true;
2661
0
    case MCK_ConstantUImm6_0: return true;
2662
0
    case MCK_UImm6Lsl2: return true;
2663
0
    case MCK_ConstantUImm7_0: return true;
2664
0
    case MCK_UImm7_N1: return true;
2665
0
    case MCK_ConstantUImm8_0: return true;
2666
0
    case MCK_SImm7Lsl2: return true;
2667
0
    case MCK_ConstantSImm9_0: return true;
2668
0
    case MCK_ConstantSImm10_0: return true;
2669
0
    case MCK_ConstantUImm10_0: return true;
2670
0
    case MCK_SImm10Lsl1: return true;
2671
0
    case MCK_ConstantSImm11_0: return true;
2672
0
    case MCK_SImm10Lsl2: return true;
2673
0
    case MCK_SImm10Lsl3: return true;
2674
0
    case MCK_SImm16: return true;
2675
0
    case MCK_SImm16_Relaxed: return true;
2676
0
    case MCK_UImm16_Relaxed: return true;
2677
0
    case MCK_ConstantUImm20_0: return true;
2678
0
    case MCK_ConstantUImm26_0: return true;
2679
0
    case MCK_SImm32: return true;
2680
0
    case MCK_SImm32_Relaxed: return true;
2681
0
    case MCK_UImm32_Coerced: return true;
2682
0
    }
2683
0
2684
0
  case MCK_ConstantUImm3_0:
2685
0
    switch (B) {
2686
0
    default: return false;
2687
0
    case MCK_ConstantSImm4_0: return true;
2688
0
    case MCK_ConstantUImm4_0: return true;
2689
0
    case MCK_ConstantSImm5_0: return true;
2690
0
    case MCK_ConstantUImm5_0: return true;
2691
0
    case MCK_ConstantUImm5_1: return true;
2692
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2693
0
    case MCK_ConstantUImm5_32_Norm: return true;
2694
0
    case MCK_ConstantUImm5_32: return true;
2695
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2696
0
    case MCK_ConstantUImm5_33: return true;
2697
0
    case MCK_ConstantUImmRange2_64: return true;
2698
0
    case MCK_UImm5Lsl2: return true;
2699
0
    case MCK_ConstantSImm6_0: return true;
2700
0
    case MCK_ConstantUImm6_0: return true;
2701
0
    case MCK_UImm6Lsl2: return true;
2702
0
    case MCK_ConstantUImm7_0: return true;
2703
0
    case MCK_UImm7_N1: return true;
2704
0
    case MCK_ConstantUImm8_0: return true;
2705
0
    case MCK_SImm7Lsl2: return true;
2706
0
    case MCK_ConstantSImm9_0: return true;
2707
0
    case MCK_ConstantSImm10_0: return true;
2708
0
    case MCK_ConstantUImm10_0: return true;
2709
0
    case MCK_SImm10Lsl1: return true;
2710
0
    case MCK_ConstantSImm11_0: return true;
2711
0
    case MCK_SImm10Lsl2: return true;
2712
0
    case MCK_SImm10Lsl3: return true;
2713
0
    case MCK_SImm16: return true;
2714
0
    case MCK_SImm16_Relaxed: return true;
2715
0
    case MCK_UImm16_Relaxed: return true;
2716
0
    case MCK_ConstantUImm20_0: return true;
2717
0
    case MCK_ConstantUImm26_0: return true;
2718
0
    case MCK_SImm32: return true;
2719
0
    case MCK_SImm32_Relaxed: return true;
2720
0
    case MCK_UImm32_Coerced: return true;
2721
0
    }
2722
0
2723
0
  case MCK_ConstantSImm4_0:
2724
0
    switch (B) {
2725
0
    default: return false;
2726
0
    case MCK_ConstantUImm4_0: return true;
2727
0
    case MCK_ConstantSImm5_0: return true;
2728
0
    case MCK_ConstantUImm5_0: return true;
2729
0
    case MCK_ConstantUImm5_1: return true;
2730
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2731
0
    case MCK_ConstantUImm5_32_Norm: return true;
2732
0
    case MCK_ConstantUImm5_32: return true;
2733
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2734
0
    case MCK_ConstantUImm5_33: return true;
2735
0
    case MCK_ConstantUImmRange2_64: return true;
2736
0
    case MCK_UImm5Lsl2: return true;
2737
0
    case MCK_ConstantSImm6_0: return true;
2738
0
    case MCK_ConstantUImm6_0: return true;
2739
0
    case MCK_UImm6Lsl2: return true;
2740
0
    case MCK_ConstantUImm7_0: return true;
2741
0
    case MCK_UImm7_N1: return true;
2742
0
    case MCK_ConstantUImm8_0: return true;
2743
0
    case MCK_SImm7Lsl2: return true;
2744
0
    case MCK_ConstantSImm9_0: return true;
2745
0
    case MCK_ConstantSImm10_0: return true;
2746
0
    case MCK_ConstantUImm10_0: return true;
2747
0
    case MCK_SImm10Lsl1: return true;
2748
0
    case MCK_ConstantSImm11_0: return true;
2749
0
    case MCK_SImm10Lsl2: return true;
2750
0
    case MCK_SImm10Lsl3: return true;
2751
0
    case MCK_SImm16: return true;
2752
0
    case MCK_SImm16_Relaxed: return true;
2753
0
    case MCK_UImm16_Relaxed: return true;
2754
0
    case MCK_ConstantUImm20_0: return true;
2755
0
    case MCK_ConstantUImm26_0: return true;
2756
0
    case MCK_SImm32: return true;
2757
0
    case MCK_SImm32_Relaxed: return true;
2758
0
    case MCK_UImm32_Coerced: return true;
2759
0
    }
2760
0
2761
6
  case MCK_ConstantUImm4_0:
2762
6
    switch (B) {
2763
6
    default: return false;
2764
6
    
case MCK_ConstantSImm5_0: return true0
;
2765
6
    
case MCK_ConstantUImm5_0: return true0
;
2766
6
    
case MCK_ConstantUImm5_1: return true0
;
2767
6
    
case MCK_ConstantUImm5_Plus1_Report_UImm6: return true0
;
2768
6
    
case MCK_ConstantUImm5_32_Norm: return true0
;
2769
6
    
case MCK_ConstantUImm5_32: return true0
;
2770
6
    
case MCK_ConstantUImm5_0_Report_UImm6: return true0
;
2771
6
    
case MCK_ConstantUImm5_33: return true0
;
2772
6
    
case MCK_ConstantUImmRange2_64: return true0
;
2773
6
    
case MCK_UImm5Lsl2: return true0
;
2774
6
    
case MCK_ConstantSImm6_0: return true0
;
2775
6
    
case MCK_ConstantUImm6_0: return true0
;
2776
6
    
case MCK_UImm6Lsl2: return true0
;
2777
6
    
case MCK_ConstantUImm7_0: return true0
;
2778
6
    
case MCK_UImm7_N1: return true0
;
2779
6
    
case MCK_ConstantUImm8_0: return true0
;
2780
6
    
case MCK_SImm7Lsl2: return true0
;
2781
6
    
case MCK_ConstantSImm9_0: return true0
;
2782
6
    
case MCK_ConstantSImm10_0: return true0
;
2783
6
    
case MCK_ConstantUImm10_0: return true0
;
2784
6
    
case MCK_SImm10Lsl1: return true0
;
2785
6
    
case MCK_ConstantSImm11_0: return true0
;
2786
6
    
case MCK_SImm10Lsl2: return true0
;
2787
6
    
case MCK_SImm10Lsl3: return true0
;
2788
6
    
case MCK_SImm16: return true0
;
2789
6
    
case MCK_SImm16_Relaxed: return true0
;
2790
6
    
case MCK_UImm16_Relaxed: return true0
;
2791
6
    
case MCK_ConstantUImm20_0: return true0
;
2792
6
    
case MCK_ConstantUImm26_0: return true0
;
2793
6
    
case MCK_SImm32: return true0
;
2794
6
    
case MCK_SImm32_Relaxed: return true0
;
2795
6
    
case MCK_UImm32_Coerced: return true0
;
2796
0
    }
2797
0
2798
0
  case MCK_ConstantSImm5_0:
2799
0
    switch (B) {
2800
0
    default: return false;
2801
0
    case MCK_ConstantUImm5_0: return true;
2802
0
    case MCK_ConstantUImm5_1: return true;
2803
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2804
0
    case MCK_ConstantUImm5_32_Norm: return true;
2805
0
    case MCK_ConstantUImm5_32: return true;
2806
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2807
0
    case MCK_ConstantUImm5_33: return true;
2808
0
    case MCK_ConstantUImmRange2_64: return true;
2809
0
    case MCK_UImm5Lsl2: return true;
2810
0
    case MCK_ConstantSImm6_0: return true;
2811
0
    case MCK_ConstantUImm6_0: return true;
2812
0
    case MCK_UImm6Lsl2: return true;
2813
0
    case MCK_ConstantUImm7_0: return true;
2814
0
    case MCK_UImm7_N1: return true;
2815
0
    case MCK_ConstantUImm8_0: return true;
2816
0
    case MCK_SImm7Lsl2: return true;
2817
0
    case MCK_ConstantSImm9_0: return true;
2818
0
    case MCK_ConstantSImm10_0: return true;
2819
0
    case MCK_ConstantUImm10_0: return true;
2820
0
    case MCK_SImm10Lsl1: return true;
2821
0
    case MCK_ConstantSImm11_0: return true;
2822
0
    case MCK_SImm10Lsl2: return true;
2823
0
    case MCK_SImm10Lsl3: return true;
2824
0
    case MCK_SImm16: return true;
2825
0
    case MCK_SImm16_Relaxed: return true;
2826
0
    case MCK_UImm16_Relaxed: return true;
2827
0
    case MCK_ConstantUImm20_0: return true;
2828
0
    case MCK_ConstantUImm26_0: return true;
2829
0
    case MCK_SImm32: return true;
2830
0
    case MCK_SImm32_Relaxed: return true;
2831
0
    case MCK_UImm32_Coerced: return true;
2832
0
    }
2833
0
2834
3
  case MCK_ConstantUImm5_0:
2835
3
    switch (B) {
2836
3
    default: return false;
2837
3
    
case MCK_ConstantUImm5_1: return true0
;
2838
3
    
case MCK_ConstantUImm5_Plus1_Report_UImm6: return true0
;
2839
3
    
case MCK_ConstantUImm5_32_Norm: return true0
;
2840
3
    
case MCK_ConstantUImm5_32: return true0
;
2841
3
    
case MCK_ConstantUImm5_0_Report_UImm6: return true0
;
2842
3
    
case MCK_ConstantUImm5_33: return true0
;
2843
3
    
case MCK_ConstantUImmRange2_64: return true0
;
2844
3
    
case MCK_UImm5Lsl2: return true0
;
2845
3
    
case MCK_ConstantSImm6_0: return true0
;
2846
3
    
case MCK_ConstantUImm6_0: return true0
;
2847
3
    
case MCK_UImm6Lsl2: return true0
;
2848
3
    
case MCK_ConstantUImm7_0: return true0
;
2849
3
    
case MCK_UImm7_N1: return true0
;
2850
3
    
case MCK_ConstantUImm8_0: return true0
;
2851
3
    
case MCK_SImm7Lsl2: return true0
;
2852
3
    
case MCK_ConstantSImm9_0: return true0
;
2853
3
    
case MCK_ConstantSImm10_0: return true0
;
2854
3
    
case MCK_ConstantUImm10_0: return true0
;
2855
3
    
case MCK_SImm10Lsl1: return true0
;
2856
3
    
case MCK_ConstantSImm11_0: return true0
;
2857
3
    
case MCK_SImm10Lsl2: return true0
;
2858
3
    
case MCK_SImm10Lsl3: return true0
;
2859
3
    
case MCK_SImm16: return true0
;
2860
3
    
case MCK_SImm16_Relaxed: return true0
;
2861
3
    
case MCK_UImm16_Relaxed: return true0
;
2862
3
    
case MCK_ConstantUImm20_0: return true0
;
2863
3
    
case MCK_ConstantUImm26_0: return true0
;
2864
3
    
case MCK_SImm32: return true0
;
2865
3
    
case MCK_SImm32_Relaxed: return true0
;
2866
3
    
case MCK_UImm32_Coerced: return true0
;
2867
0
    }
2868
0
2869
0
  case MCK_ConstantUImm5_1:
2870
0
    switch (B) {
2871
0
    default: return false;
2872
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2873
0
    case MCK_ConstantUImm5_32_Norm: return true;
2874
0
    case MCK_ConstantUImm5_32: return true;
2875
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2876
0
    case MCK_ConstantUImm5_33: return true;
2877
0
    case MCK_ConstantUImmRange2_64: return true;
2878
0
    case MCK_UImm5Lsl2: return true;
2879
0
    case MCK_ConstantSImm6_0: return true;
2880
0
    case MCK_ConstantUImm6_0: return true;
2881
0
    case MCK_UImm6Lsl2: return true;
2882
0
    case MCK_ConstantUImm7_0: return true;
2883
0
    case MCK_UImm7_N1: return true;
2884
0
    case MCK_ConstantUImm8_0: return true;
2885
0
    case MCK_SImm7Lsl2: return true;
2886
0
    case MCK_ConstantSImm9_0: return true;
2887
0
    case MCK_ConstantSImm10_0: return true;
2888
0
    case MCK_ConstantUImm10_0: return true;
2889
0
    case MCK_SImm10Lsl1: return true;
2890
0
    case MCK_ConstantSImm11_0: return true;
2891
0
    case MCK_SImm10Lsl2: return true;
2892
0
    case MCK_SImm10Lsl3: return true;
2893
0
    case MCK_SImm16: return true;
2894
0
    case MCK_SImm16_Relaxed: return true;
2895
0
    case MCK_UImm16_Relaxed: return true;
2896
0
    case MCK_ConstantUImm20_0: return true;
2897
0
    case MCK_ConstantUImm26_0: return true;
2898
0
    case MCK_SImm32: return true;
2899
0
    case MCK_SImm32_Relaxed: return true;
2900
0
    case MCK_UImm32_Coerced: return true;
2901
0
    }
2902
0
2903
0
  case MCK_ConstantUImm5_Plus1_Report_UImm6:
2904
0
    switch (B) {
2905
0
    default: return false;
2906
0
    case MCK_ConstantUImm5_32_Norm: return true;
2907
0
    case MCK_ConstantUImm5_32: return true;
2908
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2909
0
    case MCK_ConstantUImm5_33: return true;
2910
0
    case MCK_ConstantUImmRange2_64: return true;
2911
0
    case MCK_UImm5Lsl2: return true;
2912
0
    case MCK_ConstantSImm6_0: return true;
2913
0
    case MCK_ConstantUImm6_0: return true;
2914
0
    case MCK_UImm6Lsl2: return true;
2915
0
    case MCK_ConstantUImm7_0: return true;
2916
0
    case MCK_UImm7_N1: return true;
2917
0
    case MCK_ConstantUImm8_0: return true;
2918
0
    case MCK_SImm7Lsl2: return true;
2919
0
    case MCK_ConstantSImm9_0: return true;
2920
0
    case MCK_ConstantSImm10_0: return true;
2921
0
    case MCK_ConstantUImm10_0: return true;
2922
0
    case MCK_SImm10Lsl1: return true;
2923
0
    case MCK_ConstantSImm11_0: return true;
2924
0
    case MCK_SImm10Lsl2: return true;
2925
0
    case MCK_SImm10Lsl3: return true;
2926
0
    case MCK_SImm16: return true;
2927
0
    case MCK_SImm16_Relaxed: return true;
2928
0
    case MCK_UImm16_Relaxed: return true;
2929
0
    case MCK_ConstantUImm20_0: return true;
2930
0
    case MCK_ConstantUImm26_0: return true;
2931
0
    case MCK_SImm32: return true;
2932
0
    case MCK_SImm32_Relaxed: return true;
2933
0
    case MCK_UImm32_Coerced: return true;
2934
0
    }
2935
0
2936
0
  case MCK_ConstantUImm5_32_Norm:
2937
0
    switch (B) {
2938
0
    default: return false;
2939
0
    case MCK_ConstantUImm5_32: return true;
2940
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2941
0
    case MCK_ConstantUImm5_33: return true;
2942
0
    case MCK_ConstantUImmRange2_64: return true;
2943
0
    case MCK_UImm5Lsl2: return true;
2944
0
    case MCK_ConstantSImm6_0: return true;
2945
0
    case MCK_ConstantUImm6_0: return true;
2946
0
    case MCK_UImm6Lsl2: return true;
2947
0
    case MCK_ConstantUImm7_0: return true;
2948
0
    case MCK_UImm7_N1: return true;
2949
0
    case MCK_ConstantUImm8_0: return true;
2950
0
    case MCK_SImm7Lsl2: return true;
2951
0
    case MCK_ConstantSImm9_0: return true;
2952
0
    case MCK_ConstantSImm10_0: return true;
2953
0
    case MCK_ConstantUImm10_0: return true;
2954
0
    case MCK_SImm10Lsl1: return true;
2955
0
    case MCK_ConstantSImm11_0: return true;
2956
0
    case MCK_SImm10Lsl2: return true;
2957
0
    case MCK_SImm10Lsl3: return true;
2958
0
    case MCK_SImm16: return true;
2959
0
    case MCK_SImm16_Relaxed: return true;
2960
0
    case MCK_UImm16_Relaxed: return true;
2961
0
    case MCK_ConstantUImm20_0: return true;
2962
0
    case MCK_ConstantUImm26_0: return true;
2963
0
    case MCK_SImm32: return true;
2964
0
    case MCK_SImm32_Relaxed: return true;
2965
0
    case MCK_UImm32_Coerced: return true;
2966
0
    }
2967
0
2968
0
  case MCK_ConstantUImm5_32:
2969
0
    switch (B) {
2970
0
    default: return false;
2971
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2972
0
    case MCK_ConstantUImm5_33: return true;
2973
0
    case MCK_ConstantUImmRange2_64: return true;
2974
0
    case MCK_UImm5Lsl2: return true;
2975
0
    case MCK_ConstantSImm6_0: return true;
2976
0
    case MCK_ConstantUImm6_0: return true;
2977
0
    case MCK_UImm6Lsl2: return true;
2978
0
    case MCK_ConstantUImm7_0: return true;
2979
0
    case MCK_UImm7_N1: return true;
2980
0
    case MCK_ConstantUImm8_0: return true;
2981
0
    case MCK_SImm7Lsl2: return true;
2982
0
    case MCK_ConstantSImm9_0: return true;
2983
0
    case MCK_ConstantSImm10_0: return true;
2984
0
    case MCK_ConstantUImm10_0: return true;
2985
0
    case MCK_SImm10Lsl1: return true;
2986
0
    case MCK_ConstantSImm11_0: return true;
2987
0
    case MCK_SImm10Lsl2: return true;
2988
0
    case MCK_SImm10Lsl3: return true;
2989
0
    case MCK_SImm16: return true;
2990
0
    case MCK_SImm16_Relaxed: return true;
2991
0
    case MCK_UImm16_Relaxed: return true;
2992
0
    case MCK_ConstantUImm20_0: return true;
2993
0
    case MCK_ConstantUImm26_0: return true;
2994
0
    case MCK_SImm32: return true;
2995
0
    case MCK_SImm32_Relaxed: return true;
2996
0
    case MCK_UImm32_Coerced: return true;
2997
0
    }
2998
0
2999
0
  case MCK_ConstantUImm5_0_Report_UImm6:
3000
0
    switch (B) {
3001
0
    default: return false;
3002
0
    case MCK_ConstantUImm5_33: return true;
3003
0
    case MCK_ConstantUImmRange2_64: return true;
3004
0
    case MCK_UImm5Lsl2: return true;
3005
0
    case MCK_ConstantSImm6_0: return true;
3006
0
    case MCK_ConstantUImm6_0: return true;
3007
0
    case MCK_UImm6Lsl2: return true;
3008
0
    case MCK_ConstantUImm7_0: return true;
3009
0
    case MCK_UImm7_N1: return true;
3010
0
    case MCK_ConstantUImm8_0: return true;
3011
0
    case MCK_SImm7Lsl2: return true;
3012
0
    case MCK_ConstantSImm9_0: return true;
3013
0
    case MCK_ConstantSImm10_0: return true;
3014
0
    case MCK_ConstantUImm10_0: return true;
3015
0
    case MCK_SImm10Lsl1: return true;
3016
0
    case MCK_ConstantSImm11_0: return true;
3017
0
    case MCK_SImm10Lsl2: return true;
3018
0
    case MCK_SImm10Lsl3: return true;
3019
0
    case MCK_SImm16: return true;
3020
0
    case MCK_SImm16_Relaxed: return true;
3021
0
    case MCK_UImm16_Relaxed: return true;
3022
0
    case MCK_ConstantUImm20_0: return true;
3023
0
    case MCK_ConstantUImm26_0: return true;
3024
0
    case MCK_SImm32: return true;
3025
0
    case MCK_SImm32_Relaxed: return true;
3026
0
    case MCK_UImm32_Coerced: return true;
3027
0
    }
3028
0
3029
0
  case MCK_ConstantUImm5_33:
3030
0
    switch (B) {
3031
0
    default: return false;
3032
0
    case MCK_ConstantUImmRange2_64: return true;
3033
0
    case MCK_UImm5Lsl2: return true;
3034
0
    case MCK_ConstantSImm6_0: return true;
3035
0
    case MCK_ConstantUImm6_0: return true;
3036
0
    case MCK_UImm6Lsl2: return true;
3037
0
    case MCK_ConstantUImm7_0: return true;
3038
0
    case MCK_UImm7_N1: return true;
3039
0
    case MCK_ConstantUImm8_0: return true;
3040
0
    case MCK_SImm7Lsl2: return true;
3041
0
    case MCK_ConstantSImm9_0: return true;
3042
0
    case MCK_ConstantSImm10_0: return true;
3043
0
    case MCK_ConstantUImm10_0: return true;
3044
0
    case MCK_SImm10Lsl1: return true;
3045
0
    case MCK_ConstantSImm11_0: return true;
3046
0
    case MCK_SImm10Lsl2: return true;
3047
0
    case MCK_SImm10Lsl3: return true;
3048
0
    case MCK_SImm16: return true;
3049
0
    case MCK_SImm16_Relaxed: return true;
3050
0
    case MCK_UImm16_Relaxed: return true;
3051
0
    case MCK_ConstantUImm20_0: return true;
3052
0
    case MCK_ConstantUImm26_0: return true;
3053
0
    case MCK_SImm32: return true;
3054
0
    case MCK_SImm32_Relaxed: return true;
3055
0
    case MCK_UImm32_Coerced: return true;
3056
0
    }
3057
0
3058
0
  case MCK_ConstantUImmRange2_64:
3059
0
    switch (B) {
3060
0
    default: return false;
3061
0
    case MCK_UImm5Lsl2: return true;
3062
0
    case MCK_ConstantSImm6_0: return true;
3063
0
    case MCK_ConstantUImm6_0: return true;
3064
0
    case MCK_UImm6Lsl2: return true;
3065
0
    case MCK_ConstantUImm7_0: return true;
3066
0
    case MCK_UImm7_N1: return true;
3067
0
    case MCK_ConstantUImm8_0: return true;
3068
0
    case MCK_SImm7Lsl2: return true;
3069
0
    case MCK_ConstantSImm9_0: return true;
3070
0
    case MCK_ConstantSImm10_0: return true;
3071
0
    case MCK_ConstantUImm10_0: return true;
3072
0
    case MCK_SImm10Lsl1: return true;
3073
0
    case MCK_ConstantSImm11_0: return true;
3074
0
    case MCK_SImm10Lsl2: return true;
3075
0
    case MCK_SImm10Lsl3: return true;
3076
0
    case MCK_SImm16: return true;
3077
0
    case MCK_SImm16_Relaxed: return true;
3078
0
    case MCK_UImm16_Relaxed: return true;
3079
0
    case MCK_ConstantUImm20_0: return true;
3080
0
    case MCK_ConstantUImm26_0: return true;
3081
0
    case MCK_SImm32: return true;
3082
0
    case MCK_SImm32_Relaxed: return true;
3083
0
    case MCK_UImm32_Coerced: return true;
3084
0
    }
3085
0
3086
0
  case MCK_UImm5Lsl2:
3087
0
    switch (B) {
3088
0
    default: return false;
3089
0
    case MCK_ConstantSImm6_0: return true;
3090
0
    case MCK_ConstantUImm6_0: return true;
3091
0
    case MCK_UImm6Lsl2: return true;
3092
0
    case MCK_ConstantUImm7_0: return true;
3093
0
    case MCK_UImm7_N1: return true;
3094
0
    case MCK_ConstantUImm8_0: return true;
3095
0
    case MCK_SImm7Lsl2: return true;
3096
0
    case MCK_ConstantSImm9_0: return true;
3097
0
    case MCK_ConstantSImm10_0: return true;
3098
0
    case MCK_ConstantUImm10_0: return true;
3099
0
    case MCK_SImm10Lsl1: return true;
3100
0
    case MCK_ConstantSImm11_0: return true;
3101
0
    case MCK_SImm10Lsl2: return true;
3102
0
    case MCK_SImm10Lsl3: return true;
3103
0
    case MCK_SImm16: return true;
3104
0
    case MCK_SImm16_Relaxed: return true;
3105
0
    case MCK_UImm16_Relaxed: return true;
3106
0
    case MCK_ConstantUImm20_0: return true;
3107
0
    case MCK_ConstantUImm26_0: return true;
3108
0
    case MCK_SImm32: return true;
3109
0
    case MCK_SImm32_Relaxed: return true;
3110
0
    case MCK_UImm32_Coerced: return true;
3111
0
    }
3112
0
3113
0
  case MCK_ConstantSImm6_0:
3114
0
    switch (B) {
3115
0
    default: return false;
3116
0
    case MCK_ConstantUImm6_0: return true;
3117
0
    case MCK_UImm6Lsl2: return true;
3118
0
    case MCK_ConstantUImm7_0: return true;
3119
0
    case MCK_UImm7_N1: return true;
3120
0
    case MCK_ConstantUImm8_0: return true;
3121
0
    case MCK_SImm7Lsl2: return true;
3122
0
    case MCK_ConstantSImm9_0: return true;
3123
0
    case MCK_ConstantSImm10_0: return true;
3124
0
    case MCK_ConstantUImm10_0: return true;
3125
0
    case MCK_SImm10Lsl1: return true;
3126
0
    case MCK_ConstantSImm11_0: return true;
3127
0
    case MCK_SImm10Lsl2: return true;
3128
0
    case MCK_SImm10Lsl3: return true;
3129
0
    case MCK_SImm16: return true;
3130
0
    case MCK_SImm16_Relaxed: return true;
3131
0
    case MCK_UImm16_Relaxed: return true;
3132
0
    case MCK_ConstantUImm20_0: return true;
3133
0
    case MCK_ConstantUImm26_0: return true;
3134
0
    case MCK_SImm32: return true;
3135
0
    case MCK_SImm32_Relaxed: return true;
3136
0
    case MCK_UImm32_Coerced: return true;
3137
0
    }
3138
0
3139
0
  case MCK_ConstantUImm6_0:
3140
0
    switch (B) {
3141
0
    default: return false;
3142
0
    case MCK_UImm6Lsl2: return true;
3143
0
    case MCK_ConstantUImm7_0: return true;
3144
0
    case MCK_UImm7_N1: return true;
3145
0
    case MCK_ConstantUImm8_0: return true;
3146
0
    case MCK_SImm7Lsl2: return true;
3147
0
    case MCK_ConstantSImm9_0: return true;
3148
0
    case MCK_ConstantSImm10_0: return true;
3149
0
    case MCK_ConstantUImm10_0: return true;
3150
0
    case MCK_SImm10Lsl1: return true;
3151
0
    case MCK_ConstantSImm11_0: return true;
3152
0
    case MCK_SImm10Lsl2: return true;
3153
0
    case MCK_SImm10Lsl3: return true;
3154
0
    case MCK_SImm16: return true;
3155
0
    case MCK_SImm16_Relaxed: return true;
3156
0
    case MCK_UImm16_Relaxed: return true;
3157
0
    case MCK_ConstantUImm20_0: return true;
3158
0
    case MCK_ConstantUImm26_0: return true;
3159
0
    case MCK_SImm32: return true;
3160
0
    case MCK_SImm32_Relaxed: return true;
3161
0
    case MCK_UImm32_Coerced: return true;
3162
0
    }
3163
0
3164
0
  case MCK_UImm6Lsl2:
3165
0
    switch (B) {
3166
0
    default: return false;
3167
0
    case MCK_ConstantUImm7_0: return true;
3168
0
    case MCK_UImm7_N1: return true;
3169
0
    case MCK_ConstantUImm8_0: return true;
3170
0
    case MCK_SImm7Lsl2: return true;
3171
0
    case MCK_ConstantSImm9_0: return true;
3172
0
    case MCK_ConstantSImm10_0: return true;
3173
0
    case MCK_ConstantUImm10_0: return true;
3174
0
    case MCK_SImm10Lsl1: return true;
3175
0
    case MCK_ConstantSImm11_0: return true;
3176
0
    case MCK_SImm10Lsl2: return true;
3177
0
    case MCK_SImm10Lsl3: return true;
3178
0
    case MCK_SImm16: return true;
3179
0
    case MCK_SImm16_Relaxed: return true;
3180
0
    case MCK_UImm16_Relaxed: return true;
3181
0
    case MCK_ConstantUImm20_0: return true;
3182
0
    case MCK_ConstantUImm26_0: return true;
3183
0
    case MCK_SImm32: return true;
3184
0
    case MCK_SImm32_Relaxed: return true;
3185
0
    case MCK_UImm32_Coerced: return true;
3186
0
    }
3187
0
3188
0
  case MCK_ConstantUImm7_0:
3189
0
    switch (B) {
3190
0
    default: return false;
3191
0
    case MCK_UImm7_N1: return true;
3192
0
    case MCK_ConstantUImm8_0: return true;
3193
0
    case MCK_SImm7Lsl2: return true;
3194
0
    case MCK_ConstantSImm9_0: return true;
3195
0
    case MCK_ConstantSImm10_0: return true;
3196
0
    case MCK_ConstantUImm10_0: return true;
3197
0
    case MCK_SImm10Lsl1: return true;
3198
0
    case MCK_ConstantSImm11_0: return true;
3199
0
    case MCK_SImm10Lsl2: return true;
3200
0
    case MCK_SImm10Lsl3: return true;
3201
0
    case MCK_SImm16: return true;
3202
0
    case MCK_SImm16_Relaxed: return true;
3203
0
    case MCK_UImm16_Relaxed: return true;
3204
0
    case MCK_ConstantUImm20_0: return true;
3205
0
    case MCK_ConstantUImm26_0: return true;
3206
0
    case MCK_SImm32: return true;
3207
0
    case MCK_SImm32_Relaxed: return true;
3208
0
    case MCK_UImm32_Coerced: return true;
3209
0
    }
3210
0
3211
0
  case MCK_UImm7_N1:
3212
0
    switch (B) {
3213
0
    default: return false;
3214
0
    case MCK_ConstantUImm8_0: return true;
3215
0
    case MCK_SImm7Lsl2: return true;
3216
0
    case MCK_ConstantSImm9_0: return true;
3217
0
    case MCK_ConstantSImm10_0: return true;
3218
0
    case MCK_ConstantUImm10_0: return true;
3219
0
    case MCK_SImm10Lsl1: return true;
3220
0
    case MCK_ConstantSImm11_0: return true;
3221
0
    case MCK_SImm10Lsl2: return true;
3222
0
    case MCK_SImm10Lsl3: return true;
3223
0
    case MCK_SImm16: return true;
3224
0
    case MCK_SImm16_Relaxed: return true;
3225
0
    case MCK_UImm16_Relaxed: return true;
3226
0
    case MCK_ConstantUImm20_0: return true;
3227
0
    case MCK_ConstantUImm26_0: return true;
3228
0
    case MCK_SImm32: return true;
3229
0
    case MCK_SImm32_Relaxed: return true;
3230
0
    case MCK_UImm32_Coerced: return true;
3231
0
    }
3232
0
3233
0
  case MCK_ConstantUImm8_0:
3234
0
    switch (B) {
3235
0
    default: return false;
3236
0
    case MCK_SImm7Lsl2: return true;
3237
0
    case MCK_ConstantSImm9_0: return true;
3238
0
    case MCK_ConstantSImm10_0: return true;
3239
0
    case MCK_ConstantUImm10_0: return true;
3240
0
    case MCK_SImm10Lsl1: return true;
3241
0
    case MCK_ConstantSImm11_0: return true;
3242
0
    case MCK_SImm10Lsl2: return true;
3243
0
    case MCK_SImm10Lsl3: return true;
3244
0
    case MCK_SImm16: return true;
3245
0
    case MCK_SImm16_Relaxed: return true;
3246
0
    case MCK_UImm16_Relaxed: return true;
3247
0
    case MCK_ConstantUImm20_0: return true;
3248
0
    case MCK_ConstantUImm26_0: return true;
3249
0
    case MCK_SImm32: return true;
3250
0
    case MCK_SImm32_Relaxed: return true;
3251
0
    case MCK_UImm32_Coerced: return true;
3252
0
    }
3253
0
3254
0
  case MCK_SImm7Lsl2:
3255
0
    switch (B) {
3256
0
    default: return false;
3257
0
    case MCK_ConstantSImm9_0: return true;
3258
0
    case MCK_ConstantSImm10_0: return true;
3259
0
    case MCK_ConstantUImm10_0: return true;
3260
0
    case MCK_SImm10Lsl1: return true;
3261
0
    case MCK_ConstantSImm11_0: return true;
3262
0
    case MCK_SImm10Lsl2: return true;
3263
0
    case MCK_SImm10Lsl3: return true;
3264
0
    case MCK_SImm16: return true;
3265
0
    case MCK_SImm16_Relaxed: return true;
3266
0
    case MCK_UImm16_Relaxed: return true;
3267
0
    case MCK_ConstantUImm20_0: return true;
3268
0
    case MCK_ConstantUImm26_0: return true;
3269
0
    case MCK_SImm32: return true;
3270
0
    case MCK_SImm32_Relaxed: return true;
3271
0
    case MCK_UImm32_Coerced: return true;
3272
0
    }
3273
0
3274
0
  case MCK_ConstantSImm9_0:
3275
0
    switch (B) {
3276
0
    default: return false;
3277
0
    case MCK_ConstantSImm10_0: return true;
3278
0
    case MCK_ConstantUImm10_0: return true;
3279
0
    case MCK_SImm10Lsl1: return true;
3280
0
    case MCK_ConstantSImm11_0: return true;
3281
0
    case MCK_SImm10Lsl2: return true;
3282
0
    case MCK_SImm10Lsl3: return true;
3283
0
    case MCK_SImm16: return true;
3284
0
    case MCK_SImm16_Relaxed: return true;
3285
0
    case MCK_UImm16_Relaxed: return true;
3286
0
    case MCK_ConstantUImm20_0: return true;
3287
0
    case MCK_ConstantUImm26_0: return true;
3288
0
    case MCK_SImm32: return true;
3289
0
    case MCK_SImm32_Relaxed: return true;
3290
0
    case MCK_UImm32_Coerced: return true;
3291
0
    }
3292
0
3293
0
  case MCK_ConstantSImm10_0:
3294
0
    switch (B) {
3295
0
    default: return false;
3296
0
    case MCK_ConstantUImm10_0: return true;
3297
0
    case MCK_SImm10Lsl1: return true;
3298
0
    case MCK_ConstantSImm11_0: return true;
3299
0
    case MCK_SImm10Lsl2: return true;
3300
0
    case MCK_SImm10Lsl3: return true;
3301
0
    case MCK_SImm16: return true;
3302
0
    case MCK_SImm16_Relaxed: return true;
3303
0
    case MCK_UImm16_Relaxed: return true;
3304
0
    case MCK_ConstantUImm20_0: return true;
3305
0
    case MCK_ConstantUImm26_0: return true;
3306
0
    case MCK_SImm32: return true;
3307
0
    case MCK_SImm32_Relaxed: return true;
3308
0
    case MCK_UImm32_Coerced: return true;
3309
0
    }
3310
0
3311
10
  case MCK_ConstantUImm10_0:
3312
10
    switch (B) {
3313
10
    default: return false;
3314
10
    
case MCK_SImm10Lsl1: return true0
;
3315
10
    
case MCK_ConstantSImm11_0: return true0
;
3316
10
    
case MCK_SImm10Lsl2: return true0
;
3317
10
    
case MCK_SImm10Lsl3: return true0
;
3318
10
    
case MCK_SImm16: return true0
;
3319
10
    
case MCK_SImm16_Relaxed: return true0
;
3320
10
    
case MCK_UImm16_Relaxed: return true0
;
3321
10
    
case MCK_ConstantUImm20_0: return true0
;
3322
10
    
case MCK_ConstantUImm26_0: return true0
;
3323
10
    
case MCK_SImm32: return true0
;
3324
10
    
case MCK_SImm32_Relaxed: return true0
;
3325
10
    
case MCK_UImm32_Coerced: return true0
;
3326
0
    }
3327
0
3328
0
  case MCK_SImm10Lsl1:
3329
0
    switch (B) {
3330
0
    default: return false;
3331
0
    case MCK_ConstantSImm11_0: return true;
3332
0
    case MCK_SImm10Lsl2: return true;
3333
0
    case MCK_SImm10Lsl3: return true;
3334
0
    case MCK_SImm16: return true;
3335
0
    case MCK_SImm16_Relaxed: return true;
3336
0
    case MCK_UImm16_Relaxed: return true;
3337
0
    case MCK_ConstantUImm20_0: return true;
3338
0
    case MCK_ConstantUImm26_0: return true;
3339
0
    case MCK_SImm32: return true;
3340
0
    case MCK_SImm32_Relaxed: return true;
3341
0
    case MCK_UImm32_Coerced: return true;
3342
0
    }
3343
0
3344
0
  case MCK_ConstantSImm11_0:
3345
0
    switch (B) {
3346
0
    default: return false;
3347
0
    case MCK_SImm10Lsl2: return true;
3348
0
    case MCK_SImm10Lsl3: return true;
3349
0
    case MCK_SImm16: return true;
3350
0
    case MCK_SImm16_Relaxed: return true;
3351
0
    case MCK_UImm16_Relaxed: return true;
3352
0
    case MCK_ConstantUImm20_0: return true;
3353
0
    case MCK_ConstantUImm26_0: return true;
3354
0
    case MCK_SImm32: return true;
3355
0
    case MCK_SImm32_Relaxed: return true;
3356
0
    case MCK_UImm32_Coerced: return true;
3357
0
    }
3358
0
3359
0
  case MCK_SImm10Lsl2:
3360
0
    switch (B) {
3361
0
    default: return false;
3362
0
    case MCK_SImm10Lsl3: return true;
3363
0
    case MCK_SImm16: return true;
3364
0
    case MCK_SImm16_Relaxed: return true;
3365
0
    case MCK_UImm16_Relaxed: return true;
3366
0
    case MCK_ConstantUImm20_0: return true;
3367
0
    case MCK_ConstantUImm26_0: return true;
3368
0
    case MCK_SImm32: return true;
3369
0
    case MCK_SImm32_Relaxed: return true;
3370
0
    case MCK_UImm32_Coerced: return true;
3371
0
    }
3372
0
3373
0
  case MCK_SImm10Lsl3:
3374
0
    switch (B) {
3375
0
    default: return false;
3376
0
    case MCK_SImm16: return true;
3377
0
    case MCK_SImm16_Relaxed: return true;
3378
0
    case MCK_UImm16_Relaxed: return true;
3379
0
    case MCK_ConstantUImm20_0: return true;
3380
0
    case MCK_ConstantUImm26_0: return true;
3381
0
    case MCK_SImm32: return true;
3382
0
    case MCK_SImm32_Relaxed: return true;
3383
0
    case MCK_UImm32_Coerced: return true;
3384
0
    }
3385
0
3386
10
  case MCK_SImm16:
3387
10
    switch (B) {
3388
10
    default: return false;
3389
10
    
case MCK_SImm16_Relaxed: return true0
;
3390
10
    
case MCK_UImm16_Relaxed: return true0
;
3391
10
    
case MCK_ConstantUImm20_0: return true0
;
3392
10
    
case MCK_ConstantUImm26_0: return true0
;
3393
10
    
case MCK_SImm32: return true0
;
3394
10
    
case MCK_SImm32_Relaxed: return true0
;
3395
10
    
case MCK_UImm32_Coerced: return true0
;
3396
0
    }
3397
0
3398
0
  case MCK_SImm16_Relaxed:
3399
0
    switch (B) {
3400
0
    default: return false;
3401
0
    case MCK_UImm16_Relaxed: return true;
3402
0
    case MCK_ConstantUImm20_0: return true;
3403
0
    case MCK_ConstantUImm26_0: return true;
3404
0
    case MCK_SImm32: return true;
3405
0
    case MCK_SImm32_Relaxed: return true;
3406
0
    case MCK_UImm32_Coerced: return true;
3407
0
    }
3408
0
3409
0
  case MCK_UImm16_AltRelaxed:
3410
0
    switch (B) {
3411
0
    default: return false;
3412
0
    case MCK_UImm16_Relaxed: return true;
3413
0
    case MCK_ConstantUImm20_0: return true;
3414
0
    case MCK_ConstantUImm26_0: return true;
3415
0
    case MCK_SImm32: return true;
3416
0
    case MCK_SImm32_Relaxed: return true;
3417
0
    case MCK_UImm32_Coerced: return true;
3418
0
    }
3419
0
3420
0
  case MCK_UImm16:
3421
0
    switch (B) {
3422
0
    default: return false;
3423
0
    case MCK_UImm16_Relaxed: return true;
3424
0
    case MCK_ConstantUImm20_0: return true;
3425
0
    case MCK_ConstantUImm26_0: return true;
3426
0
    case MCK_SImm32: return true;
3427
0
    case MCK_SImm32_Relaxed: return true;
3428
0
    case MCK_UImm32_Coerced: return true;
3429
0
    }
3430
0
3431
0
  case MCK_SImm19Lsl2:
3432
0
    switch (B) {
3433
0
    default: return false;
3434
0
    case MCK_ConstantUImm20_0: return true;
3435
0
    case MCK_ConstantUImm26_0: return true;
3436
0
    case MCK_SImm32: return true;
3437
0
    case MCK_SImm32_Relaxed: return true;
3438
0
    case MCK_UImm32_Coerced: return true;
3439
0
    }
3440
0
3441
0
  case MCK_UImm16_Relaxed:
3442
0
    switch (B) {
3443
0
    default: return false;
3444
0
    case MCK_ConstantUImm20_0: return true;
3445
0
    case MCK_ConstantUImm26_0: return true;
3446
0
    case MCK_SImm32: return true;
3447
0
    case MCK_SImm32_Relaxed: return true;
3448
0
    case MCK_UImm32_Coerced: return true;
3449
0
    }
3450
0
3451
0
  case MCK_ConstantUImm20_0:
3452
0
    switch (B) {
3453
0
    default: return false;
3454
0
    case MCK_ConstantUImm26_0: return true;
3455
0
    case MCK_SImm32: return true;
3456
0
    case MCK_SImm32_Relaxed: return true;
3457
0
    case MCK_UImm32_Coerced: return true;
3458
0
    }
3459
0
3460
0
  case MCK_ConstantUImm26_0:
3461
0
    switch (B) {
3462
0
    default: return false;
3463
0
    case MCK_SImm32: return true;
3464
0
    case MCK_SImm32_Relaxed: return true;
3465
0
    case MCK_UImm32_Coerced: return true;
3466
0
    }
3467
0
3468
0
  case MCK_SImm32:
3469
0
    switch (B) {
3470
0
    default: return false;
3471
0
    case MCK_SImm32_Relaxed: return true;
3472
0
    case MCK_UImm32_Coerced: return true;
3473
0
    }
3474
0
3475
0
  case MCK_SImm32_Relaxed:
3476
0
    return B == MCK_UImm32_Coerced;
3477
38.6k
  }
3478
38.6k
}
3479
3480
163k
static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
3481
163k
  MipsOperand &Operand = (MipsOperand&)GOp;
3482
163k
  if (Kind == InvalidMatchClass)
3483
5.07k
    return MCTargetAsmParser::Match_InvalidOperand;
3484
158k
3485
158k
  if (Operand.isToken() && 
Kind <= MCK_LAST_TOKEN880
)
3486
880
    return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
3487
880
             MCTargetAsmParser::Match_Success :
3488
880
             
MCTargetAsmParser::Match_InvalidOperand0
;
3489
157k
3490
157k
  switch (Kind) {
3491
157k
  
default: break14.5k
;
3492
157k
  // 'ACC64DSPAsmReg' class
3493
157k
  case MCK_ACC64DSPAsmReg: {
3494
571
    DiagnosticPredicate DP(Operand.isACCAsmReg());
3495
571
    if (DP.isMatch())
3496
420
      return MCTargetAsmParser::Match_Success;
3497
151
    break;
3498
151
    }
3499
151
  // 'AFGR64AsmReg' class
3500
4.72k
  case MCK_AFGR64AsmReg: {
3501
4.72k
    DiagnosticPredicate DP(Operand.isFGRAsmReg());
3502
4.72k
    if (DP.isMatch())
3503
4.22k
      return MCTargetAsmParser::Match_Success;
3504
498
    break;
3505
498
    }
3506
498
  // 'CCRAsmReg' class
3507
498
  case MCK_CCRAsmReg: {
3508
46
    DiagnosticPredicate DP(Operand.isCCRAsmReg());
3509
46
    if (DP.isMatch())
3510
46
      return MCTargetAsmParser::Match_Success;
3511
0
    break;
3512
0
    }
3513
0
  // 'COP0AsmReg' class
3514
680
  case MCK_COP0AsmReg: {
3515
680
    DiagnosticPredicate DP(Operand.isCOP0AsmReg());
3516
680
    if (DP.isMatch())
3517
548
      return MCTargetAsmParser::Match_Success;
3518
132
    break;
3519
132
    }
3520
132
  // 'COP2AsmReg' class
3521
566
  case MCK_COP2AsmReg: {
3522
566
    DiagnosticPredicate DP(Operand.isCOP2AsmReg());
3523
566
    if (DP.isMatch())
3524
564
      return MCTargetAsmParser::Match_Success;
3525
2
    break;
3526
2
    }
3527
2
  // 'COP3AsmReg' class
3528
16
  case MCK_COP3AsmReg: {
3529
16
    DiagnosticPredicate DP(Operand.isCOP3AsmReg());
3530
16
    if (DP.isMatch())
3531
16
      return MCTargetAsmParser::Match_Success;
3532
0
    break;
3533
0
    }
3534
0
  // 'FCCAsmReg' class
3535
2.07k
  case MCK_FCCAsmReg: {
3536
2.07k
    DiagnosticPredicate DP(Operand.isFCCAsmReg());
3537
2.07k
    if (DP.isMatch())
3538
1.65k
      return MCTargetAsmParser::Match_Success;
3539
418
    break;
3540
418
    }
3541
418
  // 'FGR32AsmReg' class
3542
6.78k
  case MCK_FGR32AsmReg: {
3543
6.78k
    DiagnosticPredicate DP(Operand.isFGRAsmReg());
3544
6.78k
    if (DP.isMatch())
3545
6.24k
      return MCTargetAsmParser::Match_Success;
3546
545
    break;
3547
545
    }
3548
545
  // 'FGR64AsmReg' class
3549
4.32k
  case MCK_FGR64AsmReg: {
3550
4.32k
    DiagnosticPredicate DP(Operand.isFGRAsmReg());
3551
4.32k
    if (DP.isMatch())
3552
3.82k
      return MCTargetAsmParser::Match_Success;
3553
500
    break;
3554
500
    }
3555
500
  // 'FGRH32AsmReg' class
3556
500
  case MCK_FGRH32AsmReg: {
3557
0
    DiagnosticPredicate DP(Operand.isFGRAsmReg());
3558
0
    if (DP.isMatch())
3559
0
      return MCTargetAsmParser::Match_Success;
3560
0
    break;
3561
0
    }
3562
0
  // 'GPR32AsmReg' class
3563
66.1k
  case MCK_GPR32AsmReg: {
3564
66.1k
    DiagnosticPredicate DP(Operand.isGPRAsmReg());
3565
66.1k
    if (DP.isMatch())
3566
62.4k
      return MCTargetAsmParser::Match_Success;
3567
3.71k
    break;
3568
3.71k
    }
3569
3.71k
  // 'GPR32NonZeroAsmReg' class
3570
3.71k
  case MCK_GPR32NonZeroAsmReg: {
3571
130
    DiagnosticPredicate DP(Operand.isGPRNonZeroAsmReg());
3572
130
    if (DP.isMatch())
3573
76
      return MCTargetAsmParser::Match_Success;
3574
54
    break;
3575
54
    }
3576
54
  // 'GPR32ZeroAsmReg' class
3577
100
  case MCK_GPR32ZeroAsmReg: {
3578
100
    DiagnosticPredicate DP(Operand.isGPRZeroAsmReg());
3579
100
    if (DP.isMatch())
3580
54
      return MCTargetAsmParser::Match_Success;
3581
46
    break;
3582
46
    }
3583
46
  // 'GPR64AsmReg' class
3584
8.34k
  case MCK_GPR64AsmReg: {
3585
8.34k
    DiagnosticPredicate DP(Operand.isGPRAsmReg());
3586
8.34k
    if (DP.isMatch())
3587
7.88k
      return MCTargetAsmParser::Match_Success;
3588
461
    break;
3589
461
    }
3590
461
  // 'GPRMM16AsmReg' class
3591
461
  case MCK_GPRMM16AsmReg: {
3592
269
    DiagnosticPredicate DP(Operand.isMM16AsmReg());
3593
269
    if (DP.isMatch())
3594
234
      return MCTargetAsmParser::Match_Success;
3595
35
    break;
3596
35
    }
3597
35
  // 'GPRMM16AsmRegMoveP' class
3598
35
  case MCK_GPRMM16AsmRegMoveP: {
3599
28
    DiagnosticPredicate DP(Operand.isMM16AsmRegMoveP());
3600
28
    if (DP.isMatch())
3601
20
      return MCTargetAsmParser::Match_Success;
3602
8
    break;
3603
8
    }
3604
8
  // 'GPRMM16AsmRegMovePPairFirst' class
3605
20
  case MCK_GPRMM16AsmRegMovePPairFirst: {
3606
20
    DiagnosticPredicate DP(Operand.isMM16AsmRegMovePPairFirst());
3607
20
    if (DP.isMatch())
3608
16
      return MCTargetAsmParser::Match_Success;
3609
4
    break;
3610
4
    }
3611
4
  // 'GPRMM16AsmRegMovePPairSecond' class
3612
16
  case MCK_GPRMM16AsmRegMovePPairSecond: {
3613
16
    DiagnosticPredicate DP(Operand.isMM16AsmRegMovePPairSecond());
3614
16
    if (DP.isMatch())
3615
16
      return MCTargetAsmParser::Match_Success;
3616
0
    break;
3617
0
    }
3618
0
  // 'GPRMM16AsmRegZero' class
3619
65
  case MCK_GPRMM16AsmRegZero: {
3620
65
    DiagnosticPredicate DP(Operand.isMM16AsmRegZero());
3621
65
    if (DP.isMatch())
3622
41
      return MCTargetAsmParser::Match_Success;
3623
24
    break;
3624
24
    }
3625
24
  // 'HI32DSPAsmReg' class
3626
24
  case MCK_HI32DSPAsmReg: {
3627
9
    DiagnosticPredicate DP(Operand.isACCAsmReg());
3628
9
    if (DP.isMatch())
3629
9
      return MCTargetAsmParser::Match_Success;
3630
0
    break;
3631
0
    }
3632
0
  // 'HWRegsAsmReg' class
3633
85
  case MCK_HWRegsAsmReg: {
3634
85
    DiagnosticPredicate DP(Operand.isHWRegsAsmReg());
3635
85
    if (DP.isMatch())
3636
85
      return MCTargetAsmParser::Match_Success;
3637
0
    break;
3638
0
    }
3639
0
  // 'Imm' class
3640
2.96k
  case MCK_Imm: {
3641
2.96k
    DiagnosticPredicate DP(Operand.isImm());
3642
2.96k
    if (DP.isMatch())
3643
1.94k
      return MCTargetAsmParser::Match_Success;
3644
1.01k
    break;
3645
1.01k
    }
3646
1.01k
  // 'LO32DSPAsmReg' class
3647
1.01k
  case MCK_LO32DSPAsmReg: {
3648
9
    DiagnosticPredicate DP(Operand.isACCAsmReg());
3649
9
    if (DP.isMatch())
3650
9
      return MCTargetAsmParser::Match_Success;
3651
0
    break;
3652
0
    }
3653
0
  // 'MSA128AsmReg' class
3654
2.13k
  case MCK_MSA128AsmReg: {
3655
2.13k
    DiagnosticPredicate DP(Operand.isMSA128AsmReg());
3656
2.13k
    if (DP.isMatch())
3657
2.13k
      return MCTargetAsmParser::Match_Success;
3658
0
    break;
3659
0
    }
3660
0
  // 'MSACtrlAsmReg' class
3661
38
  case MCK_MSACtrlAsmReg: {
3662
38
    DiagnosticPredicate DP(Operand.isMSACtrlAsmReg());
3663
38
    if (DP.isMatch())
3664
32
      return MCTargetAsmParser::Match_Success;
3665
6
    break;
3666
6
    }
3667
6
  // 'MicroMipsMemGP' class
3668
6
  case MCK_MicroMipsMemGP: {
3669
0
    DiagnosticPredicate DP(Operand.isMemWithSimmWordAlignedOffsetGP<9>());
3670
0
    if (DP.isMatch())
3671
0
      return MCTargetAsmParser::Match_Success;
3672
0
    break;
3673
0
    }
3674
0
  // 'MicroMipsMem' class
3675
75
  case MCK_MicroMipsMem: {
3676
75
    DiagnosticPredicate DP(Operand.isMemWithGRPMM16Base());
3677
75
    if (DP.isMatch())
3678
57
      return MCTargetAsmParser::Match_Success;
3679
18
    break;
3680
18
    }
3681
18
  // 'MicroMipsMemSP' class
3682
10.4k
  case MCK_MicroMipsMemSP: {
3683
10.4k
    DiagnosticPredicate DP(Operand.isMemWithUimmWordAlignedOffsetSP<7>());
3684
10.4k
    if (DP.isMatch())
3685
57
      return MCTargetAsmParser::Match_Success;
3686
10.4k
    break;
3687
10.4k
    }
3688
10.4k
  // 'InvNum' class
3689
10.4k
  case MCK_InvNum: {
3690
245
    DiagnosticPredicate DP(Operand.isInvNum());
3691
245
    if (DP.isMatch())
3692
106
      return MCTargetAsmParser::Match_Success;
3693
139
    break;
3694
139
    }
3695
139
  // 'JumpTarget' class
3696
2.57k
  case MCK_JumpTarget: {
3697
2.57k
    DiagnosticPredicate DP(Operand.isImm());
3698
2.57k
    if (DP.isMatch())
3699
2.26k
      return MCTargetAsmParser::Match_Success;
3700
314
    break;
3701
314
    }
3702
314
  // 'MemOffsetSimm10' class
3703
314
  case MCK_MemOffsetSimm10: {
3704
7
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10>());
3705
7
    if (DP.isMatch())
3706
3
      return MCTargetAsmParser::Match_Success;
3707
4
    if (DP.isNearMatch())
3708
4
      return MipsAsmParser::Match_MemSImm10;
3709
0
    break;
3710
0
    }
3711
0
  // 'MemOffsetSimm10_1' class
3712
9
  case MCK_MemOffsetSimm10_1: {
3713
9
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 1>());
3714
9
    if (DP.isMatch())
3715
5
      return MCTargetAsmParser::Match_Success;
3716
4
    if (DP.isNearMatch())
3717
4
      return MipsAsmParser::Match_MemSImm10Lsl1;
3718
0
    break;
3719
0
    }
3720
0
  // 'MemOffsetSimm10_2' class
3721
10
  case MCK_MemOffsetSimm10_2: {
3722
10
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 2>());
3723
10
    if (DP.isMatch())
3724
6
      return MCTargetAsmParser::Match_Success;
3725
4
    if (DP.isNearMatch())
3726
4
      return MipsAsmParser::Match_MemSImm10Lsl2;
3727
0
    break;
3728
0
    }
3729
0
  // 'MemOffsetSimm10_3' class
3730
13
  case MCK_MemOffsetSimm10_3: {
3731
13
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 3>());
3732
13
    if (DP.isMatch())
3733
9
      return MCTargetAsmParser::Match_Success;
3734
4
    if (DP.isNearMatch())
3735
4
      return MipsAsmParser::Match_MemSImm10Lsl3;
3736
0
    break;
3737
0
    }
3738
0
  // 'MemOffsetSimm11' class
3739
304
  case MCK_MemOffsetSimm11: {
3740
304
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<11>());
3741
304
    if (DP.isMatch())
3742
58
      return MCTargetAsmParser::Match_Success;
3743
246
    if (DP.isNearMatch())
3744
246
      return MipsAsmParser::Match_MemSImm11;
3745
0
    break;
3746
0
    }
3747
0
  // 'MemOffsetSimm12' class
3748
40
  case MCK_MemOffsetSimm12: {
3749
40
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<12>());
3750
40
    if (DP.isMatch())
3751
25
      return MCTargetAsmParser::Match_Success;
3752
15
    if (DP.isNearMatch())
3753
15
      return MipsAsmParser::Match_MemSImm12;
3754
0
    break;
3755
0
    }
3756
0
  // 'MemOffsetSimm16' class
3757
977
  case MCK_MemOffsetSimm16: {
3758
977
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<16>());
3759
977
    if (DP.isMatch())
3760
690
      return MCTargetAsmParser::Match_Success;
3761
287
    if (DP.isNearMatch())
3762
287
      return MipsAsmParser::Match_MemSImm16;
3763
0
    break;
3764
0
    }
3765
0
  // 'MemOffsetSimm9' class
3766
1.83k
  case MCK_MemOffsetSimm9: {
3767
1.83k
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<9>());
3768
1.83k
    if (DP.isMatch())
3769
586
      return MCTargetAsmParser::Match_Success;
3770
1.25k
    if (DP.isNearMatch())
3771
1.25k
      return MipsAsmParser::Match_MemSImm9;
3772
0
    break;
3773
0
    }
3774
0
  // 'MemOffsetSimmPtr' class
3775
381
  case MCK_MemOffsetSimmPtr: {
3776
381
    DiagnosticPredicate DP(Operand.isMemWithPtrSizeOffset());
3777
381
    if (DP.isMatch())
3778
335
      return MCTargetAsmParser::Match_Success;
3779
46
    if (DP.isNearMatch())
3780
46
      return MipsAsmParser::Match_MemSImmPtr;
3781
0
    break;
3782
0
    }
3783
0
  // 'MemOffsetUimm4' class
3784
18
  case MCK_MemOffsetUimm4: {
3785
18
    DiagnosticPredicate DP(Operand.isMemWithUimmOffsetSP<6>());
3786
18
    if (DP.isMatch())
3787
10
      return MCTargetAsmParser::Match_Success;
3788
8
    break;
3789
8
    }
3790
8
  // 'Mem' class
3791
12.0k
  case MCK_Mem: {
3792
12.0k
    DiagnosticPredicate DP(Operand.isMem());
3793
12.0k
    if (DP.isMatch())
3794
11.8k
      return MCTargetAsmParser::Match_Success;
3795
148
    break;
3796
148
    }
3797
148
  // 'RegList16' class
3798
148
  case MCK_RegList16: {
3799
36
    DiagnosticPredicate DP(Operand.isRegList16());
3800
36
    if (DP.isMatch())
3801
18
      return MCTargetAsmParser::Match_Success;
3802
18
    break;
3803
18
    }
3804
18
  // 'RegList' class
3805
55
  case MCK_RegList: {
3806
55
    DiagnosticPredicate DP(Operand.isRegList());
3807
55
    if (DP.isMatch())
3808
55
      return MCTargetAsmParser::Match_Success;
3809
0
    break;
3810
0
    }
3811
0
  // 'Simm19_Lsl2' class
3812
94
  case MCK_Simm19_Lsl2: {
3813
94
    DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>());
3814
94
    if (DP.isMatch())
3815
52
      return MCTargetAsmParser::Match_Success;
3816
42
    if (DP.isNearMatch())
3817
42
      return MipsAsmParser::Match_SImm19_Lsl2;
3818
0
    break;
3819
0
    }
3820
0
  // 'StrictlyAFGR64AsmReg' class
3821
91
  case MCK_StrictlyAFGR64AsmReg: {
3822
91
    DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
3823
91
    if (DP.isMatch())
3824
91
      return MCTargetAsmParser::Match_Success;
3825
0
    break;
3826
0
    }
3827
0
  // 'StrictlyFGR32AsmReg' class
3828
66
  case MCK_StrictlyFGR32AsmReg: {
3829
66
    DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
3830
66
    if (DP.isMatch())
3831
66
      return MCTargetAsmParser::Match_Success;
3832
0
    break;
3833
0
    }
3834
0
  // 'StrictlyFGR64AsmReg' class
3835
52
  case MCK_StrictlyFGR64AsmReg: {
3836
52
    DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
3837
52
    if (DP.isMatch())
3838
52
      return MCTargetAsmParser::Match_Success;
3839
0
    break;
3840
0
    }
3841
0
  // 'ConstantImmz' class
3842
12
  case MCK_ConstantImmz: {
3843
12
    DiagnosticPredicate DP(Operand.isConstantImmz());
3844
12
    if (DP.isMatch())
3845
4
      return MCTargetAsmParser::Match_Success;
3846
8
    if (DP.isNearMatch())
3847
8
      return MipsAsmParser::Match_Immz;
3848
0
    break;
3849
0
    }
3850
0
  // 'ConstantUImm1_0' class
3851
69
  case MCK_ConstantUImm1_0: {
3852
69
    DiagnosticPredicate DP(Operand.isConstantUImm<1, 0>());
3853
69
    if (DP.isMatch())
3854
55
      return MCTargetAsmParser::Match_Success;
3855
14
    if (DP.isNearMatch())
3856
14
      return MipsAsmParser::Match_UImm1_0;
3857
0
    break;
3858
0
    }
3859
0
  // 'ConstantUImm2_0' class
3860
85
  case MCK_ConstantUImm2_0: {
3861
85
    DiagnosticPredicate DP(Operand.isConstantUImm<2, 0>());
3862
85
    if (DP.isMatch())
3863
31
      return MCTargetAsmParser::Match_Success;
3864
54
    if (DP.isNearMatch())
3865
54
      return MipsAsmParser::Match_UImm2_0;
3866
0
    break;
3867
0
    }
3868
0
  // 'ConstantUImm2_1' class
3869
56
  case MCK_ConstantUImm2_1: {
3870
56
    DiagnosticPredicate DP(Operand.isConstantUImm<2, 1>());
3871
56
    if (DP.isMatch())
3872
18
      return MCTargetAsmParser::Match_Success;
3873
38
    if (DP.isNearMatch())
3874
38
      return MipsAsmParser::Match_UImm2_1;
3875
0
    break;
3876
0
    }
3877
0
  // 'ConstantUImm3_0' class
3878
410
  case MCK_ConstantUImm3_0: {
3879
410
    DiagnosticPredicate DP(Operand.isConstantUImm<3, 0>());
3880
410
    if (DP.isMatch())
3881
229
      return MCTargetAsmParser::Match_Success;
3882
181
    if (DP.isNearMatch())
3883
181
      return MipsAsmParser::Match_UImm3_0;
3884
0
    break;
3885
0
    }
3886
0
  // 'ConstantSImm4_0' class
3887
8
  case MCK_ConstantSImm4_0: {
3888
8
    DiagnosticPredicate DP(Operand.isConstantSImm<4, 0>());
3889
8
    if (DP.isMatch())
3890
4
      return MCTargetAsmParser::Match_Success;
3891
4
    if (DP.isNearMatch())
3892
4
      return MipsAsmParser::Match_SImm4_0;
3893
0
    break;
3894
0
    }
3895
0
  // 'ConstantUImm4_0' class
3896
291
  case MCK_ConstantUImm4_0: {
3897
291
    DiagnosticPredicate DP(Operand.isConstantUImm<4, 0>());
3898
291
    if (DP.isMatch())
3899
81
      return MCTargetAsmParser::Match_Success;
3900
210
    if (DP.isNearMatch())
3901
210
      return MipsAsmParser::Match_UImm4_0;
3902
0
    break;
3903
0
    }
3904
0
  // 'ConstantSImm5_0' class
3905
60
  case MCK_ConstantSImm5_0: {
3906
60
    DiagnosticPredicate DP(Operand.isConstantSImm<5, 0>());
3907
60
    if (DP.isMatch())
3908
20
      return MCTargetAsmParser::Match_Success;
3909
40
    if (DP.isNearMatch())
3910
40
      return MipsAsmParser::Match_SImm5_0;
3911
0
    break;
3912
0
    }
3913
0
  // 'ConstantUImm5_0' class
3914
2.09k
  case MCK_ConstantUImm5_0: {
3915
2.09k
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>());
3916
2.09k
    if (DP.isMatch())
3917
869
      return MCTargetAsmParser::Match_Success;
3918
1.22k
    if (DP.isNearMatch())
3919
1.22k
      return MipsAsmParser::Match_UImm5_0;
3920
0
    break;
3921
0
    }
3922
0
  // 'ConstantUImm5_1' class
3923
129
  case MCK_ConstantUImm5_1: {
3924
129
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>());
3925
129
    if (DP.isMatch())
3926
79
      return MCTargetAsmParser::Match_Success;
3927
50
    if (DP.isNearMatch())
3928
50
      return MipsAsmParser::Match_UImm5_1;
3929
0
    break;
3930
0
    }
3931
0
  // 'ConstantUImm5_Plus1_Report_UImm6' class
3932
11
  case MCK_ConstantUImm5_Plus1_Report_UImm6: {
3933
11
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>());
3934
11
    if (DP.isMatch())
3935
9
      return MCTargetAsmParser::Match_Success;
3936
2
    if (DP.isNearMatch())
3937
2
      return MipsAsmParser::Match_UImm5_1;
3938
0
    break;
3939
0
    }
3940
0
  // 'ConstantUImm5_32_Norm' class
3941
16
  case MCK_ConstantUImm5_32_Norm: {
3942
16
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>());
3943
16
    if (DP.isMatch())
3944
6
      return MCTargetAsmParser::Match_Success;
3945
10
    if (DP.isNearMatch())
3946
10
      return MipsAsmParser::Match_UImm5_32;
3947
0
    break;
3948
0
    }
3949
0
  // 'ConstantUImm5_32' class
3950
76
  case MCK_ConstantUImm5_32: {
3951
76
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>());
3952
76
    if (DP.isMatch())
3953
34
      return MCTargetAsmParser::Match_Success;
3954
42
    if (DP.isNearMatch())
3955
42
      return MipsAsmParser::Match_UImm5_32;
3956
0
    break;
3957
0
    }
3958
0
  // 'ConstantUImm5_0_Report_UImm6' class
3959
23
  case MCK_ConstantUImm5_0_Report_UImm6: {
3960
23
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>());
3961
23
    if (DP.isMatch())
3962
13
      return MCTargetAsmParser::Match_Success;
3963
10
    if (DP.isNearMatch())
3964
10
      return MipsAsmParser::Match_UImm5_0_Report_UImm6;
3965
0
    break;
3966
0
    }
3967
0
  // 'ConstantUImm5_33' class
3968
26
  case MCK_ConstantUImm5_33: {
3969
26
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 33>());
3970
26
    if (DP.isMatch())
3971
11
      return MCTargetAsmParser::Match_Success;
3972
15
    if (DP.isNearMatch())
3973
15
      return MipsAsmParser::Match_UImm5_33;
3974
0
    break;
3975
0
    }
3976
0
  // 'ConstantUImmRange2_64' class
3977
28
  case MCK_ConstantUImmRange2_64: {
3978
28
    DiagnosticPredicate DP(Operand.isConstantUImmRange<2, 64>());
3979
28
    if (DP.isMatch())
3980
18
      return MCTargetAsmParser::Match_Success;
3981
10
    if (DP.isNearMatch())
3982
10
      return MipsAsmParser::Match_UImmRange2_64;
3983
0
    break;
3984
0
    }
3985
0
  // 'UImm5Lsl2' class
3986
26
  case MCK_UImm5Lsl2: {
3987
26
    DiagnosticPredicate DP(Operand.isScaledUImm<5, 2>());
3988
26
    if (DP.isMatch())
3989
4
      return MCTargetAsmParser::Match_Success;
3990
22
    if (DP.isNearMatch())
3991
22
      return MipsAsmParser::Match_UImm5_Lsl2;
3992
0
    break;
3993
0
    }
3994
0
  // 'ConstantSImm6_0' class
3995
22
  case MCK_ConstantSImm6_0: {
3996
22
    DiagnosticPredicate DP(Operand.isConstantSImm<6, 0>());
3997
22
    if (DP.isMatch())
3998
14
      return MCTargetAsmParser::Match_Success;
3999
8
    if (DP.isNearMatch())
4000
8
      return MipsAsmParser::Match_SImm6_0;
4001
0
    break;
4002
0
    }
4003
0
  // 'ConstantUImm6_0' class
4004
302
  case MCK_ConstantUImm6_0: {
4005
302
    DiagnosticPredicate DP(Operand.isConstantUImm<6, 0>());
4006
302
    if (DP.isMatch())
4007
119
      return MCTargetAsmParser::Match_Success;
4008
183
    if (DP.isNearMatch())
4009
183
      return MipsAsmParser::Match_UImm6_0;
4010
0
    break;
4011
0
    }
4012
0
  // 'UImm6Lsl2' class
4013
10
  case MCK_UImm6Lsl2: {
4014
10
    DiagnosticPredicate DP(Operand.isScaledUImm<6, 2>());
4015
10
    if (DP.isMatch())
4016
4
      return MCTargetAsmParser::Match_Success;
4017
6
    if (DP.isNearMatch())
4018
6
      return MipsAsmParser::Match_UImm6_Lsl2;
4019
0
    break;
4020
0
    }
4021
0
  // 'ConstantUImm7_0' class
4022
19
  case MCK_ConstantUImm7_0: {
4023
19
    DiagnosticPredicate DP(Operand.isConstantUImm<7, 0>());
4024
19
    if (DP.isMatch())
4025
11
      return MCTargetAsmParser::Match_Success;
4026
8
    if (DP.isNearMatch())
4027
8
      return MipsAsmParser::Match_UImm7_0;
4028
0
    break;
4029
0
    }
4030
0
  // 'UImm7_N1' class
4031
16
  case MCK_UImm7_N1: {
4032
16
    DiagnosticPredicate DP(Operand.isConstantUImm<7, -1>());
4033
16
    if (DP.isMatch())
4034
8
      return MCTargetAsmParser::Match_Success;
4035
8
    if (DP.isNearMatch())
4036
8
      return MipsAsmParser::Match_UImm7_N1;
4037
0
    break;
4038
0
    }
4039
0
  // 'ConstantUImm8_0' class
4040
46
  case MCK_ConstantUImm8_0: {
4041
46
    DiagnosticPredicate DP(Operand.isConstantUImm<8, 0>());
4042
46
    if (DP.isMatch())
4043
19
      return MCTargetAsmParser::Match_Success;
4044
27
    if (DP.isNearMatch())
4045
27
      return MipsAsmParser::Match_UImm8_0;
4046
0
    break;
4047
0
    }
4048
0
  // 'SImm7Lsl2' class
4049
0
  case MCK_SImm7Lsl2: {
4050
0
    DiagnosticPredicate DP(Operand.isScaledSImm<7, 2>());
4051
0
    if (DP.isMatch())
4052
0
      return MCTargetAsmParser::Match_Success;
4053
0
    if (DP.isNearMatch())
4054
0
      return MipsAsmParser::Match_SImm7_Lsl2;
4055
0
    break;
4056
0
    }
4057
0
  // 'ConstantSImm9_0' class
4058
0
  case MCK_ConstantSImm9_0: {
4059
0
    DiagnosticPredicate DP(Operand.isConstantSImm<9, 0>());
4060
0
    if (DP.isMatch())
4061
0
      return MCTargetAsmParser::Match_Success;
4062
0
    if (DP.isNearMatch())
4063
0
      return MipsAsmParser::Match_SImm9_0;
4064
0
    break;
4065
0
    }
4066
0
  // 'ConstantSImm10_0' class
4067
44
  case MCK_ConstantSImm10_0: {
4068
44
    DiagnosticPredicate DP(Operand.isConstantSImm<10, 0>());
4069
44
    if (DP.isMatch())
4070
18
      return MCTargetAsmParser::Match_Success;
4071
26
    if (DP.isNearMatch())
4072
26
      return MipsAsmParser::Match_SImm10_0;
4073
0
    break;
4074
0
    }
4075
0
  // 'ConstantUImm10_0' class
4076
470
  case MCK_ConstantUImm10_0: {
4077
470
    DiagnosticPredicate DP(Operand.isConstantUImm<10, 0>());
4078
470
    if (DP.isMatch())
4079
258
      return MCTargetAsmParser::Match_Success;
4080
212
    if (DP.isNearMatch())
4081
212
      return MipsAsmParser::Match_UImm10_0;
4082
0
    break;
4083
0
    }
4084
0
  // 'SImm10Lsl1' class
4085
0
  case MCK_SImm10Lsl1: {
4086
0
    DiagnosticPredicate DP(Operand.isScaledSImm<10, 1>());
4087
0
    if (DP.isMatch())
4088
0
      return MCTargetAsmParser::Match_Success;
4089
0
    if (DP.isNearMatch())
4090
0
      return MipsAsmParser::Match_SImm10_Lsl1;
4091
0
    break;
4092
0
    }
4093
0
  // 'ConstantSImm11_0' class
4094
0
  case MCK_ConstantSImm11_0: {
4095
0
    DiagnosticPredicate DP(Operand.isConstantSImm<11, 0>());
4096
0
    if (DP.isMatch())
4097
0
      return MCTargetAsmParser::Match_Success;
4098
0
    if (DP.isNearMatch())
4099
0
      return MipsAsmParser::Match_SImm11_0;
4100
0
    break;
4101
0
    }
4102
0
  // 'SImm10Lsl2' class
4103
0
  case MCK_SImm10Lsl2: {
4104
0
    DiagnosticPredicate DP(Operand.isScaledSImm<10, 2>());
4105
0
    if (DP.isMatch())
4106
0
      return MCTargetAsmParser::Match_Success;
4107
0
    if (DP.isNearMatch())
4108
0
      return MipsAsmParser::Match_SImm10_Lsl2;
4109
0
    break;
4110
0
    }
4111
0
  // 'SImm10Lsl3' class
4112
0
  case MCK_SImm10Lsl3: {
4113
0
    DiagnosticPredicate DP(Operand.isScaledSImm<10, 3>());
4114
0
    if (DP.isMatch())
4115
0
      return MCTargetAsmParser::Match_Success;
4116
0
    if (DP.isNearMatch())
4117
0
      return MipsAsmParser::Match_SImm10_Lsl3;
4118
0
    break;
4119
0
    }
4120
0
  // 'SImm16' class
4121
3.76k
  case MCK_SImm16: {
4122
3.76k
    DiagnosticPredicate DP(Operand.isSImm<16>());
4123
3.76k
    if (DP.isMatch())
4124
2.06k
      return MCTargetAsmParser::Match_Success;
4125
1.69k
    if (DP.isNearMatch())
4126
1.69k
      return MipsAsmParser::Match_SImm16;
4127
0
    break;
4128
0
    }
4129
0
  // 'SImm16_Relaxed' class
4130
1.14k
  case MCK_SImm16_Relaxed: {
4131
1.14k
    DiagnosticPredicate DP(Operand.isAnyImm<16>());
4132
1.14k
    if (DP.isMatch())
4133
519
      return MCTargetAsmParser::Match_Success;
4134
622
    if (DP.isNearMatch())
4135
622
      return MipsAsmParser::Match_SImm16_Relaxed;
4136
0
    break;
4137
0
    }
4138
0
  // 'UImm16_AltRelaxed' class
4139
11
  case MCK_UImm16_AltRelaxed: {
4140
11
    DiagnosticPredicate DP(Operand.isUImm<16>());
4141
11
    if (DP.isMatch())
4142
6
      return MCTargetAsmParser::Match_Success;
4143
5
    if (DP.isNearMatch())
4144
5
      return MipsAsmParser::Match_UImm16_AltRelaxed;
4145
0
    break;
4146
0
    }
4147
0
  // 'UImm16' class
4148
917
  case MCK_UImm16: {
4149
917
    DiagnosticPredicate DP(Operand.isUImm<16>());
4150
917
    if (DP.isMatch())
4151
361
      return MCTargetAsmParser::Match_Success;
4152
556
    if (DP.isNearMatch())
4153
556
      return MipsAsmParser::Match_UImm16;
4154
0
    break;
4155
0
    }
4156
0
  // 'SImm19Lsl2' class
4157
0
  case MCK_SImm19Lsl2: {
4158
0
    DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>());
4159
0
    if (DP.isMatch())
4160
0
      return MCTargetAsmParser::Match_Success;
4161
0
    if (DP.isNearMatch())
4162
0
      return MipsAsmParser::Match_SImm19_Lsl2;
4163
0
    break;
4164
0
    }
4165
0
  // 'UImm16_Relaxed' class
4166
225
  case MCK_UImm16_Relaxed: {
4167
225
    DiagnosticPredicate DP(Operand.isAnyImm<16>());
4168
225
    if (DP.isMatch())
4169
225
      return MCTargetAsmParser::Match_Success;
4170
0
    if (DP.isNearMatch())
4171
0
      return MipsAsmParser::Match_UImm16_Relaxed;
4172
0
    break;
4173
0
    }
4174
0
  // 'ConstantUImm20_0' class
4175
47
  case MCK_ConstantUImm20_0: {
4176
47
    DiagnosticPredicate DP(Operand.isConstantUImm<20, 0>());
4177
47
    if (DP.isMatch())
4178
32
      return MCTargetAsmParser::Match_Success;
4179
15
    if (DP.isNearMatch())
4180
15
      return MipsAsmParser::Match_UImm20_0;
4181
0
    break;
4182
0
    }
4183
0
  // 'ConstantUImm26_0' class
4184
0
  case MCK_ConstantUImm26_0: {
4185
0
    DiagnosticPredicate DP(Operand.isConstantUImm<26, 0>());
4186
0
    if (DP.isMatch())
4187
0
      return MCTargetAsmParser::Match_Success;
4188
0
    if (DP.isNearMatch())
4189
0
      return MipsAsmParser::Match_UImm26_0;
4190
0
    break;
4191
0
    }
4192
0
  // 'SImm32' class
4193
198
  case MCK_SImm32: {
4194
198
    DiagnosticPredicate DP(Operand.isSImm<32>());
4195
198
    if (DP.isMatch())
4196
50
      return MCTargetAsmParser::Match_Success;
4197
148
    if (DP.isNearMatch())
4198
148
      return MipsAsmParser::Match_SImm32;
4199
0
    break;
4200
0
    }
4201
0
  // 'SImm32_Relaxed' class
4202
2.24k
  case MCK_SImm32_Relaxed: {
4203
2.24k
    DiagnosticPredicate DP(Operand.isAnyImm<33>());
4204
2.24k
    if (DP.isMatch())
4205
1.02k
      return MCTargetAsmParser::Match_Success;
4206
1.21k
    if (DP.isNearMatch())
4207
1.21k
      return MipsAsmParser::Match_SImm32_Relaxed;
4208
0
    break;
4209
0
    }
4210
0
  // 'UImm32_Coerced' class
4211
209
  case MCK_UImm32_Coerced: {
4212
209
    DiagnosticPredicate DP(Operand.isSImm<33>());
4213
209
    if (DP.isMatch())
4214
206
      return MCTargetAsmParser::Match_Success;
4215
3
    if (DP.isNearMatch())
4216
3
      return MipsAsmParser::Match_UImm32_Coerced;
4217
0
    break;
4218
0
    }
4219
33.1k
  } // end switch (Kind)
4220
33.1k
4221
33.1k
  if (Operand.isReg()) {
4222
251
    MatchClassKind OpKind;
4223
251
    switch (Operand.getReg()) {
4224
251
    
default: OpKind = InvalidMatchClass; break0
;
4225
251
    case Mips::ZERO: OpKind = MCK_GPR32ZERO; break;
4226
251
    
case Mips::AT: OpKind = MCK_GPR32NONZERO; break0
;
4227
251
    
case Mips::V0: OpKind = MCK_Reg11; break0
;
4228
251
    
case Mips::V1: OpKind = MCK_Reg11; break0
;
4229
251
    
case Mips::A0: OpKind = MCK_GPRMM16MovePPairFirst; break0
;
4230
251
    
case Mips::A1: OpKind = MCK_Reg13; break0
;
4231
251
    
case Mips::A2: OpKind = MCK_Reg13; break0
;
4232
251
    
case Mips::A3: OpKind = MCK_Reg14; break0
;
4233
251
    
case Mips::T0: OpKind = MCK_GPR32NONZERO; break0
;
4234
251
    
case Mips::T1: OpKind = MCK_GPR32NONZERO; break0
;
4235
251
    
case Mips::T2: OpKind = MCK_GPR32NONZERO; break0
;
4236
251
    
case Mips::T3: OpKind = MCK_GPR32NONZERO; break0
;
4237
251
    
case Mips::T4: OpKind = MCK_GPR32NONZERO; break0
;
4238
251
    
case Mips::T5: OpKind = MCK_GPR32NONZERO; break0
;
4239
251
    
case Mips::T6: OpKind = MCK_GPR32NONZERO; break0
;
4240
251
    
case Mips::T7: OpKind = MCK_GPR32NONZERO; break0
;
4241
251
    
case Mips::S0: OpKind = MCK_Reg9; break0
;
4242
251
    
case Mips::S1: OpKind = MCK_Reg11; break0
;
4243
251
    
case Mips::S2: OpKind = MCK_Reg10; break0
;
4244
251
    
case Mips::S3: OpKind = MCK_Reg10; break0
;
4245
251
    
case Mips::S4: OpKind = MCK_Reg10; break0
;
4246
251
    
case Mips::S5: OpKind = MCK_GPRMM16MovePPairSecond; break0
;
4247
251
    
case Mips::S6: OpKind = MCK_GPRMM16MovePPairSecond; break0
;
4248
251
    
case Mips::S7: OpKind = MCK_GPR32NONZERO; break0
;
4249
251
    
case Mips::T8: OpKind = MCK_GPR32NONZERO; break0
;
4250
251
    
case Mips::T9: OpKind = MCK_GPR32NONZERO; break0
;
4251
251
    
case Mips::K0: OpKind = MCK_GPR32NONZERO; break0
;
4252
251
    
case Mips::K1: OpKind = MCK_GPR32NONZERO; break0
;
4253
251
    
case Mips::GP: OpKind = MCK_GP32; break0
;
4254
251
    
case Mips::SP: OpKind = MCK_CPUSPReg; break0
;
4255
251
    
case Mips::FP: OpKind = MCK_GPR32NONZERO; break0
;
4256
251
    
case Mips::RA: OpKind = MCK_CPURAReg; break0
;
4257
251
    
case Mips::ZERO_64: OpKind = MCK_Reg19; break0
;
4258
251
    
case Mips::AT_64: OpKind = MCK_Reg24; break0
;
4259
251
    
case Mips::V0_64: OpKind = MCK_Reg30; break0
;
4260
251
    
case Mips::V1_64: OpKind = MCK_Reg30; break0
;
4261
251
    
case Mips::A0_64: OpKind = MCK_Reg31; break0
;
4262
251
    
case Mips::A1_64: OpKind = MCK_Reg32; break0
;
4263
251
    
case Mips::A2_64: OpKind = MCK_Reg32; break0
;
4264
251
    
case Mips::A3_64: OpKind = MCK_Reg33; break0
;
4265
251
    
case Mips::T0_64: OpKind = MCK_Reg24; break0
;
4266
251
    
case Mips::T1_64: OpKind = MCK_Reg24; break0
;
4267
251
    
case Mips::T2_64: OpKind = MCK_Reg24; break0
;
4268
251
    
case Mips::T3_64: OpKind = MCK_Reg24; break0
;
4269
251
    
case Mips::T4_64: OpKind = MCK_Reg24; break0
;
4270
251
    
case Mips::T5_64: OpKind = MCK_Reg24; break0
;
4271
251
    
case Mips::T6_64: OpKind = MCK_Reg24; break0
;
4272
251
    
case Mips::T7_64: OpKind = MCK_Reg24; break0
;
4273
251
    
case Mips::S0_64: OpKind = MCK_Reg28; break0
;
4274
251
    
case Mips::S1_64: OpKind = MCK_Reg30; break0
;
4275
251
    
case Mips::S2_64: OpKind = MCK_Reg29; break0
;
4276
251
    
case Mips::S3_64: OpKind = MCK_Reg29; break0
;
4277
251
    
case Mips::S4_64: OpKind = MCK_Reg29; break0
;
4278
251
    
case Mips::S5_64: OpKind = MCK_Reg34; break0
;
4279
251
    
case Mips::S6_64: OpKind = MCK_Reg34; break0
;
4280
251
    
case Mips::S7_64: OpKind = MCK_Reg24; break0
;
4281
251
    
case Mips::T8_64: OpKind = MCK_Reg24; break0
;
4282
251
    
case Mips::T9_64: OpKind = MCK_Reg24; break0
;
4283
251
    
case Mips::K0_64: OpKind = MCK_Reg24; break0
;
4284
251
    
case Mips::K1_64: OpKind = MCK_Reg24; break0
;
4285
251
    
case Mips::GP_64: OpKind = MCK_GP64; break0
;
4286
251
    
case Mips::SP_64: OpKind = MCK_SP64; break0
;
4287
251
    
case Mips::FP_64: OpKind = MCK_Reg24; break0
;
4288
251
    
case Mips::RA_64: OpKind = MCK_Reg37; break0
;
4289
251
    
case Mips::F0: OpKind = MCK_FGR32; break0
;
4290
251
    
case Mips::F1: OpKind = MCK_Reg39; break0
;
4291
251
    
case Mips::F2: OpKind = MCK_FGR32; break0
;
4292
251
    
case Mips::F3: OpKind = MCK_Reg39; break0
;
4293
251
    
case Mips::F4: OpKind = MCK_FGR32; break0
;
4294
251
    
case Mips::F5: OpKind = MCK_Reg39; break0
;
4295
251
    
case Mips::F6: OpKind = MCK_FGR32; break0
;
4296
251
    
case Mips::F7: OpKind = MCK_Reg39; break0
;
4297
251
    
case Mips::F8: OpKind = MCK_FGR32; break0
;
4298
251
    
case Mips::F9: OpKind = MCK_Reg39; break0
;
4299
251
    
case Mips::F10: OpKind = MCK_FGR32; break0
;
4300
251
    
case Mips::F11: OpKind = MCK_Reg39; break0
;
4301
251
    
case Mips::F12: OpKind = MCK_FGR32; break0
;
4302
251
    
case Mips::F13: OpKind = MCK_Reg39; break0
;
4303
251
    
case Mips::F14: OpKind = MCK_FGR32; break0
;
4304
251
    
case Mips::F15: OpKind = MCK_Reg39; break0
;
4305
251
    
case Mips::F16: OpKind = MCK_FGR32; break0
;
4306
251
    
case Mips::F17: OpKind = MCK_Reg39; break0
;
4307
251
    
case Mips::F18: OpKind = MCK_FGR32; break0
;
4308
251
    
case Mips::F19: OpKind = MCK_Reg39; break0
;
4309
251
    
case Mips::F20: OpKind = MCK_FGR32; break0
;
4310
251
    
case Mips::F21: OpKind = MCK_Reg39; break0
;
4311
251
    
case Mips::F22: OpKind = MCK_FGR32; break0
;
4312
251
    
case Mips::F23: OpKind = MCK_Reg39; break0
;
4313
251
    
case Mips::F24: OpKind = MCK_FGR32; break0
;
4314
251
    
case Mips::F25: OpKind = MCK_Reg39; break0
;
4315
251
    
case Mips::F26: OpKind = MCK_FGR32; break0
;
4316
251
    
case Mips::F27: OpKind = MCK_Reg39; break0
;
4317
251
    
case Mips::F28: OpKind = MCK_FGR32; break0
;
4318
251
    
case Mips::F29: OpKind = MCK_Reg39; break0
;
4319
251
    
case Mips::F30: OpKind = MCK_FGR32; break0
;
4320
251
    
case Mips::F31: OpKind = MCK_Reg39; break0
;
4321
251
    
case Mips::F_HI0: OpKind = MCK_FGRH32; break0
;
4322
251
    
case Mips::F_HI1: OpKind = MCK_Reg42; break0
;
4323
251
    
case Mips::F_HI2: OpKind = MCK_FGRH32; break0
;
4324
251
    
case Mips::F_HI3: OpKind = MCK_Reg42; break0
;
4325
251
    
case Mips::F_HI4: OpKind = MCK_FGRH32; break0
;
4326
251
    
case Mips::F_HI5: OpKind = MCK_Reg42; break0
;
4327
251
    
case Mips::F_HI6: OpKind = MCK_FGRH32; break0
;
4328
251
    
case Mips::F_HI7: OpKind = MCK_Reg42; break0
;
4329
251
    
case Mips::F_HI8: OpKind = MCK_FGRH32; break0
;
4330
251
    
case Mips::F_HI9: OpKind = MCK_Reg42; break0
;
4331
251
    
case Mips::F_HI10: OpKind = MCK_FGRH32; break0
;
4332
251
    
case Mips::F_HI11: OpKind = MCK_Reg42; break0
;
4333
251
    
case Mips::F_HI12: OpKind = MCK_FGRH32; break0
;
4334
251
    
case Mips::F_HI13: OpKind = MCK_Reg42; break0
;
4335
251
    
case Mips::F_HI14: OpKind = MCK_FGRH32; break0
;
4336
251
    
case Mips::F_HI15: OpKind = MCK_Reg42; break0
;
4337
251
    
case Mips::F_HI16: OpKind = MCK_FGRH32; break0
;
4338
251
    
case Mips::F_HI17: OpKind = MCK_Reg42; break0
;
4339
251
    
case Mips::F_HI18: OpKind = MCK_FGRH32; break0
;
4340
251
    
case Mips::F_HI19: OpKind = MCK_Reg42; break0
;
4341
251
    
case Mips::F_HI20: OpKind = MCK_FGRH32; break0
;
4342
251
    
case Mips::F_HI21: OpKind = MCK_Reg42; break0
;
4343
251
    
case Mips::F_HI22: OpKind = MCK_FGRH32; break0
;
4344
251
    
case Mips::F_HI23: OpKind = MCK_Reg42; break0
;
4345
251
    
case Mips::F_HI24: OpKind = MCK_FGRH32; break0
;
4346
251
    
case Mips::F_HI25: OpKind = MCK_Reg42; break0
;
4347
251
    
case Mips::F_HI26: OpKind = MCK_FGRH32; break0
;
4348
251
    
case Mips::F_HI27: OpKind = MCK_Reg42; break0
;
4349
251
    
case Mips::F_HI28: OpKind = MCK_FGRH32; break0
;
4350
251
    
case Mips::F_HI29: OpKind = MCK_Reg42; break0
;
4351
251
    
case Mips::F_HI30: OpKind = MCK_FGRH32; break0
;
4352
251
    
case Mips::F_HI31: OpKind = MCK_Reg42; break0
;
4353
251
    
case Mips::D0: OpKind = MCK_AFGR64; break0
;
4354
251
    
case Mips::D1: OpKind = MCK_Reg44; break0
;
4355
251
    
case Mips::D2: OpKind = MCK_AFGR64; break0
;
4356
251
    
case Mips::D3: OpKind = MCK_Reg44; break0
;
4357
251
    
case Mips::D4: OpKind = MCK_AFGR64; break0
;
4358
251
    
case Mips::D5: OpKind = MCK_Reg44; break0
;
4359
251
    
case Mips::D6: OpKind = MCK_AFGR64; break0
;
4360
251
    
case Mips::D7: OpKind = MCK_Reg44; break0
;
4361
251
    
case Mips::D8: OpKind = MCK_AFGR64; break0
;
4362
251
    
case Mips::D9: OpKind = MCK_Reg44; break0
;
4363
251
    
case Mips::D10: OpKind = MCK_AFGR64; break0
;
4364
251
    
case Mips::D11: OpKind = MCK_Reg44; break0
;
4365
251
    
case Mips::D12: OpKind = MCK_AFGR64; break0
;
4366
251
    
case Mips::D13: OpKind = MCK_Reg44; break0
;
4367
251
    
case Mips::D14: OpKind = MCK_AFGR64; break0
;
4368
251
    
case Mips::D15: OpKind = MCK_Reg44; break0
;
4369
251
    
case Mips::D0_64: OpKind = MCK_FGR64; break0
;
4370
251
    
case Mips::D1_64: OpKind = MCK_Reg47; break0
;
4371
251
    
case Mips::D2_64: OpKind = MCK_FGR64; break0
;
4372
251
    
case Mips::D3_64: OpKind = MCK_Reg47; break0
;
4373
251
    
case Mips::D4_64: OpKind = MCK_FGR64; break0
;
4374
251
    
case Mips::D5_64: OpKind = MCK_Reg47; break0
;
4375
251
    
case Mips::D6_64: OpKind = MCK_FGR64; break0
;
4376
251
    
case Mips::D7_64: OpKind = MCK_Reg47; break0
;
4377
251
    
case Mips::D8_64: OpKind = MCK_FGR64; break0
;
4378
251
    
case Mips::D9_64: OpKind = MCK_Reg47; break0
;
4379
251
    
case Mips::D10_64: OpKind = MCK_FGR64; break0
;
4380
251
    
case Mips::D11_64: OpKind = MCK_Reg47; break0
;
4381
251
    
case Mips::D12_64: OpKind = MCK_FGR64; break0
;
4382
251
    
case Mips::D13_64: OpKind = MCK_Reg47; break0
;
4383
251
    
case Mips::D14_64: OpKind = MCK_FGR64; break0
;
4384
251
    
case Mips::D15_64: OpKind = MCK_Reg47; break0
;
4385
251
    
case Mips::D16_64: OpKind = MCK_FGR64; break0
;
4386
251
    
case Mips::D17_64: OpKind = MCK_Reg47; break0
;
4387
251
    
case Mips::D18_64: OpKind = MCK_FGR64; break0
;
4388
251
    
case Mips::D19_64: OpKind = MCK_Reg47; break0
;
4389
251
    
case Mips::D20_64: OpKind = MCK_FGR64; break0
;
4390
251
    
case Mips::D21_64: OpKind = MCK_Reg47; break0
;
4391
251
    
case Mips::D22_64: OpKind = MCK_FGR64; break0
;
4392
251
    
case Mips::D23_64: OpKind = MCK_Reg47; break0
;
4393
251
    
case Mips::D24_64: OpKind = MCK_FGR64; break0
;
4394
251
    
case Mips::D25_64: OpKind = MCK_Reg47; break0
;
4395
251
    
case Mips::D26_64: OpKind = MCK_FGR64; break0
;
4396
251
    
case Mips::D27_64: OpKind = MCK_Reg47; break0
;
4397
251
    
case Mips::D28_64: OpKind = MCK_FGR64; break0
;
4398
251
    
case Mips::D29_64: OpKind = MCK_Reg47; break0
;
4399
251
    
case Mips::D30_64: OpKind = MCK_FGR64; break0
;
4400
251
    
case Mips::D31_64: OpKind = MCK_Reg47; break0
;
4401
251
    
case Mips::W0: OpKind = MCK_MSA128WEvens; break0
;
4402
251
    
case Mips::W1: OpKind = MCK_Reg50; break0
;
4403
251
    
case Mips::W2: OpKind = MCK_MSA128WEvens; break0
;
4404
251
    
case Mips::W3: OpKind = MCK_Reg50; break0
;
4405
251
    
case Mips::W4: OpKind = MCK_MSA128WEvens; break0
;
4406
251
    
case Mips::W5: OpKind = MCK_Reg50; break0
;
4407
251
    
case Mips::W6: OpKind = MCK_MSA128WEvens; break0
;
4408
251
    
case Mips::W7: OpKind = MCK_Reg50; break0
;
4409
251
    
case Mips::W8: OpKind = MCK_MSA128WEvens; break0
;
4410
251
    
case Mips::W9: OpKind = MCK_Reg50; break0
;
4411
251
    
case Mips::W10: OpKind = MCK_MSA128WEvens; break0
;
4412
251
    
case Mips::W11: OpKind = MCK_Reg50; break0
;
4413
251
    
case Mips::W12: OpKind = MCK_MSA128WEvens; break0
;
4414
251
    
case Mips::W13: OpKind = MCK_Reg50; break0
;
4415
251
    
case Mips::W14: OpKind = MCK_MSA128WEvens; break0
;
4416
251
    
case Mips::W15: OpKind = MCK_Reg50; break0
;
4417
251
    
case Mips::W16: OpKind = MCK_MSA128WEvens; break0
;
4418
251
    
case Mips::W17: OpKind = MCK_Reg50; break0
;
4419
251
    
case Mips::W18: OpKind = MCK_MSA128WEvens; break0
;
4420
251
    
case Mips::W19: OpKind = MCK_Reg50; break0
;
4421
251
    
case Mips::W20: OpKind = MCK_MSA128WEvens; break0
;
4422
251
    
case Mips::W21: OpKind = MCK_Reg50; break0
;
4423
251
    
case Mips::W22: OpKind = MCK_MSA128WEvens; break0
;
4424
251
    
case Mips::W23: OpKind = MCK_Reg50; break0
;
4425
251
    
case Mips::W24: OpKind = MCK_MSA128WEvens; break0
;
4426
251
    
case Mips::W25: OpKind = MCK_Reg50; break0
;
4427
251
    
case Mips::W26: OpKind = MCK_MSA128WEvens; break0
;
4428
251
    
case Mips::W27: OpKind = MCK_Reg50; break0
;
4429
251
    
case Mips::W28: OpKind = MCK_MSA128WEvens; break0
;
4430
251
    
case Mips::W29: OpKind = MCK_Reg50; break0
;
4431
251
    
case Mips::W30: OpKind = MCK_MSA128WEvens; break0
;
4432
251
    
case Mips::W31: OpKind = MCK_Reg50; break0
;
4433
251
    
case Mips::HI0: OpKind = MCK_HI32; break0
;
4434
251
    
case Mips::HI1: OpKind = MCK_HI32DSP; break0
;
4435
251
    
case Mips::HI2: OpKind = MCK_HI32DSP; break0
;
4436
251
    
case Mips::HI3: OpKind = MCK_HI32DSP; break0
;
4437
251
    
case Mips::LO0: OpKind = MCK_LO32; break0
;
4438
251
    
case Mips::LO1: OpKind = MCK_LO32DSP; break0
;
4439
251
    
case Mips::LO2: OpKind = MCK_LO32DSP; break0
;
4440
251
    
case Mips::LO3: OpKind = MCK_LO32DSP; break0
;
4441
251
    
case Mips::HI0_64: OpKind = MCK_HI64; break0
;
4442
251
    
case Mips::LO0_64: OpKind = MCK_LO64; break0
;
4443
251
    
case Mips::FCR0: OpKind = MCK_CCR; break0
;
4444
251
    
case Mips::FCR1: OpKind = MCK_CCR; break0
;
4445
251
    
case Mips::FCR2: OpKind = MCK_CCR; break0
;
4446
251
    
case Mips::FCR3: OpKind = MCK_CCR; break0
;
4447
251
    
case Mips::FCR4: OpKind = MCK_CCR; break0
;
4448
251
    
case Mips::FCR5: OpKind = MCK_CCR; break0
;
4449
251
    
case Mips::FCR6: OpKind = MCK_CCR; break0
;
4450
251
    
case Mips::FCR7: OpKind = MCK_CCR; break0
;
4451
251
    
case Mips::FCR8: OpKind = MCK_CCR; break0
;
4452
251
    
case Mips::FCR9: OpKind = MCK_CCR; break0
;
4453
251
    
case Mips::FCR10: OpKind = MCK_CCR; break0
;
4454
251
    
case Mips::FCR11: OpKind = MCK_CCR; break0
;
4455
251
    
case Mips::FCR12: OpKind = MCK_CCR; break0
;
4456
251
    
case Mips::FCR13: OpKind = MCK_CCR; break0
;
4457
251
    
case Mips::FCR14: OpKind = MCK_CCR; break0
;
4458
251
    
case Mips::FCR15: OpKind = MCK_CCR; break0
;
4459
251
    
case Mips::FCR16: OpKind = MCK_CCR; break0
;
4460
251
    
case Mips::FCR17: OpKind = MCK_CCR; break0
;
4461
251
    
case Mips::FCR18: OpKind = MCK_CCR; break0
;
4462
251
    
case Mips::FCR19: OpKind = MCK_CCR; break0
;
4463
251
    
case Mips::FCR20: OpKind = MCK_CCR; break0
;
4464
251
    
case Mips::FCR21: OpKind = MCK_CCR; break0
;
4465
251
    
case Mips::FCR22: OpKind = MCK_CCR; break0
;
4466
251
    
case Mips::FCR23: OpKind = MCK_CCR; break0
;
4467
251
    
case Mips::FCR24: OpKind = MCK_CCR; break0
;
4468
251
    
case Mips::FCR25: OpKind = MCK_CCR; break0
;
4469
251
    
case Mips::FCR26: OpKind = MCK_CCR; break0
;
4470
251
    
case Mips::FCR27: OpKind = MCK_CCR; break0
;
4471
251
    
case Mips::FCR28: OpKind = MCK_CCR; break0
;
4472
251
    
case Mips::FCR29: OpKind = MCK_CCR; break0
;
4473
251
    
case Mips::FCR30: OpKind = MCK_CCR; break0
;
4474
251
    
case Mips::FCR31: OpKind = MCK_CCR; break0
;
4475
251
    
case Mips::FCC0: OpKind = MCK_FCC; break0
;
4476
251
    
case Mips::FCC1: OpKind = MCK_FCC; break0
;
4477
251
    
case Mips::FCC2: OpKind = MCK_FCC; break0
;
4478
251
    
case Mips::FCC3: OpKind = MCK_FCC; break0
;
4479
251
    
case Mips::FCC4: OpKind = MCK_FCC; break0
;
4480
251
    
case Mips::FCC5: OpKind = MCK_FCC; break0
;
4481
251
    
case Mips::FCC6: OpKind = MCK_FCC; break0
;
4482
251
    
case Mips::FCC7: OpKind = MCK_FCC; break0
;
4483
251
    
case Mips::COP00: OpKind = MCK_COP0; break0
;
4484
251
    
case Mips::COP01: OpKind = MCK_COP0; break0
;
4485
251
    
case Mips::COP02: OpKind = MCK_COP0; break0
;
4486
251
    
case Mips::COP03: OpKind = MCK_COP0; break0
;
4487
251
    
case Mips::COP04: OpKind = MCK_COP0; break0
;
4488
251
    
case Mips::COP05: OpKind = MCK_COP0; break0
;
4489
251
    
case Mips::COP06: OpKind = MCK_COP0; break0
;
4490
251
    
case Mips::COP07: OpKind = MCK_COP0; break0
;
4491
251
    
case Mips::COP08: OpKind = MCK_COP0; break0
;
4492
251
    
case Mips::COP09: OpKind = MCK_COP0; break0
;
4493
251
    
case Mips::COP010: OpKind = MCK_COP0; break0
;
4494
251
    
case Mips::COP011: OpKind = MCK_COP0; break0
;
4495
251
    
case Mips::COP012: OpKind = MCK_COP0; break0
;
4496
251
    
case Mips::COP013: OpKind = MCK_COP0; break0
;
4497
251
    
case Mips::COP014: OpKind = MCK_COP0; break0
;
4498
251
    
case Mips::COP015: OpKind = MCK_COP0; break0
;
4499
251
    
case Mips::COP016: OpKind = MCK_COP0; break0
;
4500
251
    
case Mips::COP017: OpKind = MCK_COP0; break0
;
4501
251
    
case Mips::COP018: OpKind = MCK_COP0; break0
;
4502
251
    
case Mips::COP019: OpKind = MCK_COP0; break0
;
4503
251
    
case Mips::COP020: OpKind = MCK_COP0; break0
;
4504
251
    
case Mips::COP021: OpKind = MCK_COP0; break0
;
4505
251
    
case Mips::COP022: OpKind = MCK_COP0; break0
;
4506
251
    
case Mips::COP023: OpKind = MCK_COP0; break0
;
4507
251
    
case Mips::COP024: OpKind = MCK_COP0; break0
;
4508
251
    
case Mips::COP025: OpKind = MCK_COP0; break0
;
4509
251
    
case Mips::COP026: OpKind = MCK_COP0; break0
;
4510
251
    
case Mips::COP027: OpKind = MCK_COP0; break0
;
4511
251
    
case Mips::COP028: OpKind = MCK_COP0; break0
;
4512
251
    
case Mips::COP029: OpKind = MCK_COP0; break0
;
4513
251
    
case Mips::COP030: OpKind = MCK_COP0; break0
;
4514
251
    
case Mips::COP031: OpKind = MCK_COP0; break0
;
4515
251
    
case Mips::COP20: OpKind = MCK_COP2; break0
;
4516
251
    
case Mips::COP21: OpKind = MCK_COP2; break0
;
4517