/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Mips/MipsGenAsmMatcher.inc
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1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Assembly Matcher Source Fragment *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | |
10 | | #ifdef GET_ASSEMBLER_HEADER |
11 | | #undef GET_ASSEMBLER_HEADER |
12 | | // This should be included into the middle of the declaration of |
13 | | // your subclasses implementation of MCTargetAsmParser. |
14 | | FeatureBitset ComputeAvailableFeatures(const FeatureBitset& FB) const; |
15 | | void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, |
16 | | const OperandVector &Operands); |
17 | | void convertToMapAndConstraints(unsigned Kind, |
18 | | const OperandVector &Operands) override; |
19 | | unsigned MatchInstructionImpl(const OperandVector &Operands, |
20 | | MCInst &Inst, |
21 | | uint64_t &ErrorInfo, |
22 | | FeatureBitset &MissingFeatures, |
23 | | bool matchingInlineAsm, |
24 | | unsigned VariantID = 0); |
25 | | unsigned MatchInstructionImpl(const OperandVector &Operands, |
26 | | MCInst &Inst, |
27 | | uint64_t &ErrorInfo, |
28 | | bool matchingInlineAsm, |
29 | 40.8k | unsigned VariantID = 0) { |
30 | 40.8k | FeatureBitset MissingFeatures; |
31 | 40.8k | return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures, |
32 | 40.8k | matchingInlineAsm, VariantID); |
33 | 40.8k | } |
34 | | |
35 | | OperandMatchResultTy MatchOperandParserImpl( |
36 | | OperandVector &Operands, |
37 | | StringRef Mnemonic, |
38 | | bool ParseForAllFeatures = false); |
39 | | OperandMatchResultTy tryCustomParseOperand( |
40 | | OperandVector &Operands, |
41 | | unsigned MCK); |
42 | | |
43 | | #endif // GET_ASSEMBLER_HEADER_INFO |
44 | | |
45 | | |
46 | | #ifdef GET_OPERAND_DIAGNOSTIC_TYPES |
47 | | #undef GET_OPERAND_DIAGNOSTIC_TYPES |
48 | | |
49 | | Match_Immz, |
50 | | Match_MemSImm10, |
51 | | Match_MemSImm10Lsl1, |
52 | | Match_MemSImm10Lsl2, |
53 | | Match_MemSImm10Lsl3, |
54 | | Match_MemSImm11, |
55 | | Match_MemSImm12, |
56 | | Match_MemSImm16, |
57 | | Match_MemSImm9, |
58 | | Match_MemSImmPtr, |
59 | | Match_SImm10_0, |
60 | | Match_SImm10_Lsl1, |
61 | | Match_SImm10_Lsl2, |
62 | | Match_SImm10_Lsl3, |
63 | | Match_SImm11_0, |
64 | | Match_SImm16, |
65 | | Match_SImm16_Relaxed, |
66 | | Match_SImm19_Lsl2, |
67 | | Match_SImm32, |
68 | | Match_SImm32_Relaxed, |
69 | | Match_SImm4_0, |
70 | | Match_SImm5_0, |
71 | | Match_SImm6_0, |
72 | | Match_SImm7_Lsl2, |
73 | | Match_SImm9_0, |
74 | | Match_UImm10_0, |
75 | | Match_UImm16, |
76 | | Match_UImm16_AltRelaxed, |
77 | | Match_UImm16_Relaxed, |
78 | | Match_UImm1_0, |
79 | | Match_UImm20_0, |
80 | | Match_UImm26_0, |
81 | | Match_UImm2_0, |
82 | | Match_UImm2_1, |
83 | | Match_UImm32_Coerced, |
84 | | Match_UImm3_0, |
85 | | Match_UImm4_0, |
86 | | Match_UImm5_0, |
87 | | Match_UImm5_0_Report_UImm6, |
88 | | Match_UImm5_1, |
89 | | Match_UImm5_32, |
90 | | Match_UImm5_33, |
91 | | Match_UImm5_Lsl2, |
92 | | Match_UImm6_0, |
93 | | Match_UImm6_Lsl2, |
94 | | Match_UImm7_0, |
95 | | Match_UImm7_N1, |
96 | | Match_UImm8_0, |
97 | | Match_UImmRange2_64, |
98 | | END_OPERAND_DIAGNOSTIC_TYPES |
99 | | #endif // GET_OPERAND_DIAGNOSTIC_TYPES |
100 | | |
101 | | |
102 | | #ifdef GET_REGISTER_MATCHER |
103 | | #undef GET_REGISTER_MATCHER |
104 | | |
105 | | // Bits for subtarget features that participate in instruction matching. |
106 | | enum SubtargetFeatureBits : uint8_t { |
107 | | Feature_HasMips2Bit = 10, |
108 | | Feature_HasMips3_32Bit = 16, |
109 | | Feature_HasMips3_32r2Bit = 17, |
110 | | Feature_HasMips3Bit = 11, |
111 | | Feature_NotMips3Bit = 44, |
112 | | Feature_HasMips4_32Bit = 18, |
113 | | Feature_NotMips4_32Bit = 46, |
114 | | Feature_HasMips4_32r2Bit = 19, |
115 | | Feature_HasMips5_32r2Bit = 20, |
116 | | Feature_HasMips32Bit = 12, |
117 | | Feature_HasMips32r2Bit = 13, |
118 | | Feature_HasMips32r5Bit = 14, |
119 | | Feature_HasMips32r6Bit = 15, |
120 | | Feature_NotMips32r6Bit = 45, |
121 | | Feature_IsGP64bitBit = 31, |
122 | | Feature_IsGP32bitBit = 30, |
123 | | Feature_IsPTR64bitBit = 35, |
124 | | Feature_IsPTR32bitBit = 34, |
125 | | Feature_HasMips64Bit = 21, |
126 | | Feature_NotMips64Bit = 47, |
127 | | Feature_HasMips64r2Bit = 22, |
128 | | Feature_HasMips64r5Bit = 23, |
129 | | Feature_HasMips64r6Bit = 24, |
130 | | Feature_NotMips64r6Bit = 48, |
131 | | Feature_InMips16ModeBit = 28, |
132 | | Feature_NotInMips16ModeBit = 43, |
133 | | Feature_HasCnMipsBit = 1, |
134 | | Feature_NotCnMipsBit = 40, |
135 | | Feature_IsSym32Bit = 37, |
136 | | Feature_IsSym64Bit = 38, |
137 | | Feature_HasStdEncBit = 25, |
138 | | Feature_InMicroMipsBit = 27, |
139 | | Feature_NotInMicroMipsBit = 42, |
140 | | Feature_HasEVABit = 5, |
141 | | Feature_HasMSABit = 7, |
142 | | Feature_HasMadd4Bit = 9, |
143 | | Feature_HasMTBit = 8, |
144 | | Feature_UseIndirectJumpsHazardBit = 49, |
145 | | Feature_NoIndirectJumpGuardsBit = 39, |
146 | | Feature_HasCRCBit = 0, |
147 | | Feature_HasVirtBit = 26, |
148 | | Feature_HasGINVBit = 6, |
149 | | Feature_IsFP64bitBit = 29, |
150 | | Feature_NotFP64bitBit = 41, |
151 | | Feature_IsSingleFloatBit = 36, |
152 | | Feature_IsNotSingleFloatBit = 32, |
153 | | Feature_IsNotSoftFloatBit = 33, |
154 | | Feature_HasDSPBit = 2, |
155 | | Feature_HasDSPR2Bit = 3, |
156 | | Feature_HasDSPR3Bit = 4, |
157 | | }; |
158 | | |
159 | | #endif // GET_REGISTER_MATCHER |
160 | | |
161 | | |
162 | | #ifdef GET_SUBTARGET_FEATURE_NAME |
163 | | #undef GET_SUBTARGET_FEATURE_NAME |
164 | | |
165 | | // User-level names for subtarget features that participate in |
166 | | // instruction matching. |
167 | | static const char *getSubtargetFeatureName(uint64_t Val) { |
168 | | switch(Val) { |
169 | | case Feature_HasMips2Bit: return ""; |
170 | | case Feature_HasMips3_32Bit: return ""; |
171 | | case Feature_HasMips3_32r2Bit: return ""; |
172 | | case Feature_HasMips3Bit: return ""; |
173 | | case Feature_NotMips3Bit: return ""; |
174 | | case Feature_HasMips4_32Bit: return ""; |
175 | | case Feature_NotMips4_32Bit: return ""; |
176 | | case Feature_HasMips4_32r2Bit: return ""; |
177 | | case Feature_HasMips5_32r2Bit: return ""; |
178 | | case Feature_HasMips32Bit: return ""; |
179 | | case Feature_HasMips32r2Bit: return ""; |
180 | | case Feature_HasMips32r5Bit: return ""; |
181 | | case Feature_HasMips32r6Bit: return ""; |
182 | | case Feature_NotMips32r6Bit: return ""; |
183 | | case Feature_IsGP64bitBit: return ""; |
184 | | case Feature_IsGP32bitBit: return ""; |
185 | | case Feature_IsPTR64bitBit: return ""; |
186 | | case Feature_IsPTR32bitBit: return ""; |
187 | | case Feature_HasMips64Bit: return ""; |
188 | | case Feature_NotMips64Bit: return ""; |
189 | | case Feature_HasMips64r2Bit: return ""; |
190 | | case Feature_HasMips64r5Bit: return ""; |
191 | | case Feature_HasMips64r6Bit: return ""; |
192 | | case Feature_NotMips64r6Bit: return ""; |
193 | | case Feature_InMips16ModeBit: return ""; |
194 | | case Feature_NotInMips16ModeBit: return ""; |
195 | | case Feature_HasCnMipsBit: return ""; |
196 | | case Feature_NotCnMipsBit: return ""; |
197 | | case Feature_IsSym32Bit: return ""; |
198 | | case Feature_IsSym64Bit: return ""; |
199 | | case Feature_HasStdEncBit: return ""; |
200 | | case Feature_InMicroMipsBit: return ""; |
201 | | case Feature_NotInMicroMipsBit: return ""; |
202 | | case Feature_HasEVABit: return ""; |
203 | | case Feature_HasMSABit: return ""; |
204 | | case Feature_HasMadd4Bit: return ""; |
205 | | case Feature_HasMTBit: return ""; |
206 | | case Feature_UseIndirectJumpsHazardBit: return ""; |
207 | | case Feature_NoIndirectJumpGuardsBit: return ""; |
208 | | case Feature_HasCRCBit: return ""; |
209 | | case Feature_HasVirtBit: return ""; |
210 | | case Feature_HasGINVBit: return ""; |
211 | | case Feature_IsFP64bitBit: return ""; |
212 | | case Feature_NotFP64bitBit: return ""; |
213 | | case Feature_IsSingleFloatBit: return ""; |
214 | | case Feature_IsNotSingleFloatBit: return ""; |
215 | | case Feature_IsNotSoftFloatBit: return ""; |
216 | | case Feature_HasDSPBit: return ""; |
217 | | case Feature_HasDSPR2Bit: return ""; |
218 | | case Feature_HasDSPR3Bit: return ""; |
219 | | default: return "(unknown)"; |
220 | | } |
221 | | } |
222 | | |
223 | | #endif // GET_SUBTARGET_FEATURE_NAME |
224 | | |
225 | | |
226 | | #ifdef GET_MATCHER_IMPLEMENTATION |
227 | | #undef GET_MATCHER_IMPLEMENTATION |
228 | | |
229 | | enum { |
230 | | Tie0_1_1, |
231 | | Tie0_1_2, |
232 | | }; |
233 | | |
234 | | static const uint8_t TiedAsmOperandTable[][3] = { |
235 | | /* Tie0_1_1 */ { 0, 1, 1 }, |
236 | | /* Tie0_1_2 */ { 0, 1, 2 }, |
237 | | }; |
238 | | |
239 | | namespace { |
240 | | enum OperatorConversionKind { |
241 | | CVT_Done, |
242 | | CVT_Reg, |
243 | | CVT_Tied, |
244 | | CVT_95_addGPR32AsmRegOperands, |
245 | | CVT_95_addAFGR64AsmRegOperands, |
246 | | CVT_95_addFGR64AsmRegOperands, |
247 | | CVT_95_addFGR32AsmRegOperands, |
248 | | CVT_95_addSImmOperands_LT_32_GT_, |
249 | | CVT_95_addMSA128AsmRegOperands, |
250 | | CVT_95_addSImmOperands_LT_16_GT_, |
251 | | CVT_95_Reg, |
252 | | CVT_95_addImmOperands, |
253 | | CVT_95_addGPRMM16AsmRegOperands, |
254 | | CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_, |
255 | | CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, |
256 | | CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, |
257 | | CVT_95_addUImmOperands_LT_16_GT_, |
258 | | CVT_95_addGPR64AsmRegOperands, |
259 | | CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, |
260 | | CVT_regZERO, |
261 | | CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, |
262 | | CVT_regFCC0, |
263 | | CVT_95_addFCCAsmRegOperands, |
264 | | CVT_95_addCOP2AsmRegOperands, |
265 | | CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, |
266 | | CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, |
267 | | CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, |
268 | | CVT_imm_95_0, |
269 | | CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, |
270 | | CVT_95_addMemOperands, |
271 | | CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_, |
272 | | CVT_95_addCCRAsmRegOperands, |
273 | | CVT_95_addMSACtrlAsmRegOperands, |
274 | | CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, |
275 | | CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_, |
276 | | CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, |
277 | | CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, |
278 | | CVT_95_addGPR32NonZeroAsmRegOperands, |
279 | | CVT_95_addGPR32ZeroAsmRegOperands, |
280 | | CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, |
281 | | CVT_95_addCOP0AsmRegOperands, |
282 | | CVT_regZERO_64, |
283 | | CVT_95_addACC64DSPAsmRegOperands, |
284 | | CVT_95_addConstantUImmOperands_LT_1_GT_, |
285 | | CVT_regRA, |
286 | | CVT_regRA_64, |
287 | | CVT_95_addMicroMipsMemOperands, |
288 | | CVT_95_addCOP3AsmRegOperands, |
289 | | CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, |
290 | | CVT_95_addConstantUImmOperands_LT_32_GT_, |
291 | | CVT_95_addStrictlyAFGR64AsmRegOperands, |
292 | | CVT_95_addStrictlyFGR64AsmRegOperands, |
293 | | CVT_95_addStrictlyFGR32AsmRegOperands, |
294 | | CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_, |
295 | | CVT_95_addRegListOperands, |
296 | | CVT_ConvertXWPOperands, |
297 | | CVT_regAC0, |
298 | | CVT_95_addGPRMM16AsmRegMovePPairFirstOperands, |
299 | | CVT_95_addGPRMM16AsmRegMovePPairSecondOperands, |
300 | | CVT_95_addGPRMM16AsmRegMovePOperands, |
301 | | CVT_95_addHI32DSPAsmRegOperands, |
302 | | CVT_95_addLO32DSPAsmRegOperands, |
303 | | CVT_regS0, |
304 | | CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_, |
305 | | CVT_95_addHWRegsAsmRegOperands, |
306 | | CVT_95_addGPRMM16AsmRegZeroOperands, |
307 | | CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_, |
308 | | CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_, |
309 | | CVT_imm_95_2, |
310 | | CVT_imm_95_6, |
311 | | CVT_imm_95_4, |
312 | | CVT_imm_95_5, |
313 | | CVT_imm_95_31, |
314 | | CVT_NUM_CONVERTERS |
315 | | }; |
316 | | |
317 | | enum InstructionConversionKind { |
318 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, |
319 | | Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, |
320 | | Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, |
321 | | Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, |
322 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, |
323 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, |
324 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, |
325 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, |
326 | | Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, |
327 | | Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, |
328 | | Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, |
329 | | Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, |
330 | | Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, |
331 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, |
332 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1, |
333 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, |
334 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2, |
335 | | Convert__SImm161_1, |
336 | | Convert__Reg1_0__SImm161_1, |
337 | | Convert__Reg1_0__SImm161_2, |
338 | | Convert__Reg1_0__Reg1_1__SImm161_2, |
339 | | Convert__Reg1_0__Tie0_1_1__SImm161_1, |
340 | | Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, |
341 | | Convert__GPRMM16AsmReg1_0__Imm1_1, |
342 | | Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1, |
343 | | Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, |
344 | | Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1, |
345 | | Convert__Imm1_0, |
346 | | Convert__Reg1_0__Reg1_1__Reg1_2, |
347 | | Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, |
348 | | Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, |
349 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, |
350 | | Convert__GPR32AsmReg1_0__SImm161_1, |
351 | | Convert__Reg1_0__Tie0_1_1__Reg1_1, |
352 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, |
353 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, |
354 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, |
355 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, |
356 | | Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, |
357 | | Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, |
358 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, |
359 | | Convert__regZERO__regZERO__JumpTarget1_0, |
360 | | Convert__JumpTarget1_0, |
361 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, |
362 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, |
363 | | Convert__regZERO__JumpTarget1_0, |
364 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1, |
365 | | Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, |
366 | | Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, |
367 | | Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, |
368 | | Convert__FGR64AsmReg1_0__JumpTarget1_1, |
369 | | Convert__regFCC0__JumpTarget1_0, |
370 | | Convert__FCCAsmReg1_0__JumpTarget1_1, |
371 | | Convert__COP2AsmReg1_0__JumpTarget1_1, |
372 | | Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, |
373 | | Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, |
374 | | Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, |
375 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, |
376 | | Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, |
377 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, |
378 | | Convert__Reg1_0__JumpTarget1_1, |
379 | | Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, |
380 | | Convert__GPRMM16AsmReg1_0__JumpTarget1_1, |
381 | | Convert__GPR32AsmReg1_0__JumpTarget1_1, |
382 | | Convert__GPR64AsmReg1_0__JumpTarget1_1, |
383 | | Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, |
384 | | Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2, |
385 | | Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2, |
386 | | Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2, |
387 | | Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2, |
388 | | Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, |
389 | | Convert__MSA128AsmReg1_0__JumpTarget1_1, |
390 | | Convert__imm_95_0__imm_95_0, |
391 | | Convert_NoOperands, |
392 | | Convert__ConstantUImm10_01_0__imm_95_0, |
393 | | Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, |
394 | | Convert__ConstantUImm4_01_0, |
395 | | Convert__SImm161_0, |
396 | | Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, |
397 | | Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, |
398 | | Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, |
399 | | Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, |
400 | | Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, |
401 | | Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, |
402 | | Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, |
403 | | Convert__Mem2_1__ConstantUImm5_01_0, |
404 | | Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, |
405 | | Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, |
406 | | Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, |
407 | | Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, |
408 | | Convert__GPR32AsmReg1_0__CCRAsmReg1_1, |
409 | | Convert__GPR32AsmReg1_0__COP2AsmReg1_1, |
410 | | Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1, |
411 | | Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, |
412 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, |
413 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, |
414 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, |
415 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, |
416 | | Convert__Reg1_0__Reg1_1, |
417 | | Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, |
418 | | Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, |
419 | | Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, |
420 | | Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, |
421 | | Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, |
422 | | Convert__CCRAsmReg1_1__GPR32AsmReg1_0, |
423 | | Convert__COP2AsmReg1_1__GPR32AsmReg1_0, |
424 | | Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1, |
425 | | Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, |
426 | | Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, |
427 | | Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, |
428 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, |
429 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, |
430 | | Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2, |
431 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3, |
432 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2, |
433 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, |
434 | | Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, |
435 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, |
436 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, |
437 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3, |
438 | | Convert__regZERO, |
439 | | Convert__GPR32AsmReg1_0, |
440 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1, |
441 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1, |
442 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1, |
443 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, |
444 | | Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1, |
445 | | Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1, |
446 | | Convert__Reg1_1__Reg1_2, |
447 | | Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, |
448 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, |
449 | | Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, |
450 | | Convert__GPR64AsmReg1_0__Imm1_1, |
451 | | Convert__GPR64AsmReg1_0__Mem2_1, |
452 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, |
453 | | Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, |
454 | | Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, |
455 | | Convert__GPR64AsmReg1_0__FGR64AsmReg1_1, |
456 | | Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0, |
457 | | Convert__GPR64AsmReg1_0__UImm161_1, |
458 | | Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, |
459 | | Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, |
460 | | Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, |
461 | | Convert__FGR64AsmReg1_1__GPR64AsmReg1_0, |
462 | | Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0, |
463 | | Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, |
464 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, |
465 | | Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, |
466 | | Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, |
467 | | Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, |
468 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_0, |
469 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1, |
470 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, |
471 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, |
472 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, |
473 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, |
474 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, |
475 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, |
476 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, |
477 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, |
478 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, |
479 | | Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, |
480 | | Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, |
481 | | Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, |
482 | | Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, |
483 | | Convert__MSA128AsmReg1_0__GPR64AsmReg1_1, |
484 | | Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2, |
485 | | Convert__GPR32AsmReg1_0__ConstantUImm2_01_1, |
486 | | Convert__imm_95_0, |
487 | | Convert__ConstantUImm10_01_0, |
488 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, |
489 | | Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2, |
490 | | Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2, |
491 | | Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2, |
492 | | Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2, |
493 | | Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1, |
494 | | Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6, |
495 | | Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6, |
496 | | Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6, |
497 | | Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6, |
498 | | Convert__regRA__GPR32AsmReg1_0, |
499 | | Convert__regRA_64__GPR64AsmReg1_0, |
500 | | Convert__Reg1_0, |
501 | | Convert__GPR32AsmReg1_0__imm_95_0, |
502 | | Convert__GPR64AsmReg1_0__imm_95_0, |
503 | | Convert__regZERO__GPR32AsmReg1_0, |
504 | | Convert__GPR64AsmReg1_0, |
505 | | Convert__regZERO_64__GPR64AsmReg1_0, |
506 | | Convert__UImm5Lsl21_0, |
507 | | Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, |
508 | | Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, |
509 | | Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, |
510 | | Convert__GPR32AsmReg1_0__Imm1_1, |
511 | | Convert__GPR32AsmReg1_0__Mem2_1, |
512 | | Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, |
513 | | Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, |
514 | | Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, |
515 | | Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, |
516 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, |
517 | | Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, |
518 | | Convert__MSA128AsmReg1_0__MemOffsetSimm102_1, |
519 | | Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1, |
520 | | Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1, |
521 | | Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1, |
522 | | Convert__COP2AsmReg1_0__MemOffsetSimm112_1, |
523 | | Convert__COP2AsmReg1_0__MemOffsetSimm162_1, |
524 | | Convert__COP3AsmReg1_0__Mem2_1, |
525 | | Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, |
526 | | Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1, |
527 | | Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, |
528 | | Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, |
529 | | Convert__GPR32AsmReg1_0__UImm32_Coerced1_1, |
530 | | Convert__StrictlyAFGR64AsmReg1_0__Imm1_1, |
531 | | Convert__StrictlyFGR64AsmReg1_0__Imm1_1, |
532 | | Convert__StrictlyFGR32AsmReg1_0__Imm1_1, |
533 | | Convert__GPRMM16AsmReg1_0__UImm7_N11_1, |
534 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, |
535 | | Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3, |
536 | | Convert__GPR32AsmReg1_0__UImm161_1, |
537 | | Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, |
538 | | Convert__Reg1_0__Imm1_1__imm_95_0, |
539 | | Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, |
540 | | Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1, |
541 | | Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, |
542 | | Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1, |
543 | | Convert__RegList1_0__Mem2_1, |
544 | | Convert__RegList161_0__MemOffsetUimm42_1, |
545 | | ConvertCustom_ConvertXWPOperands, |
546 | | Convert__GPR32AsmReg1_0__MemOffsetSimm122_1, |
547 | | Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, |
548 | | Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, |
549 | | Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, |
550 | | Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, |
551 | | Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, |
552 | | Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, |
553 | | Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, |
554 | | Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, |
555 | | Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, |
556 | | Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0, |
557 | | Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, |
558 | | Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, |
559 | | Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, |
560 | | Convert__GPR32AsmReg1_0__regAC0, |
561 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, |
562 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, |
563 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, |
564 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, |
565 | | Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3, |
566 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, |
567 | | Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, |
568 | | Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, |
569 | | Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, |
570 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, |
571 | | Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, |
572 | | Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, |
573 | | Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, |
574 | | Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, |
575 | | Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, |
576 | | Convert__FGR64AsmReg1_1__GPR32AsmReg1_0, |
577 | | Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0, |
578 | | Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, |
579 | | Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, |
580 | | Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, |
581 | | Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, |
582 | | Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1, |
583 | | Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, |
584 | | Convert__regAC0__GPR32AsmReg1_0, |
585 | | Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, |
586 | | Convert__GPR32AsmReg1_1__GPR32AsmReg1_0, |
587 | | Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, |
588 | | Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, |
589 | | Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, |
590 | | Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, |
591 | | Convert__regZERO__regZERO__imm_95_0, |
592 | | Convert__regZERO__regS0, |
593 | | Convert__regZERO__regZERO, |
594 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, |
595 | | Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, |
596 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, |
597 | | Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0, |
598 | | Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, |
599 | | Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, |
600 | | Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, |
601 | | Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, |
602 | | Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2, |
603 | | Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2, |
604 | | Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, |
605 | | Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, |
606 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, |
607 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, |
608 | | Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, |
609 | | Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, |
610 | | Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, |
611 | | Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, |
612 | | Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1, |
613 | | Convert__ConstantUImm20_01_0, |
614 | | Convert__Reg1_0__Tie0_1_1, |
615 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, |
616 | | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, |
617 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1, |
618 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2, |
619 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, |
620 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, |
621 | | Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1, |
622 | | Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1, |
623 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, |
624 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, |
625 | | Convert__UImm161_0, |
626 | | Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, |
627 | | Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3, |
628 | | Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3, |
629 | | Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3, |
630 | | Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3, |
631 | | Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, |
632 | | Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, |
633 | | Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, |
634 | | Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, |
635 | | Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, |
636 | | Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, |
637 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, |
638 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, |
639 | | Convert__ConstantUImm5_01_0, |
640 | | Convert__MemOffsetSimm162_0, |
641 | | Convert__imm_95_2, |
642 | | Convert__imm_95_6, |
643 | | Convert__imm_95_4, |
644 | | Convert__imm_95_5, |
645 | | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, |
646 | | Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2, |
647 | | Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2, |
648 | | Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2, |
649 | | Convert__GPR32AsmReg1_0__imm_95_31, |
650 | | CVT_NUM_SIGNATURES |
651 | | }; |
652 | | |
653 | | } // end anonymous namespace |
654 | | |
655 | | static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][11] = { |
656 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1 |
657 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
658 | | // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1 |
659 | | { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done }, |
660 | | // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1 |
661 | | { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done }, |
662 | | // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1 |
663 | | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, |
664 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1 |
665 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
666 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1 |
667 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done }, |
668 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2 |
669 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
670 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2 |
671 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done }, |
672 | | // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2 |
673 | | { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done }, |
674 | | // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2 |
675 | | { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done }, |
676 | | // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2 |
677 | | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done }, |
678 | | // Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1 |
679 | | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, |
680 | | // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2 |
681 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done }, |
682 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1 |
683 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, |
684 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1 |
685 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, |
686 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2 |
687 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, |
688 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2 |
689 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, |
690 | | // Convert__SImm161_1 |
691 | | { CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, |
692 | | // Convert__Reg1_0__SImm161_1 |
693 | | { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, |
694 | | // Convert__Reg1_0__SImm161_2 |
695 | | { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, |
696 | | // Convert__Reg1_0__Reg1_1__SImm161_2 |
697 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, |
698 | | // Convert__Reg1_0__Tie0_1_1__SImm161_1 |
699 | | { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, |
700 | | // Convert__GPR32AsmReg1_0__Simm19_Lsl21_1 |
701 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
702 | | // Convert__GPRMM16AsmReg1_0__Imm1_1 |
703 | | { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
704 | | // Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1 |
705 | | { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
706 | | // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2 |
707 | | { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
708 | | // Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1 |
709 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_, 2, CVT_Done }, |
710 | | // Convert__Imm1_0 |
711 | | { CVT_95_addImmOperands, 1, CVT_Done }, |
712 | | // Convert__Reg1_0__Reg1_1__Reg1_2 |
713 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done }, |
714 | | // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2 |
715 | | { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addGPRMM16AsmRegOperands, 3, CVT_Done }, |
716 | | // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2 |
717 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, |
718 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3 |
719 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done }, |
720 | | // Convert__GPR32AsmReg1_0__SImm161_1 |
721 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, |
722 | | // Convert__Reg1_0__Tie0_1_1__Reg1_1 |
723 | | { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done }, |
724 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1 |
725 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done }, |
726 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1 |
727 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
728 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2 |
729 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done }, |
730 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2 |
731 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
732 | | // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1 |
733 | | { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done }, |
734 | | // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2 |
735 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done }, |
736 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1 |
737 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
738 | | // Convert__regZERO__regZERO__JumpTarget1_0 |
739 | | { CVT_regZERO, 0, CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done }, |
740 | | // Convert__JumpTarget1_0 |
741 | | { CVT_95_addImmOperands, 1, CVT_Done }, |
742 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1 |
743 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done }, |
744 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2 |
745 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done }, |
746 | | // Convert__regZERO__JumpTarget1_0 |
747 | | { CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done }, |
748 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1 |
749 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
750 | | // Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2 |
751 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
752 | | // Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2 |
753 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
754 | | // Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2 |
755 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
756 | | // Convert__FGR64AsmReg1_0__JumpTarget1_1 |
757 | | { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
758 | | // Convert__regFCC0__JumpTarget1_0 |
759 | | { CVT_regFCC0, 0, CVT_95_addImmOperands, 1, CVT_Done }, |
760 | | // Convert__FCCAsmReg1_0__JumpTarget1_1 |
761 | | { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
762 | | // Convert__COP2AsmReg1_0__JumpTarget1_1 |
763 | | { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
764 | | // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2 |
765 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
766 | | // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2 |
767 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done }, |
768 | | // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2 |
769 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done }, |
770 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2 |
771 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
772 | | // Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2 |
773 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
774 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2 |
775 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
776 | | // Convert__Reg1_0__JumpTarget1_1 |
777 | | { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
778 | | // Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1 |
779 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addImmOperands, 2, CVT_Done }, |
780 | | // Convert__GPRMM16AsmReg1_0__JumpTarget1_1 |
781 | | { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
782 | | // Convert__GPR32AsmReg1_0__JumpTarget1_1 |
783 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
784 | | // Convert__GPR64AsmReg1_0__JumpTarget1_1 |
785 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
786 | | // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2 |
787 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done }, |
788 | | // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2 |
789 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
790 | | // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2 |
791 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done }, |
792 | | // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2 |
793 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done }, |
794 | | // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2 |
795 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, |
796 | | // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2 |
797 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done }, |
798 | | // Convert__MSA128AsmReg1_0__JumpTarget1_1 |
799 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
800 | | // Convert__imm_95_0__imm_95_0 |
801 | | { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done }, |
802 | | // Convert_NoOperands |
803 | | { CVT_Done }, |
804 | | // Convert__ConstantUImm10_01_0__imm_95_0 |
805 | | { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_imm_95_0, 0, CVT_Done }, |
806 | | // Convert__ConstantUImm10_01_0__ConstantUImm10_01_1 |
807 | | { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done }, |
808 | | // Convert__ConstantUImm4_01_0 |
809 | | { CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 1, CVT_Done }, |
810 | | // Convert__SImm161_0 |
811 | | { CVT_95_addSImmOperands_LT_16_GT_, 1, CVT_Done }, |
812 | | // Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1 |
813 | | { CVT_regFCC0, 0, CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done }, |
814 | | // Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1 |
815 | | { CVT_regFCC0, 0, CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done }, |
816 | | // Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2 |
817 | | { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done }, |
818 | | // Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2 |
819 | | { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done }, |
820 | | // Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1 |
821 | | { CVT_regFCC0, 0, CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, |
822 | | // Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2 |
823 | | { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done }, |
824 | | // Convert__MemOffsetSimm92_1__ConstantUImm5_01_0 |
825 | | { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done }, |
826 | | // Convert__Mem2_1__ConstantUImm5_01_0 |
827 | | { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done }, |
828 | | // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1 |
829 | | { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, |
830 | | // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1 |
831 | | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done }, |
832 | | // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1 |
833 | | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done }, |
834 | | // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2 |
835 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, |
836 | | // Convert__GPR32AsmReg1_0__CCRAsmReg1_1 |
837 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCCRAsmRegOperands, 2, CVT_Done }, |
838 | | // Convert__GPR32AsmReg1_0__COP2AsmReg1_1 |
839 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_Done }, |
840 | | // Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1 |
841 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSACtrlAsmRegOperands, 2, CVT_Done }, |
842 | | // Convert__GPR32AsmReg1_0__FGR32AsmReg1_1 |
843 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, |
844 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2 |
845 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, |
846 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2 |
847 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, |
848 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3 |
849 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done }, |
850 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3 |
851 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done }, |
852 | | // Convert__Reg1_0__Reg1_1 |
853 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done }, |
854 | | // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2 |
855 | | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done }, |
856 | | // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3 |
857 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done }, |
858 | | // Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3 |
859 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done }, |
860 | | // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3 |
861 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done }, |
862 | | // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3 |
863 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done }, |
864 | | // Convert__CCRAsmReg1_1__GPR32AsmReg1_0 |
865 | | { CVT_95_addCCRAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
866 | | // Convert__COP2AsmReg1_1__GPR32AsmReg1_0 |
867 | | { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
868 | | // Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1 |
869 | | { CVT_95_addMSACtrlAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
870 | | // Convert__FGR32AsmReg1_1__GPR32AsmReg1_0 |
871 | | { CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
872 | | // Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1 |
873 | | { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, |
874 | | // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2 |
875 | | { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done }, |
876 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1 |
877 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, |
878 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2 |
879 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, |
880 | | // Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2 |
881 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, |
882 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3 |
883 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done }, |
884 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2 |
885 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done }, |
886 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1 |
887 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done }, |
888 | | // Convert__GPR64AsmReg1_1__GPR64AsmReg1_2 |
889 | | { CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done }, |
890 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3 |
891 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_, 4, CVT_Done }, |
892 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3 |
893 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done }, |
894 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3 |
895 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done }, |
896 | | // Convert__regZERO |
897 | | { CVT_regZERO, 0, CVT_Done }, |
898 | | // Convert__GPR32AsmReg1_0 |
899 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
900 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1 |
901 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addImmOperands, 4, CVT_Tied, Tie0_1_1, CVT_Done }, |
902 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1 |
903 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done }, |
904 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1 |
905 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done }, |
906 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1 |
907 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done }, |
908 | | // Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1 |
909 | | { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
910 | | // Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1 |
911 | | { CVT_95_addGPR32ZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
912 | | // Convert__Reg1_1__Reg1_2 |
913 | | { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done }, |
914 | | // Convert__GPR32AsmReg1_1__GPR32AsmReg1_2 |
915 | | { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
916 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2 |
917 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done }, |
918 | | // Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2 |
919 | | { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
920 | | // Convert__GPR64AsmReg1_0__Imm1_1 |
921 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
922 | | // Convert__GPR64AsmReg1_0__Mem2_1 |
923 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
924 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3 |
925 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done }, |
926 | | // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0 |
927 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
928 | | // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2 |
929 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
930 | | // Convert__GPR64AsmReg1_0__FGR64AsmReg1_1 |
931 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done }, |
932 | | // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0 |
933 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
934 | | // Convert__GPR64AsmReg1_0__UImm161_1 |
935 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done }, |
936 | | // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2 |
937 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
938 | | // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0 |
939 | | { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
940 | | // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2 |
941 | | { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
942 | | // Convert__FGR64AsmReg1_1__GPR64AsmReg1_0 |
943 | | { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, |
944 | | // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0 |
945 | | { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
946 | | // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2 |
947 | | { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
948 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2 |
949 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done }, |
950 | | // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0 |
951 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, |
952 | | // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1 |
953 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done }, |
954 | | // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1 |
955 | | { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
956 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0 |
957 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, |
958 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1 |
959 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done }, |
960 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1 |
961 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 2, CVT_Done }, |
962 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2 |
963 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done }, |
964 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1 |
965 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done }, |
966 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2 |
967 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, |
968 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2 |
969 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
970 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1 |
971 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
972 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1 |
973 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
974 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2 |
975 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
976 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3 |
977 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done }, |
978 | | // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2 |
979 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, |
980 | | // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2 |
981 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
982 | | // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1 |
983 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_Done }, |
984 | | // Convert__MSA128AsmReg1_0__GPR32AsmReg1_1 |
985 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
986 | | // Convert__MSA128AsmReg1_0__GPR64AsmReg1_1 |
987 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done }, |
988 | | // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2 |
989 | | { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
990 | | // Convert__GPR32AsmReg1_0__ConstantUImm2_01_1 |
991 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 2, CVT_Done }, |
992 | | // Convert__imm_95_0 |
993 | | { CVT_imm_95_0, 0, CVT_Done }, |
994 | | // Convert__ConstantUImm10_01_0 |
995 | | { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_Done }, |
996 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1 |
997 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done }, |
998 | | // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2 |
999 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done }, |
1000 | | // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2 |
1001 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR64AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_Done }, |
1002 | | // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2 |
1003 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
1004 | | // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2 |
1005 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Done }, |
1006 | | // Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1 |
1007 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
1008 | | // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6 |
1009 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done }, |
1010 | | // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6 |
1011 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done }, |
1012 | | // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6 |
1013 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done }, |
1014 | | // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6 |
1015 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done }, |
1016 | | // Convert__regRA__GPR32AsmReg1_0 |
1017 | | { CVT_regRA, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
1018 | | // Convert__regRA_64__GPR64AsmReg1_0 |
1019 | | { CVT_regRA_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, |
1020 | | // Convert__Reg1_0 |
1021 | | { CVT_95_Reg, 1, CVT_Done }, |
1022 | | // Convert__GPR32AsmReg1_0__imm_95_0 |
1023 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
1024 | | // Convert__GPR64AsmReg1_0__imm_95_0 |
1025 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
1026 | | // Convert__regZERO__GPR32AsmReg1_0 |
1027 | | { CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
1028 | | // Convert__GPR64AsmReg1_0 |
1029 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, |
1030 | | // Convert__regZERO_64__GPR64AsmReg1_0 |
1031 | | { CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, |
1032 | | // Convert__UImm5Lsl21_0 |
1033 | | { CVT_95_addImmOperands, 1, CVT_Done }, |
1034 | | // Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1 |
1035 | | { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
1036 | | // Convert__FGR64AsmReg1_0__MemOffsetSimm162_1 |
1037 | | { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
1038 | | // Convert__FGR32AsmReg1_0__MemOffsetSimm162_1 |
1039 | | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
1040 | | // Convert__GPR32AsmReg1_0__Imm1_1 |
1041 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
1042 | | // Convert__GPR32AsmReg1_0__Mem2_1 |
1043 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
1044 | | // Convert__GPR32AsmReg1_0__MemOffsetSimm162_1 |
1045 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
1046 | | // Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1 |
1047 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
1048 | | // Convert__GPR32AsmReg1_0__MemOffsetSimm92_1 |
1049 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
1050 | | // Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1 |
1051 | | { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done }, |
1052 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1 |
1053 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
1054 | | // Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1 |
1055 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
1056 | | // Convert__MSA128AsmReg1_0__MemOffsetSimm102_1 |
1057 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
1058 | | // Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1 |
1059 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
1060 | | // Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1 |
1061 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
1062 | | // Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1 |
1063 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
1064 | | // Convert__COP2AsmReg1_0__MemOffsetSimm112_1 |
1065 | | { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
1066 | | // Convert__COP2AsmReg1_0__MemOffsetSimm162_1 |
1067 | | { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
1068 | | // Convert__COP3AsmReg1_0__Mem2_1 |
1069 | | { CVT_95_addCOP3AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
1070 | | // Convert__MSA128AsmReg1_0__ConstantSImm10_01_1 |
1071 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done }, |
1072 | | // Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1 |
1073 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done }, |
1074 | | // Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1 |
1075 | | { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
1076 | | // Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1 |
1077 | | { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
1078 | | // Convert__GPR32AsmReg1_0__UImm32_Coerced1_1 |
1079 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_32_GT_, 2, CVT_Done }, |
1080 | | // Convert__StrictlyAFGR64AsmReg1_0__Imm1_1 |
1081 | | { CVT_95_addStrictlyAFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
1082 | | // Convert__StrictlyFGR64AsmReg1_0__Imm1_1 |
1083 | | { CVT_95_addStrictlyFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
1084 | | // Convert__StrictlyFGR32AsmReg1_0__Imm1_1 |
1085 | | { CVT_95_addStrictlyFGR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
1086 | | // Convert__GPRMM16AsmReg1_0__UImm7_N11_1 |
1087 | | { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_, 2, CVT_Done }, |
1088 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3 |
1089 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done }, |
1090 | | // Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3 |
1091 | | { CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done }, |
1092 | | // Convert__GPR32AsmReg1_0__UImm161_1 |
1093 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done }, |
1094 | | // Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1 |
1095 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done }, |
1096 | | // Convert__Reg1_0__Imm1_1__imm_95_0 |
1097 | | { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
1098 | | // Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1 |
1099 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
1100 | | // Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1 |
1101 | | { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
1102 | | // Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1 |
1103 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done }, |
1104 | | // Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1 |
1105 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done }, |
1106 | | // Convert__RegList1_0__Mem2_1 |
1107 | | { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
1108 | | // Convert__RegList161_0__MemOffsetUimm42_1 |
1109 | | { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
1110 | | // ConvertCustom_ConvertXWPOperands |
1111 | | { CVT_ConvertXWPOperands, 0, CVT_Done }, |
1112 | | // Convert__GPR32AsmReg1_0__MemOffsetSimm122_1 |
1113 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
1114 | | // Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1 |
1115 | | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
1116 | | // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3 |
1117 | | { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_95_addAFGR64AsmRegOperands, 4, CVT_Done }, |
1118 | | // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3 |
1119 | | { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_95_addFGR64AsmRegOperands, 4, CVT_Done }, |
1120 | | // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3 |
1121 | | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 4, CVT_Done }, |
1122 | | // Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2 |
1123 | | { CVT_95_addFGR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done }, |
1124 | | // Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2 |
1125 | | { CVT_95_addFGR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done }, |
1126 | | // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0 |
1127 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
1128 | | // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2 |
1129 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
1130 | | // Convert__GPR32AsmReg1_0__FGR64AsmReg1_1 |
1131 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done }, |
1132 | | // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0 |
1133 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
1134 | | // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2 |
1135 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
1136 | | // Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1 |
1137 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done }, |
1138 | | // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1 |
1139 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_Done }, |
1140 | | // Convert__GPR32AsmReg1_0__regAC0 |
1141 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_regAC0, 0, CVT_Done }, |
1142 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0 |
1143 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
1144 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4 |
1145 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done }, |
1146 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO |
1147 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_regZERO, 0, CVT_Done }, |
1148 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64 |
1149 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_regZERO_64, 0, CVT_Done }, |
1150 | | // Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3 |
1151 | | { CVT_95_addGPRMM16AsmRegMovePPairFirstOperands, 1, CVT_95_addGPRMM16AsmRegMovePPairSecondOperands, 2, CVT_95_addGPRMM16AsmRegMovePOperands, 3, CVT_95_addGPRMM16AsmRegMovePOperands, 4, CVT_Done }, |
1152 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1 |
1153 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
1154 | | // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1 |
1155 | | { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
1156 | | // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1 |
1157 | | { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
1158 | | // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1 |
1159 | | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
1160 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1 |
1161 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
1162 | | // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1 |
1163 | | { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
1164 | | // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1 |
1165 | | { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
1166 | | // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1 |
1167 | | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
1168 | | // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0 |
1169 | | { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
1170 | | // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2 |
1171 | | { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
1172 | | // Convert__FGR64AsmReg1_1__GPR32AsmReg1_0 |
1173 | | { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
1174 | | // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0 |
1175 | | { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
1176 | | // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2 |
1177 | | { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
1178 | | // Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0 |
1179 | | { CVT_95_addAFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
1180 | | // Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0 |
1181 | | { CVT_95_addFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
1182 | | // Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0 |
1183 | | { CVT_95_addHI32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
1184 | | // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1 |
1185 | | { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_Done }, |
1186 | | // Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0 |
1187 | | { CVT_95_addLO32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
1188 | | // Convert__regAC0__GPR32AsmReg1_0 |
1189 | | { CVT_regAC0, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
1190 | | // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0 |
1191 | | { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
1192 | | // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0 |
1193 | | { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
1194 | | // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4 |
1195 | | { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done }, |
1196 | | // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2 |
1197 | | { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
1198 | | // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0 |
1199 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
1200 | | // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1 |
1201 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
1202 | | // Convert__regZERO__regZERO__imm_95_0 |
1203 | | { CVT_regZERO, 0, CVT_regZERO, 0, CVT_imm_95_0, 0, CVT_Done }, |
1204 | | // Convert__regZERO__regS0 |
1205 | | { CVT_regZERO, 0, CVT_regS0, 0, CVT_Done }, |
1206 | | // Convert__regZERO__regZERO |
1207 | | { CVT_regZERO, 0, CVT_regZERO, 0, CVT_Done }, |
1208 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO |
1209 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_Done }, |
1210 | | // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1 |
1211 | | { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Done }, |
1212 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0 |
1213 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
1214 | | // Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0 |
1215 | | { CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done }, |
1216 | | // Convert__GPR32AsmReg1_0__ConstantUImm7_01_1 |
1217 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_, 2, CVT_Done }, |
1218 | | // Convert__GPR32AsmReg1_0__ConstantUImm10_01_1 |
1219 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done }, |
1220 | | // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0 |
1221 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
1222 | | // Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0 |
1223 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
1224 | | // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2 |
1225 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
1226 | | // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2 |
1227 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done }, |
1228 | | // Convert__GPR32AsmReg1_0__ConstantSImm10_01_1 |
1229 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done }, |
1230 | | // Convert__GPR32AsmReg1_0__ConstantUImm8_01_1 |
1231 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 2, CVT_Done }, |
1232 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1 |
1233 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done }, |
1234 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2 |
1235 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, |
1236 | | // Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1 |
1237 | | { CVT_95_addGPRMM16AsmRegZeroOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done }, |
1238 | | // Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1 |
1239 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done }, |
1240 | | // Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1 |
1241 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done }, |
1242 | | // Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1 |
1243 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done }, |
1244 | | // Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1 |
1245 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done }, |
1246 | | // Convert__ConstantUImm20_01_0 |
1247 | | { CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_, 1, CVT_Done }, |
1248 | | // Convert__Reg1_0__Tie0_1_1 |
1249 | | { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done }, |
1250 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1 |
1251 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done }, |
1252 | | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2 |
1253 | | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done }, |
1254 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1 |
1255 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_32_GT_, 2, CVT_Done }, |
1256 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2 |
1257 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_32_GT_, 3, CVT_Done }, |
1258 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0 |
1259 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
1260 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1 |
1261 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
1262 | | // Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1 |
1263 | | { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_, 2, CVT_Tied, Tie0_1_1, CVT_Done }, |
1264 | | // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1 |
1265 | | { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done }, |
1266 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2 |
1267 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done }, |
1268 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2 |
1269 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
1270 | | // Convert__UImm161_0 |
1271 | | { CVT_95_addUImmOperands_LT_16_GT_, 1, CVT_Done }, |
1272 | | // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3 |
1273 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done }, |
1274 | | // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3 |
1275 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done }, |
1276 | | // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3 |
1277 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done }, |
1278 | | // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3 |
1279 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done }, |
1280 | | // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3 |
1281 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done }, |
1282 | | // Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2 |
1283 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, |
1284 | | // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3 |
1285 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done }, |
1286 | | // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3 |
1287 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done }, |
1288 | | // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3 |
1289 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done }, |
1290 | | // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3 |
1291 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done }, |
1292 | | // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3 |
1293 | | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done }, |
1294 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1 |
1295 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
1296 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2 |
1297 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
1298 | | // Convert__ConstantUImm5_01_0 |
1299 | | { CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done }, |
1300 | | // Convert__MemOffsetSimm162_0 |
1301 | | { CVT_95_addMemOperands, 1, CVT_Done }, |
1302 | | // Convert__imm_95_2 |
1303 | | { CVT_imm_95_2, 0, CVT_Done }, |
1304 | | // Convert__imm_95_6 |
1305 | | { CVT_imm_95_6, 0, CVT_Done }, |
1306 | | // Convert__imm_95_4 |
1307 | | { CVT_imm_95_4, 0, CVT_Done }, |
1308 | | // Convert__imm_95_5 |
1309 | | { CVT_imm_95_5, 0, CVT_Done }, |
1310 | | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2 |
1311 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done }, |
1312 | | // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2 |
1313 | | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
1314 | | // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2 |
1315 | | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
1316 | | // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2 |
1317 | | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
1318 | | // Convert__GPR32AsmReg1_0__imm_95_31 |
1319 | | { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_31, 0, CVT_Done }, |
1320 | | }; |
1321 | | |
1322 | | void MipsAsmParser:: |
1323 | | convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, |
1324 | 36.3k | const OperandVector &Operands) { |
1325 | 36.3k | assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); |
1326 | 36.3k | const uint8_t *Converter = ConversionTable[Kind]; |
1327 | 36.3k | unsigned OpIdx; |
1328 | 36.3k | Inst.setOpcode(Opcode); |
1329 | 126k | for (const uint8_t *p = Converter; *p; p+= 290.4k ) { |
1330 | 90.4k | OpIdx = *(p + 1); |
1331 | 90.4k | switch (*p) { |
1332 | 90.4k | default: 0 llvm_unreachable0 ("invalid conversion entry!"); |
1333 | 90.4k | case CVT_Reg: |
1334 | 0 | static_cast<MipsOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1); |
1335 | 0 | break; |
1336 | 90.4k | case CVT_Tied: { |
1337 | 627 | assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) - |
1338 | 627 | std::begin(TiedAsmOperandTable)) && |
1339 | 627 | "Tied operand not found"); |
1340 | 627 | unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0]; |
1341 | 627 | if (TiedResOpnd != (uint8_t) -1) |
1342 | 627 | Inst.addOperand(Inst.getOperand(TiedResOpnd)); |
1343 | 627 | break; |
1344 | 90.4k | } |
1345 | 90.4k | case CVT_95_addGPR32AsmRegOperands: |
1346 | 24.2k | static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32AsmRegOperands(Inst, 1); |
1347 | 24.2k | break; |
1348 | 90.4k | case CVT_95_addAFGR64AsmRegOperands: |
1349 | 926 | static_cast<MipsOperand&>(*Operands[OpIdx]).addAFGR64AsmRegOperands(Inst, 1); |
1350 | 926 | break; |
1351 | 90.4k | case CVT_95_addFGR64AsmRegOperands: |
1352 | 1.31k | static_cast<MipsOperand&>(*Operands[OpIdx]).addFGR64AsmRegOperands(Inst, 1); |
1353 | 1.31k | break; |
1354 | 90.4k | case CVT_95_addFGR32AsmRegOperands: |
1355 | 2.55k | static_cast<MipsOperand&>(*Operands[OpIdx]).addFGR32AsmRegOperands(Inst, 1); |
1356 | 2.55k | break; |
1357 | 90.4k | case CVT_95_addSImmOperands_LT_32_GT_: |
1358 | 642 | static_cast<MipsOperand&>(*Operands[OpIdx]).addSImmOperands<32>(Inst, 1); |
1359 | 642 | break; |
1360 | 90.4k | case CVT_95_addMSA128AsmRegOperands: |
1361 | 1.40k | static_cast<MipsOperand&>(*Operands[OpIdx]).addMSA128AsmRegOperands(Inst, 1); |
1362 | 1.40k | break; |
1363 | 90.4k | case CVT_95_addSImmOperands_LT_16_GT_: |
1364 | 1.34k | static_cast<MipsOperand&>(*Operands[OpIdx]).addSImmOperands<16>(Inst, 1); |
1365 | 1.34k | break; |
1366 | 90.4k | case CVT_95_Reg: |
1367 | 0 | static_cast<MipsOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1); |
1368 | 0 | break; |
1369 | 90.4k | case CVT_95_addImmOperands: |
1370 | 3.59k | static_cast<MipsOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1); |
1371 | 3.59k | break; |
1372 | 90.4k | case CVT_95_addGPRMM16AsmRegOperands: |
1373 | 178 | static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegOperands(Inst, 1); |
1374 | 178 | break; |
1375 | 90.4k | case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_: |
1376 | 4 | static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<4, 0>(Inst, 1); |
1377 | 4 | break; |
1378 | 90.4k | case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_: |
1379 | 475 | static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 0>(Inst, 1); |
1380 | 475 | break; |
1381 | 90.4k | case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_: |
1382 | 14 | static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<2, 0>(Inst, 1); |
1383 | 14 | break; |
1384 | 90.4k | case CVT_95_addUImmOperands_LT_16_GT_: |
1385 | 236 | static_cast<MipsOperand&>(*Operands[OpIdx]).addUImmOperands<16>(Inst, 1); |
1386 | 236 | break; |
1387 | 90.4k | case CVT_95_addGPR64AsmRegOperands: |
1388 | 3.99k | static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR64AsmRegOperands(Inst, 1); |
1389 | 3.99k | break; |
1390 | 90.4k | case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_: |
1391 | 15 | static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<8, 0>(Inst, 1); |
1392 | 15 | break; |
1393 | 90.4k | case CVT_regZERO: |
1394 | 22.0k | Inst.addOperand(MCOperand::createReg(Mips::ZERO)); |
1395 | 22.0k | break; |
1396 | 90.4k | case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_: |
1397 | 6 | static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 32, -32>(Inst, 1); |
1398 | 6 | break; |
1399 | 90.4k | case CVT_regFCC0: |
1400 | 282 | Inst.addOperand(MCOperand::createReg(Mips::FCC0)); |
1401 | 282 | break; |
1402 | 90.4k | case CVT_95_addFCCAsmRegOperands: |
1403 | 734 | static_cast<MipsOperand&>(*Operands[OpIdx]).addFCCAsmRegOperands(Inst, 1); |
1404 | 734 | break; |
1405 | 90.4k | case CVT_95_addCOP2AsmRegOperands: |
1406 | 122 | static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP2AsmRegOperands(Inst, 1); |
1407 | 122 | break; |
1408 | 90.4k | case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_: |
1409 | 155 | static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<3, 0>(Inst, 1); |
1410 | 155 | break; |
1411 | 90.4k | case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_: |
1412 | 76 | static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<6, 0>(Inst, 1); |
1413 | 76 | break; |
1414 | 90.4k | case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_: |
1415 | 62 | static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<4, 0>(Inst, 1); |
1416 | 62 | break; |
1417 | 90.4k | case CVT_imm_95_0: |
1418 | 11.1k | Inst.addOperand(MCOperand::createImm(0)); |
1419 | 11.1k | break; |
1420 | 90.4k | case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_: |
1421 | 132 | static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<10, 0>(Inst, 1); |
1422 | 132 | break; |
1423 | 90.4k | case CVT_95_addMemOperands: |
1424 | 12.6k | static_cast<MipsOperand&>(*Operands[OpIdx]).addMemOperands(Inst, 2); |
1425 | 12.6k | break; |
1426 | 90.4k | case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_: |
1427 | 20 | static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<5, 0>(Inst, 1); |
1428 | 20 | break; |
1429 | 90.4k | case CVT_95_addCCRAsmRegOperands: |
1430 | 38 | static_cast<MipsOperand&>(*Operands[OpIdx]).addCCRAsmRegOperands(Inst, 1); |
1431 | 38 | break; |
1432 | 90.4k | case CVT_95_addMSACtrlAsmRegOperands: |
1433 | 32 | static_cast<MipsOperand&>(*Operands[OpIdx]).addMSACtrlAsmRegOperands(Inst, 1); |
1434 | 32 | break; |
1435 | 90.4k | case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_: |
1436 | 53 | static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<1, 0>(Inst, 1); |
1437 | 53 | break; |
1438 | 90.4k | case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_: |
1439 | 10 | static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 33>(Inst, 1); |
1440 | 10 | break; |
1441 | 90.4k | case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_: |
1442 | 20 | static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 32>(Inst, 1); |
1443 | 20 | break; |
1444 | 90.4k | case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_: |
1445 | 42 | static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 1>(Inst, 1); |
1446 | 42 | break; |
1447 | 90.4k | case CVT_95_addGPR32NonZeroAsmRegOperands: |
1448 | 50 | static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32NonZeroAsmRegOperands(Inst, 1); |
1449 | 50 | break; |
1450 | 90.4k | case CVT_95_addGPR32ZeroAsmRegOperands: |
1451 | 16 | static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32ZeroAsmRegOperands(Inst, 1); |
1452 | 16 | break; |
1453 | 90.4k | case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_: |
1454 | 12 | static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<2, 1>(Inst, 1); |
1455 | 12 | break; |
1456 | 90.4k | case CVT_95_addCOP0AsmRegOperands: |
1457 | 116 | static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP0AsmRegOperands(Inst, 1); |
1458 | 116 | break; |
1459 | 90.4k | case CVT_regZERO_64: |
1460 | 87 | Inst.addOperand(MCOperand::createReg(Mips::ZERO_64)); |
1461 | 87 | break; |
1462 | 90.4k | case CVT_95_addACC64DSPAsmRegOperands: |
1463 | 180 | static_cast<MipsOperand&>(*Operands[OpIdx]).addACC64DSPAsmRegOperands(Inst, 1); |
1464 | 180 | break; |
1465 | 90.4k | case CVT_95_addConstantUImmOperands_LT_1_GT_: |
1466 | 4 | static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<1>(Inst, 1); |
1467 | 4 | break; |
1468 | 90.4k | case CVT_regRA: |
1469 | 40 | Inst.addOperand(MCOperand::createReg(Mips::RA)); |
1470 | 40 | break; |
1471 | 90.4k | case CVT_regRA_64: |
1472 | 5 | Inst.addOperand(MCOperand::createReg(Mips::RA_64)); |
1473 | 5 | break; |
1474 | 90.4k | case CVT_95_addMicroMipsMemOperands: |
1475 | 50 | static_cast<MipsOperand&>(*Operands[OpIdx]).addMicroMipsMemOperands(Inst, 2); |
1476 | 50 | break; |
1477 | 90.4k | case CVT_95_addCOP3AsmRegOperands: |
1478 | 6 | static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP3AsmRegOperands(Inst, 1); |
1479 | 6 | break; |
1480 | 90.4k | case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_: |
1481 | 12 | static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<10, 0>(Inst, 1); |
1482 | 12 | break; |
1483 | 90.4k | case CVT_95_addConstantUImmOperands_LT_32_GT_: |
1484 | 212 | static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<32>(Inst, 1); |
1485 | 212 | break; |
1486 | 90.4k | case CVT_95_addStrictlyAFGR64AsmRegOperands: |
1487 | 39 | static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyAFGR64AsmRegOperands(Inst, 1); |
1488 | 39 | break; |
1489 | 90.4k | case CVT_95_addStrictlyFGR64AsmRegOperands: |
1490 | 52 | static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyFGR64AsmRegOperands(Inst, 1); |
1491 | 52 | break; |
1492 | 90.4k | case CVT_95_addStrictlyFGR32AsmRegOperands: |
1493 | 66 | static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyFGR32AsmRegOperands(Inst, 1); |
1494 | 66 | break; |
1495 | 90.4k | case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_: |
1496 | 7 | static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<7, -1>(Inst, 1); |
1497 | 7 | break; |
1498 | 90.4k | case CVT_95_addRegListOperands: |
1499 | 63 | static_cast<MipsOperand&>(*Operands[OpIdx]).addRegListOperands(Inst, 1); |
1500 | 63 | break; |
1501 | 90.4k | case CVT_ConvertXWPOperands: |
1502 | 14 | ConvertXWPOperands(Inst, Operands); |
1503 | 14 | break; |
1504 | 90.4k | case CVT_regAC0: |
1505 | 4 | Inst.addOperand(MCOperand::createReg(Mips::AC0)); |
1506 | 4 | break; |
1507 | 90.4k | case CVT_95_addGPRMM16AsmRegMovePPairFirstOperands: |
1508 | 6 | static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegMovePPairFirstOperands(Inst, 1); |
1509 | 6 | break; |
1510 | 90.4k | case CVT_95_addGPRMM16AsmRegMovePPairSecondOperands: |
1511 | 6 | static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegMovePPairSecondOperands(Inst, 1); |
1512 | 6 | break; |
1513 | 90.4k | case CVT_95_addGPRMM16AsmRegMovePOperands: |
1514 | 12 | static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegMovePOperands(Inst, 1); |
1515 | 12 | break; |
1516 | 90.4k | case CVT_95_addHI32DSPAsmRegOperands: |
1517 | 3 | static_cast<MipsOperand&>(*Operands[OpIdx]).addHI32DSPAsmRegOperands(Inst, 1); |
1518 | 3 | break; |
1519 | 90.4k | case CVT_95_addLO32DSPAsmRegOperands: |
1520 | 3 | static_cast<MipsOperand&>(*Operands[OpIdx]).addLO32DSPAsmRegOperands(Inst, 1); |
1521 | 3 | break; |
1522 | 90.4k | case CVT_regS0: |
1523 | 2 | Inst.addOperand(MCOperand::createReg(Mips::S0)); |
1524 | 2 | break; |
1525 | 90.4k | case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_: |
1526 | 5 | static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<7, 0>(Inst, 1); |
1527 | 5 | break; |
1528 | 90.4k | case CVT_95_addHWRegsAsmRegOperands: |
1529 | 60 | static_cast<MipsOperand&>(*Operands[OpIdx]).addHWRegsAsmRegOperands(Inst, 1); |
1530 | 60 | break; |
1531 | 90.4k | case CVT_95_addGPRMM16AsmRegZeroOperands: |
1532 | 22 | static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegZeroOperands(Inst, 1); |
1533 | 22 | break; |
1534 | 90.4k | case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_: |
1535 | 25 | static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<20, 0>(Inst, 1); |
1536 | 25 | break; |
1537 | 90.4k | case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_: |
1538 | 6 | static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<6, 0>(Inst, 1); |
1539 | 6 | break; |
1540 | 90.4k | case CVT_imm_95_2: |
1541 | 1 | Inst.addOperand(MCOperand::createImm(2)); |
1542 | 1 | break; |
1543 | 90.4k | case CVT_imm_95_6: |
1544 | 1 | Inst.addOperand(MCOperand::createImm(6)); |
1545 | 1 | break; |
1546 | 90.4k | case CVT_imm_95_4: |
1547 | 1 | Inst.addOperand(MCOperand::createImm(4)); |
1548 | 1 | break; |
1549 | 90.4k | case CVT_imm_95_5: |
1550 | 1 | Inst.addOperand(MCOperand::createImm(5)); |
1551 | 1 | break; |
1552 | 90.4k | case CVT_imm_95_31: |
1553 | 4 | Inst.addOperand(MCOperand::createImm(31)); |
1554 | 4 | break; |
1555 | 90.4k | } |
1556 | 90.4k | } |
1557 | 36.3k | } |
1558 | | |
1559 | | void MipsAsmParser:: |
1560 | | convertToMapAndConstraints(unsigned Kind, |
1561 | 0 | const OperandVector &Operands) { |
1562 | 0 | assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); |
1563 | 0 | unsigned NumMCOperands = 0; |
1564 | 0 | const uint8_t *Converter = ConversionTable[Kind]; |
1565 | 0 | for (const uint8_t *p = Converter; *p; p+= 2) { |
1566 | 0 | switch (*p) { |
1567 | 0 | default: llvm_unreachable("invalid conversion entry!"); |
1568 | 0 | case CVT_Reg: |
1569 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1570 | 0 | Operands[*(p + 1)]->setConstraint("r"); |
1571 | 0 | ++NumMCOperands; |
1572 | 0 | break; |
1573 | 0 | case CVT_Tied: |
1574 | 0 | ++NumMCOperands; |
1575 | 0 | break; |
1576 | 0 | case CVT_95_addGPR32AsmRegOperands: |
1577 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1578 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1579 | 0 | NumMCOperands += 1; |
1580 | 0 | break; |
1581 | 0 | case CVT_95_addAFGR64AsmRegOperands: |
1582 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1583 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1584 | 0 | NumMCOperands += 1; |
1585 | 0 | break; |
1586 | 0 | case CVT_95_addFGR64AsmRegOperands: |
1587 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1588 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1589 | 0 | NumMCOperands += 1; |
1590 | 0 | break; |
1591 | 0 | case CVT_95_addFGR32AsmRegOperands: |
1592 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1593 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1594 | 0 | NumMCOperands += 1; |
1595 | 0 | break; |
1596 | 0 | case CVT_95_addSImmOperands_LT_32_GT_: |
1597 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1598 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1599 | 0 | NumMCOperands += 1; |
1600 | 0 | break; |
1601 | 0 | case CVT_95_addMSA128AsmRegOperands: |
1602 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1603 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1604 | 0 | NumMCOperands += 1; |
1605 | 0 | break; |
1606 | 0 | case CVT_95_addSImmOperands_LT_16_GT_: |
1607 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1608 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1609 | 0 | NumMCOperands += 1; |
1610 | 0 | break; |
1611 | 0 | case CVT_95_Reg: |
1612 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1613 | 0 | Operands[*(p + 1)]->setConstraint("r"); |
1614 | 0 | NumMCOperands += 1; |
1615 | 0 | break; |
1616 | 0 | case CVT_95_addImmOperands: |
1617 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1618 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1619 | 0 | NumMCOperands += 1; |
1620 | 0 | break; |
1621 | 0 | case CVT_95_addGPRMM16AsmRegOperands: |
1622 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1623 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1624 | 0 | NumMCOperands += 1; |
1625 | 0 | break; |
1626 | 0 | case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_: |
1627 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1628 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1629 | 0 | NumMCOperands += 1; |
1630 | 0 | break; |
1631 | 0 | case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_: |
1632 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1633 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1634 | 0 | NumMCOperands += 1; |
1635 | 0 | break; |
1636 | 0 | case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_: |
1637 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1638 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1639 | 0 | NumMCOperands += 1; |
1640 | 0 | break; |
1641 | 0 | case CVT_95_addUImmOperands_LT_16_GT_: |
1642 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1643 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1644 | 0 | NumMCOperands += 1; |
1645 | 0 | break; |
1646 | 0 | case CVT_95_addGPR64AsmRegOperands: |
1647 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1648 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1649 | 0 | NumMCOperands += 1; |
1650 | 0 | break; |
1651 | 0 | case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_: |
1652 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1653 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1654 | 0 | NumMCOperands += 1; |
1655 | 0 | break; |
1656 | 0 | case CVT_regZERO: |
1657 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1658 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1659 | 0 | ++NumMCOperands; |
1660 | 0 | break; |
1661 | 0 | case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_: |
1662 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1663 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1664 | 0 | NumMCOperands += 1; |
1665 | 0 | break; |
1666 | 0 | case CVT_regFCC0: |
1667 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1668 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1669 | 0 | ++NumMCOperands; |
1670 | 0 | break; |
1671 | 0 | case CVT_95_addFCCAsmRegOperands: |
1672 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1673 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1674 | 0 | NumMCOperands += 1; |
1675 | 0 | break; |
1676 | 0 | case CVT_95_addCOP2AsmRegOperands: |
1677 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1678 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1679 | 0 | NumMCOperands += 1; |
1680 | 0 | break; |
1681 | 0 | case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_: |
1682 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1683 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1684 | 0 | NumMCOperands += 1; |
1685 | 0 | break; |
1686 | 0 | case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_: |
1687 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1688 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1689 | 0 | NumMCOperands += 1; |
1690 | 0 | break; |
1691 | 0 | case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_: |
1692 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1693 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1694 | 0 | NumMCOperands += 1; |
1695 | 0 | break; |
1696 | 0 | case CVT_imm_95_0: |
1697 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1698 | 0 | Operands[*(p + 1)]->setConstraint(""); |
1699 | 0 | ++NumMCOperands; |
1700 | 0 | break; |
1701 | 0 | case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_: |
1702 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1703 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1704 | 0 | NumMCOperands += 1; |
1705 | 0 | break; |
1706 | 0 | case CVT_95_addMemOperands: |
1707 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1708 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1709 | 0 | NumMCOperands += 2; |
1710 | 0 | break; |
1711 | 0 | case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_: |
1712 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1713 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1714 | 0 | NumMCOperands += 1; |
1715 | 0 | break; |
1716 | 0 | case CVT_95_addCCRAsmRegOperands: |
1717 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1718 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1719 | 0 | NumMCOperands += 1; |
1720 | 0 | break; |
1721 | 0 | case CVT_95_addMSACtrlAsmRegOperands: |
1722 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1723 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1724 | 0 | NumMCOperands += 1; |
1725 | 0 | break; |
1726 | 0 | case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_: |
1727 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1728 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1729 | 0 | NumMCOperands += 1; |
1730 | 0 | break; |
1731 | 0 | case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_: |
1732 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1733 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1734 | 0 | NumMCOperands += 1; |
1735 | 0 | break; |
1736 | 0 | case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_: |
1737 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1738 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1739 | 0 | NumMCOperands += 1; |
1740 | 0 | break; |
1741 | 0 | case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_: |
1742 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1743 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1744 | 0 | NumMCOperands += 1; |
1745 | 0 | break; |
1746 | 0 | case CVT_95_addGPR32NonZeroAsmRegOperands: |
1747 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1748 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1749 | 0 | NumMCOperands += 1; |
1750 | 0 | break; |
1751 | 0 | case CVT_95_addGPR32ZeroAsmRegOperands: |
1752 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1753 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1754 | 0 | NumMCOperands += 1; |
1755 | 0 | break; |
1756 | 0 | case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_: |
1757 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1758 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1759 | 0 | NumMCOperands += 1; |
1760 | 0 | break; |
1761 | 0 | case CVT_95_addCOP0AsmRegOperands: |
1762 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1763 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1764 | 0 | NumMCOperands += 1; |
1765 | 0 | break; |
1766 | 0 | case CVT_regZERO_64: |
1767 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1768 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1769 | 0 | ++NumMCOperands; |
1770 | 0 | break; |
1771 | 0 | case CVT_95_addACC64DSPAsmRegOperands: |
1772 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1773 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1774 | 0 | NumMCOperands += 1; |
1775 | 0 | break; |
1776 | 0 | case CVT_95_addConstantUImmOperands_LT_1_GT_: |
1777 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1778 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1779 | 0 | NumMCOperands += 1; |
1780 | 0 | break; |
1781 | 0 | case CVT_regRA: |
1782 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1783 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1784 | 0 | ++NumMCOperands; |
1785 | 0 | break; |
1786 | 0 | case CVT_regRA_64: |
1787 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1788 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1789 | 0 | ++NumMCOperands; |
1790 | 0 | break; |
1791 | 0 | case CVT_95_addMicroMipsMemOperands: |
1792 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1793 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1794 | 0 | NumMCOperands += 2; |
1795 | 0 | break; |
1796 | 0 | case CVT_95_addCOP3AsmRegOperands: |
1797 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1798 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1799 | 0 | NumMCOperands += 1; |
1800 | 0 | break; |
1801 | 0 | case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_: |
1802 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1803 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1804 | 0 | NumMCOperands += 1; |
1805 | 0 | break; |
1806 | 0 | case CVT_95_addConstantUImmOperands_LT_32_GT_: |
1807 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1808 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1809 | 0 | NumMCOperands += 1; |
1810 | 0 | break; |
1811 | 0 | case CVT_95_addStrictlyAFGR64AsmRegOperands: |
1812 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1813 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1814 | 0 | NumMCOperands += 1; |
1815 | 0 | break; |
1816 | 0 | case CVT_95_addStrictlyFGR64AsmRegOperands: |
1817 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1818 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1819 | 0 | NumMCOperands += 1; |
1820 | 0 | break; |
1821 | 0 | case CVT_95_addStrictlyFGR32AsmRegOperands: |
1822 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1823 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1824 | 0 | NumMCOperands += 1; |
1825 | 0 | break; |
1826 | 0 | case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_: |
1827 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1828 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1829 | 0 | NumMCOperands += 1; |
1830 | 0 | break; |
1831 | 0 | case CVT_95_addRegListOperands: |
1832 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1833 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1834 | 0 | NumMCOperands += 1; |
1835 | 0 | break; |
1836 | 0 | case CVT_regAC0: |
1837 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1838 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1839 | 0 | ++NumMCOperands; |
1840 | 0 | break; |
1841 | 0 | case CVT_95_addGPRMM16AsmRegMovePPairFirstOperands: |
1842 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1843 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1844 | 0 | NumMCOperands += 1; |
1845 | 0 | break; |
1846 | 0 | case CVT_95_addGPRMM16AsmRegMovePPairSecondOperands: |
1847 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1848 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1849 | 0 | NumMCOperands += 1; |
1850 | 0 | break; |
1851 | 0 | case CVT_95_addGPRMM16AsmRegMovePOperands: |
1852 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1853 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1854 | 0 | NumMCOperands += 1; |
1855 | 0 | break; |
1856 | 0 | case CVT_95_addHI32DSPAsmRegOperands: |
1857 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1858 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1859 | 0 | NumMCOperands += 1; |
1860 | 0 | break; |
1861 | 0 | case CVT_95_addLO32DSPAsmRegOperands: |
1862 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1863 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1864 | 0 | NumMCOperands += 1; |
1865 | 0 | break; |
1866 | 0 | case CVT_regS0: |
1867 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1868 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1869 | 0 | ++NumMCOperands; |
1870 | 0 | break; |
1871 | 0 | case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_: |
1872 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1873 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1874 | 0 | NumMCOperands += 1; |
1875 | 0 | break; |
1876 | 0 | case CVT_95_addHWRegsAsmRegOperands: |
1877 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1878 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1879 | 0 | NumMCOperands += 1; |
1880 | 0 | break; |
1881 | 0 | case CVT_95_addGPRMM16AsmRegZeroOperands: |
1882 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1883 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1884 | 0 | NumMCOperands += 1; |
1885 | 0 | break; |
1886 | 0 | case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_: |
1887 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1888 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1889 | 0 | NumMCOperands += 1; |
1890 | 0 | break; |
1891 | 0 | case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_: |
1892 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1893 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
1894 | 0 | NumMCOperands += 1; |
1895 | 0 | break; |
1896 | 0 | case CVT_imm_95_2: |
1897 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1898 | 0 | Operands[*(p + 1)]->setConstraint(""); |
1899 | 0 | ++NumMCOperands; |
1900 | 0 | break; |
1901 | 0 | case CVT_imm_95_6: |
1902 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1903 | 0 | Operands[*(p + 1)]->setConstraint(""); |
1904 | 0 | ++NumMCOperands; |
1905 | 0 | break; |
1906 | 0 | case CVT_imm_95_4: |
1907 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1908 | 0 | Operands[*(p + 1)]->setConstraint(""); |
1909 | 0 | ++NumMCOperands; |
1910 | 0 | break; |
1911 | 0 | case CVT_imm_95_5: |
1912 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1913 | 0 | Operands[*(p + 1)]->setConstraint(""); |
1914 | 0 | ++NumMCOperands; |
1915 | 0 | break; |
1916 | 0 | case CVT_imm_95_31: |
1917 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
1918 | 0 | Operands[*(p + 1)]->setConstraint(""); |
1919 | 0 | ++NumMCOperands; |
1920 | 0 | break; |
1921 | 0 | } |
1922 | 0 | } |
1923 | 0 | } |
1924 | | |
1925 | | namespace { |
1926 | | |
1927 | | /// MatchClassKind - The kinds of classes which participate in |
1928 | | /// instruction matching. |
1929 | | enum MatchClassKind { |
1930 | | InvalidMatchClass = 0, |
1931 | | OptionalMatchClass = 1, |
1932 | | MCK__35_, // '#' |
1933 | | MCK__40_, // '(' |
1934 | | MCK__41_, // ')' |
1935 | | MCK_0, // '0' |
1936 | | MCK_16, // '16' |
1937 | | MCK__91_, // '[' |
1938 | | MCK__93_, // ']' |
1939 | | MCK_bit, // 'bit' |
1940 | | MCK_inst, // 'inst' |
1941 | | MCK_LAST_TOKEN = MCK_inst, |
1942 | | MCK_Reg37, // derived register class |
1943 | | MCK_Reg19, // derived register class |
1944 | | MCK_ACC128, // register class 'ACC128' |
1945 | | MCK_ACC64, // register class 'ACC64' |
1946 | | MCK_CPURAReg, // register class 'CPURAReg,RA' |
1947 | | MCK_CPUSPReg, // register class 'CPUSPReg,SP32,SP' |
1948 | | MCK_DSPCC, // register class 'DSPCC' |
1949 | | MCK_GP32, // register class 'GP32' |
1950 | | MCK_GP64, // register class 'GP64' |
1951 | | MCK_GPR32ZERO, // register class 'GPR32ZERO,ZERO' |
1952 | | MCK_HI32, // register class 'HI32' |
1953 | | MCK_HI64, // register class 'HI64' |
1954 | | MCK_LO32, // register class 'LO32' |
1955 | | MCK_LO64, // register class 'LO64' |
1956 | | MCK_PC, // register class 'PC' |
1957 | | MCK_SP64, // register class 'SP64' |
1958 | | MCK_Reg32, // derived register class |
1959 | | MCK_Reg13, // derived register class |
1960 | | MCK_Reg33, // derived register class |
1961 | | MCK_Reg31, // derived register class |
1962 | | MCK_Reg30, // derived register class |
1963 | | MCK_Reg14, // derived register class |
1964 | | MCK_Reg11, // derived register class |
1965 | | MCK_GPRMM16MovePPairFirst, // register class 'GPRMM16MovePPairFirst' |
1966 | | MCK_OCTEON_MPL, // register class 'OCTEON_MPL' |
1967 | | MCK_OCTEON_P, // register class 'OCTEON_P' |
1968 | | MCK_Reg28, // derived register class |
1969 | | MCK_Reg23, // derived register class |
1970 | | MCK_Reg9, // derived register class |
1971 | | MCK_Reg4, // derived register class |
1972 | | MCK_ACC64DSP, // register class 'ACC64DSP' |
1973 | | MCK_HI32DSP, // register class 'HI32DSP' |
1974 | | MCK_LO32DSP, // register class 'LO32DSP' |
1975 | | MCK_Reg34, // derived register class |
1976 | | MCK_GPRMM16MovePPairSecond, // register class 'GPRMM16MovePPairSecond' |
1977 | | MCK_Reg29, // derived register class |
1978 | | MCK_Reg27, // derived register class |
1979 | | MCK_Reg10, // derived register class |
1980 | | MCK_Reg8, // derived register class |
1981 | | MCK_Reg25, // derived register class |
1982 | | MCK_Reg22, // derived register class |
1983 | | MCK_Reg21, // derived register class |
1984 | | MCK_CPU16Regs, // register class 'CPU16Regs,GPRMM16' |
1985 | | MCK_FCC, // register class 'FCC' |
1986 | | MCK_GPRMM16MoveP, // register class 'GPRMM16MoveP' |
1987 | | MCK_GPRMM16Zero, // register class 'GPRMM16Zero' |
1988 | | MCK_Reg26, // derived register class |
1989 | | MCK_CPU16RegsPlusSP, // register class 'CPU16RegsPlusSP' |
1990 | | MCK_AFGR64, // register class 'AFGR64' |
1991 | | MCK_MSA128WEvens, // register class 'MSA128WEvens' |
1992 | | MCK_Reg24, // derived register class |
1993 | | MCK_GPR32NONZERO, // register class 'GPR32NONZERO' |
1994 | | MCK_CCR, // register class 'CCR' |
1995 | | MCK_COP0, // register class 'COP0' |
1996 | | MCK_COP2, // register class 'COP2' |
1997 | | MCK_COP3, // register class 'COP3' |
1998 | | MCK_DSPR, // register class 'DSPR,GPR32' |
1999 | | MCK_FGR32, // register class 'FGR32,FGRCC' |
2000 | | MCK_FGR64, // register class 'FGR64' |
2001 | | MCK_GPR64, // register class 'GPR64' |
2002 | | MCK_HWRegs, // register class 'HWRegs' |
2003 | | MCK_MSA128F16, // register class 'MSA128F16,MSA128B,MSA128D,MSA128H,MSA128W' |
2004 | | MCK_MSACtrl, // register class 'MSACtrl' |
2005 | | MCK_LAST_REGISTER = MCK_MSACtrl, |
2006 | | MCK_ACC64DSPAsmReg, // user defined class 'ACC64DSPAsmOperand' |
2007 | | MCK_AFGR64AsmReg, // user defined class 'AFGR64AsmOperand' |
2008 | | MCK_CCRAsmReg, // user defined class 'CCRAsmOperand' |
2009 | | MCK_COP0AsmReg, // user defined class 'COP0AsmOperand' |
2010 | | MCK_COP2AsmReg, // user defined class 'COP2AsmOperand' |
2011 | | MCK_COP3AsmReg, // user defined class 'COP3AsmOperand' |
2012 | | MCK_FCCAsmReg, // user defined class 'FCCRegsAsmOperand' |
2013 | | MCK_FGR32AsmReg, // user defined class 'FGR32AsmOperand' |
2014 | | MCK_FGR64AsmReg, // user defined class 'FGR64AsmOperand' |
2015 | | MCK_GPR32AsmReg, // user defined class 'GPR32AsmOperand' |
2016 | | MCK_GPR32NonZeroAsmReg, // user defined class 'GPR32NonZeroAsmOperand' |
2017 | | MCK_GPR32ZeroAsmReg, // user defined class 'GPR32ZeroAsmOperand' |
2018 | | MCK_GPR64AsmReg, // user defined class 'GPR64AsmOperand' |
2019 | | MCK_GPRMM16AsmReg, // user defined class 'GPRMM16AsmOperand' |
2020 | | MCK_GPRMM16AsmRegMoveP, // user defined class 'GPRMM16AsmOperandMoveP' |
2021 | | MCK_GPRMM16AsmRegMovePPairFirst, // user defined class 'GPRMM16AsmOperandMovePPairFirst' |
2022 | | MCK_GPRMM16AsmRegMovePPairSecond, // user defined class 'GPRMM16AsmOperandMovePPairSecond' |
2023 | | MCK_GPRMM16AsmRegZero, // user defined class 'GPRMM16AsmOperandZero' |
2024 | | MCK_HI32DSPAsmReg, // user defined class 'HI32DSPAsmOperand' |
2025 | | MCK_HWRegsAsmReg, // user defined class 'HWRegsAsmOperand' |
2026 | | MCK_Imm, // user defined class 'ImmAsmOperand' |
2027 | | MCK_LO32DSPAsmReg, // user defined class 'LO32DSPAsmOperand' |
2028 | | MCK_MSA128AsmReg, // user defined class 'MSA128AsmOperand' |
2029 | | MCK_MSACtrlAsmReg, // user defined class 'MSACtrlAsmOperand' |
2030 | | MCK_MicroMipsMemGP, // user defined class 'MicroMipsMemGPAsmOperand' |
2031 | | MCK_MicroMipsMem, // user defined class 'MicroMipsMemGPRMM16AsmOperand' |
2032 | | MCK_MicroMipsMemSP, // user defined class 'MicroMipsMemSPAsmOperand' |
2033 | | MCK_InvNum, // user defined class 'MipsInvertedImmoperand' |
2034 | | MCK_JumpTarget, // user defined class 'MipsJumpTargetAsmOperand' |
2035 | | MCK_MemOffsetSimm10, // user defined class 'MipsMemSimm10AsmOperand' |
2036 | | MCK_MemOffsetSimm10_1, // user defined class 'MipsMemSimm10Lsl1AsmOperand' |
2037 | | MCK_MemOffsetSimm10_2, // user defined class 'MipsMemSimm10Lsl2AsmOperand' |
2038 | | MCK_MemOffsetSimm10_3, // user defined class 'MipsMemSimm10Lsl3AsmOperand' |
2039 | | MCK_MemOffsetSimm11, // user defined class 'MipsMemSimm11AsmOperand' |
2040 | | MCK_MemOffsetSimm12, // user defined class 'MipsMemSimm12AsmOperand' |
2041 | | MCK_MemOffsetSimm16, // user defined class 'MipsMemSimm16AsmOperand' |
2042 | | MCK_MemOffsetSimm9, // user defined class 'MipsMemSimm9AsmOperand' |
2043 | | MCK_MemOffsetSimmPtr, // user defined class 'MipsMemSimmPtrAsmOperand' |
2044 | | MCK_MemOffsetUimm4, // user defined class 'MipsMemUimm4AsmOperand' |
2045 | | MCK_Mem, // user defined class 'MipsMemAsmOperand' |
2046 | | MCK_RegList16, // user defined class 'RegList16AsmOperand' |
2047 | | MCK_RegList, // user defined class 'RegListAsmOperand' |
2048 | | MCK_Simm19_Lsl2, // user defined class 'Simm19Lsl2AsmOperand' |
2049 | | MCK_StrictlyAFGR64AsmReg, // user defined class 'StrictlyAFGR64AsmOperand' |
2050 | | MCK_StrictlyFGR32AsmReg, // user defined class 'StrictlyFGR32AsmOperand' |
2051 | | MCK_StrictlyFGR64AsmReg, // user defined class 'StrictlyFGR64AsmOperand' |
2052 | | MCK_ConstantImmz, // user defined class 'ConstantImmzAsmOperandClass' |
2053 | | MCK_ConstantUImm1_0, // user defined class 'ConstantUImm1AsmOperandClass' |
2054 | | MCK_ConstantUImm2_0, // user defined class 'ConstantUImm2AsmOperandClass' |
2055 | | MCK_ConstantUImm2_1, // user defined class 'ConstantUImm2Plus1AsmOperandClass' |
2056 | | MCK_ConstantUImm3_0, // user defined class 'ConstantUImm3AsmOperandClass' |
2057 | | MCK_ConstantSImm4_0, // user defined class 'ConstantSImm4AsmOperandClass' |
2058 | | MCK_ConstantUImm4_0, // user defined class 'ConstantUImm4AsmOperandClass' |
2059 | | MCK_ConstantSImm5_0, // user defined class 'ConstantSImm5AsmOperandClass' |
2060 | | MCK_ConstantUImm5_0, // user defined class 'ConstantUImm5AsmOperandClass' |
2061 | | MCK_ConstantUImm5_1, // user defined class 'ConstantUImm5Plus1AsmOperandClass' |
2062 | | MCK_ConstantUImm5_Plus1_Report_UImm6, // user defined class 'ConstantUImm5Plus1ReportUImm6AsmOperandClass' |
2063 | | MCK_ConstantUImm5_32_Norm, // user defined class 'ConstantUImm5Plus32NormalizeAsmOperandClass' |
2064 | | MCK_ConstantUImm5_32, // user defined class 'ConstantUImm5Plus32AsmOperandClass' |
2065 | | MCK_ConstantUImm5_0_Report_UImm6, // user defined class 'ConstantUImm5ReportUImm6AsmOperandClass' |
2066 | | MCK_ConstantUImm5_33, // user defined class 'ConstantUImm5Plus33AsmOperandClass' |
2067 | | MCK_ConstantUImmRange2_64, // user defined class 'ConstantUImm5_Range2_64AsmOperandClass' |
2068 | | MCK_UImm5Lsl2, // user defined class 'ConstantUImm5Lsl2AsmOperandClass' |
2069 | | MCK_ConstantSImm6_0, // user defined class 'ConstantSImm6AsmOperandClass' |
2070 | | MCK_ConstantUImm6_0, // user defined class 'ConstantUImm6AsmOperandClass' |
2071 | | MCK_UImm6Lsl2, // user defined class 'ConstantUImm6Lsl2AsmOperandClass' |
2072 | | MCK_ConstantUImm7_0, // user defined class 'ConstantUImm7AsmOperandClass' |
2073 | | MCK_UImm7_N1, // user defined class 'ConstantUImm7Sub1AsmOperandClass' |
2074 | | MCK_ConstantUImm8_0, // user defined class 'ConstantUImm8AsmOperandClass' |
2075 | | MCK_SImm7Lsl2, // user defined class 'ConstantSImm7Lsl2AsmOperandClass' |
2076 | | MCK_ConstantSImm9_0, // user defined class 'ConstantSImm9AsmOperandClass' |
2077 | | MCK_ConstantSImm10_0, // user defined class 'ConstantSImm10AsmOperandClass' |
2078 | | MCK_ConstantUImm10_0, // user defined class 'ConstantUImm10AsmOperandClass' |
2079 | | MCK_SImm10Lsl1, // user defined class 'ConstantSImm10Lsl1AsmOperandClass' |
2080 | | MCK_ConstantSImm11_0, // user defined class 'ConstantSImm11AsmOperandClass' |
2081 | | MCK_SImm10Lsl2, // user defined class 'ConstantSImm10Lsl2AsmOperandClass' |
2082 | | MCK_SImm10Lsl3, // user defined class 'ConstantSImm10Lsl3AsmOperandClass' |
2083 | | MCK_SImm16, // user defined class 'SImm16AsmOperandClass' |
2084 | | MCK_SImm16_Relaxed, // user defined class 'SImm16RelaxedAsmOperandClass' |
2085 | | MCK_UImm16_AltRelaxed, // user defined class 'UImm16AltRelaxedAsmOperandClass' |
2086 | | MCK_UImm16, // user defined class 'UImm16AsmOperandClass' |
2087 | | MCK_SImm19Lsl2, // user defined class 'ConstantSImm19Lsl2AsmOperandClass' |
2088 | | MCK_UImm16_Relaxed, // user defined class 'UImm16RelaxedAsmOperandClass' |
2089 | | MCK_ConstantUImm20_0, // user defined class 'ConstantUImm20AsmOperandClass' |
2090 | | MCK_ConstantUImm26_0, // user defined class 'ConstantUImm26AsmOperandClass' |
2091 | | MCK_SImm32, // user defined class 'SImm32AsmOperandClass' |
2092 | | MCK_SImm32_Relaxed, // user defined class 'SImm32RelaxedAsmOperandClass' |
2093 | | MCK_UImm32_Coerced, // user defined class 'UImm32CoercedAsmOperandClass' |
2094 | | NumMatchClassKinds |
2095 | | }; |
2096 | | |
2097 | | } |
2098 | | |
2099 | 14.4k | static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) { |
2100 | 14.4k | return MCTargetAsmParser::Match_InvalidOperand; |
2101 | 14.4k | } |
2102 | | |
2103 | 880 | static MatchClassKind matchTokenString(StringRef Name) { |
2104 | 880 | switch (Name.size()) { |
2105 | 880 | default: break0 ; |
2106 | 880 | case 1: // 6 strings to match. |
2107 | 880 | switch (Name[0]) { |
2108 | 880 | default: break0 ; |
2109 | 880 | case '#': // 1 string to match. |
2110 | 0 | return MCK__35_; // "#" |
2111 | 880 | case '(': // 1 string to match. |
2112 | 363 | return MCK__40_; // "(" |
2113 | 880 | case ')': // 1 string to match. |
2114 | 363 | return MCK__41_; // ")" |
2115 | 880 | case '0': // 1 string to match. |
2116 | 0 | return MCK_0; // "0" |
2117 | 880 | case '[': // 1 string to match. |
2118 | 112 | return MCK__91_; // "[" |
2119 | 880 | case ']': // 1 string to match. |
2120 | 42 | return MCK__93_; // "]" |
2121 | 0 | } |
2122 | 0 | break; |
2123 | 0 | case 2: // 1 string to match. |
2124 | 0 | if (memcmp(Name.data()+0, "16", 2) != 0) |
2125 | 0 | break; |
2126 | 0 | return MCK_16; // "16" |
2127 | 0 | case 3: // 1 string to match. |
2128 | 0 | if (memcmp(Name.data()+0, "bit", 3) != 0) |
2129 | 0 | break; |
2130 | 0 | return MCK_bit; // "bit" |
2131 | 0 | case 4: // 1 string to match. |
2132 | 0 | if (memcmp(Name.data()+0, "inst", 4) != 0) |
2133 | 0 | break; |
2134 | 0 | return MCK_inst; // "inst" |
2135 | 0 | } |
2136 | 0 | return InvalidMatchClass; |
2137 | 0 | } |
2138 | | |
2139 | | /// isSubclass - Compute whether \p A is a subclass of \p B. |
2140 | 39.8k | static bool isSubclass(MatchClassKind A, MatchClassKind B) { |
2141 | 39.8k | if (A == B) |
2142 | 1.00k | return true; |
2143 | 38.8k | |
2144 | 38.8k | switch (A) { |
2145 | 38.8k | default: |
2146 | 24.4k | return false; |
2147 | 38.8k | |
2148 | 38.8k | case MCK_Reg37: |
2149 | 0 | switch (B) { |
2150 | 0 | default: return false; |
2151 | 0 | case MCK_Reg24: return true; |
2152 | 0 | case MCK_GPR64: return true; |
2153 | 0 | } |
2154 | 0 | |
2155 | 0 | case MCK_Reg19: |
2156 | 0 | switch (B) { |
2157 | 0 | default: return false; |
2158 | 0 | case MCK_Reg23: return true; |
2159 | 0 | case MCK_Reg22: return true; |
2160 | 0 | case MCK_Reg21: return true; |
2161 | 0 | case MCK_GPR64: return true; |
2162 | 0 | } |
2163 | 0 | |
2164 | 0 | case MCK_ACC64: |
2165 | 0 | return B == MCK_ACC64DSP; |
2166 | 0 |
|
2167 | 133 | case MCK_CPURAReg: |
2168 | 133 | switch (B) { |
2169 | 133 | default: return false; |
2170 | 133 | case MCK_GPR32NONZERO: return true0 ; |
2171 | 133 | case MCK_DSPR: return true0 ; |
2172 | 0 | } |
2173 | 0 | |
2174 | 551 | case MCK_CPUSPReg: |
2175 | 551 | switch (B) { |
2176 | 551 | default: return false; |
2177 | 551 | case MCK_CPU16RegsPlusSP: return true0 ; |
2178 | 551 | case MCK_GPR32NONZERO: return true0 ; |
2179 | 551 | case MCK_DSPR: return true0 ; |
2180 | 0 | } |
2181 | 0 | |
2182 | 0 | case MCK_GP32: |
2183 | 0 | switch (B) { |
2184 | 0 | default: return false; |
2185 | 0 | case MCK_GPR32NONZERO: return true; |
2186 | 0 | case MCK_DSPR: return true; |
2187 | 0 | } |
2188 | 0 | |
2189 | 0 | case MCK_GP64: |
2190 | 0 | switch (B) { |
2191 | 0 | default: return false; |
2192 | 0 | case MCK_Reg24: return true; |
2193 | 0 | case MCK_GPR64: return true; |
2194 | 0 | } |
2195 | 0 | |
2196 | 351 | case MCK_GPR32ZERO: |
2197 | 351 | switch (B) { |
2198 | 351 | default: return false; |
2199 | 351 | case MCK_Reg4: return true0 ; |
2200 | 351 | case MCK_GPRMM16MoveP: return true0 ; |
2201 | 351 | case MCK_GPRMM16Zero: return true0 ; |
2202 | 351 | case MCK_DSPR: return true0 ; |
2203 | 0 | } |
2204 | 0 | |
2205 | 0 | case MCK_HI32: |
2206 | 0 | return B == MCK_HI32DSP; |
2207 | 0 |
|
2208 | 0 | case MCK_LO32: |
2209 | 0 | return B == MCK_LO32DSP; |
2210 | 0 |
|
2211 | 0 | case MCK_SP64: |
2212 | 0 | switch (B) { |
2213 | 0 | default: return false; |
2214 | 0 | case MCK_Reg26: return true; |
2215 | 0 | case MCK_Reg24: return true; |
2216 | 0 | case MCK_GPR64: return true; |
2217 | 0 | } |
2218 | 0 | |
2219 | 0 | case MCK_Reg32: |
2220 | 0 | switch (B) { |
2221 | 0 | default: return false; |
2222 | 0 | case MCK_Reg33: return true; |
2223 | 0 | case MCK_Reg31: return true; |
2224 | 0 | case MCK_Reg34: return true; |
2225 | 0 | case MCK_Reg27: return true; |
2226 | 0 | case MCK_Reg25: return true; |
2227 | 0 | case MCK_Reg21: return true; |
2228 | 0 | case MCK_Reg26: return true; |
2229 | 0 | case MCK_Reg24: return true; |
2230 | 0 | case MCK_GPR64: return true; |
2231 | 0 | } |
2232 | 0 | |
2233 | 0 | case MCK_Reg13: |
2234 | 0 | switch (B) { |
2235 | 0 | default: return false; |
2236 | 0 | case MCK_Reg14: return true; |
2237 | 0 | case MCK_GPRMM16MovePPairFirst: return true; |
2238 | 0 | case MCK_GPRMM16MovePPairSecond: return true; |
2239 | 0 | case MCK_Reg8: return true; |
2240 | 0 | case MCK_CPU16Regs: return true; |
2241 | 0 | case MCK_GPRMM16Zero: return true; |
2242 | 0 | case MCK_CPU16RegsPlusSP: return true; |
2243 | 0 | case MCK_GPR32NONZERO: return true; |
2244 | 0 | case MCK_DSPR: return true; |
2245 | 0 | } |
2246 | 0 | |
2247 | 0 | case MCK_Reg33: |
2248 | 0 | switch (B) { |
2249 | 0 | default: return false; |
2250 | 0 | case MCK_Reg34: return true; |
2251 | 0 | case MCK_Reg27: return true; |
2252 | 0 | case MCK_Reg25: return true; |
2253 | 0 | case MCK_Reg21: return true; |
2254 | 0 | case MCK_Reg26: return true; |
2255 | 0 | case MCK_Reg24: return true; |
2256 | 0 | case MCK_GPR64: return true; |
2257 | 0 | } |
2258 | 0 | |
2259 | 0 | case MCK_Reg31: |
2260 | 0 | switch (B) { |
2261 | 0 | default: return false; |
2262 | 0 | case MCK_Reg27: return true; |
2263 | 0 | case MCK_Reg25: return true; |
2264 | 0 | case MCK_Reg21: return true; |
2265 | 0 | case MCK_Reg26: return true; |
2266 | 0 | case MCK_Reg24: return true; |
2267 | 0 | case MCK_GPR64: return true; |
2268 | 0 | } |
2269 | 0 | |
2270 | 0 | case MCK_Reg30: |
2271 | 0 | switch (B) { |
2272 | 0 | default: return false; |
2273 | 0 | case MCK_Reg28: return true; |
2274 | 0 | case MCK_Reg23: return true; |
2275 | 0 | case MCK_Reg29: return true; |
2276 | 0 | case MCK_Reg27: return true; |
2277 | 0 | case MCK_Reg25: return true; |
2278 | 0 | case MCK_Reg22: return true; |
2279 | 0 | case MCK_Reg21: return true; |
2280 | 0 | case MCK_Reg26: return true; |
2281 | 0 | case MCK_Reg24: return true; |
2282 | 0 | case MCK_GPR64: return true; |
2283 | 0 | } |
2284 | 0 | |
2285 | 0 | case MCK_Reg14: |
2286 | 0 | switch (B) { |
2287 | 0 | default: return false; |
2288 | 0 | case MCK_GPRMM16MovePPairSecond: return true; |
2289 | 0 | case MCK_Reg8: return true; |
2290 | 0 | case MCK_CPU16Regs: return true; |
2291 | 0 | case MCK_GPRMM16Zero: return true; |
2292 | 0 | case MCK_CPU16RegsPlusSP: return true; |
2293 | 0 | case MCK_GPR32NONZERO: return true; |
2294 | 0 | case MCK_DSPR: return true; |
2295 | 0 | } |
2296 | 0 | |
2297 | 0 | case MCK_Reg11: |
2298 | 0 | switch (B) { |
2299 | 0 | default: return false; |
2300 | 0 | case MCK_Reg9: return true; |
2301 | 0 | case MCK_Reg4: return true; |
2302 | 0 | case MCK_Reg10: return true; |
2303 | 0 | case MCK_Reg8: return true; |
2304 | 0 | case MCK_CPU16Regs: return true; |
2305 | 0 | case MCK_GPRMM16MoveP: return true; |
2306 | 0 | case MCK_GPRMM16Zero: return true; |
2307 | 0 | case MCK_CPU16RegsPlusSP: return true; |
2308 | 0 | case MCK_GPR32NONZERO: return true; |
2309 | 0 | case MCK_DSPR: return true; |
2310 | 0 | } |
2311 | 0 | |
2312 | 0 | case MCK_GPRMM16MovePPairFirst: |
2313 | 0 | switch (B) { |
2314 | 0 | default: return false; |
2315 | 0 | case MCK_Reg8: return true; |
2316 | 0 | case MCK_CPU16Regs: return true; |
2317 | 0 | case MCK_GPRMM16Zero: return true; |
2318 | 0 | case MCK_CPU16RegsPlusSP: return true; |
2319 | 0 | case MCK_GPR32NONZERO: return true; |
2320 | 0 | case MCK_DSPR: return true; |
2321 | 0 | } |
2322 | 0 | |
2323 | 0 | case MCK_Reg28: |
2324 | 0 | switch (B) { |
2325 | 0 | default: return false; |
2326 | 0 | case MCK_Reg29: return true; |
2327 | 0 | case MCK_Reg25: return true; |
2328 | 0 | case MCK_Reg22: return true; |
2329 | 0 | case MCK_Reg26: return true; |
2330 | 0 | case MCK_Reg24: return true; |
2331 | 0 | case MCK_GPR64: return true; |
2332 | 0 | } |
2333 | 0 | |
2334 | 0 | case MCK_Reg23: |
2335 | 0 | switch (B) { |
2336 | 0 | default: return false; |
2337 | 0 | case MCK_Reg22: return true; |
2338 | 0 | case MCK_Reg21: return true; |
2339 | 0 | case MCK_GPR64: return true; |
2340 | 0 | } |
2341 | 0 | |
2342 | 0 | case MCK_Reg9: |
2343 | 0 | switch (B) { |
2344 | 0 | default: return false; |
2345 | 0 | case MCK_Reg10: return true; |
2346 | 0 | case MCK_CPU16Regs: return true; |
2347 | 0 | case MCK_GPRMM16MoveP: return true; |
2348 | 0 | case MCK_CPU16RegsPlusSP: return true; |
2349 | 0 | case MCK_GPR32NONZERO: return true; |
2350 | 0 | case MCK_DSPR: return true; |
2351 | 0 | } |
2352 | 0 | |
2353 | 0 | case MCK_Reg4: |
2354 | 0 | switch (B) { |
2355 | 0 | default: return false; |
2356 | 0 | case MCK_GPRMM16MoveP: return true; |
2357 | 0 | case MCK_GPRMM16Zero: return true; |
2358 | 0 | case MCK_DSPR: return true; |
2359 | 0 | } |
2360 | 0 | |
2361 | 0 | case MCK_Reg34: |
2362 | 0 | switch (B) { |
2363 | 0 | default: return false; |
2364 | 0 | case MCK_Reg24: return true; |
2365 | 0 | case MCK_GPR64: return true; |
2366 | 0 | } |
2367 | 0 | |
2368 | 0 | case MCK_GPRMM16MovePPairSecond: |
2369 | 0 | switch (B) { |
2370 | 0 | default: return false; |
2371 | 0 | case MCK_GPR32NONZERO: return true; |
2372 | 0 | case MCK_DSPR: return true; |
2373 | 0 | } |
2374 | 0 | |
2375 | 0 | case MCK_Reg29: |
2376 | 0 | switch (B) { |
2377 | 0 | default: return false; |
2378 | 0 | case MCK_Reg22: return true; |
2379 | 0 | case MCK_Reg24: return true; |
2380 | 0 | case MCK_GPR64: return true; |
2381 | 0 | } |
2382 | 0 | |
2383 | 0 | case MCK_Reg27: |
2384 | 0 | switch (B) { |
2385 | 0 | default: return false; |
2386 | 0 | case MCK_Reg25: return true; |
2387 | 0 | case MCK_Reg21: return true; |
2388 | 0 | case MCK_Reg26: return true; |
2389 | 0 | case MCK_Reg24: return true; |
2390 | 0 | case MCK_GPR64: return true; |
2391 | 0 | } |
2392 | 0 | |
2393 | 0 | case MCK_Reg10: |
2394 | 0 | switch (B) { |
2395 | 0 | default: return false; |
2396 | 0 | case MCK_GPRMM16MoveP: return true; |
2397 | 0 | case MCK_GPR32NONZERO: return true; |
2398 | 0 | case MCK_DSPR: return true; |
2399 | 0 | } |
2400 | 0 | |
2401 | 0 | case MCK_Reg8: |
2402 | 0 | switch (B) { |
2403 | 0 | default: return false; |
2404 | 0 | case MCK_CPU16Regs: return true; |
2405 | 0 | case MCK_GPRMM16Zero: return true; |
2406 | 0 | case MCK_CPU16RegsPlusSP: return true; |
2407 | 0 | case MCK_GPR32NONZERO: return true; |
2408 | 0 | case MCK_DSPR: return true; |
2409 | 0 | } |
2410 | 0 | |
2411 | 0 | case MCK_Reg25: |
2412 | 0 | switch (B) { |
2413 | 0 | default: return false; |
2414 | 0 | case MCK_Reg26: return true; |
2415 | 0 | case MCK_Reg24: return true; |
2416 | 0 | case MCK_GPR64: return true; |
2417 | 0 | } |
2418 | 0 | |
2419 | 0 | case MCK_Reg22: |
2420 | 0 | return B == MCK_GPR64; |
2421 | 0 |
|
2422 | 0 | case MCK_Reg21: |
2423 | 0 | return B == MCK_GPR64; |
2424 | 0 |
|
2425 | 13.3k | case MCK_CPU16Regs: |
2426 | 13.3k | switch (B) { |
2427 | 13.3k | default: return false; |
2428 | 13.3k | case MCK_CPU16RegsPlusSP: return true0 ; |
2429 | 13.3k | case MCK_GPR32NONZERO: return true0 ; |
2430 | 13.3k | case MCK_DSPR: return true0 ; |
2431 | 0 | } |
2432 | 0 | |
2433 | 0 | case MCK_GPRMM16MoveP: |
2434 | 0 | return B == MCK_DSPR; |
2435 | 0 |
|
2436 | 0 | case MCK_GPRMM16Zero: |
2437 | 0 | return B == MCK_DSPR; |
2438 | 0 |
|
2439 | 0 | case MCK_Reg26: |
2440 | 0 | switch (B) { |
2441 | 0 | default: return false; |
2442 | 0 | case MCK_Reg24: return true; |
2443 | 0 | case MCK_GPR64: return true; |
2444 | 0 | } |
2445 | 0 | |
2446 | 0 | case MCK_CPU16RegsPlusSP: |
2447 | 0 | switch (B) { |
2448 | 0 | default: return false; |
2449 | 0 | case MCK_GPR32NONZERO: return true; |
2450 | 0 | case MCK_DSPR: return true; |
2451 | 0 | } |
2452 | 0 | |
2453 | 0 | case MCK_MSA128WEvens: |
2454 | 0 | return B == MCK_MSA128F16; |
2455 | 0 |
|
2456 | 0 | case MCK_Reg24: |
2457 | 0 | return B == MCK_GPR64; |
2458 | 0 |
|
2459 | 0 | case MCK_GPR32NONZERO: |
2460 | 0 | return B == MCK_DSPR; |
2461 | 0 |
|
2462 | 0 | case MCK_MemOffsetSimm10: |
2463 | 0 | return B == MCK_Mem; |
2464 | 0 |
|
2465 | 0 | case MCK_MemOffsetSimm10_1: |
2466 | 0 | return B == MCK_Mem; |
2467 | 0 |
|
2468 | 0 | case MCK_MemOffsetSimm10_2: |
2469 | 0 | return B == MCK_Mem; |
2470 | 0 |
|
2471 | 0 | case MCK_MemOffsetSimm10_3: |
2472 | 0 | return B == MCK_Mem; |
2473 | 0 |
|
2474 | 0 | case MCK_MemOffsetSimm11: |
2475 | 0 | return B == MCK_Mem; |
2476 | 0 |
|
2477 | 0 | case MCK_MemOffsetSimm12: |
2478 | 0 | return B == MCK_Mem; |
2479 | 0 |
|
2480 | 0 | case MCK_MemOffsetSimm16: |
2481 | 0 | return B == MCK_Mem; |
2482 | 0 |
|
2483 | 0 | case MCK_MemOffsetSimm9: |
2484 | 0 | return B == MCK_Mem; |
2485 | 0 |
|
2486 | 0 | case MCK_MemOffsetSimmPtr: |
2487 | 0 | return B == MCK_Mem; |
2488 | 0 |
|
2489 | 8 | case MCK_MemOffsetUimm4: |
2490 | 8 | return B == MCK_Mem; |
2491 | 0 |
|
2492 | 0 | case MCK_ConstantImmz: |
2493 | 0 | switch (B) { |
2494 | 0 | default: return false; |
2495 | 0 | case MCK_ConstantUImm1_0: return true; |
2496 | 0 | case MCK_ConstantUImm2_0: return true; |
2497 | 0 | case MCK_ConstantUImm3_0: return true; |
2498 | 0 | case MCK_ConstantSImm4_0: return true; |
2499 | 0 | case MCK_ConstantUImm4_0: return true; |
2500 | 0 | case MCK_ConstantSImm5_0: return true; |
2501 | 0 | case MCK_ConstantUImm5_0: return true; |
2502 | 0 | case MCK_ConstantUImm5_1: return true; |
2503 | 0 | case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; |
2504 | 0 | case MCK_ConstantUImm5_32_Norm: return true; |
2505 | 0 | case MCK_ConstantUImm5_32: return true; |
2506 | 0 | case MCK_ConstantUImm5_0_Report_UImm6: return true; |
2507 | 0 | case MCK_ConstantUImm5_33: return true; |
2508 | 0 | case MCK_ConstantUImmRange2_64: return true; |
2509 | 0 | case MCK_UImm5Lsl2: return true; |
2510 | 0 | case MCK_ConstantSImm6_0: return true; |
2511 | 0 | case MCK_ConstantUImm6_0: return true; |
2512 | 0 | case MCK_UImm6Lsl2: return true; |
2513 | 0 | case MCK_ConstantUImm7_0: return true; |
2514 | 0 | case MCK_UImm7_N1: return true; |
2515 | 0 | case MCK_ConstantUImm8_0: return true; |
2516 | 0 | case MCK_SImm7Lsl2: return true; |
2517 | 0 | case MCK_ConstantSImm9_0: return true; |
2518 | 0 | case MCK_ConstantSImm10_0: return true; |
2519 | 0 | case MCK_ConstantUImm10_0: return true; |
2520 | 0 | case MCK_SImm10Lsl1: return true; |
2521 | 0 | case MCK_ConstantSImm11_0: return true; |
2522 | 0 | case MCK_SImm10Lsl2: return true; |
2523 | 0 | case MCK_SImm10Lsl3: return true; |
2524 | 0 | case MCK_SImm16: return true; |
2525 | 0 | case MCK_SImm16_Relaxed: return true; |
2526 | 0 | case MCK_UImm16_Relaxed: return true; |
2527 | 0 | case MCK_ConstantUImm20_0: return true; |
2528 | 0 | case MCK_ConstantUImm26_0: return true; |
2529 | 0 | case MCK_SImm32: return true; |
2530 | 0 | case MCK_SImm32_Relaxed: return true; |
2531 | 0 | case MCK_UImm32_Coerced: return true; |
2532 | 0 | } |
2533 | 0 | |
2534 | 0 | case MCK_ConstantUImm1_0: |
2535 | 0 | switch (B) { |
2536 | 0 | default: return false; |
2537 | 0 | case MCK_ConstantUImm2_0: return true; |
2538 | 0 | case MCK_ConstantUImm3_0: return true; |
2539 | 0 | case MCK_ConstantSImm4_0: return true; |
2540 | 0 | case MCK_ConstantUImm4_0: return true; |
2541 | 0 | case MCK_ConstantSImm5_0: return true; |
2542 | 0 | case MCK_ConstantUImm5_0: return true; |
2543 | 0 | case MCK_ConstantUImm5_1: return true; |
2544 | 0 | case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; |
2545 | 0 | case MCK_ConstantUImm5_32_Norm: return true; |
2546 | 0 | case MCK_ConstantUImm5_32: return true; |
2547 | 0 | case MCK_ConstantUImm5_0_Report_UImm6: return true; |
2548 | 0 | case MCK_ConstantUImm5_33: return true; |
2549 | 0 | case MCK_ConstantUImmRange2_64: return true; |
2550 | 0 | case MCK_UImm5Lsl2: return true; |
2551 | 0 | case MCK_ConstantSImm6_0: return true; |
2552 | 0 | case MCK_ConstantUImm6_0: return true; |
2553 | 0 | case MCK_UImm6Lsl2: return true; |
2554 | 0 | case MCK_ConstantUImm7_0: return true; |
2555 | 0 | case MCK_UImm7_N1: return true; |
2556 | 0 | case MCK_ConstantUImm8_0: return true; |
2557 | 0 | case MCK_SImm7Lsl2: return true; |
2558 | 0 | case MCK_ConstantSImm9_0: return true; |
2559 | 0 | case MCK_ConstantSImm10_0: return true; |
2560 | 0 | case MCK_ConstantUImm10_0: return true; |
2561 | 0 | case MCK_SImm10Lsl1: return true; |
2562 | 0 | case MCK_ConstantSImm11_0: return true; |
2563 | 0 | case MCK_SImm10Lsl2: return true; |
2564 | 0 | case MCK_SImm10Lsl3: return true; |
2565 | 0 | case MCK_SImm16: return true; |
2566 | 0 | case MCK_SImm16_Relaxed: return true; |
2567 | 0 | case MCK_UImm16_Relaxed: return true; |
2568 | 0 | case MCK_ConstantUImm20_0: return true; |
2569 | 0 | case MCK_ConstantUImm26_0: return true; |
2570 | 0 | case MCK_SImm32: return true; |
2571 | 0 | case MCK_SImm32_Relaxed: return true; |
2572 | 0 | case MCK_UImm32_Coerced: return true; |
2573 | 0 | } |
2574 | 0 | |
2575 | 6 | case MCK_ConstantUImm2_0: |
2576 | 6 | switch (B) { |
2577 | 6 | default: return false; |
2578 | 6 | case MCK_ConstantUImm3_0: return true0 ; |
2579 | 6 | case MCK_ConstantSImm4_0: return true0 ; |
2580 | 6 | case MCK_ConstantUImm4_0: return true0 ; |
2581 | 6 | case MCK_ConstantSImm5_0: return true0 ; |
2582 | 6 | case MCK_ConstantUImm5_0: return true0 ; |
2583 | 6 | case MCK_ConstantUImm5_1: return true0 ; |
2584 | 6 | case MCK_ConstantUImm5_Plus1_Report_UImm6: return true0 ; |
2585 | 6 | case MCK_ConstantUImm5_32_Norm: return true0 ; |
2586 | 6 | case MCK_ConstantUImm5_32: return true0 ; |
2587 | 6 | case MCK_ConstantUImm5_0_Report_UImm6: return true0 ; |
2588 | 6 | case MCK_ConstantUImm5_33: return true0 ; |
2589 | 6 | case MCK_ConstantUImmRange2_64: return true0 ; |
2590 | 6 | case MCK_UImm5Lsl2: return true0 ; |
2591 | 6 | case MCK_ConstantSImm6_0: return true0 ; |
2592 | 6 | case MCK_ConstantUImm6_0: return true0 ; |
2593 | 6 | case MCK_UImm6Lsl2: return true0 ; |
2594 | 6 | case MCK_ConstantUImm7_0: return true0 ; |
2595 | 6 | case MCK_UImm7_N1: return true0 ; |
2596 | 6 | case MCK_ConstantUImm8_0: return true0 ; |
2597 | 6 | case MCK_SImm7Lsl2: return true0 ; |
2598 | 6 | case MCK_ConstantSImm9_0: return true0 ; |
2599 | 6 | case MCK_ConstantSImm10_0: return true0 ; |
2600 | 6 | case MCK_ConstantUImm10_0: return true0 ; |
2601 | 6 | case MCK_SImm10Lsl1: return true0 ; |
2602 | 6 | case MCK_ConstantSImm11_0: return true0 ; |
2603 | 6 | case MCK_SImm10Lsl2: return true0 ; |
2604 | 6 | case MCK_SImm10Lsl3: return true0 ; |
2605 | 6 | case MCK_SImm16: return true0 ; |
2606 | 6 | case MCK_SImm16_Relaxed: return true0 ; |
2607 | 6 | case MCK_UImm16_Relaxed: return true0 ; |
2608 | 6 | case MCK_ConstantUImm20_0: return true0 ; |
2609 | 6 | case MCK_ConstantUImm26_0: return true0 ; |
2610 | 6 | case MCK_SImm32: return true0 ; |
2611 | 6 | case MCK_SImm32_Relaxed: return true0 ; |
2612 | 6 | case MCK_UImm32_Coerced: return true0 ; |
2613 | 0 | } |
2614 | 0 | |
2615 | 0 | case MCK_ConstantUImm2_1: |
2616 | 0 | switch (B) { |
2617 | 0 | default: return false; |
2618 | 0 | case MCK_ConstantUImm3_0: return true; |
2619 | 0 | case MCK_ConstantSImm4_0: return true; |
2620 | 0 | case MCK_ConstantUImm4_0: return true; |
2621 | 0 | case MCK_ConstantSImm5_0: return true; |
2622 | 0 | case MCK_ConstantUImm5_0: return true; |
2623 | 0 | case MCK_ConstantUImm5_1: return true; |
2624 | 0 | case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; |
2625 | 0 | case MCK_ConstantUImm5_32_Norm: return true; |
2626 | 0 | case MCK_ConstantUImm5_32: return true; |
2627 | 0 | case MCK_ConstantUImm5_0_Report_UImm6: return true; |
2628 | 0 | case MCK_ConstantUImm5_33: return true; |
2629 | 0 | case MCK_ConstantUImmRange2_64: return true; |
2630 | 0 | case MCK_UImm5Lsl2: return true; |
2631 | 0 | case MCK_ConstantSImm6_0: return true; |
2632 | 0 | case MCK_ConstantUImm6_0: return true; |
2633 | 0 | case MCK_UImm6Lsl2: return true; |
2634 | 0 | case MCK_ConstantUImm7_0: return true; |
2635 | 0 | case MCK_UImm7_N1: return true; |
2636 | 0 | case MCK_ConstantUImm8_0: return true; |
2637 | 0 | case MCK_SImm7Lsl2: return true; |
2638 | 0 | case MCK_ConstantSImm9_0: return true; |
2639 | 0 | case MCK_ConstantSImm10_0: return true; |
2640 | 0 | case MCK_ConstantUImm10_0: return true; |
2641 | 0 | case MCK_SImm10Lsl1: return true; |
2642 | 0 | case MCK_ConstantSImm11_0: return true; |
2643 | 0 | case MCK_SImm10Lsl2: return true; |
2644 | 0 | case MCK_SImm10Lsl3: return true; |
2645 | 0 | case MCK_SImm16: return true; |
2646 | 0 | case MCK_SImm16_Relaxed: return true; |
2647 | 0 | case MCK_UImm16_Relaxed: return true; |
2648 | 0 | case MCK_ConstantUImm20_0: return true; |
2649 | 0 | case MCK_ConstantUImm26_0: return true; |
2650 | 0 | case MCK_SImm32: return true; |
2651 | 0 | case MCK_SImm32_Relaxed: return true; |
2652 | 0 | case MCK_UImm32_Coerced: return true; |
2653 | 0 | } |
2654 | 0 | |
2655 | 0 | case MCK_ConstantUImm3_0: |
2656 | 0 | switch (B) { |
2657 | 0 | default: return false; |
2658 | 0 | case MCK_ConstantSImm4_0: return true; |
2659 | 0 | case MCK_ConstantUImm4_0: return true; |
2660 | 0 | case MCK_ConstantSImm5_0: return true; |
2661 | 0 | case MCK_ConstantUImm5_0: return true; |
2662 | 0 | case MCK_ConstantUImm5_1: return true; |
2663 | 0 | case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; |
2664 | 0 | case MCK_ConstantUImm5_32_Norm: return true; |
2665 | 0 | case MCK_ConstantUImm5_32: return true; |
2666 | 0 | case MCK_ConstantUImm5_0_Report_UImm6: return true; |
2667 | 0 | case MCK_ConstantUImm5_33: return true; |
2668 | 0 | case MCK_ConstantUImmRange2_64: return true; |
2669 | 0 | case MCK_UImm5Lsl2: return true; |
2670 | 0 | case MCK_ConstantSImm6_0: return true; |
2671 | 0 | case MCK_ConstantUImm6_0: return true; |
2672 | 0 | case MCK_UImm6Lsl2: return true; |
2673 | 0 | case MCK_ConstantUImm7_0: return true; |
2674 | 0 | case MCK_UImm7_N1: return true; |
2675 | 0 | case MCK_ConstantUImm8_0: return true; |
2676 | 0 | case MCK_SImm7Lsl2: return true; |
2677 | 0 | case MCK_ConstantSImm9_0: return true; |
2678 | 0 | case MCK_ConstantSImm10_0: return true; |
2679 | 0 | case MCK_ConstantUImm10_0: return true; |
2680 | 0 | case MCK_SImm10Lsl1: return true; |
2681 | 0 | case MCK_ConstantSImm11_0: return true; |
2682 | 0 | case MCK_SImm10Lsl2: return true; |
2683 | 0 | case MCK_SImm10Lsl3: return true; |
2684 | 0 | case MCK_SImm16: return true; |
2685 | 0 | case MCK_SImm16_Relaxed: return true; |
2686 | 0 | case MCK_UImm16_Relaxed: return true; |
2687 | 0 | case MCK_ConstantUImm20_0: return true; |
2688 | 0 | case MCK_ConstantUImm26_0: return true; |
2689 | 0 | case MCK_SImm32: return true; |
2690 | 0 | case MCK_SImm32_Relaxed: return true; |
2691 | 0 | case MCK_UImm32_Coerced: return true; |
2692 | 0 | } |
2693 | 0 | |
2694 | 0 | case MCK_ConstantSImm4_0: |
2695 | 0 | switch (B) { |
2696 | 0 | default: return false; |
2697 | 0 | case MCK_ConstantUImm4_0: return true; |
2698 | 0 | case MCK_ConstantSImm5_0: return true; |
2699 | 0 | case MCK_ConstantUImm5_0: return true; |
2700 | 0 | case MCK_ConstantUImm5_1: return true; |
2701 | 0 | case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; |
2702 | 0 | case MCK_ConstantUImm5_32_Norm: return true; |
2703 | 0 | case MCK_ConstantUImm5_32: return true; |
2704 | 0 | case MCK_ConstantUImm5_0_Report_UImm6: return true; |
2705 | 0 | case MCK_ConstantUImm5_33: return true; |
2706 | 0 | case MCK_ConstantUImmRange2_64: return true; |
2707 | 0 | case MCK_UImm5Lsl2: return true; |
2708 | 0 | case MCK_ConstantSImm6_0: return true; |
2709 | 0 | case MCK_ConstantUImm6_0: return true; |
2710 | 0 | case MCK_UImm6Lsl2: return true; |
2711 | 0 | case MCK_ConstantUImm7_0: return true; |
2712 | 0 | case MCK_UImm7_N1: return true; |
2713 | 0 | case MCK_ConstantUImm8_0: return true; |
2714 | 0 | case MCK_SImm7Lsl2: return true; |
2715 | 0 | case MCK_ConstantSImm9_0: return true; |
2716 | 0 | case MCK_ConstantSImm10_0: return true; |
2717 | 0 | case MCK_ConstantUImm10_0: return true; |
2718 | 0 | case MCK_SImm10Lsl1: return true; |
2719 | 0 | case MCK_ConstantSImm11_0: return true; |
2720 | 0 | case MCK_SImm10Lsl2: return true; |
2721 | 0 | case MCK_SImm10Lsl3: return true; |
2722 | 0 | case MCK_SImm16: return true; |
2723 | 0 | case MCK_SImm16_Relaxed: return true; |
2724 | 0 | case MCK_UImm16_Relaxed: return true; |
2725 | 0 | case MCK_ConstantUImm20_0: return true; |
2726 | 0 | case MCK_ConstantUImm26_0: return true; |
2727 | 0 | case MCK_SImm32: return true; |
2728 | 0 | case MCK_SImm32_Relaxed: return true; |
2729 | 0 | case MCK_UImm32_Coerced: return true; |
2730 | 0 | } |
2731 | 0 | |
2732 | 6 | case MCK_ConstantUImm4_0: |
2733 | 6 | switch (B) { |
2734 | 6 | default: return false; |
2735 | 6 | case MCK_ConstantSImm5_0: return true0 ; |
2736 | 6 | case MCK_ConstantUImm5_0: return true0 ; |
2737 | 6 | case MCK_ConstantUImm5_1: return true0 ; |
2738 | 6 | case MCK_ConstantUImm5_Plus1_Report_UImm6: return true0 ; |
2739 | 6 | case MCK_ConstantUImm5_32_Norm: return true0 ; |
2740 | 6 | case MCK_ConstantUImm5_32: return true0 ; |
2741 | 6 | case MCK_ConstantUImm5_0_Report_UImm6: return true0 ; |
2742 | 6 | case MCK_ConstantUImm5_33: return true0 ; |
2743 | 6 | case MCK_ConstantUImmRange2_64: return true0 ; |
2744 | 6 | case MCK_UImm5Lsl2: return true0 ; |
2745 | 6 | case MCK_ConstantSImm6_0: return true0 ; |
2746 | 6 | case MCK_ConstantUImm6_0: return true0 ; |
2747 | 6 | case MCK_UImm6Lsl2: return true0 ; |
2748 | 6 | case MCK_ConstantUImm7_0: return true0 ; |
2749 | 6 | case MCK_UImm7_N1: return true0 ; |
2750 | 6 | case MCK_ConstantUImm8_0: return true0 ; |
2751 | 6 | case MCK_SImm7Lsl2: return true0 ; |
2752 | 6 | case MCK_ConstantSImm9_0: return true0 ; |
2753 | 6 | case MCK_ConstantSImm10_0: return true0 ; |
2754 | 6 | case MCK_ConstantUImm10_0: return true0 ; |
2755 | 6 | case MCK_SImm10Lsl1: return true0 ; |
2756 | 6 | case MCK_ConstantSImm11_0: return true0 ; |
2757 | 6 | case MCK_SImm10Lsl2: return true0 ; |
2758 | 6 | case MCK_SImm10Lsl3: return true0 ; |
2759 | 6 | case MCK_SImm16: return true0 ; |
2760 | 6 | case MCK_SImm16_Relaxed: return true0 ; |
2761 | 6 | case MCK_UImm16_Relaxed: return true0 ; |
2762 | 6 | case MCK_ConstantUImm20_0: return true0 ; |
2763 | 6 | case MCK_ConstantUImm26_0: return true0 ; |
2764 | 6 | case MCK_SImm32: return true0 ; |
2765 | 6 | case MCK_SImm32_Relaxed: return true0 ; |
2766 | 6 | case MCK_UImm32_Coerced: return true0 ; |
2767 | 0 | } |
2768 | 0 | |
2769 | 0 | case MCK_ConstantSImm5_0: |
2770 | 0 | switch (B) { |
2771 | 0 | default: return false; |
2772 | 0 | case MCK_ConstantUImm5_0: return true; |
2773 | 0 | case MCK_ConstantUImm5_1: return true; |
2774 | 0 | case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; |
2775 | 0 | case MCK_ConstantUImm5_32_Norm: return true; |
2776 | 0 | case MCK_ConstantUImm5_32: return true; |
2777 | 0 | case MCK_ConstantUImm5_0_Report_UImm6: return true; |
2778 | 0 | case MCK_ConstantUImm5_33: return true; |
2779 | 0 | case MCK_ConstantUImmRange2_64: return true; |
2780 | 0 | case MCK_UImm5Lsl2: return true; |
2781 | 0 | case MCK_ConstantSImm6_0: return true; |
2782 | 0 | case MCK_ConstantUImm6_0: return true; |
2783 | 0 | case MCK_UImm6Lsl2: return true; |
2784 | 0 | case MCK_ConstantUImm7_0: return true; |
2785 | 0 | case MCK_UImm7_N1: return true; |
2786 | 0 | case MCK_ConstantUImm8_0: return true; |
2787 | 0 | case MCK_SImm7Lsl2: return true; |
2788 | 0 | case MCK_ConstantSImm9_0: return true; |
2789 | 0 | case MCK_ConstantSImm10_0: return true; |
2790 | 0 | case MCK_ConstantUImm10_0: return true; |
2791 | 0 | case MCK_SImm10Lsl1: return true; |
2792 | 0 | case MCK_ConstantSImm11_0: return true; |
2793 | 0 | case MCK_SImm10Lsl2: return true; |
2794 | 0 | case MCK_SImm10Lsl3: return true; |
2795 | 0 | case MCK_SImm16: return true; |
2796 | 0 | case MCK_SImm16_Relaxed: return true; |
2797 | 0 | case MCK_UImm16_Relaxed: return true; |
2798 | 0 | case MCK_ConstantUImm20_0: return true; |
2799 | 0 | case MCK_ConstantUImm26_0: return true; |
2800 | 0 | case MCK_SImm32: return true; |
2801 | 0 | case MCK_SImm32_Relaxed: return true; |
2802 | 0 | case MCK_UImm32_Coerced: return true; |
2803 | 0 | } |
2804 | 0 | |
2805 | 3 | case MCK_ConstantUImm5_0: |
2806 | 3 | switch (B) { |
2807 | 3 | default: return false; |
2808 | 3 | case MCK_ConstantUImm5_1: return true0 ; |
2809 | 3 | case MCK_ConstantUImm5_Plus1_Report_UImm6: return true0 ; |
2810 | 3 | case MCK_ConstantUImm5_32_Norm: return true0 ; |
2811 | 3 | case MCK_ConstantUImm5_32: return true0 ; |
2812 | 3 | case MCK_ConstantUImm5_0_Report_UImm6: return true0 ; |
2813 | 3 | case MCK_ConstantUImm5_33: return true0 ; |
2814 | 3 | case MCK_ConstantUImmRange2_64: return true0 ; |
2815 | 3 | case MCK_UImm5Lsl2: return true0 ; |
2816 | 3 | case MCK_ConstantSImm6_0: return true0 ; |
2817 | 3 | case MCK_ConstantUImm6_0: return true0 ; |
2818 | 3 | case MCK_UImm6Lsl2: return true0 ; |
2819 | 3 | case MCK_ConstantUImm7_0: return true0 ; |
2820 | 3 | case MCK_UImm7_N1: return true0 ; |
2821 | 3 | case MCK_ConstantUImm8_0: return true0 ; |
2822 | 3 | case MCK_SImm7Lsl2: return true0 ; |
2823 | 3 | case MCK_ConstantSImm9_0: return true0 ; |
2824 | 3 | case MCK_ConstantSImm10_0: return true0 ; |
2825 | 3 | case MCK_ConstantUImm10_0: return true0 ; |
2826 | 3 | case MCK_SImm10Lsl1: return true0 ; |
2827 | 3 | case MCK_ConstantSImm11_0: return true0 ; |
2828 | 3 | case MCK_SImm10Lsl2: return true0 ; |
2829 | 3 | case MCK_SImm10Lsl3: return true0 ; |
2830 | 3 | case MCK_SImm16: return true0 ; |
2831 | 3 | case MCK_SImm16_Relaxed: return true0 ; |
2832 | 3 | case MCK_UImm16_Relaxed: return true0 ; |
2833 | 3 | case MCK_ConstantUImm20_0: return true0 ; |
2834 | 3 | case MCK_ConstantUImm26_0: return true0 ; |
2835 | 3 | case MCK_SImm32: return true0 ; |
2836 | 3 | case MCK_SImm32_Relaxed: return true0 ; |
2837 | 3 | case MCK_UImm32_Coerced: return true0 ; |
2838 | 0 | } |
2839 | 0 | |
2840 | 0 | case MCK_ConstantUImm5_1: |
2841 | 0 | switch (B) { |
2842 | 0 | default: return false; |
2843 | 0 | case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; |
2844 | 0 | case MCK_ConstantUImm5_32_Norm: return true; |
2845 | 0 | case MCK_ConstantUImm5_32: return true; |
2846 | 0 | case MCK_ConstantUImm5_0_Report_UImm6: return true; |
2847 | 0 | case MCK_ConstantUImm5_33: return true; |
2848 | 0 | case MCK_ConstantUImmRange2_64: return true; |
2849 | 0 | case MCK_UImm5Lsl2: return true; |
2850 | 0 | case MCK_ConstantSImm6_0: return true; |
2851 | 0 | case MCK_ConstantUImm6_0: return true; |
2852 | 0 | case MCK_UImm6Lsl2: return true; |
2853 | 0 | case MCK_ConstantUImm7_0: return true; |
2854 | 0 | case MCK_UImm7_N1: return true; |
2855 | 0 | case MCK_ConstantUImm8_0: return true; |
2856 | 0 | case MCK_SImm7Lsl2: return true; |
2857 | 0 | case MCK_ConstantSImm9_0: return true; |
2858 | 0 | case MCK_ConstantSImm10_0: return true; |
2859 | 0 | case MCK_ConstantUImm10_0: return true; |
2860 | 0 | case MCK_SImm10Lsl1: return true; |
2861 | 0 | case MCK_ConstantSImm11_0: return true; |
2862 | 0 | case MCK_SImm10Lsl2: return true; |
2863 | 0 | case MCK_SImm10Lsl3: return true; |
2864 | 0 | case MCK_SImm16: return true; |
2865 | 0 | case MCK_SImm16_Relaxed: return true; |
2866 | 0 | case MCK_UImm16_Relaxed: return true; |
2867 | 0 | case MCK_ConstantUImm20_0: return true; |
2868 | 0 | case MCK_ConstantUImm26_0: return true; |
2869 | 0 | case MCK_SImm32: return true; |
2870 | 0 | case MCK_SImm32_Relaxed: return true; |
2871 | 0 | case MCK_UImm32_Coerced: return true; |
2872 | 0 | } |
2873 | 0 | |
2874 | 0 | case MCK_ConstantUImm5_Plus1_Report_UImm6: |
2875 | 0 | switch (B) { |
2876 | 0 | default: return false; |
2877 | 0 | case MCK_ConstantUImm5_32_Norm: return true; |
2878 | 0 | case MCK_ConstantUImm5_32: return true; |
2879 | 0 | case MCK_ConstantUImm5_0_Report_UImm6: return true; |
2880 | 0 | case MCK_ConstantUImm5_33: return true; |
2881 | 0 | case MCK_ConstantUImmRange2_64: return true; |
2882 | 0 | case MCK_UImm5Lsl2: return true; |
2883 | 0 | case MCK_ConstantSImm6_0: return true; |
2884 | 0 | case MCK_ConstantUImm6_0: return true; |
2885 | 0 | case MCK_UImm6Lsl2: return true; |
2886 | 0 | case MCK_ConstantUImm7_0: return true; |
2887 | 0 | case MCK_UImm7_N1: return true; |
2888 | 0 | case MCK_ConstantUImm8_0: return true; |
2889 | 0 | case MCK_SImm7Lsl2: return true; |
2890 | 0 | case MCK_ConstantSImm9_0: return true; |
2891 | 0 | case MCK_ConstantSImm10_0: return true; |
2892 | 0 | case MCK_ConstantUImm10_0: return true; |
2893 | 0 | case MCK_SImm10Lsl1: return true; |
2894 | 0 | case MCK_ConstantSImm11_0: return true; |
2895 | 0 | case MCK_SImm10Lsl2: return true; |
2896 | 0 | case MCK_SImm10Lsl3: return true; |
2897 | 0 | case MCK_SImm16: return true; |
2898 | 0 | case MCK_SImm16_Relaxed: return true; |
2899 | 0 | case MCK_UImm16_Relaxed: return true; |
2900 | 0 | case MCK_ConstantUImm20_0: return true; |
2901 | 0 | case MCK_ConstantUImm26_0: return true; |
2902 | 0 | case MCK_SImm32: return true; |
2903 | 0 | case MCK_SImm32_Relaxed: return true; |
2904 | 0 | case MCK_UImm32_Coerced: return true; |
2905 | 0 | } |
2906 | 0 | |
2907 | 0 | case MCK_ConstantUImm5_32_Norm: |
2908 | 0 | switch (B) { |
2909 | 0 | default: return false; |
2910 | 0 | case MCK_ConstantUImm5_32: return true; |
2911 | 0 | case MCK_ConstantUImm5_0_Report_UImm6: return true; |
2912 | 0 | case MCK_ConstantUImm5_33: return true; |
2913 | 0 | case MCK_ConstantUImmRange2_64: return true; |
2914 | 0 | case MCK_UImm5Lsl2: return true; |
2915 | 0 | case MCK_ConstantSImm6_0: return true; |
2916 | 0 | case MCK_ConstantUImm6_0: return true; |
2917 | 0 | case MCK_UImm6Lsl2: return true; |
2918 | 0 | case MCK_ConstantUImm7_0: return true; |
2919 | 0 | case MCK_UImm7_N1: return true; |
2920 | 0 | case MCK_ConstantUImm8_0: return true; |
2921 | 0 | case MCK_SImm7Lsl2: return true; |
2922 | 0 | case MCK_ConstantSImm9_0: return true; |
2923 | 0 | case MCK_ConstantSImm10_0: return true; |
2924 | 0 | case MCK_ConstantUImm10_0: return true; |
2925 | 0 | case MCK_SImm10Lsl1: return true; |
2926 | 0 | case MCK_ConstantSImm11_0: return true; |
2927 | 0 | case MCK_SImm10Lsl2: return true; |
2928 | 0 | case MCK_SImm10Lsl3: return true; |
2929 | 0 | case MCK_SImm16: return true; |
2930 | 0 | case MCK_SImm16_Relaxed: return true; |
2931 | 0 | case MCK_UImm16_Relaxed: return true; |
2932 | 0 | case MCK_ConstantUImm20_0: return true; |
2933 | 0 | case MCK_ConstantUImm26_0: return true; |
2934 | 0 | case MCK_SImm32: return true; |
2935 | 0 | case MCK_SImm32_Relaxed: return true; |
2936 | 0 | case MCK_UImm32_Coerced: return true; |
2937 | 0 | } |
2938 | 0 | |
2939 | 0 | case MCK_ConstantUImm5_32: |
2940 | 0 | switch (B) { |
2941 | 0 | default: return false; |
2942 | 0 | case MCK_ConstantUImm5_0_Report_UImm6: return true; |
2943 | 0 | case MCK_ConstantUImm5_33: return true; |
2944 | 0 | case MCK_ConstantUImmRange2_64: return true; |
2945 | 0 | case MCK_UImm5Lsl2: return true; |
2946 | 0 | case MCK_ConstantSImm6_0: return true; |
2947 | 0 | case MCK_ConstantUImm6_0: return true; |
2948 | 0 | case MCK_UImm6Lsl2: return true; |
2949 | 0 | case MCK_ConstantUImm7_0: return true; |
2950 | 0 | case MCK_UImm7_N1: return true; |
2951 | 0 | case MCK_ConstantUImm8_0: return true; |
2952 | 0 | case MCK_SImm7Lsl2: return true; |
2953 | 0 | case MCK_ConstantSImm9_0: return true; |
2954 | 0 | case MCK_ConstantSImm10_0: return true; |
2955 | 0 | case MCK_ConstantUImm10_0: return true; |
2956 | 0 | case MCK_SImm10Lsl1: return true; |
2957 | 0 | case MCK_ConstantSImm11_0: return true; |
2958 | 0 | case MCK_SImm10Lsl2: return true; |
2959 | 0 | case MCK_SImm10Lsl3: return true; |
2960 | 0 | case MCK_SImm16: return true; |
2961 | 0 | case MCK_SImm16_Relaxed: return true; |
2962 | 0 | case MCK_UImm16_Relaxed: return true; |
2963 | 0 | case MCK_ConstantUImm20_0: return true; |
2964 | 0 | case MCK_ConstantUImm26_0: return true; |
2965 | 0 | case MCK_SImm32: return true; |
2966 | 0 | case MCK_SImm32_Relaxed: return true; |
2967 | 0 | case MCK_UImm32_Coerced: return true; |
2968 | 0 | } |
2969 | 0 | |
2970 | 0 | case MCK_ConstantUImm5_0_Report_UImm6: |
2971 | 0 | switch (B) { |
2972 | 0 | default: return false; |
2973 | 0 | case MCK_ConstantUImm5_33: return true; |
2974 | 0 | case MCK_ConstantUImmRange2_64: return true; |
2975 | 0 | case MCK_UImm5Lsl2: return true; |
2976 | 0 | case MCK_ConstantSImm6_0: return true; |
2977 | 0 | case MCK_ConstantUImm6_0: return true; |
2978 | 0 | case MCK_UImm6Lsl2: return true; |
2979 | 0 | case MCK_ConstantUImm7_0: return true; |
2980 | 0 | case MCK_UImm7_N1: return true; |
2981 | 0 | case MCK_ConstantUImm8_0: return true; |
2982 | 0 | case MCK_SImm7Lsl2: return true; |
2983 | 0 | case MCK_ConstantSImm9_0: return true; |
2984 | 0 | case MCK_ConstantSImm10_0: return true; |
2985 | 0 | case MCK_ConstantUImm10_0: return true; |
2986 | 0 | case MCK_SImm10Lsl1: return true; |
2987 | 0 | case MCK_ConstantSImm11_0: return true; |
2988 | 0 | case MCK_SImm10Lsl2: return true; |
2989 | 0 | case MCK_SImm10Lsl3: return true; |
2990 | 0 | case MCK_SImm16: return true; |
2991 | 0 | case MCK_SImm16_Relaxed: return true; |
2992 | 0 | case MCK_UImm16_Relaxed: return true; |
2993 | 0 | case MCK_ConstantUImm20_0: return true; |
2994 | 0 | case MCK_ConstantUImm26_0: return true; |
2995 | 0 | case MCK_SImm32: return true; |
2996 | 0 | case MCK_SImm32_Relaxed: return true; |
2997 | 0 | case MCK_UImm32_Coerced: return true; |
2998 | 0 | } |
2999 | 0 | |
3000 | 0 | case MCK_ConstantUImm5_33: |
3001 | 0 | switch (B) { |
3002 | 0 | default: return false; |
3003 | 0 | case MCK_ConstantUImmRange2_64: return true; |
3004 | 0 | case MCK_UImm5Lsl2: return true; |
3005 | 0 | case MCK_ConstantSImm6_0: return true; |
3006 | 0 | case MCK_ConstantUImm6_0: return true; |
3007 | 0 | case MCK_UImm6Lsl2: return true; |
3008 | 0 | case MCK_ConstantUImm7_0: return true; |
3009 | 0 | case MCK_UImm7_N1: return true; |
3010 | 0 | case MCK_ConstantUImm8_0: return true; |
3011 | 0 | case MCK_SImm7Lsl2: return true; |
3012 | 0 | case MCK_ConstantSImm9_0: return true; |
3013 | 0 | case MCK_ConstantSImm10_0: return true; |
3014 | 0 | case MCK_ConstantUImm10_0: return true; |
3015 | 0 | case MCK_SImm10Lsl1: return true; |
3016 | 0 | case MCK_ConstantSImm11_0: return true; |
3017 | 0 | case MCK_SImm10Lsl2: return true; |
3018 | 0 | case MCK_SImm10Lsl3: return true; |
3019 | 0 | case MCK_SImm16: return true; |
3020 | 0 | case MCK_SImm16_Relaxed: return true; |
3021 | 0 | case MCK_UImm16_Relaxed: return true; |
3022 | 0 | case MCK_ConstantUImm20_0: return true; |
3023 | 0 | case MCK_ConstantUImm26_0: return true; |
3024 | 0 | case MCK_SImm32: return true; |
3025 | 0 | case MCK_SImm32_Relaxed: return true; |
3026 | 0 | case MCK_UImm32_Coerced: return true; |
3027 | 0 | } |
3028 | 0 | |
3029 | 0 | case MCK_ConstantUImmRange2_64: |
3030 | 0 | switch (B) { |
3031 | 0 | default: return false; |
3032 | 0 | case MCK_UImm5Lsl2: return true; |
3033 | 0 | case MCK_ConstantSImm6_0: return true; |
3034 | 0 | case MCK_ConstantUImm6_0: return true; |
3035 | 0 | case MCK_UImm6Lsl2: return true; |
3036 | 0 | case MCK_ConstantUImm7_0: return true; |
3037 | 0 | case MCK_UImm7_N1: return true; |
3038 | 0 | case MCK_ConstantUImm8_0: return true; |
3039 | 0 | case MCK_SImm7Lsl2: return true; |
3040 | 0 | case MCK_ConstantSImm9_0: return true; |
3041 | 0 | case MCK_ConstantSImm10_0: return true; |
3042 | 0 | case MCK_ConstantUImm10_0: return true; |
3043 | 0 | case MCK_SImm10Lsl1: return true; |
3044 | 0 | case MCK_ConstantSImm11_0: return true; |
3045 | 0 | case MCK_SImm10Lsl2: return true; |
3046 | 0 | case MCK_SImm10Lsl3: return true; |
3047 | 0 | case MCK_SImm16: return true; |
3048 | 0 | case MCK_SImm16_Relaxed: return true; |
3049 | 0 | case MCK_UImm16_Relaxed: return true; |
3050 | 0 | case MCK_ConstantUImm20_0: return true; |
3051 | 0 | case MCK_ConstantUImm26_0: return true; |
3052 | 0 | case MCK_SImm32: return true; |
3053 | 0 | case MCK_SImm32_Relaxed: return true; |
3054 | 0 | case MCK_UImm32_Coerced: return true; |
3055 | 0 | } |
3056 | 0 | |
3057 | 0 | case MCK_UImm5Lsl2: |
3058 | 0 | switch (B) { |
3059 | 0 | default: return false; |
3060 | 0 | case MCK_ConstantSImm6_0: return true; |
3061 | 0 | case MCK_ConstantUImm6_0: return true; |
3062 | 0 | case MCK_UImm6Lsl2: return true; |
3063 | 0 | case MCK_ConstantUImm7_0: return true; |
3064 | 0 | case MCK_UImm7_N1: return true; |
3065 | 0 | case MCK_ConstantUImm8_0: return true; |
3066 | 0 | case MCK_SImm7Lsl2: return true; |
3067 | 0 | case MCK_ConstantSImm9_0: return true; |
3068 | 0 | case MCK_ConstantSImm10_0: return true; |
3069 | 0 | case MCK_ConstantUImm10_0: return true; |
3070 | 0 | case MCK_SImm10Lsl1: return true; |
3071 | 0 | case MCK_ConstantSImm11_0: return true; |
3072 | 0 | case MCK_SImm10Lsl2: return true; |
3073 | 0 | case MCK_SImm10Lsl3: return true; |
3074 | 0 | case MCK_SImm16: return true; |
3075 | 0 | case MCK_SImm16_Relaxed: return true; |
3076 | 0 | case MCK_UImm16_Relaxed: return true; |
3077 | 0 | case MCK_ConstantUImm20_0: return true; |
3078 | 0 | case MCK_ConstantUImm26_0: return true; |
3079 | 0 | case MCK_SImm32: return true; |
3080 | 0 | case MCK_SImm32_Relaxed: return true; |
3081 | 0 | case MCK_UImm32_Coerced: return true; |
3082 | 0 | } |
3083 | 0 | |
3084 | 0 | case MCK_ConstantSImm6_0: |
3085 | 0 | switch (B) { |
3086 | 0 | default: return false; |
3087 | 0 | case MCK_ConstantUImm6_0: return true; |
3088 | 0 | case MCK_UImm6Lsl2: return true; |
3089 | 0 | case MCK_ConstantUImm7_0: return true; |
3090 | 0 | case MCK_UImm7_N1: return true; |
3091 | 0 | case MCK_ConstantUImm8_0: return true; |
3092 | 0 | case MCK_SImm7Lsl2: return true; |
3093 | 0 | case MCK_ConstantSImm9_0: return true; |
3094 | 0 | case MCK_ConstantSImm10_0: return true; |
3095 | 0 | case MCK_ConstantUImm10_0: return true; |
3096 | 0 | case MCK_SImm10Lsl1: return true; |
3097 | 0 | case MCK_ConstantSImm11_0: return true; |
3098 | 0 | case MCK_SImm10Lsl2: return true; |
3099 | 0 | case MCK_SImm10Lsl3: return true; |
3100 | 0 | case MCK_SImm16: return true; |
3101 | 0 | case MCK_SImm16_Relaxed: return true; |
3102 | 0 | case MCK_UImm16_Relaxed: return true; |
3103 | 0 | case MCK_ConstantUImm20_0: return true; |
3104 | 0 | case MCK_ConstantUImm26_0: return true; |
3105 | 0 | case MCK_SImm32: return true; |
3106 | 0 | case MCK_SImm32_Relaxed: return true; |
3107 | 0 | case MCK_UImm32_Coerced: return true; |
3108 | 0 | } |
3109 | 0 | |
3110 | 0 | case MCK_ConstantUImm6_0: |
3111 | 0 | switch (B) { |
3112 | 0 | default: return false; |
3113 | 0 | case MCK_UImm6Lsl2: return true; |
3114 | 0 | case MCK_ConstantUImm7_0: return true; |
3115 | 0 | case MCK_UImm7_N1: return true; |
3116 | 0 | case MCK_ConstantUImm8_0: return true; |
3117 | 0 | case MCK_SImm7Lsl2: return true; |
3118 | 0 | case MCK_ConstantSImm9_0: return true; |
3119 | 0 | case MCK_ConstantSImm10_0: return true; |
3120 | 0 | case MCK_ConstantUImm10_0: return true; |
3121 | 0 | case MCK_SImm10Lsl1: return true; |
3122 | 0 | case MCK_ConstantSImm11_0: return true; |
3123 | 0 | case MCK_SImm10Lsl2: return true; |
3124 | 0 | case MCK_SImm10Lsl3: return true; |
3125 | 0 | case MCK_SImm16: return true; |
3126 | 0 | case MCK_SImm16_Relaxed: return true; |
3127 | 0 | case MCK_UImm16_Relaxed: return true; |
3128 | 0 | case MCK_ConstantUImm20_0: return true; |
3129 | 0 | case MCK_ConstantUImm26_0: return true; |
3130 | 0 | case MCK_SImm32: return true; |
3131 | 0 | case MCK_SImm32_Relaxed: return true; |
3132 | 0 | case MCK_UImm32_Coerced: return true; |
3133 | 0 | } |
3134 | 0 | |
3135 | 0 | case MCK_UImm6Lsl2: |
3136 | 0 | switch (B) { |
3137 | 0 | default: return false; |
3138 | 0 | case MCK_ConstantUImm7_0: return true; |
3139 | 0 | case MCK_UImm7_N1: return true; |
3140 | 0 | case MCK_ConstantUImm8_0: return true; |
3141 | 0 | case MCK_SImm7Lsl2: return true; |
3142 | 0 | case MCK_ConstantSImm9_0: return true; |
3143 | 0 | case MCK_ConstantSImm10_0: return true; |
3144 | 0 | case MCK_ConstantUImm10_0: return true; |
3145 | 0 | case MCK_SImm10Lsl1: return true; |
3146 | 0 | case MCK_ConstantSImm11_0: return true; |
3147 | 0 | case MCK_SImm10Lsl2: return true; |
3148 | 0 | case MCK_SImm10Lsl3: return true; |
3149 | 0 | case MCK_SImm16: return true; |
3150 | 0 | case MCK_SImm16_Relaxed: return true; |
3151 | 0 | case MCK_UImm16_Relaxed: return true; |
3152 | 0 | case MCK_ConstantUImm20_0: return true; |
3153 | 0 | case MCK_ConstantUImm26_0: return true; |
3154 | 0 | case MCK_SImm32: return true; |
3155 | 0 | case MCK_SImm32_Relaxed: return true; |
3156 | 0 | case MCK_UImm32_Coerced: return true; |
3157 | 0 | } |
3158 | 0 | |
3159 | 0 | case MCK_ConstantUImm7_0: |
3160 | 0 | switch (B) { |
3161 | 0 | default: return false; |
3162 | 0 | case MCK_UImm7_N1: return true; |
3163 | 0 | case MCK_ConstantUImm8_0: return true; |
3164 | 0 | case MCK_SImm7Lsl2: return true; |
3165 | 0 | case MCK_ConstantSImm9_0: return true; |
3166 | 0 | case MCK_ConstantSImm10_0: return true; |
3167 | 0 | case MCK_ConstantUImm10_0: return true; |
3168 | 0 | case MCK_SImm10Lsl1: return true; |
3169 | 0 | case MCK_ConstantSImm11_0: return true; |
3170 | 0 | case MCK_SImm10Lsl2: return true; |
3171 | 0 | case MCK_SImm10Lsl3: return true; |
3172 | 0 | case MCK_SImm16: return true; |
3173 | 0 | case MCK_SImm16_Relaxed: return true; |
3174 | 0 | case MCK_UImm16_Relaxed: return true; |
3175 | 0 | case MCK_ConstantUImm20_0: return true; |
3176 | 0 | case MCK_ConstantUImm26_0: return true; |
3177 | 0 | case MCK_SImm32: return true; |
3178 | 0 | case MCK_SImm32_Relaxed: return true; |
3179 | 0 | case MCK_UImm32_Coerced: return true; |
3180 | 0 | } |
3181 | 0 | |
3182 | 0 | case MCK_UImm7_N1: |
3183 | 0 | switch (B) { |
3184 | 0 | default: return false; |
3185 | 0 | case MCK_ConstantUImm8_0: return true; |
3186 | 0 | case MCK_SImm7Lsl2: return true; |
3187 | 0 | case MCK_ConstantSImm9_0: return true; |
3188 | 0 | case MCK_ConstantSImm10_0: return true; |
3189 | 0 | case MCK_ConstantUImm10_0: return true; |
3190 | 0 | case MCK_SImm10Lsl1: return true; |
3191 | 0 | case MCK_ConstantSImm11_0: return true; |
3192 | 0 | case MCK_SImm10Lsl2: return true; |
3193 | 0 | case MCK_SImm10Lsl3: return true; |
3194 | 0 | case MCK_SImm16: return true; |
3195 | 0 | case MCK_SImm16_Relaxed: return true; |
3196 | 0 | case MCK_UImm16_Relaxed: return true; |
3197 | 0 | case MCK_ConstantUImm20_0: return true; |
3198 | 0 | case MCK_ConstantUImm26_0: return true; |
3199 | 0 | case MCK_SImm32: return true; |
3200 | 0 | case MCK_SImm32_Relaxed: return true; |
3201 | 0 | case MCK_UImm32_Coerced: return true; |
3202 | 0 | } |
3203 | 0 | |
3204 | 0 | case MCK_ConstantUImm8_0: |
3205 | 0 | switch (B) { |
3206 | 0 | default: return false; |
3207 | 0 | case MCK_SImm7Lsl2: return true; |
3208 | 0 | case MCK_ConstantSImm9_0: return true; |
3209 | 0 | case MCK_ConstantSImm10_0: return true; |
3210 | 0 | case MCK_ConstantUImm10_0: return true; |
3211 | 0 | case MCK_SImm10Lsl1: return true; |
3212 | 0 | case MCK_ConstantSImm11_0: return true; |
3213 | 0 | case MCK_SImm10Lsl2: return true; |
3214 | 0 | case MCK_SImm10Lsl3: return true; |
3215 | 0 | case MCK_SImm16: return true; |
3216 | 0 | case MCK_SImm16_Relaxed: return true; |
3217 | 0 | case MCK_UImm16_Relaxed: return true; |
3218 | 0 | case MCK_ConstantUImm20_0: return true; |
3219 | 0 | case MCK_ConstantUImm26_0: return true; |
3220 | 0 | case MCK_SImm32: return true; |
3221 | 0 | case MCK_SImm32_Relaxed: return true; |
3222 | 0 | case MCK_UImm32_Coerced: return true; |
3223 | 0 | } |
3224 | 0 | |
3225 | 0 | case MCK_SImm7Lsl2: |
3226 | 0 | switch (B) { |
3227 | 0 | default: return false; |
3228 | 0 | case MCK_ConstantSImm9_0: return true; |
3229 | 0 | case MCK_ConstantSImm10_0: return true; |
3230 | 0 | case MCK_ConstantUImm10_0: return true; |
3231 | 0 | case MCK_SImm10Lsl1: return true; |
3232 | 0 | case MCK_ConstantSImm11_0: return true; |
3233 | 0 | case MCK_SImm10Lsl2: return true; |
3234 | 0 | case MCK_SImm10Lsl3: return true; |
3235 | 0 | case MCK_SImm16: return true; |
3236 | 0 | case MCK_SImm16_Relaxed: return true; |
3237 | 0 | case MCK_UImm16_Relaxed: return true; |
3238 | 0 | case MCK_ConstantUImm20_0: return true; |
3239 | 0 | case MCK_ConstantUImm26_0: return true; |
3240 | 0 | case MCK_SImm32: return true; |
3241 | 0 | case MCK_SImm32_Relaxed: return true; |
3242 | 0 | case MCK_UImm32_Coerced: return true; |
3243 | 0 | } |
3244 | 0 | |
3245 | 0 | case MCK_ConstantSImm9_0: |
3246 | 0 | switch (B) { |
3247 | 0 | default: return false; |
3248 | 0 | case MCK_ConstantSImm10_0: return true; |
3249 | 0 | case MCK_ConstantUImm10_0: return true; |
3250 | 0 | case MCK_SImm10Lsl1: return true; |
3251 | 0 | case MCK_ConstantSImm11_0: return true; |
3252 | 0 | case MCK_SImm10Lsl2: return true; |
3253 | 0 | case MCK_SImm10Lsl3: return true; |
3254 | 0 | case MCK_SImm16: return true; |
3255 | 0 | case MCK_SImm16_Relaxed: return true; |
3256 | 0 | case MCK_UImm16_Relaxed: return true; |
3257 | 0 | case MCK_ConstantUImm20_0: return true; |
3258 | 0 | case MCK_ConstantUImm26_0: return true; |
3259 | 0 | case MCK_SImm32: return true; |
3260 | 0 | case MCK_SImm32_Relaxed: return true; |
3261 | 0 | case MCK_UImm32_Coerced: return true; |
3262 | 0 | } |
3263 | 0 | |
3264 | 0 | case MCK_ConstantSImm10_0: |
3265 | 0 | switch (B) { |
3266 | 0 | default: return false; |
3267 | 0 | case MCK_ConstantUImm10_0: return true; |
3268 | 0 | case MCK_SImm10Lsl1: return true; |
3269 | 0 | case MCK_ConstantSImm11_0: return true; |
3270 | 0 | case MCK_SImm10Lsl2: return true; |
3271 | 0 | case MCK_SImm10Lsl3: return true; |
3272 | 0 | case MCK_SImm16: return true; |
3273 | 0 | case MCK_SImm16_Relaxed: return true; |
3274 | 0 | case MCK_UImm16_Relaxed: return true; |
3275 | 0 | case MCK_ConstantUImm20_0: return true; |
3276 | 0 | case MCK_ConstantUImm26_0: return true; |
3277 | 0 | case MCK_SImm32: return true; |
3278 | 0 | case MCK_SImm32_Relaxed: return true; |
3279 | 0 | case MCK_UImm32_Coerced: return true; |
3280 | 0 | } |
3281 | 0 | |
3282 | 10 | case MCK_ConstantUImm10_0: |
3283 | 10 | switch (B) { |
3284 | 10 | default: return false; |
3285 | 10 | case MCK_SImm10Lsl1: return true0 ; |
3286 | 10 | case MCK_ConstantSImm11_0: return true0 ; |
3287 | 10 | case MCK_SImm10Lsl2: return true0 ; |
3288 | 10 | case MCK_SImm10Lsl3: return true0 ; |
3289 | 10 | case MCK_SImm16: return true0 ; |
3290 | 10 | case MCK_SImm16_Relaxed: return true0 ; |
3291 | 10 | case MCK_UImm16_Relaxed: return true0 ; |
3292 | 10 | case MCK_ConstantUImm20_0: return true0 ; |
3293 | 10 | case MCK_ConstantUImm26_0: return true0 ; |
3294 | 10 | case MCK_SImm32: return true0 ; |
3295 | 10 | case MCK_SImm32_Relaxed: return true0 ; |
3296 | 10 | case MCK_UImm32_Coerced: return true0 ; |
3297 | 0 | } |
3298 | 0 | |
3299 | 0 | case MCK_SImm10Lsl1: |
3300 | 0 | switch (B) { |
3301 | 0 | default: return false; |
3302 | 0 | case MCK_ConstantSImm11_0: return true; |
3303 | 0 | case MCK_SImm10Lsl2: return true; |
3304 | 0 | case MCK_SImm10Lsl3: return true; |
3305 | 0 | case MCK_SImm16: return true; |
3306 | 0 | case MCK_SImm16_Relaxed: return true; |
3307 | 0 | case MCK_UImm16_Relaxed: return true; |
3308 | 0 | case MCK_ConstantUImm20_0: return true; |
3309 | 0 | case MCK_ConstantUImm26_0: return true; |
3310 | 0 | case MCK_SImm32: return true; |
3311 | 0 | case MCK_SImm32_Relaxed: return true; |
3312 | 0 | case MCK_UImm32_Coerced: return true; |
3313 | 0 | } |
3314 | 0 | |
3315 | 0 | case MCK_ConstantSImm11_0: |
3316 | 0 | switch (B) { |
3317 | 0 | default: return false; |
3318 | 0 | case MCK_SImm10Lsl2: return true; |
3319 | 0 | case MCK_SImm10Lsl3: return true; |
3320 | 0 | case MCK_SImm16: return true; |
3321 | 0 | case MCK_SImm16_Relaxed: return true; |
3322 | 0 | case MCK_UImm16_Relaxed: return true; |
3323 | 0 | case MCK_ConstantUImm20_0: return true; |
3324 | 0 | case MCK_ConstantUImm26_0: return true; |
3325 | 0 | case MCK_SImm32: return true; |
3326 | 0 | case MCK_SImm32_Relaxed: return true; |
3327 | 0 | case MCK_UImm32_Coerced: return true; |
3328 | 0 | } |
3329 | 0 | |
3330 | 0 | case MCK_SImm10Lsl2: |
3331 | 0 | switch (B) { |
3332 | 0 | default: return false; |
3333 | 0 | case MCK_SImm10Lsl3: return true; |
3334 | 0 | case MCK_SImm16: return true; |
3335 | 0 | case MCK_SImm16_Relaxed: return true; |
3336 | 0 | case MCK_UImm16_Relaxed: return true; |
3337 | 0 | case MCK_ConstantUImm20_0: return true; |
3338 | 0 | case MCK_ConstantUImm26_0: return true; |
3339 | 0 | case MCK_SImm32: return true; |
3340 | 0 | case MCK_SImm32_Relaxed: return true; |
3341 | 0 | case MCK_UImm32_Coerced: return true; |
3342 | 0 | } |
3343 | 0 | |
3344 | 0 | case MCK_SImm10Lsl3: |
3345 | 0 | switch (B) { |
3346 | 0 | default: return false; |
3347 | 0 | case MCK_SImm16: return true; |
3348 | 0 | case MCK_SImm16_Relaxed: return true; |
3349 | 0 | case MCK_UImm16_Relaxed: return true; |
3350 | 0 | case MCK_ConstantUImm20_0: return true; |
3351 | 0 | case MCK_ConstantUImm26_0: return true; |
3352 | 0 | case MCK_SImm32: return true; |
3353 | 0 | case MCK_SImm32_Relaxed: return true; |
3354 | 0 | case MCK_UImm32_Coerced: return true; |
3355 | 0 | } |
3356 | 0 | |
3357 | 10 | case MCK_SImm16: |
3358 | 10 | switch (B) { |
3359 | 10 | default: return false; |
3360 | 10 | case MCK_SImm16_Relaxed: return true0 ; |
3361 | 10 | case MCK_UImm16_Relaxed: return true0 ; |
3362 | 10 | case MCK_ConstantUImm20_0: return true0 ; |
3363 | 10 | case MCK_ConstantUImm26_0: return true0 ; |
3364 | 10 | case MCK_SImm32: return true0 ; |
3365 | 10 | case MCK_SImm32_Relaxed: return true0 ; |
3366 | 10 | case MCK_UImm32_Coerced: return true0 ; |
3367 | 0 | } |
3368 | 0 | |
3369 | 0 | case MCK_SImm16_Relaxed: |
3370 | 0 | switch (B) { |
3371 | 0 | default: return false; |
3372 | 0 | case MCK_UImm16_Relaxed: return true; |
3373 | 0 | case MCK_ConstantUImm20_0: return true; |
3374 | 0 | case MCK_ConstantUImm26_0: return true; |
3375 | 0 | case MCK_SImm32: return true; |
3376 | 0 | case MCK_SImm32_Relaxed: return true; |
3377 | 0 | case MCK_UImm32_Coerced: return true; |
3378 | 0 | } |
3379 | 0 | |
3380 | 0 | case MCK_UImm16_AltRelaxed: |
3381 | 0 | switch (B) { |
3382 | 0 | default: return false; |
3383 | 0 | case MCK_UImm16_Relaxed: return true; |
3384 | 0 | case MCK_ConstantUImm20_0: return true; |
3385 | 0 | case MCK_ConstantUImm26_0: return true; |
3386 | 0 | case MCK_SImm32: return true; |
3387 | 0 | case MCK_SImm32_Relaxed: return true; |
3388 | 0 | case MCK_UImm32_Coerced: return true; |
3389 | 0 | } |
3390 | 0 | |
3391 | 0 | case MCK_UImm16: |
3392 | 0 | switch (B) { |
3393 | 0 | default: return false; |
3394 | 0 | case MCK_UImm16_Relaxed: return true; |
3395 | 0 | case MCK_ConstantUImm20_0: return true; |
3396 | 0 | case MCK_ConstantUImm26_0: return true; |
3397 | 0 | case MCK_SImm32: return true; |
3398 | 0 | case MCK_SImm32_Relaxed: return true; |
3399 | 0 | case MCK_UImm32_Coerced: return true; |
3400 | 0 | } |
3401 | 0 | |
3402 | 0 | case MCK_SImm19Lsl2: |
3403 | 0 | switch (B) { |
3404 | 0 | default: return false; |
3405 | 0 | case MCK_ConstantUImm20_0: return true; |
3406 | 0 | case MCK_ConstantUImm26_0: return true; |
3407 | 0 | case MCK_SImm32: return true; |
3408 | 0 | case MCK_SImm32_Relaxed: return true; |
3409 | 0 | case MCK_UImm32_Coerced: return true; |
3410 | 0 | } |
3411 | 0 | |
3412 | 0 | case MCK_UImm16_Relaxed: |
3413 | 0 | switch (B) { |
3414 | 0 | default: return false; |
3415 | 0 | case MCK_ConstantUImm20_0: return true; |
3416 | 0 | case MCK_ConstantUImm26_0: return true; |
3417 | 0 | case MCK_SImm32: return true; |
3418 | 0 | case MCK_SImm32_Relaxed: return true; |
3419 | 0 | case MCK_UImm32_Coerced: return true; |
3420 | 0 | } |
3421 | 0 | |
3422 | 0 | case MCK_ConstantUImm20_0: |
3423 | 0 | switch (B) { |
3424 | 0 | default: return false; |
3425 | 0 | case MCK_ConstantUImm26_0: return true; |
3426 | 0 | case MCK_SImm32: return true; |
3427 | 0 | case MCK_SImm32_Relaxed: return true; |
3428 | 0 | case MCK_UImm32_Coerced: return true; |
3429 | 0 | } |
3430 | 0 | |
3431 | 0 | case MCK_ConstantUImm26_0: |
3432 | 0 | switch (B) { |
3433 | 0 | default: return false; |
3434 | 0 | case MCK_SImm32: return true; |
3435 | 0 | case MCK_SImm32_Relaxed: return true; |
3436 | 0 | case MCK_UImm32_Coerced: return true; |
3437 | 0 | } |
3438 | 0 | |
3439 | 0 | case MCK_SImm32: |
3440 | 0 | switch (B) { |
3441 | 0 | default: return false; |
3442 | 0 | case MCK_SImm32_Relaxed: return true; |
3443 | 0 | case MCK_UImm32_Coerced: return true; |
3444 | 0 | } |
3445 | 0 | |
3446 | 0 | case MCK_SImm32_Relaxed: |
3447 | 0 | return B == MCK_UImm32_Coerced; |
3448 | 38.8k | } |
3449 | 38.8k | } |
3450 | | |
3451 | 164k | static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) { |
3452 | 164k | MipsOperand &Operand = (MipsOperand&)GOp; |
3453 | 164k | if (Kind == InvalidMatchClass) |
3454 | 5.11k | return MCTargetAsmParser::Match_InvalidOperand; |
3455 | 158k | |
3456 | 158k | if (Operand.isToken() && Kind <= MCK_LAST_TOKEN880 ) |
3457 | 880 | return isSubclass(matchTokenString(Operand.getToken()), Kind) ? |
3458 | 880 | MCTargetAsmParser::Match_Success : |
3459 | 880 | MCTargetAsmParser::Match_InvalidOperand0 ; |
3460 | 158k | |
3461 | 158k | switch (Kind) { |
3462 | 158k | default: break14.5k ; |
3463 | 158k | // 'ACC64DSPAsmReg' class |
3464 | 158k | case MCK_ACC64DSPAsmReg: { |
3465 | 571 | DiagnosticPredicate DP(Operand.isACCAsmReg()); |
3466 | 571 | if (DP.isMatch()) |
3467 | 420 | return MCTargetAsmParser::Match_Success; |
3468 | 151 | break; |
3469 | 151 | } |
3470 | 151 | // 'AFGR64AsmReg' class |
3471 | 4.71k | case MCK_AFGR64AsmReg: { |
3472 | 4.71k | DiagnosticPredicate DP(Operand.isFGRAsmReg()); |
3473 | 4.71k | if (DP.isMatch()) |
3474 | 4.21k | return MCTargetAsmParser::Match_Success; |
3475 | 498 | break; |
3476 | 498 | } |
3477 | 498 | // 'CCRAsmReg' class |
3478 | 498 | case MCK_CCRAsmReg: { |
3479 | 46 | DiagnosticPredicate DP(Operand.isCCRAsmReg()); |
3480 | 46 | if (DP.isMatch()) |
3481 | 46 | return MCTargetAsmParser::Match_Success; |
3482 | 0 | break; |
3483 | 0 | } |
3484 | 0 | // 'COP0AsmReg' class |
3485 | 680 | case MCK_COP0AsmReg: { |
3486 | 680 | DiagnosticPredicate DP(Operand.isCOP0AsmReg()); |
3487 | 680 | if (DP.isMatch()) |
3488 | 548 | return MCTargetAsmParser::Match_Success; |
3489 | 132 | break; |
3490 | 132 | } |
3491 | 132 | // 'COP2AsmReg' class |
3492 | 566 | case MCK_COP2AsmReg: { |
3493 | 566 | DiagnosticPredicate DP(Operand.isCOP2AsmReg()); |
3494 | 566 | if (DP.isMatch()) |
3495 | 564 | return MCTargetAsmParser::Match_Success; |
3496 | 2 | break; |
3497 | 2 | } |
3498 | 2 | // 'COP3AsmReg' class |
3499 | 16 | case MCK_COP3AsmReg: { |
3500 | 16 | DiagnosticPredicate DP(Operand.isCOP3AsmReg()); |
3501 | 16 | if (DP.isMatch()) |
3502 | 16 | return MCTargetAsmParser::Match_Success; |
3503 | 0 | break; |
3504 | 0 | } |
3505 | 0 | // 'FCCAsmReg' class |
3506 | 2.07k | case MCK_FCCAsmReg: { |
3507 | 2.07k | DiagnosticPredicate DP(Operand.isFCCAsmReg()); |
3508 | 2.07k | if (DP.isMatch()) |
3509 | 1.65k | return MCTargetAsmParser::Match_Success; |
3510 | 418 | break; |
3511 | 418 | } |
3512 | 418 | // 'FGR32AsmReg' class |
3513 | 6.77k | case MCK_FGR32AsmReg: { |
3514 | 6.77k | DiagnosticPredicate DP(Operand.isFGRAsmReg()); |
3515 | 6.77k | if (DP.isMatch()) |
3516 | 6.23k | return MCTargetAsmParser::Match_Success; |
3517 | 545 | break; |
3518 | 545 | } |
3519 | 545 | // 'FGR64AsmReg' class |
3520 | 4.35k | case MCK_FGR64AsmReg: { |
3521 | 4.35k | DiagnosticPredicate DP(Operand.isFGRAsmReg()); |
3522 | 4.35k | if (DP.isMatch()) |
3523 | 3.85k | return MCTargetAsmParser::Match_Success; |
3524 | 500 | break; |
3525 | 500 | } |
3526 | 500 | // 'GPR32AsmReg' class |
3527 | 66.6k | case MCK_GPR32AsmReg: { |
3528 | 66.6k | DiagnosticPredicate DP(Operand.isGPRAsmReg()); |
3529 | 66.6k | if (DP.isMatch()) |
3530 | 62.8k | return MCTargetAsmParser::Match_Success; |
3531 | 3.80k | break; |
3532 | 3.80k | } |
3533 | 3.80k | // 'GPR32NonZeroAsmReg' class |
3534 | 3.80k | case MCK_GPR32NonZeroAsmReg: { |
3535 | 130 | DiagnosticPredicate DP(Operand.isGPRNonZeroAsmReg()); |
3536 | 130 | if (DP.isMatch()) |
3537 | 76 | return MCTargetAsmParser::Match_Success; |
3538 | 54 | break; |
3539 | 54 | } |
3540 | 54 | // 'GPR32ZeroAsmReg' class |
3541 | 100 | case MCK_GPR32ZeroAsmReg: { |
3542 | 100 | DiagnosticPredicate DP(Operand.isGPRZeroAsmReg()); |
3543 | 100 | if (DP.isMatch()) |
3544 | 54 | return MCTargetAsmParser::Match_Success; |
3545 | 46 | break; |
3546 | 46 | } |
3547 | 46 | // 'GPR64AsmReg' class |
3548 | 8.45k | case MCK_GPR64AsmReg: { |
3549 | 8.45k | DiagnosticPredicate DP(Operand.isGPRAsmReg()); |
3550 | 8.45k | if (DP.isMatch()) |
3551 | 7.98k | return MCTargetAsmParser::Match_Success; |
3552 | 465 | break; |
3553 | 465 | } |
3554 | 465 | // 'GPRMM16AsmReg' class |
3555 | 465 | case MCK_GPRMM16AsmReg: { |
3556 | 269 | DiagnosticPredicate DP(Operand.isMM16AsmReg()); |
3557 | 269 | if (DP.isMatch()) |
3558 | 234 | return MCTargetAsmParser::Match_Success; |
3559 | 35 | break; |
3560 | 35 | } |
3561 | 35 | // 'GPRMM16AsmRegMoveP' class |
3562 | 35 | case MCK_GPRMM16AsmRegMoveP: { |
3563 | 28 | DiagnosticPredicate DP(Operand.isMM16AsmRegMoveP()); |
3564 | 28 | if (DP.isMatch()) |
3565 | 20 | return MCTargetAsmParser::Match_Success; |
3566 | 8 | break; |
3567 | 8 | } |
3568 | 8 | // 'GPRMM16AsmRegMovePPairFirst' class |
3569 | 20 | case MCK_GPRMM16AsmRegMovePPairFirst: { |
3570 | 20 | DiagnosticPredicate DP(Operand.isMM16AsmRegMovePPairFirst()); |
3571 | 20 | if (DP.isMatch()) |
3572 | 16 | return MCTargetAsmParser::Match_Success; |
3573 | 4 | break; |
3574 | 4 | } |
3575 | 4 | // 'GPRMM16AsmRegMovePPairSecond' class |
3576 | 16 | case MCK_GPRMM16AsmRegMovePPairSecond: { |
3577 | 16 | DiagnosticPredicate DP(Operand.isMM16AsmRegMovePPairSecond()); |
3578 | 16 | if (DP.isMatch()) |
3579 | 16 | return MCTargetAsmParser::Match_Success; |
3580 | 0 | break; |
3581 | 0 | } |
3582 | 0 | // 'GPRMM16AsmRegZero' class |
3583 | 65 | case MCK_GPRMM16AsmRegZero: { |
3584 | 65 | DiagnosticPredicate DP(Operand.isMM16AsmRegZero()); |
3585 | 65 | if (DP.isMatch()) |
3586 | 41 | return MCTargetAsmParser::Match_Success; |
3587 | 24 | break; |
3588 | 24 | } |
3589 | 24 | // 'HI32DSPAsmReg' class |
3590 | 24 | case MCK_HI32DSPAsmReg: { |
3591 | 9 | DiagnosticPredicate DP(Operand.isACCAsmReg()); |
3592 | 9 | if (DP.isMatch()) |
3593 | 9 | return MCTargetAsmParser::Match_Success; |
3594 | 0 | break; |
3595 | 0 | } |
3596 | 0 | // 'HWRegsAsmReg' class |
3597 | 85 | case MCK_HWRegsAsmReg: { |
3598 | 85 | DiagnosticPredicate DP(Operand.isHWRegsAsmReg()); |
3599 | 85 | if (DP.isMatch()) |
3600 | 85 | return MCTargetAsmParser::Match_Success; |
3601 | 0 | break; |
3602 | 0 | } |
3603 | 0 | // 'Imm' class |
3604 | 3.07k | case MCK_Imm: { |
3605 | 3.07k | DiagnosticPredicate DP(Operand.isImm()); |
3606 | 3.07k | if (DP.isMatch()) |
3607 | 1.99k | return MCTargetAsmParser::Match_Success; |
3608 | 1.07k | break; |
3609 | 1.07k | } |
3610 | 1.07k | // 'LO32DSPAsmReg' class |
3611 | 1.07k | case MCK_LO32DSPAsmReg: { |
3612 | 9 | DiagnosticPredicate DP(Operand.isACCAsmReg()); |
3613 | 9 | if (DP.isMatch()) |
3614 | 9 | return MCTargetAsmParser::Match_Success; |
3615 | 0 | break; |
3616 | 0 | } |
3617 | 0 | // 'MSA128AsmReg' class |
3618 | 2.13k | case MCK_MSA128AsmReg: { |
3619 | 2.13k | DiagnosticPredicate DP(Operand.isMSA128AsmReg()); |
3620 | 2.13k | if (DP.isMatch()) |
3621 | 2.13k | return MCTargetAsmParser::Match_Success; |
3622 | 0 | break; |
3623 | 0 | } |
3624 | 0 | // 'MSACtrlAsmReg' class |
3625 | 38 | case MCK_MSACtrlAsmReg: { |
3626 | 38 | DiagnosticPredicate DP(Operand.isMSACtrlAsmReg()); |
3627 | 38 | if (DP.isMatch()) |
3628 | 32 | return MCTargetAsmParser::Match_Success; |
3629 | 6 | break; |
3630 | 6 | } |
3631 | 6 | // 'MicroMipsMemGP' class |
3632 | 6 | case MCK_MicroMipsMemGP: { |
3633 | 0 | DiagnosticPredicate DP(Operand.isMemWithSimmWordAlignedOffsetGP<9>()); |
3634 | 0 | if (DP.isMatch()) |
3635 | 0 | return MCTargetAsmParser::Match_Success; |
3636 | 0 | break; |
3637 | 0 | } |
3638 | 0 | // 'MicroMipsMem' class |
3639 | 75 | case MCK_MicroMipsMem: { |
3640 | 75 | DiagnosticPredicate DP(Operand.isMemWithGRPMM16Base()); |
3641 | 75 | if (DP.isMatch()) |
3642 | 57 | return MCTargetAsmParser::Match_Success; |
3643 | 18 | break; |
3644 | 18 | } |
3645 | 18 | // 'MicroMipsMemSP' class |
3646 | 10.4k | case MCK_MicroMipsMemSP: { |
3647 | 10.4k | DiagnosticPredicate DP(Operand.isMemWithUimmWordAlignedOffsetSP<7>()); |
3648 | 10.4k | if (DP.isMatch()) |
3649 | 59 | return MCTargetAsmParser::Match_Success; |
3650 | 10.4k | break; |
3651 | 10.4k | } |
3652 | 10.4k | // 'InvNum' class |
3653 | 10.4k | case MCK_InvNum: { |
3654 | 245 | DiagnosticPredicate DP(Operand.isInvNum()); |
3655 | 245 | if (DP.isMatch()) |
3656 | 106 | return MCTargetAsmParser::Match_Success; |
3657 | 139 | break; |
3658 | 139 | } |
3659 | 139 | // 'JumpTarget' class |
3660 | 2.60k | case MCK_JumpTarget: { |
3661 | 2.60k | DiagnosticPredicate DP(Operand.isImm()); |
3662 | 2.60k | if (DP.isMatch()) |
3663 | 2.28k | return MCTargetAsmParser::Match_Success; |
3664 | 322 | break; |
3665 | 322 | } |
3666 | 322 | // 'MemOffsetSimm10' class |
3667 | 322 | case MCK_MemOffsetSimm10: { |
3668 | 7 | DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10>()); |
3669 | 7 | if (DP.isMatch()) |
3670 | 3 | return MCTargetAsmParser::Match_Success; |
3671 | 4 | if (DP.isNearMatch()) |
3672 | 4 | return MipsAsmParser::Match_MemSImm10; |
3673 | 0 | break; |
3674 | 0 | } |
3675 | 0 | // 'MemOffsetSimm10_1' class |
3676 | 9 | case MCK_MemOffsetSimm10_1: { |
3677 | 9 | DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 1>()); |
3678 | 9 | if (DP.isMatch()) |
3679 | 5 | return MCTargetAsmParser::Match_Success; |
3680 | 4 | if (DP.isNearMatch()) |
3681 | 4 | return MipsAsmParser::Match_MemSImm10Lsl1; |
3682 | 0 | break; |
3683 | 0 | } |
3684 | 0 | // 'MemOffsetSimm10_2' class |
3685 | 10 | case MCK_MemOffsetSimm10_2: { |
3686 | 10 | DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 2>()); |
3687 | 10 | if (DP.isMatch()) |
3688 | 6 | return MCTargetAsmParser::Match_Success; |
3689 | 4 | if (DP.isNearMatch()) |
3690 | 4 | return MipsAsmParser::Match_MemSImm10Lsl2; |
3691 | 0 | break; |
3692 | 0 | } |
3693 | 0 | // 'MemOffsetSimm10_3' class |
3694 | 13 | case MCK_MemOffsetSimm10_3: { |
3695 | 13 | DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 3>()); |
3696 | 13 | if (DP.isMatch()) |
3697 | 9 | return MCTargetAsmParser::Match_Success; |
3698 | 4 | if (DP.isNearMatch()) |
3699 | 4 | return MipsAsmParser::Match_MemSImm10Lsl3; |
3700 | 0 | break; |
3701 | 0 | } |
3702 | 0 | // 'MemOffsetSimm11' class |
3703 | 304 | case MCK_MemOffsetSimm11: { |
3704 | 304 | DiagnosticPredicate DP(Operand.isMemWithSimmOffset<11>()); |
3705 | 304 | if (DP.isMatch()) |
3706 | 58 | return MCTargetAsmParser::Match_Success; |
3707 | 246 | if (DP.isNearMatch()) |
3708 | 246 | return MipsAsmParser::Match_MemSImm11; |
3709 | 0 | break; |
3710 | 0 | } |
3711 | 0 | // 'MemOffsetSimm12' class |
3712 | 40 | case MCK_MemOffsetSimm12: { |
3713 | 40 | DiagnosticPredicate DP(Operand.isMemWithSimmOffset<12>()); |
3714 | 40 | if (DP.isMatch()) |
3715 | 25 | return MCTargetAsmParser::Match_Success; |
3716 | 15 | if (DP.isNearMatch()) |
3717 | 15 | return MipsAsmParser::Match_MemSImm12; |
3718 | 0 | break; |
3719 | 0 | } |
3720 | 0 | // 'MemOffsetSimm16' class |
3721 | 1.00k | case MCK_MemOffsetSimm16: { |
3722 | 1.00k | DiagnosticPredicate DP(Operand.isMemWithSimmOffset<16>()); |
3723 | 1.00k | if (DP.isMatch()) |
3724 | 721 | return MCTargetAsmParser::Match_Success; |
3725 | 287 | if (DP.isNearMatch()) |
3726 | 287 | return MipsAsmParser::Match_MemSImm16; |
3727 | 0 | break; |
3728 | 0 | } |
3729 | 0 | // 'MemOffsetSimm9' class |
3730 | 1.83k | case MCK_MemOffsetSimm9: { |
3731 | 1.83k | DiagnosticPredicate DP(Operand.isMemWithSimmOffset<9>()); |
3732 | 1.83k | if (DP.isMatch()) |
3733 | 586 | return MCTargetAsmParser::Match_Success; |
3734 | 1.25k | if (DP.isNearMatch()) |
3735 | 1.25k | return MipsAsmParser::Match_MemSImm9; |
3736 | 0 | break; |
3737 | 0 | } |
3738 | 0 | // 'MemOffsetSimmPtr' class |
3739 | 382 | case MCK_MemOffsetSimmPtr: { |
3740 | 382 | DiagnosticPredicate DP(Operand.isMemWithPtrSizeOffset()); |
3741 | 382 | if (DP.isMatch()) |
3742 | 336 | return MCTargetAsmParser::Match_Success; |
3743 | 46 | if (DP.isNearMatch()) |
3744 | 46 | return MipsAsmParser::Match_MemSImmPtr; |
3745 | 0 | break; |
3746 | 0 | } |
3747 | 0 | // 'MemOffsetUimm4' class |
3748 | 18 | case MCK_MemOffsetUimm4: { |
3749 | 18 | DiagnosticPredicate DP(Operand.isMemWithUimmOffsetSP<6>()); |
3750 | 18 | if (DP.isMatch()) |
3751 | 10 | return MCTargetAsmParser::Match_Success; |
3752 | 8 | break; |
3753 | 8 | } |
3754 | 8 | // 'Mem' class |
3755 | 12.0k | case MCK_Mem: { |
3756 | 12.0k | DiagnosticPredicate DP(Operand.isMem()); |
3757 | 12.0k | if (DP.isMatch()) |
3758 | 11.9k | return MCTargetAsmParser::Match_Success; |
3759 | 148 | break; |
3760 | 148 | } |
3761 | 148 | // 'RegList16' class |
3762 | 148 | case MCK_RegList16: { |
3763 | 36 | DiagnosticPredicate DP(Operand.isRegList16()); |
3764 | 36 | if (DP.isMatch()) |
3765 | 18 | return MCTargetAsmParser::Match_Success; |
3766 | 18 | break; |
3767 | 18 | } |
3768 | 18 | // 'RegList' class |
3769 | 55 | case MCK_RegList: { |
3770 | 55 | DiagnosticPredicate DP(Operand.isRegList()); |
3771 | 55 | if (DP.isMatch()) |
3772 | 55 | return MCTargetAsmParser::Match_Success; |
3773 | 0 | break; |
3774 | 0 | } |
3775 | 0 | // 'Simm19_Lsl2' class |
3776 | 92 | case MCK_Simm19_Lsl2: { |
3777 | 92 | DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>()); |
3778 | 92 | if (DP.isMatch()) |
3779 | 50 | return MCTargetAsmParser::Match_Success; |
3780 | 42 | if (DP.isNearMatch()) |
3781 | 42 | return MipsAsmParser::Match_SImm19_Lsl2; |
3782 | 0 | break; |
3783 | 0 | } |
3784 | 0 | // 'StrictlyAFGR64AsmReg' class |
3785 | 91 | case MCK_StrictlyAFGR64AsmReg: { |
3786 | 91 | DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg()); |
3787 | 91 | if (DP.isMatch()) |
3788 | 91 | return MCTargetAsmParser::Match_Success; |
3789 | 0 | break; |
3790 | 0 | } |
3791 | 0 | // 'StrictlyFGR32AsmReg' class |
3792 | 66 | case MCK_StrictlyFGR32AsmReg: { |
3793 | 66 | DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg()); |
3794 | 66 | if (DP.isMatch()) |
3795 | 66 | return MCTargetAsmParser::Match_Success; |
3796 | 0 | break; |
3797 | 0 | } |
3798 | 0 | // 'StrictlyFGR64AsmReg' class |
3799 | 52 | case MCK_StrictlyFGR64AsmReg: { |
3800 | 52 | DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg()); |
3801 | 52 | if (DP.isMatch()) |
3802 | 52 | return MCTargetAsmParser::Match_Success; |
3803 | 0 | break; |
3804 | 0 | } |
3805 | 0 | // 'ConstantImmz' class |
3806 | 12 | case MCK_ConstantImmz: { |
3807 | 12 | DiagnosticPredicate DP(Operand.isConstantImmz()); |
3808 | 12 | if (DP.isMatch()) |
3809 | 4 | return MCTargetAsmParser::Match_Success; |
3810 | 8 | if (DP.isNearMatch()) |
3811 | 8 | return MipsAsmParser::Match_Immz; |
3812 | 0 | break; |
3813 | 0 | } |
3814 | 0 | // 'ConstantUImm1_0' class |
3815 | 69 | case MCK_ConstantUImm1_0: { |
3816 | 69 | DiagnosticPredicate DP(Operand.isConstantUImm<1, 0>()); |
3817 | 69 | if (DP.isMatch()) |
3818 | 55 | return MCTargetAsmParser::Match_Success; |
3819 | 14 | if (DP.isNearMatch()) |
3820 | 14 | return MipsAsmParser::Match_UImm1_0; |
3821 | 0 | break; |
3822 | 0 | } |
3823 | 0 | // 'ConstantUImm2_0' class |
3824 | 85 | case MCK_ConstantUImm2_0: { |
3825 | 85 | DiagnosticPredicate DP(Operand.isConstantUImm<2, 0>()); |
3826 | 85 | if (DP.isMatch()) |
3827 | 31 | return MCTargetAsmParser::Match_Success; |
3828 | 54 | if (DP.isNearMatch()) |
3829 | 54 | return MipsAsmParser::Match_UImm2_0; |
3830 | 0 | break; |
3831 | 0 | } |
3832 | 0 | // 'ConstantUImm2_1' class |
3833 | 56 | case MCK_ConstantUImm2_1: { |
3834 | 56 | DiagnosticPredicate DP(Operand.isConstantUImm<2, 1>()); |
3835 | 56 | if (DP.isMatch()) |
3836 | 18 | return MCTargetAsmParser::Match_Success; |
3837 | 38 | if (DP.isNearMatch()) |
3838 | 38 | return MipsAsmParser::Match_UImm2_1; |
3839 | 0 | break; |
3840 | 0 | } |
3841 | 0 | // 'ConstantUImm3_0' class |
3842 | 410 | case MCK_ConstantUImm3_0: { |
3843 | 410 | DiagnosticPredicate DP(Operand.isConstantUImm<3, 0>()); |
3844 | 410 | if (DP.isMatch()) |
3845 | 229 | return MCTargetAsmParser::Match_Success; |
3846 | 181 | if (DP.isNearMatch()) |
3847 | 181 | return MipsAsmParser::Match_UImm3_0; |
3848 | 0 | break; |
3849 | 0 | } |
3850 | 0 | // 'ConstantSImm4_0' class |
3851 | 8 | case MCK_ConstantSImm4_0: { |
3852 | 8 | DiagnosticPredicate DP(Operand.isConstantSImm<4, 0>()); |
3853 | 8 | if (DP.isMatch()) |
3854 | 4 | return MCTargetAsmParser::Match_Success; |
3855 | 4 | if (DP.isNearMatch()) |
3856 | 4 | return MipsAsmParser::Match_SImm4_0; |
3857 | 0 | break; |
3858 | 0 | } |
3859 | 0 | // 'ConstantUImm4_0' class |
3860 | 291 | case MCK_ConstantUImm4_0: { |
3861 | 291 | DiagnosticPredicate DP(Operand.isConstantUImm<4, 0>()); |
3862 | 291 | if (DP.isMatch()) |
3863 | 81 | return MCTargetAsmParser::Match_Success; |
3864 | 210 | if (DP.isNearMatch()) |
3865 | 210 | return MipsAsmParser::Match_UImm4_0; |
3866 | 0 | break; |
3867 | 0 | } |
3868 | 0 | // 'ConstantSImm5_0' class |
3869 | 60 | case MCK_ConstantSImm5_0: { |
3870 | 60 | DiagnosticPredicate DP(Operand.isConstantSImm<5, 0>()); |
3871 | 60 | if (DP.isMatch()) |
3872 | 20 | return MCTargetAsmParser::Match_Success; |
3873 | 40 | if (DP.isNearMatch()) |
3874 | 40 | return MipsAsmParser::Match_SImm5_0; |
3875 | 0 | break; |
3876 | 0 | } |
3877 | 0 | // 'ConstantUImm5_0' class |
3878 | 2.09k | case MCK_ConstantUImm5_0: { |
3879 | 2.09k | DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>()); |
3880 | 2.09k | if (DP.isMatch()) |
3881 | 869 | return MCTargetAsmParser::Match_Success; |
3882 | 1.22k | if (DP.isNearMatch()) |
3883 | 1.22k | return MipsAsmParser::Match_UImm5_0; |
3884 | 0 | break; |
3885 | 0 | } |
3886 | 0 | // 'ConstantUImm5_1' class |
3887 | 129 | case MCK_ConstantUImm5_1: { |
3888 | 129 | DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>()); |
3889 | 129 | if (DP.isMatch()) |
3890 | 79 | return MCTargetAsmParser::Match_Success; |
3891 | 50 | if (DP.isNearMatch()) |
3892 | 50 | return MipsAsmParser::Match_UImm5_1; |
3893 | 0 | break; |
3894 | 0 | } |
3895 | 0 | // 'ConstantUImm5_Plus1_Report_UImm6' class |
3896 | 11 | case MCK_ConstantUImm5_Plus1_Report_UImm6: { |
3897 | 11 | DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>()); |
3898 | 11 | if (DP.isMatch()) |
3899 | 9 | return MCTargetAsmParser::Match_Success; |
3900 | 2 | if (DP.isNearMatch()) |
3901 | 2 | return MipsAsmParser::Match_UImm5_1; |
3902 | 0 | break; |
3903 | 0 | } |
3904 | 0 | // 'ConstantUImm5_32_Norm' class |
3905 | 16 | case MCK_ConstantUImm5_32_Norm: { |
3906 | 16 | DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>()); |
3907 | 16 | if (DP.isMatch()) |
3908 | 6 | return MCTargetAsmParser::Match_Success; |
3909 | 10 | if (DP.isNearMatch()) |
3910 | 10 | return MipsAsmParser::Match_UImm5_32; |
3911 | 0 | break; |
3912 | 0 | } |
3913 | 0 | // 'ConstantUImm5_32' class |
3914 | 76 | case MCK_ConstantUImm5_32: { |
3915 | 76 | DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>()); |
3916 | 76 | if (DP.isMatch()) |
3917 | 34 | return MCTargetAsmParser::Match_Success; |
3918 | 42 | if (DP.isNearMatch()) |
3919 | 42 | return MipsAsmParser::Match_UImm5_32; |
3920 | 0 | break; |
3921 | 0 | } |
3922 | 0 | // 'ConstantUImm5_0_Report_UImm6' class |
3923 | 23 | case MCK_ConstantUImm5_0_Report_UImm6: { |
3924 | 23 | DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>()); |
3925 | 23 | if (DP.isMatch()) |
3926 | 13 | return MCTargetAsmParser::Match_Success; |
3927 | 10 | if (DP.isNearMatch()) |
3928 | 10 | return MipsAsmParser::Match_UImm5_0_Report_UImm6; |
3929 | 0 | break; |
3930 | 0 | } |
3931 | 0 | // 'ConstantUImm5_33' class |
3932 | 26 | case MCK_ConstantUImm5_33: { |
3933 | 26 | DiagnosticPredicate DP(Operand.isConstantUImm<5, 33>()); |
3934 | 26 | if (DP.isMatch()) |
3935 | 11 | return MCTargetAsmParser::Match_Success; |
3936 | 15 | if (DP.isNearMatch()) |
3937 | 15 | return MipsAsmParser::Match_UImm5_33; |
3938 | 0 | break; |
3939 | 0 | } |
3940 | 0 | // 'ConstantUImmRange2_64' class |
3941 | 28 | case MCK_ConstantUImmRange2_64: { |
3942 | 28 | DiagnosticPredicate DP(Operand.isConstantUImmRange<2, 64>()); |
3943 | 28 | if (DP.isMatch()) |
3944 | 18 | return MCTargetAsmParser::Match_Success; |
3945 | 10 | if (DP.isNearMatch()) |
3946 | 10 | return MipsAsmParser::Match_UImmRange2_64; |
3947 | 0 | break; |
3948 | 0 | } |
3949 | 0 | // 'UImm5Lsl2' class |
3950 | 26 | case MCK_UImm5Lsl2: { |
3951 | 26 | DiagnosticPredicate DP(Operand.isScaledUImm<5, 2>()); |
3952 | 26 | if (DP.isMatch()) |
3953 | 4 | return MCTargetAsmParser::Match_Success; |
3954 | 22 | if (DP.isNearMatch()) |
3955 | 22 | return MipsAsmParser::Match_UImm5_Lsl2; |
3956 | 0 | break; |
3957 | 0 | } |
3958 | 0 | // 'ConstantSImm6_0' class |
3959 | 22 | case MCK_ConstantSImm6_0: { |
3960 | 22 | DiagnosticPredicate DP(Operand.isConstantSImm<6, 0>()); |
3961 | 22 | if (DP.isMatch()) |
3962 | 14 | return MCTargetAsmParser::Match_Success; |
3963 | 8 | if (DP.isNearMatch()) |
3964 | 8 | return MipsAsmParser::Match_SImm6_0; |
3965 | 0 | break; |
3966 | 0 | } |
3967 | 0 | // 'ConstantUImm6_0' class |
3968 | 302 | case MCK_ConstantUImm6_0: { |
3969 | 302 | DiagnosticPredicate DP(Operand.isConstantUImm<6, 0>()); |
3970 | 302 | if (DP.isMatch()) |
3971 | 119 | return MCTargetAsmParser::Match_Success; |
3972 | 183 | if (DP.isNearMatch()) |
3973 | 183 | return MipsAsmParser::Match_UImm6_0; |
3974 | 0 | break; |
3975 | 0 | } |
3976 | 0 | // 'UImm6Lsl2' class |
3977 | 10 | case MCK_UImm6Lsl2: { |
3978 | 10 | DiagnosticPredicate DP(Operand.isScaledUImm<6, 2>()); |
3979 | 10 | if (DP.isMatch()) |
3980 | 4 | return MCTargetAsmParser::Match_Success; |
3981 | 6 | if (DP.isNearMatch()) |
3982 | 6 | return MipsAsmParser::Match_UImm6_Lsl2; |
3983 | 0 | break; |
3984 | 0 | } |
3985 | 0 | // 'ConstantUImm7_0' class |
3986 | 19 | case MCK_ConstantUImm7_0: { |
3987 | 19 | DiagnosticPredicate DP(Operand.isConstantUImm<7, 0>()); |
3988 | 19 | if (DP.isMatch()) |
3989 | 11 | return MCTargetAsmParser::Match_Success; |
3990 | 8 | if (DP.isNearMatch()) |
3991 | 8 | return MipsAsmParser::Match_UImm7_0; |
3992 | 0 | break; |
3993 | 0 | } |
3994 | 0 | // 'UImm7_N1' class |
3995 | 16 | case MCK_UImm7_N1: { |
3996 | 16 | DiagnosticPredicate DP(Operand.isConstantUImm<7, -1>()); |
3997 | 16 | if (DP.isMatch()) |
3998 | 8 | return MCTargetAsmParser::Match_Success; |
3999 | 8 | if (DP.isNearMatch()) |
4000 | 8 | return MipsAsmParser::Match_UImm7_N1; |
4001 | 0 | break; |
4002 | 0 | } |
4003 | 0 | // 'ConstantUImm8_0' class |
4004 | 46 | case MCK_ConstantUImm8_0: { |
4005 | 46 | DiagnosticPredicate DP(Operand.isConstantUImm<8, 0>()); |
4006 | 46 | if (DP.isMatch()) |
4007 | 19 | return MCTargetAsmParser::Match_Success; |
4008 | 27 | if (DP.isNearMatch()) |
4009 | 27 | return MipsAsmParser::Match_UImm8_0; |
4010 | 0 | break; |
4011 | 0 | } |
4012 | 0 | // 'SImm7Lsl2' class |
4013 | 0 | case MCK_SImm7Lsl2: { |
4014 | 0 | DiagnosticPredicate DP(Operand.isScaledSImm<7, 2>()); |
4015 | 0 | if (DP.isMatch()) |
4016 | 0 | return MCTargetAsmParser::Match_Success; |
4017 | 0 | if (DP.isNearMatch()) |
4018 | 0 | return MipsAsmParser::Match_SImm7_Lsl2; |
4019 | 0 | break; |
4020 | 0 | } |
4021 | 0 | // 'ConstantSImm9_0' class |
4022 | 0 | case MCK_ConstantSImm9_0: { |
4023 | 0 | DiagnosticPredicate DP(Operand.isConstantSImm<9, 0>()); |
4024 | 0 | if (DP.isMatch()) |
4025 | 0 | return MCTargetAsmParser::Match_Success; |
4026 | 0 | if (DP.isNearMatch()) |
4027 | 0 | return MipsAsmParser::Match_SImm9_0; |
4028 | 0 | break; |
4029 | 0 | } |
4030 | 0 | // 'ConstantSImm10_0' class |
4031 | 44 | case MCK_ConstantSImm10_0: { |
4032 | 44 | DiagnosticPredicate DP(Operand.isConstantSImm<10, 0>()); |
4033 | 44 | if (DP.isMatch()) |
4034 | 18 | return MCTargetAsmParser::Match_Success; |
4035 | 26 | if (DP.isNearMatch()) |
4036 | 26 | return MipsAsmParser::Match_SImm10_0; |
4037 | 0 | break; |
4038 | 0 | } |
4039 | 0 | // 'ConstantUImm10_0' class |
4040 | 470 | case MCK_ConstantUImm10_0: { |
4041 | 470 | DiagnosticPredicate DP(Operand.isConstantUImm<10, 0>()); |
4042 | 470 | if (DP.isMatch()) |
4043 | 258 | return MCTargetAsmParser::Match_Success; |
4044 | 212 | if (DP.isNearMatch()) |
4045 | 212 | return MipsAsmParser::Match_UImm10_0; |
4046 | 0 | break; |
4047 | 0 | } |
4048 | 0 | // 'SImm10Lsl1' class |
4049 | 0 | case MCK_SImm10Lsl1: { |
4050 | 0 | DiagnosticPredicate DP(Operand.isScaledSImm<10, 1>()); |
4051 | 0 | if (DP.isMatch()) |
4052 | 0 | return MCTargetAsmParser::Match_Success; |
4053 | 0 | if (DP.isNearMatch()) |
4054 | 0 | return MipsAsmParser::Match_SImm10_Lsl1; |
4055 | 0 | break; |
4056 | 0 | } |
4057 | 0 | // 'ConstantSImm11_0' class |
4058 | 0 | case MCK_ConstantSImm11_0: { |
4059 | 0 | DiagnosticPredicate DP(Operand.isConstantSImm<11, 0>()); |
4060 | 0 | if (DP.isMatch()) |
4061 | 0 | return MCTargetAsmParser::Match_Success; |
4062 | 0 | if (DP.isNearMatch()) |
4063 | 0 | return MipsAsmParser::Match_SImm11_0; |
4064 | 0 | break; |
4065 | 0 | } |
4066 | 0 | // 'SImm10Lsl2' class |
4067 | 0 | case MCK_SImm10Lsl2: { |
4068 | 0 | DiagnosticPredicate DP(Operand.isScaledSImm<10, 2>()); |
4069 | 0 | if (DP.isMatch()) |
4070 | 0 | return MCTargetAsmParser::Match_Success; |
4071 | 0 | if (DP.isNearMatch()) |
4072 | 0 | return MipsAsmParser::Match_SImm10_Lsl2; |
4073 | 0 | break; |
4074 | 0 | } |
4075 | 0 | // 'SImm10Lsl3' class |
4076 | 0 | case MCK_SImm10Lsl3: { |
4077 | 0 | DiagnosticPredicate DP(Operand.isScaledSImm<10, 3>()); |
4078 | 0 | if (DP.isMatch()) |
4079 | 0 | return MCTargetAsmParser::Match_Success; |
4080 | 0 | if (DP.isNearMatch()) |
4081 | 0 | return MipsAsmParser::Match_SImm10_Lsl3; |
4082 | 0 | break; |
4083 | 0 | } |
4084 | 0 | // 'SImm16' class |
4085 | 3.76k | case MCK_SImm16: { |
4086 | 3.76k | DiagnosticPredicate DP(Operand.isSImm<16>()); |
4087 | 3.76k | if (DP.isMatch()) |
4088 | 2.06k | return MCTargetAsmParser::Match_Success; |
4089 | 1.69k | if (DP.isNearMatch()) |
4090 | 1.69k | return MipsAsmParser::Match_SImm16; |
4091 | 0 | break; |
4092 | 0 | } |
4093 | 0 | // 'SImm16_Relaxed' class |
4094 | 1.14k | case MCK_SImm16_Relaxed: { |
4095 | 1.14k | DiagnosticPredicate DP(Operand.isAnyImm<16>()); |
4096 | 1.14k | if (DP.isMatch()) |
4097 | 519 | return MCTargetAsmParser::Match_Success; |
4098 | 622 | if (DP.isNearMatch()) |
4099 | 622 | return MipsAsmParser::Match_SImm16_Relaxed; |
4100 | 0 | break; |
4101 | 0 | } |
4102 | 0 | // 'UImm16_AltRelaxed' class |
4103 | 11 | case MCK_UImm16_AltRelaxed: { |
4104 | 11 | DiagnosticPredicate DP(Operand.isUImm<16>()); |
4105 | 11 | if (DP.isMatch()) |
4106 | 6 | return MCTargetAsmParser::Match_Success; |
4107 | 5 | if (DP.isNearMatch()) |
4108 | 5 | return MipsAsmParser::Match_UImm16_AltRelaxed; |
4109 | 0 | break; |
4110 | 0 | } |
4111 | 0 | // 'UImm16' class |
4112 | 917 | case MCK_UImm16: { |
4113 | 917 | DiagnosticPredicate DP(Operand.isUImm<16>()); |
4114 | 917 | if (DP.isMatch()) |
4115 | 361 | return MCTargetAsmParser::Match_Success; |
4116 | 556 | if (DP.isNearMatch()) |
4117 | 556 | return MipsAsmParser::Match_UImm16; |
4118 | 0 | break; |
4119 | 0 | } |
4120 | 0 | // 'SImm19Lsl2' class |
4121 | 0 | case MCK_SImm19Lsl2: { |
4122 | 0 | DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>()); |
4123 | 0 | if (DP.isMatch()) |
4124 | 0 | return MCTargetAsmParser::Match_Success; |
4125 | 0 | if (DP.isNearMatch()) |
4126 | 0 | return MipsAsmParser::Match_SImm19_Lsl2; |
4127 | 0 | break; |
4128 | 0 | } |
4129 | 0 | // 'UImm16_Relaxed' class |
4130 | 225 | case MCK_UImm16_Relaxed: { |
4131 | 225 | DiagnosticPredicate DP(Operand.isAnyImm<16>()); |
4132 | 225 | if (DP.isMatch()) |
4133 | 225 | return MCTargetAsmParser::Match_Success; |
4134 | 0 | if (DP.isNearMatch()) |
4135 | 0 | return MipsAsmParser::Match_UImm16_Relaxed; |
4136 | 0 | break; |
4137 | 0 | } |
4138 | 0 | // 'ConstantUImm20_0' class |
4139 | 47 | case MCK_ConstantUImm20_0: { |
4140 | 47 | DiagnosticPredicate DP(Operand.isConstantUImm<20, 0>()); |
4141 | 47 | if (DP.isMatch()) |
4142 | 32 | return MCTargetAsmParser::Match_Success; |
4143 | 15 | if (DP.isNearMatch()) |
4144 | 15 | return MipsAsmParser::Match_UImm20_0; |
4145 | 0 | break; |
4146 | 0 | } |
4147 | 0 | // 'ConstantUImm26_0' class |
4148 | 0 | case MCK_ConstantUImm26_0: { |
4149 | 0 | DiagnosticPredicate DP(Operand.isConstantUImm<26, 0>()); |
4150 | 0 | if (DP.isMatch()) |
4151 | 0 | return MCTargetAsmParser::Match_Success; |
4152 | 0 | if (DP.isNearMatch()) |
4153 | 0 | return MipsAsmParser::Match_UImm26_0; |
4154 | 0 | break; |
4155 | 0 | } |
4156 | 0 | // 'SImm32' class |
4157 | 247 | case MCK_SImm32: { |
4158 | 247 | DiagnosticPredicate DP(Operand.isSImm<32>()); |
4159 | 247 | if (DP.isMatch()) |
4160 | 62 | return MCTargetAsmParser::Match_Success; |
4161 | 185 | if (DP.isNearMatch()) |
4162 | 185 | return MipsAsmParser::Match_SImm32; |
4163 | 0 | break; |
4164 | 0 | } |
4165 | 0 | // 'SImm32_Relaxed' class |
4166 | 2.24k | case MCK_SImm32_Relaxed: { |
4167 | 2.24k | DiagnosticPredicate DP(Operand.isAnyImm<33>()); |
4168 | 2.24k | if (DP.isMatch()) |
4169 | 1.02k | return MCTargetAsmParser::Match_Success; |
4170 | 1.21k | if (DP.isNearMatch()) |
4171 | 1.21k | return MipsAsmParser::Match_SImm32_Relaxed; |
4172 | 0 | break; |
4173 | 0 | } |
4174 | 0 | // 'UImm32_Coerced' class |
4175 | 258 | case MCK_UImm32_Coerced: { |
4176 | 258 | DiagnosticPredicate DP(Operand.isSImm<33>()); |
4177 | 258 | if (DP.isMatch()) |
4178 | 218 | return MCTargetAsmParser::Match_Success; |
4179 | 40 | if (DP.isNearMatch()) |
4180 | 40 | return MipsAsmParser::Match_UImm32_Coerced; |
4181 | 0 | break; |
4182 | 0 | } |
4183 | 33.3k | } // end switch (Kind) |
4184 | 33.3k | |
4185 | 33.3k | if (Operand.isReg()) { |
4186 | 251 | MatchClassKind OpKind; |
4187 | 251 | switch (Operand.getReg()) { |
4188 | 251 | default: OpKind = InvalidMatchClass; break0 ; |
4189 | 251 | case Mips::ZERO: OpKind = MCK_GPR32ZERO; break; |
4190 | 251 | case Mips::AT: OpKind = MCK_GPR32NONZERO; break0 ; |
4191 | 251 | case Mips::V0: OpKind = MCK_Reg11; break0 ; |
4192 | 251 | case Mips::V1: OpKind = MCK_Reg11; break0 ; |
4193 | 251 | case Mips::A0: OpKind = MCK_GPRMM16MovePPairFirst; break0 ; |
4194 | 251 | case Mips::A1: OpKind = MCK_Reg13; break0 ; |
4195 | 251 | case Mips::A2: OpKind = MCK_Reg13; break0 ; |
4196 | 251 | case Mips::A3: OpKind = MCK_Reg14; break0 ; |
4197 | 251 | case Mips::T0: OpKind = MCK_GPR32NONZERO; break0 ; |
4198 | 251 | case Mips::T1: OpKind = MCK_GPR32NONZERO; break0 ; |
4199 | 251 | case Mips::T2: OpKind = MCK_GPR32NONZERO; break0 ; |
4200 | 251 | case Mips::T3: OpKind = MCK_GPR32NONZERO; break0 ; |
4201 | 251 | case Mips::T4: OpKind = MCK_GPR32NONZERO; break0 ; |
4202 | 251 | case Mips::T5: OpKind = MCK_GPR32NONZERO; break0 ; |
4203 | 251 | case Mips::T6: OpKind = MCK_GPR32NONZERO; break0 ; |
4204 | 251 | case Mips::T7: OpKind = MCK_GPR32NONZERO; break0 ; |
4205 | 251 | case Mips::S0: OpKind = MCK_Reg9; break0 ; |
4206 | 251 | case Mips::S1: OpKind = MCK_Reg11; break0 ; |
4207 | 251 | case Mips::S2: OpKind = MCK_Reg10; break0 ; |
4208 | 251 | case Mips::S3: OpKind = MCK_Reg10; break0 ; |
4209 | 251 | case Mips::S4: OpKind = MCK_Reg10; break0 ; |
4210 | 251 | case Mips::S5: OpKind = MCK_GPRMM16MovePPairSecond; break0 ; |
4211 | 251 | case Mips::S6: OpKind = MCK_GPRMM16MovePPairSecond; break0 ; |
4212 | 251 | case Mips::S7: OpKind = MCK_GPR32NONZERO; break0 ; |
4213 | 251 | case Mips::T8: OpKind = MCK_GPR32NONZERO; break0 ; |
4214 | 251 | case Mips::T9: OpKind = MCK_GPR32NONZERO; break0 ; |
4215 | 251 | case Mips::K0: OpKind = MCK_GPR32NONZERO; break0 ; |
4216 | 251 | case Mips::K1: OpKind = MCK_GPR32NONZERO; break0 ; |
4217 | 251 | case Mips::GP: OpKind = MCK_GP32; break0 ; |
4218 | 251 | case Mips::SP: OpKind = MCK_CPUSPReg; break0 ; |
4219 | 251 | case Mips::FP: OpKind = MCK_GPR32NONZERO; break0 ; |
4220 | 251 | case Mips::RA: OpKind = MCK_CPURAReg; break0 ; |
4221 | 251 | case Mips::ZERO_64: OpKind = MCK_Reg19; break0 ; |
4222 | 251 | case Mips::AT_64: OpKind = MCK_Reg24; break0 ; |
4223 | 251 | case Mips::V0_64: OpKind = MCK_Reg30; break0 ; |
4224 | 251 | case Mips::V1_64: OpKind = MCK_Reg30; break0 ; |
4225 | 251 | case Mips::A0_64: OpKind = MCK_Reg31; break0 ; |
4226 | 251 | case Mips::A1_64: OpKind = MCK_Reg32; break0 ; |
4227 | 251 | case Mips::A2_64: OpKind = MCK_Reg32; break0 ; |
4228 | 251 | case Mips::A3_64: OpKind = MCK_Reg33; break0 ; |
4229 | 251 | case Mips::T0_64: OpKind = MCK_Reg24; break0 ; |
4230 | 251 | case Mips::T1_64: OpKind = MCK_Reg24; break0 ; |
4231 | 251 | case Mips::T2_64: OpKind = MCK_Reg24; break0 ; |
4232 | 251 | case Mips::T3_64: OpKind = MCK_Reg24; break0 ; |
4233 | 251 | case Mips::T4_64: OpKind = MCK_Reg24; break0 ; |
4234 | 251 | case Mips::T5_64: OpKind = MCK_Reg24; break0 ; |
4235 | 251 | case Mips::T6_64: OpKind = MCK_Reg24; break0 ; |
4236 | 251 | case Mips::T7_64: OpKind = MCK_Reg24; break0 ; |
4237 | 251 | case Mips::S0_64: OpKind = MCK_Reg28; break0 ; |
4238 | 251 | case Mips::S1_64: OpKind = MCK_Reg30; break0 ; |
4239 | 251 | case Mips::S2_64: OpKind = MCK_Reg29; break0 ; |
4240 | 251 | case Mips::S3_64: OpKind = MCK_Reg29; break0 ; |
4241 | 251 | case Mips::S4_64: OpKind = MCK_Reg29; break0 ; |
4242 | 251 | case Mips::S5_64: OpKind = MCK_Reg34; break0 ; |
4243 | 251 | case Mips::S6_64: OpKind = MCK_Reg34; break0 ; |
4244 | 251 | case Mips::S7_64: OpKind = MCK_Reg24; break0 ; |
4245 | 251 | case Mips::T8_64: OpKind = MCK_Reg24; break0 ; |
4246 | 251 | case Mips::T9_64: OpKind = MCK_Reg24; break0 ; |
4247 | 251 | case Mips::K0_64: OpKind = MCK_Reg24; break0 ; |
4248 | 251 | case Mips::K1_64: OpKind = MCK_Reg24; break0 ; |
4249 | 251 | case Mips::GP_64: OpKind = MCK_GP64; break0 ; |
4250 | 251 | case Mips::SP_64: OpKind = MCK_SP64; break0 ; |
4251 | 251 | case Mips::FP_64: OpKind = MCK_Reg24; break0 ; |
4252 | 251 | case Mips::RA_64: OpKind = MCK_Reg37; break0 ; |
4253 | 251 | case Mips::F0: OpKind = MCK_FGR32; break0 ; |
4254 | 251 | case Mips::F1: OpKind = MCK_FGR32; break0 ; |
4255 | 251 | case Mips::F2: OpKind = MCK_FGR32; break0 ; |
4256 | 251 | case Mips::F3: OpKind = MCK_FGR32; break0 ; |
4257 | 251 | case Mips::F4: OpKind = MCK_FGR32; break0 ; |
4258 | 251 | case Mips::F5: OpKind = MCK_FGR32; break0 ; |
4259 | 251 | case Mips::F6: OpKind = MCK_FGR32; break0 ; |
4260 | 251 | case Mips::F7: OpKind = MCK_FGR32; break0 ; |
4261 | 251 | case Mips::F8: OpKind = MCK_FGR32; break0 ; |
4262 | 251 | case Mips::F9: OpKind = MCK_FGR32; break0 ; |
4263 | 251 | case Mips::F10: OpKind = MCK_FGR32; break0 ; |
4264 | 251 | case Mips::F11: OpKind = MCK_FGR32; break0 ; |
4265 | 251 | case Mips::F12: OpKind = MCK_FGR32; break0 ; |
4266 | 251 | case Mips::F13: OpKind = MCK_FGR32; break0 ; |
4267 | 251 | case Mips::F14: OpKind = MCK_FGR32; break0 ; |
4268 | 251 | case Mips::F15: OpKind = MCK_FGR32; break0 ; |
4269 | 251 | case Mips::F16: OpKind = MCK_FGR32; break0 ; |
4270 | 251 | case Mips::F17: OpKind = MCK_FGR32; break0 ; |
4271 | 251 | case Mips::F18: OpKind = MCK_FGR32; break0 ; |
4272 | 251 | case Mips::F19: OpKind = MCK_FGR32; break0 ; |
4273 | 251 | case Mips::F20: OpKind = MCK_FGR32; break0 ; |
4274 | 251 | case Mips::F21: OpKind = MCK_FGR32; break0 ; |
4275 | 251 | case Mips::F22: OpKind = MCK_FGR32; break0 ; |
4276 | 251 | case Mips::F23: OpKind = MCK_FGR32; break0 ; |
4277 | 251 | case Mips::F24: OpKind = MCK_FGR32; break0 ; |
4278 | 251 | case Mips::F25: OpKind = MCK_FGR32; break0 ; |
4279 | 251 | case Mips::F26: OpKind = MCK_FGR32; break0 ; |
4280 | 251 | case Mips::F27: OpKind = MCK_FGR32; break0 ; |
4281 | 251 | case Mips::F28: OpKind = MCK_FGR32; break0 ; |
4282 | 251 | case Mips::F29: OpKind = MCK_FGR32; break0 ; |
4283 | 251 | case Mips::F30: OpKind = MCK_FGR32; break0 ; |
4284 | 251 | case Mips::F31: OpKind = MCK_FGR32; break0 ; |
4285 | 251 | case Mips::D0: OpKind = MCK_AFGR64; break0 ; |
4286 | 251 | case Mips::D1: OpKind = MCK_AFGR64; break0 ; |
4287 | 251 | case Mips::D2: OpKind = MCK_AFGR64; break0 ; |
4288 | 251 | case Mips::D3: OpKind = MCK_AFGR64; break0 ; |
4289 | 251 | case Mips::D4: OpKind = MCK_AFGR64; break0 ; |
4290 | 251 | case Mips::D5: OpKind = MCK_AFGR64; break0 ; |
4291 | 251 | case Mips::D6: OpKind = MCK_AFGR64; break0 ; |
4292 | 251 | case Mips::D7: OpKind = MCK_AFGR64; break0 ; |
4293 | 251 | case Mips::D8: OpKind = MCK_AFGR64; break0 ; |
4294 | 251 | case Mips::D9: OpKind = MCK_AFGR64; break0 ; |
4295 | 251 | case Mips::D10: OpKind = MCK_AFGR64; break0 ; |
4296 | 251 | case Mips::D11: OpKind = MCK_AFGR64; break0 ; |
4297 | 251 | case Mips::D12: OpKind = MCK_AFGR64; break0 ; |
4298 | 251 | case Mips::D13: OpKind = MCK_AFGR64; break0 ; |
4299 | 251 | case Mips::D14: OpKind = MCK_AFGR64; break0 ; |
4300 | 251 | case Mips::D15: OpKind = MCK_AFGR64; break0 ; |
4301 | 251 | case Mips::D0_64: OpKind = MCK_FGR64; break0 ; |
4302 | 251 | case Mips::D1_64: OpKind = MCK_FGR64; break0 ; |
4303 | 251 | case Mips::D2_64: OpKind = MCK_FGR64; break0 ; |
4304 | 251 | case Mips::D3_64: OpKind = MCK_FGR64; break0 ; |
4305 | 251 | case Mips::D4_64: OpKind = MCK_FGR64; break0 ; |
4306 | 251 | case Mips::D5_64: OpKind = MCK_FGR64; break0 ; |
4307 | 251 | case Mips::D6_64: OpKind = MCK_FGR64; break0 ; |
4308 | 251 | case Mips::D7_64: OpKind = MCK_FGR64; break0 ; |
4309 | 251 | case Mips::D8_64: OpKind = MCK_FGR64; break0 ; |
4310 | 251 | case Mips::D9_64: OpKind = MCK_FGR64; break0 ; |
4311 | 251 | case Mips::D10_64: OpKind = MCK_FGR64; break0 ; |
4312 | 251 | case Mips::D11_64: OpKind = MCK_FGR64; break0 ; |
4313 | 251 | case Mips::D12_64: OpKind = MCK_FGR64; break0 ; |
4314 | 251 | case Mips::D13_64: OpKind = MCK_FGR64; break0 ; |
4315 | 251 | case Mips::D14_64: OpKind = MCK_FGR64; break0 ; |
4316 | 251 | case Mips::D15_64: OpKind = MCK_FGR64; break0 ; |
4317 | 251 | case Mips::D16_64: OpKind = MCK_FGR64; break0 ; |
4318 | 251 | case Mips::D17_64: OpKind = MCK_FGR64; break0 ; |
4319 | 251 | case Mips::D18_64: OpKind = MCK_FGR64; break0 ; |
4320 | 251 | case Mips::D19_64: OpKind = MCK_FGR64; break0 ; |
4321 | 251 | case Mips::D20_64: OpKind = MCK_FGR64; break0 ; |
4322 | 251 | case Mips::D21_64: OpKind = MCK_FGR64; break0 ; |
4323 | 251 | case Mips::D22_64: OpKind = MCK_FGR64; break0 ; |
4324 | 251 | case Mips::D23_64: OpKind = MCK_FGR64; break0 ; |
4325 | 251 | case Mips::D24_64: OpKind = MCK_FGR64; break0 ; |
4326 | 251 | case Mips::D25_64: OpKind = MCK_FGR64; break0 ; |
4327 | 251 | case Mips::D26_64: OpKind = MCK_FGR64; break0 ; |
4328 | 251 | case Mips::D27_64: OpKind = MCK_FGR64; break0 ; |
4329 | 251 | case Mips::D28_64: OpKind = MCK_FGR64; break0 ; |
4330 | 251 | case Mips::D29_64: OpKind = MCK_FGR64; break0 ; |
4331 | 251 | case Mips::D30_64: OpKind = MCK_FGR64; break0 ; |
4332 | 251 | case Mips::D31_64: OpKind = MCK_FGR64; break0 ; |
4333 | 251 | case Mips::W0: OpKind = MCK_MSA128WEvens; break0 ; |
4334 | 251 | case Mips::W1: OpKind = MCK_MSA128F16; break0 ; |
4335 | 251 | case Mips::W2: OpKind = MCK_MSA128WEvens; break0 ; |
4336 | 251 | case Mips::W3: OpKind = MCK_MSA128F16; break0 ; |
4337 | 251 | case Mips::W4: OpKind = MCK_MSA128WEvens; break0 ; |
4338 | 251 | case Mips::W5: OpKind = MCK_MSA128F16; break0 ; |
4339 | 251 | case Mips::W6: OpKind = MCK_MSA128WEvens; break0 ; |
4340 | 251 | case Mips::W7: OpKind = MCK_MSA128F16; break0 ; |
4341 | 251 | case Mips::W8: OpKind = MCK_MSA128WEvens; break0 ; |
4342 | 251 | case Mips::W9: OpKind = MCK_MSA128F16; break0 ; |
4343 | 251 | case Mips::W10: OpKind = MCK_MSA128WEvens; break0 ; |
4344 | 251 | case Mips::W11: OpKind = MCK_MSA128F16; break0 ; |
4345 | 251 | case Mips::W12: OpKind = MCK_MSA128WEvens; break0 ; |
4346 | 251 | case Mips::W13: OpKind = MCK_MSA128F16; break0 ; |
4347 | 251 | case Mips::W14: OpKind = MCK_MSA128WEvens; break0 ; |
4348 | 251 | case Mips::W15: OpKind = MCK_MSA128F16; break0 ; |
4349 | 251 | case Mips::W16: OpKind = MCK_MSA128WEvens; break0 ; |
4350 | 251 | case Mips::W17: OpKind = MCK_MSA128F16; break0 ; |
4351 | 251 | case Mips::W18: OpKind = MCK_MSA128WEvens; break0 ; |
4352 | 251 | case Mips::W19: OpKind = MCK_MSA128F16; break0 ; |
4353 | 251 | case Mips::W20: OpKind = MCK_MSA128WEvens; break0 ; |
4354 | 251 | case Mips::W21: OpKind = MCK_MSA128F16; break0 ; |
4355 | 251 | case Mips::W22: OpKind = MCK_MSA128WEvens; break0 ; |
4356 | 251 | case Mips::W23: OpKind = MCK_MSA128F16; break0 ; |
4357 | 251 | case Mips::W24: OpKind = MCK_MSA128WEvens; break0 ; |
4358 | 251 | case Mips::W25: OpKind = MCK_MSA128F16; break0 ; |
4359 | 251 | case Mips::W26: OpKind = MCK_MSA128WEvens; break0 ; |
4360 | 251 | case Mips::W27: OpKind = MCK_MSA128F16; break0 ; |
4361 | 251 | case Mips::W28: OpKind = MCK_MSA128WEvens; break0 ; |
4362 | 251 | case Mips::W29: OpKind = MCK_MSA128F16; break0 ; |
4363 | 251 | case Mips::W30: OpKind = MCK_MSA128WEvens; break0 ; |
4364 | 251 | case Mips::W31: OpKind = MCK_MSA128F16; break0 ; |
4365 | 251 | case Mips::HI0: OpKind = MCK_HI32; break0 ; |
4366 | 251 | case Mips::HI1: OpKind = MCK_HI32DSP; break0 ; |
4367 | 251 | case Mips::HI2: OpKind = MCK_HI32DSP; break0 ; |
4368 | 251 | case Mips::HI3: OpKind = MCK_HI32DSP; break0 ; |
4369 | 251 | case Mips::LO0: OpKind = MCK_LO32; break0 ; |
4370 | 251 | case Mips::LO1: OpKind = MCK_LO32DSP; break0 ; |
4371 | 251 | case Mips::LO2: OpKind = MCK_LO32DSP; break0 ; |
4372 | 251 | case Mips::LO3: OpKind = MCK_LO32DSP; break0 ; |
4373 | 251 | case Mips::HI0_64: OpKind = MCK_HI64; break0 ; |
4374 | 251 | case Mips::LO0_64: OpKind = MCK_LO64; break0 ; |
4375 | 251 | case Mips::FCR0: OpKind = MCK_CCR; break0 ; |
4376 | 251 | case Mips::FCR1: OpKind = MCK_CCR; break0 ; |
4377 | 251 | case Mips::FCR2: OpKind = MCK_CCR; break0 ; |
4378 | 251 | case Mips::FCR3: OpKind = MCK_CCR; break0 ; |
4379 | 251 | case Mips::FCR4: OpKind = MCK_CCR; break0 ; |
4380 | 251 | case Mips::FCR5: OpKind = MCK_CCR; break0 ; |
4381 | 251 | case Mips::FCR6: OpKind = MCK_CCR; break0 ; |
4382 | 251 | case Mips::FCR7: OpKind = MCK_CCR; break0 ; |
4383 | 251 | case Mips::FCR8: OpKind = MCK_CCR; break0 ; |
4384 | 251 | case Mips::FCR9: OpKind = MCK_CCR; break0 ; |
4385 | 251 | case Mips::FCR10: OpKind = MCK_CCR; break0 ; |
4386 | 251 | case Mips::FCR11: OpKind = MCK_CCR; break0 ; |
4387 | 251 | case Mips::FCR12: OpKind = MCK_CCR; break0 ; |
4388 | 251 | case Mips::FCR13: OpKind = MCK_CCR; break0 ; |
4389 | 251 | case Mips::FCR14: OpKind = MCK_CCR; break0 ; |
4390 | 251 | case Mips::FCR15: OpKind = MCK_CCR; break0 ; |
4391 | 251 | case Mips::FCR16: OpKind = MCK_CCR; break0 ; |
4392 | 251 | case Mips::FCR17: OpKind = MCK_CCR; break0 ; |
4393 | 251 | case Mips::FCR18: OpKind = MCK_CCR; break0 ; |
4394 | 251 | case Mips::FCR19: OpKind = MCK_CCR; break0 ; |
4395 | 251 | case Mips::FCR20: OpKind = MCK_CCR; break0 ; |
4396 | 251 | case Mips::FCR21: OpKind = MCK_CCR; break0 ; |
4397 | 251 | case Mips::FCR22: OpKind = MCK_CCR; break0 ; |
4398 | 251 | case Mips::FCR23: OpKind = MCK_CCR; break0 ; |
4399 | 251 | case Mips::FCR24: OpKind = MCK_CCR; break0 ; |
4400 | 251 | case Mips::FCR25: OpKind = MCK_CCR; break0 ; |
4401 | 251 | case Mips::FCR26: OpKind = MCK_CCR; break0 ; |
4402 | 251 | case Mips::FCR27: OpKind = MCK_CCR; break0 ; |
4403 | 251 | case Mips::FCR28: OpKind = MCK_CCR; break0 ; |
4404 | 251 | case Mips::FCR29: OpKind = MCK_CCR; break0 ; |
4405 | 251 | case Mips::FCR30: OpKind = MCK_CCR; break0 ; |
4406 | 251 | case Mips::FCR31: OpKind = MCK_CCR; break0 ; |
4407 | 251 | case Mips::FCC0: OpKind = MCK_FCC; break0 ; |
4408 | 251 | case Mips::FCC1: OpKind = MCK_FCC; break0 ; |
4409 | 251 | case Mips::FCC2: OpKind = MCK_FCC; break0 ; |
4410 | 251 | case Mips::FCC3: OpKind = MCK_FCC; break0 ; |
4411 | 251 | case Mips::FCC4: OpKind = MCK_FCC; break0 ; |
4412 | 251 | case Mips::FCC5: OpKind = MCK_FCC; break0 ; |
4413 | 251 | case Mips::FCC6: OpKind = MCK_FCC; break0 ; |
4414 | 251 | case Mips::FCC7: OpKind = MCK_FCC; break0 ; |
4415 | 251 | case Mips::COP00: OpKind = MCK_COP0; break0 ; |
4416 | 251 | case Mips::COP01: OpKind = MCK_COP0; break0 ; |
4417 | 251 | case Mips::COP02: OpKind = MCK_COP0; break0 ; |
4418 | 251 | case Mips::COP03: OpKind = MCK_COP0; break0 ; |
4419 | 251 | case Mips::COP04: OpKind = MCK_COP0; break0 ; |
4420 | 251 | case Mips::COP05: OpKind = MCK_COP0; break0 ; |
4421 | 251 | case Mips::COP06: OpKind = MCK_COP0; break0 ; |
4422 | 251 | case Mips::COP07: OpKind = MCK_COP0; break0 ; |
4423 | 251 | case Mips::COP08: OpKind = MCK_COP0; break0 ; |
4424 | 251 | case Mips::COP09: OpKind = MCK_COP0; break0 ; |
4425 | 251 | case Mips::COP010: OpKind = MCK_COP0; break0 ; |
4426 | 251 | case Mips::COP011: OpKind = MCK_COP0; break0 ; |
4427 | 251 | case Mips::COP012: OpKind = MCK_COP0; break0 ; |
4428 | 251 | case Mips::COP013: OpKind = MCK_COP0; break0 ; |
4429 | 251 | case Mips::COP014: OpKind = MCK_COP0; break0 ; |
4430 | 251 | case Mips::COP015: OpKind = MCK_COP0; break0 ; |
4431 | 251 | case Mips::COP016: OpKind = MCK_COP0; break0 ; |
4432 | 251 | case Mips::COP017: OpKind = MCK_COP0; break0 ; |
4433 | 251 | case Mips::COP018: OpKind = MCK_COP0; break0 ; |
4434 | 251 | case Mips::COP019: OpKind = MCK_COP0; break0 ; |
4435 | 251 | case Mips::COP020: OpKind = MCK_COP0; break0 ; |
4436 | 251 | case Mips::COP021: OpKind = MCK_COP0; break0 ; |
4437 | 251 | case Mips::COP022: OpKind = MCK_COP0; break0 ; |
4438 | 251 | case Mips::COP023: OpKind = MCK_COP0; break0 ; |
4439 | 251 | case Mips::COP024: OpKind = MCK_COP0; break0 ; |
4440 | 251 | case Mips::COP025: OpKind = MCK_COP0; break0 ; |
4441 | 251 | case Mips::COP026: OpKind = MCK_COP0; break0 ; |
4442 | 251 | case Mips::COP027: OpKind = MCK_COP0; break0 ; |
4443 | 251 | case Mips::COP028: OpKind = MCK_COP0; break0 ; |
4444 | 251 | case Mips::COP029: OpKind = MCK_COP0; break0 ; |
4445 | 251 | case Mips::COP030: OpKind = MCK_COP0; break0 ; |
4446 | 251 | case Mips::COP031: OpKind = MCK_COP0; break0 ; |
4447 | 251 | case Mips::COP20: OpKind = MCK_COP2; break0 ; |
4448 | 251 | case Mips::COP21: OpKind = MCK_COP2; break0 ; |
4449 | 251 | case Mips::COP22: OpKind = MCK_COP2; break0 ; |
4450 | 251 | case Mips::COP23: OpKind = MCK_COP2; break0 ; |
4451 | 251 | case Mips::COP24: OpKind = MCK_COP2; break0 ; |
4452 | 251 | case Mips::COP25: OpKind = MCK_COP2; break0 ; |
4453 | 251 | case Mips::COP26: OpKind = MCK_COP2; break0 ; |
4454 | 251 | case Mips::COP27: OpKind = MCK_COP2; break0 ; |
4455 | 251 | case Mips::COP28: OpKind = MCK_COP2; break0 ; |
4456 | 251 | case Mips::COP29: OpKind = MCK_COP2; break0 ; |
4457 | 251 | case Mips::COP210: OpKind = MCK_COP2; break0 ; |
4458 | 251 | case Mips::COP211: OpKind = MCK_COP2; break0 ; |
4459 | 251 | case Mips::COP212: OpKind = MCK_COP2; break0 ; |
4460 | 251 | case Mips::COP213: OpKind = MCK_COP2; break0 ; |
4461 | 251 | case Mips::COP214: OpKind = MCK_COP2; break0 ; |
4462 | 251 | case Mips::COP215: OpKind = MCK_COP2; break0 ; |
4463 | 251 | case Mips::COP216: OpKind = MCK_COP2; break0 ; |
4464 | 251 | case Mips::COP217: OpKind = MCK_COP2; break0 ; |
4465 | 251 | case Mips::COP218: OpKind = MCK_COP2; break0 ; |
4466 | 251 | case Mips::COP219: OpKind = MCK_COP2; break0 ; |
4467 | 251 | case Mips::COP220: OpKind = MCK_COP2; break0 ; |
4468 | 251 | case Mips::COP221: OpKind = MCK_COP2; break0 ; |
4469 | 251 | case Mips::COP222: OpKind = MCK_COP2; break0 ; |
4470 | 251 | case Mips::COP223: OpKind = MCK_COP2; break0 ; |
4471 | 251 | case Mips::COP224: OpKind = MCK_COP2; break0 ; |
4472 | 251 | case Mips::COP225: OpKind = MCK_COP2; break0 ; |
4473 | 251 | case Mips::COP226: OpKind = MCK_COP2; break0 ; |
4474 | 251 | case Mips::COP227: OpKind = MCK_COP2; break0 ; |
4475 | 251 | case Mips::COP228: OpKind = MCK_COP2; break0 ; |
4476 | 251 | case Mips::COP229: OpKind = MCK_COP2; break0 ; |
4477 | 251 | case Mips::COP230: OpKind = MCK_COP2; break0 ; |
4478 | 251 | case Mips::COP231: OpKind = MCK_COP2; break0 ; |
4479 | 251 | case Mips::COP30: OpKind = MCK_COP3; break0 ; |
4480 | 251 | case Mips::COP31: OpKind = MCK_COP3; break0 ; |
4481 | 251 | case Mips::COP32: OpKind = MCK_COP3; break0 ; |
4482 | 251 | case Mips::COP33: OpKind = MCK_COP3; break0 ; |
4483 | 251 | case Mips::COP34: OpKind = MCK_COP3; break0 ; |
4484 | 251 | case Mips::COP35: OpKind = MCK_COP3; break0 ; |
4485 | 251 | case Mips::COP36: OpKind = MCK_COP3; break0 ; |
4486 | 251 | case Mips::COP37: OpKind = MCK_COP3; break0 ; |
4487 | 251 | case Mips::COP38: OpKind = MCK_COP3; break0 ; |
4488 | 251 | case Mips::COP39: OpKind = MCK_COP3; break0 ; |
4489 | 251 | case Mips::COP310: OpKind = MCK_COP3; break0 ; |
4490 | 251 | case Mips::COP311: OpKind = MCK_COP3; break0 ; |
4491 | 251 | case Mips::COP312: OpKind = MCK_COP3; break0 ; |
4492 | 251 | case Mips::COP313: OpKind = MCK_COP3; break0 ; |
4493 | 251 | case Mips::COP314: OpKind = MCK_COP3; break0 ; |
4494 | 251 | case Mips::COP315: OpKind = MCK_COP3; break0 ; |
4495 | 251 | case Mips::COP316: OpKind = MCK_COP3; break0 ; |
4496 | 251 | case Mips::COP317: OpKind = MCK_COP3; break0 ; |
4497 | 251 | case Mips::COP318: OpKind = MCK_COP3; break0 ; |
4498 | 251 | case Mips::COP319: OpKind = MCK_COP3; break0 ; |
4499 | 251 | case Mips::COP320: OpKind = MCK_COP3; break0 ; |
4500 | 251 | case Mips::COP321: OpKind = MCK_COP3; break0 ; |
4501 | 251 | case Mips::COP322: OpKind = MCK_COP3; break0 ; |
4502 | 251 | case Mips::COP323: OpKind = MCK_COP3; break0 ; |
4503 | 251 | case Mips::COP324: OpKind = MCK_COP3; break0 ; |
4504 | 251 | case Mips::COP325: OpKind = MCK_COP3; break0 ; |
4505 | 251 | case Mips::COP326: OpKind = MCK_COP3; break0 ; |
4506 | 251 | case Mips::COP327: OpKind = MCK_COP3; break0 ; |
4507 | 251 | case Mips::COP328: OpKind = MCK_COP3; break0 ; |
4508 | 251 | case Mips::COP329: OpKind = MCK_COP3; break0 ; |
4509 | 251 | case Mips::COP330: OpKind = MCK_COP3; break0 ; |
4510 | 251 | case Mips::COP331: OpKind = MCK_COP3; break0 ; |
4511 | 251 | case Mips::PC: OpKind = MCK_PC; break0 ; |
4512 | 251 | case Mips::HWR0: OpKind = MCK_HWRegs; break0 ; |
4513 | 251 | case Mips::HWR1: OpKind = MCK_HWRegs; break0 ; |
4514 | 251 | case Mips::HWR2: OpKind = MCK_HWRegs; break0 ; |
4515 | 251 | case Mips::HWR3: OpKind = MCK_HWRegs; break0 ; |
4516 | 251 | case Mips::HWR4: OpKind = MCK_HWRegs; break0 ; |
4517 | 251 | case Mips::HWR5: OpKind = MCK_HWRegs; break0 ; |
4518 | 251 | case Mips::HWR6: OpKind = MCK_HWRegs; break0 ; |
4519 | 251 | case Mips::HWR7: OpKind = MCK_HWRegs; break0 ; |
4520 | 251 | case Mips::HWR8: OpKind = MCK_HWRegs; break0 ; |
4521 | 251 | case Mips::HWR9: OpKind = MCK_HWRegs; break0 ; |
4522 | 251 | case Mips::HWR10: OpKind = MCK_HWRegs; break0 ; |
4523 | 251 | case Mips::HWR11: OpKind = MCK_HWRegs; break0 ; |
4524 | 251 | case Mips::HWR12: OpKind = MCK_HWRegs; break0 ; |
4525 | 251 | case Mips::HWR13: OpKind = MCK_HWRegs; break0 ; |
4526 | 251 | case Mips::HWR14: OpKind = MCK_HWRegs; break0 ; |
4527 | 251 | case Mips::HWR15: OpKind = MCK_HWRegs; break0 ; |
4528 | 251 | case Mips::HWR16: OpKind = MCK_HWRegs; break0 ; |
4529 | 251 | case Mips::HWR17: OpKind = MCK_HWRegs; break0 ; |
4530 | 251 | case Mips::HWR18: OpKind = MCK_HWRegs; break0 ; |
4531 | 251 | case Mips::HWR19: OpKind = MCK_HWRegs; break0 ; |
4532 | 251 | case Mips::HWR20: OpKind = MCK_HWRegs; break0 ; |
4533 | 251 | case Mips::HWR21: OpKind = MCK_HWRegs; break0 ; |
4534 | 251 | case Mips::HWR22: OpKind = MCK_HWRegs; break0 ; |
4535 | 251 | case Mips::HWR23: OpKind = MCK_HWRegs; break0 ; |
4536 | 251 | case Mips::HWR24: OpKind = MCK_HWRegs; break0 ; |
4537 | 251 | case Mips::HWR25: OpKind = MCK_HWRegs; break0 ; |
4538 | 251 | case Mips::HWR26: OpKind = MCK_HWRegs; break0 ; |
4539 | 251 | case Mips::HWR27: OpKind = MCK_HWRegs; break0 ; |
4540 | 251 | case Mips::HWR28: OpKind = MCK_HWRegs; break0 ; |
4541 | 251 | case Mips::HWR29: OpKind = MCK_HWRegs; break0 ; |
4542 | 251 | case Mips::HWR30: OpKind = MCK_HWRegs; break0 ; |
4543 | 251 | case Mips::HWR31: OpKind = MCK_HWRegs; break0 ; |
4544 | 251 | case Mips::AC0: OpKind = MCK_ACC64; break0 ; |
4545 | 251 | case Mips::AC1: OpKind = MCK_ACC64DSP; break0 ; |
4546 | 251 | case Mips::AC2: OpKind = MCK_ACC64DSP; break0 ; |
4547 | 251 | case Mips::AC3: OpKind = MCK_ACC64DSP; break0 ; |
4548 | 251 | case Mips::AC0_64: OpKind = MCK_ACC128; break0 ; |
4549 | 251 | case Mips::DSPCCond: OpKind = MCK_DSPCC; break0 ; |
4550 | 251 | case Mips::MSAIR: OpKind = MCK_MSACtrl; break0 ; |
4551 | 251 | case Mips::MSACSR: OpKind = MCK_MSACtrl; break0 ; |
4552 | 251 | case Mips::MSAAccess: OpKind = MCK_MSACtrl; break0 ; |
4553 | 251 | case Mips::MSASave: OpKind = MCK_MSACtrl; break0 ; |
4554 | 251 | case Mips::MSAModify: OpKind = MCK_MSACtrl; break0 ; |
4555 | 251 | case Mips::MSARequest: OpKind = MCK_MSACtrl; break0 ; |
4556 | 251 | case Mips::MSAMap: OpKind = MCK_MSACtrl; break0 ; |
4557 | 251 | case Mips::MSAUnmap: OpKind = MCK_MSACtrl; break0 ; |
4558 | 251 | case Mips::MSA8: OpKind = MCK_MSACtrl; break0 ; |
4559 | 251 | case Mips::MSA9: OpKind = MCK_MSACtrl; break0 ; |
4560 | 251 | case Mips::MSA10: OpKind = MCK_MSACtrl; break0 ; |
4561 | 251 | case Mips::MSA11: OpKind = MCK_MSACtrl; break0 ; |
4562 | 251 | case Mips::MSA12: OpKind = MCK_MSACtrl; break0 ; |
4563 | 251 | case Mips::MSA13: OpKind = MCK_MSACtrl; break0 ; |
4564 | 251 | case Mips::MSA14: OpKind = MCK_MSACtrl; break0 ; |
4565 | 251 | case Mips::MSA15: OpKind = MCK_MSACtrl; break0 ; |
4566 | 251 | case Mips::MSA16: OpKind = MCK_MSACtrl; break0 ; |
4567 | 251 | case Mips::MSA17: OpKind = MCK_MSACtrl; break0 ; |
4568 | 251 | case Mips::MSA18: OpKind = MCK_MSACtrl; break0 ; |
4569 | 251 | case Mips::MSA19: OpKind = MCK_MSACtrl; break0 ; |
4570 | 251 | case Mips::MSA20: OpKind = MCK_MSACtrl; break0 ; |
4571 | 251 | case Mips::MSA21: OpKind = MCK_MSACtrl; break0 ; |
4572 | 251 | case Mips::MSA22: OpKind = MCK_MSACtrl; break0 ; |
4573 | 251 | case Mips::MSA23: OpKind = MCK_MSACtrl; break0 ; |
4574 | 251 | case Mips::MSA24: OpKind = MCK_MSACtrl; break0 ; |
4575 | 251 | case Mips::MSA25: OpKind = MCK_MSACtrl; break0 ; |
4576 | 251 | case Mips::MSA26: OpKind = MCK_MSACtrl; break0 ; |
4577 | 251 | case Mips::MSA27: OpKind = MCK_MSACtrl; break0 ; |
4578 | 251 | case Mips::MSA28: OpKind = MCK_MSACtrl; break0 ; |
4579 | 251 | case Mips::MSA29: OpKind = MCK_MSACtrl; break0 ; |
4580 | 251 | case Mips::MSA30: OpKind = MCK_MSACtrl; break0 ; |
4581 | 251 | case Mips::MSA31: OpKind = MCK_MSACtrl; break0 ; |
4582 | 251 | case Mips::MPL0: OpKind = MCK_OCTEON_MPL; break0 ; |
4583 | 251 | case Mips::MPL1: OpKind = MCK_OCTEON_MPL; break0 ; |
4584 | 251 | case Mips::MPL2: OpKind = MCK_OCTEON_MPL; break0 ; |
4585 | 251 | case Mips::P0: OpKind = MCK_OCTEON_P; break0 ; |
4586 | 251 | case Mips::P1: OpKind = MCK_OCTEON_P; break0 ; |
4587 | 251 | case Mips::P2: OpKind = MCK_OCTEON_P; break0 ; |
4588 | 251 | } |
4589 | 251 | return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success120 : |
4590 | 251 | getDiagKindFromRegisterClass(Kind)131 ; |
4591 | 251 | } |
4592 | 33.1k | |
4593 | 33.1k | if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER33.0k ) |
4594 | 14.3k | return getDiagKindFromRegisterClass(Kind); |
4595 | 18.7k | |
4596 | 18.7k | return MCTargetAsmParser::Match_InvalidOperand; |
4597 | 18.7k | } |
4598 | | |
4599 | | #ifndef NDEBUG |
4600 | | const char *getMatchClassName(MatchClassKind Kind) { |
4601 | | switch (Kind) { |
4602 | | case InvalidMatchClass: return "InvalidMatchClass"; |
4603 | | case OptionalMatchClass: return "OptionalMatchClass"; |
4604 | | case MCK__35_: return "MCK__35_"; |
4605 | | case MCK__40_: return "MCK__40_"; |
4606 | | case MCK__41_: return "MCK__41_"; |
4607 | | case MCK_0: return "MCK_0"; |
4608 | | case MCK_16: return "MCK_16"; |
4609 | | case MCK__91_: return "MCK__91_"; |
4610 | | case MCK__93_: return "MCK__93_"; |
4611 | | case MCK_bit: return "MCK_bit"; |
4612 | | case MCK_inst: return "MCK_inst"; |
4613 | | case MCK_Reg37: return "MCK_Reg37"; |
4614 | | case MCK_Reg19: return "MCK_Reg19"; |
4615 | | case MCK_ACC128: return "MCK_ACC128"; |
4616 | | case MCK_ACC64: return "MCK_ACC64"; |
4617 | | case MCK_CPURAReg: return "MCK_CPURAReg"; |
4618 | | case MCK_CPUSPReg: return "MCK_CPUSPReg"; |
4619 | | case MCK_DSPCC: return "MCK_DSPCC"; |
4620 | | case MCK_GP32: return "MCK_GP32"; |
4621 | | case MCK_GP64: return "MCK_GP64"; |
4622 | | case MCK_GPR32ZERO: return "MCK_GPR32ZERO"; |
4623 | | case MCK_HI32: return "MCK_HI32"; |
4624 | | case MCK_HI64: return "MCK_HI64"; |
4625 | | case MCK_LO32: return "MCK_LO32"; |
4626 | | case MCK_LO64: return "MCK_LO64"; |
4627 | | case MCK_PC: return "MCK_PC"; |
4628 | | case MCK_SP64: return "MCK_SP64"; |
4629 | | case MCK_Reg32: return "MCK_Reg32"; |
4630 | | case MCK_Reg13: return "MCK_Reg13"; |
4631 | | case MCK_Reg33: return "MCK_Reg33"; |
4632 | | case MCK_Reg31: return "MCK_Reg31"; |
4633 | | case MCK_Reg30: return "MCK_Reg30"; |
4634 | | case MCK_Reg14: return "MCK_Reg14"; |
4635 | | case MCK_Reg11: return "MCK_Reg11"; |
4636 | | case MCK_GPRMM16MovePPairFirst: return "MCK_GPRMM16MovePPairFirst"; |
4637 | | case MCK_OCTEON_MPL: return "MCK_OCTEON_MPL"; |
4638 | | case MCK_OCTEON_P: return "MCK_OCTEON_P"; |
4639 | | case MCK_Reg28: return "MCK_Reg28"; |
4640 | | case MCK_Reg23: return "MCK_Reg23"; |
4641 | | case MCK_Reg9: return "MCK_Reg9"; |
4642 | | case MCK_Reg4: return "MCK_Reg4"; |
4643 | | case MCK_ACC64DSP: return "MCK_ACC64DSP"; |
4644 | | case MCK_HI32DSP: return "MCK_HI32DSP"; |
4645 | | case MCK_LO32DSP: return "MCK_LO32DSP"; |
4646 | | case MCK_Reg34: return "MCK_Reg34"; |
4647 | | case MCK_GPRMM16MovePPairSecond: return "MCK_GPRMM16MovePPairSecond"; |
4648 | | case MCK_Reg29: return "MCK_Reg29"; |
4649 | | case MCK_Reg27: return "MCK_Reg27"; |
4650 | | case MCK_Reg10: return "MCK_Reg10"; |
4651 | | case MCK_Reg8: return "MCK_Reg8"; |
4652 | | case MCK_Reg25: return "MCK_Reg25"; |
4653 | | case MCK_Reg22: return "MCK_Reg22"; |
4654 | | case MCK_Reg21: return "MCK_Reg21"; |
4655 | | case MCK_CPU16Regs: return "MCK_CPU16Regs"; |
4656 | | case MCK_FCC: return "MCK_FCC"; |
4657 | | case MCK_GPRMM16MoveP: return "MCK_GPRMM16MoveP"; |
4658 | | case MCK_GPRMM16Zero: return "MCK_GPRMM16Zero"; |
4659 | | case MCK_Reg26: return "MCK_Reg26"; |
4660 | | case MCK_CPU16RegsPlusSP: return "MCK_CPU16RegsPlusSP"; |
4661 | | case MCK_AFGR64: return "MCK_AFGR64"; |
4662 | | case MCK_MSA128WEvens: return "MCK_MSA128WEvens"; |
4663 | | case MCK_Reg24: return "MCK_Reg24"; |
4664 | | case MCK_GPR32NONZERO: return "MCK_GPR32NONZERO"; |
4665 | | case MCK_CCR: return "MCK_CCR"; |
4666 | | case MCK_COP0: return "MCK_COP0"; |
4667 | | case MCK_COP2: return "MCK_COP2"; |
4668 | | case MCK_COP3: return "MCK_COP3"; |
4669 | | case MCK_DSPR: return "MCK_DSPR"; |
4670 | | case MCK_FGR32: return "MCK_FGR32"; |
4671 | | case MCK_FGR64: return "MCK_FGR64"; |
4672 | | case MCK_GPR64: return "MCK_GPR64"; |
4673 | | case MCK_HWRegs: return "MCK_HWRegs"; |
4674 | | case MCK_MSA128F16: return "MCK_MSA128F16"; |
4675 | | case MCK_MSACtrl: return "MCK_MSACtrl"; |
4676 | | case MCK_ACC64DSPAsmReg: return "MCK_ACC64DSPAsmReg"; |
4677 | | case MCK_AFGR64AsmReg: return "MCK_AFGR64AsmReg"; |
4678 | | case MCK_CCRAsmReg: return "MCK_CCRAsmReg"; |
4679 | | case MCK_COP0AsmReg: return "MCK_COP0AsmReg"; |
4680 | | case MCK_COP2AsmReg: return "MCK_COP2AsmReg"; |
4681 | | case MCK_COP3AsmReg: return "MCK_COP3AsmReg"; |
4682 | | case MCK_FCCAsmReg: return "MCK_FCCAsmReg"; |
4683 | | case MCK_FGR32AsmReg: return "MCK_FGR32AsmReg"; |
4684 | | case MCK_FGR64AsmReg: return "MCK_FGR64AsmReg"; |
4685 | | case MCK_GPR32AsmReg: return "MCK_GPR32AsmReg"; |
4686 | | case MCK_GPR32NonZeroAsmReg: return "MCK_GPR32NonZeroAsmReg"; |
4687 | | case MCK_GPR32ZeroAsmReg: return "MCK_GPR32ZeroAsmReg"; |
4688 | | case MCK_GPR64AsmReg: return "MCK_GPR64AsmReg"; |
4689 | | case MCK_GPRMM16AsmReg: return "MCK_GPRMM16AsmReg"; |
4690 | | case MCK_GPRMM16AsmRegMoveP: return "MCK_GPRMM16AsmRegMoveP"; |
4691 | | case MCK_GPRMM16AsmRegMovePPairFirst: return "MCK_GPRMM16AsmRegMovePPairFirst"; |
4692 | | case MCK_GPRMM16AsmRegMovePPairSecond: return "MCK_GPRMM16AsmRegMovePPairSecond"; |
4693 | | case MCK_GPRMM16AsmRegZero: return "MCK_GPRMM16AsmRegZero"; |
4694 | | case MCK_HI32DSPAsmReg: return "MCK_HI32DSPAsmReg"; |
4695 | | case MCK_HWRegsAsmReg: return "MCK_HWRegsAsmReg"; |
4696 | | case MCK_Imm: return "MCK_Imm"; |
4697 | | case MCK_LO32DSPAsmReg: return "MCK_LO32DSPAsmReg"; |
4698 | | case MCK_MSA128AsmReg: return "MCK_MSA128AsmReg"; |
4699 | | case MCK_MSACtrlAsmReg: return "MCK_MSACtrlAsmReg"; |
4700 | | case MCK_MicroMipsMemGP: return "MCK_MicroMipsMemGP"; |
4701 | | case MCK_MicroMipsMem: return "MCK_MicroMipsMem"; |
4702 | | case MCK_MicroMipsMemSP: return "MCK_MicroMipsMemSP"; |
4703 | | case MCK_InvNum: return "MCK_InvNum"; |
4704 | | case MCK_JumpTarget: return "MCK_JumpTarget"; |
4705 | | case MCK_MemOffsetSimm10: return "MCK_MemOffsetSimm10"; |
4706 | | case MCK_MemOffsetSimm10_1: return "MCK_MemOffsetSimm10_1"; |
4707 | | case MCK_MemOffsetSimm10_2: return "MCK_MemOffsetSimm10_2"; |
4708 | | case MCK_MemOffsetSimm10_3: return "MCK_MemOffsetSimm10_3"; |
4709 | | case MCK_MemOffsetSimm11: return "MCK_MemOffsetSimm11"; |
4710 | | case MCK_MemOffsetSimm12: return "MCK_MemOffsetSimm12"; |
4711 | | case MCK_MemOffsetSimm16: return "MCK_MemOffsetSimm16"; |
4712 | | case MCK_MemOffsetSimm9: return "MCK_MemOffsetSimm9"; |
4713 | | case MCK_MemOffsetSimmPtr: return "MCK_MemOffsetSimmPtr"; |
4714 | | case MCK_MemOffsetUimm4: return "MCK_MemOffsetUimm4"; |
4715 | | case MCK_Mem: return "MCK_Mem"; |
4716 | | case MCK_RegList16: return "MCK_RegList16"; |
4717 | | case MCK_RegList: return "MCK_RegList"; |
4718 | | case MCK_Simm19_Lsl2: return "MCK_Simm19_Lsl2"; |
4719 | | case MCK_StrictlyAFGR64AsmReg: return "MCK_StrictlyAFGR64AsmReg"; |
4720 | | case MCK_StrictlyFGR32AsmReg: return "MCK_StrictlyFGR32AsmReg"; |
4721 | | case MCK_StrictlyFGR64AsmReg: return "MCK_StrictlyFGR64AsmReg"; |
4722 | | case MCK_ConstantImmz: return "MCK_ConstantImmz"; |
4723 | | case MCK_ConstantUImm1_0: return "MCK_ConstantUImm1_0"; |
4724 | | case MCK_ConstantUImm2_0: return "MCK_ConstantUImm2_0"; |
4725 | | case MCK_ConstantUImm2_1: return "MCK_ConstantUImm2_1"; |
4726 | | case MCK_ConstantUImm3_0: return "MCK_ConstantUImm3_0"; |
4727 | | case MCK_ConstantSImm4_0: return "MCK_ConstantSImm4_0"; |
4728 | | case MCK_ConstantUImm4_0: return "MCK_ConstantUImm4_0"; |
4729 | | case MCK_ConstantSImm5_0: return "MCK_ConstantSImm5_0"; |
4730 | | case MCK_ConstantUImm5_0: return "MCK_ConstantUImm5_0"; |
4731 | | case MCK_ConstantUImm5_1: return "MCK_ConstantUImm5_1"; |
4732 | | case MCK_ConstantUImm5_Plus1_Report_UImm6: return "MCK_ConstantUImm5_Plus1_Report_UImm6"; |
4733 | | case MCK_ConstantUImm5_32_Norm: return "MCK_ConstantUImm5_32_Norm"; |
4734 | | case MCK_ConstantUImm5_32: return "MCK_ConstantUImm5_32"; |
4735 | | case MCK_ConstantUImm5_0_Report_UImm6: return "MCK_ConstantUImm5_0_Report_UImm6"; |
4736 | | case MCK_ConstantUImm5_33: return "MCK_ConstantUImm5_33"; |
4737 | | case MCK_ConstantUImmRange2_64: return "MCK_ConstantUImmRange2_64"; |
4738 | | case MCK_UImm5Lsl2: return "MCK_UImm5Lsl2"; |
4739 | | case MCK_ConstantSImm6_0: return "MCK_ConstantSImm6_0"; |
4740 | | case MCK_ConstantUImm6_0: return "MCK_ConstantUImm6_0"; |
4741 | | case MCK_UImm6Lsl2: return "MCK_UImm6Lsl2"; |
4742 | | case MCK_ConstantUImm7_0: return "MCK_ConstantUImm7_0"; |
4743 | | case MCK_UImm7_N1: return "MCK_UImm7_N1"; |
4744 | | case MCK_ConstantUImm8_0: return "MCK_ConstantUImm8_0"; |
4745 | | case MCK_SImm7Lsl2: return "MCK_SImm7Lsl2"; |
4746 | | case MCK_ConstantSImm9_0: return "MCK_ConstantSImm9_0"; |
4747 | | case MCK_ConstantSImm10_0: return "MCK_ConstantSImm10_0"; |
4748 | | case MCK_ConstantUImm10_0: return "MCK_ConstantUImm10_0"; |
4749 | | case MCK_SImm10Lsl1: return "MCK_SImm10Lsl1"; |
4750 | | case MCK_ConstantSImm11_0: return "MCK_ConstantSImm11_0"; |
4751 | | case MCK_SImm10Lsl2: return "MCK_SImm10Lsl2"; |
4752 | | case MCK_SImm10Lsl3: return "MCK_SImm10Lsl3"; |
4753 | | case MCK_SImm16: return "MCK_SImm16"; |
4754 | | case MCK_SImm16_Relaxed: return "MCK_SImm16_Relaxed"; |
4755 | | case MCK_UImm16_AltRelaxed: return "MCK_UImm16_AltRelaxed"; |
4756 | | case MCK_UImm16: return "MCK_UImm16"; |
4757 | | case MCK_SImm19Lsl2: return "MCK_SImm19Lsl2"; |
4758 | | case MCK_UImm16_Relaxed: return "MCK_UImm16_Relaxed"; |
4759 | | case MCK_ConstantUImm20_0: return "MCK_ConstantUImm20_0"; |
4760 | | case MCK_ConstantUImm26_0: return "MCK_ConstantUImm26_0"; |
4761 | | case MCK_SImm32: return "MCK_SImm32"; |
4762 | | case MCK_SImm32_Relaxed: return "MCK_SImm32_Relaxed"; |
4763 | | case MCK_UImm32_Coerced: return "MCK_UImm32_Coerced"; |
4764 | | case NumMatchClassKinds: return "NumMatchClassKinds"; |
4765 | | } |
4766 | | llvm_unreachable("unhandled MatchClassKind!"); |
4767 | | } |
4768 | | |
4769 | | #endif // NDEBUG |
4770 | | FeatureBitset MipsAsmParser:: |
4771 | 2.30k | ComputeAvailableFeatures(const FeatureBitset& FB) const { |
4772 | 2.30k | FeatureBitset Features; |
4773 | 2.30k | if ((FB[Mips::FeatureMips2])) |
4774 | 2.24k | Features[Feature_HasMips2Bit] = 1; |
4775 | 2.30k | if ((FB[Mips::FeatureMips3_32])) |
4776 | 2.19k | Features[Feature_HasMips3_32Bit] = 1; |
4777 | 2.30k | if ((FB[Mips::FeatureMips3_32r2])) |
4778 | 1.51k | Features[Feature_HasMips3_32r2Bit] = 1; |
4779 | 2.30k | if ((FB[Mips::FeatureMips3])) |
4780 | 925 | Features[Feature_HasMips3Bit] = 1; |
4781 | 2.30k | if ((!FB[Mips::FeatureMips3])) |
4782 | 1.38k | Features[Feature_NotMips3Bit] = 1; |
4783 | 2.30k | if ((FB[Mips::FeatureMips4_32])) |
4784 | 2.13k | Features[Feature_HasMips4_32Bit] = 1; |
4785 | 2.30k | if ((!FB[Mips::FeatureMips4_32])) |
4786 | 173 | Features[Feature_NotMips4_32Bit] = 1; |
4787 | 2.30k | if ((FB[Mips::FeatureMips4_32r2])) |
4788 | 1.45k | Features[Feature_HasMips4_32r2Bit] = 1; |
4789 | 2.30k | if ((FB[Mips::FeatureMips5_32r2])) |
4790 | 1.38k | Features[Feature_HasMips5_32r2Bit] = 1; |
4791 | 2.30k | if ((FB[Mips::FeatureMips32])) |
4792 | 2.01k | Features[Feature_HasMips32Bit] = 1; |
4793 | 2.30k | if ((FB[Mips::FeatureMips32r2])) |
4794 | 1.00k | Features[Feature_HasMips32r2Bit] = 1; |
4795 | 2.30k | if ((FB[Mips::FeatureMips32r5])) |
4796 | 486 | Features[Feature_HasMips32r5Bit] = 1; |
4797 | 2.30k | if ((FB[Mips::FeatureMips32r6])) |
4798 | 336 | Features[Feature_HasMips32r6Bit] = 1; |
4799 | 2.30k | if ((!FB[Mips::FeatureMips32r6])) |
4800 | 1.97k | Features[Feature_NotMips32r6Bit] = 1; |
4801 | 2.30k | if ((FB[Mips::FeatureGP64Bit])) |
4802 | 931 | Features[Feature_IsGP64bitBit] = 1; |
4803 | 2.30k | if ((!FB[Mips::FeatureGP64Bit])) |
4804 | 1.37k | Features[Feature_IsGP32bitBit] = 1; |
4805 | 2.30k | if ((FB[Mips::FeaturePTR64Bit])) |
4806 | 0 | Features[Feature_IsPTR64bitBit] = 1; |
4807 | 2.30k | if ((!FB[Mips::FeaturePTR64Bit])) |
4808 | 2.30k | Features[Feature_IsPTR32bitBit] = 1; |
4809 | 2.30k | if ((FB[Mips::FeatureMips64])) |
4810 | 743 | Features[Feature_HasMips64Bit] = 1; |
4811 | 2.30k | if ((!FB[Mips::FeatureMips64])) |
4812 | 1.56k | Features[Feature_NotMips64Bit] = 1; |
4813 | 2.30k | if ((FB[Mips::FeatureMips64r2])) |
4814 | 413 | Features[Feature_HasMips64r2Bit] = 1; |
4815 | 2.30k | if ((FB[Mips::FeatureMips64r5])) |
4816 | 202 | Features[Feature_HasMips64r5Bit] = 1; |
4817 | 2.30k | if ((FB[Mips::FeatureMips64r6])) |
4818 | 128 | Features[Feature_HasMips64r6Bit] = 1; |
4819 | 2.30k | if ((!FB[Mips::FeatureMips64r6])) |
4820 | 2.18k | Features[Feature_NotMips64r6Bit] = 1; |
4821 | 2.30k | if ((FB[Mips::FeatureMips16])) |
4822 | 46 | Features[Feature_InMips16ModeBit] = 1; |
4823 | 2.30k | if ((!FB[Mips::FeatureMips16])) |
4824 | 2.26k | Features[Feature_NotInMips16ModeBit] = 1; |
4825 | 2.30k | if ((FB[Mips::FeatureCnMips])) |
4826 | 11 | Features[Feature_HasCnMipsBit] = 1; |
4827 | 2.30k | if ((!FB[Mips::FeatureCnMips])) |
4828 | 2.29k | Features[Feature_NotCnMipsBit] = 1; |
4829 | 2.30k | if ((FB[Mips::FeatureSym32])) |
4830 | 0 | Features[Feature_IsSym32Bit] = 1; |
4831 | 2.30k | if ((!FB[Mips::FeatureSym32])) |
4832 | 2.30k | Features[Feature_IsSym64Bit] = 1; |
4833 | 2.30k | if ((!FB[Mips::FeatureMips16])) |
4834 | 2.26k | Features[Feature_HasStdEncBit] = 1; |
4835 | 2.30k | if ((FB[Mips::FeatureMicroMips])) |
4836 | 173 | Features[Feature_InMicroMipsBit] = 1; |
4837 | 2.30k | if ((!FB[Mips::FeatureMicroMips])) |
4838 | 2.13k | Features[Feature_NotInMicroMipsBit] = 1; |
4839 | 2.30k | if ((FB[Mips::FeatureEVA])) |
4840 | 18 | Features[Feature_HasEVABit] = 1; |
4841 | 2.30k | if ((FB[Mips::FeatureMSA])) |
4842 | 44 | Features[Feature_HasMSABit] = 1; |
4843 | 2.30k | if ((!FB[Mips::FeatureMadd4])) |
4844 | 2.30k | Features[Feature_HasMadd4Bit] = 1; |
4845 | 2.30k | if ((FB[Mips::FeatureMT])) |
4846 | 12 | Features[Feature_HasMTBit] = 1; |
4847 | 2.30k | if ((FB[Mips::FeatureUseIndirectJumpsHazard])) |
4848 | 8 | Features[Feature_UseIndirectJumpsHazardBit] = 1; |
4849 | 2.30k | if ((!FB[Mips::FeatureUseIndirectJumpsHazard])) |
4850 | 2.30k | Features[Feature_NoIndirectJumpGuardsBit] = 1; |
4851 | 2.30k | if ((FB[Mips::FeatureCRC])) |
4852 | 20 | Features[Feature_HasCRCBit] = 1; |
4853 | 2.30k | if ((FB[Mips::FeatureVirt])) |
4854 | 16 | Features[Feature_HasVirtBit] = 1; |
4855 | 2.30k | if ((FB[Mips::FeatureGINV])) |
4856 | 14 | Features[Feature_HasGINVBit] = 1; |
4857 | 2.30k | if ((FB[Mips::FeatureFP64Bit])) |
4858 | 1.17k | Features[Feature_IsFP64bitBit] = 1; |
4859 | 2.30k | if ((!FB[Mips::FeatureFP64Bit])) |
4860 | 1.13k | Features[Feature_NotFP64bitBit] = 1; |
4861 | 2.30k | if ((FB[Mips::FeatureSingleFloat])) |
4862 | 0 | Features[Feature_IsSingleFloatBit] = 1; |
4863 | 2.30k | if ((!FB[Mips::FeatureSingleFloat])) |
4864 | 2.30k | Features[Feature_IsNotSingleFloatBit] = 1; |
4865 | 2.30k | if ((!FB[Mips::FeatureSoftFloat])) |
4866 | 2.25k | Features[Feature_IsNotSoftFloatBit] = 1; |
4867 | 2.30k | if ((FB[Mips::FeatureDSP])) |
4868 | 21 | Features[Feature_HasDSPBit] = 1; |
4869 | 2.30k | if ((FB[Mips::FeatureDSPR2])) |
4870 | 9 | Features[Feature_HasDSPR2Bit] = 1; |
4871 | 2.30k | if ((FB[Mips::FeatureDSPR3])) |
4872 | 1 | Features[Feature_HasDSPR3Bit] = 1; |
4873 | 2.30k | return Features; |
4874 | 2.30k | } |
4875 | | |
4876 | | static bool checkAsmTiedOperandConstraints(const MipsAsmParser&AsmParser, |
4877 | | unsigned Kind, |
4878 | | const OperandVector &Operands, |
4879 | 35.9k | uint64_t &ErrorInfo) { |
4880 | 35.9k | assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); |
4881 | 35.9k | const uint8_t *Converter = ConversionTable[Kind]; |
4882 | 125k | for (const uint8_t *p = Converter; *p; p+= 289.3k ) { |
4883 | 89.3k | switch (*p) { |
4884 | 89.3k | case CVT_Tied: { |
4885 | 617 | unsigned OpIdx = *(p+1); |
4886 | 617 | assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) - |
4887 | 617 | std::begin(TiedAsmOperandTable)) && |
4888 | 617 | "Tied operand not found"); |
4889 | 617 | unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1]; |
4890 | 617 | unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2]; |
4891 | 617 | if (OpndNum1 != OpndNum2) { |
4892 | 2 | auto &SrcOp1 = Operands[OpndNum1]; |
4893 | 2 | auto &SrcOp2 = Operands[OpndNum2]; |
4894 | 2 | if (SrcOp1->isReg() && SrcOp2->isReg()0 ) { |
4895 | 0 | if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) { |
4896 | 0 | ErrorInfo = OpndNum2; |
4897 | 0 | return false; |
4898 | 0 | } |
4899 | 617 | } |
4900 | 2 | } |
4901 | 617 | break; |
4902 | 617 | } |
4903 | 88.6k | default: |
4904 | 88.6k | break; |
4905 | 89.3k | } |
4906 | 89.3k | } |
4907 | 35.9k | return true; |
4908 | 35.9k | } |
4909 | | |
4910 | | static const char *const MnemonicTable = |
4911 | | "\003abs\005abs.d\005abs.s\tabsq_s.ph\tabsq_s.qb\010absq_s.w\003add\005a" |
4912 | | "dd.d\005add.s\007add_a.b\007add_a.d\007add_a.h\007add_a.w\004addi\005ad" |
4913 | | "diu\007addiupc\taddiur1sp\007addiur2\007addius5\007addiusp\007addq.ph\t" |
4914 | | "addq_s.ph\010addq_s.w\010addqh.ph\007addqh.w\naddqh_r.ph\taddqh_r.w\010" |
4915 | | "adds_a.b\010adds_a.d\010adds_a.h\010adds_a.w\010adds_s.b\010adds_s.d\010" |
4916 | | "adds_s.h\010adds_s.w\010adds_u.b\010adds_u.d\010adds_u.h\010adds_u.w\005" |
4917 | | "addsc\004addu\007addu.ph\007addu.qb\006addu16\taddu_s.ph\taddu_s.qb\010" |
4918 | | "adduh.qb\nadduh_r.qb\006addv.b\006addv.d\006addv.h\006addv.w\007addvi.b" |
4919 | | "\007addvi.d\007addvi.h\007addvi.w\005addwc\005align\006aluipc\003and\005" |
4920 | | "and.v\005and16\004andi\006andi.b\006andi16\006append\010asub_s.b\010asu" |
4921 | | "b_s.d\010asub_s.h\010asub_s.w\010asub_u.b\010asub_u.d\010asub_u.h\010as" |
4922 | | "ub_u.w\003aui\005auipc\007ave_s.b\007ave_s.d\007ave_s.h\007ave_s.w\007a" |
4923 | | "ve_u.b\007ave_u.d\007ave_u.h\007ave_u.w\010aver_s.b\010aver_s.d\010aver" |
4924 | | "_s.h\010aver_s.w\010aver_u.b\010aver_u.d\010aver_u.h\010aver_u.w\001b\003" |
4925 | | "b16\005baddu\003bal\004balc\006balign\005bbit0\007bbit032\005bbit1\007b" |
4926 | | "bit132\002bc\004bc16\006bc1eqz\007bc1eqzc\004bc1f\005bc1fl\006bc1nez\007" |
4927 | | "bc1nezc\004bc1t\005bc1tl\006bc2eqz\007bc2eqzc\006bc2nez\007bc2nezc\006b" |
4928 | | "clr.b\006bclr.d\006bclr.h\006bclr.w\007bclri.b\007bclri.d\007bclri.h\007" |
4929 | | "bclri.w\003beq\004beqc\004beql\004beqz\006beqz16\007beqzalc\005beqzc\007" |
4930 | | "beqzc16\005beqzl\003bge\004bgec\004bgel\004bgeu\005bgeuc\005bgeul\004bg" |
4931 | | "ez\006bgezal\007bgezalc\007bgezall\007bgezals\005bgezc\005bgezl\003bgt\004" |
4932 | | "bgtl\004bgtu\005bgtul\004bgtz\007bgtzalc\005bgtzc\005bgtzl\007binsl.b\007" |
4933 | | "binsl.d\007binsl.h\007binsl.w\010binsli.b\010binsli.d\010binsli.h\010bi" |
4934 | | "nsli.w\007binsr.b\007binsr.d\007binsr.h\007binsr.w\010binsri.b\010binsr" |
4935 | | "i.d\010binsri.h\010binsri.w\006bitrev\007bitswap\003ble\004blel\004bleu" |
4936 | | "\005bleul\004blez\007blezalc\005blezc\005blezl\003blt\004bltc\004bltl\004" |
4937 | | "bltu\005bltuc\005bltul\004bltz\006bltzal\007bltzalc\007bltzall\007bltza" |
4938 | | "ls\005bltzc\005bltzl\006bmnz.v\007bmnzi.b\005bmz.v\006bmzi.b\003bne\004" |
4939 | | "bnec\006bneg.b\006bneg.d\006bneg.h\006bneg.w\007bnegi.b\007bnegi.d\007b" |
4940 | | "negi.h\007bnegi.w\004bnel\004bnez\006bnez16\007bnezalc\005bnezc\007bnez" |
4941 | | "c16\005bnezl\004bnvc\005bnz.b\005bnz.d\005bnz.h\005bnz.v\005bnz.w\004bo" |
4942 | | "vc\010bposge32\tbposge32c\005break\007break16\006bsel.v\007bseli.b\006b" |
4943 | | "set.b\006bset.d\006bset.h\006bset.w\007bseti.b\007bseti.d\007bseti.h\007" |
4944 | | "bseti.w\005bteqz\005btnez\004bz.b\004bz.d\004bz.h\004bz.v\004bz.w\006c." |
4945 | | "eq.d\006c.eq.s\005c.f.d\005c.f.s\006c.le.d\006c.le.s\006c.lt.d\006c.lt." |
4946 | | "s\007c.nge.d\007c.nge.s\007c.ngl.d\007c.ngl.s\010c.ngle.d\010c.ngle.s\007" |
4947 | | "c.ngt.d\007c.ngt.s\007c.ole.d\007c.ole.s\007c.olt.d\007c.olt.s\007c.seq" |
4948 | | ".d\007c.seq.s\006c.sf.d\006c.sf.s\007c.ueq.d\007c.ueq.s\007c.ule.d\007c" |
4949 | | ".ule.s\007c.ult.d\007c.ult.s\006c.un.d\006c.un.s\005cache\006cachee\010" |
4950 | | "ceil.l.d\010ceil.l.s\010ceil.w.d\010ceil.w.s\005ceq.b\005ceq.d\005ceq.h" |
4951 | | "\005ceq.w\006ceqi.b\006ceqi.d\006ceqi.h\006ceqi.w\004cfc1\004cfc2\006cf" |
4952 | | "cmsa\005cftc1\004cins\006cins32\007class.d\007class.s\007cle_s.b\007cle" |
4953 | | "_s.d\007cle_s.h\007cle_s.w\007cle_u.b\007cle_u.d\007cle_u.h\007cle_u.w\010" |
4954 | | "clei_s.b\010clei_s.d\010clei_s.h\010clei_s.w\010clei_u.b\010clei_u.d\010" |
4955 | | "clei_u.h\010clei_u.w\003clo\007clt_s.b\007clt_s.d\007clt_s.h\007clt_s.w" |
4956 | | "\007clt_u.b\007clt_u.d\007clt_u.h\007clt_u.w\010clti_s.b\010clti_s.d\010" |
4957 | | "clti_s.h\010clti_s.w\010clti_u.b\010clti_u.d\010clti_u.h\010clti_u.w\003" |
4958 | | "clz\003cmp\010cmp.af.d\010cmp.af.s\010cmp.eq.d\tcmp.eq.ph\010cmp.eq.s\010" |
4959 | | "cmp.le.d\tcmp.le.ph\010cmp.le.s\010cmp.lt.d\tcmp.lt.ph\010cmp.lt.s\tcmp" |
4960 | | ".saf.d\tcmp.saf.s\tcmp.seq.d\tcmp.seq.s\tcmp.sle.d\tcmp.sle.s\tcmp.slt." |
4961 | | "d\tcmp.slt.s\ncmp.sueq.d\ncmp.sueq.s\ncmp.sule.d\ncmp.sule.s\ncmp.sult." |
4962 | | "d\ncmp.sult.s\tcmp.sun.d\tcmp.sun.s\tcmp.ueq.d\tcmp.ueq.s\tcmp.ule.d\tc" |
4963 | | "mp.ule.s\tcmp.ult.d\tcmp.ult.s\010cmp.un.d\010cmp.un.s\014cmpgdu.eq.qb\014" |
4964 | | "cmpgdu.le.qb\014cmpgdu.lt.qb\013cmpgu.eq.qb\013cmpgu.le.qb\013cmpgu.lt." |
4965 | | "qb\004cmpi\ncmpu.eq.qb\ncmpu.le.qb\ncmpu.lt.qb\010copy_s.b\010copy_s.d\010" |
4966 | | "copy_s.h\010copy_s.w\010copy_u.b\010copy_u.h\010copy_u.w\006crc32b\007c" |
4967 | | "rc32cb\007crc32cd\007crc32ch\007crc32cw\006crc32d\006crc32h\006crc32w\004" |
4968 | | "ctc1\004ctc2\006ctcmsa\005cttc1\007cvt.d.l\007cvt.d.s\007cvt.d.w\007cvt" |
4969 | | ".l.d\007cvt.l.s\010cvt.ps.s\007cvt.s.d\007cvt.s.l\010cvt.s.pl\010cvt.s." |
4970 | | "pu\007cvt.s.w\007cvt.w.d\007cvt.w.s\004dadd\005daddi\006daddiu\005daddu" |
4971 | | "\004dahi\006dalign\004dati\004daui\010dbitswap\004dclo\004dclz\004ddiv\005" |
4972 | | "ddivu\005deret\004dext\005dextm\005dextu\002di\004dins\005dinsm\005dins" |
4973 | | "u\003div\005div.d\005div.s\007div_s.b\007div_s.d\007div_s.h\007div_s.w\007" |
4974 | | "div_u.b\007div_u.d\007div_u.h\007div_u.w\004divu\003dla\003dli\004dlsa\005" |
4975 | | "dmfc0\005dmfc1\005dmfc2\006dmfgc0\004dmod\005dmodu\003dmt\005dmtc0\005d" |
4976 | | "mtc1\005dmtc2\006dmtgc0\004dmuh\005dmuhu\004dmul\005dmulo\006dmulou\005" |
4977 | | "dmult\006dmultu\005dmulu\004dneg\005dnegu\010dotp_s.d\010dotp_s.h\010do" |
4978 | | "tp_s.w\010dotp_u.d\010dotp_u.h\010dotp_u.w\010dpa.w.ph\tdpadd_s.d\tdpad" |
4979 | | "d_s.h\tdpadd_s.w\tdpadd_u.d\tdpadd_u.h\tdpadd_u.w\013dpaq_s.w.ph\013dpa" |
4980 | | "q_sa.l.w\014dpaqx_s.w.ph\015dpaqx_sa.w.ph\ndpau.h.qbl\ndpau.h.qbr\tdpax" |
4981 | | ".w.ph\004dpop\010dps.w.ph\013dpsq_s.w.ph\013dpsq_sa.l.w\014dpsqx_s.w.ph" |
4982 | | "\015dpsqx_sa.w.ph\ndpsu.h.qbl\ndpsu.h.qbr\tdpsub_s.d\tdpsub_s.h\tdpsub_" |
4983 | | "s.w\tdpsub_u.d\tdpsub_u.h\tdpsub_u.w\tdpsx.w.ph\004drem\005dremu\004dro" |
4984 | | "l\004dror\005drotr\007drotr32\006drotrv\004dsbh\004dshd\004dsll\006dsll" |
4985 | | "32\005dsllv\004dsra\006dsra32\005dsrav\004dsrl\006dsrl32\005dsrlv\004ds" |
4986 | | "ub\005dsubi\005dsubu\003dvp\004dvpe\003ehb\002ei\003emt\004eret\006eret" |
4987 | | "nc\003evp\004evpe\003ext\004extp\006extpdp\007extpdpv\005extpv\006extr." |
4988 | | "w\010extr_r.w\textr_rs.w\010extr_s.h\007extrv.w\textrv_r.w\nextrv_rs.w\t" |
4989 | | "extrv_s.h\004exts\006exts32\006fadd.d\006fadd.w\006fcaf.d\006fcaf.w\006" |
4990 | | "fceq.d\006fceq.w\010fclass.d\010fclass.w\006fcle.d\006fcle.w\006fclt.d\006" |
4991 | | "fclt.w\006fcne.d\006fcne.w\006fcor.d\006fcor.w\007fcueq.d\007fcueq.w\007" |
4992 | | "fcule.d\007fcule.w\007fcult.d\007fcult.w\006fcun.d\006fcun.w\007fcune.d" |
4993 | | "\007fcune.w\006fdiv.d\006fdiv.w\007fexdo.h\007fexdo.w\007fexp2.d\007fex" |
4994 | | "p2.w\010fexupl.d\010fexupl.w\010fexupr.d\010fexupr.w\tffint_s.d\tffint_" |
4995 | | "s.w\tffint_u.d\tffint_u.w\006ffql.d\006ffql.w\006ffqr.d\006ffqr.w\006fi" |
4996 | | "ll.b\006fill.d\006fill.h\006fill.w\007flog2.d\007flog2.w\tfloor.l.d\tfl" |
4997 | | "oor.l.s\tfloor.w.d\tfloor.w.s\007fmadd.d\007fmadd.w\006fmax.d\006fmax.w" |
4998 | | "\010fmax_a.d\010fmax_a.w\006fmin.d\006fmin.w\010fmin_a.d\010fmin_a.w\007" |
4999 | | "fmsub.d\007fmsub.w\006fmul.d\006fmul.w\004fork\006frcp.d\006frcp.w\007f" |
5000 | | "rint.d\007frint.w\010frsqrt.d\010frsqrt.w\006fsaf.d\006fsaf.w\006fseq.d" |
5001 | | "\006fseq.w\006fsle.d\006fsle.w\006fslt.d\006fslt.w\006fsne.d\006fsne.w\006" |
5002 | | "fsor.d\006fsor.w\007fsqrt.d\007fsqrt.w\006fsub.d\006fsub.w\007fsueq.d\007" |
5003 | | "fsueq.w\007fsule.d\007fsule.w\007fsult.d\007fsult.w\006fsun.d\006fsun.w" |
5004 | | "\007fsune.d\007fsune.w\tftint_s.d\tftint_s.w\tftint_u.d\tftint_u.w\005f" |
5005 | | "tq.h\005ftq.w\nftrunc_s.d\nftrunc_s.w\nftrunc_u.d\nftrunc_u.w\005ginvi\005" |
5006 | | "ginvt\010hadd_s.d\010hadd_s.h\010hadd_s.w\010hadd_u.d\010hadd_u.h\010ha" |
5007 | | "dd_u.w\010hsub_s.d\010hsub_s.h\010hsub_s.w\010hsub_u.d\010hsub_u.h\010h" |
5008 | | "sub_u.w\007hypcall\007ilvev.b\007ilvev.d\007ilvev.h\007ilvev.w\006ilvl." |
5009 | | "b\006ilvl.d\006ilvl.h\006ilvl.w\007ilvod.b\007ilvod.d\007ilvod.h\007ilv" |
5010 | | "od.w\006ilvr.b\006ilvr.d\006ilvr.h\006ilvr.w\003ins\010insert.b\010inse" |
5011 | | "rt.d\010insert.h\010insert.w\004insv\007insve.b\007insve.d\007insve.h\007" |
5012 | | "insve.w\001j\003jal\004jalr\007jalr.hb\005jalrc\010jalrc.hb\005jalrs\007" |
5013 | | "jalrs16\004jals\004jalx\005jialc\003jic\002jr\005jr.hb\004jr16\tjraddiu" |
5014 | | "sp\003jrc\005jrc16\njrcaddiusp\003l.d\003l.s\002la\004lapc\002lb\003lbe" |
5015 | | "\003lbu\005lbu16\004lbue\004lbux\002ld\004ld.b\004ld.d\004ld.h\004ld.w\004" |
5016 | | "ldc1\004ldc2\004ldc3\005ldi.b\005ldi.d\005ldi.h\005ldi.w\003ldl\004ldpc" |
5017 | | "\003ldr\005ldxc1\002lh\003lhe\003lhu\005lhu16\004lhue\003lhx\002li\004l" |
5018 | | "i.d\004li.s\004li16\002ll\003lld\003lle\003lsa\003lui\005luxc1\002lw\004" |
5019 | | "lw16\004lwc1\004lwc2\004lwc3\003lwe\003lwl\004lwle\003lwm\005lwm16\005l" |
5020 | | "wm32\003lwp\004lwpc\003lwr\004lwre\003lwu\005lwupc\003lwx\005lwxc1\004l" |
5021 | | "wxs\004madd\006madd.d\006madd.s\010madd_q.h\010madd_q.w\007maddf.d\007m" |
5022 | | "addf.s\tmaddr_q.h\tmaddr_q.w\005maddu\007maddv.b\007maddv.d\007maddv.h\007" |
5023 | | "maddv.w\013maq_s.w.phl\013maq_s.w.phr\014maq_sa.w.phl\014maq_sa.w.phr\005" |
5024 | | "max.d\005max.s\007max_a.b\007max_a.d\007max_a.h\007max_a.w\007max_s.b\007" |
5025 | | "max_s.d\007max_s.h\007max_s.w\007max_u.b\007max_u.d\007max_u.h\007max_u" |
5026 | | ".w\006maxa.d\006maxa.s\010maxi_s.b\010maxi_s.d\010maxi_s.h\010maxi_s.w\010" |
5027 | | "maxi_u.b\010maxi_u.d\010maxi_u.h\010maxi_u.w\004mfc0\004mfc1\004mfc2\005" |
5028 | | "mfgc0\005mfhc0\005mfhc1\005mfhc2\006mfhgc0\004mfhi\006mfhi16\004mflo\006" |
5029 | | "mflo16\006mftacx\005mftc0\005mftc1\006mftdsp\006mftgpr\006mfthc1\005mft" |
5030 | | "hi\005mftlo\004mftr\005min.d\005min.s\007min_a.b\007min_a.d\007min_a.h\007" |
5031 | | "min_a.w\007min_s.b\007min_s.d\007min_s.h\007min_s.w\007min_u.b\007min_u" |
5032 | | ".d\007min_u.h\007min_u.w\006mina.d\006mina.s\010mini_s.b\010mini_s.d\010" |
5033 | | "mini_s.h\010mini_s.w\010mini_u.b\010mini_u.d\010mini_u.h\010mini_u.w\003" |
5034 | | "mod\007mod_s.b\007mod_s.d\007mod_s.h\007mod_s.w\007mod_u.b\007mod_u.d\007" |
5035 | | "mod_u.h\007mod_u.w\006modsub\004modu\005mov.d\005mov.s\004move\006move." |
5036 | | "v\006move16\005movep\004movf\006movf.d\006movf.s\004movn\006movn.d\006m" |
5037 | | "ovn.s\004movt\006movt.d\006movt.s\004movz\006movz.d\006movz.s\004msub\006" |
5038 | | "msub.d\006msub.s\010msub_q.h\010msub_q.w\007msubf.d\007msubf.s\tmsubr_q" |
5039 | | ".h\tmsubr_q.w\005msubu\007msubv.b\007msubv.d\007msubv.h\007msubv.w\004m" |
5040 | | "tc0\004mtc1\004mtc2\005mtgc0\005mthc0\005mthc1\005mthc2\006mthgc0\004mt" |
5041 | | "hi\006mthlip\004mtlo\004mtm0\004mtm1\004mtm2\004mtp0\004mtp1\004mtp2\006" |
5042 | | "mttacx\005mttc0\005mttc1\006mttdsp\006mttgpr\006mtthc1\005mtthi\005mttl" |
5043 | | "o\004mttr\003muh\004muhu\003mul\005mul.d\006mul.ph\005mul.s\007mul_q.h\007" |
5044 | | "mul_q.w\010mul_s.ph\015muleq_s.w.phl\015muleq_s.w.phr\016muleu_s.ph.qbl" |
5045 | | "\016muleu_s.ph.qbr\004mulo\005mulou\nmulq_rs.ph\tmulq_rs.w\tmulq_s.ph\010" |
5046 | | "mulq_s.w\010mulr_q.h\010mulr_q.w\nmulsa.w.ph\015mulsaq_s.w.ph\004mult\005" |
5047 | | "multu\004mulu\006mulv.b\006mulv.d\006mulv.h\006mulv.w\003neg\005neg.d\005" |
5048 | | "neg.s\004negu\006nloc.b\006nloc.d\006nloc.h\006nloc.w\006nlzc.b\006nlzc" |
5049 | | ".d\006nlzc.h\006nlzc.w\007nmadd.d\007nmadd.s\007nmsub.d\007nmsub.s\003n" |
5050 | | "op\003nor\005nor.v\006nori.b\003not\005not16\002or\004or.v\004or16\003o" |
5051 | | "ri\005ori.b\tpackrl.ph\005pause\007pckev.b\007pckev.d\007pckev.h\007pck" |
5052 | | "ev.w\007pckod.b\007pckod.d\007pckod.h\007pckod.w\006pcnt.b\006pcnt.d\006" |
5053 | | "pcnt.h\006pcnt.w\007pick.ph\007pick.qb\006pll.ps\006plu.ps\003pop\014pr" |
5054 | | "eceq.w.phl\014preceq.w.phr\016precequ.ph.qbl\017precequ.ph.qbla\016prec" |
5055 | | "equ.ph.qbr\017precequ.ph.qbra\015preceu.ph.qbl\016preceu.ph.qbla\015pre" |
5056 | | "ceu.ph.qbr\016preceu.ph.qbra\013precr.qb.ph\016precr_sra.ph.w\020precr_" |
5057 | | "sra_r.ph.w\013precrq.ph.w\014precrq.qb.ph\016precrq_rs.ph.w\017precrqu_" |
5058 | | "s.qb.ph\004pref\005prefe\005prefx\007prepend\nraddu.w.qb\005rddsp\005rd" |
5059 | | "hwr\006rdpgpr\007recip.d\007recip.s\003rem\004remu\007repl.ph\007repl.q" |
5060 | | "b\010replv.ph\010replv.qb\006rint.d\006rint.s\003rol\003ror\004rotr\005" |
5061 | | "rotrv\tround.l.d\tround.l.s\tround.w.d\tround.w.s\007rsqrt.d\007rsqrt.s" |
5062 | | "\003s.d\003s.s\007sat_s.b\007sat_s.d\007sat_s.h\007sat_s.w\007sat_u.b\007" |
5063 | | "sat_u.d\007sat_u.h\007sat_u.w\002sb\004sb16\003sbe\002sc\003scd\003sce\002" |
5064 | | "sd\005sdbbp\007sdbbp16\004sdc1\004sdc2\004sdc3\003sdl\003sdr\005sdxc1\003" |
5065 | | "seb\003seh\005sel.d\005sel.s\006seleqz\010seleqz.d\010seleqz.s\006selne" |
5066 | | "z\010selnez.d\010selnez.s\003seq\004seqi\003sge\004sgeu\003sgt\004sgtu\002" |
5067 | | "sh\004sh16\003she\005shf.b\005shf.h\005shf.w\005shilo\006shilov\007shll" |
5068 | | ".ph\007shll.qb\tshll_s.ph\010shll_s.w\010shllv.ph\010shllv.qb\nshllv_s." |
5069 | | "ph\tshllv_s.w\007shra.ph\007shra.qb\tshra_r.ph\tshra_r.qb\010shra_r.w\010" |
5070 | | "shrav.ph\010shrav.qb\nshrav_r.ph\nshrav_r.qb\tshrav_r.w\007shrl.ph\007s" |
5071 | | "hrl.qb\010shrlv.ph\010shrlv.qb\006sigrie\005sld.b\005sld.d\005sld.h\005" |
5072 | | "sld.w\006sldi.b\006sldi.d\006sldi.h\006sldi.w\003sll\005sll.b\005sll.d\005" |
5073 | | "sll.h\005sll.w\005sll16\006slli.b\006slli.d\006slli.h\006slli.w\004sllv" |
5074 | | "\003slt\004slti\005sltiu\004sltu\003sne\004snei\007splat.b\007splat.d\007" |
5075 | | "splat.h\007splat.w\010splati.b\010splati.d\010splati.h\010splati.w\006s" |
5076 | | "qrt.d\006sqrt.s\003sra\005sra.b\005sra.d\005sra.h\005sra.w\006srai.b\006" |
5077 | | "srai.d\006srai.h\006srai.w\006srar.b\006srar.d\006srar.h\006srar.w\007s" |
5078 | | "rari.b\007srari.d\007srari.h\007srari.w\004srav\003srl\005srl.b\005srl." |
5079 | | "d\005srl.h\005srl.w\005srl16\006srli.b\006srli.d\006srli.h\006srli.w\006" |
5080 | | "srlr.b\006srlr.d\006srlr.h\006srlr.w\007srlri.b\007srlri.d\007srlri.h\007" |
5081 | | "srlri.w\004srlv\005ssnop\004st.b\004st.d\004st.h\004st.w\003sub\005sub." |
5082 | | "d\005sub.s\007subq.ph\tsubq_s.ph\010subq_s.w\010subqh.ph\007subqh.w\nsu" |
5083 | | "bqh_r.ph\tsubqh_r.w\010subs_s.b\010subs_s.d\010subs_s.h\010subs_s.w\010" |
5084 | | "subs_u.b\010subs_u.d\010subs_u.h\010subs_u.w\nsubsus_u.b\nsubsus_u.d\ns" |
5085 | | "ubsus_u.h\nsubsus_u.w\nsubsuu_s.b\nsubsuu_s.d\nsubsuu_s.h\nsubsuu_s.w\004" |
5086 | | "subu\007subu.ph\007subu.qb\006subu16\tsubu_s.ph\tsubu_s.qb\010subuh.qb\n" |
5087 | | "subuh_r.qb\006subv.b\006subv.d\006subv.h\006subv.w\007subvi.b\007subvi." |
5088 | | "d\007subvi.h\007subvi.w\005suxc1\002sw\004sw16\004swc1\004swc2\004swc3\003" |
5089 | | "swe\003swl\004swle\003swm\005swm16\005swm32\003swp\003swr\004swre\004sw" |
5090 | | "sp\005swxc1\004sync\005synci\nsynciobdma\005syncs\005syncw\006syncws\007" |
5091 | | "syscall\003teq\004teqi\003tge\004tgei\005tgeiu\004tgeu\007tlbginv\010tl" |
5092 | | "bginvf\005tlbgp\005tlbgr\006tlbgwi\006tlbgwr\006tlbinv\007tlbinvf\004tl" |
5093 | | "bp\004tlbr\005tlbwi\005tlbwr\003tlt\004tlti\005tltiu\004tltu\003tne\004" |
5094 | | "tnei\ttrunc.l.d\ttrunc.l.s\ttrunc.w.d\ttrunc.w.s\003ulh\004ulhu\003ulw\003" |
5095 | | "ush\003usw\006v3mulu\004vmm0\005vmulu\006vshf.b\006vshf.d\006vshf.h\006" |
5096 | | "vshf.w\004wait\005wrdsp\006wrpgpr\004wsbh\003xor\005xor.v\005xor16\004x" |
5097 | | "ori\006xori.b\005yield"; |
5098 | | |
5099 | | // Feature bitsets. |
5100 | | enum : uint8_t { |
5101 | | AMFBS_None, |
5102 | | AMFBS_HasCnMips, |
5103 | | AMFBS_HasDSP, |
5104 | | AMFBS_HasDSPR2, |
5105 | | AMFBS_HasMT, |
5106 | | AMFBS_InMicroMips, |
5107 | | AMFBS_InMips16Mode, |
5108 | | AMFBS_IsGP32bit, |
5109 | | AMFBS_IsGP64bit, |
5110 | | AMFBS_IsNotSoftFloat, |
5111 | | AMFBS_NotCnMips, |
5112 | | AMFBS_NotInMicroMips, |
5113 | | AMFBS_HasDSP_InMicroMips, |
5114 | | AMFBS_HasDSP_NotInMicroMips, |
5115 | | AMFBS_HasMT_NotInMicroMips, |
5116 | | AMFBS_HasMips64_HasCnMips, |
5117 | | AMFBS_HasStdEnc_HasMSA, |
5118 | | AMFBS_HasStdEnc_HasMips3, |
5119 | | AMFBS_HasStdEnc_HasMips32, |
5120 | | AMFBS_HasStdEnc_HasMips32r6, |
5121 | | AMFBS_HasStdEnc_HasMips64, |
5122 | | AMFBS_HasStdEnc_HasMips64r6, |
5123 | | AMFBS_HasStdEnc_IsNotSoftFloat, |
5124 | | AMFBS_HasStdEnc_NotInMicroMips, |
5125 | | AMFBS_HasStdEnc_NotMips3, |
5126 | | AMFBS_InMicroMips_HasDSP, |
5127 | | AMFBS_InMicroMips_HasDSPR2, |
5128 | | AMFBS_InMicroMips_HasDSPR3, |
5129 | | AMFBS_InMicroMips_HasEVA, |
5130 | | AMFBS_InMicroMips_HasMips32r6, |
5131 | | AMFBS_InMicroMips_IsNotSoftFloat, |
5132 | | AMFBS_InMicroMips_NotMips32r6, |
5133 | | AMFBS_IsFP64bit_IsNotSoftFloat, |
5134 | | AMFBS_IsGP32bit_NotInMicroMips, |
5135 | | AMFBS_IsGP64bit_NotInMicroMips, |
5136 | | AMFBS_NotFP64bit_IsNotSoftFloat, |
5137 | | AMFBS_NotInMips16Mode_HasDSP, |
5138 | | AMFBS_NotInMips16Mode_IsPTR64bit, |
5139 | | AMFBS_HasMips3_NotMips64r6_NotCnMips, |
5140 | | AMFBS_HasMips64_HasCnMips_NotInMicroMips, |
5141 | | AMFBS_HasStdEnc_HasMSA_HasMips64, |
5142 | | AMFBS_HasStdEnc_HasMT_NotInMicroMips, |
5143 | | AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat, |
5144 | | AMFBS_HasStdEnc_HasMips2_NotInMicroMips, |
5145 | | AMFBS_HasStdEnc_HasMips3_NotInMicroMips, |
5146 | | AMFBS_HasStdEnc_HasMips32_NotInMicroMips, |
5147 | | AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, |
5148 | | AMFBS_HasStdEnc_HasMips32r5_NotInMicroMips, |
5149 | | AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, |
5150 | | AMFBS_HasStdEnc_HasMips3_32_NotInMicroMips, |
5151 | | AMFBS_HasStdEnc_HasMips64_NotInMicroMips, |
5152 | | AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, |
5153 | | AMFBS_HasStdEnc_HasMips64r5_HasVirt, |
5154 | | AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, |
5155 | | AMFBS_HasStdEnc_IsGP32bit_HasMips32r6, |
5156 | | AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, |
5157 | | AMFBS_HasStdEnc_IsGP64bit_HasMips3, |
5158 | | AMFBS_HasStdEnc_IsGP64bit_HasMips32r6, |
5159 | | AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, |
5160 | | AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
5161 | | AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, |
5162 | | AMFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, |
5163 | | AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, |
5164 | | AMFBS_InMicroMips_HasMips32r5_HasVirt, |
5165 | | AMFBS_InMicroMips_HasMips32r6_HasGINV, |
5166 | | AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, |
5167 | | AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, |
5168 | | AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, |
5169 | | AMFBS_InMicroMips_NotMips32r6_HasDSP, |
5170 | | AMFBS_InMicroMips_NotMips32r6_HasEVA, |
5171 | | AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, |
5172 | | AMFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, |
5173 | | AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, |
5174 | | AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, |
5175 | | AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, |
5176 | | AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, |
5177 | | AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, |
5178 | | AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, |
5179 | | AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, |
5180 | | AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, |
5181 | | AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, |
5182 | | AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, |
5183 | | AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, |
5184 | | AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, |
5185 | | AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, |
5186 | | AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, |
5187 | | AMFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, |
5188 | | AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips, |
5189 | | AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, |
5190 | | AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat, |
5191 | | AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, |
5192 | | AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, |
5193 | | AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, |
5194 | | AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, |
5195 | | AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, |
5196 | | AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat, |
5197 | | AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, |
5198 | | AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, |
5199 | | AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, |
5200 | | AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, |
5201 | | AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, |
5202 | | AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, |
5203 | | AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, |
5204 | | AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, |
5205 | | AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, |
5206 | | AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, |
5207 | | AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, |
5208 | | AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, |
5209 | | AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, |
5210 | | AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, |
5211 | | AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, |
5212 | | AMFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, |
5213 | | AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, |
5214 | | AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, |
5215 | | AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, |
5216 | | AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, |
5217 | | AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, |
5218 | | AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
5219 | | AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, |
5220 | | AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, |
5221 | | AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
5222 | | AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, |
5223 | | AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
5224 | | AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, |
5225 | | AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
5226 | | AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, |
5227 | | AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, |
5228 | | AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
5229 | | AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, |
5230 | | AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, |
5231 | | AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
5232 | | AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
5233 | | AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
5234 | | AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
5235 | | AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
5236 | | AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
5237 | | AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, |
5238 | | AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, |
5239 | | AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, |
5240 | | AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, |
5241 | | }; |
5242 | | |
5243 | | const static FeatureBitset FeatureBitsets[] { |
5244 | | {}, // AMFBS_None |
5245 | | {Feature_HasCnMipsBit, }, |
5246 | | {Feature_HasDSPBit, }, |
5247 | | {Feature_HasDSPR2Bit, }, |
5248 | | {Feature_HasMTBit, }, |
5249 | | {Feature_InMicroMipsBit, }, |
5250 | | {Feature_InMips16ModeBit, }, |
5251 | | {Feature_IsGP32bitBit, }, |
5252 | | {Feature_IsGP64bitBit, }, |
5253 | | {Feature_IsNotSoftFloatBit, }, |
5254 | | {Feature_NotCnMipsBit, }, |
5255 | | {Feature_NotInMicroMipsBit, }, |
5256 | | {Feature_HasDSPBit, Feature_InMicroMipsBit, }, |
5257 | | {Feature_HasDSPBit, Feature_NotInMicroMipsBit, }, |
5258 | | {Feature_HasMTBit, Feature_NotInMicroMipsBit, }, |
5259 | | {Feature_HasMips64Bit, Feature_HasCnMipsBit, }, |
5260 | | {Feature_HasStdEncBit, Feature_HasMSABit, }, |
5261 | | {Feature_HasStdEncBit, Feature_HasMips3Bit, }, |
5262 | | {Feature_HasStdEncBit, Feature_HasMips32Bit, }, |
5263 | | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, }, |
5264 | | {Feature_HasStdEncBit, Feature_HasMips64Bit, }, |
5265 | | {Feature_HasStdEncBit, Feature_HasMips64r6Bit, }, |
5266 | | {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, }, |
5267 | | {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, |
5268 | | {Feature_HasStdEncBit, Feature_NotMips3Bit, }, |
5269 | | {Feature_InMicroMipsBit, Feature_HasDSPBit, }, |
5270 | | {Feature_InMicroMipsBit, Feature_HasDSPR2Bit, }, |
5271 | | {Feature_InMicroMipsBit, Feature_HasDSPR3Bit, }, |
5272 | | {Feature_InMicroMipsBit, Feature_HasEVABit, }, |
5273 | | {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, }, |
5274 | | {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, }, |
5275 | | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, }, |
5276 | | {Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, }, |
5277 | | {Feature_IsGP32bitBit, Feature_NotInMicroMipsBit, }, |
5278 | | {Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, }, |
5279 | | {Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, |
5280 | | {Feature_NotInMips16ModeBit, Feature_HasDSPBit, }, |
5281 | | {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, }, |
5282 | | {Feature_HasMips3Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, }, |
5283 | | {Feature_HasMips64Bit, Feature_HasCnMipsBit, Feature_NotInMicroMipsBit, }, |
5284 | | {Feature_HasStdEncBit, Feature_HasMSABit, Feature_HasMips64Bit, }, |
5285 | | {Feature_HasStdEncBit, Feature_HasMTBit, Feature_NotInMicroMipsBit, }, |
5286 | | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, }, |
5287 | | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotInMicroMipsBit, }, |
5288 | | {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotInMicroMipsBit, }, |
5289 | | {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotInMicroMipsBit, }, |
5290 | | {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotInMicroMipsBit, }, |
5291 | | {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_NotInMicroMipsBit, }, |
5292 | | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, |
5293 | | {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotInMicroMipsBit, }, |
5294 | | {Feature_HasStdEncBit, Feature_HasMips64Bit, Feature_NotInMicroMipsBit, }, |
5295 | | {Feature_HasStdEncBit, Feature_HasMips64r2Bit, Feature_NotInMicroMipsBit, }, |
5296 | | {Feature_HasStdEncBit, Feature_HasMips64r5Bit, Feature_HasVirtBit, }, |
5297 | | {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, }, |
5298 | | {Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_HasMips32r6Bit, }, |
5299 | | {Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_NotInMicroMipsBit, }, |
5300 | | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips3Bit, }, |
5301 | | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r6Bit, }, |
5302 | | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64r6Bit, }, |
5303 | | {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
5304 | | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, |
5305 | | {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, |
5306 | | {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
5307 | | {Feature_InMicroMipsBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, }, |
5308 | | {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, }, |
5309 | | {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
5310 | | {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, }, |
5311 | | {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, |
5312 | | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasDSPBit, }, |
5313 | | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasEVABit, }, |
5314 | | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
5315 | | {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NotInMicroMipsBit, }, |
5316 | | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
5317 | | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, }, |
5318 | | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
5319 | | {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
5320 | | {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
5321 | | {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
5322 | | {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, }, |
5323 | | {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
5324 | | {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, Feature_NotInMicroMipsBit, }, |
5325 | | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, }, |
5326 | | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, Feature_NotInMicroMipsBit, }, |
5327 | | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
5328 | | {Feature_HasStdEncBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
5329 | | {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
5330 | | {Feature_HasStdEncBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
5331 | | {Feature_HasStdEncBit, Feature_HasMips64r5Bit, Feature_HasVirtBit, Feature_NotInMicroMipsBit, }, |
5332 | | {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, }, |
5333 | | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, }, |
5334 | | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
5335 | | {Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, |
5336 | | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips3Bit, Feature_NotInMicroMipsBit, }, |
5337 | | {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, |
5338 | | {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, }, |
5339 | | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, }, |
5340 | | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
5341 | | {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
5342 | | {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
5343 | | {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
5344 | | {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
5345 | | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, }, |
5346 | | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
5347 | | {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
5348 | | {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
5349 | | {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
5350 | | {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
5351 | | {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, |
5352 | | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
5353 | | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
5354 | | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
5355 | | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
5356 | | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
5357 | | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
5358 | | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
5359 | | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
5360 | | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
5361 | | {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
5362 | | {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, }, |
5363 | | {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, }, |
5364 | | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
5365 | | {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, }, |
5366 | | {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
5367 | | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, |
5368 | | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
5369 | | {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
5370 | | {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
5371 | | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
5372 | | {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, |
5373 | | {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, |
5374 | | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
5375 | | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
5376 | | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
5377 | | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
5378 | | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
5379 | | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
5380 | | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, |
5381 | | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, |
5382 | | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, |
5383 | | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, |
5384 | | }; |
5385 | | |
5386 | | namespace { |
5387 | | struct MatchEntry { |
5388 | | uint16_t Mnemonic; |
5389 | | uint16_t Opcode; |
5390 | | uint16_t ConvertFn; |
5391 | | uint8_t RequiredFeaturesIdx; |
5392 | | uint8_t Classes[8]; |
5393 | 1.89M | StringRef getMnemonic() const { |
5394 | 1.89M | return StringRef(MnemonicTable + Mnemonic + 1, |
5395 | 1.89M | MnemonicTable[Mnemonic]); |
5396 | 1.89M | } |
5397 | | }; |
5398 | | |
5399 | | // Predicate for searching for an opcode. |
5400 | | struct LessOpcode { |
5401 | 946k | bool operator()(const MatchEntry &LHS, StringRef RHS) { |
5402 | 946k | return LHS.getMnemonic() < RHS; |
5403 | 946k | } |
5404 | 668k | bool operator()(StringRef LHS, const MatchEntry &RHS) { |
5405 | 668k | return LHS < RHS.getMnemonic(); |
5406 | 668k | } |
5407 | 0 | bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) { |
5408 | 0 | return LHS.getMnemonic() < RHS.getMnemonic(); |
5409 | 0 | } |
5410 | | }; |
5411 | | } // end anonymous namespace. |
5412 | | |
5413 | | static const MatchEntry MatchTable0[] = { |
5414 | | { 0 /* abs */, Mips::ABSMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5415 | | { 4 /* abs.d */, Mips::FABS_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5416 | | { 4 /* abs.d */, Mips::FABS_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5417 | | { 4 /* abs.d */, Mips::FABS_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5418 | | { 4 /* abs.d */, Mips::FABS_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5419 | | { 10 /* abs.s */, Mips::FABS_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5420 | | { 10 /* abs.s */, Mips::FABS_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5421 | | { 16 /* absq_s.ph */, Mips::ABSQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5422 | | { 16 /* absq_s.ph */, Mips::ABSQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5423 | | { 26 /* absq_s.qb */, Mips::ABSQ_S_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5424 | | { 26 /* absq_s.qb */, Mips::ABSQ_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5425 | | { 36 /* absq_s.w */, Mips::ABSQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5426 | | { 36 /* absq_s.w */, Mips::ABSQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5427 | | { 45 /* add */, Mips::ADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5428 | | { 45 /* add */, Mips::ADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5429 | | { 45 /* add */, Mips::ADD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5430 | | { 45 /* add */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
5431 | | { 45 /* add */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
5432 | | { 45 /* add */, Mips::ADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5433 | | { 45 /* add */, Mips::ADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5434 | | { 45 /* add */, Mips::ADD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5435 | | { 45 /* add */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
5436 | | { 45 /* add */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
5437 | | { 49 /* add.d */, Mips::FADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5438 | | { 49 /* add.d */, Mips::FADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5439 | | { 49 /* add.d */, Mips::FADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5440 | | { 49 /* add.d */, Mips::FADD_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5441 | | { 55 /* add.s */, Mips::FADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5442 | | { 55 /* add.s */, Mips::FADD_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5443 | | { 55 /* add.s */, Mips::FADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5444 | | { 61 /* add_a.b */, Mips::ADD_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5445 | | { 69 /* add_a.d */, Mips::ADD_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5446 | | { 77 /* add_a.h */, Mips::ADD_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5447 | | { 85 /* add_a.w */, Mips::ADD_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5448 | | { 93 /* addi */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
5449 | | { 93 /* addi */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, }, |
5450 | | { 93 /* addi */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, |
5451 | | { 93 /* addi */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, }, |
5452 | | { 98 /* addiu */, Mips::AddiuSpImmX16, Convert__SImm161_1, AMFBS_InMips16Mode, { MCK_CPUSPReg, MCK_SImm16 }, }, |
5453 | | { 98 /* addiu */, Mips::AddiuRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, }, |
5454 | | { 98 /* addiu */, Mips::ADDIU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
5455 | | { 98 /* addiu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
5456 | | { 98 /* addiu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, }, |
5457 | | { 98 /* addiu */, Mips::AddiuRxPcImmX16, Convert__Reg1_0__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_PC, MCK_SImm16 }, }, |
5458 | | { 98 /* addiu */, Mips::AddiuRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, }, |
5459 | | { 98 /* addiu */, Mips::ADDIU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, |
5460 | | { 98 /* addiu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, |
5461 | | { 98 /* addiu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, }, |
5462 | | { 98 /* addiu */, Mips::AddiuSpImm16, Convert__SImm161_1, AMFBS_InMips16Mode, { MCK_CPUSPReg, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, }, |
5463 | | { 98 /* addiu */, Mips::AddiuRxRxImm16, Convert__Reg1_0__Tie0_1_1__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, }, |
5464 | | { 104 /* addiupc */, Mips::ADDIUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, |
5465 | | { 104 /* addiupc */, Mips::ADDIUPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, |
5466 | | { 104 /* addiupc */, Mips::ADDIUPC_MM, Convert__GPRMM16AsmReg1_0__Imm1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_Imm }, }, |
5467 | | { 112 /* addiur1sp */, Mips::ADDIUR1SP_MM, Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_UImm6Lsl2 }, }, |
5468 | | { 122 /* addiur2 */, Mips::ADDIUR2_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, |
5469 | | { 130 /* addius5 */, Mips::ADDIUS5_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantSImm4_0 }, }, |
5470 | | { 138 /* addiusp */, Mips::ADDIUSP_MM, Convert__Imm1_0, AMFBS_InMicroMips, { MCK_Imm }, }, |
5471 | | { 146 /* addq.ph */, Mips::ADDQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5472 | | { 146 /* addq.ph */, Mips::ADDQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5473 | | { 154 /* addq_s.ph */, Mips::ADDQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5474 | | { 154 /* addq_s.ph */, Mips::ADDQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5475 | | { 164 /* addq_s.w */, Mips::ADDQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5476 | | { 164 /* addq_s.w */, Mips::ADDQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5477 | | { 173 /* addqh.ph */, Mips::ADDQH_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5478 | | { 173 /* addqh.ph */, Mips::ADDQH_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5479 | | { 182 /* addqh.w */, Mips::ADDQH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5480 | | { 182 /* addqh.w */, Mips::ADDQH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5481 | | { 190 /* addqh_r.ph */, Mips::ADDQH_R_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5482 | | { 190 /* addqh_r.ph */, Mips::ADDQH_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5483 | | { 201 /* addqh_r.w */, Mips::ADDQH_R_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5484 | | { 201 /* addqh_r.w */, Mips::ADDQH_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5485 | | { 211 /* adds_a.b */, Mips::ADDS_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5486 | | { 220 /* adds_a.d */, Mips::ADDS_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5487 | | { 229 /* adds_a.h */, Mips::ADDS_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5488 | | { 238 /* adds_a.w */, Mips::ADDS_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5489 | | { 247 /* adds_s.b */, Mips::ADDS_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5490 | | { 256 /* adds_s.d */, Mips::ADDS_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5491 | | { 265 /* adds_s.h */, Mips::ADDS_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5492 | | { 274 /* adds_s.w */, Mips::ADDS_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5493 | | { 283 /* adds_u.b */, Mips::ADDS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5494 | | { 292 /* adds_u.d */, Mips::ADDS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5495 | | { 301 /* adds_u.h */, Mips::ADDS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5496 | | { 310 /* adds_u.w */, Mips::ADDS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5497 | | { 319 /* addsc */, Mips::ADDSC_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5498 | | { 319 /* addsc */, Mips::ADDSC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5499 | | { 325 /* addu */, Mips::ADDU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5500 | | { 325 /* addu */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5501 | | { 325 /* addu */, Mips::ADDu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5502 | | { 325 /* addu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
5503 | | { 325 /* addu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
5504 | | { 325 /* addu */, Mips::AdduRxRyRz16, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_CPU16Regs }, }, |
5505 | | { 325 /* addu */, Mips::ADDU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5506 | | { 325 /* addu */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5507 | | { 325 /* addu */, Mips::ADDu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5508 | | { 325 /* addu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
5509 | | { 325 /* addu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
5510 | | { 330 /* addu.ph */, Mips::ADDU_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5511 | | { 330 /* addu.ph */, Mips::ADDU_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5512 | | { 338 /* addu.qb */, Mips::ADDU_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5513 | | { 338 /* addu.qb */, Mips::ADDU_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5514 | | { 346 /* addu16 */, Mips::ADDU16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, |
5515 | | { 346 /* addu16 */, Mips::ADDU16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, |
5516 | | { 353 /* addu_s.ph */, Mips::ADDU_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5517 | | { 353 /* addu_s.ph */, Mips::ADDU_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5518 | | { 363 /* addu_s.qb */, Mips::ADDU_S_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5519 | | { 363 /* addu_s.qb */, Mips::ADDU_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5520 | | { 373 /* adduh.qb */, Mips::ADDUH_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5521 | | { 373 /* adduh.qb */, Mips::ADDUH_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5522 | | { 382 /* adduh_r.qb */, Mips::ADDUH_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5523 | | { 382 /* adduh_r.qb */, Mips::ADDUH_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5524 | | { 393 /* addv.b */, Mips::ADDV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5525 | | { 400 /* addv.d */, Mips::ADDV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5526 | | { 407 /* addv.h */, Mips::ADDV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5527 | | { 414 /* addv.w */, Mips::ADDV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5528 | | { 421 /* addvi.b */, Mips::ADDVI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
5529 | | { 429 /* addvi.d */, Mips::ADDVI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
5530 | | { 437 /* addvi.h */, Mips::ADDVI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
5531 | | { 445 /* addvi.w */, Mips::ADDVI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
5532 | | { 453 /* addwc */, Mips::ADDWC_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5533 | | { 453 /* addwc */, Mips::ADDWC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5534 | | { 459 /* align */, Mips::ALIGN, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, }, |
5535 | | { 459 /* align */, Mips::ALIGN_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, }, |
5536 | | { 465 /* aluipc */, Mips::ALUIPC, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
5537 | | { 465 /* aluipc */, Mips::ALUIPC_MMR6, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
5538 | | { 472 /* and */, Mips::AndRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, |
5539 | | { 472 /* and */, Mips::AND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5540 | | { 472 /* and */, Mips::AND_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5541 | | { 472 /* and */, Mips::AND_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5542 | | { 472 /* and */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, |
5543 | | { 472 /* and */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
5544 | | { 472 /* and */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
5545 | | { 472 /* and */, Mips::ANDi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, }, |
5546 | | { 472 /* and */, Mips::AND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5547 | | { 472 /* and */, Mips::AND_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5548 | | { 472 /* and */, Mips::AND_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5549 | | { 472 /* and */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
5550 | | { 472 /* and */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
5551 | | { 472 /* and */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
5552 | | { 472 /* and */, Mips::ANDi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, |
5553 | | { 476 /* and.v */, Mips::AND_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5554 | | { 482 /* and16 */, Mips::AND16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, |
5555 | | { 482 /* and16 */, Mips::AND16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, |
5556 | | { 488 /* andi */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, |
5557 | | { 488 /* andi */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, }, |
5558 | | { 488 /* andi */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, |
5559 | | { 488 /* andi */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
5560 | | { 488 /* andi */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
5561 | | { 488 /* andi */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
5562 | | { 493 /* andi.b */, Mips::ANDI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, |
5563 | | { 500 /* andi16 */, Mips::ANDI16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, |
5564 | | { 500 /* andi16 */, Mips::ANDI16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, |
5565 | | { 507 /* append */, Mips::APPEND_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
5566 | | { 507 /* append */, Mips::APPEND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
5567 | | { 514 /* asub_s.b */, Mips::ASUB_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5568 | | { 523 /* asub_s.d */, Mips::ASUB_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5569 | | { 532 /* asub_s.h */, Mips::ASUB_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5570 | | { 541 /* asub_s.w */, Mips::ASUB_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5571 | | { 550 /* asub_u.b */, Mips::ASUB_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5572 | | { 559 /* asub_u.d */, Mips::ASUB_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5573 | | { 568 /* asub_u.h */, Mips::ASUB_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5574 | | { 577 /* asub_u.w */, Mips::ASUB_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5575 | | { 586 /* aui */, Mips::AUI, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
5576 | | { 586 /* aui */, Mips::AUI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
5577 | | { 590 /* auipc */, Mips::AUIPC, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
5578 | | { 590 /* auipc */, Mips::AUIPC_MMR6, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
5579 | | { 596 /* ave_s.b */, Mips::AVE_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5580 | | { 604 /* ave_s.d */, Mips::AVE_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5581 | | { 612 /* ave_s.h */, Mips::AVE_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5582 | | { 620 /* ave_s.w */, Mips::AVE_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5583 | | { 628 /* ave_u.b */, Mips::AVE_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5584 | | { 636 /* ave_u.d */, Mips::AVE_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5585 | | { 644 /* ave_u.h */, Mips::AVE_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5586 | | { 652 /* ave_u.w */, Mips::AVE_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5587 | | { 660 /* aver_s.b */, Mips::AVER_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5588 | | { 669 /* aver_s.d */, Mips::AVER_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5589 | | { 678 /* aver_s.h */, Mips::AVER_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5590 | | { 687 /* aver_s.w */, Mips::AVER_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5591 | | { 696 /* aver_u.b */, Mips::AVER_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5592 | | { 705 /* aver_u.d */, Mips::AVER_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5593 | | { 714 /* aver_u.h */, Mips::AVER_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5594 | | { 723 /* aver_u.w */, Mips::AVER_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5595 | | { 732 /* b */, Mips::BEQ, Convert__regZERO__regZERO__JumpTarget1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_JumpTarget }, }, |
5596 | | { 732 /* b */, Mips::B_MM_Pseudo, Convert__JumpTarget1_0, AMFBS_InMicroMips, { MCK_JumpTarget }, }, |
5597 | | { 732 /* b */, Mips::BimmX16, Convert__JumpTarget1_0, AMFBS_InMips16Mode, { MCK_JumpTarget }, }, |
5598 | | { 732 /* b */, Mips::B_MMR6_Pseudo, Convert__JumpTarget1_0, AMFBS_None, { MCK_JumpTarget }, }, |
5599 | | { 732 /* b */, Mips::Bimm16, Convert__JumpTarget1_0, AMFBS_InMips16Mode, { MCK_JumpTarget, MCK__35_, MCK_16, MCK_bit, MCK_inst }, }, |
5600 | | { 734 /* b16 */, Mips::BC16_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, }, |
5601 | | { 734 /* b16 */, Mips::B16_MM, Convert__JumpTarget1_0, AMFBS_InMicroMips, { MCK_JumpTarget }, }, |
5602 | | { 738 /* baddu */, Mips::BADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
5603 | | { 738 /* baddu */, Mips::BADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
5604 | | { 744 /* bal */, Mips::BGEZAL, Convert__regZERO__JumpTarget1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_JumpTarget }, }, |
5605 | | { 744 /* bal */, Mips::BAL, Convert__JumpTarget1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_JumpTarget }, }, |
5606 | | { 744 /* bal */, Mips::BGEZAL_MM, Convert__regZERO__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_JumpTarget }, }, |
5607 | | { 748 /* balc */, Mips::BALC, Convert__JumpTarget1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_JumpTarget }, }, |
5608 | | { 748 /* balc */, Mips::BALC_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, }, |
5609 | | { 753 /* balign */, Mips::BALIGN_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, }, |
5610 | | { 753 /* balign */, Mips::BALIGN, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, }, |
5611 | | { 760 /* bbit0 */, Mips::BBIT032, Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_JumpTarget }, }, |
5612 | | { 760 /* bbit0 */, Mips::BBIT0, Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_JumpTarget }, }, |
5613 | | { 766 /* bbit032 */, Mips::BBIT032, Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_JumpTarget }, }, |
5614 | | { 774 /* bbit1 */, Mips::BBIT132, Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_JumpTarget }, }, |
5615 | | { 774 /* bbit1 */, Mips::BBIT1, Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_JumpTarget }, }, |
5616 | | { 780 /* bbit132 */, Mips::BBIT132, Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_JumpTarget }, }, |
5617 | | { 788 /* bc */, Mips::BC, Convert__JumpTarget1_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_JumpTarget }, }, |
5618 | | { 788 /* bc */, Mips::BC_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, }, |
5619 | | { 791 /* bc16 */, Mips::BC16_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, }, |
5620 | | { 796 /* bc1eqz */, Mips::BC1EQZ, Convert__FGR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_JumpTarget }, }, |
5621 | | { 803 /* bc1eqzc */, Mips::BC1EQZC_MMR6, Convert__FGR64AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_JumpTarget }, }, |
5622 | | { 811 /* bc1f */, Mips::BC1F, Convert__regFCC0__JumpTarget1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_JumpTarget }, }, |
5623 | | { 811 /* bc1f */, Mips::BC1F_MM, Convert__regFCC0__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_JumpTarget }, }, |
5624 | | { 811 /* bc1f */, Mips::BC1F, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, }, |
5625 | | { 811 /* bc1f */, Mips::BC1F_MM, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, }, |
5626 | | { 816 /* bc1fl */, Mips::BC1FL, Convert__regFCC0__JumpTarget1_0, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_JumpTarget }, }, |
5627 | | { 816 /* bc1fl */, Mips::BC1FL, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, }, |
5628 | | { 822 /* bc1nez */, Mips::BC1NEZ, Convert__FGR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_JumpTarget }, }, |
5629 | | { 829 /* bc1nezc */, Mips::BC1NEZC_MMR6, Convert__FGR64AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_JumpTarget }, }, |
5630 | | { 837 /* bc1t */, Mips::BC1T, Convert__regFCC0__JumpTarget1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_JumpTarget }, }, |
5631 | | { 837 /* bc1t */, Mips::BC1T_MM, Convert__regFCC0__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_JumpTarget }, }, |
5632 | | { 837 /* bc1t */, Mips::BC1T, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, }, |
5633 | | { 837 /* bc1t */, Mips::BC1T_MM, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, }, |
5634 | | { 842 /* bc1tl */, Mips::BC1TL, Convert__regFCC0__JumpTarget1_0, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_JumpTarget }, }, |
5635 | | { 842 /* bc1tl */, Mips::BC1TL, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, }, |
5636 | | { 848 /* bc2eqz */, Mips::BC2EQZ, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_JumpTarget }, }, |
5637 | | { 855 /* bc2eqzc */, Mips::BC2EQZC_MMR6, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_JumpTarget }, }, |
5638 | | { 863 /* bc2nez */, Mips::BC2NEZ, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_JumpTarget }, }, |
5639 | | { 870 /* bc2nezc */, Mips::BC2NEZC_MMR6, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_JumpTarget }, }, |
5640 | | { 878 /* bclr.b */, Mips::BCLR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5641 | | { 885 /* bclr.d */, Mips::BCLR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5642 | | { 892 /* bclr.h */, Mips::BCLR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5643 | | { 899 /* bclr.w */, Mips::BCLR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5644 | | { 906 /* bclri.b */, Mips::BCLRI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, |
5645 | | { 914 /* bclri.d */, Mips::BCLRI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, |
5646 | | { 922 /* bclri.h */, Mips::BCLRI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, |
5647 | | { 930 /* bclri.w */, Mips::BCLRI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
5648 | | { 938 /* beq */, Mips::BEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5649 | | { 938 /* beq */, Mips::BEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5650 | | { 938 /* beq */, Mips::BeqImm, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
5651 | | { 942 /* beqc */, Mips::BEQC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5652 | | { 942 /* beqc */, Mips::BEQC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5653 | | { 942 /* beqc */, Mips::BEQC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
5654 | | { 947 /* beql */, Mips::BEQL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5655 | | { 947 /* beql */, Mips::BEQLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
5656 | | { 952 /* beqz */, Mips::BeqzRxImmX16, Convert__Reg1_0__JumpTarget1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget }, }, |
5657 | | { 952 /* beqz */, Mips::BEQ, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5658 | | { 952 /* beqz */, Mips::BEQ_MM, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5659 | | { 952 /* beqz */, Mips::BeqzRxImm16, Convert__Reg1_0__JumpTarget1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget, MCK__35_, MCK_16, MCK_bit, MCK_inst }, }, |
5660 | | { 957 /* beqz16 */, Mips::BEQZ16_MM, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, }, |
5661 | | { 957 /* beqz16 */, Mips::BEQZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, }, |
5662 | | { 964 /* beqzalc */, Mips::BEQZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5663 | | { 964 /* beqzalc */, Mips::BEQZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5664 | | { 972 /* beqzc */, Mips::BEQZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5665 | | { 972 /* beqzc */, Mips::BEQZC_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5666 | | { 972 /* beqzc */, Mips::BEQZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5667 | | { 972 /* beqzc */, Mips::BEQZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
5668 | | { 978 /* beqzc16 */, Mips::BEQZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, }, |
5669 | | { 986 /* beqzl */, Mips::BEQL, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5670 | | { 992 /* bge */, Mips::BGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5671 | | { 992 /* bge */, Mips::BGEImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
5672 | | { 996 /* bgec */, Mips::BGEC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5673 | | { 996 /* bgec */, Mips::BGEC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5674 | | { 996 /* bgec */, Mips::BGEC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
5675 | | { 1001 /* bgel */, Mips::BGEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5676 | | { 1001 /* bgel */, Mips::BGELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
5677 | | { 1006 /* bgeu */, Mips::BGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5678 | | { 1006 /* bgeu */, Mips::BGEUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
5679 | | { 1011 /* bgeuc */, Mips::BGEUC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5680 | | { 1011 /* bgeuc */, Mips::BGEUC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5681 | | { 1011 /* bgeuc */, Mips::BGEUC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
5682 | | { 1017 /* bgeul */, Mips::BGEUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5683 | | { 1017 /* bgeul */, Mips::BGEULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
5684 | | { 1023 /* bgez */, Mips::BGEZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5685 | | { 1023 /* bgez */, Mips::BGEZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5686 | | { 1028 /* bgezal */, Mips::BGEZAL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5687 | | { 1028 /* bgezal */, Mips::BGEZAL_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5688 | | { 1035 /* bgezalc */, Mips::BGEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5689 | | { 1035 /* bgezalc */, Mips::BGEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5690 | | { 1043 /* bgezall */, Mips::BGEZALL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5691 | | { 1051 /* bgezals */, Mips::BGEZALS_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5692 | | { 1059 /* bgezc */, Mips::BGEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5693 | | { 1059 /* bgezc */, Mips::BGEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5694 | | { 1059 /* bgezc */, Mips::BGEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
5695 | | { 1065 /* bgezl */, Mips::BGEZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5696 | | { 1071 /* bgt */, Mips::BGT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5697 | | { 1071 /* bgt */, Mips::BGTImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
5698 | | { 1075 /* bgtl */, Mips::BGTL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5699 | | { 1075 /* bgtl */, Mips::BGTLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
5700 | | { 1080 /* bgtu */, Mips::BGTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5701 | | { 1080 /* bgtu */, Mips::BGTUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
5702 | | { 1085 /* bgtul */, Mips::BGTUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5703 | | { 1085 /* bgtul */, Mips::BGTULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
5704 | | { 1091 /* bgtz */, Mips::BGTZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5705 | | { 1091 /* bgtz */, Mips::BGTZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5706 | | { 1096 /* bgtzalc */, Mips::BGTZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5707 | | { 1096 /* bgtzalc */, Mips::BGTZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5708 | | { 1104 /* bgtzc */, Mips::BGTZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5709 | | { 1104 /* bgtzc */, Mips::BGTZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5710 | | { 1104 /* bgtzc */, Mips::BGTZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
5711 | | { 1110 /* bgtzl */, Mips::BGTZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5712 | | { 1116 /* binsl.b */, Mips::BINSL_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5713 | | { 1124 /* binsl.d */, Mips::BINSL_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5714 | | { 1132 /* binsl.h */, Mips::BINSL_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5715 | | { 1140 /* binsl.w */, Mips::BINSL_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5716 | | { 1148 /* binsli.b */, Mips::BINSLI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, |
5717 | | { 1157 /* binsli.d */, Mips::BINSLI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, |
5718 | | { 1166 /* binsli.h */, Mips::BINSLI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, |
5719 | | { 1175 /* binsli.w */, Mips::BINSLI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
5720 | | { 1184 /* binsr.b */, Mips::BINSR_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5721 | | { 1192 /* binsr.d */, Mips::BINSR_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5722 | | { 1200 /* binsr.h */, Mips::BINSR_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5723 | | { 1208 /* binsr.w */, Mips::BINSR_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5724 | | { 1216 /* binsri.b */, Mips::BINSRI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, |
5725 | | { 1225 /* binsri.d */, Mips::BINSRI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, |
5726 | | { 1234 /* binsri.h */, Mips::BINSRI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, |
5727 | | { 1243 /* binsri.w */, Mips::BINSRI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
5728 | | { 1252 /* bitrev */, Mips::BITREV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5729 | | { 1252 /* bitrev */, Mips::BITREV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5730 | | { 1259 /* bitswap */, Mips::BITSWAP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5731 | | { 1259 /* bitswap */, Mips::BITSWAP_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
5732 | | { 1267 /* ble */, Mips::BLE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5733 | | { 1267 /* ble */, Mips::BLEImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
5734 | | { 1271 /* blel */, Mips::BLEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5735 | | { 1271 /* blel */, Mips::BLELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
5736 | | { 1276 /* bleu */, Mips::BLEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5737 | | { 1276 /* bleu */, Mips::BLEUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
5738 | | { 1281 /* bleul */, Mips::BLEUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5739 | | { 1281 /* bleul */, Mips::BLEULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
5740 | | { 1287 /* blez */, Mips::BLEZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5741 | | { 1287 /* blez */, Mips::BLEZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5742 | | { 1292 /* blezalc */, Mips::BLEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5743 | | { 1292 /* blezalc */, Mips::BLEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5744 | | { 1300 /* blezc */, Mips::BLEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5745 | | { 1300 /* blezc */, Mips::BLEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5746 | | { 1300 /* blezc */, Mips::BLEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
5747 | | { 1306 /* blezl */, Mips::BLEZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5748 | | { 1312 /* blt */, Mips::BLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5749 | | { 1312 /* blt */, Mips::BLTImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
5750 | | { 1316 /* bltc */, Mips::BLTC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5751 | | { 1316 /* bltc */, Mips::BLTC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5752 | | { 1316 /* bltc */, Mips::BLTC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
5753 | | { 1321 /* bltl */, Mips::BLTL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5754 | | { 1321 /* bltl */, Mips::BLTLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
5755 | | { 1326 /* bltu */, Mips::BLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5756 | | { 1326 /* bltu */, Mips::BLTUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
5757 | | { 1331 /* bltuc */, Mips::BLTUC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5758 | | { 1331 /* bltuc */, Mips::BLTUC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5759 | | { 1331 /* bltuc */, Mips::BLTUC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
5760 | | { 1337 /* bltul */, Mips::BLTUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5761 | | { 1337 /* bltul */, Mips::BLTULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
5762 | | { 1343 /* bltz */, Mips::BLTZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5763 | | { 1343 /* bltz */, Mips::BLTZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5764 | | { 1348 /* bltzal */, Mips::BLTZAL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5765 | | { 1348 /* bltzal */, Mips::BLTZAL_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5766 | | { 1355 /* bltzalc */, Mips::BLTZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5767 | | { 1355 /* bltzalc */, Mips::BLTZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5768 | | { 1363 /* bltzall */, Mips::BLTZALL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5769 | | { 1371 /* bltzals */, Mips::BLTZALS_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5770 | | { 1379 /* bltzc */, Mips::BLTZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5771 | | { 1379 /* bltzc */, Mips::BLTZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5772 | | { 1379 /* bltzc */, Mips::BLTZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
5773 | | { 1385 /* bltzl */, Mips::BLTZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5774 | | { 1391 /* bmnz.v */, Mips::BMNZ_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5775 | | { 1398 /* bmnzi.b */, Mips::BMNZI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, |
5776 | | { 1406 /* bmz.v */, Mips::BMZ_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5777 | | { 1412 /* bmzi.b */, Mips::BMZI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, |
5778 | | { 1419 /* bne */, Mips::BNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5779 | | { 1419 /* bne */, Mips::BNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5780 | | { 1419 /* bne */, Mips::BneImm, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
5781 | | { 1423 /* bnec */, Mips::BNEC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5782 | | { 1423 /* bnec */, Mips::BNEC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5783 | | { 1423 /* bnec */, Mips::BNEC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
5784 | | { 1428 /* bneg.b */, Mips::BNEG_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5785 | | { 1435 /* bneg.d */, Mips::BNEG_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5786 | | { 1442 /* bneg.h */, Mips::BNEG_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5787 | | { 1449 /* bneg.w */, Mips::BNEG_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5788 | | { 1456 /* bnegi.b */, Mips::BNEGI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, |
5789 | | { 1464 /* bnegi.d */, Mips::BNEGI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, |
5790 | | { 1472 /* bnegi.h */, Mips::BNEGI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, |
5791 | | { 1480 /* bnegi.w */, Mips::BNEGI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
5792 | | { 1488 /* bnel */, Mips::BNEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5793 | | { 1488 /* bnel */, Mips::BNELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
5794 | | { 1493 /* bnez */, Mips::BnezRxImmX16, Convert__Reg1_0__JumpTarget1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget }, }, |
5795 | | { 1493 /* bnez */, Mips::BNE, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5796 | | { 1493 /* bnez */, Mips::BNE_MM, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5797 | | { 1493 /* bnez */, Mips::BnezRxImm16, Convert__Reg1_0__JumpTarget1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget, MCK__35_, MCK_16, MCK_bit, MCK_inst }, }, |
5798 | | { 1498 /* bnez16 */, Mips::BNEZ16_MM, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, }, |
5799 | | { 1498 /* bnez16 */, Mips::BNEZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, }, |
5800 | | { 1505 /* bnezalc */, Mips::BNEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5801 | | { 1505 /* bnezalc */, Mips::BNEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5802 | | { 1513 /* bnezc */, Mips::BNEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5803 | | { 1513 /* bnezc */, Mips::BNEZC_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5804 | | { 1513 /* bnezc */, Mips::BNEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5805 | | { 1513 /* bnezc */, Mips::BNEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
5806 | | { 1519 /* bnezc16 */, Mips::BNEZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, }, |
5807 | | { 1527 /* bnezl */, Mips::BNEL, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5808 | | { 1533 /* bnvc */, Mips::BNVC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5809 | | { 1533 /* bnvc */, Mips::BNVC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5810 | | { 1538 /* bnz.b */, Mips::BNZ_B, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, |
5811 | | { 1544 /* bnz.d */, Mips::BNZ_D, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, |
5812 | | { 1550 /* bnz.h */, Mips::BNZ_H, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, |
5813 | | { 1556 /* bnz.v */, Mips::BNZ_V, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, |
5814 | | { 1562 /* bnz.w */, Mips::BNZ_W, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, |
5815 | | { 1568 /* bovc */, Mips::BOVC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5816 | | { 1568 /* bovc */, Mips::BOVC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
5817 | | { 1573 /* bposge32 */, Mips::BPOSGE32_MM, Convert__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6_HasDSP, { MCK_JumpTarget }, }, |
5818 | | { 1573 /* bposge32 */, Mips::BPOSGE32, Convert__JumpTarget1_0, AMFBS_HasDSP_NotInMicroMips, { MCK_JumpTarget }, }, |
5819 | | { 1582 /* bposge32c */, Mips::BPOSGE32C_MMR3, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasDSPR3, { MCK_JumpTarget }, }, |
5820 | | { 1592 /* break */, Mips::BREAK, Convert__imm_95_0__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { }, }, |
5821 | | { 1592 /* break */, Mips::BREAK_MM, Convert__imm_95_0__imm_95_0, AMFBS_InMicroMips, { }, }, |
5822 | | { 1592 /* break */, Mips::Break16, Convert_NoOperands, AMFBS_InMips16Mode, { MCK_0 }, }, |
5823 | | { 1592 /* break */, Mips::BREAK, Convert__ConstantUImm10_01_0__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_ConstantUImm10_0 }, }, |
5824 | | { 1592 /* break */, Mips::BREAK_MM, Convert__ConstantUImm10_01_0__imm_95_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, }, |
5825 | | { 1592 /* break */, Mips::BREAK, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, }, |
5826 | | { 1592 /* break */, Mips::BREAK_MMR6, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, }, |
5827 | | { 1592 /* break */, Mips::BREAK_MM, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, AMFBS_InMicroMips, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, }, |
5828 | | { 1598 /* break16 */, Mips::BREAK16_MM, Convert__ConstantUImm4_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm4_0 }, }, |
5829 | | { 1598 /* break16 */, Mips::BREAK16_MMR6, Convert__ConstantUImm4_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm4_0 }, }, |
5830 | | { 1606 /* bsel.v */, Mips::BSEL_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5831 | | { 1613 /* bseli.b */, Mips::BSELI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, |
5832 | | { 1621 /* bset.b */, Mips::BSET_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5833 | | { 1628 /* bset.d */, Mips::BSET_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5834 | | { 1635 /* bset.h */, Mips::BSET_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5835 | | { 1642 /* bset.w */, Mips::BSET_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
5836 | | { 1649 /* bseti.b */, Mips::BSETI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, |
5837 | | { 1657 /* bseti.d */, Mips::BSETI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, |
5838 | | { 1665 /* bseti.h */, Mips::BSETI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, |
5839 | | { 1673 /* bseti.w */, Mips::BSETI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
5840 | | { 1681 /* bteqz */, Mips::BteqzX16, Convert__SImm161_0, AMFBS_InMips16Mode, { MCK_SImm16 }, }, |
5841 | | { 1681 /* bteqz */, Mips::Bteqz16, Convert__SImm161_0, AMFBS_InMips16Mode, { MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, }, |
5842 | | { 1687 /* btnez */, Mips::BtnezX16, Convert__SImm161_0, AMFBS_InMips16Mode, { MCK_SImm16 }, }, |
5843 | | { 1687 /* btnez */, Mips::Btnez16, Convert__SImm161_0, AMFBS_InMips16Mode, { MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, }, |
5844 | | { 1693 /* bz.b */, Mips::BZ_B, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, |
5845 | | { 1698 /* bz.d */, Mips::BZ_D, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, |
5846 | | { 1703 /* bz.h */, Mips::BZ_H, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, |
5847 | | { 1708 /* bz.v */, Mips::BZ_V, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, |
5848 | | { 1713 /* bz.w */, Mips::BZ_W, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, |
5849 | | { 1718 /* c.eq.d */, Mips::C_EQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5850 | | { 1718 /* c.eq.d */, Mips::C_EQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5851 | | { 1718 /* c.eq.d */, Mips::C_EQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5852 | | { 1718 /* c.eq.d */, Mips::C_EQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5853 | | { 1718 /* c.eq.d */, Mips::C_EQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5854 | | { 1718 /* c.eq.d */, Mips::C_EQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5855 | | { 1718 /* c.eq.d */, Mips::C_EQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5856 | | { 1718 /* c.eq.d */, Mips::C_EQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5857 | | { 1725 /* c.eq.s */, Mips::C_EQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5858 | | { 1725 /* c.eq.s */, Mips::C_EQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5859 | | { 1725 /* c.eq.s */, Mips::C_EQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5860 | | { 1725 /* c.eq.s */, Mips::C_EQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5861 | | { 1732 /* c.f.d */, Mips::C_F_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5862 | | { 1732 /* c.f.d */, Mips::C_F_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5863 | | { 1732 /* c.f.d */, Mips::C_F_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5864 | | { 1732 /* c.f.d */, Mips::C_F_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5865 | | { 1732 /* c.f.d */, Mips::C_F_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5866 | | { 1732 /* c.f.d */, Mips::C_F_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5867 | | { 1732 /* c.f.d */, Mips::C_F_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5868 | | { 1732 /* c.f.d */, Mips::C_F_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5869 | | { 1738 /* c.f.s */, Mips::C_F_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5870 | | { 1738 /* c.f.s */, Mips::C_F_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5871 | | { 1738 /* c.f.s */, Mips::C_F_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5872 | | { 1738 /* c.f.s */, Mips::C_F_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5873 | | { 1744 /* c.le.d */, Mips::C_LE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5874 | | { 1744 /* c.le.d */, Mips::C_LE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5875 | | { 1744 /* c.le.d */, Mips::C_LE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5876 | | { 1744 /* c.le.d */, Mips::C_LE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5877 | | { 1744 /* c.le.d */, Mips::C_LE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5878 | | { 1744 /* c.le.d */, Mips::C_LE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5879 | | { 1744 /* c.le.d */, Mips::C_LE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5880 | | { 1744 /* c.le.d */, Mips::C_LE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5881 | | { 1751 /* c.le.s */, Mips::C_LE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5882 | | { 1751 /* c.le.s */, Mips::C_LE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5883 | | { 1751 /* c.le.s */, Mips::C_LE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5884 | | { 1751 /* c.le.s */, Mips::C_LE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5885 | | { 1758 /* c.lt.d */, Mips::C_LT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5886 | | { 1758 /* c.lt.d */, Mips::C_LT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5887 | | { 1758 /* c.lt.d */, Mips::C_LT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5888 | | { 1758 /* c.lt.d */, Mips::C_LT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5889 | | { 1758 /* c.lt.d */, Mips::C_LT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5890 | | { 1758 /* c.lt.d */, Mips::C_LT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5891 | | { 1758 /* c.lt.d */, Mips::C_LT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5892 | | { 1758 /* c.lt.d */, Mips::C_LT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5893 | | { 1765 /* c.lt.s */, Mips::C_LT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5894 | | { 1765 /* c.lt.s */, Mips::C_LT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5895 | | { 1765 /* c.lt.s */, Mips::C_LT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5896 | | { 1765 /* c.lt.s */, Mips::C_LT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5897 | | { 1772 /* c.nge.d */, Mips::C_NGE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5898 | | { 1772 /* c.nge.d */, Mips::C_NGE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5899 | | { 1772 /* c.nge.d */, Mips::C_NGE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5900 | | { 1772 /* c.nge.d */, Mips::C_NGE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5901 | | { 1772 /* c.nge.d */, Mips::C_NGE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5902 | | { 1772 /* c.nge.d */, Mips::C_NGE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5903 | | { 1772 /* c.nge.d */, Mips::C_NGE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5904 | | { 1772 /* c.nge.d */, Mips::C_NGE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5905 | | { 1780 /* c.nge.s */, Mips::C_NGE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5906 | | { 1780 /* c.nge.s */, Mips::C_NGE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5907 | | { 1780 /* c.nge.s */, Mips::C_NGE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5908 | | { 1780 /* c.nge.s */, Mips::C_NGE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5909 | | { 1788 /* c.ngl.d */, Mips::C_NGL_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5910 | | { 1788 /* c.ngl.d */, Mips::C_NGL_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5911 | | { 1788 /* c.ngl.d */, Mips::C_NGL_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5912 | | { 1788 /* c.ngl.d */, Mips::C_NGL_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5913 | | { 1788 /* c.ngl.d */, Mips::C_NGL_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5914 | | { 1788 /* c.ngl.d */, Mips::C_NGL_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5915 | | { 1788 /* c.ngl.d */, Mips::C_NGL_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5916 | | { 1788 /* c.ngl.d */, Mips::C_NGL_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5917 | | { 1796 /* c.ngl.s */, Mips::C_NGL_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5918 | | { 1796 /* c.ngl.s */, Mips::C_NGL_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5919 | | { 1796 /* c.ngl.s */, Mips::C_NGL_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5920 | | { 1796 /* c.ngl.s */, Mips::C_NGL_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5921 | | { 1804 /* c.ngle.d */, Mips::C_NGLE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5922 | | { 1804 /* c.ngle.d */, Mips::C_NGLE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5923 | | { 1804 /* c.ngle.d */, Mips::C_NGLE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5924 | | { 1804 /* c.ngle.d */, Mips::C_NGLE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5925 | | { 1804 /* c.ngle.d */, Mips::C_NGLE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5926 | | { 1804 /* c.ngle.d */, Mips::C_NGLE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5927 | | { 1804 /* c.ngle.d */, Mips::C_NGLE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5928 | | { 1804 /* c.ngle.d */, Mips::C_NGLE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5929 | | { 1813 /* c.ngle.s */, Mips::C_NGLE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5930 | | { 1813 /* c.ngle.s */, Mips::C_NGLE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5931 | | { 1813 /* c.ngle.s */, Mips::C_NGLE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5932 | | { 1813 /* c.ngle.s */, Mips::C_NGLE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5933 | | { 1822 /* c.ngt.d */, Mips::C_NGT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5934 | | { 1822 /* c.ngt.d */, Mips::C_NGT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5935 | | { 1822 /* c.ngt.d */, Mips::C_NGT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5936 | | { 1822 /* c.ngt.d */, Mips::C_NGT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5937 | | { 1822 /* c.ngt.d */, Mips::C_NGT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5938 | | { 1822 /* c.ngt.d */, Mips::C_NGT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5939 | | { 1822 /* c.ngt.d */, Mips::C_NGT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5940 | | { 1822 /* c.ngt.d */, Mips::C_NGT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5941 | | { 1830 /* c.ngt.s */, Mips::C_NGT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5942 | | { 1830 /* c.ngt.s */, Mips::C_NGT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5943 | | { 1830 /* c.ngt.s */, Mips::C_NGT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5944 | | { 1830 /* c.ngt.s */, Mips::C_NGT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5945 | | { 1838 /* c.ole.d */, Mips::C_OLE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5946 | | { 1838 /* c.ole.d */, Mips::C_OLE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5947 | | { 1838 /* c.ole.d */, Mips::C_OLE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5948 | | { 1838 /* c.ole.d */, Mips::C_OLE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5949 | | { 1838 /* c.ole.d */, Mips::C_OLE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5950 | | { 1838 /* c.ole.d */, Mips::C_OLE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5951 | | { 1838 /* c.ole.d */, Mips::C_OLE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5952 | | { 1838 /* c.ole.d */, Mips::C_OLE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5953 | | { 1846 /* c.ole.s */, Mips::C_OLE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5954 | | { 1846 /* c.ole.s */, Mips::C_OLE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5955 | | { 1846 /* c.ole.s */, Mips::C_OLE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5956 | | { 1846 /* c.ole.s */, Mips::C_OLE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5957 | | { 1854 /* c.olt.d */, Mips::C_OLT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5958 | | { 1854 /* c.olt.d */, Mips::C_OLT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5959 | | { 1854 /* c.olt.d */, Mips::C_OLT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5960 | | { 1854 /* c.olt.d */, Mips::C_OLT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5961 | | { 1854 /* c.olt.d */, Mips::C_OLT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5962 | | { 1854 /* c.olt.d */, Mips::C_OLT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5963 | | { 1854 /* c.olt.d */, Mips::C_OLT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5964 | | { 1854 /* c.olt.d */, Mips::C_OLT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5965 | | { 1862 /* c.olt.s */, Mips::C_OLT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5966 | | { 1862 /* c.olt.s */, Mips::C_OLT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5967 | | { 1862 /* c.olt.s */, Mips::C_OLT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5968 | | { 1862 /* c.olt.s */, Mips::C_OLT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5969 | | { 1870 /* c.seq.d */, Mips::C_SEQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5970 | | { 1870 /* c.seq.d */, Mips::C_SEQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5971 | | { 1870 /* c.seq.d */, Mips::C_SEQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5972 | | { 1870 /* c.seq.d */, Mips::C_SEQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5973 | | { 1870 /* c.seq.d */, Mips::C_SEQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5974 | | { 1870 /* c.seq.d */, Mips::C_SEQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5975 | | { 1870 /* c.seq.d */, Mips::C_SEQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5976 | | { 1870 /* c.seq.d */, Mips::C_SEQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5977 | | { 1878 /* c.seq.s */, Mips::C_SEQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5978 | | { 1878 /* c.seq.s */, Mips::C_SEQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5979 | | { 1878 /* c.seq.s */, Mips::C_SEQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5980 | | { 1878 /* c.seq.s */, Mips::C_SEQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5981 | | { 1886 /* c.sf.d */, Mips::C_SF_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5982 | | { 1886 /* c.sf.d */, Mips::C_SF_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5983 | | { 1886 /* c.sf.d */, Mips::C_SF_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5984 | | { 1886 /* c.sf.d */, Mips::C_SF_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5985 | | { 1886 /* c.sf.d */, Mips::C_SF_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5986 | | { 1886 /* c.sf.d */, Mips::C_SF_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5987 | | { 1886 /* c.sf.d */, Mips::C_SF_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5988 | | { 1886 /* c.sf.d */, Mips::C_SF_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5989 | | { 1893 /* c.sf.s */, Mips::C_SF_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5990 | | { 1893 /* c.sf.s */, Mips::C_SF_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5991 | | { 1893 /* c.sf.s */, Mips::C_SF_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5992 | | { 1893 /* c.sf.s */, Mips::C_SF_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
5993 | | { 1900 /* c.ueq.d */, Mips::C_UEQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5994 | | { 1900 /* c.ueq.d */, Mips::C_UEQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5995 | | { 1900 /* c.ueq.d */, Mips::C_UEQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5996 | | { 1900 /* c.ueq.d */, Mips::C_UEQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
5997 | | { 1900 /* c.ueq.d */, Mips::C_UEQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5998 | | { 1900 /* c.ueq.d */, Mips::C_UEQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
5999 | | { 1900 /* c.ueq.d */, Mips::C_UEQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6000 | | { 1900 /* c.ueq.d */, Mips::C_UEQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6001 | | { 1908 /* c.ueq.s */, Mips::C_UEQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6002 | | { 1908 /* c.ueq.s */, Mips::C_UEQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6003 | | { 1908 /* c.ueq.s */, Mips::C_UEQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6004 | | { 1908 /* c.ueq.s */, Mips::C_UEQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6005 | | { 1916 /* c.ule.d */, Mips::C_ULE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
6006 | | { 1916 /* c.ule.d */, Mips::C_ULE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
6007 | | { 1916 /* c.ule.d */, Mips::C_ULE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6008 | | { 1916 /* c.ule.d */, Mips::C_ULE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6009 | | { 1916 /* c.ule.d */, Mips::C_ULE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
6010 | | { 1916 /* c.ule.d */, Mips::C_ULE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
6011 | | { 1916 /* c.ule.d */, Mips::C_ULE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6012 | | { 1916 /* c.ule.d */, Mips::C_ULE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6013 | | { 1924 /* c.ule.s */, Mips::C_ULE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6014 | | { 1924 /* c.ule.s */, Mips::C_ULE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6015 | | { 1924 /* c.ule.s */, Mips::C_ULE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6016 | | { 1924 /* c.ule.s */, Mips::C_ULE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6017 | | { 1932 /* c.ult.d */, Mips::C_ULT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
6018 | | { 1932 /* c.ult.d */, Mips::C_ULT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
6019 | | { 1932 /* c.ult.d */, Mips::C_ULT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6020 | | { 1932 /* c.ult.d */, Mips::C_ULT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6021 | | { 1932 /* c.ult.d */, Mips::C_ULT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
6022 | | { 1932 /* c.ult.d */, Mips::C_ULT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
6023 | | { 1932 /* c.ult.d */, Mips::C_ULT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6024 | | { 1932 /* c.ult.d */, Mips::C_ULT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6025 | | { 1940 /* c.ult.s */, Mips::C_ULT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6026 | | { 1940 /* c.ult.s */, Mips::C_ULT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6027 | | { 1940 /* c.ult.s */, Mips::C_ULT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6028 | | { 1940 /* c.ult.s */, Mips::C_ULT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6029 | | { 1948 /* c.un.d */, Mips::C_UN_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
6030 | | { 1948 /* c.un.d */, Mips::C_UN_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
6031 | | { 1948 /* c.un.d */, Mips::C_UN_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6032 | | { 1948 /* c.un.d */, Mips::C_UN_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6033 | | { 1948 /* c.un.d */, Mips::C_UN_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
6034 | | { 1948 /* c.un.d */, Mips::C_UN_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
6035 | | { 1948 /* c.un.d */, Mips::C_UN_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6036 | | { 1948 /* c.un.d */, Mips::C_UN_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6037 | | { 1955 /* c.un.s */, Mips::C_UN_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6038 | | { 1955 /* c.un.s */, Mips::C_UN_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6039 | | { 1955 /* c.un.s */, Mips::C_UN_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6040 | | { 1955 /* c.un.s */, Mips::C_UN_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6041 | | { 1962 /* cache */, Mips::CACHE_R6, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, }, |
6042 | | { 1962 /* cache */, Mips::CACHE, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_Mem }, }, |
6043 | | { 1962 /* cache */, Mips::CACHE_MM, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, }, |
6044 | | { 1962 /* cache */, Mips::CACHE_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, }, |
6045 | | { 1968 /* cachee */, Mips::CACHEE, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, }, |
6046 | | { 1968 /* cachee */, Mips::CACHEE_MM, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasEVA, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, }, |
6047 | | { 1975 /* ceil.l.d */, Mips::CEIL_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6048 | | { 1975 /* ceil.l.d */, Mips::CEIL_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6049 | | { 1984 /* ceil.l.s */, Mips::CEIL_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
6050 | | { 1984 /* ceil.l.s */, Mips::CEIL_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
6051 | | { 1993 /* ceil.w.d */, Mips::CEIL_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
6052 | | { 1993 /* ceil.w.d */, Mips::CEIL_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
6053 | | { 1993 /* ceil.w.d */, Mips::CEIL_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
6054 | | { 1993 /* ceil.w.d */, Mips::CEIL_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, |
6055 | | { 2002 /* ceil.w.s */, Mips::CEIL_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6056 | | { 2002 /* ceil.w.s */, Mips::CEIL_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6057 | | { 2002 /* ceil.w.s */, Mips::CEIL_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6058 | | { 2011 /* ceq.b */, Mips::CEQ_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6059 | | { 2017 /* ceq.d */, Mips::CEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6060 | | { 2023 /* ceq.h */, Mips::CEQ_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6061 | | { 2029 /* ceq.w */, Mips::CEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6062 | | { 2035 /* ceqi.b */, Mips::CEQI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
6063 | | { 2042 /* ceqi.d */, Mips::CEQI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
6064 | | { 2049 /* ceqi.h */, Mips::CEQI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
6065 | | { 2056 /* ceqi.w */, Mips::CEQI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
6066 | | { 2063 /* cfc1 */, Mips::CFC1, Convert__GPR32AsmReg1_0__CCRAsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, }, |
6067 | | { 2063 /* cfc1 */, Mips::CFC1_MM, Convert__GPR32AsmReg1_0__CCRAsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, }, |
6068 | | { 2068 /* cfc2 */, Mips::CFC2_MM, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, |
6069 | | { 2073 /* cfcmsa */, Mips::CFCMSA, Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSACtrlAsmReg }, }, |
6070 | | { 2080 /* cftc1 */, Mips::CFTC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, |
6071 | | { 2086 /* cins */, Mips::CINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, |
6072 | | { 2086 /* cins */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, }, |
6073 | | { 2086 /* cins */, Mips::CINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, |
6074 | | { 2086 /* cins */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, }, |
6075 | | { 2091 /* cins32 */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, |
6076 | | { 2091 /* cins32 */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, |
6077 | | { 2098 /* class.d */, Mips::CLASS_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6078 | | { 2098 /* class.d */, Mips::CLASS_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6079 | | { 2106 /* class.s */, Mips::CLASS_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6080 | | { 2106 /* class.s */, Mips::CLASS_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6081 | | { 2114 /* cle_s.b */, Mips::CLE_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6082 | | { 2122 /* cle_s.d */, Mips::CLE_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6083 | | { 2130 /* cle_s.h */, Mips::CLE_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6084 | | { 2138 /* cle_s.w */, Mips::CLE_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6085 | | { 2146 /* cle_u.b */, Mips::CLE_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6086 | | { 2154 /* cle_u.d */, Mips::CLE_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6087 | | { 2162 /* cle_u.h */, Mips::CLE_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6088 | | { 2170 /* cle_u.w */, Mips::CLE_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6089 | | { 2178 /* clei_s.b */, Mips::CLEI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
6090 | | { 2187 /* clei_s.d */, Mips::CLEI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
6091 | | { 2196 /* clei_s.h */, Mips::CLEI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
6092 | | { 2205 /* clei_s.w */, Mips::CLEI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
6093 | | { 2214 /* clei_u.b */, Mips::CLEI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
6094 | | { 2223 /* clei_u.d */, Mips::CLEI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
6095 | | { 2232 /* clei_u.h */, Mips::CLEI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
6096 | | { 2241 /* clei_u.w */, Mips::CLEI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
6097 | | { 2250 /* clo */, Mips::CLO, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6098 | | { 2250 /* clo */, Mips::CLO_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6099 | | { 2250 /* clo */, Mips::CLO_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6100 | | { 2250 /* clo */, Mips::CLO_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6101 | | { 2254 /* clt_s.b */, Mips::CLT_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6102 | | { 2262 /* clt_s.d */, Mips::CLT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6103 | | { 2270 /* clt_s.h */, Mips::CLT_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6104 | | { 2278 /* clt_s.w */, Mips::CLT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6105 | | { 2286 /* clt_u.b */, Mips::CLT_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6106 | | { 2294 /* clt_u.d */, Mips::CLT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6107 | | { 2302 /* clt_u.h */, Mips::CLT_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6108 | | { 2310 /* clt_u.w */, Mips::CLT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6109 | | { 2318 /* clti_s.b */, Mips::CLTI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
6110 | | { 2327 /* clti_s.d */, Mips::CLTI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
6111 | | { 2336 /* clti_s.h */, Mips::CLTI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
6112 | | { 2345 /* clti_s.w */, Mips::CLTI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
6113 | | { 2354 /* clti_u.b */, Mips::CLTI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
6114 | | { 2363 /* clti_u.d */, Mips::CLTI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
6115 | | { 2372 /* clti_u.h */, Mips::CLTI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
6116 | | { 2381 /* clti_u.w */, Mips::CLTI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
6117 | | { 2390 /* clz */, Mips::CLZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6118 | | { 2390 /* clz */, Mips::CLZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6119 | | { 2390 /* clz */, Mips::CLZ_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6120 | | { 2390 /* clz */, Mips::CLZ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6121 | | { 2394 /* cmp */, Mips::CmpRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, |
6122 | | { 2398 /* cmp.af.d */, Mips::CMP_F_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6123 | | { 2398 /* cmp.af.d */, Mips::CMP_AF_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6124 | | { 2407 /* cmp.af.s */, Mips::CMP_F_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6125 | | { 2407 /* cmp.af.s */, Mips::CMP_AF_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6126 | | { 2416 /* cmp.eq.d */, Mips::CMP_EQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6127 | | { 2416 /* cmp.eq.d */, Mips::CMP_EQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6128 | | { 2425 /* cmp.eq.ph */, Mips::CMP_EQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6129 | | { 2425 /* cmp.eq.ph */, Mips::CMP_EQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6130 | | { 2435 /* cmp.eq.s */, Mips::CMP_EQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6131 | | { 2435 /* cmp.eq.s */, Mips::CMP_EQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6132 | | { 2444 /* cmp.le.d */, Mips::CMP_LE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6133 | | { 2444 /* cmp.le.d */, Mips::CMP_LE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6134 | | { 2453 /* cmp.le.ph */, Mips::CMP_LE_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6135 | | { 2453 /* cmp.le.ph */, Mips::CMP_LE_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6136 | | { 2463 /* cmp.le.s */, Mips::CMP_LE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6137 | | { 2463 /* cmp.le.s */, Mips::CMP_LE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6138 | | { 2472 /* cmp.lt.d */, Mips::CMP_LT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6139 | | { 2472 /* cmp.lt.d */, Mips::CMP_LT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6140 | | { 2481 /* cmp.lt.ph */, Mips::CMP_LT_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6141 | | { 2481 /* cmp.lt.ph */, Mips::CMP_LT_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6142 | | { 2491 /* cmp.lt.s */, Mips::CMP_LT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6143 | | { 2491 /* cmp.lt.s */, Mips::CMP_LT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6144 | | { 2500 /* cmp.saf.d */, Mips::CMP_SAF_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6145 | | { 2500 /* cmp.saf.d */, Mips::CMP_SAF_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6146 | | { 2510 /* cmp.saf.s */, Mips::CMP_SAF_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6147 | | { 2510 /* cmp.saf.s */, Mips::CMP_SAF_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6148 | | { 2520 /* cmp.seq.d */, Mips::CMP_SEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6149 | | { 2520 /* cmp.seq.d */, Mips::CMP_SEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6150 | | { 2530 /* cmp.seq.s */, Mips::CMP_SEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6151 | | { 2530 /* cmp.seq.s */, Mips::CMP_SEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6152 | | { 2540 /* cmp.sle.d */, Mips::CMP_SLE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6153 | | { 2540 /* cmp.sle.d */, Mips::CMP_SLE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6154 | | { 2550 /* cmp.sle.s */, Mips::CMP_SLE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6155 | | { 2550 /* cmp.sle.s */, Mips::CMP_SLE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6156 | | { 2560 /* cmp.slt.d */, Mips::CMP_SLT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6157 | | { 2560 /* cmp.slt.d */, Mips::CMP_SLT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6158 | | { 2570 /* cmp.slt.s */, Mips::CMP_SLT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6159 | | { 2570 /* cmp.slt.s */, Mips::CMP_SLT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6160 | | { 2580 /* cmp.sueq.d */, Mips::CMP_SUEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6161 | | { 2580 /* cmp.sueq.d */, Mips::CMP_SUEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6162 | | { 2591 /* cmp.sueq.s */, Mips::CMP_SUEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6163 | | { 2591 /* cmp.sueq.s */, Mips::CMP_SUEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6164 | | { 2602 /* cmp.sule.d */, Mips::CMP_SULE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6165 | | { 2602 /* cmp.sule.d */, Mips::CMP_SULE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6166 | | { 2613 /* cmp.sule.s */, Mips::CMP_SULE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6167 | | { 2613 /* cmp.sule.s */, Mips::CMP_SULE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6168 | | { 2624 /* cmp.sult.d */, Mips::CMP_SULT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6169 | | { 2624 /* cmp.sult.d */, Mips::CMP_SULT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6170 | | { 2635 /* cmp.sult.s */, Mips::CMP_SULT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6171 | | { 2635 /* cmp.sult.s */, Mips::CMP_SULT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6172 | | { 2646 /* cmp.sun.d */, Mips::CMP_SUN_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6173 | | { 2646 /* cmp.sun.d */, Mips::CMP_SUN_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6174 | | { 2656 /* cmp.sun.s */, Mips::CMP_SUN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6175 | | { 2656 /* cmp.sun.s */, Mips::CMP_SUN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6176 | | { 2666 /* cmp.ueq.d */, Mips::CMP_UEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6177 | | { 2666 /* cmp.ueq.d */, Mips::CMP_UEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6178 | | { 2676 /* cmp.ueq.s */, Mips::CMP_UEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6179 | | { 2676 /* cmp.ueq.s */, Mips::CMP_UEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6180 | | { 2686 /* cmp.ule.d */, Mips::CMP_ULE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6181 | | { 2686 /* cmp.ule.d */, Mips::CMP_ULE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6182 | | { 2696 /* cmp.ule.s */, Mips::CMP_ULE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6183 | | { 2696 /* cmp.ule.s */, Mips::CMP_ULE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6184 | | { 2706 /* cmp.ult.d */, Mips::CMP_ULT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6185 | | { 2706 /* cmp.ult.d */, Mips::CMP_ULT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6186 | | { 2716 /* cmp.ult.s */, Mips::CMP_ULT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6187 | | { 2716 /* cmp.ult.s */, Mips::CMP_ULT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6188 | | { 2726 /* cmp.un.d */, Mips::CMP_UN_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6189 | | { 2726 /* cmp.un.d */, Mips::CMP_UN_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6190 | | { 2735 /* cmp.un.s */, Mips::CMP_UN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6191 | | { 2735 /* cmp.un.s */, Mips::CMP_UN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6192 | | { 2744 /* cmpgdu.eq.qb */, Mips::CMPGDU_EQ_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6193 | | { 2744 /* cmpgdu.eq.qb */, Mips::CMPGDU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6194 | | { 2757 /* cmpgdu.le.qb */, Mips::CMPGDU_LE_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6195 | | { 2757 /* cmpgdu.le.qb */, Mips::CMPGDU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6196 | | { 2770 /* cmpgdu.lt.qb */, Mips::CMPGDU_LT_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6197 | | { 2770 /* cmpgdu.lt.qb */, Mips::CMPGDU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6198 | | { 2783 /* cmpgu.eq.qb */, Mips::CMPGU_EQ_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6199 | | { 2783 /* cmpgu.eq.qb */, Mips::CMPGU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6200 | | { 2795 /* cmpgu.le.qb */, Mips::CMPGU_LE_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6201 | | { 2795 /* cmpgu.le.qb */, Mips::CMPGU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6202 | | { 2807 /* cmpgu.lt.qb */, Mips::CMPGU_LT_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6203 | | { 2807 /* cmpgu.lt.qb */, Mips::CMPGU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6204 | | { 2819 /* cmpi */, Mips::CmpiRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, }, |
6205 | | { 2819 /* cmpi */, Mips::CmpiRxImm16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, }, |
6206 | | { 2824 /* cmpu.eq.qb */, Mips::CMPU_EQ_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6207 | | { 2824 /* cmpu.eq.qb */, Mips::CMPU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6208 | | { 2835 /* cmpu.le.qb */, Mips::CMPU_LE_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6209 | | { 2835 /* cmpu.le.qb */, Mips::CMPU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6210 | | { 2846 /* cmpu.lt.qb */, Mips::CMPU_LT_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6211 | | { 2846 /* cmpu.lt.qb */, Mips::CMPU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6212 | | { 2857 /* copy_s.b */, Mips::COPY_S_B, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, }, |
6213 | | { 2866 /* copy_s.d */, Mips::COPY_S_D, Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_GPR64AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, }, |
6214 | | { 2875 /* copy_s.h */, Mips::COPY_S_H, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, }, |
6215 | | { 2884 /* copy_s.w */, Mips::COPY_S_W, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, }, |
6216 | | { 2893 /* copy_u.b */, Mips::COPY_U_B, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, }, |
6217 | | { 2902 /* copy_u.h */, Mips::COPY_U_H, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, }, |
6218 | | { 2911 /* copy_u.w */, Mips::COPY_U_W, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, }, |
6219 | | { 2920 /* crc32b */, Mips::CRC32B, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6220 | | { 2927 /* crc32cb */, Mips::CRC32CB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6221 | | { 2935 /* crc32cd */, Mips::CRC32CD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6222 | | { 2943 /* crc32ch */, Mips::CRC32CH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6223 | | { 2951 /* crc32cw */, Mips::CRC32CW, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6224 | | { 2959 /* crc32d */, Mips::CRC32D, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6225 | | { 2966 /* crc32h */, Mips::CRC32H, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6226 | | { 2973 /* crc32w */, Mips::CRC32W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6227 | | { 2980 /* ctc1 */, Mips::CTC1, Convert__CCRAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, }, |
6228 | | { 2980 /* ctc1 */, Mips::CTC1_MM, Convert__CCRAsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, }, |
6229 | | { 2985 /* ctc2 */, Mips::CTC2_MM, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, |
6230 | | { 2990 /* ctcmsa */, Mips::CTCMSA, Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSACtrlAsmReg, MCK_GPR32AsmReg }, }, |
6231 | | { 2997 /* cttc1 */, Mips::CTTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, |
6232 | | { 3003 /* cvt.d.l */, Mips::CVT_D64_L, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6233 | | { 3003 /* cvt.d.l */, Mips::CVT_D_L_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6234 | | { 3011 /* cvt.d.s */, Mips::CVT_D32_S, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, }, |
6235 | | { 3011 /* cvt.d.s */, Mips::CVT_D32_S_MM, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, }, |
6236 | | { 3011 /* cvt.d.s */, Mips::CVT_D64_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
6237 | | { 3011 /* cvt.d.s */, Mips::CVT_D64_S_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
6238 | | { 3019 /* cvt.d.w */, Mips::CVT_D32_W, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, }, |
6239 | | { 3019 /* cvt.d.w */, Mips::CVT_D32_W_MM, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, }, |
6240 | | { 3019 /* cvt.d.w */, Mips::CVT_D64_W, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
6241 | | { 3019 /* cvt.d.w */, Mips::CVT_D64_W_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
6242 | | { 3027 /* cvt.l.d */, Mips::CVT_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6243 | | { 3027 /* cvt.l.d */, Mips::CVT_L_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6244 | | { 3027 /* cvt.l.d */, Mips::CVT_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6245 | | { 3035 /* cvt.l.s */, Mips::CVT_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
6246 | | { 3035 /* cvt.l.s */, Mips::CVT_L_S_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
6247 | | { 3035 /* cvt.l.s */, Mips::CVT_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
6248 | | { 3043 /* cvt.ps.s */, Mips::CVT_PS_S64, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6249 | | { 3052 /* cvt.s.d */, Mips::CVT_S_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
6250 | | { 3052 /* cvt.s.d */, Mips::CVT_S_D32_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
6251 | | { 3052 /* cvt.s.d */, Mips::CVT_S_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, |
6252 | | { 3052 /* cvt.s.d */, Mips::CVT_S_D64_MM, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, |
6253 | | { 3060 /* cvt.s.l */, Mips::CVT_S_L, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, |
6254 | | { 3060 /* cvt.s.l */, Mips::CVT_S_L_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
6255 | | { 3068 /* cvt.s.pl */, Mips::CVT_S_PL64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, |
6256 | | { 3077 /* cvt.s.pu */, Mips::CVT_S_PU64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, |
6257 | | { 3086 /* cvt.s.w */, Mips::CVT_S_W, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6258 | | { 3086 /* cvt.s.w */, Mips::CVT_S_W_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6259 | | { 3086 /* cvt.s.w */, Mips::CVT_S_W_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6260 | | { 3094 /* cvt.w.d */, Mips::CVT_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
6261 | | { 3094 /* cvt.w.d */, Mips::CVT_W_D32_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
6262 | | { 3094 /* cvt.w.d */, Mips::CVT_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, |
6263 | | { 3094 /* cvt.w.d */, Mips::CVT_W_D64_MM, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, |
6264 | | { 3102 /* cvt.w.s */, Mips::CVT_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6265 | | { 3102 /* cvt.w.s */, Mips::CVT_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6266 | | { 3102 /* cvt.w.s */, Mips::CVT_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6267 | | { 3110 /* dadd */, Mips::DADD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6268 | | { 3110 /* dadd */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, }, |
6269 | | { 3110 /* dadd */, Mips::DADD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6270 | | { 3110 /* dadd */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, }, |
6271 | | { 3115 /* daddi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_SImm16 }, }, |
6272 | | { 3115 /* daddi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, }, |
6273 | | { 3121 /* daddiu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, }, |
6274 | | { 3121 /* daddiu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, }, |
6275 | | { 3128 /* daddu */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6276 | | { 3128 /* daddu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, }, |
6277 | | { 3128 /* daddu */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6278 | | { 3128 /* daddu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, }, |
6279 | | { 3134 /* dahi */, Mips::DAHI, Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16_AltRelaxed }, }, |
6280 | | { 3139 /* dalign */, Mips::DALIGN, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm3_0 }, }, |
6281 | | { 3146 /* dati */, Mips::DATI, Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16_AltRelaxed }, }, |
6282 | | { 3151 /* daui */, Mips::DAUI, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16 }, }, |
6283 | | { 3156 /* dbitswap */, Mips::DBITSWAP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6284 | | { 3165 /* dclo */, Mips::DCLO, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6285 | | { 3165 /* dclo */, Mips::DCLO_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6286 | | { 3170 /* dclz */, Mips::DCLZ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6287 | | { 3170 /* dclz */, Mips::DCLZ_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6288 | | { 3175 /* ddiv */, Mips::DSDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6289 | | { 3175 /* ddiv */, Mips::DSDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, }, |
6290 | | { 3175 /* ddiv */, Mips::DSDIV, Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6291 | | { 3175 /* ddiv */, Mips::DSDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6292 | | { 3175 /* ddiv */, Mips::DDIV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6293 | | { 3175 /* ddiv */, Mips::DSDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, |
6294 | | { 3180 /* ddivu */, Mips::DUDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6295 | | { 3180 /* ddivu */, Mips::DUDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, }, |
6296 | | { 3180 /* ddivu */, Mips::DUDIV, Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6297 | | { 3180 /* ddivu */, Mips::DUDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6298 | | { 3180 /* ddivu */, Mips::DDIVU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6299 | | { 3180 /* ddivu */, Mips::DUDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, |
6300 | | { 3186 /* deret */, Mips::DERET, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32_NotInMicroMips, { }, }, |
6301 | | { 3186 /* deret */, Mips::DERET_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, }, |
6302 | | { 3186 /* deret */, Mips::DERET_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, }, |
6303 | | { 3192 /* dext */, Mips::DEXTM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_33 }, }, |
6304 | | { 3192 /* dext */, Mips::DEXTU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, }, |
6305 | | { 3192 /* dext */, Mips::DEXT, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_ConstantUImm5_Plus1_Report_UImm6 }, }, |
6306 | | { 3197 /* dextm */, Mips::DEXTM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_33 }, }, |
6307 | | { 3203 /* dextu */, Mips::DEXTU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, }, |
6308 | | { 3209 /* di */, Mips::DI, Convert__regZERO, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { }, }, |
6309 | | { 3209 /* di */, Mips::DI_MMR6, Convert__regZERO, AMFBS_InMicroMips_HasMips32r6, { }, }, |
6310 | | { 3209 /* di */, Mips::DI_MM, Convert__regZERO, AMFBS_InMicroMips, { }, }, |
6311 | | { 3209 /* di */, Mips::DI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
6312 | | { 3209 /* di */, Mips::DI_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, |
6313 | | { 3209 /* di */, Mips::DI_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, }, |
6314 | | { 3212 /* dins */, Mips::DINSM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImmRange2_64 }, }, |
6315 | | { 3212 /* dins */, Mips::DINSU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, }, |
6316 | | { 3212 /* dins */, Mips::DINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0, MCK_ConstantUImm5_1 }, }, |
6317 | | { 3217 /* dinsm */, Mips::DINSM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImmRange2_64 }, }, |
6318 | | { 3223 /* dinsu */, Mips::DINSU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, }, |
6319 | | { 3229 /* div */, Mips::DIV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6320 | | { 3229 /* div */, Mips::SDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32 }, }, |
6321 | | { 3229 /* div */, Mips::SDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg }, }, |
6322 | | { 3229 /* div */, Mips::SDIV, Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32ZeroAsmReg, MCK_GPR32AsmReg }, }, |
6323 | | { 3229 /* div */, Mips::DivRxRy16, Convert__Reg1_1__Reg1_2, AMFBS_InMips16Mode, { MCK_GPR32ZERO, MCK_CPU16Regs, MCK_CPU16Regs }, }, |
6324 | | { 3229 /* div */, Mips::SDIV, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6325 | | { 3229 /* div */, Mips::SDIV_MM, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6326 | | { 3229 /* div */, Mips::DIV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6327 | | { 3229 /* div */, Mips::DIV_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6328 | | { 3229 /* div */, Mips::SDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, }, |
6329 | | { 3229 /* div */, Mips::SDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6330 | | { 3233 /* div.d */, Mips::FDIV_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
6331 | | { 3233 /* div.d */, Mips::FDIV_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
6332 | | { 3233 /* div.d */, Mips::FDIV_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6333 | | { 3233 /* div.d */, Mips::FDIV_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6334 | | { 3239 /* div.s */, Mips::FDIV_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6335 | | { 3239 /* div.s */, Mips::FDIV_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6336 | | { 3239 /* div.s */, Mips::FDIV_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6337 | | { 3245 /* div_s.b */, Mips::DIV_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6338 | | { 3253 /* div_s.d */, Mips::DIV_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6339 | | { 3261 /* div_s.h */, Mips::DIV_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6340 | | { 3269 /* div_s.w */, Mips::DIV_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6341 | | { 3277 /* div_u.b */, Mips::DIV_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6342 | | { 3285 /* div_u.d */, Mips::DIV_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6343 | | { 3293 /* div_u.h */, Mips::DIV_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6344 | | { 3301 /* div_u.w */, Mips::DIV_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6345 | | { 3309 /* divu */, Mips::DIVU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6346 | | { 3309 /* divu */, Mips::UDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32 }, }, |
6347 | | { 3309 /* divu */, Mips::UDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg }, }, |
6348 | | { 3309 /* divu */, Mips::UDIV, Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32ZeroAsmReg, MCK_GPR32AsmReg }, }, |
6349 | | { 3309 /* divu */, Mips::DivuRxRy16, Convert__Reg1_1__Reg1_2, AMFBS_InMips16Mode, { MCK_GPR32ZERO, MCK_CPU16Regs, MCK_CPU16Regs }, }, |
6350 | | { 3309 /* divu */, Mips::UDIV, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6351 | | { 3309 /* divu */, Mips::UDIV_MM, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6352 | | { 3309 /* divu */, Mips::UDivMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6353 | | { 3309 /* divu */, Mips::DIVU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6354 | | { 3309 /* divu */, Mips::DIVU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6355 | | { 3309 /* divu */, Mips::UDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, }, |
6356 | | { 3314 /* dla */, Mips::LoadAddrImm64, Convert__GPR64AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR64AsmReg, MCK_Imm }, }, |
6357 | | { 3314 /* dla */, Mips::LoadAddrReg64, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR64AsmReg, MCK_Mem }, }, |
6358 | | { 3318 /* dli */, Mips::LoadImm64, Convert__GPR64AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR64AsmReg, MCK_Imm }, }, |
6359 | | { 3322 /* dlsa */, Mips::DLSA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm2_1 }, }, |
6360 | | { 3322 /* dlsa */, Mips::DLSA_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm2_1 }, }, |
6361 | | { 3327 /* dmfc0 */, Mips::DMFC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, }, |
6362 | | { 3327 /* dmfc0 */, Mips::DMFC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
6363 | | { 3333 /* dmfc1 */, Mips::DMFC1, Convert__GPR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, { MCK_GPR64AsmReg, MCK_FGR64AsmReg }, }, |
6364 | | { 3339 /* dmfc2 */, Mips::DMFC2, Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0, AMFBS_None, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, }, |
6365 | | { 3339 /* dmfc2 */, Mips::DMFC2_OCTEON, Convert__GPR64AsmReg1_0__UImm161_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_UImm16 }, }, |
6366 | | { 3339 /* dmfc2 */, Mips::DMFC2, Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3, { MCK_GPR64AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, }, |
6367 | | { 3345 /* dmfgc0 */, Mips::DMFGC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, }, |
6368 | | { 3345 /* dmfgc0 */, Mips::DMFGC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips64r5_HasVirt, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
6369 | | { 3352 /* dmod */, Mips::DMOD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6370 | | { 3357 /* dmodu */, Mips::DMODU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6371 | | { 3363 /* dmt */, Mips::DMT, Convert__regZERO, AMFBS_HasMT_NotInMicroMips, { }, }, |
6372 | | { 3363 /* dmt */, Mips::DMT, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
6373 | | { 3367 /* dmtc0 */, Mips::DMTC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, AMFBS_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, }, |
6374 | | { 3367 /* dmtc0 */, Mips::DMTC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
6375 | | { 3373 /* dmtc1 */, Mips::DMTC1, Convert__FGR64AsmReg1_1__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, { MCK_GPR64AsmReg, MCK_FGR64AsmReg }, }, |
6376 | | { 3379 /* dmtc2 */, Mips::DMTC2, Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0, AMFBS_None, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, }, |
6377 | | { 3379 /* dmtc2 */, Mips::DMTC2_OCTEON, Convert__GPR64AsmReg1_0__UImm161_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_UImm16 }, }, |
6378 | | { 3379 /* dmtc2 */, Mips::DMTC2, Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3, { MCK_GPR64AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, }, |
6379 | | { 3385 /* dmtgc0 */, Mips::DMTGC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, }, |
6380 | | { 3385 /* dmtgc0 */, Mips::DMTGC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips64r5_HasVirt, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
6381 | | { 3392 /* dmuh */, Mips::DMUH, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6382 | | { 3397 /* dmuhu */, Mips::DMUHU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6383 | | { 3403 /* dmul */, Mips::DMUL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6384 | | { 3403 /* dmul */, Mips::DMULMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasMips3_NotMips64r6_NotCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6385 | | { 3403 /* dmul */, Mips::DMUL_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6386 | | { 3403 /* dmul */, Mips::DMUL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6387 | | { 3403 /* dmul */, Mips::DMULImmMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, }, |
6388 | | { 3408 /* dmulo */, Mips::DMULOMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6389 | | { 3414 /* dmulou */, Mips::DMULOUMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6390 | | { 3421 /* dmult */, Mips::DMULT, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6391 | | { 3427 /* dmultu */, Mips::DMULTu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6392 | | { 3434 /* dmulu */, Mips::DMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6393 | | { 3440 /* dneg */, Mips::DSUB, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg }, }, |
6394 | | { 3440 /* dneg */, Mips::DSUB, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6395 | | { 3445 /* dnegu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg }, }, |
6396 | | { 3445 /* dnegu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6397 | | { 3451 /* dotp_s.d */, Mips::DOTP_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6398 | | { 3460 /* dotp_s.h */, Mips::DOTP_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6399 | | { 3469 /* dotp_s.w */, Mips::DOTP_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6400 | | { 3478 /* dotp_u.d */, Mips::DOTP_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6401 | | { 3487 /* dotp_u.h */, Mips::DOTP_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6402 | | { 3496 /* dotp_u.w */, Mips::DOTP_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6403 | | { 3505 /* dpa.w.ph */, Mips::DPA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6404 | | { 3505 /* dpa.w.ph */, Mips::DPA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6405 | | { 3514 /* dpadd_s.d */, Mips::DPADD_S_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6406 | | { 3524 /* dpadd_s.h */, Mips::DPADD_S_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6407 | | { 3534 /* dpadd_s.w */, Mips::DPADD_S_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6408 | | { 3544 /* dpadd_u.d */, Mips::DPADD_U_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6409 | | { 3554 /* dpadd_u.h */, Mips::DPADD_U_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6410 | | { 3564 /* dpadd_u.w */, Mips::DPADD_U_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6411 | | { 3574 /* dpaq_s.w.ph */, Mips::DPAQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6412 | | { 3574 /* dpaq_s.w.ph */, Mips::DPAQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6413 | | { 3586 /* dpaq_sa.l.w */, Mips::DPAQ_SA_L_W_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6414 | | { 3586 /* dpaq_sa.l.w */, Mips::DPAQ_SA_L_W, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6415 | | { 3598 /* dpaqx_s.w.ph */, Mips::DPAQX_S_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6416 | | { 3598 /* dpaqx_s.w.ph */, Mips::DPAQX_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6417 | | { 3611 /* dpaqx_sa.w.ph */, Mips::DPAQX_SA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6418 | | { 3611 /* dpaqx_sa.w.ph */, Mips::DPAQX_SA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6419 | | { 3625 /* dpau.h.qbl */, Mips::DPAU_H_QBL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6420 | | { 3625 /* dpau.h.qbl */, Mips::DPAU_H_QBL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6421 | | { 3636 /* dpau.h.qbr */, Mips::DPAU_H_QBR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6422 | | { 3636 /* dpau.h.qbr */, Mips::DPAU_H_QBR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6423 | | { 3647 /* dpax.w.ph */, Mips::DPAX_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6424 | | { 3647 /* dpax.w.ph */, Mips::DPAX_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6425 | | { 3657 /* dpop */, Mips::DPOP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, }, |
6426 | | { 3657 /* dpop */, Mips::DPOP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6427 | | { 3662 /* dps.w.ph */, Mips::DPS_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6428 | | { 3662 /* dps.w.ph */, Mips::DPS_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6429 | | { 3671 /* dpsq_s.w.ph */, Mips::DPSQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6430 | | { 3671 /* dpsq_s.w.ph */, Mips::DPSQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6431 | | { 3683 /* dpsq_sa.l.w */, Mips::DPSQ_SA_L_W_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6432 | | { 3683 /* dpsq_sa.l.w */, Mips::DPSQ_SA_L_W, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6433 | | { 3695 /* dpsqx_s.w.ph */, Mips::DPSQX_S_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6434 | | { 3695 /* dpsqx_s.w.ph */, Mips::DPSQX_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6435 | | { 3708 /* dpsqx_sa.w.ph */, Mips::DPSQX_SA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6436 | | { 3708 /* dpsqx_sa.w.ph */, Mips::DPSQX_SA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6437 | | { 3722 /* dpsu.h.qbl */, Mips::DPSU_H_QBL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6438 | | { 3722 /* dpsu.h.qbl */, Mips::DPSU_H_QBL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6439 | | { 3733 /* dpsu.h.qbr */, Mips::DPSU_H_QBR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6440 | | { 3733 /* dpsu.h.qbr */, Mips::DPSU_H_QBR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6441 | | { 3744 /* dpsub_s.d */, Mips::DPSUB_S_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6442 | | { 3754 /* dpsub_s.h */, Mips::DPSUB_S_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6443 | | { 3764 /* dpsub_s.w */, Mips::DPSUB_S_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6444 | | { 3774 /* dpsub_u.d */, Mips::DPSUB_U_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6445 | | { 3784 /* dpsub_u.h */, Mips::DPSUB_U_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6446 | | { 3794 /* dpsub_u.w */, Mips::DPSUB_U_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6447 | | { 3804 /* dpsx.w.ph */, Mips::DPSX_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6448 | | { 3804 /* dpsx.w.ph */, Mips::DPSX_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6449 | | { 3814 /* drem */, Mips::DSRemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6450 | | { 3814 /* drem */, Mips::DSRemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, }, |
6451 | | { 3814 /* drem */, Mips::DSRemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6452 | | { 3814 /* drem */, Mips::DSRemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, }, |
6453 | | { 3819 /* dremu */, Mips::DURemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6454 | | { 3819 /* dremu */, Mips::DURemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, }, |
6455 | | { 3819 /* dremu */, Mips::DURemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6456 | | { 3819 /* dremu */, Mips::DURemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, }, |
6457 | | { 3825 /* drol */, Mips::DROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6458 | | { 3825 /* drol */, Mips::DROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
6459 | | { 3825 /* drol */, Mips::DROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6460 | | { 3825 /* drol */, Mips::DROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, |
6461 | | { 3830 /* dror */, Mips::DROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6462 | | { 3830 /* dror */, Mips::DRORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
6463 | | { 3830 /* dror */, Mips::DROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6464 | | { 3830 /* dror */, Mips::DRORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, |
6465 | | { 3835 /* drotr */, Mips::DROTR, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, |
6466 | | { 3835 /* drotr */, Mips::DROTR, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, |
6467 | | { 3841 /* drotr32 */, Mips::DROTR32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, |
6468 | | { 3841 /* drotr32 */, Mips::DROTR32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, |
6469 | | { 3849 /* drotrv */, Mips::DROTRV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, |
6470 | | { 3856 /* dsbh */, Mips::DSBH, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6471 | | { 3861 /* dshd */, Mips::DSHD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6472 | | { 3866 /* dsll */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, |
6473 | | { 3866 /* dsll */, Mips::DSLL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, |
6474 | | { 3866 /* dsll */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, |
6475 | | { 3866 /* dsll */, Mips::DSLL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, |
6476 | | { 3871 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, |
6477 | | { 3871 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, |
6478 | | { 3878 /* dsllv */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, |
6479 | | { 3884 /* dsra */, Mips::DSRA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, |
6480 | | { 3884 /* dsra */, Mips::DSRAV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, |
6481 | | { 3884 /* dsra */, Mips::DSRA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, |
6482 | | { 3889 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, |
6483 | | { 3889 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, |
6484 | | { 3896 /* dsrav */, Mips::DSRAV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, |
6485 | | { 3902 /* dsrl */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, |
6486 | | { 3902 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, |
6487 | | { 3902 /* dsrl */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, |
6488 | | { 3902 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, |
6489 | | { 3907 /* dsrl32 */, Mips::DSRL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, |
6490 | | { 3907 /* dsrl32 */, Mips::DSRL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, |
6491 | | { 3914 /* dsrlv */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, |
6492 | | { 3920 /* dsub */, Mips::DSUB, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6493 | | { 3920 /* dsub */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_InvNum }, }, |
6494 | | { 3920 /* dsub */, Mips::DSUB, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6495 | | { 3920 /* dsub */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, }, |
6496 | | { 3925 /* dsubi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_InvNum }, }, |
6497 | | { 3925 /* dsubi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, }, |
6498 | | { 3931 /* dsubu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6499 | | { 3931 /* dsubu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_InvNum }, }, |
6500 | | { 3931 /* dsubu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6501 | | { 3931 /* dsubu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, }, |
6502 | | { 3937 /* dvp */, Mips::DVP, Convert__regZERO, AMFBS_HasStdEnc_HasMips32r6, { }, }, |
6503 | | { 3937 /* dvp */, Mips::DVP_MMR6, Convert__regZERO, AMFBS_InMicroMips_HasMips32r6, { }, }, |
6504 | | { 3937 /* dvp */, Mips::DVP, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg }, }, |
6505 | | { 3937 /* dvp */, Mips::DVP_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, |
6506 | | { 3941 /* dvpe */, Mips::DVPE, Convert__regZERO, AMFBS_HasMT_NotInMicroMips, { }, }, |
6507 | | { 3941 /* dvpe */, Mips::DVPE, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
6508 | | { 3946 /* ehb */, Mips::EHB, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, }, |
6509 | | { 3946 /* ehb */, Mips::EHB_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, }, |
6510 | | { 3946 /* ehb */, Mips::EHB_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, }, |
6511 | | { 3950 /* ei */, Mips::EI, Convert__regZERO, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { }, }, |
6512 | | { 3950 /* ei */, Mips::EI_MMR6, Convert__regZERO, AMFBS_InMicroMips_HasMips32r6, { }, }, |
6513 | | { 3950 /* ei */, Mips::EI_MM, Convert__regZERO, AMFBS_InMicroMips, { }, }, |
6514 | | { 3950 /* ei */, Mips::EI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
6515 | | { 3950 /* ei */, Mips::EI_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, |
6516 | | { 3950 /* ei */, Mips::EI_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, }, |
6517 | | { 3953 /* emt */, Mips::EMT, Convert__regZERO, AMFBS_HasMT_NotInMicroMips, { }, }, |
6518 | | { 3953 /* emt */, Mips::EMT, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
6519 | | { 3957 /* eret */, Mips::ERET, Convert_NoOperands, AMFBS_HasStdEnc_HasMips3_32_NotInMicroMips, { }, }, |
6520 | | { 3957 /* eret */, Mips::ERET_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, }, |
6521 | | { 3957 /* eret */, Mips::ERET_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, }, |
6522 | | { 3962 /* eretnc */, Mips::ERETNC, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_NotInMicroMips, { }, }, |
6523 | | { 3962 /* eretnc */, Mips::ERETNC_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, }, |
6524 | | { 3969 /* evp */, Mips::EVP, Convert__regZERO, AMFBS_HasStdEnc_HasMips32r6, { }, }, |
6525 | | { 3969 /* evp */, Mips::EVP_MMR6, Convert__regZERO, AMFBS_InMicroMips_HasMips32r6, { }, }, |
6526 | | { 3969 /* evp */, Mips::EVP, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg }, }, |
6527 | | { 3969 /* evp */, Mips::EVP_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, |
6528 | | { 3973 /* evpe */, Mips::EVPE, Convert__regZERO, AMFBS_HasMT_NotInMicroMips, { }, }, |
6529 | | { 3973 /* evpe */, Mips::EVPE, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
6530 | | { 3978 /* ext */, Mips::EXT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, }, |
6531 | | { 3978 /* ext */, Mips::EXT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, }, |
6532 | | { 3978 /* ext */, Mips::EXT_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, }, |
6533 | | { 3982 /* extp */, Mips::EXTP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, |
6534 | | { 3982 /* extp */, Mips::EXTP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, |
6535 | | { 3987 /* extpdp */, Mips::EXTPDP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, |
6536 | | { 3987 /* extpdp */, Mips::EXTPDP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, |
6537 | | { 3994 /* extpdpv */, Mips::EXTPDPV_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
6538 | | { 3994 /* extpdpv */, Mips::EXTPDPV, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
6539 | | { 4002 /* extpv */, Mips::EXTPV_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
6540 | | { 4002 /* extpv */, Mips::EXTPV, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
6541 | | { 4008 /* extr.w */, Mips::EXTR_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, |
6542 | | { 4008 /* extr.w */, Mips::EXTR_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, |
6543 | | { 4015 /* extr_r.w */, Mips::EXTR_R_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, |
6544 | | { 4015 /* extr_r.w */, Mips::EXTR_R_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, |
6545 | | { 4024 /* extr_rs.w */, Mips::EXTR_RS_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, |
6546 | | { 4024 /* extr_rs.w */, Mips::EXTR_RS_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, |
6547 | | { 4034 /* extr_s.h */, Mips::EXTR_S_H_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, |
6548 | | { 4034 /* extr_s.h */, Mips::EXTR_S_H, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, |
6549 | | { 4043 /* extrv.w */, Mips::EXTRV_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
6550 | | { 4043 /* extrv.w */, Mips::EXTRV_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
6551 | | { 4051 /* extrv_r.w */, Mips::EXTRV_R_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
6552 | | { 4051 /* extrv_r.w */, Mips::EXTRV_R_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
6553 | | { 4061 /* extrv_rs.w */, Mips::EXTRV_RS_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
6554 | | { 4061 /* extrv_rs.w */, Mips::EXTRV_RS_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
6555 | | { 4072 /* extrv_s.h */, Mips::EXTRV_S_H_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
6556 | | { 4072 /* extrv_s.h */, Mips::EXTRV_S_H, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
6557 | | { 4082 /* exts */, Mips::EXTS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, |
6558 | | { 4082 /* exts */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, }, |
6559 | | { 4082 /* exts */, Mips::EXTS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, |
6560 | | { 4082 /* exts */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, }, |
6561 | | { 4087 /* exts32 */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, |
6562 | | { 4087 /* exts32 */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, |
6563 | | { 4094 /* fadd.d */, Mips::FADD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6564 | | { 4101 /* fadd.w */, Mips::FADD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6565 | | { 4108 /* fcaf.d */, Mips::FCAF_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6566 | | { 4115 /* fcaf.w */, Mips::FCAF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6567 | | { 4122 /* fceq.d */, Mips::FCEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6568 | | { 4129 /* fceq.w */, Mips::FCEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6569 | | { 4136 /* fclass.d */, Mips::FCLASS_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6570 | | { 4145 /* fclass.w */, Mips::FCLASS_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6571 | | { 4154 /* fcle.d */, Mips::FCLE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6572 | | { 4161 /* fcle.w */, Mips::FCLE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6573 | | { 4168 /* fclt.d */, Mips::FCLT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6574 | | { 4175 /* fclt.w */, Mips::FCLT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6575 | | { 4182 /* fcne.d */, Mips::FCNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6576 | | { 4189 /* fcne.w */, Mips::FCNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6577 | | { 4196 /* fcor.d */, Mips::FCOR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6578 | | { 4203 /* fcor.w */, Mips::FCOR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6579 | | { 4210 /* fcueq.d */, Mips::FCUEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6580 | | { 4218 /* fcueq.w */, Mips::FCUEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6581 | | { 4226 /* fcule.d */, Mips::FCULE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6582 | | { 4234 /* fcule.w */, Mips::FCULE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6583 | | { 4242 /* fcult.d */, Mips::FCULT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6584 | | { 4250 /* fcult.w */, Mips::FCULT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6585 | | { 4258 /* fcun.d */, Mips::FCUN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6586 | | { 4265 /* fcun.w */, Mips::FCUN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6587 | | { 4272 /* fcune.d */, Mips::FCUNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6588 | | { 4280 /* fcune.w */, Mips::FCUNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6589 | | { 4288 /* fdiv.d */, Mips::FDIV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6590 | | { 4295 /* fdiv.w */, Mips::FDIV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6591 | | { 4302 /* fexdo.h */, Mips::FEXDO_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6592 | | { 4310 /* fexdo.w */, Mips::FEXDO_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6593 | | { 4318 /* fexp2.d */, Mips::FEXP2_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6594 | | { 4326 /* fexp2.w */, Mips::FEXP2_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6595 | | { 4334 /* fexupl.d */, Mips::FEXUPL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6596 | | { 4343 /* fexupl.w */, Mips::FEXUPL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6597 | | { 4352 /* fexupr.d */, Mips::FEXUPR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6598 | | { 4361 /* fexupr.w */, Mips::FEXUPR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6599 | | { 4370 /* ffint_s.d */, Mips::FFINT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6600 | | { 4380 /* ffint_s.w */, Mips::FFINT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6601 | | { 4390 /* ffint_u.d */, Mips::FFINT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6602 | | { 4400 /* ffint_u.w */, Mips::FFINT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6603 | | { 4410 /* ffql.d */, Mips::FFQL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6604 | | { 4417 /* ffql.w */, Mips::FFQL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6605 | | { 4424 /* ffqr.d */, Mips::FFQR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6606 | | { 4431 /* ffqr.w */, Mips::FFQR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6607 | | { 4438 /* fill.b */, Mips::FILL_B, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, }, |
6608 | | { 4445 /* fill.d */, Mips::FILL_D, Convert__MSA128AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_MSA128AsmReg, MCK_GPR64AsmReg }, }, |
6609 | | { 4452 /* fill.h */, Mips::FILL_H, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, }, |
6610 | | { 4459 /* fill.w */, Mips::FILL_W, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, }, |
6611 | | { 4466 /* flog2.d */, Mips::FLOG2_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6612 | | { 4474 /* flog2.w */, Mips::FLOG2_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6613 | | { 4482 /* floor.l.d */, Mips::FLOOR_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6614 | | { 4482 /* floor.l.d */, Mips::FLOOR_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6615 | | { 4492 /* floor.l.s */, Mips::FLOOR_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
6616 | | { 4492 /* floor.l.s */, Mips::FLOOR_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
6617 | | { 4502 /* floor.w.d */, Mips::FLOOR_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
6618 | | { 4502 /* floor.w.d */, Mips::FLOOR_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
6619 | | { 4502 /* floor.w.d */, Mips::FLOOR_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
6620 | | { 4502 /* floor.w.d */, Mips::FLOOR_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, |
6621 | | { 4512 /* floor.w.s */, Mips::FLOOR_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6622 | | { 4512 /* floor.w.s */, Mips::FLOOR_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6623 | | { 4512 /* floor.w.s */, Mips::FLOOR_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6624 | | { 4522 /* fmadd.d */, Mips::FMADD_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6625 | | { 4530 /* fmadd.w */, Mips::FMADD_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6626 | | { 4538 /* fmax.d */, Mips::FMAX_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6627 | | { 4545 /* fmax.w */, Mips::FMAX_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6628 | | { 4552 /* fmax_a.d */, Mips::FMAX_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6629 | | { 4561 /* fmax_a.w */, Mips::FMAX_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6630 | | { 4570 /* fmin.d */, Mips::FMIN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6631 | | { 4577 /* fmin.w */, Mips::FMIN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6632 | | { 4584 /* fmin_a.d */, Mips::FMIN_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6633 | | { 4593 /* fmin_a.w */, Mips::FMIN_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6634 | | { 4602 /* fmsub.d */, Mips::FMSUB_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6635 | | { 4610 /* fmsub.w */, Mips::FMSUB_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6636 | | { 4618 /* fmul.d */, Mips::FMUL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6637 | | { 4625 /* fmul.w */, Mips::FMUL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6638 | | { 4632 /* fork */, Mips::FORK, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6639 | | { 4637 /* frcp.d */, Mips::FRCP_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6640 | | { 4644 /* frcp.w */, Mips::FRCP_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6641 | | { 4651 /* frint.d */, Mips::FRINT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6642 | | { 4659 /* frint.w */, Mips::FRINT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6643 | | { 4667 /* frsqrt.d */, Mips::FRSQRT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6644 | | { 4676 /* frsqrt.w */, Mips::FRSQRT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6645 | | { 4685 /* fsaf.d */, Mips::FSAF_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6646 | | { 4692 /* fsaf.w */, Mips::FSAF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6647 | | { 4699 /* fseq.d */, Mips::FSEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6648 | | { 4706 /* fseq.w */, Mips::FSEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6649 | | { 4713 /* fsle.d */, Mips::FSLE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6650 | | { 4720 /* fsle.w */, Mips::FSLE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6651 | | { 4727 /* fslt.d */, Mips::FSLT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6652 | | { 4734 /* fslt.w */, Mips::FSLT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6653 | | { 4741 /* fsne.d */, Mips::FSNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6654 | | { 4748 /* fsne.w */, Mips::FSNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6655 | | { 4755 /* fsor.d */, Mips::FSOR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6656 | | { 4762 /* fsor.w */, Mips::FSOR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6657 | | { 4769 /* fsqrt.d */, Mips::FSQRT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6658 | | { 4777 /* fsqrt.w */, Mips::FSQRT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6659 | | { 4785 /* fsub.d */, Mips::FSUB_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6660 | | { 4792 /* fsub.w */, Mips::FSUB_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6661 | | { 4799 /* fsueq.d */, Mips::FSUEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6662 | | { 4807 /* fsueq.w */, Mips::FSUEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6663 | | { 4815 /* fsule.d */, Mips::FSULE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6664 | | { 4823 /* fsule.w */, Mips::FSULE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6665 | | { 4831 /* fsult.d */, Mips::FSULT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6666 | | { 4839 /* fsult.w */, Mips::FSULT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6667 | | { 4847 /* fsun.d */, Mips::FSUN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6668 | | { 4854 /* fsun.w */, Mips::FSUN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6669 | | { 4861 /* fsune.d */, Mips::FSUNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6670 | | { 4869 /* fsune.w */, Mips::FSUNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6671 | | { 4877 /* ftint_s.d */, Mips::FTINT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6672 | | { 4887 /* ftint_s.w */, Mips::FTINT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6673 | | { 4897 /* ftint_u.d */, Mips::FTINT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6674 | | { 4907 /* ftint_u.w */, Mips::FTINT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6675 | | { 4917 /* ftq.h */, Mips::FTQ_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6676 | | { 4923 /* ftq.w */, Mips::FTQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6677 | | { 4929 /* ftrunc_s.d */, Mips::FTRUNC_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6678 | | { 4940 /* ftrunc_s.w */, Mips::FTRUNC_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6679 | | { 4951 /* ftrunc_u.d */, Mips::FTRUNC_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6680 | | { 4962 /* ftrunc_u.w */, Mips::FTRUNC_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6681 | | { 4973 /* ginvi */, Mips::GINVI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
6682 | | { 4973 /* ginvi */, Mips::GINVI_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6_HasGINV, { MCK_GPR32AsmReg }, }, |
6683 | | { 4979 /* ginvt */, Mips::GINVT, Convert__GPR32AsmReg1_0__ConstantUImm2_01_1, AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, }, |
6684 | | { 4979 /* ginvt */, Mips::GINVT_MMR6, Convert__GPR32AsmReg1_0__ConstantUImm2_01_1, AMFBS_InMicroMips_HasMips32r6_HasGINV, { MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, }, |
6685 | | { 4985 /* hadd_s.d */, Mips::HADD_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6686 | | { 4994 /* hadd_s.h */, Mips::HADD_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6687 | | { 5003 /* hadd_s.w */, Mips::HADD_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6688 | | { 5012 /* hadd_u.d */, Mips::HADD_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6689 | | { 5021 /* hadd_u.h */, Mips::HADD_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6690 | | { 5030 /* hadd_u.w */, Mips::HADD_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6691 | | { 5039 /* hsub_s.d */, Mips::HSUB_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6692 | | { 5048 /* hsub_s.h */, Mips::HSUB_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6693 | | { 5057 /* hsub_s.w */, Mips::HSUB_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6694 | | { 5066 /* hsub_u.d */, Mips::HSUB_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6695 | | { 5075 /* hsub_u.h */, Mips::HSUB_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6696 | | { 5084 /* hsub_u.w */, Mips::HSUB_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6697 | | { 5093 /* hypcall */, Mips::HYPCALL, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, }, |
6698 | | { 5093 /* hypcall */, Mips::HYPCALL_MM, Convert__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, }, |
6699 | | { 5093 /* hypcall */, Mips::HYPCALL, Convert__ConstantUImm10_01_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_ConstantUImm10_0 }, }, |
6700 | | { 5093 /* hypcall */, Mips::HYPCALL_MM, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_ConstantUImm10_0 }, }, |
6701 | | { 5101 /* ilvev.b */, Mips::ILVEV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6702 | | { 5109 /* ilvev.d */, Mips::ILVEV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6703 | | { 5117 /* ilvev.h */, Mips::ILVEV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6704 | | { 5125 /* ilvev.w */, Mips::ILVEV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6705 | | { 5133 /* ilvl.b */, Mips::ILVL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6706 | | { 5140 /* ilvl.d */, Mips::ILVL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6707 | | { 5147 /* ilvl.h */, Mips::ILVL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6708 | | { 5154 /* ilvl.w */, Mips::ILVL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6709 | | { 5161 /* ilvod.b */, Mips::ILVOD_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6710 | | { 5169 /* ilvod.d */, Mips::ILVOD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6711 | | { 5177 /* ilvod.h */, Mips::ILVOD_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6712 | | { 5185 /* ilvod.w */, Mips::ILVOD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6713 | | { 5193 /* ilvr.b */, Mips::ILVR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6714 | | { 5200 /* ilvr.d */, Mips::ILVR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6715 | | { 5207 /* ilvr.h */, Mips::ILVR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6716 | | { 5214 /* ilvr.w */, Mips::ILVR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6717 | | { 5221 /* ins */, Mips::INS, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, }, |
6718 | | { 5221 /* ins */, Mips::INS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, }, |
6719 | | { 5221 /* ins */, Mips::INS_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, }, |
6720 | | { 5225 /* insert.b */, Mips::INSERT_B, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_, MCK_GPR32AsmReg }, }, |
6721 | | { 5234 /* insert.d */, Mips::INSERT_D, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_, MCK_GPR64AsmReg }, }, |
6722 | | { 5243 /* insert.h */, Mips::INSERT_H, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_, MCK_GPR32AsmReg }, }, |
6723 | | { 5252 /* insert.w */, Mips::INSERT_W, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_, MCK_GPR32AsmReg }, }, |
6724 | | { 5261 /* insv */, Mips::INSV_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6725 | | { 5261 /* insv */, Mips::INSV, Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6726 | | { 5266 /* insve.b */, Mips::INSVE_B, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, }, |
6727 | | { 5274 /* insve.d */, Mips::INSVE_D, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, }, |
6728 | | { 5282 /* insve.h */, Mips::INSVE_H, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, }, |
6729 | | { 5290 /* insve.w */, Mips::INSVE_W, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, }, |
6730 | | { 5298 /* j */, Mips::JR, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
6731 | | { 5298 /* j */, Mips::JR_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
6732 | | { 5298 /* j */, Mips::J_MM, Convert__Imm1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_Imm }, }, |
6733 | | { 5298 /* j */, Mips::J, Convert__JumpTarget1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_JumpTarget }, }, |
6734 | | { 5300 /* jal */, Mips::JalOneReg, Convert__GPR32AsmReg1_0, AMFBS_None, { MCK_GPR32AsmReg }, }, |
6735 | | { 5300 /* jal */, Mips::JAL_MM, Convert__Imm1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_Imm }, }, |
6736 | | { 5300 /* jal */, Mips::JAL, Convert__JumpTarget1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_JumpTarget }, }, |
6737 | | { 5300 /* jal */, Mips::BALC_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, }, |
6738 | | { 5300 /* jal */, Mips::JalTwoReg, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6739 | | { 5304 /* jalr */, Mips::JALR16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
6740 | | { 5304 /* jalr */, Mips::JALRC16_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, |
6741 | | { 5304 /* jalr */, Mips::JALR, Convert__regRA__GPR32AsmReg1_0, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
6742 | | { 5304 /* jalr */, Mips::JALR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6743 | | { 5304 /* jalr */, Mips::JALR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6744 | | { 5304 /* jalr */, Mips::JALR64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_NotInMips16Mode_IsPTR64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6745 | | { 5309 /* jalr.hb */, Mips::JALR_HB, Convert__regRA__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
6746 | | { 5309 /* jalr.hb */, Mips::JALR_HB64, Convert__regRA_64__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips64_NotInMicroMips, { MCK_GPR64AsmReg }, }, |
6747 | | { 5309 /* jalr.hb */, Mips::JALR_HB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6748 | | { 5309 /* jalr.hb */, Mips::JALR_HB64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
6749 | | { 5317 /* jalrc */, Mips::JumpLinkReg16, Convert__Reg1_0, AMFBS_InMips16Mode, { MCK_CPU16Regs }, }, |
6750 | | { 5317 /* jalrc */, Mips::JIALC, Convert__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
6751 | | { 5317 /* jalrc */, Mips::JALRC_MMR6, Convert__regRA__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, |
6752 | | { 5317 /* jalrc */, Mips::JIALC64, Convert__GPR64AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR64AsmReg }, }, |
6753 | | { 5317 /* jalrc */, Mips::JALRC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6754 | | { 5323 /* jalrc.hb */, Mips::JALRC_HB_MMR6, Convert__regRA__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, |
6755 | | { 5323 /* jalrc.hb */, Mips::JALRC_HB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6756 | | { 5332 /* jalrs */, Mips::JALRS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6757 | | { 5338 /* jalrs16 */, Mips::JALRS16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
6758 | | { 5346 /* jals */, Mips::JALS_MM, Convert__Imm1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_Imm }, }, |
6759 | | { 5351 /* jalx */, Mips::JALX, Convert__JumpTarget1_0, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_JumpTarget }, }, |
6760 | | { 5351 /* jalx */, Mips::JALX_MM, Convert__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_JumpTarget }, }, |
6761 | | { 5356 /* jialc */, Mips::JIALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
6762 | | { 5356 /* jialc */, Mips::JIALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
6763 | | { 5356 /* jialc */, Mips::JIALC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
6764 | | { 5362 /* jic */, Mips::JIC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
6765 | | { 5362 /* jic */, Mips::JIC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
6766 | | { 5362 /* jic */, Mips::JIC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
6767 | | { 5366 /* jr */, Mips::JrRa16, Convert_NoOperands, AMFBS_InMips16Mode, { MCK_CPURAReg }, }, |
6768 | | { 5366 /* jr */, Mips::JR, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
6769 | | { 5366 /* jr */, Mips::JALR, Convert__regZERO__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
6770 | | { 5366 /* jr */, Mips::JR_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
6771 | | { 5366 /* jr */, Mips::JR64, Convert__GPR64AsmReg1_0, AMFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, { MCK_GPR64AsmReg }, }, |
6772 | | { 5366 /* jr */, Mips::JALR64, Convert__regZERO_64__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR64AsmReg }, }, |
6773 | | { 5369 /* jr.hb */, Mips::JR_HB, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg }, }, |
6774 | | { 5369 /* jr.hb */, Mips::JR_HB_R6, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg }, }, |
6775 | | { 5369 /* jr.hb */, Mips::JR_HB64, Convert__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg }, }, |
6776 | | { 5369 /* jr.hb */, Mips::JR_HB64_R6, Convert__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR64AsmReg }, }, |
6777 | | { 5375 /* jr16 */, Mips::JR16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
6778 | | { 5380 /* jraddiusp */, Mips::JRADDIUSP, Convert__UImm5Lsl21_0, AMFBS_InMicroMips_NotMips32r6, { MCK_UImm5Lsl2 }, }, |
6779 | | { 5390 /* jrc */, Mips::JrcRa16, Convert_NoOperands, AMFBS_InMips16Mode, { MCK_CPURAReg }, }, |
6780 | | { 5390 /* jrc */, Mips::JrcRx16, Convert__Reg1_0, AMFBS_InMips16Mode, { MCK_CPU16Regs }, }, |
6781 | | { 5390 /* jrc */, Mips::JIC, Convert__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6, { MCK_GPR32AsmReg }, }, |
6782 | | { 5390 /* jrc */, Mips::JRC16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
6783 | | { 5390 /* jrc */, Mips::JIC64, Convert__GPR64AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR64AsmReg }, }, |
6784 | | { 5394 /* jrc16 */, Mips::JRC16_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, |
6785 | | { 5400 /* jrcaddiusp */, Mips::JRCADDIUSP_MMR6, Convert__UImm5Lsl21_0, AMFBS_InMicroMips_HasMips32r6, { MCK_UImm5Lsl2 }, }, |
6786 | | { 5411 /* l.d */, Mips::LDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, }, |
6787 | | { 5411 /* l.d */, Mips::LDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, }, |
6788 | | { 5415 /* l.s */, Mips::LWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, }, |
6789 | | { 5419 /* la */, Mips::LoadAddrImm32, Convert__GPR32AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm }, }, |
6790 | | { 5419 /* la */, Mips::LoadAddrReg32, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, }, |
6791 | | { 5422 /* lapc */, Mips::ADDIUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, |
6792 | | { 5422 /* lapc */, Mips::ADDIUPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, |
6793 | | { 5427 /* lb */, Mips::LB_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, }, |
6794 | | { 5427 /* lb */, Mips::LB_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, }, |
6795 | | { 5427 /* lb */, Mips::LB, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, |
6796 | | { 5430 /* lbe */, Mips::LBE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
6797 | | { 5430 /* lbe */, Mips::LBE_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_Mem }, }, |
6798 | | { 5434 /* lbu */, Mips::LBU_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, }, |
6799 | | { 5434 /* lbu */, Mips::LBu_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, }, |
6800 | | { 5434 /* lbu */, Mips::LBu, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, |
6801 | | { 5438 /* lbu16 */, Mips::LBU16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, }, |
6802 | | { 5444 /* lbue */, Mips::LBuE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
6803 | | { 5444 /* lbue */, Mips::LBuE_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_Mem }, }, |
6804 | | { 5449 /* lbux */, Mips::LBUX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
6805 | | { 5449 /* lbux */, Mips::LBUX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
6806 | | { 5454 /* ld */, Mips::LDMacro, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_NotMips3, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, }, |
6807 | | { 5454 /* ld */, Mips::LD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, }, |
6808 | | { 5457 /* ld.b */, Mips::LD_B, Convert__MSA128AsmReg1_0__MemOffsetSimm102_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10 }, }, |
6809 | | { 5462 /* ld.d */, Mips::LD_D, Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_3 }, }, |
6810 | | { 5467 /* ld.h */, Mips::LD_H, Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_1 }, }, |
6811 | | { 5472 /* ld.w */, Mips::LD_W, Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_2 }, }, |
6812 | | { 5477 /* ldc1 */, Mips::LDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, }, |
6813 | | { 5477 /* ldc1 */, Mips::LDC1_MM, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, }, |
6814 | | { 5477 /* ldc1 */, Mips::LDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, }, |
6815 | | { 5477 /* ldc1 */, Mips::LDC1_D64_MMR6, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, }, |
6816 | | { 5482 /* ldc2 */, Mips::LDC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, }, |
6817 | | { 5482 /* ldc2 */, Mips::LDC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, }, |
6818 | | { 5482 /* ldc2 */, Mips::LDC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, }, |
6819 | | { 5487 /* ldc3 */, Mips::LDC3, Convert__COP3AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, }, |
6820 | | { 5492 /* ldi.b */, Mips::LDI_B, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, }, |
6821 | | { 5498 /* ldi.d */, Mips::LDI_D, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, }, |
6822 | | { 5504 /* ldi.h */, Mips::LDI_H, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, }, |
6823 | | { 5510 /* ldi.w */, Mips::LDI_W, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, }, |
6824 | | { 5516 /* ldl */, Mips::LDL, Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, }, |
6825 | | { 5520 /* ldpc */, Mips::LDPC, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
6826 | | { 5525 /* ldr */, Mips::LDR, Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, }, |
6827 | | { 5529 /* ldxc1 */, Mips::LDXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
6828 | | { 5529 /* ldxc1 */, Mips::LDXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
6829 | | { 5535 /* lh */, Mips::LH, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, |
6830 | | { 5535 /* lh */, Mips::LH_MM, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, |
6831 | | { 5538 /* lhe */, Mips::LHE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
6832 | | { 5538 /* lhe */, Mips::LHE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
6833 | | { 5542 /* lhu */, Mips::LHu, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, |
6834 | | { 5542 /* lhu */, Mips::LHu_MM, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, |
6835 | | { 5546 /* lhu16 */, Mips::LHU16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, }, |
6836 | | { 5552 /* lhue */, Mips::LHuE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
6837 | | { 5552 /* lhue */, Mips::LHuE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
6838 | | { 5557 /* lhx */, Mips::LHX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
6839 | | { 5557 /* lhx */, Mips::LHX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
6840 | | { 5561 /* li */, Mips::LiRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, }, |
6841 | | { 5561 /* li */, Mips::LoadImm32, Convert__GPR32AsmReg1_0__UImm32_Coerced1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, }, |
6842 | | { 5561 /* li */, Mips::LiRxImm16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, }, |
6843 | | { 5564 /* li.d */, Mips::LoadImmDoubleGPR, Convert__GPR32AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm }, }, |
6844 | | { 5564 /* li.d */, Mips::LoadImmDoubleFGR_32, Convert__StrictlyAFGR64AsmReg1_0__Imm1_1, AMFBS_NotFP64bit_IsNotSoftFloat, { MCK_StrictlyAFGR64AsmReg, MCK_Imm }, }, |
6845 | | { 5564 /* li.d */, Mips::LoadImmDoubleFGR, Convert__StrictlyFGR64AsmReg1_0__Imm1_1, AMFBS_IsFP64bit_IsNotSoftFloat, { MCK_StrictlyFGR64AsmReg, MCK_Imm }, }, |
6846 | | { 5569 /* li.s */, Mips::LoadImmSingleGPR, Convert__GPR32AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm }, }, |
6847 | | { 5569 /* li.s */, Mips::LoadImmSingleFGR, Convert__StrictlyFGR32AsmReg1_0__Imm1_1, AMFBS_IsNotSoftFloat, { MCK_StrictlyFGR32AsmReg, MCK_Imm }, }, |
6848 | | { 5574 /* li16 */, Mips::LI16_MM, Convert__GPRMM16AsmReg1_0__UImm7_N11_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_UImm7_N1 }, }, |
6849 | | { 5574 /* li16 */, Mips::LI16_MMR6, Convert__GPRMM16AsmReg1_0__UImm7_N11_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_UImm7_N1 }, }, |
6850 | | { 5579 /* ll */, Mips::LL64_R6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
6851 | | { 5579 /* ll */, Mips::LL_R6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
6852 | | { 5579 /* ll */, Mips::LL_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
6853 | | { 5579 /* ll */, Mips::LL, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
6854 | | { 5579 /* ll */, Mips::LL64, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
6855 | | { 5579 /* ll */, Mips::LL_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, |
6856 | | { 5582 /* lld */, Mips::LLD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, }, |
6857 | | { 5582 /* lld */, Mips::LLD_R6, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, }, |
6858 | | { 5586 /* lle */, Mips::LLE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
6859 | | { 5586 /* lle */, Mips::LLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
6860 | | { 5590 /* lsa */, Mips::LSA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, }, |
6861 | | { 5590 /* lsa */, Mips::LSA_MMR6, Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, }, |
6862 | | { 5590 /* lsa */, Mips::LSA_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, }, |
6863 | | { 5594 /* lui */, Mips::LUI_MMR6, Convert__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, |
6864 | | { 5594 /* lui */, Mips::LUi, Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16_Relaxed }, }, |
6865 | | { 5594 /* lui */, Mips::LUi_MM, Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16_Relaxed }, }, |
6866 | | { 5598 /* luxc1 */, Mips::LUXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
6867 | | { 5598 /* luxc1 */, Mips::LUXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
6868 | | { 5598 /* luxc1 */, Mips::LUXC1_MM, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
6869 | | { 5604 /* lw */, Mips::LwRxPcTcpX16, Convert__Reg1_0__Imm1_1__imm_95_0, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_Imm }, }, |
6870 | | { 5604 /* lw */, Mips::LWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, }, |
6871 | | { 5604 /* lw */, Mips::LW, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
6872 | | { 5604 /* lw */, Mips::LWDSP, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_NotInMips16Mode_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, }, |
6873 | | { 5604 /* lw */, Mips::LWDSP_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, }, |
6874 | | { 5604 /* lw */, Mips::LW_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, |
6875 | | { 5604 /* lw */, Mips::LW_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
6876 | | { 5604 /* lw */, Mips::LWGP_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMemGP }, }, |
6877 | | { 5604 /* lw */, Mips::LwRxSpImmX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, }, |
6878 | | { 5604 /* lw */, Mips::LwRxPcTcp16, Convert__Reg1_0__Imm1_1__imm_95_0, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_Imm, MCK__35_, MCK_16, MCK_bit, MCK_inst }, }, |
6879 | | { 5607 /* lw16 */, Mips::LW16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, }, |
6880 | | { 5612 /* lwc1 */, Mips::LWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, }, |
6881 | | { 5612 /* lwc1 */, Mips::LWC1_MM, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, }, |
6882 | | { 5617 /* lwc2 */, Mips::LWC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, }, |
6883 | | { 5617 /* lwc2 */, Mips::LWC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, }, |
6884 | | { 5617 /* lwc2 */, Mips::LWC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, }, |
6885 | | { 5622 /* lwc3 */, Mips::LWC3, Convert__COP3AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, }, |
6886 | | { 5627 /* lwe */, Mips::LWE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
6887 | | { 5627 /* lwe */, Mips::LWE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
6888 | | { 5631 /* lwl */, Mips::LWL, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
6889 | | { 5631 /* lwl */, Mips::LWL_MM, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, |
6890 | | { 5635 /* lwle */, Mips::LWLE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
6891 | | { 5635 /* lwle */, Mips::LWLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
6892 | | { 5640 /* lwm */, Mips::LWM_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, }, |
6893 | | { 5644 /* lwm16 */, Mips::LWM16_MM, Convert__RegList161_0__MemOffsetUimm42_1, AMFBS_InMicroMips_NotMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, }, |
6894 | | { 5644 /* lwm16 */, Mips::LWM16_MMR6, Convert__RegList161_0__MemOffsetUimm42_1, AMFBS_InMicroMips_HasMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, }, |
6895 | | { 5650 /* lwm32 */, Mips::LWM32_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, }, |
6896 | | { 5656 /* lwp */, Mips::LWP_MM, ConvertCustom_ConvertXWPOperands, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12 }, }, |
6897 | | { 5660 /* lwpc */, Mips::LWPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, |
6898 | | { 5660 /* lwpc */, Mips::LWPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, |
6899 | | { 5665 /* lwr */, Mips::LWR, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
6900 | | { 5665 /* lwr */, Mips::LWR_MM, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, |
6901 | | { 5669 /* lwre */, Mips::LWRE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
6902 | | { 5669 /* lwre */, Mips::LWRE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
6903 | | { 5674 /* lwu */, Mips::LWU_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm122_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12 }, }, |
6904 | | { 5674 /* lwu */, Mips::LWu, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Mem }, }, |
6905 | | { 5678 /* lwupc */, Mips::LWUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, |
6906 | | { 5684 /* lwx */, Mips::LWX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
6907 | | { 5684 /* lwx */, Mips::LWX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
6908 | | { 5688 /* lwxc1 */, Mips::LWXC1, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
6909 | | { 5688 /* lwxc1 */, Mips::LWXC1_MM, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
6910 | | { 5694 /* lwxs */, Mips::LWXS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
6911 | | { 5699 /* madd */, Mips::MADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6912 | | { 5699 /* madd */, Mips::MADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6913 | | { 5699 /* madd */, Mips::MADD_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6914 | | { 5699 /* madd */, Mips::MADD_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6915 | | { 5704 /* madd.d */, Mips::MADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
6916 | | { 5704 /* madd.d */, Mips::MADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
6917 | | { 5704 /* madd.d */, Mips::MADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6918 | | { 5711 /* madd.s */, Mips::MADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6919 | | { 5711 /* madd.s */, Mips::MADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6920 | | { 5718 /* madd_q.h */, Mips::MADD_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6921 | | { 5727 /* madd_q.w */, Mips::MADD_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6922 | | { 5736 /* maddf.d */, Mips::MADDF_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6923 | | { 5736 /* maddf.d */, Mips::MADDF_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6924 | | { 5744 /* maddf.s */, Mips::MADDF_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6925 | | { 5744 /* maddf.s */, Mips::MADDF_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6926 | | { 5752 /* maddr_q.h */, Mips::MADDR_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6927 | | { 5762 /* maddr_q.w */, Mips::MADDR_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6928 | | { 5772 /* maddu */, Mips::MADDU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6929 | | { 5772 /* maddu */, Mips::MADDU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6930 | | { 5772 /* maddu */, Mips::MADDU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6931 | | { 5772 /* maddu */, Mips::MADDU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6932 | | { 5778 /* maddv.b */, Mips::MADDV_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6933 | | { 5786 /* maddv.d */, Mips::MADDV_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6934 | | { 5794 /* maddv.h */, Mips::MADDV_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6935 | | { 5802 /* maddv.w */, Mips::MADDV_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6936 | | { 5810 /* maq_s.w.phl */, Mips::MAQ_S_W_PHL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6937 | | { 5810 /* maq_s.w.phl */, Mips::MAQ_S_W_PHL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6938 | | { 5822 /* maq_s.w.phr */, Mips::MAQ_S_W_PHR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6939 | | { 5822 /* maq_s.w.phr */, Mips::MAQ_S_W_PHR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6940 | | { 5834 /* maq_sa.w.phl */, Mips::MAQ_SA_W_PHL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6941 | | { 5834 /* maq_sa.w.phl */, Mips::MAQ_SA_W_PHL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6942 | | { 5847 /* maq_sa.w.phr */, Mips::MAQ_SA_W_PHR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6943 | | { 5847 /* maq_sa.w.phr */, Mips::MAQ_SA_W_PHR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
6944 | | { 5860 /* max.d */, Mips::MAX_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6945 | | { 5860 /* max.d */, Mips::MAX_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6946 | | { 5866 /* max.s */, Mips::MAX_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6947 | | { 5866 /* max.s */, Mips::MAX_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6948 | | { 5872 /* max_a.b */, Mips::MAX_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6949 | | { 5880 /* max_a.d */, Mips::MAX_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6950 | | { 5888 /* max_a.h */, Mips::MAX_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6951 | | { 5896 /* max_a.w */, Mips::MAX_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6952 | | { 5904 /* max_s.b */, Mips::MAX_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6953 | | { 5912 /* max_s.d */, Mips::MAX_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6954 | | { 5920 /* max_s.h */, Mips::MAX_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6955 | | { 5928 /* max_s.w */, Mips::MAX_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6956 | | { 5936 /* max_u.b */, Mips::MAX_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6957 | | { 5944 /* max_u.d */, Mips::MAX_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6958 | | { 5952 /* max_u.h */, Mips::MAX_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6959 | | { 5960 /* max_u.w */, Mips::MAX_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
6960 | | { 5968 /* maxa.d */, Mips::MAXA_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6961 | | { 5968 /* maxa.d */, Mips::MAXA_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
6962 | | { 5975 /* maxa.s */, Mips::MAXA_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6963 | | { 5975 /* maxa.s */, Mips::MAXA_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
6964 | | { 5982 /* maxi_s.b */, Mips::MAXI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
6965 | | { 5991 /* maxi_s.d */, Mips::MAXI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
6966 | | { 6000 /* maxi_s.h */, Mips::MAXI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
6967 | | { 6009 /* maxi_s.w */, Mips::MAXI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
6968 | | { 6018 /* maxi_u.b */, Mips::MAXI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
6969 | | { 6027 /* maxi_u.d */, Mips::MAXI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
6970 | | { 6036 /* maxi_u.h */, Mips::MAXI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
6971 | | { 6045 /* maxi_u.w */, Mips::MAXI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
6972 | | { 6054 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
6973 | | { 6054 /* mfc0 */, Mips::MFC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
6974 | | { 6054 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
6975 | | { 6054 /* mfc0 */, Mips::MFC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
6976 | | { 6059 /* mfc1 */, Mips::MFC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, |
6977 | | { 6059 /* mfc1 */, Mips::MFC1_MMR6, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, |
6978 | | { 6059 /* mfc1 */, Mips::MFC1_MM, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, |
6979 | | { 6059 /* mfc1 */, Mips::MFC1_D64, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, }, |
6980 | | { 6064 /* mfc2 */, Mips::MFC2_MMR6, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, |
6981 | | { 6064 /* mfc2 */, Mips::MFC2, Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, |
6982 | | { 6064 /* mfc2 */, Mips::MFC2, Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, }, |
6983 | | { 6069 /* mfgc0 */, Mips::MFGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
6984 | | { 6069 /* mfgc0 */, Mips::MFGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
6985 | | { 6069 /* mfgc0 */, Mips::MFGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
6986 | | { 6069 /* mfgc0 */, Mips::MFGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
6987 | | { 6075 /* mfhc0 */, Mips::MFHC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
6988 | | { 6075 /* mfhc0 */, Mips::MFHC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
6989 | | { 6081 /* mfhc1 */, Mips::MFHC1_D32, Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, }, |
6990 | | { 6081 /* mfhc1 */, Mips::MFHC1_D32_MM, Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, }, |
6991 | | { 6081 /* mfhc1 */, Mips::MFHC1_D64, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, }, |
6992 | | { 6081 /* mfhc1 */, Mips::MFHC1_D64_MM, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, }, |
6993 | | { 6087 /* mfhc2 */, Mips::MFHC2_MMR6, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, |
6994 | | { 6093 /* mfhgc0 */, Mips::MFHGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
6995 | | { 6093 /* mfhgc0 */, Mips::MFHGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
6996 | | { 6093 /* mfhgc0 */, Mips::MFHGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
6997 | | { 6093 /* mfhgc0 */, Mips::MFHGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
6998 | | { 6100 /* mfhi */, Mips::Mfhi16, Convert__Reg1_0, AMFBS_InMips16Mode, { MCK_CPU16Regs }, }, |
6999 | | { 6100 /* mfhi */, Mips::MFHI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
7000 | | { 6100 /* mfhi */, Mips::MFHI_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
7001 | | { 6100 /* mfhi */, Mips::MFHI_DSP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, |
7002 | | { 6100 /* mfhi */, Mips::MFHI_DSP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, |
7003 | | { 6105 /* mfhi16 */, Mips::MFHI16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
7004 | | { 6112 /* mflo */, Mips::Mflo16, Convert__Reg1_0, AMFBS_InMips16Mode, { MCK_CPU16Regs }, }, |
7005 | | { 6112 /* mflo */, Mips::MFLO, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
7006 | | { 6112 /* mflo */, Mips::MFLO_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
7007 | | { 6112 /* mflo */, Mips::MFLO_DSP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, |
7008 | | { 6112 /* mflo */, Mips::MFLO_DSP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, |
7009 | | { 6117 /* mflo16 */, Mips::MFLO16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
7010 | | { 6124 /* mftacx */, Mips::MFTACX, Convert__GPR32AsmReg1_0__regAC0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
7011 | | { 6124 /* mftacx */, Mips::MFTACX, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, |
7012 | | { 6131 /* mftc0 */, Mips::MFTC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
7013 | | { 6131 /* mftc0 */, Mips::MFTC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
7014 | | { 6137 /* mftc1 */, Mips::MFTC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, |
7015 | | { 6143 /* mftdsp */, Mips::MFTDSP, Convert__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg }, }, |
7016 | | { 6150 /* mftgpr */, Mips::MFTGPR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7017 | | { 6157 /* mfthc1 */, Mips::MFTHC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, |
7018 | | { 6164 /* mfthi */, Mips::MFTHI, Convert__GPR32AsmReg1_0__regAC0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
7019 | | { 6164 /* mfthi */, Mips::MFTHI, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, |
7020 | | { 6170 /* mftlo */, Mips::MFTLO, Convert__GPR32AsmReg1_0__regAC0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
7021 | | { 6170 /* mftlo */, Mips::MFTLO, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, |
7022 | | { 6176 /* mftr */, Mips::MFTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm1_0, MCK_ConstantUImm3_0, MCK_ConstantUImm1_0 }, }, |
7023 | | { 6181 /* min.d */, Mips::MIN_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7024 | | { 6181 /* min.d */, Mips::MIN_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7025 | | { 6187 /* min.s */, Mips::MIN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7026 | | { 6187 /* min.s */, Mips::MIN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7027 | | { 6193 /* min_a.b */, Mips::MIN_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7028 | | { 6201 /* min_a.d */, Mips::MIN_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7029 | | { 6209 /* min_a.h */, Mips::MIN_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7030 | | { 6217 /* min_a.w */, Mips::MIN_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7031 | | { 6225 /* min_s.b */, Mips::MIN_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7032 | | { 6233 /* min_s.d */, Mips::MIN_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7033 | | { 6241 /* min_s.h */, Mips::MIN_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7034 | | { 6249 /* min_s.w */, Mips::MIN_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7035 | | { 6257 /* min_u.b */, Mips::MIN_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7036 | | { 6265 /* min_u.d */, Mips::MIN_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7037 | | { 6273 /* min_u.h */, Mips::MIN_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7038 | | { 6281 /* min_u.w */, Mips::MIN_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7039 | | { 6289 /* mina.d */, Mips::MINA_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7040 | | { 6289 /* mina.d */, Mips::MINA_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7041 | | { 6296 /* mina.s */, Mips::MINA_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7042 | | { 6296 /* mina.s */, Mips::MINA_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7043 | | { 6303 /* mini_s.b */, Mips::MINI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
7044 | | { 6312 /* mini_s.d */, Mips::MINI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
7045 | | { 6321 /* mini_s.h */, Mips::MINI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
7046 | | { 6330 /* mini_s.w */, Mips::MINI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
7047 | | { 6339 /* mini_u.b */, Mips::MINI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
7048 | | { 6348 /* mini_u.d */, Mips::MINI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
7049 | | { 6357 /* mini_u.h */, Mips::MINI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
7050 | | { 6366 /* mini_u.w */, Mips::MINI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
7051 | | { 6375 /* mod */, Mips::MOD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7052 | | { 6375 /* mod */, Mips::MOD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7053 | | { 6379 /* mod_s.b */, Mips::MOD_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7054 | | { 6387 /* mod_s.d */, Mips::MOD_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7055 | | { 6395 /* mod_s.h */, Mips::MOD_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7056 | | { 6403 /* mod_s.w */, Mips::MOD_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7057 | | { 6411 /* mod_u.b */, Mips::MOD_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7058 | | { 6419 /* mod_u.d */, Mips::MOD_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7059 | | { 6427 /* mod_u.h */, Mips::MOD_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7060 | | { 6435 /* mod_u.w */, Mips::MOD_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7061 | | { 6443 /* modsub */, Mips::MODSUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7062 | | { 6443 /* modsub */, Mips::MODSUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7063 | | { 6450 /* modu */, Mips::MODU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7064 | | { 6450 /* modu */, Mips::MODU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7065 | | { 6455 /* mov.d */, Mips::FMOV_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
7066 | | { 6455 /* mov.d */, Mips::FMOV_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
7067 | | { 6455 /* mov.d */, Mips::FMOV_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7068 | | { 6455 /* mov.d */, Mips::FMOV_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7069 | | { 6455 /* mov.d */, Mips::FMOV_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7070 | | { 6461 /* mov.s */, Mips::FMOV_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7071 | | { 6461 /* mov.s */, Mips::FMOV_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7072 | | { 6461 /* mov.s */, Mips::FMOV_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7073 | | { 6467 /* move */, Mips::MoveR3216, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_DSPR }, }, |
7074 | | { 6467 /* move */, Mips::Move32R16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_DSPR, MCK_CPU16Regs }, }, |
7075 | | { 6467 /* move */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7076 | | { 6467 /* move */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7077 | | { 6467 /* move */, Mips::MOVE16_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7078 | | { 6467 /* move */, Mips::OR64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, AMFBS_IsGP64bit_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
7079 | | { 6467 /* move */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, AMFBS_IsGP64bit_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
7080 | | { 6472 /* move.v */, Mips::MOVE_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7081 | | { 6479 /* move16 */, Mips::MOVE16_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7082 | | { 6486 /* movep */, Mips::MOVEP_MM, Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmRegMovePPairFirst, MCK_GPRMM16AsmRegMovePPairSecond, MCK_GPRMM16AsmRegMoveP, MCK_GPRMM16AsmRegMoveP }, }, |
7083 | | { 6486 /* movep */, Mips::MOVEP_MMR6, Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegMovePPairFirst, MCK_GPRMM16AsmRegMovePPairSecond, MCK_GPRMM16AsmRegMoveP, MCK_GPRMM16AsmRegMoveP }, }, |
7084 | | { 6492 /* movf */, Mips::MOVF_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, }, |
7085 | | { 6492 /* movf */, Mips::MOVF_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, }, |
7086 | | { 6497 /* movf.d */, Mips::MOVF_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, }, |
7087 | | { 6497 /* movf.d */, Mips::MOVF_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, }, |
7088 | | { 6497 /* movf.d */, Mips::MOVF_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FCCAsmReg }, }, |
7089 | | { 6504 /* movf.s */, Mips::MOVF_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, }, |
7090 | | { 6504 /* movf.s */, Mips::MOVF_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, }, |
7091 | | { 6511 /* movn */, Mips::MOVN_I_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7092 | | { 6511 /* movn */, Mips::MOVN_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7093 | | { 6516 /* movn.d */, Mips::MOVN_I_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, }, |
7094 | | { 6516 /* movn.d */, Mips::MOVN_I_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, }, |
7095 | | { 6516 /* movn.d */, Mips::MOVN_I_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, }, |
7096 | | { 6523 /* movn.s */, Mips::MOVN_I_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, }, |
7097 | | { 6523 /* movn.s */, Mips::MOVN_I_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, }, |
7098 | | { 6530 /* movt */, Mips::MOVT_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, }, |
7099 | | { 6530 /* movt */, Mips::MOVT_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, }, |
7100 | | { 6535 /* movt.d */, Mips::MOVT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, }, |
7101 | | { 6535 /* movt.d */, Mips::MOVT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, }, |
7102 | | { 6535 /* movt.d */, Mips::MOVT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FCCAsmReg }, }, |
7103 | | { 6542 /* movt.s */, Mips::MOVT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, }, |
7104 | | { 6542 /* movt.s */, Mips::MOVT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, }, |
7105 | | { 6549 /* movz */, Mips::MOVZ_I_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7106 | | { 6549 /* movz */, Mips::MOVZ_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7107 | | { 6554 /* movz.d */, Mips::MOVZ_I_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, }, |
7108 | | { 6554 /* movz.d */, Mips::MOVZ_I_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, }, |
7109 | | { 6554 /* movz.d */, Mips::MOVZ_I_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, }, |
7110 | | { 6561 /* movz.s */, Mips::MOVZ_I_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, }, |
7111 | | { 6561 /* movz.s */, Mips::MOVZ_I_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, }, |
7112 | | { 6568 /* msub */, Mips::MSUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7113 | | { 6568 /* msub */, Mips::MSUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7114 | | { 6568 /* msub */, Mips::MSUB_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7115 | | { 6568 /* msub */, Mips::MSUB_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7116 | | { 6573 /* msub.d */, Mips::MSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
7117 | | { 6573 /* msub.d */, Mips::MSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
7118 | | { 6573 /* msub.d */, Mips::MSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7119 | | { 6580 /* msub.s */, Mips::MSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7120 | | { 6580 /* msub.s */, Mips::MSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7121 | | { 6587 /* msub_q.h */, Mips::MSUB_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7122 | | { 6596 /* msub_q.w */, Mips::MSUB_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7123 | | { 6605 /* msubf.d */, Mips::MSUBF_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7124 | | { 6605 /* msubf.d */, Mips::MSUBF_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7125 | | { 6613 /* msubf.s */, Mips::MSUBF_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7126 | | { 6613 /* msubf.s */, Mips::MSUBF_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7127 | | { 6621 /* msubr_q.h */, Mips::MSUBR_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7128 | | { 6631 /* msubr_q.w */, Mips::MSUBR_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7129 | | { 6641 /* msubu */, Mips::MSUBU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7130 | | { 6641 /* msubu */, Mips::MSUBU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7131 | | { 6641 /* msubu */, Mips::MSUBU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7132 | | { 6641 /* msubu */, Mips::MSUBU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7133 | | { 6647 /* msubv.b */, Mips::MSUBV_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7134 | | { 6655 /* msubv.d */, Mips::MSUBV_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7135 | | { 6663 /* msubv.h */, Mips::MSUBV_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7136 | | { 6671 /* msubv.w */, Mips::MSUBV_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7137 | | { 6679 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
7138 | | { 6679 /* mtc0 */, Mips::MTC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
7139 | | { 6679 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
7140 | | { 6679 /* mtc0 */, Mips::MTC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
7141 | | { 6684 /* mtc1 */, Mips::MTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, |
7142 | | { 6684 /* mtc1 */, Mips::MTC1_MMR6, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, |
7143 | | { 6684 /* mtc1 */, Mips::MTC1_MM, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, |
7144 | | { 6684 /* mtc1 */, Mips::MTC1_D64, Convert__FGR64AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, }, |
7145 | | { 6684 /* mtc1 */, Mips::MTC1_D64_MM, Convert__FGR64AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, }, |
7146 | | { 6689 /* mtc2 */, Mips::MTC2_MMR6, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, |
7147 | | { 6689 /* mtc2 */, Mips::MTC2, Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, |
7148 | | { 6689 /* mtc2 */, Mips::MTC2, Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, }, |
7149 | | { 6694 /* mtgc0 */, Mips::MTGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
7150 | | { 6694 /* mtgc0 */, Mips::MTGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
7151 | | { 6694 /* mtgc0 */, Mips::MTGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
7152 | | { 6694 /* mtgc0 */, Mips::MTGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
7153 | | { 6700 /* mthc0 */, Mips::MTHC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
7154 | | { 6700 /* mthc0 */, Mips::MTHC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
7155 | | { 6706 /* mthc1 */, Mips::MTHC1_D32, Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, }, |
7156 | | { 6706 /* mthc1 */, Mips::MTHC1_D32_MM, Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, }, |
7157 | | { 6706 /* mthc1 */, Mips::MTHC1_D64, Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, }, |
7158 | | { 6706 /* mthc1 */, Mips::MTHC1_D64_MM, Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, }, |
7159 | | { 6712 /* mthc2 */, Mips::MTHC2_MMR6, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, |
7160 | | { 6718 /* mthgc0 */, Mips::MTHGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
7161 | | { 6718 /* mthgc0 */, Mips::MTHGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
7162 | | { 6718 /* mthgc0 */, Mips::MTHGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
7163 | | { 6718 /* mthgc0 */, Mips::MTHGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
7164 | | { 6725 /* mthi */, Mips::MTHI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
7165 | | { 6725 /* mthi */, Mips::MTHI_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
7166 | | { 6725 /* mthi */, Mips::MTHI_DSP_MM, Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_HI32DSPAsmReg }, }, |
7167 | | { 6725 /* mthi */, Mips::MTHI_DSP, Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_HI32DSPAsmReg }, }, |
7168 | | { 6730 /* mthlip */, Mips::MTHLIP_MM, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, |
7169 | | { 6730 /* mthlip */, Mips::MTHLIP, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, |
7170 | | { 6737 /* mtlo */, Mips::MTLO, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
7171 | | { 6737 /* mtlo */, Mips::MTLO_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
7172 | | { 6737 /* mtlo */, Mips::MTLO_DSP_MM, Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_LO32DSPAsmReg }, }, |
7173 | | { 6737 /* mtlo */, Mips::MTLO_DSP, Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_LO32DSPAsmReg }, }, |
7174 | | { 6742 /* mtm0 */, Mips::MTM0, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, }, |
7175 | | { 6747 /* mtm1 */, Mips::MTM1, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, }, |
7176 | | { 6752 /* mtm2 */, Mips::MTM2, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, }, |
7177 | | { 6757 /* mtp0 */, Mips::MTP0, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, }, |
7178 | | { 6762 /* mtp1 */, Mips::MTP1, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, }, |
7179 | | { 6767 /* mtp2 */, Mips::MTP2, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, }, |
7180 | | { 6772 /* mttacx */, Mips::MTTACX, Convert__regAC0__GPR32AsmReg1_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
7181 | | { 6772 /* mttacx */, Mips::MTTACX, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, |
7182 | | { 6779 /* mttc0 */, Mips::MTTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
7183 | | { 6779 /* mttc0 */, Mips::MTTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
7184 | | { 6785 /* mttc1 */, Mips::MTTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, |
7185 | | { 6791 /* mttdsp */, Mips::MTTDSP, Convert__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg }, }, |
7186 | | { 6798 /* mttgpr */, Mips::MTTGPR, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7187 | | { 6805 /* mtthc1 */, Mips::MTTHC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, |
7188 | | { 6812 /* mtthi */, Mips::MTTHI, Convert__regAC0__GPR32AsmReg1_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
7189 | | { 6812 /* mtthi */, Mips::MTTHI, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, |
7190 | | { 6818 /* mttlo */, Mips::MTTLO, Convert__regAC0__GPR32AsmReg1_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
7191 | | { 6818 /* mttlo */, Mips::MTTLO, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, |
7192 | | { 6824 /* mttr */, Mips::MTTR, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm1_0, MCK_ConstantUImm3_0, MCK_ConstantUImm1_0 }, }, |
7193 | | { 6829 /* muh */, Mips::MUH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7194 | | { 6829 /* muh */, Mips::MUH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7195 | | { 6829 /* muh */, Mips::MUH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7196 | | { 6833 /* muhu */, Mips::MUHU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7197 | | { 6833 /* muhu */, Mips::MUHU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7198 | | { 6833 /* muhu */, Mips::MUHU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7199 | | { 6838 /* mul */, Mips::MUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7200 | | { 6838 /* mul */, Mips::MUL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7201 | | { 6838 /* mul */, Mips::MUL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7202 | | { 6838 /* mul */, Mips::MUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7203 | | { 6838 /* mul */, Mips::MUL_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7204 | | { 6838 /* mul */, Mips::MUL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7205 | | { 6838 /* mul */, Mips::MUL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7206 | | { 6838 /* mul */, Mips::MULImmMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
7207 | | { 6842 /* mul.d */, Mips::FMUL_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
7208 | | { 6842 /* mul.d */, Mips::FMUL_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
7209 | | { 6842 /* mul.d */, Mips::FMUL_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7210 | | { 6842 /* mul.d */, Mips::FMUL_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7211 | | { 6848 /* mul.ph */, Mips::MUL_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7212 | | { 6848 /* mul.ph */, Mips::MUL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7213 | | { 6855 /* mul.s */, Mips::FMUL_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7214 | | { 6855 /* mul.s */, Mips::FMUL_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7215 | | { 6855 /* mul.s */, Mips::FMUL_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7216 | | { 6861 /* mul_q.h */, Mips::MUL_Q_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7217 | | { 6869 /* mul_q.w */, Mips::MUL_Q_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7218 | | { 6877 /* mul_s.ph */, Mips::MUL_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7219 | | { 6877 /* mul_s.ph */, Mips::MUL_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7220 | | { 6886 /* muleq_s.w.phl */, Mips::MULEQ_S_W_PHL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7221 | | { 6886 /* muleq_s.w.phl */, Mips::MULEQ_S_W_PHL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7222 | | { 6900 /* muleq_s.w.phr */, Mips::MULEQ_S_W_PHR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7223 | | { 6900 /* muleq_s.w.phr */, Mips::MULEQ_S_W_PHR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7224 | | { 6914 /* muleu_s.ph.qbl */, Mips::MULEU_S_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7225 | | { 6914 /* muleu_s.ph.qbl */, Mips::MULEU_S_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7226 | | { 6929 /* muleu_s.ph.qbr */, Mips::MULEU_S_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7227 | | { 6929 /* muleu_s.ph.qbr */, Mips::MULEU_S_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7228 | | { 6944 /* mulo */, Mips::MULOMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7229 | | { 6944 /* mulo */, Mips::MULOMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7230 | | { 6949 /* mulou */, Mips::MULOUMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7231 | | { 6949 /* mulou */, Mips::MULOUMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7232 | | { 6955 /* mulq_rs.ph */, Mips::MULQ_RS_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7233 | | { 6955 /* mulq_rs.ph */, Mips::MULQ_RS_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7234 | | { 6966 /* mulq_rs.w */, Mips::MULQ_RS_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7235 | | { 6966 /* mulq_rs.w */, Mips::MULQ_RS_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7236 | | { 6976 /* mulq_s.ph */, Mips::MULQ_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7237 | | { 6976 /* mulq_s.ph */, Mips::MULQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7238 | | { 6986 /* mulq_s.w */, Mips::MULQ_S_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7239 | | { 6986 /* mulq_s.w */, Mips::MULQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7240 | | { 6995 /* mulr_q.h */, Mips::MULR_Q_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7241 | | { 7004 /* mulr_q.w */, Mips::MULR_Q_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7242 | | { 7013 /* mulsa.w.ph */, Mips::MULSA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7243 | | { 7013 /* mulsa.w.ph */, Mips::MULSA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7244 | | { 7024 /* mulsaq_s.w.ph */, Mips::MULSAQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7245 | | { 7024 /* mulsaq_s.w.ph */, Mips::MULSAQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7246 | | { 7038 /* mult */, Mips::MULT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7247 | | { 7038 /* mult */, Mips::MULT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7248 | | { 7038 /* mult */, Mips::MULT_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7249 | | { 7038 /* mult */, Mips::MULT_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7250 | | { 7043 /* multu */, Mips::MULTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7251 | | { 7043 /* multu */, Mips::MULTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7252 | | { 7043 /* multu */, Mips::MULTU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7253 | | { 7043 /* multu */, Mips::MULTU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7254 | | { 7049 /* mulu */, Mips::MULU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7255 | | { 7049 /* mulu */, Mips::MULU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7256 | | { 7049 /* mulu */, Mips::MULU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7257 | | { 7054 /* mulv.b */, Mips::MULV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7258 | | { 7061 /* mulv.d */, Mips::MULV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7259 | | { 7068 /* mulv.h */, Mips::MULV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7260 | | { 7075 /* mulv.w */, Mips::MULV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7261 | | { 7082 /* neg */, Mips::SUB, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
7262 | | { 7082 /* neg */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
7263 | | { 7082 /* neg */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, |
7264 | | { 7082 /* neg */, Mips::NegRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, |
7265 | | { 7082 /* neg */, Mips::SUB, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7266 | | { 7082 /* neg */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7267 | | { 7082 /* neg */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7268 | | { 7086 /* neg.d */, Mips::FNEG_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
7269 | | { 7086 /* neg.d */, Mips::FNEG_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
7270 | | { 7086 /* neg.d */, Mips::FNEG_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7271 | | { 7086 /* neg.d */, Mips::FNEG_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7272 | | { 7092 /* neg.s */, Mips::FNEG_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7273 | | { 7092 /* neg.s */, Mips::FNEG_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7274 | | { 7092 /* neg.s */, Mips::FNEG_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7275 | | { 7098 /* negu */, Mips::SUBu, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
7276 | | { 7098 /* negu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
7277 | | { 7098 /* negu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, |
7278 | | { 7098 /* negu */, Mips::SUBu, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7279 | | { 7098 /* negu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7280 | | { 7098 /* negu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7281 | | { 7103 /* nloc.b */, Mips::NLOC_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7282 | | { 7110 /* nloc.d */, Mips::NLOC_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7283 | | { 7117 /* nloc.h */, Mips::NLOC_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7284 | | { 7124 /* nloc.w */, Mips::NLOC_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7285 | | { 7131 /* nlzc.b */, Mips::NLZC_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7286 | | { 7138 /* nlzc.d */, Mips::NLZC_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7287 | | { 7145 /* nlzc.h */, Mips::NLZC_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7288 | | { 7152 /* nlzc.w */, Mips::NLZC_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7289 | | { 7159 /* nmadd.d */, Mips::NMADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
7290 | | { 7159 /* nmadd.d */, Mips::NMADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
7291 | | { 7159 /* nmadd.d */, Mips::NMADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7292 | | { 7167 /* nmadd.s */, Mips::NMADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7293 | | { 7167 /* nmadd.s */, Mips::NMADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7294 | | { 7175 /* nmsub.d */, Mips::NMSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
7295 | | { 7175 /* nmsub.d */, Mips::NMSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
7296 | | { 7175 /* nmsub.d */, Mips::NMSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7297 | | { 7183 /* nmsub.s */, Mips::NMSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7298 | | { 7183 /* nmsub.s */, Mips::NMSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7299 | | { 7191 /* nop */, Mips::SLL, Convert__regZERO__regZERO__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { }, }, |
7300 | | { 7191 /* nop */, Mips::SLL_MMR6, Convert__regZERO__regZERO__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { }, }, |
7301 | | { 7191 /* nop */, Mips::Move32R16, Convert__regZERO__regS0, AMFBS_InMips16Mode, { }, }, |
7302 | | { 7191 /* nop */, Mips::SLL_MM, Convert__regZERO__regZERO__imm_95_0, AMFBS_InMicroMips, { }, }, |
7303 | | { 7191 /* nop */, Mips::MOVE16_MM, Convert__regZERO__regZERO, AMFBS_InMicroMips, { }, }, |
7304 | | { 7195 /* nor */, Mips::NORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_IsGP32bit, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
7305 | | { 7195 /* nor */, Mips::NORImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, }, |
7306 | | { 7195 /* nor */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7307 | | { 7195 /* nor */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7308 | | { 7195 /* nor */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7309 | | { 7195 /* nor */, Mips::NORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_IsGP32bit, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
7310 | | { 7195 /* nor */, Mips::NORImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, |
7311 | | { 7199 /* nor.v */, Mips::NOR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7312 | | { 7205 /* nori.b */, Mips::NORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, |
7313 | | { 7212 /* not */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
7314 | | { 7212 /* not */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
7315 | | { 7212 /* not */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, |
7316 | | { 7212 /* not */, Mips::NotRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, |
7317 | | { 7212 /* not */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7318 | | { 7212 /* not */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7319 | | { 7212 /* not */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7320 | | { 7216 /* not16 */, Mips::NOT16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, |
7321 | | { 7216 /* not16 */, Mips::NOT16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, |
7322 | | { 7222 /* or */, Mips::OrRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, |
7323 | | { 7222 /* or */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7324 | | { 7222 /* or */, Mips::OR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7325 | | { 7222 /* or */, Mips::OR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7326 | | { 7222 /* or */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, |
7327 | | { 7222 /* or */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
7328 | | { 7222 /* or */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
7329 | | { 7222 /* or */, Mips::ORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, }, |
7330 | | { 7222 /* or */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7331 | | { 7222 /* or */, Mips::OR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7332 | | { 7222 /* or */, Mips::OR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7333 | | { 7222 /* or */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
7334 | | { 7222 /* or */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
7335 | | { 7222 /* or */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
7336 | | { 7222 /* or */, Mips::ORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, |
7337 | | { 7225 /* or.v */, Mips::OR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7338 | | { 7230 /* or16 */, Mips::OR16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, |
7339 | | { 7230 /* or16 */, Mips::OR16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, |
7340 | | { 7235 /* ori */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, |
7341 | | { 7235 /* ori */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, }, |
7342 | | { 7235 /* ori */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, |
7343 | | { 7235 /* ori */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
7344 | | { 7235 /* ori */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
7345 | | { 7235 /* ori */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
7346 | | { 7239 /* ori.b */, Mips::ORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, |
7347 | | { 7245 /* packrl.ph */, Mips::PACKRL_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7348 | | { 7245 /* packrl.ph */, Mips::PACKRL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7349 | | { 7255 /* pause */, Mips::PAUSE, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { }, }, |
7350 | | { 7255 /* pause */, Mips::PAUSE_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, }, |
7351 | | { 7255 /* pause */, Mips::PAUSE_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, }, |
7352 | | { 7261 /* pckev.b */, Mips::PCKEV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7353 | | { 7269 /* pckev.d */, Mips::PCKEV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7354 | | { 7277 /* pckev.h */, Mips::PCKEV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7355 | | { 7285 /* pckev.w */, Mips::PCKEV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7356 | | { 7293 /* pckod.b */, Mips::PCKOD_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7357 | | { 7301 /* pckod.d */, Mips::PCKOD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7358 | | { 7309 /* pckod.h */, Mips::PCKOD_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7359 | | { 7317 /* pckod.w */, Mips::PCKOD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7360 | | { 7325 /* pcnt.b */, Mips::PCNT_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7361 | | { 7332 /* pcnt.d */, Mips::PCNT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7362 | | { 7339 /* pcnt.h */, Mips::PCNT_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7363 | | { 7346 /* pcnt.w */, Mips::PCNT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7364 | | { 7353 /* pick.ph */, Mips::PICK_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7365 | | { 7353 /* pick.ph */, Mips::PICK_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7366 | | { 7361 /* pick.qb */, Mips::PICK_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7367 | | { 7361 /* pick.qb */, Mips::PICK_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7368 | | { 7369 /* pll.ps */, Mips::PLL_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7369 | | { 7376 /* plu.ps */, Mips::PLU_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7370 | | { 7383 /* pop */, Mips::POP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR32AsmReg }, }, |
7371 | | { 7383 /* pop */, Mips::POP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7372 | | { 7387 /* preceq.w.phl */, Mips::PRECEQ_W_PHL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7373 | | { 7387 /* preceq.w.phl */, Mips::PRECEQ_W_PHL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7374 | | { 7400 /* preceq.w.phr */, Mips::PRECEQ_W_PHR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7375 | | { 7400 /* preceq.w.phr */, Mips::PRECEQ_W_PHR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7376 | | { 7413 /* precequ.ph.qbl */, Mips::PRECEQU_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7377 | | { 7413 /* precequ.ph.qbl */, Mips::PRECEQU_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7378 | | { 7428 /* precequ.ph.qbla */, Mips::PRECEQU_PH_QBLA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7379 | | { 7428 /* precequ.ph.qbla */, Mips::PRECEQU_PH_QBLA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7380 | | { 7444 /* precequ.ph.qbr */, Mips::PRECEQU_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7381 | | { 7444 /* precequ.ph.qbr */, Mips::PRECEQU_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7382 | | { 7459 /* precequ.ph.qbra */, Mips::PRECEQU_PH_QBRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7383 | | { 7459 /* precequ.ph.qbra */, Mips::PRECEQU_PH_QBRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7384 | | { 7475 /* preceu.ph.qbl */, Mips::PRECEU_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7385 | | { 7475 /* preceu.ph.qbl */, Mips::PRECEU_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7386 | | { 7489 /* preceu.ph.qbla */, Mips::PRECEU_PH_QBLA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7387 | | { 7489 /* preceu.ph.qbla */, Mips::PRECEU_PH_QBLA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7388 | | { 7504 /* preceu.ph.qbr */, Mips::PRECEU_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7389 | | { 7504 /* preceu.ph.qbr */, Mips::PRECEU_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7390 | | { 7518 /* preceu.ph.qbra */, Mips::PRECEU_PH_QBRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7391 | | { 7518 /* preceu.ph.qbra */, Mips::PRECEU_PH_QBRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7392 | | { 7533 /* precr.qb.ph */, Mips::PRECR_QB_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7393 | | { 7533 /* precr.qb.ph */, Mips::PRECR_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7394 | | { 7545 /* precr_sra.ph.w */, Mips::PRECR_SRA_PH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7395 | | { 7545 /* precr_sra.ph.w */, Mips::PRECR_SRA_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7396 | | { 7560 /* precr_sra_r.ph.w */, Mips::PRECR_SRA_R_PH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7397 | | { 7560 /* precr_sra_r.ph.w */, Mips::PRECR_SRA_R_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7398 | | { 7577 /* precrq.ph.w */, Mips::PRECRQ_PH_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7399 | | { 7577 /* precrq.ph.w */, Mips::PRECRQ_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7400 | | { 7589 /* precrq.qb.ph */, Mips::PRECRQ_QB_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7401 | | { 7589 /* precrq.qb.ph */, Mips::PRECRQ_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7402 | | { 7602 /* precrq_rs.ph.w */, Mips::PRECRQ_RS_PH_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7403 | | { 7602 /* precrq_rs.ph.w */, Mips::PRECRQ_RS_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7404 | | { 7617 /* precrqu_s.qb.ph */, Mips::PRECRQU_S_QB_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7405 | | { 7617 /* precrqu_s.qb.ph */, Mips::PRECRQU_S_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7406 | | { 7633 /* pref */, Mips::PREF_R6, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, }, |
7407 | | { 7633 /* pref */, Mips::PREF, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_Mem }, }, |
7408 | | { 7633 /* pref */, Mips::PREF_MM, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, }, |
7409 | | { 7633 /* pref */, Mips::PREF_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, }, |
7410 | | { 7638 /* prefe */, Mips::PREFE, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, }, |
7411 | | { 7638 /* prefe */, Mips::PREFE_MM, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasEVA, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, }, |
7412 | | { 7644 /* prefx */, Mips::PREFX_MM, Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm5_0, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
7413 | | { 7650 /* prepend */, Mips::PREPEND_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7414 | | { 7650 /* prepend */, Mips::PREPEND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7415 | | { 7658 /* raddu.w.qb */, Mips::RADDU_W_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7416 | | { 7658 /* raddu.w.qb */, Mips::RADDU_W_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7417 | | { 7669 /* rddsp */, Mips::RDDSP_MM, Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm7_0 }, }, |
7418 | | { 7669 /* rddsp */, Mips::RDDSP, Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, |
7419 | | { 7675 /* rdhwr */, Mips::RDHWR, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, }, |
7420 | | { 7675 /* rdhwr */, Mips::RDHWR_MM, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, }, |
7421 | | { 7675 /* rdhwr */, Mips::RDHWR_MMR6, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, }, |
7422 | | { 7675 /* rdhwr */, Mips::RDHWR64, Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_HWRegsAsmReg }, }, |
7423 | | { 7675 /* rdhwr */, Mips::RDHWR_MMR6, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm3_0 }, }, |
7424 | | { 7675 /* rdhwr */, Mips::RDHWR, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm8_0 }, }, |
7425 | | { 7675 /* rdhwr */, Mips::RDHWR_MM, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm8_0 }, }, |
7426 | | { 7681 /* rdpgpr */, Mips::RDPGPR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7427 | | { 7688 /* recip.d */, Mips::RECIP_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
7428 | | { 7688 /* recip.d */, Mips::RECIP_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
7429 | | { 7688 /* recip.d */, Mips::RECIP_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7430 | | { 7688 /* recip.d */, Mips::RECIP_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7431 | | { 7696 /* recip.s */, Mips::RECIP_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7432 | | { 7696 /* recip.s */, Mips::RECIP_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7433 | | { 7704 /* rem */, Mips::SRemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7434 | | { 7704 /* rem */, Mips::SRemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
7435 | | { 7704 /* rem */, Mips::SRemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7436 | | { 7704 /* rem */, Mips::SRemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
7437 | | { 7708 /* remu */, Mips::URemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7438 | | { 7708 /* remu */, Mips::URemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
7439 | | { 7708 /* remu */, Mips::URemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7440 | | { 7708 /* remu */, Mips::URemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
7441 | | { 7713 /* repl.ph */, Mips::REPL_PH_MM, Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantSImm10_0 }, }, |
7442 | | { 7713 /* repl.ph */, Mips::REPL_PH, Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantSImm10_0 }, }, |
7443 | | { 7721 /* repl.qb */, Mips::REPL_QB_MM, Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm8_0 }, }, |
7444 | | { 7721 /* repl.qb */, Mips::REPL_QB, Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm8_0 }, }, |
7445 | | { 7729 /* replv.ph */, Mips::REPLV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7446 | | { 7729 /* replv.ph */, Mips::REPLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7447 | | { 7738 /* replv.qb */, Mips::REPLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7448 | | { 7738 /* replv.qb */, Mips::REPLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7449 | | { 7747 /* rint.d */, Mips::RINT_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7450 | | { 7747 /* rint.d */, Mips::RINT_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7451 | | { 7754 /* rint.s */, Mips::RINT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7452 | | { 7754 /* rint.s */, Mips::RINT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7453 | | { 7761 /* rol */, Mips::ROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7454 | | { 7761 /* rol */, Mips::ROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
7455 | | { 7761 /* rol */, Mips::ROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7456 | | { 7761 /* rol */, Mips::ROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, |
7457 | | { 7765 /* ror */, Mips::ROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7458 | | { 7765 /* ror */, Mips::RORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
7459 | | { 7765 /* ror */, Mips::ROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7460 | | { 7765 /* ror */, Mips::RORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, |
7461 | | { 7769 /* rotr */, Mips::ROTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7462 | | { 7769 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7463 | | { 7769 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7464 | | { 7769 /* rotr */, Mips::ROTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7465 | | { 7769 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7466 | | { 7774 /* rotrv */, Mips::ROTRV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7467 | | { 7774 /* rotrv */, Mips::ROTRV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7468 | | { 7780 /* round.l.d */, Mips::ROUND_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7469 | | { 7780 /* round.l.d */, Mips::ROUND_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7470 | | { 7790 /* round.l.s */, Mips::ROUND_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
7471 | | { 7790 /* round.l.s */, Mips::ROUND_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
7472 | | { 7800 /* round.w.d */, Mips::ROUND_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
7473 | | { 7800 /* round.w.d */, Mips::ROUND_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
7474 | | { 7800 /* round.w.d */, Mips::ROUND_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, |
7475 | | { 7800 /* round.w.d */, Mips::ROUND_W_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7476 | | { 7810 /* round.w.s */, Mips::ROUND_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7477 | | { 7810 /* round.w.s */, Mips::ROUND_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7478 | | { 7810 /* round.w.s */, Mips::ROUND_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7479 | | { 7820 /* rsqrt.d */, Mips::RSQRT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
7480 | | { 7820 /* rsqrt.d */, Mips::RSQRT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
7481 | | { 7820 /* rsqrt.d */, Mips::RSQRT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7482 | | { 7820 /* rsqrt.d */, Mips::RSQRT_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7483 | | { 7828 /* rsqrt.s */, Mips::RSQRT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7484 | | { 7828 /* rsqrt.s */, Mips::RSQRT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7485 | | { 7836 /* s.d */, Mips::SDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, }, |
7486 | | { 7836 /* s.d */, Mips::SDC1_M1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, }, |
7487 | | { 7836 /* s.d */, Mips::SDC1_M1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, }, |
7488 | | { 7836 /* s.d */, Mips::SDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, }, |
7489 | | { 7840 /* s.s */, Mips::SWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, }, |
7490 | | { 7844 /* sat_s.b */, Mips::SAT_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, |
7491 | | { 7852 /* sat_s.d */, Mips::SAT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, |
7492 | | { 7860 /* sat_s.h */, Mips::SAT_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, |
7493 | | { 7868 /* sat_s.w */, Mips::SAT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
7494 | | { 7876 /* sat_u.b */, Mips::SAT_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, |
7495 | | { 7884 /* sat_u.d */, Mips::SAT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, |
7496 | | { 7892 /* sat_u.h */, Mips::SAT_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, |
7497 | | { 7900 /* sat_u.w */, Mips::SAT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
7498 | | { 7908 /* sb */, Mips::SB, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
7499 | | { 7908 /* sb */, Mips::SB_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, |
7500 | | { 7908 /* sb */, Mips::SB_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
7501 | | { 7908 /* sb */, Mips::SbRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, }, |
7502 | | { 7911 /* sb16 */, Mips::SB16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, }, |
7503 | | { 7911 /* sb16 */, Mips::SB16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, }, |
7504 | | { 7916 /* sbe */, Mips::SBE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
7505 | | { 7916 /* sbe */, Mips::SBE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
7506 | | { 7920 /* sc */, Mips::SC64_R6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
7507 | | { 7920 /* sc */, Mips::SC_R6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
7508 | | { 7920 /* sc */, Mips::SC_MMR6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
7509 | | { 7920 /* sc */, Mips::SC, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
7510 | | { 7920 /* sc */, Mips::SC64, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
7511 | | { 7920 /* sc */, Mips::SC_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, |
7512 | | { 7923 /* scd */, Mips::SCD_R6, Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR64AsmReg, MCK_MemOffsetSimm9 }, }, |
7513 | | { 7923 /* scd */, Mips::SCD, Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, }, |
7514 | | { 7927 /* sce */, Mips::SCE, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
7515 | | { 7927 /* sce */, Mips::SCE_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
7516 | | { 7931 /* sd */, Mips::SDMacro, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_NotMips3, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, }, |
7517 | | { 7931 /* sd */, Mips::SD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, }, |
7518 | | { 7934 /* sdbbp */, Mips::SDBBP, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, { }, }, |
7519 | | { 7934 /* sdbbp */, Mips::SDBBP_R6, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { }, }, |
7520 | | { 7934 /* sdbbp */, Mips::SDBBP_MMR6, Convert__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { }, }, |
7521 | | { 7934 /* sdbbp */, Mips::SDBBP_MM, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, }, |
7522 | | { 7934 /* sdbbp */, Mips::SDBBP, Convert__ConstantUImm20_01_0, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_ConstantUImm20_0 }, }, |
7523 | | { 7934 /* sdbbp */, Mips::SDBBP_R6, Convert__ConstantUImm20_01_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_ConstantUImm20_0 }, }, |
7524 | | { 7934 /* sdbbp */, Mips::SDBBP_MMR6, Convert__ConstantUImm20_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm20_0 }, }, |
7525 | | { 7940 /* sdbbp16 */, Mips::SDBBP16_MM, Convert__ConstantUImm4_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm4_0 }, }, |
7526 | | { 7940 /* sdbbp16 */, Mips::SDBBP16_MMR6, Convert__ConstantUImm4_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm4_0 }, }, |
7527 | | { 7948 /* sdc1 */, Mips::SDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, }, |
7528 | | { 7948 /* sdc1 */, Mips::SDC1_MM, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, }, |
7529 | | { 7948 /* sdc1 */, Mips::SDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, }, |
7530 | | { 7948 /* sdc1 */, Mips::SDC1_D64_MMR6, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, }, |
7531 | | { 7953 /* sdc2 */, Mips::SDC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, }, |
7532 | | { 7953 /* sdc2 */, Mips::SDC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, }, |
7533 | | { 7953 /* sdc2 */, Mips::SDC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, }, |
7534 | | { 7958 /* sdc3 */, Mips::SDC3, Convert__COP3AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, }, |
7535 | | { 7963 /* sdl */, Mips::SDL, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, }, |
7536 | | { 7967 /* sdr */, Mips::SDR, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, }, |
7537 | | { 7971 /* sdxc1 */, Mips::SDXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
7538 | | { 7971 /* sdxc1 */, Mips::SDXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
7539 | | { 7977 /* seb */, Mips::SebRx16, Convert__Reg1_0__Tie0_1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs }, }, |
7540 | | { 7977 /* seb */, Mips::SEB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
7541 | | { 7977 /* seb */, Mips::SEB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, }, |
7542 | | { 7977 /* seb */, Mips::SEB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7543 | | { 7977 /* seb */, Mips::SEB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7544 | | { 7981 /* seh */, Mips::SehRx16, Convert__Reg1_0__Tie0_1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs }, }, |
7545 | | { 7981 /* seh */, Mips::SEH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
7546 | | { 7981 /* seh */, Mips::SEH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, }, |
7547 | | { 7981 /* seh */, Mips::SEH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7548 | | { 7981 /* seh */, Mips::SEH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7549 | | { 7985 /* sel.d */, Mips::SEL_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7550 | | { 7985 /* sel.d */, Mips::SEL_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7551 | | { 7991 /* sel.s */, Mips::SEL_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7552 | | { 7991 /* sel.s */, Mips::SEL_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7553 | | { 7997 /* seleqz */, Mips::SELEQZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7554 | | { 7997 /* seleqz */, Mips::SELEQZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7555 | | { 7997 /* seleqz */, Mips::SELEQZ64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips32r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
7556 | | { 8004 /* seleqz.d */, Mips::SELEQZ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7557 | | { 8004 /* seleqz.d */, Mips::SELEQZ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7558 | | { 8013 /* seleqz.s */, Mips::SELEQZ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7559 | | { 8013 /* seleqz.s */, Mips::SELEQZ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7560 | | { 8022 /* selnez */, Mips::SELNEZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7561 | | { 8022 /* selnez */, Mips::SELNEZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7562 | | { 8022 /* selnez */, Mips::SELNEZ64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips32r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
7563 | | { 8029 /* selnez.d */, Mips::SELNEZ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7564 | | { 8029 /* selnez.d */, Mips::SELNEZ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7565 | | { 8038 /* selnez.s */, Mips::SELNEZ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7566 | | { 8038 /* selnez.s */, Mips::SELNEZ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7567 | | { 8047 /* seq */, Mips::SEQMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7568 | | { 8047 /* seq */, Mips::SEQIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_SImm32 }, }, |
7569 | | { 8047 /* seq */, Mips::SEQ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
7570 | | { 8047 /* seq */, Mips::SEQMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7571 | | { 8047 /* seq */, Mips::SEQIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
7572 | | { 8047 /* seq */, Mips::SEQ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
7573 | | { 8051 /* seqi */, Mips::SEQi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, }, |
7574 | | { 8051 /* seqi */, Mips::SEQi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, }, |
7575 | | { 8056 /* sge */, Mips::SGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7576 | | { 8056 /* sge */, Mips::SGEImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32 }, }, |
7577 | | { 8056 /* sge */, Mips::SGEImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, }, |
7578 | | { 8056 /* sge */, Mips::SGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7579 | | { 8056 /* sge */, Mips::SGEImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, }, |
7580 | | { 8056 /* sge */, Mips::SGEImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, |
7581 | | { 8060 /* sgeu */, Mips::SGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7582 | | { 8060 /* sgeu */, Mips::SGEUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, }, |
7583 | | { 8060 /* sgeu */, Mips::SGEUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, }, |
7584 | | { 8060 /* sgeu */, Mips::SGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7585 | | { 8060 /* sgeu */, Mips::SGEUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm32_Coerced }, }, |
7586 | | { 8060 /* sgeu */, Mips::SGEUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, |
7587 | | { 8065 /* sgt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7588 | | { 8065 /* sgt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7589 | | { 8065 /* sgt */, Mips::SGTImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32 }, }, |
7590 | | { 8065 /* sgt */, Mips::SGTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, }, |
7591 | | { 8065 /* sgt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7592 | | { 8065 /* sgt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7593 | | { 8065 /* sgt */, Mips::SGTImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, }, |
7594 | | { 8065 /* sgt */, Mips::SGTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, |
7595 | | { 8069 /* sgtu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7596 | | { 8069 /* sgtu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7597 | | { 8069 /* sgtu */, Mips::SGTUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, }, |
7598 | | { 8069 /* sgtu */, Mips::SGTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, }, |
7599 | | { 8069 /* sgtu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7600 | | { 8069 /* sgtu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7601 | | { 8069 /* sgtu */, Mips::SGTUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm32_Coerced }, }, |
7602 | | { 8069 /* sgtu */, Mips::SGTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, |
7603 | | { 8074 /* sh */, Mips::SH, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
7604 | | { 8074 /* sh */, Mips::SH_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, |
7605 | | { 8074 /* sh */, Mips::SH_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
7606 | | { 8074 /* sh */, Mips::ShRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, }, |
7607 | | { 8077 /* sh16 */, Mips::SH16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, }, |
7608 | | { 8077 /* sh16 */, Mips::SH16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, }, |
7609 | | { 8082 /* she */, Mips::SHE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
7610 | | { 8082 /* she */, Mips::SHE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
7611 | | { 8086 /* shf.b */, Mips::SHF_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, |
7612 | | { 8092 /* shf.h */, Mips::SHF_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, |
7613 | | { 8098 /* shf.w */, Mips::SHF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, |
7614 | | { 8104 /* shilo */, Mips::SHILO_MM, Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_ConstantSImm6_0 }, }, |
7615 | | { 8104 /* shilo */, Mips::SHILO, Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_ConstantSImm6_0 }, }, |
7616 | | { 8110 /* shilov */, Mips::SHILOV_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
7617 | | { 8110 /* shilov */, Mips::SHILOV, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
7618 | | { 8117 /* shll.ph */, Mips::SHLL_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
7619 | | { 8117 /* shll.ph */, Mips::SHLL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
7620 | | { 8125 /* shll.qb */, Mips::SHLL_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, |
7621 | | { 8125 /* shll.qb */, Mips::SHLL_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, |
7622 | | { 8133 /* shll_s.ph */, Mips::SHLL_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
7623 | | { 8133 /* shll_s.ph */, Mips::SHLL_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
7624 | | { 8143 /* shll_s.w */, Mips::SHLL_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7625 | | { 8143 /* shll_s.w */, Mips::SHLL_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7626 | | { 8152 /* shllv.ph */, Mips::SHLLV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7627 | | { 8152 /* shllv.ph */, Mips::SHLLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7628 | | { 8161 /* shllv.qb */, Mips::SHLLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7629 | | { 8161 /* shllv.qb */, Mips::SHLLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7630 | | { 8170 /* shllv_s.ph */, Mips::SHLLV_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7631 | | { 8170 /* shllv_s.ph */, Mips::SHLLV_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7632 | | { 8181 /* shllv_s.w */, Mips::SHLLV_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7633 | | { 8181 /* shllv_s.w */, Mips::SHLLV_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7634 | | { 8191 /* shra.ph */, Mips::SHRA_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
7635 | | { 8191 /* shra.ph */, Mips::SHRA_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
7636 | | { 8199 /* shra.qb */, Mips::SHRA_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, |
7637 | | { 8199 /* shra.qb */, Mips::SHRA_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, |
7638 | | { 8207 /* shra_r.ph */, Mips::SHRA_R_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
7639 | | { 8207 /* shra_r.ph */, Mips::SHRA_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
7640 | | { 8217 /* shra_r.qb */, Mips::SHRA_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, |
7641 | | { 8217 /* shra_r.qb */, Mips::SHRA_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, |
7642 | | { 8227 /* shra_r.w */, Mips::SHRA_R_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7643 | | { 8227 /* shra_r.w */, Mips::SHRA_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7644 | | { 8236 /* shrav.ph */, Mips::SHRAV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7645 | | { 8236 /* shrav.ph */, Mips::SHRAV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7646 | | { 8245 /* shrav.qb */, Mips::SHRAV_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7647 | | { 8245 /* shrav.qb */, Mips::SHRAV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7648 | | { 8254 /* shrav_r.ph */, Mips::SHRAV_R_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7649 | | { 8254 /* shrav_r.ph */, Mips::SHRAV_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7650 | | { 8265 /* shrav_r.qb */, Mips::SHRAV_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7651 | | { 8265 /* shrav_r.qb */, Mips::SHRAV_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7652 | | { 8276 /* shrav_r.w */, Mips::SHRAV_R_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7653 | | { 8276 /* shrav_r.w */, Mips::SHRAV_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7654 | | { 8286 /* shrl.ph */, Mips::SHRL_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
7655 | | { 8286 /* shrl.ph */, Mips::SHRL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
7656 | | { 8294 /* shrl.qb */, Mips::SHRL_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, |
7657 | | { 8294 /* shrl.qb */, Mips::SHRL_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, |
7658 | | { 8302 /* shrlv.ph */, Mips::SHRLV_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7659 | | { 8302 /* shrlv.ph */, Mips::SHRLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7660 | | { 8311 /* shrlv.qb */, Mips::SHRLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7661 | | { 8311 /* shrlv.qb */, Mips::SHRLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7662 | | { 8320 /* sigrie */, Mips::SIGRIE, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { }, }, |
7663 | | { 8320 /* sigrie */, Mips::SIGRIE_MMR6, Convert__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { }, }, |
7664 | | { 8320 /* sigrie */, Mips::SIGRIE, Convert__UImm161_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_UImm16 }, }, |
7665 | | { 8320 /* sigrie */, Mips::SIGRIE_MMR6, Convert__UImm161_0, AMFBS_InMicroMips_HasMips32r6, { MCK_UImm16 }, }, |
7666 | | { 8327 /* sld.b */, Mips::SLD_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, |
7667 | | { 8333 /* sld.d */, Mips::SLD_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, |
7668 | | { 8339 /* sld.h */, Mips::SLD_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, |
7669 | | { 8345 /* sld.w */, Mips::SLD_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, |
7670 | | { 8351 /* sldi.b */, Mips::SLDI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, }, |
7671 | | { 8358 /* sldi.d */, Mips::SLDI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, }, |
7672 | | { 8365 /* sldi.h */, Mips::SLDI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, }, |
7673 | | { 8372 /* sldi.w */, Mips::SLDI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, }, |
7674 | | { 8379 /* sll */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7675 | | { 8379 /* sll */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7676 | | { 8379 /* sll */, Mips::SLL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7677 | | { 8379 /* sll */, Mips::SLL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7678 | | { 8379 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7679 | | { 8379 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7680 | | { 8379 /* sll */, Mips::SllX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, }, |
7681 | | { 8379 /* sll */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7682 | | { 8379 /* sll */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7683 | | { 8379 /* sll */, Mips::SLL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7684 | | { 8379 /* sll */, Mips::SLL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7685 | | { 8379 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7686 | | { 8383 /* sll.b */, Mips::SLL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7687 | | { 8389 /* sll.d */, Mips::SLL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7688 | | { 8395 /* sll.h */, Mips::SLL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7689 | | { 8401 /* sll.w */, Mips::SLL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7690 | | { 8407 /* sll16 */, Mips::SLL16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, |
7691 | | { 8407 /* sll16 */, Mips::SLL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, |
7692 | | { 8413 /* slli.b */, Mips::SLLI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, |
7693 | | { 8420 /* slli.d */, Mips::SLLI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, |
7694 | | { 8427 /* slli.h */, Mips::SLLI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, |
7695 | | { 8434 /* slli.w */, Mips::SLLI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
7696 | | { 8441 /* sllv */, Mips::SllvRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, |
7697 | | { 8441 /* sllv */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7698 | | { 8441 /* sllv */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7699 | | { 8446 /* slt */, Mips::SltRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, |
7700 | | { 8446 /* slt */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
7701 | | { 8446 /* slt */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
7702 | | { 8446 /* slt */, Mips::SLTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, }, |
7703 | | { 8446 /* slt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7704 | | { 8446 /* slt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7705 | | { 8446 /* slt */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
7706 | | { 8446 /* slt */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
7707 | | { 8446 /* slt */, Mips::SLTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, |
7708 | | { 8450 /* slti */, Mips::SltiRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, }, |
7709 | | { 8450 /* slti */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, |
7710 | | { 8450 /* slti */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, |
7711 | | { 8450 /* slti */, Mips::SltiRxImm16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, }, |
7712 | | { 8455 /* sltiu */, Mips::SltiuRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, }, |
7713 | | { 8455 /* sltiu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, |
7714 | | { 8455 /* sltiu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, |
7715 | | { 8455 /* sltiu */, Mips::SltiuRxImm16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, }, |
7716 | | { 8461 /* sltu */, Mips::SltuRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, |
7717 | | { 8461 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
7718 | | { 8461 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
7719 | | { 8461 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, }, |
7720 | | { 8461 /* sltu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7721 | | { 8461 /* sltu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7722 | | { 8461 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
7723 | | { 8461 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
7724 | | { 8461 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, |
7725 | | { 8466 /* sne */, Mips::SNE, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
7726 | | { 8466 /* sne */, Mips::SNE, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
7727 | | { 8470 /* snei */, Mips::SNEi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, }, |
7728 | | { 8470 /* snei */, Mips::SNEi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, }, |
7729 | | { 8475 /* splat.b */, Mips::SPLAT_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, |
7730 | | { 8483 /* splat.d */, Mips::SPLAT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, |
7731 | | { 8491 /* splat.h */, Mips::SPLAT_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, |
7732 | | { 8499 /* splat.w */, Mips::SPLAT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, |
7733 | | { 8507 /* splati.b */, Mips::SPLATI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, }, |
7734 | | { 8516 /* splati.d */, Mips::SPLATI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, }, |
7735 | | { 8525 /* splati.h */, Mips::SPLATI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, }, |
7736 | | { 8534 /* splati.w */, Mips::SPLATI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, }, |
7737 | | { 8543 /* sqrt.d */, Mips::FSQRT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
7738 | | { 8543 /* sqrt.d */, Mips::FSQRT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
7739 | | { 8543 /* sqrt.d */, Mips::FSQRT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7740 | | { 8543 /* sqrt.d */, Mips::FSQRT_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7741 | | { 8550 /* sqrt.s */, Mips::FSQRT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7742 | | { 8550 /* sqrt.s */, Mips::FSQRT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7743 | | { 8557 /* sra */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7744 | | { 8557 /* sra */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7745 | | { 8557 /* sra */, Mips::SRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7746 | | { 8557 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7747 | | { 8557 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7748 | | { 8557 /* sra */, Mips::SraX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, }, |
7749 | | { 8557 /* sra */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7750 | | { 8557 /* sra */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7751 | | { 8557 /* sra */, Mips::SRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7752 | | { 8557 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7753 | | { 8561 /* sra.b */, Mips::SRA_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7754 | | { 8567 /* sra.d */, Mips::SRA_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7755 | | { 8573 /* sra.h */, Mips::SRA_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7756 | | { 8579 /* sra.w */, Mips::SRA_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7757 | | { 8585 /* srai.b */, Mips::SRAI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, |
7758 | | { 8592 /* srai.d */, Mips::SRAI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, |
7759 | | { 8599 /* srai.h */, Mips::SRAI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, |
7760 | | { 8606 /* srai.w */, Mips::SRAI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
7761 | | { 8613 /* srar.b */, Mips::SRAR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7762 | | { 8620 /* srar.d */, Mips::SRAR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7763 | | { 8627 /* srar.h */, Mips::SRAR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7764 | | { 8634 /* srar.w */, Mips::SRAR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7765 | | { 8641 /* srari.b */, Mips::SRARI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, |
7766 | | { 8649 /* srari.d */, Mips::SRARI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, |
7767 | | { 8657 /* srari.h */, Mips::SRARI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, |
7768 | | { 8665 /* srari.w */, Mips::SRARI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
7769 | | { 8673 /* srav */, Mips::SravRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, |
7770 | | { 8673 /* srav */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7771 | | { 8673 /* srav */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7772 | | { 8678 /* srl */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7773 | | { 8678 /* srl */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7774 | | { 8678 /* srl */, Mips::SRL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7775 | | { 8678 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7776 | | { 8678 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7777 | | { 8678 /* srl */, Mips::SrlX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, }, |
7778 | | { 8678 /* srl */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7779 | | { 8678 /* srl */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7780 | | { 8678 /* srl */, Mips::SRL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7781 | | { 8678 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
7782 | | { 8682 /* srl.b */, Mips::SRL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7783 | | { 8688 /* srl.d */, Mips::SRL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7784 | | { 8694 /* srl.h */, Mips::SRL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7785 | | { 8700 /* srl.w */, Mips::SRL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7786 | | { 8706 /* srl16 */, Mips::SRL16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, |
7787 | | { 8706 /* srl16 */, Mips::SRL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, |
7788 | | { 8712 /* srli.b */, Mips::SRLI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, |
7789 | | { 8719 /* srli.d */, Mips::SRLI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, |
7790 | | { 8726 /* srli.h */, Mips::SRLI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, |
7791 | | { 8733 /* srli.w */, Mips::SRLI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
7792 | | { 8740 /* srlr.b */, Mips::SRLR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7793 | | { 8747 /* srlr.d */, Mips::SRLR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7794 | | { 8754 /* srlr.h */, Mips::SRLR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7795 | | { 8761 /* srlr.w */, Mips::SRLR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7796 | | { 8768 /* srlri.b */, Mips::SRLRI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, |
7797 | | { 8776 /* srlri.d */, Mips::SRLRI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, |
7798 | | { 8784 /* srlri.h */, Mips::SRLRI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, |
7799 | | { 8792 /* srlri.w */, Mips::SRLRI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
7800 | | { 8800 /* srlv */, Mips::SrlvRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, |
7801 | | { 8800 /* srlv */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7802 | | { 8800 /* srlv */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7803 | | { 8805 /* ssnop */, Mips::SSNOP, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, }, |
7804 | | { 8805 /* ssnop */, Mips::SSNOP_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, }, |
7805 | | { 8805 /* ssnop */, Mips::SSNOP_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, }, |
7806 | | { 8811 /* st.b */, Mips::ST_B, Convert__MSA128AsmReg1_0__MemOffsetSimm102_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10 }, }, |
7807 | | { 8816 /* st.d */, Mips::ST_D, Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_3 }, }, |
7808 | | { 8821 /* st.h */, Mips::ST_H, Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_1 }, }, |
7809 | | { 8826 /* st.w */, Mips::ST_W, Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_2 }, }, |
7810 | | { 8831 /* sub */, Mips::SUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7811 | | { 8831 /* sub */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7812 | | { 8831 /* sub */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7813 | | { 8831 /* sub */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_InvNum }, }, |
7814 | | { 8831 /* sub */, Mips::SUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7815 | | { 8831 /* sub */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7816 | | { 8831 /* sub */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7817 | | { 8831 /* sub */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_InvNum }, }, |
7818 | | { 8835 /* sub.d */, Mips::FSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
7819 | | { 8835 /* sub.d */, Mips::FSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
7820 | | { 8835 /* sub.d */, Mips::FSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7821 | | { 8835 /* sub.d */, Mips::FSUB_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
7822 | | { 8841 /* sub.s */, Mips::FSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7823 | | { 8841 /* sub.s */, Mips::FSUB_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7824 | | { 8841 /* sub.s */, Mips::FSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
7825 | | { 8847 /* subq.ph */, Mips::SUBQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7826 | | { 8847 /* subq.ph */, Mips::SUBQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7827 | | { 8855 /* subq_s.ph */, Mips::SUBQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7828 | | { 8855 /* subq_s.ph */, Mips::SUBQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7829 | | { 8865 /* subq_s.w */, Mips::SUBQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7830 | | { 8865 /* subq_s.w */, Mips::SUBQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7831 | | { 8874 /* subqh.ph */, Mips::SUBQH_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7832 | | { 8874 /* subqh.ph */, Mips::SUBQH_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7833 | | { 8883 /* subqh.w */, Mips::SUBQH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7834 | | { 8883 /* subqh.w */, Mips::SUBQH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7835 | | { 8891 /* subqh_r.ph */, Mips::SUBQH_R_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7836 | | { 8891 /* subqh_r.ph */, Mips::SUBQH_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7837 | | { 8902 /* subqh_r.w */, Mips::SUBQH_R_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7838 | | { 8902 /* subqh_r.w */, Mips::SUBQH_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7839 | | { 8912 /* subs_s.b */, Mips::SUBS_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7840 | | { 8921 /* subs_s.d */, Mips::SUBS_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7841 | | { 8930 /* subs_s.h */, Mips::SUBS_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7842 | | { 8939 /* subs_s.w */, Mips::SUBS_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7843 | | { 8948 /* subs_u.b */, Mips::SUBS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7844 | | { 8957 /* subs_u.d */, Mips::SUBS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7845 | | { 8966 /* subs_u.h */, Mips::SUBS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7846 | | { 8975 /* subs_u.w */, Mips::SUBS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7847 | | { 8984 /* subsus_u.b */, Mips::SUBSUS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7848 | | { 8995 /* subsus_u.d */, Mips::SUBSUS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7849 | | { 9006 /* subsus_u.h */, Mips::SUBSUS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7850 | | { 9017 /* subsus_u.w */, Mips::SUBSUS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7851 | | { 9028 /* subsuu_s.b */, Mips::SUBSUU_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7852 | | { 9039 /* subsuu_s.d */, Mips::SUBSUU_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7853 | | { 9050 /* subsuu_s.h */, Mips::SUBSUU_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7854 | | { 9061 /* subsuu_s.w */, Mips::SUBSUU_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7855 | | { 9072 /* subu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7856 | | { 9072 /* subu */, Mips::SUBu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7857 | | { 9072 /* subu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7858 | | { 9072 /* subu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_InvNum }, }, |
7859 | | { 9072 /* subu */, Mips::SubuRxRyRz16, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_CPU16Regs }, }, |
7860 | | { 9072 /* subu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7861 | | { 9072 /* subu */, Mips::SUBu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7862 | | { 9072 /* subu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7863 | | { 9072 /* subu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_InvNum }, }, |
7864 | | { 9077 /* subu.ph */, Mips::SUBU_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7865 | | { 9077 /* subu.ph */, Mips::SUBU_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7866 | | { 9085 /* subu.qb */, Mips::SUBU_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7867 | | { 9085 /* subu.qb */, Mips::SUBU_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7868 | | { 9093 /* subu16 */, Mips::SUBU16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, |
7869 | | { 9093 /* subu16 */, Mips::SUBU16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, |
7870 | | { 9100 /* subu_s.ph */, Mips::SUBU_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7871 | | { 9100 /* subu_s.ph */, Mips::SUBU_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7872 | | { 9110 /* subu_s.qb */, Mips::SUBU_S_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7873 | | { 9110 /* subu_s.qb */, Mips::SUBU_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7874 | | { 9120 /* subuh.qb */, Mips::SUBUH_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7875 | | { 9120 /* subuh.qb */, Mips::SUBUH_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7876 | | { 9129 /* subuh_r.qb */, Mips::SUBUH_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7877 | | { 9129 /* subuh_r.qb */, Mips::SUBUH_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7878 | | { 9140 /* subv.b */, Mips::SUBV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7879 | | { 9147 /* subv.d */, Mips::SUBV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7880 | | { 9154 /* subv.h */, Mips::SUBV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7881 | | { 9161 /* subv.w */, Mips::SUBV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
7882 | | { 9168 /* subvi.b */, Mips::SUBVI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
7883 | | { 9176 /* subvi.d */, Mips::SUBVI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
7884 | | { 9184 /* subvi.h */, Mips::SUBVI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
7885 | | { 9192 /* subvi.w */, Mips::SUBVI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
7886 | | { 9200 /* suxc1 */, Mips::SUXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
7887 | | { 9200 /* suxc1 */, Mips::SUXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
7888 | | { 9200 /* suxc1 */, Mips::SUXC1_MM, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
7889 | | { 9206 /* sw */, Mips::SWSP_MMR6, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, }, |
7890 | | { 9206 /* sw */, Mips::SWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, }, |
7891 | | { 9206 /* sw */, Mips::SW, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
7892 | | { 9206 /* sw */, Mips::SWDSP, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_NotInMips16Mode_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, }, |
7893 | | { 9206 /* sw */, Mips::SWDSP_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, }, |
7894 | | { 9206 /* sw */, Mips::SW_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, |
7895 | | { 9206 /* sw */, Mips::SW_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
7896 | | { 9206 /* sw */, Mips::SwRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, }, |
7897 | | { 9206 /* sw */, Mips::SwRxSpImmX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, }, |
7898 | | { 9209 /* sw16 */, Mips::SW16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, }, |
7899 | | { 9209 /* sw16 */, Mips::SW16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, }, |
7900 | | { 9214 /* swc1 */, Mips::SWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, }, |
7901 | | { 9214 /* swc1 */, Mips::SWC1_MM, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, }, |
7902 | | { 9219 /* swc2 */, Mips::SWC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, }, |
7903 | | { 9219 /* swc2 */, Mips::SWC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, }, |
7904 | | { 9219 /* swc2 */, Mips::SWC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, }, |
7905 | | { 9224 /* swc3 */, Mips::SWC3, Convert__COP3AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, }, |
7906 | | { 9229 /* swe */, Mips::SWE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
7907 | | { 9229 /* swe */, Mips::SWE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
7908 | | { 9233 /* swl */, Mips::SWL, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
7909 | | { 9233 /* swl */, Mips::SWL_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, |
7910 | | { 9237 /* swle */, Mips::SWLE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
7911 | | { 9237 /* swle */, Mips::SWLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
7912 | | { 9242 /* swm */, Mips::SWM_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, }, |
7913 | | { 9246 /* swm16 */, Mips::SWM16_MM, Convert__RegList161_0__MemOffsetUimm42_1, AMFBS_InMicroMips_NotMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, }, |
7914 | | { 9246 /* swm16 */, Mips::SWM16_MMR6, Convert__RegList161_0__MemOffsetUimm42_1, AMFBS_InMicroMips_HasMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, }, |
7915 | | { 9252 /* swm32 */, Mips::SWM32_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, }, |
7916 | | { 9258 /* swp */, Mips::SWP_MM, ConvertCustom_ConvertXWPOperands, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12 }, }, |
7917 | | { 9262 /* swr */, Mips::SWR, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
7918 | | { 9262 /* swr */, Mips::SWR_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, |
7919 | | { 9266 /* swre */, Mips::SWRE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
7920 | | { 9266 /* swre */, Mips::SWRE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, |
7921 | | { 9271 /* swsp */, Mips::SWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, }, |
7922 | | { 9276 /* swxc1 */, Mips::SWXC1, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
7923 | | { 9276 /* swxc1 */, Mips::SWXC1_MM, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
7924 | | { 9282 /* sync */, Mips::SYNC, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { }, }, |
7925 | | { 9282 /* sync */, Mips::SYNC_MMR6, Convert__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { }, }, |
7926 | | { 9282 /* sync */, Mips::SYNC_MM, Convert__imm_95_0, AMFBS_InMicroMips, { }, }, |
7927 | | { 9282 /* sync */, Mips::SYNC, Convert__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_ConstantUImm5_0 }, }, |
7928 | | { 9282 /* sync */, Mips::SYNC_MMR6, Convert__ConstantUImm5_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm5_0 }, }, |
7929 | | { 9282 /* sync */, Mips::SYNC_MM, Convert__ConstantUImm5_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm5_0 }, }, |
7930 | | { 9287 /* synci */, Mips::SYNCI, Convert__MemOffsetSimm162_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_MemOffsetSimm16 }, }, |
7931 | | { 9287 /* synci */, Mips::SYNCI_MM, Convert__MemOffsetSimm162_0, AMFBS_InMicroMips_NotMips32r6, { MCK_MemOffsetSimm16 }, }, |
7932 | | { 9287 /* synci */, Mips::SYNCI_MMR6, Convert__MemOffsetSimm162_0, AMFBS_InMicroMips_HasMips32r6, { MCK_MemOffsetSimm16 }, }, |
7933 | | { 9293 /* synciobdma */, Mips::SYNC, Convert__imm_95_2, AMFBS_HasMips64_HasCnMips, { }, }, |
7934 | | { 9304 /* syncs */, Mips::SYNC, Convert__imm_95_6, AMFBS_HasMips64_HasCnMips, { }, }, |
7935 | | { 9310 /* syncw */, Mips::SYNC, Convert__imm_95_4, AMFBS_HasMips64_HasCnMips, { }, }, |
7936 | | { 9316 /* syncws */, Mips::SYNC, Convert__imm_95_5, AMFBS_HasMips64_HasCnMips, { }, }, |
7937 | | { 9323 /* syscall */, Mips::SYSCALL, Convert__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { }, }, |
7938 | | { 9323 /* syscall */, Mips::SYSCALL_MM, Convert__imm_95_0, AMFBS_InMicroMips, { }, }, |
7939 | | { 9323 /* syscall */, Mips::SYSCALL_MM, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, }, |
7940 | | { 9323 /* syscall */, Mips::SYSCALL, Convert__ConstantUImm20_01_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_ConstantUImm20_0 }, }, |
7941 | | { 9331 /* teq */, Mips::TEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7942 | | { 9331 /* teq */, Mips::TEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7943 | | { 9331 /* teq */, Mips::TEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
7944 | | { 9331 /* teq */, Mips::TEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, |
7945 | | { 9335 /* teqi */, Mips::TEQI, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
7946 | | { 9335 /* teqi */, Mips::TEQI_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
7947 | | { 9340 /* tge */, Mips::TGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7948 | | { 9340 /* tge */, Mips::TGE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7949 | | { 9340 /* tge */, Mips::TGE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
7950 | | { 9340 /* tge */, Mips::TGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, |
7951 | | { 9344 /* tgei */, Mips::TGEI, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
7952 | | { 9344 /* tgei */, Mips::TGEI_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
7953 | | { 9349 /* tgeiu */, Mips::TGEIU, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
7954 | | { 9349 /* tgeiu */, Mips::TGEIU_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
7955 | | { 9355 /* tgeu */, Mips::TGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7956 | | { 9355 /* tgeu */, Mips::TGEU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7957 | | { 9355 /* tgeu */, Mips::TGEU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
7958 | | { 9355 /* tgeu */, Mips::TGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, |
7959 | | { 9360 /* tlbginv */, Mips::TLBGINV, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, }, |
7960 | | { 9360 /* tlbginv */, Mips::TLBGINV_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, }, |
7961 | | { 9368 /* tlbginvf */, Mips::TLBGINVF, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, }, |
7962 | | { 9368 /* tlbginvf */, Mips::TLBGINVF_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, }, |
7963 | | { 9377 /* tlbgp */, Mips::TLBGP, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, }, |
7964 | | { 9377 /* tlbgp */, Mips::TLBGP_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, }, |
7965 | | { 9383 /* tlbgr */, Mips::TLBGR, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, }, |
7966 | | { 9383 /* tlbgr */, Mips::TLBGR_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, }, |
7967 | | { 9389 /* tlbgwi */, Mips::TLBGWI, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, }, |
7968 | | { 9389 /* tlbgwi */, Mips::TLBGWI_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, }, |
7969 | | { 9396 /* tlbgwr */, Mips::TLBGWR, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, }, |
7970 | | { 9396 /* tlbgwr */, Mips::TLBGWR_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, }, |
7971 | | { 9403 /* tlbinv */, Mips::TLBINV, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { }, }, |
7972 | | { 9403 /* tlbinv */, Mips::TLBINV_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, }, |
7973 | | { 9410 /* tlbinvf */, Mips::TLBINVF, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { }, }, |
7974 | | { 9410 /* tlbinvf */, Mips::TLBINVF_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, }, |
7975 | | { 9418 /* tlbp */, Mips::TLBP, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, }, |
7976 | | { 9418 /* tlbp */, Mips::TLBP_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, }, |
7977 | | { 9423 /* tlbr */, Mips::TLBR, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, }, |
7978 | | { 9423 /* tlbr */, Mips::TLBR_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, }, |
7979 | | { 9428 /* tlbwi */, Mips::TLBWI, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, }, |
7980 | | { 9428 /* tlbwi */, Mips::TLBWI_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, }, |
7981 | | { 9434 /* tlbwr */, Mips::TLBWR, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, }, |
7982 | | { 9434 /* tlbwr */, Mips::TLBWR_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, }, |
7983 | | { 9440 /* tlt */, Mips::TLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7984 | | { 9440 /* tlt */, Mips::TLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7985 | | { 9440 /* tlt */, Mips::TLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
7986 | | { 9440 /* tlt */, Mips::TLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, |
7987 | | { 9444 /* tlti */, Mips::TLTI, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
7988 | | { 9444 /* tlti */, Mips::TLTI_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
7989 | | { 9449 /* tltiu */, Mips::TTLTIU, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
7990 | | { 9449 /* tltiu */, Mips::TLTIU_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
7991 | | { 9455 /* tltu */, Mips::TLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7992 | | { 9455 /* tltu */, Mips::TLTU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7993 | | { 9455 /* tltu */, Mips::TLTU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
7994 | | { 9455 /* tltu */, Mips::TLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, |
7995 | | { 9460 /* tne */, Mips::TNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7996 | | { 9460 /* tne */, Mips::TNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
7997 | | { 9460 /* tne */, Mips::TNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
7998 | | { 9460 /* tne */, Mips::TNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, |
7999 | | { 9464 /* tnei */, Mips::TNEI, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
8000 | | { 9464 /* tnei */, Mips::TNEI_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
8001 | | { 9469 /* trunc.l.d */, Mips::TRUNC_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
8002 | | { 9469 /* trunc.l.d */, Mips::TRUNC_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
8003 | | { 9479 /* trunc.l.s */, Mips::TRUNC_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
8004 | | { 9479 /* trunc.l.s */, Mips::TRUNC_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
8005 | | { 9489 /* trunc.w.d */, Mips::TRUNC_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
8006 | | { 9489 /* trunc.w.d */, Mips::TRUNC_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
8007 | | { 9489 /* trunc.w.d */, Mips::TRUNC_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, |
8008 | | { 9489 /* trunc.w.d */, Mips::TRUNC_W_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, |
8009 | | { 9489 /* trunc.w.d */, Mips::PseudoTRUNC_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, }, |
8010 | | { 9489 /* trunc.w.d */, Mips::PseudoTRUNC_W_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_IsFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, }, |
8011 | | { 9499 /* trunc.w.s */, Mips::TRUNC_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
8012 | | { 9499 /* trunc.w.s */, Mips::TRUNC_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
8013 | | { 9499 /* trunc.w.s */, Mips::TRUNC_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
8014 | | { 9499 /* trunc.w.s */, Mips::PseudoTRUNC_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_None, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, }, |
8015 | | { 9509 /* ulh */, Mips::Ulh, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, }, |
8016 | | { 9513 /* ulhu */, Mips::Ulhu, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, }, |
8017 | | { 9518 /* ulw */, Mips::Ulw, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, }, |
8018 | | { 9522 /* ush */, Mips::Ush, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, }, |
8019 | | { 9526 /* usw */, Mips::Usw, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, }, |
8020 | | { 9530 /* v3mulu */, Mips::V3MULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
8021 | | { 9530 /* v3mulu */, Mips::V3MULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
8022 | | { 9537 /* vmm0 */, Mips::VMM0, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
8023 | | { 9537 /* vmm0 */, Mips::VMM0, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
8024 | | { 9542 /* vmulu */, Mips::VMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
8025 | | { 9542 /* vmulu */, Mips::VMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
8026 | | { 9548 /* vshf.b */, Mips::VSHF_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
8027 | | { 9555 /* vshf.d */, Mips::VSHF_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
8028 | | { 9562 /* vshf.h */, Mips::VSHF_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
8029 | | { 9569 /* vshf.w */, Mips::VSHF_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
8030 | | { 9576 /* wait */, Mips::WAIT, Convert_NoOperands, AMFBS_HasStdEnc_HasMips3_32_NotInMicroMips, { }, }, |
8031 | | { 9576 /* wait */, Mips::WAIT_MM, Convert__imm_95_0, AMFBS_InMicroMips, { }, }, |
8032 | | { 9576 /* wait */, Mips::WAIT_MMR6, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm10_0 }, }, |
8033 | | { 9576 /* wait */, Mips::WAIT_MM, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, }, |
8034 | | { 9581 /* wrdsp */, Mips::WRDSP, Convert__GPR32AsmReg1_0__imm_95_31, AMFBS_HasDSP_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
8035 | | { 9581 /* wrdsp */, Mips::WRDSP_MM, Convert__GPR32AsmReg1_0__imm_95_31, AMFBS_HasDSP_InMicroMips, { MCK_GPR32AsmReg }, }, |
8036 | | { 9581 /* wrdsp */, Mips::WRDSP_MM, Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm7_0 }, }, |
8037 | | { 9581 /* wrdsp */, Mips::WRDSP, Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, AMFBS_HasDSP_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, |
8038 | | { 9587 /* wrpgpr */, Mips::WRPGPR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
8039 | | { 9594 /* wsbh */, Mips::WSBH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
8040 | | { 9594 /* wsbh */, Mips::WSBH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
8041 | | { 9594 /* wsbh */, Mips::WSBH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
8042 | | { 9599 /* xor */, Mips::XorRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, |
8043 | | { 9599 /* xor */, Mips::XOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
8044 | | { 9599 /* xor */, Mips::XOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
8045 | | { 9599 /* xor */, Mips::XOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
8046 | | { 9599 /* xor */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, |
8047 | | { 9599 /* xor */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
8048 | | { 9599 /* xor */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
8049 | | { 9599 /* xor */, Mips::XORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, }, |
8050 | | { 9599 /* xor */, Mips::XOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
8051 | | { 9599 /* xor */, Mips::XOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
8052 | | { 9599 /* xor */, Mips::XOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
8053 | | { 9599 /* xor */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
8054 | | { 9599 /* xor */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
8055 | | { 9599 /* xor */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
8056 | | { 9599 /* xor */, Mips::XORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, |
8057 | | { 9603 /* xor.v */, Mips::XOR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
8058 | | { 9609 /* xor16 */, Mips::XOR16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, |
8059 | | { 9609 /* xor16 */, Mips::XOR16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, |
8060 | | { 9615 /* xori */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, |
8061 | | { 9615 /* xori */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, }, |
8062 | | { 9615 /* xori */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, |
8063 | | { 9615 /* xori */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
8064 | | { 9615 /* xori */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
8065 | | { 9615 /* xori */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
8066 | | { 9620 /* xori.b */, Mips::XORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, |
8067 | | { 9627 /* yield */, Mips::YIELD, Convert__regZERO__GPR32AsmReg1_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
8068 | | { 9627 /* yield */, Mips::YIELD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
8069 | | }; |
8070 | | |
8071 | | #include "llvm/Support/Debug.h" |
8072 | | #include "llvm/Support/Format.h" |
8073 | | |
8074 | | unsigned MipsAsmParser:: |
8075 | | MatchInstructionImpl(const OperandVector &Operands, |
8076 | | MCInst &Inst, |
8077 | | uint64_t &ErrorInfo, |
8078 | | FeatureBitset &MissingFeatures, |
8079 | 40.8k | bool matchingInlineAsm, unsigned VariantID) { |
8080 | 40.8k | // Eliminate obvious mismatches. |
8081 | 40.8k | if (Operands.size() > 9) { |
8082 | 0 | ErrorInfo = 9; |
8083 | 0 | return Match_InvalidOperand; |
8084 | 0 | } |
8085 | 40.8k | |
8086 | 40.8k | // Get the current feature set. |
8087 | 40.8k | const FeatureBitset &AvailableFeatures = getAvailableFeatures(); |
8088 | 40.8k | |
8089 | 40.8k | // Get the instruction mnemonic, which is the first token. |
8090 | 40.8k | StringRef Mnemonic = ((MipsOperand&)*Operands[0]).getToken(); |
8091 | 40.8k | |
8092 | 40.8k | // Some state to try to produce better error messages. |
8093 | 40.8k | bool HadMatchOtherThanFeatures = false; |
8094 | 40.8k | bool HadMatchOtherThanPredicate = false; |
8095 | 40.8k | unsigned RetCode = Match_InvalidOperand; |
8096 | 40.8k | MissingFeatures.set(); |
8097 | 40.8k | // Set ErrorInfo to the operand that mismatches if it is |
8098 | 40.8k | // wrong for all instances of the instruction. |
8099 | 40.8k | ErrorInfo = ~0ULL; |
8100 | 40.8k | // Find the appropriate table for this asm variant. |
8101 | 40.8k | const MatchEntry *Start, *End; |
8102 | 40.8k | switch (VariantID) { |
8103 | 40.8k | default: 0 llvm_unreachable0 ("invalid variant!"); |
8104 | 40.8k | case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; |
8105 | 40.8k | } |
8106 | 40.8k | // Search the table. |
8107 | 40.8k | auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode()); |
8108 | 40.8k | |
8109 | 40.8k | DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " << |
8110 | 40.8k | std::distance(MnemonicRange.first, MnemonicRange.second) << |
8111 | 40.8k | " encodings with mnemonic '" << Mnemonic << "'\n"); |
8112 | 40.8k | |
8113 | 40.8k | // Return a more specific error code if no mnemonics match. |
8114 | 40.8k | if (MnemonicRange.first == MnemonicRange.second) |
8115 | 0 | return Match_MnemonicFail; |
8116 | 40.8k | |
8117 | 40.8k | for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second; |
8118 | 99.9k | it != ie; ++it59.0k ) { |
8119 | 95.0k | const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx]; |
8120 | 95.0k | bool HasRequiredFeatures = |
8121 | 95.0k | (AvailableFeatures & RequiredFeatures) == RequiredFeatures; |
8122 | 95.0k | DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode " |
8123 | 95.0k | << MII.getName(it->Opcode) << "\n"); |
8124 | 95.0k | // equal_range guarantees that instruction mnemonic matches. |
8125 | 95.0k | assert(Mnemonic == it->getMnemonic()); |
8126 | 95.0k | bool OperandsValid = true; |
8127 | 212k | for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 8; ++FormalIdx117k ) { |
8128 | 212k | auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]); |
8129 | 212k | DEBUG_WITH_TYPE("asm-matcher", |
8130 | 212k | dbgs() << " Matching formal operand class " << getMatchClassName(Formal) |
8131 | 212k | << " against actual operand at index " << ActualIdx); |
8132 | 212k | if (ActualIdx < Operands.size()) |
8133 | 212k | DEBUG_WITH_TYPE164k ("asm-matcher", dbgs() << " ("; |
8134 | 212k | Operands[ActualIdx]->print(dbgs()); dbgs() << "): "); |
8135 | 212k | else |
8136 | 212k | DEBUG_WITH_TYPE48.0k ("asm-matcher", dbgs() << ": "); |
8137 | 212k | if (ActualIdx >= Operands.size()) { |
8138 | 48.0k | DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range "); |
8139 | 48.0k | OperandsValid = (Formal == InvalidMatchClass) || isSubclass(Formal, OptionalMatchClass)416 ; |
8140 | 48.0k | if (!OperandsValid) ErrorInfo = ActualIdx416 ; |
8141 | 48.0k | break; |
8142 | 48.0k | } |
8143 | 164k | MCParsedAsmOperand &Actual = *Operands[ActualIdx]; |
8144 | 164k | unsigned Diag = validateOperandClass(Actual, Formal); |
8145 | 164k | if (Diag == Match_Success) { |
8146 | 117k | DEBUG_WITH_TYPE("asm-matcher", |
8147 | 117k | dbgs() << "match success using generic matcher\n"); |
8148 | 117k | ++ActualIdx; |
8149 | 117k | continue; |
8150 | 117k | } |
8151 | 47.0k | // If the generic handler indicates an invalid operand |
8152 | 47.0k | // failure, check for a special case. |
8153 | 47.0k | if (Diag != Match_Success) { |
8154 | 47.0k | unsigned TargetDiag = validateTargetOperandClass(Actual, Formal); |
8155 | 47.0k | if (TargetDiag == Match_Success) { |
8156 | 0 | DEBUG_WITH_TYPE("asm-matcher", |
8157 | 0 | dbgs() << "match success using target matcher\n"); |
8158 | 0 | ++ActualIdx; |
8159 | 0 | continue; |
8160 | 0 | } |
8161 | 47.0k | // If the target matcher returned a specific error code use |
8162 | 47.0k | // that, else use the one from the generic matcher. |
8163 | 47.0k | if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures0 ) |
8164 | 0 | Diag = TargetDiag; |
8165 | 47.0k | } |
8166 | 47.0k | // If current formal operand wasn't matched and it is optional |
8167 | 47.0k | // then try to match next formal operand |
8168 | 47.0k | if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)38.3k ) { |
8169 | 0 | DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n"); |
8170 | 0 | continue; |
8171 | 0 | } |
8172 | 47.0k | // If this operand is broken for all of the instances of this |
8173 | 47.0k | // mnemonic, keep track of it so we can report loc info. |
8174 | 47.0k | // If we already had a match that only failed due to a |
8175 | 47.0k | // target predicate, that diagnostic is preferred. |
8176 | 47.0k | if (!HadMatchOtherThanPredicate && |
8177 | 47.0k | (46.9k it == MnemonicRange.first46.9k || ErrorInfo <= ActualIdx27.8k )) { |
8178 | 41.9k | if (HasRequiredFeatures && (8.54k ErrorInfo != ActualIdx8.54k || Diag != Match_InvalidOperand3.24k )) |
8179 | 6.60k | RetCode = Diag; |
8180 | 41.9k | ErrorInfo = ActualIdx; |
8181 | 41.9k | } |
8182 | 47.0k | // Otherwise, just reject this instance of the mnemonic. |
8183 | 47.0k | OperandsValid = false; |
8184 | 47.0k | break; |
8185 | 47.0k | } |
8186 | 95.0k | |
8187 | 95.0k | if (!OperandsValid) { |
8188 | 47.4k | DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple " |
8189 | 47.4k | "operand mismatches, ignoring " |
8190 | 47.4k | "this opcode\n"); |
8191 | 47.4k | continue; |
8192 | 47.4k | } |
8193 | 47.6k | if (!HasRequiredFeatures) { |
8194 | 11.2k | HadMatchOtherThanFeatures = true; |
8195 | 11.2k | FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures; |
8196 | 11.2k | DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:"; |
8197 | 11.2k | for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I) |
8198 | 11.2k | if (NewMissingFeatures[I]) |
8199 | 11.2k | dbgs() << ' ' << I; |
8200 | 11.2k | dbgs() << "\n"); |
8201 | 11.2k | if (NewMissingFeatures.count() <= |
8202 | 11.2k | MissingFeatures.count()) |
8203 | 9.34k | MissingFeatures = NewMissingFeatures; |
8204 | 11.2k | continue; |
8205 | 11.2k | } |
8206 | 36.3k | |
8207 | 36.3k | Inst.clear(); |
8208 | 36.3k | |
8209 | 36.3k | Inst.setOpcode(it->Opcode); |
8210 | 36.3k | // We have a potential match but have not rendered the operands. |
8211 | 36.3k | // Check the target predicate to handle any context sensitive |
8212 | 36.3k | // constraints. |
8213 | 36.3k | // For example, Ties that are referenced multiple times must be |
8214 | 36.3k | // checked here to ensure the input is the same for each match |
8215 | 36.3k | // constraints. If we leave it any later the ties will have been |
8216 | 36.3k | // canonicalized |
8217 | 36.3k | unsigned MatchResult; |
8218 | 36.3k | if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) { |
8219 | 4 | Inst.clear(); |
8220 | 4 | DEBUG_WITH_TYPE( |
8221 | 4 | "asm-matcher", |
8222 | 4 | dbgs() << "Early target match predicate failed with diag code " |
8223 | 4 | << MatchResult << "\n"); |
8224 | 4 | RetCode = MatchResult; |
8225 | 4 | HadMatchOtherThanPredicate = true; |
8226 | 4 | continue; |
8227 | 4 | } |
8228 | 36.3k | |
8229 | 36.3k | if (matchingInlineAsm) { |
8230 | 0 | convertToMapAndConstraints(it->ConvertFn, Operands); |
8231 | 0 | if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo)) |
8232 | 0 | return Match_InvalidTiedOperand; |
8233 | 0 | |
8234 | 0 | return Match_Success; |
8235 | 0 | } |
8236 | 36.3k | |
8237 | 36.3k | // We have selected a definite instruction, convert the parsed |
8238 | 36.3k | // operands into the appropriate MCInst. |
8239 | 36.3k | convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands); |
8240 | 36.3k | |
8241 | 36.3k | // We have a potential match. Check the target predicate to |
8242 | 36.3k | // handle any context sensitive constraints. |
8243 | 36.3k | if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) { |
8244 | 387 | DEBUG_WITH_TYPE("asm-matcher", |
8245 | 387 | dbgs() << "Target match predicate failed with diag code " |
8246 | 387 | << MatchResult << "\n"); |
8247 | 387 | Inst.clear(); |
8248 | 387 | RetCode = MatchResult; |
8249 | 387 | HadMatchOtherThanPredicate = true; |
8250 | 387 | continue; |
8251 | 387 | } |
8252 | 35.9k | |
8253 | 35.9k | if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo)) |
8254 | 0 | return Match_InvalidTiedOperand; |
8255 | 35.9k | |
8256 | 35.9k | DEBUG_WITH_TYPE( |
8257 | 35.9k | "asm-matcher", |
8258 | 35.9k | dbgs() << "Opcode result: complete match, selecting this opcode\n"); |
8259 | 35.9k | return Match_Success; |
8260 | 35.9k | } |
8261 | 40.8k | |
8262 | 40.8k | // Okay, we had no match. Try to return a useful error code. |
8263 | 40.8k | if (4.90k HadMatchOtherThanPredicate4.90k || !HadMatchOtherThanFeatures4.54k ) |
8264 | 2.61k | return RetCode; |
8265 | 2.28k | |
8266 | 2.28k | ErrorInfo = 0; |
8267 | 2.28k | return Match_MissingFeature; |
8268 | 2.28k | } |
8269 | | |
8270 | | namespace { |
8271 | | struct OperandMatchEntry { |
8272 | | uint16_t Mnemonic; |
8273 | | uint8_t OperandMask; |
8274 | | uint8_t Class; |
8275 | | uint8_t RequiredFeaturesIdx; |
8276 | | |
8277 | 1.36M | StringRef getMnemonic() const { |
8278 | 1.36M | return StringRef(MnemonicTable + Mnemonic + 1, |
8279 | 1.36M | MnemonicTable[Mnemonic]); |
8280 | 1.36M | } |
8281 | | }; |
8282 | | |
8283 | | // Predicate for searching for an opcode. |
8284 | | struct LessOpcodeOperand { |
8285 | 790k | bool operator()(const OperandMatchEntry &LHS, StringRef RHS) { |
8286 | 790k | return LHS.getMnemonic() < RHS; |
8287 | 790k | } |
8288 | 574k | bool operator()(StringRef LHS, const OperandMatchEntry &RHS) { |
8289 | 574k | return LHS < RHS.getMnemonic(); |
8290 | 574k | } |
8291 | 0 | bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) { |
8292 | 0 | return LHS.getMnemonic() < RHS.getMnemonic(); |
8293 | 0 | } |
8294 | | }; |
8295 | | } // end anonymous namespace. |
8296 | | |
8297 | | static const OperandMatchEntry OperandMatchTable[3278] = { |
8298 | | /* Operand List Mnemonic, Mask, Operand Class, Features */ |
8299 | | { 0 /* abs */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
8300 | | { 4 /* abs.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
8301 | | { 4 /* abs.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
8302 | | { 4 /* abs.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
8303 | | { 4 /* abs.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
8304 | | { 10 /* abs.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
8305 | | { 10 /* abs.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
8306 | | { 16 /* absq_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
8307 | | { 16 /* absq_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
8308 | | { 26 /* absq_s.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
8309 | | { 26 /* absq_s.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
8310 | | { 36 /* absq_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
8311 | | { 36 /* absq_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
8312 | | { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
8313 | | { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8314 | | { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8315 | | { 45 /* add */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
8316 | | { 45 /* add */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
8317 | | { 45 /* add */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
8318 | | { 45 /* add */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8319 | | { 45 /* add */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8320 | | { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
8321 | | { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
8322 | | { 49 /* add.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
8323 | | { 49 /* add.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
8324 | | { 49 /* add.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
8325 | | { 49 /* add.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
8326 | | { 55 /* add.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
8327 | | { 55 /* add.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
8328 | | { 55 /* add.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
8329 | | { 61 /* add_a.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8330 | | { 69 /* add_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8331 | | { 77 /* add_a.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8332 | | { 85 /* add_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8333 | | { 93 /* addi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8334 | | { 93 /* addi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
8335 | | { 93 /* addi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8336 | | { 93 /* addi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
8337 | | { 98 /* addiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8338 | | { 98 /* addiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8339 | | { 98 /* addiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
8340 | | { 98 /* addiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8341 | | { 98 /* addiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8342 | | { 98 /* addiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
8343 | | { 104 /* addiupc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
8344 | | { 104 /* addiupc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8345 | | { 104 /* addiupc */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8346 | | { 112 /* addiur1sp */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips }, |
8347 | | { 122 /* addiur2 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips }, |
8348 | | { 130 /* addius5 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
8349 | | { 146 /* addq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
8350 | | { 146 /* addq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
8351 | | { 154 /* addq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
8352 | | { 154 /* addq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
8353 | | { 164 /* addq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
8354 | | { 164 /* addq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
8355 | | { 173 /* addqh.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
8356 | | { 173 /* addqh.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
8357 | | { 182 /* addqh.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
8358 | | { 182 /* addqh.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
8359 | | { 190 /* addqh_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
8360 | | { 190 /* addqh_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
8361 | | { 201 /* addqh_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
8362 | | { 201 /* addqh_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
8363 | | { 211 /* adds_a.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8364 | | { 220 /* adds_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8365 | | { 229 /* adds_a.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8366 | | { 238 /* adds_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8367 | | { 247 /* adds_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8368 | | { 256 /* adds_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8369 | | { 265 /* adds_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8370 | | { 274 /* adds_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8371 | | { 283 /* adds_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8372 | | { 292 /* adds_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8373 | | { 301 /* adds_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8374 | | { 310 /* adds_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8375 | | { 319 /* addsc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
8376 | | { 319 /* addsc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
8377 | | { 325 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8378 | | { 325 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
8379 | | { 325 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8380 | | { 325 /* addu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
8381 | | { 325 /* addu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
8382 | | { 325 /* addu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8383 | | { 325 /* addu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
8384 | | { 325 /* addu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8385 | | { 325 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
8386 | | { 325 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
8387 | | { 330 /* addu.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
8388 | | { 330 /* addu.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
8389 | | { 338 /* addu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
8390 | | { 338 /* addu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
8391 | | { 346 /* addu16 */, 7 /* 0, 1, 2 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8392 | | { 346 /* addu16 */, 7 /* 0, 1, 2 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8393 | | { 353 /* addu_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
8394 | | { 353 /* addu_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
8395 | | { 363 /* addu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
8396 | | { 363 /* addu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
8397 | | { 373 /* adduh.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
8398 | | { 373 /* adduh.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
8399 | | { 382 /* adduh_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
8400 | | { 382 /* adduh_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
8401 | | { 393 /* addv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8402 | | { 400 /* addv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8403 | | { 407 /* addv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8404 | | { 414 /* addv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8405 | | { 421 /* addvi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8406 | | { 429 /* addvi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8407 | | { 437 /* addvi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8408 | | { 445 /* addvi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8409 | | { 453 /* addwc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
8410 | | { 453 /* addwc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
8411 | | { 459 /* align */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
8412 | | { 459 /* align */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8413 | | { 465 /* aluipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
8414 | | { 465 /* aluipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8415 | | { 472 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
8416 | | { 472 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8417 | | { 472 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8418 | | { 472 /* and */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8419 | | { 472 /* and */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, |
8420 | | { 472 /* and */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
8421 | | { 472 /* and */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips }, |
8422 | | { 472 /* and */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
8423 | | { 472 /* and */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8424 | | { 472 /* and */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8425 | | { 472 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8426 | | { 472 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, |
8427 | | { 472 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
8428 | | { 472 /* and */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips }, |
8429 | | { 476 /* and.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8430 | | { 482 /* and16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8431 | | { 482 /* and16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8432 | | { 488 /* andi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8433 | | { 488 /* andi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
8434 | | { 488 /* andi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8435 | | { 488 /* andi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8436 | | { 488 /* andi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
8437 | | { 488 /* andi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8438 | | { 493 /* andi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8439 | | { 500 /* andi16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8440 | | { 500 /* andi16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8441 | | { 507 /* append */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
8442 | | { 507 /* append */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
8443 | | { 514 /* asub_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8444 | | { 523 /* asub_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8445 | | { 532 /* asub_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8446 | | { 541 /* asub_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8447 | | { 550 /* asub_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8448 | | { 559 /* asub_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8449 | | { 568 /* asub_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8450 | | { 577 /* asub_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8451 | | { 586 /* aui */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
8452 | | { 586 /* aui */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8453 | | { 590 /* auipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
8454 | | { 590 /* auipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8455 | | { 596 /* ave_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8456 | | { 604 /* ave_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8457 | | { 612 /* ave_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8458 | | { 620 /* ave_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8459 | | { 628 /* ave_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8460 | | { 636 /* ave_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8461 | | { 644 /* ave_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8462 | | { 652 /* ave_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8463 | | { 660 /* aver_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8464 | | { 669 /* aver_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8465 | | { 678 /* aver_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8466 | | { 687 /* aver_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8467 | | { 696 /* aver_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8468 | | { 705 /* aver_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8469 | | { 714 /* aver_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8470 | | { 723 /* aver_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8471 | | { 732 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, |
8472 | | { 732 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips }, |
8473 | | { 732 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMips16Mode }, |
8474 | | { 732 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_None }, |
8475 | | { 732 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMips16Mode }, |
8476 | | { 734 /* b16 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8477 | | { 734 /* b16 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips }, |
8478 | | { 738 /* baddu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
8479 | | { 738 /* baddu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
8480 | | { 744 /* bal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
8481 | | { 744 /* bal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 }, |
8482 | | { 744 /* bal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
8483 | | { 748 /* balc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 }, |
8484 | | { 748 /* balc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8485 | | { 753 /* balign */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
8486 | | { 753 /* balign */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
8487 | | { 760 /* bbit0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
8488 | | { 760 /* bbit0 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips }, |
8489 | | { 760 /* bbit0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
8490 | | { 760 /* bbit0 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips }, |
8491 | | { 766 /* bbit032 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
8492 | | { 766 /* bbit032 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips }, |
8493 | | { 774 /* bbit1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
8494 | | { 774 /* bbit1 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips }, |
8495 | | { 774 /* bbit1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
8496 | | { 774 /* bbit1 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips }, |
8497 | | { 780 /* bbit132 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
8498 | | { 780 /* bbit132 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips }, |
8499 | | { 788 /* bc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8500 | | { 788 /* bc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8501 | | { 791 /* bc16 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8502 | | { 796 /* bc1eqz */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
8503 | | { 796 /* bc1eqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
8504 | | { 803 /* bc1eqzc */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
8505 | | { 803 /* bc1eqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
8506 | | { 811 /* bc1f */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8507 | | { 811 /* bc1f */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
8508 | | { 811 /* bc1f */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8509 | | { 811 /* bc1f */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8510 | | { 811 /* bc1f */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
8511 | | { 811 /* bc1f */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
8512 | | { 816 /* bc1fl */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8513 | | { 816 /* bc1fl */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8514 | | { 816 /* bc1fl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8515 | | { 822 /* bc1nez */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
8516 | | { 822 /* bc1nez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
8517 | | { 829 /* bc1nezc */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
8518 | | { 829 /* bc1nezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
8519 | | { 837 /* bc1t */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8520 | | { 837 /* bc1t */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
8521 | | { 837 /* bc1t */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8522 | | { 837 /* bc1t */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8523 | | { 837 /* bc1t */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
8524 | | { 837 /* bc1t */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
8525 | | { 842 /* bc1tl */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8526 | | { 842 /* bc1tl */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8527 | | { 842 /* bc1tl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8528 | | { 848 /* bc2eqz */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8529 | | { 848 /* bc2eqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8530 | | { 855 /* bc2eqzc */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8531 | | { 855 /* bc2eqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8532 | | { 863 /* bc2nez */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8533 | | { 863 /* bc2nez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8534 | | { 870 /* bc2nezc */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8535 | | { 870 /* bc2nezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8536 | | { 878 /* bclr.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8537 | | { 885 /* bclr.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8538 | | { 892 /* bclr.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8539 | | { 899 /* bclr.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8540 | | { 906 /* bclri.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8541 | | { 914 /* bclri.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8542 | | { 922 /* bclri.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8543 | | { 930 /* bclri.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8544 | | { 938 /* beq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
8545 | | { 938 /* beq */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, |
8546 | | { 938 /* beq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8547 | | { 938 /* beq */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
8548 | | { 938 /* beq */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
8549 | | { 938 /* beq */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
8550 | | { 942 /* beqc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8551 | | { 942 /* beqc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8552 | | { 942 /* beqc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8553 | | { 942 /* beqc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8554 | | { 942 /* beqc */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
8555 | | { 942 /* beqc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
8556 | | { 947 /* beql */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
8557 | | { 947 /* beql */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
8558 | | { 947 /* beql */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8559 | | { 947 /* beql */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8560 | | { 952 /* beqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMips16Mode }, |
8561 | | { 952 /* beqz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
8562 | | { 952 /* beqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, |
8563 | | { 952 /* beqz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
8564 | | { 952 /* beqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips }, |
8565 | | { 952 /* beqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMips16Mode }, |
8566 | | { 957 /* beqz16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8567 | | { 957 /* beqz16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
8568 | | { 957 /* beqz16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8569 | | { 957 /* beqz16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8570 | | { 964 /* beqzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8571 | | { 964 /* beqzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8572 | | { 964 /* beqzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8573 | | { 964 /* beqzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8574 | | { 972 /* beqzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8575 | | { 972 /* beqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8576 | | { 972 /* beqzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8577 | | { 972 /* beqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
8578 | | { 972 /* beqzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8579 | | { 972 /* beqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8580 | | { 972 /* beqzc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
8581 | | { 972 /* beqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
8582 | | { 978 /* beqzc16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8583 | | { 978 /* beqzc16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8584 | | { 986 /* beqzl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
8585 | | { 986 /* beqzl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
8586 | | { 992 /* bge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
8587 | | { 992 /* bge */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
8588 | | { 992 /* bge */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
8589 | | { 992 /* bge */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
8590 | | { 996 /* bgec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8591 | | { 996 /* bgec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8592 | | { 996 /* bgec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8593 | | { 996 /* bgec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8594 | | { 996 /* bgec */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
8595 | | { 996 /* bgec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
8596 | | { 1001 /* bgel */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8597 | | { 1001 /* bgel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8598 | | { 1001 /* bgel */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8599 | | { 1001 /* bgel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8600 | | { 1006 /* bgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
8601 | | { 1006 /* bgeu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
8602 | | { 1006 /* bgeu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
8603 | | { 1006 /* bgeu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
8604 | | { 1011 /* bgeuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8605 | | { 1011 /* bgeuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8606 | | { 1011 /* bgeuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8607 | | { 1011 /* bgeuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8608 | | { 1011 /* bgeuc */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
8609 | | { 1011 /* bgeuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
8610 | | { 1017 /* bgeul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8611 | | { 1017 /* bgeul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8612 | | { 1017 /* bgeul */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8613 | | { 1017 /* bgeul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8614 | | { 1023 /* bgez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
8615 | | { 1023 /* bgez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, |
8616 | | { 1023 /* bgez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8617 | | { 1023 /* bgez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
8618 | | { 1028 /* bgezal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
8619 | | { 1028 /* bgezal */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
8620 | | { 1028 /* bgezal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8621 | | { 1028 /* bgezal */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
8622 | | { 1035 /* bgezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8623 | | { 1035 /* bgezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8624 | | { 1035 /* bgezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8625 | | { 1035 /* bgezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8626 | | { 1043 /* bgezall */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
8627 | | { 1043 /* bgezall */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
8628 | | { 1051 /* bgezals */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8629 | | { 1051 /* bgezals */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
8630 | | { 1059 /* bgezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8631 | | { 1059 /* bgezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8632 | | { 1059 /* bgezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8633 | | { 1059 /* bgezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8634 | | { 1059 /* bgezc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
8635 | | { 1059 /* bgezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
8636 | | { 1065 /* bgezl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
8637 | | { 1065 /* bgezl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
8638 | | { 1071 /* bgt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
8639 | | { 1071 /* bgt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
8640 | | { 1071 /* bgt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
8641 | | { 1071 /* bgt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
8642 | | { 1075 /* bgtl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8643 | | { 1075 /* bgtl */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8644 | | { 1075 /* bgtl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8645 | | { 1075 /* bgtl */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8646 | | { 1080 /* bgtu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
8647 | | { 1080 /* bgtu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
8648 | | { 1080 /* bgtu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
8649 | | { 1080 /* bgtu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
8650 | | { 1085 /* bgtul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8651 | | { 1085 /* bgtul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8652 | | { 1085 /* bgtul */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8653 | | { 1085 /* bgtul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8654 | | { 1091 /* bgtz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
8655 | | { 1091 /* bgtz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, |
8656 | | { 1091 /* bgtz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8657 | | { 1091 /* bgtz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
8658 | | { 1096 /* bgtzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8659 | | { 1096 /* bgtzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8660 | | { 1096 /* bgtzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8661 | | { 1096 /* bgtzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8662 | | { 1104 /* bgtzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8663 | | { 1104 /* bgtzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8664 | | { 1104 /* bgtzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8665 | | { 1104 /* bgtzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8666 | | { 1104 /* bgtzc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
8667 | | { 1104 /* bgtzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
8668 | | { 1110 /* bgtzl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
8669 | | { 1110 /* bgtzl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
8670 | | { 1116 /* binsl.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8671 | | { 1124 /* binsl.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8672 | | { 1132 /* binsl.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8673 | | { 1140 /* binsl.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8674 | | { 1148 /* binsli.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8675 | | { 1157 /* binsli.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8676 | | { 1166 /* binsli.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8677 | | { 1175 /* binsli.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8678 | | { 1184 /* binsr.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8679 | | { 1192 /* binsr.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8680 | | { 1200 /* binsr.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8681 | | { 1208 /* binsr.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8682 | | { 1216 /* binsri.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8683 | | { 1225 /* binsri.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8684 | | { 1234 /* binsri.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8685 | | { 1243 /* binsri.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8686 | | { 1252 /* bitrev */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
8687 | | { 1252 /* bitrev */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
8688 | | { 1259 /* bitswap */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
8689 | | { 1259 /* bitswap */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8690 | | { 1267 /* ble */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
8691 | | { 1267 /* ble */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
8692 | | { 1267 /* ble */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
8693 | | { 1267 /* ble */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
8694 | | { 1271 /* blel */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8695 | | { 1271 /* blel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8696 | | { 1271 /* blel */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8697 | | { 1271 /* blel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8698 | | { 1276 /* bleu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
8699 | | { 1276 /* bleu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
8700 | | { 1276 /* bleu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
8701 | | { 1276 /* bleu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
8702 | | { 1281 /* bleul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8703 | | { 1281 /* bleul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8704 | | { 1281 /* bleul */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8705 | | { 1281 /* bleul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8706 | | { 1287 /* blez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
8707 | | { 1287 /* blez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, |
8708 | | { 1287 /* blez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8709 | | { 1287 /* blez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
8710 | | { 1292 /* blezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8711 | | { 1292 /* blezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8712 | | { 1292 /* blezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8713 | | { 1292 /* blezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8714 | | { 1300 /* blezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8715 | | { 1300 /* blezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8716 | | { 1300 /* blezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8717 | | { 1300 /* blezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8718 | | { 1300 /* blezc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
8719 | | { 1300 /* blezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
8720 | | { 1306 /* blezl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
8721 | | { 1306 /* blezl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
8722 | | { 1312 /* blt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
8723 | | { 1312 /* blt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
8724 | | { 1312 /* blt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
8725 | | { 1312 /* blt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
8726 | | { 1316 /* bltc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8727 | | { 1316 /* bltc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8728 | | { 1316 /* bltc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8729 | | { 1316 /* bltc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8730 | | { 1316 /* bltc */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
8731 | | { 1316 /* bltc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
8732 | | { 1321 /* bltl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8733 | | { 1321 /* bltl */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8734 | | { 1321 /* bltl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8735 | | { 1321 /* bltl */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8736 | | { 1326 /* bltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
8737 | | { 1326 /* bltu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
8738 | | { 1326 /* bltu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
8739 | | { 1326 /* bltu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
8740 | | { 1331 /* bltuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8741 | | { 1331 /* bltuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8742 | | { 1331 /* bltuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8743 | | { 1331 /* bltuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8744 | | { 1331 /* bltuc */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
8745 | | { 1331 /* bltuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
8746 | | { 1337 /* bltul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8747 | | { 1337 /* bltul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8748 | | { 1337 /* bltul */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8749 | | { 1337 /* bltul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8750 | | { 1343 /* bltz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
8751 | | { 1343 /* bltz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, |
8752 | | { 1343 /* bltz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8753 | | { 1343 /* bltz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
8754 | | { 1348 /* bltzal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
8755 | | { 1348 /* bltzal */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
8756 | | { 1348 /* bltzal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8757 | | { 1348 /* bltzal */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
8758 | | { 1355 /* bltzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8759 | | { 1355 /* bltzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8760 | | { 1355 /* bltzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8761 | | { 1355 /* bltzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8762 | | { 1363 /* bltzall */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
8763 | | { 1363 /* bltzall */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
8764 | | { 1371 /* bltzals */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8765 | | { 1371 /* bltzals */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
8766 | | { 1379 /* bltzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8767 | | { 1379 /* bltzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8768 | | { 1379 /* bltzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8769 | | { 1379 /* bltzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8770 | | { 1379 /* bltzc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
8771 | | { 1379 /* bltzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
8772 | | { 1385 /* bltzl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
8773 | | { 1385 /* bltzl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
8774 | | { 1391 /* bmnz.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8775 | | { 1398 /* bmnzi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8776 | | { 1406 /* bmz.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8777 | | { 1412 /* bmzi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8778 | | { 1419 /* bne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
8779 | | { 1419 /* bne */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, |
8780 | | { 1419 /* bne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8781 | | { 1419 /* bne */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
8782 | | { 1419 /* bne */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
8783 | | { 1419 /* bne */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
8784 | | { 1423 /* bnec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8785 | | { 1423 /* bnec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8786 | | { 1423 /* bnec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8787 | | { 1423 /* bnec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8788 | | { 1423 /* bnec */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
8789 | | { 1423 /* bnec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
8790 | | { 1428 /* bneg.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8791 | | { 1435 /* bneg.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8792 | | { 1442 /* bneg.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8793 | | { 1449 /* bneg.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8794 | | { 1456 /* bnegi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8795 | | { 1464 /* bnegi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8796 | | { 1472 /* bnegi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8797 | | { 1480 /* bnegi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8798 | | { 1488 /* bnel */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
8799 | | { 1488 /* bnel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
8800 | | { 1488 /* bnel */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8801 | | { 1488 /* bnel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
8802 | | { 1493 /* bnez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMips16Mode }, |
8803 | | { 1493 /* bnez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
8804 | | { 1493 /* bnez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, |
8805 | | { 1493 /* bnez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
8806 | | { 1493 /* bnez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips }, |
8807 | | { 1493 /* bnez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMips16Mode }, |
8808 | | { 1498 /* bnez16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8809 | | { 1498 /* bnez16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
8810 | | { 1498 /* bnez16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8811 | | { 1498 /* bnez16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8812 | | { 1505 /* bnezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8813 | | { 1505 /* bnezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8814 | | { 1505 /* bnezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8815 | | { 1505 /* bnezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8816 | | { 1513 /* bnezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8817 | | { 1513 /* bnezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8818 | | { 1513 /* bnezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
8819 | | { 1513 /* bnezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
8820 | | { 1513 /* bnezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8821 | | { 1513 /* bnezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8822 | | { 1513 /* bnezc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
8823 | | { 1513 /* bnezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
8824 | | { 1519 /* bnezc16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8825 | | { 1519 /* bnezc16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8826 | | { 1527 /* bnezl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
8827 | | { 1527 /* bnezl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
8828 | | { 1533 /* bnvc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8829 | | { 1533 /* bnvc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8830 | | { 1533 /* bnvc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8831 | | { 1533 /* bnvc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8832 | | { 1538 /* bnz.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8833 | | { 1538 /* bnz.b */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, |
8834 | | { 1544 /* bnz.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8835 | | { 1544 /* bnz.d */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, |
8836 | | { 1550 /* bnz.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8837 | | { 1550 /* bnz.h */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, |
8838 | | { 1556 /* bnz.v */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8839 | | { 1556 /* bnz.v */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, |
8840 | | { 1562 /* bnz.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8841 | | { 1562 /* bnz.w */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, |
8842 | | { 1568 /* bovc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8843 | | { 1568 /* bovc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
8844 | | { 1568 /* bovc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
8845 | | { 1568 /* bovc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
8846 | | { 1573 /* bposge32 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_HasDSP }, |
8847 | | { 1573 /* bposge32 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasDSP_NotInMicroMips }, |
8848 | | { 1582 /* bposge32c */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasDSPR3 }, |
8849 | | { 1606 /* bsel.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8850 | | { 1613 /* bseli.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8851 | | { 1621 /* bset.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8852 | | { 1628 /* bset.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8853 | | { 1635 /* bset.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8854 | | { 1642 /* bset.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8855 | | { 1649 /* bseti.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8856 | | { 1657 /* bseti.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8857 | | { 1665 /* bseti.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8858 | | { 1673 /* bseti.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8859 | | { 1693 /* bz.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8860 | | { 1693 /* bz.b */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, |
8861 | | { 1698 /* bz.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8862 | | { 1698 /* bz.d */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, |
8863 | | { 1703 /* bz.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8864 | | { 1703 /* bz.h */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, |
8865 | | { 1708 /* bz.v */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8866 | | { 1708 /* bz.v */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, |
8867 | | { 1713 /* bz.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
8868 | | { 1713 /* bz.w */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, |
8869 | | { 1718 /* c.eq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8870 | | { 1718 /* c.eq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
8871 | | { 1718 /* c.eq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8872 | | { 1718 /* c.eq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
8873 | | { 1718 /* c.eq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8874 | | { 1718 /* c.eq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8875 | | { 1718 /* c.eq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
8876 | | { 1718 /* c.eq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
8877 | | { 1718 /* c.eq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8878 | | { 1718 /* c.eq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8879 | | { 1718 /* c.eq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
8880 | | { 1718 /* c.eq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
8881 | | { 1725 /* c.eq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8882 | | { 1725 /* c.eq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
8883 | | { 1725 /* c.eq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8884 | | { 1725 /* c.eq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8885 | | { 1725 /* c.eq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
8886 | | { 1725 /* c.eq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
8887 | | { 1732 /* c.f.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8888 | | { 1732 /* c.f.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
8889 | | { 1732 /* c.f.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8890 | | { 1732 /* c.f.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
8891 | | { 1732 /* c.f.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8892 | | { 1732 /* c.f.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8893 | | { 1732 /* c.f.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
8894 | | { 1732 /* c.f.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
8895 | | { 1732 /* c.f.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8896 | | { 1732 /* c.f.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8897 | | { 1732 /* c.f.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
8898 | | { 1732 /* c.f.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
8899 | | { 1738 /* c.f.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8900 | | { 1738 /* c.f.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
8901 | | { 1738 /* c.f.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8902 | | { 1738 /* c.f.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8903 | | { 1738 /* c.f.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
8904 | | { 1738 /* c.f.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
8905 | | { 1744 /* c.le.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8906 | | { 1744 /* c.le.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
8907 | | { 1744 /* c.le.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8908 | | { 1744 /* c.le.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
8909 | | { 1744 /* c.le.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8910 | | { 1744 /* c.le.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8911 | | { 1744 /* c.le.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
8912 | | { 1744 /* c.le.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
8913 | | { 1744 /* c.le.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8914 | | { 1744 /* c.le.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8915 | | { 1744 /* c.le.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
8916 | | { 1744 /* c.le.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
8917 | | { 1751 /* c.le.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8918 | | { 1751 /* c.le.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
8919 | | { 1751 /* c.le.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8920 | | { 1751 /* c.le.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8921 | | { 1751 /* c.le.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
8922 | | { 1751 /* c.le.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
8923 | | { 1758 /* c.lt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8924 | | { 1758 /* c.lt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
8925 | | { 1758 /* c.lt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8926 | | { 1758 /* c.lt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
8927 | | { 1758 /* c.lt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8928 | | { 1758 /* c.lt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8929 | | { 1758 /* c.lt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
8930 | | { 1758 /* c.lt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
8931 | | { 1758 /* c.lt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8932 | | { 1758 /* c.lt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8933 | | { 1758 /* c.lt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
8934 | | { 1758 /* c.lt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
8935 | | { 1765 /* c.lt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8936 | | { 1765 /* c.lt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
8937 | | { 1765 /* c.lt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8938 | | { 1765 /* c.lt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8939 | | { 1765 /* c.lt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
8940 | | { 1765 /* c.lt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
8941 | | { 1772 /* c.nge.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8942 | | { 1772 /* c.nge.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
8943 | | { 1772 /* c.nge.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8944 | | { 1772 /* c.nge.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
8945 | | { 1772 /* c.nge.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8946 | | { 1772 /* c.nge.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8947 | | { 1772 /* c.nge.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
8948 | | { 1772 /* c.nge.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
8949 | | { 1772 /* c.nge.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8950 | | { 1772 /* c.nge.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8951 | | { 1772 /* c.nge.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
8952 | | { 1772 /* c.nge.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
8953 | | { 1780 /* c.nge.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8954 | | { 1780 /* c.nge.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
8955 | | { 1780 /* c.nge.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8956 | | { 1780 /* c.nge.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8957 | | { 1780 /* c.nge.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
8958 | | { 1780 /* c.nge.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
8959 | | { 1788 /* c.ngl.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8960 | | { 1788 /* c.ngl.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
8961 | | { 1788 /* c.ngl.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8962 | | { 1788 /* c.ngl.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
8963 | | { 1788 /* c.ngl.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8964 | | { 1788 /* c.ngl.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8965 | | { 1788 /* c.ngl.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
8966 | | { 1788 /* c.ngl.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
8967 | | { 1788 /* c.ngl.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8968 | | { 1788 /* c.ngl.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8969 | | { 1788 /* c.ngl.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
8970 | | { 1788 /* c.ngl.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
8971 | | { 1796 /* c.ngl.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8972 | | { 1796 /* c.ngl.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
8973 | | { 1796 /* c.ngl.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8974 | | { 1796 /* c.ngl.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8975 | | { 1796 /* c.ngl.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
8976 | | { 1796 /* c.ngl.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
8977 | | { 1804 /* c.ngle.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8978 | | { 1804 /* c.ngle.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
8979 | | { 1804 /* c.ngle.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8980 | | { 1804 /* c.ngle.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
8981 | | { 1804 /* c.ngle.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8982 | | { 1804 /* c.ngle.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8983 | | { 1804 /* c.ngle.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
8984 | | { 1804 /* c.ngle.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
8985 | | { 1804 /* c.ngle.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8986 | | { 1804 /* c.ngle.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8987 | | { 1804 /* c.ngle.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
8988 | | { 1804 /* c.ngle.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
8989 | | { 1813 /* c.ngle.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8990 | | { 1813 /* c.ngle.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
8991 | | { 1813 /* c.ngle.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8992 | | { 1813 /* c.ngle.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8993 | | { 1813 /* c.ngle.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
8994 | | { 1813 /* c.ngle.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
8995 | | { 1822 /* c.ngt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8996 | | { 1822 /* c.ngt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
8997 | | { 1822 /* c.ngt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
8998 | | { 1822 /* c.ngt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
8999 | | { 1822 /* c.ngt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9000 | | { 1822 /* c.ngt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9001 | | { 1822 /* c.ngt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
9002 | | { 1822 /* c.ngt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
9003 | | { 1822 /* c.ngt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9004 | | { 1822 /* c.ngt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9005 | | { 1822 /* c.ngt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
9006 | | { 1822 /* c.ngt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
9007 | | { 1830 /* c.ngt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9008 | | { 1830 /* c.ngt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
9009 | | { 1830 /* c.ngt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9010 | | { 1830 /* c.ngt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9011 | | { 1830 /* c.ngt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
9012 | | { 1830 /* c.ngt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
9013 | | { 1838 /* c.ole.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9014 | | { 1838 /* c.ole.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
9015 | | { 1838 /* c.ole.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9016 | | { 1838 /* c.ole.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
9017 | | { 1838 /* c.ole.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9018 | | { 1838 /* c.ole.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9019 | | { 1838 /* c.ole.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
9020 | | { 1838 /* c.ole.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
9021 | | { 1838 /* c.ole.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9022 | | { 1838 /* c.ole.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9023 | | { 1838 /* c.ole.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
9024 | | { 1838 /* c.ole.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
9025 | | { 1846 /* c.ole.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9026 | | { 1846 /* c.ole.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
9027 | | { 1846 /* c.ole.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9028 | | { 1846 /* c.ole.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9029 | | { 1846 /* c.ole.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
9030 | | { 1846 /* c.ole.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
9031 | | { 1854 /* c.olt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9032 | | { 1854 /* c.olt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
9033 | | { 1854 /* c.olt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9034 | | { 1854 /* c.olt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
9035 | | { 1854 /* c.olt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9036 | | { 1854 /* c.olt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9037 | | { 1854 /* c.olt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
9038 | | { 1854 /* c.olt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
9039 | | { 1854 /* c.olt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9040 | | { 1854 /* c.olt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9041 | | { 1854 /* c.olt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
9042 | | { 1854 /* c.olt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
9043 | | { 1862 /* c.olt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9044 | | { 1862 /* c.olt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
9045 | | { 1862 /* c.olt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9046 | | { 1862 /* c.olt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9047 | | { 1862 /* c.olt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
9048 | | { 1862 /* c.olt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
9049 | | { 1870 /* c.seq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9050 | | { 1870 /* c.seq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
9051 | | { 1870 /* c.seq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9052 | | { 1870 /* c.seq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
9053 | | { 1870 /* c.seq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9054 | | { 1870 /* c.seq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9055 | | { 1870 /* c.seq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
9056 | | { 1870 /* c.seq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
9057 | | { 1870 /* c.seq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9058 | | { 1870 /* c.seq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9059 | | { 1870 /* c.seq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
9060 | | { 1870 /* c.seq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
9061 | | { 1878 /* c.seq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9062 | | { 1878 /* c.seq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
9063 | | { 1878 /* c.seq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9064 | | { 1878 /* c.seq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9065 | | { 1878 /* c.seq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
9066 | | { 1878 /* c.seq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
9067 | | { 1886 /* c.sf.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9068 | | { 1886 /* c.sf.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
9069 | | { 1886 /* c.sf.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9070 | | { 1886 /* c.sf.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
9071 | | { 1886 /* c.sf.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9072 | | { 1886 /* c.sf.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9073 | | { 1886 /* c.sf.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
9074 | | { 1886 /* c.sf.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
9075 | | { 1886 /* c.sf.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9076 | | { 1886 /* c.sf.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9077 | | { 1886 /* c.sf.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
9078 | | { 1886 /* c.sf.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
9079 | | { 1893 /* c.sf.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9080 | | { 1893 /* c.sf.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
9081 | | { 1893 /* c.sf.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9082 | | { 1893 /* c.sf.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9083 | | { 1893 /* c.sf.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
9084 | | { 1893 /* c.sf.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
9085 | | { 1900 /* c.ueq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9086 | | { 1900 /* c.ueq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
9087 | | { 1900 /* c.ueq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9088 | | { 1900 /* c.ueq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
9089 | | { 1900 /* c.ueq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9090 | | { 1900 /* c.ueq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9091 | | { 1900 /* c.ueq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
9092 | | { 1900 /* c.ueq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
9093 | | { 1900 /* c.ueq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9094 | | { 1900 /* c.ueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9095 | | { 1900 /* c.ueq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
9096 | | { 1900 /* c.ueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
9097 | | { 1908 /* c.ueq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9098 | | { 1908 /* c.ueq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
9099 | | { 1908 /* c.ueq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9100 | | { 1908 /* c.ueq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9101 | | { 1908 /* c.ueq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
9102 | | { 1908 /* c.ueq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
9103 | | { 1916 /* c.ule.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9104 | | { 1916 /* c.ule.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
9105 | | { 1916 /* c.ule.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9106 | | { 1916 /* c.ule.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
9107 | | { 1916 /* c.ule.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9108 | | { 1916 /* c.ule.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9109 | | { 1916 /* c.ule.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
9110 | | { 1916 /* c.ule.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
9111 | | { 1916 /* c.ule.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9112 | | { 1916 /* c.ule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9113 | | { 1916 /* c.ule.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
9114 | | { 1916 /* c.ule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
9115 | | { 1924 /* c.ule.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9116 | | { 1924 /* c.ule.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
9117 | | { 1924 /* c.ule.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9118 | | { 1924 /* c.ule.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9119 | | { 1924 /* c.ule.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
9120 | | { 1924 /* c.ule.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
9121 | | { 1932 /* c.ult.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9122 | | { 1932 /* c.ult.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
9123 | | { 1932 /* c.ult.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9124 | | { 1932 /* c.ult.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
9125 | | { 1932 /* c.ult.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9126 | | { 1932 /* c.ult.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9127 | | { 1932 /* c.ult.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
9128 | | { 1932 /* c.ult.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
9129 | | { 1932 /* c.ult.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9130 | | { 1932 /* c.ult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9131 | | { 1932 /* c.ult.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
9132 | | { 1932 /* c.ult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
9133 | | { 1940 /* c.ult.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9134 | | { 1940 /* c.ult.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
9135 | | { 1940 /* c.ult.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9136 | | { 1940 /* c.ult.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9137 | | { 1940 /* c.ult.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
9138 | | { 1940 /* c.ult.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
9139 | | { 1948 /* c.un.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9140 | | { 1948 /* c.un.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
9141 | | { 1948 /* c.un.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9142 | | { 1948 /* c.un.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
9143 | | { 1948 /* c.un.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9144 | | { 1948 /* c.un.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9145 | | { 1948 /* c.un.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
9146 | | { 1948 /* c.un.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
9147 | | { 1948 /* c.un.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9148 | | { 1948 /* c.un.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9149 | | { 1948 /* c.un.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
9150 | | { 1948 /* c.un.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
9151 | | { 1955 /* c.un.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9152 | | { 1955 /* c.un.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
9153 | | { 1955 /* c.un.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9154 | | { 1955 /* c.un.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9155 | | { 1955 /* c.un.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
9156 | | { 1955 /* c.un.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
9157 | | { 1962 /* cache */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
9158 | | { 1962 /* cache */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips }, |
9159 | | { 1962 /* cache */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 }, |
9160 | | { 1962 /* cache */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 }, |
9161 | | { 1968 /* cachee */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
9162 | | { 1968 /* cachee */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA }, |
9163 | | { 1975 /* ceil.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips }, |
9164 | | { 1975 /* ceil.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9165 | | { 1984 /* ceil.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
9166 | | { 1984 /* ceil.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
9167 | | { 1984 /* ceil.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9168 | | { 1984 /* ceil.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9169 | | { 1993 /* ceil.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
9170 | | { 1993 /* ceil.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
9171 | | { 1993 /* ceil.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9172 | | { 1993 /* ceil.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9173 | | { 1993 /* ceil.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
9174 | | { 1993 /* ceil.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
9175 | | { 1993 /* ceil.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
9176 | | { 1993 /* ceil.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
9177 | | { 2002 /* ceil.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
9178 | | { 2002 /* ceil.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9179 | | { 2002 /* ceil.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
9180 | | { 2011 /* ceq.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9181 | | { 2017 /* ceq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9182 | | { 2023 /* ceq.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9183 | | { 2029 /* ceq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9184 | | { 2035 /* ceqi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9185 | | { 2042 /* ceqi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9186 | | { 2049 /* ceqi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9187 | | { 2056 /* ceqi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9188 | | { 2063 /* cfc1 */, 2 /* 1 */, MCK_CCRAsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
9189 | | { 2063 /* cfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
9190 | | { 2063 /* cfc1 */, 2 /* 1 */, MCK_CCRAsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
9191 | | { 2063 /* cfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
9192 | | { 2068 /* cfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips }, |
9193 | | { 2068 /* cfc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
9194 | | { 2073 /* cfcmsa */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9195 | | { 2073 /* cfcmsa */, 2 /* 1 */, MCK_MSACtrlAsmReg, AMFBS_HasStdEnc_HasMSA }, |
9196 | | { 2080 /* cftc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT }, |
9197 | | { 2080 /* cftc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
9198 | | { 2086 /* cins */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips }, |
9199 | | { 2086 /* cins */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips }, |
9200 | | { 2086 /* cins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips }, |
9201 | | { 2086 /* cins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips }, |
9202 | | { 2091 /* cins32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips }, |
9203 | | { 2091 /* cins32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips }, |
9204 | | { 2098 /* class.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9205 | | { 2098 /* class.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
9206 | | { 2106 /* class.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9207 | | { 2106 /* class.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
9208 | | { 2114 /* cle_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9209 | | { 2122 /* cle_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9210 | | { 2130 /* cle_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9211 | | { 2138 /* cle_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9212 | | { 2146 /* cle_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9213 | | { 2154 /* cle_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9214 | | { 2162 /* cle_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9215 | | { 2170 /* cle_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9216 | | { 2178 /* clei_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9217 | | { 2187 /* clei_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9218 | | { 2196 /* clei_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9219 | | { 2205 /* clei_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9220 | | { 2214 /* clei_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9221 | | { 2223 /* clei_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9222 | | { 2232 /* clei_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9223 | | { 2241 /* clei_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9224 | | { 2250 /* clo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips }, |
9225 | | { 2250 /* clo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
9226 | | { 2250 /* clo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
9227 | | { 2250 /* clo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
9228 | | { 2254 /* clt_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9229 | | { 2262 /* clt_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9230 | | { 2270 /* clt_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9231 | | { 2278 /* clt_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9232 | | { 2286 /* clt_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9233 | | { 2294 /* clt_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9234 | | { 2302 /* clt_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9235 | | { 2310 /* clt_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9236 | | { 2318 /* clti_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9237 | | { 2327 /* clti_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9238 | | { 2336 /* clti_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9239 | | { 2345 /* clti_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9240 | | { 2354 /* clti_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9241 | | { 2363 /* clti_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9242 | | { 2372 /* clti_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9243 | | { 2381 /* clti_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9244 | | { 2390 /* clz */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips }, |
9245 | | { 2390 /* clz */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
9246 | | { 2390 /* clz */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
9247 | | { 2390 /* clz */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
9248 | | { 2398 /* cmp.af.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9249 | | { 2398 /* cmp.af.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9250 | | { 2398 /* cmp.af.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9251 | | { 2398 /* cmp.af.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9252 | | { 2407 /* cmp.af.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9253 | | { 2407 /* cmp.af.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9254 | | { 2416 /* cmp.eq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9255 | | { 2416 /* cmp.eq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9256 | | { 2416 /* cmp.eq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9257 | | { 2416 /* cmp.eq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9258 | | { 2425 /* cmp.eq.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9259 | | { 2425 /* cmp.eq.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9260 | | { 2435 /* cmp.eq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9261 | | { 2435 /* cmp.eq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9262 | | { 2444 /* cmp.le.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9263 | | { 2444 /* cmp.le.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9264 | | { 2444 /* cmp.le.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9265 | | { 2444 /* cmp.le.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9266 | | { 2453 /* cmp.le.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9267 | | { 2453 /* cmp.le.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9268 | | { 2463 /* cmp.le.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9269 | | { 2463 /* cmp.le.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9270 | | { 2472 /* cmp.lt.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9271 | | { 2472 /* cmp.lt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9272 | | { 2472 /* cmp.lt.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9273 | | { 2472 /* cmp.lt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9274 | | { 2481 /* cmp.lt.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9275 | | { 2481 /* cmp.lt.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9276 | | { 2491 /* cmp.lt.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9277 | | { 2491 /* cmp.lt.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9278 | | { 2500 /* cmp.saf.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9279 | | { 2500 /* cmp.saf.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9280 | | { 2500 /* cmp.saf.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9281 | | { 2500 /* cmp.saf.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9282 | | { 2510 /* cmp.saf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9283 | | { 2510 /* cmp.saf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9284 | | { 2520 /* cmp.seq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9285 | | { 2520 /* cmp.seq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9286 | | { 2520 /* cmp.seq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9287 | | { 2520 /* cmp.seq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9288 | | { 2530 /* cmp.seq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9289 | | { 2530 /* cmp.seq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9290 | | { 2540 /* cmp.sle.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9291 | | { 2540 /* cmp.sle.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9292 | | { 2540 /* cmp.sle.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9293 | | { 2540 /* cmp.sle.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9294 | | { 2550 /* cmp.sle.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9295 | | { 2550 /* cmp.sle.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9296 | | { 2560 /* cmp.slt.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9297 | | { 2560 /* cmp.slt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9298 | | { 2560 /* cmp.slt.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9299 | | { 2560 /* cmp.slt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9300 | | { 2570 /* cmp.slt.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9301 | | { 2570 /* cmp.slt.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9302 | | { 2580 /* cmp.sueq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9303 | | { 2580 /* cmp.sueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9304 | | { 2580 /* cmp.sueq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9305 | | { 2580 /* cmp.sueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9306 | | { 2591 /* cmp.sueq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9307 | | { 2591 /* cmp.sueq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9308 | | { 2602 /* cmp.sule.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9309 | | { 2602 /* cmp.sule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9310 | | { 2602 /* cmp.sule.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9311 | | { 2602 /* cmp.sule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9312 | | { 2613 /* cmp.sule.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9313 | | { 2613 /* cmp.sule.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9314 | | { 2624 /* cmp.sult.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9315 | | { 2624 /* cmp.sult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9316 | | { 2624 /* cmp.sult.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9317 | | { 2624 /* cmp.sult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9318 | | { 2635 /* cmp.sult.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9319 | | { 2635 /* cmp.sult.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9320 | | { 2646 /* cmp.sun.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9321 | | { 2646 /* cmp.sun.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9322 | | { 2646 /* cmp.sun.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9323 | | { 2646 /* cmp.sun.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9324 | | { 2656 /* cmp.sun.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9325 | | { 2656 /* cmp.sun.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9326 | | { 2666 /* cmp.ueq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9327 | | { 2666 /* cmp.ueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9328 | | { 2666 /* cmp.ueq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9329 | | { 2666 /* cmp.ueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9330 | | { 2676 /* cmp.ueq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9331 | | { 2676 /* cmp.ueq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9332 | | { 2686 /* cmp.ule.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9333 | | { 2686 /* cmp.ule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9334 | | { 2686 /* cmp.ule.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9335 | | { 2686 /* cmp.ule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9336 | | { 2696 /* cmp.ule.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9337 | | { 2696 /* cmp.ule.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9338 | | { 2706 /* cmp.ult.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9339 | | { 2706 /* cmp.ult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9340 | | { 2706 /* cmp.ult.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9341 | | { 2706 /* cmp.ult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9342 | | { 2716 /* cmp.ult.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9343 | | { 2716 /* cmp.ult.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9344 | | { 2726 /* cmp.un.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9345 | | { 2726 /* cmp.un.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9346 | | { 2726 /* cmp.un.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9347 | | { 2726 /* cmp.un.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9348 | | { 2735 /* cmp.un.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
9349 | | { 2735 /* cmp.un.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9350 | | { 2744 /* cmpgdu.eq.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
9351 | | { 2744 /* cmpgdu.eq.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
9352 | | { 2757 /* cmpgdu.le.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
9353 | | { 2757 /* cmpgdu.le.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
9354 | | { 2770 /* cmpgdu.lt.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
9355 | | { 2770 /* cmpgdu.lt.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
9356 | | { 2783 /* cmpgu.eq.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9357 | | { 2783 /* cmpgu.eq.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9358 | | { 2795 /* cmpgu.le.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9359 | | { 2795 /* cmpgu.le.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9360 | | { 2807 /* cmpgu.lt.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9361 | | { 2807 /* cmpgu.lt.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9362 | | { 2824 /* cmpu.eq.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9363 | | { 2824 /* cmpu.eq.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9364 | | { 2835 /* cmpu.le.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9365 | | { 2835 /* cmpu.le.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9366 | | { 2846 /* cmpu.lt.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9367 | | { 2846 /* cmpu.lt.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9368 | | { 2857 /* copy_s.b */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9369 | | { 2857 /* copy_s.b */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9370 | | { 2866 /* copy_s.d */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 }, |
9371 | | { 2866 /* copy_s.d */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 }, |
9372 | | { 2875 /* copy_s.h */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9373 | | { 2875 /* copy_s.h */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9374 | | { 2884 /* copy_s.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9375 | | { 2884 /* copy_s.w */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9376 | | { 2893 /* copy_u.b */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9377 | | { 2893 /* copy_u.b */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9378 | | { 2902 /* copy_u.h */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9379 | | { 2902 /* copy_u.h */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9380 | | { 2911 /* copy_u.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 }, |
9381 | | { 2911 /* copy_u.w */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 }, |
9382 | | { 2920 /* crc32b */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips }, |
9383 | | { 2927 /* crc32cb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips }, |
9384 | | { 2935 /* crc32cd */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips }, |
9385 | | { 2943 /* crc32ch */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips }, |
9386 | | { 2951 /* crc32cw */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips }, |
9387 | | { 2959 /* crc32d */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips }, |
9388 | | { 2966 /* crc32h */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips }, |
9389 | | { 2973 /* crc32w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips }, |
9390 | | { 2980 /* ctc1 */, 2 /* 1 */, MCK_CCRAsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
9391 | | { 2980 /* ctc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
9392 | | { 2980 /* ctc1 */, 2 /* 1 */, MCK_CCRAsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
9393 | | { 2980 /* ctc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
9394 | | { 2985 /* ctc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips }, |
9395 | | { 2985 /* ctc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
9396 | | { 2990 /* ctcmsa */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9397 | | { 2990 /* ctcmsa */, 1 /* 0 */, MCK_MSACtrlAsmReg, AMFBS_HasStdEnc_HasMSA }, |
9398 | | { 2997 /* cttc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT }, |
9399 | | { 2997 /* cttc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
9400 | | { 3003 /* cvt.d.l */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips }, |
9401 | | { 3003 /* cvt.d.l */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat }, |
9402 | | { 3011 /* cvt.d.s */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
9403 | | { 3011 /* cvt.d.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
9404 | | { 3011 /* cvt.d.s */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
9405 | | { 3011 /* cvt.d.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
9406 | | { 3011 /* cvt.d.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
9407 | | { 3011 /* cvt.d.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
9408 | | { 3011 /* cvt.d.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
9409 | | { 3011 /* cvt.d.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
9410 | | { 3019 /* cvt.d.w */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
9411 | | { 3019 /* cvt.d.w */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
9412 | | { 3019 /* cvt.d.w */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
9413 | | { 3019 /* cvt.d.w */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
9414 | | { 3019 /* cvt.d.w */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
9415 | | { 3019 /* cvt.d.w */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
9416 | | { 3019 /* cvt.d.w */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
9417 | | { 3019 /* cvt.d.w */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
9418 | | { 3027 /* cvt.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips }, |
9419 | | { 3027 /* cvt.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
9420 | | { 3027 /* cvt.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9421 | | { 3035 /* cvt.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips }, |
9422 | | { 3035 /* cvt.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips }, |
9423 | | { 3035 /* cvt.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
9424 | | { 3035 /* cvt.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
9425 | | { 3035 /* cvt.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9426 | | { 3035 /* cvt.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9427 | | { 3043 /* cvt.ps.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9428 | | { 3043 /* cvt.ps.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9429 | | { 3052 /* cvt.s.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
9430 | | { 3052 /* cvt.s.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
9431 | | { 3052 /* cvt.s.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
9432 | | { 3052 /* cvt.s.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
9433 | | { 3052 /* cvt.s.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
9434 | | { 3052 /* cvt.s.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
9435 | | { 3052 /* cvt.s.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
9436 | | { 3052 /* cvt.s.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
9437 | | { 3060 /* cvt.s.l */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips }, |
9438 | | { 3060 /* cvt.s.l */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips }, |
9439 | | { 3060 /* cvt.s.l */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat }, |
9440 | | { 3060 /* cvt.s.l */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat }, |
9441 | | { 3068 /* cvt.s.pl */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9442 | | { 3068 /* cvt.s.pl */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9443 | | { 3077 /* cvt.s.pu */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9444 | | { 3077 /* cvt.s.pu */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
9445 | | { 3086 /* cvt.s.w */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
9446 | | { 3086 /* cvt.s.w */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9447 | | { 3086 /* cvt.s.w */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
9448 | | { 3094 /* cvt.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
9449 | | { 3094 /* cvt.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
9450 | | { 3094 /* cvt.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
9451 | | { 3094 /* cvt.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
9452 | | { 3094 /* cvt.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
9453 | | { 3094 /* cvt.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
9454 | | { 3094 /* cvt.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
9455 | | { 3094 /* cvt.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
9456 | | { 3102 /* cvt.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
9457 | | { 3102 /* cvt.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9458 | | { 3102 /* cvt.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
9459 | | { 3110 /* dadd */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9460 | | { 3110 /* dadd */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
9461 | | { 3110 /* dadd */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9462 | | { 3110 /* dadd */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
9463 | | { 3115 /* daddi */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
9464 | | { 3115 /* daddi */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
9465 | | { 3121 /* daddiu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9466 | | { 3121 /* daddiu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9467 | | { 3128 /* daddu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9468 | | { 3128 /* daddu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9469 | | { 3128 /* daddu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9470 | | { 3128 /* daddu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9471 | | { 3134 /* dahi */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
9472 | | { 3139 /* dalign */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
9473 | | { 3146 /* dati */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
9474 | | { 3151 /* daui */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
9475 | | { 3156 /* dbitswap */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
9476 | | { 3165 /* dclo */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips }, |
9477 | | { 3165 /* dclo */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
9478 | | { 3170 /* dclz */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips }, |
9479 | | { 3170 /* dclz */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
9480 | | { 3175 /* ddiv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
9481 | | { 3175 /* ddiv */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
9482 | | { 3175 /* ddiv */, 6 /* 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
9483 | | { 3175 /* ddiv */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
9484 | | { 3175 /* ddiv */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
9485 | | { 3175 /* ddiv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
9486 | | { 3180 /* ddivu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
9487 | | { 3180 /* ddivu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
9488 | | { 3180 /* ddivu */, 6 /* 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
9489 | | { 3180 /* ddivu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
9490 | | { 3180 /* ddivu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
9491 | | { 3180 /* ddivu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
9492 | | { 3192 /* dext */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
9493 | | { 3192 /* dext */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
9494 | | { 3192 /* dext */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
9495 | | { 3197 /* dextm */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
9496 | | { 3203 /* dextu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
9497 | | { 3209 /* di */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, |
9498 | | { 3209 /* di */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
9499 | | { 3209 /* di */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
9500 | | { 3212 /* dins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
9501 | | { 3212 /* dins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
9502 | | { 3212 /* dins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
9503 | | { 3217 /* dinsm */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
9504 | | { 3223 /* dinsu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
9505 | | { 3229 /* div */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
9506 | | { 3229 /* div */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
9507 | | { 3229 /* div */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
9508 | | { 3229 /* div */, 1 /* 0 */, MCK_GPR32NonZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
9509 | | { 3229 /* div */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
9510 | | { 3229 /* div */, 1 /* 0 */, MCK_GPR32ZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
9511 | | { 3229 /* div */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
9512 | | { 3229 /* div */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
9513 | | { 3229 /* div */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
9514 | | { 3229 /* div */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
9515 | | { 3229 /* div */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
9516 | | { 3229 /* div */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
9517 | | { 3229 /* div */, 1 /* 0 */, MCK_GPR32NonZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
9518 | | { 3233 /* div.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
9519 | | { 3233 /* div.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
9520 | | { 3233 /* div.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
9521 | | { 3233 /* div.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
9522 | | { 3239 /* div.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
9523 | | { 3239 /* div.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9524 | | { 3239 /* div.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
9525 | | { 3245 /* div_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9526 | | { 3253 /* div_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9527 | | { 3261 /* div_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9528 | | { 3269 /* div_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9529 | | { 3277 /* div_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9530 | | { 3285 /* div_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9531 | | { 3293 /* div_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9532 | | { 3301 /* div_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9533 | | { 3309 /* divu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
9534 | | { 3309 /* divu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
9535 | | { 3309 /* divu */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
9536 | | { 3309 /* divu */, 1 /* 0 */, MCK_GPR32NonZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
9537 | | { 3309 /* divu */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
9538 | | { 3309 /* divu */, 1 /* 0 */, MCK_GPR32ZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
9539 | | { 3309 /* divu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
9540 | | { 3309 /* divu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
9541 | | { 3309 /* divu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
9542 | | { 3309 /* divu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
9543 | | { 3309 /* divu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
9544 | | { 3309 /* divu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
9545 | | { 3314 /* dla */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None }, |
9546 | | { 3314 /* dla */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None }, |
9547 | | { 3314 /* dla */, 2 /* 1 */, MCK_Mem, AMFBS_None }, |
9548 | | { 3318 /* dli */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None }, |
9549 | | { 3322 /* dlsa */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 }, |
9550 | | { 3322 /* dlsa */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
9551 | | { 3327 /* dmfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_NotInMicroMips }, |
9552 | | { 3327 /* dmfc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_NotInMicroMips }, |
9553 | | { 3327 /* dmfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 }, |
9554 | | { 3327 /* dmfc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 }, |
9555 | | { 3333 /* dmfc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips }, |
9556 | | { 3333 /* dmfc1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips }, |
9557 | | { 3339 /* dmfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_None }, |
9558 | | { 3339 /* dmfc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None }, |
9559 | | { 3339 /* dmfc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
9560 | | { 3339 /* dmfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 }, |
9561 | | { 3339 /* dmfc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 }, |
9562 | | { 3345 /* dmfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips }, |
9563 | | { 3345 /* dmfgc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips }, |
9564 | | { 3345 /* dmfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt }, |
9565 | | { 3345 /* dmfgc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt }, |
9566 | | { 3352 /* dmod */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
9567 | | { 3357 /* dmodu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
9568 | | { 3363 /* dmt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips }, |
9569 | | { 3367 /* dmtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_NotInMicroMips }, |
9570 | | { 3367 /* dmtc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_NotInMicroMips }, |
9571 | | { 3367 /* dmtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 }, |
9572 | | { 3367 /* dmtc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 }, |
9573 | | { 3373 /* dmtc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips }, |
9574 | | { 3373 /* dmtc1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips }, |
9575 | | { 3379 /* dmtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_None }, |
9576 | | { 3379 /* dmtc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None }, |
9577 | | { 3379 /* dmtc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
9578 | | { 3379 /* dmtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 }, |
9579 | | { 3379 /* dmtc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 }, |
9580 | | { 3385 /* dmtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips }, |
9581 | | { 3385 /* dmtgc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips }, |
9582 | | { 3385 /* dmtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt }, |
9583 | | { 3385 /* dmtgc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt }, |
9584 | | { 3392 /* dmuh */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
9585 | | { 3397 /* dmuhu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
9586 | | { 3403 /* dmul */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
9587 | | { 3403 /* dmul */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasMips3_NotMips64r6_NotCnMips }, |
9588 | | { 3403 /* dmul */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
9589 | | { 3403 /* dmul */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
9590 | | { 3403 /* dmul */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
9591 | | { 3408 /* dmulo */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
9592 | | { 3414 /* dmulou */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
9593 | | { 3421 /* dmult */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
9594 | | { 3427 /* dmultu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
9595 | | { 3434 /* dmulu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
9596 | | { 3440 /* dneg */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9597 | | { 3440 /* dneg */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9598 | | { 3445 /* dnegu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9599 | | { 3445 /* dnegu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9600 | | { 3451 /* dotp_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9601 | | { 3460 /* dotp_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9602 | | { 3469 /* dotp_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9603 | | { 3478 /* dotp_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9604 | | { 3487 /* dotp_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9605 | | { 3496 /* dotp_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9606 | | { 3505 /* dpa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
9607 | | { 3505 /* dpa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
9608 | | { 3505 /* dpa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 }, |
9609 | | { 3505 /* dpa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
9610 | | { 3514 /* dpadd_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9611 | | { 3524 /* dpadd_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9612 | | { 3534 /* dpadd_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9613 | | { 3544 /* dpadd_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9614 | | { 3554 /* dpadd_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9615 | | { 3564 /* dpadd_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9616 | | { 3574 /* dpaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
9617 | | { 3574 /* dpaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9618 | | { 3574 /* dpaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
9619 | | { 3574 /* dpaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9620 | | { 3586 /* dpaq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
9621 | | { 3586 /* dpaq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9622 | | { 3586 /* dpaq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
9623 | | { 3586 /* dpaq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9624 | | { 3598 /* dpaqx_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
9625 | | { 3598 /* dpaqx_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
9626 | | { 3598 /* dpaqx_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 }, |
9627 | | { 3598 /* dpaqx_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
9628 | | { 3611 /* dpaqx_sa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
9629 | | { 3611 /* dpaqx_sa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
9630 | | { 3611 /* dpaqx_sa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 }, |
9631 | | { 3611 /* dpaqx_sa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
9632 | | { 3625 /* dpau.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
9633 | | { 3625 /* dpau.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9634 | | { 3625 /* dpau.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
9635 | | { 3625 /* dpau.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9636 | | { 3636 /* dpau.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
9637 | | { 3636 /* dpau.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9638 | | { 3636 /* dpau.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
9639 | | { 3636 /* dpau.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9640 | | { 3647 /* dpax.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
9641 | | { 3647 /* dpax.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
9642 | | { 3647 /* dpax.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 }, |
9643 | | { 3647 /* dpax.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
9644 | | { 3657 /* dpop */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
9645 | | { 3657 /* dpop */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
9646 | | { 3662 /* dps.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
9647 | | { 3662 /* dps.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
9648 | | { 3662 /* dps.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 }, |
9649 | | { 3662 /* dps.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
9650 | | { 3671 /* dpsq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
9651 | | { 3671 /* dpsq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9652 | | { 3671 /* dpsq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
9653 | | { 3671 /* dpsq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9654 | | { 3683 /* dpsq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
9655 | | { 3683 /* dpsq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9656 | | { 3683 /* dpsq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
9657 | | { 3683 /* dpsq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9658 | | { 3695 /* dpsqx_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
9659 | | { 3695 /* dpsqx_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
9660 | | { 3695 /* dpsqx_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 }, |
9661 | | { 3695 /* dpsqx_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
9662 | | { 3708 /* dpsqx_sa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
9663 | | { 3708 /* dpsqx_sa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
9664 | | { 3708 /* dpsqx_sa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 }, |
9665 | | { 3708 /* dpsqx_sa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
9666 | | { 3722 /* dpsu.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
9667 | | { 3722 /* dpsu.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9668 | | { 3722 /* dpsu.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
9669 | | { 3722 /* dpsu.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9670 | | { 3733 /* dpsu.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
9671 | | { 3733 /* dpsu.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9672 | | { 3733 /* dpsu.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
9673 | | { 3733 /* dpsu.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9674 | | { 3744 /* dpsub_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9675 | | { 3754 /* dpsub_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9676 | | { 3764 /* dpsub_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9677 | | { 3774 /* dpsub_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9678 | | { 3784 /* dpsub_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9679 | | { 3794 /* dpsub_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9680 | | { 3804 /* dpsx.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
9681 | | { 3804 /* dpsx.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
9682 | | { 3804 /* dpsx.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 }, |
9683 | | { 3804 /* dpsx.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
9684 | | { 3814 /* drem */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
9685 | | { 3814 /* drem */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
9686 | | { 3814 /* drem */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
9687 | | { 3814 /* drem */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
9688 | | { 3819 /* dremu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
9689 | | { 3819 /* dremu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
9690 | | { 3819 /* dremu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
9691 | | { 3819 /* dremu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
9692 | | { 3825 /* drol */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 }, |
9693 | | { 3825 /* drol */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 }, |
9694 | | { 3825 /* drol */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 }, |
9695 | | { 3825 /* drol */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 }, |
9696 | | { 3830 /* dror */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 }, |
9697 | | { 3830 /* dror */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 }, |
9698 | | { 3830 /* dror */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 }, |
9699 | | { 3830 /* dror */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 }, |
9700 | | { 3835 /* drotr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
9701 | | { 3835 /* drotr */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
9702 | | { 3841 /* drotr32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
9703 | | { 3841 /* drotr32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
9704 | | { 3849 /* drotrv */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
9705 | | { 3849 /* drotrv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
9706 | | { 3856 /* dsbh */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
9707 | | { 3861 /* dshd */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
9708 | | { 3866 /* dsll */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9709 | | { 3866 /* dsll */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9710 | | { 3866 /* dsll */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9711 | | { 3866 /* dsll */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9712 | | { 3866 /* dsll */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9713 | | { 3866 /* dsll */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9714 | | { 3871 /* dsll32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9715 | | { 3871 /* dsll32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9716 | | { 3878 /* dsllv */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9717 | | { 3878 /* dsllv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9718 | | { 3884 /* dsra */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9719 | | { 3884 /* dsra */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3 }, |
9720 | | { 3884 /* dsra */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3 }, |
9721 | | { 3884 /* dsra */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9722 | | { 3889 /* dsra32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9723 | | { 3889 /* dsra32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9724 | | { 3896 /* dsrav */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9725 | | { 3896 /* dsrav */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9726 | | { 3902 /* dsrl */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9727 | | { 3902 /* dsrl */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9728 | | { 3902 /* dsrl */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9729 | | { 3902 /* dsrl */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9730 | | { 3902 /* dsrl */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9731 | | { 3902 /* dsrl */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9732 | | { 3907 /* dsrl32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9733 | | { 3907 /* dsrl32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9734 | | { 3914 /* dsrlv */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9735 | | { 3914 /* dsrlv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9736 | | { 3920 /* dsub */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9737 | | { 3920 /* dsub */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
9738 | | { 3920 /* dsub */, 2 /* 1 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
9739 | | { 3920 /* dsub */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9740 | | { 3920 /* dsub */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
9741 | | { 3920 /* dsub */, 4 /* 2 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
9742 | | { 3925 /* dsubi */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
9743 | | { 3925 /* dsubi */, 2 /* 1 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
9744 | | { 3925 /* dsubi */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
9745 | | { 3925 /* dsubi */, 4 /* 2 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
9746 | | { 3931 /* dsubu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9747 | | { 3931 /* dsubu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9748 | | { 3931 /* dsubu */, 2 /* 1 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9749 | | { 3931 /* dsubu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9750 | | { 3931 /* dsubu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9751 | | { 3931 /* dsubu */, 4 /* 2 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
9752 | | { 3937 /* dvp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
9753 | | { 3937 /* dvp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
9754 | | { 3941 /* dvpe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips }, |
9755 | | { 3950 /* ei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, |
9756 | | { 3950 /* ei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
9757 | | { 3950 /* ei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
9758 | | { 3953 /* emt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips }, |
9759 | | { 3969 /* evp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
9760 | | { 3969 /* evp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
9761 | | { 3973 /* evpe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips }, |
9762 | | { 3978 /* ext */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, |
9763 | | { 3978 /* ext */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
9764 | | { 3978 /* ext */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
9765 | | { 3982 /* extp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
9766 | | { 3982 /* extp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9767 | | { 3982 /* extp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
9768 | | { 3982 /* extp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9769 | | { 3987 /* extpdp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
9770 | | { 3987 /* extpdp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9771 | | { 3987 /* extpdp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
9772 | | { 3987 /* extpdp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9773 | | { 3994 /* extpdpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
9774 | | { 3994 /* extpdpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9775 | | { 3994 /* extpdpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
9776 | | { 3994 /* extpdpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9777 | | { 4002 /* extpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
9778 | | { 4002 /* extpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9779 | | { 4002 /* extpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
9780 | | { 4002 /* extpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9781 | | { 4008 /* extr.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
9782 | | { 4008 /* extr.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9783 | | { 4008 /* extr.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
9784 | | { 4008 /* extr.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9785 | | { 4015 /* extr_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
9786 | | { 4015 /* extr_r.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9787 | | { 4015 /* extr_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
9788 | | { 4015 /* extr_r.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9789 | | { 4024 /* extr_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
9790 | | { 4024 /* extr_rs.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9791 | | { 4024 /* extr_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
9792 | | { 4024 /* extr_rs.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9793 | | { 4034 /* extr_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
9794 | | { 4034 /* extr_s.h */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9795 | | { 4034 /* extr_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
9796 | | { 4034 /* extr_s.h */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9797 | | { 4043 /* extrv.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
9798 | | { 4043 /* extrv.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9799 | | { 4043 /* extrv.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
9800 | | { 4043 /* extrv.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9801 | | { 4051 /* extrv_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
9802 | | { 4051 /* extrv_r.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9803 | | { 4051 /* extrv_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
9804 | | { 4051 /* extrv_r.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9805 | | { 4061 /* extrv_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
9806 | | { 4061 /* extrv_rs.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9807 | | { 4061 /* extrv_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
9808 | | { 4061 /* extrv_rs.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9809 | | { 4072 /* extrv_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
9810 | | { 4072 /* extrv_s.h */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9811 | | { 4072 /* extrv_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
9812 | | { 4072 /* extrv_s.h */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9813 | | { 4082 /* exts */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips }, |
9814 | | { 4082 /* exts */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips }, |
9815 | | { 4082 /* exts */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips }, |
9816 | | { 4082 /* exts */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips }, |
9817 | | { 4087 /* exts32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips }, |
9818 | | { 4087 /* exts32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips }, |
9819 | | { 4094 /* fadd.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9820 | | { 4101 /* fadd.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9821 | | { 4108 /* fcaf.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9822 | | { 4115 /* fcaf.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9823 | | { 4122 /* fceq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9824 | | { 4129 /* fceq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9825 | | { 4136 /* fclass.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9826 | | { 4145 /* fclass.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9827 | | { 4154 /* fcle.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9828 | | { 4161 /* fcle.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9829 | | { 4168 /* fclt.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9830 | | { 4175 /* fclt.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9831 | | { 4182 /* fcne.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9832 | | { 4189 /* fcne.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9833 | | { 4196 /* fcor.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9834 | | { 4203 /* fcor.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9835 | | { 4210 /* fcueq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9836 | | { 4218 /* fcueq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9837 | | { 4226 /* fcule.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9838 | | { 4234 /* fcule.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9839 | | { 4242 /* fcult.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9840 | | { 4250 /* fcult.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9841 | | { 4258 /* fcun.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9842 | | { 4265 /* fcun.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9843 | | { 4272 /* fcune.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9844 | | { 4280 /* fcune.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9845 | | { 4288 /* fdiv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9846 | | { 4295 /* fdiv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9847 | | { 4302 /* fexdo.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9848 | | { 4310 /* fexdo.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9849 | | { 4318 /* fexp2.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9850 | | { 4326 /* fexp2.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9851 | | { 4334 /* fexupl.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9852 | | { 4343 /* fexupl.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9853 | | { 4352 /* fexupr.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9854 | | { 4361 /* fexupr.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9855 | | { 4370 /* ffint_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9856 | | { 4380 /* ffint_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9857 | | { 4390 /* ffint_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9858 | | { 4400 /* ffint_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9859 | | { 4410 /* ffql.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9860 | | { 4417 /* ffql.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9861 | | { 4424 /* ffqr.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9862 | | { 4431 /* ffqr.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9863 | | { 4438 /* fill.b */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9864 | | { 4438 /* fill.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9865 | | { 4445 /* fill.d */, 2 /* 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 }, |
9866 | | { 4445 /* fill.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 }, |
9867 | | { 4452 /* fill.h */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9868 | | { 4452 /* fill.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9869 | | { 4459 /* fill.w */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9870 | | { 4459 /* fill.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9871 | | { 4466 /* flog2.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9872 | | { 4474 /* flog2.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9873 | | { 4482 /* floor.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips }, |
9874 | | { 4482 /* floor.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9875 | | { 4492 /* floor.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
9876 | | { 4492 /* floor.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
9877 | | { 4492 /* floor.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9878 | | { 4492 /* floor.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9879 | | { 4502 /* floor.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
9880 | | { 4502 /* floor.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
9881 | | { 4502 /* floor.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9882 | | { 4502 /* floor.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9883 | | { 4502 /* floor.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
9884 | | { 4502 /* floor.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
9885 | | { 4502 /* floor.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
9886 | | { 4502 /* floor.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
9887 | | { 4512 /* floor.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
9888 | | { 4512 /* floor.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
9889 | | { 4512 /* floor.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
9890 | | { 4522 /* fmadd.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9891 | | { 4530 /* fmadd.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9892 | | { 4538 /* fmax.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9893 | | { 4545 /* fmax.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9894 | | { 4552 /* fmax_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9895 | | { 4561 /* fmax_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9896 | | { 4570 /* fmin.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9897 | | { 4577 /* fmin.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9898 | | { 4584 /* fmin_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9899 | | { 4593 /* fmin_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9900 | | { 4602 /* fmsub.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9901 | | { 4610 /* fmsub.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9902 | | { 4618 /* fmul.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9903 | | { 4625 /* fmul.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9904 | | { 4632 /* fork */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips }, |
9905 | | { 4637 /* frcp.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9906 | | { 4644 /* frcp.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9907 | | { 4651 /* frint.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9908 | | { 4659 /* frint.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9909 | | { 4667 /* frsqrt.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9910 | | { 4676 /* frsqrt.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9911 | | { 4685 /* fsaf.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9912 | | { 4692 /* fsaf.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9913 | | { 4699 /* fseq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9914 | | { 4706 /* fseq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9915 | | { 4713 /* fsle.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9916 | | { 4720 /* fsle.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9917 | | { 4727 /* fslt.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9918 | | { 4734 /* fslt.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9919 | | { 4741 /* fsne.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9920 | | { 4748 /* fsne.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9921 | | { 4755 /* fsor.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9922 | | { 4762 /* fsor.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9923 | | { 4769 /* fsqrt.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9924 | | { 4777 /* fsqrt.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9925 | | { 4785 /* fsub.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9926 | | { 4792 /* fsub.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9927 | | { 4799 /* fsueq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9928 | | { 4807 /* fsueq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9929 | | { 4815 /* fsule.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9930 | | { 4823 /* fsule.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9931 | | { 4831 /* fsult.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9932 | | { 4839 /* fsult.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9933 | | { 4847 /* fsun.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9934 | | { 4854 /* fsun.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9935 | | { 4861 /* fsune.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9936 | | { 4869 /* fsune.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9937 | | { 4877 /* ftint_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9938 | | { 4887 /* ftint_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9939 | | { 4897 /* ftint_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9940 | | { 4907 /* ftint_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9941 | | { 4917 /* ftq.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9942 | | { 4923 /* ftq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9943 | | { 4929 /* ftrunc_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9944 | | { 4940 /* ftrunc_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9945 | | { 4951 /* ftrunc_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9946 | | { 4962 /* ftrunc_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9947 | | { 4973 /* ginvi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips }, |
9948 | | { 4973 /* ginvi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6_HasGINV }, |
9949 | | { 4979 /* ginvt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips }, |
9950 | | { 4979 /* ginvt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6_HasGINV }, |
9951 | | { 4985 /* hadd_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9952 | | { 4994 /* hadd_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9953 | | { 5003 /* hadd_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9954 | | { 5012 /* hadd_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9955 | | { 5021 /* hadd_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9956 | | { 5030 /* hadd_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9957 | | { 5039 /* hsub_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9958 | | { 5048 /* hsub_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9959 | | { 5057 /* hsub_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9960 | | { 5066 /* hsub_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9961 | | { 5075 /* hsub_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9962 | | { 5084 /* hsub_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9963 | | { 5101 /* ilvev.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9964 | | { 5109 /* ilvev.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9965 | | { 5117 /* ilvev.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9966 | | { 5125 /* ilvev.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9967 | | { 5133 /* ilvl.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9968 | | { 5140 /* ilvl.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9969 | | { 5147 /* ilvl.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9970 | | { 5154 /* ilvl.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9971 | | { 5161 /* ilvod.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9972 | | { 5169 /* ilvod.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9973 | | { 5177 /* ilvod.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9974 | | { 5185 /* ilvod.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9975 | | { 5193 /* ilvr.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9976 | | { 5200 /* ilvr.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9977 | | { 5207 /* ilvr.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9978 | | { 5214 /* ilvr.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9979 | | { 5221 /* ins */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, |
9980 | | { 5221 /* ins */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
9981 | | { 5221 /* ins */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
9982 | | { 5225 /* insert.b */, 16 /* 4 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9983 | | { 5225 /* insert.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9984 | | { 5234 /* insert.d */, 16 /* 4 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 }, |
9985 | | { 5234 /* insert.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 }, |
9986 | | { 5243 /* insert.h */, 16 /* 4 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9987 | | { 5243 /* insert.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9988 | | { 5252 /* insert.w */, 16 /* 4 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9989 | | { 5252 /* insert.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9990 | | { 5261 /* insv */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
9991 | | { 5261 /* insv */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
9992 | | { 5266 /* insve.b */, 17 /* 0, 4 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9993 | | { 5274 /* insve.d */, 17 /* 0, 4 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9994 | | { 5282 /* insve.h */, 17 /* 0, 4 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9995 | | { 5290 /* insve.w */, 17 /* 0, 4 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
9996 | | { 5298 /* j */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
9997 | | { 5298 /* j */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
9998 | | { 5298 /* j */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, |
9999 | | { 5300 /* jal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
10000 | | { 5300 /* jal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, |
10001 | | { 5300 /* jal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
10002 | | { 5300 /* jal */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
10003 | | { 5304 /* jalr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10004 | | { 5304 /* jalr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10005 | | { 5304 /* jalr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips }, |
10006 | | { 5304 /* jalr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards }, |
10007 | | { 5304 /* jalr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10008 | | { 5304 /* jalr */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_NotInMips16Mode_IsPTR64bit }, |
10009 | | { 5309 /* jalr.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotInMicroMips }, |
10010 | | { 5309 /* jalr.hb */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64_NotInMicroMips }, |
10011 | | { 5309 /* jalr.hb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32 }, |
10012 | | { 5309 /* jalr.hb */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
10013 | | { 5317 /* jalrc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips }, |
10014 | | { 5317 /* jalrc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10015 | | { 5317 /* jalrc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6 }, |
10016 | | { 5317 /* jalrc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10017 | | { 5323 /* jalrc.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10018 | | { 5323 /* jalrc.hb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10019 | | { 5332 /* jalrs */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10020 | | { 5338 /* jalrs16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10021 | | { 5351 /* jalx */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10022 | | { 5351 /* jalx */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
10023 | | { 5356 /* jialc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
10024 | | { 5356 /* jialc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 }, |
10025 | | { 5356 /* jialc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10026 | | { 5356 /* jialc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
10027 | | { 5356 /* jialc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
10028 | | { 5356 /* jialc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
10029 | | { 5362 /* jic */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
10030 | | { 5362 /* jic */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 }, |
10031 | | { 5362 /* jic */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10032 | | { 5362 /* jic */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
10033 | | { 5362 /* jic */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
10034 | | { 5362 /* jic */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
10035 | | { 5366 /* jr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10036 | | { 5366 /* jr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips }, |
10037 | | { 5366 /* jr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10038 | | { 5366 /* jr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips }, |
10039 | | { 5366 /* jr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6 }, |
10040 | | { 5369 /* jr.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6 }, |
10041 | | { 5369 /* jr.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
10042 | | { 5369 /* jr.hb */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips }, |
10043 | | { 5369 /* jr.hb */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
10044 | | { 5375 /* jr16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10045 | | { 5390 /* jrc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6 }, |
10046 | | { 5390 /* jrc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10047 | | { 5390 /* jrc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6 }, |
10048 | | { 5394 /* jrc16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10049 | | { 5411 /* l.d */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat }, |
10050 | | { 5411 /* l.d */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat }, |
10051 | | { 5411 /* l.d */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat }, |
10052 | | { 5411 /* l.d */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat }, |
10053 | | { 5415 /* l.s */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat }, |
10054 | | { 5415 /* l.s */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat }, |
10055 | | { 5419 /* la */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
10056 | | { 5419 /* la */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
10057 | | { 5419 /* la */, 2 /* 1 */, MCK_Mem, AMFBS_None }, |
10058 | | { 5422 /* lapc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
10059 | | { 5422 /* lapc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10060 | | { 5427 /* lb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10061 | | { 5427 /* lb */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips_HasMips32r6 }, |
10062 | | { 5427 /* lb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
10063 | | { 5427 /* lb */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips }, |
10064 | | { 5427 /* lb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10065 | | { 5427 /* lb */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_NotInMicroMips }, |
10066 | | { 5430 /* lbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
10067 | | { 5430 /* lbe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
10068 | | { 5430 /* lbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, |
10069 | | { 5430 /* lbe */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasEVA }, |
10070 | | { 5434 /* lbu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10071 | | { 5434 /* lbu */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips_HasMips32r6 }, |
10072 | | { 5434 /* lbu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
10073 | | { 5434 /* lbu */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips }, |
10074 | | { 5434 /* lbu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10075 | | { 5434 /* lbu */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_NotInMicroMips }, |
10076 | | { 5438 /* lbu16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips }, |
10077 | | { 5438 /* lbu16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips }, |
10078 | | { 5444 /* lbue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
10079 | | { 5444 /* lbue */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
10080 | | { 5444 /* lbue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, |
10081 | | { 5444 /* lbue */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasEVA }, |
10082 | | { 5449 /* lbux */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10083 | | { 5449 /* lbux */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10084 | | { 5454 /* ld */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips3 }, |
10085 | | { 5454 /* ld */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_NotMips3 }, |
10086 | | { 5454 /* ld */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
10087 | | { 5454 /* ld */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
10088 | | { 5457 /* ld.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10089 | | { 5457 /* ld.b */, 2 /* 1 */, MCK_MemOffsetSimm10, AMFBS_HasStdEnc_HasMSA }, |
10090 | | { 5462 /* ld.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10091 | | { 5462 /* ld.d */, 2 /* 1 */, MCK_MemOffsetSimm10_3, AMFBS_HasStdEnc_HasMSA }, |
10092 | | { 5467 /* ld.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10093 | | { 5467 /* ld.h */, 2 /* 1 */, MCK_MemOffsetSimm10_1, AMFBS_HasStdEnc_HasMSA }, |
10094 | | { 5472 /* ld.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10095 | | { 5472 /* ld.w */, 2 /* 1 */, MCK_MemOffsetSimm10_2, AMFBS_HasStdEnc_HasMSA }, |
10096 | | { 5477 /* ldc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
10097 | | { 5477 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
10098 | | { 5477 /* ldc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
10099 | | { 5477 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
10100 | | { 5477 /* ldc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
10101 | | { 5477 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
10102 | | { 5477 /* ldc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat }, |
10103 | | { 5477 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat }, |
10104 | | { 5482 /* ldc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
10105 | | { 5482 /* ldc2 */, 2 /* 1 */, MCK_MemOffsetSimm11, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
10106 | | { 5482 /* ldc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10107 | | { 5482 /* ldc2 */, 2 /* 1 */, MCK_MemOffsetSimm11, AMFBS_InMicroMips_HasMips32r6 }, |
10108 | | { 5482 /* ldc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10109 | | { 5482 /* ldc2 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10110 | | { 5487 /* ldc3 */, 1 /* 0 */, MCK_COP3AsmReg, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips }, |
10111 | | { 5487 /* ldc3 */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips }, |
10112 | | { 5492 /* ldi.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10113 | | { 5498 /* ldi.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10114 | | { 5504 /* ldi.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10115 | | { 5510 /* ldi.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10116 | | { 5516 /* ldl */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
10117 | | { 5516 /* ldl */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
10118 | | { 5520 /* ldpc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6 }, |
10119 | | { 5520 /* ldpc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips64r6 }, |
10120 | | { 5525 /* ldr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
10121 | | { 5525 /* ldr */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
10122 | | { 5529 /* ldxc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10123 | | { 5529 /* ldxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10124 | | { 5529 /* ldxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat }, |
10125 | | { 5529 /* ldxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat }, |
10126 | | { 5535 /* lh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10127 | | { 5535 /* lh */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_NotInMicroMips }, |
10128 | | { 5535 /* lh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
10129 | | { 5535 /* lh */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_InMicroMips }, |
10130 | | { 5538 /* lhe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
10131 | | { 5538 /* lhe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
10132 | | { 5538 /* lhe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, |
10133 | | { 5538 /* lhe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA }, |
10134 | | { 5542 /* lhu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10135 | | { 5542 /* lhu */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_NotInMicroMips }, |
10136 | | { 5542 /* lhu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
10137 | | { 5542 /* lhu */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_InMicroMips }, |
10138 | | { 5546 /* lhu16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips }, |
10139 | | { 5546 /* lhu16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips }, |
10140 | | { 5552 /* lhue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
10141 | | { 5552 /* lhue */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
10142 | | { 5552 /* lhue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, |
10143 | | { 5552 /* lhue */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA }, |
10144 | | { 5557 /* lhx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10145 | | { 5557 /* lhx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10146 | | { 5561 /* li */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
10147 | | { 5564 /* li.d */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
10148 | | { 5564 /* li.d */, 1 /* 0 */, MCK_StrictlyAFGR64AsmReg, AMFBS_NotFP64bit_IsNotSoftFloat }, |
10149 | | { 5564 /* li.d */, 1 /* 0 */, MCK_StrictlyFGR64AsmReg, AMFBS_IsFP64bit_IsNotSoftFloat }, |
10150 | | { 5569 /* li.s */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
10151 | | { 5569 /* li.s */, 1 /* 0 */, MCK_StrictlyFGR32AsmReg, AMFBS_IsNotSoftFloat }, |
10152 | | { 5574 /* li16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10153 | | { 5574 /* li16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10154 | | { 5579 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips }, |
10155 | | { 5579 /* ll */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips }, |
10156 | | { 5579 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips }, |
10157 | | { 5579 /* ll */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips }, |
10158 | | { 5579 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10159 | | { 5579 /* ll */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasMips32r6 }, |
10160 | | { 5579 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10161 | | { 5579 /* ll */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10162 | | { 5579 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10163 | | { 5579 /* ll */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10164 | | { 5579 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10165 | | { 5579 /* ll */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 }, |
10166 | | { 5582 /* lld */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10167 | | { 5582 /* lld */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10168 | | { 5582 /* lld */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
10169 | | { 5582 /* lld */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
10170 | | { 5586 /* lle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
10171 | | { 5586 /* lle */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
10172 | | { 5586 /* lle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, |
10173 | | { 5586 /* lle */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA }, |
10174 | | { 5590 /* lsa */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10175 | | { 5590 /* lsa */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10176 | | { 5590 /* lsa */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
10177 | | { 5594 /* lui */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10178 | | { 5594 /* lui */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10179 | | { 5594 /* lui */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10180 | | { 5598 /* luxc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10181 | | { 5598 /* luxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10182 | | { 5598 /* luxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10183 | | { 5598 /* luxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10184 | | { 5598 /* luxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
10185 | | { 5598 /* luxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
10186 | | { 5604 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
10187 | | { 5604 /* lw */, 2 /* 1 */, MCK_MicroMipsMemSP, AMFBS_InMicroMips }, |
10188 | | { 5604 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10189 | | { 5604 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotInMicroMips }, |
10190 | | { 5604 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotInMips16Mode_HasDSP }, |
10191 | | { 5604 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_NotInMips16Mode_HasDSP }, |
10192 | | { 5604 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10193 | | { 5604 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasDSP }, |
10194 | | { 5604 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10195 | | { 5604 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 }, |
10196 | | { 5604 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
10197 | | { 5604 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips }, |
10198 | | { 5604 /* lw */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips }, |
10199 | | { 5604 /* lw */, 2 /* 1 */, MCK_MicroMipsMemGP, AMFBS_InMicroMips }, |
10200 | | { 5607 /* lw16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips }, |
10201 | | { 5607 /* lw16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips }, |
10202 | | { 5612 /* lwc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
10203 | | { 5612 /* lwc1 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
10204 | | { 5612 /* lwc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
10205 | | { 5612 /* lwc1 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips_IsNotSoftFloat }, |
10206 | | { 5617 /* lwc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
10207 | | { 5617 /* lwc2 */, 2 /* 1 */, MCK_MemOffsetSimm11, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
10208 | | { 5617 /* lwc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10209 | | { 5617 /* lwc2 */, 2 /* 1 */, MCK_MemOffsetSimm11, AMFBS_InMicroMips_HasMips32r6 }, |
10210 | | { 5617 /* lwc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10211 | | { 5617 /* lwc2 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10212 | | { 5622 /* lwc3 */, 1 /* 0 */, MCK_COP3AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips }, |
10213 | | { 5622 /* lwc3 */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips }, |
10214 | | { 5627 /* lwe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
10215 | | { 5627 /* lwe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
10216 | | { 5627 /* lwe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, |
10217 | | { 5627 /* lwe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA }, |
10218 | | { 5631 /* lwl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10219 | | { 5631 /* lwl */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10220 | | { 5631 /* lwl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10221 | | { 5631 /* lwl */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 }, |
10222 | | { 5635 /* lwle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips }, |
10223 | | { 5635 /* lwle */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips }, |
10224 | | { 5635 /* lwle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_HasEVA }, |
10225 | | { 5635 /* lwle */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_NotMips32r6_HasEVA }, |
10226 | | { 5640 /* lwm */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips }, |
10227 | | { 5640 /* lwm */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips }, |
10228 | | { 5644 /* lwm16 */, 2 /* 1 */, MCK_MemOffsetUimm4, AMFBS_InMicroMips_NotMips32r6 }, |
10229 | | { 5644 /* lwm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_NotMips32r6 }, |
10230 | | { 5644 /* lwm16 */, 2 /* 1 */, MCK_MemOffsetUimm4, AMFBS_InMicroMips_HasMips32r6 }, |
10231 | | { 5644 /* lwm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_HasMips32r6 }, |
10232 | | { 5650 /* lwm32 */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips }, |
10233 | | { 5650 /* lwm32 */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips }, |
10234 | | { 5656 /* lwp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
10235 | | { 5656 /* lwp */, 2 /* 1 */, MCK_MemOffsetSimm12, AMFBS_InMicroMips }, |
10236 | | { 5660 /* lwpc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
10237 | | { 5660 /* lwpc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10238 | | { 5665 /* lwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10239 | | { 5665 /* lwr */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10240 | | { 5665 /* lwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10241 | | { 5665 /* lwr */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 }, |
10242 | | { 5669 /* lwre */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips }, |
10243 | | { 5669 /* lwre */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips }, |
10244 | | { 5669 /* lwre */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_HasEVA }, |
10245 | | { 5669 /* lwre */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_NotMips32r6_HasEVA }, |
10246 | | { 5674 /* lwu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10247 | | { 5674 /* lwu */, 2 /* 1 */, MCK_MemOffsetSimm12, AMFBS_InMicroMips_NotMips32r6 }, |
10248 | | { 5674 /* lwu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
10249 | | { 5674 /* lwu */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
10250 | | { 5678 /* lwupc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64r6 }, |
10251 | | { 5684 /* lwx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10252 | | { 5684 /* lwx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10253 | | { 5688 /* lwxc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat }, |
10254 | | { 5688 /* lwxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat }, |
10255 | | { 5688 /* lwxc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
10256 | | { 5688 /* lwxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
10257 | | { 5694 /* lwxs */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
10258 | | { 5699 /* madd */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10259 | | { 5699 /* madd */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10260 | | { 5699 /* madd */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
10261 | | { 5699 /* madd */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10262 | | { 5699 /* madd */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
10263 | | { 5699 /* madd */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10264 | | { 5704 /* madd.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 }, |
10265 | | { 5704 /* madd.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4 }, |
10266 | | { 5704 /* madd.d */, 15 /* 0, 1, 2, 3 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 }, |
10267 | | { 5711 /* madd.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 }, |
10268 | | { 5711 /* madd.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4 }, |
10269 | | { 5718 /* madd_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10270 | | { 5727 /* madd_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10271 | | { 5736 /* maddf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
10272 | | { 5736 /* maddf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
10273 | | { 5744 /* maddf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
10274 | | { 5744 /* maddf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
10275 | | { 5752 /* maddr_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10276 | | { 5762 /* maddr_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10277 | | { 5772 /* maddu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10278 | | { 5772 /* maddu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10279 | | { 5772 /* maddu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
10280 | | { 5772 /* maddu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10281 | | { 5772 /* maddu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
10282 | | { 5772 /* maddu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10283 | | { 5778 /* maddv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10284 | | { 5786 /* maddv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10285 | | { 5794 /* maddv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10286 | | { 5802 /* maddv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10287 | | { 5810 /* maq_s.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
10288 | | { 5810 /* maq_s.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10289 | | { 5810 /* maq_s.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
10290 | | { 5810 /* maq_s.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10291 | | { 5822 /* maq_s.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
10292 | | { 5822 /* maq_s.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10293 | | { 5822 /* maq_s.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
10294 | | { 5822 /* maq_s.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10295 | | { 5834 /* maq_sa.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
10296 | | { 5834 /* maq_sa.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10297 | | { 5834 /* maq_sa.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
10298 | | { 5834 /* maq_sa.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10299 | | { 5847 /* maq_sa.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
10300 | | { 5847 /* maq_sa.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10301 | | { 5847 /* maq_sa.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
10302 | | { 5847 /* maq_sa.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10303 | | { 5860 /* max.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
10304 | | { 5860 /* max.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
10305 | | { 5866 /* max.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
10306 | | { 5866 /* max.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
10307 | | { 5872 /* max_a.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10308 | | { 5880 /* max_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10309 | | { 5888 /* max_a.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10310 | | { 5896 /* max_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10311 | | { 5904 /* max_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10312 | | { 5912 /* max_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10313 | | { 5920 /* max_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10314 | | { 5928 /* max_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10315 | | { 5936 /* max_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10316 | | { 5944 /* max_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10317 | | { 5952 /* max_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10318 | | { 5960 /* max_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10319 | | { 5968 /* maxa.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
10320 | | { 5968 /* maxa.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
10321 | | { 5975 /* maxa.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
10322 | | { 5975 /* maxa.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
10323 | | { 5982 /* maxi_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10324 | | { 5991 /* maxi_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10325 | | { 6000 /* maxi_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10326 | | { 6009 /* maxi_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10327 | | { 6018 /* maxi_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10328 | | { 6027 /* maxi_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10329 | | { 6036 /* maxi_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10330 | | { 6045 /* maxi_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10331 | | { 6054 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10332 | | { 6054 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10333 | | { 6054 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10334 | | { 6054 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10335 | | { 6054 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10336 | | { 6054 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10337 | | { 6054 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10338 | | { 6054 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10339 | | { 6059 /* mfc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
10340 | | { 6059 /* mfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
10341 | | { 6059 /* mfc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
10342 | | { 6059 /* mfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
10343 | | { 6059 /* mfc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
10344 | | { 6059 /* mfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
10345 | | { 6059 /* mfc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
10346 | | { 6059 /* mfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
10347 | | { 6064 /* mfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10348 | | { 6064 /* mfc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10349 | | { 6064 /* mfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10350 | | { 6064 /* mfc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10351 | | { 6064 /* mfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10352 | | { 6064 /* mfc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10353 | | { 6069 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
10354 | | { 6069 /* mfgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
10355 | | { 6069 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
10356 | | { 6069 /* mfgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
10357 | | { 6069 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
10358 | | { 6069 /* mfgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
10359 | | { 6069 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
10360 | | { 6069 /* mfgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
10361 | | { 6075 /* mfhc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10362 | | { 6075 /* mfhc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10363 | | { 6075 /* mfhc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10364 | | { 6075 /* mfhc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10365 | | { 6081 /* mfhc1 */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips }, |
10366 | | { 6081 /* mfhc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips }, |
10367 | | { 6081 /* mfhc1 */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
10368 | | { 6081 /* mfhc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
10369 | | { 6081 /* mfhc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips }, |
10370 | | { 6081 /* mfhc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips }, |
10371 | | { 6081 /* mfhc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
10372 | | { 6081 /* mfhc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
10373 | | { 6087 /* mfhc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10374 | | { 6087 /* mfhc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10375 | | { 6093 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
10376 | | { 6093 /* mfhgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
10377 | | { 6093 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
10378 | | { 6093 /* mfhgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
10379 | | { 6093 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
10380 | | { 6093 /* mfhgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
10381 | | { 6093 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
10382 | | { 6093 /* mfhgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
10383 | | { 6100 /* mfhi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10384 | | { 6100 /* mfhi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10385 | | { 6100 /* mfhi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
10386 | | { 6100 /* mfhi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10387 | | { 6100 /* mfhi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
10388 | | { 6100 /* mfhi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10389 | | { 6105 /* mfhi16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10390 | | { 6112 /* mflo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10391 | | { 6112 /* mflo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10392 | | { 6112 /* mflo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
10393 | | { 6112 /* mflo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10394 | | { 6112 /* mflo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
10395 | | { 6112 /* mflo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10396 | | { 6117 /* mflo16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10397 | | { 6124 /* mftacx */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips }, |
10398 | | { 6124 /* mftacx */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT }, |
10399 | | { 6124 /* mftacx */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
10400 | | { 6131 /* mftc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT_NotInMicroMips }, |
10401 | | { 6131 /* mftc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips }, |
10402 | | { 6131 /* mftc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT }, |
10403 | | { 6131 /* mftc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
10404 | | { 6137 /* mftc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT }, |
10405 | | { 6137 /* mftc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
10406 | | { 6143 /* mftdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
10407 | | { 6150 /* mftgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
10408 | | { 6157 /* mfthc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT }, |
10409 | | { 6157 /* mfthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
10410 | | { 6164 /* mfthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips }, |
10411 | | { 6164 /* mfthi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT }, |
10412 | | { 6164 /* mfthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
10413 | | { 6170 /* mftlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips }, |
10414 | | { 6170 /* mftlo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT }, |
10415 | | { 6170 /* mftlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
10416 | | { 6176 /* mftr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips }, |
10417 | | { 6181 /* min.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
10418 | | { 6181 /* min.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
10419 | | { 6187 /* min.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
10420 | | { 6187 /* min.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
10421 | | { 6193 /* min_a.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10422 | | { 6201 /* min_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10423 | | { 6209 /* min_a.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10424 | | { 6217 /* min_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10425 | | { 6225 /* min_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10426 | | { 6233 /* min_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10427 | | { 6241 /* min_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10428 | | { 6249 /* min_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10429 | | { 6257 /* min_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10430 | | { 6265 /* min_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10431 | | { 6273 /* min_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10432 | | { 6281 /* min_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10433 | | { 6289 /* mina.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
10434 | | { 6289 /* mina.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
10435 | | { 6296 /* mina.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
10436 | | { 6296 /* mina.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
10437 | | { 6303 /* mini_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10438 | | { 6312 /* mini_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10439 | | { 6321 /* mini_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10440 | | { 6330 /* mini_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10441 | | { 6339 /* mini_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10442 | | { 6348 /* mini_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10443 | | { 6357 /* mini_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10444 | | { 6366 /* mini_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10445 | | { 6375 /* mod */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
10446 | | { 6375 /* mod */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10447 | | { 6379 /* mod_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10448 | | { 6387 /* mod_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10449 | | { 6395 /* mod_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10450 | | { 6403 /* mod_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10451 | | { 6411 /* mod_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10452 | | { 6419 /* mod_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10453 | | { 6427 /* mod_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10454 | | { 6435 /* mod_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10455 | | { 6443 /* modsub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10456 | | { 6443 /* modsub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10457 | | { 6450 /* modu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
10458 | | { 6450 /* modu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10459 | | { 6455 /* mov.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
10460 | | { 6455 /* mov.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
10461 | | { 6455 /* mov.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
10462 | | { 6455 /* mov.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
10463 | | { 6455 /* mov.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
10464 | | { 6461 /* mov.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
10465 | | { 6461 /* mov.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
10466 | | { 6461 /* mov.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
10467 | | { 6467 /* move */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, |
10468 | | { 6467 /* move */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, |
10469 | | { 6467 /* move */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10470 | | { 6467 /* move */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit_NotInMicroMips }, |
10471 | | { 6467 /* move */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit_NotInMicroMips }, |
10472 | | { 6472 /* move.v */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10473 | | { 6479 /* move16 */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10474 | | { 6486 /* movep */, 12 /* 2, 3 */, MCK_GPRMM16AsmRegMoveP, AMFBS_InMicroMips_NotMips32r6 }, |
10475 | | { 6486 /* movep */, 1 /* 0 */, MCK_GPRMM16AsmRegMovePPairFirst, AMFBS_InMicroMips_NotMips32r6 }, |
10476 | | { 6486 /* movep */, 2 /* 1 */, MCK_GPRMM16AsmRegMovePPairSecond, AMFBS_InMicroMips_NotMips32r6 }, |
10477 | | { 6486 /* movep */, 12 /* 2, 3 */, MCK_GPRMM16AsmRegMoveP, AMFBS_InMicroMips_HasMips32r6 }, |
10478 | | { 6486 /* movep */, 1 /* 0 */, MCK_GPRMM16AsmRegMovePPairFirst, AMFBS_InMicroMips_HasMips32r6 }, |
10479 | | { 6486 /* movep */, 2 /* 1 */, MCK_GPRMM16AsmRegMovePPairSecond, AMFBS_InMicroMips_HasMips32r6 }, |
10480 | | { 6492 /* movf */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10481 | | { 6492 /* movf */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10482 | | { 6492 /* movf */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
10483 | | { 6492 /* movf */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
10484 | | { 6497 /* movf.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10485 | | { 6497 /* movf.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10486 | | { 6497 /* movf.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
10487 | | { 6497 /* movf.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
10488 | | { 6497 /* movf.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10489 | | { 6497 /* movf.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10490 | | { 6504 /* movf.s */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10491 | | { 6504 /* movf.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10492 | | { 6504 /* movf.s */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
10493 | | { 6504 /* movf.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
10494 | | { 6511 /* movn */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10495 | | { 6511 /* movn */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10496 | | { 6516 /* movn.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10497 | | { 6516 /* movn.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10498 | | { 6516 /* movn.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
10499 | | { 6516 /* movn.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
10500 | | { 6516 /* movn.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10501 | | { 6516 /* movn.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10502 | | { 6523 /* movn.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10503 | | { 6523 /* movn.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10504 | | { 6523 /* movn.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
10505 | | { 6523 /* movn.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
10506 | | { 6530 /* movt */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10507 | | { 6530 /* movt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10508 | | { 6530 /* movt */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
10509 | | { 6530 /* movt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
10510 | | { 6535 /* movt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10511 | | { 6535 /* movt.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10512 | | { 6535 /* movt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
10513 | | { 6535 /* movt.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
10514 | | { 6535 /* movt.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10515 | | { 6535 /* movt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10516 | | { 6542 /* movt.s */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10517 | | { 6542 /* movt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10518 | | { 6542 /* movt.s */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
10519 | | { 6542 /* movt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
10520 | | { 6549 /* movz */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10521 | | { 6549 /* movz */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10522 | | { 6554 /* movz.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10523 | | { 6554 /* movz.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10524 | | { 6554 /* movz.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
10525 | | { 6554 /* movz.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
10526 | | { 6554 /* movz.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10527 | | { 6554 /* movz.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10528 | | { 6561 /* movz.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10529 | | { 6561 /* movz.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10530 | | { 6561 /* movz.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
10531 | | { 6561 /* movz.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
10532 | | { 6568 /* msub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10533 | | { 6568 /* msub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10534 | | { 6568 /* msub */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
10535 | | { 6568 /* msub */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10536 | | { 6568 /* msub */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
10537 | | { 6568 /* msub */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10538 | | { 6573 /* msub.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 }, |
10539 | | { 6573 /* msub.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4 }, |
10540 | | { 6573 /* msub.d */, 15 /* 0, 1, 2, 3 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 }, |
10541 | | { 6580 /* msub.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 }, |
10542 | | { 6580 /* msub.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4 }, |
10543 | | { 6587 /* msub_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10544 | | { 6596 /* msub_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10545 | | { 6605 /* msubf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
10546 | | { 6605 /* msubf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
10547 | | { 6613 /* msubf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
10548 | | { 6613 /* msubf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
10549 | | { 6621 /* msubr_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10550 | | { 6631 /* msubr_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10551 | | { 6641 /* msubu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10552 | | { 6641 /* msubu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10553 | | { 6641 /* msubu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
10554 | | { 6641 /* msubu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10555 | | { 6641 /* msubu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
10556 | | { 6641 /* msubu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10557 | | { 6647 /* msubv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10558 | | { 6655 /* msubv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10559 | | { 6663 /* msubv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10560 | | { 6671 /* msubv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10561 | | { 6679 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10562 | | { 6679 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10563 | | { 6679 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10564 | | { 6679 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10565 | | { 6679 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10566 | | { 6679 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10567 | | { 6679 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10568 | | { 6679 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10569 | | { 6684 /* mtc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
10570 | | { 6684 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
10571 | | { 6684 /* mtc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
10572 | | { 6684 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
10573 | | { 6684 /* mtc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
10574 | | { 6684 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
10575 | | { 6684 /* mtc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
10576 | | { 6684 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
10577 | | { 6684 /* mtc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
10578 | | { 6684 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
10579 | | { 6689 /* mtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10580 | | { 6689 /* mtc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10581 | | { 6689 /* mtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10582 | | { 6689 /* mtc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10583 | | { 6689 /* mtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10584 | | { 6689 /* mtc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10585 | | { 6694 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
10586 | | { 6694 /* mtgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
10587 | | { 6694 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
10588 | | { 6694 /* mtgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
10589 | | { 6694 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
10590 | | { 6694 /* mtgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
10591 | | { 6694 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
10592 | | { 6694 /* mtgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
10593 | | { 6700 /* mthc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10594 | | { 6700 /* mthc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10595 | | { 6700 /* mthc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10596 | | { 6700 /* mthc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10597 | | { 6706 /* mthc1 */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips }, |
10598 | | { 6706 /* mthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips }, |
10599 | | { 6706 /* mthc1 */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
10600 | | { 6706 /* mthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
10601 | | { 6706 /* mthc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips }, |
10602 | | { 6706 /* mthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips }, |
10603 | | { 6706 /* mthc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
10604 | | { 6706 /* mthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
10605 | | { 6712 /* mthc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10606 | | { 6712 /* mthc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10607 | | { 6718 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
10608 | | { 6718 /* mthgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
10609 | | { 6718 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
10610 | | { 6718 /* mthgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
10611 | | { 6718 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
10612 | | { 6718 /* mthgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
10613 | | { 6718 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
10614 | | { 6718 /* mthgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
10615 | | { 6725 /* mthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10616 | | { 6725 /* mthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10617 | | { 6725 /* mthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10618 | | { 6725 /* mthi */, 2 /* 1 */, MCK_HI32DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
10619 | | { 6725 /* mthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10620 | | { 6725 /* mthi */, 2 /* 1 */, MCK_HI32DSPAsmReg, AMFBS_HasDSP }, |
10621 | | { 6730 /* mthlip */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
10622 | | { 6730 /* mthlip */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10623 | | { 6730 /* mthlip */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
10624 | | { 6730 /* mthlip */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10625 | | { 6737 /* mtlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10626 | | { 6737 /* mtlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10627 | | { 6737 /* mtlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10628 | | { 6737 /* mtlo */, 2 /* 1 */, MCK_LO32DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
10629 | | { 6737 /* mtlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10630 | | { 6737 /* mtlo */, 2 /* 1 */, MCK_LO32DSPAsmReg, AMFBS_HasDSP }, |
10631 | | { 6742 /* mtm0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
10632 | | { 6747 /* mtm1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
10633 | | { 6752 /* mtm2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
10634 | | { 6757 /* mtp0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
10635 | | { 6762 /* mtp1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
10636 | | { 6767 /* mtp2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
10637 | | { 6772 /* mttacx */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips }, |
10638 | | { 6772 /* mttacx */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT }, |
10639 | | { 6772 /* mttacx */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
10640 | | { 6779 /* mttc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT_NotInMicroMips }, |
10641 | | { 6779 /* mttc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips }, |
10642 | | { 6779 /* mttc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT }, |
10643 | | { 6779 /* mttc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
10644 | | { 6785 /* mttc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT }, |
10645 | | { 6785 /* mttc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
10646 | | { 6791 /* mttdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
10647 | | { 6798 /* mttgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
10648 | | { 6805 /* mtthc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT }, |
10649 | | { 6805 /* mtthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
10650 | | { 6812 /* mtthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips }, |
10651 | | { 6812 /* mtthi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT }, |
10652 | | { 6812 /* mtthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
10653 | | { 6818 /* mttlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips }, |
10654 | | { 6818 /* mttlo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT }, |
10655 | | { 6818 /* mttlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
10656 | | { 6824 /* mttr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips }, |
10657 | | { 6829 /* muh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10658 | | { 6829 /* muh */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
10659 | | { 6829 /* muh */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10660 | | { 6833 /* muhu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10661 | | { 6833 /* muhu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
10662 | | { 6833 /* muhu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10663 | | { 6838 /* mul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10664 | | { 6838 /* mul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10665 | | { 6838 /* mul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10666 | | { 6838 /* mul */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10667 | | { 6838 /* mul */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
10668 | | { 6838 /* mul */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10669 | | { 6838 /* mul */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10670 | | { 6838 /* mul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
10671 | | { 6842 /* mul.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
10672 | | { 6842 /* mul.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
10673 | | { 6842 /* mul.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
10674 | | { 6842 /* mul.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
10675 | | { 6848 /* mul.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
10676 | | { 6848 /* mul.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
10677 | | { 6855 /* mul.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
10678 | | { 6855 /* mul.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
10679 | | { 6855 /* mul.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
10680 | | { 6861 /* mul_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10681 | | { 6869 /* mul_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10682 | | { 6877 /* mul_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
10683 | | { 6877 /* mul_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
10684 | | { 6886 /* muleq_s.w.phl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10685 | | { 6886 /* muleq_s.w.phl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10686 | | { 6900 /* muleq_s.w.phr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10687 | | { 6900 /* muleq_s.w.phr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10688 | | { 6914 /* muleu_s.ph.qbl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10689 | | { 6914 /* muleu_s.ph.qbl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10690 | | { 6929 /* muleu_s.ph.qbr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10691 | | { 6929 /* muleu_s.ph.qbr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10692 | | { 6944 /* mulo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
10693 | | { 6944 /* mulo */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
10694 | | { 6949 /* mulou */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
10695 | | { 6949 /* mulou */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
10696 | | { 6955 /* mulq_rs.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10697 | | { 6955 /* mulq_rs.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10698 | | { 6966 /* mulq_rs.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
10699 | | { 6966 /* mulq_rs.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
10700 | | { 6976 /* mulq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
10701 | | { 6976 /* mulq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
10702 | | { 6986 /* mulq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
10703 | | { 6986 /* mulq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
10704 | | { 6995 /* mulr_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10705 | | { 7004 /* mulr_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10706 | | { 7013 /* mulsa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
10707 | | { 7013 /* mulsa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
10708 | | { 7013 /* mulsa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 }, |
10709 | | { 7013 /* mulsa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
10710 | | { 7024 /* mulsaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
10711 | | { 7024 /* mulsaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10712 | | { 7024 /* mulsaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
10713 | | { 7024 /* mulsaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10714 | | { 7038 /* mult */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10715 | | { 7038 /* mult */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10716 | | { 7038 /* mult */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
10717 | | { 7038 /* mult */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10718 | | { 7038 /* mult */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
10719 | | { 7038 /* mult */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10720 | | { 7043 /* multu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10721 | | { 7043 /* multu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10722 | | { 7043 /* multu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
10723 | | { 7043 /* multu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10724 | | { 7043 /* multu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
10725 | | { 7043 /* multu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10726 | | { 7049 /* mulu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10727 | | { 7049 /* mulu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
10728 | | { 7049 /* mulu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10729 | | { 7054 /* mulv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10730 | | { 7061 /* mulv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10731 | | { 7068 /* mulv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10732 | | { 7075 /* mulv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10733 | | { 7082 /* neg */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10734 | | { 7082 /* neg */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10735 | | { 7082 /* neg */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10736 | | { 7082 /* neg */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10737 | | { 7082 /* neg */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10738 | | { 7082 /* neg */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10739 | | { 7086 /* neg.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
10740 | | { 7086 /* neg.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
10741 | | { 7086 /* neg.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
10742 | | { 7086 /* neg.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
10743 | | { 7092 /* neg.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
10744 | | { 7092 /* neg.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat }, |
10745 | | { 7092 /* neg.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
10746 | | { 7098 /* negu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10747 | | { 7098 /* negu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10748 | | { 7098 /* negu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10749 | | { 7098 /* negu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10750 | | { 7098 /* negu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10751 | | { 7098 /* negu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10752 | | { 7103 /* nloc.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10753 | | { 7110 /* nloc.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10754 | | { 7117 /* nloc.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10755 | | { 7124 /* nloc.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10756 | | { 7131 /* nlzc.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10757 | | { 7138 /* nlzc.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10758 | | { 7145 /* nlzc.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10759 | | { 7152 /* nlzc.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10760 | | { 7159 /* nmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips }, |
10761 | | { 7159 /* nmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4 }, |
10762 | | { 7159 /* nmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips }, |
10763 | | { 7167 /* nmadd.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips }, |
10764 | | { 7167 /* nmadd.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4 }, |
10765 | | { 7175 /* nmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips }, |
10766 | | { 7175 /* nmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4 }, |
10767 | | { 7175 /* nmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips }, |
10768 | | { 7183 /* nmsub.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips }, |
10769 | | { 7183 /* nmsub.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4 }, |
10770 | | { 7195 /* nor */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit }, |
10771 | | { 7195 /* nor */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
10772 | | { 7195 /* nor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10773 | | { 7195 /* nor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10774 | | { 7195 /* nor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10775 | | { 7195 /* nor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit }, |
10776 | | { 7195 /* nor */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
10777 | | { 7199 /* nor.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10778 | | { 7205 /* nori.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10779 | | { 7212 /* not */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10780 | | { 7212 /* not */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10781 | | { 7212 /* not */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10782 | | { 7212 /* not */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10783 | | { 7212 /* not */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10784 | | { 7212 /* not */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10785 | | { 7216 /* not16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10786 | | { 7216 /* not16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10787 | | { 7222 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10788 | | { 7222 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10789 | | { 7222 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10790 | | { 7222 /* or */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10791 | | { 7222 /* or */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, |
10792 | | { 7222 /* or */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
10793 | | { 7222 /* or */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips }, |
10794 | | { 7222 /* or */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10795 | | { 7222 /* or */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10796 | | { 7222 /* or */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10797 | | { 7222 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10798 | | { 7222 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, |
10799 | | { 7222 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
10800 | | { 7222 /* or */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips }, |
10801 | | { 7225 /* or.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10802 | | { 7230 /* or16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10803 | | { 7230 /* or16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10804 | | { 7235 /* ori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10805 | | { 7235 /* ori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10806 | | { 7235 /* ori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10807 | | { 7235 /* ori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10808 | | { 7235 /* ori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10809 | | { 7235 /* ori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10810 | | { 7239 /* ori.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10811 | | { 7245 /* packrl.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10812 | | { 7245 /* packrl.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10813 | | { 7261 /* pckev.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10814 | | { 7269 /* pckev.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10815 | | { 7277 /* pckev.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10816 | | { 7285 /* pckev.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10817 | | { 7293 /* pckod.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10818 | | { 7301 /* pckod.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10819 | | { 7309 /* pckod.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10820 | | { 7317 /* pckod.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10821 | | { 7325 /* pcnt.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10822 | | { 7332 /* pcnt.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10823 | | { 7339 /* pcnt.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10824 | | { 7346 /* pcnt.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10825 | | { 7353 /* pick.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10826 | | { 7353 /* pick.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10827 | | { 7361 /* pick.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10828 | | { 7361 /* pick.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10829 | | { 7369 /* pll.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10830 | | { 7376 /* plu.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
10831 | | { 7383 /* pop */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasCnMips }, |
10832 | | { 7383 /* pop */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasCnMips }, |
10833 | | { 7387 /* preceq.w.phl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10834 | | { 7387 /* preceq.w.phl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10835 | | { 7400 /* preceq.w.phr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10836 | | { 7400 /* preceq.w.phr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10837 | | { 7413 /* precequ.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10838 | | { 7413 /* precequ.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10839 | | { 7428 /* precequ.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10840 | | { 7428 /* precequ.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10841 | | { 7444 /* precequ.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10842 | | { 7444 /* precequ.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10843 | | { 7459 /* precequ.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10844 | | { 7459 /* precequ.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10845 | | { 7475 /* preceu.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10846 | | { 7475 /* preceu.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10847 | | { 7489 /* preceu.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10848 | | { 7489 /* preceu.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10849 | | { 7504 /* preceu.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10850 | | { 7504 /* preceu.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10851 | | { 7518 /* preceu.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10852 | | { 7518 /* preceu.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10853 | | { 7533 /* precr.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
10854 | | { 7533 /* precr.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
10855 | | { 7545 /* precr_sra.ph.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
10856 | | { 7545 /* precr_sra.ph.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
10857 | | { 7560 /* precr_sra_r.ph.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
10858 | | { 7560 /* precr_sra_r.ph.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
10859 | | { 7577 /* precrq.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10860 | | { 7577 /* precrq.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10861 | | { 7589 /* precrq.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10862 | | { 7589 /* precrq.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10863 | | { 7602 /* precrq_rs.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10864 | | { 7602 /* precrq_rs.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10865 | | { 7617 /* precrqu_s.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10866 | | { 7617 /* precrqu_s.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10867 | | { 7633 /* pref */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
10868 | | { 7633 /* pref */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10869 | | { 7633 /* pref */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 }, |
10870 | | { 7633 /* pref */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 }, |
10871 | | { 7638 /* prefe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
10872 | | { 7638 /* prefe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA }, |
10873 | | { 7644 /* prefx */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10874 | | { 7650 /* prepend */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
10875 | | { 7650 /* prepend */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
10876 | | { 7658 /* raddu.w.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10877 | | { 7658 /* raddu.w.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10878 | | { 7669 /* rddsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10879 | | { 7669 /* rddsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10880 | | { 7675 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10881 | | { 7675 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10882 | | { 7675 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10883 | | { 7675 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10884 | | { 7675 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10885 | | { 7675 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10886 | | { 7675 /* rdhwr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
10887 | | { 7675 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_IsGP64bit }, |
10888 | | { 7675 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10889 | | { 7675 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10890 | | { 7675 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10891 | | { 7675 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10892 | | { 7675 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10893 | | { 7675 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
10894 | | { 7681 /* rdpgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10895 | | { 7688 /* recip.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips }, |
10896 | | { 7688 /* recip.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
10897 | | { 7688 /* recip.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips }, |
10898 | | { 7688 /* recip.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
10899 | | { 7696 /* recip.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips }, |
10900 | | { 7696 /* recip.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
10901 | | { 7704 /* rem */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
10902 | | { 7704 /* rem */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
10903 | | { 7704 /* rem */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
10904 | | { 7704 /* rem */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
10905 | | { 7708 /* remu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
10906 | | { 7708 /* remu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
10907 | | { 7708 /* remu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
10908 | | { 7708 /* remu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
10909 | | { 7713 /* repl.ph */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10910 | | { 7713 /* repl.ph */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10911 | | { 7721 /* repl.qb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10912 | | { 7721 /* repl.qb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10913 | | { 7729 /* replv.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10914 | | { 7729 /* replv.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10915 | | { 7738 /* replv.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
10916 | | { 7738 /* replv.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
10917 | | { 7747 /* rint.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
10918 | | { 7747 /* rint.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10919 | | { 7754 /* rint.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
10920 | | { 7754 /* rint.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10921 | | { 7761 /* rol */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
10922 | | { 7761 /* rol */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
10923 | | { 7761 /* rol */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_None }, |
10924 | | { 7761 /* rol */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
10925 | | { 7765 /* ror */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
10926 | | { 7765 /* ror */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
10927 | | { 7765 /* ror */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_None }, |
10928 | | { 7765 /* ror */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
10929 | | { 7769 /* rotr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, |
10930 | | { 7769 /* rotr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
10931 | | { 7769 /* rotr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
10932 | | { 7769 /* rotr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, |
10933 | | { 7769 /* rotr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
10934 | | { 7774 /* rotrv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, |
10935 | | { 7774 /* rotrv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
10936 | | { 7780 /* round.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips }, |
10937 | | { 7780 /* round.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
10938 | | { 7790 /* round.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
10939 | | { 7790 /* round.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
10940 | | { 7790 /* round.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
10941 | | { 7790 /* round.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
10942 | | { 7800 /* round.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
10943 | | { 7800 /* round.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
10944 | | { 7800 /* round.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
10945 | | { 7800 /* round.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
10946 | | { 7800 /* round.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
10947 | | { 7800 /* round.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
10948 | | { 7800 /* round.w.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
10949 | | { 7810 /* round.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
10950 | | { 7810 /* round.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
10951 | | { 7810 /* round.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
10952 | | { 7820 /* rsqrt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips }, |
10953 | | { 7820 /* rsqrt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
10954 | | { 7820 /* rsqrt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips }, |
10955 | | { 7820 /* rsqrt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
10956 | | { 7828 /* rsqrt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips }, |
10957 | | { 7828 /* rsqrt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
10958 | | { 7836 /* s.d */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat }, |
10959 | | { 7836 /* s.d */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat }, |
10960 | | { 7836 /* s.d */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat }, |
10961 | | { 7836 /* s.d */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat }, |
10962 | | { 7836 /* s.d */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat }, |
10963 | | { 7836 /* s.d */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat }, |
10964 | | { 7836 /* s.d */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat }, |
10965 | | { 7836 /* s.d */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat }, |
10966 | | { 7840 /* s.s */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat }, |
10967 | | { 7840 /* s.s */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat }, |
10968 | | { 7844 /* sat_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10969 | | { 7852 /* sat_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10970 | | { 7860 /* sat_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10971 | | { 7868 /* sat_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10972 | | { 7876 /* sat_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10973 | | { 7884 /* sat_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10974 | | { 7892 /* sat_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10975 | | { 7900 /* sat_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
10976 | | { 7908 /* sb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
10977 | | { 7908 /* sb */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotInMicroMips }, |
10978 | | { 7908 /* sb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10979 | | { 7908 /* sb */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 }, |
10980 | | { 7908 /* sb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
10981 | | { 7908 /* sb */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips }, |
10982 | | { 7911 /* sb16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_NotMips32r6 }, |
10983 | | { 7911 /* sb16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_NotMips32r6 }, |
10984 | | { 7911 /* sb16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_HasMips32r6 }, |
10985 | | { 7911 /* sb16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_HasMips32r6 }, |
10986 | | { 7916 /* sbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
10987 | | { 7916 /* sbe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
10988 | | { 7916 /* sbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, |
10989 | | { 7916 /* sbe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA }, |
10990 | | { 7920 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips }, |
10991 | | { 7920 /* sc */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips }, |
10992 | | { 7920 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips }, |
10993 | | { 7920 /* sc */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips }, |
10994 | | { 7920 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
10995 | | { 7920 /* sc */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasMips32r6 }, |
10996 | | { 7920 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10997 | | { 7920 /* sc */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10998 | | { 7920 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
10999 | | { 7920 /* sc */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
11000 | | { 7920 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
11001 | | { 7920 /* sc */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 }, |
11002 | | { 7923 /* scd */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
11003 | | { 7923 /* scd */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r6 }, |
11004 | | { 7923 /* scd */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
11005 | | { 7923 /* scd */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
11006 | | { 7927 /* sce */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
11007 | | { 7927 /* sce */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
11008 | | { 7927 /* sce */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, |
11009 | | { 7927 /* sce */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA }, |
11010 | | { 7931 /* sd */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips3 }, |
11011 | | { 7931 /* sd */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_NotMips3 }, |
11012 | | { 7931 /* sd */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
11013 | | { 7931 /* sd */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
11014 | | { 7948 /* sdc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
11015 | | { 7948 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
11016 | | { 7948 /* sdc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
11017 | | { 7948 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
11018 | | { 7948 /* sdc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
11019 | | { 7948 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
11020 | | { 7948 /* sdc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat }, |
11021 | | { 7948 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat }, |
11022 | | { 7953 /* sdc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
11023 | | { 7953 /* sdc2 */, 2 /* 1 */, MCK_MemOffsetSimm11, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
11024 | | { 7953 /* sdc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11025 | | { 7953 /* sdc2 */, 2 /* 1 */, MCK_MemOffsetSimm11, AMFBS_InMicroMips_HasMips32r6 }, |
11026 | | { 7953 /* sdc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
11027 | | { 7953 /* sdc2 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
11028 | | { 7958 /* sdc3 */, 1 /* 0 */, MCK_COP3AsmReg, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips }, |
11029 | | { 7958 /* sdc3 */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips }, |
11030 | | { 7963 /* sdl */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
11031 | | { 7963 /* sdl */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
11032 | | { 7967 /* sdr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
11033 | | { 7967 /* sdr */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
11034 | | { 7971 /* sdxc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
11035 | | { 7971 /* sdxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
11036 | | { 7971 /* sdxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat }, |
11037 | | { 7971 /* sdxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat }, |
11038 | | { 7977 /* seb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, |
11039 | | { 7977 /* seb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11040 | | { 7977 /* seb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, |
11041 | | { 7977 /* seb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11042 | | { 7981 /* seh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, |
11043 | | { 7981 /* seh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11044 | | { 7981 /* seh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, |
11045 | | { 7981 /* seh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11046 | | { 7985 /* sel.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
11047 | | { 7985 /* sel.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11048 | | { 7991 /* sel.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
11049 | | { 7991 /* sel.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11050 | | { 7997 /* seleqz */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips }, |
11051 | | { 7997 /* seleqz */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11052 | | { 7997 /* seleqz */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips32r6 }, |
11053 | | { 8004 /* seleqz.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
11054 | | { 8004 /* seleqz.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11055 | | { 8013 /* seleqz.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
11056 | | { 8013 /* seleqz.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11057 | | { 8022 /* selnez */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips }, |
11058 | | { 8022 /* selnez */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11059 | | { 8022 /* selnez */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips32r6 }, |
11060 | | { 8029 /* selnez.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
11061 | | { 8029 /* selnez.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11062 | | { 8038 /* selnez.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
11063 | | { 8038 /* selnez.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11064 | | { 8047 /* seq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotCnMips }, |
11065 | | { 8047 /* seq */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotCnMips }, |
11066 | | { 8047 /* seq */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
11067 | | { 8047 /* seq */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotCnMips }, |
11068 | | { 8047 /* seq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotCnMips }, |
11069 | | { 8047 /* seq */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
11070 | | { 8051 /* seqi */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
11071 | | { 8051 /* seqi */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
11072 | | { 8056 /* sge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11073 | | { 8056 /* sge */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, |
11074 | | { 8056 /* sge */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
11075 | | { 8056 /* sge */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11076 | | { 8056 /* sge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, |
11077 | | { 8056 /* sge */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
11078 | | { 8060 /* sgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11079 | | { 8060 /* sgeu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, |
11080 | | { 8060 /* sgeu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
11081 | | { 8060 /* sgeu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11082 | | { 8060 /* sgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, |
11083 | | { 8060 /* sgeu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
11084 | | { 8065 /* sgt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11085 | | { 8065 /* sgt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11086 | | { 8065 /* sgt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, |
11087 | | { 8065 /* sgt */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
11088 | | { 8065 /* sgt */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11089 | | { 8065 /* sgt */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11090 | | { 8065 /* sgt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, |
11091 | | { 8065 /* sgt */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
11092 | | { 8069 /* sgtu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11093 | | { 8069 /* sgtu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11094 | | { 8069 /* sgtu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, |
11095 | | { 8069 /* sgtu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
11096 | | { 8069 /* sgtu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11097 | | { 8069 /* sgtu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11098 | | { 8069 /* sgtu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, |
11099 | | { 8069 /* sgtu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
11100 | | { 8074 /* sh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11101 | | { 8074 /* sh */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotInMicroMips }, |
11102 | | { 8074 /* sh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11103 | | { 8074 /* sh */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 }, |
11104 | | { 8074 /* sh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11105 | | { 8074 /* sh */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips }, |
11106 | | { 8077 /* sh16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_NotMips32r6 }, |
11107 | | { 8077 /* sh16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_NotMips32r6 }, |
11108 | | { 8077 /* sh16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_HasMips32r6 }, |
11109 | | { 8077 /* sh16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_HasMips32r6 }, |
11110 | | { 8082 /* she */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
11111 | | { 8082 /* she */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
11112 | | { 8082 /* she */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, |
11113 | | { 8082 /* she */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA }, |
11114 | | { 8086 /* shf.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11115 | | { 8092 /* shf.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11116 | | { 8098 /* shf.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11117 | | { 8104 /* shilo */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
11118 | | { 8104 /* shilo */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
11119 | | { 8110 /* shilov */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
11120 | | { 8110 /* shilov */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
11121 | | { 8110 /* shilov */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
11122 | | { 8110 /* shilov */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
11123 | | { 8117 /* shll.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
11124 | | { 8117 /* shll.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
11125 | | { 8125 /* shll.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
11126 | | { 8125 /* shll.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
11127 | | { 8133 /* shll_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
11128 | | { 8133 /* shll_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
11129 | | { 8143 /* shll_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
11130 | | { 8143 /* shll_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
11131 | | { 8152 /* shllv.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
11132 | | { 8152 /* shllv.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
11133 | | { 8161 /* shllv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
11134 | | { 8161 /* shllv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
11135 | | { 8170 /* shllv_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
11136 | | { 8170 /* shllv_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
11137 | | { 8181 /* shllv_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
11138 | | { 8181 /* shllv_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
11139 | | { 8191 /* shra.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
11140 | | { 8191 /* shra.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
11141 | | { 8199 /* shra.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
11142 | | { 8199 /* shra.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
11143 | | { 8207 /* shra_r.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
11144 | | { 8207 /* shra_r.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
11145 | | { 8217 /* shra_r.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
11146 | | { 8217 /* shra_r.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
11147 | | { 8227 /* shra_r.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
11148 | | { 8227 /* shra_r.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
11149 | | { 8236 /* shrav.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
11150 | | { 8236 /* shrav.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
11151 | | { 8245 /* shrav.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
11152 | | { 8245 /* shrav.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
11153 | | { 8254 /* shrav_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
11154 | | { 8254 /* shrav_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
11155 | | { 8265 /* shrav_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
11156 | | { 8265 /* shrav_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
11157 | | { 8276 /* shrav_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
11158 | | { 8276 /* shrav_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
11159 | | { 8286 /* shrl.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
11160 | | { 8286 /* shrl.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
11161 | | { 8294 /* shrl.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
11162 | | { 8294 /* shrl.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
11163 | | { 8302 /* shrlv.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
11164 | | { 8302 /* shrlv.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
11165 | | { 8311 /* shrlv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
11166 | | { 8311 /* shrlv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
11167 | | { 8327 /* sld.b */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11168 | | { 8327 /* sld.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11169 | | { 8333 /* sld.d */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11170 | | { 8333 /* sld.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11171 | | { 8339 /* sld.h */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11172 | | { 8339 /* sld.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11173 | | { 8345 /* sld.w */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11174 | | { 8345 /* sld.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11175 | | { 8351 /* sldi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11176 | | { 8358 /* sldi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11177 | | { 8365 /* sldi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11178 | | { 8372 /* sldi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11179 | | { 8379 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips }, |
11180 | | { 8379 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11181 | | { 8379 /* sll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11182 | | { 8379 /* sll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11183 | | { 8379 /* sll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11184 | | { 8379 /* sll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11185 | | { 8379 /* sll */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips }, |
11186 | | { 8379 /* sll */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11187 | | { 8379 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11188 | | { 8379 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11189 | | { 8379 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11190 | | { 8383 /* sll.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11191 | | { 8389 /* sll.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11192 | | { 8395 /* sll.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11193 | | { 8401 /* sll.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11194 | | { 8407 /* sll16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
11195 | | { 8407 /* sll16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11196 | | { 8413 /* slli.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11197 | | { 8420 /* slli.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11198 | | { 8427 /* slli.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11199 | | { 8434 /* slli.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11200 | | { 8441 /* sllv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11201 | | { 8441 /* sllv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11202 | | { 8446 /* slt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, |
11203 | | { 8446 /* slt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11204 | | { 8446 /* slt */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
11205 | | { 8446 /* slt */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11206 | | { 8446 /* slt */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11207 | | { 8446 /* slt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, |
11208 | | { 8446 /* slt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11209 | | { 8446 /* slt */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
11210 | | { 8450 /* slti */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11211 | | { 8450 /* slti */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11212 | | { 8455 /* sltiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11213 | | { 8455 /* sltiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11214 | | { 8461 /* sltu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, |
11215 | | { 8461 /* sltu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11216 | | { 8461 /* sltu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
11217 | | { 8461 /* sltu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11218 | | { 8461 /* sltu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11219 | | { 8461 /* sltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, |
11220 | | { 8461 /* sltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11221 | | { 8461 /* sltu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
11222 | | { 8466 /* sne */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
11223 | | { 8466 /* sne */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
11224 | | { 8470 /* snei */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
11225 | | { 8470 /* snei */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
11226 | | { 8475 /* splat.b */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11227 | | { 8475 /* splat.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11228 | | { 8483 /* splat.d */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11229 | | { 8483 /* splat.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11230 | | { 8491 /* splat.h */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11231 | | { 8491 /* splat.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11232 | | { 8499 /* splat.w */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11233 | | { 8499 /* splat.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11234 | | { 8507 /* splati.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11235 | | { 8516 /* splati.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11236 | | { 8525 /* splati.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11237 | | { 8534 /* splati.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11238 | | { 8543 /* sqrt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
11239 | | { 8543 /* sqrt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
11240 | | { 8543 /* sqrt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
11241 | | { 8543 /* sqrt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
11242 | | { 8550 /* sqrt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
11243 | | { 8550 /* sqrt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
11244 | | { 8557 /* sra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips }, |
11245 | | { 8557 /* sra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11246 | | { 8557 /* sra */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11247 | | { 8557 /* sra */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11248 | | { 8557 /* sra */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11249 | | { 8557 /* sra */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips }, |
11250 | | { 8557 /* sra */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11251 | | { 8557 /* sra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11252 | | { 8557 /* sra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11253 | | { 8561 /* sra.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11254 | | { 8567 /* sra.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11255 | | { 8573 /* sra.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11256 | | { 8579 /* sra.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11257 | | { 8585 /* srai.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11258 | | { 8592 /* srai.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11259 | | { 8599 /* srai.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11260 | | { 8606 /* srai.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11261 | | { 8613 /* srar.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11262 | | { 8620 /* srar.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11263 | | { 8627 /* srar.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11264 | | { 8634 /* srar.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11265 | | { 8641 /* srari.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11266 | | { 8649 /* srari.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11267 | | { 8657 /* srari.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11268 | | { 8665 /* srari.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11269 | | { 8673 /* srav */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11270 | | { 8673 /* srav */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11271 | | { 8678 /* srl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips }, |
11272 | | { 8678 /* srl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11273 | | { 8678 /* srl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11274 | | { 8678 /* srl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11275 | | { 8678 /* srl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11276 | | { 8678 /* srl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips }, |
11277 | | { 8678 /* srl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11278 | | { 8678 /* srl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11279 | | { 8678 /* srl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11280 | | { 8682 /* srl.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11281 | | { 8688 /* srl.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11282 | | { 8694 /* srl.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11283 | | { 8700 /* srl.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11284 | | { 8706 /* srl16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
11285 | | { 8706 /* srl16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11286 | | { 8712 /* srli.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11287 | | { 8719 /* srli.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11288 | | { 8726 /* srli.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11289 | | { 8733 /* srli.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11290 | | { 8740 /* srlr.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11291 | | { 8747 /* srlr.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11292 | | { 8754 /* srlr.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11293 | | { 8761 /* srlr.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11294 | | { 8768 /* srlri.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11295 | | { 8776 /* srlri.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11296 | | { 8784 /* srlri.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11297 | | { 8792 /* srlri.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11298 | | { 8800 /* srlv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11299 | | { 8800 /* srlv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11300 | | { 8811 /* st.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11301 | | { 8811 /* st.b */, 2 /* 1 */, MCK_MemOffsetSimm10, AMFBS_HasStdEnc_HasMSA }, |
11302 | | { 8816 /* st.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11303 | | { 8816 /* st.d */, 2 /* 1 */, MCK_MemOffsetSimm10_3, AMFBS_HasStdEnc_HasMSA }, |
11304 | | { 8821 /* st.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11305 | | { 8821 /* st.h */, 2 /* 1 */, MCK_MemOffsetSimm10_1, AMFBS_HasStdEnc_HasMSA }, |
11306 | | { 8826 /* st.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11307 | | { 8826 /* st.w */, 2 /* 1 */, MCK_MemOffsetSimm10_2, AMFBS_HasStdEnc_HasMSA }, |
11308 | | { 8831 /* sub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11309 | | { 8831 /* sub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
11310 | | { 8831 /* sub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11311 | | { 8831 /* sub */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
11312 | | { 8831 /* sub */, 2 /* 1 */, MCK_InvNum, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
11313 | | { 8831 /* sub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11314 | | { 8831 /* sub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
11315 | | { 8831 /* sub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11316 | | { 8831 /* sub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
11317 | | { 8831 /* sub */, 4 /* 2 */, MCK_InvNum, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
11318 | | { 8835 /* sub.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
11319 | | { 8835 /* sub.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
11320 | | { 8835 /* sub.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
11321 | | { 8835 /* sub.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
11322 | | { 8841 /* sub.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
11323 | | { 8841 /* sub.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
11324 | | { 8841 /* sub.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
11325 | | { 8847 /* subq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
11326 | | { 8847 /* subq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
11327 | | { 8855 /* subq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
11328 | | { 8855 /* subq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
11329 | | { 8865 /* subq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
11330 | | { 8865 /* subq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
11331 | | { 8874 /* subqh.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
11332 | | { 8874 /* subqh.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
11333 | | { 8883 /* subqh.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
11334 | | { 8883 /* subqh.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
11335 | | { 8891 /* subqh_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
11336 | | { 8891 /* subqh_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
11337 | | { 8902 /* subqh_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
11338 | | { 8902 /* subqh_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
11339 | | { 8912 /* subs_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11340 | | { 8921 /* subs_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11341 | | { 8930 /* subs_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11342 | | { 8939 /* subs_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11343 | | { 8948 /* subs_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11344 | | { 8957 /* subs_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11345 | | { 8966 /* subs_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11346 | | { 8975 /* subs_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11347 | | { 8984 /* subsus_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11348 | | { 8995 /* subsus_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11349 | | { 9006 /* subsus_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11350 | | { 9017 /* subsus_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11351 | | { 9028 /* subsuu_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11352 | | { 9039 /* subsuu_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11353 | | { 9050 /* subsuu_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11354 | | { 9061 /* subsuu_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11355 | | { 9072 /* subu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11356 | | { 9072 /* subu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11357 | | { 9072 /* subu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
11358 | | { 9072 /* subu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
11359 | | { 9072 /* subu */, 2 /* 1 */, MCK_InvNum, AMFBS_None }, |
11360 | | { 9072 /* subu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11361 | | { 9072 /* subu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11362 | | { 9072 /* subu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
11363 | | { 9072 /* subu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
11364 | | { 9072 /* subu */, 4 /* 2 */, MCK_InvNum, AMFBS_None }, |
11365 | | { 9077 /* subu.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
11366 | | { 9077 /* subu.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
11367 | | { 9085 /* subu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
11368 | | { 9085 /* subu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
11369 | | { 9093 /* subu16 */, 7 /* 0, 1, 2 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
11370 | | { 9093 /* subu16 */, 7 /* 0, 1, 2 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11371 | | { 9100 /* subu_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
11372 | | { 9100 /* subu_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
11373 | | { 9110 /* subu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
11374 | | { 9110 /* subu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
11375 | | { 9120 /* subuh.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
11376 | | { 9120 /* subuh.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
11377 | | { 9129 /* subuh_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
11378 | | { 9129 /* subuh_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
11379 | | { 9140 /* subv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11380 | | { 9147 /* subv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11381 | | { 9154 /* subv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11382 | | { 9161 /* subv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11383 | | { 9168 /* subvi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11384 | | { 9176 /* subvi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11385 | | { 9184 /* subvi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11386 | | { 9192 /* subvi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11387 | | { 9200 /* suxc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
11388 | | { 9200 /* suxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
11389 | | { 9200 /* suxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
11390 | | { 9200 /* suxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
11391 | | { 9200 /* suxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
11392 | | { 9200 /* suxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
11393 | | { 9206 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11394 | | { 9206 /* sw */, 2 /* 1 */, MCK_MicroMipsMemSP, AMFBS_InMicroMips_HasMips32r6 }, |
11395 | | { 9206 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11396 | | { 9206 /* sw */, 2 /* 1 */, MCK_MicroMipsMemSP, AMFBS_InMicroMips }, |
11397 | | { 9206 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11398 | | { 9206 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotInMicroMips }, |
11399 | | { 9206 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotInMips16Mode_HasDSP }, |
11400 | | { 9206 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_NotInMips16Mode_HasDSP }, |
11401 | | { 9206 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
11402 | | { 9206 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasDSP }, |
11403 | | { 9206 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11404 | | { 9206 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 }, |
11405 | | { 9206 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11406 | | { 9206 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips }, |
11407 | | { 9209 /* sw16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_NotMips32r6 }, |
11408 | | { 9209 /* sw16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_NotMips32r6 }, |
11409 | | { 9209 /* sw16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_HasMips32r6 }, |
11410 | | { 9209 /* sw16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_HasMips32r6 }, |
11411 | | { 9214 /* swc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
11412 | | { 9214 /* swc1 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
11413 | | { 9214 /* swc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
11414 | | { 9214 /* swc1 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips_IsNotSoftFloat }, |
11415 | | { 9219 /* swc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
11416 | | { 9219 /* swc2 */, 2 /* 1 */, MCK_MemOffsetSimm11, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
11417 | | { 9219 /* swc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11418 | | { 9219 /* swc2 */, 2 /* 1 */, MCK_MemOffsetSimm11, AMFBS_InMicroMips_HasMips32r6 }, |
11419 | | { 9219 /* swc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
11420 | | { 9219 /* swc2 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
11421 | | { 9224 /* swc3 */, 1 /* 0 */, MCK_COP3AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips }, |
11422 | | { 9224 /* swc3 */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips }, |
11423 | | { 9229 /* swe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
11424 | | { 9229 /* swe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
11425 | | { 9229 /* swe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, |
11426 | | { 9229 /* swe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA }, |
11427 | | { 9233 /* swl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
11428 | | { 9233 /* swl */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
11429 | | { 9233 /* swl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
11430 | | { 9233 /* swl */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 }, |
11431 | | { 9237 /* swle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips }, |
11432 | | { 9237 /* swle */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips }, |
11433 | | { 9237 /* swle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_HasEVA }, |
11434 | | { 9237 /* swle */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_NotMips32r6_HasEVA }, |
11435 | | { 9242 /* swm */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips }, |
11436 | | { 9242 /* swm */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips }, |
11437 | | { 9246 /* swm16 */, 2 /* 1 */, MCK_MemOffsetUimm4, AMFBS_InMicroMips_NotMips32r6 }, |
11438 | | { 9246 /* swm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_NotMips32r6 }, |
11439 | | { 9246 /* swm16 */, 2 /* 1 */, MCK_MemOffsetUimm4, AMFBS_InMicroMips_HasMips32r6 }, |
11440 | | { 9246 /* swm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_HasMips32r6 }, |
11441 | | { 9252 /* swm32 */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips }, |
11442 | | { 9252 /* swm32 */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips }, |
11443 | | { 9258 /* swp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11444 | | { 9258 /* swp */, 2 /* 1 */, MCK_MemOffsetSimm12, AMFBS_InMicroMips }, |
11445 | | { 9262 /* swr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
11446 | | { 9262 /* swr */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
11447 | | { 9262 /* swr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
11448 | | { 9262 /* swr */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 }, |
11449 | | { 9266 /* swre */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips }, |
11450 | | { 9266 /* swre */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips }, |
11451 | | { 9266 /* swre */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_HasEVA }, |
11452 | | { 9266 /* swre */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_NotMips32r6_HasEVA }, |
11453 | | { 9271 /* swsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
11454 | | { 9271 /* swsp */, 2 /* 1 */, MCK_MicroMipsMemSP, AMFBS_InMicroMips_NotMips32r6 }, |
11455 | | { 9276 /* swxc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat }, |
11456 | | { 9276 /* swxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat }, |
11457 | | { 9276 /* swxc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
11458 | | { 9276 /* swxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
11459 | | { 9287 /* synci */, 1 /* 0 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, |
11460 | | { 9287 /* synci */, 1 /* 0 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips_NotMips32r6 }, |
11461 | | { 9287 /* synci */, 1 /* 0 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips_HasMips32r6 }, |
11462 | | { 9331 /* teq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
11463 | | { 9331 /* teq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11464 | | { 9331 /* teq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11465 | | { 9331 /* teq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
11466 | | { 9335 /* teqi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
11467 | | { 9335 /* teqi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
11468 | | { 9340 /* tge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
11469 | | { 9340 /* tge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11470 | | { 9340 /* tge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11471 | | { 9340 /* tge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
11472 | | { 9344 /* tgei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
11473 | | { 9344 /* tgei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
11474 | | { 9349 /* tgeiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
11475 | | { 9349 /* tgeiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
11476 | | { 9355 /* tgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
11477 | | { 9355 /* tgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11478 | | { 9355 /* tgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11479 | | { 9355 /* tgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
11480 | | { 9440 /* tlt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
11481 | | { 9440 /* tlt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11482 | | { 9440 /* tlt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11483 | | { 9440 /* tlt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
11484 | | { 9444 /* tlti */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
11485 | | { 9444 /* tlti */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
11486 | | { 9449 /* tltiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
11487 | | { 9449 /* tltiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
11488 | | { 9455 /* tltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
11489 | | { 9455 /* tltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11490 | | { 9455 /* tltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11491 | | { 9455 /* tltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
11492 | | { 9460 /* tne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
11493 | | { 9460 /* tne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11494 | | { 9460 /* tne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11495 | | { 9460 /* tne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
11496 | | { 9464 /* tnei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
11497 | | { 9464 /* tnei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
11498 | | { 9469 /* trunc.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips }, |
11499 | | { 9469 /* trunc.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
11500 | | { 9479 /* trunc.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
11501 | | { 9479 /* trunc.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
11502 | | { 9479 /* trunc.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
11503 | | { 9479 /* trunc.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
11504 | | { 9489 /* trunc.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
11505 | | { 9489 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
11506 | | { 9489 /* trunc.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
11507 | | { 9489 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
11508 | | { 9489 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
11509 | | { 9489 /* trunc.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
11510 | | { 9489 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
11511 | | { 9489 /* trunc.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
11512 | | { 9489 /* trunc.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_NotFP64bit_IsNotSoftFloat }, |
11513 | | { 9489 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_NotFP64bit_IsNotSoftFloat }, |
11514 | | { 9489 /* trunc.w.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_NotFP64bit_IsNotSoftFloat }, |
11515 | | { 9489 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_IsFP64bit_IsNotSoftFloat }, |
11516 | | { 9489 /* trunc.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_IsFP64bit_IsNotSoftFloat }, |
11517 | | { 9489 /* trunc.w.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_IsFP64bit_IsNotSoftFloat }, |
11518 | | { 9499 /* trunc.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
11519 | | { 9499 /* trunc.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
11520 | | { 9499 /* trunc.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
11521 | | { 9499 /* trunc.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_None }, |
11522 | | { 9499 /* trunc.w.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_None }, |
11523 | | { 9509 /* ulh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
11524 | | { 9509 /* ulh */, 2 /* 1 */, MCK_Mem, AMFBS_None }, |
11525 | | { 9513 /* ulhu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
11526 | | { 9513 /* ulhu */, 2 /* 1 */, MCK_Mem, AMFBS_None }, |
11527 | | { 9518 /* ulw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
11528 | | { 9518 /* ulw */, 2 /* 1 */, MCK_Mem, AMFBS_None }, |
11529 | | { 9522 /* ush */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
11530 | | { 9522 /* ush */, 2 /* 1 */, MCK_Mem, AMFBS_None }, |
11531 | | { 9526 /* usw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
11532 | | { 9526 /* usw */, 2 /* 1 */, MCK_Mem, AMFBS_None }, |
11533 | | { 9530 /* v3mulu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
11534 | | { 9530 /* v3mulu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
11535 | | { 9537 /* vmm0 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
11536 | | { 9537 /* vmm0 */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
11537 | | { 9542 /* vmulu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
11538 | | { 9542 /* vmulu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
11539 | | { 9548 /* vshf.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11540 | | { 9555 /* vshf.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11541 | | { 9562 /* vshf.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11542 | | { 9569 /* vshf.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11543 | | { 9581 /* wrdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP_NotInMicroMips }, |
11544 | | { 9581 /* wrdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP_InMicroMips }, |
11545 | | { 9581 /* wrdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
11546 | | { 9581 /* wrdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP_NotInMicroMips }, |
11547 | | { 9587 /* wrpgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11548 | | { 9594 /* wsbh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, |
11549 | | { 9594 /* wsbh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11550 | | { 9594 /* wsbh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11551 | | { 9599 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11552 | | { 9599 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
11553 | | { 9599 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11554 | | { 9599 /* xor */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11555 | | { 9599 /* xor */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, |
11556 | | { 9599 /* xor */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11557 | | { 9599 /* xor */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips }, |
11558 | | { 9599 /* xor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11559 | | { 9599 /* xor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
11560 | | { 9599 /* xor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11561 | | { 9599 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11562 | | { 9599 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, |
11563 | | { 9599 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
11564 | | { 9599 /* xor */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips }, |
11565 | | { 9603 /* xor.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11566 | | { 9609 /* xor16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
11567 | | { 9609 /* xor16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11568 | | { 9615 /* xori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11569 | | { 9615 /* xori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11570 | | { 9615 /* xori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
11571 | | { 9615 /* xori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
11572 | | { 9615 /* xori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
11573 | | { 9615 /* xori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
11574 | | { 9620 /* xori.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
11575 | | { 9627 /* yield */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips }, |
11576 | | { 9627 /* yield */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips }, |
11577 | | }; |
11578 | | |
11579 | | OperandMatchResultTy MipsAsmParser:: |
11580 | | tryCustomParseOperand(OperandVector &Operands, |
11581 | 57.2k | unsigned MCK) { |
11582 | 57.2k | |
11583 | 57.2k | switch(MCK) { |
11584 | 57.2k | case MCK_ACC64DSPAsmReg: |
11585 | 192 | return parseAnyRegister(Operands); |
11586 | 57.2k | case MCK_AFGR64AsmReg: |
11587 | 1.06k | return parseAnyRegister(Operands); |
11588 | 57.2k | case MCK_CCRAsmReg: |
11589 | 38 | return parseAnyRegister(Operands); |
11590 | 57.2k | case MCK_COP0AsmReg: |
11591 | 273 | return parseAnyRegister(Operands); |
11592 | 57.2k | case MCK_COP2AsmReg: |
11593 | 242 | return parseAnyRegister(Operands); |
11594 | 57.2k | case MCK_COP3AsmReg: |
11595 | 6 | return parseAnyRegister(Operands); |
11596 | 57.2k | case MCK_FCCAsmReg: |
11597 | 84 | return parseAnyRegister(Operands); |
11598 | 57.2k | case MCK_FGR32AsmReg: |
11599 | 2.88k | return parseAnyRegister(Operands); |
11600 | 57.2k | case MCK_FGR64AsmReg: |
11601 | 1.45k | return parseAnyRegister(Operands); |
11602 | 57.2k | case MCK_GPR32AsmReg: |
11603 | 28.1k | return parseAnyRegister(Operands); |
11604 | 57.2k | case MCK_GPR32NonZeroAsmReg: |
11605 | 0 | return parseAnyRegister(Operands); |
11606 | 57.2k | case MCK_GPR32ZeroAsmReg: |
11607 | 0 | return parseAnyRegister(Operands); |
11608 | 57.2k | case MCK_GPR64AsmReg: |
11609 | 4.43k | return parseAnyRegister(Operands); |
11610 | 57.2k | case MCK_GPRMM16AsmReg: |
11611 | 231 | return parseAnyRegister(Operands); |
11612 | 57.2k | case MCK_GPRMM16AsmRegMoveP: |
11613 | 24 | return parseAnyRegister(Operands); |
11614 | 57.2k | case MCK_GPRMM16AsmRegMovePPairFirst: |
11615 | 12 | return parseAnyRegister(Operands); |
11616 | 57.2k | case MCK_GPRMM16AsmRegMovePPairSecond: |
11617 | 12 | return parseAnyRegister(Operands); |
11618 | 57.2k | case MCK_GPRMM16AsmRegZero: |
11619 | 40 | return parseAnyRegister(Operands); |
11620 | 57.2k | case MCK_HI32DSPAsmReg: |
11621 | 3 | return parseAnyRegister(Operands); |
11622 | 57.2k | case MCK_HWRegsAsmReg: |
11623 | 60 | return parseAnyRegister(Operands); |
11624 | 57.2k | case MCK_LO32DSPAsmReg: |
11625 | 3 | return parseAnyRegister(Operands); |
11626 | 57.2k | case MCK_MSA128AsmReg: |
11627 | 2.02k | return parseAnyRegister(Operands); |
11628 | 57.2k | case MCK_MSACtrlAsmReg: |
11629 | 32 | return parseAnyRegister(Operands); |
11630 | 57.2k | case MCK_MicroMipsMemGP: |
11631 | 0 | return parseMemOperand(Operands); |
11632 | 57.2k | case MCK_MicroMipsMem: |
11633 | 80 | return parseMemOperand(Operands); |
11634 | 57.2k | case MCK_MicroMipsMemSP: |
11635 | 77 | return parseMemOperand(Operands); |
11636 | 57.2k | case MCK_InvNum: |
11637 | 126 | return parseInvNum(Operands); |
11638 | 57.2k | case MCK_JumpTarget: |
11639 | 1.93k | return parseJumpTarget(Operands); |
11640 | 57.2k | case MCK_MemOffsetSimm10: |
11641 | 7 | return parseMemOperand(Operands); |
11642 | 57.2k | case MCK_MemOffsetSimm10_1: |
11643 | 9 | return parseMemOperand(Operands); |
11644 | 57.2k | case MCK_MemOffsetSimm10_2: |
11645 | 10 | return parseMemOperand(Operands); |
11646 | 57.2k | case MCK_MemOffsetSimm10_3: |
11647 | 13 | return parseMemOperand(Operands); |
11648 | 57.2k | case MCK_MemOffsetSimm11: |
11649 | 72 | return parseMemOperand(Operands); |
11650 | 57.2k | case MCK_MemOffsetSimm12: |
11651 | 26 | return parseMemOperand(Operands); |
11652 | 57.2k | case MCK_MemOffsetSimm16: |
11653 | 431 | return parseMemOperand(Operands); |
11654 | 57.2k | case MCK_MemOffsetSimm9: |
11655 | 601 | return parseMemOperand(Operands); |
11656 | 57.2k | case MCK_MemOffsetSimmPtr: |
11657 | 380 | return parseMemOperand(Operands); |
11658 | 57.2k | case MCK_MemOffsetUimm4: |
11659 | 0 | return parseMemOperand(Operands); |
11660 | 57.2k | case MCK_Mem: |
11661 | 12.0k | return parseMemOperand(Operands); |
11662 | 57.2k | case MCK_RegList16: |
11663 | 33 | return parseRegisterList(Operands); |
11664 | 57.2k | case MCK_RegList: |
11665 | 69 | return parseRegisterList(Operands); |
11666 | 57.2k | case MCK_StrictlyAFGR64AsmReg: |
11667 | 0 | return parseAnyRegister(Operands); |
11668 | 57.2k | case MCK_StrictlyFGR32AsmReg: |
11669 | 0 | return parseAnyRegister(Operands); |
11670 | 57.2k | case MCK_StrictlyFGR64AsmReg: |
11671 | 0 | return parseAnyRegister(Operands); |
11672 | 57.2k | default: |
11673 | 0 | return MatchOperand_NoMatch; |
11674 | 0 | } |
11675 | 0 | return MatchOperand_NoMatch; |
11676 | 0 | } |
11677 | | |
11678 | | OperandMatchResultTy MipsAsmParser:: |
11679 | | MatchOperandParserImpl(OperandVector &Operands, |
11680 | | StringRef Mnemonic, |
11681 | 66.9k | bool ParseForAllFeatures) { |
11682 | 66.9k | // Get the current feature set. |
11683 | 66.9k | const FeatureBitset &AvailableFeatures = getAvailableFeatures(); |
11684 | 66.9k | |
11685 | 66.9k | // Get the next operand index. |
11686 | 66.9k | unsigned NextOpNum = Operands.size() - 1; |
11687 | 66.9k | // Search the table. |
11688 | 66.9k | auto MnemonicRange = |
11689 | 66.9k | std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable), |
11690 | 66.9k | Mnemonic, LessOpcodeOperand()); |
11691 | 66.9k | |
11692 | 66.9k | if (MnemonicRange.first == MnemonicRange.second) |
11693 | 663 | return MatchOperand_NoMatch; |
11694 | 66.3k | |
11695 | 66.3k | for (const OperandMatchEntry *it = MnemonicRange.first, |
11696 | 204k | *ie = MnemonicRange.second; it != ie; ++it137k ) { |
11697 | 191k | // equal_range guarantees that instruction mnemonic matches. |
11698 | 191k | assert(Mnemonic == it->getMnemonic()); |
11699 | 191k | |
11700 | 191k | // check if the available features match |
11701 | 191k | const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx]; |
11702 | 191k | if (!ParseForAllFeatures && (AvailableFeatures & RequiredFeatures) != RequiredFeatures) |
11703 | 101k | continue; |
11704 | 89.9k | |
11705 | 89.9k | // check if the operand in question has a custom parser. |
11706 | 89.9k | if (!(it->OperandMask & (1 << NextOpNum))) |
11707 | 32.7k | continue; |
11708 | 57.2k | |
11709 | 57.2k | // call custom parse method to handle the operand |
11710 | 57.2k | OperandMatchResultTy Result = tryCustomParseOperand(Operands, it->Class); |
11711 | 57.2k | if (Result != MatchOperand_NoMatch) |
11712 | 53.3k | return Result; |
11713 | 57.2k | } |
11714 | 66.3k | |
11715 | 66.3k | // Okay, we had no match. |
11716 | 66.3k | return MatchOperand_NoMatch12.9k ; |
11717 | 66.3k | } |
11718 | | |
11719 | | #endif // GET_MATCHER_IMPLEMENTATION |
11720 | | |
11721 | | |
11722 | | #ifdef GET_MNEMONIC_SPELL_CHECKER |
11723 | | #undef GET_MNEMONIC_SPELL_CHECKER |
11724 | | |
11725 | 556 | static std::string MipsMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) { |
11726 | 556 | const unsigned MaxEditDist = 2; |
11727 | 556 | std::vector<StringRef> Candidates; |
11728 | 556 | StringRef Prev = ""; |
11729 | 556 | |
11730 | 556 | // Find the appropriate table for this asm variant. |
11731 | 556 | const MatchEntry *Start, *End; |
11732 | 556 | switch (VariantID) { |
11733 | 556 | default: 0 llvm_unreachable0 ("invalid variant!"); |
11734 | 556 | case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; |
11735 | 556 | } |
11736 | 556 | |
11737 | 1.47M | for (auto I = Start; 556 I < End; I++1.47M ) { |
11738 | 1.47M | // Ignore unsupported instructions. |
11739 | 1.47M | const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx]; |
11740 | 1.47M | if ((FBS & RequiredFeatures) != RequiredFeatures) |
11741 | 1.19M | continue; |
11742 | 279k | |
11743 | 279k | StringRef T = I->getMnemonic(); |
11744 | 279k | // Avoid recomputing the edit distance for the same string. |
11745 | 279k | if (T.equals(Prev)) |
11746 | 108k | continue; |
11747 | 171k | |
11748 | 171k | Prev = T; |
11749 | 171k | unsigned Dist = S.edit_distance(T, false, MaxEditDist); |
11750 | 171k | if (Dist <= MaxEditDist) |
11751 | 928 | Candidates.push_back(T); |
11752 | 171k | } |
11753 | 556 | |
11754 | 556 | if (Candidates.empty()) |
11755 | 102 | return ""; |
11756 | 454 | |
11757 | 454 | std::string Res = ", did you mean: "; |
11758 | 454 | unsigned i = 0; |
11759 | 928 | for( ; i < Candidates.size() - 1; i++474 ) |
11760 | 474 | Res += Candidates[i].str() + ", "; |
11761 | 454 | return Res + Candidates[i].str() + "?"; |
11762 | 454 | } |
11763 | | |
11764 | | #endif // GET_MNEMONIC_SPELL_CHECKER |
11765 | | |