Coverage Report

Created: 2018-09-23 22:08

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Mips/MipsGenFastISel.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* "Fast" Instruction Selector for the Mips target                            *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
// FastEmit Immediate Predicate functions.
11
8
static bool Predicate_immZExt5(int64_t Imm) {
12
8
return Imm == (Imm & 0x1f);
13
8
}
14
8
static bool Predicate_immZExt6(int64_t Imm) {
15
8
return Imm == (Imm & 0x3f);
16
8
}
17
0
static bool Predicate_immSExt6(int64_t Imm) {
18
0
return isInt<6>(Imm);
19
0
}
20
0
static bool Predicate_immZExt4Ptr(int64_t Imm) {
21
0
return isUInt<4>(Imm);
22
0
}
23
0
static bool Predicate_immZExt3Ptr(int64_t Imm) {
24
0
return isUInt<3>(Imm);
25
0
}
26
0
static bool Predicate_immZExt2Ptr(int64_t Imm) {
27
0
return isUInt<2>(Imm);
28
0
}
29
0
static bool Predicate_immZExt1Ptr(int64_t Imm) {
30
0
return isUInt<1>(Imm);
31
0
}
32
8
static bool Predicate_immZExt4(int64_t Imm) {
33
8
return isUInt<4>(Imm);
34
8
}
35
0
static bool Predicate_immZExt3(int64_t Imm) {
36
0
return isUInt<3>(Imm);
37
0
}
38
0
static bool Predicate_immZExt2(int64_t Imm) {
39
0
return isUInt<2>(Imm);
40
0
}
41
0
static bool Predicate_immZExt1(int64_t Imm) {
42
0
return isUInt<1>(Imm);
43
0
}
44
0
static bool Predicate_immZExt8(int64_t Imm) {
45
0
return isUInt<8>(Imm);
46
0
}
47
8
static bool Predicate_immSExtAddiur2(int64_t Imm) {
48
8
return Imm == 1 || 
Imm == -17
||
49
8
                                           
(7
(Imm % 4 == 0)7
&&
50
7
                                            Imm < 28 && Imm > 0);
51
8
}
52
8
static bool Predicate_immSExtAddius5(int64_t Imm) {
53
8
return Imm >= -8 && Imm <= 7;
54
8
}
55
8
static bool Predicate_immZExtAndi16(int64_t Imm) {
56
8
return (Imm == 128 || (Imm >= 1 && 
Imm <= 41
) ||
Imm == 77
||
Imm == 87
||
57
8
            
Imm == 157
||
Imm == 167
||
Imm == 317
||
Imm == 327
||
Imm == 637
||
58
8
            
Imm == 647
||
Imm == 2557
||
Imm == 327687
||
Imm == 655357
);
59
8
}
60
8
static bool Predicate_immZExt2Shift(int64_t Imm) {
61
8
return Imm >= 1 && 
Imm <= 81
;
62
8
}
63
64
65
// FastEmit functions for ISD::BITCAST.
66
67
0
unsigned fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
68
0
  if (RetVT.SimpleTy != MVT::f32)
69
0
    return 0;
70
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
71
0
    return fastEmitInst_r(Mips::MTC1_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill);
72
0
  }
73
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
74
0
    return fastEmitInst_r(Mips::MTC1_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
75
0
  }
76
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
77
0
    return fastEmitInst_r(Mips::MTC1, &Mips::FGR32RegClass, Op0, Op0IsKill);
78
0
  }
79
0
  return 0;
80
0
}
81
82
0
unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
83
0
  if (RetVT.SimpleTy != MVT::f64)
84
0
    return 0;
85
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
86
0
    return fastEmitInst_r(Mips::DMTC1, &Mips::FGR64RegClass, Op0, Op0IsKill);
87
0
  }
88
0
  return 0;
89
0
}
90
91
0
unsigned fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
92
0
  if (RetVT.SimpleTy != MVT::i32)
93
0
    return 0;
94
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
95
0
    return fastEmitInst_r(Mips::MFC1_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
96
0
  }
97
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
98
0
    return fastEmitInst_r(Mips::MFC1_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
99
0
  }
100
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
101
0
    return fastEmitInst_r(Mips::MFC1, &Mips::GPR32RegClass, Op0, Op0IsKill);
102
0
  }
103
0
  return 0;
104
0
}
105
106
0
unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
107
0
  if (RetVT.SimpleTy != MVT::i64)
108
0
    return 0;
109
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
110
0
    return fastEmitInst_r(Mips::DMFC1, &Mips::GPR64RegClass, Op0, Op0IsKill);
111
0
  }
112
0
  return 0;
113
0
}
114
115
unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
116
  switch (VT.SimpleTy) {
117
  case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0, Op0IsKill);
118
  case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0, Op0IsKill);
119
  case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0, Op0IsKill);
120
  case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill);
121
  default: return 0;
122
  }
123
}
124
125
// FastEmit functions for ISD::BRIND.
126
127
0
unsigned fastEmit_ISD_BRIND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
128
0
  if (RetVT.SimpleTy != MVT::isVoid)
129
0
    return 0;
130
0
  if ((Subtarget->inMips16Mode())) {
131
0
    return fastEmitInst_r(Mips::JrcRx16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill);
132
0
  }
133
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
134
0
    return fastEmitInst_r(Mips::PseudoIndirectBranch_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
135
0
  }
136
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
137
0
    return fastEmitInst_r(Mips::PseudoIndirectBranch_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
138
0
  }
139
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
140
0
    return fastEmitInst_r(Mips::PseudoIndrectHazardBranchR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
141
0
  }
142
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
143
0
    return fastEmitInst_r(Mips::PseudoIndirectBranchR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
144
0
  }
145
0
  if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
146
0
    return fastEmitInst_r(Mips::PseudoIndirectHazardBranch, &Mips::GPR32RegClass, Op0, Op0IsKill);
147
0
  }
148
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
149
0
    return fastEmitInst_r(Mips::PseudoIndirectBranch, &Mips::GPR32RegClass, Op0, Op0IsKill);
150
0
  }
151
0
  return 0;
152
0
}
153
154
0
unsigned fastEmit_ISD_BRIND_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
155
0
  if (RetVT.SimpleTy != MVT::isVoid)
156
0
    return 0;
157
0
  if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
158
0
    return fastEmitInst_r(Mips::PseudoIndrectHazardBranch64R6, &Mips::GPR64RegClass, Op0, Op0IsKill);
159
0
  }
160
0
  if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
161
0
    return fastEmitInst_r(Mips::PseudoIndirectBranch64R6, &Mips::GPR64RegClass, Op0, Op0IsKill);
162
0
  }
163
0
  if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
164
0
    return fastEmitInst_r(Mips::PseudoIndirectHazardBranch64, &Mips::GPR64RegClass, Op0, Op0IsKill);
165
0
  }
166
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
167
0
    return fastEmitInst_r(Mips::PseudoIndirectBranch64, &Mips::GPR64RegClass, Op0, Op0IsKill);
168
0
  }
169
0
  return 0;
170
0
}
171
172
unsigned fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
173
  switch (VT.SimpleTy) {
174
  case MVT::i32: return fastEmit_ISD_BRIND_MVT_i32_r(RetVT, Op0, Op0IsKill);
175
  case MVT::i64: return fastEmit_ISD_BRIND_MVT_i64_r(RetVT, Op0, Op0IsKill);
176
  default: return 0;
177
  }
178
}
179
180
// FastEmit functions for ISD::CTLZ.
181
182
0
unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
183
0
  if (RetVT.SimpleTy != MVT::i32)
184
0
    return 0;
185
0
  if ((Subtarget->inMicroMipsMode())) {
186
0
    return fastEmitInst_r(Mips::CLZ_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
187
0
  }
188
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding())) {
189
0
    return fastEmitInst_r(Mips::CLZ_R6, &Mips::GPR32RegClass, Op0, Op0IsKill);
190
0
  }
191
0
  if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
192
0
    return fastEmitInst_r(Mips::CLZ, &Mips::GPR32RegClass, Op0, Op0IsKill);
193
0
  }
194
0
  return 0;
195
0
}
196
197
0
unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
198
0
  if (RetVT.SimpleTy != MVT::i64)
199
0
    return 0;
200
0
  if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
201
0
    return fastEmitInst_r(Mips::DCLZ_R6, &Mips::GPR64RegClass, Op0, Op0IsKill);
202
0
  }
203
0
  if ((Subtarget->hasMips64()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips64r6())) {
204
0
    return fastEmitInst_r(Mips::DCLZ, &Mips::GPR64RegClass, Op0, Op0IsKill);
205
0
  }
206
0
  return 0;
207
0
}
208
209
0
unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
210
0
  if (RetVT.SimpleTy != MVT::v16i8)
211
0
    return 0;
212
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
213
0
    return fastEmitInst_r(Mips::NLZC_B, &Mips::MSA128BRegClass, Op0, Op0IsKill);
214
0
  }
215
0
  return 0;
216
0
}
217
218
0
unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
219
0
  if (RetVT.SimpleTy != MVT::v8i16)
220
0
    return 0;
221
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
222
0
    return fastEmitInst_r(Mips::NLZC_H, &Mips::MSA128HRegClass, Op0, Op0IsKill);
223
0
  }
224
0
  return 0;
225
0
}
226
227
0
unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
228
0
  if (RetVT.SimpleTy != MVT::v4i32)
229
0
    return 0;
230
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
231
0
    return fastEmitInst_r(Mips::NLZC_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
232
0
  }
233
0
  return 0;
234
0
}
235
236
0
unsigned fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
237
0
  if (RetVT.SimpleTy != MVT::v2i64)
238
0
    return 0;
239
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
240
0
    return fastEmitInst_r(Mips::NLZC_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
241
0
  }
242
0
  return 0;
243
0
}
244
245
unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
246
  switch (VT.SimpleTy) {
247
  case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
248
  case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0, Op0IsKill);
249
  case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
250
  case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
251
  case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
252
  case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
253
  default: return 0;
254
  }
255
}
256
257
// FastEmit functions for ISD::CTPOP.
258
259
0
unsigned fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
260
0
  if (RetVT.SimpleTy != MVT::i32)
261
0
    return 0;
262
0
  if ((Subtarget->hasCnMips())) {
263
0
    return fastEmitInst_r(Mips::POP, &Mips::GPR32RegClass, Op0, Op0IsKill);
264
0
  }
265
0
  return 0;
266
0
}
267
268
0
unsigned fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
269
0
  if (RetVT.SimpleTy != MVT::i64)
270
0
    return 0;
271
0
  if ((Subtarget->hasCnMips())) {
272
0
    return fastEmitInst_r(Mips::DPOP, &Mips::GPR64RegClass, Op0, Op0IsKill);
273
0
  }
274
0
  return 0;
275
0
}
276
277
0
unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
278
0
  if (RetVT.SimpleTy != MVT::v16i8)
279
0
    return 0;
280
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
281
0
    return fastEmitInst_r(Mips::PCNT_B, &Mips::MSA128BRegClass, Op0, Op0IsKill);
282
0
  }
283
0
  return 0;
284
0
}
285
286
0
unsigned fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
287
0
  if (RetVT.SimpleTy != MVT::v8i16)
288
0
    return 0;
289
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
290
0
    return fastEmitInst_r(Mips::PCNT_H, &Mips::MSA128HRegClass, Op0, Op0IsKill);
291
0
  }
292
0
  return 0;
293
0
}
294
295
0
unsigned fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
296
0
  if (RetVT.SimpleTy != MVT::v4i32)
297
0
    return 0;
298
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
299
0
    return fastEmitInst_r(Mips::PCNT_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
300
0
  }
301
0
  return 0;
302
0
}
303
304
0
unsigned fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
305
0
  if (RetVT.SimpleTy != MVT::v2i64)
306
0
    return 0;
307
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
308
0
    return fastEmitInst_r(Mips::PCNT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
309
0
  }
310
0
  return 0;
311
0
}
312
313
unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
314
  switch (VT.SimpleTy) {
315
  case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0, Op0IsKill);
316
  case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0, Op0IsKill);
317
  case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
318
  case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
319
  case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
320
  case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
321
  default: return 0;
322
  }
323
}
324
325
// FastEmit functions for ISD::FABS.
326
327
0
unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
328
0
  if (RetVT.SimpleTy != MVT::f32)
329
0
    return 0;
330
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
331
0
    return fastEmitInst_r(Mips::FABS_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
332
0
  }
333
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
334
0
    return fastEmitInst_r(Mips::FABS_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
335
0
  }
336
0
  return 0;
337
0
}
338
339
0
unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
340
0
  if (RetVT.SimpleTy != MVT::f64)
341
0
    return 0;
342
0
  if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
343
0
    return fastEmitInst_r(Mips::FABS_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
344
0
  }
345
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
346
0
    return fastEmitInst_r(Mips::FABS_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
347
0
  }
348
0
  if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
349
0
    return fastEmitInst_r(Mips::FABS_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
350
0
  }
351
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
352
0
    return fastEmitInst_r(Mips::FABS_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill);
353
0
  }
354
0
  return 0;
355
0
}
356
357
0
unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
358
0
  if (RetVT.SimpleTy != MVT::v4f32)
359
0
    return 0;
360
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
361
0
    return fastEmitInst_r(Mips::FABS_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
362
0
  }
363
0
  return 0;
364
0
}
365
366
0
unsigned fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
367
0
  if (RetVT.SimpleTy != MVT::v2f64)
368
0
    return 0;
369
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
370
0
    return fastEmitInst_r(Mips::FABS_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
371
0
  }
372
0
  return 0;
373
0
}
374
375
unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
376
  switch (VT.SimpleTy) {
377
  case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill);
378
  case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0, Op0IsKill);
379
  case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
380
  case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
381
  default: return 0;
382
  }
383
}
384
385
// FastEmit functions for ISD::FEXP2.
386
387
0
unsigned fastEmit_ISD_FEXP2_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
388
0
  if (RetVT.SimpleTy != MVT::v4f32)
389
0
    return 0;
390
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
391
0
    return fastEmitInst_r(Mips::FEXP2_W_1_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill);
392
0
  }
393
0
  return 0;
394
0
}
395
396
0
unsigned fastEmit_ISD_FEXP2_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
397
0
  if (RetVT.SimpleTy != MVT::v2f64)
398
0
    return 0;
399
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
400
0
    return fastEmitInst_r(Mips::FEXP2_D_1_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill);
401
0
  }
402
0
  return 0;
403
0
}
404
405
unsigned fastEmit_ISD_FEXP2_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
406
  switch (VT.SimpleTy) {
407
  case MVT::v4f32: return fastEmit_ISD_FEXP2_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
408
  case MVT::v2f64: return fastEmit_ISD_FEXP2_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
409
  default: return 0;
410
  }
411
}
412
413
// FastEmit functions for ISD::FLOG2.
414
415
0
unsigned fastEmit_ISD_FLOG2_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
416
0
  if (RetVT.SimpleTy != MVT::v4f32)
417
0
    return 0;
418
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
419
0
    return fastEmitInst_r(Mips::FLOG2_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
420
0
  }
421
0
  return 0;
422
0
}
423
424
0
unsigned fastEmit_ISD_FLOG2_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
425
0
  if (RetVT.SimpleTy != MVT::v2f64)
426
0
    return 0;
427
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
428
0
    return fastEmitInst_r(Mips::FLOG2_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
429
0
  }
430
0
  return 0;
431
0
}
432
433
unsigned fastEmit_ISD_FLOG2_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
434
  switch (VT.SimpleTy) {
435
  case MVT::v4f32: return fastEmit_ISD_FLOG2_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
436
  case MVT::v2f64: return fastEmit_ISD_FLOG2_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
437
  default: return 0;
438
  }
439
}
440
441
// FastEmit functions for ISD::FNEG.
442
443
0
unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
444
0
  if (RetVT.SimpleTy != MVT::f32)
445
0
    return 0;
446
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
447
0
    return fastEmitInst_r(Mips::FNEG_S_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill);
448
0
  }
449
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
450
0
    return fastEmitInst_r(Mips::FNEG_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
451
0
  }
452
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
453
0
    return fastEmitInst_r(Mips::FNEG_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
454
0
  }
455
0
  return 0;
456
0
}
457
458
0
unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
459
0
  if (RetVT.SimpleTy != MVT::f64)
460
0
    return 0;
461
0
  if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
462
0
    return fastEmitInst_r(Mips::FNEG_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
463
0
  }
464
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
465
0
    return fastEmitInst_r(Mips::FNEG_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
466
0
  }
467
0
  if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
468
0
    return fastEmitInst_r(Mips::FNEG_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
469
0
  }
470
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
471
0
    return fastEmitInst_r(Mips::FNEG_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill);
472
0
  }
473
0
  return 0;
474
0
}
475
476
unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
477
  switch (VT.SimpleTy) {
478
  case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill);
479
  case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0, Op0IsKill);
480
  default: return 0;
481
  }
482
}
483
484
// FastEmit functions for ISD::FP_EXTEND.
485
486
0
unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
487
0
  if ((Subtarget->hasMSA())) {
488
0
    return fastEmitInst_r(Mips::MSA_FP_EXTEND_W_PSEUDO, &Mips::FGR32RegClass, Op0, Op0IsKill);
489
0
  }
490
0
  return 0;
491
0
}
492
493
0
unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
494
0
  if ((Subtarget->hasMSA())) {
495
0
    return fastEmitInst_r(Mips::MSA_FP_EXTEND_D_PSEUDO, &Mips::FGR64RegClass, Op0, Op0IsKill);
496
0
  }
497
0
  return 0;
498
0
}
499
500
unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
501
switch (RetVT.SimpleTy) {
502
  case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(Op0, Op0IsKill);
503
  case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(Op0, Op0IsKill);
504
  default: return 0;
505
}
506
}
507
508
0
unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
509
0
  if (RetVT.SimpleTy != MVT::f64)
510
0
    return 0;
511
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())) {
512
0
    return fastEmitInst_r(Mips::CVT_D32_S_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
513
0
  }
514
0
  if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) {
515
0
    return fastEmitInst_r(Mips::CVT_D64_S_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
516
0
  }
517
0
  if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
518
0
    return fastEmitInst_r(Mips::CVT_D64_S, &Mips::FGR64RegClass, Op0, Op0IsKill);
519
0
  }
520
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
521
0
    return fastEmitInst_r(Mips::CVT_D32_S, &Mips::AFGR64RegClass, Op0, Op0IsKill);
522
0
  }
523
0
  return 0;
524
0
}
525
526
unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
527
  switch (VT.SimpleTy) {
528
  case MVT::f16: return fastEmit_ISD_FP_EXTEND_MVT_f16_r(RetVT, Op0, Op0IsKill);
529
  case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill);
530
  default: return 0;
531
  }
532
}
533
534
// FastEmit functions for ISD::FP_ROUND.
535
536
0
unsigned fastEmit_ISD_FP_ROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
537
0
  if (RetVT.SimpleTy != MVT::f16)
538
0
    return 0;
539
0
  if ((Subtarget->hasMSA())) {
540
0
    return fastEmitInst_r(Mips::MSA_FP_ROUND_W_PSEUDO, &Mips::MSA128F16RegClass, Op0, Op0IsKill);
541
0
  }
542
0
  return 0;
543
0
}
544
545
0
unsigned fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(unsigned Op0, bool Op0IsKill) {
546
0
  if ((Subtarget->hasMSA())) {
547
0
    return fastEmitInst_r(Mips::MSA_FP_ROUND_D_PSEUDO, &Mips::MSA128F16RegClass, Op0, Op0IsKill);
548
0
  }
549
0
  return 0;
550
0
}
551
552
0
unsigned fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
553
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())) {
554
0
    return fastEmitInst_r(Mips::CVT_S_D32_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
555
0
  }
556
0
  if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) {
557
0
    return fastEmitInst_r(Mips::CVT_S_D64_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
558
0
  }
559
0
  if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
560
0
    return fastEmitInst_r(Mips::CVT_S_D64, &Mips::FGR32RegClass, Op0, Op0IsKill);
561
0
  }
562
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
563
0
    return fastEmitInst_r(Mips::CVT_S_D32, &Mips::FGR32RegClass, Op0, Op0IsKill);
564
0
  }
565
0
  return 0;
566
0
}
567
568
unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
569
switch (RetVT.SimpleTy) {
570
  case MVT::f16: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(Op0, Op0IsKill);
571
  case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(Op0, Op0IsKill);
572
  default: return 0;
573
}
574
}
575
576
unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
577
  switch (VT.SimpleTy) {
578
  case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f32_r(RetVT, Op0, Op0IsKill);
579
  case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
580
  default: return 0;
581
  }
582
}
583
584
// FastEmit functions for ISD::FP_TO_SINT.
585
586
0
unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
587
0
  if (RetVT.SimpleTy != MVT::v4i32)
588
0
    return 0;
589
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
590
0
    return fastEmitInst_r(Mips::FTRUNC_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
591
0
  }
592
0
  return 0;
593
0
}
594
595
0
unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
596
0
  if (RetVT.SimpleTy != MVT::v2i64)
597
0
    return 0;
598
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
599
0
    return fastEmitInst_r(Mips::FTRUNC_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
600
0
  }
601
0
  return 0;
602
0
}
603
604
4
unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
605
4
  switch (VT.SimpleTy) {
606
4
  
case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill)0
;
607
4
  
case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill)0
;
608
4
  default: return 0;
609
4
  }
610
4
}
611
612
// FastEmit functions for ISD::FP_TO_UINT.
613
614
0
unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
615
0
  if (RetVT.SimpleTy != MVT::v4i32)
616
0
    return 0;
617
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
618
0
    return fastEmitInst_r(Mips::FTRUNC_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
619
0
  }
620
0
  return 0;
621
0
}
622
623
0
unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
624
0
  if (RetVT.SimpleTy != MVT::v2i64)
625
0
    return 0;
626
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
627
0
    return fastEmitInst_r(Mips::FTRUNC_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
628
0
  }
629
0
  return 0;
630
0
}
631
632
unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
633
  switch (VT.SimpleTy) {
634
  case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
635
  case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
636
  default: return 0;
637
  }
638
}
639
640
// FastEmit functions for ISD::FRINT.
641
642
0
unsigned fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
643
0
  if (RetVT.SimpleTy != MVT::v4f32)
644
0
    return 0;
645
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
646
0
    return fastEmitInst_r(Mips::FRINT_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
647
0
  }
648
0
  return 0;
649
0
}
650
651
0
unsigned fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
652
0
  if (RetVT.SimpleTy != MVT::v2f64)
653
0
    return 0;
654
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
655
0
    return fastEmitInst_r(Mips::FRINT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
656
0
  }
657
0
  return 0;
658
0
}
659
660
unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
661
  switch (VT.SimpleTy) {
662
  case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
663
  case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
664
  default: return 0;
665
  }
666
}
667
668
// FastEmit functions for ISD::FSQRT.
669
670
0
unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
671
0
  if (RetVT.SimpleTy != MVT::f32)
672
0
    return 0;
673
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
674
0
    return fastEmitInst_r(Mips::FSQRT_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
675
0
  }
676
0
  if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
677
0
    return fastEmitInst_r(Mips::FSQRT_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
678
0
  }
679
0
  return 0;
680
0
}
681
682
0
unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
683
0
  if (RetVT.SimpleTy != MVT::f64)
684
0
    return 0;
685
0
  if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
686
0
    return fastEmitInst_r(Mips::FSQRT_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
687
0
  }
688
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
689
0
    return fastEmitInst_r(Mips::FSQRT_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
690
0
  }
691
0
  if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
692
0
    return fastEmitInst_r(Mips::FSQRT_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
693
0
  }
694
0
  if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
695
0
    return fastEmitInst_r(Mips::FSQRT_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill);
696
0
  }
697
0
  return 0;
698
0
}
699
700
0
unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
701
0
  if (RetVT.SimpleTy != MVT::v4f32)
702
0
    return 0;
703
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
704
0
    return fastEmitInst_r(Mips::FSQRT_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
705
0
  }
706
0
  return 0;
707
0
}
708
709
0
unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
710
0
  if (RetVT.SimpleTy != MVT::v2f64)
711
0
    return 0;
712
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
713
0
    return fastEmitInst_r(Mips::FSQRT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
714
0
  }
715
0
  return 0;
716
0
}
717
718
unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
719
  switch (VT.SimpleTy) {
720
  case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill);
721
  case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0, Op0IsKill);
722
  case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
723
  case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
724
  default: return 0;
725
  }
726
}
727
728
// FastEmit functions for ISD::SIGN_EXTEND.
729
730
0
unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
731
0
  if (RetVT.SimpleTy != MVT::i64)
732
0
    return 0;
733
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())) {
734
0
    return fastEmitInst_r(Mips::SLL64_32, &Mips::GPR64RegClass, Op0, Op0IsKill);
735
0
  }
736
0
  return 0;
737
0
}
738
739
unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
740
  switch (VT.SimpleTy) {
741
  case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0, Op0IsKill);
742
  default: return 0;
743
  }
744
}
745
746
// FastEmit functions for ISD::SINT_TO_FP.
747
748
0
unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
749
0
  return fastEmitInst_r(Mips::PseudoCVT_S_W, &Mips::FGR32RegClass, Op0, Op0IsKill);
750
0
}
751
752
0
unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
753
0
  if ((Subtarget->isFP64bit())) {
754
0
    return fastEmitInst_r(Mips::PseudoCVT_D64_W, &Mips::FGR64RegClass, Op0, Op0IsKill);
755
0
  }
756
0
  if ((!Subtarget->isFP64bit())) {
757
0
    return fastEmitInst_r(Mips::PseudoCVT_D32_W, &Mips::AFGR64RegClass, Op0, Op0IsKill);
758
0
  }
759
0
  return 0;
760
0
}
761
762
unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
763
switch (RetVT.SimpleTy) {
764
  case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill);
765
  case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0, Op0IsKill);
766
  default: return 0;
767
}
768
}
769
770
0
unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
771
0
  if (RetVT.SimpleTy != MVT::f64)
772
0
    return 0;
773
0
  if ((Subtarget->isFP64bit())) {
774
0
    return fastEmitInst_r(Mips::PseudoCVT_D64_L, &Mips::FGR64RegClass, Op0, Op0IsKill);
775
0
  }
776
0
  return 0;
777
0
}
778
779
0
unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
780
0
  if (RetVT.SimpleTy != MVT::v4f32)
781
0
    return 0;
782
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
783
0
    return fastEmitInst_r(Mips::FFINT_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
784
0
  }
785
0
  return 0;
786
0
}
787
788
0
unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
789
0
  if (RetVT.SimpleTy != MVT::v2f64)
790
0
    return 0;
791
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
792
0
    return fastEmitInst_r(Mips::FFINT_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
793
0
  }
794
0
  return 0;
795
0
}
796
797
unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
798
  switch (VT.SimpleTy) {
799
  case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0, Op0IsKill);
800
  case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0, Op0IsKill);
801
  case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
802
  case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
803
  default: return 0;
804
  }
805
}
806
807
// FastEmit functions for ISD::UINT_TO_FP.
808
809
0
unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
810
0
  if (RetVT.SimpleTy != MVT::v4f32)
811
0
    return 0;
812
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
813
0
    return fastEmitInst_r(Mips::FFINT_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
814
0
  }
815
0
  return 0;
816
0
}
817
818
0
unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
819
0
  if (RetVT.SimpleTy != MVT::v2f64)
820
0
    return 0;
821
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
822
0
    return fastEmitInst_r(Mips::FFINT_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
823
0
  }
824
0
  return 0;
825
0
}
826
827
unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
828
  switch (VT.SimpleTy) {
829
  case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
830
  case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
831
  default: return 0;
832
  }
833
}
834
835
// FastEmit functions for MipsISD::JmpLink.
836
837
0
unsigned fastEmit_MipsISD_JmpLink_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
838
0
  if (RetVT.SimpleTy != MVT::isVoid)
839
0
    return 0;
840
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
841
0
    return fastEmitInst_r(Mips::JALR16_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
842
0
  }
843
0
  if ((Subtarget->inMips16Mode())) {
844
0
    return fastEmitInst_r(Mips::JumpLinkReg16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill);
845
0
  }
846
0
  if ((!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
847
0
    return fastEmitInst_r(Mips::JALRHBPseudo, &Mips::GPR32RegClass, Op0, Op0IsKill);
848
0
  }
849
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode())) {
850
0
    return fastEmitInst_r(Mips::JALRPseudo, &Mips::GPR32RegClass, Op0, Op0IsKill);
851
0
  }
852
0
  return 0;
853
0
}
854
855
0
unsigned fastEmit_MipsISD_JmpLink_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
856
0
  if (RetVT.SimpleTy != MVT::isVoid)
857
0
    return 0;
858
0
  if ((!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
859
0
    return fastEmitInst_r(Mips::JALRHB64Pseudo, &Mips::GPR64RegClass, Op0, Op0IsKill);
860
0
  }
861
0
  if ((!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMips16Mode())) {
862
0
    return fastEmitInst_r(Mips::JALR64Pseudo, &Mips::GPR64RegClass, Op0, Op0IsKill);
863
0
  }
864
0
  return 0;
865
0
}
866
867
unsigned fastEmit_MipsISD_JmpLink_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
868
  switch (VT.SimpleTy) {
869
  case MVT::i32: return fastEmit_MipsISD_JmpLink_MVT_i32_r(RetVT, Op0, Op0IsKill);
870
  case MVT::i64: return fastEmit_MipsISD_JmpLink_MVT_i64_r(RetVT, Op0, Op0IsKill);
871
  default: return 0;
872
  }
873
}
874
875
// FastEmit functions for MipsISD::MFHI.
876
877
0
unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(unsigned Op0, bool Op0IsKill) {
878
0
  if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
879
0
    return fastEmitInst_r(Mips::MFHI_DSP_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
880
0
  }
881
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
882
0
    return fastEmitInst_r(Mips::PseudoMFHI_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
883
0
  }
884
0
  if ((Subtarget->hasDSP())) {
885
0
    return fastEmitInst_r(Mips::MFHI_DSP, &Mips::GPR32RegClass, Op0, Op0IsKill);
886
0
  }
887
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
888
0
    return fastEmitInst_r(Mips::PseudoMFHI, &Mips::GPR32RegClass, Op0, Op0IsKill);
889
0
  }
890
0
  return 0;
891
0
}
892
893
0
unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(unsigned Op0, bool Op0IsKill) {
894
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
895
0
    return fastEmitInst_r(Mips::PseudoMFHI64, &Mips::GPR64RegClass, Op0, Op0IsKill);
896
0
  }
897
0
  return 0;
898
0
}
899
900
unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
901
switch (RetVT.SimpleTy) {
902
  case MVT::i32: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(Op0, Op0IsKill);
903
  case MVT::i64: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(Op0, Op0IsKill);
904
  default: return 0;
905
}
906
}
907
908
unsigned fastEmit_MipsISD_MFHI_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
909
  switch (VT.SimpleTy) {
910
  case MVT::Untyped: return fastEmit_MipsISD_MFHI_MVT_Untyped_r(RetVT, Op0, Op0IsKill);
911
  default: return 0;
912
  }
913
}
914
915
// FastEmit functions for MipsISD::MFLO.
916
917
0
unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(unsigned Op0, bool Op0IsKill) {
918
0
  if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
919
0
    return fastEmitInst_r(Mips::MFLO_DSP_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
920
0
  }
921
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
922
0
    return fastEmitInst_r(Mips::PseudoMFLO_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
923
0
  }
924
0
  if ((Subtarget->hasDSP())) {
925
0
    return fastEmitInst_r(Mips::MFLO_DSP, &Mips::GPR32RegClass, Op0, Op0IsKill);
926
0
  }
927
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
928
0
    return fastEmitInst_r(Mips::PseudoMFLO, &Mips::GPR32RegClass, Op0, Op0IsKill);
929
0
  }
930
0
  return 0;
931
0
}
932
933
0
unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(unsigned Op0, bool Op0IsKill) {
934
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
935
0
    return fastEmitInst_r(Mips::PseudoMFLO64, &Mips::GPR64RegClass, Op0, Op0IsKill);
936
0
  }
937
0
  return 0;
938
0
}
939
940
unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
941
switch (RetVT.SimpleTy) {
942
  case MVT::i32: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(Op0, Op0IsKill);
943
  case MVT::i64: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(Op0, Op0IsKill);
944
  default: return 0;
945
}
946
}
947
948
unsigned fastEmit_MipsISD_MFLO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
949
  switch (VT.SimpleTy) {
950
  case MVT::Untyped: return fastEmit_MipsISD_MFLO_MVT_Untyped_r(RetVT, Op0, Op0IsKill);
951
  default: return 0;
952
  }
953
}
954
955
// FastEmit functions for MipsISD::MTC1_D64.
956
957
0
unsigned fastEmit_MipsISD_MTC1_D64_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
958
0
  if (RetVT.SimpleTy != MVT::f64)
959
0
    return 0;
960
0
  if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) {
961
0
    return fastEmitInst_r(Mips::MTC1_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
962
0
  }
963
0
  if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
964
0
    return fastEmitInst_r(Mips::MTC1_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
965
0
  }
966
0
  return 0;
967
0
}
968
969
unsigned fastEmit_MipsISD_MTC1_D64_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
970
  switch (VT.SimpleTy) {
971
  case MVT::i32: return fastEmit_MipsISD_MTC1_D64_MVT_i32_r(RetVT, Op0, Op0IsKill);
972
  default: return 0;
973
  }
974
}
975
976
// FastEmit functions for MipsISD::TailCall.
977
978
0
unsigned fastEmit_MipsISD_TailCall_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
979
0
  if (RetVT.SimpleTy != MVT::isVoid)
980
0
    return 0;
981
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
982
0
    return fastEmitInst_r(Mips::TAILCALLREG_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
983
0
  }
984
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
985
0
    return fastEmitInst_r(Mips::TAILCALLREG_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
986
0
  }
987
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
988
0
    return fastEmitInst_r(Mips::TAILCALLHBR6REG, &Mips::GPR32RegClass, Op0, Op0IsKill);
989
0
  }
990
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
991
0
    return fastEmitInst_r(Mips::TAILCALLR6REG, &Mips::GPR32RegClass, Op0, Op0IsKill);
992
0
  }
993
0
  if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
994
0
    return fastEmitInst_r(Mips::TAILCALLREGHB, &Mips::GPR32RegClass, Op0, Op0IsKill);
995
0
  }
996
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
997
0
    return fastEmitInst_r(Mips::TAILCALLREG, &Mips::GPR32RegClass, Op0, Op0IsKill);
998
0
  }
999
0
  return 0;
1000
0
}
1001
1002
0
unsigned fastEmit_MipsISD_TailCall_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1003
0
  if (RetVT.SimpleTy != MVT::isVoid)
1004
0
    return 0;
1005
0
  if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
1006
0
    return fastEmitInst_r(Mips::TAILCALLHB64R6REG, &Mips::GPR64RegClass, Op0, Op0IsKill);
1007
0
  }
1008
0
  if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
1009
0
    return fastEmitInst_r(Mips::TAILCALL64R6REG, &Mips::GPR64RegClass, Op0, Op0IsKill);
1010
0
  }
1011
0
  if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
1012
0
    return fastEmitInst_r(Mips::TAILCALLREGHB64, &Mips::GPR64RegClass, Op0, Op0IsKill);
1013
0
  }
1014
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1015
0
    return fastEmitInst_r(Mips::TAILCALLREG64, &Mips::GPR64RegClass, Op0, Op0IsKill);
1016
0
  }
1017
0
  return 0;
1018
0
}
1019
1020
unsigned fastEmit_MipsISD_TailCall_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1021
  switch (VT.SimpleTy) {
1022
  case MVT::i32: return fastEmit_MipsISD_TailCall_MVT_i32_r(RetVT, Op0, Op0IsKill);
1023
  case MVT::i64: return fastEmit_MipsISD_TailCall_MVT_i64_r(RetVT, Op0, Op0IsKill);
1024
  default: return 0;
1025
  }
1026
}
1027
1028
// FastEmit functions for MipsISD::TruncIntFP.
1029
1030
0
unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
1031
0
  if ((Subtarget->hasStandardEncoding())) {
1032
0
    return fastEmitInst_r(Mips::TRUNC_W_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
1033
0
  }
1034
0
  return 0;
1035
0
}
1036
1037
0
unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
1038
0
  if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
1039
0
    return fastEmitInst_r(Mips::TRUNC_L_S, &Mips::FGR64RegClass, Op0, Op0IsKill);
1040
0
  }
1041
0
  return 0;
1042
0
}
1043
1044
unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1045
switch (RetVT.SimpleTy) {
1046
  case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(Op0, Op0IsKill);
1047
  case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(Op0, Op0IsKill);
1048
  default: return 0;
1049
}
1050
}
1051
1052
0
unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
1053
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1054
0
    return fastEmitInst_r(Mips::TRUNC_W_D_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill);
1055
0
  }
1056
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())) {
1057
0
    return fastEmitInst_r(Mips::TRUNC_W_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
1058
0
  }
1059
0
  if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
1060
0
    return fastEmitInst_r(Mips::TRUNC_W_D64, &Mips::FGR32RegClass, Op0, Op0IsKill);
1061
0
  }
1062
0
  if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1063
0
    return fastEmitInst_r(Mips::TRUNC_W_D32, &Mips::FGR32RegClass, Op0, Op0IsKill);
1064
0
  }
1065
0
  return 0;
1066
0
}
1067
1068
0
unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
1069
0
  if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
1070
0
    return fastEmitInst_r(Mips::TRUNC_L_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
1071
0
  }
1072
0
  return 0;
1073
0
}
1074
1075
unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1076
switch (RetVT.SimpleTy) {
1077
  case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(Op0, Op0IsKill);
1078
  case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(Op0, Op0IsKill);
1079
  default: return 0;
1080
}
1081
}
1082
1083
unsigned fastEmit_MipsISD_TruncIntFP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1084
  switch (VT.SimpleTy) {
1085
  case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_r(RetVT, Op0, Op0IsKill);
1086
  case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_r(RetVT, Op0, Op0IsKill);
1087
  default: return 0;
1088
  }
1089
}
1090
1091
// FastEmit functions for MipsISD::VALL_NONZERO.
1092
1093
0
unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1094
0
  if (RetVT.SimpleTy != MVT::i32)
1095
0
    return 0;
1096
0
  return fastEmitInst_r(Mips::SNZ_B_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1097
0
}
1098
1099
0
unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1100
0
  if (RetVT.SimpleTy != MVT::i32)
1101
0
    return 0;
1102
0
  return fastEmitInst_r(Mips::SNZ_H_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1103
0
}
1104
1105
0
unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1106
0
  if (RetVT.SimpleTy != MVT::i32)
1107
0
    return 0;
1108
0
  return fastEmitInst_r(Mips::SNZ_W_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1109
0
}
1110
1111
0
unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1112
0
  if (RetVT.SimpleTy != MVT::i32)
1113
0
    return 0;
1114
0
  return fastEmitInst_r(Mips::SNZ_D_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1115
0
}
1116
1117
unsigned fastEmit_MipsISD_VALL_NONZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1118
  switch (VT.SimpleTy) {
1119
  case MVT::v16i8: return fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
1120
  case MVT::v8i16: return fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
1121
  case MVT::v4i32: return fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
1122
  case MVT::v2i64: return fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
1123
  default: return 0;
1124
  }
1125
}
1126
1127
// FastEmit functions for MipsISD::VALL_ZERO.
1128
1129
0
unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1130
0
  if (RetVT.SimpleTy != MVT::i32)
1131
0
    return 0;
1132
0
  return fastEmitInst_r(Mips::SZ_B_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1133
0
}
1134
1135
0
unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1136
0
  if (RetVT.SimpleTy != MVT::i32)
1137
0
    return 0;
1138
0
  return fastEmitInst_r(Mips::SZ_H_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1139
0
}
1140
1141
0
unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1142
0
  if (RetVT.SimpleTy != MVT::i32)
1143
0
    return 0;
1144
0
  return fastEmitInst_r(Mips::SZ_W_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1145
0
}
1146
1147
0
unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1148
0
  if (RetVT.SimpleTy != MVT::i32)
1149
0
    return 0;
1150
0
  return fastEmitInst_r(Mips::SZ_D_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1151
0
}
1152
1153
unsigned fastEmit_MipsISD_VALL_ZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1154
  switch (VT.SimpleTy) {
1155
  case MVT::v16i8: return fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
1156
  case MVT::v8i16: return fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
1157
  case MVT::v4i32: return fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
1158
  case MVT::v2i64: return fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
1159
  default: return 0;
1160
  }
1161
}
1162
1163
// FastEmit functions for MipsISD::VANY_NONZERO.
1164
1165
0
unsigned fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1166
0
  if (RetVT.SimpleTy != MVT::i32)
1167
0
    return 0;
1168
0
  return fastEmitInst_r(Mips::SNZ_V_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1169
0
}
1170
1171
unsigned fastEmit_MipsISD_VANY_NONZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1172
  switch (VT.SimpleTy) {
1173
  case MVT::v16i8: return fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
1174
  default: return 0;
1175
  }
1176
}
1177
1178
// FastEmit functions for MipsISD::VANY_ZERO.
1179
1180
0
unsigned fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1181
0
  if (RetVT.SimpleTy != MVT::i32)
1182
0
    return 0;
1183
0
  return fastEmitInst_r(Mips::SZ_V_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1184
0
}
1185
1186
unsigned fastEmit_MipsISD_VANY_ZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1187
  switch (VT.SimpleTy) {
1188
  case MVT::v16i8: return fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
1189
  default: return 0;
1190
  }
1191
}
1192
1193
// Top-level FastEmit function.
1194
1195
4
unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill) override {
1196
4
  switch (Opcode) {
1197
4
  
case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0, Op0IsKill)0
;
1198
4
  
case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0, Op0IsKill)0
;
1199
4
  
case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill)0
;
1200
4
  
case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill)0
;
1201
4
  
case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill)0
;
1202
4
  
case ISD::FEXP2: return fastEmit_ISD_FEXP2_r(VT, RetVT, Op0, Op0IsKill)0
;
1203
4
  
case ISD::FLOG2: return fastEmit_ISD_FLOG2_r(VT, RetVT, Op0, Op0IsKill)0
;
1204
4
  
case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill)0
;
1205
4
  
case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill)0
;
1206
4
  
case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill)0
;
1207
4
  case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill);
1208
4
  
case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill)0
;
1209
4
  
case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0, Op0IsKill)0
;
1210
4
  
case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill)0
;
1211
4
  
case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill)0
;
1212
4
  
case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill)0
;
1213
4
  
case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill)0
;
1214
4
  
case MipsISD::JmpLink: return fastEmit_MipsISD_JmpLink_r(VT, RetVT, Op0, Op0IsKill)0
;
1215
4
  
case MipsISD::MFHI: return fastEmit_MipsISD_MFHI_r(VT, RetVT, Op0, Op0IsKill)0
;
1216
4
  
case MipsISD::MFLO: return fastEmit_MipsISD_MFLO_r(VT, RetVT, Op0, Op0IsKill)0
;
1217
4
  
case MipsISD::MTC1_D64: return fastEmit_MipsISD_MTC1_D64_r(VT, RetVT, Op0, Op0IsKill)0
;
1218
4
  
case MipsISD::TailCall: return fastEmit_MipsISD_TailCall_r(VT, RetVT, Op0, Op0IsKill)0
;
1219
4
  
case MipsISD::TruncIntFP: return fastEmit_MipsISD_TruncIntFP_r(VT, RetVT, Op0, Op0IsKill)0
;
1220
4
  
case MipsISD::VALL_NONZERO: return fastEmit_MipsISD_VALL_NONZERO_r(VT, RetVT, Op0, Op0IsKill)0
;
1221
4
  
case MipsISD::VALL_ZERO: return fastEmit_MipsISD_VALL_ZERO_r(VT, RetVT, Op0, Op0IsKill)0
;
1222
4
  
case MipsISD::VANY_NONZERO: return fastEmit_MipsISD_VANY_NONZERO_r(VT, RetVT, Op0, Op0IsKill)0
;
1223
4
  
case MipsISD::VANY_ZERO: return fastEmit_MipsISD_VANY_ZERO_r(VT, RetVT, Op0, Op0IsKill)0
;
1224
4
  
default: return 00
;
1225
4
  }
1226
4
}
1227
1228
// FastEmit functions for ISD::ADD.
1229
1230
6
unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1231
6
  if (RetVT.SimpleTy != MVT::i32)
1232
0
    return 0;
1233
6
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->inMicroMipsMode())0
) {
1234
0
    return fastEmitInst_rr(Mips::ADDU16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1235
0
  }
1236
6
  if ((Subtarget->inMips16Mode())) {
1237
0
    return fastEmitInst_rr(Mips::AdduRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1238
0
  }
1239
6
  if ((Subtarget->inMicroMipsMode()) && 
(!Subtarget->hasMips32r6())0
) {
1240
0
    return fastEmitInst_rr(Mips::ADDu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1241
0
  }
1242
6
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1243
6
    return fastEmitInst_rr(Mips::ADDu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1244
6
  }
1245
0
  return 0;
1246
0
}
1247
1248
0
unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1249
0
  if (RetVT.SimpleTy != MVT::i64)
1250
0
    return 0;
1251
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1252
0
    return fastEmitInst_rr(Mips::DADDu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1253
0
  }
1254
0
  return 0;
1255
0
}
1256
1257
0
unsigned fastEmit_ISD_ADD_MVT_v4i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1258
0
  if (RetVT.SimpleTy != MVT::v4i8)
1259
0
    return 0;
1260
0
  if ((Subtarget->hasDSP())) {
1261
0
    return fastEmitInst_rr(Mips::ADDU_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1262
0
  }
1263
0
  return 0;
1264
0
}
1265
1266
0
unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1267
0
  if (RetVT.SimpleTy != MVT::v16i8)
1268
0
    return 0;
1269
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1270
0
    return fastEmitInst_rr(Mips::ADDV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1271
0
  }
1272
0
  return 0;
1273
0
}
1274
1275
0
unsigned fastEmit_ISD_ADD_MVT_v2i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1276
0
  if (RetVT.SimpleTy != MVT::v2i16)
1277
0
    return 0;
1278
0
  if ((Subtarget->hasDSP())) {
1279
0
    return fastEmitInst_rr(Mips::ADDQ_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1280
0
  }
1281
0
  return 0;
1282
0
}
1283
1284
0
unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1285
0
  if (RetVT.SimpleTy != MVT::v8i16)
1286
0
    return 0;
1287
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1288
0
    return fastEmitInst_rr(Mips::ADDV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1289
0
  }
1290
0
  return 0;
1291
0
}
1292
1293
0
unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1294
0
  if (RetVT.SimpleTy != MVT::v4i32)
1295
0
    return 0;
1296
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1297
0
    return fastEmitInst_rr(Mips::ADDV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1298
0
  }
1299
0
  return 0;
1300
0
}
1301
1302
0
unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1303
0
  if (RetVT.SimpleTy != MVT::v2i64)
1304
0
    return 0;
1305
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1306
0
    return fastEmitInst_rr(Mips::ADDV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1307
0
  }
1308
0
  return 0;
1309
0
}
1310
1311
6
unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1312
6
  switch (VT.SimpleTy) {
1313
6
  case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1314
6
  
case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1315
6
  
case MVT::v4i8: return fastEmit_ISD_ADD_MVT_v4i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1316
6
  
case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1317
6
  
case MVT::v2i16: return fastEmit_ISD_ADD_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1318
6
  
case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1319
6
  
case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1320
6
  
case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1321
6
  
default: return 00
;
1322
6
  }
1323
6
}
1324
1325
// FastEmit functions for ISD::ADDC.
1326
1327
0
unsigned fastEmit_ISD_ADDC_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1328
0
  if (RetVT.SimpleTy != MVT::i32)
1329
0
    return 0;
1330
0
  if ((Subtarget->hasDSP())) {
1331
0
    return fastEmitInst_rr(Mips::ADDSC, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1332
0
  }
1333
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP())) {
1334
0
    return fastEmitInst_rr(Mips::ADDu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1335
0
  }
1336
0
  return 0;
1337
0
}
1338
1339
0
unsigned fastEmit_ISD_ADDC_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1340
0
  if (RetVT.SimpleTy != MVT::i64)
1341
0
    return 0;
1342
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->hasDSP()) && (!Subtarget->inMicroMipsMode())) {
1343
0
    return fastEmitInst_rr(Mips::DADDu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1344
0
  }
1345
0
  return 0;
1346
0
}
1347
1348
unsigned fastEmit_ISD_ADDC_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1349
  switch (VT.SimpleTy) {
1350
  case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1351
  case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1352
  default: return 0;
1353
  }
1354
}
1355
1356
// FastEmit functions for ISD::ADDE.
1357
1358
0
unsigned fastEmit_ISD_ADDE_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1359
0
  if (RetVT.SimpleTy != MVT::i32)
1360
0
    return 0;
1361
0
  if ((Subtarget->hasDSP())) {
1362
0
    return fastEmitInst_rr(Mips::ADDWC, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1363
0
  }
1364
0
  return 0;
1365
0
}
1366
1367
unsigned fastEmit_ISD_ADDE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1368
  switch (VT.SimpleTy) {
1369
  case MVT::i32: return fastEmit_ISD_ADDE_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1370
  default: return 0;
1371
  }
1372
}
1373
1374
// FastEmit functions for ISD::AND.
1375
1376
5
unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1377
5
  if (RetVT.SimpleTy != MVT::i32)
1378
0
    return 0;
1379
5
  if ((Subtarget->inMips16Mode())) {
1380
0
    return fastEmitInst_rr(Mips::AndRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1381
0
  }
1382
5
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->inMicroMipsMode())0
) {
1383
0
    return fastEmitInst_rr(Mips::AND_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1384
0
  }
1385
5
  if ((Subtarget->inMicroMipsMode()) && 
(!Subtarget->hasMips32r6())0
) {
1386
0
    return fastEmitInst_rr(Mips::AND_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1387
0
  }
1388
5
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1389
5
    return fastEmitInst_rr(Mips::AND, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1390
5
  }
1391
0
  return 0;
1392
0
}
1393
1394
0
unsigned fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1395
0
  if (RetVT.SimpleTy != MVT::i64)
1396
0
    return 0;
1397
0
  if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
1398
0
    return fastEmitInst_rr(Mips::AND64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1399
0
  }
1400
0
  return 0;
1401
0
}
1402
1403
0
unsigned fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1404
0
  if (RetVT.SimpleTy != MVT::v16i8)
1405
0
    return 0;
1406
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1407
0
    return fastEmitInst_rr(Mips::AND_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1408
0
  }
1409
0
  return 0;
1410
0
}
1411
1412
0
unsigned fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1413
0
  if (RetVT.SimpleTy != MVT::v8i16)
1414
0
    return 0;
1415
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1416
0
    return fastEmitInst_rr(Mips::AND_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1417
0
  }
1418
0
  return 0;
1419
0
}
1420
1421
0
unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1422
0
  if (RetVT.SimpleTy != MVT::v4i32)
1423
0
    return 0;
1424
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1425
0
    return fastEmitInst_rr(Mips::AND_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1426
0
  }
1427
0
  return 0;
1428
0
}
1429
1430
0
unsigned fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1431
0
  if (RetVT.SimpleTy != MVT::v2i64)
1432
0
    return 0;
1433
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1434
0
    return fastEmitInst_rr(Mips::AND_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1435
0
  }
1436
0
  return 0;
1437
0
}
1438
1439
5
unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1440
5
  switch (VT.SimpleTy) {
1441
5
  case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1442
5
  
case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1443
5
  
case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1444
5
  
case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1445
5
  
case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1446
5
  
case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1447
5
  
default: return 00
;
1448
5
  }
1449
5
}
1450
1451
// FastEmit functions for ISD::FADD.
1452
1453
0
unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1454
0
  if (RetVT.SimpleTy != MVT::f32)
1455
0
    return 0;
1456
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1457
0
    return fastEmitInst_rr(Mips::FADD_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1458
0
  }
1459
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1460
0
    return fastEmitInst_rr(Mips::FADD_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1461
0
  }
1462
0
  return 0;
1463
0
}
1464
1465
0
unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1466
0
  if (RetVT.SimpleTy != MVT::f64)
1467
0
    return 0;
1468
0
  if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
1469
0
    return fastEmitInst_rr(Mips::FADD_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1470
0
  }
1471
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1472
0
    return fastEmitInst_rr(Mips::FADD_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1473
0
  }
1474
0
  if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1475
0
    return fastEmitInst_rr(Mips::FADD_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1476
0
  }
1477
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1478
0
    return fastEmitInst_rr(Mips::FADD_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1479
0
  }
1480
0
  return 0;
1481
0
}
1482
1483
0
unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1484
0
  if (RetVT.SimpleTy != MVT::v4f32)
1485
0
    return 0;
1486
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1487
0
    return fastEmitInst_rr(Mips::FADD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1488
0
  }
1489
0
  return 0;
1490
0
}
1491
1492
0
unsigned fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1493
0
  if (RetVT.SimpleTy != MVT::v2f64)
1494
0
    return 0;
1495
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1496
0
    return fastEmitInst_rr(Mips::FADD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1497
0
  }
1498
0
  return 0;
1499
0
}
1500
1501
unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1502
  switch (VT.SimpleTy) {
1503
  case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1504
  case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1505
  case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1506
  case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1507
  default: return 0;
1508
  }
1509
}
1510
1511
// FastEmit functions for ISD::FDIV.
1512
1513
0
unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1514
0
  if (RetVT.SimpleTy != MVT::f32)
1515
0
    return 0;
1516
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1517
0
    return fastEmitInst_rr(Mips::FDIV_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1518
0
  }
1519
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1520
0
    return fastEmitInst_rr(Mips::FDIV_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1521
0
  }
1522
0
  return 0;
1523
0
}
1524
1525
0
unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1526
0
  if (RetVT.SimpleTy != MVT::f64)
1527
0
    return 0;
1528
0
  if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
1529
0
    return fastEmitInst_rr(Mips::FDIV_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1530
0
  }
1531
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1532
0
    return fastEmitInst_rr(Mips::FDIV_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1533
0
  }
1534
0
  if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1535
0
    return fastEmitInst_rr(Mips::FDIV_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1536
0
  }
1537
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1538
0
    return fastEmitInst_rr(Mips::FDIV_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1539
0
  }
1540
0
  return 0;
1541
0
}
1542
1543
0
unsigned fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1544
0
  if (RetVT.SimpleTy != MVT::v4f32)
1545
0
    return 0;
1546
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1547
0
    return fastEmitInst_rr(Mips::FDIV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1548
0
  }
1549
0
  return 0;
1550
0
}
1551
1552
0
unsigned fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1553
0
  if (RetVT.SimpleTy != MVT::v2f64)
1554
0
    return 0;
1555
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1556
0
    return fastEmitInst_rr(Mips::FDIV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1557
0
  }
1558
0
  return 0;
1559
0
}
1560
1561
unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1562
  switch (VT.SimpleTy) {
1563
  case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1564
  case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1565
  case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1566
  case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1567
  default: return 0;
1568
  }
1569
}
1570
1571
// FastEmit functions for ISD::FMUL.
1572
1573
0
unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1574
0
  if (RetVT.SimpleTy != MVT::f32)
1575
0
    return 0;
1576
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1577
0
    return fastEmitInst_rr(Mips::FMUL_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1578
0
  }
1579
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1580
0
    return fastEmitInst_rr(Mips::FMUL_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1581
0
  }
1582
0
  return 0;
1583
0
}
1584
1585
0
unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1586
0
  if (RetVT.SimpleTy != MVT::f64)
1587
0
    return 0;
1588
0
  if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
1589
0
    return fastEmitInst_rr(Mips::FMUL_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1590
0
  }
1591
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1592
0
    return fastEmitInst_rr(Mips::FMUL_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1593
0
  }
1594
0
  if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1595
0
    return fastEmitInst_rr(Mips::FMUL_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1596
0
  }
1597
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1598
0
    return fastEmitInst_rr(Mips::FMUL_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1599
0
  }
1600
0
  return 0;
1601
0
}
1602
1603
0
unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1604
0
  if (RetVT.SimpleTy != MVT::v4f32)
1605
0
    return 0;
1606
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1607
0
    return fastEmitInst_rr(Mips::FMUL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1608
0
  }
1609
0
  return 0;
1610
0
}
1611
1612
0
unsigned fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1613
0
  if (RetVT.SimpleTy != MVT::v2f64)
1614
0
    return 0;
1615
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1616
0
    return fastEmitInst_rr(Mips::FMUL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1617
0
  }
1618
0
  return 0;
1619
0
}
1620
1621
unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1622
  switch (VT.SimpleTy) {
1623
  case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1624
  case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1625
  case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1626
  case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1627
  default: return 0;
1628
  }
1629
}
1630
1631
// FastEmit functions for ISD::FSUB.
1632
1633
0
unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1634
0
  if (RetVT.SimpleTy != MVT::f32)
1635
0
    return 0;
1636
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1637
0
    return fastEmitInst_rr(Mips::FSUB_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1638
0
  }
1639
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1640
0
    return fastEmitInst_rr(Mips::FSUB_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1641
0
  }
1642
0
  return 0;
1643
0
}
1644
1645
0
unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1646
0
  if (RetVT.SimpleTy != MVT::f64)
1647
0
    return 0;
1648
0
  if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
1649
0
    return fastEmitInst_rr(Mips::FSUB_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1650
0
  }
1651
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1652
0
    return fastEmitInst_rr(Mips::FSUB_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1653
0
  }
1654
0
  if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1655
0
    return fastEmitInst_rr(Mips::FSUB_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1656
0
  }
1657
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1658
0
    return fastEmitInst_rr(Mips::FSUB_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1659
0
  }
1660
0
  return 0;
1661
0
}
1662
1663
0
unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1664
0
  if (RetVT.SimpleTy != MVT::v4f32)
1665
0
    return 0;
1666
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1667
0
    return fastEmitInst_rr(Mips::FSUB_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1668
0
  }
1669
0
  return 0;
1670
0
}
1671
1672
0
unsigned fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1673
0
  if (RetVT.SimpleTy != MVT::v2f64)
1674
0
    return 0;
1675
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1676
0
    return fastEmitInst_rr(Mips::FSUB_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1677
0
  }
1678
0
  return 0;
1679
0
}
1680
1681
unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1682
  switch (VT.SimpleTy) {
1683
  case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1684
  case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1685
  case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1686
  case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1687
  default: return 0;
1688
  }
1689
}
1690
1691
// FastEmit functions for ISD::MUL.
1692
1693
2
unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1694
2
  if (RetVT.SimpleTy != MVT::i32)
1695
0
    return 0;
1696
2
  if ((Subtarget->inMips16Mode())) {
1697
0
    return fastEmitInst_rr(Mips::MultRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1698
0
  }
1699
2
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->inMicroMipsMode())0
) {
1700
0
    return fastEmitInst_rr(Mips::MUL_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1701
0
  }
1702
2
  if ((Subtarget->inMicroMipsMode()) && 
(!Subtarget->hasMips32r6())0
) {
1703
0
    return fastEmitInst_rr(Mips::MUL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1704
0
  }
1705
2
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->hasStandardEncoding())0
&&
(!Subtarget->inMicroMipsMode())0
) {
1706
0
    return fastEmitInst_rr(Mips::MUL_R6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1707
0
  }
1708
2
  if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1709
2
    return fastEmitInst_rr(Mips::MUL, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1710
2
  }
1711
0
  return 0;
1712
0
}
1713
1714
0
unsigned fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1715
0
  if (RetVT.SimpleTy != MVT::i64)
1716
0
    return 0;
1717
0
  if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1718
0
    return fastEmitInst_rr(Mips::DMUL_R6, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1719
0
  }
1720
0
  if ((Subtarget->hasCnMips())) {
1721
0
    return fastEmitInst_rr(Mips::DMUL, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1722
0
  }
1723
0
  return 0;
1724
0
}
1725
1726
0
unsigned fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1727
0
  if (RetVT.SimpleTy != MVT::v16i8)
1728
0
    return 0;
1729
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1730
0
    return fastEmitInst_rr(Mips::MULV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1731
0
  }
1732
0
  return 0;
1733
0
}
1734
1735
0
unsigned fastEmit_ISD_MUL_MVT_v2i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1736
0
  if (RetVT.SimpleTy != MVT::v2i16)
1737
0
    return 0;
1738
0
  if ((Subtarget->hasDSPR2())) {
1739
0
    return fastEmitInst_rr(Mips::MUL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1740
0
  }
1741
0
  return 0;
1742
0
}
1743
1744
0
unsigned fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1745
0
  if (RetVT.SimpleTy != MVT::v8i16)
1746
0
    return 0;
1747
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1748
0
    return fastEmitInst_rr(Mips::MULV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1749
0
  }
1750
0
  return 0;
1751
0
}
1752
1753
0
unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1754
0
  if (RetVT.SimpleTy != MVT::v4i32)
1755
0
    return 0;
1756
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1757
0
    return fastEmitInst_rr(Mips::MULV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1758
0
  }
1759
0
  return 0;
1760
0
}
1761
1762
0
unsigned fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1763
0
  if (RetVT.SimpleTy != MVT::v2i64)
1764
0
    return 0;
1765
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1766
0
    return fastEmitInst_rr(Mips::MULV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1767
0
  }
1768
0
  return 0;
1769
0
}
1770
1771
2
unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1772
2
  switch (VT.SimpleTy) {
1773
2
  case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1774
2
  
case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1775
2
  
case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1776
2
  
case MVT::v2i16: return fastEmit_ISD_MUL_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1777
2
  
case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1778
2
  
case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1779
2
  
case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1780
2
  
default: return 00
;
1781
2
  }
1782
2
}
1783
1784
// FastEmit functions for ISD::MULHS.
1785
1786
0
unsigned fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1787
0
  if (RetVT.SimpleTy != MVT::i32)
1788
0
    return 0;
1789
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1790
0
    return fastEmitInst_rr(Mips::MUH_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1791
0
  }
1792
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1793
0
    return fastEmitInst_rr(Mips::MUH, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1794
0
  }
1795
0
  return 0;
1796
0
}
1797
1798
0
unsigned fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1799
0
  if (RetVT.SimpleTy != MVT::i64)
1800
0
    return 0;
1801
0
  if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1802
0
    return fastEmitInst_rr(Mips::DMUH, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1803
0
  }
1804
0
  return 0;
1805
0
}
1806
1807
unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1808
  switch (VT.SimpleTy) {
1809
  case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1810
  case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1811
  default: return 0;
1812
  }
1813
}
1814
1815
// FastEmit functions for ISD::MULHU.
1816
1817
0
unsigned fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1818
0
  if (RetVT.SimpleTy != MVT::i32)
1819
0
    return 0;
1820
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1821
0
    return fastEmitInst_rr(Mips::MUHU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1822
0
  }
1823
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1824
0
    return fastEmitInst_rr(Mips::MUHU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1825
0
  }
1826
0
  return 0;
1827
0
}
1828
1829
0
unsigned fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1830
0
  if (RetVT.SimpleTy != MVT::i64)
1831
0
    return 0;
1832
0
  if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1833
0
    return fastEmitInst_rr(Mips::DMUHU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1834
0
  }
1835
0
  return 0;
1836
0
}
1837
1838
unsigned fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1839
  switch (VT.SimpleTy) {
1840
  case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1841
  case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1842
  default: return 0;
1843
  }
1844
}
1845
1846
// FastEmit functions for ISD::OR.
1847
1848
4
unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1849
4
  if (RetVT.SimpleTy != MVT::i32)
1850
0
    return 0;
1851
4
  if ((Subtarget->inMips16Mode())) {
1852
0
    return fastEmitInst_rr(Mips::OrRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1853
0
  }
1854
4
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->inMicroMipsMode())0
) {
1855
0
    return fastEmitInst_rr(Mips::OR_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1856
0
  }
1857
4
  if ((Subtarget->inMicroMipsMode()) && 
(!Subtarget->hasMips32r6())0
) {
1858
0
    return fastEmitInst_rr(Mips::OR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1859
0
  }
1860
4
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1861
4
    return fastEmitInst_rr(Mips::OR, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1862
4
  }
1863
0
  return 0;
1864
0
}
1865
1866
0
unsigned fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1867
0
  if (RetVT.SimpleTy != MVT::i64)
1868
0
    return 0;
1869
0
  if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
1870
0
    return fastEmitInst_rr(Mips::OR64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1871
0
  }
1872
0
  return 0;
1873
0
}
1874
1875
0
unsigned fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1876
0
  if (RetVT.SimpleTy != MVT::v16i8)
1877
0
    return 0;
1878
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1879
0
    return fastEmitInst_rr(Mips::OR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1880
0
  }
1881
0
  return 0;
1882
0
}
1883
1884
0
unsigned fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1885
0
  if (RetVT.SimpleTy != MVT::v8i16)
1886
0
    return 0;
1887
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1888
0
    return fastEmitInst_rr(Mips::OR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1889
0
  }
1890
0
  return 0;
1891
0
}
1892
1893
0
unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1894
0
  if (RetVT.SimpleTy != MVT::v4i32)
1895
0
    return 0;
1896
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1897
0
    return fastEmitInst_rr(Mips::OR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1898
0
  }
1899
0
  return 0;
1900
0
}
1901
1902
0
unsigned fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1903
0
  if (RetVT.SimpleTy != MVT::v2i64)
1904
0
    return 0;
1905
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1906
0
    return fastEmitInst_rr(Mips::OR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1907
0
  }
1908
0
  return 0;
1909
0
}
1910
1911
4
unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1912
4
  switch (VT.SimpleTy) {
1913
4
  case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1914
4
  
case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1915
4
  
case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1916
4
  
case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1917
4
  
case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1918
4
  
case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1919
4
  
default: return 00
;
1920
4
  }
1921
4
}
1922
1923
// FastEmit functions for ISD::ROTR.
1924
1925
0
unsigned fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1926
0
  if (RetVT.SimpleTy != MVT::i32)
1927
0
    return 0;
1928
0
  if ((Subtarget->inMicroMipsMode())) {
1929
0
    return fastEmitInst_rr(Mips::ROTRV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1930
0
  }
1931
0
  if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1932
0
    return fastEmitInst_rr(Mips::ROTRV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1933
0
  }
1934
0
  return 0;
1935
0
}
1936
1937
unsigned fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1938
  switch (VT.SimpleTy) {
1939
  case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1940
  default: return 0;
1941
  }
1942
}
1943
1944
// FastEmit functions for ISD::SDIV.
1945
1946
4
unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1947
4
  if (RetVT.SimpleTy != MVT::i32)
1948
0
    return 0;
1949
4
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->inMicroMipsMode())0
) {
1950
0
    return fastEmitInst_rr(Mips::DIV_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1951
0
  }
1952
4
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->hasStandardEncoding())0
&&
(!Subtarget->inMicroMipsMode())0
) {
1953
0
    return fastEmitInst_rr(Mips::DIV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1954
0
  }
1955
4
  return 0;
1956
4
}
1957
1958
0
unsigned fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1959
0
  if (RetVT.SimpleTy != MVT::i64)
1960
0
    return 0;
1961
0
  if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1962
0
    return fastEmitInst_rr(Mips::DDIV, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1963
0
  }
1964
0
  return 0;
1965
0
}
1966
1967
0
unsigned fastEmit_ISD_SDIV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1968
0
  if (RetVT.SimpleTy != MVT::v16i8)
1969
0
    return 0;
1970
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1971
0
    return fastEmitInst_rr(Mips::DIV_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1972
0
  }
1973
0
  return 0;
1974
0
}
1975
1976
0
unsigned fastEmit_ISD_SDIV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1977
0
  if (RetVT.SimpleTy != MVT::v8i16)
1978
0
    return 0;
1979
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1980
0
    return fastEmitInst_rr(Mips::DIV_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1981
0
  }
1982
0
  return 0;
1983
0
}
1984
1985
0
unsigned fastEmit_ISD_SDIV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1986
0
  if (RetVT.SimpleTy != MVT::v4i32)
1987
0
    return 0;
1988
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1989
0
    return fastEmitInst_rr(Mips::DIV_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1990
0
  }
1991
0
  return 0;
1992
0
}
1993
1994
0
unsigned fastEmit_ISD_SDIV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1995
0
  if (RetVT.SimpleTy != MVT::v2i64)
1996
0
    return 0;
1997
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1998
0
    return fastEmitInst_rr(Mips::DIV_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1999
0
  }
2000
0
  return 0;
2001
0
}
2002
2003
4
unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2004
4
  switch (VT.SimpleTy) {
2005
4
  case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2006
4
  
case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2007
4
  
case MVT::v16i8: return fastEmit_ISD_SDIV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2008
4
  
case MVT::v8i16: return fastEmit_ISD_SDIV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2009
4
  
case MVT::v4i32: return fastEmit_ISD_SDIV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2010
4
  
case MVT::v2i64: return fastEmit_ISD_SDIV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2011
4
  
default: return 00
;
2012
4
  }
2013
4
}
2014
2015
// FastEmit functions for ISD::SHL.
2016
2017
0
unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2018
0
  if (RetVT.SimpleTy != MVT::i32)
2019
0
    return 0;
2020
0
  if ((Subtarget->inMicroMipsMode())) {
2021
0
    return fastEmitInst_rr(Mips::SLLV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2022
0
  }
2023
0
  if ((Subtarget->inMips16Mode())) {
2024
0
    return fastEmitInst_rr(Mips::SllvRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2025
0
  }
2026
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2027
0
    return fastEmitInst_rr(Mips::SLLV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2028
0
  }
2029
0
  return 0;
2030
0
}
2031
2032
0
unsigned fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2033
0
  if (RetVT.SimpleTy != MVT::v16i8)
2034
0
    return 0;
2035
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2036
0
    return fastEmitInst_rr(Mips::SLL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2037
0
  }
2038
0
  return 0;
2039
0
}
2040
2041
0
unsigned fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2042
0
  if (RetVT.SimpleTy != MVT::v8i16)
2043
0
    return 0;
2044
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2045
0
    return fastEmitInst_rr(Mips::SLL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2046
0
  }
2047
0
  return 0;
2048
0
}
2049
2050
0
unsigned fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2051
0
  if (RetVT.SimpleTy != MVT::v4i32)
2052
0
    return 0;
2053
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2054
0
    return fastEmitInst_rr(Mips::SLL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2055
0
  }
2056
0
  return 0;
2057
0
}
2058
2059
0
unsigned fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2060
0
  if (RetVT.SimpleTy != MVT::v2i64)
2061
0
    return 0;
2062
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2063
0
    return fastEmitInst_rr(Mips::SLL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2064
0
  }
2065
0
  return 0;
2066
0
}
2067
2068
unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2069
  switch (VT.SimpleTy) {
2070
  case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2071
  case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2072
  case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2073
  case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2074
  case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2075
  default: return 0;
2076
  }
2077
}
2078
2079
// FastEmit functions for ISD::SMAX.
2080
2081
0
unsigned fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2082
0
  if (RetVT.SimpleTy != MVT::v16i8)
2083
0
    return 0;
2084
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2085
0
    return fastEmitInst_rr(Mips::MAX_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2086
0
  }
2087
0
  return 0;
2088
0
}
2089
2090
0
unsigned fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2091
0
  if (RetVT.SimpleTy != MVT::v8i16)
2092
0
    return 0;
2093
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2094
0
    return fastEmitInst_rr(Mips::MAX_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2095
0
  }
2096
0
  return 0;
2097
0
}
2098
2099
0
unsigned fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2100
0
  if (RetVT.SimpleTy != MVT::v4i32)
2101
0
    return 0;
2102
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2103
0
    return fastEmitInst_rr(Mips::MAX_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2104
0
  }
2105
0
  return 0;
2106
0
}
2107
2108
0
unsigned fastEmit_ISD_SMAX_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2109
0
  if (RetVT.SimpleTy != MVT::v2i64)
2110
0
    return 0;
2111
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2112
0
    return fastEmitInst_rr(Mips::MAX_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2113
0
  }
2114
0
  return 0;
2115
0
}
2116
2117
unsigned fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2118
  switch (VT.SimpleTy) {
2119
  case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2120
  case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2121
  case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2122
  case MVT::v2i64: return fastEmit_ISD_SMAX_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2123
  default: return 0;
2124
  }
2125
}
2126
2127
// FastEmit functions for ISD::SMIN.
2128
2129
0
unsigned fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2130
0
  if (RetVT.SimpleTy != MVT::v16i8)
2131
0
    return 0;
2132
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2133
0
    return fastEmitInst_rr(Mips::MIN_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2134
0
  }
2135
0
  return 0;
2136
0
}
2137
2138
0
unsigned fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2139
0
  if (RetVT.SimpleTy != MVT::v8i16)
2140
0
    return 0;
2141
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2142
0
    return fastEmitInst_rr(Mips::MIN_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2143
0
  }
2144
0
  return 0;
2145
0
}
2146
2147
0
unsigned fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2148
0
  if (RetVT.SimpleTy != MVT::v4i32)
2149
0
    return 0;
2150
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2151
0
    return fastEmitInst_rr(Mips::MIN_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2152
0
  }
2153
0
  return 0;
2154
0
}
2155
2156
0
unsigned fastEmit_ISD_SMIN_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2157
0
  if (RetVT.SimpleTy != MVT::v2i64)
2158
0
    return 0;
2159
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2160
0
    return fastEmitInst_rr(Mips::MIN_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2161
0
  }
2162
0
  return 0;
2163
0
}
2164
2165
unsigned fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2166
  switch (VT.SimpleTy) {
2167
  case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2168
  case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2169
  case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2170
  case MVT::v2i64: return fastEmit_ISD_SMIN_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2171
  default: return 0;
2172
  }
2173
}
2174
2175
// FastEmit functions for ISD::SRA.
2176
2177
0
unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2178
0
  if (RetVT.SimpleTy != MVT::i32)
2179
0
    return 0;
2180
0
  if ((Subtarget->inMicroMipsMode())) {
2181
0
    return fastEmitInst_rr(Mips::SRAV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2182
0
  }
2183
0
  if ((Subtarget->inMips16Mode())) {
2184
0
    return fastEmitInst_rr(Mips::SravRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2185
0
  }
2186
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2187
0
    return fastEmitInst_rr(Mips::SRAV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2188
0
  }
2189
0
  return 0;
2190
0
}
2191
2192
0
unsigned fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2193
0
  if (RetVT.SimpleTy != MVT::v16i8)
2194
0
    return 0;
2195
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2196
0
    return fastEmitInst_rr(Mips::SRA_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2197
0
  }
2198
0
  return 0;
2199
0
}
2200
2201
0
unsigned fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2202
0
  if (RetVT.SimpleTy != MVT::v8i16)
2203
0
    return 0;
2204
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2205
0
    return fastEmitInst_rr(Mips::SRA_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2206
0
  }
2207
0
  return 0;
2208
0
}
2209
2210
0
unsigned fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2211
0
  if (RetVT.SimpleTy != MVT::v4i32)
2212
0
    return 0;
2213
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2214
0
    return fastEmitInst_rr(Mips::SRA_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2215
0
  }
2216
0
  return 0;
2217
0
}
2218
2219
0
unsigned fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2220
0
  if (RetVT.SimpleTy != MVT::v2i64)
2221
0
    return 0;
2222
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2223
0
    return fastEmitInst_rr(Mips::SRA_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2224
0
  }
2225
0
  return 0;
2226
0
}
2227
2228
unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2229
  switch (VT.SimpleTy) {
2230
  case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2231
  case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2232
  case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2233
  case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2234
  case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2235
  default: return 0;
2236
  }
2237
}
2238
2239
// FastEmit functions for ISD::SREM.
2240
2241
4
unsigned fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2242
4
  if (RetVT.SimpleTy != MVT::i32)
2243
0
    return 0;
2244
4
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->inMicroMipsMode())0
) {
2245
0
    return fastEmitInst_rr(Mips::MOD_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2246
0
  }
2247
4
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->hasStandardEncoding())0
&&
(!Subtarget->inMicroMipsMode())0
) {
2248
0
    return fastEmitInst_rr(Mips::MOD, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2249
0
  }
2250
4
  return 0;
2251
4
}
2252
2253
0
unsigned fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2254
0
  if (RetVT.SimpleTy != MVT::i64)
2255
0
    return 0;
2256
0
  if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2257
0
    return fastEmitInst_rr(Mips::DMOD, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2258
0
  }
2259
0
  return 0;
2260
0
}
2261
2262
0
unsigned fastEmit_ISD_SREM_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2263
0
  if (RetVT.SimpleTy != MVT::v16i8)
2264
0
    return 0;
2265
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2266
0
    return fastEmitInst_rr(Mips::MOD_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2267
0
  }
2268
0
  return 0;
2269
0
}
2270
2271
0
unsigned fastEmit_ISD_SREM_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2272
0
  if (RetVT.SimpleTy != MVT::v8i16)
2273
0
    return 0;
2274
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2275
0
    return fastEmitInst_rr(Mips::MOD_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2276
0
  }
2277
0
  return 0;
2278
0
}
2279
2280
0
unsigned fastEmit_ISD_SREM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2281
0
  if (RetVT.SimpleTy != MVT::v4i32)
2282
0
    return 0;
2283
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2284
0
    return fastEmitInst_rr(Mips::MOD_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2285
0
  }
2286
0
  return 0;
2287
0
}
2288
2289
0
unsigned fastEmit_ISD_SREM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2290
0
  if (RetVT.SimpleTy != MVT::v2i64)
2291
0
    return 0;
2292
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2293
0
    return fastEmitInst_rr(Mips::MOD_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2294
0
  }
2295
0
  return 0;
2296
0
}
2297
2298
4
unsigned fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2299
4
  switch (VT.SimpleTy) {
2300
4
  case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2301
4
  
case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2302
4
  
case MVT::v16i8: return fastEmit_ISD_SREM_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2303
4
  
case MVT::v8i16: return fastEmit_ISD_SREM_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2304
4
  
case MVT::v4i32: return fastEmit_ISD_SREM_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2305
4
  
case MVT::v2i64: return fastEmit_ISD_SREM_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2306
4
  
default: return 00
;
2307
4
  }
2308
4
}
2309
2310
// FastEmit functions for ISD::SRL.
2311
2312
0
unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2313
0
  if (RetVT.SimpleTy != MVT::i32)
2314
0
    return 0;
2315
0
  if ((Subtarget->inMicroMipsMode())) {
2316
0
    return fastEmitInst_rr(Mips::SRLV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2317
0
  }
2318
0
  if ((Subtarget->inMips16Mode())) {
2319
0
    return fastEmitInst_rr(Mips::SrlvRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2320
0
  }
2321
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2322
0
    return fastEmitInst_rr(Mips::SRLV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2323
0
  }
2324
0
  return 0;
2325
0
}
2326
2327
0
unsigned fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2328
0
  if (RetVT.SimpleTy != MVT::v16i8)
2329
0
    return 0;
2330
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2331
0
    return fastEmitInst_rr(Mips::SRL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2332
0
  }
2333
0
  return 0;
2334
0
}
2335
2336
0
unsigned fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2337
0
  if (RetVT.SimpleTy != MVT::v8i16)
2338
0
    return 0;
2339
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2340
0
    return fastEmitInst_rr(Mips::SRL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2341
0
  }
2342
0
  return 0;
2343
0
}
2344
2345
0
unsigned fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2346
0
  if (RetVT.SimpleTy != MVT::v4i32)
2347
0
    return 0;
2348
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2349
0
    return fastEmitInst_rr(Mips::SRL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2350
0
  }
2351
0
  return 0;
2352
0
}
2353
2354
0
unsigned fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2355
0
  if (RetVT.SimpleTy != MVT::v2i64)
2356
0
    return 0;
2357
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2358
0
    return fastEmitInst_rr(Mips::SRL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2359
0
  }
2360
0
  return 0;
2361
0
}
2362
2363
unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2364
  switch (VT.SimpleTy) {
2365
  case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2366
  case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2367
  case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2368
  case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2369
  case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2370
  default: return 0;
2371
  }
2372
}
2373
2374
// FastEmit functions for ISD::SUB.
2375
2376
0
unsigned fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2377
0
  if (RetVT.SimpleTy != MVT::i32)
2378
0
    return 0;
2379
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2380
0
    return fastEmitInst_rr(Mips::SUBU16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2381
0
  }
2382
0
  if ((Subtarget->inMips16Mode())) {
2383
0
    return fastEmitInst_rr(Mips::SubuRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2384
0
  }
2385
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
2386
0
    return fastEmitInst_rr(Mips::SUBu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2387
0
  }
2388
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2389
0
    return fastEmitInst_rr(Mips::SUBu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2390
0
  }
2391
0
  return 0;
2392
0
}
2393
2394
0
unsigned fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2395
0
  if (RetVT.SimpleTy != MVT::i64)
2396
0
    return 0;
2397
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2398
0
    return fastEmitInst_rr(Mips::DSUBu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2399
0
  }
2400
0
  return 0;
2401
0
}
2402
2403
0
unsigned fastEmit_ISD_SUB_MVT_v4i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2404
0
  if (RetVT.SimpleTy != MVT::v4i8)
2405
0
    return 0;
2406
0
  if ((Subtarget->hasDSP())) {
2407
0
    return fastEmitInst_rr(Mips::SUBU_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2408
0
  }
2409
0
  return 0;
2410
0
}
2411
2412
0
unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2413
0
  if (RetVT.SimpleTy != MVT::v16i8)
2414
0
    return 0;
2415
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2416
0
    return fastEmitInst_rr(Mips::SUBV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2417
0
  }
2418
0
  return 0;
2419
0
}
2420
2421
0
unsigned fastEmit_ISD_SUB_MVT_v2i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2422
0
  if (RetVT.SimpleTy != MVT::v2i16)
2423
0
    return 0;
2424
0
  if ((Subtarget->hasDSP())) {
2425
0
    return fastEmitInst_rr(Mips::SUBQ_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2426
0
  }
2427
0
  return 0;
2428
0
}
2429
2430
0
unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2431
0
  if (RetVT.SimpleTy != MVT::v8i16)
2432
0
    return 0;
2433
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2434
0
    return fastEmitInst_rr(Mips::SUBV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2435
0
  }
2436
0
  return 0;
2437
0
}
2438
2439
0
unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2440
0
  if (RetVT.SimpleTy != MVT::v4i32)
2441
0
    return 0;
2442
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2443
0
    return fastEmitInst_rr(Mips::SUBV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2444
0
  }
2445
0
  return 0;
2446
0
}
2447
2448
0
unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2449
0
  if (RetVT.SimpleTy != MVT::v2i64)
2450
0
    return 0;
2451
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2452
0
    return fastEmitInst_rr(Mips::SUBV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2453
0
  }
2454
0
  return 0;
2455
0
}
2456
2457
unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2458
  switch (VT.SimpleTy) {
2459
  case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2460
  case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2461
  case MVT::v4i8: return fastEmit_ISD_SUB_MVT_v4i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2462
  case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2463
  case MVT::v2i16: return fastEmit_ISD_SUB_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2464
  case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2465
  case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2466
  case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2467
  default: return 0;
2468
  }
2469
}
2470
2471
// FastEmit functions for ISD::SUBC.
2472
2473
0
unsigned fastEmit_ISD_SUBC_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2474
0
  if (RetVT.SimpleTy != MVT::i32)
2475
0
    return 0;
2476
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2477
0
    return fastEmitInst_rr(Mips::SUBU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2478
0
  }
2479
0
  if ((Subtarget->inMicroMipsMode())) {
2480
0
    return fastEmitInst_rr(Mips::SUBu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2481
0
  }
2482
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2483
0
    return fastEmitInst_rr(Mips::SUBu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2484
0
  }
2485
0
  return 0;
2486
0
}
2487
2488
0
unsigned fastEmit_ISD_SUBC_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2489
0
  if (RetVT.SimpleTy != MVT::i64)
2490
0
    return 0;
2491
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())) {
2492
0
    return fastEmitInst_rr(Mips::DSUBu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2493
0
  }
2494
0
  return 0;
2495
0
}
2496
2497
unsigned fastEmit_ISD_SUBC_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2498
  switch (VT.SimpleTy) {
2499
  case MVT::i32: return fastEmit_ISD_SUBC_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2500
  case MVT::i64: return fastEmit_ISD_SUBC_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2501
  default: return 0;
2502
  }
2503
}
2504
2505
// FastEmit functions for ISD::UDIV.
2506
2507
4
unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2508
4
  if (RetVT.SimpleTy != MVT::i32)
2509
0
    return 0;
2510
4
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->inMicroMipsMode())0
) {
2511
0
    return fastEmitInst_rr(Mips::DIVU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2512
0
  }
2513
4
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->hasStandardEncoding())0
&&
(!Subtarget->inMicroMipsMode())0
) {
2514
0
    return fastEmitInst_rr(Mips::DIVU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2515
0
  }
2516
4
  return 0;
2517
4
}
2518
2519
0
unsigned fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2520
0
  if (RetVT.SimpleTy != MVT::i64)
2521
0
    return 0;
2522
0
  if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2523
0
    return fastEmitInst_rr(Mips::DDIVU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2524
0
  }
2525
0
  return 0;
2526
0
}
2527
2528
0
unsigned fastEmit_ISD_UDIV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2529
0
  if (RetVT.SimpleTy != MVT::v16i8)
2530
0
    return 0;
2531
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2532
0
    return fastEmitInst_rr(Mips::DIV_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2533
0
  }
2534
0
  return 0;
2535
0
}
2536
2537
0
unsigned fastEmit_ISD_UDIV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2538
0
  if (RetVT.SimpleTy != MVT::v8i16)
2539
0
    return 0;
2540
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2541
0
    return fastEmitInst_rr(Mips::DIV_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2542
0
  }
2543
0
  return 0;
2544
0
}
2545
2546
0
unsigned fastEmit_ISD_UDIV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2547
0
  if (RetVT.SimpleTy != MVT::v4i32)
2548
0
    return 0;
2549
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2550
0
    return fastEmitInst_rr(Mips::DIV_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2551
0
  }
2552
0
  return 0;
2553
0
}
2554
2555
0
unsigned fastEmit_ISD_UDIV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2556
0
  if (RetVT.SimpleTy != MVT::v2i64)
2557
0
    return 0;
2558
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2559
0
    return fastEmitInst_rr(Mips::DIV_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2560
0
  }
2561
0
  return 0;
2562
0
}
2563
2564
4
unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2565
4
  switch (VT.SimpleTy) {
2566
4
  case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2567
4
  
case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2568
4
  
case MVT::v16i8: return fastEmit_ISD_UDIV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2569
4
  
case MVT::v8i16: return fastEmit_ISD_UDIV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2570
4
  
case MVT::v4i32: return fastEmit_ISD_UDIV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2571
4
  
case MVT::v2i64: return fastEmit_ISD_UDIV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2572
4
  
default: return 00
;
2573
4
  }
2574
4
}
2575
2576
// FastEmit functions for ISD::UMAX.
2577
2578
0
unsigned fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2579
0
  if (RetVT.SimpleTy != MVT::v16i8)
2580
0
    return 0;
2581
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2582
0
    return fastEmitInst_rr(Mips::MAX_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2583
0
  }
2584
0
  return 0;
2585
0
}
2586
2587
0
unsigned fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2588
0
  if (RetVT.SimpleTy != MVT::v8i16)
2589
0
    return 0;
2590
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2591
0
    return fastEmitInst_rr(Mips::MAX_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2592
0
  }
2593
0
  return 0;
2594
0
}
2595
2596
0
unsigned fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2597
0
  if (RetVT.SimpleTy != MVT::v4i32)
2598
0
    return 0;
2599
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2600
0
    return fastEmitInst_rr(Mips::MAX_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2601
0
  }
2602
0
  return 0;
2603
0
}
2604
2605
0
unsigned fastEmit_ISD_UMAX_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2606
0
  if (RetVT.SimpleTy != MVT::v2i64)
2607
0
    return 0;
2608
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2609
0
    return fastEmitInst_rr(Mips::MAX_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2610
0
  }
2611
0
  return 0;
2612
0
}
2613
2614
unsigned fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2615
  switch (VT.SimpleTy) {
2616
  case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2617
  case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2618
  case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2619
  case MVT::v2i64: return fastEmit_ISD_UMAX_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2620
  default: return 0;
2621
  }
2622
}
2623
2624
// FastEmit functions for ISD::UMIN.
2625
2626
0
unsigned fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2627
0
  if (RetVT.SimpleTy != MVT::v16i8)
2628
0
    return 0;
2629
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2630
0
    return fastEmitInst_rr(Mips::MIN_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2631
0
  }
2632
0
  return 0;
2633
0
}
2634
2635
0
unsigned fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2636
0
  if (RetVT.SimpleTy != MVT::v8i16)
2637
0
    return 0;
2638
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2639
0
    return fastEmitInst_rr(Mips::MIN_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2640
0
  }
2641
0
  return 0;
2642
0
}
2643
2644
0
unsigned fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2645
0
  if (RetVT.SimpleTy != MVT::v4i32)
2646
0
    return 0;
2647
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2648
0
    return fastEmitInst_rr(Mips::MIN_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2649
0
  }
2650
0
  return 0;
2651
0
}
2652
2653
0
unsigned fastEmit_ISD_UMIN_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2654
0
  if (RetVT.SimpleTy != MVT::v2i64)
2655
0
    return 0;
2656
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2657
0
    return fastEmitInst_rr(Mips::MIN_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2658
0
  }
2659
0
  return 0;
2660
0
}
2661
2662
unsigned fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2663
  switch (VT.SimpleTy) {
2664
  case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2665
  case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2666
  case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2667
  case MVT::v2i64: return fastEmit_ISD_UMIN_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2668
  default: return 0;
2669
  }
2670
}
2671
2672
// FastEmit functions for ISD::UREM.
2673
2674
4
unsigned fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2675
4
  if (RetVT.SimpleTy != MVT::i32)
2676
0
    return 0;
2677
4
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->inMicroMipsMode())0
) {
2678
0
    return fastEmitInst_rr(Mips::MODU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2679
0
  }
2680
4
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->hasStandardEncoding())0
&&
(!Subtarget->inMicroMipsMode())0
) {
2681
0
    return fastEmitInst_rr(Mips::MODU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2682
0
  }
2683
4
  return 0;
2684
4
}
2685
2686
0
unsigned fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2687
0
  if (RetVT.SimpleTy != MVT::i64)
2688
0
    return 0;
2689
0
  if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2690
0
    return fastEmitInst_rr(Mips::DMODU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2691
0
  }
2692
0
  return 0;
2693
0
}
2694
2695
0
unsigned fastEmit_ISD_UREM_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2696
0
  if (RetVT.SimpleTy != MVT::v16i8)
2697
0
    return 0;
2698
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2699
0
    return fastEmitInst_rr(Mips::MOD_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2700
0
  }
2701
0
  return 0;
2702
0
}
2703
2704
0
unsigned fastEmit_ISD_UREM_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2705
0
  if (RetVT.SimpleTy != MVT::v8i16)
2706
0
    return 0;
2707
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2708
0
    return fastEmitInst_rr(Mips::MOD_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2709
0
  }
2710
0
  return 0;
2711
0
}
2712
2713
0
unsigned fastEmit_ISD_UREM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2714
0
  if (RetVT.SimpleTy != MVT::v4i32)
2715
0
    return 0;
2716
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2717
0
    return fastEmitInst_rr(Mips::MOD_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2718
0
  }
2719
0
  return 0;
2720
0
}
2721
2722
0
unsigned fastEmit_ISD_UREM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2723
0
  if (RetVT.SimpleTy != MVT::v2i64)
2724
0
    return 0;
2725
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2726
0
    return fastEmitInst_rr(Mips::MOD_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2727
0
  }
2728
0
  return 0;
2729
0
}
2730
2731
4
unsigned fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2732
4
  switch (VT.SimpleTy) {
2733
4
  case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2734
4
  
case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2735
4
  
case MVT::v16i8: return fastEmit_ISD_UREM_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2736
4
  
case MVT::v8i16: return fastEmit_ISD_UREM_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2737
4
  
case MVT::v4i32: return fastEmit_ISD_UREM_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2738
4
  
case MVT::v2i64: return fastEmit_ISD_UREM_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2739
4
  
default: return 00
;
2740
4
  }
2741
4
}
2742
2743
// FastEmit functions for ISD::XOR.
2744
2745
5
unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2746
5
  if (RetVT.SimpleTy != MVT::i32)
2747
0
    return 0;
2748
5
  if ((Subtarget->inMips16Mode())) {
2749
0
    return fastEmitInst_rr(Mips::XorRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2750
0
  }
2751
5
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->inMicroMipsMode())0
) {
2752
0
    return fastEmitInst_rr(Mips::XOR_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2753
0
  }
2754
5
  if ((Subtarget->inMicroMipsMode()) && 
(!Subtarget->hasMips32r6())0
) {
2755
0
    return fastEmitInst_rr(Mips::XOR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2756
0
  }
2757
5
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2758
5
    return fastEmitInst_rr(Mips::XOR, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2759
5
  }
2760
0
  return 0;
2761
0
}
2762
2763
0
unsigned fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2764
0
  if (RetVT.SimpleTy != MVT::i64)
2765
0
    return 0;
2766
0
  if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
2767
0
    return fastEmitInst_rr(Mips::XOR64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2768
0
  }
2769
0
  return 0;
2770
0
}
2771
2772
0
unsigned fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2773
0
  if (RetVT.SimpleTy != MVT::v16i8)
2774
0
    return 0;
2775
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2776
0
    return fastEmitInst_rr(Mips::XOR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2777
0
  }
2778
0
  return 0;
2779
0
}
2780
2781
0
unsigned fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2782
0
  if (RetVT.SimpleTy != MVT::v8i16)
2783
0
    return 0;
2784
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2785
0
    return fastEmitInst_rr(Mips::XOR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2786
0
  }
2787
0
  return 0;
2788
0
}
2789
2790
0
unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2791
0
  if (RetVT.SimpleTy != MVT::v4i32)
2792
0
    return 0;
2793
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2794
0
    return fastEmitInst_rr(Mips::XOR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2795
0
  }
2796
0
  return 0;
2797
0
}
2798
2799
0
unsigned fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2800
0
  if (RetVT.SimpleTy != MVT::v2i64)
2801
0
    return 0;
2802
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2803
0
    return fastEmitInst_rr(Mips::XOR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2804
0
  }
2805
0
  return 0;
2806
0
}
2807
2808
5
unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2809
5
  switch (VT.SimpleTy) {
2810
5
  case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2811
5
  
case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2812
5
  
case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2813
5
  
case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2814
5
  
case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2815
5
  
case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2816
5
  
default: return 00
;
2817
5
  }
2818
5
}
2819
2820
// FastEmit functions for MipsISD::BuildPairF64.
2821
2822
0
unsigned fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2823
0
  if (RetVT.SimpleTy != MVT::f64)
2824
0
    return 0;
2825
0
  if ((Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())) {
2826
0
    return fastEmitInst_rr(Mips::BuildPairF64_64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2827
0
  }
2828
0
  if ((!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) {
2829
0
    return fastEmitInst_rr(Mips::BuildPairF64, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2830
0
  }
2831
0
  return 0;
2832
0
}
2833
2834
unsigned fastEmit_MipsISD_BuildPairF64_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2835
  switch (VT.SimpleTy) {
2836
  case MVT::i32: return fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2837
  default: return 0;
2838
  }
2839
}
2840
2841
// FastEmit functions for MipsISD::DivRem.
2842
2843
0
unsigned fastEmit_MipsISD_DivRem_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2844
0
  if (RetVT.SimpleTy != MVT::Untyped)
2845
0
    return 0;
2846
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
2847
0
    return fastEmitInst_rr(Mips::SDIV_MM_Pseudo, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2848
0
  }
2849
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
2850
0
    return fastEmitInst_rr(Mips::PseudoSDIV, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2851
0
  }
2852
0
  return 0;
2853
0
}
2854
2855
0
unsigned fastEmit_MipsISD_DivRem_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2856
0
  if (RetVT.SimpleTy != MVT::Untyped)
2857
0
    return 0;
2858
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
2859
0
    return fastEmitInst_rr(Mips::PseudoDSDIV, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2860
0
  }
2861
0
  return 0;
2862
0
}
2863
2864
unsigned fastEmit_MipsISD_DivRem_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2865
  switch (VT.SimpleTy) {
2866
  case MVT::i32: return fastEmit_MipsISD_DivRem_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2867
  case MVT::i64: return fastEmit_MipsISD_DivRem_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2868
  default: return 0;
2869
  }
2870
}
2871
2872
// FastEmit functions for MipsISD::DivRem16.
2873
2874
0
unsigned fastEmit_MipsISD_DivRem16_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2875
0
  if (RetVT.SimpleTy != MVT::isVoid)
2876
0
    return 0;
2877
0
  if ((Subtarget->inMips16Mode())) {
2878
0
    return fastEmitInst_rr(Mips::DivRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2879
0
  }
2880
0
  return 0;
2881
0
}
2882
2883
unsigned fastEmit_MipsISD_DivRem16_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2884
  switch (VT.SimpleTy) {
2885
  case MVT::i32: return fastEmit_MipsISD_DivRem16_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2886
  default: return 0;
2887
  }
2888
}
2889
2890
// FastEmit functions for MipsISD::DivRemU.
2891
2892
0
unsigned fastEmit_MipsISD_DivRemU_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2893
0
  if (RetVT.SimpleTy != MVT::Untyped)
2894
0
    return 0;
2895
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
2896
0
    return fastEmitInst_rr(Mips::UDIV_MM_Pseudo, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2897
0
  }
2898
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
2899
0
    return fastEmitInst_rr(Mips::PseudoUDIV, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2900
0
  }
2901
0
  return 0;
2902
0
}
2903
2904
0
unsigned fastEmit_MipsISD_DivRemU_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2905
0
  if (RetVT.SimpleTy != MVT::Untyped)
2906
0
    return 0;
2907
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
2908
0
    return fastEmitInst_rr(Mips::PseudoDUDIV, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2909
0
  }
2910
0
  return 0;
2911
0
}
2912
2913
unsigned fastEmit_MipsISD_DivRemU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2914
  switch (VT.SimpleTy) {
2915
  case MVT::i32: return fastEmit_MipsISD_DivRemU_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2916
  case MVT::i64: return fastEmit_MipsISD_DivRemU_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2917
  default: return 0;
2918
  }
2919
}
2920
2921
// FastEmit functions for MipsISD::DivRemU16.
2922
2923
0
unsigned fastEmit_MipsISD_DivRemU16_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2924
0
  if (RetVT.SimpleTy != MVT::isVoid)
2925
0
    return 0;
2926
0
  if ((Subtarget->inMips16Mode())) {
2927
0
    return fastEmitInst_rr(Mips::DivuRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2928
0
  }
2929
0
  return 0;
2930
0
}
2931
2932
unsigned fastEmit_MipsISD_DivRemU16_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2933
  switch (VT.SimpleTy) {
2934
  case MVT::i32: return fastEmit_MipsISD_DivRemU16_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2935
  default: return 0;
2936
  }
2937
}
2938
2939
// FastEmit functions for MipsISD::EH_RETURN.
2940
2941
0
unsigned fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2942
0
  if (RetVT.SimpleTy != MVT::isVoid)
2943
0
    return 0;
2944
0
  return fastEmitInst_rr(Mips::MIPSeh_return32, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2945
0
}
2946
2947
0
unsigned fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2948
0
  if (RetVT.SimpleTy != MVT::isVoid)
2949
0
    return 0;
2950
0
  return fastEmitInst_rr(Mips::MIPSeh_return64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2951
0
}
2952
2953
unsigned fastEmit_MipsISD_EH_RETURN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2954
  switch (VT.SimpleTy) {
2955
  case MVT::i32: return fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2956
  case MVT::i64: return fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2957
  default: return 0;
2958
  }
2959
}
2960
2961
// FastEmit functions for MipsISD::ILVEV.
2962
2963
0
unsigned fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2964
0
  if (RetVT.SimpleTy != MVT::v16i8)
2965
0
    return 0;
2966
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2967
0
    return fastEmitInst_rr(Mips::ILVEV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2968
0
  }
2969
0
  return 0;
2970
0
}
2971
2972
0
unsigned fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2973
0
  if (RetVT.SimpleTy != MVT::v8i16)
2974
0
    return 0;
2975
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2976
0
    return fastEmitInst_rr(Mips::ILVEV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2977
0
  }
2978
0
  return 0;
2979
0
}
2980
2981
0
unsigned fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2982
0
  if (RetVT.SimpleTy != MVT::v4i32)
2983
0
    return 0;
2984
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2985
0
    return fastEmitInst_rr(Mips::ILVEV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2986
0
  }
2987
0
  return 0;
2988
0
}
2989
2990
0
unsigned fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2991
0
  if (RetVT.SimpleTy != MVT::v2i64)
2992
0
    return 0;
2993
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2994
0
    return fastEmitInst_rr(Mips::ILVEV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2995
0
  }
2996
0
  return 0;
2997
0
}
2998
2999
unsigned fastEmit_MipsISD_ILVEV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3000
  switch (VT.SimpleTy) {
3001
  case MVT::v16i8: return fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3002
  case MVT::v8i16: return fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3003
  case MVT::v4i32: return fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3004
  case MVT::v2i64: return fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3005
  default: return 0;
3006
  }
3007
}
3008
3009
// FastEmit functions for MipsISD::ILVL.
3010
3011
0
unsigned fastEmit_MipsISD_ILVL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3012
0
  if (RetVT.SimpleTy != MVT::v16i8)
3013
0
    return 0;
3014
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3015
0
    return fastEmitInst_rr(Mips::ILVL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3016
0
  }
3017
0
  return 0;
3018
0
}
3019
3020
0
unsigned fastEmit_MipsISD_ILVL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3021
0
  if (RetVT.SimpleTy != MVT::v8i16)
3022
0
    return 0;
3023
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3024
0
    return fastEmitInst_rr(Mips::ILVL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3025
0
  }
3026
0
  return 0;
3027
0
}
3028
3029
0
unsigned fastEmit_MipsISD_ILVL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3030
0
  if (RetVT.SimpleTy != MVT::v4i32)
3031
0
    return 0;
3032
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3033
0
    return fastEmitInst_rr(Mips::ILVL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3034
0
  }
3035
0
  return 0;
3036
0
}
3037
3038
0
unsigned fastEmit_MipsISD_ILVL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3039
0
  if (RetVT.SimpleTy != MVT::v2i64)
3040
0
    return 0;
3041
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3042
0
    return fastEmitInst_rr(Mips::ILVL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3043
0
  }
3044
0
  return 0;
3045
0
}
3046
3047
unsigned fastEmit_MipsISD_ILVL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3048
  switch (VT.SimpleTy) {
3049
  case MVT::v16i8: return fastEmit_MipsISD_ILVL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3050
  case MVT::v8i16: return fastEmit_MipsISD_ILVL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3051
  case MVT::v4i32: return fastEmit_MipsISD_ILVL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3052
  case MVT::v2i64: return fastEmit_MipsISD_ILVL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3053
  default: return 0;
3054
  }
3055
}
3056
3057
// FastEmit functions for MipsISD::ILVOD.
3058
3059
0
unsigned fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3060
0
  if (RetVT.SimpleTy != MVT::v16i8)
3061
0
    return 0;
3062
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3063
0
    return fastEmitInst_rr(Mips::ILVOD_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3064
0
  }
3065
0
  return 0;
3066
0
}
3067
3068
0
unsigned fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3069
0
  if (RetVT.SimpleTy != MVT::v8i16)
3070
0
    return 0;
3071
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3072
0
    return fastEmitInst_rr(Mips::ILVOD_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3073
0
  }
3074
0
  return 0;
3075
0
}
3076
3077
0
unsigned fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3078
0
  if (RetVT.SimpleTy != MVT::v4i32)
3079
0
    return 0;
3080
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3081
0
    return fastEmitInst_rr(Mips::ILVOD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3082
0
  }
3083
0
  return 0;
3084
0
}
3085
3086
0
unsigned fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3087
0
  if (RetVT.SimpleTy != MVT::v2i64)
3088
0
    return 0;
3089
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3090
0
    return fastEmitInst_rr(Mips::ILVOD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3091
0
  }
3092
0
  return 0;
3093
0
}
3094
3095
unsigned fastEmit_MipsISD_ILVOD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3096
  switch (VT.SimpleTy) {
3097
  case MVT::v16i8: return fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3098
  case MVT::v8i16: return fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3099
  case MVT::v4i32: return fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3100
  case MVT::v2i64: return fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3101
  default: return 0;
3102
  }
3103
}
3104
3105
// FastEmit functions for MipsISD::ILVR.
3106
3107
0
unsigned fastEmit_MipsISD_ILVR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3108
0
  if (RetVT.SimpleTy != MVT::v16i8)
3109
0
    return 0;
3110
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3111
0
    return fastEmitInst_rr(Mips::ILVR_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3112
0
  }
3113
0
  return 0;
3114
0
}
3115
3116
0
unsigned fastEmit_MipsISD_ILVR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3117
0
  if (RetVT.SimpleTy != MVT::v8i16)
3118
0
    return 0;
3119
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3120
0
    return fastEmitInst_rr(Mips::ILVR_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3121
0
  }
3122
0
  return 0;
3123
0
}
3124
3125
0
unsigned fastEmit_MipsISD_ILVR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3126
0
  if (RetVT.SimpleTy != MVT::v4i32)
3127
0
    return 0;
3128
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3129
0
    return fastEmitInst_rr(Mips::ILVR_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3130
0
  }
3131
0
  return 0;
3132
0
}
3133
3134
0
unsigned fastEmit_MipsISD_ILVR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3135
0
  if (RetVT.SimpleTy != MVT::v2i64)
3136
0
    return 0;
3137
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3138
0
    return fastEmitInst_rr(Mips::ILVR_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3139
0
  }
3140
0
  return 0;
3141
0
}
3142
3143
unsigned fastEmit_MipsISD_ILVR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3144
  switch (VT.SimpleTy) {
3145
  case MVT::v16i8: return fastEmit_MipsISD_ILVR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3146
  case MVT::v8i16: return fastEmit_MipsISD_ILVR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3147
  case MVT::v4i32: return fastEmit_MipsISD_ILVR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3148
  case MVT::v2i64: return fastEmit_MipsISD_ILVR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3149
  default: return 0;
3150
  }
3151
}
3152
3153
// FastEmit functions for MipsISD::MTLOHI.
3154
3155
0
unsigned fastEmit_MipsISD_MTLOHI_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3156
0
  if (RetVT.SimpleTy != MVT::Untyped)
3157
0
    return 0;
3158
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
3159
0
    return fastEmitInst_rr(Mips::PseudoMTLOHI_MM, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3160
0
  }
3161
0
  if ((!Subtarget->inMips16Mode())) {
3162
0
    return fastEmitInst_rr(Mips::PseudoMTLOHI_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3163
0
  }
3164
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3165
0
    return fastEmitInst_rr(Mips::PseudoMTLOHI, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3166
0
  }
3167
0
  return 0;
3168
0
}
3169
3170
0
unsigned fastEmit_MipsISD_MTLOHI_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3171
0
  if (RetVT.SimpleTy != MVT::Untyped)
3172
0
    return 0;
3173
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3174
0
    return fastEmitInst_rr(Mips::PseudoMTLOHI64, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3175
0
  }
3176
0
  return 0;
3177
0
}
3178
3179
unsigned fastEmit_MipsISD_MTLOHI_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3180
  switch (VT.SimpleTy) {
3181
  case MVT::i32: return fastEmit_MipsISD_MTLOHI_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3182
  case MVT::i64: return fastEmit_MipsISD_MTLOHI_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3183
  default: return 0;
3184
  }
3185
}
3186
3187
// FastEmit functions for MipsISD::Mult.
3188
3189
0
unsigned fastEmit_MipsISD_Mult_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3190
0
  if (RetVT.SimpleTy != MVT::Untyped)
3191
0
    return 0;
3192
0
  if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
3193
0
    return fastEmitInst_rr(Mips::MULT_DSP_MM, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3194
0
  }
3195
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
3196
0
    return fastEmitInst_rr(Mips::PseudoMULT_MM, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3197
0
  }
3198
0
  if ((Subtarget->hasDSP())) {
3199
0
    return fastEmitInst_rr(Mips::MULT_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3200
0
  }
3201
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3202
0
    return fastEmitInst_rr(Mips::PseudoMULT, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3203
0
  }
3204
0
  return 0;
3205
0
}
3206
3207
0
unsigned fastEmit_MipsISD_Mult_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3208
0
  if (RetVT.SimpleTy != MVT::Untyped)
3209
0
    return 0;
3210
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3211
0
    return fastEmitInst_rr(Mips::PseudoDMULT, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3212
0
  }
3213
0
  return 0;
3214
0
}
3215
3216
unsigned fastEmit_MipsISD_Mult_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3217
  switch (VT.SimpleTy) {
3218
  case MVT::i32: return fastEmit_MipsISD_Mult_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3219
  case MVT::i64: return fastEmit_MipsISD_Mult_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3220
  default: return 0;
3221
  }
3222
}
3223
3224
// FastEmit functions for MipsISD::Multu.
3225
3226
0
unsigned fastEmit_MipsISD_Multu_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3227
0
  if (RetVT.SimpleTy != MVT::Untyped)
3228
0
    return 0;
3229
0
  if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
3230
0
    return fastEmitInst_rr(Mips::MULTU_DSP_MM, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3231
0
  }
3232
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
3233
0
    return fastEmitInst_rr(Mips::PseudoMULTu_MM, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3234
0
  }
3235
0
  if ((Subtarget->hasDSP())) {
3236
0
    return fastEmitInst_rr(Mips::MULTU_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3237
0
  }
3238
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3239
0
    return fastEmitInst_rr(Mips::PseudoMULTu, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3240
0
  }
3241
0
  return 0;
3242
0
}
3243
3244
0
unsigned fastEmit_MipsISD_Multu_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3245
0
  if (RetVT.SimpleTy != MVT::Untyped)
3246
0
    return 0;
3247
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3248
0
    return fastEmitInst_rr(Mips::PseudoDMULTu, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3249
0
  }
3250
0
  return 0;
3251
0
}
3252
3253
unsigned fastEmit_MipsISD_Multu_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3254
  switch (VT.SimpleTy) {
3255
  case MVT::i32: return fastEmit_MipsISD_Multu_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3256
  case MVT::i64: return fastEmit_MipsISD_Multu_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3257
  default: return 0;
3258
  }
3259
}
3260
3261
// FastEmit functions for MipsISD::PCKEV.
3262
3263
0
unsigned fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3264
0
  if (RetVT.SimpleTy != MVT::v16i8)
3265
0
    return 0;
3266
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3267
0
    return fastEmitInst_rr(Mips::PCKEV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3268
0
  }
3269
0
  return 0;
3270
0
}
3271
3272
0
unsigned fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3273
0
  if (RetVT.SimpleTy != MVT::v8i16)
3274
0
    return 0;
3275
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3276
0
    return fastEmitInst_rr(Mips::PCKEV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3277
0
  }
3278
0
  return 0;
3279
0
}
3280
3281
0
unsigned fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3282
0
  if (RetVT.SimpleTy != MVT::v4i32)
3283
0
    return 0;
3284
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3285
0
    return fastEmitInst_rr(Mips::PCKEV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3286
0
  }
3287
0
  return 0;
3288
0
}
3289
3290
0
unsigned fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3291
0
  if (RetVT.SimpleTy != MVT::v2i64)
3292
0
    return 0;
3293
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3294
0
    return fastEmitInst_rr(Mips::PCKEV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3295
0
  }
3296
0
  return 0;
3297
0
}
3298
3299
unsigned fastEmit_MipsISD_PCKEV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3300
  switch (VT.SimpleTy) {
3301
  case MVT::v16i8: return fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3302
  case MVT::v8i16: return fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3303
  case MVT::v4i32: return fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3304
  case MVT::v2i64: return fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3305
  default: return 0;
3306
  }
3307
}
3308
3309
// FastEmit functions for MipsISD::PCKOD.
3310
3311
0
unsigned fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3312
0
  if (RetVT.SimpleTy != MVT::v16i8)
3313
0
    return 0;
3314
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3315
0
    return fastEmitInst_rr(Mips::PCKOD_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3316
0
  }
3317
0
  return 0;
3318
0
}
3319
3320
0
unsigned fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3321
0
  if (RetVT.SimpleTy != MVT::v8i16)
3322
0
    return 0;
3323
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3324
0
    return fastEmitInst_rr(Mips::PCKOD_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3325
0
  }
3326
0
  return 0;
3327
0
}
3328
3329
0
unsigned fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3330
0
  if (RetVT.SimpleTy != MVT::v4i32)
3331
0
    return 0;
3332
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3333
0
    return fastEmitInst_rr(Mips::PCKOD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3334
0
  }
3335
0
  return 0;
3336
0
}
3337
3338
0
unsigned fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3339
0
  if (RetVT.SimpleTy != MVT::v2i64)
3340
0
    return 0;
3341
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3342
0
    return fastEmitInst_rr(Mips::PCKOD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3343
0
  }
3344
0
  return 0;
3345
0
}
3346
3347
unsigned fastEmit_MipsISD_PCKOD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3348
  switch (VT.SimpleTy) {
3349
  case MVT::v16i8: return fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3350
  case MVT::v8i16: return fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3351
  case MVT::v4i32: return fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3352
  case MVT::v2i64: return fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3353
  default: return 0;
3354
  }
3355
}
3356
3357
// FastEmit functions for MipsISD::VNOR.
3358
3359
0
unsigned fastEmit_MipsISD_VNOR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3360
0
  if (RetVT.SimpleTy != MVT::v16i8)
3361
0
    return 0;
3362
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3363
0
    return fastEmitInst_rr(Mips::NOR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3364
0
  }
3365
0
  return 0;
3366
0
}
3367
3368
0
unsigned fastEmit_MipsISD_VNOR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3369
0
  if (RetVT.SimpleTy != MVT::v8i16)
3370
0
    return 0;
3371
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3372
0
    return fastEmitInst_rr(Mips::NOR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3373
0
  }
3374
0
  return 0;
3375
0
}
3376
3377
0
unsigned fastEmit_MipsISD_VNOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3378
0
  if (RetVT.SimpleTy != MVT::v4i32)
3379
0
    return 0;
3380
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3381
0
    return fastEmitInst_rr(Mips::NOR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3382
0
  }
3383
0
  return 0;
3384
0
}
3385
3386
0
unsigned fastEmit_MipsISD_VNOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3387
0
  if (RetVT.SimpleTy != MVT::v2i64)
3388
0
    return 0;
3389
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3390
0
    return fastEmitInst_rr(Mips::NOR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3391
0
  }
3392
0
  return 0;
3393
0
}
3394
3395
unsigned fastEmit_MipsISD_VNOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3396
  switch (VT.SimpleTy) {
3397
  case MVT::v16i8: return fastEmit_MipsISD_VNOR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3398
  case MVT::v8i16: return fastEmit_MipsISD_VNOR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3399
  case MVT::v4i32: return fastEmit_MipsISD_VNOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3400
  case MVT::v2i64: return fastEmit_MipsISD_VNOR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3401
  default: return 0;
3402
  }
3403
}
3404
3405
// Top-level FastEmit function.
3406
3407
38
unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) override {
3408
38
  switch (Opcode) {
3409
38
  
case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)6
;
3410
38
  
case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3411
38
  
case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3412
38
  
case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)5
;
3413
38
  
case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3414
38
  
case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3415
38
  
case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3416
38
  
case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3417
38
  
case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)2
;
3418
38
  
case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3419
38
  
case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3420
38
  
case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)4
;
3421
38
  
case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3422
38
  
case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)4
;
3423
38
  
case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3424
38
  
case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3425
38
  
case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3426
38
  
case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3427
38
  
case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)4
;
3428
38
  
case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3429
38
  
case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3430
38
  
case ISD::SUBC: return fastEmit_ISD_SUBC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3431
38
  
case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)4
;
3432
38
  
case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3433
38
  
case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3434
38
  
case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)4
;
3435
38
  
case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)5
;
3436
38
  
case MipsISD::BuildPairF64: return fastEmit_MipsISD_BuildPairF64_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3437
38
  
case MipsISD::DivRem: return fastEmit_MipsISD_DivRem_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3438
38
  
case MipsISD::DivRem16: return fastEmit_MipsISD_DivRem16_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3439
38
  
case MipsISD::DivRemU: return fastEmit_MipsISD_DivRemU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3440
38
  
case MipsISD::DivRemU16: return fastEmit_MipsISD_DivRemU16_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3441
38
  
case MipsISD::EH_RETURN: return fastEmit_MipsISD_EH_RETURN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3442
38
  
case MipsISD::ILVEV: return fastEmit_MipsISD_ILVEV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3443
38
  
case MipsISD::ILVL: return fastEmit_MipsISD_ILVL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3444
38
  
case MipsISD::ILVOD: return fastEmit_MipsISD_ILVOD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3445
38
  
case MipsISD::ILVR: return fastEmit_MipsISD_ILVR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3446
38
  
case MipsISD::MTLOHI: return fastEmit_MipsISD_MTLOHI_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3447
38
  
case MipsISD::Mult: return fastEmit_MipsISD_Mult_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3448
38
  
case MipsISD::Multu: return fastEmit_MipsISD_Multu_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3449
38
  
case MipsISD::PCKEV: return fastEmit_MipsISD_PCKEV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3450
38
  
case MipsISD::PCKOD: return fastEmit_MipsISD_PCKOD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3451
38
  
case MipsISD::VNOR: return fastEmit_MipsISD_VNOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3452
38
  
default: return 00
;
3453
38
  }
3454
38
}
3455
3456
// FastEmit functions for MipsISD::ExtractElementF64.
3457
3458
0
unsigned fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3459
0
  if (RetVT.SimpleTy != MVT::i32)
3460
0
    return 0;
3461
0
  if ((Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())) {
3462
0
    return fastEmitInst_ri(Mips::ExtractElementF64_64, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3463
0
  }
3464
0
  if ((!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) {
3465
0
    return fastEmitInst_ri(Mips::ExtractElementF64, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3466
0
  }
3467
0
  return 0;
3468
0
}
3469
3470
unsigned fastEmit_MipsISD_ExtractElementF64_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3471
  switch (VT.SimpleTy) {
3472
  case MVT::f64: return fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(RetVT, Op0, Op0IsKill, imm1);
3473
  default: return 0;
3474
  }
3475
}
3476
3477
// FastEmit functions for MipsISD::SHLL_DSP.
3478
3479
0
unsigned fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3480
0
  if (RetVT.SimpleTy != MVT::v4i8)
3481
0
    return 0;
3482
0
  if ((Subtarget->hasDSP())) {
3483
0
    return fastEmitInst_ri(Mips::SHLL_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
3484
0
  }
3485
0
  return 0;
3486
0
}
3487
3488
0
unsigned fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3489
0
  if (RetVT.SimpleTy != MVT::v2i16)
3490
0
    return 0;
3491
0
  if ((Subtarget->hasDSP())) {
3492
0
    return fastEmitInst_ri(Mips::SHLL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
3493
0
  }
3494
0
  return 0;
3495
0
}
3496
3497
unsigned fastEmit_MipsISD_SHLL_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3498
  switch (VT.SimpleTy) {
3499
  case MVT::v4i8: return fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1);
3500
  case MVT::v2i16: return fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1);
3501
  default: return 0;
3502
  }
3503
}
3504
3505
// FastEmit functions for MipsISD::SHRA_DSP.
3506
3507
0
unsigned fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3508
0
  if (RetVT.SimpleTy != MVT::v4i8)
3509
0
    return 0;
3510
0
  if ((Subtarget->hasDSPR2())) {
3511
0
    return fastEmitInst_ri(Mips::SHRA_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
3512
0
  }
3513
0
  return 0;
3514
0
}
3515
3516
0
unsigned fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3517
0
  if (RetVT.SimpleTy != MVT::v2i16)
3518
0
    return 0;
3519
0
  if ((Subtarget->hasDSP())) {
3520
0
    return fastEmitInst_ri(Mips::SHRA_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
3521
0
  }
3522
0
  return 0;
3523
0
}
3524
3525
unsigned fastEmit_MipsISD_SHRA_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3526
  switch (VT.SimpleTy) {
3527
  case MVT::v4i8: return fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1);
3528
  case MVT::v2i16: return fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1);
3529
  default: return 0;
3530
  }
3531
}
3532
3533
// FastEmit functions for MipsISD::SHRL_DSP.
3534
3535
0
unsigned fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3536
0
  if (RetVT.SimpleTy != MVT::v4i8)
3537
0
    return 0;
3538
0
  if ((Subtarget->hasDSP())) {
3539
0
    return fastEmitInst_ri(Mips::SHRL_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
3540
0
  }
3541
0
  return 0;
3542
0
}
3543
3544
0
unsigned fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3545
0
  if (RetVT.SimpleTy != MVT::v2i16)
3546
0
    return 0;
3547
0
  if ((Subtarget->hasDSPR2())) {
3548
0
    return fastEmitInst_ri(Mips::SHRL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
3549
0
  }
3550
0
  return 0;
3551
0
}
3552
3553
unsigned fastEmit_MipsISD_SHRL_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3554
  switch (VT.SimpleTy) {
3555
  case MVT::v4i8: return fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1);
3556
  case MVT::v2i16: return fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1);
3557
  default: return 0;
3558
  }
3559
}
3560
3561
// Top-level FastEmit function.
3562
3563
8
unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) override {
3564
8
  if (VT == MVT::i32 && Predicate_immZExt5(imm1))
3565
8
    if (unsigned Reg = fastEmit_ri_Predicate_immZExt5(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
3566
0
      return Reg;
3567
8
3568
8
  if (VT == MVT::i32 && Predicate_immZExt6(imm1))
3569
8
    if (unsigned Reg = fastEmit_ri_Predicate_immZExt6(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
3570
0
      return Reg;
3571
8
3572
8
  if (VT == MVT::iPTR && 
Predicate_immZExt2Ptr(imm1)0
)
3573
0
    if (unsigned Reg = fastEmit_ri_Predicate_immZExt2Ptr(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
3574
0
      return Reg;
3575
8
3576
8
  if (VT == MVT::iPTR && 
Predicate_immZExt1Ptr(imm1)0
)
3577
0
    if (unsigned Reg = fastEmit_ri_Predicate_immZExt1Ptr(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
3578
0
      return Reg;
3579
8
3580
8
  if (VT == MVT::i32 && Predicate_immZExt4(imm1))
3581
8
    if (unsigned Reg = fastEmit_ri_Predicate_immZExt4(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
3582
0
      return Reg;
3583
8
3584
8
  if (VT == MVT::i32 && Predicate_immSExtAddiur2(imm1))
3585
1
    if (unsigned Reg = fastEmit_ri_Predicate_immSExtAddiur2(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
3586
0
      return Reg;
3587
8
3588
8
  if (VT == MVT::i32 && Predicate_immSExtAddius5(imm1))
3589
8
    if (unsigned Reg = fastEmit_ri_Predicate_immSExtAddius5(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
3590
0
      return Reg;
3591
8
3592
8
  if (VT == MVT::i32 && Predicate_immZExtAndi16(imm1))
3593
1
    if (unsigned Reg = fastEmit_ri_Predicate_immZExtAndi16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
3594
0
      return Reg;
3595
8
3596
8
  if (VT == MVT::i32 && Predicate_immZExt2Shift(imm1))
3597
1
    if (unsigned Reg = fastEmit_ri_Predicate_immZExt2Shift(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
3598
0
      return Reg;
3599
8
3600
8
  switch (Opcode) {
3601
8
  
case MipsISD::ExtractElementF64: return fastEmit_MipsISD_ExtractElementF64_ri(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3602
8
  
case MipsISD::SHLL_DSP: return fastEmit_MipsISD_SHLL_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3603
8
  
case MipsISD::SHRA_DSP: return fastEmit_MipsISD_SHRA_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3604
8
  
case MipsISD::SHRL_DSP: return fastEmit_MipsISD_SHRL_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3605
8
  default: return 0;
3606
8
  }
3607
8
}
3608
3609
// FastEmit functions for ISD::ROTR.
3610
3611
0
unsigned fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3612
0
  if (RetVT.SimpleTy != MVT::i32)
3613
0
    return 0;
3614
0
  if ((Subtarget->inMicroMipsMode())) {
3615
0
    return fastEmitInst_ri(Mips::ROTR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3616
0
  }
3617
0
  if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3618
0
    return fastEmitInst_ri(Mips::ROTR, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3619
0
  }
3620
0
  return 0;
3621
0
}
3622
3623
unsigned fastEmit_ISD_ROTR_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3624
  switch (VT.SimpleTy) {
3625
  case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
3626
  default: return 0;
3627
  }
3628
}
3629
3630
// FastEmit functions for ISD::SHL.
3631
3632
0
unsigned fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3633
0
  if (RetVT.SimpleTy != MVT::i32)
3634
0
    return 0;
3635
0
  if ((Subtarget->inMicroMipsMode())) {
3636
0
    return fastEmitInst_ri(Mips::SLL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3637
0
  }
3638
0
  if ((Subtarget->inMips16Mode())) {
3639
0
    return fastEmitInst_ri(Mips::SllX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1);
3640
0
  }
3641
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3642
0
    return fastEmitInst_ri(Mips::SLL, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3643
0
  }
3644
0
  return 0;
3645
0
}
3646
3647
unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3648
  switch (VT.SimpleTy) {
3649
  case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
3650
  default: return 0;
3651
  }
3652
}
3653
3654
// FastEmit functions for ISD::SRA.
3655
3656
0
unsigned fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3657
0
  if (RetVT.SimpleTy != MVT::i32)
3658
0
    return 0;
3659
0
  if ((Subtarget->inMicroMipsMode())) {
3660
0
    return fastEmitInst_ri(Mips::SRA_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3661
0
  }
3662
0
  if ((Subtarget->inMips16Mode())) {
3663
0
    return fastEmitInst_ri(Mips::SraX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1);
3664
0
  }
3665
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3666
0
    return fastEmitInst_ri(Mips::SRA, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3667
0
  }
3668
0
  return 0;
3669
0
}
3670
3671
unsigned fastEmit_ISD_SRA_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3672
  switch (VT.SimpleTy) {
3673
  case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
3674
  default: return 0;
3675
  }
3676
}
3677
3678
// FastEmit functions for ISD::SRL.
3679
3680
0
unsigned fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3681
0
  if (RetVT.SimpleTy != MVT::i32)
3682
0
    return 0;
3683
0
  if ((Subtarget->inMicroMipsMode())) {
3684
0
    return fastEmitInst_ri(Mips::SRL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3685
0
  }
3686
0
  if ((Subtarget->inMips16Mode())) {
3687
0
    return fastEmitInst_ri(Mips::SrlX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1);
3688
0
  }
3689
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3690
0
    return fastEmitInst_ri(Mips::SRL, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3691
0
  }
3692
0
  return 0;
3693
0
}
3694
3695
unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3696
  switch (VT.SimpleTy) {
3697
  case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
3698
  default: return 0;
3699
  }
3700
}
3701
3702
// Top-level FastEmit function.
3703
3704
8
unsigned fastEmit_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3705
8
  switch (Opcode) {
3706
8
  
case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3707
8
  
case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3708
8
  
case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3709
8
  
case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3710
8
  default: return 0;
3711
8
  }
3712
8
}
3713
3714
// FastEmit functions for ISD::ROTR.
3715
3716
0
unsigned fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3717
0
  if (RetVT.SimpleTy != MVT::i64)
3718
0
    return 0;
3719
0
  if ((Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3720
0
    return fastEmitInst_ri(Mips::DROTR, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
3721
0
  }
3722
0
  return 0;
3723
0
}
3724
3725
unsigned fastEmit_ISD_ROTR_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3726
  switch (VT.SimpleTy) {
3727
  case MVT::i64: return fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
3728
  default: return 0;
3729
  }
3730
}
3731
3732
// FastEmit functions for ISD::SHL.
3733
3734
0
unsigned fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3735
0
  if (RetVT.SimpleTy != MVT::i64)
3736
0
    return 0;
3737
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3738
0
    return fastEmitInst_ri(Mips::DSLL, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
3739
0
  }
3740
0
  return 0;
3741
0
}
3742
3743
unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3744
  switch (VT.SimpleTy) {
3745
  case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
3746
  default: return 0;
3747
  }
3748
}
3749
3750
// FastEmit functions for ISD::SRA.
3751
3752
0
unsigned fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3753
0
  if (RetVT.SimpleTy != MVT::i64)
3754
0
    return 0;
3755
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3756
0
    return fastEmitInst_ri(Mips::DSRA, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
3757
0
  }
3758
0
  return 0;
3759
0
}
3760
3761
unsigned fastEmit_ISD_SRA_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3762
  switch (VT.SimpleTy) {
3763
  case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
3764
  default: return 0;
3765
  }
3766
}
3767
3768
// FastEmit functions for ISD::SRL.
3769
3770
0
unsigned fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3771
0
  if (RetVT.SimpleTy != MVT::i64)
3772
0
    return 0;
3773
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3774
0
    return fastEmitInst_ri(Mips::DSRL, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
3775
0
  }
3776
0
  return 0;
3777
0
}
3778
3779
unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3780
  switch (VT.SimpleTy) {
3781
  case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
3782
  default: return 0;
3783
  }
3784
}
3785
3786
// Top-level FastEmit function.
3787
3788
8
unsigned fastEmit_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3789
8
  switch (Opcode) {
3790
8
  
case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3791
8
  
case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3792
8
  
case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3793
8
  
case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3794
8
  default: return 0;
3795
8
  }
3796
8
}
3797
3798
// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
3799
3800
0
unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3801
0
  if (RetVT.SimpleTy != MVT::f32)
3802
0
    return 0;
3803
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3804
0
    return fastEmitInst_ri(Mips::COPY_FW_PSEUDO, &Mips::FGR32RegClass, Op0, Op0IsKill, imm1);
3805
0
  }
3806
0
  return 0;
3807
0
}
3808
3809
unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3810
  switch (VT.SimpleTy) {
3811
  case MVT::v4f32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(RetVT, Op0, Op0IsKill, imm1);
3812
  default: return 0;
3813
  }
3814
}
3815
3816
// Top-level FastEmit function.
3817
3818
unsigned fastEmit_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3819
  switch (Opcode) {
3820
  case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(VT, RetVT, Op0, Op0IsKill, imm1);
3821
  default: return 0;
3822
  }
3823
}
3824
3825
// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
3826
3827
0
unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3828
0
  if (RetVT.SimpleTy != MVT::f64)
3829
0
    return 0;
3830
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3831
0
    return fastEmitInst_ri(Mips::COPY_FD_PSEUDO, &Mips::FGR64RegClass, Op0, Op0IsKill, imm1);
3832
0
  }
3833
0
  return 0;
3834
0
}
3835
3836
unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3837
  switch (VT.SimpleTy) {
3838
  case MVT::v2f64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(RetVT, Op0, Op0IsKill, imm1);
3839
  default: return 0;
3840
  }
3841
}
3842
3843
// Top-level FastEmit function.
3844
3845
unsigned fastEmit_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3846
  switch (Opcode) {
3847
  case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(VT, RetVT, Op0, Op0IsKill, imm1);
3848
  default: return 0;
3849
  }
3850
}
3851
3852
// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
3853
3854
0
unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3855
0
  if (RetVT.SimpleTy != MVT::i32)
3856
0
    return 0;
3857
0
  if ((Subtarget->hasMSA())) {
3858
0
    return fastEmitInst_ri(Mips::COPY_S_W, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3859
0
  }
3860
0
  return 0;
3861
0
}
3862
3863
unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3864
  switch (VT.SimpleTy) {
3865
  case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(RetVT, Op0, Op0IsKill, imm1);
3866
  default: return 0;
3867
  }
3868
}
3869
3870
// Top-level FastEmit function.
3871
3872
8
unsigned fastEmit_ri_Predicate_immZExt4(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3873
8
  switch (Opcode) {
3874
8
  
case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3875
8
  default: return 0;
3876
8
  }
3877
8
}
3878
3879
// FastEmit functions for ISD::ADD.
3880
3881
1
unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3882
1
  if (RetVT.SimpleTy != MVT::i32)
3883
0
    return 0;
3884
1
  if ((Subtarget->inMicroMipsMode())) {
3885
0
    return fastEmitInst_ri(Mips::ADDIUR2_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
3886
0
  }
3887
1
  return 0;
3888
1
}
3889
3890
1
unsigned fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3891
1
  switch (VT.SimpleTy) {
3892
1
  case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(RetVT, Op0, Op0IsKill, imm1);
3893
1
  
default: return 00
;
3894
1
  }
3895
1
}
3896
3897
// Top-level FastEmit function.
3898
3899
1
unsigned fastEmit_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3900
1
  switch (Opcode) {
3901
1
  case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(VT, RetVT, Op0, Op0IsKill, imm1);
3902
1
  
default: return 00
;
3903
1
  }
3904
1
}
3905
3906
// FastEmit functions for ISD::ADD.
3907
3908
1
unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3909
1
  if (RetVT.SimpleTy != MVT::i32)
3910
0
    return 0;
3911
1
  if ((Subtarget->inMicroMipsMode())) {
3912
0
    return fastEmitInst_ri(Mips::ADDIUS5_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3913
0
  }
3914
1
  return 0;
3915
1
}
3916
3917
1
unsigned fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3918
1
  switch (VT.SimpleTy) {
3919
1
  case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(RetVT, Op0, Op0IsKill, imm1);
3920
1
  
default: return 00
;
3921
1
  }
3922
1
}
3923
3924
// Top-level FastEmit function.
3925
3926
8
unsigned fastEmit_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3927
8
  switch (Opcode) {
3928
8
  
case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(VT, RetVT, Op0, Op0IsKill, imm1)1
;
3929
8
  
default: return 07
;
3930
8
  }
3931
8
}
3932
3933
// FastEmit functions for ISD::AND.
3934
3935
0
unsigned fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3936
0
  if (RetVT.SimpleTy != MVT::i32)
3937
0
    return 0;
3938
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
3939
0
    return fastEmitInst_ri(Mips::ANDI16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
3940
0
  }
3941
0
  if ((Subtarget->inMicroMipsMode())) {
3942
0
    return fastEmitInst_ri(Mips::ANDI16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
3943
0
  }
3944
0
  return 0;
3945
0
}
3946
3947
unsigned fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3948
  switch (VT.SimpleTy) {
3949
  case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(RetVT, Op0, Op0IsKill, imm1);
3950
  default: return 0;
3951
  }
3952
}
3953
3954
// Top-level FastEmit function.
3955
3956
1
unsigned fastEmit_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3957
1
  switch (Opcode) {
3958
1
  
case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3959
1
  default: return 0;
3960
1
  }
3961
1
}
3962
3963
// FastEmit functions for ISD::SHL.
3964
3965
0
unsigned fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3966
0
  if (RetVT.SimpleTy != MVT::i32)
3967
0
    return 0;
3968
0
  if ((Subtarget->inMicroMipsMode())) {
3969
0
    return fastEmitInst_ri(Mips::SLL16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
3970
0
  }
3971
0
  return 0;
3972
0
}
3973
3974
unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3975
  switch (VT.SimpleTy) {
3976
  case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, Op0IsKill, imm1);
3977
  default: return 0;
3978
  }
3979
}
3980
3981
// FastEmit functions for ISD::SRL.
3982
3983
0
unsigned fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3984
0
  if (RetVT.SimpleTy != MVT::i32)
3985
0
    return 0;
3986
0
  if ((Subtarget->inMicroMipsMode())) {
3987
0
    return fastEmitInst_ri(Mips::SRL16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
3988
0
  }
3989
0
  return 0;
3990
0
}
3991
3992
unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3993
  switch (VT.SimpleTy) {
3994
  case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, Op0IsKill, imm1);
3995
  default: return 0;
3996
  }
3997
}
3998
3999
// Top-level FastEmit function.
4000
4001
1
unsigned fastEmit_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4002
1
  switch (Opcode) {
4003
1
  
case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, Op0IsKill, imm1)0
;
4004
1
  
case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, Op0IsKill, imm1)0
;
4005
1
  default: return 0;
4006
1
  }
4007
1
}
4008
4009
// FastEmit functions for ISD::Constant.
4010
4011
8
unsigned fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
4012
8
  if (RetVT.SimpleTy != MVT::i32)
4013
0
    return 0;
4014
8
  if ((Subtarget->inMips16Mode())) {
4015
0
    return fastEmitInst_i(Mips::LwConstant32, &Mips::CPU16RegsRegClass, imm0);
4016
0
  }
4017
8
  return 0;
4018
8
}
4019
4020
8
unsigned fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
4021
8
  switch (VT.SimpleTy) {
4022
8
  case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0);
4023
8
  
default: return 00
;
4024
8
  }
4025
8
}
4026
4027
// Top-level FastEmit function.
4028
4029
8
unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override {
4030
8
  switch (Opcode) {
4031
8
  case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0);
4032
8
  
default: return 00
;
4033
8
  }
4034
8
}
4035