Coverage Report

Created: 2018-07-20 23:04

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Mips/MipsGenFastISel.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* "Fast" Instruction Selector for the Mips target                            *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
// FastEmit Immediate Predicate functions.
11
8
static bool Predicate_immZExt5(int64_t Imm) {
12
8
return Imm == (Imm & 0x1f);
13
8
}
14
8
static bool Predicate_immZExt6(int64_t Imm) {
15
8
return Imm == (Imm & 0x3f);
16
8
}
17
0
static bool Predicate_immSExt6(int64_t Imm) {
18
0
return isInt<6>(Imm);
19
0
}
20
0
static bool Predicate_immZExt4Ptr(int64_t Imm) {
21
0
return isUInt<4>(Imm);
22
0
}
23
0
static bool Predicate_immZExt3Ptr(int64_t Imm) {
24
0
return isUInt<3>(Imm);
25
0
}
26
0
static bool Predicate_immZExt2Ptr(int64_t Imm) {
27
0
return isUInt<2>(Imm);
28
0
}
29
0
static bool Predicate_immZExt1Ptr(int64_t Imm) {
30
0
return isUInt<1>(Imm);
31
0
}
32
8
static bool Predicate_immZExt4(int64_t Imm) {
33
8
return isUInt<4>(Imm);
34
8
}
35
0
static bool Predicate_immZExt3(int64_t Imm) {
36
0
return isUInt<3>(Imm);
37
0
}
38
0
static bool Predicate_immZExt2(int64_t Imm) {
39
0
return isUInt<2>(Imm);
40
0
}
41
0
static bool Predicate_immZExt1(int64_t Imm) {
42
0
return isUInt<1>(Imm);
43
0
}
44
0
static bool Predicate_immZExt8(int64_t Imm) {
45
0
return isUInt<8>(Imm);
46
0
}
47
8
static bool Predicate_immSExtAddiur2(int64_t Imm) {
48
8
return Imm == 1 || 
Imm == -17
||
49
8
                                           
(7
(Imm % 4 == 0)7
&&
50
7
                                            Imm < 28 && Imm > 0);
51
8
}
52
8
static bool Predicate_immSExtAddius5(int64_t Imm) {
53
8
return Imm >= -8 && Imm <= 7;
54
8
}
55
8
static bool Predicate_immZExtAndi16(int64_t Imm) {
56
8
return (Imm == 128 || (Imm >= 1 && 
Imm <= 41
) ||
Imm == 77
||
Imm == 87
||
57
8
            
Imm == 157
||
Imm == 167
||
Imm == 317
||
Imm == 327
||
Imm == 637
||
58
8
            
Imm == 647
||
Imm == 2557
||
Imm == 327687
||
Imm == 655357
);
59
8
}
60
8
static bool Predicate_immZExt2Shift(int64_t Imm) {
61
8
return Imm >= 1 && 
Imm <= 81
;
62
8
}
63
64
65
// FastEmit functions for ISD::BITCAST.
66
67
0
unsigned fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
68
0
  if (RetVT.SimpleTy != MVT::f32)
69
0
    return 0;
70
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
71
0
    return fastEmitInst_r(Mips::MTC1_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill);
72
0
  }
73
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
74
0
    return fastEmitInst_r(Mips::MTC1_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
75
0
  }
76
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
77
0
    return fastEmitInst_r(Mips::MTC1, &Mips::FGR32RegClass, Op0, Op0IsKill);
78
0
  }
79
0
  return 0;
80
0
}
81
82
0
unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
83
0
  if (RetVT.SimpleTy != MVT::f64)
84
0
    return 0;
85
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
86
0
    return fastEmitInst_r(Mips::DMTC1, &Mips::FGR64RegClass, Op0, Op0IsKill);
87
0
  }
88
0
  return 0;
89
0
}
90
91
0
unsigned fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
92
0
  if (RetVT.SimpleTy != MVT::i32)
93
0
    return 0;
94
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
95
0
    return fastEmitInst_r(Mips::MFC1_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
96
0
  }
97
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
98
0
    return fastEmitInst_r(Mips::MFC1_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
99
0
  }
100
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
101
0
    return fastEmitInst_r(Mips::MFC1, &Mips::GPR32RegClass, Op0, Op0IsKill);
102
0
  }
103
0
  return 0;
104
0
}
105
106
0
unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
107
0
  if (RetVT.SimpleTy != MVT::i64)
108
0
    return 0;
109
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
110
0
    return fastEmitInst_r(Mips::DMFC1, &Mips::GPR64RegClass, Op0, Op0IsKill);
111
0
  }
112
0
  return 0;
113
0
}
114
115
unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
116
  switch (VT.SimpleTy) {
117
  case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0, Op0IsKill);
118
  case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0, Op0IsKill);
119
  case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0, Op0IsKill);
120
  case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill);
121
  default: return 0;
122
  }
123
}
124
125
// FastEmit functions for ISD::BRIND.
126
127
0
unsigned fastEmit_ISD_BRIND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
128
0
  if (RetVT.SimpleTy != MVT::isVoid)
129
0
    return 0;
130
0
  if ((Subtarget->inMips16Mode())) {
131
0
    return fastEmitInst_r(Mips::JrcRx16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill);
132
0
  }
133
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
134
0
    return fastEmitInst_r(Mips::PseudoIndirectBranch_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
135
0
  }
136
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
137
0
    return fastEmitInst_r(Mips::PseudoIndirectBranch_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
138
0
  }
139
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
140
0
    return fastEmitInst_r(Mips::PseudoIndrectHazardBranchR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
141
0
  }
142
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
143
0
    return fastEmitInst_r(Mips::PseudoIndirectBranchR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
144
0
  }
145
0
  if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
146
0
    return fastEmitInst_r(Mips::PseudoIndirectHazardBranch, &Mips::GPR32RegClass, Op0, Op0IsKill);
147
0
  }
148
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
149
0
    return fastEmitInst_r(Mips::PseudoIndirectBranch, &Mips::GPR32RegClass, Op0, Op0IsKill);
150
0
  }
151
0
  return 0;
152
0
}
153
154
0
unsigned fastEmit_ISD_BRIND_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
155
0
  if (RetVT.SimpleTy != MVT::isVoid)
156
0
    return 0;
157
0
  if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
158
0
    return fastEmitInst_r(Mips::PseudoIndrectHazardBranch64R6, &Mips::GPR64RegClass, Op0, Op0IsKill);
159
0
  }
160
0
  if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
161
0
    return fastEmitInst_r(Mips::PseudoIndirectBranch64R6, &Mips::GPR64RegClass, Op0, Op0IsKill);
162
0
  }
163
0
  if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
164
0
    return fastEmitInst_r(Mips::PseudoIndirectHazardBranch64, &Mips::GPR64RegClass, Op0, Op0IsKill);
165
0
  }
166
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
167
0
    return fastEmitInst_r(Mips::PseudoIndirectBranch64, &Mips::GPR64RegClass, Op0, Op0IsKill);
168
0
  }
169
0
  return 0;
170
0
}
171
172
unsigned fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
173
  switch (VT.SimpleTy) {
174
  case MVT::i32: return fastEmit_ISD_BRIND_MVT_i32_r(RetVT, Op0, Op0IsKill);
175
  case MVT::i64: return fastEmit_ISD_BRIND_MVT_i64_r(RetVT, Op0, Op0IsKill);
176
  default: return 0;
177
  }
178
}
179
180
// FastEmit functions for ISD::CTLZ.
181
182
0
unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
183
0
  if (RetVT.SimpleTy != MVT::i32)
184
0
    return 0;
185
0
  if ((Subtarget->inMicroMipsMode())) {
186
0
    return fastEmitInst_r(Mips::CLZ_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
187
0
  }
188
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding())) {
189
0
    return fastEmitInst_r(Mips::CLZ_R6, &Mips::GPR32RegClass, Op0, Op0IsKill);
190
0
  }
191
0
  if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
192
0
    return fastEmitInst_r(Mips::CLZ, &Mips::GPR32RegClass, Op0, Op0IsKill);
193
0
  }
194
0
  return 0;
195
0
}
196
197
0
unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
198
0
  if (RetVT.SimpleTy != MVT::i64)
199
0
    return 0;
200
0
  if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
201
0
    return fastEmitInst_r(Mips::DCLZ_R6, &Mips::GPR64RegClass, Op0, Op0IsKill);
202
0
  }
203
0
  if ((Subtarget->hasMips64()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips64r6())) {
204
0
    return fastEmitInst_r(Mips::DCLZ, &Mips::GPR64RegClass, Op0, Op0IsKill);
205
0
  }
206
0
  return 0;
207
0
}
208
209
0
unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
210
0
  if (RetVT.SimpleTy != MVT::v16i8)
211
0
    return 0;
212
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
213
0
    return fastEmitInst_r(Mips::NLZC_B, &Mips::MSA128BRegClass, Op0, Op0IsKill);
214
0
  }
215
0
  return 0;
216
0
}
217
218
0
unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
219
0
  if (RetVT.SimpleTy != MVT::v8i16)
220
0
    return 0;
221
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
222
0
    return fastEmitInst_r(Mips::NLZC_H, &Mips::MSA128HRegClass, Op0, Op0IsKill);
223
0
  }
224
0
  return 0;
225
0
}
226
227
0
unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
228
0
  if (RetVT.SimpleTy != MVT::v4i32)
229
0
    return 0;
230
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
231
0
    return fastEmitInst_r(Mips::NLZC_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
232
0
  }
233
0
  return 0;
234
0
}
235
236
0
unsigned fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
237
0
  if (RetVT.SimpleTy != MVT::v2i64)
238
0
    return 0;
239
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
240
0
    return fastEmitInst_r(Mips::NLZC_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
241
0
  }
242
0
  return 0;
243
0
}
244
245
unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
246
  switch (VT.SimpleTy) {
247
  case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
248
  case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0, Op0IsKill);
249
  case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
250
  case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
251
  case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
252
  case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
253
  default: return 0;
254
  }
255
}
256
257
// FastEmit functions for ISD::CTPOP.
258
259
0
unsigned fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
260
0
  if (RetVT.SimpleTy != MVT::i32)
261
0
    return 0;
262
0
  if ((Subtarget->hasCnMips())) {
263
0
    return fastEmitInst_r(Mips::POP, &Mips::GPR32RegClass, Op0, Op0IsKill);
264
0
  }
265
0
  return 0;
266
0
}
267
268
0
unsigned fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
269
0
  if (RetVT.SimpleTy != MVT::i64)
270
0
    return 0;
271
0
  if ((Subtarget->hasCnMips())) {
272
0
    return fastEmitInst_r(Mips::DPOP, &Mips::GPR64RegClass, Op0, Op0IsKill);
273
0
  }
274
0
  return 0;
275
0
}
276
277
0
unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
278
0
  if (RetVT.SimpleTy != MVT::v16i8)
279
0
    return 0;
280
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
281
0
    return fastEmitInst_r(Mips::PCNT_B, &Mips::MSA128BRegClass, Op0, Op0IsKill);
282
0
  }
283
0
  return 0;
284
0
}
285
286
0
unsigned fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
287
0
  if (RetVT.SimpleTy != MVT::v8i16)
288
0
    return 0;
289
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
290
0
    return fastEmitInst_r(Mips::PCNT_H, &Mips::MSA128HRegClass, Op0, Op0IsKill);
291
0
  }
292
0
  return 0;
293
0
}
294
295
0
unsigned fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
296
0
  if (RetVT.SimpleTy != MVT::v4i32)
297
0
    return 0;
298
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
299
0
    return fastEmitInst_r(Mips::PCNT_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
300
0
  }
301
0
  return 0;
302
0
}
303
304
0
unsigned fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
305
0
  if (RetVT.SimpleTy != MVT::v2i64)
306
0
    return 0;
307
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
308
0
    return fastEmitInst_r(Mips::PCNT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
309
0
  }
310
0
  return 0;
311
0
}
312
313
unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
314
  switch (VT.SimpleTy) {
315
  case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0, Op0IsKill);
316
  case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0, Op0IsKill);
317
  case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
318
  case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
319
  case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
320
  case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
321
  default: return 0;
322
  }
323
}
324
325
// FastEmit functions for ISD::FABS.
326
327
0
unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
328
0
  if (RetVT.SimpleTy != MVT::f32)
329
0
    return 0;
330
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
331
0
    return fastEmitInst_r(Mips::FABS_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
332
0
  }
333
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
334
0
    return fastEmitInst_r(Mips::FABS_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
335
0
  }
336
0
  return 0;
337
0
}
338
339
0
unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
340
0
  if (RetVT.SimpleTy != MVT::f64)
341
0
    return 0;
342
0
  if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
343
0
    return fastEmitInst_r(Mips::FABS_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
344
0
  }
345
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
346
0
    return fastEmitInst_r(Mips::FABS_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
347
0
  }
348
0
  if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
349
0
    return fastEmitInst_r(Mips::FABS_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
350
0
  }
351
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
352
0
    return fastEmitInst_r(Mips::FABS_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill);
353
0
  }
354
0
  return 0;
355
0
}
356
357
0
unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
358
0
  if (RetVT.SimpleTy != MVT::v4f32)
359
0
    return 0;
360
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
361
0
    return fastEmitInst_r(Mips::FABS_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
362
0
  }
363
0
  return 0;
364
0
}
365
366
0
unsigned fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
367
0
  if (RetVT.SimpleTy != MVT::v2f64)
368
0
    return 0;
369
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
370
0
    return fastEmitInst_r(Mips::FABS_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
371
0
  }
372
0
  return 0;
373
0
}
374
375
unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
376
  switch (VT.SimpleTy) {
377
  case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill);
378
  case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0, Op0IsKill);
379
  case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
380
  case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
381
  default: return 0;
382
  }
383
}
384
385
// FastEmit functions for ISD::FEXP2.
386
387
0
unsigned fastEmit_ISD_FEXP2_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
388
0
  if (RetVT.SimpleTy != MVT::v4f32)
389
0
    return 0;
390
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
391
0
    return fastEmitInst_r(Mips::FEXP2_W_1_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill);
392
0
  }
393
0
  return 0;
394
0
}
395
396
0
unsigned fastEmit_ISD_FEXP2_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
397
0
  if (RetVT.SimpleTy != MVT::v2f64)
398
0
    return 0;
399
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
400
0
    return fastEmitInst_r(Mips::FEXP2_D_1_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill);
401
0
  }
402
0
  return 0;
403
0
}
404
405
unsigned fastEmit_ISD_FEXP2_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
406
  switch (VT.SimpleTy) {
407
  case MVT::v4f32: return fastEmit_ISD_FEXP2_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
408
  case MVT::v2f64: return fastEmit_ISD_FEXP2_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
409
  default: return 0;
410
  }
411
}
412
413
// FastEmit functions for ISD::FLOG2.
414
415
0
unsigned fastEmit_ISD_FLOG2_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
416
0
  if (RetVT.SimpleTy != MVT::v4f32)
417
0
    return 0;
418
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
419
0
    return fastEmitInst_r(Mips::FLOG2_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
420
0
  }
421
0
  return 0;
422
0
}
423
424
0
unsigned fastEmit_ISD_FLOG2_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
425
0
  if (RetVT.SimpleTy != MVT::v2f64)
426
0
    return 0;
427
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
428
0
    return fastEmitInst_r(Mips::FLOG2_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
429
0
  }
430
0
  return 0;
431
0
}
432
433
unsigned fastEmit_ISD_FLOG2_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
434
  switch (VT.SimpleTy) {
435
  case MVT::v4f32: return fastEmit_ISD_FLOG2_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
436
  case MVT::v2f64: return fastEmit_ISD_FLOG2_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
437
  default: return 0;
438
  }
439
}
440
441
// FastEmit functions for ISD::FNEG.
442
443
0
unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
444
0
  if (RetVT.SimpleTy != MVT::f32)
445
0
    return 0;
446
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
447
0
    return fastEmitInst_r(Mips::FNEG_S_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill);
448
0
  }
449
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
450
0
    return fastEmitInst_r(Mips::FNEG_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
451
0
  }
452
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
453
0
    return fastEmitInst_r(Mips::FNEG_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
454
0
  }
455
0
  return 0;
456
0
}
457
458
0
unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
459
0
  if (RetVT.SimpleTy != MVT::f64)
460
0
    return 0;
461
0
  if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
462
0
    return fastEmitInst_r(Mips::FNEG_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
463
0
  }
464
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
465
0
    return fastEmitInst_r(Mips::FNEG_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
466
0
  }
467
0
  if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
468
0
    return fastEmitInst_r(Mips::FNEG_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
469
0
  }
470
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
471
0
    return fastEmitInst_r(Mips::FNEG_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill);
472
0
  }
473
0
  return 0;
474
0
}
475
476
unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
477
  switch (VT.SimpleTy) {
478
  case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill);
479
  case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0, Op0IsKill);
480
  default: return 0;
481
  }
482
}
483
484
// FastEmit functions for ISD::FP_EXTEND.
485
486
0
unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
487
0
  if ((Subtarget->hasMSA())) {
488
0
    return fastEmitInst_r(Mips::MSA_FP_EXTEND_W_PSEUDO, &Mips::FGR32RegClass, Op0, Op0IsKill);
489
0
  }
490
0
  return 0;
491
0
}
492
493
0
unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
494
0
  if ((Subtarget->hasMSA())) {
495
0
    return fastEmitInst_r(Mips::MSA_FP_EXTEND_D_PSEUDO, &Mips::FGR64RegClass, Op0, Op0IsKill);
496
0
  }
497
0
  return 0;
498
0
}
499
500
unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
501
switch (RetVT.SimpleTy) {
502
  case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(Op0, Op0IsKill);
503
  case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(Op0, Op0IsKill);
504
  default: return 0;
505
}
506
}
507
508
0
unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
509
0
  if (RetVT.SimpleTy != MVT::f64)
510
0
    return 0;
511
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())) {
512
0
    return fastEmitInst_r(Mips::CVT_D32_S_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
513
0
  }
514
0
  if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) {
515
0
    return fastEmitInst_r(Mips::CVT_D64_S_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
516
0
  }
517
0
  if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
518
0
    return fastEmitInst_r(Mips::CVT_D64_S, &Mips::FGR64RegClass, Op0, Op0IsKill);
519
0
  }
520
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
521
0
    return fastEmitInst_r(Mips::CVT_D32_S, &Mips::AFGR64RegClass, Op0, Op0IsKill);
522
0
  }
523
0
  return 0;
524
0
}
525
526
unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
527
  switch (VT.SimpleTy) {
528
  case MVT::f16: return fastEmit_ISD_FP_EXTEND_MVT_f16_r(RetVT, Op0, Op0IsKill);
529
  case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill);
530
  default: return 0;
531
  }
532
}
533
534
// FastEmit functions for ISD::FP_ROUND.
535
536
0
unsigned fastEmit_ISD_FP_ROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
537
0
  if (RetVT.SimpleTy != MVT::f16)
538
0
    return 0;
539
0
  if ((Subtarget->hasMSA())) {
540
0
    return fastEmitInst_r(Mips::MSA_FP_ROUND_W_PSEUDO, &Mips::MSA128F16RegClass, Op0, Op0IsKill);
541
0
  }
542
0
  return 0;
543
0
}
544
545
0
unsigned fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(unsigned Op0, bool Op0IsKill) {
546
0
  if ((Subtarget->hasMSA())) {
547
0
    return fastEmitInst_r(Mips::MSA_FP_ROUND_D_PSEUDO, &Mips::MSA128F16RegClass, Op0, Op0IsKill);
548
0
  }
549
0
  return 0;
550
0
}
551
552
0
unsigned fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
553
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())) {
554
0
    return fastEmitInst_r(Mips::CVT_S_D32_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
555
0
  }
556
0
  if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) {
557
0
    return fastEmitInst_r(Mips::CVT_S_D64_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
558
0
  }
559
0
  if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
560
0
    return fastEmitInst_r(Mips::CVT_S_D64, &Mips::FGR32RegClass, Op0, Op0IsKill);
561
0
  }
562
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
563
0
    return fastEmitInst_r(Mips::CVT_S_D32, &Mips::FGR32RegClass, Op0, Op0IsKill);
564
0
  }
565
0
  return 0;
566
0
}
567
568
unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
569
switch (RetVT.SimpleTy) {
570
  case MVT::f16: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(Op0, Op0IsKill);
571
  case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(Op0, Op0IsKill);
572
  default: return 0;
573
}
574
}
575
576
unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
577
  switch (VT.SimpleTy) {
578
  case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f32_r(RetVT, Op0, Op0IsKill);
579
  case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
580
  default: return 0;
581
  }
582
}
583
584
// FastEmit functions for ISD::FP_TO_SINT.
585
586
0
unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
587
0
  if (RetVT.SimpleTy != MVT::v4i32)
588
0
    return 0;
589
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
590
0
    return fastEmitInst_r(Mips::FTRUNC_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
591
0
  }
592
0
  return 0;
593
0
}
594
595
0
unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
596
0
  if (RetVT.SimpleTy != MVT::v2i64)
597
0
    return 0;
598
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
599
0
    return fastEmitInst_r(Mips::FTRUNC_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
600
0
  }
601
0
  return 0;
602
0
}
603
604
4
unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
605
4
  switch (VT.SimpleTy) {
606
4
  
case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill)0
;
607
4
  
case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill)0
;
608
4
  default: return 0;
609
4
  }
610
4
}
611
612
// FastEmit functions for ISD::FP_TO_UINT.
613
614
0
unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
615
0
  if (RetVT.SimpleTy != MVT::v4i32)
616
0
    return 0;
617
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
618
0
    return fastEmitInst_r(Mips::FTRUNC_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
619
0
  }
620
0
  return 0;
621
0
}
622
623
0
unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
624
0
  if (RetVT.SimpleTy != MVT::v2i64)
625
0
    return 0;
626
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
627
0
    return fastEmitInst_r(Mips::FTRUNC_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
628
0
  }
629
0
  return 0;
630
0
}
631
632
unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
633
  switch (VT.SimpleTy) {
634
  case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
635
  case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
636
  default: return 0;
637
  }
638
}
639
640
// FastEmit functions for ISD::FRINT.
641
642
0
unsigned fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
643
0
  if (RetVT.SimpleTy != MVT::v4f32)
644
0
    return 0;
645
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
646
0
    return fastEmitInst_r(Mips::FRINT_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
647
0
  }
648
0
  return 0;
649
0
}
650
651
0
unsigned fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
652
0
  if (RetVT.SimpleTy != MVT::v2f64)
653
0
    return 0;
654
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
655
0
    return fastEmitInst_r(Mips::FRINT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
656
0
  }
657
0
  return 0;
658
0
}
659
660
unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
661
  switch (VT.SimpleTy) {
662
  case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
663
  case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
664
  default: return 0;
665
  }
666
}
667
668
// FastEmit functions for ISD::FSQRT.
669
670
0
unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
671
0
  if (RetVT.SimpleTy != MVT::f32)
672
0
    return 0;
673
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
674
0
    return fastEmitInst_r(Mips::FSQRT_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
675
0
  }
676
0
  if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
677
0
    return fastEmitInst_r(Mips::FSQRT_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
678
0
  }
679
0
  return 0;
680
0
}
681
682
0
unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
683
0
  if (RetVT.SimpleTy != MVT::f64)
684
0
    return 0;
685
0
  if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
686
0
    return fastEmitInst_r(Mips::FSQRT_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
687
0
  }
688
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
689
0
    return fastEmitInst_r(Mips::FSQRT_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
690
0
  }
691
0
  if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
692
0
    return fastEmitInst_r(Mips::FSQRT_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
693
0
  }
694
0
  if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
695
0
    return fastEmitInst_r(Mips::FSQRT_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill);
696
0
  }
697
0
  return 0;
698
0
}
699
700
0
unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
701
0
  if (RetVT.SimpleTy != MVT::v4f32)
702
0
    return 0;
703
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
704
0
    return fastEmitInst_r(Mips::FSQRT_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
705
0
  }
706
0
  return 0;
707
0
}
708
709
0
unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
710
0
  if (RetVT.SimpleTy != MVT::v2f64)
711
0
    return 0;
712
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
713
0
    return fastEmitInst_r(Mips::FSQRT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
714
0
  }
715
0
  return 0;
716
0
}
717
718
unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
719
  switch (VT.SimpleTy) {
720
  case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill);
721
  case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0, Op0IsKill);
722
  case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
723
  case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
724
  default: return 0;
725
  }
726
}
727
728
// FastEmit functions for ISD::SIGN_EXTEND.
729
730
0
unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
731
0
  if (RetVT.SimpleTy != MVT::i64)
732
0
    return 0;
733
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())) {
734
0
    return fastEmitInst_r(Mips::SLL64_32, &Mips::GPR64RegClass, Op0, Op0IsKill);
735
0
  }
736
0
  return 0;
737
0
}
738
739
unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
740
  switch (VT.SimpleTy) {
741
  case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0, Op0IsKill);
742
  default: return 0;
743
  }
744
}
745
746
// FastEmit functions for ISD::SINT_TO_FP.
747
748
0
unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
749
0
  return fastEmitInst_r(Mips::PseudoCVT_S_W, &Mips::FGR32RegClass, Op0, Op0IsKill);
750
0
}
751
752
0
unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
753
0
  if ((Subtarget->isFP64bit())) {
754
0
    return fastEmitInst_r(Mips::PseudoCVT_D64_W, &Mips::FGR64RegClass, Op0, Op0IsKill);
755
0
  }
756
0
  if ((!Subtarget->isFP64bit())) {
757
0
    return fastEmitInst_r(Mips::PseudoCVT_D32_W, &Mips::AFGR64RegClass, Op0, Op0IsKill);
758
0
  }
759
0
  return 0;
760
0
}
761
762
unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
763
switch (RetVT.SimpleTy) {
764
  case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill);
765
  case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0, Op0IsKill);
766
  default: return 0;
767
}
768
}
769
770
0
unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
771
0
  if (RetVT.SimpleTy != MVT::f64)
772
0
    return 0;
773
0
  if ((Subtarget->isFP64bit())) {
774
0
    return fastEmitInst_r(Mips::PseudoCVT_D64_L, &Mips::FGR64RegClass, Op0, Op0IsKill);
775
0
  }
776
0
  return 0;
777
0
}
778
779
0
unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
780
0
  if (RetVT.SimpleTy != MVT::v4f32)
781
0
    return 0;
782
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
783
0
    return fastEmitInst_r(Mips::FFINT_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
784
0
  }
785
0
  return 0;
786
0
}
787
788
0
unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
789
0
  if (RetVT.SimpleTy != MVT::v2f64)
790
0
    return 0;
791
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
792
0
    return fastEmitInst_r(Mips::FFINT_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
793
0
  }
794
0
  return 0;
795
0
}
796
797
unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
798
  switch (VT.SimpleTy) {
799
  case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0, Op0IsKill);
800
  case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0, Op0IsKill);
801
  case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
802
  case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
803
  default: return 0;
804
  }
805
}
806
807
// FastEmit functions for ISD::UINT_TO_FP.
808
809
0
unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
810
0
  if (RetVT.SimpleTy != MVT::v4f32)
811
0
    return 0;
812
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
813
0
    return fastEmitInst_r(Mips::FFINT_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
814
0
  }
815
0
  return 0;
816
0
}
817
818
0
unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
819
0
  if (RetVT.SimpleTy != MVT::v2f64)
820
0
    return 0;
821
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
822
0
    return fastEmitInst_r(Mips::FFINT_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
823
0
  }
824
0
  return 0;
825
0
}
826
827
unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
828
  switch (VT.SimpleTy) {
829
  case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
830
  case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
831
  default: return 0;
832
  }
833
}
834
835
// FastEmit functions for MipsISD::JmpLink.
836
837
0
unsigned fastEmit_MipsISD_JmpLink_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
838
0
  if (RetVT.SimpleTy != MVT::isVoid)
839
0
    return 0;
840
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
841
0
    return fastEmitInst_r(Mips::JALR16_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
842
0
  }
843
0
  if ((Subtarget->inMips16Mode())) {
844
0
    return fastEmitInst_r(Mips::JumpLinkReg16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill);
845
0
  }
846
0
  if ((!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
847
0
    return fastEmitInst_r(Mips::JALRHBPseudo, &Mips::GPR32RegClass, Op0, Op0IsKill);
848
0
  }
849
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode())) {
850
0
    return fastEmitInst_r(Mips::JALRPseudo, &Mips::GPR32RegClass, Op0, Op0IsKill);
851
0
  }
852
0
  return 0;
853
0
}
854
855
0
unsigned fastEmit_MipsISD_JmpLink_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
856
0
  if (RetVT.SimpleTy != MVT::isVoid)
857
0
    return 0;
858
0
  if ((!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
859
0
    return fastEmitInst_r(Mips::JALRHB64Pseudo, &Mips::GPR64RegClass, Op0, Op0IsKill);
860
0
  }
861
0
  if ((!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMips16Mode())) {
862
0
    return fastEmitInst_r(Mips::JALR64Pseudo, &Mips::GPR64RegClass, Op0, Op0IsKill);
863
0
  }
864
0
  return 0;
865
0
}
866
867
unsigned fastEmit_MipsISD_JmpLink_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
868
  switch (VT.SimpleTy) {
869
  case MVT::i32: return fastEmit_MipsISD_JmpLink_MVT_i32_r(RetVT, Op0, Op0IsKill);
870
  case MVT::i64: return fastEmit_MipsISD_JmpLink_MVT_i64_r(RetVT, Op0, Op0IsKill);
871
  default: return 0;
872
  }
873
}
874
875
// FastEmit functions for MipsISD::MFHI.
876
877
0
unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(unsigned Op0, bool Op0IsKill) {
878
0
  if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
879
0
    return fastEmitInst_r(Mips::MFHI_DSP_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
880
0
  }
881
0
  if ((Subtarget->hasDSP())) {
882
0
    return fastEmitInst_r(Mips::MFHI_DSP, &Mips::GPR32RegClass, Op0, Op0IsKill);
883
0
  }
884
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
885
0
    return fastEmitInst_r(Mips::PseudoMFHI, &Mips::GPR32RegClass, Op0, Op0IsKill);
886
0
  }
887
0
  return 0;
888
0
}
889
890
0
unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(unsigned Op0, bool Op0IsKill) {
891
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
892
0
    return fastEmitInst_r(Mips::PseudoMFHI64, &Mips::GPR64RegClass, Op0, Op0IsKill);
893
0
  }
894
0
  return 0;
895
0
}
896
897
unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
898
switch (RetVT.SimpleTy) {
899
  case MVT::i32: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(Op0, Op0IsKill);
900
  case MVT::i64: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(Op0, Op0IsKill);
901
  default: return 0;
902
}
903
}
904
905
unsigned fastEmit_MipsISD_MFHI_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
906
  switch (VT.SimpleTy) {
907
  case MVT::Untyped: return fastEmit_MipsISD_MFHI_MVT_Untyped_r(RetVT, Op0, Op0IsKill);
908
  default: return 0;
909
  }
910
}
911
912
// FastEmit functions for MipsISD::MFLO.
913
914
0
unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(unsigned Op0, bool Op0IsKill) {
915
0
  if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
916
0
    return fastEmitInst_r(Mips::MFLO_DSP_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
917
0
  }
918
0
  if ((Subtarget->hasDSP())) {
919
0
    return fastEmitInst_r(Mips::MFLO_DSP, &Mips::GPR32RegClass, Op0, Op0IsKill);
920
0
  }
921
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
922
0
    return fastEmitInst_r(Mips::PseudoMFLO, &Mips::GPR32RegClass, Op0, Op0IsKill);
923
0
  }
924
0
  return 0;
925
0
}
926
927
0
unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(unsigned Op0, bool Op0IsKill) {
928
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
929
0
    return fastEmitInst_r(Mips::PseudoMFLO64, &Mips::GPR64RegClass, Op0, Op0IsKill);
930
0
  }
931
0
  return 0;
932
0
}
933
934
unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
935
switch (RetVT.SimpleTy) {
936
  case MVT::i32: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(Op0, Op0IsKill);
937
  case MVT::i64: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(Op0, Op0IsKill);
938
  default: return 0;
939
}
940
}
941
942
unsigned fastEmit_MipsISD_MFLO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
943
  switch (VT.SimpleTy) {
944
  case MVT::Untyped: return fastEmit_MipsISD_MFLO_MVT_Untyped_r(RetVT, Op0, Op0IsKill);
945
  default: return 0;
946
  }
947
}
948
949
// FastEmit functions for MipsISD::MTC1_D64.
950
951
0
unsigned fastEmit_MipsISD_MTC1_D64_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
952
0
  if (RetVT.SimpleTy != MVT::f64)
953
0
    return 0;
954
0
  if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
955
0
    return fastEmitInst_r(Mips::MTC1_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
956
0
  }
957
0
  return 0;
958
0
}
959
960
unsigned fastEmit_MipsISD_MTC1_D64_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
961
  switch (VT.SimpleTy) {
962
  case MVT::i32: return fastEmit_MipsISD_MTC1_D64_MVT_i32_r(RetVT, Op0, Op0IsKill);
963
  default: return 0;
964
  }
965
}
966
967
// FastEmit functions for MipsISD::TailCall.
968
969
0
unsigned fastEmit_MipsISD_TailCall_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
970
0
  if (RetVT.SimpleTy != MVT::isVoid)
971
0
    return 0;
972
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
973
0
    return fastEmitInst_r(Mips::TAILCALLREG_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
974
0
  }
975
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
976
0
    return fastEmitInst_r(Mips::TAILCALLREG_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
977
0
  }
978
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
979
0
    return fastEmitInst_r(Mips::TAILCALLHBR6REG, &Mips::GPR32RegClass, Op0, Op0IsKill);
980
0
  }
981
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
982
0
    return fastEmitInst_r(Mips::TAILCALLR6REG, &Mips::GPR32RegClass, Op0, Op0IsKill);
983
0
  }
984
0
  if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
985
0
    return fastEmitInst_r(Mips::TAILCALLREGHB, &Mips::GPR32RegClass, Op0, Op0IsKill);
986
0
  }
987
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
988
0
    return fastEmitInst_r(Mips::TAILCALLREG, &Mips::GPR32RegClass, Op0, Op0IsKill);
989
0
  }
990
0
  return 0;
991
0
}
992
993
0
unsigned fastEmit_MipsISD_TailCall_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
994
0
  if (RetVT.SimpleTy != MVT::isVoid)
995
0
    return 0;
996
0
  if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
997
0
    return fastEmitInst_r(Mips::TAILCALLHB64R6REG, &Mips::GPR64RegClass, Op0, Op0IsKill);
998
0
  }
999
0
  if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
1000
0
    return fastEmitInst_r(Mips::TAILCALL64R6REG, &Mips::GPR64RegClass, Op0, Op0IsKill);
1001
0
  }
1002
0
  if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
1003
0
    return fastEmitInst_r(Mips::TAILCALLREGHB64, &Mips::GPR64RegClass, Op0, Op0IsKill);
1004
0
  }
1005
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1006
0
    return fastEmitInst_r(Mips::TAILCALLREG64, &Mips::GPR64RegClass, Op0, Op0IsKill);
1007
0
  }
1008
0
  return 0;
1009
0
}
1010
1011
unsigned fastEmit_MipsISD_TailCall_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1012
  switch (VT.SimpleTy) {
1013
  case MVT::i32: return fastEmit_MipsISD_TailCall_MVT_i32_r(RetVT, Op0, Op0IsKill);
1014
  case MVT::i64: return fastEmit_MipsISD_TailCall_MVT_i64_r(RetVT, Op0, Op0IsKill);
1015
  default: return 0;
1016
  }
1017
}
1018
1019
// FastEmit functions for MipsISD::TruncIntFP.
1020
1021
0
unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
1022
0
  if ((Subtarget->hasStandardEncoding())) {
1023
0
    return fastEmitInst_r(Mips::TRUNC_W_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
1024
0
  }
1025
0
  return 0;
1026
0
}
1027
1028
0
unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
1029
0
  if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
1030
0
    return fastEmitInst_r(Mips::TRUNC_L_S, &Mips::FGR64RegClass, Op0, Op0IsKill);
1031
0
  }
1032
0
  return 0;
1033
0
}
1034
1035
unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1036
switch (RetVT.SimpleTy) {
1037
  case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(Op0, Op0IsKill);
1038
  case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(Op0, Op0IsKill);
1039
  default: return 0;
1040
}
1041
}
1042
1043
0
unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
1044
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1045
0
    return fastEmitInst_r(Mips::TRUNC_W_D_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill);
1046
0
  }
1047
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())) {
1048
0
    return fastEmitInst_r(Mips::TRUNC_W_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
1049
0
  }
1050
0
  if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
1051
0
    return fastEmitInst_r(Mips::TRUNC_W_D64, &Mips::FGR32RegClass, Op0, Op0IsKill);
1052
0
  }
1053
0
  if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1054
0
    return fastEmitInst_r(Mips::TRUNC_W_D32, &Mips::FGR32RegClass, Op0, Op0IsKill);
1055
0
  }
1056
0
  return 0;
1057
0
}
1058
1059
0
unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
1060
0
  if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
1061
0
    return fastEmitInst_r(Mips::TRUNC_L_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
1062
0
  }
1063
0
  return 0;
1064
0
}
1065
1066
unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1067
switch (RetVT.SimpleTy) {
1068
  case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(Op0, Op0IsKill);
1069
  case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(Op0, Op0IsKill);
1070
  default: return 0;
1071
}
1072
}
1073
1074
unsigned fastEmit_MipsISD_TruncIntFP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1075
  switch (VT.SimpleTy) {
1076
  case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_r(RetVT, Op0, Op0IsKill);
1077
  case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_r(RetVT, Op0, Op0IsKill);
1078
  default: return 0;
1079
  }
1080
}
1081
1082
// FastEmit functions for MipsISD::VALL_NONZERO.
1083
1084
0
unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1085
0
  if (RetVT.SimpleTy != MVT::i32)
1086
0
    return 0;
1087
0
  return fastEmitInst_r(Mips::SNZ_B_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1088
0
}
1089
1090
0
unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1091
0
  if (RetVT.SimpleTy != MVT::i32)
1092
0
    return 0;
1093
0
  return fastEmitInst_r(Mips::SNZ_H_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1094
0
}
1095
1096
0
unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1097
0
  if (RetVT.SimpleTy != MVT::i32)
1098
0
    return 0;
1099
0
  return fastEmitInst_r(Mips::SNZ_W_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1100
0
}
1101
1102
0
unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1103
0
  if (RetVT.SimpleTy != MVT::i32)
1104
0
    return 0;
1105
0
  return fastEmitInst_r(Mips::SNZ_D_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1106
0
}
1107
1108
unsigned fastEmit_MipsISD_VALL_NONZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1109
  switch (VT.SimpleTy) {
1110
  case MVT::v16i8: return fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
1111
  case MVT::v8i16: return fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
1112
  case MVT::v4i32: return fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
1113
  case MVT::v2i64: return fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
1114
  default: return 0;
1115
  }
1116
}
1117
1118
// FastEmit functions for MipsISD::VALL_ZERO.
1119
1120
0
unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1121
0
  if (RetVT.SimpleTy != MVT::i32)
1122
0
    return 0;
1123
0
  return fastEmitInst_r(Mips::SZ_B_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1124
0
}
1125
1126
0
unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1127
0
  if (RetVT.SimpleTy != MVT::i32)
1128
0
    return 0;
1129
0
  return fastEmitInst_r(Mips::SZ_H_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1130
0
}
1131
1132
0
unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1133
0
  if (RetVT.SimpleTy != MVT::i32)
1134
0
    return 0;
1135
0
  return fastEmitInst_r(Mips::SZ_W_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1136
0
}
1137
1138
0
unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1139
0
  if (RetVT.SimpleTy != MVT::i32)
1140
0
    return 0;
1141
0
  return fastEmitInst_r(Mips::SZ_D_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1142
0
}
1143
1144
unsigned fastEmit_MipsISD_VALL_ZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1145
  switch (VT.SimpleTy) {
1146
  case MVT::v16i8: return fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
1147
  case MVT::v8i16: return fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
1148
  case MVT::v4i32: return fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
1149
  case MVT::v2i64: return fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
1150
  default: return 0;
1151
  }
1152
}
1153
1154
// FastEmit functions for MipsISD::VANY_NONZERO.
1155
1156
0
unsigned fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1157
0
  if (RetVT.SimpleTy != MVT::i32)
1158
0
    return 0;
1159
0
  return fastEmitInst_r(Mips::SNZ_V_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1160
0
}
1161
1162
unsigned fastEmit_MipsISD_VANY_NONZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1163
  switch (VT.SimpleTy) {
1164
  case MVT::v16i8: return fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
1165
  default: return 0;
1166
  }
1167
}
1168
1169
// FastEmit functions for MipsISD::VANY_ZERO.
1170
1171
0
unsigned fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1172
0
  if (RetVT.SimpleTy != MVT::i32)
1173
0
    return 0;
1174
0
  return fastEmitInst_r(Mips::SZ_V_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
1175
0
}
1176
1177
unsigned fastEmit_MipsISD_VANY_ZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1178
  switch (VT.SimpleTy) {
1179
  case MVT::v16i8: return fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
1180
  default: return 0;
1181
  }
1182
}
1183
1184
// Top-level FastEmit function.
1185
1186
4
unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill) override {
1187
4
  switch (Opcode) {
1188
4
  
case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0, Op0IsKill)0
;
1189
4
  
case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0, Op0IsKill)0
;
1190
4
  
case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill)0
;
1191
4
  
case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill)0
;
1192
4
  
case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill)0
;
1193
4
  
case ISD::FEXP2: return fastEmit_ISD_FEXP2_r(VT, RetVT, Op0, Op0IsKill)0
;
1194
4
  
case ISD::FLOG2: return fastEmit_ISD_FLOG2_r(VT, RetVT, Op0, Op0IsKill)0
;
1195
4
  
case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill)0
;
1196
4
  
case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill)0
;
1197
4
  
case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill)0
;
1198
4
  case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill);
1199
4
  
case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill)0
;
1200
4
  
case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0, Op0IsKill)0
;
1201
4
  
case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill)0
;
1202
4
  
case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill)0
;
1203
4
  
case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill)0
;
1204
4
  
case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill)0
;
1205
4
  
case MipsISD::JmpLink: return fastEmit_MipsISD_JmpLink_r(VT, RetVT, Op0, Op0IsKill)0
;
1206
4
  
case MipsISD::MFHI: return fastEmit_MipsISD_MFHI_r(VT, RetVT, Op0, Op0IsKill)0
;
1207
4
  
case MipsISD::MFLO: return fastEmit_MipsISD_MFLO_r(VT, RetVT, Op0, Op0IsKill)0
;
1208
4
  
case MipsISD::MTC1_D64: return fastEmit_MipsISD_MTC1_D64_r(VT, RetVT, Op0, Op0IsKill)0
;
1209
4
  
case MipsISD::TailCall: return fastEmit_MipsISD_TailCall_r(VT, RetVT, Op0, Op0IsKill)0
;
1210
4
  
case MipsISD::TruncIntFP: return fastEmit_MipsISD_TruncIntFP_r(VT, RetVT, Op0, Op0IsKill)0
;
1211
4
  
case MipsISD::VALL_NONZERO: return fastEmit_MipsISD_VALL_NONZERO_r(VT, RetVT, Op0, Op0IsKill)0
;
1212
4
  
case MipsISD::VALL_ZERO: return fastEmit_MipsISD_VALL_ZERO_r(VT, RetVT, Op0, Op0IsKill)0
;
1213
4
  
case MipsISD::VANY_NONZERO: return fastEmit_MipsISD_VANY_NONZERO_r(VT, RetVT, Op0, Op0IsKill)0
;
1214
4
  
case MipsISD::VANY_ZERO: return fastEmit_MipsISD_VANY_ZERO_r(VT, RetVT, Op0, Op0IsKill)0
;
1215
4
  
default: return 00
;
1216
4
  }
1217
4
}
1218
1219
// FastEmit functions for ISD::ADD.
1220
1221
6
unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1222
6
  if (RetVT.SimpleTy != MVT::i32)
1223
0
    return 0;
1224
6
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->inMicroMipsMode())0
) {
1225
0
    return fastEmitInst_rr(Mips::ADDU16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1226
0
  }
1227
6
  if ((Subtarget->inMips16Mode())) {
1228
0
    return fastEmitInst_rr(Mips::AdduRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1229
0
  }
1230
6
  if ((Subtarget->inMicroMipsMode()) && 
(!Subtarget->hasMips32r6())0
) {
1231
0
    return fastEmitInst_rr(Mips::ADDu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1232
0
  }
1233
6
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1234
6
    return fastEmitInst_rr(Mips::ADDu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1235
6
  }
1236
0
  return 0;
1237
0
}
1238
1239
0
unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1240
0
  if (RetVT.SimpleTy != MVT::i64)
1241
0
    return 0;
1242
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1243
0
    return fastEmitInst_rr(Mips::DADDu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1244
0
  }
1245
0
  return 0;
1246
0
}
1247
1248
0
unsigned fastEmit_ISD_ADD_MVT_v4i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1249
0
  if (RetVT.SimpleTy != MVT::v4i8)
1250
0
    return 0;
1251
0
  if ((Subtarget->hasDSP())) {
1252
0
    return fastEmitInst_rr(Mips::ADDU_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1253
0
  }
1254
0
  return 0;
1255
0
}
1256
1257
0
unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1258
0
  if (RetVT.SimpleTy != MVT::v16i8)
1259
0
    return 0;
1260
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1261
0
    return fastEmitInst_rr(Mips::ADDV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1262
0
  }
1263
0
  return 0;
1264
0
}
1265
1266
0
unsigned fastEmit_ISD_ADD_MVT_v2i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1267
0
  if (RetVT.SimpleTy != MVT::v2i16)
1268
0
    return 0;
1269
0
  if ((Subtarget->hasDSP())) {
1270
0
    return fastEmitInst_rr(Mips::ADDQ_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1271
0
  }
1272
0
  return 0;
1273
0
}
1274
1275
0
unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1276
0
  if (RetVT.SimpleTy != MVT::v8i16)
1277
0
    return 0;
1278
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1279
0
    return fastEmitInst_rr(Mips::ADDV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1280
0
  }
1281
0
  return 0;
1282
0
}
1283
1284
0
unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1285
0
  if (RetVT.SimpleTy != MVT::v4i32)
1286
0
    return 0;
1287
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1288
0
    return fastEmitInst_rr(Mips::ADDV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1289
0
  }
1290
0
  return 0;
1291
0
}
1292
1293
0
unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1294
0
  if (RetVT.SimpleTy != MVT::v2i64)
1295
0
    return 0;
1296
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1297
0
    return fastEmitInst_rr(Mips::ADDV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1298
0
  }
1299
0
  return 0;
1300
0
}
1301
1302
6
unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1303
6
  switch (VT.SimpleTy) {
1304
6
  case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1305
6
  
case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1306
6
  
case MVT::v4i8: return fastEmit_ISD_ADD_MVT_v4i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1307
6
  
case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1308
6
  
case MVT::v2i16: return fastEmit_ISD_ADD_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1309
6
  
case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1310
6
  
case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1311
6
  
case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1312
6
  
default: return 00
;
1313
6
  }
1314
6
}
1315
1316
// FastEmit functions for ISD::ADDC.
1317
1318
0
unsigned fastEmit_ISD_ADDC_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1319
0
  if (RetVT.SimpleTy != MVT::i32)
1320
0
    return 0;
1321
0
  if ((Subtarget->hasDSP())) {
1322
0
    return fastEmitInst_rr(Mips::ADDSC, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1323
0
  }
1324
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP())) {
1325
0
    return fastEmitInst_rr(Mips::ADDu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1326
0
  }
1327
0
  return 0;
1328
0
}
1329
1330
0
unsigned fastEmit_ISD_ADDC_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1331
0
  if (RetVT.SimpleTy != MVT::i64)
1332
0
    return 0;
1333
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->hasDSP()) && (!Subtarget->inMicroMipsMode())) {
1334
0
    return fastEmitInst_rr(Mips::DADDu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1335
0
  }
1336
0
  return 0;
1337
0
}
1338
1339
unsigned fastEmit_ISD_ADDC_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1340
  switch (VT.SimpleTy) {
1341
  case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1342
  case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1343
  default: return 0;
1344
  }
1345
}
1346
1347
// FastEmit functions for ISD::ADDE.
1348
1349
0
unsigned fastEmit_ISD_ADDE_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1350
0
  if (RetVT.SimpleTy != MVT::i32)
1351
0
    return 0;
1352
0
  if ((Subtarget->hasDSP())) {
1353
0
    return fastEmitInst_rr(Mips::ADDWC, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1354
0
  }
1355
0
  return 0;
1356
0
}
1357
1358
unsigned fastEmit_ISD_ADDE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1359
  switch (VT.SimpleTy) {
1360
  case MVT::i32: return fastEmit_ISD_ADDE_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1361
  default: return 0;
1362
  }
1363
}
1364
1365
// FastEmit functions for ISD::AND.
1366
1367
5
unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1368
5
  if (RetVT.SimpleTy != MVT::i32)
1369
0
    return 0;
1370
5
  if ((Subtarget->inMips16Mode())) {
1371
0
    return fastEmitInst_rr(Mips::AndRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1372
0
  }
1373
5
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->inMicroMipsMode())0
) {
1374
0
    return fastEmitInst_rr(Mips::AND_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1375
0
  }
1376
5
  if ((Subtarget->inMicroMipsMode()) && 
(!Subtarget->hasMips32r6())0
) {
1377
0
    return fastEmitInst_rr(Mips::AND_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1378
0
  }
1379
5
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1380
5
    return fastEmitInst_rr(Mips::AND, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1381
5
  }
1382
0
  return 0;
1383
0
}
1384
1385
0
unsigned fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1386
0
  if (RetVT.SimpleTy != MVT::i64)
1387
0
    return 0;
1388
0
  if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
1389
0
    return fastEmitInst_rr(Mips::AND64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1390
0
  }
1391
0
  return 0;
1392
0
}
1393
1394
0
unsigned fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1395
0
  if (RetVT.SimpleTy != MVT::v16i8)
1396
0
    return 0;
1397
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1398
0
    return fastEmitInst_rr(Mips::AND_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1399
0
  }
1400
0
  return 0;
1401
0
}
1402
1403
0
unsigned fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1404
0
  if (RetVT.SimpleTy != MVT::v8i16)
1405
0
    return 0;
1406
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1407
0
    return fastEmitInst_rr(Mips::AND_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1408
0
  }
1409
0
  return 0;
1410
0
}
1411
1412
0
unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1413
0
  if (RetVT.SimpleTy != MVT::v4i32)
1414
0
    return 0;
1415
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1416
0
    return fastEmitInst_rr(Mips::AND_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1417
0
  }
1418
0
  return 0;
1419
0
}
1420
1421
0
unsigned fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1422
0
  if (RetVT.SimpleTy != MVT::v2i64)
1423
0
    return 0;
1424
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1425
0
    return fastEmitInst_rr(Mips::AND_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1426
0
  }
1427
0
  return 0;
1428
0
}
1429
1430
5
unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1431
5
  switch (VT.SimpleTy) {
1432
5
  case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1433
5
  
case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1434
5
  
case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1435
5
  
case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1436
5
  
case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1437
5
  
case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1438
5
  
default: return 00
;
1439
5
  }
1440
5
}
1441
1442
// FastEmit functions for ISD::FADD.
1443
1444
0
unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1445
0
  if (RetVT.SimpleTy != MVT::f32)
1446
0
    return 0;
1447
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1448
0
    return fastEmitInst_rr(Mips::FADD_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1449
0
  }
1450
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1451
0
    return fastEmitInst_rr(Mips::FADD_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1452
0
  }
1453
0
  return 0;
1454
0
}
1455
1456
0
unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1457
0
  if (RetVT.SimpleTy != MVT::f64)
1458
0
    return 0;
1459
0
  if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
1460
0
    return fastEmitInst_rr(Mips::FADD_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1461
0
  }
1462
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1463
0
    return fastEmitInst_rr(Mips::FADD_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1464
0
  }
1465
0
  if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1466
0
    return fastEmitInst_rr(Mips::FADD_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1467
0
  }
1468
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1469
0
    return fastEmitInst_rr(Mips::FADD_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1470
0
  }
1471
0
  return 0;
1472
0
}
1473
1474
0
unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1475
0
  if (RetVT.SimpleTy != MVT::v4f32)
1476
0
    return 0;
1477
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1478
0
    return fastEmitInst_rr(Mips::FADD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1479
0
  }
1480
0
  return 0;
1481
0
}
1482
1483
0
unsigned fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1484
0
  if (RetVT.SimpleTy != MVT::v2f64)
1485
0
    return 0;
1486
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1487
0
    return fastEmitInst_rr(Mips::FADD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1488
0
  }
1489
0
  return 0;
1490
0
}
1491
1492
unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1493
  switch (VT.SimpleTy) {
1494
  case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1495
  case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1496
  case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1497
  case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1498
  default: return 0;
1499
  }
1500
}
1501
1502
// FastEmit functions for ISD::FDIV.
1503
1504
0
unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1505
0
  if (RetVT.SimpleTy != MVT::f32)
1506
0
    return 0;
1507
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1508
0
    return fastEmitInst_rr(Mips::FDIV_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1509
0
  }
1510
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1511
0
    return fastEmitInst_rr(Mips::FDIV_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1512
0
  }
1513
0
  return 0;
1514
0
}
1515
1516
0
unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1517
0
  if (RetVT.SimpleTy != MVT::f64)
1518
0
    return 0;
1519
0
  if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
1520
0
    return fastEmitInst_rr(Mips::FDIV_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1521
0
  }
1522
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1523
0
    return fastEmitInst_rr(Mips::FDIV_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1524
0
  }
1525
0
  if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1526
0
    return fastEmitInst_rr(Mips::FDIV_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1527
0
  }
1528
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1529
0
    return fastEmitInst_rr(Mips::FDIV_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1530
0
  }
1531
0
  return 0;
1532
0
}
1533
1534
0
unsigned fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1535
0
  if (RetVT.SimpleTy != MVT::v4f32)
1536
0
    return 0;
1537
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1538
0
    return fastEmitInst_rr(Mips::FDIV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1539
0
  }
1540
0
  return 0;
1541
0
}
1542
1543
0
unsigned fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1544
0
  if (RetVT.SimpleTy != MVT::v2f64)
1545
0
    return 0;
1546
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1547
0
    return fastEmitInst_rr(Mips::FDIV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1548
0
  }
1549
0
  return 0;
1550
0
}
1551
1552
unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1553
  switch (VT.SimpleTy) {
1554
  case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1555
  case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1556
  case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1557
  case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1558
  default: return 0;
1559
  }
1560
}
1561
1562
// FastEmit functions for ISD::FMUL.
1563
1564
0
unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1565
0
  if (RetVT.SimpleTy != MVT::f32)
1566
0
    return 0;
1567
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1568
0
    return fastEmitInst_rr(Mips::FMUL_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1569
0
  }
1570
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1571
0
    return fastEmitInst_rr(Mips::FMUL_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1572
0
  }
1573
0
  return 0;
1574
0
}
1575
1576
0
unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1577
0
  if (RetVT.SimpleTy != MVT::f64)
1578
0
    return 0;
1579
0
  if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
1580
0
    return fastEmitInst_rr(Mips::FMUL_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1581
0
  }
1582
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1583
0
    return fastEmitInst_rr(Mips::FMUL_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1584
0
  }
1585
0
  if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1586
0
    return fastEmitInst_rr(Mips::FMUL_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1587
0
  }
1588
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1589
0
    return fastEmitInst_rr(Mips::FMUL_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1590
0
  }
1591
0
  return 0;
1592
0
}
1593
1594
0
unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1595
0
  if (RetVT.SimpleTy != MVT::v4f32)
1596
0
    return 0;
1597
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1598
0
    return fastEmitInst_rr(Mips::FMUL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1599
0
  }
1600
0
  return 0;
1601
0
}
1602
1603
0
unsigned fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1604
0
  if (RetVT.SimpleTy != MVT::v2f64)
1605
0
    return 0;
1606
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1607
0
    return fastEmitInst_rr(Mips::FMUL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1608
0
  }
1609
0
  return 0;
1610
0
}
1611
1612
unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1613
  switch (VT.SimpleTy) {
1614
  case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1615
  case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1616
  case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1617
  case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1618
  default: return 0;
1619
  }
1620
}
1621
1622
// FastEmit functions for ISD::FSUB.
1623
1624
0
unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1625
0
  if (RetVT.SimpleTy != MVT::f32)
1626
0
    return 0;
1627
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1628
0
    return fastEmitInst_rr(Mips::FSUB_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1629
0
  }
1630
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1631
0
    return fastEmitInst_rr(Mips::FSUB_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1632
0
  }
1633
0
  return 0;
1634
0
}
1635
1636
0
unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1637
0
  if (RetVT.SimpleTy != MVT::f64)
1638
0
    return 0;
1639
0
  if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
1640
0
    return fastEmitInst_rr(Mips::FSUB_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1641
0
  }
1642
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1643
0
    return fastEmitInst_rr(Mips::FSUB_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1644
0
  }
1645
0
  if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1646
0
    return fastEmitInst_rr(Mips::FSUB_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1647
0
  }
1648
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1649
0
    return fastEmitInst_rr(Mips::FSUB_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1650
0
  }
1651
0
  return 0;
1652
0
}
1653
1654
0
unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1655
0
  if (RetVT.SimpleTy != MVT::v4f32)
1656
0
    return 0;
1657
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1658
0
    return fastEmitInst_rr(Mips::FSUB_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1659
0
  }
1660
0
  return 0;
1661
0
}
1662
1663
0
unsigned fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1664
0
  if (RetVT.SimpleTy != MVT::v2f64)
1665
0
    return 0;
1666
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1667
0
    return fastEmitInst_rr(Mips::FSUB_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1668
0
  }
1669
0
  return 0;
1670
0
}
1671
1672
unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1673
  switch (VT.SimpleTy) {
1674
  case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1675
  case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1676
  case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1677
  case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1678
  default: return 0;
1679
  }
1680
}
1681
1682
// FastEmit functions for ISD::MUL.
1683
1684
2
unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1685
2
  if (RetVT.SimpleTy != MVT::i32)
1686
0
    return 0;
1687
2
  if ((Subtarget->inMips16Mode())) {
1688
0
    return fastEmitInst_rr(Mips::MultRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1689
0
  }
1690
2
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->inMicroMipsMode())0
) {
1691
0
    return fastEmitInst_rr(Mips::MUL_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1692
0
  }
1693
2
  if ((Subtarget->inMicroMipsMode()) && 
(!Subtarget->hasMips32r6())0
) {
1694
0
    return fastEmitInst_rr(Mips::MUL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1695
0
  }
1696
2
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->hasStandardEncoding())0
&&
(!Subtarget->inMicroMipsMode())0
) {
1697
0
    return fastEmitInst_rr(Mips::MUL_R6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1698
0
  }
1699
2
  if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1700
2
    return fastEmitInst_rr(Mips::MUL, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1701
2
  }
1702
0
  return 0;
1703
0
}
1704
1705
0
unsigned fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1706
0
  if (RetVT.SimpleTy != MVT::i64)
1707
0
    return 0;
1708
0
  if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1709
0
    return fastEmitInst_rr(Mips::DMUL_R6, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1710
0
  }
1711
0
  if ((Subtarget->hasCnMips())) {
1712
0
    return fastEmitInst_rr(Mips::DMUL, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1713
0
  }
1714
0
  return 0;
1715
0
}
1716
1717
0
unsigned fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1718
0
  if (RetVT.SimpleTy != MVT::v16i8)
1719
0
    return 0;
1720
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1721
0
    return fastEmitInst_rr(Mips::MULV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1722
0
  }
1723
0
  return 0;
1724
0
}
1725
1726
0
unsigned fastEmit_ISD_MUL_MVT_v2i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1727
0
  if (RetVT.SimpleTy != MVT::v2i16)
1728
0
    return 0;
1729
0
  if ((Subtarget->hasDSPR2())) {
1730
0
    return fastEmitInst_rr(Mips::MUL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1731
0
  }
1732
0
  return 0;
1733
0
}
1734
1735
0
unsigned fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1736
0
  if (RetVT.SimpleTy != MVT::v8i16)
1737
0
    return 0;
1738
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1739
0
    return fastEmitInst_rr(Mips::MULV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1740
0
  }
1741
0
  return 0;
1742
0
}
1743
1744
0
unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1745
0
  if (RetVT.SimpleTy != MVT::v4i32)
1746
0
    return 0;
1747
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1748
0
    return fastEmitInst_rr(Mips::MULV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1749
0
  }
1750
0
  return 0;
1751
0
}
1752
1753
0
unsigned fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1754
0
  if (RetVT.SimpleTy != MVT::v2i64)
1755
0
    return 0;
1756
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1757
0
    return fastEmitInst_rr(Mips::MULV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1758
0
  }
1759
0
  return 0;
1760
0
}
1761
1762
2
unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1763
2
  switch (VT.SimpleTy) {
1764
2
  case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1765
2
  
case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1766
2
  
case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1767
2
  
case MVT::v2i16: return fastEmit_ISD_MUL_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1768
2
  
case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1769
2
  
case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1770
2
  
case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1771
2
  
default: return 00
;
1772
2
  }
1773
2
}
1774
1775
// FastEmit functions for ISD::MULHS.
1776
1777
0
unsigned fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1778
0
  if (RetVT.SimpleTy != MVT::i32)
1779
0
    return 0;
1780
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1781
0
    return fastEmitInst_rr(Mips::MUH_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1782
0
  }
1783
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1784
0
    return fastEmitInst_rr(Mips::MUH, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1785
0
  }
1786
0
  return 0;
1787
0
}
1788
1789
0
unsigned fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1790
0
  if (RetVT.SimpleTy != MVT::i64)
1791
0
    return 0;
1792
0
  if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1793
0
    return fastEmitInst_rr(Mips::DMUH, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1794
0
  }
1795
0
  return 0;
1796
0
}
1797
1798
unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1799
  switch (VT.SimpleTy) {
1800
  case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1801
  case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1802
  default: return 0;
1803
  }
1804
}
1805
1806
// FastEmit functions for ISD::MULHU.
1807
1808
0
unsigned fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1809
0
  if (RetVT.SimpleTy != MVT::i32)
1810
0
    return 0;
1811
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1812
0
    return fastEmitInst_rr(Mips::MUHU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1813
0
  }
1814
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1815
0
    return fastEmitInst_rr(Mips::MUHU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1816
0
  }
1817
0
  return 0;
1818
0
}
1819
1820
0
unsigned fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1821
0
  if (RetVT.SimpleTy != MVT::i64)
1822
0
    return 0;
1823
0
  if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1824
0
    return fastEmitInst_rr(Mips::DMUHU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1825
0
  }
1826
0
  return 0;
1827
0
}
1828
1829
unsigned fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1830
  switch (VT.SimpleTy) {
1831
  case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1832
  case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1833
  default: return 0;
1834
  }
1835
}
1836
1837
// FastEmit functions for ISD::OR.
1838
1839
4
unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1840
4
  if (RetVT.SimpleTy != MVT::i32)
1841
0
    return 0;
1842
4
  if ((Subtarget->inMips16Mode())) {
1843
0
    return fastEmitInst_rr(Mips::OrRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1844
0
  }
1845
4
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->inMicroMipsMode())0
) {
1846
0
    return fastEmitInst_rr(Mips::OR_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1847
0
  }
1848
4
  if ((Subtarget->inMicroMipsMode()) && 
(!Subtarget->hasMips32r6())0
) {
1849
0
    return fastEmitInst_rr(Mips::OR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1850
0
  }
1851
4
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1852
4
    return fastEmitInst_rr(Mips::OR, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1853
4
  }
1854
0
  return 0;
1855
0
}
1856
1857
0
unsigned fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1858
0
  if (RetVT.SimpleTy != MVT::i64)
1859
0
    return 0;
1860
0
  if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
1861
0
    return fastEmitInst_rr(Mips::OR64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1862
0
  }
1863
0
  return 0;
1864
0
}
1865
1866
0
unsigned fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1867
0
  if (RetVT.SimpleTy != MVT::v16i8)
1868
0
    return 0;
1869
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1870
0
    return fastEmitInst_rr(Mips::OR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1871
0
  }
1872
0
  return 0;
1873
0
}
1874
1875
0
unsigned fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1876
0
  if (RetVT.SimpleTy != MVT::v8i16)
1877
0
    return 0;
1878
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1879
0
    return fastEmitInst_rr(Mips::OR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1880
0
  }
1881
0
  return 0;
1882
0
}
1883
1884
0
unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1885
0
  if (RetVT.SimpleTy != MVT::v4i32)
1886
0
    return 0;
1887
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1888
0
    return fastEmitInst_rr(Mips::OR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1889
0
  }
1890
0
  return 0;
1891
0
}
1892
1893
0
unsigned fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1894
0
  if (RetVT.SimpleTy != MVT::v2i64)
1895
0
    return 0;
1896
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1897
0
    return fastEmitInst_rr(Mips::OR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1898
0
  }
1899
0
  return 0;
1900
0
}
1901
1902
4
unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1903
4
  switch (VT.SimpleTy) {
1904
4
  case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1905
4
  
case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1906
4
  
case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1907
4
  
case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1908
4
  
case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1909
4
  
case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1910
4
  
default: return 00
;
1911
4
  }
1912
4
}
1913
1914
// FastEmit functions for ISD::ROTR.
1915
1916
0
unsigned fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1917
0
  if (RetVT.SimpleTy != MVT::i32)
1918
0
    return 0;
1919
0
  if ((Subtarget->inMicroMipsMode())) {
1920
0
    return fastEmitInst_rr(Mips::ROTRV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1921
0
  }
1922
0
  if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1923
0
    return fastEmitInst_rr(Mips::ROTRV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1924
0
  }
1925
0
  return 0;
1926
0
}
1927
1928
unsigned fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1929
  switch (VT.SimpleTy) {
1930
  case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1931
  default: return 0;
1932
  }
1933
}
1934
1935
// FastEmit functions for ISD::SDIV.
1936
1937
4
unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1938
4
  if (RetVT.SimpleTy != MVT::i32)
1939
0
    return 0;
1940
4
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->inMicroMipsMode())0
) {
1941
0
    return fastEmitInst_rr(Mips::DIV_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1942
0
  }
1943
4
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->hasStandardEncoding())0
&&
(!Subtarget->inMicroMipsMode())0
) {
1944
0
    return fastEmitInst_rr(Mips::DIV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1945
0
  }
1946
4
  return 0;
1947
4
}
1948
1949
0
unsigned fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1950
0
  if (RetVT.SimpleTy != MVT::i64)
1951
0
    return 0;
1952
0
  if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1953
0
    return fastEmitInst_rr(Mips::DDIV, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1954
0
  }
1955
0
  return 0;
1956
0
}
1957
1958
0
unsigned fastEmit_ISD_SDIV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1959
0
  if (RetVT.SimpleTy != MVT::v16i8)
1960
0
    return 0;
1961
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1962
0
    return fastEmitInst_rr(Mips::DIV_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1963
0
  }
1964
0
  return 0;
1965
0
}
1966
1967
0
unsigned fastEmit_ISD_SDIV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1968
0
  if (RetVT.SimpleTy != MVT::v8i16)
1969
0
    return 0;
1970
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1971
0
    return fastEmitInst_rr(Mips::DIV_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1972
0
  }
1973
0
  return 0;
1974
0
}
1975
1976
0
unsigned fastEmit_ISD_SDIV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1977
0
  if (RetVT.SimpleTy != MVT::v4i32)
1978
0
    return 0;
1979
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1980
0
    return fastEmitInst_rr(Mips::DIV_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1981
0
  }
1982
0
  return 0;
1983
0
}
1984
1985
0
unsigned fastEmit_ISD_SDIV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1986
0
  if (RetVT.SimpleTy != MVT::v2i64)
1987
0
    return 0;
1988
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1989
0
    return fastEmitInst_rr(Mips::DIV_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1990
0
  }
1991
0
  return 0;
1992
0
}
1993
1994
4
unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1995
4
  switch (VT.SimpleTy) {
1996
4
  case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1997
4
  
case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1998
4
  
case MVT::v16i8: return fastEmit_ISD_SDIV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1999
4
  
case MVT::v8i16: return fastEmit_ISD_SDIV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2000
4
  
case MVT::v4i32: return fastEmit_ISD_SDIV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2001
4
  
case MVT::v2i64: return fastEmit_ISD_SDIV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2002
4
  
default: return 00
;
2003
4
  }
2004
4
}
2005
2006
// FastEmit functions for ISD::SHL.
2007
2008
0
unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2009
0
  if (RetVT.SimpleTy != MVT::i32)
2010
0
    return 0;
2011
0
  if ((Subtarget->inMicroMipsMode())) {
2012
0
    return fastEmitInst_rr(Mips::SLLV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2013
0
  }
2014
0
  if ((Subtarget->inMips16Mode())) {
2015
0
    return fastEmitInst_rr(Mips::SllvRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2016
0
  }
2017
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2018
0
    return fastEmitInst_rr(Mips::SLLV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2019
0
  }
2020
0
  return 0;
2021
0
}
2022
2023
0
unsigned fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2024
0
  if (RetVT.SimpleTy != MVT::v16i8)
2025
0
    return 0;
2026
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2027
0
    return fastEmitInst_rr(Mips::SLL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2028
0
  }
2029
0
  return 0;
2030
0
}
2031
2032
0
unsigned fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2033
0
  if (RetVT.SimpleTy != MVT::v8i16)
2034
0
    return 0;
2035
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2036
0
    return fastEmitInst_rr(Mips::SLL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2037
0
  }
2038
0
  return 0;
2039
0
}
2040
2041
0
unsigned fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2042
0
  if (RetVT.SimpleTy != MVT::v4i32)
2043
0
    return 0;
2044
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2045
0
    return fastEmitInst_rr(Mips::SLL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2046
0
  }
2047
0
  return 0;
2048
0
}
2049
2050
0
unsigned fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2051
0
  if (RetVT.SimpleTy != MVT::v2i64)
2052
0
    return 0;
2053
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2054
0
    return fastEmitInst_rr(Mips::SLL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2055
0
  }
2056
0
  return 0;
2057
0
}
2058
2059
unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2060
  switch (VT.SimpleTy) {
2061
  case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2062
  case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2063
  case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2064
  case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2065
  case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2066
  default: return 0;
2067
  }
2068
}
2069
2070
// FastEmit functions for ISD::SMAX.
2071
2072
0
unsigned fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2073
0
  if (RetVT.SimpleTy != MVT::v16i8)
2074
0
    return 0;
2075
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2076
0
    return fastEmitInst_rr(Mips::MAX_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2077
0
  }
2078
0
  return 0;
2079
0
}
2080
2081
0
unsigned fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2082
0
  if (RetVT.SimpleTy != MVT::v8i16)
2083
0
    return 0;
2084
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2085
0
    return fastEmitInst_rr(Mips::MAX_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2086
0
  }
2087
0
  return 0;
2088
0
}
2089
2090
0
unsigned fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2091
0
  if (RetVT.SimpleTy != MVT::v4i32)
2092
0
    return 0;
2093
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2094
0
    return fastEmitInst_rr(Mips::MAX_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2095
0
  }
2096
0
  return 0;
2097
0
}
2098
2099
0
unsigned fastEmit_ISD_SMAX_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2100
0
  if (RetVT.SimpleTy != MVT::v2i64)
2101
0
    return 0;
2102
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2103
0
    return fastEmitInst_rr(Mips::MAX_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2104
0
  }
2105
0
  return 0;
2106
0
}
2107
2108
unsigned fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2109
  switch (VT.SimpleTy) {
2110
  case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2111
  case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2112
  case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2113
  case MVT::v2i64: return fastEmit_ISD_SMAX_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2114
  default: return 0;
2115
  }
2116
}
2117
2118
// FastEmit functions for ISD::SMIN.
2119
2120
0
unsigned fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2121
0
  if (RetVT.SimpleTy != MVT::v16i8)
2122
0
    return 0;
2123
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2124
0
    return fastEmitInst_rr(Mips::MIN_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2125
0
  }
2126
0
  return 0;
2127
0
}
2128
2129
0
unsigned fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2130
0
  if (RetVT.SimpleTy != MVT::v8i16)
2131
0
    return 0;
2132
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2133
0
    return fastEmitInst_rr(Mips::MIN_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2134
0
  }
2135
0
  return 0;
2136
0
}
2137
2138
0
unsigned fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2139
0
  if (RetVT.SimpleTy != MVT::v4i32)
2140
0
    return 0;
2141
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2142
0
    return fastEmitInst_rr(Mips::MIN_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2143
0
  }
2144
0
  return 0;
2145
0
}
2146
2147
0
unsigned fastEmit_ISD_SMIN_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2148
0
  if (RetVT.SimpleTy != MVT::v2i64)
2149
0
    return 0;
2150
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2151
0
    return fastEmitInst_rr(Mips::MIN_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2152
0
  }
2153
0
  return 0;
2154
0
}
2155
2156
unsigned fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2157
  switch (VT.SimpleTy) {
2158
  case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2159
  case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2160
  case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2161
  case MVT::v2i64: return fastEmit_ISD_SMIN_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2162
  default: return 0;
2163
  }
2164
}
2165
2166
// FastEmit functions for ISD::SRA.
2167
2168
0
unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2169
0
  if (RetVT.SimpleTy != MVT::i32)
2170
0
    return 0;
2171
0
  if ((Subtarget->inMicroMipsMode())) {
2172
0
    return fastEmitInst_rr(Mips::SRAV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2173
0
  }
2174
0
  if ((Subtarget->inMips16Mode())) {
2175
0
    return fastEmitInst_rr(Mips::SravRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2176
0
  }
2177
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2178
0
    return fastEmitInst_rr(Mips::SRAV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2179
0
  }
2180
0
  return 0;
2181
0
}
2182
2183
0
unsigned fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2184
0
  if (RetVT.SimpleTy != MVT::v16i8)
2185
0
    return 0;
2186
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2187
0
    return fastEmitInst_rr(Mips::SRA_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2188
0
  }
2189
0
  return 0;
2190
0
}
2191
2192
0
unsigned fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2193
0
  if (RetVT.SimpleTy != MVT::v8i16)
2194
0
    return 0;
2195
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2196
0
    return fastEmitInst_rr(Mips::SRA_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2197
0
  }
2198
0
  return 0;
2199
0
}
2200
2201
0
unsigned fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2202
0
  if (RetVT.SimpleTy != MVT::v4i32)
2203
0
    return 0;
2204
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2205
0
    return fastEmitInst_rr(Mips::SRA_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2206
0
  }
2207
0
  return 0;
2208
0
}
2209
2210
0
unsigned fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2211
0
  if (RetVT.SimpleTy != MVT::v2i64)
2212
0
    return 0;
2213
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2214
0
    return fastEmitInst_rr(Mips::SRA_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2215
0
  }
2216
0
  return 0;
2217
0
}
2218
2219
unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2220
  switch (VT.SimpleTy) {
2221
  case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2222
  case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2223
  case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2224
  case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2225
  case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2226
  default: return 0;
2227
  }
2228
}
2229
2230
// FastEmit functions for ISD::SREM.
2231
2232
4
unsigned fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2233
4
  if (RetVT.SimpleTy != MVT::i32)
2234
0
    return 0;
2235
4
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->inMicroMipsMode())0
) {
2236
0
    return fastEmitInst_rr(Mips::MOD_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2237
0
  }
2238
4
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->hasStandardEncoding())0
&&
(!Subtarget->inMicroMipsMode())0
) {
2239
0
    return fastEmitInst_rr(Mips::MOD, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2240
0
  }
2241
4
  return 0;
2242
4
}
2243
2244
0
unsigned fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2245
0
  if (RetVT.SimpleTy != MVT::i64)
2246
0
    return 0;
2247
0
  if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2248
0
    return fastEmitInst_rr(Mips::DMOD, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2249
0
  }
2250
0
  return 0;
2251
0
}
2252
2253
0
unsigned fastEmit_ISD_SREM_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2254
0
  if (RetVT.SimpleTy != MVT::v16i8)
2255
0
    return 0;
2256
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2257
0
    return fastEmitInst_rr(Mips::MOD_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2258
0
  }
2259
0
  return 0;
2260
0
}
2261
2262
0
unsigned fastEmit_ISD_SREM_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2263
0
  if (RetVT.SimpleTy != MVT::v8i16)
2264
0
    return 0;
2265
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2266
0
    return fastEmitInst_rr(Mips::MOD_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2267
0
  }
2268
0
  return 0;
2269
0
}
2270
2271
0
unsigned fastEmit_ISD_SREM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2272
0
  if (RetVT.SimpleTy != MVT::v4i32)
2273
0
    return 0;
2274
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2275
0
    return fastEmitInst_rr(Mips::MOD_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2276
0
  }
2277
0
  return 0;
2278
0
}
2279
2280
0
unsigned fastEmit_ISD_SREM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2281
0
  if (RetVT.SimpleTy != MVT::v2i64)
2282
0
    return 0;
2283
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2284
0
    return fastEmitInst_rr(Mips::MOD_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2285
0
  }
2286
0
  return 0;
2287
0
}
2288
2289
4
unsigned fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2290
4
  switch (VT.SimpleTy) {
2291
4
  case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2292
4
  
case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2293
4
  
case MVT::v16i8: return fastEmit_ISD_SREM_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2294
4
  
case MVT::v8i16: return fastEmit_ISD_SREM_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2295
4
  
case MVT::v4i32: return fastEmit_ISD_SREM_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2296
4
  
case MVT::v2i64: return fastEmit_ISD_SREM_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2297
4
  
default: return 00
;
2298
4
  }
2299
4
}
2300
2301
// FastEmit functions for ISD::SRL.
2302
2303
0
unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2304
0
  if (RetVT.SimpleTy != MVT::i32)
2305
0
    return 0;
2306
0
  if ((Subtarget->inMicroMipsMode())) {
2307
0
    return fastEmitInst_rr(Mips::SRLV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2308
0
  }
2309
0
  if ((Subtarget->inMips16Mode())) {
2310
0
    return fastEmitInst_rr(Mips::SrlvRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2311
0
  }
2312
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2313
0
    return fastEmitInst_rr(Mips::SRLV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2314
0
  }
2315
0
  return 0;
2316
0
}
2317
2318
0
unsigned fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2319
0
  if (RetVT.SimpleTy != MVT::v16i8)
2320
0
    return 0;
2321
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2322
0
    return fastEmitInst_rr(Mips::SRL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2323
0
  }
2324
0
  return 0;
2325
0
}
2326
2327
0
unsigned fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2328
0
  if (RetVT.SimpleTy != MVT::v8i16)
2329
0
    return 0;
2330
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2331
0
    return fastEmitInst_rr(Mips::SRL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2332
0
  }
2333
0
  return 0;
2334
0
}
2335
2336
0
unsigned fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2337
0
  if (RetVT.SimpleTy != MVT::v4i32)
2338
0
    return 0;
2339
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2340
0
    return fastEmitInst_rr(Mips::SRL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2341
0
  }
2342
0
  return 0;
2343
0
}
2344
2345
0
unsigned fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2346
0
  if (RetVT.SimpleTy != MVT::v2i64)
2347
0
    return 0;
2348
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2349
0
    return fastEmitInst_rr(Mips::SRL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2350
0
  }
2351
0
  return 0;
2352
0
}
2353
2354
unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2355
  switch (VT.SimpleTy) {
2356
  case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2357
  case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2358
  case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2359
  case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2360
  case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2361
  default: return 0;
2362
  }
2363
}
2364
2365
// FastEmit functions for ISD::SUB.
2366
2367
0
unsigned fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2368
0
  if (RetVT.SimpleTy != MVT::i32)
2369
0
    return 0;
2370
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2371
0
    return fastEmitInst_rr(Mips::SUBU16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2372
0
  }
2373
0
  if ((Subtarget->inMips16Mode())) {
2374
0
    return fastEmitInst_rr(Mips::SubuRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2375
0
  }
2376
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
2377
0
    return fastEmitInst_rr(Mips::SUBu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2378
0
  }
2379
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2380
0
    return fastEmitInst_rr(Mips::SUBu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2381
0
  }
2382
0
  return 0;
2383
0
}
2384
2385
0
unsigned fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2386
0
  if (RetVT.SimpleTy != MVT::i64)
2387
0
    return 0;
2388
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2389
0
    return fastEmitInst_rr(Mips::DSUBu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2390
0
  }
2391
0
  return 0;
2392
0
}
2393
2394
0
unsigned fastEmit_ISD_SUB_MVT_v4i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2395
0
  if (RetVT.SimpleTy != MVT::v4i8)
2396
0
    return 0;
2397
0
  if ((Subtarget->hasDSP())) {
2398
0
    return fastEmitInst_rr(Mips::SUBU_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2399
0
  }
2400
0
  return 0;
2401
0
}
2402
2403
0
unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2404
0
  if (RetVT.SimpleTy != MVT::v16i8)
2405
0
    return 0;
2406
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2407
0
    return fastEmitInst_rr(Mips::SUBV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2408
0
  }
2409
0
  return 0;
2410
0
}
2411
2412
0
unsigned fastEmit_ISD_SUB_MVT_v2i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2413
0
  if (RetVT.SimpleTy != MVT::v2i16)
2414
0
    return 0;
2415
0
  if ((Subtarget->hasDSP())) {
2416
0
    return fastEmitInst_rr(Mips::SUBQ_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2417
0
  }
2418
0
  return 0;
2419
0
}
2420
2421
0
unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2422
0
  if (RetVT.SimpleTy != MVT::v8i16)
2423
0
    return 0;
2424
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2425
0
    return fastEmitInst_rr(Mips::SUBV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2426
0
  }
2427
0
  return 0;
2428
0
}
2429
2430
0
unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2431
0
  if (RetVT.SimpleTy != MVT::v4i32)
2432
0
    return 0;
2433
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2434
0
    return fastEmitInst_rr(Mips::SUBV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2435
0
  }
2436
0
  return 0;
2437
0
}
2438
2439
0
unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2440
0
  if (RetVT.SimpleTy != MVT::v2i64)
2441
0
    return 0;
2442
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2443
0
    return fastEmitInst_rr(Mips::SUBV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2444
0
  }
2445
0
  return 0;
2446
0
}
2447
2448
unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2449
  switch (VT.SimpleTy) {
2450
  case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2451
  case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2452
  case MVT::v4i8: return fastEmit_ISD_SUB_MVT_v4i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2453
  case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2454
  case MVT::v2i16: return fastEmit_ISD_SUB_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2455
  case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2456
  case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2457
  case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2458
  default: return 0;
2459
  }
2460
}
2461
2462
// FastEmit functions for ISD::SUBC.
2463
2464
0
unsigned fastEmit_ISD_SUBC_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2465
0
  if (RetVT.SimpleTy != MVT::i32)
2466
0
    return 0;
2467
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2468
0
    return fastEmitInst_rr(Mips::SUBU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2469
0
  }
2470
0
  if ((Subtarget->inMicroMipsMode())) {
2471
0
    return fastEmitInst_rr(Mips::SUBu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2472
0
  }
2473
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2474
0
    return fastEmitInst_rr(Mips::SUBu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2475
0
  }
2476
0
  return 0;
2477
0
}
2478
2479
0
unsigned fastEmit_ISD_SUBC_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2480
0
  if (RetVT.SimpleTy != MVT::i64)
2481
0
    return 0;
2482
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())) {
2483
0
    return fastEmitInst_rr(Mips::DSUBu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2484
0
  }
2485
0
  return 0;
2486
0
}
2487
2488
unsigned fastEmit_ISD_SUBC_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2489
  switch (VT.SimpleTy) {
2490
  case MVT::i32: return fastEmit_ISD_SUBC_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2491
  case MVT::i64: return fastEmit_ISD_SUBC_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2492
  default: return 0;
2493
  }
2494
}
2495
2496
// FastEmit functions for ISD::UDIV.
2497
2498
4
unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2499
4
  if (RetVT.SimpleTy != MVT::i32)
2500
0
    return 0;
2501
4
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->inMicroMipsMode())0
) {
2502
0
    return fastEmitInst_rr(Mips::DIVU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2503
0
  }
2504
4
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->hasStandardEncoding())0
&&
(!Subtarget->inMicroMipsMode())0
) {
2505
0
    return fastEmitInst_rr(Mips::DIVU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2506
0
  }
2507
4
  return 0;
2508
4
}
2509
2510
0
unsigned fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2511
0
  if (RetVT.SimpleTy != MVT::i64)
2512
0
    return 0;
2513
0
  if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2514
0
    return fastEmitInst_rr(Mips::DDIVU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2515
0
  }
2516
0
  return 0;
2517
0
}
2518
2519
0
unsigned fastEmit_ISD_UDIV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2520
0
  if (RetVT.SimpleTy != MVT::v16i8)
2521
0
    return 0;
2522
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2523
0
    return fastEmitInst_rr(Mips::DIV_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2524
0
  }
2525
0
  return 0;
2526
0
}
2527
2528
0
unsigned fastEmit_ISD_UDIV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2529
0
  if (RetVT.SimpleTy != MVT::v8i16)
2530
0
    return 0;
2531
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2532
0
    return fastEmitInst_rr(Mips::DIV_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2533
0
  }
2534
0
  return 0;
2535
0
}
2536
2537
0
unsigned fastEmit_ISD_UDIV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2538
0
  if (RetVT.SimpleTy != MVT::v4i32)
2539
0
    return 0;
2540
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2541
0
    return fastEmitInst_rr(Mips::DIV_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2542
0
  }
2543
0
  return 0;
2544
0
}
2545
2546
0
unsigned fastEmit_ISD_UDIV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2547
0
  if (RetVT.SimpleTy != MVT::v2i64)
2548
0
    return 0;
2549
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2550
0
    return fastEmitInst_rr(Mips::DIV_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2551
0
  }
2552
0
  return 0;
2553
0
}
2554
2555
4
unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2556
4
  switch (VT.SimpleTy) {
2557
4
  case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2558
4
  
case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2559
4
  
case MVT::v16i8: return fastEmit_ISD_UDIV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2560
4
  
case MVT::v8i16: return fastEmit_ISD_UDIV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2561
4
  
case MVT::v4i32: return fastEmit_ISD_UDIV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2562
4
  
case MVT::v2i64: return fastEmit_ISD_UDIV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2563
4
  
default: return 00
;
2564
4
  }
2565
4
}
2566
2567
// FastEmit functions for ISD::UMAX.
2568
2569
0
unsigned fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2570
0
  if (RetVT.SimpleTy != MVT::v16i8)
2571
0
    return 0;
2572
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2573
0
    return fastEmitInst_rr(Mips::MAX_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2574
0
  }
2575
0
  return 0;
2576
0
}
2577
2578
0
unsigned fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2579
0
  if (RetVT.SimpleTy != MVT::v8i16)
2580
0
    return 0;
2581
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2582
0
    return fastEmitInst_rr(Mips::MAX_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2583
0
  }
2584
0
  return 0;
2585
0
}
2586
2587
0
unsigned fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2588
0
  if (RetVT.SimpleTy != MVT::v4i32)
2589
0
    return 0;
2590
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2591
0
    return fastEmitInst_rr(Mips::MAX_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2592
0
  }
2593
0
  return 0;
2594
0
}
2595
2596
0
unsigned fastEmit_ISD_UMAX_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2597
0
  if (RetVT.SimpleTy != MVT::v2i64)
2598
0
    return 0;
2599
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2600
0
    return fastEmitInst_rr(Mips::MAX_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2601
0
  }
2602
0
  return 0;
2603
0
}
2604
2605
unsigned fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2606
  switch (VT.SimpleTy) {
2607
  case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2608
  case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2609
  case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2610
  case MVT::v2i64: return fastEmit_ISD_UMAX_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2611
  default: return 0;
2612
  }
2613
}
2614
2615
// FastEmit functions for ISD::UMIN.
2616
2617
0
unsigned fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2618
0
  if (RetVT.SimpleTy != MVT::v16i8)
2619
0
    return 0;
2620
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2621
0
    return fastEmitInst_rr(Mips::MIN_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2622
0
  }
2623
0
  return 0;
2624
0
}
2625
2626
0
unsigned fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2627
0
  if (RetVT.SimpleTy != MVT::v8i16)
2628
0
    return 0;
2629
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2630
0
    return fastEmitInst_rr(Mips::MIN_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2631
0
  }
2632
0
  return 0;
2633
0
}
2634
2635
0
unsigned fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2636
0
  if (RetVT.SimpleTy != MVT::v4i32)
2637
0
    return 0;
2638
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2639
0
    return fastEmitInst_rr(Mips::MIN_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2640
0
  }
2641
0
  return 0;
2642
0
}
2643
2644
0
unsigned fastEmit_ISD_UMIN_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2645
0
  if (RetVT.SimpleTy != MVT::v2i64)
2646
0
    return 0;
2647
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2648
0
    return fastEmitInst_rr(Mips::MIN_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2649
0
  }
2650
0
  return 0;
2651
0
}
2652
2653
unsigned fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2654
  switch (VT.SimpleTy) {
2655
  case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2656
  case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2657
  case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2658
  case MVT::v2i64: return fastEmit_ISD_UMIN_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2659
  default: return 0;
2660
  }
2661
}
2662
2663
// FastEmit functions for ISD::UREM.
2664
2665
4
unsigned fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2666
4
  if (RetVT.SimpleTy != MVT::i32)
2667
0
    return 0;
2668
4
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->inMicroMipsMode())0
) {
2669
0
    return fastEmitInst_rr(Mips::MODU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2670
0
  }
2671
4
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->hasStandardEncoding())0
&&
(!Subtarget->inMicroMipsMode())0
) {
2672
0
    return fastEmitInst_rr(Mips::MODU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2673
0
  }
2674
4
  return 0;
2675
4
}
2676
2677
0
unsigned fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2678
0
  if (RetVT.SimpleTy != MVT::i64)
2679
0
    return 0;
2680
0
  if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2681
0
    return fastEmitInst_rr(Mips::DMODU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2682
0
  }
2683
0
  return 0;
2684
0
}
2685
2686
0
unsigned fastEmit_ISD_UREM_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2687
0
  if (RetVT.SimpleTy != MVT::v16i8)
2688
0
    return 0;
2689
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2690
0
    return fastEmitInst_rr(Mips::MOD_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2691
0
  }
2692
0
  return 0;
2693
0
}
2694
2695
0
unsigned fastEmit_ISD_UREM_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2696
0
  if (RetVT.SimpleTy != MVT::v8i16)
2697
0
    return 0;
2698
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2699
0
    return fastEmitInst_rr(Mips::MOD_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2700
0
  }
2701
0
  return 0;
2702
0
}
2703
2704
0
unsigned fastEmit_ISD_UREM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2705
0
  if (RetVT.SimpleTy != MVT::v4i32)
2706
0
    return 0;
2707
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2708
0
    return fastEmitInst_rr(Mips::MOD_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2709
0
  }
2710
0
  return 0;
2711
0
}
2712
2713
0
unsigned fastEmit_ISD_UREM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2714
0
  if (RetVT.SimpleTy != MVT::v2i64)
2715
0
    return 0;
2716
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2717
0
    return fastEmitInst_rr(Mips::MOD_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2718
0
  }
2719
0
  return 0;
2720
0
}
2721
2722
4
unsigned fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2723
4
  switch (VT.SimpleTy) {
2724
4
  case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2725
4
  
case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2726
4
  
case MVT::v16i8: return fastEmit_ISD_UREM_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2727
4
  
case MVT::v8i16: return fastEmit_ISD_UREM_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2728
4
  
case MVT::v4i32: return fastEmit_ISD_UREM_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2729
4
  
case MVT::v2i64: return fastEmit_ISD_UREM_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2730
4
  
default: return 00
;
2731
4
  }
2732
4
}
2733
2734
// FastEmit functions for ISD::XOR.
2735
2736
5
unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2737
5
  if (RetVT.SimpleTy != MVT::i32)
2738
0
    return 0;
2739
5
  if ((Subtarget->inMips16Mode())) {
2740
0
    return fastEmitInst_rr(Mips::XorRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2741
0
  }
2742
5
  if ((Subtarget->hasMips32r6()) && 
(Subtarget->inMicroMipsMode())0
) {
2743
0
    return fastEmitInst_rr(Mips::XOR_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2744
0
  }
2745
5
  if ((Subtarget->inMicroMipsMode()) && 
(!Subtarget->hasMips32r6())0
) {
2746
0
    return fastEmitInst_rr(Mips::XOR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2747
0
  }
2748
5
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2749
5
    return fastEmitInst_rr(Mips::XOR, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2750
5
  }
2751
0
  return 0;
2752
0
}
2753
2754
0
unsigned fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2755
0
  if (RetVT.SimpleTy != MVT::i64)
2756
0
    return 0;
2757
0
  if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
2758
0
    return fastEmitInst_rr(Mips::XOR64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2759
0
  }
2760
0
  return 0;
2761
0
}
2762
2763
0
unsigned fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2764
0
  if (RetVT.SimpleTy != MVT::v16i8)
2765
0
    return 0;
2766
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2767
0
    return fastEmitInst_rr(Mips::XOR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2768
0
  }
2769
0
  return 0;
2770
0
}
2771
2772
0
unsigned fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2773
0
  if (RetVT.SimpleTy != MVT::v8i16)
2774
0
    return 0;
2775
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2776
0
    return fastEmitInst_rr(Mips::XOR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2777
0
  }
2778
0
  return 0;
2779
0
}
2780
2781
0
unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2782
0
  if (RetVT.SimpleTy != MVT::v4i32)
2783
0
    return 0;
2784
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2785
0
    return fastEmitInst_rr(Mips::XOR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2786
0
  }
2787
0
  return 0;
2788
0
}
2789
2790
0
unsigned fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2791
0
  if (RetVT.SimpleTy != MVT::v2i64)
2792
0
    return 0;
2793
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2794
0
    return fastEmitInst_rr(Mips::XOR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2795
0
  }
2796
0
  return 0;
2797
0
}
2798
2799
5
unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2800
5
  switch (VT.SimpleTy) {
2801
5
  case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2802
5
  
case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2803
5
  
case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2804
5
  
case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2805
5
  
case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2806
5
  
case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2807
5
  
default: return 00
;
2808
5
  }
2809
5
}
2810
2811
// FastEmit functions for MipsISD::BuildPairF64.
2812
2813
0
unsigned fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2814
0
  if (RetVT.SimpleTy != MVT::f64)
2815
0
    return 0;
2816
0
  if ((Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())) {
2817
0
    return fastEmitInst_rr(Mips::BuildPairF64_64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2818
0
  }
2819
0
  if ((!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) {
2820
0
    return fastEmitInst_rr(Mips::BuildPairF64, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2821
0
  }
2822
0
  return 0;
2823
0
}
2824
2825
unsigned fastEmit_MipsISD_BuildPairF64_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2826
  switch (VT.SimpleTy) {
2827
  case MVT::i32: return fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2828
  default: return 0;
2829
  }
2830
}
2831
2832
// FastEmit functions for MipsISD::DivRem.
2833
2834
0
unsigned fastEmit_MipsISD_DivRem_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2835
0
  if (RetVT.SimpleTy != MVT::Untyped)
2836
0
    return 0;
2837
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
2838
0
    return fastEmitInst_rr(Mips::SDIV_MM_Pseudo, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2839
0
  }
2840
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
2841
0
    return fastEmitInst_rr(Mips::PseudoSDIV, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2842
0
  }
2843
0
  return 0;
2844
0
}
2845
2846
0
unsigned fastEmit_MipsISD_DivRem_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2847
0
  if (RetVT.SimpleTy != MVT::Untyped)
2848
0
    return 0;
2849
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
2850
0
    return fastEmitInst_rr(Mips::PseudoDSDIV, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2851
0
  }
2852
0
  return 0;
2853
0
}
2854
2855
unsigned fastEmit_MipsISD_DivRem_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2856
  switch (VT.SimpleTy) {
2857
  case MVT::i32: return fastEmit_MipsISD_DivRem_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2858
  case MVT::i64: return fastEmit_MipsISD_DivRem_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2859
  default: return 0;
2860
  }
2861
}
2862
2863
// FastEmit functions for MipsISD::DivRem16.
2864
2865
0
unsigned fastEmit_MipsISD_DivRem16_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2866
0
  if (RetVT.SimpleTy != MVT::isVoid)
2867
0
    return 0;
2868
0
  if ((Subtarget->inMips16Mode())) {
2869
0
    return fastEmitInst_rr(Mips::DivRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2870
0
  }
2871
0
  return 0;
2872
0
}
2873
2874
unsigned fastEmit_MipsISD_DivRem16_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2875
  switch (VT.SimpleTy) {
2876
  case MVT::i32: return fastEmit_MipsISD_DivRem16_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2877
  default: return 0;
2878
  }
2879
}
2880
2881
// FastEmit functions for MipsISD::DivRemU.
2882
2883
0
unsigned fastEmit_MipsISD_DivRemU_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2884
0
  if (RetVT.SimpleTy != MVT::Untyped)
2885
0
    return 0;
2886
0
  if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
2887
0
    return fastEmitInst_rr(Mips::UDIV_MM_Pseudo, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2888
0
  }
2889
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
2890
0
    return fastEmitInst_rr(Mips::PseudoUDIV, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2891
0
  }
2892
0
  return 0;
2893
0
}
2894
2895
0
unsigned fastEmit_MipsISD_DivRemU_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2896
0
  if (RetVT.SimpleTy != MVT::Untyped)
2897
0
    return 0;
2898
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
2899
0
    return fastEmitInst_rr(Mips::PseudoDUDIV, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2900
0
  }
2901
0
  return 0;
2902
0
}
2903
2904
unsigned fastEmit_MipsISD_DivRemU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2905
  switch (VT.SimpleTy) {
2906
  case MVT::i32: return fastEmit_MipsISD_DivRemU_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2907
  case MVT::i64: return fastEmit_MipsISD_DivRemU_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2908
  default: return 0;
2909
  }
2910
}
2911
2912
// FastEmit functions for MipsISD::DivRemU16.
2913
2914
0
unsigned fastEmit_MipsISD_DivRemU16_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2915
0
  if (RetVT.SimpleTy != MVT::isVoid)
2916
0
    return 0;
2917
0
  if ((Subtarget->inMips16Mode())) {
2918
0
    return fastEmitInst_rr(Mips::DivuRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2919
0
  }
2920
0
  return 0;
2921
0
}
2922
2923
unsigned fastEmit_MipsISD_DivRemU16_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2924
  switch (VT.SimpleTy) {
2925
  case MVT::i32: return fastEmit_MipsISD_DivRemU16_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2926
  default: return 0;
2927
  }
2928
}
2929
2930
// FastEmit functions for MipsISD::EH_RETURN.
2931
2932
0
unsigned fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2933
0
  if (RetVT.SimpleTy != MVT::isVoid)
2934
0
    return 0;
2935
0
  return fastEmitInst_rr(Mips::MIPSeh_return32, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2936
0
}
2937
2938
0
unsigned fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2939
0
  if (RetVT.SimpleTy != MVT::isVoid)
2940
0
    return 0;
2941
0
  return fastEmitInst_rr(Mips::MIPSeh_return64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2942
0
}
2943
2944
unsigned fastEmit_MipsISD_EH_RETURN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2945
  switch (VT.SimpleTy) {
2946
  case MVT::i32: return fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2947
  case MVT::i64: return fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2948
  default: return 0;
2949
  }
2950
}
2951
2952
// FastEmit functions for MipsISD::ILVEV.
2953
2954
0
unsigned fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2955
0
  if (RetVT.SimpleTy != MVT::v16i8)
2956
0
    return 0;
2957
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2958
0
    return fastEmitInst_rr(Mips::ILVEV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2959
0
  }
2960
0
  return 0;
2961
0
}
2962
2963
0
unsigned fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2964
0
  if (RetVT.SimpleTy != MVT::v8i16)
2965
0
    return 0;
2966
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2967
0
    return fastEmitInst_rr(Mips::ILVEV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2968
0
  }
2969
0
  return 0;
2970
0
}
2971
2972
0
unsigned fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2973
0
  if (RetVT.SimpleTy != MVT::v4i32)
2974
0
    return 0;
2975
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2976
0
    return fastEmitInst_rr(Mips::ILVEV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2977
0
  }
2978
0
  return 0;
2979
0
}
2980
2981
0
unsigned fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2982
0
  if (RetVT.SimpleTy != MVT::v2i64)
2983
0
    return 0;
2984
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2985
0
    return fastEmitInst_rr(Mips::ILVEV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2986
0
  }
2987
0
  return 0;
2988
0
}
2989
2990
unsigned fastEmit_MipsISD_ILVEV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2991
  switch (VT.SimpleTy) {
2992
  case MVT::v16i8: return fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2993
  case MVT::v8i16: return fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2994
  case MVT::v4i32: return fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2995
  case MVT::v2i64: return fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2996
  default: return 0;
2997
  }
2998
}
2999
3000
// FastEmit functions for MipsISD::ILVL.
3001
3002
0
unsigned fastEmit_MipsISD_ILVL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3003
0
  if (RetVT.SimpleTy != MVT::v16i8)
3004
0
    return 0;
3005
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3006
0
    return fastEmitInst_rr(Mips::ILVL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3007
0
  }
3008
0
  return 0;
3009
0
}
3010
3011
0
unsigned fastEmit_MipsISD_ILVL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3012
0
  if (RetVT.SimpleTy != MVT::v8i16)
3013
0
    return 0;
3014
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3015
0
    return fastEmitInst_rr(Mips::ILVL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3016
0
  }
3017
0
  return 0;
3018
0
}
3019
3020
0
unsigned fastEmit_MipsISD_ILVL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3021
0
  if (RetVT.SimpleTy != MVT::v4i32)
3022
0
    return 0;
3023
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3024
0
    return fastEmitInst_rr(Mips::ILVL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3025
0
  }
3026
0
  return 0;
3027
0
}
3028
3029
0
unsigned fastEmit_MipsISD_ILVL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3030
0
  if (RetVT.SimpleTy != MVT::v2i64)
3031
0
    return 0;
3032
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3033
0
    return fastEmitInst_rr(Mips::ILVL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3034
0
  }
3035
0
  return 0;
3036
0
}
3037
3038
unsigned fastEmit_MipsISD_ILVL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3039
  switch (VT.SimpleTy) {
3040
  case MVT::v16i8: return fastEmit_MipsISD_ILVL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3041
  case MVT::v8i16: return fastEmit_MipsISD_ILVL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3042
  case MVT::v4i32: return fastEmit_MipsISD_ILVL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3043
  case MVT::v2i64: return fastEmit_MipsISD_ILVL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3044
  default: return 0;
3045
  }
3046
}
3047
3048
// FastEmit functions for MipsISD::ILVOD.
3049
3050
0
unsigned fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3051
0
  if (RetVT.SimpleTy != MVT::v16i8)
3052
0
    return 0;
3053
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3054
0
    return fastEmitInst_rr(Mips::ILVOD_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3055
0
  }
3056
0
  return 0;
3057
0
}
3058
3059
0
unsigned fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3060
0
  if (RetVT.SimpleTy != MVT::v8i16)
3061
0
    return 0;
3062
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3063
0
    return fastEmitInst_rr(Mips::ILVOD_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3064
0
  }
3065
0
  return 0;
3066
0
}
3067
3068
0
unsigned fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3069
0
  if (RetVT.SimpleTy != MVT::v4i32)
3070
0
    return 0;
3071
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3072
0
    return fastEmitInst_rr(Mips::ILVOD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3073
0
  }
3074
0
  return 0;
3075
0
}
3076
3077
0
unsigned fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3078
0
  if (RetVT.SimpleTy != MVT::v2i64)
3079
0
    return 0;
3080
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3081
0
    return fastEmitInst_rr(Mips::ILVOD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3082
0
  }
3083
0
  return 0;
3084
0
}
3085
3086
unsigned fastEmit_MipsISD_ILVOD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3087
  switch (VT.SimpleTy) {
3088
  case MVT::v16i8: return fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3089
  case MVT::v8i16: return fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3090
  case MVT::v4i32: return fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3091
  case MVT::v2i64: return fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3092
  default: return 0;
3093
  }
3094
}
3095
3096
// FastEmit functions for MipsISD::ILVR.
3097
3098
0
unsigned fastEmit_MipsISD_ILVR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3099
0
  if (RetVT.SimpleTy != MVT::v16i8)
3100
0
    return 0;
3101
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3102
0
    return fastEmitInst_rr(Mips::ILVR_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3103
0
  }
3104
0
  return 0;
3105
0
}
3106
3107
0
unsigned fastEmit_MipsISD_ILVR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3108
0
  if (RetVT.SimpleTy != MVT::v8i16)
3109
0
    return 0;
3110
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3111
0
    return fastEmitInst_rr(Mips::ILVR_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3112
0
  }
3113
0
  return 0;
3114
0
}
3115
3116
0
unsigned fastEmit_MipsISD_ILVR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3117
0
  if (RetVT.SimpleTy != MVT::v4i32)
3118
0
    return 0;
3119
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3120
0
    return fastEmitInst_rr(Mips::ILVR_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3121
0
  }
3122
0
  return 0;
3123
0
}
3124
3125
0
unsigned fastEmit_MipsISD_ILVR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3126
0
  if (RetVT.SimpleTy != MVT::v2i64)
3127
0
    return 0;
3128
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3129
0
    return fastEmitInst_rr(Mips::ILVR_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3130
0
  }
3131
0
  return 0;
3132
0
}
3133
3134
unsigned fastEmit_MipsISD_ILVR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3135
  switch (VT.SimpleTy) {
3136
  case MVT::v16i8: return fastEmit_MipsISD_ILVR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3137
  case MVT::v8i16: return fastEmit_MipsISD_ILVR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3138
  case MVT::v4i32: return fastEmit_MipsISD_ILVR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3139
  case MVT::v2i64: return fastEmit_MipsISD_ILVR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3140
  default: return 0;
3141
  }
3142
}
3143
3144
// FastEmit functions for MipsISD::MTLOHI.
3145
3146
0
unsigned fastEmit_MipsISD_MTLOHI_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3147
0
  if (RetVT.SimpleTy != MVT::Untyped)
3148
0
    return 0;
3149
0
  if ((!Subtarget->inMips16Mode())) {
3150
0
    return fastEmitInst_rr(Mips::PseudoMTLOHI_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3151
0
  }
3152
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3153
0
    return fastEmitInst_rr(Mips::PseudoMTLOHI, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3154
0
  }
3155
0
  return 0;
3156
0
}
3157
3158
0
unsigned fastEmit_MipsISD_MTLOHI_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3159
0
  if (RetVT.SimpleTy != MVT::Untyped)
3160
0
    return 0;
3161
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3162
0
    return fastEmitInst_rr(Mips::PseudoMTLOHI64, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3163
0
  }
3164
0
  return 0;
3165
0
}
3166
3167
unsigned fastEmit_MipsISD_MTLOHI_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3168
  switch (VT.SimpleTy) {
3169
  case MVT::i32: return fastEmit_MipsISD_MTLOHI_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3170
  case MVT::i64: return fastEmit_MipsISD_MTLOHI_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3171
  default: return 0;
3172
  }
3173
}
3174
3175
// FastEmit functions for MipsISD::Mult.
3176
3177
0
unsigned fastEmit_MipsISD_Mult_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3178
0
  if (RetVT.SimpleTy != MVT::Untyped)
3179
0
    return 0;
3180
0
  if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
3181
0
    return fastEmitInst_rr(Mips::MULT_DSP_MM, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3182
0
  }
3183
0
  if ((Subtarget->hasDSP())) {
3184
0
    return fastEmitInst_rr(Mips::MULT_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3185
0
  }
3186
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3187
0
    return fastEmitInst_rr(Mips::PseudoMULT, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3188
0
  }
3189
0
  return 0;
3190
0
}
3191
3192
0
unsigned fastEmit_MipsISD_Mult_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3193
0
  if (RetVT.SimpleTy != MVT::Untyped)
3194
0
    return 0;
3195
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3196
0
    return fastEmitInst_rr(Mips::PseudoDMULT, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3197
0
  }
3198
0
  return 0;
3199
0
}
3200
3201
unsigned fastEmit_MipsISD_Mult_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3202
  switch (VT.SimpleTy) {
3203
  case MVT::i32: return fastEmit_MipsISD_Mult_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3204
  case MVT::i64: return fastEmit_MipsISD_Mult_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3205
  default: return 0;
3206
  }
3207
}
3208
3209
// FastEmit functions for MipsISD::Multu.
3210
3211
0
unsigned fastEmit_MipsISD_Multu_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3212
0
  if (RetVT.SimpleTy != MVT::Untyped)
3213
0
    return 0;
3214
0
  if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
3215
0
    return fastEmitInst_rr(Mips::MULTU_DSP_MM, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3216
0
  }
3217
0
  if ((Subtarget->hasDSP())) {
3218
0
    return fastEmitInst_rr(Mips::MULTU_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3219
0
  }
3220
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3221
0
    return fastEmitInst_rr(Mips::PseudoMULTu, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3222
0
  }
3223
0
  return 0;
3224
0
}
3225
3226
0
unsigned fastEmit_MipsISD_Multu_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3227
0
  if (RetVT.SimpleTy != MVT::Untyped)
3228
0
    return 0;
3229
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3230
0
    return fastEmitInst_rr(Mips::PseudoDMULTu, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3231
0
  }
3232
0
  return 0;
3233
0
}
3234
3235
unsigned fastEmit_MipsISD_Multu_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3236
  switch (VT.SimpleTy) {
3237
  case MVT::i32: return fastEmit_MipsISD_Multu_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3238
  case MVT::i64: return fastEmit_MipsISD_Multu_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3239
  default: return 0;
3240
  }
3241
}
3242
3243
// FastEmit functions for MipsISD::PCKEV.
3244
3245
0
unsigned fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3246
0
  if (RetVT.SimpleTy != MVT::v16i8)
3247
0
    return 0;
3248
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3249
0
    return fastEmitInst_rr(Mips::PCKEV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3250
0
  }
3251
0
  return 0;
3252
0
}
3253
3254
0
unsigned fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3255
0
  if (RetVT.SimpleTy != MVT::v8i16)
3256
0
    return 0;
3257
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3258
0
    return fastEmitInst_rr(Mips::PCKEV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3259
0
  }
3260
0
  return 0;
3261
0
}
3262
3263
0
unsigned fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3264
0
  if (RetVT.SimpleTy != MVT::v4i32)
3265
0
    return 0;
3266
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3267
0
    return fastEmitInst_rr(Mips::PCKEV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3268
0
  }
3269
0
  return 0;
3270
0
}
3271
3272
0
unsigned fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3273
0
  if (RetVT.SimpleTy != MVT::v2i64)
3274
0
    return 0;
3275
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3276
0
    return fastEmitInst_rr(Mips::PCKEV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3277
0
  }
3278
0
  return 0;
3279
0
}
3280
3281
unsigned fastEmit_MipsISD_PCKEV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3282
  switch (VT.SimpleTy) {
3283
  case MVT::v16i8: return fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3284
  case MVT::v8i16: return fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3285
  case MVT::v4i32: return fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3286
  case MVT::v2i64: return fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3287
  default: return 0;
3288
  }
3289
}
3290
3291
// FastEmit functions for MipsISD::PCKOD.
3292
3293
0
unsigned fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3294
0
  if (RetVT.SimpleTy != MVT::v16i8)
3295
0
    return 0;
3296
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3297
0
    return fastEmitInst_rr(Mips::PCKOD_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3298
0
  }
3299
0
  return 0;
3300
0
}
3301
3302
0
unsigned fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3303
0
  if (RetVT.SimpleTy != MVT::v8i16)
3304
0
    return 0;
3305
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3306
0
    return fastEmitInst_rr(Mips::PCKOD_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3307
0
  }
3308
0
  return 0;
3309
0
}
3310
3311
0
unsigned fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3312
0
  if (RetVT.SimpleTy != MVT::v4i32)
3313
0
    return 0;
3314
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3315
0
    return fastEmitInst_rr(Mips::PCKOD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3316
0
  }
3317
0
  return 0;
3318
0
}
3319
3320
0
unsigned fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3321
0
  if (RetVT.SimpleTy != MVT::v2i64)
3322
0
    return 0;
3323
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3324
0
    return fastEmitInst_rr(Mips::PCKOD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3325
0
  }
3326
0
  return 0;
3327
0
}
3328
3329
unsigned fastEmit_MipsISD_PCKOD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3330
  switch (VT.SimpleTy) {
3331
  case MVT::v16i8: return fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3332
  case MVT::v8i16: return fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3333
  case MVT::v4i32: return fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3334
  case MVT::v2i64: return fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3335
  default: return 0;
3336
  }
3337
}
3338
3339
// FastEmit functions for MipsISD::VNOR.
3340
3341
0
unsigned fastEmit_MipsISD_VNOR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3342
0
  if (RetVT.SimpleTy != MVT::v16i8)
3343
0
    return 0;
3344
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3345
0
    return fastEmitInst_rr(Mips::NOR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3346
0
  }
3347
0
  return 0;
3348
0
}
3349
3350
0
unsigned fastEmit_MipsISD_VNOR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3351
0
  if (RetVT.SimpleTy != MVT::v8i16)
3352
0
    return 0;
3353
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3354
0
    return fastEmitInst_rr(Mips::NOR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3355
0
  }
3356
0
  return 0;
3357
0
}
3358
3359
0
unsigned fastEmit_MipsISD_VNOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3360
0
  if (RetVT.SimpleTy != MVT::v4i32)
3361
0
    return 0;
3362
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3363
0
    return fastEmitInst_rr(Mips::NOR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3364
0
  }
3365
0
  return 0;
3366
0
}
3367
3368
0
unsigned fastEmit_MipsISD_VNOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3369
0
  if (RetVT.SimpleTy != MVT::v2i64)
3370
0
    return 0;
3371
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3372
0
    return fastEmitInst_rr(Mips::NOR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3373
0
  }
3374
0
  return 0;
3375
0
}
3376
3377
unsigned fastEmit_MipsISD_VNOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3378
  switch (VT.SimpleTy) {
3379
  case MVT::v16i8: return fastEmit_MipsISD_VNOR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3380
  case MVT::v8i16: return fastEmit_MipsISD_VNOR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3381
  case MVT::v4i32: return fastEmit_MipsISD_VNOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3382
  case MVT::v2i64: return fastEmit_MipsISD_VNOR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3383
  default: return 0;
3384
  }
3385
}
3386
3387
// Top-level FastEmit function.
3388
3389
38
unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) override {
3390
38
  switch (Opcode) {
3391
38
  
case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)6
;
3392
38
  
case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3393
38
  
case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3394
38
  
case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)5
;
3395
38
  
case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3396
38
  
case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3397
38
  
case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3398
38
  
case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3399
38
  
case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)2
;
3400
38
  
case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3401
38
  
case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3402
38
  
case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)4
;
3403
38
  
case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3404
38
  
case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)4
;
3405
38
  
case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3406
38
  
case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3407
38
  
case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3408
38
  
case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3409
38
  
case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)4
;
3410
38
  
case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3411
38
  
case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3412
38
  
case ISD::SUBC: return fastEmit_ISD_SUBC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3413
38
  
case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)4
;
3414
38
  
case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3415
38
  
case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3416
38
  
case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)4
;
3417
38
  
case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)5
;
3418
38
  
case MipsISD::BuildPairF64: return fastEmit_MipsISD_BuildPairF64_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3419
38
  
case MipsISD::DivRem: return fastEmit_MipsISD_DivRem_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3420
38
  
case MipsISD::DivRem16: return fastEmit_MipsISD_DivRem16_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3421
38
  
case MipsISD::DivRemU: return fastEmit_MipsISD_DivRemU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3422
38
  
case MipsISD::DivRemU16: return fastEmit_MipsISD_DivRemU16_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3423
38
  
case MipsISD::EH_RETURN: return fastEmit_MipsISD_EH_RETURN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3424
38
  
case MipsISD::ILVEV: return fastEmit_MipsISD_ILVEV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3425
38
  
case MipsISD::ILVL: return fastEmit_MipsISD_ILVL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3426
38
  
case MipsISD::ILVOD: return fastEmit_MipsISD_ILVOD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3427
38
  
case MipsISD::ILVR: return fastEmit_MipsISD_ILVR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3428
38
  
case MipsISD::MTLOHI: return fastEmit_MipsISD_MTLOHI_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3429
38
  
case MipsISD::Mult: return fastEmit_MipsISD_Mult_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3430
38
  
case MipsISD::Multu: return fastEmit_MipsISD_Multu_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3431
38
  
case MipsISD::PCKEV: return fastEmit_MipsISD_PCKEV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3432
38
  
case MipsISD::PCKOD: return fastEmit_MipsISD_PCKOD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3433
38
  
case MipsISD::VNOR: return fastEmit_MipsISD_VNOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
3434
38
  
default: return 00
;
3435
38
  }
3436
38
}
3437
3438
// FastEmit functions for MipsISD::ExtractElementF64.
3439
3440
0
unsigned fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3441
0
  if (RetVT.SimpleTy != MVT::i32)
3442
0
    return 0;
3443
0
  if ((Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())) {
3444
0
    return fastEmitInst_ri(Mips::ExtractElementF64_64, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3445
0
  }
3446
0
  if ((!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) {
3447
0
    return fastEmitInst_ri(Mips::ExtractElementF64, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3448
0
  }
3449
0
  return 0;
3450
0
}
3451
3452
unsigned fastEmit_MipsISD_ExtractElementF64_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3453
  switch (VT.SimpleTy) {
3454
  case MVT::f64: return fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(RetVT, Op0, Op0IsKill, imm1);
3455
  default: return 0;
3456
  }
3457
}
3458
3459
// FastEmit functions for MipsISD::SHLL_DSP.
3460
3461
0
unsigned fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3462
0
  if (RetVT.SimpleTy != MVT::v4i8)
3463
0
    return 0;
3464
0
  if ((Subtarget->hasDSP())) {
3465
0
    return fastEmitInst_ri(Mips::SHLL_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
3466
0
  }
3467
0
  return 0;
3468
0
}
3469
3470
0
unsigned fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3471
0
  if (RetVT.SimpleTy != MVT::v2i16)
3472
0
    return 0;
3473
0
  if ((Subtarget->hasDSP())) {
3474
0
    return fastEmitInst_ri(Mips::SHLL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
3475
0
  }
3476
0
  return 0;
3477
0
}
3478
3479
unsigned fastEmit_MipsISD_SHLL_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3480
  switch (VT.SimpleTy) {
3481
  case MVT::v4i8: return fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1);
3482
  case MVT::v2i16: return fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1);
3483
  default: return 0;
3484
  }
3485
}
3486
3487
// FastEmit functions for MipsISD::SHRA_DSP.
3488
3489
0
unsigned fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3490
0
  if (RetVT.SimpleTy != MVT::v4i8)
3491
0
    return 0;
3492
0
  if ((Subtarget->hasDSPR2())) {
3493
0
    return fastEmitInst_ri(Mips::SHRA_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
3494
0
  }
3495
0
  return 0;
3496
0
}
3497
3498
0
unsigned fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3499
0
  if (RetVT.SimpleTy != MVT::v2i16)
3500
0
    return 0;
3501
0
  if ((Subtarget->hasDSP())) {
3502
0
    return fastEmitInst_ri(Mips::SHRA_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
3503
0
  }
3504
0
  return 0;
3505
0
}
3506
3507
unsigned fastEmit_MipsISD_SHRA_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3508
  switch (VT.SimpleTy) {
3509
  case MVT::v4i8: return fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1);
3510
  case MVT::v2i16: return fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1);
3511
  default: return 0;
3512
  }
3513
}
3514
3515
// FastEmit functions for MipsISD::SHRL_DSP.
3516
3517
0
unsigned fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3518
0
  if (RetVT.SimpleTy != MVT::v4i8)
3519
0
    return 0;
3520
0
  if ((Subtarget->hasDSP())) {
3521
0
    return fastEmitInst_ri(Mips::SHRL_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
3522
0
  }
3523
0
  return 0;
3524
0
}
3525
3526
0
unsigned fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3527
0
  if (RetVT.SimpleTy != MVT::v2i16)
3528
0
    return 0;
3529
0
  if ((Subtarget->hasDSPR2())) {
3530
0
    return fastEmitInst_ri(Mips::SHRL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
3531
0
  }
3532
0
  return 0;
3533
0
}
3534
3535
unsigned fastEmit_MipsISD_SHRL_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3536
  switch (VT.SimpleTy) {
3537
  case MVT::v4i8: return fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1);
3538
  case MVT::v2i16: return fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1);
3539
  default: return 0;
3540
  }
3541
}
3542
3543
// Top-level FastEmit function.
3544
3545
8
unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) override {
3546
8
  if (VT == MVT::i32 && Predicate_immZExt5(imm1))
3547
8
    if (unsigned Reg = fastEmit_ri_Predicate_immZExt5(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
3548
0
      return Reg;
3549
8
3550
8
  if (VT == MVT::i32 && Predicate_immZExt6(imm1))
3551
8
    if (unsigned Reg = fastEmit_ri_Predicate_immZExt6(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
3552
0
      return Reg;
3553
8
3554
8
  if (VT == MVT::iPTR && 
Predicate_immZExt2Ptr(imm1)0
)
3555
0
    if (unsigned Reg = fastEmit_ri_Predicate_immZExt2Ptr(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
3556
0
      return Reg;
3557
8
3558
8
  if (VT == MVT::iPTR && 
Predicate_immZExt1Ptr(imm1)0
)
3559
0
    if (unsigned Reg = fastEmit_ri_Predicate_immZExt1Ptr(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
3560
0
      return Reg;
3561
8
3562
8
  if (VT == MVT::i32 && Predicate_immZExt4(imm1))
3563
8
    if (unsigned Reg = fastEmit_ri_Predicate_immZExt4(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
3564
0
      return Reg;
3565
8
3566
8
  if (VT == MVT::i32 && Predicate_immSExtAddiur2(imm1))
3567
1
    if (unsigned Reg = fastEmit_ri_Predicate_immSExtAddiur2(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
3568
0
      return Reg;
3569
8
3570
8
  if (VT == MVT::i32 && Predicate_immSExtAddius5(imm1))
3571
8
    if (unsigned Reg = fastEmit_ri_Predicate_immSExtAddius5(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
3572
0
      return Reg;
3573
8
3574
8
  if (VT == MVT::i32 && Predicate_immZExtAndi16(imm1))
3575
1
    if (unsigned Reg = fastEmit_ri_Predicate_immZExtAndi16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
3576
0
      return Reg;
3577
8
3578
8
  if (VT == MVT::i32 && Predicate_immZExt2Shift(imm1))
3579
1
    if (unsigned Reg = fastEmit_ri_Predicate_immZExt2Shift(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
3580
0
      return Reg;
3581
8
3582
8
  switch (Opcode) {
3583
8
  
case MipsISD::ExtractElementF64: return fastEmit_MipsISD_ExtractElementF64_ri(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3584
8
  
case MipsISD::SHLL_DSP: return fastEmit_MipsISD_SHLL_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3585
8
  
case MipsISD::SHRA_DSP: return fastEmit_MipsISD_SHRA_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3586
8
  
case MipsISD::SHRL_DSP: return fastEmit_MipsISD_SHRL_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3587
8
  default: return 0;
3588
8
  }
3589
8
}
3590
3591
// FastEmit functions for ISD::ROTR.
3592
3593
0
unsigned fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3594
0
  if (RetVT.SimpleTy != MVT::i32)
3595
0
    return 0;
3596
0
  if ((Subtarget->inMicroMipsMode())) {
3597
0
    return fastEmitInst_ri(Mips::ROTR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3598
0
  }
3599
0
  if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3600
0
    return fastEmitInst_ri(Mips::ROTR, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3601
0
  }
3602
0
  return 0;
3603
0
}
3604
3605
unsigned fastEmit_ISD_ROTR_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3606
  switch (VT.SimpleTy) {
3607
  case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
3608
  default: return 0;
3609
  }
3610
}
3611
3612
// FastEmit functions for ISD::SHL.
3613
3614
0
unsigned fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3615
0
  if (RetVT.SimpleTy != MVT::i32)
3616
0
    return 0;
3617
0
  if ((Subtarget->inMicroMipsMode())) {
3618
0
    return fastEmitInst_ri(Mips::SLL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3619
0
  }
3620
0
  if ((Subtarget->inMips16Mode())) {
3621
0
    return fastEmitInst_ri(Mips::SllX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1);
3622
0
  }
3623
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3624
0
    return fastEmitInst_ri(Mips::SLL, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3625
0
  }
3626
0
  return 0;
3627
0
}
3628
3629
unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3630
  switch (VT.SimpleTy) {
3631
  case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
3632
  default: return 0;
3633
  }
3634
}
3635
3636
// FastEmit functions for ISD::SRA.
3637
3638
0
unsigned fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3639
0
  if (RetVT.SimpleTy != MVT::i32)
3640
0
    return 0;
3641
0
  if ((Subtarget->inMicroMipsMode())) {
3642
0
    return fastEmitInst_ri(Mips::SRA_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3643
0
  }
3644
0
  if ((Subtarget->inMips16Mode())) {
3645
0
    return fastEmitInst_ri(Mips::SraX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1);
3646
0
  }
3647
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3648
0
    return fastEmitInst_ri(Mips::SRA, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3649
0
  }
3650
0
  return 0;
3651
0
}
3652
3653
unsigned fastEmit_ISD_SRA_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3654
  switch (VT.SimpleTy) {
3655
  case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
3656
  default: return 0;
3657
  }
3658
}
3659
3660
// FastEmit functions for ISD::SRL.
3661
3662
0
unsigned fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3663
0
  if (RetVT.SimpleTy != MVT::i32)
3664
0
    return 0;
3665
0
  if ((Subtarget->inMicroMipsMode())) {
3666
0
    return fastEmitInst_ri(Mips::SRL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3667
0
  }
3668
0
  if ((Subtarget->inMips16Mode())) {
3669
0
    return fastEmitInst_ri(Mips::SrlX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1);
3670
0
  }
3671
0
  if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3672
0
    return fastEmitInst_ri(Mips::SRL, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3673
0
  }
3674
0
  return 0;
3675
0
}
3676
3677
unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3678
  switch (VT.SimpleTy) {
3679
  case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
3680
  default: return 0;
3681
  }
3682
}
3683
3684
// Top-level FastEmit function.
3685
3686
8
unsigned fastEmit_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3687
8
  switch (Opcode) {
3688
8
  
case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3689
8
  
case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3690
8
  
case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3691
8
  
case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3692
8
  default: return 0;
3693
8
  }
3694
8
}
3695
3696
// FastEmit functions for ISD::ROTR.
3697
3698
0
unsigned fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3699
0
  if (RetVT.SimpleTy != MVT::i64)
3700
0
    return 0;
3701
0
  if ((Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3702
0
    return fastEmitInst_ri(Mips::DROTR, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
3703
0
  }
3704
0
  return 0;
3705
0
}
3706
3707
unsigned fastEmit_ISD_ROTR_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3708
  switch (VT.SimpleTy) {
3709
  case MVT::i64: return fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
3710
  default: return 0;
3711
  }
3712
}
3713
3714
// FastEmit functions for ISD::SHL.
3715
3716
0
unsigned fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3717
0
  if (RetVT.SimpleTy != MVT::i64)
3718
0
    return 0;
3719
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3720
0
    return fastEmitInst_ri(Mips::DSLL, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
3721
0
  }
3722
0
  return 0;
3723
0
}
3724
3725
unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3726
  switch (VT.SimpleTy) {
3727
  case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
3728
  default: return 0;
3729
  }
3730
}
3731
3732
// FastEmit functions for ISD::SRA.
3733
3734
0
unsigned fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3735
0
  if (RetVT.SimpleTy != MVT::i64)
3736
0
    return 0;
3737
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3738
0
    return fastEmitInst_ri(Mips::DSRA, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
3739
0
  }
3740
0
  return 0;
3741
0
}
3742
3743
unsigned fastEmit_ISD_SRA_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3744
  switch (VT.SimpleTy) {
3745
  case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
3746
  default: return 0;
3747
  }
3748
}
3749
3750
// FastEmit functions for ISD::SRL.
3751
3752
0
unsigned fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3753
0
  if (RetVT.SimpleTy != MVT::i64)
3754
0
    return 0;
3755
0
  if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3756
0
    return fastEmitInst_ri(Mips::DSRL, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
3757
0
  }
3758
0
  return 0;
3759
0
}
3760
3761
unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3762
  switch (VT.SimpleTy) {
3763
  case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
3764
  default: return 0;
3765
  }
3766
}
3767
3768
// Top-level FastEmit function.
3769
3770
8
unsigned fastEmit_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3771
8
  switch (Opcode) {
3772
8
  
case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3773
8
  
case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3774
8
  
case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3775
8
  
case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3776
8
  default: return 0;
3777
8
  }
3778
8
}
3779
3780
// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
3781
3782
0
unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3783
0
  if (RetVT.SimpleTy != MVT::f32)
3784
0
    return 0;
3785
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3786
0
    return fastEmitInst_ri(Mips::COPY_FW_PSEUDO, &Mips::FGR32RegClass, Op0, Op0IsKill, imm1);
3787
0
  }
3788
0
  return 0;
3789
0
}
3790
3791
unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3792
  switch (VT.SimpleTy) {
3793
  case MVT::v4f32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(RetVT, Op0, Op0IsKill, imm1);
3794
  default: return 0;
3795
  }
3796
}
3797
3798
// Top-level FastEmit function.
3799
3800
unsigned fastEmit_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3801
  switch (Opcode) {
3802
  case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(VT, RetVT, Op0, Op0IsKill, imm1);
3803
  default: return 0;
3804
  }
3805
}
3806
3807
// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
3808
3809
0
unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3810
0
  if (RetVT.SimpleTy != MVT::f64)
3811
0
    return 0;
3812
0
  if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3813
0
    return fastEmitInst_ri(Mips::COPY_FD_PSEUDO, &Mips::FGR64RegClass, Op0, Op0IsKill, imm1);
3814
0
  }
3815
0
  return 0;
3816
0
}
3817
3818
unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3819
  switch (VT.SimpleTy) {
3820
  case MVT::v2f64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(RetVT, Op0, Op0IsKill, imm1);
3821
  default: return 0;
3822
  }
3823
}
3824
3825
// Top-level FastEmit function.
3826
3827
unsigned fastEmit_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3828
  switch (Opcode) {
3829
  case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(VT, RetVT, Op0, Op0IsKill, imm1);
3830
  default: return 0;
3831
  }
3832
}
3833
3834
// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
3835
3836
0
unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3837
0
  if (RetVT.SimpleTy != MVT::i32)
3838
0
    return 0;
3839
0
  if ((Subtarget->hasMSA())) {
3840
0
    return fastEmitInst_ri(Mips::COPY_S_W, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3841
0
  }
3842
0
  return 0;
3843
0
}
3844
3845
unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3846
  switch (VT.SimpleTy) {
3847
  case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(RetVT, Op0, Op0IsKill, imm1);
3848
  default: return 0;
3849
  }
3850
}
3851
3852
// Top-level FastEmit function.
3853
3854
8
unsigned fastEmit_ri_Predicate_immZExt4(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3855
8
  switch (Opcode) {
3856
8
  
case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3857
8
  default: return 0;
3858
8
  }
3859
8
}
3860
3861
// FastEmit functions for ISD::ADD.
3862
3863
1
unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3864
1
  if (RetVT.SimpleTy != MVT::i32)
3865
0
    return 0;
3866
1
  if ((Subtarget->inMicroMipsMode())) {
3867
0
    return fastEmitInst_ri(Mips::ADDIUR2_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
3868
0
  }
3869
1
  return 0;
3870
1
}
3871
3872
1
unsigned fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3873
1
  switch (VT.SimpleTy) {
3874
1
  case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(RetVT, Op0, Op0IsKill, imm1);
3875
1
  
default: return 00
;
3876
1
  }
3877
1
}
3878
3879
// Top-level FastEmit function.
3880
3881
1
unsigned fastEmit_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3882
1
  switch (Opcode) {
3883
1
  case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(VT, RetVT, Op0, Op0IsKill, imm1);
3884
1
  
default: return 00
;
3885
1
  }
3886
1
}
3887
3888
// FastEmit functions for ISD::ADD.
3889
3890
1
unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3891
1
  if (RetVT.SimpleTy != MVT::i32)
3892
0
    return 0;
3893
1
  if ((Subtarget->inMicroMipsMode())) {
3894
0
    return fastEmitInst_ri(Mips::ADDIUS5_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
3895
0
  }
3896
1
  return 0;
3897
1
}
3898
3899
1
unsigned fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3900
1
  switch (VT.SimpleTy) {
3901
1
  case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(RetVT, Op0, Op0IsKill, imm1);
3902
1
  
default: return 00
;
3903
1
  }
3904
1
}
3905
3906
// Top-level FastEmit function.
3907
3908
8
unsigned fastEmit_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3909
8
  switch (Opcode) {
3910
8
  
case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(VT, RetVT, Op0, Op0IsKill, imm1)1
;
3911
8
  
default: return 07
;
3912
8
  }
3913
8
}
3914
3915
// FastEmit functions for ISD::AND.
3916
3917
0
unsigned fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3918
0
  if (RetVT.SimpleTy != MVT::i32)
3919
0
    return 0;
3920
0
  if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
3921
0
    return fastEmitInst_ri(Mips::ANDI16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
3922
0
  }
3923
0
  if ((Subtarget->inMicroMipsMode())) {
3924
0
    return fastEmitInst_ri(Mips::ANDI16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
3925
0
  }
3926
0
  return 0;
3927
0
}
3928
3929
unsigned fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3930
  switch (VT.SimpleTy) {
3931
  case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(RetVT, Op0, Op0IsKill, imm1);
3932
  default: return 0;
3933
  }
3934
}
3935
3936
// Top-level FastEmit function.
3937
3938
1
unsigned fastEmit_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3939
1
  switch (Opcode) {
3940
1
  
case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3941
1
  default: return 0;
3942
1
  }
3943
1
}
3944
3945
// FastEmit functions for ISD::SHL.
3946
3947
0
unsigned fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3948
0
  if (RetVT.SimpleTy != MVT::i32)
3949
0
    return 0;
3950
0
  if ((Subtarget->inMicroMipsMode())) {
3951
0
    return fastEmitInst_ri(Mips::SLL16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
3952
0
  }
3953
0
  return 0;
3954
0
}
3955
3956
unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3957
  switch (VT.SimpleTy) {
3958
  case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, Op0IsKill, imm1);
3959
  default: return 0;
3960
  }
3961
}
3962
3963
// FastEmit functions for ISD::SRL.
3964
3965
0
unsigned fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3966
0
  if (RetVT.SimpleTy != MVT::i32)
3967
0
    return 0;
3968
0
  if ((Subtarget->inMicroMipsMode())) {
3969
0
    return fastEmitInst_ri(Mips::SRL16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
3970
0
  }
3971
0
  return 0;
3972
0
}
3973
3974
unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3975
  switch (VT.SimpleTy) {
3976
  case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, Op0IsKill, imm1);
3977
  default: return 0;
3978
  }
3979
}
3980
3981
// Top-level FastEmit function.
3982
3983
1
unsigned fastEmit_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3984
1
  switch (Opcode) {
3985
1
  
case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3986
1
  
case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3987
1
  default: return 0;
3988
1
  }
3989
1
}
3990
3991
// FastEmit functions for ISD::Constant.
3992
3993
8
unsigned fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
3994
8
  if (RetVT.SimpleTy != MVT::i32)
3995
0
    return 0;
3996
8
  if ((Subtarget->inMips16Mode())) {
3997
0
    return fastEmitInst_i(Mips::LwConstant32, &Mips::CPU16RegsRegClass, imm0);
3998
0
  }
3999
8
  return 0;
4000
8
}
4001
4002
8
unsigned fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
4003
8
  switch (VT.SimpleTy) {
4004
8
  case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0);
4005
8
  
default: return 00
;
4006
8
  }
4007
8
}
4008
4009
// Top-level FastEmit function.
4010
4011
8
unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override {
4012
8
  switch (Opcode) {
4013
8
  case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0);
4014
8
  
default: return 00
;
4015
8
  }
4016
8
}
4017