Coverage Report

Created: 2018-11-16 02:38

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Mips/MipsGenGlobalISel.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Global Instruction Selector for the Mips target                            *|
4
|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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9
#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10
const unsigned MAX_SUBTARGET_PREDICATES = 41;
11
using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
12
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
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#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15
  mutable MatcherState State;
16
  typedef ComplexRendererFns(MipsInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17
  typedef void(MipsInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const;
18
  const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
19
  static MipsInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20
  static MipsInstructionSelector::CustomRendererFn CustomRenderers[];
21
  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22
  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23
  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24
  const int64_t *getMatchTable() const override;
25
  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
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#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
27
28
#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
29
, State(0),
30
ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
31
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
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#ifdef GET_GLOBALISEL_IMPL
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// Bits for subtarget features that participate in instruction matching.
35
enum SubtargetFeatureBits : uint8_t {
36
  Feature_HasMips2Bit = 7,
37
  Feature_HasMips3Bit = 16,
38
  Feature_HasMips4_32Bit = 26,
39
  Feature_NotMips4_32Bit = 27,
40
  Feature_HasMips4_32r2Bit = 17,
41
  Feature_HasMips32Bit = 3,
42
  Feature_HasMips32r2Bit = 6,
43
  Feature_HasMips32r6Bit = 28,
44
  Feature_NotMips32r6Bit = 4,
45
  Feature_IsGP64bitBit = 21,
46
  Feature_IsPTR64bitBit = 23,
47
  Feature_HasMips64Bit = 24,
48
  Feature_HasMips64r2Bit = 22,
49
  Feature_HasMips64r6Bit = 29,
50
  Feature_NotMips64r6Bit = 5,
51
  Feature_InMips16ModeBit = 30,
52
  Feature_NotInMips16ModeBit = 0,
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  Feature_HasCnMipsBit = 25,
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  Feature_NotCnMipsBit = 8,
55
  Feature_IsN64Bit = 37,
56
  Feature_RelocNotPICBit = 9,
57
  Feature_RelocPICBit = 36,
58
  Feature_NoNaNsFPMathBit = 20,
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  Feature_HasStdEncBit = 1,
60
  Feature_NotDSPBit = 11,
61
  Feature_InMicroMipsBit = 34,
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  Feature_NotInMicroMipsBit = 2,
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  Feature_IsLEBit = 39,
64
  Feature_IsBEBit = 40,
65
  Feature_IsNotNaClBit = 18,
66
  Feature_HasEVABit = 35,
67
  Feature_HasMSABit = 33,
68
  Feature_HasMadd4Bit = 19,
69
  Feature_UseIndirectJumpsHazardBit = 12,
70
  Feature_NoIndirectJumpGuardsBit = 10,
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  Feature_AllowFPOpFusionBit = 38,
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  Feature_IsFP64bitBit = 15,
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  Feature_NotFP64bitBit = 14,
74
  Feature_IsNotSoftFloatBit = 13,
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  Feature_HasDSPBit = 31,
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  Feature_HasDSPR2Bit = 32,
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};
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PredicateBitset MipsInstructionSelector::
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10.3k
computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const {
81
10.3k
  PredicateBitset Features;
82
10.3k
  if (Subtarget->hasMips2())
83
10.3k
    Features[Feature_HasMips2Bit] = 1;
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10.3k
  if (Subtarget->hasMips3())
85
3.60k
    Features[Feature_HasMips3Bit] = 1;
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10.3k
  if (Subtarget->hasMips4_32())
87
10.0k
    Features[Feature_HasMips4_32Bit] = 1;
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10.3k
  if (!Subtarget->hasMips4_32())
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271
    Features[Feature_NotMips4_32Bit] = 1;
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10.3k
  if (Subtarget->hasMips4_32r2())
91
6.00k
    Features[Feature_HasMips4_32r2Bit] = 1;
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10.3k
  if (Subtarget->hasMips32())
93
9.70k
    Features[Feature_HasMips32Bit] = 1;
94
10.3k
  if (Subtarget->hasMips32r2())
95
4.28k
    Features[Feature_HasMips32r2Bit] = 1;
96
10.3k
  if (Subtarget->hasMips32r6())
97
1.34k
    Features[Feature_HasMips32r6Bit] = 1;
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10.3k
  if (!Subtarget->hasMips32r6())
99
8.96k
    Features[Feature_NotMips32r6Bit] = 1;
100
10.3k
  if (Subtarget->isGP64bit())
101
3.60k
    Features[Feature_IsGP64bitBit] = 1;
102
10.3k
  if (Subtarget->isABI_N64())
103
3.08k
    Features[Feature_IsPTR64bitBit] = 1;
104
10.3k
  if (Subtarget->hasMips64())
105
3.11k
    Features[Feature_HasMips64Bit] = 1;
106
10.3k
  if (Subtarget->hasMips64r2())
107
1.75k
    Features[Feature_HasMips64r2Bit] = 1;
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10.3k
  if (Subtarget->hasMips64r6())
109
500
    Features[Feature_HasMips64r6Bit] = 1;
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10.3k
  if (!Subtarget->hasMips64r6())
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9.81k
    Features[Feature_NotMips64r6Bit] = 1;
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10.3k
  if (Subtarget->inMips16Mode())
113
2.68k
    Features[Feature_InMips16ModeBit] = 1;
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10.3k
  if (!Subtarget->inMips16Mode())
115
7.62k
    Features[Feature_NotInMips16ModeBit] = 1;
116
10.3k
  if (Subtarget->hasCnMips())
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20
    Features[Feature_HasCnMipsBit] = 1;
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10.3k
  if (!Subtarget->hasCnMips())
119
10.2k
    Features[Feature_NotCnMipsBit] = 1;
120
10.3k
  if (Subtarget->isABI_N64())
121
3.08k
    Features[Feature_IsN64Bit] = 1;
122
10.3k
  if (!TM.isPositionIndependent())
123
6.13k
    Features[Feature_RelocNotPICBit] = 1;
124
10.3k
  if (TM.isPositionIndependent())
125
4.17k
    Features[Feature_RelocPICBit] = 1;
126
10.3k
  if (TM.Options.NoNaNsFPMath)
127
130
    Features[Feature_NoNaNsFPMathBit] = 1;
128
10.3k
  if (Subtarget->hasStandardEncoding())
129
6.92k
    Features[Feature_HasStdEncBit] = 1;
130
10.3k
  if (!Subtarget->hasDSP())
131
10.2k
    Features[Feature_NotDSPBit] = 1;
132
10.3k
  if (Subtarget->inMicroMipsMode())
133
701
    Features[Feature_InMicroMipsBit] = 1;
134
10.3k
  if (!Subtarget->inMicroMipsMode())
135
9.61k
    Features[Feature_NotInMicroMipsBit] = 1;
136
10.3k
  if (Subtarget->isLittle())
137
5.05k
    Features[Feature_IsLEBit] = 1;
138
10.3k
  if (!Subtarget->isLittle())
139
5.25k
    Features[Feature_IsBEBit] = 1;
140
10.3k
  if (!Subtarget->isTargetNaCl())
141
10.2k
    Features[Feature_IsNotNaClBit] = 1;
142
10.3k
  if (Subtarget->hasEVA())
143
10
    Features[Feature_HasEVABit] = 1;
144
10.3k
  if (Subtarget->hasMSA())
145
947
    Features[Feature_HasMSABit] = 1;
146
10.3k
  if (!Subtarget->disableMadd4())
147
10.2k
    Features[Feature_HasMadd4Bit] = 1;
148
10.3k
  if (Subtarget->useIndirectJumpsHazard())
149
143
    Features[Feature_UseIndirectJumpsHazardBit] = 1;
150
10.3k
  if (!Subtarget->useIndirectJumpsHazard())
151
10.1k
    Features[Feature_NoIndirectJumpGuardsBit] = 1;
152
10.3k
  if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast)
153
5
    Features[Feature_AllowFPOpFusionBit] = 1;
154
10.3k
  if (Subtarget->isFP64bit())
155
5.37k
    Features[Feature_IsFP64bitBit] = 1;
156
10.3k
  if (!Subtarget->isFP64bit())
157
4.93k
    Features[Feature_NotFP64bitBit] = 1;
158
10.3k
  if (!Subtarget->useSoftFloat())
159
9.99k
    Features[Feature_IsNotSoftFloatBit] = 1;
160
10.3k
  if (Subtarget->hasDSP())
161
102
    Features[Feature_HasDSPBit] = 1;
162
10.3k
  if (Subtarget->hasDSPR2())
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26
    Features[Feature_HasDSPR2Bit] = 1;
164
10.3k
  return Features;
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10.3k
}
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PredicateBitset MipsInstructionSelector::
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144
computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget, const MachineFunction *MF) const {
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144
  PredicateBitset Features;
170
144
  return Features;
171
144
}
172
173
// LLT Objects.
174
enum {
175
  GILLT_s16,
176
  GILLT_s32,
177
  GILLT_s64,
178
  GILLT_v2s16,
179
  GILLT_v2s64,
180
  GILLT_v4s8,
181
  GILLT_v4s32,
182
  GILLT_v8s16,
183
  GILLT_v16s8,
184
};
185
const static size_t NumTypeObjects = 9;
186
const static LLT TypeObjects[] = {
187
  LLT::scalar(16),
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  LLT::scalar(32),
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  LLT::scalar(64),
190
  LLT::vector(2, 16),
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  LLT::vector(2, 64),
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  LLT::vector(4, 8),
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  LLT::vector(4, 32),
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  LLT::vector(8, 16),
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  LLT::vector(16, 8),
196
};
197
198
// Feature bitsets.
199
enum {
200
  GIFBS_Invalid,
201
  GIFBS_HasCnMips,
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  GIFBS_HasDSP,
203
  GIFBS_HasDSPR2,
204
  GIFBS_HasMSA,
205
  GIFBS_InMicroMips,
206
  GIFBS_InMips16Mode,
207
  GIFBS_IsFP64bit,
208
  GIFBS_NotFP64bit,
209
  GIFBS_HasDSP_InMicroMips,
210
  GIFBS_HasDSP_NotInMicroMips,
211
  GIFBS_HasDSPR2_InMicroMips,
212
  GIFBS_HasMSA_HasStdEnc,
213
  GIFBS_HasMSA_IsBE,
214
  GIFBS_HasMSA_IsLE,
215
  GIFBS_HasMips32r6_HasStdEnc,
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  GIFBS_HasMips32r6_InMicroMips,
217
  GIFBS_HasMips64r2_HasStdEnc,
218
  GIFBS_HasMips64r6_HasStdEnc,
219
  GIFBS_HasStdEnc_IsNotSoftFloat,
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  GIFBS_HasStdEnc_NotInMicroMips,
221
  GIFBS_HasStdEnc_NotMips4_32,
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  GIFBS_InMicroMips_IsFP64bit,
223
  GIFBS_InMicroMips_IsNotSoftFloat,
224
  GIFBS_InMicroMips_NotFP64bit,
225
  GIFBS_InMicroMips_NotMips32r6,
226
  GIFBS_IsGP64bit_NotInMips16Mode,
227
  GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
228
  GIFBS_HasMSA_HasMips64_HasStdEnc,
229
  GIFBS_HasMips3_HasStdEnc_IsGP64bit,
230
  GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
231
  GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips,
232
  GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
233
  GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
234
  GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
235
  GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips,
236
  GIFBS_HasStdEnc_IsFP64bit_NotMips4_32,
237
  GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
238
  GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips,
239
  GIFBS_HasStdEnc_NotFP64bit_NotMips4_32,
240
  GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC,
241
  GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
242
  GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
243
  GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
244
  GIFBS_InMicroMips_NotMips32r6_RelocNotPIC,
245
  GIFBS_InMicroMips_NotMips32r6_RelocPIC,
246
  GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
247
  GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
248
  GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
249
  GIFBS_HasMips64_HasStdEnc_NotInMicroMips_NotMips64r6,
250
  GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips,
251
  GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
252
  GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
253
  GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
254
  GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
255
  GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotMips32r6_NotMips32r6,
256
  GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
257
  GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
258
  GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
259
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
260
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
261
  GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6_NotMips32r6,
262
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
263
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
264
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
265
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
266
};
267
const static PredicateBitset FeatureBitsets[] {
268
  {}, // GIFBS_Invalid
269
  {Feature_HasCnMipsBit, },
270
  {Feature_HasDSPBit, },
271
  {Feature_HasDSPR2Bit, },
272
  {Feature_HasMSABit, },
273
  {Feature_InMicroMipsBit, },
274
  {Feature_InMips16ModeBit, },
275
  {Feature_IsFP64bitBit, },
276
  {Feature_NotFP64bitBit, },
277
  {Feature_HasDSPBit, Feature_InMicroMipsBit, },
278
  {Feature_HasDSPBit, Feature_NotInMicroMipsBit, },
279
  {Feature_HasDSPR2Bit, Feature_InMicroMipsBit, },
280
  {Feature_HasMSABit, Feature_HasStdEncBit, },
281
  {Feature_HasMSABit, Feature_IsBEBit, },
282
  {Feature_HasMSABit, Feature_IsLEBit, },
283
  {Feature_HasMips32r6Bit, Feature_HasStdEncBit, },
284
  {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, },
285
  {Feature_HasMips64r2Bit, Feature_HasStdEncBit, },
286
  {Feature_HasMips64r6Bit, Feature_HasStdEncBit, },
287
  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },
288
  {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
289
  {Feature_HasStdEncBit, Feature_NotMips4_32Bit, },
290
  {Feature_InMicroMipsBit, Feature_IsFP64bitBit, },
291
  {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
292
  {Feature_InMicroMipsBit, Feature_NotFP64bitBit, },
293
  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },
294
  {Feature_IsGP64bitBit, Feature_NotInMips16ModeBit, },
295
  {Feature_AllowFPOpFusionBit, Feature_HasMSABit, Feature_HasStdEncBit, },
296
  {Feature_HasMSABit, Feature_HasMips64Bit, Feature_HasStdEncBit, },
297
  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, },
298
  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
299
  {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
300
  {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
301
  {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
302
  {Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
303
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, },
304
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, },
305
  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
306
  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
307
  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, },
308
  {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_RelocNotPICBit, },
309
  {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },
310
  {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, },
311
  {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, },
312
  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocNotPICBit, },
313
  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocPICBit, },
314
  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
315
  {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
316
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
317
  {Feature_HasMips64Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips64r6Bit, },
318
  {Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
319
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
320
  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
321
  {Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
322
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
323
  {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotMips32r6Bit, Feature_NotMips32r6Bit, },
324
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
325
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
326
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
327
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
328
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
329
  {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips32r6Bit, },
330
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
331
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
332
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
333
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
334
};
335
336
// ComplexPattern predicates.
337
enum {
338
  GICP_Invalid,
339
};
340
// See constructor for table contents
341
342
// PatFrag predicates.
343
enum {
344
  GIPFP_I64_Predicate_immLi16 = GIPFP_I64_Invalid + 1,
345
  GIPFP_I64_Predicate_immSExt10,
346
  GIPFP_I64_Predicate_immSExt6,
347
  GIPFP_I64_Predicate_immSExtAddiur2,
348
  GIPFP_I64_Predicate_immSExtAddius5,
349
  GIPFP_I64_Predicate_immZExt1,
350
  GIPFP_I64_Predicate_immZExt10,
351
  GIPFP_I64_Predicate_immZExt1Ptr,
352
  GIPFP_I64_Predicate_immZExt2,
353
  GIPFP_I64_Predicate_immZExt2Lsa,
354
  GIPFP_I64_Predicate_immZExt2Ptr,
355
  GIPFP_I64_Predicate_immZExt2Shift,
356
  GIPFP_I64_Predicate_immZExt3,
357
  GIPFP_I64_Predicate_immZExt3Ptr,
358
  GIPFP_I64_Predicate_immZExt4,
359
  GIPFP_I64_Predicate_immZExt4Ptr,
360
  GIPFP_I64_Predicate_immZExt5,
361
  GIPFP_I64_Predicate_immZExt5_64,
362
  GIPFP_I64_Predicate_immZExt6,
363
  GIPFP_I64_Predicate_immZExt8,
364
  GIPFP_I64_Predicate_immZExtAndi16,
365
  GIPFP_I64_Predicate_immi32Cst15,
366
  GIPFP_I64_Predicate_immi32Cst31,
367
  GIPFP_I64_Predicate_immi32Cst7,
368
};
369
14
bool MipsInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
370
14
  switch (PredicateID) {
371
14
  case GIPFP_I64_Predicate_immLi16: {
372
0
    return Imm >= -1 && Imm <= 126;
373
14
    
llvm_unreachable0
("ImmediateCode should have returned");
374
14
    
return false0
;
375
14
  }
376
14
  case GIPFP_I64_Predicate_immSExt10: {
377
0
    return isInt<10>(Imm);
378
14
    
llvm_unreachable0
("ImmediateCode should have returned");
379
14
    
return false0
;
380
14
  }
381
14
  case GIPFP_I64_Predicate_immSExt6: {
382
0
    return isInt<6>(Imm);
383
14
    
llvm_unreachable0
("ImmediateCode should have returned");
384
14
    
return false0
;
385
14
  }
386
14
  case GIPFP_I64_Predicate_immSExtAddiur2: {
387
0
    return Imm == 1 || Imm == -1 ||
388
0
                                           ((Imm % 4 == 0) &&
389
0
                                            Imm < 28 && Imm > 0);
390
14
    
llvm_unreachable0
("ImmediateCode should have returned");
391
14
    
return false0
;
392
14
  }
393
14
  case GIPFP_I64_Predicate_immSExtAddius5: {
394
0
    return Imm >= -8 && Imm <= 7;
395
14
    
llvm_unreachable0
("ImmediateCode should have returned");
396
14
    
return false0
;
397
14
  }
398
14
  case GIPFP_I64_Predicate_immZExt1: {
399
0
    return isUInt<1>(Imm);
400
14
    
llvm_unreachable0
("ImmediateCode should have returned");
401
14
    
return false0
;
402
14
  }
403
14
  case GIPFP_I64_Predicate_immZExt10: {
404
0
    return isUInt<10>(Imm);
405
14
    
llvm_unreachable0
("ImmediateCode should have returned");
406
14
    
return false0
;
407
14
  }
408
14
  case GIPFP_I64_Predicate_immZExt1Ptr: {
409
0
    return isUInt<1>(Imm);
410
14
    
llvm_unreachable0
("ImmediateCode should have returned");
411
14
    
return false0
;
412
14
  }
413
14
  case GIPFP_I64_Predicate_immZExt2: {
414
0
    return isUInt<2>(Imm);
415
14
    
llvm_unreachable0
("ImmediateCode should have returned");
416
14
    
return false0
;
417
14
  }
418
14
  case GIPFP_I64_Predicate_immZExt2Lsa: {
419
0
    return isUInt<2>(Imm - 1);
420
14
    
llvm_unreachable0
("ImmediateCode should have returned");
421
14
    
return false0
;
422
14
  }
423
14
  case GIPFP_I64_Predicate_immZExt2Ptr: {
424
0
    return isUInt<2>(Imm);
425
14
    
llvm_unreachable0
("ImmediateCode should have returned");
426
14
    
return false0
;
427
14
  }
428
14
  case GIPFP_I64_Predicate_immZExt2Shift: {
429
0
    return Imm >= 1 && Imm <= 8;
430
14
    
llvm_unreachable0
("ImmediateCode should have returned");
431
14
    
return false0
;
432
14
  }
433
14
  case GIPFP_I64_Predicate_immZExt3: {
434
0
    return isUInt<3>(Imm);
435
14
    
llvm_unreachable0
("ImmediateCode should have returned");
436
14
    
return false0
;
437
14
  }
438
14
  case GIPFP_I64_Predicate_immZExt3Ptr: {
439
0
    return isUInt<3>(Imm);
440
14
    
llvm_unreachable0
("ImmediateCode should have returned");
441
14
    
return false0
;
442
14
  }
443
14
  case GIPFP_I64_Predicate_immZExt4: {
444
0
    return isUInt<4>(Imm);
445
14
    
llvm_unreachable0
("ImmediateCode should have returned");
446
14
    
return false0
;
447
14
  }
448
14
  case GIPFP_I64_Predicate_immZExt4Ptr: {
449
0
    return isUInt<4>(Imm);
450
14
    
llvm_unreachable0
("ImmediateCode should have returned");
451
14
    
return false0
;
452
14
  }
453
14
  case GIPFP_I64_Predicate_immZExt5: {
454
14
    return Imm == (Imm & 0x1f);
455
14
    
llvm_unreachable0
("ImmediateCode should have returned");
456
14
    
return false0
;
457
14
  }
458
14
  case GIPFP_I64_Predicate_immZExt5_64: {
459
0
     return Imm == (Imm & 0x1f); 
460
14
    
llvm_unreachable0
("ImmediateCode should have returned");
461
14
    
return false0
;
462
14
  }
463
14
  case GIPFP_I64_Predicate_immZExt6: {
464
0
    return Imm == (Imm & 0x3f);
465
14
    
llvm_unreachable0
("ImmediateCode should have returned");
466
14
    
return false0
;
467
14
  }
468
14
  case GIPFP_I64_Predicate_immZExt8: {
469
0
    return isUInt<8>(Imm);
470
14
    
llvm_unreachable0
("ImmediateCode should have returned");
471
14
    
return false0
;
472
14
  }
473
14
  case GIPFP_I64_Predicate_immZExtAndi16: {
474
0
    return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
475
0
            Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
476
0
            Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
477
14
    
llvm_unreachable0
("ImmediateCode should have returned");
478
14
    
return false0
;
479
14
  }
480
14
  case GIPFP_I64_Predicate_immi32Cst15: {
481
0
    return isUInt<32>(Imm) && Imm == 15;
482
14
    
llvm_unreachable0
("ImmediateCode should have returned");
483
14
    
return false0
;
484
14
  }
485
14
  case GIPFP_I64_Predicate_immi32Cst31: {
486
0
    return isUInt<32>(Imm) && Imm == 31;
487
14
    
llvm_unreachable0
("ImmediateCode should have returned");
488
14
    
return false0
;
489
14
  }
490
14
  case GIPFP_I64_Predicate_immi32Cst7: {
491
0
    return isUInt<32>(Imm) && Imm == 7;
492
14
    
llvm_unreachable0
("ImmediateCode should have returned");
493
14
    
return false0
;
494
0
  }
495
0
  }
496
0
  llvm_unreachable("Unknown predicate");
497
0
  return false;
498
0
}
499
0
bool MipsInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
500
0
  llvm_unreachable("Unknown predicate");
501
0
  return false;
502
0
}
503
0
bool MipsInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
504
0
  llvm_unreachable("Unknown predicate");
505
0
  return false;
506
0
}
507
0
bool MipsInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
508
0
  const MachineFunction &MF = *MI.getParent()->getParent();
509
0
  const MachineRegisterInfo &MRI = MF.getRegInfo();
510
0
  (void)MRI;
511
0
  llvm_unreachable("Unknown predicate");
512
0
  return false;
513
0
}
514
515
MipsInstructionSelector::ComplexMatcherMemFn
516
MipsInstructionSelector::ComplexPredicateFns[] = {
517
  nullptr, // GICP_Invalid
518
};
519
520
// Custom renderers.
521
enum {
522
  GICR_Invalid,
523
};
524
MipsInstructionSelector::CustomRendererFn
525
MipsInstructionSelector::CustomRenderers[] = {
526
  nullptr, // GICP_Invalid
527
};
528
529
144
bool MipsInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
530
144
  MachineFunction &MF = *I.getParent()->getParent();
531
144
  MachineRegisterInfo &MRI = MF.getRegInfo();
532
144
  // FIXME: This should be computed on a per-function basis rather than per-insn.
533
144
  AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
534
144
  const PredicateBitset AvailableFeatures = getAvailableFeatures();
535
144
  NewMIVector OutMIs;
536
144
  State.MIs.clear();
537
144
  State.MIs.push_back(&I);
538
144
539
144
  if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
540
64
    return true;
541
64
  }
542
80
543
80
  return false;
544
80
}
545
546
144
const int64_t *MipsInstructionSelector::getMatchTable() const {
547
144
  constexpr static int64_t MatchTable0[] = {
548
144
    GIM_SwitchOpcode, /*MI*/0, /*[*/34, 135, /*)*//*default:*//*Label 42*/ 38274,
549
144
    /*TargetOpcode::G_ADD*//*Label 0*/ 106,
550
144
    /*TargetOpcode::G_SUB*//*Label 1*/ 1283,
551
144
    /*TargetOpcode::G_MUL*//*Label 2*/ 1895,
552
144
    /*TargetOpcode::G_SDIV*//*Label 3*/ 2271,
553
144
    /*TargetOpcode::G_UDIV*//*Label 4*/ 2492,
554
144
    /*TargetOpcode::G_SREM*//*Label 5*/ 2713,
555
144
    /*TargetOpcode::G_UREM*//*Label 6*/ 2934,
556
144
    /*TargetOpcode::G_AND*//*Label 7*/ 3155,
557
144
    /*TargetOpcode::G_OR*//*Label 8*/ 3599,
558
144
    /*TargetOpcode::G_XOR*//*Label 9*/ 3901, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
559
144
    /*TargetOpcode::G_BITCAST*//*Label 10*/ 4695, 0, 0,
560
144
    /*TargetOpcode::G_LOAD*//*Label 11*/ 8348,
561
144
    /*TargetOpcode::G_SEXTLOAD*//*Label 12*/ 8414,
562
144
    /*TargetOpcode::G_ZEXTLOAD*//*Label 13*/ 8480, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
563
144
    /*TargetOpcode::G_INTRINSIC*//*Label 14*/ 8546,
564
144
    /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 15*/ 25057, 0,
565
144
    /*TargetOpcode::G_TRUNC*//*Label 16*/ 29981,
566
144
    /*TargetOpcode::G_CONSTANT*//*Label 17*/ 30038, 0, 0, 0,
567
144
    /*TargetOpcode::G_SEXT*//*Label 18*/ 30098,
568
144
    /*TargetOpcode::G_ZEXT*//*Label 19*/ 30126,
569
144
    /*TargetOpcode::G_SHL*//*Label 20*/ 30211,
570
144
    /*TargetOpcode::G_LSHR*//*Label 21*/ 30735,
571
144
    /*TargetOpcode::G_ASHR*//*Label 22*/ 31259, 0, 0,
572
144
    /*TargetOpcode::G_SELECT*//*Label 23*/ 31740, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
573
144
    /*TargetOpcode::G_FADD*//*Label 24*/ 33194,
574
144
    /*TargetOpcode::G_FSUB*//*Label 25*/ 34073,
575
144
    /*TargetOpcode::G_FMUL*//*Label 26*/ 34649,
576
144
    /*TargetOpcode::G_FMA*//*Label 27*/ 35086,
577
144
    /*TargetOpcode::G_FDIV*//*Label 28*/ 35176, 0, 0, 0,
578
144
    /*TargetOpcode::G_FEXP2*//*Label 29*/ 35427, 0,
579
144
    /*TargetOpcode::G_FLOG2*//*Label 30*/ 35485,
580
144
    /*TargetOpcode::G_FNEG*//*Label 31*/ 35543,
581
144
    /*TargetOpcode::G_FPEXT*//*Label 32*/ 36839,
582
144
    /*TargetOpcode::G_FPTRUNC*//*Label 33*/ 36988,
583
144
    /*TargetOpcode::G_FPTOSI*//*Label 34*/ 37116,
584
144
    /*TargetOpcode::G_FPTOUI*//*Label 35*/ 37174,
585
144
    /*TargetOpcode::G_SITOFP*//*Label 36*/ 37232,
586
144
    /*TargetOpcode::G_UITOFP*//*Label 37*/ 37385, 0, 0, 0,
587
144
    /*TargetOpcode::G_BR*//*Label 38*/ 37443, 0, 0, 0, 0, 0,
588
144
    /*TargetOpcode::G_CTLZ*//*Label 39*/ 37528, 0,
589
144
    /*TargetOpcode::G_CTPOP*//*Label 40*/ 37963,
590
144
    /*TargetOpcode::G_BSWAP*//*Label 41*/ 38122,
591
144
    // Label 0: @106
592
144
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 51*/ 1282,
593
144
    /*GILLT_s32*//*Label 43*/ 120,
594
144
    /*GILLT_s64*//*Label 44*/ 469,
595
144
    /*GILLT_v2s16*//*Label 45*/ 632,
596
144
    /*GILLT_v2s64*//*Label 46*/ 659,
597
144
    /*GILLT_v4s8*//*Label 47*/ 808,
598
144
    /*GILLT_v4s32*//*Label 48*/ 835,
599
144
    /*GILLT_v8s16*//*Label 49*/ 984,
600
144
    /*GILLT_v16s8*//*Label 50*/ 1133,
601
144
    // Label 43: @120
602
144
    GIM_Try, /*On fail goto*//*Label 52*/ 468,
603
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
604
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
605
144
      GIM_Try, /*On fail goto*//*Label 53*/ 198, // Rule ID 2310 //
606
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
607
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
608
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
609
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
610
144
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
611
144
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
612
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
613
144
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
614
144
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
615
144
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
616
144
        // MIs[2] Operand 1
617
144
        // No operand predicates
618
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
619
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
620
144
        GIM_CheckIsSafeToFold, /*InsnID*/2,
621
144
        // (add:{ *:[i32] } (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR32Opnd:{ *:[i32] }:$rt)  =>  (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
622
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA,
623
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
624
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
625
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
626
144
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
627
144
        GIR_EraseFromParent, /*InsnID*/0,
628
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
629
144
        // GIR_Coverage, 2310,
630
144
        GIR_Done,
631
144
      // Label 53: @198
632
144
      GIM_Try, /*On fail goto*//*Label 54*/ 266, // Rule ID 802 //
633
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
634
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
635
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
636
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
637
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
638
144
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
639
144
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
640
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
641
144
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
642
144
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
643
144
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
644
144
        // MIs[2] Operand 1
645
144
        // No operand predicates
646
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
647
144
        GIM_CheckIsSafeToFold, /*InsnID*/2,
648
144
        // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa))  =>  (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
649
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA,
650
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
651
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
652
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
653
144
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
654
144
        GIR_EraseFromParent, /*InsnID*/0,
655
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
656
144
        // GIR_Coverage, 802,
657
144
        GIR_Done,
658
144
      // Label 54: @266
659
144
      GIM_Try, /*On fail goto*//*Label 55*/ 309, // Rule ID 2084 //
660
144
        GIM_CheckFeatures, GIFBS_InMicroMips,
661
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
662
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
663
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
664
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
665
144
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExtAddiur2,
666
144
        // MIs[1] Operand 1
667
144
        // No operand predicates
668
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
669
144
        // (add:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)  =>  (ADDIUR2_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)
670
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUR2_MM,
671
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
672
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
673
144
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
674
144
        GIR_EraseFromParent, /*InsnID*/0,
675
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
676
144
        // GIR_Coverage, 2084,
677
144
        GIR_Done,
678
144
      // Label 55: @309
679
144
      GIM_Try, /*On fail goto*//*Label 56*/ 352, // Rule ID 2085 //
680
144
        GIM_CheckFeatures, GIFBS_InMicroMips,
681
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
682
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
683
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
684
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
685
144
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExtAddius5,
686
144
        // MIs[1] Operand 1
687
144
        // No operand predicates
688
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
689
144
        // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)  =>  (ADDIUS5_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)
690
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUS5_MM,
691
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
692
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
693
144
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
694
144
        GIR_EraseFromParent, /*InsnID*/0,
695
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
696
144
        // GIR_Coverage, 2085,
697
144
        GIR_Done,
698
144
      // Label 56: @352
699
144
      GIM_Try, /*On fail goto*//*Label 57*/ 375, // Rule ID 1174 //
700
144
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
701
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
702
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
703
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
704
144
        // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (ADDU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
705
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU16_MMR6,
706
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
707
144
        // GIR_Coverage, 1174,
708
144
        GIR_Done,
709
144
      // Label 57: @375
710
144
      GIM_Try, /*On fail goto*//*Label 58*/ 398, // Rule ID 34 //
711
144
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
712
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
713
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
714
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
715
144
        // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
716
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDu,
717
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
718
144
        // GIR_Coverage, 34,
719
144
        GIR_Done,
720
144
      // Label 58: @398
721
144
      GIM_Try, /*On fail goto*//*Label 59*/ 421, // Rule ID 1028 //
722
144
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
723
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
724
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
725
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
726
144
        // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (ADDU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
727
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU16_MM,
728
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
729
144
        // GIR_Coverage, 1028,
730
144
        GIR_Done,
731
144
      // Label 59: @421
732
144
      GIM_Try, /*On fail goto*//*Label 60*/ 444, // Rule ID 1040 //
733
144
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
734
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
735
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
736
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
737
144
        // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
738
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDu_MM,
739
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
740
144
        // GIR_Coverage, 1040,
741
144
        GIR_Done,
742
144
      // Label 60: @444
743
144
      GIM_Try, /*On fail goto*//*Label 61*/ 467, // Rule ID 1745 //
744
144
        GIM_CheckFeatures, GIFBS_InMips16Mode,
745
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
746
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
747
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
748
144
        // (add:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (AdduRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
749
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AdduRxRyRz16,
750
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
751
144
        // GIR_Coverage, 1745,
752
144
        GIR_Done,
753
144
      // Label 61: @467
754
144
      GIM_Reject,
755
144
    // Label 52: @468
756
144
    GIM_Reject,
757
144
    // Label 44: @469
758
144
    GIM_Try, /*On fail goto*//*Label 62*/ 631,
759
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
760
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
761
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
762
144
      GIM_Try, /*On fail goto*//*Label 63*/ 547, // Rule ID 2311 //
763
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc,
764
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
765
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
766
144
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
767
144
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
768
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
769
144
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
770
144
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
771
144
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
772
144
        // MIs[2] Operand 1
773
144
        // No operand predicates
774
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
775
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
776
144
        GIM_CheckIsSafeToFold, /*InsnID*/2,
777
144
        // (add:{ *:[i64] } (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR64Opnd:{ *:[i64] }:$rt)  =>  (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
778
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA,
779
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
780
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
781
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
782
144
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
783
144
        GIR_EraseFromParent, /*InsnID*/0,
784
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
785
144
        // GIR_Coverage, 2311,
786
144
        GIR_Done,
787
144
      // Label 63: @547
788
144
      GIM_Try, /*On fail goto*//*Label 64*/ 611, // Rule ID 803 //
789
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc,
790
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
791
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
792
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
793
144
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
794
144
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
795
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
796
144
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
797
144
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
798
144
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
799
144
        // MIs[2] Operand 1
800
144
        // No operand predicates
801
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
802
144
        GIM_CheckIsSafeToFold, /*InsnID*/2,
803
144
        // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa))  =>  (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
804
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA,
805
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
806
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
807
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
808
144
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
809
144
        GIR_EraseFromParent, /*InsnID*/0,
810
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
811
144
        // GIR_Coverage, 803,
812
144
        GIR_Done,
813
144
      // Label 64: @611
814
144
      GIM_Try, /*On fail goto*//*Label 65*/ 630, // Rule ID 180 //
815
144
        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
816
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
817
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
818
144
        // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
819
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DADDu,
820
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
821
144
        // GIR_Coverage, 180,
822
144
        GIR_Done,
823
144
      // Label 65: @630
824
144
      GIM_Reject,
825
144
    // Label 62: @631
826
144
    GIM_Reject,
827
144
    // Label 45: @632
828
144
    GIM_Try, /*On fail goto*//*Label 66*/ 658, // Rule ID 1844 //
829
144
      GIM_CheckFeatures, GIFBS_HasDSP,
830
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
831
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
832
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
833
144
      // (add:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
834
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDQ_PH,
835
144
      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
836
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
837
144
      // GIR_Coverage, 1844,
838
144
      GIR_Done,
839
144
    // Label 66: @658
840
144
    GIM_Reject,
841
144
    // Label 46: @659
842
144
    GIM_Try, /*On fail goto*//*Label 67*/ 807,
843
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
844
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
845
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
846
144
      GIM_Try, /*On fail goto*//*Label 68*/ 730, // Rule ID 2315 //
847
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
848
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
849
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
850
144
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
851
144
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
852
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
853
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
854
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
855
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
856
144
        // (add:{ *:[v2i64] } (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt), MSA128DOpnd:{ *:[v2i64] }:$wd_in)  =>  (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
857
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D,
858
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
859
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
860
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
861
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
862
144
        GIR_EraseFromParent, /*InsnID*/0,
863
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
864
144
        // GIR_Coverage, 2315,
865
144
        GIR_Done,
866
144
      // Label 68: @730
867
144
      GIM_Try, /*On fail goto*//*Label 69*/ 787, // Rule ID 811 //
868
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
869
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
870
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
871
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
872
144
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
873
144
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
874
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
875
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
876
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
877
144
        // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt))  =>  (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
878
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D,
879
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
880
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
881
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
882
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
883
144
        GIR_EraseFromParent, /*InsnID*/0,
884
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
885
144
        // GIR_Coverage, 811,
886
144
        GIR_Done,
887
144
      // Label 69: @787
888
144
      GIM_Try, /*On fail goto*//*Label 70*/ 806, // Rule ID 478 //
889
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
890
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
891
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
892
144
        // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
893
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_D,
894
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
895
144
        // GIR_Coverage, 478,
896
144
        GIR_Done,
897
144
      // Label 70: @806
898
144
      GIM_Reject,
899
144
    // Label 67: @807
900
144
    GIM_Reject,
901
144
    // Label 47: @808
902
144
    GIM_Try, /*On fail goto*//*Label 71*/ 834, // Rule ID 1850 //
903
144
      GIM_CheckFeatures, GIFBS_HasDSP,
904
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
905
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
906
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
907
144
      // (add:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)  =>  (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
908
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU_QB,
909
144
      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
910
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
911
144
      // GIR_Coverage, 1850,
912
144
      GIR_Done,
913
144
    // Label 71: @834
914
144
    GIM_Reject,
915
144
    // Label 48: @835
916
144
    GIM_Try, /*On fail goto*//*Label 72*/ 983,
917
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
918
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
919
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
920
144
      GIM_Try, /*On fail goto*//*Label 73*/ 906, // Rule ID 2314 //
921
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
922
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
923
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
924
144
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
925
144
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
926
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
927
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
928
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
929
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
930
144
        // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt), MSA128WOpnd:{ *:[v4i32] }:$wd_in)  =>  (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
931
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W,
932
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
933
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
934
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
935
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
936
144
        GIR_EraseFromParent, /*InsnID*/0,
937
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
938
144
        // GIR_Coverage, 2314,
939
144
        GIR_Done,
940
144
      // Label 73: @906
941
144
      GIM_Try, /*On fail goto*//*Label 74*/ 963, // Rule ID 810 //
942
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
943
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
944
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
945
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
946
144
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
947
144
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
948
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
949
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
950
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
951
144
        // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt))  =>  (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
952
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W,
953
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
954
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
955
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
956
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
957
144
        GIR_EraseFromParent, /*InsnID*/0,
958
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
959
144
        // GIR_Coverage, 810,
960
144
        GIR_Done,
961
144
      // Label 74: @963
962
144
      GIM_Try, /*On fail goto*//*Label 75*/ 982, // Rule ID 477 //
963
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
964
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
965
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
966
144
        // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
967
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_W,
968
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
969
144
        // GIR_Coverage, 477,
970
144
        GIR_Done,
971
144
      // Label 75: @982
972
144
      GIM_Reject,
973
144
    // Label 72: @983
974
144
    GIM_Reject,
975
144
    // Label 49: @984
976
144
    GIM_Try, /*On fail goto*//*Label 76*/ 1132,
977
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
978
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
979
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
980
144
      GIM_Try, /*On fail goto*//*Label 77*/ 1055, // Rule ID 2313 //
981
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
982
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
983
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
984
144
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
985
144
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
986
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
987
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
988
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
989
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
990
144
        // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt), MSA128HOpnd:{ *:[v8i16] }:$wd_in)  =>  (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
991
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H,
992
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
993
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
994
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
995
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
996
144
        GIR_EraseFromParent, /*InsnID*/0,
997
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
998
144
        // GIR_Coverage, 2313,
999
144
        GIR_Done,
1000
144
      // Label 77: @1055
1001
144
      GIM_Try, /*On fail goto*//*Label 78*/ 1112, // Rule ID 809 //
1002
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1003
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1004
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1005
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1006
144
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1007
144
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1008
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1009
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1010
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1011
144
        // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt))  =>  (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1012
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H,
1013
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1014
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1015
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1016
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1017
144
        GIR_EraseFromParent, /*InsnID*/0,
1018
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1019
144
        // GIR_Coverage, 809,
1020
144
        GIR_Done,
1021
144
      // Label 78: @1112
1022
144
      GIM_Try, /*On fail goto*//*Label 79*/ 1131, // Rule ID 476 //
1023
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1024
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1025
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1026
144
        // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1027
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_H,
1028
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1029
144
        // GIR_Coverage, 476,
1030
144
        GIR_Done,
1031
144
      // Label 79: @1131
1032
144
      GIM_Reject,
1033
144
    // Label 76: @1132
1034
144
    GIM_Reject,
1035
144
    // Label 50: @1133
1036
144
    GIM_Try, /*On fail goto*//*Label 80*/ 1281,
1037
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1038
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1039
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1040
144
      GIM_Try, /*On fail goto*//*Label 81*/ 1204, // Rule ID 2312 //
1041
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1042
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1043
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1044
144
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1045
144
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1046
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1047
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1048
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1049
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1050
144
        // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt), MSA128BOpnd:{ *:[v16i8] }:$wd_in)  =>  (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1051
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B,
1052
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1053
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
1054
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1055
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1056
144
        GIR_EraseFromParent, /*InsnID*/0,
1057
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1058
144
        // GIR_Coverage, 2312,
1059
144
        GIR_Done,
1060
144
      // Label 81: @1204
1061
144
      GIM_Try, /*On fail goto*//*Label 82*/ 1261, // Rule ID 808 //
1062
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1063
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1064
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1065
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1066
144
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1067
144
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1068
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1069
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1070
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1071
144
        // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt))  =>  (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1072
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B,
1073
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1074
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1075
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1076
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1077
144
        GIR_EraseFromParent, /*InsnID*/0,
1078
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1079
144
        // GIR_Coverage, 808,
1080
144
        GIR_Done,
1081
144
      // Label 82: @1261
1082
144
      GIM_Try, /*On fail goto*//*Label 83*/ 1280, // Rule ID 475 //
1083
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1084
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1085
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1086
144
        // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1087
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_B,
1088
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1089
144
        // GIR_Coverage, 475,
1090
144
        GIR_Done,
1091
144
      // Label 83: @1280
1092
144
      GIM_Reject,
1093
144
    // Label 80: @1281
1094
144
    GIM_Reject,
1095
144
    // Label 51: @1282
1096
144
    GIM_Reject,
1097
144
    // Label 1: @1283
1098
144
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 92*/ 1894,
1099
144
    /*GILLT_s32*//*Label 84*/ 1297,
1100
144
    /*GILLT_s64*//*Label 85*/ 1456,
1101
144
    /*GILLT_v2s16*//*Label 86*/ 1488,
1102
144
    /*GILLT_v2s64*//*Label 87*/ 1515,
1103
144
    /*GILLT_v4s8*//*Label 88*/ 1603,
1104
144
    /*GILLT_v4s32*//*Label 89*/ 1630,
1105
144
    /*GILLT_v8s16*//*Label 90*/ 1718,
1106
144
    /*GILLT_v16s8*//*Label 91*/ 1806,
1107
144
    // Label 84: @1297
1108
144
    GIM_Try, /*On fail goto*//*Label 93*/ 1455,
1109
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1110
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1111
144
      GIM_Try, /*On fail goto*//*Label 94*/ 1339, // Rule ID 1744 //
1112
144
        GIM_CheckFeatures, GIFBS_InMips16Mode,
1113
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
1114
144
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
1115
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
1116
144
        // (sub:{ *:[i32] } 0:{ *:[i32] }, CPU16Regs:{ *:[i32] }:$r)  =>  (NegRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
1117
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NegRxRy16,
1118
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
1119
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // r
1120
144
        GIR_EraseFromParent, /*InsnID*/0,
1121
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1122
144
        // GIR_Coverage, 1744,
1123
144
        GIR_Done,
1124
144
      // Label 94: @1339
1125
144
      GIM_Try, /*On fail goto*//*Label 95*/ 1362, // Rule ID 1176 //
1126
144
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1127
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
1128
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
1129
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
1130
144
        // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (SUBU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1131
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU16_MMR6,
1132
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1133
144
        // GIR_Coverage, 1176,
1134
144
        GIR_Done,
1135
144
      // Label 95: @1362
1136
144
      GIM_Try, /*On fail goto*//*Label 96*/ 1385, // Rule ID 35 //
1137
144
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
1138
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1139
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1140
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1141
144
        // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1142
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBu,
1143
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1144
144
        // GIR_Coverage, 35,
1145
144
        GIR_Done,
1146
144
      // Label 96: @1385
1147
144
      GIM_Try, /*On fail goto*//*Label 97*/ 1408, // Rule ID 1032 //
1148
144
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
1149
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
1150
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
1151
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
1152
144
        // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (SUBU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1153
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU16_MM,
1154
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1155
144
        // GIR_Coverage, 1032,
1156
144
        GIR_Done,
1157
144
      // Label 97: @1408
1158
144
      GIM_Try, /*On fail goto*//*Label 98*/ 1431, // Rule ID 1041 //
1159
144
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
1160
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1161
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1162
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1163
144
        // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1164
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBu_MM,
1165
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1166
144
        // GIR_Coverage, 1041,
1167
144
        GIR_Done,
1168
144
      // Label 98: @1431
1169
144
      GIM_Try, /*On fail goto*//*Label 99*/ 1454, // Rule ID 1749 //
1170
144
        GIM_CheckFeatures, GIFBS_InMips16Mode,
1171
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
1172
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
1173
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
1174
144
        // (sub:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (SubuRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1175
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SubuRxRyRz16,
1176
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1177
144
        // GIR_Coverage, 1749,
1178
144
        GIR_Done,
1179
144
      // Label 99: @1454
1180
144
      GIM_Reject,
1181
144
    // Label 93: @1455
1182
144
    GIM_Reject,
1183
144
    // Label 85: @1456
1184
144
    GIM_Try, /*On fail goto*//*Label 100*/ 1487, // Rule ID 181 //
1185
144
      GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
1186
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1187
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1188
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1189
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1190
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1191
144
      // (sub:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DSUBu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1192
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSUBu,
1193
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1194
144
      // GIR_Coverage, 181,
1195
144
      GIR_Done,
1196
144
    // Label 100: @1487
1197
144
    GIM_Reject,
1198
144
    // Label 86: @1488
1199
144
    GIM_Try, /*On fail goto*//*Label 101*/ 1514, // Rule ID 1846 //
1200
144
      GIM_CheckFeatures, GIFBS_HasDSP,
1201
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1202
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
1203
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
1204
144
      // (sub:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1205
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBQ_PH,
1206
144
      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
1207
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1208
144
      // GIR_Coverage, 1846,
1209
144
      GIR_Done,
1210
144
    // Label 101: @1514
1211
144
    GIM_Reject,
1212
144
    // Label 87: @1515
1213
144
    GIM_Try, /*On fail goto*//*Label 102*/ 1602,
1214
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1215
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1216
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1217
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1218
144
      GIM_Try, /*On fail goto*//*Label 103*/ 1586, // Rule ID 867 //
1219
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1220
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1221
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1222
144
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
1223
144
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
1224
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1225
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1226
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1227
144
        // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt))  =>  (MSUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1228
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_D,
1229
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1230
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1231
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1232
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1233
144
        GIR_EraseFromParent, /*InsnID*/0,
1234
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1235
144
        // GIR_Coverage, 867,
1236
144
        GIR_Done,
1237
144
      // Label 103: @1586
1238
144
      GIM_Try, /*On fail goto*//*Label 104*/ 1601, // Rule ID 996 //
1239
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1240
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1241
144
        // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1242
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_D,
1243
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1244
144
        // GIR_Coverage, 996,
1245
144
        GIR_Done,
1246
144
      // Label 104: @1601
1247
144
      GIM_Reject,
1248
144
    // Label 102: @1602
1249
144
    GIM_Reject,
1250
144
    // Label 88: @1603
1251
144
    GIM_Try, /*On fail goto*//*Label 105*/ 1629, // Rule ID 1852 //
1252
144
      GIM_CheckFeatures, GIFBS_HasDSP,
1253
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
1254
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
1255
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
1256
144
      // (sub:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)  =>  (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
1257
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU_QB,
1258
144
      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
1259
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1260
144
      // GIR_Coverage, 1852,
1261
144
      GIR_Done,
1262
144
    // Label 105: @1629
1263
144
    GIM_Reject,
1264
144
    // Label 89: @1630
1265
144
    GIM_Try, /*On fail goto*//*Label 106*/ 1717,
1266
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1267
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1268
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1269
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1270
144
      GIM_Try, /*On fail goto*//*Label 107*/ 1701, // Rule ID 866 //
1271
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1272
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1273
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1274
144
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1275
144
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1276
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1277
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1278
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1279
144
        // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt))  =>  (MSUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1280
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_W,
1281
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1282
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1283
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1284
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1285
144
        GIR_EraseFromParent, /*InsnID*/0,
1286
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1287
144
        // GIR_Coverage, 866,
1288
144
        GIR_Done,
1289
144
      // Label 107: @1701
1290
144
      GIM_Try, /*On fail goto*//*Label 108*/ 1716, // Rule ID 995 //
1291
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1292
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1293
144
        // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1294
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_W,
1295
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1296
144
        // GIR_Coverage, 995,
1297
144
        GIR_Done,
1298
144
      // Label 108: @1716
1299
144
      GIM_Reject,
1300
144
    // Label 106: @1717
1301
144
    GIM_Reject,
1302
144
    // Label 90: @1718
1303
144
    GIM_Try, /*On fail goto*//*Label 109*/ 1805,
1304
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1305
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1306
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1307
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1308
144
      GIM_Try, /*On fail goto*//*Label 110*/ 1789, // Rule ID 865 //
1309
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1310
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1311
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1312
144
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1313
144
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1314
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1315
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1316
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1317
144
        // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt))  =>  (MSUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1318
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_H,
1319
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1320
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1321
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1322
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1323
144
        GIR_EraseFromParent, /*InsnID*/0,
1324
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1325
144
        // GIR_Coverage, 865,
1326
144
        GIR_Done,
1327
144
      // Label 110: @1789
1328
144
      GIM_Try, /*On fail goto*//*Label 111*/ 1804, // Rule ID 994 //
1329
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1330
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1331
144
        // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1332
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_H,
1333
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1334
144
        // GIR_Coverage, 994,
1335
144
        GIR_Done,
1336
144
      // Label 111: @1804
1337
144
      GIM_Reject,
1338
144
    // Label 109: @1805
1339
144
    GIM_Reject,
1340
144
    // Label 91: @1806
1341
144
    GIM_Try, /*On fail goto*//*Label 112*/ 1893,
1342
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1343
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1344
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1345
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1346
144
      GIM_Try, /*On fail goto*//*Label 113*/ 1877, // Rule ID 864 //
1347
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1348
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1349
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1350
144
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1351
144
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1352
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1353
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1354
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1355
144
        // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt))  =>  (MSUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1356
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_B,
1357
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1358
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1359
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1360
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1361
144
        GIR_EraseFromParent, /*InsnID*/0,
1362
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1363
144
        // GIR_Coverage, 864,
1364
144
        GIR_Done,
1365
144
      // Label 113: @1877
1366
144
      GIM_Try, /*On fail goto*//*Label 114*/ 1892, // Rule ID 993 //
1367
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1368
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1369
144
        // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1370
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_B,
1371
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1372
144
        // GIR_Coverage, 993,
1373
144
        GIR_Done,
1374
144
      // Label 114: @1892
1375
144
      GIM_Reject,
1376
144
    // Label 112: @1893
1377
144
    GIM_Reject,
1378
144
    // Label 92: @1894
1379
144
    GIM_Reject,
1380
144
    // Label 2: @1895
1381
144
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 122*/ 2270,
1382
144
    /*GILLT_s32*//*Label 115*/ 1909,
1383
144
    /*GILLT_s64*//*Label 116*/ 2054,
1384
144
    /*GILLT_v2s16*//*Label 117*/ 2115,
1385
144
    /*GILLT_v2s64*//*Label 118*/ 2142, 0,
1386
144
    /*GILLT_v4s32*//*Label 119*/ 2174,
1387
144
    /*GILLT_v8s16*//*Label 120*/ 2206,
1388
144
    /*GILLT_v16s8*//*Label 121*/ 2238,
1389
144
    // Label 115: @1909
1390
144
    GIM_Try, /*On fail goto*//*Label 123*/ 2053,
1391
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1392
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1393
144
      GIM_Try, /*On fail goto*//*Label 124*/ 1948, // Rule ID 36 //
1394
144
        GIM_CheckFeatures, GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
1395
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1396
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1397
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1398
144
        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1399
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL,
1400
144
        GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1401
144
        GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1402
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1403
144
        // GIR_Coverage, 36,
1404
144
        GIR_Done,
1405
144
      // Label 124: @1948
1406
144
      GIM_Try, /*On fail goto*//*Label 125*/ 1971, // Rule ID 304 //
1407
144
        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1408
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1409
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1410
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1411
144
        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1412
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_R6,
1413
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1414
144
        // GIR_Coverage, 304,
1415
144
        GIR_Done,
1416
144
      // Label 125: @1971
1417
144
      GIM_Try, /*On fail goto*//*Label 126*/ 2000, // Rule ID 1042 //
1418
144
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
1419
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1420
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1421
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1422
144
        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL_MM:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1423
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_MM,
1424
144
        GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1425
144
        GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1426
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1427
144
        // GIR_Coverage, 1042,
1428
144
        GIR_Done,
1429
144
      // Label 126: @2000
1430
144
      GIM_Try, /*On fail goto*//*Label 127*/ 2023, // Rule ID 1145 //
1431
144
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1432
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1433
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1434
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1435
144
        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1436
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_MMR6,
1437
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1438
144
        // GIR_Coverage, 1145,
1439
144
        GIR_Done,
1440
144
      // Label 127: @2023
1441
144
      GIM_Try, /*On fail goto*//*Label 128*/ 2052, // Rule ID 1747 //
1442
144
        GIM_CheckFeatures, GIFBS_InMips16Mode,
1443
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
1444
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
1445
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
1446
144
        // (mul:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (MultRxRyRz16:{ *:[i32] }:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1447
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MultRxRyRz16,
1448
144
        GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1449
144
        GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1450
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1451
144
        // GIR_Coverage, 1747,
1452
144
        GIR_Done,
1453
144
      // Label 128: @2052
1454
144
      GIM_Reject,
1455
144
    // Label 123: @2053
1456
144
    GIM_Reject,
1457
144
    // Label 116: @2054
1458
144
    GIM_Try, /*On fail goto*//*Label 129*/ 2114,
1459
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1460
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1461
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1462
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1463
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1464
144
      GIM_Try, /*On fail goto*//*Label 130*/ 2102, // Rule ID 246 //
1465
144
        GIM_CheckFeatures, GIFBS_HasCnMips,
1466
144
        // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMUL:{ *:[i64] }:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1467
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUL,
1468
144
        GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1469
144
        GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1470
144
        GIR_AddImplicitDef, /*InsnID*/0, Mips::P0,
1471
144
        GIR_AddImplicitDef, /*InsnID*/0, Mips::P1,
1472
144
        GIR_AddImplicitDef, /*InsnID*/0, Mips::P2,
1473
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1474
144
        // GIR_Coverage, 246,
1475
144
        GIR_Done,
1476
144
      // Label 130: @2102
1477
144
      GIM_Try, /*On fail goto*//*Label 131*/ 2113, // Rule ID 319 //
1478
144
        GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1479
144
        // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMUL_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1480
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUL_R6,
1481
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1482
144
        // GIR_Coverage, 319,
1483
144
        GIR_Done,
1484
144
      // Label 131: @2113
1485
144
      GIM_Reject,
1486
144
    // Label 129: @2114
1487
144
    GIM_Reject,
1488
144
    // Label 117: @2115
1489
144
    GIM_Try, /*On fail goto*//*Label 132*/ 2141, // Rule ID 1848 //
1490
144
      GIM_CheckFeatures, GIFBS_HasDSPR2,
1491
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1492
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
1493
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
1494
144
      // (mul:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1495
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_PH,
1496
144
      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag21,
1497
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1498
144
      // GIR_Coverage, 1848,
1499
144
      GIR_Done,
1500
144
    // Label 132: @2141
1501
144
    GIM_Reject,
1502
144
    // Label 118: @2142
1503
144
    GIM_Try, /*On fail goto*//*Label 133*/ 2173, // Rule ID 875 //
1504
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1505
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1506
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1507
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1508
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1509
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1510
144
      // (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MULV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1511
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_D,
1512
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1513
144
      // GIR_Coverage, 875,
1514
144
      GIR_Done,
1515
144
    // Label 133: @2173
1516
144
    GIM_Reject,
1517
144
    // Label 119: @2174
1518
144
    GIM_Try, /*On fail goto*//*Label 134*/ 2205, // Rule ID 874 //
1519
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1520
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1521
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1522
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1523
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1524
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1525
144
      // (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MULV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1526
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_W,
1527
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1528
144
      // GIR_Coverage, 874,
1529
144
      GIR_Done,
1530
144
    // Label 134: @2205
1531
144
    GIM_Reject,
1532
144
    // Label 120: @2206
1533
144
    GIM_Try, /*On fail goto*//*Label 135*/ 2237, // Rule ID 873 //
1534
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1535
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1536
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1537
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1538
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1539
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1540
144
      // (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MULV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1541
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_H,
1542
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1543
144
      // GIR_Coverage, 873,
1544
144
      GIR_Done,
1545
144
    // Label 135: @2237
1546
144
    GIM_Reject,
1547
144
    // Label 121: @2238
1548
144
    GIM_Try, /*On fail goto*//*Label 136*/ 2269, // Rule ID 872 //
1549
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1550
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1551
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1552
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1553
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1554
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1555
144
      // (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MULV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1556
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_B,
1557
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1558
144
      // GIR_Coverage, 872,
1559
144
      GIR_Done,
1560
144
    // Label 136: @2269
1561
144
    GIM_Reject,
1562
144
    // Label 122: @2270
1563
144
    GIM_Reject,
1564
144
    // Label 3: @2271
1565
144
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 143*/ 2491,
1566
144
    /*GILLT_s32*//*Label 137*/ 2285,
1567
144
    /*GILLT_s64*//*Label 138*/ 2331, 0,
1568
144
    /*GILLT_v2s64*//*Label 139*/ 2363, 0,
1569
144
    /*GILLT_v4s32*//*Label 140*/ 2395,
1570
144
    /*GILLT_v8s16*//*Label 141*/ 2427,
1571
144
    /*GILLT_v16s8*//*Label 142*/ 2459,
1572
144
    // Label 137: @2285
1573
144
    GIM_Try, /*On fail goto*//*Label 144*/ 2330,
1574
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1575
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1576
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1577
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1578
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1579
144
      GIM_Try, /*On fail goto*//*Label 145*/ 2318, // Rule ID 298 //
1580
144
        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1581
144
        // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1582
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV,
1583
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1584
144
        // GIR_Coverage, 298,
1585
144
        GIR_Done,
1586
144
      // Label 145: @2318
1587
144
      GIM_Try, /*On fail goto*//*Label 146*/ 2329, // Rule ID 1138 //
1588
144
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1589
144
        // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIV_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1590
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_MMR6,
1591
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1592
144
        // GIR_Coverage, 1138,
1593
144
        GIR_Done,
1594
144
      // Label 146: @2329
1595
144
      GIM_Reject,
1596
144
    // Label 144: @2330
1597
144
    GIM_Reject,
1598
144
    // Label 138: @2331
1599
144
    GIM_Try, /*On fail goto*//*Label 147*/ 2362, // Rule ID 313 //
1600
144
      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1601
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1602
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1603
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1604
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1605
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1606
144
      // (sdiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DDIV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1607
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DDIV,
1608
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1609
144
      // GIR_Coverage, 313,
1610
144
      GIR_Done,
1611
144
    // Label 147: @2362
1612
144
    GIM_Reject,
1613
144
    // Label 139: @2363
1614
144
    GIM_Try, /*On fail goto*//*Label 148*/ 2394, // Rule ID 615 //
1615
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1616
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1617
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1618
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1619
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1620
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1621
144
      // (sdiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (DIV_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1622
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_D,
1623
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1624
144
      // GIR_Coverage, 615,
1625
144
      GIR_Done,
1626
144
    // Label 148: @2394
1627
144
    GIM_Reject,
1628
144
    // Label 140: @2395
1629
144
    GIM_Try, /*On fail goto*//*Label 149*/ 2426, // Rule ID 614 //
1630
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1631
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1632
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1633
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1634
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1635
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1636
144
      // (sdiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DIV_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1637
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_W,
1638
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1639
144
      // GIR_Coverage, 614,
1640
144
      GIR_Done,
1641
144
    // Label 149: @2426
1642
144
    GIM_Reject,
1643
144
    // Label 141: @2427
1644
144
    GIM_Try, /*On fail goto*//*Label 150*/ 2458, // Rule ID 613 //
1645
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1646
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1647
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1648
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1649
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1650
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1651
144
      // (sdiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DIV_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1652
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_H,
1653
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1654
144
      // GIR_Coverage, 613,
1655
144
      GIR_Done,
1656
144
    // Label 150: @2458
1657
144
    GIM_Reject,
1658
144
    // Label 142: @2459
1659
144
    GIM_Try, /*On fail goto*//*Label 151*/ 2490, // Rule ID 612 //
1660
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1661
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1662
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1663
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1664
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1665
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1666
144
      // (sdiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DIV_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1667
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_B,
1668
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1669
144
      // GIR_Coverage, 612,
1670
144
      GIR_Done,
1671
144
    // Label 151: @2490
1672
144
    GIM_Reject,
1673
144
    // Label 143: @2491
1674
144
    GIM_Reject,
1675
144
    // Label 4: @2492
1676
144
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 158*/ 2712,
1677
144
    /*GILLT_s32*//*Label 152*/ 2506,
1678
144
    /*GILLT_s64*//*Label 153*/ 2552, 0,
1679
144
    /*GILLT_v2s64*//*Label 154*/ 2584, 0,
1680
144
    /*GILLT_v4s32*//*Label 155*/ 2616,
1681
144
    /*GILLT_v8s16*//*Label 156*/ 2648,
1682
144
    /*GILLT_v16s8*//*Label 157*/ 2680,
1683
144
    // Label 152: @2506
1684
144
    GIM_Try, /*On fail goto*//*Label 159*/ 2551,
1685
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1686
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1687
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1688
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1689
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1690
144
      GIM_Try, /*On fail goto*//*Label 160*/ 2539, // Rule ID 299 //
1691
144
        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1692
144
        // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIVU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1693
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIVU,
1694
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1695
144
        // GIR_Coverage, 299,
1696
144
        GIR_Done,
1697
144
      // Label 160: @2539
1698
144
      GIM_Try, /*On fail goto*//*Label 161*/ 2550, // Rule ID 1139 //
1699
144
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1700
144
        // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIVU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1701
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIVU_MMR6,
1702
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1703
144
        // GIR_Coverage, 1139,
1704
144
        GIR_Done,
1705
144
      // Label 161: @2550
1706
144
      GIM_Reject,
1707
144
    // Label 159: @2551
1708
144
    GIM_Reject,
1709
144
    // Label 153: @2552
1710
144
    GIM_Try, /*On fail goto*//*Label 162*/ 2583, // Rule ID 314 //
1711
144
      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1712
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1713
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1714
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1715
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1716
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1717
144
      // (udiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DDIVU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1718
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DDIVU,
1719
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1720
144
      // GIR_Coverage, 314,
1721
144
      GIR_Done,
1722
144
    // Label 162: @2583
1723
144
    GIM_Reject,
1724
144
    // Label 154: @2584
1725
144
    GIM_Try, /*On fail goto*//*Label 163*/ 2615, // Rule ID 619 //
1726
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1727
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1728
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1729
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1730
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1731
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1732
144
      // (udiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (DIV_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1733
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_D,
1734
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1735
144
      // GIR_Coverage, 619,
1736
144
      GIR_Done,
1737
144
    // Label 163: @2615
1738
144
    GIM_Reject,
1739
144
    // Label 155: @2616
1740
144
    GIM_Try, /*On fail goto*//*Label 164*/ 2647, // Rule ID 618 //
1741
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1742
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1743
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1744
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1745
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1746
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1747
144
      // (udiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DIV_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1748
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_W,
1749
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1750
144
      // GIR_Coverage, 618,
1751
144
      GIR_Done,
1752
144
    // Label 164: @2647
1753
144
    GIM_Reject,
1754
144
    // Label 156: @2648
1755
144
    GIM_Try, /*On fail goto*//*Label 165*/ 2679, // Rule ID 617 //
1756
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1757
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1758
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1759
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1760
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1761
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1762
144
      // (udiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DIV_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1763
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_H,
1764
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1765
144
      // GIR_Coverage, 617,
1766
144
      GIR_Done,
1767
144
    // Label 165: @2679
1768
144
    GIM_Reject,
1769
144
    // Label 157: @2680
1770
144
    GIM_Try, /*On fail goto*//*Label 166*/ 2711, // Rule ID 616 //
1771
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1772
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1773
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1774
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1775
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1776
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1777
144
      // (udiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DIV_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1778
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_B,
1779
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1780
144
      // GIR_Coverage, 616,
1781
144
      GIR_Done,
1782
144
    // Label 166: @2711
1783
144
    GIM_Reject,
1784
144
    // Label 158: @2712
1785
144
    GIM_Reject,
1786
144
    // Label 5: @2713
1787
144
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 173*/ 2933,
1788
144
    /*GILLT_s32*//*Label 167*/ 2727,
1789
144
    /*GILLT_s64*//*Label 168*/ 2773, 0,
1790
144
    /*GILLT_v2s64*//*Label 169*/ 2805, 0,
1791
144
    /*GILLT_v4s32*//*Label 170*/ 2837,
1792
144
    /*GILLT_v8s16*//*Label 171*/ 2869,
1793
144
    /*GILLT_v16s8*//*Label 172*/ 2901,
1794
144
    // Label 167: @2727
1795
144
    GIM_Try, /*On fail goto*//*Label 174*/ 2772,
1796
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1797
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1798
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1799
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1800
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1801
144
      GIM_Try, /*On fail goto*//*Label 175*/ 2760, // Rule ID 300 //
1802
144
        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1803
144
        // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MOD:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1804
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD,
1805
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1806
144
        // GIR_Coverage, 300,
1807
144
        GIR_Done,
1808
144
      // Label 175: @2760
1809
144
      GIM_Try, /*On fail goto*//*Label 176*/ 2771, // Rule ID 1143 //
1810
144
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1811
144
        // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MOD_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1812
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_MMR6,
1813
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1814
144
        // GIR_Coverage, 1143,
1815
144
        GIR_Done,
1816
144
      // Label 176: @2771
1817
144
      GIM_Reject,
1818
144
    // Label 174: @2772
1819
144
    GIM_Reject,
1820
144
    // Label 168: @2773
1821
144
    GIM_Try, /*On fail goto*//*Label 177*/ 2804, // Rule ID 315 //
1822
144
      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1823
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1824
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1825
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1826
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1827
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1828
144
      // (srem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMOD:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1829
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMOD,
1830
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1831
144
      // GIR_Coverage, 315,
1832
144
      GIR_Done,
1833
144
    // Label 177: @2804
1834
144
    GIM_Reject,
1835
144
    // Label 169: @2805
1836
144
    GIM_Try, /*On fail goto*//*Label 178*/ 2836, // Rule ID 855 //
1837
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1838
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1839
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1840
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1841
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1842
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1843
144
      // (srem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MOD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1844
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_D,
1845
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1846
144
      // GIR_Coverage, 855,
1847
144
      GIR_Done,
1848
144
    // Label 178: @2836
1849
144
    GIM_Reject,
1850
144
    // Label 170: @2837
1851
144
    GIM_Try, /*On fail goto*//*Label 179*/ 2868, // Rule ID 854 //
1852
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1853
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1854
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1855
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1856
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1857
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1858
144
      // (srem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MOD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1859
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_W,
1860
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1861
144
      // GIR_Coverage, 854,
1862
144
      GIR_Done,
1863
144
    // Label 179: @2868
1864
144
    GIM_Reject,
1865
144
    // Label 171: @2869
1866
144
    GIM_Try, /*On fail goto*//*Label 180*/ 2900, // Rule ID 853 //
1867
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1868
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1869
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1870
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1871
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1872
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1873
144
      // (srem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MOD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1874
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_H,
1875
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1876
144
      // GIR_Coverage, 853,
1877
144
      GIR_Done,
1878
144
    // Label 180: @2900
1879
144
    GIM_Reject,
1880
144
    // Label 172: @2901
1881
144
    GIM_Try, /*On fail goto*//*Label 181*/ 2932, // Rule ID 852 //
1882
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1883
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1884
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1885
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1886
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1887
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1888
144
      // (srem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MOD_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1889
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_B,
1890
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1891
144
      // GIR_Coverage, 852,
1892
144
      GIR_Done,
1893
144
    // Label 181: @2932
1894
144
    GIM_Reject,
1895
144
    // Label 173: @2933
1896
144
    GIM_Reject,
1897
144
    // Label 6: @2934
1898
144
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 188*/ 3154,
1899
144
    /*GILLT_s32*//*Label 182*/ 2948,
1900
144
    /*GILLT_s64*//*Label 183*/ 2994, 0,
1901
144
    /*GILLT_v2s64*//*Label 184*/ 3026, 0,
1902
144
    /*GILLT_v4s32*//*Label 185*/ 3058,
1903
144
    /*GILLT_v8s16*//*Label 186*/ 3090,
1904
144
    /*GILLT_v16s8*//*Label 187*/ 3122,
1905
144
    // Label 182: @2948
1906
144
    GIM_Try, /*On fail goto*//*Label 189*/ 2993,
1907
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1908
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1909
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1910
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1911
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1912
144
      GIM_Try, /*On fail goto*//*Label 190*/ 2981, // Rule ID 301 //
1913
144
        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1914
144
        // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MODU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1915
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MODU,
1916
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1917
144
        // GIR_Coverage, 301,
1918
144
        GIR_Done,
1919
144
      // Label 190: @2981
1920
144
      GIM_Try, /*On fail goto*//*Label 191*/ 2992, // Rule ID 1144 //
1921
144
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1922
144
        // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MODU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1923
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MODU_MMR6,
1924
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1925
144
        // GIR_Coverage, 1144,
1926
144
        GIR_Done,
1927
144
      // Label 191: @2992
1928
144
      GIM_Reject,
1929
144
    // Label 189: @2993
1930
144
    GIM_Reject,
1931
144
    // Label 183: @2994
1932
144
    GIM_Try, /*On fail goto*//*Label 192*/ 3025, // Rule ID 316 //
1933
144
      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1934
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1935
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1936
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1937
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1938
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1939
144
      // (urem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMODU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1940
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMODU,
1941
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1942
144
      // GIR_Coverage, 316,
1943
144
      GIR_Done,
1944
144
    // Label 192: @3025
1945
144
    GIM_Reject,
1946
144
    // Label 184: @3026
1947
144
    GIM_Try, /*On fail goto*//*Label 193*/ 3057, // Rule ID 859 //
1948
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1949
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1950
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1951
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1952
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1953
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1954
144
      // (urem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MOD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1955
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_D,
1956
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1957
144
      // GIR_Coverage, 859,
1958
144
      GIR_Done,
1959
144
    // Label 193: @3057
1960
144
    GIM_Reject,
1961
144
    // Label 185: @3058
1962
144
    GIM_Try, /*On fail goto*//*Label 194*/ 3089, // Rule ID 858 //
1963
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1964
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1965
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1966
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1967
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1968
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1969
144
      // (urem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MOD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1970
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_W,
1971
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1972
144
      // GIR_Coverage, 858,
1973
144
      GIR_Done,
1974
144
    // Label 194: @3089
1975
144
    GIM_Reject,
1976
144
    // Label 186: @3090
1977
144
    GIM_Try, /*On fail goto*//*Label 195*/ 3121, // Rule ID 857 //
1978
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1979
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1980
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1981
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1982
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1983
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1984
144
      // (urem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MOD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1985
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_H,
1986
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1987
144
      // GIR_Coverage, 857,
1988
144
      GIR_Done,
1989
144
    // Label 195: @3121
1990
144
    GIM_Reject,
1991
144
    // Label 187: @3122
1992
144
    GIM_Try, /*On fail goto*//*Label 196*/ 3153, // Rule ID 856 //
1993
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1994
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1995
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1996
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1997
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1998
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1999
144
      // (urem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MOD_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2000
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_B,
2001
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2002
144
      // GIR_Coverage, 856,
2003
144
      GIR_Done,
2004
144
    // Label 196: @3153
2005
144
    GIM_Reject,
2006
144
    // Label 188: @3154
2007
144
    GIM_Reject,
2008
144
    // Label 7: @3155
2009
144
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 203*/ 3598,
2010
144
    /*GILLT_s32*//*Label 197*/ 3169,
2011
144
    /*GILLT_s64*//*Label 198*/ 3382, 0,
2012
144
    /*GILLT_v2s64*//*Label 199*/ 3470, 0,
2013
144
    /*GILLT_v4s32*//*Label 200*/ 3502,
2014
144
    /*GILLT_v8s16*//*Label 201*/ 3534,
2015
144
    /*GILLT_v16s8*//*Label 202*/ 3566,
2016
144
    // Label 197: @3169
2017
144
    GIM_Try, /*On fail goto*//*Label 204*/ 3381,
2018
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2019
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2020
144
      GIM_Try, /*On fail goto*//*Label 205*/ 3222, // Rule ID 2087 //
2021
144
        GIM_CheckFeatures, GIFBS_InMicroMips,
2022
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2023
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2024
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2025
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2026
144
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExtAndi16,
2027
144
        // MIs[1] Operand 1
2028
144
        // No operand predicates
2029
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2030
144
        // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)  =>  (ANDI16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2031
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MM,
2032
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2033
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
2034
144
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2035
144
        GIR_EraseFromParent, /*InsnID*/0,
2036
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2037
144
        // GIR_Coverage, 2087,
2038
144
        GIR_Done,
2039
144
      // Label 205: @3222
2040
144
      GIM_Try, /*On fail goto*//*Label 206*/ 3265, // Rule ID 2241 //
2041
144
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2042
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2043
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2044
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2045
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2046
144
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExtAndi16,
2047
144
        // MIs[1] Operand 1
2048
144
        // No operand predicates
2049
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2050
144
        // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)  =>  (ANDI16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2051
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MMR6,
2052
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2053
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
2054
144
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2055
144
        GIR_EraseFromParent, /*InsnID*/0,
2056
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2057
144
        // GIR_Coverage, 2241,
2058
144
        GIR_Done,
2059
144
      // Label 206: @3265
2060
144
      GIM_Try, /*On fail goto*//*Label 207*/ 3288, // Rule ID 39 //
2061
144
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2062
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2063
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2064
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2065
144
        // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (AND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2066
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND,
2067
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2068
144
        // GIR_Coverage, 39,
2069
144
        GIR_Done,
2070
144
      // Label 207: @3288
2071
144
      GIM_Try, /*On fail goto*//*Label 208*/ 3311, // Rule ID 1029 //
2072
144
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2073
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2074
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2075
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
2076
144
        // (and:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (AND16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2077
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND16_MM,
2078
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2079
144
        // GIR_Coverage, 1029,
2080
144
        GIR_Done,
2081
144
      // Label 208: @3311
2082
144
      GIM_Try, /*On fail goto*//*Label 209*/ 3334, // Rule ID 1045 //
2083
144
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2084
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2085
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2086
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2087
144
        // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (AND_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2088
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_MM,
2089
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2090
144
        // GIR_Coverage, 1045,
2091
144
        GIR_Done,
2092
144
      // Label 209: @3334
2093
144
      GIM_Try, /*On fail goto*//*Label 210*/ 3357, // Rule ID 1136 //
2094
144
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2095
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2096
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2097
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2098
144
        // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (AND_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2099
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_MMR6,
2100
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2101
144
        // GIR_Coverage, 1136,
2102
144
        GIR_Done,
2103
144
      // Label 210: @3357
2104
144
      GIM_Try, /*On fail goto*//*Label 211*/ 3380, // Rule ID 1746 //
2105
144
        GIM_CheckFeatures, GIFBS_InMips16Mode,
2106
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2107
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2108
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
2109
144
        // (and:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (AndRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2110
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AndRxRxRy16,
2111
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2112
144
        // GIR_Coverage, 1746,
2113
144
        GIR_Done,
2114
144
      // Label 211: @3380
2115
144
      GIM_Reject,
2116
144
    // Label 204: @3381
2117
144
    GIM_Reject,
2118
144
    // Label 198: @3382
2119
144
    GIM_Try, /*On fail goto*//*Label 212*/ 3469,
2120
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2121
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2122
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2123
144
      GIM_Try, /*On fail goto*//*Label 213*/ 3449, // Rule ID 241 //
2124
144
        GIM_CheckFeatures, GIFBS_HasCnMips,
2125
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2126
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
2127
144
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2128
144
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2129
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2130
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2131
144
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
2132
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2133
144
        // (and:{ *:[i64] } (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), 255:{ *:[i64] })  =>  (BADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2134
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BADDu,
2135
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2136
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2137
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2138
144
        GIR_EraseFromParent, /*InsnID*/0,
2139
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2140
144
        // GIR_Coverage, 241,
2141
144
        GIR_Done,
2142
144
      // Label 213: @3449
2143
144
      GIM_Try, /*On fail goto*//*Label 214*/ 3468, // Rule ID 184 //
2144
144
        GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2145
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2146
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2147
144
        // (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (AND64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2148
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND64,
2149
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2150
144
        // GIR_Coverage, 184,
2151
144
        GIR_Done,
2152
144
      // Label 214: @3468
2153
144
      GIM_Reject,
2154
144
    // Label 212: @3469
2155
144
    GIM_Reject,
2156
144
    // Label 199: @3470
2157
144
    GIM_Try, /*On fail goto*//*Label 215*/ 3501, // Rule ID 486 //
2158
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2159
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2160
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2161
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2162
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
2163
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
2164
144
      // (and:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (AND_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2165
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_D_PSEUDO,
2166
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2167
144
      // GIR_Coverage, 486,
2168
144
      GIR_Done,
2169
144
    // Label 215: @3501
2170
144
    GIM_Reject,
2171
144
    // Label 200: @3502
2172
144
    GIM_Try, /*On fail goto*//*Label 216*/ 3533, // Rule ID 485 //
2173
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2174
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2175
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2176
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2177
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2178
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2179
144
      // (and:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (AND_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2180
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_W_PSEUDO,
2181
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2182
144
      // GIR_Coverage, 485,
2183
144
      GIR_Done,
2184
144
    // Label 216: @3533
2185
144
    GIM_Reject,
2186
144
    // Label 201: @3534
2187
144
    GIM_Try, /*On fail goto*//*Label 217*/ 3565, // Rule ID 484 //
2188
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2189
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2190
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2191
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2192
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2193
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2194
144
      // (and:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (AND_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2195
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_H_PSEUDO,
2196
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2197
144
      // GIR_Coverage, 484,
2198
144
      GIR_Done,
2199
144
    // Label 217: @3565
2200
144
    GIM_Reject,
2201
144
    // Label 202: @3566
2202
144
    GIM_Try, /*On fail goto*//*Label 218*/ 3597, // Rule ID 483 //
2203
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2204
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2205
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2206
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2207
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2208
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2209
144
      // (and:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (AND_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2210
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V,
2211
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2212
144
      // GIR_Coverage, 483,
2213
144
      GIR_Done,
2214
144
    // Label 218: @3597
2215
144
    GIM_Reject,
2216
144
    // Label 203: @3598
2217
144
    GIM_Reject,
2218
144
    // Label 8: @3599
2219
144
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 225*/ 3900,
2220
144
    /*GILLT_s32*//*Label 219*/ 3613,
2221
144
    /*GILLT_s64*//*Label 220*/ 3740, 0,
2222
144
    /*GILLT_v2s64*//*Label 221*/ 3772, 0,
2223
144
    /*GILLT_v4s32*//*Label 222*/ 3804,
2224
144
    /*GILLT_v8s16*//*Label 223*/ 3836,
2225
144
    /*GILLT_v16s8*//*Label 224*/ 3868,
2226
144
    // Label 219: @3613
2227
144
    GIM_Try, /*On fail goto*//*Label 226*/ 3739,
2228
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2229
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2230
144
      GIM_Try, /*On fail goto*//*Label 227*/ 3646, // Rule ID 40 //
2231
144
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2232
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2233
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2234
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2235
144
        // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (OR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2236
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR,
2237
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2238
144
        // GIR_Coverage, 40,
2239
144
        GIR_Done,
2240
144
      // Label 227: @3646
2241
144
      GIM_Try, /*On fail goto*//*Label 228*/ 3669, // Rule ID 1031 //
2242
144
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2243
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2244
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2245
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
2246
144
        // (or:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (OR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2247
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR16_MM,
2248
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2249
144
        // GIR_Coverage, 1031,
2250
144
        GIR_Done,
2251
144
      // Label 228: @3669
2252
144
      GIM_Try, /*On fail goto*//*Label 229*/ 3692, // Rule ID 1046 //
2253
144
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2254
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2255
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2256
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2257
144
        // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (OR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2258
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_MM,
2259
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2260
144
        // GIR_Coverage, 1046,
2261
144
        GIR_Done,
2262
144
      // Label 229: @3692
2263
144
      GIM_Try, /*On fail goto*//*Label 230*/ 3715, // Rule ID 1149 //
2264
144
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2265
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2266
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2267
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2268
144
        // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (OR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2269
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_MMR6,
2270
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2271
144
        // GIR_Coverage, 1149,
2272
144
        GIR_Done,
2273
144
      // Label 230: @3715
2274
144
      GIM_Try, /*On fail goto*//*Label 231*/ 3738, // Rule ID 1748 //
2275
144
        GIM_CheckFeatures, GIFBS_InMips16Mode,
2276
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2277
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2278
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
2279
144
        // (or:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (OrRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2280
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OrRxRxRy16,
2281
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2282
144
        // GIR_Coverage, 1748,
2283
144
        GIR_Done,
2284
144
      // Label 231: @3738
2285
144
      GIM_Reject,
2286
144
    // Label 226: @3739
2287
144
    GIM_Reject,
2288
144
    // Label 220: @3740
2289
144
    GIM_Try, /*On fail goto*//*Label 232*/ 3771, // Rule ID 185 //
2290
144
      GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2291
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2292
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2293
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2294
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2295
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2296
144
      // (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (OR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2297
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR64,
2298
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2299
144
      // GIR_Coverage, 185,
2300
144
      GIR_Done,
2301
144
    // Label 232: @3771
2302
144
    GIM_Reject,
2303
144
    // Label 221: @3772
2304
144
    GIM_Try, /*On fail goto*//*Label 233*/ 3803, // Rule ID 892 //
2305
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2306
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2307
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2308
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2309
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
2310
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
2311
144
      // (or:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (OR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2312
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_D_PSEUDO,
2313
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2314
144
      // GIR_Coverage, 892,
2315
144
      GIR_Done,
2316
144
    // Label 233: @3803
2317
144
    GIM_Reject,
2318
144
    // Label 222: @3804
2319
144
    GIM_Try, /*On fail goto*//*Label 234*/ 3835, // Rule ID 891 //
2320
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2321
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2322
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2323
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2324
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2325
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2326
144
      // (or:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (OR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2327
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_W_PSEUDO,
2328
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2329
144
      // GIR_Coverage, 891,
2330
144
      GIR_Done,
2331
144
    // Label 234: @3835
2332
144
    GIM_Reject,
2333
144
    // Label 223: @3836
2334
144
    GIM_Try, /*On fail goto*//*Label 235*/ 3867, // Rule ID 890 //
2335
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2336
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2337
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2338
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2339
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2340
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2341
144
      // (or:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (OR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2342
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_H_PSEUDO,
2343
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2344
144
      // GIR_Coverage, 890,
2345
144
      GIR_Done,
2346
144
    // Label 235: @3867
2347
144
    GIM_Reject,
2348
144
    // Label 224: @3868
2349
144
    GIM_Try, /*On fail goto*//*Label 236*/ 3899, // Rule ID 889 //
2350
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2351
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2352
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2353
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2354
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2355
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2356
144
      // (or:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (OR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2357
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V,
2358
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2359
144
      // GIR_Coverage, 889,
2360
144
      GIR_Done,
2361
144
    // Label 236: @3899
2362
144
    GIM_Reject,
2363
144
    // Label 225: @3900
2364
144
    GIM_Reject,
2365
144
    // Label 9: @3901
2366
144
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 243*/ 4694,
2367
144
    /*GILLT_s32*//*Label 237*/ 3915,
2368
144
    /*GILLT_s64*//*Label 238*/ 4478, 0,
2369
144
    /*GILLT_v2s64*//*Label 239*/ 4566, 0,
2370
144
    /*GILLT_v4s32*//*Label 240*/ 4598,
2371
144
    /*GILLT_v8s16*//*Label 241*/ 4630,
2372
144
    /*GILLT_v16s8*//*Label 242*/ 4662,
2373
144
    // Label 237: @3915
2374
144
    GIM_Try, /*On fail goto*//*Label 244*/ 4477,
2375
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2376
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2377
144
      GIM_Try, /*On fail goto*//*Label 245*/ 3982, // Rule ID 42 //
2378
144
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2379
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2380
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2381
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2382
144
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2383
144
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2384
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2385
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2386
144
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2387
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2388
144
        // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] })  =>  (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2389
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
2390
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2391
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2392
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2393
144
        GIR_EraseFromParent, /*InsnID*/0,
2394
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2395
144
        // GIR_Coverage, 42,
2396
144
        GIR_Done,
2397
144
      // Label 245: @3982
2398
144
      GIM_Try, /*On fail goto*//*Label 246*/ 4039, // Rule ID 1048 //
2399
144
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2400
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2401
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2402
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2403
144
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2404
144
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2405
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2406
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2407
144
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2408
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2409
144
        // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] })  =>  (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2410
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MM,
2411
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2412
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2413
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2414
144
        GIR_EraseFromParent, /*InsnID*/0,
2415
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2416
144
        // GIR_Coverage, 1048,
2417
144
        GIR_Done,
2418
144
      // Label 246: @4039
2419
144
      GIM_Try, /*On fail goto*//*Label 247*/ 4096, // Rule ID 1148 //
2420
144
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2421
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2422
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2423
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2424
144
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2425
144
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2426
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2427
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2428
144
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2429
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2430
144
        // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] })  =>  (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2431
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
2432
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2433
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2434
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2435
144
        GIR_EraseFromParent, /*InsnID*/0,
2436
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2437
144
        // GIR_Coverage, 1148,
2438
144
        GIR_Done,
2439
144
      // Label 247: @4096
2440
144
      GIM_Try, /*On fail goto*//*Label 248*/ 4128, // Rule ID 1175 //
2441
144
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2442
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2443
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2444
144
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2445
144
        // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })  =>  (NOT16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2446
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MMR6,
2447
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2448
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
2449
144
        GIR_EraseFromParent, /*InsnID*/0,
2450
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2451
144
        // GIR_Coverage, 1175,
2452
144
        GIR_Done,
2453
144
      // Label 248: @4128
2454
144
      GIM_Try, /*On fail goto*//*Label 249*/ 4160, // Rule ID 1030 //
2455
144
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2456
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2457
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2458
144
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2459
144
        // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })  =>  (NOT16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2460
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MM,
2461
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2462
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
2463
144
        GIR_EraseFromParent, /*InsnID*/0,
2464
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2465
144
        // GIR_Coverage, 1030,
2466
144
        GIR_Done,
2467
144
      // Label 249: @4160
2468
144
      GIM_Try, /*On fail goto*//*Label 250*/ 4195, // Rule ID 1362 //
2469
144
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2470
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2471
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2472
144
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2473
144
        // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2474
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
2475
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2476
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2477
144
        GIR_AddRegister, /*InsnID*/0, Mips::ZERO,
2478
144
        GIR_EraseFromParent, /*InsnID*/0,
2479
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2480
144
        // GIR_Coverage, 1362,
2481
144
        GIR_Done,
2482
144
      // Label 250: @4195
2483
144
      GIM_Try, /*On fail goto*//*Label 251*/ 4227, // Rule ID 1743 //
2484
144
        GIM_CheckFeatures, GIFBS_InMips16Mode,
2485
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2486
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2487
144
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2488
144
        // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, -1:{ *:[i32] })  =>  (NotRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
2489
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NotRxRy16,
2490
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
2491
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // r
2492
144
        GIR_EraseFromParent, /*InsnID*/0,
2493
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2494
144
        // GIR_Coverage, 1743,
2495
144
        GIR_Done,
2496
144
      // Label 251: @4227
2497
144
      GIM_Try, /*On fail goto*//*Label 252*/ 4259, // Rule ID 2082 //
2498
144
        GIM_CheckFeatures, GIFBS_InMicroMips,
2499
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2500
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2501
144
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2502
144
        // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOT16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2503
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MM,
2504
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2505
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2506
144
        GIR_EraseFromParent, /*InsnID*/0,
2507
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2508
144
        // GIR_Coverage, 2082,
2509
144
        GIR_Done,
2510
144
      // Label 252: @4259
2511
144
      GIM_Try, /*On fail goto*//*Label 253*/ 4294, // Rule ID 2083 //
2512
144
        GIM_CheckFeatures, GIFBS_InMicroMips,
2513
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2514
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2515
144
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2516
144
        // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2517
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MM,
2518
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2519
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2520
144
        GIR_AddRegister, /*InsnID*/0, Mips::ZERO,
2521
144
        GIR_EraseFromParent, /*InsnID*/0,
2522
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2523
144
        // GIR_Coverage, 2083,
2524
144
        GIR_Done,
2525
144
      // Label 253: @4294
2526
144
      GIM_Try, /*On fail goto*//*Label 254*/ 4326, // Rule ID 2244 //
2527
144
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2528
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2529
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2530
144
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2531
144
        // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOT16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2532
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MMR6,
2533
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2534
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2535
144
        GIR_EraseFromParent, /*InsnID*/0,
2536
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2537
144
        // GIR_Coverage, 2244,
2538
144
        GIR_Done,
2539
144
      // Label 254: @4326
2540
144
      GIM_Try, /*On fail goto*//*Label 255*/ 4361, // Rule ID 2245 //
2541
144
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2542
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2543
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2544
144
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2545
144
        // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2546
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
2547
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2548
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2549
144
        GIR_AddRegister, /*InsnID*/0, Mips::ZERO,
2550
144
        GIR_EraseFromParent, /*InsnID*/0,
2551
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2552
144
        // GIR_Coverage, 2245,
2553
144
        GIR_Done,
2554
144
      // Label 255: @4361
2555
144
      GIM_Try, /*On fail goto*//*Label 256*/ 4384, // Rule ID 41 //
2556
144
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2557
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2558
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2559
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2560
144
        // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (XOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2561
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR,
2562
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2563
144
        // GIR_Coverage, 41,
2564
144
        GIR_Done,
2565
144
      // Label 256: @4384
2566
144
      GIM_Try, /*On fail goto*//*Label 257*/ 4407, // Rule ID 1033 //
2567
144
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2568
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2569
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2570
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
2571
144
        // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (XOR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2572
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR16_MM,
2573
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2574
144
        // GIR_Coverage, 1033,
2575
144
        GIR_Done,
2576
144
      // Label 257: @4407
2577
144
      GIM_Try, /*On fail goto*//*Label 258*/ 4430, // Rule ID 1047 //
2578
144
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2579
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2580
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2581
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2582
144
        // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (XOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2583
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_MM,
2584
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2585
144
        // GIR_Coverage, 1047,
2586
144
        GIR_Done,
2587
144
      // Label 258: @4430
2588
144
      GIM_Try, /*On fail goto*//*Label 259*/ 4453, // Rule ID 1152 //
2589
144
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2590
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2591
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2592
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2593
144
        // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (XOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2594
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_MMR6,
2595
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2596
144
        // GIR_Coverage, 1152,
2597
144
        GIR_Done,
2598
144
      // Label 259: @4453
2599
144
      GIM_Try, /*On fail goto*//*Label 260*/ 4476, // Rule ID 1750 //
2600
144
        GIM_CheckFeatures, GIFBS_InMips16Mode,
2601
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2602
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2603
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
2604
144
        // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2605
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XorRxRxRy16,
2606
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2607
144
        // GIR_Coverage, 1750,
2608
144
        GIR_Done,
2609
144
      // Label 260: @4476
2610
144
      GIM_Reject,
2611
144
    // Label 244: @4477
2612
144
    GIM_Reject,
2613
144
    // Label 238: @4478
2614
144
    GIM_Try, /*On fail goto*//*Label 261*/ 4565,
2615
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2616
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2617
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2618
144
      GIM_Try, /*On fail goto*//*Label 262*/ 4545, // Rule ID 187 //
2619
144
        GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2620
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2621
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2622
144
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2623
144
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2624
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2625
144
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2626
144
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2627
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2628
144
        // (xor:{ *:[i64] } (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), -1:{ *:[i64] })  =>  (NOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2629
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR64,
2630
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2631
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2632
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2633
144
        GIR_EraseFromParent, /*InsnID*/0,
2634
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2635
144
        // GIR_Coverage, 187,
2636
144
        GIR_Done,
2637
144
      // Label 262: @4545
2638
144
      GIM_Try, /*On fail goto*//*Label 263*/ 4564, // Rule ID 186 //
2639
144
        GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2640
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2641
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2642
144
        // (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (XOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2643
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR64,
2644
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2645
144
        // GIR_Coverage, 186,
2646
144
        GIR_Done,
2647
144
      // Label 263: @4564
2648
144
      GIM_Reject,
2649
144
    // Label 261: @4565
2650
144
    GIM_Reject,
2651
144
    // Label 239: @4566
2652
144
    GIM_Try, /*On fail goto*//*Label 264*/ 4597, // Rule ID 1008 //
2653
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2654
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2655
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2656
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2657
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
2658
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
2659
144
      // (xor:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (XOR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2660
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_D_PSEUDO,
2661
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2662
144
      // GIR_Coverage, 1008,
2663
144
      GIR_Done,
2664
144
    // Label 264: @4597
2665
144
    GIM_Reject,
2666
144
    // Label 240: @4598
2667
144
    GIM_Try, /*On fail goto*//*Label 265*/ 4629, // Rule ID 1007 //
2668
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2669
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2670
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2671
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2672
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2673
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2674
144
      // (xor:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (XOR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2675
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_W_PSEUDO,
2676
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2677
144
      // GIR_Coverage, 1007,
2678
144
      GIR_Done,
2679
144
    // Label 265: @4629
2680
144
    GIM_Reject,
2681
144
    // Label 241: @4630
2682
144
    GIM_Try, /*On fail goto*//*Label 266*/ 4661, // Rule ID 1006 //
2683
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2684
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2685
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2686
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2687
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2688
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2689
144
      // (xor:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (XOR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2690
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_H_PSEUDO,
2691
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2692
144
      // GIR_Coverage, 1006,
2693
144
      GIR_Done,
2694
144
    // Label 266: @4661
2695
144
    GIM_Reject,
2696
144
    // Label 242: @4662
2697
144
    GIM_Try, /*On fail goto*//*Label 267*/ 4693, // Rule ID 1005 //
2698
144
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2699
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2700
144
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2701
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2702
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2703
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2704
144
      // (xor:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (XOR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2705
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V,
2706
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2707
144
      // GIR_Coverage, 1005,
2708
144
      GIR_Done,
2709
144
    // Label 267: @4693
2710
144
    GIM_Reject,
2711
144
    // Label 243: @4694
2712
144
    GIM_Reject,
2713
144
    // Label 10: @4695
2714
144
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 276*/ 8347,
2715
144
    /*GILLT_s32*//*Label 268*/ 4709,
2716
144
    /*GILLT_s64*//*Label 269*/ 4948,
2717
144
    /*GILLT_v2s16*//*Label 270*/ 4994,
2718
144
    /*GILLT_v2s64*//*Label 271*/ 5040,
2719
144
    /*GILLT_v4s8*//*Label 272*/ 6013,
2720
144
    /*GILLT_v4s32*//*Label 273*/ 6059,
2721
144
    /*GILLT_v8s16*//*Label 274*/ 6962,
2722
144
    /*GILLT_v16s8*//*Label 275*/ 7760,
2723
144
    // Label 268: @4709
2724
144
    GIM_Try, /*On fail goto*//*Label 277*/ 4732, // Rule ID 117 //
2725
144
      GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
2726
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2727
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2728
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
2729
144
      // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (MFC1:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
2730
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1,
2731
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2732
144
      // GIR_Coverage, 117,
2733
144
      GIR_Done,
2734
144
    // Label 277: @4732
2735
144
    GIM_Try, /*On fail goto*//*Label 278*/ 4755, // Rule ID 118 //
2736
144
      GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
2737
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2738
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2739
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2740
144
      // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)  =>  (MTC1:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
2741
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1,
2742
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2743
144
      // GIR_Coverage, 118,
2744
144
      GIR_Done,
2745
144
    // Label 278: @4755
2746
144
    GIM_Try, /*On fail goto*//*Label 279*/ 4778, // Rule ID 1128 //
2747
144
      GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
2748
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2749
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2750
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
2751
144
      // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (MFC1_MM:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
2752
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1_MM,
2753
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2754
144
      // GIR_Coverage, 1128,
2755
144
      GIR_Done,
2756
144
    // Label 279: @4778
2757
144
    GIM_Try, /*On fail goto*//*Label 280*/ 4801, // Rule ID 1129 //
2758
144
      GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
2759
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2760
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2761
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2762
144
      // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)  =>  (MTC1_MM:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
2763
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1_MM,
2764
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2765
144
      // GIR_Coverage, 1129,
2766
144
      GIR_Done,
2767
144
    // Label 280: @4801
2768
144
    GIM_Try, /*On fail goto*//*Label 281*/ 4824, // Rule ID 1141 //
2769
144
      GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
2770
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2771
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2772
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2773
144
      // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)  =>  (MTC1_MMR6:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
2774
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1_MMR6,
2775
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2776
144
      // GIR_Coverage, 1141,
2777
144
      GIR_Done,
2778
144
    // Label 281: @4824
2779
144
    GIM_Try, /*On fail goto*//*Label 282*/ 4847, // Rule ID 1142 //
2780
144
      GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
2781
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2782
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2783
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
2784
144
      // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (MFC1_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
2785
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1_MMR6,
2786
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2787
144
      // GIR_Coverage, 1142,
2788
144
      GIR_Done,
2789
144
    // Label 282: @4847
2790
144
    GIM_Try, /*On fail goto*//*Label 283*/ 4872, // Rule ID 1831 //
2791
144
      GIM_CheckFeatures, GIFBS_HasDSP,
2792
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
2793
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2794
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
2795
144
      // (bitconvert:{ *:[i32] } DSPR:{ *:[v2i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v2i16] }:$src, GPR32:{ *:[i32] })
2796
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2797
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR32*/11,
2798
144
      // GIR_Coverage, 1831,
2799
144
      GIR_Done,
2800
144
    // Label 283: @4872
2801
144
    GIM_Try, /*On fail goto*//*Label 284*/ 4897, // Rule ID 1832 //
2802
144
      GIM_CheckFeatures, GIFBS_HasDSP,
2803
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
2804
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2805
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
2806
144
      // (bitconvert:{ *:[i32] } DSPR:{ *:[v4i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v4i8] }:$src, GPR32:{ *:[i32] })
2807
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2808
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR32*/11,
2809
144
      // GIR_Coverage, 1832,
2810
144
      GIR_Done,
2811
144
    // Label 284: @4897
2812
144
    GIM_Try, /*On fail goto*//*Label 285*/ 4922, // Rule ID 1835 //
2813
144
      GIM_CheckFeatures, GIFBS_HasDSP,
2814
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
2815
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2816
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
2817
144
      // (bitconvert:{ *:[f32] } DSPR:{ *:[v2i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v2i16] }:$src, FGR32:{ *:[i32] })
2818
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2819
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FGR32*/8,
2820
144
      // GIR_Coverage, 1835,
2821
144
      GIR_Done,
2822
144
    // Label 285: @4922
2823
144
    GIM_Try, /*On fail goto*//*Label 286*/ 4947, // Rule ID 1836 //
2824
144
      GIM_CheckFeatures, GIFBS_HasDSP,
2825
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
2826
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2827
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
2828
144
      // (bitconvert:{ *:[f32] } DSPR:{ *:[v4i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v4i8] }:$src, FGR32:{ *:[i32] })
2829
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2830
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FGR32*/8,
2831
144
      // GIR_Coverage, 1836,
2832
144
      GIR_Done,
2833
144
    // Label 286: @4947
2834
144
    GIM_Reject,
2835
144
    // Label 269: @4948
2836
144
    GIM_Try, /*On fail goto*//*Label 287*/ 4993,
2837
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2838
144
      GIM_Try, /*On fail goto*//*Label 288*/ 4973, // Rule ID 119 //
2839
144
        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
2840
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
2841
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2842
144
        // (bitconvert:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMTC1:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt)
2843
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMTC1,
2844
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2845
144
        // GIR_Coverage, 119,
2846
144
        GIR_Done,
2847
144
      // Label 288: @4973
2848
144
      GIM_Try, /*On fail goto*//*Label 289*/ 4992, // Rule ID 120 //
2849
144
        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
2850
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2851
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
2852
144
        // (bitconvert:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (DMFC1:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs)
2853
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMFC1,
2854
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2855
144
        // GIR_Coverage, 120,
2856
144
        GIR_Done,
2857
144
      // Label 289: @4992
2858
144
      GIM_Reject,
2859
144
    // Label 287: @4993
2860
144
    GIM_Reject,
2861
144
    // Label 270: @4994
2862
144
    GIM_Try, /*On fail goto*//*Label 290*/ 5039,
2863
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2864
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
2865
144
      GIM_Try, /*On fail goto*//*Label 291*/ 5021, // Rule ID 1833 //
2866
144
        GIM_CheckFeatures, GIFBS_HasDSP,
2867
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2868
144
        // (bitconvert:{ *:[v2i16] } GPR32:{ *:[i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i16] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
2869
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2870
144
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
2871
144
        // GIR_Coverage, 1833,
2872
144
        GIR_Done,
2873
144
      // Label 291: @5021
2874
144
      GIM_Try, /*On fail goto*//*Label 292*/ 5038, // Rule ID 1837 //
2875
144
        GIM_CheckFeatures, GIFBS_HasDSP,
2876
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
2877
144
        // (bitconvert:{ *:[v2i16] } FGR32:{ *:[f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i16] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
2878
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2879
144
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
2880
144
        // GIR_Coverage, 1837,
2881
144
        GIR_Done,
2882
144
      // Label 292: @5038
2883
144
      GIM_Reject,
2884
144
    // Label 290: @5039
2885
144
    GIM_Reject,
2886
144
    // Label 271: @5040
2887
144
    GIM_Try, /*On fail goto*//*Label 293*/ 5061, // Rule ID 1918 //
2888
144
      GIM_CheckFeatures, GIFBS_HasMSA,
2889
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2890
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2891
144
      // (bitconvert:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src, MSA128D:{ *:[i32] })
2892
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2893
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2894
144
      // GIR_Coverage, 1918,
2895
144
      GIR_Done,
2896
144
    // Label 293: @5061
2897
144
    GIM_Try, /*On fail goto*//*Label 294*/ 5082, // Rule ID 1921 //
2898
144
      GIM_CheckFeatures, GIFBS_HasMSA,
2899
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2900
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2901
144
      // (bitconvert:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src, MSA128D:{ *:[i32] })
2902
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2903
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2904
144
      // GIR_Coverage, 1921,
2905
144
      GIR_Done,
2906
144
    // Label 294: @5082
2907
144
    GIM_Try, /*On fail goto*//*Label 295*/ 5103, // Rule ID 1938 //
2908
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2909
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2910
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2911
144
      // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
2912
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2913
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2914
144
      // GIR_Coverage, 1938,
2915
144
      GIR_Done,
2916
144
    // Label 295: @5103
2917
144
    GIM_Try, /*On fail goto*//*Label 296*/ 5124, // Rule ID 1939 //
2918
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2919
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2920
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2921
144
      // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
2922
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2923
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2924
144
      // GIR_Coverage, 1939,
2925
144
      GIR_Done,
2926
144
    // Label 296: @5124
2927
144
    GIM_Try, /*On fail goto*//*Label 297*/ 5145, // Rule ID 1940 //
2928
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2929
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2930
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2931
144
      // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
2932
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2933
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2934
144
      // GIR_Coverage, 1940,
2935
144
      GIR_Done,
2936
144
    // Label 297: @5145
2937
144
    GIM_Try, /*On fail goto*//*Label 298*/ 5166, // Rule ID 1941 //
2938
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2939
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2940
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2941
144
      // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
2942
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2943
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2944
144
      // GIR_Coverage, 1941,
2945
144
      GIR_Done,
2946
144
    // Label 298: @5166
2947
144
    GIM_Try, /*On fail goto*//*Label 299*/ 5187, // Rule ID 1942 //
2948
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2949
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2950
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2951
144
      // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
2952
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2953
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2954
144
      // GIR_Coverage, 1942,
2955
144
      GIR_Done,
2956
144
    // Label 299: @5187
2957
144
    GIM_Try, /*On fail goto*//*Label 300*/ 5208, // Rule ID 1948 //
2958
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2959
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2960
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2961
144
      // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
2962
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2963
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2964
144
      // GIR_Coverage, 1948,
2965
144
      GIR_Done,
2966
144
    // Label 300: @5208
2967
144
    GIM_Try, /*On fail goto*//*Label 301*/ 5229, // Rule ID 1949 //
2968
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2969
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2970
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2971
144
      // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
2972
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2973
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2974
144
      // GIR_Coverage, 1949,
2975
144
      GIR_Done,
2976
144
    // Label 301: @5229
2977
144
    GIM_Try, /*On fail goto*//*Label 302*/ 5250, // Rule ID 1950 //
2978
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2979
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2980
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2981
144
      // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
2982
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2983
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2984
144
      // GIR_Coverage, 1950,
2985
144
      GIR_Done,
2986
144
    // Label 302: @5250
2987
144
    GIM_Try, /*On fail goto*//*Label 303*/ 5271, // Rule ID 1951 //
2988
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2989
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2990
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2991
144
      // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
2992
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2993
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2994
144
      // GIR_Coverage, 1951,
2995
144
      GIR_Done,
2996
144
    // Label 303: @5271
2997
144
    GIM_Try, /*On fail goto*//*Label 304*/ 5292, // Rule ID 1952 //
2998
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2999
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3000
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3001
144
      // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
3002
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3003
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3004
144
      // GIR_Coverage, 1952,
3005
144
      GIR_Done,
3006
144
    // Label 304: @5292
3007
144
    GIM_Try, /*On fail goto*//*Label 305*/ 5392, // Rule ID 1957 //
3008
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3009
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3010
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3011
144
      // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3012
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3013
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3014
144
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3015
144
      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3016
144
      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
3017
144
      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
3018
144
      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3019
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
3020
144
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
3021
144
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3022
144
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
3023
144
      GIR_AddImm, /*InsnID*/3, /*Imm*/27,
3024
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3025
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3026
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3027
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
3028
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3029
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3030
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3031
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3032
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3033
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3034
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3035
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3036
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3037
144
      GIR_EraseFromParent, /*InsnID*/0,
3038
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3039
144
      // GIR_Coverage, 1957,
3040
144
      GIR_Done,
3041
144
    // Label 305: @5392
3042
144
    GIM_Try, /*On fail goto*//*Label 306*/ 5492, // Rule ID 1958 //
3043
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3044
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3045
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3046
144
      // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3047
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3048
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3049
144
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3050
144
      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3051
144
      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
3052
144
      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
3053
144
      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3054
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
3055
144
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
3056
144
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3057
144
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
3058
144
      GIR_AddImm, /*InsnID*/3, /*Imm*/27,
3059
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3060
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3061
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3062
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
3063
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3064
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3065
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3066
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3067
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3068
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3069
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3070
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3071
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3072
144
      GIR_EraseFromParent, /*InsnID*/0,
3073
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3074
144
      // GIR_Coverage, 1958,
3075
144
      GIR_Done,
3076
144
    // Label 306: @5492
3077
144
    GIM_Try, /*On fail goto*//*Label 307*/ 5557, // Rule ID 1962 //
3078
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3079
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3080
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3081
144
      // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3082
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3083
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3084
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3085
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3086
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3087
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3088
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3089
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3090
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3091
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3092
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3093
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3094
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3095
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3096
144
      GIR_EraseFromParent, /*InsnID*/0,
3097
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3098
144
      // GIR_Coverage, 1962,
3099
144
      GIR_Done,
3100
144
    // Label 307: @5557
3101
144
    GIM_Try, /*On fail goto*//*Label 308*/ 5622, // Rule ID 1963 //
3102
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3103
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3104
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3105
144
      // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3106
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3107
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3108
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3109
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3110
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3111
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3112
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3113
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3114
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3115
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3116
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3117
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3118
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3119
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3120
144
      GIR_EraseFromParent, /*InsnID*/0,
3121
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3122
144
      // GIR_Coverage, 1963,
3123
144
      GIR_Done,
3124
144
    // Label 308: @5622
3125
144
    GIM_Try, /*On fail goto*//*Label 309*/ 5687, // Rule ID 1967 //
3126
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3127
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3128
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3129
144
      // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3130
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3131
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3132
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3133
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3134
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3135
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3136
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3137
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3138
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3139
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3140
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3141
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3142
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3143
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3144
144
      GIR_EraseFromParent, /*InsnID*/0,
3145
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3146
144
      // GIR_Coverage, 1967,
3147
144
      GIR_Done,
3148
144
    // Label 309: @5687
3149
144
    GIM_Try, /*On fail goto*//*Label 310*/ 5752, // Rule ID 1968 //
3150
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3151
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3152
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3153
144
      // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3154
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3155
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3156
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3157
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3158
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3159
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3160
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3161
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3162
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3163
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3164
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3165
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3166
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3167
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3168
144
      GIR_EraseFromParent, /*InsnID*/0,
3169
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3170
144
      // GIR_Coverage, 1968,
3171
144
      GIR_Done,
3172
144
    // Label 310: @5752
3173
144
    GIM_Try, /*On fail goto*//*Label 311*/ 5817, // Rule ID 1972 //
3174
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3175
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3176
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3177
144
      // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3178
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3179
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3180
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3181
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3182
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3183
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3184
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3185
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3186
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3187
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3188
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3189
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3190
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3191
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3192
144
      GIR_EraseFromParent, /*InsnID*/0,
3193
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3194
144
      // GIR_Coverage, 1972,
3195
144
      GIR_Done,
3196
144
    // Label 311: @5817
3197
144
    GIM_Try, /*On fail goto*//*Label 312*/ 5882, // Rule ID 1973 //
3198
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3199
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3200
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3201
144
      // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3202
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3203
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3204
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3205
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3206
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3207
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3208
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3209
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3210
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3211
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3212
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3213
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3214
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3215
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3216
144
      GIR_EraseFromParent, /*InsnID*/0,
3217
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3218
144
      // GIR_Coverage, 1973,
3219
144
      GIR_Done,
3220
144
    // Label 312: @5882
3221
144
    GIM_Try, /*On fail goto*//*Label 313*/ 5947, // Rule ID 1977 //
3222
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3223
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3224
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3225
144
      // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3226
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3227
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3228
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3229
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3230
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3231
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3232
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3233
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3234
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3235
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3236
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3237
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3238
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3239
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3240
144
      GIR_EraseFromParent, /*InsnID*/0,
3241
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3242
144
      // GIR_Coverage, 1977,
3243
144
      GIR_Done,
3244
144
    // Label 313: @5947
3245
144
    GIM_Try, /*On fail goto*//*Label 314*/ 6012, // Rule ID 1978 //
3246
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3247
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3248
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3249
144
      // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3250
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3251
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3252
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3253
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3254
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3255
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3256
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3257
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3258
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3259
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3260
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3261
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3262
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3263
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3264
144
      GIR_EraseFromParent, /*InsnID*/0,
3265
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3266
144
      // GIR_Coverage, 1978,
3267
144
      GIR_Done,
3268
144
    // Label 314: @6012
3269
144
    GIM_Reject,
3270
144
    // Label 272: @6013
3271
144
    GIM_Try, /*On fail goto*//*Label 315*/ 6058,
3272
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3273
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
3274
144
      GIM_Try, /*On fail goto*//*Label 316*/ 6040, // Rule ID 1834 //
3275
144
        GIM_CheckFeatures, GIFBS_HasDSP,
3276
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
3277
144
        // (bitconvert:{ *:[v4i8] } GPR32:{ *:[i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i8] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
3278
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3279
144
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
3280
144
        // GIR_Coverage, 1834,
3281
144
        GIR_Done,
3282
144
      // Label 316: @6040
3283
144
      GIM_Try, /*On fail goto*//*Label 317*/ 6057, // Rule ID 1838 //
3284
144
        GIM_CheckFeatures, GIFBS_HasDSP,
3285
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
3286
144
        // (bitconvert:{ *:[v4i8] } FGR32:{ *:[f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i8] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
3287
144
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3288
144
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
3289
144
        // GIR_Coverage, 1838,
3290
144
        GIR_Done,
3291
144
      // Label 317: @6057
3292
144
      GIM_Reject,
3293
144
    // Label 315: @6058
3294
144
    GIM_Reject,
3295
144
    // Label 273: @6059
3296
144
    GIM_Try, /*On fail goto*//*Label 318*/ 6080, // Rule ID 1917 //
3297
144
      GIM_CheckFeatures, GIFBS_HasMSA,
3298
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3299
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3300
144
      // (bitconvert:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] })
3301
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3302
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3303
144
      // GIR_Coverage, 1917,
3304
144
      GIR_Done,
3305
144
    // Label 318: @6080
3306
144
    GIM_Try, /*On fail goto*//*Label 319*/ 6101, // Rule ID 1920 //
3307
144
      GIM_CheckFeatures, GIFBS_HasMSA,
3308
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3309
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3310
144
      // (bitconvert:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] })
3311
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3312
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3313
144
      // GIR_Coverage, 1920,
3314
144
      GIR_Done,
3315
144
    // Label 319: @6101
3316
144
    GIM_Try, /*On fail goto*//*Label 320*/ 6122, // Rule ID 1933 //
3317
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3318
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3319
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3320
144
      // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3321
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3322
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3323
144
      // GIR_Coverage, 1933,
3324
144
      GIR_Done,
3325
144
    // Label 320: @6122
3326
144
    GIM_Try, /*On fail goto*//*Label 321*/ 6143, // Rule ID 1934 //
3327
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3328
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3329
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3330
144
      // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3331
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3332
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3333
144
      // GIR_Coverage, 1934,
3334
144
      GIR_Done,
3335
144
    // Label 321: @6143
3336
144
    GIM_Try, /*On fail goto*//*Label 322*/ 6164, // Rule ID 1935 //
3337
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3338
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3339
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3340
144
      // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3341
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3342
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3343
144
      // GIR_Coverage, 1935,
3344
144
      GIR_Done,
3345
144
    // Label 322: @6164
3346
144
    GIM_Try, /*On fail goto*//*Label 323*/ 6185, // Rule ID 1936 //
3347
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3348
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3349
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3350
144
      // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3351
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3352
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3353
144
      // GIR_Coverage, 1936,
3354
144
      GIR_Done,
3355
144
    // Label 323: @6185
3356
144
    GIM_Try, /*On fail goto*//*Label 324*/ 6206, // Rule ID 1937 //
3357
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3358
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3359
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3360
144
      // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3361
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3362
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3363
144
      // GIR_Coverage, 1937,
3364
144
      GIR_Done,
3365
144
    // Label 324: @6206
3366
144
    GIM_Try, /*On fail goto*//*Label 325*/ 6227, // Rule ID 1943 //
3367
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3368
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3369
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3370
144
      // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3371
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3372
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3373
144
      // GIR_Coverage, 1943,
3374
144
      GIR_Done,
3375
144
    // Label 325: @6227
3376
144
    GIM_Try, /*On fail goto*//*Label 326*/ 6248, // Rule ID 1944 //
3377
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3378
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3379
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3380
144
      // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3381
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3382
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3383
144
      // GIR_Coverage, 1944,
3384
144
      GIR_Done,
3385
144
    // Label 326: @6248
3386
144
    GIM_Try, /*On fail goto*//*Label 327*/ 6269, // Rule ID 1945 //
3387
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3388
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3389
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3390
144
      // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3391
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3392
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3393
144
      // GIR_Coverage, 1945,
3394
144
      GIR_Done,
3395
144
    // Label 327: @6269
3396
144
    GIM_Try, /*On fail goto*//*Label 328*/ 6290, // Rule ID 1946 //
3397
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3398
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3399
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3400
144
      // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3401
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3402
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3403
144
      // GIR_Coverage, 1946,
3404
144
      GIR_Done,
3405
144
    // Label 328: @6290
3406
144
    GIM_Try, /*On fail goto*//*Label 329*/ 6311, // Rule ID 1947 //
3407
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3408
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3409
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3410
144
      // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3411
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3412
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3413
144
      // GIR_Coverage, 1947,
3414
144
      GIR_Done,
3415
144
    // Label 329: @6311
3416
144
    GIM_Try, /*On fail goto*//*Label 330*/ 6376, // Rule ID 1955 //
3417
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3418
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3419
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3420
144
      // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3421
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3422
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3423
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3424
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3425
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3426
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3427
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3428
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3429
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3430
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3431
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3432
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3433
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3434
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3435
144
      GIR_EraseFromParent, /*InsnID*/0,
3436
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3437
144
      // GIR_Coverage, 1955,
3438
144
      GIR_Done,
3439
144
    // Label 330: @6376
3440
144
    GIM_Try, /*On fail goto*//*Label 331*/ 6441, // Rule ID 1956 //
3441
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3442
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3443
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3444
144
      // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3445
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3446
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3447
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3448
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3449
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3450
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3451
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3452
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3453
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3454
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3455
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3456
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3457
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3458
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3459
144
      GIR_EraseFromParent, /*InsnID*/0,
3460
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3461
144
      // GIR_Coverage, 1956,
3462
144
      GIR_Done,
3463
144
    // Label 331: @6441
3464
144
    GIM_Try, /*On fail goto*//*Label 332*/ 6506, // Rule ID 1960 //
3465
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3466
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3467
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3468
144
      // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3469
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3470
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3471
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3472
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3473
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3474
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3475
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3476
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3477
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3478
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3479
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3480
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3481
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3482
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3483
144
      GIR_EraseFromParent, /*InsnID*/0,
3484
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3485
144
      // GIR_Coverage, 1960,
3486
144
      GIR_Done,
3487
144
    // Label 332: @6506
3488
144
    GIM_Try, /*On fail goto*//*Label 333*/ 6571, // Rule ID 1961 //
3489
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3490
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3491
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3492
144
      // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3493
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3494
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3495
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3496
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3497
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3498
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3499
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3500
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3501
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3502
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3503
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3504
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3505
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3506
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3507
144
      GIR_EraseFromParent, /*InsnID*/0,
3508
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3509
144
      // GIR_Coverage, 1961,
3510
144
      GIR_Done,
3511
144
    // Label 333: @6571
3512
144
    GIM_Try, /*On fail goto*//*Label 334*/ 6636, // Rule ID 1965 //
3513
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3514
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3515
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3516
144
      // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3517
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3518
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3519
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3520
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3521
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3522
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3523
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3524
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3525
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3526
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3527
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3528
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3529
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3530
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3531
144
      GIR_EraseFromParent, /*InsnID*/0,
3532
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3533
144
      // GIR_Coverage, 1965,
3534
144
      GIR_Done,
3535
144
    // Label 334: @6636
3536
144
    GIM_Try, /*On fail goto*//*Label 335*/ 6701, // Rule ID 1966 //
3537
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3538
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3539
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3540
144
      // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3541
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3542
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3543
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3544
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3545
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3546
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3547
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3548
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3549
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3550
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3551
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3552
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3553
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3554
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3555
144
      GIR_EraseFromParent, /*InsnID*/0,
3556
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3557
144
      // GIR_Coverage, 1966,
3558
144
      GIR_Done,
3559
144
    // Label 335: @6701
3560
144
    GIM_Try, /*On fail goto*//*Label 336*/ 6766, // Rule ID 1982 //
3561
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3562
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3563
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3564
144
      // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3565
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3566
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3567
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3568
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3569
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3570
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3571
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3572
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3573
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3574
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3575
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3576
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3577
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3578
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3579
144
      GIR_EraseFromParent, /*InsnID*/0,
3580
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3581
144
      // GIR_Coverage, 1982,
3582
144
      GIR_Done,
3583
144
    // Label 336: @6766
3584
144
    GIM_Try, /*On fail goto*//*Label 337*/ 6831, // Rule ID 1983 //
3585
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3586
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3587
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3588
144
      // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3589
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3590
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3591
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3592
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3593
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3594
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3595
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3596
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3597
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3598
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3599
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3600
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3601
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3602
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3603
144
      GIR_EraseFromParent, /*InsnID*/0,
3604
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3605
144
      // GIR_Coverage, 1983,
3606
144
      GIR_Done,
3607
144
    // Label 337: @6831
3608
144
    GIM_Try, /*On fail goto*//*Label 338*/ 6896, // Rule ID 1987 //
3609
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3610
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3611
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3612
144
      // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3613
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3614
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3615
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3616
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3617
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3618
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3619
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3620
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3621
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3622
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3623
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3624
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3625
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3626
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3627
144
      GIR_EraseFromParent, /*InsnID*/0,
3628
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3629
144
      // GIR_Coverage, 1987,
3630
144
      GIR_Done,
3631
144
    // Label 338: @6896
3632
144
    GIM_Try, /*On fail goto*//*Label 339*/ 6961, // Rule ID 1988 //
3633
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3634
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3635
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3636
144
      // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3637
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3638
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3639
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3640
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3641
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3642
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3643
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3644
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3645
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3646
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3647
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3648
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3649
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3650
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3651
144
      GIR_EraseFromParent, /*InsnID*/0,
3652
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3653
144
      // GIR_Coverage, 1988,
3654
144
      GIR_Done,
3655
144
    // Label 339: @6961
3656
144
    GIM_Reject,
3657
144
    // Label 274: @6962
3658
144
    GIM_Try, /*On fail goto*//*Label 340*/ 6983, // Rule ID 1916 //
3659
144
      GIM_CheckFeatures, GIFBS_HasMSA,
3660
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3661
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3662
144
      // (bitconvert:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] })
3663
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3664
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3665
144
      // GIR_Coverage, 1916,
3666
144
      GIR_Done,
3667
144
    // Label 340: @6983
3668
144
    GIM_Try, /*On fail goto*//*Label 341*/ 7004, // Rule ID 1919 //
3669
144
      GIM_CheckFeatures, GIFBS_HasMSA,
3670
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3671
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3672
144
      // (bitconvert:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] })
3673
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3674
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3675
144
      // GIR_Coverage, 1919,
3676
144
      GIR_Done,
3677
144
    // Label 341: @7004
3678
144
    GIM_Try, /*On fail goto*//*Label 342*/ 7025, // Rule ID 1928 //
3679
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3680
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3681
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3682
144
      // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src, MSA128H:{ *:[i32] })
3683
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3684
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3685
144
      // GIR_Coverage, 1928,
3686
144
      GIR_Done,
3687
144
    // Label 342: @7025
3688
144
    GIM_Try, /*On fail goto*//*Label 343*/ 7046, // Rule ID 1929 //
3689
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3690
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3691
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3692
144
      // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] })
3693
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3694
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3695
144
      // GIR_Coverage, 1929,
3696
144
      GIR_Done,
3697
144
    // Label 343: @7046
3698
144
    GIM_Try, /*On fail goto*//*Label 344*/ 7067, // Rule ID 1930 //
3699
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3700
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3701
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3702
144
      // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] })
3703
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3704
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3705
144
      // GIR_Coverage, 1930,
3706
144
      GIR_Done,
3707
144
    // Label 344: @7067
3708
144
    GIM_Try, /*On fail goto*//*Label 345*/ 7088, // Rule ID 1931 //
3709
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3710
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3711
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3712
144
      // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] })
3713
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3714
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3715
144
      // GIR_Coverage, 1931,
3716
144
      GIR_Done,
3717
144
    // Label 345: @7088
3718
144
    GIM_Try, /*On fail goto*//*Label 346*/ 7109, // Rule ID 1932 //
3719
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3720
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3721
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3722
144
      // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] })
3723
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3724
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3725
144
      // GIR_Coverage, 1932,
3726
144
      GIR_Done,
3727
144
    // Label 346: @7109
3728
144
    GIM_Try, /*On fail goto*//*Label 347*/ 7174, // Rule ID 1953 //
3729
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3730
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3731
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3732
144
      // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3733
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3734
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3735
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3736
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3737
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3738
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3739
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3740
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3741
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3742
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3743
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3744
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3745
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3746
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3747
144
      GIR_EraseFromParent, /*InsnID*/0,
3748
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3749
144
      // GIR_Coverage, 1953,
3750
144
      GIR_Done,
3751
144
    // Label 347: @7174
3752
144
    GIM_Try, /*On fail goto*//*Label 348*/ 7239, // Rule ID 1954 //
3753
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3754
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3755
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3756
144
      // (bitconvert:{ *:[v8f16] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3757
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3758
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3759
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3760
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3761
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3762
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3763
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3764
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3765
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3766
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3767
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3768
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3769
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3770
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3771
144
      GIR_EraseFromParent, /*InsnID*/0,
3772
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3773
144
      // GIR_Coverage, 1954,
3774
144
      GIR_Done,
3775
144
    // Label 348: @7239
3776
144
    GIM_Try, /*On fail goto*//*Label 349*/ 7304, // Rule ID 1970 //
3777
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3778
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3779
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3780
144
      // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3781
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3782
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3783
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3784
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3785
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3786
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3787
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3788
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3789
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3790
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3791
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3792
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3793
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3794
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3795
144
      GIR_EraseFromParent, /*InsnID*/0,
3796
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3797
144
      // GIR_Coverage, 1970,
3798
144
      GIR_Done,
3799
144
    // Label 349: @7304
3800
144
    GIM_Try, /*On fail goto*//*Label 350*/ 7369, // Rule ID 1971 //
3801
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3802
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3803
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3804
144
      // (bitconvert:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3805
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3806
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3807
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3808
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3809
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3810
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3811
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3812
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3813
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3814
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3815
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3816
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3817
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3818
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3819
144
      GIR_EraseFromParent, /*InsnID*/0,
3820
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3821
144
      // GIR_Coverage, 1971,
3822
144
      GIR_Done,
3823
144
    // Label 350: @7369
3824
144
    GIM_Try, /*On fail goto*//*Label 351*/ 7434, // Rule ID 1975 //
3825
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3826
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3827
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3828
144
      // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3829
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3830
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3831
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3832
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3833
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3834
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3835
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3836
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3837
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3838
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3839
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3840
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3841
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3842
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3843
144
      GIR_EraseFromParent, /*InsnID*/0,
3844
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3845
144
      // GIR_Coverage, 1975,
3846
144
      GIR_Done,
3847
144
    // Label 351: @7434
3848
144
    GIM_Try, /*On fail goto*//*Label 352*/ 7499, // Rule ID 1976 //
3849
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3850
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3851
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3852
144
      // (bitconvert:{ *:[v8f16] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3853
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3854
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3855
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3856
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3857
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3858
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3859
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3860
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3861
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3862
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3863
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3864
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3865
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3866
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3867
144
      GIR_EraseFromParent, /*InsnID*/0,
3868
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3869
144
      // GIR_Coverage, 1976,
3870
144
      GIR_Done,
3871
144
    // Label 352: @7499
3872
144
    GIM_Try, /*On fail goto*//*Label 353*/ 7564, // Rule ID 1980 //
3873
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3874
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3875
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3876
144
      // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3877
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3878
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3879
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3880
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3881
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3882
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3883
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3884
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3885
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3886
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3887
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3888
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3889
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3890
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3891
144
      GIR_EraseFromParent, /*InsnID*/0,
3892
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3893
144
      // GIR_Coverage, 1980,
3894
144
      GIR_Done,
3895
144
    // Label 353: @7564
3896
144
    GIM_Try, /*On fail goto*//*Label 354*/ 7629, // Rule ID 1981 //
3897
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3898
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3899
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3900
144
      // (bitconvert:{ *:[v8f16] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3901
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3902
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3903
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3904
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3905
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3906
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3907
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3908
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3909
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3910
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3911
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3912
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3913
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3914
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3915
144
      GIR_EraseFromParent, /*InsnID*/0,
3916
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3917
144
      // GIR_Coverage, 1981,
3918
144
      GIR_Done,
3919
144
    // Label 354: @7629
3920
144
    GIM_Try, /*On fail goto*//*Label 355*/ 7694, // Rule ID 1985 //
3921
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3922
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3923
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3924
144
      // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3925
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3926
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3927
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3928
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3929
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3930
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3931
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3932
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3933
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3934
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3935
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3936
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3937
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3938
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3939
144
      GIR_EraseFromParent, /*InsnID*/0,
3940
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3941
144
      // GIR_Coverage, 1985,
3942
144
      GIR_Done,
3943
144
    // Label 355: @7694
3944
144
    GIM_Try, /*On fail goto*//*Label 356*/ 7759, // Rule ID 1986 //
3945
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3946
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3947
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3948
144
      // (bitconvert:{ *:[v8f16] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3949
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3950
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3951
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3952
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3953
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3954
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3955
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3956
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3957
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3958
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3959
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3960
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3961
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3962
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3963
144
      GIR_EraseFromParent, /*InsnID*/0,
3964
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3965
144
      // GIR_Coverage, 1986,
3966
144
      GIR_Done,
3967
144
    // Label 356: @7759
3968
144
    GIM_Reject,
3969
144
    // Label 275: @7760
3970
144
    GIM_Try, /*On fail goto*//*Label 357*/ 7781, // Rule ID 1922 //
3971
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3972
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3973
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
3974
144
      // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] })
3975
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3976
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
3977
144
      // GIR_Coverage, 1922,
3978
144
      GIR_Done,
3979
144
    // Label 357: @7781
3980
144
    GIM_Try, /*On fail goto*//*Label 358*/ 7802, // Rule ID 1923 //
3981
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3982
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3983
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
3984
144
      // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] })
3985
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3986
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
3987
144
      // GIR_Coverage, 1923,
3988
144
      GIR_Done,
3989
144
    // Label 358: @7802
3990
144
    GIM_Try, /*On fail goto*//*Label 359*/ 7823, // Rule ID 1924 //
3991
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3992
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3993
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
3994
144
      // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] })
3995
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3996
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
3997
144
      // GIR_Coverage, 1924,
3998
144
      GIR_Done,
3999
144
    // Label 359: @7823
4000
144
    GIM_Try, /*On fail goto*//*Label 360*/ 7844, // Rule ID 1925 //
4001
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4002
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4003
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4004
144
      // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] })
4005
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4006
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4007
144
      // GIR_Coverage, 1925,
4008
144
      GIR_Done,
4009
144
    // Label 360: @7844
4010
144
    GIM_Try, /*On fail goto*//*Label 361*/ 7865, // Rule ID 1926 //
4011
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4012
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4013
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4014
144
      // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] })
4015
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4016
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4017
144
      // GIR_Coverage, 1926,
4018
144
      GIR_Done,
4019
144
    // Label 361: @7865
4020
144
    GIM_Try, /*On fail goto*//*Label 362*/ 7886, // Rule ID 1927 //
4021
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4022
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4023
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4024
144
      // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] })
4025
144
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4026
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4027
144
      // GIR_Coverage, 1927,
4028
144
      GIR_Done,
4029
144
    // Label 362: @7886
4030
144
    GIM_Try, /*On fail goto*//*Label 363*/ 7951, // Rule ID 1959 //
4031
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4032
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4033
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4034
144
      // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4035
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4036
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4037
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4038
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4039
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4040
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4041
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4042
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4043
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4044
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4045
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4046
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4047
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4048
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4049
144
      GIR_EraseFromParent, /*InsnID*/0,
4050
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4051
144
      // GIR_Coverage, 1959,
4052
144
      GIR_Done,
4053
144
    // Label 363: @7951
4054
144
    GIM_Try, /*On fail goto*//*Label 364*/ 8016, // Rule ID 1964 //
4055
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4056
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4057
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4058
144
      // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4059
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4060
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4061
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4062
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4063
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4064
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4065
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4066
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4067
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4068
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4069
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4070
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4071
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4072
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4073
144
      GIR_EraseFromParent, /*InsnID*/0,
4074
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4075
144
      // GIR_Coverage, 1964,
4076
144
      GIR_Done,
4077
144
    // Label 364: @8016
4078
144
    GIM_Try, /*On fail goto*//*Label 365*/ 8081, // Rule ID 1969 //
4079
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4080
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4081
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4082
144
      // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
4083
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4084
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4085
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4086
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4087
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4088
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4089
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4090
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4091
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4092
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
4093
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4094
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4095
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4096
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4097
144
      GIR_EraseFromParent, /*InsnID*/0,
4098
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4099
144
      // GIR_Coverage, 1969,
4100
144
      GIR_Done,
4101
144
    // Label 365: @8081
4102
144
    GIM_Try, /*On fail goto*//*Label 366*/ 8146, // Rule ID 1974 //
4103
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4104
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4105
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4106
144
      // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
4107
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4108
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4109
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4110
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4111
144
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4112
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4113
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4114
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4115
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4116
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
4117
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4118
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4119
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4120
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4121
144
      GIR_EraseFromParent, /*InsnID*/0,
4122
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4123
144
      // GIR_Coverage, 1974,
4124
144
      GIR_Done,
4125
144
    // Label 366: @8146
4126
144
    GIM_Try, /*On fail goto*//*Label 367*/ 8246, // Rule ID 1979 //
4127
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4128
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4129
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4130
144
      // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4131
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4132
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4133
144
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4134
144
      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4135
144
      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
4136
144
      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
4137
144
      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4138
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
4139
144
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
4140
144
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
4141
144
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
4142
144
      GIR_AddImm, /*InsnID*/3, /*Imm*/27,
4143
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4144
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4145
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4146
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
4147
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4148
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
4149
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4150
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4151
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4152
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4153
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4154
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4155
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4156
144
      GIR_EraseFromParent, /*InsnID*/0,
4157
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4158
144
      // GIR_Coverage, 1979,
4159
144
      GIR_Done,
4160
144
    // Label 367: @8246
4161
144
    GIM_Try, /*On fail goto*//*Label 368*/ 8346, // Rule ID 1984 //
4162
144
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4163
144
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4164
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4165
144
      // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4166
144
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4167
144
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4168
144
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4169
144
      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4170
144
      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
4171
144
      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
4172
144
      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4173
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
4174
144
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
4175
144
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
4176
144
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
4177
144
      GIR_AddImm, /*InsnID*/3, /*Imm*/27,
4178
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4179
144
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4180
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4181
144
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
4182
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4183
144
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
4184
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4185
144
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4186
144
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4187
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4188
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4189
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4190
144
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4191
144
      GIR_EraseFromParent, /*InsnID*/0,
4192
144
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4193
144
      // GIR_Coverage, 1984,
4194
144
      GIR_Done,
4195
144
    // Label 368: @8346
4196
144
    GIM_Reject,
4197
144
    // Label 276: @8347
4198
144
    GIM_Reject,
4199
144
    // Label 11: @8348
4200
144
    GIM_Try, /*On fail goto*//*Label 369*/ 8413, // Rule ID 1907 //
4201
144
      GIM_CheckFeatures, GIFBS_HasDSP,
4202
144
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4203
144
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
4204
144
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
4205
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4206
144
      // MIs[0] Operand 1
4207
144
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4208
144
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4209
144
      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4210
144
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4211
144
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4212
144
      GIM_CheckIsSafeToFold, /*InsnID*/1,
4213
144
      // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LWX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4214
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LWX,
4215
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4216
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4217
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4218
144
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
4219
144
      GIR_EraseFromParent, /*InsnID*/0,
4220
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4221
144
      // GIR_Coverage, 1907,
4222
144
      GIR_Done,
4223
144
    // Label 369: @8413
4224
144
    GIM_Reject,
4225
144
    // Label 12: @8414
4226
144
    GIM_Try, /*On fail goto*//*Label 370*/ 8479, // Rule ID 1906 //
4227
144
      GIM_CheckFeatures, GIFBS_HasDSP,
4228
144
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4229
144
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
4230
144
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
4231
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4232
144
      // MIs[0] Operand 1
4233
144
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4234
144
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4235
144
      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4236
144
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4237
144
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4238
144
      GIM_CheckIsSafeToFold, /*InsnID*/1,
4239
144
      // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LHX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4240
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LHX,
4241
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4242
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4243
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4244
144
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
4245
144
      GIR_EraseFromParent, /*InsnID*/0,
4246
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4247
144
      // GIR_Coverage, 1906,
4248
144
      GIR_Done,
4249
144
    // Label 370: @8479
4250
144
    GIM_Reject,
4251
144
    // Label 13: @8480
4252
144
    GIM_Try, /*On fail goto*//*Label 371*/ 8545, // Rule ID 1905 //
4253
144
      GIM_CheckFeatures, GIFBS_HasDSP,
4254
144
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4255
144
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
4256
144
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
4257
144
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4258
144
      // MIs[0] Operand 1
4259
144
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4260
144
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4261
144
      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4262
144
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4263
144
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4264
144
      GIM_CheckIsSafeToFold, /*InsnID*/1,
4265
144
      // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (LBUX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4266
144
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LBUX,
4267
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4268
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4269
144
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4270
144
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
4271
144
      GIR_EraseFromParent, /*InsnID*/0,
4272
144
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4273
144
      // GIR_Coverage, 1905,
4274
144
      GIR_Done,
4275
144
    // Label 371: @8545
4276
144
    GIM_Reject,
4277
144
    // Label 14: @8546
4278
144
    GIM_Try, /*On fail goto*//*Label 372*/ 10740,
4279
144
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
4280
144
      GIM_Try, /*On fail goto*//*Label 373*/ 8598, // Rule ID 400 //
4281
144
        GIM_CheckFeatures, GIFBS_HasDSP,
4282
144
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
4283
144
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
4284
144
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4285
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4286
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4287
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4288
144
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt8,
4289
144
        // MIs[1] Operand 1
4290
144
        // No operand predicates
4291
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4292
144
        // (intrinsic_wo_chain:{ *:[v4i8] } 3523:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm)  =>  (REPL_QB:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
4293
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_QB,
4294
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4295
144
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4296
144
        GIR_EraseFromParent, /*InsnID*/0,
4297
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4298
144
        // GIR_Coverage, 400,
4299
144
        GIR_Done,
4300
144
      // Label 373: @8598
4301
144
      GIM_Try, /*On fail goto*//*Label 374*/ 8645, // Rule ID 401 //
4302
144
        GIM_CheckFeatures, GIFBS_HasDSP,
4303
144
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
4304
144
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4305
144
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4306
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4307
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4308
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4309
144
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExt10,
4310
144
        // MIs[1] Operand 1
4311
144
        // No operand predicates
4312
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4313
144
        // (intrinsic_wo_chain:{ *:[v2i16] } 3522:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm)  =>  (REPL_PH:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
4314
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_PH,
4315
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4316
144
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4317
144
        GIR_EraseFromParent, /*InsnID*/0,
4318
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4319
144
        // GIR_Coverage, 401,
4320
144
        GIR_Done,
4321
144
      // Label 374: @8645
4322
144
      GIM_Try, /*On fail goto*//*Label 375*/ 8692, // Rule ID 1254 //
4323
144
        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
4324
144
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
4325
144
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4326
144
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4327
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4328
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4329
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4330
144
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExt10,
4331
144
        // MIs[1] Operand 1
4332
144
        // No operand predicates
4333
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4334
144
        // (intrinsic_wo_chain:{ *:[v2i16] } 3522:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm)  =>  (REPL_PH_MM:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
4335
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_PH_MM,
4336
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4337
144
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4338
144
        GIR_EraseFromParent, /*InsnID*/0,
4339
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4340
144
        // GIR_Coverage, 1254,
4341
144
        GIR_Done,
4342
144
      // Label 375: @8692
4343
144
      GIM_Try, /*On fail goto*//*Label 376*/ 8739, // Rule ID 1255 //
4344
144
        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
4345
144
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
4346
144
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
4347
144
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4348
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4349
144
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4350
144
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4351
144
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt8,
4352
144
        // MIs[1] Operand 1
4353
144
        // No operand predicates
4354
144
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4355
144
        // (intrinsic_wo_chain:{ *:[v4i8] } 3523:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm)  =>  (REPL_QB_MM:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
4356
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_QB_MM,
4357
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
4358
144
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4359
144
        GIR_EraseFromParent, /*InsnID*/0,
4360
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4361
144
        // GIR_Coverage, 1255,
4362
144
        GIR_Done,
4363
144
      // Label 376: @8739
4364
144
      GIM_Try, /*On fail goto*//*Label 377*/ 8779, // Rule ID 334 //
4365
144
        GIM_CheckFeatures, GIFBS_HasDSP,
4366
144
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_raddu_w_qb,
4367
144
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4368
144
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4369
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4370
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4371
144
        // (intrinsic_wo_chain:{ *:[i32] } 3520:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (RADDU_W_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
4372
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RADDU_W_QB,
4373
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4374
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
4375
144
        GIR_EraseFromParent, /*InsnID*/0,
4376
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4377
144
        // GIR_Coverage, 334,
4378
144
        GIR_Done,
4379
144
      // Label 377: @8779
4380
144
      GIM_Try, /*On fail goto*//*Label 378*/ 8819, // Rule ID 341 //
4381
144
        GIM_CheckFeatures, GIFBS_HasDSP,
4382
144
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phl,
4383
144
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4384
144
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
4385
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4386
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4387
144
        // (intrinsic_wo_chain:{ *:[i32] } 3502:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECEQ_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
4388
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHL,
4389
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4390
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4391
144
        GIR_EraseFromParent, /*InsnID*/0,
4392
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4393
144
        // GIR_Coverage, 341,
4394
144
        GIR_Done,
4395
144
      // Label 378: @8819
4396
144
      GIM_Try, /*On fail goto*//*Label 379*/ 8859, // Rule ID 342 //
4397
144
        GIM_CheckFeatures, GIFBS_HasDSP,
4398
144
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phr,
4399
144
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4400
144
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
4401
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4402
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4403
144
        // (intrinsic_wo_chain:{ *:[i32] } 3503:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECEQ_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
4404
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHR,
4405
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4406
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4407
144
        GIR_EraseFromParent, /*InsnID*/0,
4408
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4409
144
        // GIR_Coverage, 342,
4410
144
        GIR_Done,
4411
144
      // Label 379: @8859
4412
144
      GIM_Try, /*On fail goto*//*Label 380*/ 8899, // Rule ID 343 //
4413
144
        GIM_CheckFeatures, GIFBS_HasDSP,
4414
144
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbl,
4415
144
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4416
144
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4417
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4418
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4419
144
        // (intrinsic_wo_chain:{ *:[v2i16] } 3504:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4420
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBL,
4421
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4422
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4423
144
        GIR_EraseFromParent, /*InsnID*/0,
4424
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4425
144
        // GIR_Coverage, 343,
4426
144
        GIR_Done,
4427
144
      // Label 380: @8899
4428
144
      GIM_Try, /*On fail goto*//*Label 381*/ 8939, // Rule ID 344 //
4429
144
        GIM_CheckFeatures, GIFBS_HasDSP,
4430
144
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbr,
4431
144
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4432
144
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4433
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4434
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4435
144
        // (intrinsic_wo_chain:{ *:[v2i16] } 3506:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4436
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBR,
4437
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4438
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4439
144
        GIR_EraseFromParent, /*InsnID*/0,
4440
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4441
144
        // GIR_Coverage, 344,
4442
144
        GIR_Done,
4443
144
      // Label 381: @8939
4444
144
      GIM_Try, /*On fail goto*//*Label 382*/ 8979, // Rule ID 345 //
4445
144
        GIM_CheckFeatures, GIFBS_HasDSP,
4446
144
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbla,
4447
144
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4448
144
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4449
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4450
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4451
144
        // (intrinsic_wo_chain:{ *:[v2i16] } 3505:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4452
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBLA,
4453
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4454
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4455
144
        GIR_EraseFromParent, /*InsnID*/0,
4456
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4457
144
        // GIR_Coverage, 345,
4458
144
        GIR_Done,
4459
144
      // Label 382: @8979
4460
144
      GIM_Try, /*On fail goto*//*Label 383*/ 9019, // Rule ID 346 //
4461
144
        GIM_CheckFeatures, GIFBS_HasDSP,
4462
144
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbra,
4463
144
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4464
144
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4465
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4466
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4467
144
        // (intrinsic_wo_chain:{ *:[v2i16] } 3507:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4468
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBRA,
4469
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4470
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4471
144
        GIR_EraseFromParent, /*InsnID*/0,
4472
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4473
144
        // GIR_Coverage, 346,
4474
144
        GIR_Done,
4475
144
      // Label 383: @9019
4476
144
      GIM_Try, /*On fail goto*//*Label 384*/ 9059, // Rule ID 347 //
4477
144
        GIM_CheckFeatures, GIFBS_HasDSP,
4478
144
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbl,
4479
144
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4480
144
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4481
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4482
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4483
144
        // (intrinsic_wo_chain:{ *:[v2i16] } 3508:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4484
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBL,
4485
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4486
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4487
144
        GIR_EraseFromParent, /*InsnID*/0,
4488
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4489
144
        // GIR_Coverage, 347,
4490
144
        GIR_Done,
4491
144
      // Label 384: @9059
4492
144
      GIM_Try, /*On fail goto*//*Label 385*/ 9099, // Rule ID 348 //
4493
144
        GIM_CheckFeatures, GIFBS_HasDSP,
4494
144
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbr,
4495
144
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4496
144
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4497
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4498
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4499
144
        // (intrinsic_wo_chain:{ *:[v2i16] } 3510:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4500
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBR,
4501
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4502
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4503
144
        GIR_EraseFromParent, /*InsnID*/0,
4504
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4505
144
        // GIR_Coverage, 348,
4506
144
        GIR_Done,
4507
144
      // Label 385: @9099
4508
144
      GIM_Try, /*On fail goto*//*Label 386*/ 9139, // Rule ID 349 //
4509
144
        GIM_CheckFeatures, GIFBS_HasDSP,
4510
144
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbla,
4511
144
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4512
144
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4513
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4514
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4515
144
        // (intrinsic_wo_chain:{ *:[v2i16] } 3509:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4516
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBLA,
4517
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4518
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4519
144
        GIR_EraseFromParent, /*InsnID*/0,
4520
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4521
144
        // GIR_Coverage, 349,
4522
144
        GIR_Done,
4523
144
      // Label 386: @9139
4524
144
      GIM_Try, /*On fail goto*//*Label 387*/ 9179, // Rule ID 350 //
4525
144
        GIM_CheckFeatures, GIFBS_HasDSP,
4526
144
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbra,
4527
144
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4528
144
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4529
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4530
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4531
144
        // (intrinsic_wo_chain:{ *:[v2i16] } 3511:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4532
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBRA,
4533
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4534
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4535
144
        GIR_EraseFromParent, /*InsnID*/0,
4536
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4537
144
        // GIR_Coverage, 350,
4538
144
        GIR_Done,
4539
144
      // Label 387: @9179
4540
144
      GIM_Try, /*On fail goto*//*Label 388*/ 9219, // Rule ID 398 //
4541
144
        GIM_CheckFeatures, GIFBS_HasDSP,
4542
144
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_bitrev,
4543
144
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4544
144
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4545
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4546
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
4547
144
        // (intrinsic_wo_chain:{ *:[i32] } 3078:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (BITREV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
4548
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BITREV,
4549
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4550
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4551
144
        GIR_EraseFromParent, /*InsnID*/0,
4552
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4553
144
        // GIR_Coverage, 398,
4554
144
        GIR_Done,
4555
144
      // Label 388: @9219
4556
144
      GIM_Try, /*On fail goto*//*Label 389*/ 9259, // Rule ID 402 //
4557
144
        GIM_CheckFeatures, GIFBS_HasDSP,
4558
144
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
4559
144
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
4560
144
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4561
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4562
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
4563
144
        // (intrinsic_wo_chain:{ *:[v4i8] } 3523:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (REPLV_QB:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rt)
4564
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_QB,
4565
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4566
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4567
144
        GIR_EraseFromParent, /*InsnID*/0,
4568
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4569
144
        // GIR_Coverage, 402,
4570
144
        GIR_Done,
4571
144
      // Label 389: @9259
4572
144
      GIM_Try, /*On fail goto*//*Label 390*/ 9299, // Rule ID 403 //
4573
144
        GIM_CheckFeatures, GIFBS_HasDSP,
4574
144
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
4575
144
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4576
144
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4577
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4578
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
4579
144
        // (intrinsic_wo_chain:{ *:[v2i16] } 3522:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (REPLV_PH:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rt)
4580
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_PH,
4581
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4582
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4583
144
        GIR_EraseFromParent, /*InsnID*/0,
4584
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4585
144
        // GIR_Coverage, 403,
4586
144
        GIR_Done,
4587
144
      // Label 390: @9299
4588
144
      GIM_Try, /*On fail goto*//*Label 391*/ 9339, // Rule ID 648 //
4589
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4590
144
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fclass_w,
4591
144
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4592
144
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4593
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4594
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4595
144
        // (intrinsic_wo_chain:{ *:[v4i32] } 3230:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FCLASS_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
4596
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCLASS_W,
4597
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4598
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4599
144
        GIR_EraseFromParent, /*InsnID*/0,
4600
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4601
144
        // GIR_Coverage, 648,
4602
144
        GIR_Done,
4603
144
      // Label 391: @9339
4604
144
      GIM_Try, /*On fail goto*//*Label 392*/ 9379, // Rule ID 649 //
4605
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4606
144
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fclass_d,
4607
144
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4608
144
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
4609
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4610
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
4611
144
        // (intrinsic_wo_chain:{ *:[v2i64] } 3229:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FCLASS_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
4612
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCLASS_D,
4613
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4614
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4615
144
        GIR_EraseFromParent, /*InsnID*/0,
4616
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4617
144
        // GIR_Coverage, 649,
4618
144
        GIR_Done,
4619
144
      // Label 392: @9379
4620
144
      GIM_Try, /*On fail goto*//*Label 393*/ 9419, // Rule ID 672 //
4621
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4622
144
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupl_w,
4623
144
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4624
144
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4625
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4626
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
4627
144
        // (intrinsic_wo_chain:{ *:[v4f32] } 3256:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws)  =>  (FEXUPL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
4628
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPL_W,
4629
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4630
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4631
144
        GIR_EraseFromParent, /*InsnID*/0,
4632
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4633
144
        // GIR_Coverage, 672,
4634
144
        GIR_Done,
4635
144
      // Label 393: @9419
4636
144
      GIM_Try, /*On fail goto*//*Label 394*/ 9459, // Rule ID 673 //
4637
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4638
144
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupl_d,
4639
144
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4640
144
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4641
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4642
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4643
144
        // (intrinsic_wo_chain:{ *:[v2f64] } 3255:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FEXUPL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
4644
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPL_D,
4645
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4646
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4647
144
        GIR_EraseFromParent, /*InsnID*/0,
4648
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4649
144
        // GIR_Coverage, 673,
4650
144
        GIR_Done,
4651
144
      // Label 394: @9459
4652
144
      GIM_Try, /*On fail goto*//*Label 395*/ 9499, // Rule ID 674 //
4653
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4654
144
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupr_w,
4655
144
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4656
144
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4657
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4658
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
4659
144
        // (intrinsic_wo_chain:{ *:[v4f32] } 3258:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws)  =>  (FEXUPR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
4660
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPR_W,
4661
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4662
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4663
144
        GIR_EraseFromParent, /*InsnID*/0,
4664
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4665
144
        // GIR_Coverage, 674,
4666
144
        GIR_Done,
4667
144
      // Label 395: @9499
4668
144
      GIM_Try, /*On fail goto*//*Label 396*/ 9539, // Rule ID 675 //
4669
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4670
144
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupr_d,
4671
144
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4672
144
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4673
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4674
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4675
144
        // (intrinsic_wo_chain:{ *:[v2f64] } 3257:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FEXUPR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
4676
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPR_D,
4677
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4678
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4679
144
        GIR_EraseFromParent, /*InsnID*/0,
4680
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4681
144
        // GIR_Coverage, 675,
4682
144
        GIR_Done,
4683
144
      // Label 396: @9539
4684
144
      GIM_Try, /*On fail goto*//*Label 397*/ 9579, // Rule ID 680 //
4685
144
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4686
144
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffql_w,
4687
144
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4688
144
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4689
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4690
144
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
4691
144
        // (intrinsic_wo_chain:{ *:[v4f32] } 3264:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws)  =>  (FFQL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
4692
144
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQL_W,
4693
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4694
144
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4695
144
        GIR_EraseFromParent, /*InsnID*/0,
4696
144
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4697
144
        // GIR_Coverage, 680,
4698
144
        GIR_Done,
4699
144
      // Label 397: @9579
4700
144
      GIM_Try, /*On fail goto*//*Label 398*/ 9619, // Rule ID 681 //
4701
</