Coverage Report

Created: 2019-02-15 18:59

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Mips/MipsGenGlobalISel.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Global Instruction Selector for the Mips target                            *|
4
|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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9
#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10
const unsigned MAX_SUBTARGET_PREDICATES = 42;
11
using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
12
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
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#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15
  mutable MatcherState State;
16
  typedef ComplexRendererFns(MipsInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17
  typedef void(MipsInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const;
18
  const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
19
  static MipsInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20
  static MipsInstructionSelector::CustomRendererFn CustomRenderers[];
21
  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22
  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23
  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24
  const int64_t *getMatchTable() const override;
25
  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
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#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
27
28
#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
29
, State(0),
30
ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
31
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
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#ifdef GET_GLOBALISEL_IMPL
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// Bits for subtarget features that participate in instruction matching.
35
enum SubtargetFeatureBits : uint8_t {
36
  Feature_HasMips2Bit = 7,
37
  Feature_HasMips3Bit = 17,
38
  Feature_HasMips4_32Bit = 27,
39
  Feature_NotMips4_32Bit = 28,
40
  Feature_HasMips4_32r2Bit = 18,
41
  Feature_HasMips32Bit = 3,
42
  Feature_HasMips32r2Bit = 6,
43
  Feature_HasMips32r6Bit = 29,
44
  Feature_NotMips32r6Bit = 4,
45
  Feature_IsGP64bitBit = 22,
46
  Feature_IsPTR64bitBit = 24,
47
  Feature_HasMips64Bit = 25,
48
  Feature_HasMips64r2Bit = 23,
49
  Feature_HasMips64r6Bit = 30,
50
  Feature_NotMips64r6Bit = 5,
51
  Feature_InMips16ModeBit = 31,
52
  Feature_NotInMips16ModeBit = 0,
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  Feature_HasCnMipsBit = 26,
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  Feature_NotCnMipsBit = 8,
55
  Feature_IsN64Bit = 38,
56
  Feature_RelocNotPICBit = 9,
57
  Feature_RelocPICBit = 37,
58
  Feature_NoNaNsFPMathBit = 21,
59
  Feature_UseAbsBit = 14,
60
  Feature_HasStdEncBit = 1,
61
  Feature_NotDSPBit = 11,
62
  Feature_InMicroMipsBit = 35,
63
  Feature_NotInMicroMipsBit = 2,
64
  Feature_IsLEBit = 40,
65
  Feature_IsBEBit = 41,
66
  Feature_IsNotNaClBit = 19,
67
  Feature_HasEVABit = 36,
68
  Feature_HasMSABit = 34,
69
  Feature_HasMadd4Bit = 20,
70
  Feature_UseIndirectJumpsHazardBit = 12,
71
  Feature_NoIndirectJumpGuardsBit = 10,
72
  Feature_AllowFPOpFusionBit = 39,
73
  Feature_IsFP64bitBit = 16,
74
  Feature_NotFP64bitBit = 15,
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  Feature_IsNotSoftFloatBit = 13,
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  Feature_HasDSPBit = 32,
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  Feature_HasDSPR2Bit = 33,
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};
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PredicateBitset MipsInstructionSelector::
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10.7k
computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const {
82
10.7k
  PredicateBitset Features;
83
10.7k
  if (Subtarget->hasMips2())
84
10.7k
    Features[Feature_HasMips2Bit] = 1;
85
10.7k
  if (Subtarget->hasMips3())
86
3.71k
    Features[Feature_HasMips3Bit] = 1;
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10.7k
  if (Subtarget->hasMips4_32())
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10.4k
    Features[Feature_HasMips4_32Bit] = 1;
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10.7k
  if (!Subtarget->hasMips4_32())
90
271
    Features[Feature_NotMips4_32Bit] = 1;
91
10.7k
  if (Subtarget->hasMips4_32r2())
92
6.19k
    Features[Feature_HasMips4_32r2Bit] = 1;
93
10.7k
  if (Subtarget->hasMips32())
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10.1k
    Features[Feature_HasMips32Bit] = 1;
95
10.7k
  if (Subtarget->hasMips32r2())
96
4.42k
    Features[Feature_HasMips32r2Bit] = 1;
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10.7k
  if (Subtarget->hasMips32r6())
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1.41k
    Features[Feature_HasMips32r6Bit] = 1;
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10.7k
  if (!Subtarget->hasMips32r6())
100
9.31k
    Features[Feature_NotMips32r6Bit] = 1;
101
10.7k
  if (Subtarget->isGP64bit())
102
3.71k
    Features[Feature_IsGP64bitBit] = 1;
103
10.7k
  if (Subtarget->isABI_N64())
104
3.19k
    Features[Feature_IsPTR64bitBit] = 1;
105
10.7k
  if (Subtarget->hasMips64())
106
3.21k
    Features[Feature_HasMips64Bit] = 1;
107
10.7k
  if (Subtarget->hasMips64r2())
108
1.80k
    Features[Feature_HasMips64r2Bit] = 1;
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10.7k
  if (Subtarget->hasMips64r6())
110
530
    Features[Feature_HasMips64r6Bit] = 1;
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10.7k
  if (!Subtarget->hasMips64r6())
112
10.1k
    Features[Feature_NotMips64r6Bit] = 1;
113
10.7k
  if (Subtarget->inMips16Mode())
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2.77k
    Features[Feature_InMips16ModeBit] = 1;
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10.7k
  if (!Subtarget->inMips16Mode())
116
7.94k
    Features[Feature_NotInMips16ModeBit] = 1;
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10.7k
  if (Subtarget->hasCnMips())
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20
    Features[Feature_HasCnMipsBit] = 1;
119
10.7k
  if (!Subtarget->hasCnMips())
120
10.7k
    Features[Feature_NotCnMipsBit] = 1;
121
10.7k
  if (Subtarget->isABI_N64())
122
3.19k
    Features[Feature_IsN64Bit] = 1;
123
10.7k
  if (!TM.isPositionIndependent())
124
6.43k
    Features[Feature_RelocNotPICBit] = 1;
125
10.7k
  if (TM.isPositionIndependent())
126
4.28k
    Features[Feature_RelocPICBit] = 1;
127
10.7k
  if (TM.Options.NoNaNsFPMath)
128
150
    Features[Feature_NoNaNsFPMathBit] = 1;
129
10.7k
  if (Subtarget->inAbs2008Mode() ||
TM.Options.NoNaNsFPMath9.25k
)
130
1.60k
    Features[Feature_UseAbsBit] = 1;
131
10.7k
  if (Subtarget->hasStandardEncoding())
132
7.18k
    Features[Feature_HasStdEncBit] = 1;
133
10.7k
  if (!Subtarget->hasDSP())
134
10.6k
    Features[Feature_NotDSPBit] = 1;
135
10.7k
  if (Subtarget->inMicroMipsMode())
136
761
    Features[Feature_InMicroMipsBit] = 1;
137
10.7k
  if (!Subtarget->inMicroMipsMode())
138
9.96k
    Features[Feature_NotInMicroMipsBit] = 1;
139
10.7k
  if (Subtarget->isLittle())
140
5.25k
    Features[Feature_IsLEBit] = 1;
141
10.7k
  if (!Subtarget->isLittle())
142
5.47k
    Features[Feature_IsBEBit] = 1;
143
10.7k
  if (!Subtarget->isTargetNaCl())
144
10.6k
    Features[Feature_IsNotNaClBit] = 1;
145
10.7k
  if (Subtarget->hasEVA())
146
10
    Features[Feature_HasEVABit] = 1;
147
10.7k
  if (Subtarget->hasMSA())
148
947
    Features[Feature_HasMSABit] = 1;
149
10.7k
  if (!Subtarget->disableMadd4())
150
10.6k
    Features[Feature_HasMadd4Bit] = 1;
151
10.7k
  if (Subtarget->useIndirectJumpsHazard())
152
143
    Features[Feature_UseIndirectJumpsHazardBit] = 1;
153
10.7k
  if (!Subtarget->useIndirectJumpsHazard())
154
10.5k
    Features[Feature_NoIndirectJumpGuardsBit] = 1;
155
10.7k
  if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast)
156
5
    Features[Feature_AllowFPOpFusionBit] = 1;
157
10.7k
  if (Subtarget->isFP64bit())
158
5.52k
    Features[Feature_IsFP64bitBit] = 1;
159
10.7k
  if (!Subtarget->isFP64bit())
160
5.20k
    Features[Feature_NotFP64bitBit] = 1;
161
10.7k
  if (!Subtarget->useSoftFloat())
162
10.4k
    Features[Feature_IsNotSoftFloatBit] = 1;
163
10.7k
  if (Subtarget->hasDSP())
164
102
    Features[Feature_HasDSPBit] = 1;
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10.7k
  if (Subtarget->hasDSPR2())
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26
    Features[Feature_HasDSPR2Bit] = 1;
167
10.7k
  return Features;
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10.7k
}
169
170
PredicateBitset MipsInstructionSelector::
171
423
computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget, const MachineFunction *MF) const {
172
423
  PredicateBitset Features;
173
423
  return Features;
174
423
}
175
176
// LLT Objects.
177
enum {
178
  GILLT_s16,
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  GILLT_s32,
180
  GILLT_s64,
181
  GILLT_v2s16,
182
  GILLT_v2s64,
183
  GILLT_v4s8,
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  GILLT_v4s32,
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  GILLT_v8s16,
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  GILLT_v16s8,
187
};
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const static size_t NumTypeObjects = 9;
189
const static LLT TypeObjects[] = {
190
  LLT::scalar(16),
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  LLT::scalar(32),
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  LLT::scalar(64),
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  LLT::vector(2, 16),
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  LLT::vector(2, 64),
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  LLT::vector(4, 8),
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  LLT::vector(4, 32),
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  LLT::vector(8, 16),
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  LLT::vector(16, 8),
199
};
200
201
// Feature bitsets.
202
enum {
203
  GIFBS_Invalid,
204
  GIFBS_HasCnMips,
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  GIFBS_HasDSP,
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  GIFBS_HasDSPR2,
207
  GIFBS_HasMSA,
208
  GIFBS_InMicroMips,
209
  GIFBS_InMips16Mode,
210
  GIFBS_IsFP64bit,
211
  GIFBS_NotFP64bit,
212
  GIFBS_HasDSP_InMicroMips,
213
  GIFBS_HasDSP_NotInMicroMips,
214
  GIFBS_HasDSPR2_InMicroMips,
215
  GIFBS_HasMSA_HasStdEnc,
216
  GIFBS_HasMSA_IsBE,
217
  GIFBS_HasMSA_IsLE,
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  GIFBS_HasMips32r6_HasStdEnc,
219
  GIFBS_HasMips32r6_InMicroMips,
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  GIFBS_HasMips64r2_HasStdEnc,
221
  GIFBS_HasMips64r6_HasStdEnc,
222
  GIFBS_HasStdEnc_IsNotSoftFloat,
223
  GIFBS_HasStdEnc_NotInMicroMips,
224
  GIFBS_HasStdEnc_NotMips4_32,
225
  GIFBS_InMicroMips_IsFP64bit,
226
  GIFBS_InMicroMips_IsNotSoftFloat,
227
  GIFBS_InMicroMips_NotFP64bit,
228
  GIFBS_InMicroMips_NotMips32r6,
229
  GIFBS_IsGP64bit_NotInMips16Mode,
230
  GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
231
  GIFBS_HasMSA_HasMips64_HasStdEnc,
232
  GIFBS_HasMips3_HasStdEnc_IsGP64bit,
233
  GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
234
  GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips,
235
  GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
236
  GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
237
  GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
238
  GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips,
239
  GIFBS_HasStdEnc_IsFP64bit_NotMips4_32,
240
  GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
241
  GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips,
242
  GIFBS_HasStdEnc_NotFP64bit_NotMips4_32,
243
  GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC,
244
  GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
245
  GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
246
  GIFBS_InMicroMips_IsNotSoftFloat_UseAbs,
247
  GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
248
  GIFBS_InMicroMips_NotMips32r6_RelocNotPIC,
249
  GIFBS_InMicroMips_NotMips32r6_RelocPIC,
250
  GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
251
  GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
252
  GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
253
  GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
254
  GIFBS_HasMips64_HasStdEnc_NotInMicroMips_NotMips64r6,
255
  GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips,
256
  GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
257
  GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
258
  GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips_UseAbs,
259
  GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
260
  GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
261
  GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
262
  GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
263
  GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_UseAbs,
264
  GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_UseAbs,
265
  GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotMips32r6_NotMips32r6,
266
  GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
267
  GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
268
  GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
269
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
270
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
271
  GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6_NotMips32r6,
272
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
273
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
274
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
275
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
276
};
277
const static PredicateBitset FeatureBitsets[] {
278
  {}, // GIFBS_Invalid
279
  {Feature_HasCnMipsBit, },
280
  {Feature_HasDSPBit, },
281
  {Feature_HasDSPR2Bit, },
282
  {Feature_HasMSABit, },
283
  {Feature_InMicroMipsBit, },
284
  {Feature_InMips16ModeBit, },
285
  {Feature_IsFP64bitBit, },
286
  {Feature_NotFP64bitBit, },
287
  {Feature_HasDSPBit, Feature_InMicroMipsBit, },
288
  {Feature_HasDSPBit, Feature_NotInMicroMipsBit, },
289
  {Feature_HasDSPR2Bit, Feature_InMicroMipsBit, },
290
  {Feature_HasMSABit, Feature_HasStdEncBit, },
291
  {Feature_HasMSABit, Feature_IsBEBit, },
292
  {Feature_HasMSABit, Feature_IsLEBit, },
293
  {Feature_HasMips32r6Bit, Feature_HasStdEncBit, },
294
  {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, },
295
  {Feature_HasMips64r2Bit, Feature_HasStdEncBit, },
296
  {Feature_HasMips64r6Bit, Feature_HasStdEncBit, },
297
  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },
298
  {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
299
  {Feature_HasStdEncBit, Feature_NotMips4_32Bit, },
300
  {Feature_InMicroMipsBit, Feature_IsFP64bitBit, },
301
  {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
302
  {Feature_InMicroMipsBit, Feature_NotFP64bitBit, },
303
  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },
304
  {Feature_IsGP64bitBit, Feature_NotInMips16ModeBit, },
305
  {Feature_AllowFPOpFusionBit, Feature_HasMSABit, Feature_HasStdEncBit, },
306
  {Feature_HasMSABit, Feature_HasMips64Bit, Feature_HasStdEncBit, },
307
  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, },
308
  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
309
  {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
310
  {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
311
  {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
312
  {Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
313
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, },
314
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, },
315
  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
316
  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
317
  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, },
318
  {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_RelocNotPICBit, },
319
  {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },
320
  {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, },
321
  {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_UseAbsBit, },
322
  {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, },
323
  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocNotPICBit, },
324
  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocPICBit, },
325
  {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
326
  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
327
  {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
328
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
329
  {Feature_HasMips64Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips64r6Bit, },
330
  {Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
331
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
332
  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
333
  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, },
334
  {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
335
  {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
336
  {Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
337
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
338
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, },
339
  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, },
340
  {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotMips32r6Bit, Feature_NotMips32r6Bit, },
341
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
342
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
343
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
344
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
345
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
346
  {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips32r6Bit, },
347
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
348
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
349
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
350
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
351
};
352
353
// ComplexPattern predicates.
354
enum {
355
  GICP_Invalid,
356
};
357
// See constructor for table contents
358
359
// PatFrag predicates.
360
enum {
361
  GIPFP_I64_Predicate_immLi16 = GIPFP_I64_Invalid + 1,
362
  GIPFP_I64_Predicate_immSExt10,
363
  GIPFP_I64_Predicate_immSExt6,
364
  GIPFP_I64_Predicate_immSExtAddiur2,
365
  GIPFP_I64_Predicate_immSExtAddius5,
366
  GIPFP_I64_Predicate_immZExt1,
367
  GIPFP_I64_Predicate_immZExt10,
368
  GIPFP_I64_Predicate_immZExt1Ptr,
369
  GIPFP_I64_Predicate_immZExt2,
370
  GIPFP_I64_Predicate_immZExt2Lsa,
371
  GIPFP_I64_Predicate_immZExt2Ptr,
372
  GIPFP_I64_Predicate_immZExt2Shift,
373
  GIPFP_I64_Predicate_immZExt3,
374
  GIPFP_I64_Predicate_immZExt3Ptr,
375
  GIPFP_I64_Predicate_immZExt4,
376
  GIPFP_I64_Predicate_immZExt4Ptr,
377
  GIPFP_I64_Predicate_immZExt5,
378
  GIPFP_I64_Predicate_immZExt5_64,
379
  GIPFP_I64_Predicate_immZExt6,
380
  GIPFP_I64_Predicate_immZExt8,
381
  GIPFP_I64_Predicate_immZExtAndi16,
382
  GIPFP_I64_Predicate_immi32Cst15,
383
  GIPFP_I64_Predicate_immi32Cst31,
384
  GIPFP_I64_Predicate_immi32Cst7,
385
};
386
54
bool MipsInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
387
54
  switch (PredicateID) {
388
54
  case GIPFP_I64_Predicate_immLi16: {
389
0
    return Imm >= -1 && Imm <= 126;
390
54
    
llvm_unreachable0
("ImmediateCode should have returned");
391
54
    
return false0
;
392
54
  }
393
54
  case GIPFP_I64_Predicate_immSExt10: {
394
0
    return isInt<10>(Imm);
395
54
    
llvm_unreachable0
("ImmediateCode should have returned");
396
54
    
return false0
;
397
54
  }
398
54
  case GIPFP_I64_Predicate_immSExt6: {
399
0
    return isInt<6>(Imm);
400
54
    
llvm_unreachable0
("ImmediateCode should have returned");
401
54
    
return false0
;
402
54
  }
403
54
  case GIPFP_I64_Predicate_immSExtAddiur2: {
404
0
    return Imm == 1 || Imm == -1 ||
405
0
                                           ((Imm % 4 == 0) &&
406
0
                                            Imm < 28 && Imm > 0);
407
54
    
llvm_unreachable0
("ImmediateCode should have returned");
408
54
    
return false0
;
409
54
  }
410
54
  case GIPFP_I64_Predicate_immSExtAddius5: {
411
0
    return Imm >= -8 && Imm <= 7;
412
54
    
llvm_unreachable0
("ImmediateCode should have returned");
413
54
    
return false0
;
414
54
  }
415
54
  case GIPFP_I64_Predicate_immZExt1: {
416
0
    return isUInt<1>(Imm);
417
54
    
llvm_unreachable0
("ImmediateCode should have returned");
418
54
    
return false0
;
419
54
  }
420
54
  case GIPFP_I64_Predicate_immZExt10: {
421
0
    return isUInt<10>(Imm);
422
54
    
llvm_unreachable0
("ImmediateCode should have returned");
423
54
    
return false0
;
424
54
  }
425
54
  case GIPFP_I64_Predicate_immZExt1Ptr: {
426
0
    return isUInt<1>(Imm);
427
54
    
llvm_unreachable0
("ImmediateCode should have returned");
428
54
    
return false0
;
429
54
  }
430
54
  case GIPFP_I64_Predicate_immZExt2: {
431
0
    return isUInt<2>(Imm);
432
54
    
llvm_unreachable0
("ImmediateCode should have returned");
433
54
    
return false0
;
434
54
  }
435
54
  case GIPFP_I64_Predicate_immZExt2Lsa: {
436
0
    return isUInt<2>(Imm - 1);
437
54
    
llvm_unreachable0
("ImmediateCode should have returned");
438
54
    
return false0
;
439
54
  }
440
54
  case GIPFP_I64_Predicate_immZExt2Ptr: {
441
0
    return isUInt<2>(Imm);
442
54
    
llvm_unreachable0
("ImmediateCode should have returned");
443
54
    
return false0
;
444
54
  }
445
54
  case GIPFP_I64_Predicate_immZExt2Shift: {
446
0
    return Imm >= 1 && Imm <= 8;
447
54
    
llvm_unreachable0
("ImmediateCode should have returned");
448
54
    
return false0
;
449
54
  }
450
54
  case GIPFP_I64_Predicate_immZExt3: {
451
0
    return isUInt<3>(Imm);
452
54
    
llvm_unreachable0
("ImmediateCode should have returned");
453
54
    
return false0
;
454
54
  }
455
54
  case GIPFP_I64_Predicate_immZExt3Ptr: {
456
0
    return isUInt<3>(Imm);
457
54
    
llvm_unreachable0
("ImmediateCode should have returned");
458
54
    
return false0
;
459
54
  }
460
54
  case GIPFP_I64_Predicate_immZExt4: {
461
0
    return isUInt<4>(Imm);
462
54
    
llvm_unreachable0
("ImmediateCode should have returned");
463
54
    
return false0
;
464
54
  }
465
54
  case GIPFP_I64_Predicate_immZExt4Ptr: {
466
0
    return isUInt<4>(Imm);
467
54
    
llvm_unreachable0
("ImmediateCode should have returned");
468
54
    
return false0
;
469
54
  }
470
54
  case GIPFP_I64_Predicate_immZExt5: {
471
54
    return Imm == (Imm & 0x1f);
472
54
    
llvm_unreachable0
("ImmediateCode should have returned");
473
54
    
return false0
;
474
54
  }
475
54
  case GIPFP_I64_Predicate_immZExt5_64: {
476
0
     return Imm == (Imm & 0x1f); 
477
54
    
llvm_unreachable0
("ImmediateCode should have returned");
478
54
    
return false0
;
479
54
  }
480
54
  case GIPFP_I64_Predicate_immZExt6: {
481
0
    return Imm == (Imm & 0x3f);
482
54
    
llvm_unreachable0
("ImmediateCode should have returned");
483
54
    
return false0
;
484
54
  }
485
54
  case GIPFP_I64_Predicate_immZExt8: {
486
0
    return isUInt<8>(Imm);
487
54
    
llvm_unreachable0
("ImmediateCode should have returned");
488
54
    
return false0
;
489
54
  }
490
54
  case GIPFP_I64_Predicate_immZExtAndi16: {
491
0
    return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
492
0
            Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
493
0
            Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
494
54
    
llvm_unreachable0
("ImmediateCode should have returned");
495
54
    
return false0
;
496
54
  }
497
54
  case GIPFP_I64_Predicate_immi32Cst15: {
498
0
    return isUInt<32>(Imm) && Imm == 15;
499
54
    
llvm_unreachable0
("ImmediateCode should have returned");
500
54
    
return false0
;
501
54
  }
502
54
  case GIPFP_I64_Predicate_immi32Cst31: {
503
0
    return isUInt<32>(Imm) && Imm == 31;
504
54
    
llvm_unreachable0
("ImmediateCode should have returned");
505
54
    
return false0
;
506
54
  }
507
54
  case GIPFP_I64_Predicate_immi32Cst7: {
508
0
    return isUInt<32>(Imm) && Imm == 7;
509
54
    
llvm_unreachable0
("ImmediateCode should have returned");
510
54
    
return false0
;
511
0
  }
512
0
  }
513
0
  llvm_unreachable("Unknown predicate");
514
0
  return false;
515
0
}
516
0
bool MipsInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
517
0
  llvm_unreachable("Unknown predicate");
518
0
  return false;
519
0
}
520
0
bool MipsInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
521
0
  llvm_unreachable("Unknown predicate");
522
0
  return false;
523
0
}
524
0
bool MipsInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
525
0
  const MachineFunction &MF = *MI.getParent()->getParent();
526
0
  const MachineRegisterInfo &MRI = MF.getRegInfo();
527
0
  (void)MRI;
528
0
  llvm_unreachable("Unknown predicate");
529
0
  return false;
530
0
}
531
532
MipsInstructionSelector::ComplexMatcherMemFn
533
MipsInstructionSelector::ComplexPredicateFns[] = {
534
  nullptr, // GICP_Invalid
535
};
536
537
// Custom renderers.
538
enum {
539
  GICR_Invalid,
540
};
541
MipsInstructionSelector::CustomRendererFn
542
MipsInstructionSelector::CustomRenderers[] = {
543
  nullptr, // GICP_Invalid
544
};
545
546
423
bool MipsInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
547
423
  MachineFunction &MF = *I.getParent()->getParent();
548
423
  MachineRegisterInfo &MRI = MF.getRegInfo();
549
423
  // FIXME: This should be computed on a per-function basis rather than per-insn.
550
423
  AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
551
423
  const PredicateBitset AvailableFeatures = getAvailableFeatures();
552
423
  NewMIVector OutMIs;
553
423
  State.MIs.clear();
554
423
  State.MIs.push_back(&I);
555
423
556
423
  if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
557
217
    return true;
558
217
  }
559
206
560
206
  return false;
561
206
}
562
563
423
const int64_t *MipsInstructionSelector::getMatchTable() const {
564
423
  constexpr static int64_t MatchTable0[] = {
565
423
    GIM_SwitchOpcode, /*MI*/0, /*[*/35, 145, /*)*//*default:*//*Label 44*/ 38649,
566
423
    /*TargetOpcode::G_ADD*//*Label 0*/ 115,
567
423
    /*TargetOpcode::G_SUB*//*Label 1*/ 1292,
568
423
    /*TargetOpcode::G_MUL*//*Label 2*/ 1904,
569
423
    /*TargetOpcode::G_SDIV*//*Label 3*/ 2280,
570
423
    /*TargetOpcode::G_UDIV*//*Label 4*/ 2501,
571
423
    /*TargetOpcode::G_SREM*//*Label 5*/ 2722,
572
423
    /*TargetOpcode::G_UREM*//*Label 6*/ 2943,
573
423
    /*TargetOpcode::G_AND*//*Label 7*/ 3164,
574
423
    /*TargetOpcode::G_OR*//*Label 8*/ 3608,
575
423
    /*TargetOpcode::G_XOR*//*Label 9*/ 3910, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
576
423
    /*TargetOpcode::G_BITCAST*//*Label 10*/ 4704, 0, 0,
577
423
    /*TargetOpcode::G_LOAD*//*Label 11*/ 8357,
578
423
    /*TargetOpcode::G_SEXTLOAD*//*Label 12*/ 8423,
579
423
    /*TargetOpcode::G_ZEXTLOAD*//*Label 13*/ 8489, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
580
423
    /*TargetOpcode::G_INTRINSIC*//*Label 14*/ 8555,
581
423
    /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 15*/ 25066, 0,
582
423
    /*TargetOpcode::G_TRUNC*//*Label 16*/ 29990,
583
423
    /*TargetOpcode::G_CONSTANT*//*Label 17*/ 30047, 0, 0, 0,
584
423
    /*TargetOpcode::G_SEXT*//*Label 18*/ 30107,
585
423
    /*TargetOpcode::G_ZEXT*//*Label 19*/ 30135,
586
423
    /*TargetOpcode::G_SHL*//*Label 20*/ 30220,
587
423
    /*TargetOpcode::G_LSHR*//*Label 21*/ 30744,
588
423
    /*TargetOpcode::G_ASHR*//*Label 22*/ 31268, 0, 0,
589
423
    /*TargetOpcode::G_SELECT*//*Label 23*/ 31749, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
590
423
    /*TargetOpcode::G_FADD*//*Label 24*/ 33203,
591
423
    /*TargetOpcode::G_FSUB*//*Label 25*/ 34082,
592
423
    /*TargetOpcode::G_FMUL*//*Label 26*/ 34658,
593
423
    /*TargetOpcode::G_FMA*//*Label 27*/ 35095,
594
423
    /*TargetOpcode::G_FDIV*//*Label 28*/ 35185, 0, 0, 0,
595
423
    /*TargetOpcode::G_FEXP2*//*Label 29*/ 35436, 0,
596
423
    /*TargetOpcode::G_FLOG2*//*Label 30*/ 35494, 0,
597
423
    /*TargetOpcode::G_FNEG*//*Label 31*/ 35552,
598
423
    /*TargetOpcode::G_FPEXT*//*Label 32*/ 36848,
599
423
    /*TargetOpcode::G_FPTRUNC*//*Label 33*/ 36997,
600
423
    /*TargetOpcode::G_FPTOSI*//*Label 34*/ 37125,
601
423
    /*TargetOpcode::G_FPTOUI*//*Label 35*/ 37183,
602
423
    /*TargetOpcode::G_SITOFP*//*Label 36*/ 37241,
603
423
    /*TargetOpcode::G_UITOFP*//*Label 37*/ 37394,
604
423
    /*TargetOpcode::G_FABS*//*Label 38*/ 37452, 0, 0, 0,
605
423
    /*TargetOpcode::G_BR*//*Label 39*/ 37635, 0, 0, 0, 0, 0,
606
423
    /*TargetOpcode::G_CTLZ*//*Label 40*/ 37720, 0,
607
423
    /*TargetOpcode::G_CTPOP*//*Label 41*/ 38155,
608
423
    /*TargetOpcode::G_BSWAP*//*Label 42*/ 38314, 0, 0, 0,
609
423
    /*TargetOpcode::G_FSQRT*//*Label 43*/ 38466,
610
423
    // Label 0: @115
611
423
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 53*/ 1291,
612
423
    /*GILLT_s32*//*Label 45*/ 129,
613
423
    /*GILLT_s64*//*Label 46*/ 478,
614
423
    /*GILLT_v2s16*//*Label 47*/ 641,
615
423
    /*GILLT_v2s64*//*Label 48*/ 668,
616
423
    /*GILLT_v4s8*//*Label 49*/ 817,
617
423
    /*GILLT_v4s32*//*Label 50*/ 844,
618
423
    /*GILLT_v8s16*//*Label 51*/ 993,
619
423
    /*GILLT_v16s8*//*Label 52*/ 1142,
620
423
    // Label 45: @129
621
423
    GIM_Try, /*On fail goto*//*Label 54*/ 477,
622
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
623
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
624
423
      GIM_Try, /*On fail goto*//*Label 55*/ 207, // Rule ID 2310 //
625
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
626
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
627
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
628
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
629
423
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
630
423
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
631
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
632
423
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
633
423
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
634
423
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
635
423
        // MIs[2] Operand 1
636
423
        // No operand predicates
637
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
638
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
639
423
        GIM_CheckIsSafeToFold, /*InsnID*/2,
640
423
        // (add:{ *:[i32] } (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR32Opnd:{ *:[i32] }:$rt)  =>  (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
641
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA,
642
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
643
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
644
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
645
423
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
646
423
        GIR_EraseFromParent, /*InsnID*/0,
647
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
648
423
        // GIR_Coverage, 2310,
649
423
        GIR_Done,
650
423
      // Label 55: @207
651
423
      GIM_Try, /*On fail goto*//*Label 56*/ 275, // Rule ID 802 //
652
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
653
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
654
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
655
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
656
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
657
423
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
658
423
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
659
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
660
423
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
661
423
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
662
423
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
663
423
        // MIs[2] Operand 1
664
423
        // No operand predicates
665
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
666
423
        GIM_CheckIsSafeToFold, /*InsnID*/2,
667
423
        // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa))  =>  (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
668
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA,
669
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
670
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
671
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
672
423
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
673
423
        GIR_EraseFromParent, /*InsnID*/0,
674
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
675
423
        // GIR_Coverage, 802,
676
423
        GIR_Done,
677
423
      // Label 56: @275
678
423
      GIM_Try, /*On fail goto*//*Label 57*/ 318, // Rule ID 2084 //
679
423
        GIM_CheckFeatures, GIFBS_InMicroMips,
680
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
681
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
682
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
683
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
684
423
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExtAddiur2,
685
423
        // MIs[1] Operand 1
686
423
        // No operand predicates
687
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
688
423
        // (add:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)  =>  (ADDIUR2_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)
689
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUR2_MM,
690
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
691
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
692
423
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
693
423
        GIR_EraseFromParent, /*InsnID*/0,
694
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
695
423
        // GIR_Coverage, 2084,
696
423
        GIR_Done,
697
423
      // Label 57: @318
698
423
      GIM_Try, /*On fail goto*//*Label 58*/ 361, // Rule ID 2085 //
699
423
        GIM_CheckFeatures, GIFBS_InMicroMips,
700
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
701
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
702
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
703
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
704
423
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExtAddius5,
705
423
        // MIs[1] Operand 1
706
423
        // No operand predicates
707
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
708
423
        // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)  =>  (ADDIUS5_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)
709
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUS5_MM,
710
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
711
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
712
423
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
713
423
        GIR_EraseFromParent, /*InsnID*/0,
714
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
715
423
        // GIR_Coverage, 2085,
716
423
        GIR_Done,
717
423
      // Label 58: @361
718
423
      GIM_Try, /*On fail goto*//*Label 59*/ 384, // Rule ID 1174 //
719
423
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
720
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
721
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
722
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
723
423
        // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (ADDU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
724
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU16_MMR6,
725
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
726
423
        // GIR_Coverage, 1174,
727
423
        GIR_Done,
728
423
      // Label 59: @384
729
423
      GIM_Try, /*On fail goto*//*Label 60*/ 407, // Rule ID 34 //
730
423
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
731
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
732
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
733
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
734
423
        // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
735
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDu,
736
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
737
423
        // GIR_Coverage, 34,
738
423
        GIR_Done,
739
423
      // Label 60: @407
740
423
      GIM_Try, /*On fail goto*//*Label 61*/ 430, // Rule ID 1028 //
741
423
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
742
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
743
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
744
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
745
423
        // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (ADDU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
746
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU16_MM,
747
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
748
423
        // GIR_Coverage, 1028,
749
423
        GIR_Done,
750
423
      // Label 61: @430
751
423
      GIM_Try, /*On fail goto*//*Label 62*/ 453, // Rule ID 1040 //
752
423
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
753
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
754
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
755
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
756
423
        // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
757
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDu_MM,
758
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
759
423
        // GIR_Coverage, 1040,
760
423
        GIR_Done,
761
423
      // Label 62: @453
762
423
      GIM_Try, /*On fail goto*//*Label 63*/ 476, // Rule ID 1745 //
763
423
        GIM_CheckFeatures, GIFBS_InMips16Mode,
764
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
765
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
766
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
767
423
        // (add:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (AdduRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
768
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AdduRxRyRz16,
769
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
770
423
        // GIR_Coverage, 1745,
771
423
        GIR_Done,
772
423
      // Label 63: @476
773
423
      GIM_Reject,
774
423
    // Label 54: @477
775
423
    GIM_Reject,
776
423
    // Label 46: @478
777
423
    GIM_Try, /*On fail goto*//*Label 64*/ 640,
778
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
779
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
780
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
781
423
      GIM_Try, /*On fail goto*//*Label 65*/ 556, // Rule ID 2311 //
782
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc,
783
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
784
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
785
423
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
786
423
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
787
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
788
423
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
789
423
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
790
423
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
791
423
        // MIs[2] Operand 1
792
423
        // No operand predicates
793
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
794
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
795
423
        GIM_CheckIsSafeToFold, /*InsnID*/2,
796
423
        // (add:{ *:[i64] } (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR64Opnd:{ *:[i64] }:$rt)  =>  (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
797
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA,
798
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
799
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
800
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
801
423
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
802
423
        GIR_EraseFromParent, /*InsnID*/0,
803
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
804
423
        // GIR_Coverage, 2311,
805
423
        GIR_Done,
806
423
      // Label 65: @556
807
423
      GIM_Try, /*On fail goto*//*Label 66*/ 620, // Rule ID 803 //
808
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc,
809
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
810
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
811
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
812
423
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
813
423
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
814
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
815
423
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
816
423
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
817
423
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
818
423
        // MIs[2] Operand 1
819
423
        // No operand predicates
820
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
821
423
        GIM_CheckIsSafeToFold, /*InsnID*/2,
822
423
        // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa))  =>  (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
823
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA,
824
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
825
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
826
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
827
423
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
828
423
        GIR_EraseFromParent, /*InsnID*/0,
829
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
830
423
        // GIR_Coverage, 803,
831
423
        GIR_Done,
832
423
      // Label 66: @620
833
423
      GIM_Try, /*On fail goto*//*Label 67*/ 639, // Rule ID 180 //
834
423
        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
835
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
836
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
837
423
        // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
838
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DADDu,
839
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
840
423
        // GIR_Coverage, 180,
841
423
        GIR_Done,
842
423
      // Label 67: @639
843
423
      GIM_Reject,
844
423
    // Label 64: @640
845
423
    GIM_Reject,
846
423
    // Label 47: @641
847
423
    GIM_Try, /*On fail goto*//*Label 68*/ 667, // Rule ID 1844 //
848
423
      GIM_CheckFeatures, GIFBS_HasDSP,
849
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
850
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
851
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
852
423
      // (add:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
853
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDQ_PH,
854
423
      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
855
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
856
423
      // GIR_Coverage, 1844,
857
423
      GIR_Done,
858
423
    // Label 68: @667
859
423
    GIM_Reject,
860
423
    // Label 48: @668
861
423
    GIM_Try, /*On fail goto*//*Label 69*/ 816,
862
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
863
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
864
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
865
423
      GIM_Try, /*On fail goto*//*Label 70*/ 739, // Rule ID 2315 //
866
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
867
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
868
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
869
423
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
870
423
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
871
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
872
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
873
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
874
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
875
423
        // (add:{ *:[v2i64] } (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt), MSA128DOpnd:{ *:[v2i64] }:$wd_in)  =>  (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
876
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D,
877
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
878
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
879
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
880
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
881
423
        GIR_EraseFromParent, /*InsnID*/0,
882
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
883
423
        // GIR_Coverage, 2315,
884
423
        GIR_Done,
885
423
      // Label 70: @739
886
423
      GIM_Try, /*On fail goto*//*Label 71*/ 796, // Rule ID 811 //
887
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
888
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
889
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
890
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
891
423
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
892
423
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
893
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
894
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
895
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
896
423
        // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt))  =>  (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
897
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D,
898
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
899
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
900
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
901
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
902
423
        GIR_EraseFromParent, /*InsnID*/0,
903
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
904
423
        // GIR_Coverage, 811,
905
423
        GIR_Done,
906
423
      // Label 71: @796
907
423
      GIM_Try, /*On fail goto*//*Label 72*/ 815, // Rule ID 478 //
908
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
909
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
910
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
911
423
        // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
912
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_D,
913
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
914
423
        // GIR_Coverage, 478,
915
423
        GIR_Done,
916
423
      // Label 72: @815
917
423
      GIM_Reject,
918
423
    // Label 69: @816
919
423
    GIM_Reject,
920
423
    // Label 49: @817
921
423
    GIM_Try, /*On fail goto*//*Label 73*/ 843, // Rule ID 1850 //
922
423
      GIM_CheckFeatures, GIFBS_HasDSP,
923
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
924
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
925
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
926
423
      // (add:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)  =>  (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
927
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU_QB,
928
423
      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
929
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
930
423
      // GIR_Coverage, 1850,
931
423
      GIR_Done,
932
423
    // Label 73: @843
933
423
    GIM_Reject,
934
423
    // Label 50: @844
935
423
    GIM_Try, /*On fail goto*//*Label 74*/ 992,
936
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
937
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
938
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
939
423
      GIM_Try, /*On fail goto*//*Label 75*/ 915, // Rule ID 2314 //
940
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
941
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
942
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
943
423
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
944
423
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
945
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
946
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
947
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
948
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
949
423
        // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt), MSA128WOpnd:{ *:[v4i32] }:$wd_in)  =>  (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
950
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W,
951
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
952
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
953
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
954
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
955
423
        GIR_EraseFromParent, /*InsnID*/0,
956
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
957
423
        // GIR_Coverage, 2314,
958
423
        GIR_Done,
959
423
      // Label 75: @915
960
423
      GIM_Try, /*On fail goto*//*Label 76*/ 972, // Rule ID 810 //
961
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
962
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
963
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
964
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
965
423
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
966
423
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
967
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
968
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
969
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
970
423
        // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt))  =>  (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
971
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W,
972
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
973
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
974
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
975
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
976
423
        GIR_EraseFromParent, /*InsnID*/0,
977
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
978
423
        // GIR_Coverage, 810,
979
423
        GIR_Done,
980
423
      // Label 76: @972
981
423
      GIM_Try, /*On fail goto*//*Label 77*/ 991, // Rule ID 477 //
982
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
983
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
984
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
985
423
        // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
986
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_W,
987
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
988
423
        // GIR_Coverage, 477,
989
423
        GIR_Done,
990
423
      // Label 77: @991
991
423
      GIM_Reject,
992
423
    // Label 74: @992
993
423
    GIM_Reject,
994
423
    // Label 51: @993
995
423
    GIM_Try, /*On fail goto*//*Label 78*/ 1141,
996
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
997
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
998
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
999
423
      GIM_Try, /*On fail goto*//*Label 79*/ 1064, // Rule ID 2313 //
1000
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1001
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1002
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1003
423
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1004
423
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1005
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1006
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1007
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1008
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1009
423
        // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt), MSA128HOpnd:{ *:[v8i16] }:$wd_in)  =>  (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1010
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H,
1011
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1012
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
1013
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1014
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1015
423
        GIR_EraseFromParent, /*InsnID*/0,
1016
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1017
423
        // GIR_Coverage, 2313,
1018
423
        GIR_Done,
1019
423
      // Label 79: @1064
1020
423
      GIM_Try, /*On fail goto*//*Label 80*/ 1121, // Rule ID 809 //
1021
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1022
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1023
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1024
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1025
423
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1026
423
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1027
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1028
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1029
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1030
423
        // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt))  =>  (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1031
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H,
1032
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1033
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1034
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1035
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1036
423
        GIR_EraseFromParent, /*InsnID*/0,
1037
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1038
423
        // GIR_Coverage, 809,
1039
423
        GIR_Done,
1040
423
      // Label 80: @1121
1041
423
      GIM_Try, /*On fail goto*//*Label 81*/ 1140, // Rule ID 476 //
1042
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1043
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1044
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1045
423
        // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1046
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_H,
1047
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1048
423
        // GIR_Coverage, 476,
1049
423
        GIR_Done,
1050
423
      // Label 81: @1140
1051
423
      GIM_Reject,
1052
423
    // Label 78: @1141
1053
423
    GIM_Reject,
1054
423
    // Label 52: @1142
1055
423
    GIM_Try, /*On fail goto*//*Label 82*/ 1290,
1056
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1057
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1058
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1059
423
      GIM_Try, /*On fail goto*//*Label 83*/ 1213, // Rule ID 2312 //
1060
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1061
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1062
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1063
423
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1064
423
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1065
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1066
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1067
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1068
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1069
423
        // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt), MSA128BOpnd:{ *:[v16i8] }:$wd_in)  =>  (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1070
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B,
1071
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1072
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
1073
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1074
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1075
423
        GIR_EraseFromParent, /*InsnID*/0,
1076
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1077
423
        // GIR_Coverage, 2312,
1078
423
        GIR_Done,
1079
423
      // Label 83: @1213
1080
423
      GIM_Try, /*On fail goto*//*Label 84*/ 1270, // Rule ID 808 //
1081
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1082
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1083
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1084
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1085
423
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1086
423
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1087
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1088
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1089
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1090
423
        // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt))  =>  (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1091
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B,
1092
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1093
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1094
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1095
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1096
423
        GIR_EraseFromParent, /*InsnID*/0,
1097
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1098
423
        // GIR_Coverage, 808,
1099
423
        GIR_Done,
1100
423
      // Label 84: @1270
1101
423
      GIM_Try, /*On fail goto*//*Label 85*/ 1289, // Rule ID 475 //
1102
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1103
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1104
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1105
423
        // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1106
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_B,
1107
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1108
423
        // GIR_Coverage, 475,
1109
423
        GIR_Done,
1110
423
      // Label 85: @1289
1111
423
      GIM_Reject,
1112
423
    // Label 82: @1290
1113
423
    GIM_Reject,
1114
423
    // Label 53: @1291
1115
423
    GIM_Reject,
1116
423
    // Label 1: @1292
1117
423
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 94*/ 1903,
1118
423
    /*GILLT_s32*//*Label 86*/ 1306,
1119
423
    /*GILLT_s64*//*Label 87*/ 1465,
1120
423
    /*GILLT_v2s16*//*Label 88*/ 1497,
1121
423
    /*GILLT_v2s64*//*Label 89*/ 1524,
1122
423
    /*GILLT_v4s8*//*Label 90*/ 1612,
1123
423
    /*GILLT_v4s32*//*Label 91*/ 1639,
1124
423
    /*GILLT_v8s16*//*Label 92*/ 1727,
1125
423
    /*GILLT_v16s8*//*Label 93*/ 1815,
1126
423
    // Label 86: @1306
1127
423
    GIM_Try, /*On fail goto*//*Label 95*/ 1464,
1128
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1129
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1130
423
      GIM_Try, /*On fail goto*//*Label 96*/ 1348, // Rule ID 1744 //
1131
423
        GIM_CheckFeatures, GIFBS_InMips16Mode,
1132
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
1133
423
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
1134
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
1135
423
        // (sub:{ *:[i32] } 0:{ *:[i32] }, CPU16Regs:{ *:[i32] }:$r)  =>  (NegRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
1136
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NegRxRy16,
1137
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
1138
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // r
1139
423
        GIR_EraseFromParent, /*InsnID*/0,
1140
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1141
423
        // GIR_Coverage, 1744,
1142
423
        GIR_Done,
1143
423
      // Label 96: @1348
1144
423
      GIM_Try, /*On fail goto*//*Label 97*/ 1371, // Rule ID 1176 //
1145
423
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1146
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
1147
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
1148
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
1149
423
        // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (SUBU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1150
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU16_MMR6,
1151
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1152
423
        // GIR_Coverage, 1176,
1153
423
        GIR_Done,
1154
423
      // Label 97: @1371
1155
423
      GIM_Try, /*On fail goto*//*Label 98*/ 1394, // Rule ID 35 //
1156
423
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
1157
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1158
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1159
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1160
423
        // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1161
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBu,
1162
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1163
423
        // GIR_Coverage, 35,
1164
423
        GIR_Done,
1165
423
      // Label 98: @1394
1166
423
      GIM_Try, /*On fail goto*//*Label 99*/ 1417, // Rule ID 1032 //
1167
423
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
1168
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
1169
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
1170
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
1171
423
        // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (SUBU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1172
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU16_MM,
1173
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1174
423
        // GIR_Coverage, 1032,
1175
423
        GIR_Done,
1176
423
      // Label 99: @1417
1177
423
      GIM_Try, /*On fail goto*//*Label 100*/ 1440, // Rule ID 1041 //
1178
423
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
1179
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1180
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1181
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1182
423
        // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1183
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBu_MM,
1184
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1185
423
        // GIR_Coverage, 1041,
1186
423
        GIR_Done,
1187
423
      // Label 100: @1440
1188
423
      GIM_Try, /*On fail goto*//*Label 101*/ 1463, // Rule ID 1749 //
1189
423
        GIM_CheckFeatures, GIFBS_InMips16Mode,
1190
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
1191
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
1192
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
1193
423
        // (sub:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (SubuRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1194
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SubuRxRyRz16,
1195
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1196
423
        // GIR_Coverage, 1749,
1197
423
        GIR_Done,
1198
423
      // Label 101: @1463
1199
423
      GIM_Reject,
1200
423
    // Label 95: @1464
1201
423
    GIM_Reject,
1202
423
    // Label 87: @1465
1203
423
    GIM_Try, /*On fail goto*//*Label 102*/ 1496, // Rule ID 181 //
1204
423
      GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
1205
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1206
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1207
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1208
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1209
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1210
423
      // (sub:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DSUBu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1211
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSUBu,
1212
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1213
423
      // GIR_Coverage, 181,
1214
423
      GIR_Done,
1215
423
    // Label 102: @1496
1216
423
    GIM_Reject,
1217
423
    // Label 88: @1497
1218
423
    GIM_Try, /*On fail goto*//*Label 103*/ 1523, // Rule ID 1846 //
1219
423
      GIM_CheckFeatures, GIFBS_HasDSP,
1220
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1221
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
1222
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
1223
423
      // (sub:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1224
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBQ_PH,
1225
423
      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
1226
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1227
423
      // GIR_Coverage, 1846,
1228
423
      GIR_Done,
1229
423
    // Label 103: @1523
1230
423
    GIM_Reject,
1231
423
    // Label 89: @1524
1232
423
    GIM_Try, /*On fail goto*//*Label 104*/ 1611,
1233
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1234
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1235
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1236
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1237
423
      GIM_Try, /*On fail goto*//*Label 105*/ 1595, // Rule ID 867 //
1238
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1239
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1240
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1241
423
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
1242
423
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
1243
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1244
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1245
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1246
423
        // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt))  =>  (MSUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1247
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_D,
1248
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1249
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1250
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1251
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1252
423
        GIR_EraseFromParent, /*InsnID*/0,
1253
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1254
423
        // GIR_Coverage, 867,
1255
423
        GIR_Done,
1256
423
      // Label 105: @1595
1257
423
      GIM_Try, /*On fail goto*//*Label 106*/ 1610, // Rule ID 996 //
1258
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1259
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1260
423
        // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1261
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_D,
1262
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1263
423
        // GIR_Coverage, 996,
1264
423
        GIR_Done,
1265
423
      // Label 106: @1610
1266
423
      GIM_Reject,
1267
423
    // Label 104: @1611
1268
423
    GIM_Reject,
1269
423
    // Label 90: @1612
1270
423
    GIM_Try, /*On fail goto*//*Label 107*/ 1638, // Rule ID 1852 //
1271
423
      GIM_CheckFeatures, GIFBS_HasDSP,
1272
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
1273
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
1274
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
1275
423
      // (sub:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)  =>  (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
1276
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU_QB,
1277
423
      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
1278
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1279
423
      // GIR_Coverage, 1852,
1280
423
      GIR_Done,
1281
423
    // Label 107: @1638
1282
423
    GIM_Reject,
1283
423
    // Label 91: @1639
1284
423
    GIM_Try, /*On fail goto*//*Label 108*/ 1726,
1285
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1286
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1287
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1288
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1289
423
      GIM_Try, /*On fail goto*//*Label 109*/ 1710, // Rule ID 866 //
1290
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1291
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1292
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1293
423
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1294
423
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1295
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1296
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1297
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1298
423
        // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt))  =>  (MSUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1299
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_W,
1300
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1301
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1302
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1303
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1304
423
        GIR_EraseFromParent, /*InsnID*/0,
1305
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1306
423
        // GIR_Coverage, 866,
1307
423
        GIR_Done,
1308
423
      // Label 109: @1710
1309
423
      GIM_Try, /*On fail goto*//*Label 110*/ 1725, // Rule ID 995 //
1310
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1311
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1312
423
        // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1313
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_W,
1314
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1315
423
        // GIR_Coverage, 995,
1316
423
        GIR_Done,
1317
423
      // Label 110: @1725
1318
423
      GIM_Reject,
1319
423
    // Label 108: @1726
1320
423
    GIM_Reject,
1321
423
    // Label 92: @1727
1322
423
    GIM_Try, /*On fail goto*//*Label 111*/ 1814,
1323
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1324
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1325
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1326
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1327
423
      GIM_Try, /*On fail goto*//*Label 112*/ 1798, // Rule ID 865 //
1328
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1329
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1330
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1331
423
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1332
423
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1333
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1334
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1335
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1336
423
        // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt))  =>  (MSUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1337
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_H,
1338
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1339
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1340
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1341
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1342
423
        GIR_EraseFromParent, /*InsnID*/0,
1343
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1344
423
        // GIR_Coverage, 865,
1345
423
        GIR_Done,
1346
423
      // Label 112: @1798
1347
423
      GIM_Try, /*On fail goto*//*Label 113*/ 1813, // Rule ID 994 //
1348
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1349
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1350
423
        // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1351
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_H,
1352
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1353
423
        // GIR_Coverage, 994,
1354
423
        GIR_Done,
1355
423
      // Label 113: @1813
1356
423
      GIM_Reject,
1357
423
    // Label 111: @1814
1358
423
    GIM_Reject,
1359
423
    // Label 93: @1815
1360
423
    GIM_Try, /*On fail goto*//*Label 114*/ 1902,
1361
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1362
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1363
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1364
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1365
423
      GIM_Try, /*On fail goto*//*Label 115*/ 1886, // Rule ID 864 //
1366
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1367
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1368
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1369
423
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1370
423
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1371
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1372
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1373
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1374
423
        // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt))  =>  (MSUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1375
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_B,
1376
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1377
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1378
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1379
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1380
423
        GIR_EraseFromParent, /*InsnID*/0,
1381
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1382
423
        // GIR_Coverage, 864,
1383
423
        GIR_Done,
1384
423
      // Label 115: @1886
1385
423
      GIM_Try, /*On fail goto*//*Label 116*/ 1901, // Rule ID 993 //
1386
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1387
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1388
423
        // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1389
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_B,
1390
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1391
423
        // GIR_Coverage, 993,
1392
423
        GIR_Done,
1393
423
      // Label 116: @1901
1394
423
      GIM_Reject,
1395
423
    // Label 114: @1902
1396
423
    GIM_Reject,
1397
423
    // Label 94: @1903
1398
423
    GIM_Reject,
1399
423
    // Label 2: @1904
1400
423
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 124*/ 2279,
1401
423
    /*GILLT_s32*//*Label 117*/ 1918,
1402
423
    /*GILLT_s64*//*Label 118*/ 2063,
1403
423
    /*GILLT_v2s16*//*Label 119*/ 2124,
1404
423
    /*GILLT_v2s64*//*Label 120*/ 2151, 0,
1405
423
    /*GILLT_v4s32*//*Label 121*/ 2183,
1406
423
    /*GILLT_v8s16*//*Label 122*/ 2215,
1407
423
    /*GILLT_v16s8*//*Label 123*/ 2247,
1408
423
    // Label 117: @1918
1409
423
    GIM_Try, /*On fail goto*//*Label 125*/ 2062,
1410
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1411
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1412
423
      GIM_Try, /*On fail goto*//*Label 126*/ 1957, // Rule ID 36 //
1413
423
        GIM_CheckFeatures, GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
1414
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1415
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1416
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1417
423
        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1418
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL,
1419
423
        GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1420
423
        GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1421
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1422
423
        // GIR_Coverage, 36,
1423
423
        GIR_Done,
1424
423
      // Label 126: @1957
1425
423
      GIM_Try, /*On fail goto*//*Label 127*/ 1980, // Rule ID 304 //
1426
423
        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1427
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1428
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1429
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1430
423
        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1431
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_R6,
1432
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1433
423
        // GIR_Coverage, 304,
1434
423
        GIR_Done,
1435
423
      // Label 127: @1980
1436
423
      GIM_Try, /*On fail goto*//*Label 128*/ 2009, // Rule ID 1042 //
1437
423
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
1438
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1439
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1440
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1441
423
        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL_MM:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1442
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_MM,
1443
423
        GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1444
423
        GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1445
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1446
423
        // GIR_Coverage, 1042,
1447
423
        GIR_Done,
1448
423
      // Label 128: @2009
1449
423
      GIM_Try, /*On fail goto*//*Label 129*/ 2032, // Rule ID 1145 //
1450
423
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1451
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1452
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1453
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1454
423
        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1455
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_MMR6,
1456
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1457
423
        // GIR_Coverage, 1145,
1458
423
        GIR_Done,
1459
423
      // Label 129: @2032
1460
423
      GIM_Try, /*On fail goto*//*Label 130*/ 2061, // Rule ID 1747 //
1461
423
        GIM_CheckFeatures, GIFBS_InMips16Mode,
1462
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
1463
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
1464
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
1465
423
        // (mul:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (MultRxRyRz16:{ *:[i32] }:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1466
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MultRxRyRz16,
1467
423
        GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1468
423
        GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1469
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1470
423
        // GIR_Coverage, 1747,
1471
423
        GIR_Done,
1472
423
      // Label 130: @2061
1473
423
      GIM_Reject,
1474
423
    // Label 125: @2062
1475
423
    GIM_Reject,
1476
423
    // Label 118: @2063
1477
423
    GIM_Try, /*On fail goto*//*Label 131*/ 2123,
1478
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1479
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1480
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1481
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1482
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1483
423
      GIM_Try, /*On fail goto*//*Label 132*/ 2111, // Rule ID 246 //
1484
423
        GIM_CheckFeatures, GIFBS_HasCnMips,
1485
423
        // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMUL:{ *:[i64] }:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1486
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUL,
1487
423
        GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1488
423
        GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1489
423
        GIR_AddImplicitDef, /*InsnID*/0, Mips::P0,
1490
423
        GIR_AddImplicitDef, /*InsnID*/0, Mips::P1,
1491
423
        GIR_AddImplicitDef, /*InsnID*/0, Mips::P2,
1492
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1493
423
        // GIR_Coverage, 246,
1494
423
        GIR_Done,
1495
423
      // Label 132: @2111
1496
423
      GIM_Try, /*On fail goto*//*Label 133*/ 2122, // Rule ID 319 //
1497
423
        GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1498
423
        // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMUL_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1499
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUL_R6,
1500
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1501
423
        // GIR_Coverage, 319,
1502
423
        GIR_Done,
1503
423
      // Label 133: @2122
1504
423
      GIM_Reject,
1505
423
    // Label 131: @2123
1506
423
    GIM_Reject,
1507
423
    // Label 119: @2124
1508
423
    GIM_Try, /*On fail goto*//*Label 134*/ 2150, // Rule ID 1848 //
1509
423
      GIM_CheckFeatures, GIFBS_HasDSPR2,
1510
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1511
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
1512
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
1513
423
      // (mul:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1514
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_PH,
1515
423
      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag21,
1516
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1517
423
      // GIR_Coverage, 1848,
1518
423
      GIR_Done,
1519
423
    // Label 134: @2150
1520
423
    GIM_Reject,
1521
423
    // Label 120: @2151
1522
423
    GIM_Try, /*On fail goto*//*Label 135*/ 2182, // Rule ID 875 //
1523
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1524
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1525
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1526
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1527
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1528
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1529
423
      // (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MULV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1530
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_D,
1531
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1532
423
      // GIR_Coverage, 875,
1533
423
      GIR_Done,
1534
423
    // Label 135: @2182
1535
423
    GIM_Reject,
1536
423
    // Label 121: @2183
1537
423
    GIM_Try, /*On fail goto*//*Label 136*/ 2214, // Rule ID 874 //
1538
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1539
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1540
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1541
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1542
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1543
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1544
423
      // (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MULV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1545
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_W,
1546
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1547
423
      // GIR_Coverage, 874,
1548
423
      GIR_Done,
1549
423
    // Label 136: @2214
1550
423
    GIM_Reject,
1551
423
    // Label 122: @2215
1552
423
    GIM_Try, /*On fail goto*//*Label 137*/ 2246, // Rule ID 873 //
1553
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1554
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1555
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1556
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1557
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1558
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1559
423
      // (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MULV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1560
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_H,
1561
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1562
423
      // GIR_Coverage, 873,
1563
423
      GIR_Done,
1564
423
    // Label 137: @2246
1565
423
    GIM_Reject,
1566
423
    // Label 123: @2247
1567
423
    GIM_Try, /*On fail goto*//*Label 138*/ 2278, // Rule ID 872 //
1568
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1569
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1570
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1571
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1572
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1573
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1574
423
      // (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MULV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1575
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_B,
1576
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1577
423
      // GIR_Coverage, 872,
1578
423
      GIR_Done,
1579
423
    // Label 138: @2278
1580
423
    GIM_Reject,
1581
423
    // Label 124: @2279
1582
423
    GIM_Reject,
1583
423
    // Label 3: @2280
1584
423
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 145*/ 2500,
1585
423
    /*GILLT_s32*//*Label 139*/ 2294,
1586
423
    /*GILLT_s64*//*Label 140*/ 2340, 0,
1587
423
    /*GILLT_v2s64*//*Label 141*/ 2372, 0,
1588
423
    /*GILLT_v4s32*//*Label 142*/ 2404,
1589
423
    /*GILLT_v8s16*//*Label 143*/ 2436,
1590
423
    /*GILLT_v16s8*//*Label 144*/ 2468,
1591
423
    // Label 139: @2294
1592
423
    GIM_Try, /*On fail goto*//*Label 146*/ 2339,
1593
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1594
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1595
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1596
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1597
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1598
423
      GIM_Try, /*On fail goto*//*Label 147*/ 2327, // Rule ID 298 //
1599
423
        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1600
423
        // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1601
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV,
1602
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1603
423
        // GIR_Coverage, 298,
1604
423
        GIR_Done,
1605
423
      // Label 147: @2327
1606
423
      GIM_Try, /*On fail goto*//*Label 148*/ 2338, // Rule ID 1138 //
1607
423
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1608
423
        // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIV_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1609
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_MMR6,
1610
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1611
423
        // GIR_Coverage, 1138,
1612
423
        GIR_Done,
1613
423
      // Label 148: @2338
1614
423
      GIM_Reject,
1615
423
    // Label 146: @2339
1616
423
    GIM_Reject,
1617
423
    // Label 140: @2340
1618
423
    GIM_Try, /*On fail goto*//*Label 149*/ 2371, // Rule ID 313 //
1619
423
      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1620
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1621
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1622
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1623
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1624
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1625
423
      // (sdiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DDIV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1626
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DDIV,
1627
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1628
423
      // GIR_Coverage, 313,
1629
423
      GIR_Done,
1630
423
    // Label 149: @2371
1631
423
    GIM_Reject,
1632
423
    // Label 141: @2372
1633
423
    GIM_Try, /*On fail goto*//*Label 150*/ 2403, // Rule ID 615 //
1634
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1635
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1636
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1637
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1638
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1639
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1640
423
      // (sdiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (DIV_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1641
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_D,
1642
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1643
423
      // GIR_Coverage, 615,
1644
423
      GIR_Done,
1645
423
    // Label 150: @2403
1646
423
    GIM_Reject,
1647
423
    // Label 142: @2404
1648
423
    GIM_Try, /*On fail goto*//*Label 151*/ 2435, // Rule ID 614 //
1649
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1650
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1651
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1652
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1653
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1654
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1655
423
      // (sdiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DIV_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1656
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_W,
1657
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1658
423
      // GIR_Coverage, 614,
1659
423
      GIR_Done,
1660
423
    // Label 151: @2435
1661
423
    GIM_Reject,
1662
423
    // Label 143: @2436
1663
423
    GIM_Try, /*On fail goto*//*Label 152*/ 2467, // Rule ID 613 //
1664
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1665
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1666
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1667
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1668
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1669
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1670
423
      // (sdiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DIV_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1671
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_H,
1672
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1673
423
      // GIR_Coverage, 613,
1674
423
      GIR_Done,
1675
423
    // Label 152: @2467
1676
423
    GIM_Reject,
1677
423
    // Label 144: @2468
1678
423
    GIM_Try, /*On fail goto*//*Label 153*/ 2499, // Rule ID 612 //
1679
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1680
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1681
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1682
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1683
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1684
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1685
423
      // (sdiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DIV_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1686
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_B,
1687
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1688
423
      // GIR_Coverage, 612,
1689
423
      GIR_Done,
1690
423
    // Label 153: @2499
1691
423
    GIM_Reject,
1692
423
    // Label 145: @2500
1693
423
    GIM_Reject,
1694
423
    // Label 4: @2501
1695
423
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 160*/ 2721,
1696
423
    /*GILLT_s32*//*Label 154*/ 2515,
1697
423
    /*GILLT_s64*//*Label 155*/ 2561, 0,
1698
423
    /*GILLT_v2s64*//*Label 156*/ 2593, 0,
1699
423
    /*GILLT_v4s32*//*Label 157*/ 2625,
1700
423
    /*GILLT_v8s16*//*Label 158*/ 2657,
1701
423
    /*GILLT_v16s8*//*Label 159*/ 2689,
1702
423
    // Label 154: @2515
1703
423
    GIM_Try, /*On fail goto*//*Label 161*/ 2560,
1704
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1705
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1706
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1707
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1708
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1709
423
      GIM_Try, /*On fail goto*//*Label 162*/ 2548, // Rule ID 299 //
1710
423
        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1711
423
        // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIVU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1712
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIVU,
1713
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1714
423
        // GIR_Coverage, 299,
1715
423
        GIR_Done,
1716
423
      // Label 162: @2548
1717
423
      GIM_Try, /*On fail goto*//*Label 163*/ 2559, // Rule ID 1139 //
1718
423
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1719
423
        // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIVU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1720
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIVU_MMR6,
1721
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1722
423
        // GIR_Coverage, 1139,
1723
423
        GIR_Done,
1724
423
      // Label 163: @2559
1725
423
      GIM_Reject,
1726
423
    // Label 161: @2560
1727
423
    GIM_Reject,
1728
423
    // Label 155: @2561
1729
423
    GIM_Try, /*On fail goto*//*Label 164*/ 2592, // Rule ID 314 //
1730
423
      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1731
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1732
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1733
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1734
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1735
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1736
423
      // (udiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DDIVU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1737
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DDIVU,
1738
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1739
423
      // GIR_Coverage, 314,
1740
423
      GIR_Done,
1741
423
    // Label 164: @2592
1742
423
    GIM_Reject,
1743
423
    // Label 156: @2593
1744
423
    GIM_Try, /*On fail goto*//*Label 165*/ 2624, // Rule ID 619 //
1745
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1746
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1747
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1748
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1749
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1750
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1751
423
      // (udiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (DIV_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1752
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_D,
1753
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1754
423
      // GIR_Coverage, 619,
1755
423
      GIR_Done,
1756
423
    // Label 165: @2624
1757
423
    GIM_Reject,
1758
423
    // Label 157: @2625
1759
423
    GIM_Try, /*On fail goto*//*Label 166*/ 2656, // Rule ID 618 //
1760
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1761
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1762
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1763
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1764
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1765
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1766
423
      // (udiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DIV_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1767
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_W,
1768
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1769
423
      // GIR_Coverage, 618,
1770
423
      GIR_Done,
1771
423
    // Label 166: @2656
1772
423
    GIM_Reject,
1773
423
    // Label 158: @2657
1774
423
    GIM_Try, /*On fail goto*//*Label 167*/ 2688, // Rule ID 617 //
1775
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1776
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1777
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1778
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1779
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1780
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1781
423
      // (udiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DIV_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1782
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_H,
1783
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1784
423
      // GIR_Coverage, 617,
1785
423
      GIR_Done,
1786
423
    // Label 167: @2688
1787
423
    GIM_Reject,
1788
423
    // Label 159: @2689
1789
423
    GIM_Try, /*On fail goto*//*Label 168*/ 2720, // Rule ID 616 //
1790
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1791
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1792
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1793
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1794
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1795
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1796
423
      // (udiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DIV_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1797
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_B,
1798
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1799
423
      // GIR_Coverage, 616,
1800
423
      GIR_Done,
1801
423
    // Label 168: @2720
1802
423
    GIM_Reject,
1803
423
    // Label 160: @2721
1804
423
    GIM_Reject,
1805
423
    // Label 5: @2722
1806
423
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 175*/ 2942,
1807
423
    /*GILLT_s32*//*Label 169*/ 2736,
1808
423
    /*GILLT_s64*//*Label 170*/ 2782, 0,
1809
423
    /*GILLT_v2s64*//*Label 171*/ 2814, 0,
1810
423
    /*GILLT_v4s32*//*Label 172*/ 2846,
1811
423
    /*GILLT_v8s16*//*Label 173*/ 2878,
1812
423
    /*GILLT_v16s8*//*Label 174*/ 2910,
1813
423
    // Label 169: @2736
1814
423
    GIM_Try, /*On fail goto*//*Label 176*/ 2781,
1815
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1816
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1817
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1818
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1819
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1820
423
      GIM_Try, /*On fail goto*//*Label 177*/ 2769, // Rule ID 300 //
1821
423
        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1822
423
        // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MOD:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1823
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD,
1824
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1825
423
        // GIR_Coverage, 300,
1826
423
        GIR_Done,
1827
423
      // Label 177: @2769
1828
423
      GIM_Try, /*On fail goto*//*Label 178*/ 2780, // Rule ID 1143 //
1829
423
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1830
423
        // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MOD_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1831
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_MMR6,
1832
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1833
423
        // GIR_Coverage, 1143,
1834
423
        GIR_Done,
1835
423
      // Label 178: @2780
1836
423
      GIM_Reject,
1837
423
    // Label 176: @2781
1838
423
    GIM_Reject,
1839
423
    // Label 170: @2782
1840
423
    GIM_Try, /*On fail goto*//*Label 179*/ 2813, // Rule ID 315 //
1841
423
      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1842
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1843
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1844
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1845
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1846
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1847
423
      // (srem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMOD:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1848
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMOD,
1849
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1850
423
      // GIR_Coverage, 315,
1851
423
      GIR_Done,
1852
423
    // Label 179: @2813
1853
423
    GIM_Reject,
1854
423
    // Label 171: @2814
1855
423
    GIM_Try, /*On fail goto*//*Label 180*/ 2845, // Rule ID 855 //
1856
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1857
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1858
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1859
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1860
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1861
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1862
423
      // (srem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MOD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1863
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_D,
1864
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1865
423
      // GIR_Coverage, 855,
1866
423
      GIR_Done,
1867
423
    // Label 180: @2845
1868
423
    GIM_Reject,
1869
423
    // Label 172: @2846
1870
423
    GIM_Try, /*On fail goto*//*Label 181*/ 2877, // Rule ID 854 //
1871
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1872
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1873
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1874
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1875
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1876
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1877
423
      // (srem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MOD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1878
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_W,
1879
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1880
423
      // GIR_Coverage, 854,
1881
423
      GIR_Done,
1882
423
    // Label 181: @2877
1883
423
    GIM_Reject,
1884
423
    // Label 173: @2878
1885
423
    GIM_Try, /*On fail goto*//*Label 182*/ 2909, // Rule ID 853 //
1886
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1887
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1888
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1889
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1890
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1891
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1892
423
      // (srem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MOD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1893
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_H,
1894
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1895
423
      // GIR_Coverage, 853,
1896
423
      GIR_Done,
1897
423
    // Label 182: @2909
1898
423
    GIM_Reject,
1899
423
    // Label 174: @2910
1900
423
    GIM_Try, /*On fail goto*//*Label 183*/ 2941, // Rule ID 852 //
1901
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1902
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1903
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1904
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1905
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1906
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1907
423
      // (srem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MOD_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1908
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_B,
1909
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1910
423
      // GIR_Coverage, 852,
1911
423
      GIR_Done,
1912
423
    // Label 183: @2941
1913
423
    GIM_Reject,
1914
423
    // Label 175: @2942
1915
423
    GIM_Reject,
1916
423
    // Label 6: @2943
1917
423
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 190*/ 3163,
1918
423
    /*GILLT_s32*//*Label 184*/ 2957,
1919
423
    /*GILLT_s64*//*Label 185*/ 3003, 0,
1920
423
    /*GILLT_v2s64*//*Label 186*/ 3035, 0,
1921
423
    /*GILLT_v4s32*//*Label 187*/ 3067,
1922
423
    /*GILLT_v8s16*//*Label 188*/ 3099,
1923
423
    /*GILLT_v16s8*//*Label 189*/ 3131,
1924
423
    // Label 184: @2957
1925
423
    GIM_Try, /*On fail goto*//*Label 191*/ 3002,
1926
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1927
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1928
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1929
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1930
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1931
423
      GIM_Try, /*On fail goto*//*Label 192*/ 2990, // Rule ID 301 //
1932
423
        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1933
423
        // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MODU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1934
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MODU,
1935
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1936
423
        // GIR_Coverage, 301,
1937
423
        GIR_Done,
1938
423
      // Label 192: @2990
1939
423
      GIM_Try, /*On fail goto*//*Label 193*/ 3001, // Rule ID 1144 //
1940
423
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1941
423
        // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MODU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1942
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MODU_MMR6,
1943
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1944
423
        // GIR_Coverage, 1144,
1945
423
        GIR_Done,
1946
423
      // Label 193: @3001
1947
423
      GIM_Reject,
1948
423
    // Label 191: @3002
1949
423
    GIM_Reject,
1950
423
    // Label 185: @3003
1951
423
    GIM_Try, /*On fail goto*//*Label 194*/ 3034, // Rule ID 316 //
1952
423
      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1953
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1954
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1955
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1956
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1957
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1958
423
      // (urem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMODU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1959
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMODU,
1960
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1961
423
      // GIR_Coverage, 316,
1962
423
      GIR_Done,
1963
423
    // Label 194: @3034
1964
423
    GIM_Reject,
1965
423
    // Label 186: @3035
1966
423
    GIM_Try, /*On fail goto*//*Label 195*/ 3066, // Rule ID 859 //
1967
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1968
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1969
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1970
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1971
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1972
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1973
423
      // (urem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MOD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1974
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_D,
1975
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1976
423
      // GIR_Coverage, 859,
1977
423
      GIR_Done,
1978
423
    // Label 195: @3066
1979
423
    GIM_Reject,
1980
423
    // Label 187: @3067
1981
423
    GIM_Try, /*On fail goto*//*Label 196*/ 3098, // Rule ID 858 //
1982
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1983
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1984
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1985
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1986
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1987
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1988
423
      // (urem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MOD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1989
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_W,
1990
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1991
423
      // GIR_Coverage, 858,
1992
423
      GIR_Done,
1993
423
    // Label 196: @3098
1994
423
    GIM_Reject,
1995
423
    // Label 188: @3099
1996
423
    GIM_Try, /*On fail goto*//*Label 197*/ 3130, // Rule ID 857 //
1997
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1998
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1999
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2000
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2001
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2002
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2003
423
      // (urem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MOD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2004
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_H,
2005
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2006
423
      // GIR_Coverage, 857,
2007
423
      GIR_Done,
2008
423
    // Label 197: @3130
2009
423
    GIM_Reject,
2010
423
    // Label 189: @3131
2011
423
    GIM_Try, /*On fail goto*//*Label 198*/ 3162, // Rule ID 856 //
2012
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2013
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2014
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2015
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2016
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2017
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2018
423
      // (urem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MOD_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2019
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_B,
2020
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2021
423
      // GIR_Coverage, 856,
2022
423
      GIR_Done,
2023
423
    // Label 198: @3162
2024
423
    GIM_Reject,
2025
423
    // Label 190: @3163
2026
423
    GIM_Reject,
2027
423
    // Label 7: @3164
2028
423
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 205*/ 3607,
2029
423
    /*GILLT_s32*//*Label 199*/ 3178,
2030
423
    /*GILLT_s64*//*Label 200*/ 3391, 0,
2031
423
    /*GILLT_v2s64*//*Label 201*/ 3479, 0,
2032
423
    /*GILLT_v4s32*//*Label 202*/ 3511,
2033
423
    /*GILLT_v8s16*//*Label 203*/ 3543,
2034
423
    /*GILLT_v16s8*//*Label 204*/ 3575,
2035
423
    // Label 199: @3178
2036
423
    GIM_Try, /*On fail goto*//*Label 206*/ 3390,
2037
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2038
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2039
423
      GIM_Try, /*On fail goto*//*Label 207*/ 3231, // Rule ID 2087 //
2040
423
        GIM_CheckFeatures, GIFBS_InMicroMips,
2041
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2042
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2043
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2044
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2045
423
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExtAndi16,
2046
423
        // MIs[1] Operand 1
2047
423
        // No operand predicates
2048
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2049
423
        // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)  =>  (ANDI16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2050
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MM,
2051
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2052
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
2053
423
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2054
423
        GIR_EraseFromParent, /*InsnID*/0,
2055
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2056
423
        // GIR_Coverage, 2087,
2057
423
        GIR_Done,
2058
423
      // Label 207: @3231
2059
423
      GIM_Try, /*On fail goto*//*Label 208*/ 3274, // Rule ID 2241 //
2060
423
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2061
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2062
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2063
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2064
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2065
423
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExtAndi16,
2066
423
        // MIs[1] Operand 1
2067
423
        // No operand predicates
2068
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2069
423
        // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)  =>  (ANDI16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2070
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MMR6,
2071
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2072
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
2073
423
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2074
423
        GIR_EraseFromParent, /*InsnID*/0,
2075
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2076
423
        // GIR_Coverage, 2241,
2077
423
        GIR_Done,
2078
423
      // Label 208: @3274
2079
423
      GIM_Try, /*On fail goto*//*Label 209*/ 3297, // Rule ID 39 //
2080
423
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2081
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2082
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2083
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2084
423
        // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (AND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2085
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND,
2086
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2087
423
        // GIR_Coverage, 39,
2088
423
        GIR_Done,
2089
423
      // Label 209: @3297
2090
423
      GIM_Try, /*On fail goto*//*Label 210*/ 3320, // Rule ID 1029 //
2091
423
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2092
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2093
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2094
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
2095
423
        // (and:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (AND16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2096
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND16_MM,
2097
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2098
423
        // GIR_Coverage, 1029,
2099
423
        GIR_Done,
2100
423
      // Label 210: @3320
2101
423
      GIM_Try, /*On fail goto*//*Label 211*/ 3343, // Rule ID 1045 //
2102
423
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2103
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2104
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2105
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2106
423
        // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (AND_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2107
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_MM,
2108
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2109
423
        // GIR_Coverage, 1045,
2110
423
        GIR_Done,
2111
423
      // Label 211: @3343
2112
423
      GIM_Try, /*On fail goto*//*Label 212*/ 3366, // Rule ID 1136 //
2113
423
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2114
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2115
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2116
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2117
423
        // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (AND_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2118
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_MMR6,
2119
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2120
423
        // GIR_Coverage, 1136,
2121
423
        GIR_Done,
2122
423
      // Label 212: @3366
2123
423
      GIM_Try, /*On fail goto*//*Label 213*/ 3389, // Rule ID 1746 //
2124
423
        GIM_CheckFeatures, GIFBS_InMips16Mode,
2125
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2126
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2127
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
2128
423
        // (and:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (AndRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2129
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AndRxRxRy16,
2130
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2131
423
        // GIR_Coverage, 1746,
2132
423
        GIR_Done,
2133
423
      // Label 213: @3389
2134
423
      GIM_Reject,
2135
423
    // Label 206: @3390
2136
423
    GIM_Reject,
2137
423
    // Label 200: @3391
2138
423
    GIM_Try, /*On fail goto*//*Label 214*/ 3478,
2139
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2140
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2141
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2142
423
      GIM_Try, /*On fail goto*//*Label 215*/ 3458, // Rule ID 241 //
2143
423
        GIM_CheckFeatures, GIFBS_HasCnMips,
2144
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2145
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
2146
423
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2147
423
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2148
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2149
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2150
423
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
2151
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2152
423
        // (and:{ *:[i64] } (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), 255:{ *:[i64] })  =>  (BADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2153
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BADDu,
2154
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2155
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2156
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2157
423
        GIR_EraseFromParent, /*InsnID*/0,
2158
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2159
423
        // GIR_Coverage, 241,
2160
423
        GIR_Done,
2161
423
      // Label 215: @3458
2162
423
      GIM_Try, /*On fail goto*//*Label 216*/ 3477, // Rule ID 184 //
2163
423
        GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2164
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2165
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2166
423
        // (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (AND64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2167
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND64,
2168
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2169
423
        // GIR_Coverage, 184,
2170
423
        GIR_Done,
2171
423
      // Label 216: @3477
2172
423
      GIM_Reject,
2173
423
    // Label 214: @3478
2174
423
    GIM_Reject,
2175
423
    // Label 201: @3479
2176
423
    GIM_Try, /*On fail goto*//*Label 217*/ 3510, // Rule ID 486 //
2177
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2178
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2179
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2180
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2181
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
2182
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
2183
423
      // (and:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (AND_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2184
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_D_PSEUDO,
2185
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2186
423
      // GIR_Coverage, 486,
2187
423
      GIR_Done,
2188
423
    // Label 217: @3510
2189
423
    GIM_Reject,
2190
423
    // Label 202: @3511
2191
423
    GIM_Try, /*On fail goto*//*Label 218*/ 3542, // Rule ID 485 //
2192
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2193
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2194
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2195
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2196
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2197
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2198
423
      // (and:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (AND_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2199
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_W_PSEUDO,
2200
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2201
423
      // GIR_Coverage, 485,
2202
423
      GIR_Done,
2203
423
    // Label 218: @3542
2204
423
    GIM_Reject,
2205
423
    // Label 203: @3543
2206
423
    GIM_Try, /*On fail goto*//*Label 219*/ 3574, // Rule ID 484 //
2207
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2208
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2209
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2210
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2211
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2212
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2213
423
      // (and:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (AND_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2214
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_H_PSEUDO,
2215
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2216
423
      // GIR_Coverage, 484,
2217
423
      GIR_Done,
2218
423
    // Label 219: @3574
2219
423
    GIM_Reject,
2220
423
    // Label 204: @3575
2221
423
    GIM_Try, /*On fail goto*//*Label 220*/ 3606, // Rule ID 483 //
2222
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2223
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2224
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2225
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2226
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2227
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2228
423
      // (and:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (AND_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2229
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V,
2230
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2231
423
      // GIR_Coverage, 483,
2232
423
      GIR_Done,
2233
423
    // Label 220: @3606
2234
423
    GIM_Reject,
2235
423
    // Label 205: @3607
2236
423
    GIM_Reject,
2237
423
    // Label 8: @3608
2238
423
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 227*/ 3909,
2239
423
    /*GILLT_s32*//*Label 221*/ 3622,
2240
423
    /*GILLT_s64*//*Label 222*/ 3749, 0,
2241
423
    /*GILLT_v2s64*//*Label 223*/ 3781, 0,
2242
423
    /*GILLT_v4s32*//*Label 224*/ 3813,
2243
423
    /*GILLT_v8s16*//*Label 225*/ 3845,
2244
423
    /*GILLT_v16s8*//*Label 226*/ 3877,
2245
423
    // Label 221: @3622
2246
423
    GIM_Try, /*On fail goto*//*Label 228*/ 3748,
2247
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2248
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2249
423
      GIM_Try, /*On fail goto*//*Label 229*/ 3655, // Rule ID 40 //
2250
423
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2251
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2252
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2253
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2254
423
        // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (OR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2255
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR,
2256
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2257
423
        // GIR_Coverage, 40,
2258
423
        GIR_Done,
2259
423
      // Label 229: @3655
2260
423
      GIM_Try, /*On fail goto*//*Label 230*/ 3678, // Rule ID 1031 //
2261
423
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2262
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2263
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2264
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
2265
423
        // (or:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (OR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2266
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR16_MM,
2267
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2268
423
        // GIR_Coverage, 1031,
2269
423
        GIR_Done,
2270
423
      // Label 230: @3678
2271
423
      GIM_Try, /*On fail goto*//*Label 231*/ 3701, // Rule ID 1046 //
2272
423
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2273
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2274
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2275
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2276
423
        // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (OR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2277
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_MM,
2278
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2279
423
        // GIR_Coverage, 1046,
2280
423
        GIR_Done,
2281
423
      // Label 231: @3701
2282
423
      GIM_Try, /*On fail goto*//*Label 232*/ 3724, // Rule ID 1149 //
2283
423
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2284
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2285
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2286
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2287
423
        // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (OR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2288
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_MMR6,
2289
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2290
423
        // GIR_Coverage, 1149,
2291
423
        GIR_Done,
2292
423
      // Label 232: @3724
2293
423
      GIM_Try, /*On fail goto*//*Label 233*/ 3747, // Rule ID 1748 //
2294
423
        GIM_CheckFeatures, GIFBS_InMips16Mode,
2295
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2296
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2297
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
2298
423
        // (or:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (OrRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2299
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OrRxRxRy16,
2300
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2301
423
        // GIR_Coverage, 1748,
2302
423
        GIR_Done,
2303
423
      // Label 233: @3747
2304
423
      GIM_Reject,
2305
423
    // Label 228: @3748
2306
423
    GIM_Reject,
2307
423
    // Label 222: @3749
2308
423
    GIM_Try, /*On fail goto*//*Label 234*/ 3780, // Rule ID 185 //
2309
423
      GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2310
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2311
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2312
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2313
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2314
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2315
423
      // (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (OR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2316
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR64,
2317
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2318
423
      // GIR_Coverage, 185,
2319
423
      GIR_Done,
2320
423
    // Label 234: @3780
2321
423
    GIM_Reject,
2322
423
    // Label 223: @3781
2323
423
    GIM_Try, /*On fail goto*//*Label 235*/ 3812, // Rule ID 892 //
2324
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2325
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2326
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2327
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2328
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
2329
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
2330
423
      // (or:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (OR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2331
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_D_PSEUDO,
2332
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2333
423
      // GIR_Coverage, 892,
2334
423
      GIR_Done,
2335
423
    // Label 235: @3812
2336
423
    GIM_Reject,
2337
423
    // Label 224: @3813
2338
423
    GIM_Try, /*On fail goto*//*Label 236*/ 3844, // Rule ID 891 //
2339
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2340
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2341
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2342
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2343
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2344
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2345
423
      // (or:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (OR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2346
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_W_PSEUDO,
2347
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2348
423
      // GIR_Coverage, 891,
2349
423
      GIR_Done,
2350
423
    // Label 236: @3844
2351
423
    GIM_Reject,
2352
423
    // Label 225: @3845
2353
423
    GIM_Try, /*On fail goto*//*Label 237*/ 3876, // Rule ID 890 //
2354
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2355
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2356
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2357
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2358
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2359
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2360
423
      // (or:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (OR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2361
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_H_PSEUDO,
2362
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2363
423
      // GIR_Coverage, 890,
2364
423
      GIR_Done,
2365
423
    // Label 237: @3876
2366
423
    GIM_Reject,
2367
423
    // Label 226: @3877
2368
423
    GIM_Try, /*On fail goto*//*Label 238*/ 3908, // Rule ID 889 //
2369
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2370
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2371
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2372
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2373
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2374
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2375
423
      // (or:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (OR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2376
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V,
2377
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2378
423
      // GIR_Coverage, 889,
2379
423
      GIR_Done,
2380
423
    // Label 238: @3908
2381
423
    GIM_Reject,
2382
423
    // Label 227: @3909
2383
423
    GIM_Reject,
2384
423
    // Label 9: @3910
2385
423
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 245*/ 4703,
2386
423
    /*GILLT_s32*//*Label 239*/ 3924,
2387
423
    /*GILLT_s64*//*Label 240*/ 4487, 0,
2388
423
    /*GILLT_v2s64*//*Label 241*/ 4575, 0,
2389
423
    /*GILLT_v4s32*//*Label 242*/ 4607,
2390
423
    /*GILLT_v8s16*//*Label 243*/ 4639,
2391
423
    /*GILLT_v16s8*//*Label 244*/ 4671,
2392
423
    // Label 239: @3924
2393
423
    GIM_Try, /*On fail goto*//*Label 246*/ 4486,
2394
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2395
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2396
423
      GIM_Try, /*On fail goto*//*Label 247*/ 3991, // Rule ID 42 //
2397
423
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2398
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2399
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2400
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2401
423
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2402
423
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2403
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2404
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2405
423
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2406
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2407
423
        // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] })  =>  (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2408
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
2409
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2410
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2411
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2412
423
        GIR_EraseFromParent, /*InsnID*/0,
2413
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2414
423
        // GIR_Coverage, 42,
2415
423
        GIR_Done,
2416
423
      // Label 247: @3991
2417
423
      GIM_Try, /*On fail goto*//*Label 248*/ 4048, // Rule ID 1048 //
2418
423
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2419
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2420
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2421
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2422
423
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2423
423
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2424
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2425
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2426
423
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2427
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2428
423
        // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] })  =>  (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2429
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MM,
2430
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2431
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2432
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2433
423
        GIR_EraseFromParent, /*InsnID*/0,
2434
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2435
423
        // GIR_Coverage, 1048,
2436
423
        GIR_Done,
2437
423
      // Label 248: @4048
2438
423
      GIM_Try, /*On fail goto*//*Label 249*/ 4105, // Rule ID 1148 //
2439
423
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2440
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2441
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2442
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2443
423
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2444
423
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2445
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2446
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2447
423
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2448
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2449
423
        // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] })  =>  (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2450
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
2451
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2452
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2453
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2454
423
        GIR_EraseFromParent, /*InsnID*/0,
2455
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2456
423
        // GIR_Coverage, 1148,
2457
423
        GIR_Done,
2458
423
      // Label 249: @4105
2459
423
      GIM_Try, /*On fail goto*//*Label 250*/ 4137, // Rule ID 1175 //
2460
423
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2461
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2462
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2463
423
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2464
423
        // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })  =>  (NOT16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2465
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MMR6,
2466
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2467
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
2468
423
        GIR_EraseFromParent, /*InsnID*/0,
2469
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2470
423
        // GIR_Coverage, 1175,
2471
423
        GIR_Done,
2472
423
      // Label 250: @4137
2473
423
      GIM_Try, /*On fail goto*//*Label 251*/ 4169, // Rule ID 1030 //
2474
423
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2475
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2476
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2477
423
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2478
423
        // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })  =>  (NOT16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2479
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MM,
2480
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2481
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
2482
423
        GIR_EraseFromParent, /*InsnID*/0,
2483
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2484
423
        // GIR_Coverage, 1030,
2485
423
        GIR_Done,
2486
423
      // Label 251: @4169
2487
423
      GIM_Try, /*On fail goto*//*Label 252*/ 4204, // Rule ID 1362 //
2488
423
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2489
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2490
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2491
423
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2492
423
        // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2493
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
2494
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2495
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2496
423
        GIR_AddRegister, /*InsnID*/0, Mips::ZERO,
2497
423
        GIR_EraseFromParent, /*InsnID*/0,
2498
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2499
423
        // GIR_Coverage, 1362,
2500
423
        GIR_Done,
2501
423
      // Label 252: @4204
2502
423
      GIM_Try, /*On fail goto*//*Label 253*/ 4236, // Rule ID 1743 //
2503
423
        GIM_CheckFeatures, GIFBS_InMips16Mode,
2504
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2505
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2506
423
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2507
423
        // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, -1:{ *:[i32] })  =>  (NotRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
2508
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NotRxRy16,
2509
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
2510
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // r
2511
423
        GIR_EraseFromParent, /*InsnID*/0,
2512
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2513
423
        // GIR_Coverage, 1743,
2514
423
        GIR_Done,
2515
423
      // Label 253: @4236
2516
423
      GIM_Try, /*On fail goto*//*Label 254*/ 4268, // Rule ID 2082 //
2517
423
        GIM_CheckFeatures, GIFBS_InMicroMips,
2518
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2519
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2520
423
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2521
423
        // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOT16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2522
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MM,
2523
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2524
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2525
423
        GIR_EraseFromParent, /*InsnID*/0,
2526
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2527
423
        // GIR_Coverage, 2082,
2528
423
        GIR_Done,
2529
423
      // Label 254: @4268
2530
423
      GIM_Try, /*On fail goto*//*Label 255*/ 4303, // Rule ID 2083 //
2531
423
        GIM_CheckFeatures, GIFBS_InMicroMips,
2532
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2533
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2534
423
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2535
423
        // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2536
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MM,
2537
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2538
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2539
423
        GIR_AddRegister, /*InsnID*/0, Mips::ZERO,
2540
423
        GIR_EraseFromParent, /*InsnID*/0,
2541
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2542
423
        // GIR_Coverage, 2083,
2543
423
        GIR_Done,
2544
423
      // Label 255: @4303
2545
423
      GIM_Try, /*On fail goto*//*Label 256*/ 4335, // Rule ID 2244 //
2546
423
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2547
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2548
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2549
423
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2550
423
        // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOT16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2551
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MMR6,
2552
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2553
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2554
423
        GIR_EraseFromParent, /*InsnID*/0,
2555
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2556
423
        // GIR_Coverage, 2244,
2557
423
        GIR_Done,
2558
423
      // Label 256: @4335
2559
423
      GIM_Try, /*On fail goto*//*Label 257*/ 4370, // Rule ID 2245 //
2560
423
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2561
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2562
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2563
423
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2564
423
        // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2565
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
2566
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2567
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2568
423
        GIR_AddRegister, /*InsnID*/0, Mips::ZERO,
2569
423
        GIR_EraseFromParent, /*InsnID*/0,
2570
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2571
423
        // GIR_Coverage, 2245,
2572
423
        GIR_Done,
2573
423
      // Label 257: @4370
2574
423
      GIM_Try, /*On fail goto*//*Label 258*/ 4393, // Rule ID 41 //
2575
423
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2576
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2577
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2578
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2579
423
        // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (XOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2580
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR,
2581
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2582
423
        // GIR_Coverage, 41,
2583
423
        GIR_Done,
2584
423
      // Label 258: @4393
2585
423
      GIM_Try, /*On fail goto*//*Label 259*/ 4416, // Rule ID 1033 //
2586
423
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2587
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2588
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2589
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
2590
423
        // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (XOR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2591
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR16_MM,
2592
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2593
423
        // GIR_Coverage, 1033,
2594
423
        GIR_Done,
2595
423
      // Label 259: @4416
2596
423
      GIM_Try, /*On fail goto*//*Label 260*/ 4439, // Rule ID 1047 //
2597
423
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2598
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2599
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2600
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2601
423
        // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (XOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2602
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_MM,
2603
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2604
423
        // GIR_Coverage, 1047,
2605
423
        GIR_Done,
2606
423
      // Label 260: @4439
2607
423
      GIM_Try, /*On fail goto*//*Label 261*/ 4462, // Rule ID 1152 //
2608
423
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2609
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2610
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2611
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2612
423
        // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (XOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2613
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_MMR6,
2614
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2615
423
        // GIR_Coverage, 1152,
2616
423
        GIR_Done,
2617
423
      // Label 261: @4462
2618
423
      GIM_Try, /*On fail goto*//*Label 262*/ 4485, // Rule ID 1750 //
2619
423
        GIM_CheckFeatures, GIFBS_InMips16Mode,
2620
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2621
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2622
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
2623
423
        // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2624
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XorRxRxRy16,
2625
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2626
423
        // GIR_Coverage, 1750,
2627
423
        GIR_Done,
2628
423
      // Label 262: @4485
2629
423
      GIM_Reject,
2630
423
    // Label 246: @4486
2631
423
    GIM_Reject,
2632
423
    // Label 240: @4487
2633
423
    GIM_Try, /*On fail goto*//*Label 263*/ 4574,
2634
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2635
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2636
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2637
423
      GIM_Try, /*On fail goto*//*Label 264*/ 4554, // Rule ID 187 //
2638
423
        GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2639
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2640
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2641
423
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2642
423
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2643
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2644
423
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2645
423
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2646
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2647
423
        // (xor:{ *:[i64] } (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), -1:{ *:[i64] })  =>  (NOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2648
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR64,
2649
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2650
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2651
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2652
423
        GIR_EraseFromParent, /*InsnID*/0,
2653
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2654
423
        // GIR_Coverage, 187,
2655
423
        GIR_Done,
2656
423
      // Label 264: @4554
2657
423
      GIM_Try, /*On fail goto*//*Label 265*/ 4573, // Rule ID 186 //
2658
423
        GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2659
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2660
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2661
423
        // (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (XOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2662
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR64,
2663
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2664
423
        // GIR_Coverage, 186,
2665
423
        GIR_Done,
2666
423
      // Label 265: @4573
2667
423
      GIM_Reject,
2668
423
    // Label 263: @4574
2669
423
    GIM_Reject,
2670
423
    // Label 241: @4575
2671
423
    GIM_Try, /*On fail goto*//*Label 266*/ 4606, // Rule ID 1008 //
2672
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2673
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2674
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2675
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2676
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
2677
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
2678
423
      // (xor:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (XOR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2679
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_D_PSEUDO,
2680
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2681
423
      // GIR_Coverage, 1008,
2682
423
      GIR_Done,
2683
423
    // Label 266: @4606
2684
423
    GIM_Reject,
2685
423
    // Label 242: @4607
2686
423
    GIM_Try, /*On fail goto*//*Label 267*/ 4638, // Rule ID 1007 //
2687
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2688
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2689
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2690
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2691
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2692
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2693
423
      // (xor:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (XOR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2694
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_W_PSEUDO,
2695
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2696
423
      // GIR_Coverage, 1007,
2697
423
      GIR_Done,
2698
423
    // Label 267: @4638
2699
423
    GIM_Reject,
2700
423
    // Label 243: @4639
2701
423
    GIM_Try, /*On fail goto*//*Label 268*/ 4670, // Rule ID 1006 //
2702
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2703
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2704
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2705
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2706
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2707
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2708
423
      // (xor:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (XOR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2709
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_H_PSEUDO,
2710
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2711
423
      // GIR_Coverage, 1006,
2712
423
      GIR_Done,
2713
423
    // Label 268: @4670
2714
423
    GIM_Reject,
2715
423
    // Label 244: @4671
2716
423
    GIM_Try, /*On fail goto*//*Label 269*/ 4702, // Rule ID 1005 //
2717
423
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2718
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2719
423
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2720
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2721
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2722
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2723
423
      // (xor:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (XOR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2724
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V,
2725
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2726
423
      // GIR_Coverage, 1005,
2727
423
      GIR_Done,
2728
423
    // Label 269: @4702
2729
423
    GIM_Reject,
2730
423
    // Label 245: @4703
2731
423
    GIM_Reject,
2732
423
    // Label 10: @4704
2733
423
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 278*/ 8356,
2734
423
    /*GILLT_s32*//*Label 270*/ 4718,
2735
423
    /*GILLT_s64*//*Label 271*/ 4957,
2736
423
    /*GILLT_v2s16*//*Label 272*/ 5003,
2737
423
    /*GILLT_v2s64*//*Label 273*/ 5049,
2738
423
    /*GILLT_v4s8*//*Label 274*/ 6022,
2739
423
    /*GILLT_v4s32*//*Label 275*/ 6068,
2740
423
    /*GILLT_v8s16*//*Label 276*/ 6971,
2741
423
    /*GILLT_v16s8*//*Label 277*/ 7769,
2742
423
    // Label 270: @4718
2743
423
    GIM_Try, /*On fail goto*//*Label 279*/ 4741, // Rule ID 117 //
2744
423
      GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
2745
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2746
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2747
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
2748
423
      // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (MFC1:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
2749
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1,
2750
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2751
423
      // GIR_Coverage, 117,
2752
423
      GIR_Done,
2753
423
    // Label 279: @4741
2754
423
    GIM_Try, /*On fail goto*//*Label 280*/ 4764, // Rule ID 118 //
2755
423
      GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
2756
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2757
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2758
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2759
423
      // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)  =>  (MTC1:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
2760
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1,
2761
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2762
423
      // GIR_Coverage, 118,
2763
423
      GIR_Done,
2764
423
    // Label 280: @4764
2765
423
    GIM_Try, /*On fail goto*//*Label 281*/ 4787, // Rule ID 1128 //
2766
423
      GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
2767
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2768
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2769
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
2770
423
      // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (MFC1_MM:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
2771
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1_MM,
2772
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2773
423
      // GIR_Coverage, 1128,
2774
423
      GIR_Done,
2775
423
    // Label 281: @4787
2776
423
    GIM_Try, /*On fail goto*//*Label 282*/ 4810, // Rule ID 1129 //
2777
423
      GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
2778
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2779
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2780
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2781
423
      // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)  =>  (MTC1_MM:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
2782
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1_MM,
2783
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2784
423
      // GIR_Coverage, 1129,
2785
423
      GIR_Done,
2786
423
    // Label 282: @4810
2787
423
    GIM_Try, /*On fail goto*//*Label 283*/ 4833, // Rule ID 1141 //
2788
423
      GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
2789
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2790
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2791
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2792
423
      // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)  =>  (MTC1_MMR6:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
2793
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1_MMR6,
2794
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2795
423
      // GIR_Coverage, 1141,
2796
423
      GIR_Done,
2797
423
    // Label 283: @4833
2798
423
    GIM_Try, /*On fail goto*//*Label 284*/ 4856, // Rule ID 1142 //
2799
423
      GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
2800
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2801
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2802
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
2803
423
      // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (MFC1_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
2804
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1_MMR6,
2805
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2806
423
      // GIR_Coverage, 1142,
2807
423
      GIR_Done,
2808
423
    // Label 284: @4856
2809
423
    GIM_Try, /*On fail goto*//*Label 285*/ 4881, // Rule ID 1831 //
2810
423
      GIM_CheckFeatures, GIFBS_HasDSP,
2811
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
2812
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2813
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
2814
423
      // (bitconvert:{ *:[i32] } DSPR:{ *:[v2i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v2i16] }:$src, GPR32:{ *:[i32] })
2815
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2816
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR32*/11,
2817
423
      // GIR_Coverage, 1831,
2818
423
      GIR_Done,
2819
423
    // Label 285: @4881
2820
423
    GIM_Try, /*On fail goto*//*Label 286*/ 4906, // Rule ID 1832 //
2821
423
      GIM_CheckFeatures, GIFBS_HasDSP,
2822
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
2823
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2824
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
2825
423
      // (bitconvert:{ *:[i32] } DSPR:{ *:[v4i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v4i8] }:$src, GPR32:{ *:[i32] })
2826
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2827
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR32*/11,
2828
423
      // GIR_Coverage, 1832,
2829
423
      GIR_Done,
2830
423
    // Label 286: @4906
2831
423
    GIM_Try, /*On fail goto*//*Label 287*/ 4931, // Rule ID 1835 //
2832
423
      GIM_CheckFeatures, GIFBS_HasDSP,
2833
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
2834
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2835
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
2836
423
      // (bitconvert:{ *:[f32] } DSPR:{ *:[v2i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v2i16] }:$src, FGR32:{ *:[i32] })
2837
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2838
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FGR32*/8,
2839
423
      // GIR_Coverage, 1835,
2840
423
      GIR_Done,
2841
423
    // Label 287: @4931
2842
423
    GIM_Try, /*On fail goto*//*Label 288*/ 4956, // Rule ID 1836 //
2843
423
      GIM_CheckFeatures, GIFBS_HasDSP,
2844
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
2845
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2846
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
2847
423
      // (bitconvert:{ *:[f32] } DSPR:{ *:[v4i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v4i8] }:$src, FGR32:{ *:[i32] })
2848
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2849
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FGR32*/8,
2850
423
      // GIR_Coverage, 1836,
2851
423
      GIR_Done,
2852
423
    // Label 288: @4956
2853
423
    GIM_Reject,
2854
423
    // Label 271: @4957
2855
423
    GIM_Try, /*On fail goto*//*Label 289*/ 5002,
2856
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2857
423
      GIM_Try, /*On fail goto*//*Label 290*/ 4982, // Rule ID 119 //
2858
423
        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
2859
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
2860
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2861
423
        // (bitconvert:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMTC1:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt)
2862
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMTC1,
2863
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2864
423
        // GIR_Coverage, 119,
2865
423
        GIR_Done,
2866
423
      // Label 290: @4982
2867
423
      GIM_Try, /*On fail goto*//*Label 291*/ 5001, // Rule ID 120 //
2868
423
        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
2869
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2870
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
2871
423
        // (bitconvert:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (DMFC1:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs)
2872
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMFC1,
2873
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2874
423
        // GIR_Coverage, 120,
2875
423
        GIR_Done,
2876
423
      // Label 291: @5001
2877
423
      GIM_Reject,
2878
423
    // Label 289: @5002
2879
423
    GIM_Reject,
2880
423
    // Label 272: @5003
2881
423
    GIM_Try, /*On fail goto*//*Label 292*/ 5048,
2882
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2883
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
2884
423
      GIM_Try, /*On fail goto*//*Label 293*/ 5030, // Rule ID 1833 //
2885
423
        GIM_CheckFeatures, GIFBS_HasDSP,
2886
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2887
423
        // (bitconvert:{ *:[v2i16] } GPR32:{ *:[i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i16] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
2888
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2889
423
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
2890
423
        // GIR_Coverage, 1833,
2891
423
        GIR_Done,
2892
423
      // Label 293: @5030
2893
423
      GIM_Try, /*On fail goto*//*Label 294*/ 5047, // Rule ID 1837 //
2894
423
        GIM_CheckFeatures, GIFBS_HasDSP,
2895
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
2896
423
        // (bitconvert:{ *:[v2i16] } FGR32:{ *:[f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i16] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
2897
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2898
423
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
2899
423
        // GIR_Coverage, 1837,
2900
423
        GIR_Done,
2901
423
      // Label 294: @5047
2902
423
      GIM_Reject,
2903
423
    // Label 292: @5048
2904
423
    GIM_Reject,
2905
423
    // Label 273: @5049
2906
423
    GIM_Try, /*On fail goto*//*Label 295*/ 5070, // Rule ID 1918 //
2907
423
      GIM_CheckFeatures, GIFBS_HasMSA,
2908
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2909
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2910
423
      // (bitconvert:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src, MSA128D:{ *:[i32] })
2911
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2912
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2913
423
      // GIR_Coverage, 1918,
2914
423
      GIR_Done,
2915
423
    // Label 295: @5070
2916
423
    GIM_Try, /*On fail goto*//*Label 296*/ 5091, // Rule ID 1921 //
2917
423
      GIM_CheckFeatures, GIFBS_HasMSA,
2918
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2919
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2920
423
      // (bitconvert:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src, MSA128D:{ *:[i32] })
2921
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2922
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2923
423
      // GIR_Coverage, 1921,
2924
423
      GIR_Done,
2925
423
    // Label 296: @5091
2926
423
    GIM_Try, /*On fail goto*//*Label 297*/ 5112, // Rule ID 1938 //
2927
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2928
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2929
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2930
423
      // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
2931
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2932
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2933
423
      // GIR_Coverage, 1938,
2934
423
      GIR_Done,
2935
423
    // Label 297: @5112
2936
423
    GIM_Try, /*On fail goto*//*Label 298*/ 5133, // Rule ID 1939 //
2937
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2938
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2939
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2940
423
      // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
2941
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2942
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2943
423
      // GIR_Coverage, 1939,
2944
423
      GIR_Done,
2945
423
    // Label 298: @5133
2946
423
    GIM_Try, /*On fail goto*//*Label 299*/ 5154, // Rule ID 1940 //
2947
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2948
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2949
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2950
423
      // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
2951
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2952
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2953
423
      // GIR_Coverage, 1940,
2954
423
      GIR_Done,
2955
423
    // Label 299: @5154
2956
423
    GIM_Try, /*On fail goto*//*Label 300*/ 5175, // Rule ID 1941 //
2957
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2958
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2959
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2960
423
      // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
2961
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2962
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2963
423
      // GIR_Coverage, 1941,
2964
423
      GIR_Done,
2965
423
    // Label 300: @5175
2966
423
    GIM_Try, /*On fail goto*//*Label 301*/ 5196, // Rule ID 1942 //
2967
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2968
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2969
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2970
423
      // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
2971
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2972
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2973
423
      // GIR_Coverage, 1942,
2974
423
      GIR_Done,
2975
423
    // Label 301: @5196
2976
423
    GIM_Try, /*On fail goto*//*Label 302*/ 5217, // Rule ID 1948 //
2977
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2978
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2979
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2980
423
      // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
2981
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2982
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2983
423
      // GIR_Coverage, 1948,
2984
423
      GIR_Done,
2985
423
    // Label 302: @5217
2986
423
    GIM_Try, /*On fail goto*//*Label 303*/ 5238, // Rule ID 1949 //
2987
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2988
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2989
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2990
423
      // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
2991
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2992
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2993
423
      // GIR_Coverage, 1949,
2994
423
      GIR_Done,
2995
423
    // Label 303: @5238
2996
423
    GIM_Try, /*On fail goto*//*Label 304*/ 5259, // Rule ID 1950 //
2997
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2998
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2999
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3000
423
      // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
3001
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3002
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3003
423
      // GIR_Coverage, 1950,
3004
423
      GIR_Done,
3005
423
    // Label 304: @5259
3006
423
    GIM_Try, /*On fail goto*//*Label 305*/ 5280, // Rule ID 1951 //
3007
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3008
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3009
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3010
423
      // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
3011
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3012
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3013
423
      // GIR_Coverage, 1951,
3014
423
      GIR_Done,
3015
423
    // Label 305: @5280
3016
423
    GIM_Try, /*On fail goto*//*Label 306*/ 5301, // Rule ID 1952 //
3017
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3018
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3019
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3020
423
      // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
3021
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3022
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3023
423
      // GIR_Coverage, 1952,
3024
423
      GIR_Done,
3025
423
    // Label 306: @5301
3026
423
    GIM_Try, /*On fail goto*//*Label 307*/ 5401, // Rule ID 1957 //
3027
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3028
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3029
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3030
423
      // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3031
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3032
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3033
423
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3034
423
      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3035
423
      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
3036
423
      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
3037
423
      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3038
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
3039
423
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
3040
423
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3041
423
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
3042
423
      GIR_AddImm, /*InsnID*/3, /*Imm*/27,
3043
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3044
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3045
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3046
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
3047
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3048
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3049
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3050
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3051
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3052
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3053
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3054
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3055
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3056
423
      GIR_EraseFromParent, /*InsnID*/0,
3057
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3058
423
      // GIR_Coverage, 1957,
3059
423
      GIR_Done,
3060
423
    // Label 307: @5401
3061
423
    GIM_Try, /*On fail goto*//*Label 308*/ 5501, // Rule ID 1958 //
3062
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3063
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3064
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3065
423
      // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3066
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3067
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3068
423
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3069
423
      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3070
423
      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
3071
423
      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
3072
423
      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3073
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
3074
423
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
3075
423
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3076
423
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
3077
423
      GIR_AddImm, /*InsnID*/3, /*Imm*/27,
3078
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3079
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3080
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3081
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
3082
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3083
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3084
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3085
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3086
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3087
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3088
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3089
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3090
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3091
423
      GIR_EraseFromParent, /*InsnID*/0,
3092
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3093
423
      // GIR_Coverage, 1958,
3094
423
      GIR_Done,
3095
423
    // Label 308: @5501
3096
423
    GIM_Try, /*On fail goto*//*Label 309*/ 5566, // Rule ID 1962 //
3097
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3098
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3099
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3100
423
      // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3101
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3102
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3103
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3104
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3105
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3106
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3107
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3108
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3109
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3110
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3111
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3112
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3113
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3114
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3115
423
      GIR_EraseFromParent, /*InsnID*/0,
3116
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3117
423
      // GIR_Coverage, 1962,
3118
423
      GIR_Done,
3119
423
    // Label 309: @5566
3120
423
    GIM_Try, /*On fail goto*//*Label 310*/ 5631, // Rule ID 1963 //
3121
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3122
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3123
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3124
423
      // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3125
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3126
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3127
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3128
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3129
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3130
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3131
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3132
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3133
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3134
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3135
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3136
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3137
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3138
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3139
423
      GIR_EraseFromParent, /*InsnID*/0,
3140
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3141
423
      // GIR_Coverage, 1963,
3142
423
      GIR_Done,
3143
423
    // Label 310: @5631
3144
423
    GIM_Try, /*On fail goto*//*Label 311*/ 5696, // Rule ID 1967 //
3145
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3146
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3147
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3148
423
      // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3149
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3150
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3151
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3152
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3153
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3154
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3155
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3156
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3157
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3158
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3159
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3160
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3161
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3162
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3163
423
      GIR_EraseFromParent, /*InsnID*/0,
3164
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3165
423
      // GIR_Coverage, 1967,
3166
423
      GIR_Done,
3167
423
    // Label 311: @5696
3168
423
    GIM_Try, /*On fail goto*//*Label 312*/ 5761, // Rule ID 1968 //
3169
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3170
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3171
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3172
423
      // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3173
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3174
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3175
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3176
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3177
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3178
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3179
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3180
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3181
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3182
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3183
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3184
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3185
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3186
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3187
423
      GIR_EraseFromParent, /*InsnID*/0,
3188
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3189
423
      // GIR_Coverage, 1968,
3190
423
      GIR_Done,
3191
423
    // Label 312: @5761
3192
423
    GIM_Try, /*On fail goto*//*Label 313*/ 5826, // Rule ID 1972 //
3193
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3194
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3195
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3196
423
      // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3197
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3198
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3199
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3200
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3201
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3202
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3203
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3204
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3205
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3206
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3207
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3208
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3209
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3210
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3211
423
      GIR_EraseFromParent, /*InsnID*/0,
3212
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3213
423
      // GIR_Coverage, 1972,
3214
423
      GIR_Done,
3215
423
    // Label 313: @5826
3216
423
    GIM_Try, /*On fail goto*//*Label 314*/ 5891, // Rule ID 1973 //
3217
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3218
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3219
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3220
423
      // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3221
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3222
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3223
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3224
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3225
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3226
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3227
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3228
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3229
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3230
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3231
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3232
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3233
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3234
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3235
423
      GIR_EraseFromParent, /*InsnID*/0,
3236
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3237
423
      // GIR_Coverage, 1973,
3238
423
      GIR_Done,
3239
423
    // Label 314: @5891
3240
423
    GIM_Try, /*On fail goto*//*Label 315*/ 5956, // Rule ID 1977 //
3241
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3242
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3243
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3244
423
      // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3245
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3246
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3247
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3248
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3249
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3250
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3251
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3252
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3253
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3254
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3255
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3256
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3257
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3258
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3259
423
      GIR_EraseFromParent, /*InsnID*/0,
3260
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3261
423
      // GIR_Coverage, 1977,
3262
423
      GIR_Done,
3263
423
    // Label 315: @5956
3264
423
    GIM_Try, /*On fail goto*//*Label 316*/ 6021, // Rule ID 1978 //
3265
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3266
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3267
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3268
423
      // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3269
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3270
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3271
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3272
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3273
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3274
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3275
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3276
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3277
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3278
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3279
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3280
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3281
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3282
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3283
423
      GIR_EraseFromParent, /*InsnID*/0,
3284
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3285
423
      // GIR_Coverage, 1978,
3286
423
      GIR_Done,
3287
423
    // Label 316: @6021
3288
423
    GIM_Reject,
3289
423
    // Label 274: @6022
3290
423
    GIM_Try, /*On fail goto*//*Label 317*/ 6067,
3291
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3292
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
3293
423
      GIM_Try, /*On fail goto*//*Label 318*/ 6049, // Rule ID 1834 //
3294
423
        GIM_CheckFeatures, GIFBS_HasDSP,
3295
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
3296
423
        // (bitconvert:{ *:[v4i8] } GPR32:{ *:[i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i8] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
3297
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3298
423
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
3299
423
        // GIR_Coverage, 1834,
3300
423
        GIR_Done,
3301
423
      // Label 318: @6049
3302
423
      GIM_Try, /*On fail goto*//*Label 319*/ 6066, // Rule ID 1838 //
3303
423
        GIM_CheckFeatures, GIFBS_HasDSP,
3304
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
3305
423
        // (bitconvert:{ *:[v4i8] } FGR32:{ *:[f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i8] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
3306
423
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3307
423
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
3308
423
        // GIR_Coverage, 1838,
3309
423
        GIR_Done,
3310
423
      // Label 319: @6066
3311
423
      GIM_Reject,
3312
423
    // Label 317: @6067
3313
423
    GIM_Reject,
3314
423
    // Label 275: @6068
3315
423
    GIM_Try, /*On fail goto*//*Label 320*/ 6089, // Rule ID 1917 //
3316
423
      GIM_CheckFeatures, GIFBS_HasMSA,
3317
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3318
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3319
423
      // (bitconvert:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] })
3320
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3321
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3322
423
      // GIR_Coverage, 1917,
3323
423
      GIR_Done,
3324
423
    // Label 320: @6089
3325
423
    GIM_Try, /*On fail goto*//*Label 321*/ 6110, // Rule ID 1920 //
3326
423
      GIM_CheckFeatures, GIFBS_HasMSA,
3327
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3328
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3329
423
      // (bitconvert:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] })
3330
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3331
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3332
423
      // GIR_Coverage, 1920,
3333
423
      GIR_Done,
3334
423
    // Label 321: @6110
3335
423
    GIM_Try, /*On fail goto*//*Label 322*/ 6131, // Rule ID 1933 //
3336
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3337
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3338
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3339
423
      // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3340
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3341
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3342
423
      // GIR_Coverage, 1933,
3343
423
      GIR_Done,
3344
423
    // Label 322: @6131
3345
423
    GIM_Try, /*On fail goto*//*Label 323*/ 6152, // Rule ID 1934 //
3346
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3347
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3348
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3349
423
      // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3350
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3351
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3352
423
      // GIR_Coverage, 1934,
3353
423
      GIR_Done,
3354
423
    // Label 323: @6152
3355
423
    GIM_Try, /*On fail goto*//*Label 324*/ 6173, // Rule ID 1935 //
3356
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3357
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3358
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3359
423
      // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3360
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3361
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3362
423
      // GIR_Coverage, 1935,
3363
423
      GIR_Done,
3364
423
    // Label 324: @6173
3365
423
    GIM_Try, /*On fail goto*//*Label 325*/ 6194, // Rule ID 1936 //
3366
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3367
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3368
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3369
423
      // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3370
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3371
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3372
423
      // GIR_Coverage, 1936,
3373
423
      GIR_Done,
3374
423
    // Label 325: @6194
3375
423
    GIM_Try, /*On fail goto*//*Label 326*/ 6215, // Rule ID 1937 //
3376
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3377
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3378
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3379
423
      // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3380
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3381
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3382
423
      // GIR_Coverage, 1937,
3383
423
      GIR_Done,
3384
423
    // Label 326: @6215
3385
423
    GIM_Try, /*On fail goto*//*Label 327*/ 6236, // Rule ID 1943 //
3386
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3387
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3388
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3389
423
      // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3390
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3391
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3392
423
      // GIR_Coverage, 1943,
3393
423
      GIR_Done,
3394
423
    // Label 327: @6236
3395
423
    GIM_Try, /*On fail goto*//*Label 328*/ 6257, // Rule ID 1944 //
3396
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3397
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3398
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3399
423
      // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3400
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3401
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3402
423
      // GIR_Coverage, 1944,
3403
423
      GIR_Done,
3404
423
    // Label 328: @6257
3405
423
    GIM_Try, /*On fail goto*//*Label 329*/ 6278, // Rule ID 1945 //
3406
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3407
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3408
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3409
423
      // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3410
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3411
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3412
423
      // GIR_Coverage, 1945,
3413
423
      GIR_Done,
3414
423
    // Label 329: @6278
3415
423
    GIM_Try, /*On fail goto*//*Label 330*/ 6299, // Rule ID 1946 //
3416
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3417
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3418
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3419
423
      // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3420
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3421
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3422
423
      // GIR_Coverage, 1946,
3423
423
      GIR_Done,
3424
423
    // Label 330: @6299
3425
423
    GIM_Try, /*On fail goto*//*Label 331*/ 6320, // Rule ID 1947 //
3426
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3427
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3428
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3429
423
      // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3430
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3431
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3432
423
      // GIR_Coverage, 1947,
3433
423
      GIR_Done,
3434
423
    // Label 331: @6320
3435
423
    GIM_Try, /*On fail goto*//*Label 332*/ 6385, // Rule ID 1955 //
3436
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3437
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3438
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3439
423
      // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3440
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3441
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3442
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3443
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3444
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3445
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3446
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3447
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3448
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3449
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3450
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3451
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3452
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3453
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3454
423
      GIR_EraseFromParent, /*InsnID*/0,
3455
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3456
423
      // GIR_Coverage, 1955,
3457
423
      GIR_Done,
3458
423
    // Label 332: @6385
3459
423
    GIM_Try, /*On fail goto*//*Label 333*/ 6450, // Rule ID 1956 //
3460
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3461
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3462
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3463
423
      // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3464
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3465
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3466
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3467
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3468
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3469
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3470
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3471
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3472
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3473
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3474
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3475
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3476
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3477
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3478
423
      GIR_EraseFromParent, /*InsnID*/0,
3479
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3480
423
      // GIR_Coverage, 1956,
3481
423
      GIR_Done,
3482
423
    // Label 333: @6450
3483
423
    GIM_Try, /*On fail goto*//*Label 334*/ 6515, // Rule ID 1960 //
3484
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3485
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3486
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3487
423
      // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3488
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3489
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3490
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3491
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3492
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3493
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3494
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3495
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3496
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3497
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3498
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3499
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3500
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3501
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3502
423
      GIR_EraseFromParent, /*InsnID*/0,
3503
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3504
423
      // GIR_Coverage, 1960,
3505
423
      GIR_Done,
3506
423
    // Label 334: @6515
3507
423
    GIM_Try, /*On fail goto*//*Label 335*/ 6580, // Rule ID 1961 //
3508
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3509
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3510
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3511
423
      // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3512
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3513
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3514
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3515
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3516
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3517
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3518
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3519
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3520
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3521
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3522
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3523
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3524
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3525
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3526
423
      GIR_EraseFromParent, /*InsnID*/0,
3527
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3528
423
      // GIR_Coverage, 1961,
3529
423
      GIR_Done,
3530
423
    // Label 335: @6580
3531
423
    GIM_Try, /*On fail goto*//*Label 336*/ 6645, // Rule ID 1965 //
3532
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3533
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3534
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3535
423
      // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3536
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3537
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3538
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3539
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3540
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3541
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3542
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3543
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3544
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3545
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3546
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3547
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3548
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3549
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3550
423
      GIR_EraseFromParent, /*InsnID*/0,
3551
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3552
423
      // GIR_Coverage, 1965,
3553
423
      GIR_Done,
3554
423
    // Label 336: @6645
3555
423
    GIM_Try, /*On fail goto*//*Label 337*/ 6710, // Rule ID 1966 //
3556
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3557
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3558
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3559
423
      // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3560
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3561
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3562
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3563
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3564
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3565
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3566
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3567
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3568
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3569
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3570
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3571
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3572
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3573
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3574
423
      GIR_EraseFromParent, /*InsnID*/0,
3575
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3576
423
      // GIR_Coverage, 1966,
3577
423
      GIR_Done,
3578
423
    // Label 337: @6710
3579
423
    GIM_Try, /*On fail goto*//*Label 338*/ 6775, // Rule ID 1982 //
3580
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3581
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3582
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3583
423
      // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3584
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3585
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3586
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3587
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3588
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3589
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3590
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3591
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3592
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3593
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3594
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3595
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3596
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3597
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3598
423
      GIR_EraseFromParent, /*InsnID*/0,
3599
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3600
423
      // GIR_Coverage, 1982,
3601
423
      GIR_Done,
3602
423
    // Label 338: @6775
3603
423
    GIM_Try, /*On fail goto*//*Label 339*/ 6840, // Rule ID 1983 //
3604
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3605
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3606
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3607
423
      // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3608
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3609
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3610
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3611
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3612
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3613
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3614
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3615
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3616
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3617
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3618
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3619
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3620
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3621
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3622
423
      GIR_EraseFromParent, /*InsnID*/0,
3623
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3624
423
      // GIR_Coverage, 1983,
3625
423
      GIR_Done,
3626
423
    // Label 339: @6840
3627
423
    GIM_Try, /*On fail goto*//*Label 340*/ 6905, // Rule ID 1987 //
3628
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3629
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3630
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3631
423
      // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3632
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3633
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3634
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3635
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3636
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3637
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3638
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3639
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3640
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3641
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3642
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3643
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3644
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3645
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3646
423
      GIR_EraseFromParent, /*InsnID*/0,
3647
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3648
423
      // GIR_Coverage, 1987,
3649
423
      GIR_Done,
3650
423
    // Label 340: @6905
3651
423
    GIM_Try, /*On fail goto*//*Label 341*/ 6970, // Rule ID 1988 //
3652
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3653
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3654
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3655
423
      // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3656
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3657
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3658
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3659
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3660
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3661
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3662
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3663
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3664
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3665
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3666
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3667
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3668
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3669
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3670
423
      GIR_EraseFromParent, /*InsnID*/0,
3671
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3672
423
      // GIR_Coverage, 1988,
3673
423
      GIR_Done,
3674
423
    // Label 341: @6970
3675
423
    GIM_Reject,
3676
423
    // Label 276: @6971
3677
423
    GIM_Try, /*On fail goto*//*Label 342*/ 6992, // Rule ID 1916 //
3678
423
      GIM_CheckFeatures, GIFBS_HasMSA,
3679
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3680
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3681
423
      // (bitconvert:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] })
3682
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3683
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3684
423
      // GIR_Coverage, 1916,
3685
423
      GIR_Done,
3686
423
    // Label 342: @6992
3687
423
    GIM_Try, /*On fail goto*//*Label 343*/ 7013, // Rule ID 1919 //
3688
423
      GIM_CheckFeatures, GIFBS_HasMSA,
3689
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3690
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3691
423
      // (bitconvert:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] })
3692
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3693
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3694
423
      // GIR_Coverage, 1919,
3695
423
      GIR_Done,
3696
423
    // Label 343: @7013
3697
423
    GIM_Try, /*On fail goto*//*Label 344*/ 7034, // Rule ID 1928 //
3698
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3699
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3700
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3701
423
      // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src, MSA128H:{ *:[i32] })
3702
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3703
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3704
423
      // GIR_Coverage, 1928,
3705
423
      GIR_Done,
3706
423
    // Label 344: @7034
3707
423
    GIM_Try, /*On fail goto*//*Label 345*/ 7055, // Rule ID 1929 //
3708
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3709
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3710
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3711
423
      // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] })
3712
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3713
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3714
423
      // GIR_Coverage, 1929,
3715
423
      GIR_Done,
3716
423
    // Label 345: @7055
3717
423
    GIM_Try, /*On fail goto*//*Label 346*/ 7076, // Rule ID 1930 //
3718
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3719
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3720
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3721
423
      // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] })
3722
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3723
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3724
423
      // GIR_Coverage, 1930,
3725
423
      GIR_Done,
3726
423
    // Label 346: @7076
3727
423
    GIM_Try, /*On fail goto*//*Label 347*/ 7097, // Rule ID 1931 //
3728
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3729
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3730
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3731
423
      // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] })
3732
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3733
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3734
423
      // GIR_Coverage, 1931,
3735
423
      GIR_Done,
3736
423
    // Label 347: @7097
3737
423
    GIM_Try, /*On fail goto*//*Label 348*/ 7118, // Rule ID 1932 //
3738
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3739
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3740
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3741
423
      // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] })
3742
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3743
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3744
423
      // GIR_Coverage, 1932,
3745
423
      GIR_Done,
3746
423
    // Label 348: @7118
3747
423
    GIM_Try, /*On fail goto*//*Label 349*/ 7183, // Rule ID 1953 //
3748
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3749
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3750
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3751
423
      // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3752
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3753
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3754
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3755
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3756
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3757
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3758
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3759
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3760
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3761
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3762
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3763
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3764
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3765
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3766
423
      GIR_EraseFromParent, /*InsnID*/0,
3767
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3768
423
      // GIR_Coverage, 1953,
3769
423
      GIR_Done,
3770
423
    // Label 349: @7183
3771
423
    GIM_Try, /*On fail goto*//*Label 350*/ 7248, // Rule ID 1954 //
3772
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3773
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3774
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3775
423
      // (bitconvert:{ *:[v8f16] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3776
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3777
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3778
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3779
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3780
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3781
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3782
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3783
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3784
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3785
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3786
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3787
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3788
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3789
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3790
423
      GIR_EraseFromParent, /*InsnID*/0,
3791
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3792
423
      // GIR_Coverage, 1954,
3793
423
      GIR_Done,
3794
423
    // Label 350: @7248
3795
423
    GIM_Try, /*On fail goto*//*Label 351*/ 7313, // Rule ID 1970 //
3796
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3797
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3798
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3799
423
      // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3800
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3801
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3802
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3803
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3804
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3805
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3806
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3807
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3808
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3809
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3810
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3811
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3812
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3813
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3814
423
      GIR_EraseFromParent, /*InsnID*/0,
3815
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3816
423
      // GIR_Coverage, 1970,
3817
423
      GIR_Done,
3818
423
    // Label 351: @7313
3819
423
    GIM_Try, /*On fail goto*//*Label 352*/ 7378, // Rule ID 1971 //
3820
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3821
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3822
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3823
423
      // (bitconvert:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3824
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3825
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3826
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3827
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3828
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3829
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3830
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3831
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3832
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3833
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3834
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3835
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3836
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3837
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3838
423
      GIR_EraseFromParent, /*InsnID*/0,
3839
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3840
423
      // GIR_Coverage, 1971,
3841
423
      GIR_Done,
3842
423
    // Label 352: @7378
3843
423
    GIM_Try, /*On fail goto*//*Label 353*/ 7443, // Rule ID 1975 //
3844
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3845
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3846
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3847
423
      // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3848
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3849
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3850
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3851
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3852
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3853
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3854
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3855
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3856
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3857
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3858
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3859
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3860
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3861
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3862
423
      GIR_EraseFromParent, /*InsnID*/0,
3863
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3864
423
      // GIR_Coverage, 1975,
3865
423
      GIR_Done,
3866
423
    // Label 353: @7443
3867
423
    GIM_Try, /*On fail goto*//*Label 354*/ 7508, // Rule ID 1976 //
3868
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3869
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3870
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3871
423
      // (bitconvert:{ *:[v8f16] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3872
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3873
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3874
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3875
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3876
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3877
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3878
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3879
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3880
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3881
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3882
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3883
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3884
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3885
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3886
423
      GIR_EraseFromParent, /*InsnID*/0,
3887
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3888
423
      // GIR_Coverage, 1976,
3889
423
      GIR_Done,
3890
423
    // Label 354: @7508
3891
423
    GIM_Try, /*On fail goto*//*Label 355*/ 7573, // Rule ID 1980 //
3892
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3893
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3894
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3895
423
      // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3896
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3897
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3898
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3899
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3900
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3901
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3902
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3903
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3904
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3905
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3906
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3907
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3908
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3909
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3910
423
      GIR_EraseFromParent, /*InsnID*/0,
3911
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3912
423
      // GIR_Coverage, 1980,
3913
423
      GIR_Done,
3914
423
    // Label 355: @7573
3915
423
    GIM_Try, /*On fail goto*//*Label 356*/ 7638, // Rule ID 1981 //
3916
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3917
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3918
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3919
423
      // (bitconvert:{ *:[v8f16] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3920
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3921
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3922
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3923
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3924
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3925
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3926
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3927
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3928
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3929
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3930
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3931
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3932
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3933
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3934
423
      GIR_EraseFromParent, /*InsnID*/0,
3935
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3936
423
      // GIR_Coverage, 1981,
3937
423
      GIR_Done,
3938
423
    // Label 356: @7638
3939
423
    GIM_Try, /*On fail goto*//*Label 357*/ 7703, // Rule ID 1985 //
3940
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3941
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3942
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3943
423
      // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3944
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3945
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3946
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3947
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3948
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3949
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3950
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3951
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3952
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3953
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3954
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3955
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3956
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3957
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3958
423
      GIR_EraseFromParent, /*InsnID*/0,
3959
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3960
423
      // GIR_Coverage, 1985,
3961
423
      GIR_Done,
3962
423
    // Label 357: @7703
3963
423
    GIM_Try, /*On fail goto*//*Label 358*/ 7768, // Rule ID 1986 //
3964
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3965
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3966
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3967
423
      // (bitconvert:{ *:[v8f16] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3968
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3969
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3970
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3971
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3972
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3973
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3974
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3975
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3976
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3977
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3978
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3979
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3980
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3981
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3982
423
      GIR_EraseFromParent, /*InsnID*/0,
3983
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3984
423
      // GIR_Coverage, 1986,
3985
423
      GIR_Done,
3986
423
    // Label 358: @7768
3987
423
    GIM_Reject,
3988
423
    // Label 277: @7769
3989
423
    GIM_Try, /*On fail goto*//*Label 359*/ 7790, // Rule ID 1922 //
3990
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3991
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3992
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
3993
423
      // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] })
3994
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3995
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
3996
423
      // GIR_Coverage, 1922,
3997
423
      GIR_Done,
3998
423
    // Label 359: @7790
3999
423
    GIM_Try, /*On fail goto*//*Label 360*/ 7811, // Rule ID 1923 //
4000
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4001
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4002
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4003
423
      // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] })
4004
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4005
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4006
423
      // GIR_Coverage, 1923,
4007
423
      GIR_Done,
4008
423
    // Label 360: @7811
4009
423
    GIM_Try, /*On fail goto*//*Label 361*/ 7832, // Rule ID 1924 //
4010
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4011
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4012
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4013
423
      // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] })
4014
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4015
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4016
423
      // GIR_Coverage, 1924,
4017
423
      GIR_Done,
4018
423
    // Label 361: @7832
4019
423
    GIM_Try, /*On fail goto*//*Label 362*/ 7853, // Rule ID 1925 //
4020
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4021
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4022
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4023
423
      // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] })
4024
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4025
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4026
423
      // GIR_Coverage, 1925,
4027
423
      GIR_Done,
4028
423
    // Label 362: @7853
4029
423
    GIM_Try, /*On fail goto*//*Label 363*/ 7874, // Rule ID 1926 //
4030
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4031
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4032
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4033
423
      // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] })
4034
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4035
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4036
423
      // GIR_Coverage, 1926,
4037
423
      GIR_Done,
4038
423
    // Label 363: @7874
4039
423
    GIM_Try, /*On fail goto*//*Label 364*/ 7895, // Rule ID 1927 //
4040
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4041
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4042
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4043
423
      // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] })
4044
423
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4045
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4046
423
      // GIR_Coverage, 1927,
4047
423
      GIR_Done,
4048
423
    // Label 364: @7895
4049
423
    GIM_Try, /*On fail goto*//*Label 365*/ 7960, // Rule ID 1959 //
4050
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4051
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4052
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4053
423
      // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4054
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4055
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4056
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4057
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4058
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4059
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4060
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4061
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4062
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4063
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4064
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4065
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4066
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4067
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4068
423
      GIR_EraseFromParent, /*InsnID*/0,
4069
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4070
423
      // GIR_Coverage, 1959,
4071
423
      GIR_Done,
4072
423
    // Label 365: @7960
4073
423
    GIM_Try, /*On fail goto*//*Label 366*/ 8025, // Rule ID 1964 //
4074
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4075
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4076
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4077
423
      // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4078
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4079
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4080
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4081
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4082
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4083
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4084
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4085
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4086
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4087
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4088
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4089
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4090
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4091
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4092
423
      GIR_EraseFromParent, /*InsnID*/0,
4093
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4094
423
      // GIR_Coverage, 1964,
4095
423
      GIR_Done,
4096
423
    // Label 366: @8025
4097
423
    GIM_Try, /*On fail goto*//*Label 367*/ 8090, // Rule ID 1969 //
4098
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4099
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4100
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4101
423
      // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
4102
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4103
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4104
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4105
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4106
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4107
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4108
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4109
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4110
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4111
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
4112
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4113
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4114
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4115
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4116
423
      GIR_EraseFromParent, /*InsnID*/0,
4117
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4118
423
      // GIR_Coverage, 1969,
4119
423
      GIR_Done,
4120
423
    // Label 367: @8090
4121
423
    GIM_Try, /*On fail goto*//*Label 368*/ 8155, // Rule ID 1974 //
4122
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4123
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4124
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4125
423
      // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
4126
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4127
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4128
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4129
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4130
423
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4131
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4132
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4133
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4134
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4135
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
4136
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4137
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4138
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4139
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4140
423
      GIR_EraseFromParent, /*InsnID*/0,
4141
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4142
423
      // GIR_Coverage, 1974,
4143
423
      GIR_Done,
4144
423
    // Label 368: @8155
4145
423
    GIM_Try, /*On fail goto*//*Label 369*/ 8255, // Rule ID 1979 //
4146
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4147
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4148
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4149
423
      // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4150
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4151
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4152
423
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4153
423
      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4154
423
      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
4155
423
      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
4156
423
      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4157
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
4158
423
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
4159
423
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
4160
423
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
4161
423
      GIR_AddImm, /*InsnID*/3, /*Imm*/27,
4162
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4163
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4164
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4165
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
4166
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4167
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
4168
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4169
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4170
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4171
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4172
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4173
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4174
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4175
423
      GIR_EraseFromParent, /*InsnID*/0,
4176
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4177
423
      // GIR_Coverage, 1979,
4178
423
      GIR_Done,
4179
423
    // Label 369: @8255
4180
423
    GIM_Try, /*On fail goto*//*Label 370*/ 8355, // Rule ID 1984 //
4181
423
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4182
423
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4183
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4184
423
      // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4185
423
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4186
423
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4187
423
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4188
423
      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4189
423
      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
4190
423
      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
4191
423
      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4192
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
4193
423
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
4194
423
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
4195
423
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
4196
423
      GIR_AddImm, /*InsnID*/3, /*Imm*/27,
4197
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4198
423
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4199
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4200
423
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
4201
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4202
423
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
4203
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4204
423
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4205
423
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4206
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4207
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4208
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4209
423
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4210
423
      GIR_EraseFromParent, /*InsnID*/0,
4211
423
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4212
423
      // GIR_Coverage, 1984,
4213
423
      GIR_Done,
4214
423
    // Label 370: @8355
4215
423
    GIM_Reject,
4216
423
    // Label 278: @8356
4217
423
    GIM_Reject,
4218
423
    // Label 11: @8357
4219
423
    GIM_Try, /*On fail goto*//*Label 371*/ 8422, // Rule ID 1907 //
4220
423
      GIM_CheckFeatures, GIFBS_HasDSP,
4221
423
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4222
423
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
4223
423
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
4224
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4225
423
      // MIs[0] Operand 1
4226
423
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4227
423
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4228
423
      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4229
423
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4230
423
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4231
423
      GIM_CheckIsSafeToFold, /*InsnID*/1,
4232
423
      // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LWX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4233
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LWX,
4234
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4235
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4236
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4237
423
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
4238
423
      GIR_EraseFromParent, /*InsnID*/0,
4239
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4240
423
      // GIR_Coverage, 1907,
4241
423
      GIR_Done,
4242
423
    // Label 371: @8422
4243
423
    GIM_Reject,
4244
423
    // Label 12: @8423
4245
423
    GIM_Try, /*On fail goto*//*Label 372*/ 8488, // Rule ID 1906 //
4246
423
      GIM_CheckFeatures, GIFBS_HasDSP,
4247
423
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4248
423
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
4249
423
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
4250
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4251
423
      // MIs[0] Operand 1
4252
423
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4253
423
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4254
423
      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4255
423
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4256
423
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4257
423
      GIM_CheckIsSafeToFold, /*InsnID*/1,
4258
423
      // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LHX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4259
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LHX,
4260
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4261
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4262
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4263
423
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
4264
423
      GIR_EraseFromParent, /*InsnID*/0,
4265
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4266
423
      // GIR_Coverage, 1906,
4267
423
      GIR_Done,
4268
423
    // Label 372: @8488
4269
423
    GIM_Reject,
4270
423
    // Label 13: @8489
4271
423
    GIM_Try, /*On fail goto*//*Label 373*/ 8554, // Rule ID 1905 //
4272
423
      GIM_CheckFeatures, GIFBS_HasDSP,
4273
423
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4274
423
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
4275
423
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
4276
423
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4277
423
      // MIs[0] Operand 1
4278
423
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4279
423
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4280
423
      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4281
423
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4282
423
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4283
423
      GIM_CheckIsSafeToFold, /*InsnID*/1,
4284
423
      // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (LBUX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4285
423
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LBUX,
4286
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4287
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4288
423
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4289
423
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
4290
423
      GIR_EraseFromParent, /*InsnID*/0,
4291
423
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4292
423
      // GIR_Coverage, 1905,
4293
423
      GIR_Done,
4294
423
    // Label 373: @8554
4295
423
    GIM_Reject,
4296
423
    // Label 14: @8555
4297
423
    GIM_Try, /*On fail goto*//*Label 374*/ 10749,
4298
423
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
4299
423
      GIM_Try, /*On fail goto*//*Label 375*/ 8607, // Rule ID 400 //
4300
423
        GIM_CheckFeatures, GIFBS_HasDSP,
4301
423
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
4302
423
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
4303
423
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4304
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4305
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4306
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4307
423
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt8,
4308
423
        // MIs[1] Operand 1
4309
423
        // No operand predicates
4310
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4311
423
        // (intrinsic_wo_chain:{ *:[v4i8] } 3622:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm)  =>  (REPL_QB:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
4312
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_QB,
4313
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4314
423
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4315
423
        GIR_EraseFromParent, /*InsnID*/0,
4316
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4317
423
        // GIR_Coverage, 400,
4318
423
        GIR_Done,
4319
423
      // Label 375: @8607
4320
423
      GIM_Try, /*On fail goto*//*Label 376*/ 8654, // Rule ID 401 //
4321
423
        GIM_CheckFeatures, GIFBS_HasDSP,
4322
423
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
4323
423
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4324
423
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4325
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4326
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4327
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4328
423
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExt10,
4329
423
        // MIs[1] Operand 1
4330
423
        // No operand predicates
4331
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4332
423
        // (intrinsic_wo_chain:{ *:[v2i16] } 3621:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm)  =>  (REPL_PH:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
4333
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_PH,
4334
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4335
423
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4336
423
        GIR_EraseFromParent, /*InsnID*/0,
4337
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4338
423
        // GIR_Coverage, 401,
4339
423
        GIR_Done,
4340
423
      // Label 376: @8654
4341
423
      GIM_Try, /*On fail goto*//*Label 377*/ 8701, // Rule ID 1254 //
4342
423
        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
4343
423
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
4344
423
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4345
423
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4346
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4347
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4348
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4349
423
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExt10,
4350
423
        // MIs[1] Operand 1
4351
423
        // No operand predicates
4352
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4353
423
        // (intrinsic_wo_chain:{ *:[v2i16] } 3621:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm)  =>  (REPL_PH_MM:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
4354
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_PH_MM,
4355
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4356
423
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4357
423
        GIR_EraseFromParent, /*InsnID*/0,
4358
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4359
423
        // GIR_Coverage, 1254,
4360
423
        GIR_Done,
4361
423
      // Label 377: @8701
4362
423
      GIM_Try, /*On fail goto*//*Label 378*/ 8748, // Rule ID 1255 //
4363
423
        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
4364
423
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
4365
423
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
4366
423
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4367
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4368
423
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4369
423
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4370
423
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt8,
4371
423
        // MIs[1] Operand 1
4372
423
        // No operand predicates
4373
423
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4374
423
        // (intrinsic_wo_chain:{ *:[v4i8] } 3622:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm)  =>  (REPL_QB_MM:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
4375
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_QB_MM,
4376
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
4377
423
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4378
423
        GIR_EraseFromParent, /*InsnID*/0,
4379
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4380
423
        // GIR_Coverage, 1255,
4381
423
        GIR_Done,
4382
423
      // Label 378: @8748
4383
423
      GIM_Try, /*On fail goto*//*Label 379*/ 8788, // Rule ID 334 //
4384
423
        GIM_CheckFeatures, GIFBS_HasDSP,
4385
423
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_raddu_w_qb,
4386
423
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4387
423
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4388
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4389
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4390
423
        // (intrinsic_wo_chain:{ *:[i32] } 3619:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (RADDU_W_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
4391
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RADDU_W_QB,
4392
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4393
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
4394
423
        GIR_EraseFromParent, /*InsnID*/0,
4395
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4396
423
        // GIR_Coverage, 334,
4397
423
        GIR_Done,
4398
423
      // Label 379: @8788
4399
423
      GIM_Try, /*On fail goto*//*Label 380*/ 8828, // Rule ID 341 //
4400
423
        GIM_CheckFeatures, GIFBS_HasDSP,
4401
423
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phl,
4402
423
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4403
423
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
4404
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4405
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4406
423
        // (intrinsic_wo_chain:{ *:[i32] } 3601:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECEQ_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
4407
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHL,
4408
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4409
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4410
423
        GIR_EraseFromParent, /*InsnID*/0,
4411
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4412
423
        // GIR_Coverage, 341,
4413
423
        GIR_Done,
4414
423
      // Label 380: @8828
4415
423
      GIM_Try, /*On fail goto*//*Label 381*/ 8868, // Rule ID 342 //
4416
423
        GIM_CheckFeatures, GIFBS_HasDSP,
4417
423
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phr,
4418
423
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4419
423
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
4420
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4421
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4422
423
        // (intrinsic_wo_chain:{ *:[i32] } 3602:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECEQ_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
4423
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHR,
4424
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4425
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4426
423
        GIR_EraseFromParent, /*InsnID*/0,
4427
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4428
423
        // GIR_Coverage, 342,
4429
423
        GIR_Done,
4430
423
      // Label 381: @8868
4431
423
      GIM_Try, /*On fail goto*//*Label 382*/ 8908, // Rule ID 343 //
4432
423
        GIM_CheckFeatures, GIFBS_HasDSP,
4433
423
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbl,
4434
423
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4435
423
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4436
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4437
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4438
423
        // (intrinsic_wo_chain:{ *:[v2i16] } 3603:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4439
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBL,
4440
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4441
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4442
423
        GIR_EraseFromParent, /*InsnID*/0,
4443
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4444
423
        // GIR_Coverage, 343,
4445
423
        GIR_Done,
4446
423
      // Label 382: @8908
4447
423
      GIM_Try, /*On fail goto*//*Label 383*/ 8948, // Rule ID 344 //
4448
423
        GIM_CheckFeatures, GIFBS_HasDSP,
4449
423
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbr,
4450
423
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4451
423
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4452
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4453
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4454
423
        // (intrinsic_wo_chain:{ *:[v2i16] } 3605:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4455
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBR,
4456
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4457
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4458
423
        GIR_EraseFromParent, /*InsnID*/0,
4459
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4460
423
        // GIR_Coverage, 344,
4461
423
        GIR_Done,
4462
423
      // Label 383: @8948
4463
423
      GIM_Try, /*On fail goto*//*Label 384*/ 8988, // Rule ID 345 //
4464
423
        GIM_CheckFeatures, GIFBS_HasDSP,
4465
423
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbla,
4466
423
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4467
423
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4468
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4469
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4470
423
        // (intrinsic_wo_chain:{ *:[v2i16] } 3604:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4471
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBLA,
4472
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4473
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4474
423
        GIR_EraseFromParent, /*InsnID*/0,
4475
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4476
423
        // GIR_Coverage, 345,
4477
423
        GIR_Done,
4478
423
      // Label 384: @8988
4479
423
      GIM_Try, /*On fail goto*//*Label 385*/ 9028, // Rule ID 346 //
4480
423
        GIM_CheckFeatures, GIFBS_HasDSP,
4481
423
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbra,
4482
423
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4483
423
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4484
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4485
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4486
423
        // (intrinsic_wo_chain:{ *:[v2i16] } 3606:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4487
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBRA,
4488
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4489
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4490
423
        GIR_EraseFromParent, /*InsnID*/0,
4491
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4492
423
        // GIR_Coverage, 346,
4493
423
        GIR_Done,
4494
423
      // Label 385: @9028
4495
423
      GIM_Try, /*On fail goto*//*Label 386*/ 9068, // Rule ID 347 //
4496
423
        GIM_CheckFeatures, GIFBS_HasDSP,
4497
423
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbl,
4498
423
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4499
423
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4500
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4501
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4502
423
        // (intrinsic_wo_chain:{ *:[v2i16] } 3607:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4503
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBL,
4504
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4505
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4506
423
        GIR_EraseFromParent, /*InsnID*/0,
4507
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4508
423
        // GIR_Coverage, 347,
4509
423
        GIR_Done,
4510
423
      // Label 386: @9068
4511
423
      GIM_Try, /*On fail goto*//*Label 387*/ 9108, // Rule ID 348 //
4512
423
        GIM_CheckFeatures, GIFBS_HasDSP,
4513
423
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbr,
4514
423
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4515
423
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4516
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4517
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4518
423
        // (intrinsic_wo_chain:{ *:[v2i16] } 3609:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4519
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBR,
4520
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4521
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4522
423
        GIR_EraseFromParent, /*InsnID*/0,
4523
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4524
423
        // GIR_Coverage, 348,
4525
423
        GIR_Done,
4526
423
      // Label 387: @9108
4527
423
      GIM_Try, /*On fail goto*//*Label 388*/ 9148, // Rule ID 349 //
4528
423
        GIM_CheckFeatures, GIFBS_HasDSP,
4529
423
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbla,
4530
423
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4531
423
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4532
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4533
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4534
423
        // (intrinsic_wo_chain:{ *:[v2i16] } 3608:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4535
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBLA,
4536
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4537
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4538
423
        GIR_EraseFromParent, /*InsnID*/0,
4539
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4540
423
        // GIR_Coverage, 349,
4541
423
        GIR_Done,
4542
423
      // Label 388: @9148
4543
423
      GIM_Try, /*On fail goto*//*Label 389*/ 9188, // Rule ID 350 //
4544
423
        GIM_CheckFeatures, GIFBS_HasDSP,
4545
423
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbra,
4546
423
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4547
423
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4548
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4549
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4550
423
        // (intrinsic_wo_chain:{ *:[v2i16] } 3610:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4551
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBRA,
4552
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4553
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4554
423
        GIR_EraseFromParent, /*InsnID*/0,
4555
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4556
423
        // GIR_Coverage, 350,
4557
423
        GIR_Done,
4558
423
      // Label 389: @9188
4559
423
      GIM_Try, /*On fail goto*//*Label 390*/ 9228, // Rule ID 398 //
4560
423
        GIM_CheckFeatures, GIFBS_HasDSP,
4561
423
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_bitrev,
4562
423
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4563
423
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4564
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4565
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
4566
423
        // (intrinsic_wo_chain:{ *:[i32] } 3177:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (BITREV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
4567
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BITREV,
4568
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4569
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4570
423
        GIR_EraseFromParent, /*InsnID*/0,
4571
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4572
423
        // GIR_Coverage, 398,
4573
423
        GIR_Done,
4574
423
      // Label 390: @9228
4575
423
      GIM_Try, /*On fail goto*//*Label 391*/ 9268, // Rule ID 402 //
4576
423
        GIM_CheckFeatures, GIFBS_HasDSP,
4577
423
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
4578
423
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
4579
423
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4580
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4581
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
4582
423
        // (intrinsic_wo_chain:{ *:[v4i8] } 3622:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (REPLV_QB:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rt)
4583
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_QB,
4584
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4585
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4586
423
        GIR_EraseFromParent, /*InsnID*/0,
4587
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4588
423
        // GIR_Coverage, 402,
4589
423
        GIR_Done,
4590
423
      // Label 391: @9268
4591
423
      GIM_Try, /*On fail goto*//*Label 392*/ 9308, // Rule ID 403 //
4592
423
        GIM_CheckFeatures, GIFBS_HasDSP,
4593
423
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
4594
423
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4595
423
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4596
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4597
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
4598
423
        // (intrinsic_wo_chain:{ *:[v2i16] } 3621:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (REPLV_PH:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rt)
4599
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_PH,
4600
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4601
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4602
423
        GIR_EraseFromParent, /*InsnID*/0,
4603
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4604
423
        // GIR_Coverage, 403,
4605
423
        GIR_Done,
4606
423
      // Label 392: @9308
4607
423
      GIM_Try, /*On fail goto*//*Label 393*/ 9348, // Rule ID 648 //
4608
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4609
423
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fclass_w,
4610
423
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4611
423
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4612
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4613
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4614
423
        // (intrinsic_wo_chain:{ *:[v4i32] } 3329:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FCLASS_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
4615
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCLASS_W,
4616
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4617
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4618
423
        GIR_EraseFromParent, /*InsnID*/0,
4619
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4620
423
        // GIR_Coverage, 648,
4621
423
        GIR_Done,
4622
423
      // Label 393: @9348
4623
423
      GIM_Try, /*On fail goto*//*Label 394*/ 9388, // Rule ID 649 //
4624
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4625
423
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fclass_d,
4626
423
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4627
423
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
4628
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4629
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
4630
423
        // (intrinsic_wo_chain:{ *:[v2i64] } 3328:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FCLASS_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
4631
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCLASS_D,
4632
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4633
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4634
423
        GIR_EraseFromParent, /*InsnID*/0,
4635
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4636
423
        // GIR_Coverage, 649,
4637
423
        GIR_Done,
4638
423
      // Label 394: @9388
4639
423
      GIM_Try, /*On fail goto*//*Label 395*/ 9428, // Rule ID 672 //
4640
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4641
423
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupl_w,
4642
423
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4643
423
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4644
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4645
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
4646
423
        // (intrinsic_wo_chain:{ *:[v4f32] } 3355:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws)  =>  (FEXUPL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
4647
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPL_W,
4648
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4649
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4650
423
        GIR_EraseFromParent, /*InsnID*/0,
4651
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4652
423
        // GIR_Coverage, 672,
4653
423
        GIR_Done,
4654
423
      // Label 395: @9428
4655
423
      GIM_Try, /*On fail goto*//*Label 396*/ 9468, // Rule ID 673 //
4656
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4657
423
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupl_d,
4658
423
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4659
423
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4660
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4661
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4662
423
        // (intrinsic_wo_chain:{ *:[v2f64] } 3354:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FEXUPL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
4663
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPL_D,
4664
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4665
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4666
423
        GIR_EraseFromParent, /*InsnID*/0,
4667
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4668
423
        // GIR_Coverage, 673,
4669
423
        GIR_Done,
4670
423
      // Label 396: @9468
4671
423
      GIM_Try, /*On fail goto*//*Label 397*/ 9508, // Rule ID 674 //
4672
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4673
423
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupr_w,
4674
423
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4675
423
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4676
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4677
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
4678
423
        // (intrinsic_wo_chain:{ *:[v4f32] } 3357:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws)  =>  (FEXUPR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
4679
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPR_W,
4680
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4681
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4682
423
        GIR_EraseFromParent, /*InsnID*/0,
4683
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4684
423
        // GIR_Coverage, 674,
4685
423
        GIR_Done,
4686
423
      // Label 397: @9508
4687
423
      GIM_Try, /*On fail goto*//*Label 398*/ 9548, // Rule ID 675 //
4688
423
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4689
423
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupr_d,
4690
423
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4691
423
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4692
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4693
423
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4694
423
        // (intrinsic_wo_chain:{ *:[v2f64] } 3356:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FEXUPR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
4695
423
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPR_D,
4696
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4697
423
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4698
423
        GIR_EraseFromParent, /*InsnID*/0,
4699
423
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,