Coverage Report

Created: 2018-07-20 23:04

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Mips/MipsGenGlobalISel.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Global Instruction Selector for the Mips target                            *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10
const unsigned MAX_SUBTARGET_PREDICATES = 41;
11
using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
12
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
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14
#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15
  mutable MatcherState State;
16
  typedef ComplexRendererFns(MipsInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17
  typedef void(MipsInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const;
18
  const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
19
  static MipsInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20
  static MipsInstructionSelector::CustomRendererFn CustomRenderers[];
21
  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22
  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23
  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24
  const int64_t *getMatchTable() const override;
25
  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
26
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
27
28
#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
29
, State(0),
30
ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
31
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
32
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#ifdef GET_GLOBALISEL_IMPL
34
// Bits for subtarget features that participate in instruction matching.
35
enum SubtargetFeatureBits : uint8_t {
36
  Feature_HasMips2Bit = 7,
37
  Feature_HasMips3Bit = 16,
38
  Feature_HasMips4_32Bit = 26,
39
  Feature_NotMips4_32Bit = 27,
40
  Feature_HasMips4_32r2Bit = 17,
41
  Feature_HasMips32Bit = 3,
42
  Feature_HasMips32r2Bit = 6,
43
  Feature_HasMips32r6Bit = 28,
44
  Feature_NotMips32r6Bit = 4,
45
  Feature_IsGP64bitBit = 21,
46
  Feature_IsPTR64bitBit = 23,
47
  Feature_HasMips64Bit = 24,
48
  Feature_HasMips64r2Bit = 22,
49
  Feature_HasMips64r6Bit = 29,
50
  Feature_NotMips64r6Bit = 5,
51
  Feature_InMips16ModeBit = 30,
52
  Feature_NotInMips16ModeBit = 0,
53
  Feature_HasCnMipsBit = 25,
54
  Feature_NotCnMipsBit = 8,
55
  Feature_IsN64Bit = 37,
56
  Feature_RelocNotPICBit = 9,
57
  Feature_RelocPICBit = 36,
58
  Feature_NoNaNsFPMathBit = 20,
59
  Feature_HasStdEncBit = 1,
60
  Feature_NotDSPBit = 11,
61
  Feature_InMicroMipsBit = 34,
62
  Feature_NotInMicroMipsBit = 2,
63
  Feature_IsLEBit = 39,
64
  Feature_IsBEBit = 40,
65
  Feature_IsNotNaClBit = 18,
66
  Feature_HasEVABit = 35,
67
  Feature_HasMSABit = 33,
68
  Feature_HasMadd4Bit = 19,
69
  Feature_UseIndirectJumpsHazardBit = 12,
70
  Feature_NoIndirectJumpGuardsBit = 10,
71
  Feature_AllowFPOpFusionBit = 38,
72
  Feature_IsFP64bitBit = 15,
73
  Feature_NotFP64bitBit = 14,
74
  Feature_IsNotSoftFloatBit = 13,
75
  Feature_HasDSPBit = 31,
76
  Feature_HasDSPR2Bit = 32,
77
};
78
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PredicateBitset MipsInstructionSelector::
80
9.89k
computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const {
81
9.89k
  PredicateBitset Features;
82
9.89k
  if (Subtarget->hasMips2())
83
9.89k
    Features[Feature_HasMips2Bit] = 1;
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9.89k
  if (Subtarget->hasMips3())
85
3.42k
    Features[Feature_HasMips3Bit] = 1;
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9.89k
  if (Subtarget->hasMips4_32())
87
9.62k
    Features[Feature_HasMips4_32Bit] = 1;
88
9.89k
  if (!Subtarget->hasMips4_32())
89
271
    Features[Feature_NotMips4_32Bit] = 1;
90
9.89k
  if (Subtarget->hasMips4_32r2())
91
5.69k
    Features[Feature_HasMips4_32r2Bit] = 1;
92
9.89k
  if (Subtarget->hasMips32())
93
9.28k
    Features[Feature_HasMips32Bit] = 1;
94
9.89k
  if (Subtarget->hasMips32r2())
95
3.99k
    Features[Feature_HasMips32r2Bit] = 1;
96
9.89k
  if (Subtarget->hasMips32r6())
97
1.20k
    Features[Feature_HasMips32r6Bit] = 1;
98
9.89k
  if (!Subtarget->hasMips32r6())
99
8.68k
    Features[Feature_NotMips32r6Bit] = 1;
100
9.89k
  if (Subtarget->isGP64bit())
101
3.42k
    Features[Feature_IsGP64bitBit] = 1;
102
9.89k
  if (Subtarget->isABI_N64())
103
2.94k
    Features[Feature_IsPTR64bitBit] = 1;
104
9.89k
  if (Subtarget->hasMips64())
105
2.92k
    Features[Feature_HasMips64Bit] = 1;
106
9.89k
  if (Subtarget->hasMips64r2())
107
1.58k
    Features[Feature_HasMips64r2Bit] = 1;
108
9.89k
  if (Subtarget->hasMips64r6())
109
411
    Features[Feature_HasMips64r6Bit] = 1;
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9.89k
  if (!Subtarget->hasMips64r6())
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9.48k
    Features[Feature_NotMips64r6Bit] = 1;
112
9.89k
  if (Subtarget->inMips16Mode())
113
2.57k
    Features[Feature_InMips16ModeBit] = 1;
114
9.89k
  if (!Subtarget->inMips16Mode())
115
7.31k
    Features[Feature_NotInMips16ModeBit] = 1;
116
9.89k
  if (Subtarget->hasCnMips())
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20
    Features[Feature_HasCnMipsBit] = 1;
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9.89k
  if (!Subtarget->hasCnMips())
119
9.87k
    Features[Feature_NotCnMipsBit] = 1;
120
9.89k
  if (Subtarget->isABI_N64())
121
2.94k
    Features[Feature_IsN64Bit] = 1;
122
9.89k
  if (!TM.isPositionIndependent())
123
5.89k
    Features[Feature_RelocNotPICBit] = 1;
124
9.89k
  if (TM.isPositionIndependent())
125
3.99k
    Features[Feature_RelocPICBit] = 1;
126
9.89k
  if (TM.Options.NoNaNsFPMath)
127
130
    Features[Feature_NoNaNsFPMathBit] = 1;
128
9.89k
  if (Subtarget->hasStandardEncoding())
129
7.31k
    Features[Feature_HasStdEncBit] = 1;
130
9.89k
  if (!Subtarget->hasDSP())
131
9.78k
    Features[Feature_NotDSPBit] = 1;
132
9.89k
  if (Subtarget->inMicroMipsMode())
133
831
    Features[Feature_InMicroMipsBit] = 1;
134
9.89k
  if (!Subtarget->inMicroMipsMode())
135
9.06k
    Features[Feature_NotInMicroMipsBit] = 1;
136
9.89k
  if (Subtarget->isLittle())
137
4.84k
    Features[Feature_IsLEBit] = 1;
138
9.89k
  if (!Subtarget->isLittle())
139
5.04k
    Features[Feature_IsBEBit] = 1;
140
9.89k
  if (!Subtarget->isTargetNaCl())
141
9.85k
    Features[Feature_IsNotNaClBit] = 1;
142
9.89k
  if (Subtarget->hasEVA())
143
10
    Features[Feature_HasEVABit] = 1;
144
9.89k
  if (Subtarget->hasMSA())
145
942
    Features[Feature_HasMSABit] = 1;
146
9.89k
  if (!Subtarget->disableMadd4())
147
9.85k
    Features[Feature_HasMadd4Bit] = 1;
148
9.89k
  if (Subtarget->useIndirectJumpsHazard())
149
123
    Features[Feature_UseIndirectJumpsHazardBit] = 1;
150
9.89k
  if (!Subtarget->useIndirectJumpsHazard())
151
9.76k
    Features[Feature_NoIndirectJumpGuardsBit] = 1;
152
9.89k
  if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast)
153
5
    Features[Feature_AllowFPOpFusionBit] = 1;
154
9.89k
  if (Subtarget->isFP64bit())
155
5.14k
    Features[Feature_IsFP64bitBit] = 1;
156
9.89k
  if (!Subtarget->isFP64bit())
157
4.75k
    Features[Feature_NotFP64bitBit] = 1;
158
9.89k
  if (!Subtarget->useSoftFloat())
159
9.57k
    Features[Feature_IsNotSoftFloatBit] = 1;
160
9.89k
  if (Subtarget->hasDSP())
161
102
    Features[Feature_HasDSPBit] = 1;
162
9.89k
  if (Subtarget->hasDSPR2())
163
26
    Features[Feature_HasDSPR2Bit] = 1;
164
9.89k
  return Features;
165
9.89k
}
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167
PredicateBitset MipsInstructionSelector::
168
13
computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget, const MachineFunction *MF) const {
169
13
  PredicateBitset Features;
170
13
  return Features;
171
13
}
172
173
// LLT Objects.
174
enum {
175
  GILLT_s16,
176
  GILLT_s32,
177
  GILLT_s64,
178
  GILLT_v2s16,
179
  GILLT_v2s64,
180
  GILLT_v4s8,
181
  GILLT_v4s32,
182
  GILLT_v8s16,
183
  GILLT_v16s8,
184
};
185
const static size_t NumTypeObjects = 9;
186
const static LLT TypeObjects[] = {
187
  LLT::scalar(16),
188
  LLT::scalar(32),
189
  LLT::scalar(64),
190
  LLT::vector(2, 16),
191
  LLT::vector(2, 64),
192
  LLT::vector(4, 8),
193
  LLT::vector(4, 32),
194
  LLT::vector(8, 16),
195
  LLT::vector(16, 8),
196
};
197
198
// Feature bitsets.
199
enum {
200
  GIFBS_Invalid,
201
  GIFBS_HasCnMips,
202
  GIFBS_HasDSP,
203
  GIFBS_HasDSPR2,
204
  GIFBS_HasMSA,
205
  GIFBS_InMicroMips,
206
  GIFBS_InMips16Mode,
207
  GIFBS_IsFP64bit,
208
  GIFBS_NotFP64bit,
209
  GIFBS_HasDSP_InMicroMips,
210
  GIFBS_HasDSP_NotInMicroMips,
211
  GIFBS_HasDSPR2_InMicroMips,
212
  GIFBS_HasMSA_HasStdEnc,
213
  GIFBS_HasMSA_IsBE,
214
  GIFBS_HasMSA_IsLE,
215
  GIFBS_HasMips32r6_InMicroMips,
216
  GIFBS_HasMips64r2_HasStdEnc,
217
  GIFBS_HasMips64r6_HasStdEnc,
218
  GIFBS_HasStdEnc_IsNotSoftFloat,
219
  GIFBS_HasStdEnc_NotInMicroMips,
220
  GIFBS_HasStdEnc_NotMips4_32,
221
  GIFBS_InMicroMips_IsFP64bit,
222
  GIFBS_InMicroMips_IsNotSoftFloat,
223
  GIFBS_InMicroMips_NotFP64bit,
224
  GIFBS_InMicroMips_NotMips32r6,
225
  GIFBS_IsGP64bit_NotInMips16Mode,
226
  GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
227
  GIFBS_HasMSA_HasMips64_HasStdEnc,
228
  GIFBS_HasMips3_HasStdEnc_IsGP64bit,
229
  GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
230
  GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips,
231
  GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
232
  GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
233
  GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
234
  GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips,
235
  GIFBS_HasStdEnc_IsFP64bit_NotMips4_32,
236
  GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
237
  GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips,
238
  GIFBS_HasStdEnc_NotFP64bit_NotMips4_32,
239
  GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC,
240
  GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
241
  GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
242
  GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
243
  GIFBS_InMicroMips_NotMips32r6_RelocNotPIC,
244
  GIFBS_InMicroMips_NotMips32r6_RelocPIC,
245
  GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
246
  GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
247
  GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
248
  GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips,
249
  GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
250
  GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
251
  GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
252
  GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
253
  GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotMips32r6_NotMips32r6,
254
  GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
255
  GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
256
  GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
257
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
258
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
259
  GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6_NotMips32r6,
260
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
261
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
262
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
263
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
264
};
265
const static PredicateBitset FeatureBitsets[] {
266
  {}, // GIFBS_Invalid
267
  {Feature_HasCnMipsBit, },
268
  {Feature_HasDSPBit, },
269
  {Feature_HasDSPR2Bit, },
270
  {Feature_HasMSABit, },
271
  {Feature_InMicroMipsBit, },
272
  {Feature_InMips16ModeBit, },
273
  {Feature_IsFP64bitBit, },
274
  {Feature_NotFP64bitBit, },
275
  {Feature_HasDSPBit, Feature_InMicroMipsBit, },
276
  {Feature_HasDSPBit, Feature_NotInMicroMipsBit, },
277
  {Feature_HasDSPR2Bit, Feature_InMicroMipsBit, },
278
  {Feature_HasMSABit, Feature_HasStdEncBit, },
279
  {Feature_HasMSABit, Feature_IsBEBit, },
280
  {Feature_HasMSABit, Feature_IsLEBit, },
281
  {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, },
282
  {Feature_HasMips64r2Bit, Feature_HasStdEncBit, },
283
  {Feature_HasMips64r6Bit, Feature_HasStdEncBit, },
284
  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },
285
  {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
286
  {Feature_HasStdEncBit, Feature_NotMips4_32Bit, },
287
  {Feature_InMicroMipsBit, Feature_IsFP64bitBit, },
288
  {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
289
  {Feature_InMicroMipsBit, Feature_NotFP64bitBit, },
290
  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },
291
  {Feature_IsGP64bitBit, Feature_NotInMips16ModeBit, },
292
  {Feature_AllowFPOpFusionBit, Feature_HasMSABit, Feature_HasStdEncBit, },
293
  {Feature_HasMSABit, Feature_HasMips64Bit, Feature_HasStdEncBit, },
294
  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, },
295
  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
296
  {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
297
  {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
298
  {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
299
  {Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
300
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, },
301
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, },
302
  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
303
  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
304
  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, },
305
  {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_RelocNotPICBit, },
306
  {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },
307
  {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, },
308
  {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, },
309
  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocNotPICBit, },
310
  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocPICBit, },
311
  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
312
  {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
313
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
314
  {Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
315
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
316
  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
317
  {Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
318
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
319
  {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotMips32r6Bit, Feature_NotMips32r6Bit, },
320
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
321
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
322
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
323
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
324
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
325
  {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips32r6Bit, },
326
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
327
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
328
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
329
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
330
};
331
332
// ComplexPattern predicates.
333
enum {
334
  GICP_Invalid,
335
};
336
// See constructor for table contents
337
338
// PatFrag predicates.
339
enum {
340
  GIPFP_I64_Predicate_immLi16 = GIPFP_I64_Invalid + 1,
341
  GIPFP_I64_Predicate_immSExt10,
342
  GIPFP_I64_Predicate_immSExt6,
343
  GIPFP_I64_Predicate_immSExtAddiur2,
344
  GIPFP_I64_Predicate_immSExtAddius5,
345
  GIPFP_I64_Predicate_immZExt1,
346
  GIPFP_I64_Predicate_immZExt10,
347
  GIPFP_I64_Predicate_immZExt1Ptr,
348
  GIPFP_I64_Predicate_immZExt2,
349
  GIPFP_I64_Predicate_immZExt2Lsa,
350
  GIPFP_I64_Predicate_immZExt2Ptr,
351
  GIPFP_I64_Predicate_immZExt2Shift,
352
  GIPFP_I64_Predicate_immZExt3,
353
  GIPFP_I64_Predicate_immZExt3Ptr,
354
  GIPFP_I64_Predicate_immZExt4,
355
  GIPFP_I64_Predicate_immZExt4Ptr,
356
  GIPFP_I64_Predicate_immZExt5,
357
  GIPFP_I64_Predicate_immZExt5_64,
358
  GIPFP_I64_Predicate_immZExt6,
359
  GIPFP_I64_Predicate_immZExt8,
360
  GIPFP_I64_Predicate_immZExtAndi16,
361
  GIPFP_I64_Predicate_immi32Cst15,
362
  GIPFP_I64_Predicate_immi32Cst31,
363
  GIPFP_I64_Predicate_immi32Cst7,
364
};
365
0
bool MipsInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
366
0
  switch (PredicateID) {
367
0
  case GIPFP_I64_Predicate_immLi16: {
368
0
    return Imm >= -1 && Imm <= 126;
369
0
    llvm_unreachable("ImmediateCode should have returned");
370
0
    return false;
371
0
  }
372
0
  case GIPFP_I64_Predicate_immSExt10: {
373
0
    return isInt<10>(Imm);
374
0
    llvm_unreachable("ImmediateCode should have returned");
375
0
    return false;
376
0
  }
377
0
  case GIPFP_I64_Predicate_immSExt6: {
378
0
    return isInt<6>(Imm);
379
0
    llvm_unreachable("ImmediateCode should have returned");
380
0
    return false;
381
0
  }
382
0
  case GIPFP_I64_Predicate_immSExtAddiur2: {
383
0
    return Imm == 1 || Imm == -1 ||
384
0
                                           ((Imm % 4 == 0) &&
385
0
                                            Imm < 28 && Imm > 0);
386
0
    llvm_unreachable("ImmediateCode should have returned");
387
0
    return false;
388
0
  }
389
0
  case GIPFP_I64_Predicate_immSExtAddius5: {
390
0
    return Imm >= -8 && Imm <= 7;
391
0
    llvm_unreachable("ImmediateCode should have returned");
392
0
    return false;
393
0
  }
394
0
  case GIPFP_I64_Predicate_immZExt1: {
395
0
    return isUInt<1>(Imm);
396
0
    llvm_unreachable("ImmediateCode should have returned");
397
0
    return false;
398
0
  }
399
0
  case GIPFP_I64_Predicate_immZExt10: {
400
0
    return isUInt<10>(Imm);
401
0
    llvm_unreachable("ImmediateCode should have returned");
402
0
    return false;
403
0
  }
404
0
  case GIPFP_I64_Predicate_immZExt1Ptr: {
405
0
    return isUInt<1>(Imm);
406
0
    llvm_unreachable("ImmediateCode should have returned");
407
0
    return false;
408
0
  }
409
0
  case GIPFP_I64_Predicate_immZExt2: {
410
0
    return isUInt<2>(Imm);
411
0
    llvm_unreachable("ImmediateCode should have returned");
412
0
    return false;
413
0
  }
414
0
  case GIPFP_I64_Predicate_immZExt2Lsa: {
415
0
    return isUInt<2>(Imm - 1);
416
0
    llvm_unreachable("ImmediateCode should have returned");
417
0
    return false;
418
0
  }
419
0
  case GIPFP_I64_Predicate_immZExt2Ptr: {
420
0
    return isUInt<2>(Imm);
421
0
    llvm_unreachable("ImmediateCode should have returned");
422
0
    return false;
423
0
  }
424
0
  case GIPFP_I64_Predicate_immZExt2Shift: {
425
0
    return Imm >= 1 && Imm <= 8;
426
0
    llvm_unreachable("ImmediateCode should have returned");
427
0
    return false;
428
0
  }
429
0
  case GIPFP_I64_Predicate_immZExt3: {
430
0
    return isUInt<3>(Imm);
431
0
    llvm_unreachable("ImmediateCode should have returned");
432
0
    return false;
433
0
  }
434
0
  case GIPFP_I64_Predicate_immZExt3Ptr: {
435
0
    return isUInt<3>(Imm);
436
0
    llvm_unreachable("ImmediateCode should have returned");
437
0
    return false;
438
0
  }
439
0
  case GIPFP_I64_Predicate_immZExt4: {
440
0
    return isUInt<4>(Imm);
441
0
    llvm_unreachable("ImmediateCode should have returned");
442
0
    return false;
443
0
  }
444
0
  case GIPFP_I64_Predicate_immZExt4Ptr: {
445
0
    return isUInt<4>(Imm);
446
0
    llvm_unreachable("ImmediateCode should have returned");
447
0
    return false;
448
0
  }
449
0
  case GIPFP_I64_Predicate_immZExt5: {
450
0
    return Imm == (Imm & 0x1f);
451
0
    llvm_unreachable("ImmediateCode should have returned");
452
0
    return false;
453
0
  }
454
0
  case GIPFP_I64_Predicate_immZExt5_64: {
455
0
     return Imm == (Imm & 0x1f); 
456
0
    llvm_unreachable("ImmediateCode should have returned");
457
0
    return false;
458
0
  }
459
0
  case GIPFP_I64_Predicate_immZExt6: {
460
0
    return Imm == (Imm & 0x3f);
461
0
    llvm_unreachable("ImmediateCode should have returned");
462
0
    return false;
463
0
  }
464
0
  case GIPFP_I64_Predicate_immZExt8: {
465
0
    return isUInt<8>(Imm);
466
0
    llvm_unreachable("ImmediateCode should have returned");
467
0
    return false;
468
0
  }
469
0
  case GIPFP_I64_Predicate_immZExtAndi16: {
470
0
    return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
471
0
            Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
472
0
            Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
473
0
    llvm_unreachable("ImmediateCode should have returned");
474
0
    return false;
475
0
  }
476
0
  case GIPFP_I64_Predicate_immi32Cst15: {
477
0
    return isUInt<32>(Imm) && Imm == 15;
478
0
    llvm_unreachable("ImmediateCode should have returned");
479
0
    return false;
480
0
  }
481
0
  case GIPFP_I64_Predicate_immi32Cst31: {
482
0
    return isUInt<32>(Imm) && Imm == 31;
483
0
    llvm_unreachable("ImmediateCode should have returned");
484
0
    return false;
485
0
  }
486
0
  case GIPFP_I64_Predicate_immi32Cst7: {
487
0
    return isUInt<32>(Imm) && Imm == 7;
488
0
    llvm_unreachable("ImmediateCode should have returned");
489
0
    return false;
490
0
  }
491
0
  }
492
0
  llvm_unreachable("Unknown predicate");
493
0
  return false;
494
0
}
495
0
bool MipsInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
496
0
  llvm_unreachable("Unknown predicate");
497
0
  return false;
498
0
}
499
0
bool MipsInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
500
0
  llvm_unreachable("Unknown predicate");
501
0
  return false;
502
0
}
503
0
bool MipsInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
504
0
  const MachineFunction &MF = *MI.getParent()->getParent();
505
0
  const MachineRegisterInfo &MRI = MF.getRegInfo();
506
0
  (void)MRI;
507
0
  llvm_unreachable("Unknown predicate");
508
0
  return false;
509
0
}
510
511
MipsInstructionSelector::ComplexMatcherMemFn
512
MipsInstructionSelector::ComplexPredicateFns[] = {
513
  nullptr, // GICP_Invalid
514
};
515
516
// Custom renderers.
517
enum {
518
  GICR_Invalid,
519
};
520
MipsInstructionSelector::CustomRendererFn
521
MipsInstructionSelector::CustomRenderers[] = {
522
  nullptr, // GICP_Invalid
523
};
524
525
13
bool MipsInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
526
13
  MachineFunction &MF = *I.getParent()->getParent();
527
13
  MachineRegisterInfo &MRI = MF.getRegInfo();
528
13
  // FIXME: This should be computed on a per-function basis rather than per-insn.
529
13
  AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
530
13
  const PredicateBitset AvailableFeatures = getAvailableFeatures();
531
13
  NewMIVector OutMIs;
532
13
  State.MIs.clear();
533
13
  State.MIs.push_back(&I);
534
13
535
13
  if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
536
3
    return true;
537
3
  }
538
10
539
10
  return false;
540
10
}
541
542
13
const int64_t *MipsInstructionSelector::getMatchTable() const {
543
13
  constexpr static int64_t MatchTable0[] = {
544
13
    GIM_SwitchOpcode, /*MI*/0, /*[*/34, 124, /*)*//*default:*//*Label 40*/ 37669,
545
13
    /*TargetOpcode::G_ADD*//*Label 0*/ 95,
546
13
    /*TargetOpcode::G_SUB*//*Label 1*/ 1272,
547
13
    /*TargetOpcode::G_MUL*//*Label 2*/ 1884,
548
13
    /*TargetOpcode::G_SDIV*//*Label 3*/ 2260,
549
13
    /*TargetOpcode::G_UDIV*//*Label 4*/ 2481,
550
13
    /*TargetOpcode::G_SREM*//*Label 5*/ 2702,
551
13
    /*TargetOpcode::G_UREM*//*Label 6*/ 2923,
552
13
    /*TargetOpcode::G_AND*//*Label 7*/ 3144,
553
13
    /*TargetOpcode::G_OR*//*Label 8*/ 3588,
554
13
    /*TargetOpcode::G_XOR*//*Label 9*/ 3890, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
555
13
    /*TargetOpcode::G_BITCAST*//*Label 10*/ 4684,
556
13
    /*TargetOpcode::G_LOAD*//*Label 11*/ 8337,
557
13
    /*TargetOpcode::G_SEXTLOAD*//*Label 12*/ 8403,
558
13
    /*TargetOpcode::G_ZEXTLOAD*//*Label 13*/ 8469, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
559
13
    /*TargetOpcode::G_INTRINSIC*//*Label 14*/ 8535,
560
13
    /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 15*/ 25046, 0,
561
13
    /*TargetOpcode::G_TRUNC*//*Label 16*/ 29970,
562
13
    /*TargetOpcode::G_CONSTANT*//*Label 17*/ 30027, 0, 0, 0,
563
13
    /*TargetOpcode::G_SEXT*//*Label 18*/ 30087,
564
13
    /*TargetOpcode::G_ZEXT*//*Label 19*/ 30115,
565
13
    /*TargetOpcode::G_SHL*//*Label 20*/ 30200,
566
13
    /*TargetOpcode::G_LSHR*//*Label 21*/ 30724,
567
13
    /*TargetOpcode::G_ASHR*//*Label 22*/ 31248, 0, 0,
568
13
    /*TargetOpcode::G_SELECT*//*Label 23*/ 31729, 0, 0, 0, 0, 0, 0, 0, 0,
569
13
    /*TargetOpcode::G_FADD*//*Label 24*/ 33183,
570
13
    /*TargetOpcode::G_FSUB*//*Label 25*/ 34062,
571
13
    /*TargetOpcode::G_FMUL*//*Label 26*/ 34638,
572
13
    /*TargetOpcode::G_FMA*//*Label 27*/ 35075,
573
13
    /*TargetOpcode::G_FDIV*//*Label 28*/ 35165, 0, 0, 0,
574
13
    /*TargetOpcode::G_FEXP2*//*Label 29*/ 35416, 0,
575
13
    /*TargetOpcode::G_FLOG2*//*Label 30*/ 35474,
576
13
    /*TargetOpcode::G_FNEG*//*Label 31*/ 35532,
577
13
    /*TargetOpcode::G_FPEXT*//*Label 32*/ 36828,
578
13
    /*TargetOpcode::G_FPTRUNC*//*Label 33*/ 36977,
579
13
    /*TargetOpcode::G_FPTOSI*//*Label 34*/ 37105,
580
13
    /*TargetOpcode::G_FPTOUI*//*Label 35*/ 37163,
581
13
    /*TargetOpcode::G_SITOFP*//*Label 36*/ 37221,
582
13
    /*TargetOpcode::G_UITOFP*//*Label 37*/ 37374, 0, 0, 0,
583
13
    /*TargetOpcode::G_BR*//*Label 38*/ 37432, 0, 0, 0,
584
13
    /*TargetOpcode::G_BSWAP*//*Label 39*/ 37517,
585
13
    // Label 0: @95
586
13
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 49*/ 1271,
587
13
    /*GILLT_s32*//*Label 41*/ 109,
588
13
    /*GILLT_s64*//*Label 42*/ 458,
589
13
    /*GILLT_v2s16*//*Label 43*/ 621,
590
13
    /*GILLT_v2s64*//*Label 44*/ 648,
591
13
    /*GILLT_v4s8*//*Label 45*/ 797,
592
13
    /*GILLT_v4s32*//*Label 46*/ 824,
593
13
    /*GILLT_v8s16*//*Label 47*/ 973,
594
13
    /*GILLT_v16s8*//*Label 48*/ 1122,
595
13
    // Label 41: @109
596
13
    GIM_Try, /*On fail goto*//*Label 50*/ 457,
597
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
598
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
599
13
      GIM_Try, /*On fail goto*//*Label 51*/ 187, // Rule ID 2278 //
600
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
601
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
602
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
603
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
604
13
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
605
13
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
606
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
607
13
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
608
13
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
609
13
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
610
13
        // MIs[2] Operand 1
611
13
        // No operand predicates
612
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
613
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
614
13
        GIM_CheckIsSafeToFold, /*InsnID*/2,
615
13
        // (add:{ *:[i32] } (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR32Opnd:{ *:[i32] }:$rt)  =>  (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
616
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA,
617
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
618
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
619
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
620
13
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
621
13
        GIR_EraseFromParent, /*InsnID*/0,
622
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
623
13
        // GIR_Coverage, 2278,
624
13
        GIR_Done,
625
13
      // Label 51: @187
626
13
      GIM_Try, /*On fail goto*//*Label 52*/ 255, // Rule ID 802 //
627
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
628
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
629
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
630
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
631
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
632
13
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
633
13
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
634
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
635
13
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
636
13
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
637
13
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
638
13
        // MIs[2] Operand 1
639
13
        // No operand predicates
640
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
641
13
        GIM_CheckIsSafeToFold, /*InsnID*/2,
642
13
        // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa))  =>  (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
643
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA,
644
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
645
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
646
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
647
13
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
648
13
        GIR_EraseFromParent, /*InsnID*/0,
649
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
650
13
        // GIR_Coverage, 802,
651
13
        GIR_Done,
652
13
      // Label 52: @255
653
13
      GIM_Try, /*On fail goto*//*Label 53*/ 298, // Rule ID 2054 //
654
13
        GIM_CheckFeatures, GIFBS_InMicroMips,
655
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
656
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
657
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
658
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
659
13
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExtAddiur2,
660
13
        // MIs[1] Operand 1
661
13
        // No operand predicates
662
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
663
13
        // (add:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)  =>  (ADDIUR2_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)
664
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUR2_MM,
665
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
666
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
667
13
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
668
13
        GIR_EraseFromParent, /*InsnID*/0,
669
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
670
13
        // GIR_Coverage, 2054,
671
13
        GIR_Done,
672
13
      // Label 53: @298
673
13
      GIM_Try, /*On fail goto*//*Label 54*/ 341, // Rule ID 2055 //
674
13
        GIM_CheckFeatures, GIFBS_InMicroMips,
675
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
676
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
677
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
678
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
679
13
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExtAddius5,
680
13
        // MIs[1] Operand 1
681
13
        // No operand predicates
682
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
683
13
        // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)  =>  (ADDIUS5_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)
684
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUS5_MM,
685
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
686
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
687
13
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
688
13
        GIR_EraseFromParent, /*InsnID*/0,
689
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
690
13
        // GIR_Coverage, 2055,
691
13
        GIR_Done,
692
13
      // Label 54: @341
693
13
      GIM_Try, /*On fail goto*//*Label 55*/ 364, // Rule ID 1165 //
694
13
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
695
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
696
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
697
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
698
13
        // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (ADDU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
699
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU16_MMR6,
700
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
701
13
        // GIR_Coverage, 1165,
702
13
        GIR_Done,
703
13
      // Label 55: @364
704
13
      GIM_Try, /*On fail goto*//*Label 56*/ 387, // Rule ID 34 //
705
13
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
706
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
707
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
708
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
709
13
        // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
710
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDu,
711
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
712
13
        // GIR_Coverage, 34,
713
13
        GIR_Done,
714
13
      // Label 56: @387
715
13
      GIM_Try, /*On fail goto*//*Label 57*/ 410, // Rule ID 1028 //
716
13
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
717
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
718
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
719
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
720
13
        // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (ADDU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
721
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU16_MM,
722
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
723
13
        // GIR_Coverage, 1028,
724
13
        GIR_Done,
725
13
      // Label 57: @410
726
13
      GIM_Try, /*On fail goto*//*Label 58*/ 433, // Rule ID 1040 //
727
13
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
728
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
729
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
730
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
731
13
        // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
732
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDu_MM,
733
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
734
13
        // GIR_Coverage, 1040,
735
13
        GIR_Done,
736
13
      // Label 58: @433
737
13
      GIM_Try, /*On fail goto*//*Label 59*/ 456, // Rule ID 1723 //
738
13
        GIM_CheckFeatures, GIFBS_InMips16Mode,
739
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
740
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
741
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
742
13
        // (add:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (AdduRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
743
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AdduRxRyRz16,
744
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
745
13
        // GIR_Coverage, 1723,
746
13
        GIR_Done,
747
13
      // Label 59: @456
748
13
      GIM_Reject,
749
13
    // Label 50: @457
750
13
    GIM_Reject,
751
13
    // Label 42: @458
752
13
    GIM_Try, /*On fail goto*//*Label 60*/ 620,
753
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
754
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
755
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
756
13
      GIM_Try, /*On fail goto*//*Label 61*/ 536, // Rule ID 2279 //
757
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc,
758
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
759
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
760
13
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
761
13
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
762
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
763
13
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
764
13
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
765
13
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
766
13
        // MIs[2] Operand 1
767
13
        // No operand predicates
768
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
769
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
770
13
        GIM_CheckIsSafeToFold, /*InsnID*/2,
771
13
        // (add:{ *:[i64] } (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR64Opnd:{ *:[i64] }:$rt)  =>  (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
772
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA,
773
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
774
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
775
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
776
13
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
777
13
        GIR_EraseFromParent, /*InsnID*/0,
778
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
779
13
        // GIR_Coverage, 2279,
780
13
        GIR_Done,
781
13
      // Label 61: @536
782
13
      GIM_Try, /*On fail goto*//*Label 62*/ 600, // Rule ID 803 //
783
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc,
784
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
785
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
786
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
787
13
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
788
13
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
789
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
790
13
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
791
13
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
792
13
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
793
13
        // MIs[2] Operand 1
794
13
        // No operand predicates
795
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
796
13
        GIM_CheckIsSafeToFold, /*InsnID*/2,
797
13
        // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa))  =>  (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
798
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA,
799
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
800
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
801
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
802
13
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
803
13
        GIR_EraseFromParent, /*InsnID*/0,
804
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
805
13
        // GIR_Coverage, 803,
806
13
        GIR_Done,
807
13
      // Label 62: @600
808
13
      GIM_Try, /*On fail goto*//*Label 63*/ 619, // Rule ID 180 //
809
13
        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
810
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
811
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
812
13
        // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
813
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DADDu,
814
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
815
13
        // GIR_Coverage, 180,
816
13
        GIR_Done,
817
13
      // Label 63: @619
818
13
      GIM_Reject,
819
13
    // Label 60: @620
820
13
    GIM_Reject,
821
13
    // Label 43: @621
822
13
    GIM_Try, /*On fail goto*//*Label 64*/ 647, // Rule ID 1822 //
823
13
      GIM_CheckFeatures, GIFBS_HasDSP,
824
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
825
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
826
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
827
13
      // (add:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
828
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDQ_PH,
829
13
      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
830
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
831
13
      // GIR_Coverage, 1822,
832
13
      GIR_Done,
833
13
    // Label 64: @647
834
13
    GIM_Reject,
835
13
    // Label 44: @648
836
13
    GIM_Try, /*On fail goto*//*Label 65*/ 796,
837
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
838
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
839
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
840
13
      GIM_Try, /*On fail goto*//*Label 66*/ 719, // Rule ID 2283 //
841
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
842
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
843
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
844
13
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
845
13
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
846
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
847
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
848
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
849
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
850
13
        // (add:{ *:[v2i64] } (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt), MSA128DOpnd:{ *:[v2i64] }:$wd_in)  =>  (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
851
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D,
852
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
853
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
854
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
855
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
856
13
        GIR_EraseFromParent, /*InsnID*/0,
857
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
858
13
        // GIR_Coverage, 2283,
859
13
        GIR_Done,
860
13
      // Label 66: @719
861
13
      GIM_Try, /*On fail goto*//*Label 67*/ 776, // Rule ID 811 //
862
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
863
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
864
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
865
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
866
13
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
867
13
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
868
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
869
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
870
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
871
13
        // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt))  =>  (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
872
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D,
873
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
874
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
875
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
876
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
877
13
        GIR_EraseFromParent, /*InsnID*/0,
878
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
879
13
        // GIR_Coverage, 811,
880
13
        GIR_Done,
881
13
      // Label 67: @776
882
13
      GIM_Try, /*On fail goto*//*Label 68*/ 795, // Rule ID 478 //
883
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
884
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
885
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
886
13
        // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
887
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_D,
888
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
889
13
        // GIR_Coverage, 478,
890
13
        GIR_Done,
891
13
      // Label 68: @795
892
13
      GIM_Reject,
893
13
    // Label 65: @796
894
13
    GIM_Reject,
895
13
    // Label 45: @797
896
13
    GIM_Try, /*On fail goto*//*Label 69*/ 823, // Rule ID 1828 //
897
13
      GIM_CheckFeatures, GIFBS_HasDSP,
898
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
899
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
900
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
901
13
      // (add:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)  =>  (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
902
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU_QB,
903
13
      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
904
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
905
13
      // GIR_Coverage, 1828,
906
13
      GIR_Done,
907
13
    // Label 69: @823
908
13
    GIM_Reject,
909
13
    // Label 46: @824
910
13
    GIM_Try, /*On fail goto*//*Label 70*/ 972,
911
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
912
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
913
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
914
13
      GIM_Try, /*On fail goto*//*Label 71*/ 895, // Rule ID 2282 //
915
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
916
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
917
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
918
13
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
919
13
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
920
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
921
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
922
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
923
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
924
13
        // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt), MSA128WOpnd:{ *:[v4i32] }:$wd_in)  =>  (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
925
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W,
926
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
927
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
928
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
929
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
930
13
        GIR_EraseFromParent, /*InsnID*/0,
931
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
932
13
        // GIR_Coverage, 2282,
933
13
        GIR_Done,
934
13
      // Label 71: @895
935
13
      GIM_Try, /*On fail goto*//*Label 72*/ 952, // Rule ID 810 //
936
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
937
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
938
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
939
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
940
13
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
941
13
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
942
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
943
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
944
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
945
13
        // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt))  =>  (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
946
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W,
947
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
948
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
949
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
950
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
951
13
        GIR_EraseFromParent, /*InsnID*/0,
952
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
953
13
        // GIR_Coverage, 810,
954
13
        GIR_Done,
955
13
      // Label 72: @952
956
13
      GIM_Try, /*On fail goto*//*Label 73*/ 971, // Rule ID 477 //
957
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
958
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
959
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
960
13
        // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
961
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_W,
962
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
963
13
        // GIR_Coverage, 477,
964
13
        GIR_Done,
965
13
      // Label 73: @971
966
13
      GIM_Reject,
967
13
    // Label 70: @972
968
13
    GIM_Reject,
969
13
    // Label 47: @973
970
13
    GIM_Try, /*On fail goto*//*Label 74*/ 1121,
971
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
972
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
973
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
974
13
      GIM_Try, /*On fail goto*//*Label 75*/ 1044, // Rule ID 2281 //
975
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
976
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
977
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
978
13
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
979
13
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
980
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
981
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
982
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
983
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
984
13
        // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt), MSA128HOpnd:{ *:[v8i16] }:$wd_in)  =>  (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
985
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H,
986
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
987
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
988
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
989
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
990
13
        GIR_EraseFromParent, /*InsnID*/0,
991
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
992
13
        // GIR_Coverage, 2281,
993
13
        GIR_Done,
994
13
      // Label 75: @1044
995
13
      GIM_Try, /*On fail goto*//*Label 76*/ 1101, // Rule ID 809 //
996
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
997
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
998
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
999
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1000
13
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1001
13
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1002
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1003
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1004
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1005
13
        // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt))  =>  (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1006
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H,
1007
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1008
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1009
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1010
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1011
13
        GIR_EraseFromParent, /*InsnID*/0,
1012
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1013
13
        // GIR_Coverage, 809,
1014
13
        GIR_Done,
1015
13
      // Label 76: @1101
1016
13
      GIM_Try, /*On fail goto*//*Label 77*/ 1120, // Rule ID 476 //
1017
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1018
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1019
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1020
13
        // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1021
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_H,
1022
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1023
13
        // GIR_Coverage, 476,
1024
13
        GIR_Done,
1025
13
      // Label 77: @1120
1026
13
      GIM_Reject,
1027
13
    // Label 74: @1121
1028
13
    GIM_Reject,
1029
13
    // Label 48: @1122
1030
13
    GIM_Try, /*On fail goto*//*Label 78*/ 1270,
1031
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1032
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1033
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1034
13
      GIM_Try, /*On fail goto*//*Label 79*/ 1193, // Rule ID 2280 //
1035
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1036
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1037
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1038
13
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1039
13
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1040
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1041
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1042
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1043
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1044
13
        // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt), MSA128BOpnd:{ *:[v16i8] }:$wd_in)  =>  (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1045
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B,
1046
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1047
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
1048
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1049
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1050
13
        GIR_EraseFromParent, /*InsnID*/0,
1051
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1052
13
        // GIR_Coverage, 2280,
1053
13
        GIR_Done,
1054
13
      // Label 79: @1193
1055
13
      GIM_Try, /*On fail goto*//*Label 80*/ 1250, // Rule ID 808 //
1056
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1057
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1058
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1059
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1060
13
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1061
13
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1062
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1063
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1064
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1065
13
        // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt))  =>  (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1066
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B,
1067
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1068
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1069
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1070
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1071
13
        GIR_EraseFromParent, /*InsnID*/0,
1072
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1073
13
        // GIR_Coverage, 808,
1074
13
        GIR_Done,
1075
13
      // Label 80: @1250
1076
13
      GIM_Try, /*On fail goto*//*Label 81*/ 1269, // Rule ID 475 //
1077
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1078
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1079
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1080
13
        // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1081
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_B,
1082
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1083
13
        // GIR_Coverage, 475,
1084
13
        GIR_Done,
1085
13
      // Label 81: @1269
1086
13
      GIM_Reject,
1087
13
    // Label 78: @1270
1088
13
    GIM_Reject,
1089
13
    // Label 49: @1271
1090
13
    GIM_Reject,
1091
13
    // Label 1: @1272
1092
13
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 90*/ 1883,
1093
13
    /*GILLT_s32*//*Label 82*/ 1286,
1094
13
    /*GILLT_s64*//*Label 83*/ 1445,
1095
13
    /*GILLT_v2s16*//*Label 84*/ 1477,
1096
13
    /*GILLT_v2s64*//*Label 85*/ 1504,
1097
13
    /*GILLT_v4s8*//*Label 86*/ 1592,
1098
13
    /*GILLT_v4s32*//*Label 87*/ 1619,
1099
13
    /*GILLT_v8s16*//*Label 88*/ 1707,
1100
13
    /*GILLT_v16s8*//*Label 89*/ 1795,
1101
13
    // Label 82: @1286
1102
13
    GIM_Try, /*On fail goto*//*Label 91*/ 1444,
1103
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1104
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1105
13
      GIM_Try, /*On fail goto*//*Label 92*/ 1328, // Rule ID 1722 //
1106
13
        GIM_CheckFeatures, GIFBS_InMips16Mode,
1107
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
1108
13
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
1109
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
1110
13
        // (sub:{ *:[i32] } 0:{ *:[i32] }, CPU16Regs:{ *:[i32] }:$r)  =>  (NegRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
1111
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NegRxRy16,
1112
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
1113
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // r
1114
13
        GIR_EraseFromParent, /*InsnID*/0,
1115
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1116
13
        // GIR_Coverage, 1722,
1117
13
        GIR_Done,
1118
13
      // Label 92: @1328
1119
13
      GIM_Try, /*On fail goto*//*Label 93*/ 1351, // Rule ID 1167 //
1120
13
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1121
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
1122
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
1123
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
1124
13
        // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (SUBU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1125
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU16_MMR6,
1126
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1127
13
        // GIR_Coverage, 1167,
1128
13
        GIR_Done,
1129
13
      // Label 93: @1351
1130
13
      GIM_Try, /*On fail goto*//*Label 94*/ 1374, // Rule ID 35 //
1131
13
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
1132
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1133
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1134
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1135
13
        // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1136
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBu,
1137
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1138
13
        // GIR_Coverage, 35,
1139
13
        GIR_Done,
1140
13
      // Label 94: @1374
1141
13
      GIM_Try, /*On fail goto*//*Label 95*/ 1397, // Rule ID 1032 //
1142
13
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
1143
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
1144
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
1145
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
1146
13
        // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (SUBU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1147
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU16_MM,
1148
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1149
13
        // GIR_Coverage, 1032,
1150
13
        GIR_Done,
1151
13
      // Label 95: @1397
1152
13
      GIM_Try, /*On fail goto*//*Label 96*/ 1420, // Rule ID 1041 //
1153
13
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
1154
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1155
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1156
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1157
13
        // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1158
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBu_MM,
1159
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1160
13
        // GIR_Coverage, 1041,
1161
13
        GIR_Done,
1162
13
      // Label 96: @1420
1163
13
      GIM_Try, /*On fail goto*//*Label 97*/ 1443, // Rule ID 1727 //
1164
13
        GIM_CheckFeatures, GIFBS_InMips16Mode,
1165
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
1166
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
1167
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
1168
13
        // (sub:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (SubuRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1169
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SubuRxRyRz16,
1170
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1171
13
        // GIR_Coverage, 1727,
1172
13
        GIR_Done,
1173
13
      // Label 97: @1443
1174
13
      GIM_Reject,
1175
13
    // Label 91: @1444
1176
13
    GIM_Reject,
1177
13
    // Label 83: @1445
1178
13
    GIM_Try, /*On fail goto*//*Label 98*/ 1476, // Rule ID 181 //
1179
13
      GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
1180
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1181
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1182
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1183
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1184
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1185
13
      // (sub:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DSUBu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1186
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSUBu,
1187
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1188
13
      // GIR_Coverage, 181,
1189
13
      GIR_Done,
1190
13
    // Label 98: @1476
1191
13
    GIM_Reject,
1192
13
    // Label 84: @1477
1193
13
    GIM_Try, /*On fail goto*//*Label 99*/ 1503, // Rule ID 1824 //
1194
13
      GIM_CheckFeatures, GIFBS_HasDSP,
1195
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1196
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
1197
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
1198
13
      // (sub:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1199
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBQ_PH,
1200
13
      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
1201
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1202
13
      // GIR_Coverage, 1824,
1203
13
      GIR_Done,
1204
13
    // Label 99: @1503
1205
13
    GIM_Reject,
1206
13
    // Label 85: @1504
1207
13
    GIM_Try, /*On fail goto*//*Label 100*/ 1591,
1208
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1209
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1210
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1211
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1212
13
      GIM_Try, /*On fail goto*//*Label 101*/ 1575, // Rule ID 867 //
1213
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1214
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1215
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1216
13
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
1217
13
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
1218
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1219
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1220
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1221
13
        // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt))  =>  (MSUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1222
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_D,
1223
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1224
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1225
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1226
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1227
13
        GIR_EraseFromParent, /*InsnID*/0,
1228
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1229
13
        // GIR_Coverage, 867,
1230
13
        GIR_Done,
1231
13
      // Label 101: @1575
1232
13
      GIM_Try, /*On fail goto*//*Label 102*/ 1590, // Rule ID 996 //
1233
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1234
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1235
13
        // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1236
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_D,
1237
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1238
13
        // GIR_Coverage, 996,
1239
13
        GIR_Done,
1240
13
      // Label 102: @1590
1241
13
      GIM_Reject,
1242
13
    // Label 100: @1591
1243
13
    GIM_Reject,
1244
13
    // Label 86: @1592
1245
13
    GIM_Try, /*On fail goto*//*Label 103*/ 1618, // Rule ID 1830 //
1246
13
      GIM_CheckFeatures, GIFBS_HasDSP,
1247
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
1248
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
1249
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
1250
13
      // (sub:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)  =>  (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
1251
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU_QB,
1252
13
      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
1253
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1254
13
      // GIR_Coverage, 1830,
1255
13
      GIR_Done,
1256
13
    // Label 103: @1618
1257
13
    GIM_Reject,
1258
13
    // Label 87: @1619
1259
13
    GIM_Try, /*On fail goto*//*Label 104*/ 1706,
1260
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1261
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1262
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1263
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1264
13
      GIM_Try, /*On fail goto*//*Label 105*/ 1690, // Rule ID 866 //
1265
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1266
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1267
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1268
13
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1269
13
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1270
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1271
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1272
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1273
13
        // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt))  =>  (MSUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1274
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_W,
1275
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1276
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1277
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1278
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1279
13
        GIR_EraseFromParent, /*InsnID*/0,
1280
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1281
13
        // GIR_Coverage, 866,
1282
13
        GIR_Done,
1283
13
      // Label 105: @1690
1284
13
      GIM_Try, /*On fail goto*//*Label 106*/ 1705, // Rule ID 995 //
1285
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1286
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1287
13
        // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1288
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_W,
1289
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1290
13
        // GIR_Coverage, 995,
1291
13
        GIR_Done,
1292
13
      // Label 106: @1705
1293
13
      GIM_Reject,
1294
13
    // Label 104: @1706
1295
13
    GIM_Reject,
1296
13
    // Label 88: @1707
1297
13
    GIM_Try, /*On fail goto*//*Label 107*/ 1794,
1298
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1299
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1300
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1301
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1302
13
      GIM_Try, /*On fail goto*//*Label 108*/ 1778, // Rule ID 865 //
1303
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1304
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1305
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1306
13
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1307
13
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1308
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1309
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1310
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1311
13
        // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt))  =>  (MSUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1312
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_H,
1313
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1314
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1315
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1316
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1317
13
        GIR_EraseFromParent, /*InsnID*/0,
1318
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1319
13
        // GIR_Coverage, 865,
1320
13
        GIR_Done,
1321
13
      // Label 108: @1778
1322
13
      GIM_Try, /*On fail goto*//*Label 109*/ 1793, // Rule ID 994 //
1323
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1324
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1325
13
        // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1326
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_H,
1327
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1328
13
        // GIR_Coverage, 994,
1329
13
        GIR_Done,
1330
13
      // Label 109: @1793
1331
13
      GIM_Reject,
1332
13
    // Label 107: @1794
1333
13
    GIM_Reject,
1334
13
    // Label 89: @1795
1335
13
    GIM_Try, /*On fail goto*//*Label 110*/ 1882,
1336
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1337
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1338
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1339
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1340
13
      GIM_Try, /*On fail goto*//*Label 111*/ 1866, // Rule ID 864 //
1341
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1342
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1343
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1344
13
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1345
13
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1346
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1347
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1348
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1349
13
        // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt))  =>  (MSUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1350
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_B,
1351
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1352
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1353
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1354
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1355
13
        GIR_EraseFromParent, /*InsnID*/0,
1356
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1357
13
        // GIR_Coverage, 864,
1358
13
        GIR_Done,
1359
13
      // Label 111: @1866
1360
13
      GIM_Try, /*On fail goto*//*Label 112*/ 1881, // Rule ID 993 //
1361
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1362
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1363
13
        // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1364
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_B,
1365
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1366
13
        // GIR_Coverage, 993,
1367
13
        GIR_Done,
1368
13
      // Label 112: @1881
1369
13
      GIM_Reject,
1370
13
    // Label 110: @1882
1371
13
    GIM_Reject,
1372
13
    // Label 90: @1883
1373
13
    GIM_Reject,
1374
13
    // Label 2: @1884
1375
13
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 120*/ 2259,
1376
13
    /*GILLT_s32*//*Label 113*/ 1898,
1377
13
    /*GILLT_s64*//*Label 114*/ 2043,
1378
13
    /*GILLT_v2s16*//*Label 115*/ 2104,
1379
13
    /*GILLT_v2s64*//*Label 116*/ 2131, 0,
1380
13
    /*GILLT_v4s32*//*Label 117*/ 2163,
1381
13
    /*GILLT_v8s16*//*Label 118*/ 2195,
1382
13
    /*GILLT_v16s8*//*Label 119*/ 2227,
1383
13
    // Label 113: @1898
1384
13
    GIM_Try, /*On fail goto*//*Label 121*/ 2042,
1385
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1386
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1387
13
      GIM_Try, /*On fail goto*//*Label 122*/ 1937, // Rule ID 36 //
1388
13
        GIM_CheckFeatures, GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
1389
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1390
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1391
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1392
13
        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1393
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL,
1394
13
        GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1395
13
        GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1396
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1397
13
        // GIR_Coverage, 36,
1398
13
        GIR_Done,
1399
13
      // Label 122: @1937
1400
13
      GIM_Try, /*On fail goto*//*Label 123*/ 1960, // Rule ID 304 //
1401
13
        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1402
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1403
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1404
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1405
13
        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1406
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_R6,
1407
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1408
13
        // GIR_Coverage, 304,
1409
13
        GIR_Done,
1410
13
      // Label 123: @1960
1411
13
      GIM_Try, /*On fail goto*//*Label 124*/ 1989, // Rule ID 1042 //
1412
13
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
1413
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1414
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1415
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1416
13
        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL_MM:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1417
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_MM,
1418
13
        GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1419
13
        GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1420
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1421
13
        // GIR_Coverage, 1042,
1422
13
        GIR_Done,
1423
13
      // Label 124: @1989
1424
13
      GIM_Try, /*On fail goto*//*Label 125*/ 2012, // Rule ID 1136 //
1425
13
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1426
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1427
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1428
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1429
13
        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1430
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_MMR6,
1431
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1432
13
        // GIR_Coverage, 1136,
1433
13
        GIR_Done,
1434
13
      // Label 125: @2012
1435
13
      GIM_Try, /*On fail goto*//*Label 126*/ 2041, // Rule ID 1725 //
1436
13
        GIM_CheckFeatures, GIFBS_InMips16Mode,
1437
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
1438
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
1439
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
1440
13
        // (mul:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (MultRxRyRz16:{ *:[i32] }:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1441
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MultRxRyRz16,
1442
13
        GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1443
13
        GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1444
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1445
13
        // GIR_Coverage, 1725,
1446
13
        GIR_Done,
1447
13
      // Label 126: @2041
1448
13
      GIM_Reject,
1449
13
    // Label 121: @2042
1450
13
    GIM_Reject,
1451
13
    // Label 114: @2043
1452
13
    GIM_Try, /*On fail goto*//*Label 127*/ 2103,
1453
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1454
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1455
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1456
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1457
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1458
13
      GIM_Try, /*On fail goto*//*Label 128*/ 2091, // Rule ID 246 //
1459
13
        GIM_CheckFeatures, GIFBS_HasCnMips,
1460
13
        // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMUL:{ *:[i64] }:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1461
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUL,
1462
13
        GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1463
13
        GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1464
13
        GIR_AddImplicitDef, /*InsnID*/0, Mips::P0,
1465
13
        GIR_AddImplicitDef, /*InsnID*/0, Mips::P1,
1466
13
        GIR_AddImplicitDef, /*InsnID*/0, Mips::P2,
1467
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1468
13
        // GIR_Coverage, 246,
1469
13
        GIR_Done,
1470
13
      // Label 128: @2091
1471
13
      GIM_Try, /*On fail goto*//*Label 129*/ 2102, // Rule ID 319 //
1472
13
        GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1473
13
        // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMUL_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1474
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUL_R6,
1475
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1476
13
        // GIR_Coverage, 319,
1477
13
        GIR_Done,
1478
13
      // Label 129: @2102
1479
13
      GIM_Reject,
1480
13
    // Label 127: @2103
1481
13
    GIM_Reject,
1482
13
    // Label 115: @2104
1483
13
    GIM_Try, /*On fail goto*//*Label 130*/ 2130, // Rule ID 1826 //
1484
13
      GIM_CheckFeatures, GIFBS_HasDSPR2,
1485
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1486
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
1487
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
1488
13
      // (mul:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1489
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_PH,
1490
13
      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag21,
1491
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1492
13
      // GIR_Coverage, 1826,
1493
13
      GIR_Done,
1494
13
    // Label 130: @2130
1495
13
    GIM_Reject,
1496
13
    // Label 116: @2131
1497
13
    GIM_Try, /*On fail goto*//*Label 131*/ 2162, // Rule ID 875 //
1498
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1499
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1500
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1501
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1502
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1503
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1504
13
      // (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MULV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1505
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_D,
1506
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1507
13
      // GIR_Coverage, 875,
1508
13
      GIR_Done,
1509
13
    // Label 131: @2162
1510
13
    GIM_Reject,
1511
13
    // Label 117: @2163
1512
13
    GIM_Try, /*On fail goto*//*Label 132*/ 2194, // Rule ID 874 //
1513
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1514
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1515
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1516
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1517
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1518
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1519
13
      // (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MULV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1520
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_W,
1521
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1522
13
      // GIR_Coverage, 874,
1523
13
      GIR_Done,
1524
13
    // Label 132: @2194
1525
13
    GIM_Reject,
1526
13
    // Label 118: @2195
1527
13
    GIM_Try, /*On fail goto*//*Label 133*/ 2226, // Rule ID 873 //
1528
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1529
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1530
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1531
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1532
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1533
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1534
13
      // (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MULV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1535
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_H,
1536
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1537
13
      // GIR_Coverage, 873,
1538
13
      GIR_Done,
1539
13
    // Label 133: @2226
1540
13
    GIM_Reject,
1541
13
    // Label 119: @2227
1542
13
    GIM_Try, /*On fail goto*//*Label 134*/ 2258, // Rule ID 872 //
1543
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1544
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1545
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1546
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1547
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1548
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1549
13
      // (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MULV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1550
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_B,
1551
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1552
13
      // GIR_Coverage, 872,
1553
13
      GIR_Done,
1554
13
    // Label 134: @2258
1555
13
    GIM_Reject,
1556
13
    // Label 120: @2259
1557
13
    GIM_Reject,
1558
13
    // Label 3: @2260
1559
13
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 141*/ 2480,
1560
13
    /*GILLT_s32*//*Label 135*/ 2274,
1561
13
    /*GILLT_s64*//*Label 136*/ 2320, 0,
1562
13
    /*GILLT_v2s64*//*Label 137*/ 2352, 0,
1563
13
    /*GILLT_v4s32*//*Label 138*/ 2384,
1564
13
    /*GILLT_v8s16*//*Label 139*/ 2416,
1565
13
    /*GILLT_v16s8*//*Label 140*/ 2448,
1566
13
    // Label 135: @2274
1567
13
    GIM_Try, /*On fail goto*//*Label 142*/ 2319,
1568
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1569
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1570
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1571
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1572
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1573
13
      GIM_Try, /*On fail goto*//*Label 143*/ 2307, // Rule ID 298 //
1574
13
        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1575
13
        // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1576
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV,
1577
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1578
13
        // GIR_Coverage, 298,
1579
13
        GIR_Done,
1580
13
      // Label 143: @2307
1581
13
      GIM_Try, /*On fail goto*//*Label 144*/ 2318, // Rule ID 1129 //
1582
13
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1583
13
        // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIV_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1584
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_MMR6,
1585
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1586
13
        // GIR_Coverage, 1129,
1587
13
        GIR_Done,
1588
13
      // Label 144: @2318
1589
13
      GIM_Reject,
1590
13
    // Label 142: @2319
1591
13
    GIM_Reject,
1592
13
    // Label 136: @2320
1593
13
    GIM_Try, /*On fail goto*//*Label 145*/ 2351, // Rule ID 313 //
1594
13
      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1595
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1596
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1597
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1598
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1599
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1600
13
      // (sdiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DDIV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1601
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DDIV,
1602
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1603
13
      // GIR_Coverage, 313,
1604
13
      GIR_Done,
1605
13
    // Label 145: @2351
1606
13
    GIM_Reject,
1607
13
    // Label 137: @2352
1608
13
    GIM_Try, /*On fail goto*//*Label 146*/ 2383, // Rule ID 615 //
1609
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1610
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1611
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1612
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1613
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1614
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1615
13
      // (sdiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (DIV_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1616
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_D,
1617
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1618
13
      // GIR_Coverage, 615,
1619
13
      GIR_Done,
1620
13
    // Label 146: @2383
1621
13
    GIM_Reject,
1622
13
    // Label 138: @2384
1623
13
    GIM_Try, /*On fail goto*//*Label 147*/ 2415, // Rule ID 614 //
1624
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1625
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1626
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1627
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1628
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1629
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1630
13
      // (sdiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DIV_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1631
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_W,
1632
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1633
13
      // GIR_Coverage, 614,
1634
13
      GIR_Done,
1635
13
    // Label 147: @2415
1636
13
    GIM_Reject,
1637
13
    // Label 139: @2416
1638
13
    GIM_Try, /*On fail goto*//*Label 148*/ 2447, // Rule ID 613 //
1639
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1640
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1641
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1642
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1643
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1644
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1645
13
      // (sdiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DIV_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1646
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_H,
1647
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1648
13
      // GIR_Coverage, 613,
1649
13
      GIR_Done,
1650
13
    // Label 148: @2447
1651
13
    GIM_Reject,
1652
13
    // Label 140: @2448
1653
13
    GIM_Try, /*On fail goto*//*Label 149*/ 2479, // Rule ID 612 //
1654
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1655
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1656
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1657
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1658
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1659
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1660
13
      // (sdiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DIV_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1661
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_B,
1662
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1663
13
      // GIR_Coverage, 612,
1664
13
      GIR_Done,
1665
13
    // Label 149: @2479
1666
13
    GIM_Reject,
1667
13
    // Label 141: @2480
1668
13
    GIM_Reject,
1669
13
    // Label 4: @2481
1670
13
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 156*/ 2701,
1671
13
    /*GILLT_s32*//*Label 150*/ 2495,
1672
13
    /*GILLT_s64*//*Label 151*/ 2541, 0,
1673
13
    /*GILLT_v2s64*//*Label 152*/ 2573, 0,
1674
13
    /*GILLT_v4s32*//*Label 153*/ 2605,
1675
13
    /*GILLT_v8s16*//*Label 154*/ 2637,
1676
13
    /*GILLT_v16s8*//*Label 155*/ 2669,
1677
13
    // Label 150: @2495
1678
13
    GIM_Try, /*On fail goto*//*Label 157*/ 2540,
1679
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1680
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1681
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1682
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1683
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1684
13
      GIM_Try, /*On fail goto*//*Label 158*/ 2528, // Rule ID 299 //
1685
13
        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1686
13
        // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIVU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1687
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIVU,
1688
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1689
13
        // GIR_Coverage, 299,
1690
13
        GIR_Done,
1691
13
      // Label 158: @2528
1692
13
      GIM_Try, /*On fail goto*//*Label 159*/ 2539, // Rule ID 1130 //
1693
13
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1694
13
        // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIVU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1695
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIVU_MMR6,
1696
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1697
13
        // GIR_Coverage, 1130,
1698
13
        GIR_Done,
1699
13
      // Label 159: @2539
1700
13
      GIM_Reject,
1701
13
    // Label 157: @2540
1702
13
    GIM_Reject,
1703
13
    // Label 151: @2541
1704
13
    GIM_Try, /*On fail goto*//*Label 160*/ 2572, // Rule ID 314 //
1705
13
      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1706
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1707
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1708
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1709
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1710
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1711
13
      // (udiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DDIVU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1712
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DDIVU,
1713
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1714
13
      // GIR_Coverage, 314,
1715
13
      GIR_Done,
1716
13
    // Label 160: @2572
1717
13
    GIM_Reject,
1718
13
    // Label 152: @2573
1719
13
    GIM_Try, /*On fail goto*//*Label 161*/ 2604, // Rule ID 619 //
1720
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1721
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1722
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1723
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1724
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1725
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1726
13
      // (udiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (DIV_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1727
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_D,
1728
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1729
13
      // GIR_Coverage, 619,
1730
13
      GIR_Done,
1731
13
    // Label 161: @2604
1732
13
    GIM_Reject,
1733
13
    // Label 153: @2605
1734
13
    GIM_Try, /*On fail goto*//*Label 162*/ 2636, // Rule ID 618 //
1735
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1736
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1737
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1738
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1739
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1740
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1741
13
      // (udiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DIV_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1742
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_W,
1743
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1744
13
      // GIR_Coverage, 618,
1745
13
      GIR_Done,
1746
13
    // Label 162: @2636
1747
13
    GIM_Reject,
1748
13
    // Label 154: @2637
1749
13
    GIM_Try, /*On fail goto*//*Label 163*/ 2668, // Rule ID 617 //
1750
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1751
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1752
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1753
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1754
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1755
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1756
13
      // (udiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DIV_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1757
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_H,
1758
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1759
13
      // GIR_Coverage, 617,
1760
13
      GIR_Done,
1761
13
    // Label 163: @2668
1762
13
    GIM_Reject,
1763
13
    // Label 155: @2669
1764
13
    GIM_Try, /*On fail goto*//*Label 164*/ 2700, // Rule ID 616 //
1765
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1766
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1767
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1768
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1769
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1770
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1771
13
      // (udiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DIV_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1772
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_B,
1773
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1774
13
      // GIR_Coverage, 616,
1775
13
      GIR_Done,
1776
13
    // Label 164: @2700
1777
13
    GIM_Reject,
1778
13
    // Label 156: @2701
1779
13
    GIM_Reject,
1780
13
    // Label 5: @2702
1781
13
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 171*/ 2922,
1782
13
    /*GILLT_s32*//*Label 165*/ 2716,
1783
13
    /*GILLT_s64*//*Label 166*/ 2762, 0,
1784
13
    /*GILLT_v2s64*//*Label 167*/ 2794, 0,
1785
13
    /*GILLT_v4s32*//*Label 168*/ 2826,
1786
13
    /*GILLT_v8s16*//*Label 169*/ 2858,
1787
13
    /*GILLT_v16s8*//*Label 170*/ 2890,
1788
13
    // Label 165: @2716
1789
13
    GIM_Try, /*On fail goto*//*Label 172*/ 2761,
1790
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1791
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1792
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1793
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1794
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1795
13
      GIM_Try, /*On fail goto*//*Label 173*/ 2749, // Rule ID 300 //
1796
13
        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1797
13
        // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MOD:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1798
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD,
1799
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1800
13
        // GIR_Coverage, 300,
1801
13
        GIR_Done,
1802
13
      // Label 173: @2749
1803
13
      GIM_Try, /*On fail goto*//*Label 174*/ 2760, // Rule ID 1134 //
1804
13
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1805
13
        // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MOD_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1806
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_MMR6,
1807
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1808
13
        // GIR_Coverage, 1134,
1809
13
        GIR_Done,
1810
13
      // Label 174: @2760
1811
13
      GIM_Reject,
1812
13
    // Label 172: @2761
1813
13
    GIM_Reject,
1814
13
    // Label 166: @2762
1815
13
    GIM_Try, /*On fail goto*//*Label 175*/ 2793, // Rule ID 315 //
1816
13
      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1817
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1818
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1819
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1820
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1821
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1822
13
      // (srem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMOD:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1823
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMOD,
1824
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1825
13
      // GIR_Coverage, 315,
1826
13
      GIR_Done,
1827
13
    // Label 175: @2793
1828
13
    GIM_Reject,
1829
13
    // Label 167: @2794
1830
13
    GIM_Try, /*On fail goto*//*Label 176*/ 2825, // Rule ID 855 //
1831
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1832
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1833
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1834
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1835
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1836
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1837
13
      // (srem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MOD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1838
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_D,
1839
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1840
13
      // GIR_Coverage, 855,
1841
13
      GIR_Done,
1842
13
    // Label 176: @2825
1843
13
    GIM_Reject,
1844
13
    // Label 168: @2826
1845
13
    GIM_Try, /*On fail goto*//*Label 177*/ 2857, // Rule ID 854 //
1846
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1847
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1848
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1849
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1850
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1851
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1852
13
      // (srem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MOD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1853
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_W,
1854
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1855
13
      // GIR_Coverage, 854,
1856
13
      GIR_Done,
1857
13
    // Label 177: @2857
1858
13
    GIM_Reject,
1859
13
    // Label 169: @2858
1860
13
    GIM_Try, /*On fail goto*//*Label 178*/ 2889, // Rule ID 853 //
1861
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1862
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1863
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1864
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1865
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1866
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1867
13
      // (srem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MOD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1868
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_H,
1869
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1870
13
      // GIR_Coverage, 853,
1871
13
      GIR_Done,
1872
13
    // Label 178: @2889
1873
13
    GIM_Reject,
1874
13
    // Label 170: @2890
1875
13
    GIM_Try, /*On fail goto*//*Label 179*/ 2921, // Rule ID 852 //
1876
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1877
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1878
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1879
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1880
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1881
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1882
13
      // (srem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MOD_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1883
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_B,
1884
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1885
13
      // GIR_Coverage, 852,
1886
13
      GIR_Done,
1887
13
    // Label 179: @2921
1888
13
    GIM_Reject,
1889
13
    // Label 171: @2922
1890
13
    GIM_Reject,
1891
13
    // Label 6: @2923
1892
13
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 186*/ 3143,
1893
13
    /*GILLT_s32*//*Label 180*/ 2937,
1894
13
    /*GILLT_s64*//*Label 181*/ 2983, 0,
1895
13
    /*GILLT_v2s64*//*Label 182*/ 3015, 0,
1896
13
    /*GILLT_v4s32*//*Label 183*/ 3047,
1897
13
    /*GILLT_v8s16*//*Label 184*/ 3079,
1898
13
    /*GILLT_v16s8*//*Label 185*/ 3111,
1899
13
    // Label 180: @2937
1900
13
    GIM_Try, /*On fail goto*//*Label 187*/ 2982,
1901
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1902
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1903
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1904
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1905
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1906
13
      GIM_Try, /*On fail goto*//*Label 188*/ 2970, // Rule ID 301 //
1907
13
        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1908
13
        // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MODU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1909
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MODU,
1910
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1911
13
        // GIR_Coverage, 301,
1912
13
        GIR_Done,
1913
13
      // Label 188: @2970
1914
13
      GIM_Try, /*On fail goto*//*Label 189*/ 2981, // Rule ID 1135 //
1915
13
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1916
13
        // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MODU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1917
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MODU_MMR6,
1918
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1919
13
        // GIR_Coverage, 1135,
1920
13
        GIR_Done,
1921
13
      // Label 189: @2981
1922
13
      GIM_Reject,
1923
13
    // Label 187: @2982
1924
13
    GIM_Reject,
1925
13
    // Label 181: @2983
1926
13
    GIM_Try, /*On fail goto*//*Label 190*/ 3014, // Rule ID 316 //
1927
13
      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1928
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1929
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1930
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1931
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1932
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1933
13
      // (urem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMODU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1934
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMODU,
1935
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1936
13
      // GIR_Coverage, 316,
1937
13
      GIR_Done,
1938
13
    // Label 190: @3014
1939
13
    GIM_Reject,
1940
13
    // Label 182: @3015
1941
13
    GIM_Try, /*On fail goto*//*Label 191*/ 3046, // Rule ID 859 //
1942
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1943
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1944
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1945
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1946
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1947
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1948
13
      // (urem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MOD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1949
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_D,
1950
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1951
13
      // GIR_Coverage, 859,
1952
13
      GIR_Done,
1953
13
    // Label 191: @3046
1954
13
    GIM_Reject,
1955
13
    // Label 183: @3047
1956
13
    GIM_Try, /*On fail goto*//*Label 192*/ 3078, // Rule ID 858 //
1957
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1958
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1959
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1960
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1961
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1962
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1963
13
      // (urem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MOD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1964
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_W,
1965
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1966
13
      // GIR_Coverage, 858,
1967
13
      GIR_Done,
1968
13
    // Label 192: @3078
1969
13
    GIM_Reject,
1970
13
    // Label 184: @3079
1971
13
    GIM_Try, /*On fail goto*//*Label 193*/ 3110, // Rule ID 857 //
1972
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1973
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1974
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1975
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1976
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1977
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1978
13
      // (urem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MOD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1979
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_H,
1980
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1981
13
      // GIR_Coverage, 857,
1982
13
      GIR_Done,
1983
13
    // Label 193: @3110
1984
13
    GIM_Reject,
1985
13
    // Label 185: @3111
1986
13
    GIM_Try, /*On fail goto*//*Label 194*/ 3142, // Rule ID 856 //
1987
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1988
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1989
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1990
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1991
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1992
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1993
13
      // (urem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MOD_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1994
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_B,
1995
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1996
13
      // GIR_Coverage, 856,
1997
13
      GIR_Done,
1998
13
    // Label 194: @3142
1999
13
    GIM_Reject,
2000
13
    // Label 186: @3143
2001
13
    GIM_Reject,
2002
13
    // Label 7: @3144
2003
13
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 201*/ 3587,
2004
13
    /*GILLT_s32*//*Label 195*/ 3158,
2005
13
    /*GILLT_s64*//*Label 196*/ 3371, 0,
2006
13
    /*GILLT_v2s64*//*Label 197*/ 3459, 0,
2007
13
    /*GILLT_v4s32*//*Label 198*/ 3491,
2008
13
    /*GILLT_v8s16*//*Label 199*/ 3523,
2009
13
    /*GILLT_v16s8*//*Label 200*/ 3555,
2010
13
    // Label 195: @3158
2011
13
    GIM_Try, /*On fail goto*//*Label 202*/ 3370,
2012
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2013
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2014
13
      GIM_Try, /*On fail goto*//*Label 203*/ 3211, // Rule ID 2057 //
2015
13
        GIM_CheckFeatures, GIFBS_InMicroMips,
2016
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2017
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2018
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2019
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2020
13
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExtAndi16,
2021
13
        // MIs[1] Operand 1
2022
13
        // No operand predicates
2023
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2024
13
        // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)  =>  (ANDI16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2025
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MM,
2026
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2027
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
2028
13
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2029
13
        GIR_EraseFromParent, /*InsnID*/0,
2030
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2031
13
        // GIR_Coverage, 2057,
2032
13
        GIR_Done,
2033
13
      // Label 203: @3211
2034
13
      GIM_Try, /*On fail goto*//*Label 204*/ 3254, // Rule ID 2209 //
2035
13
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2036
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2037
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2038
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2039
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2040
13
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExtAndi16,
2041
13
        // MIs[1] Operand 1
2042
13
        // No operand predicates
2043
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2044
13
        // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)  =>  (ANDI16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2045
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MMR6,
2046
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2047
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
2048
13
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2049
13
        GIR_EraseFromParent, /*InsnID*/0,
2050
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2051
13
        // GIR_Coverage, 2209,
2052
13
        GIR_Done,
2053
13
      // Label 204: @3254
2054
13
      GIM_Try, /*On fail goto*//*Label 205*/ 3277, // Rule ID 39 //
2055
13
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2056
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2057
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2058
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2059
13
        // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (AND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2060
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND,
2061
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2062
13
        // GIR_Coverage, 39,
2063
13
        GIR_Done,
2064
13
      // Label 205: @3277
2065
13
      GIM_Try, /*On fail goto*//*Label 206*/ 3300, // Rule ID 1029 //
2066
13
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2067
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2068
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2069
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
2070
13
        // (and:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (AND16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2071
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND16_MM,
2072
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2073
13
        // GIR_Coverage, 1029,
2074
13
        GIR_Done,
2075
13
      // Label 206: @3300
2076
13
      GIM_Try, /*On fail goto*//*Label 207*/ 3323, // Rule ID 1045 //
2077
13
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2078
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2079
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2080
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2081
13
        // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (AND_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2082
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_MM,
2083
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2084
13
        // GIR_Coverage, 1045,
2085
13
        GIR_Done,
2086
13
      // Label 207: @3323
2087
13
      GIM_Try, /*On fail goto*//*Label 208*/ 3346, // Rule ID 1127 //
2088
13
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2089
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2090
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2091
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2092
13
        // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (AND_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2093
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_MMR6,
2094
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2095
13
        // GIR_Coverage, 1127,
2096
13
        GIR_Done,
2097
13
      // Label 208: @3346
2098
13
      GIM_Try, /*On fail goto*//*Label 209*/ 3369, // Rule ID 1724 //
2099
13
        GIM_CheckFeatures, GIFBS_InMips16Mode,
2100
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2101
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2102
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
2103
13
        // (and:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (AndRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2104
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AndRxRxRy16,
2105
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2106
13
        // GIR_Coverage, 1724,
2107
13
        GIR_Done,
2108
13
      // Label 209: @3369
2109
13
      GIM_Reject,
2110
13
    // Label 202: @3370
2111
13
    GIM_Reject,
2112
13
    // Label 196: @3371
2113
13
    GIM_Try, /*On fail goto*//*Label 210*/ 3458,
2114
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2115
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2116
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2117
13
      GIM_Try, /*On fail goto*//*Label 211*/ 3438, // Rule ID 241 //
2118
13
        GIM_CheckFeatures, GIFBS_HasCnMips,
2119
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2120
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
2121
13
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2122
13
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2123
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2124
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2125
13
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
2126
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2127
13
        // (and:{ *:[i64] } (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), 255:{ *:[i64] })  =>  (BADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2128
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BADDu,
2129
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2130
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2131
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2132
13
        GIR_EraseFromParent, /*InsnID*/0,
2133
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2134
13
        // GIR_Coverage, 241,
2135
13
        GIR_Done,
2136
13
      // Label 211: @3438
2137
13
      GIM_Try, /*On fail goto*//*Label 212*/ 3457, // Rule ID 184 //
2138
13
        GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2139
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2140
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2141
13
        // (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (AND64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2142
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND64,
2143
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2144
13
        // GIR_Coverage, 184,
2145
13
        GIR_Done,
2146
13
      // Label 212: @3457
2147
13
      GIM_Reject,
2148
13
    // Label 210: @3458
2149
13
    GIM_Reject,
2150
13
    // Label 197: @3459
2151
13
    GIM_Try, /*On fail goto*//*Label 213*/ 3490, // Rule ID 486 //
2152
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2153
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2154
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2155
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2156
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
2157
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
2158
13
      // (and:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (AND_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2159
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_D_PSEUDO,
2160
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2161
13
      // GIR_Coverage, 486,
2162
13
      GIR_Done,
2163
13
    // Label 213: @3490
2164
13
    GIM_Reject,
2165
13
    // Label 198: @3491
2166
13
    GIM_Try, /*On fail goto*//*Label 214*/ 3522, // Rule ID 485 //
2167
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2168
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2169
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2170
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2171
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2172
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2173
13
      // (and:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (AND_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2174
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_W_PSEUDO,
2175
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2176
13
      // GIR_Coverage, 485,
2177
13
      GIR_Done,
2178
13
    // Label 214: @3522
2179
13
    GIM_Reject,
2180
13
    // Label 199: @3523
2181
13
    GIM_Try, /*On fail goto*//*Label 215*/ 3554, // Rule ID 484 //
2182
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2183
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2184
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2185
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2186
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2187
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2188
13
      // (and:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (AND_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2189
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_H_PSEUDO,
2190
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2191
13
      // GIR_Coverage, 484,
2192
13
      GIR_Done,
2193
13
    // Label 215: @3554
2194
13
    GIM_Reject,
2195
13
    // Label 200: @3555
2196
13
    GIM_Try, /*On fail goto*//*Label 216*/ 3586, // Rule ID 483 //
2197
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2198
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2199
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2200
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2201
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2202
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2203
13
      // (and:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (AND_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2204
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V,
2205
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2206
13
      // GIR_Coverage, 483,
2207
13
      GIR_Done,
2208
13
    // Label 216: @3586
2209
13
    GIM_Reject,
2210
13
    // Label 201: @3587
2211
13
    GIM_Reject,
2212
13
    // Label 8: @3588
2213
13
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 223*/ 3889,
2214
13
    /*GILLT_s32*//*Label 217*/ 3602,
2215
13
    /*GILLT_s64*//*Label 218*/ 3729, 0,
2216
13
    /*GILLT_v2s64*//*Label 219*/ 3761, 0,
2217
13
    /*GILLT_v4s32*//*Label 220*/ 3793,
2218
13
    /*GILLT_v8s16*//*Label 221*/ 3825,
2219
13
    /*GILLT_v16s8*//*Label 222*/ 3857,
2220
13
    // Label 217: @3602
2221
13
    GIM_Try, /*On fail goto*//*Label 224*/ 3728,
2222
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2223
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2224
13
      GIM_Try, /*On fail goto*//*Label 225*/ 3635, // Rule ID 40 //
2225
13
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2226
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2227
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2228
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2229
13
        // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (OR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2230
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR,
2231
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2232
13
        // GIR_Coverage, 40,
2233
13
        GIR_Done,
2234
13
      // Label 225: @3635
2235
13
      GIM_Try, /*On fail goto*//*Label 226*/ 3658, // Rule ID 1031 //
2236
13
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2237
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2238
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2239
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
2240
13
        // (or:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (OR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2241
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR16_MM,
2242
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2243
13
        // GIR_Coverage, 1031,
2244
13
        GIR_Done,
2245
13
      // Label 226: @3658
2246
13
      GIM_Try, /*On fail goto*//*Label 227*/ 3681, // Rule ID 1046 //
2247
13
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2248
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2249
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2250
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2251
13
        // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (OR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2252
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_MM,
2253
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2254
13
        // GIR_Coverage, 1046,
2255
13
        GIR_Done,
2256
13
      // Label 227: @3681
2257
13
      GIM_Try, /*On fail goto*//*Label 228*/ 3704, // Rule ID 1140 //
2258
13
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2259
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2260
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2261
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2262
13
        // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (OR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2263
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_MMR6,
2264
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2265
13
        // GIR_Coverage, 1140,
2266
13
        GIR_Done,
2267
13
      // Label 228: @3704
2268
13
      GIM_Try, /*On fail goto*//*Label 229*/ 3727, // Rule ID 1726 //
2269
13
        GIM_CheckFeatures, GIFBS_InMips16Mode,
2270
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2271
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2272
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
2273
13
        // (or:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (OrRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2274
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OrRxRxRy16,
2275
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2276
13
        // GIR_Coverage, 1726,
2277
13
        GIR_Done,
2278
13
      // Label 229: @3727
2279
13
      GIM_Reject,
2280
13
    // Label 224: @3728
2281
13
    GIM_Reject,
2282
13
    // Label 218: @3729
2283
13
    GIM_Try, /*On fail goto*//*Label 230*/ 3760, // Rule ID 185 //
2284
13
      GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2285
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2286
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2287
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2288
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2289
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2290
13
      // (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (OR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2291
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR64,
2292
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2293
13
      // GIR_Coverage, 185,
2294
13
      GIR_Done,
2295
13
    // Label 230: @3760
2296
13
    GIM_Reject,
2297
13
    // Label 219: @3761
2298
13
    GIM_Try, /*On fail goto*//*Label 231*/ 3792, // Rule ID 892 //
2299
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2300
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2301
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2302
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2303
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
2304
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
2305
13
      // (or:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (OR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2306
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_D_PSEUDO,
2307
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2308
13
      // GIR_Coverage, 892,
2309
13
      GIR_Done,
2310
13
    // Label 231: @3792
2311
13
    GIM_Reject,
2312
13
    // Label 220: @3793
2313
13
    GIM_Try, /*On fail goto*//*Label 232*/ 3824, // Rule ID 891 //
2314
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2315
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2316
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2317
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2318
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2319
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2320
13
      // (or:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (OR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2321
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_W_PSEUDO,
2322
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2323
13
      // GIR_Coverage, 891,
2324
13
      GIR_Done,
2325
13
    // Label 232: @3824
2326
13
    GIM_Reject,
2327
13
    // Label 221: @3825
2328
13
    GIM_Try, /*On fail goto*//*Label 233*/ 3856, // Rule ID 890 //
2329
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2330
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2331
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2332
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2333
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2334
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2335
13
      // (or:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (OR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2336
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_H_PSEUDO,
2337
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2338
13
      // GIR_Coverage, 890,
2339
13
      GIR_Done,
2340
13
    // Label 233: @3856
2341
13
    GIM_Reject,
2342
13
    // Label 222: @3857
2343
13
    GIM_Try, /*On fail goto*//*Label 234*/ 3888, // Rule ID 889 //
2344
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2345
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2346
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2347
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2348
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2349
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2350
13
      // (or:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (OR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2351
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V,
2352
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2353
13
      // GIR_Coverage, 889,
2354
13
      GIR_Done,
2355
13
    // Label 234: @3888
2356
13
    GIM_Reject,
2357
13
    // Label 223: @3889
2358
13
    GIM_Reject,
2359
13
    // Label 9: @3890
2360
13
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 241*/ 4683,
2361
13
    /*GILLT_s32*//*Label 235*/ 3904,
2362
13
    /*GILLT_s64*//*Label 236*/ 4467, 0,
2363
13
    /*GILLT_v2s64*//*Label 237*/ 4555, 0,
2364
13
    /*GILLT_v4s32*//*Label 238*/ 4587,
2365
13
    /*GILLT_v8s16*//*Label 239*/ 4619,
2366
13
    /*GILLT_v16s8*//*Label 240*/ 4651,
2367
13
    // Label 235: @3904
2368
13
    GIM_Try, /*On fail goto*//*Label 242*/ 4466,
2369
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2370
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2371
13
      GIM_Try, /*On fail goto*//*Label 243*/ 3971, // Rule ID 42 //
2372
13
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2373
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2374
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2375
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2376
13
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2377
13
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2378
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2379
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2380
13
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2381
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2382
13
        // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] })  =>  (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2383
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
2384
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2385
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2386
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2387
13
        GIR_EraseFromParent, /*InsnID*/0,
2388
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2389
13
        // GIR_Coverage, 42,
2390
13
        GIR_Done,
2391
13
      // Label 243: @3971
2392
13
      GIM_Try, /*On fail goto*//*Label 244*/ 4028, // Rule ID 1048 //
2393
13
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2394
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2395
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2396
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2397
13
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2398
13
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2399
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2400
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2401
13
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2402
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2403
13
        // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] })  =>  (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2404
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MM,
2405
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2406
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2407
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2408
13
        GIR_EraseFromParent, /*InsnID*/0,
2409
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2410
13
        // GIR_Coverage, 1048,
2411
13
        GIR_Done,
2412
13
      // Label 244: @4028
2413
13
      GIM_Try, /*On fail goto*//*Label 245*/ 4085, // Rule ID 1139 //
2414
13
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2415
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2416
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2417
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2418
13
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2419
13
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2420
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2421
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2422
13
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2423
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2424
13
        // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] })  =>  (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2425
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
2426
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2427
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2428
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2429
13
        GIR_EraseFromParent, /*InsnID*/0,
2430
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2431
13
        // GIR_Coverage, 1139,
2432
13
        GIR_Done,
2433
13
      // Label 245: @4085
2434
13
      GIM_Try, /*On fail goto*//*Label 246*/ 4117, // Rule ID 1166 //
2435
13
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2436
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2437
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2438
13
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2439
13
        // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })  =>  (NOT16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2440
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MMR6,
2441
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2442
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
2443
13
        GIR_EraseFromParent, /*InsnID*/0,
2444
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2445
13
        // GIR_Coverage, 1166,
2446
13
        GIR_Done,
2447
13
      // Label 246: @4117
2448
13
      GIM_Try, /*On fail goto*//*Label 247*/ 4149, // Rule ID 1030 //
2449
13
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2450
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2451
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2452
13
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2453
13
        // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })  =>  (NOT16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2454
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MM,
2455
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2456
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
2457
13
        GIR_EraseFromParent, /*InsnID*/0,
2458
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2459
13
        // GIR_Coverage, 1030,
2460
13
        GIR_Done,
2461
13
      // Label 247: @4149
2462
13
      GIM_Try, /*On fail goto*//*Label 248*/ 4184, // Rule ID 1353 //
2463
13
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2464
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2465
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2466
13
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2467
13
        // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2468
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
2469
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2470
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2471
13
        GIR_AddRegister, /*InsnID*/0, Mips::ZERO,
2472
13
        GIR_EraseFromParent, /*InsnID*/0,
2473
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2474
13
        // GIR_Coverage, 1353,
2475
13
        GIR_Done,
2476
13
      // Label 248: @4184
2477
13
      GIM_Try, /*On fail goto*//*Label 249*/ 4216, // Rule ID 1721 //
2478
13
        GIM_CheckFeatures, GIFBS_InMips16Mode,
2479
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2480
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2481
13
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2482
13
        // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, -1:{ *:[i32] })  =>  (NotRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
2483
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NotRxRy16,
2484
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
2485
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // r
2486
13
        GIR_EraseFromParent, /*InsnID*/0,
2487
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2488
13
        // GIR_Coverage, 1721,
2489
13
        GIR_Done,
2490
13
      // Label 249: @4216
2491
13
      GIM_Try, /*On fail goto*//*Label 250*/ 4248, // Rule ID 2052 //
2492
13
        GIM_CheckFeatures, GIFBS_InMicroMips,
2493
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2494
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2495
13
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2496
13
        // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOT16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2497
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MM,
2498
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2499
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2500
13
        GIR_EraseFromParent, /*InsnID*/0,
2501
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2502
13
        // GIR_Coverage, 2052,
2503
13
        GIR_Done,
2504
13
      // Label 250: @4248
2505
13
      GIM_Try, /*On fail goto*//*Label 251*/ 4283, // Rule ID 2053 //
2506
13
        GIM_CheckFeatures, GIFBS_InMicroMips,
2507
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2508
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2509
13
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2510
13
        // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2511
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MM,
2512
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2513
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2514
13
        GIR_AddRegister, /*InsnID*/0, Mips::ZERO,
2515
13
        GIR_EraseFromParent, /*InsnID*/0,
2516
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2517
13
        // GIR_Coverage, 2053,
2518
13
        GIR_Done,
2519
13
      // Label 251: @4283
2520
13
      GIM_Try, /*On fail goto*//*Label 252*/ 4315, // Rule ID 2212 //
2521
13
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2522
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2523
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2524
13
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2525
13
        // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOT16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2526
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MMR6,
2527
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2528
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2529
13
        GIR_EraseFromParent, /*InsnID*/0,
2530
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2531
13
        // GIR_Coverage, 2212,
2532
13
        GIR_Done,
2533
13
      // Label 252: @4315
2534
13
      GIM_Try, /*On fail goto*//*Label 253*/ 4350, // Rule ID 2213 //
2535
13
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2536
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2537
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2538
13
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2539
13
        // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2540
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
2541
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2542
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2543
13
        GIR_AddRegister, /*InsnID*/0, Mips::ZERO,
2544
13
        GIR_EraseFromParent, /*InsnID*/0,
2545
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2546
13
        // GIR_Coverage, 2213,
2547
13
        GIR_Done,
2548
13
      // Label 253: @4350
2549
13
      GIM_Try, /*On fail goto*//*Label 254*/ 4373, // Rule ID 41 //
2550
13
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2551
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2552
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2553
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2554
13
        // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (XOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2555
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR,
2556
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2557
13
        // GIR_Coverage, 41,
2558
13
        GIR_Done,
2559
13
      // Label 254: @4373
2560
13
      GIM_Try, /*On fail goto*//*Label 255*/ 4396, // Rule ID 1033 //
2561
13
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2562
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2563
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2564
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
2565
13
        // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (XOR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2566
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR16_MM,
2567
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2568
13
        // GIR_Coverage, 1033,
2569
13
        GIR_Done,
2570
13
      // Label 255: @4396
2571
13
      GIM_Try, /*On fail goto*//*Label 256*/ 4419, // Rule ID 1047 //
2572
13
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2573
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2574
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2575
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2576
13
        // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (XOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2577
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_MM,
2578
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2579
13
        // GIR_Coverage, 1047,
2580
13
        GIR_Done,
2581
13
      // Label 256: @4419
2582
13
      GIM_Try, /*On fail goto*//*Label 257*/ 4442, // Rule ID 1143 //
2583
13
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2584
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2585
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2586
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2587
13
        // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (XOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2588
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_MMR6,
2589
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2590
13
        // GIR_Coverage, 1143,
2591
13
        GIR_Done,
2592
13
      // Label 257: @4442
2593
13
      GIM_Try, /*On fail goto*//*Label 258*/ 4465, // Rule ID 1728 //
2594
13
        GIM_CheckFeatures, GIFBS_InMips16Mode,
2595
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2596
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2597
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
2598
13
        // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2599
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XorRxRxRy16,
2600
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2601
13
        // GIR_Coverage, 1728,
2602
13
        GIR_Done,
2603
13
      // Label 258: @4465
2604
13
      GIM_Reject,
2605
13
    // Label 242: @4466
2606
13
    GIM_Reject,
2607
13
    // Label 236: @4467
2608
13
    GIM_Try, /*On fail goto*//*Label 259*/ 4554,
2609
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2610
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2611
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2612
13
      GIM_Try, /*On fail goto*//*Label 260*/ 4534, // Rule ID 187 //
2613
13
        GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2614
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2615
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2616
13
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2617
13
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2618
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2619
13
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2620
13
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2621
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2622
13
        // (xor:{ *:[i64] } (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), -1:{ *:[i64] })  =>  (NOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2623
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR64,
2624
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2625
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2626
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2627
13
        GIR_EraseFromParent, /*InsnID*/0,
2628
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2629
13
        // GIR_Coverage, 187,
2630
13
        GIR_Done,
2631
13
      // Label 260: @4534
2632
13
      GIM_Try, /*On fail goto*//*Label 261*/ 4553, // Rule ID 186 //
2633
13
        GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2634
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2635
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2636
13
        // (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (XOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2637
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR64,
2638
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2639
13
        // GIR_Coverage, 186,
2640
13
        GIR_Done,
2641
13
      // Label 261: @4553
2642
13
      GIM_Reject,
2643
13
    // Label 259: @4554
2644
13
    GIM_Reject,
2645
13
    // Label 237: @4555
2646
13
    GIM_Try, /*On fail goto*//*Label 262*/ 4586, // Rule ID 1008 //
2647
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2648
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2649
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2650
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2651
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
2652
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
2653
13
      // (xor:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (XOR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2654
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_D_PSEUDO,
2655
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2656
13
      // GIR_Coverage, 1008,
2657
13
      GIR_Done,
2658
13
    // Label 262: @4586
2659
13
    GIM_Reject,
2660
13
    // Label 238: @4587
2661
13
    GIM_Try, /*On fail goto*//*Label 263*/ 4618, // Rule ID 1007 //
2662
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2663
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2664
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2665
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2666
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2667
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2668
13
      // (xor:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (XOR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2669
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_W_PSEUDO,
2670
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2671
13
      // GIR_Coverage, 1007,
2672
13
      GIR_Done,
2673
13
    // Label 263: @4618
2674
13
    GIM_Reject,
2675
13
    // Label 239: @4619
2676
13
    GIM_Try, /*On fail goto*//*Label 264*/ 4650, // Rule ID 1006 //
2677
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2678
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2679
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2680
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2681
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2682
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2683
13
      // (xor:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (XOR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2684
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_H_PSEUDO,
2685
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2686
13
      // GIR_Coverage, 1006,
2687
13
      GIR_Done,
2688
13
    // Label 264: @4650
2689
13
    GIM_Reject,
2690
13
    // Label 240: @4651
2691
13
    GIM_Try, /*On fail goto*//*Label 265*/ 4682, // Rule ID 1005 //
2692
13
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2693
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2694
13
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2695
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2696
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2697
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2698
13
      // (xor:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (XOR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2699
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V,
2700
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2701
13
      // GIR_Coverage, 1005,
2702
13
      GIR_Done,
2703
13
    // Label 265: @4682
2704
13
    GIM_Reject,
2705
13
    // Label 241: @4683
2706
13
    GIM_Reject,
2707
13
    // Label 10: @4684
2708
13
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 274*/ 8336,
2709
13
    /*GILLT_s32*//*Label 266*/ 4698,
2710
13
    /*GILLT_s64*//*Label 267*/ 4937,
2711
13
    /*GILLT_v2s16*//*Label 268*/ 4983,
2712
13
    /*GILLT_v2s64*//*Label 269*/ 5029,
2713
13
    /*GILLT_v4s8*//*Label 270*/ 6002,
2714
13
    /*GILLT_v4s32*//*Label 271*/ 6048,
2715
13
    /*GILLT_v8s16*//*Label 272*/ 6951,
2716
13
    /*GILLT_v16s8*//*Label 273*/ 7749,
2717
13
    // Label 266: @4698
2718
13
    GIM_Try, /*On fail goto*//*Label 275*/ 4721, // Rule ID 117 //
2719
13
      GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
2720
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2721
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2722
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
2723
13
      // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (MFC1:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
2724
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1,
2725
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2726
13
      // GIR_Coverage, 117,
2727
13
      GIR_Done,
2728
13
    // Label 275: @4721
2729
13
    GIM_Try, /*On fail goto*//*Label 276*/ 4744, // Rule ID 118 //
2730
13
      GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
2731
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2732
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2733
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2734
13
      // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)  =>  (MTC1:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
2735
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1,
2736
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2737
13
      // GIR_Coverage, 118,
2738
13
      GIR_Done,
2739
13
    // Label 276: @4744
2740
13
    GIM_Try, /*On fail goto*//*Label 277*/ 4767, // Rule ID 1119 //
2741
13
      GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
2742
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2743
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2744
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
2745
13
      // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (MFC1_MM:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
2746
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1_MM,
2747
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2748
13
      // GIR_Coverage, 1119,
2749
13
      GIR_Done,
2750
13
    // Label 277: @4767
2751
13
    GIM_Try, /*On fail goto*//*Label 278*/ 4790, // Rule ID 1120 //
2752
13
      GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
2753
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2754
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2755
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2756
13
      // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)  =>  (MTC1_MM:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
2757
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1_MM,
2758
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2759
13
      // GIR_Coverage, 1120,
2760
13
      GIR_Done,
2761
13
    // Label 278: @4790
2762
13
    GIM_Try, /*On fail goto*//*Label 279*/ 4813, // Rule ID 1132 //
2763
13
      GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
2764
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2765
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2766
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2767
13
      // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)  =>  (MTC1_MMR6:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
2768
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1_MMR6,
2769
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2770
13
      // GIR_Coverage, 1132,
2771
13
      GIR_Done,
2772
13
    // Label 279: @4813
2773
13
    GIM_Try, /*On fail goto*//*Label 280*/ 4836, // Rule ID 1133 //
2774
13
      GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
2775
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2776
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2777
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
2778
13
      // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (MFC1_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
2779
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1_MMR6,
2780
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2781
13
      // GIR_Coverage, 1133,
2782
13
      GIR_Done,
2783
13
    // Label 280: @4836
2784
13
    GIM_Try, /*On fail goto*//*Label 281*/ 4861, // Rule ID 1809 //
2785
13
      GIM_CheckFeatures, GIFBS_HasDSP,
2786
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
2787
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2788
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
2789
13
      // (bitconvert:{ *:[i32] } DSPR:{ *:[v2i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v2i16] }:$src, GPR32:{ *:[i32] })
2790
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2791
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR32*/11,
2792
13
      // GIR_Coverage, 1809,
2793
13
      GIR_Done,
2794
13
    // Label 281: @4861
2795
13
    GIM_Try, /*On fail goto*//*Label 282*/ 4886, // Rule ID 1810 //
2796
13
      GIM_CheckFeatures, GIFBS_HasDSP,
2797
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
2798
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2799
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
2800
13
      // (bitconvert:{ *:[i32] } DSPR:{ *:[v4i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v4i8] }:$src, GPR32:{ *:[i32] })
2801
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2802
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR32*/11,
2803
13
      // GIR_Coverage, 1810,
2804
13
      GIR_Done,
2805
13
    // Label 282: @4886
2806
13
    GIM_Try, /*On fail goto*//*Label 283*/ 4911, // Rule ID 1813 //
2807
13
      GIM_CheckFeatures, GIFBS_HasDSP,
2808
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
2809
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2810
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
2811
13
      // (bitconvert:{ *:[f32] } DSPR:{ *:[v2i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v2i16] }:$src, FGR32:{ *:[i32] })
2812
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2813
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FGR32*/8,
2814
13
      // GIR_Coverage, 1813,
2815
13
      GIR_Done,
2816
13
    // Label 283: @4911
2817
13
    GIM_Try, /*On fail goto*//*Label 284*/ 4936, // Rule ID 1814 //
2818
13
      GIM_CheckFeatures, GIFBS_HasDSP,
2819
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
2820
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2821
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
2822
13
      // (bitconvert:{ *:[f32] } DSPR:{ *:[v4i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v4i8] }:$src, FGR32:{ *:[i32] })
2823
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2824
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FGR32*/8,
2825
13
      // GIR_Coverage, 1814,
2826
13
      GIR_Done,
2827
13
    // Label 284: @4936
2828
13
    GIM_Reject,
2829
13
    // Label 267: @4937
2830
13
    GIM_Try, /*On fail goto*//*Label 285*/ 4982,
2831
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2832
13
      GIM_Try, /*On fail goto*//*Label 286*/ 4962, // Rule ID 119 //
2833
13
        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
2834
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
2835
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2836
13
        // (bitconvert:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMTC1:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt)
2837
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMTC1,
2838
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2839
13
        // GIR_Coverage, 119,
2840
13
        GIR_Done,
2841
13
      // Label 286: @4962
2842
13
      GIM_Try, /*On fail goto*//*Label 287*/ 4981, // Rule ID 120 //
2843
13
        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
2844
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2845
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
2846
13
        // (bitconvert:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (DMFC1:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs)
2847
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMFC1,
2848
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2849
13
        // GIR_Coverage, 120,
2850
13
        GIR_Done,
2851
13
      // Label 287: @4981
2852
13
      GIM_Reject,
2853
13
    // Label 285: @4982
2854
13
    GIM_Reject,
2855
13
    // Label 268: @4983
2856
13
    GIM_Try, /*On fail goto*//*Label 288*/ 5028,
2857
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2858
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
2859
13
      GIM_Try, /*On fail goto*//*Label 289*/ 5010, // Rule ID 1811 //
2860
13
        GIM_CheckFeatures, GIFBS_HasDSP,
2861
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2862
13
        // (bitconvert:{ *:[v2i16] } GPR32:{ *:[i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i16] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
2863
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2864
13
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
2865
13
        // GIR_Coverage, 1811,
2866
13
        GIR_Done,
2867
13
      // Label 289: @5010
2868
13
      GIM_Try, /*On fail goto*//*Label 290*/ 5027, // Rule ID 1815 //
2869
13
        GIM_CheckFeatures, GIFBS_HasDSP,
2870
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
2871
13
        // (bitconvert:{ *:[v2i16] } FGR32:{ *:[f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i16] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
2872
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2873
13
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
2874
13
        // GIR_Coverage, 1815,
2875
13
        GIR_Done,
2876
13
      // Label 290: @5027
2877
13
      GIM_Reject,
2878
13
    // Label 288: @5028
2879
13
    GIM_Reject,
2880
13
    // Label 269: @5029
2881
13
    GIM_Try, /*On fail goto*//*Label 291*/ 5050, // Rule ID 1896 //
2882
13
      GIM_CheckFeatures, GIFBS_HasMSA,
2883
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2884
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2885
13
      // (bitconvert:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src, MSA128D:{ *:[i32] })
2886
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2887
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
2888
13
      // GIR_Coverage, 1896,
2889
13
      GIR_Done,
2890
13
    // Label 291: @5050
2891
13
    GIM_Try, /*On fail goto*//*Label 292*/ 5071, // Rule ID 1899 //
2892
13
      GIM_CheckFeatures, GIFBS_HasMSA,
2893
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2894
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2895
13
      // (bitconvert:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src, MSA128D:{ *:[i32] })
2896
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2897
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
2898
13
      // GIR_Coverage, 1899,
2899
13
      GIR_Done,
2900
13
    // Label 292: @5071
2901
13
    GIM_Try, /*On fail goto*//*Label 293*/ 5092, // Rule ID 1916 //
2902
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2903
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2904
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2905
13
      // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
2906
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2907
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
2908
13
      // GIR_Coverage, 1916,
2909
13
      GIR_Done,
2910
13
    // Label 293: @5092
2911
13
    GIM_Try, /*On fail goto*//*Label 294*/ 5113, // Rule ID 1917 //
2912
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2913
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2914
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2915
13
      // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
2916
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2917
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
2918
13
      // GIR_Coverage, 1917,
2919
13
      GIR_Done,
2920
13
    // Label 294: @5113
2921
13
    GIM_Try, /*On fail goto*//*Label 295*/ 5134, // Rule ID 1918 //
2922
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2923
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2924
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2925
13
      // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
2926
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2927
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
2928
13
      // GIR_Coverage, 1918,
2929
13
      GIR_Done,
2930
13
    // Label 295: @5134
2931
13
    GIM_Try, /*On fail goto*//*Label 296*/ 5155, // Rule ID 1919 //
2932
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2933
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2934
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2935
13
      // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
2936
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2937
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
2938
13
      // GIR_Coverage, 1919,
2939
13
      GIR_Done,
2940
13
    // Label 296: @5155
2941
13
    GIM_Try, /*On fail goto*//*Label 297*/ 5176, // Rule ID 1920 //
2942
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2943
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2944
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2945
13
      // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
2946
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2947
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
2948
13
      // GIR_Coverage, 1920,
2949
13
      GIR_Done,
2950
13
    // Label 297: @5176
2951
13
    GIM_Try, /*On fail goto*//*Label 298*/ 5197, // Rule ID 1926 //
2952
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2953
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2954
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2955
13
      // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
2956
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2957
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
2958
13
      // GIR_Coverage, 1926,
2959
13
      GIR_Done,
2960
13
    // Label 298: @5197
2961
13
    GIM_Try, /*On fail goto*//*Label 299*/ 5218, // Rule ID 1927 //
2962
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2963
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2964
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2965
13
      // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
2966
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2967
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
2968
13
      // GIR_Coverage, 1927,
2969
13
      GIR_Done,
2970
13
    // Label 299: @5218
2971
13
    GIM_Try, /*On fail goto*//*Label 300*/ 5239, // Rule ID 1928 //
2972
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2973
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2974
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2975
13
      // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
2976
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2977
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
2978
13
      // GIR_Coverage, 1928,
2979
13
      GIR_Done,
2980
13
    // Label 300: @5239
2981
13
    GIM_Try, /*On fail goto*//*Label 301*/ 5260, // Rule ID 1929 //
2982
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2983
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2984
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2985
13
      // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
2986
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2987
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
2988
13
      // GIR_Coverage, 1929,
2989
13
      GIR_Done,
2990
13
    // Label 301: @5260
2991
13
    GIM_Try, /*On fail goto*//*Label 302*/ 5281, // Rule ID 1930 //
2992
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2993
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2994
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2995
13
      // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
2996
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2997
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
2998
13
      // GIR_Coverage, 1930,
2999
13
      GIR_Done,
3000
13
    // Label 302: @5281
3001
13
    GIM_Try, /*On fail goto*//*Label 303*/ 5381, // Rule ID 1935 //
3002
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3003
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3004
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3005
13
      // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3006
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3007
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3008
13
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3009
13
      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3010
13
      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
3011
13
      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
3012
13
      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3013
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
3014
13
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
3015
13
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3016
13
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
3017
13
      GIR_AddImm, /*InsnID*/3, /*Imm*/27,
3018
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3019
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3020
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3021
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
3022
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3023
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3024
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3025
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3026
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3027
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3028
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3029
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3030
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3031
13
      GIR_EraseFromParent, /*InsnID*/0,
3032
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
3033
13
      // GIR_Coverage, 1935,
3034
13
      GIR_Done,
3035
13
    // Label 303: @5381
3036
13
    GIM_Try, /*On fail goto*//*Label 304*/ 5481, // Rule ID 1936 //
3037
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3038
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3039
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3040
13
      // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3041
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3042
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3043
13
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3044
13
      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3045
13
      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
3046
13
      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
3047
13
      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3048
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
3049
13
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
3050
13
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3051
13
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
3052
13
      GIR_AddImm, /*InsnID*/3, /*Imm*/27,
3053
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3054
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3055
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3056
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
3057
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3058
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3059
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3060
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3061
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3062
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3063
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3064
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3065
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3066
13
      GIR_EraseFromParent, /*InsnID*/0,
3067
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
3068
13
      // GIR_Coverage, 1936,
3069
13
      GIR_Done,
3070
13
    // Label 304: @5481
3071
13
    GIM_Try, /*On fail goto*//*Label 305*/ 5546, // Rule ID 1940 //
3072
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3073
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3074
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3075
13
      // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3076
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3077
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3078
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3079
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3080
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3081
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3082
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3083
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3084
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3085
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3086
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3087
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3088
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3089
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3090
13
      GIR_EraseFromParent, /*InsnID*/0,
3091
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
3092
13
      // GIR_Coverage, 1940,
3093
13
      GIR_Done,
3094
13
    // Label 305: @5546
3095
13
    GIM_Try, /*On fail goto*//*Label 306*/ 5611, // Rule ID 1941 //
3096
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3097
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3098
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3099
13
      // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3100
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3101
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3102
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3103
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3104
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3105
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3106
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3107
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3108
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3109
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3110
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3111
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3112
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3113
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3114
13
      GIR_EraseFromParent, /*InsnID*/0,
3115
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
3116
13
      // GIR_Coverage, 1941,
3117
13
      GIR_Done,
3118
13
    // Label 306: @5611
3119
13
    GIM_Try, /*On fail goto*//*Label 307*/ 5676, // Rule ID 1945 //
3120
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3121
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3122
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3123
13
      // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3124
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3125
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3126
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3127
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3128
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3129
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3130
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3131
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3132
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3133
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3134
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3135
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3136
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3137
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3138
13
      GIR_EraseFromParent, /*InsnID*/0,
3139
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
3140
13
      // GIR_Coverage, 1945,
3141
13
      GIR_Done,
3142
13
    // Label 307: @5676
3143
13
    GIM_Try, /*On fail goto*//*Label 308*/ 5741, // Rule ID 1946 //
3144
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3145
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3146
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3147
13
      // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3148
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3149
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3150
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3151
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3152
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3153
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3154
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3155
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3156
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3157
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3158
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3159
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3160
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3161
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3162
13
      GIR_EraseFromParent, /*InsnID*/0,
3163
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
3164
13
      // GIR_Coverage, 1946,
3165
13
      GIR_Done,
3166
13
    // Label 308: @5741
3167
13
    GIM_Try, /*On fail goto*//*Label 309*/ 5806, // Rule ID 1950 //
3168
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3169
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3170
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3171
13
      // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3172
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3173
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3174
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3175
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3176
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3177
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3178
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3179
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3180
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3181
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3182
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3183
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3184
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3185
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3186
13
      GIR_EraseFromParent, /*InsnID*/0,
3187
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
3188
13
      // GIR_Coverage, 1950,
3189
13
      GIR_Done,
3190
13
    // Label 309: @5806
3191
13
    GIM_Try, /*On fail goto*//*Label 310*/ 5871, // Rule ID 1951 //
3192
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3193
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3194
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3195
13
      // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3196
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3197
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3198
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3199
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3200
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3201
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3202
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3203
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3204
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3205
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3206
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3207
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3208
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3209
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3210
13
      GIR_EraseFromParent, /*InsnID*/0,
3211
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
3212
13
      // GIR_Coverage, 1951,
3213
13
      GIR_Done,
3214
13
    // Label 310: @5871
3215
13
    GIM_Try, /*On fail goto*//*Label 311*/ 5936, // Rule ID 1955 //
3216
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3217
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3218
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3219
13
      // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3220
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3221
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3222
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3223
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3224
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3225
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3226
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3227
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3228
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3229
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3230
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3231
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3232
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3233
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3234
13
      GIR_EraseFromParent, /*InsnID*/0,
3235
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
3236
13
      // GIR_Coverage, 1955,
3237
13
      GIR_Done,
3238
13
    // Label 311: @5936
3239
13
    GIM_Try, /*On fail goto*//*Label 312*/ 6001, // Rule ID 1956 //
3240
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3241
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3242
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3243
13
      // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3244
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3245
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3246
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3247
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3248
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3249
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3250
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3251
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3252
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3253
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3254
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3255
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3256
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3257
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3258
13
      GIR_EraseFromParent, /*InsnID*/0,
3259
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
3260
13
      // GIR_Coverage, 1956,
3261
13
      GIR_Done,
3262
13
    // Label 312: @6001
3263
13
    GIM_Reject,
3264
13
    // Label 270: @6002
3265
13
    GIM_Try, /*On fail goto*//*Label 313*/ 6047,
3266
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3267
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
3268
13
      GIM_Try, /*On fail goto*//*Label 314*/ 6029, // Rule ID 1812 //
3269
13
        GIM_CheckFeatures, GIFBS_HasDSP,
3270
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
3271
13
        // (bitconvert:{ *:[v4i8] } GPR32:{ *:[i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i8] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
3272
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3273
13
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
3274
13
        // GIR_Coverage, 1812,
3275
13
        GIR_Done,
3276
13
      // Label 314: @6029
3277
13
      GIM_Try, /*On fail goto*//*Label 315*/ 6046, // Rule ID 1816 //
3278
13
        GIM_CheckFeatures, GIFBS_HasDSP,
3279
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
3280
13
        // (bitconvert:{ *:[v4i8] } FGR32:{ *:[f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i8] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
3281
13
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3282
13
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
3283
13
        // GIR_Coverage, 1816,
3284
13
        GIR_Done,
3285
13
      // Label 315: @6046
3286
13
      GIM_Reject,
3287
13
    // Label 313: @6047
3288
13
    GIM_Reject,
3289
13
    // Label 271: @6048
3290
13
    GIM_Try, /*On fail goto*//*Label 316*/ 6069, // Rule ID 1895 //
3291
13
      GIM_CheckFeatures, GIFBS_HasMSA,
3292
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3293
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3294
13
      // (bitconvert:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] })
3295
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3296
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
3297
13
      // GIR_Coverage, 1895,
3298
13
      GIR_Done,
3299
13
    // Label 316: @6069
3300
13
    GIM_Try, /*On fail goto*//*Label 317*/ 6090, // Rule ID 1898 //
3301
13
      GIM_CheckFeatures, GIFBS_HasMSA,
3302
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3303
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3304
13
      // (bitconvert:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] })
3305
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3306
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
3307
13
      // GIR_Coverage, 1898,
3308
13
      GIR_Done,
3309
13
    // Label 317: @6090
3310
13
    GIM_Try, /*On fail goto*//*Label 318*/ 6111, // Rule ID 1911 //
3311
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3312
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3313
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3314
13
      // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3315
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3316
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
3317
13
      // GIR_Coverage, 1911,
3318
13
      GIR_Done,
3319
13
    // Label 318: @6111
3320
13
    GIM_Try, /*On fail goto*//*Label 319*/ 6132, // Rule ID 1912 //
3321
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3322
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3323
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3324
13
      // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3325
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3326
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
3327
13
      // GIR_Coverage, 1912,
3328
13
      GIR_Done,
3329
13
    // Label 319: @6132
3330
13
    GIM_Try, /*On fail goto*//*Label 320*/ 6153, // Rule ID 1913 //
3331
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3332
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3333
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3334
13
      // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3335
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3336
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
3337
13
      // GIR_Coverage, 1913,
3338
13
      GIR_Done,
3339
13
    // Label 320: @6153
3340
13
    GIM_Try, /*On fail goto*//*Label 321*/ 6174, // Rule ID 1914 //
3341
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3342
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3343
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3344
13
      // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3345
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3346
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
3347
13
      // GIR_Coverage, 1914,
3348
13
      GIR_Done,
3349
13
    // Label 321: @6174
3350
13
    GIM_Try, /*On fail goto*//*Label 322*/ 6195, // Rule ID 1915 //
3351
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3352
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3353
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3354
13
      // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3355
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3356
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
3357
13
      // GIR_Coverage, 1915,
3358
13
      GIR_Done,
3359
13
    // Label 322: @6195
3360
13
    GIM_Try, /*On fail goto*//*Label 323*/ 6216, // Rule ID 1921 //
3361
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3362
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3363
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3364
13
      // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3365
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3366
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
3367
13
      // GIR_Coverage, 1921,
3368
13
      GIR_Done,
3369
13
    // Label 323: @6216
3370
13
    GIM_Try, /*On fail goto*//*Label 324*/ 6237, // Rule ID 1922 //
3371
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3372
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3373
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3374
13
      // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3375
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3376
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
3377
13
      // GIR_Coverage, 1922,
3378
13
      GIR_Done,
3379
13
    // Label 324: @6237
3380
13
    GIM_Try, /*On fail goto*//*Label 325*/ 6258, // Rule ID 1923 //
3381
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3382
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3383
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3384
13
      // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3385
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3386
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
3387
13
      // GIR_Coverage, 1923,
3388
13
      GIR_Done,
3389
13
    // Label 325: @6258
3390
13
    GIM_Try, /*On fail goto*//*Label 326*/ 6279, // Rule ID 1924 //
3391
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3392
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3393
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3394
13
      // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3395
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3396
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
3397
13
      // GIR_Coverage, 1924,
3398
13
      GIR_Done,
3399
13
    // Label 326: @6279
3400
13
    GIM_Try, /*On fail goto*//*Label 327*/ 6300, // Rule ID 1925 //
3401
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3402
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3403
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3404
13
      // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3405
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3406
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
3407
13
      // GIR_Coverage, 1925,
3408
13
      GIR_Done,
3409
13
    // Label 327: @6300
3410
13
    GIM_Try, /*On fail goto*//*Label 328*/ 6365, // Rule ID 1933 //
3411
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3412
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3413
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3414
13
      // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3415
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3416
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3417
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3418
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3419
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3420
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3421
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3422
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3423
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3424
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3425
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3426
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3427
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3428
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3429
13
      GIR_EraseFromParent, /*InsnID*/0,
3430
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
3431
13
      // GIR_Coverage, 1933,
3432
13
      GIR_Done,
3433
13
    // Label 328: @6365
3434
13
    GIM_Try, /*On fail goto*//*Label 329*/ 6430, // Rule ID 1934 //
3435
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3436
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3437
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3438
13
      // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3439
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3440
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3441
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3442
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3443
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3444
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3445
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3446
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3447
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3448
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3449
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3450
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3451
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3452
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3453
13
      GIR_EraseFromParent, /*InsnID*/0,
3454
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
3455
13
      // GIR_Coverage, 1934,
3456
13
      GIR_Done,
3457
13
    // Label 329: @6430
3458
13
    GIM_Try, /*On fail goto*//*Label 330*/ 6495, // Rule ID 1938 //
3459
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3460
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3461
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3462
13
      // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3463
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3464
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3465
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3466
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3467
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3468
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3469
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3470
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3471
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3472
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3473
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3474
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3475
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3476
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3477
13
      GIR_EraseFromParent, /*InsnID*/0,
3478
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
3479
13
      // GIR_Coverage, 1938,
3480
13
      GIR_Done,
3481
13
    // Label 330: @6495
3482
13
    GIM_Try, /*On fail goto*//*Label 331*/ 6560, // Rule ID 1939 //
3483
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3484
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3485
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3486
13
      // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3487
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3488
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3489
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3490
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3491
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3492
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3493
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3494
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3495
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3496
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3497
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3498
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3499
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3500
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3501
13
      GIR_EraseFromParent, /*InsnID*/0,
3502
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
3503
13
      // GIR_Coverage, 1939,
3504
13
      GIR_Done,
3505
13
    // Label 331: @6560
3506
13
    GIM_Try, /*On fail goto*//*Label 332*/ 6625, // Rule ID 1943 //
3507
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3508
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3509
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3510
13
      // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3511
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3512
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3513
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3514
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3515
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3516
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3517
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3518
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3519
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3520
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3521
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3522
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3523
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3524
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3525
13
      GIR_EraseFromParent, /*InsnID*/0,
3526
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
3527
13
      // GIR_Coverage, 1943,
3528
13
      GIR_Done,
3529
13
    // Label 332: @6625
3530
13
    GIM_Try, /*On fail goto*//*Label 333*/ 6690, // Rule ID 1944 //
3531
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3532
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3533
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3534
13
      // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3535
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3536
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3537
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3538
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3539
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3540
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3541
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3542
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3543
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3544
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3545
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3546
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3547
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3548
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3549
13
      GIR_EraseFromParent, /*InsnID*/0,
3550
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
3551
13
      // GIR_Coverage, 1944,
3552
13
      GIR_Done,
3553
13
    // Label 333: @6690
3554
13
    GIM_Try, /*On fail goto*//*Label 334*/ 6755, // Rule ID 1960 //
3555
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3556
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3557
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3558
13
      // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3559
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3560
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3561
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3562
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3563
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3564
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3565
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3566
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3567
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3568
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3569
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3570
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3571
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3572
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3573
13
      GIR_EraseFromParent, /*InsnID*/0,
3574
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
3575
13
      // GIR_Coverage, 1960,
3576
13
      GIR_Done,
3577
13
    // Label 334: @6755
3578
13
    GIM_Try, /*On fail goto*//*Label 335*/ 6820, // Rule ID 1961 //
3579
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3580
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3581
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3582
13
      // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3583
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3584
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3585
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3586
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3587
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3588
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3589
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3590
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3591
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3592
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3593
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3594
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3595
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3596
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3597
13
      GIR_EraseFromParent, /*InsnID*/0,
3598
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
3599
13
      // GIR_Coverage, 1961,
3600
13
      GIR_Done,
3601
13
    // Label 335: @6820
3602
13
    GIM_Try, /*On fail goto*//*Label 336*/ 6885, // Rule ID 1965 //
3603
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3604
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3605
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3606
13
      // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3607
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3608
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3609
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3610
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3611
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3612
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3613
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3614
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3615
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3616
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3617
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3618
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3619
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3620
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3621
13
      GIR_EraseFromParent, /*InsnID*/0,
3622
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
3623
13
      // GIR_Coverage, 1965,
3624
13
      GIR_Done,
3625
13
    // Label 336: @6885
3626
13
    GIM_Try, /*On fail goto*//*Label 337*/ 6950, // Rule ID 1966 //
3627
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3628
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3629
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3630
13
      // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3631
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3632
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3633
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3634
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3635
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3636
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3637
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3638
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3639
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3640
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3641
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3642
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3643
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3644
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3645
13
      GIR_EraseFromParent, /*InsnID*/0,
3646
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
3647
13
      // GIR_Coverage, 1966,
3648
13
      GIR_Done,
3649
13
    // Label 337: @6950
3650
13
    GIM_Reject,
3651
13
    // Label 272: @6951
3652
13
    GIM_Try, /*On fail goto*//*Label 338*/ 6972, // Rule ID 1894 //
3653
13
      GIM_CheckFeatures, GIFBS_HasMSA,
3654
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3655
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3656
13
      // (bitconvert:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] })
3657
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3658
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
3659
13
      // GIR_Coverage, 1894,
3660
13
      GIR_Done,
3661
13
    // Label 338: @6972
3662
13
    GIM_Try, /*On fail goto*//*Label 339*/ 6993, // Rule ID 1897 //
3663
13
      GIM_CheckFeatures, GIFBS_HasMSA,
3664
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3665
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3666
13
      // (bitconvert:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] })
3667
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3668
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
3669
13
      // GIR_Coverage, 1897,
3670
13
      GIR_Done,
3671
13
    // Label 339: @6993
3672
13
    GIM_Try, /*On fail goto*//*Label 340*/ 7014, // Rule ID 1906 //
3673
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3674
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3675
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3676
13
      // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src, MSA128H:{ *:[i32] })
3677
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3678
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
3679
13
      // GIR_Coverage, 1906,
3680
13
      GIR_Done,
3681
13
    // Label 340: @7014
3682
13
    GIM_Try, /*On fail goto*//*Label 341*/ 7035, // Rule ID 1907 //
3683
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3684
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3685
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3686
13
      // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] })
3687
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3688
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
3689
13
      // GIR_Coverage, 1907,
3690
13
      GIR_Done,
3691
13
    // Label 341: @7035
3692
13
    GIM_Try, /*On fail goto*//*Label 342*/ 7056, // Rule ID 1908 //
3693
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3694
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3695
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3696
13
      // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] })
3697
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3698
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
3699
13
      // GIR_Coverage, 1908,
3700
13
      GIR_Done,
3701
13
    // Label 342: @7056
3702
13
    GIM_Try, /*On fail goto*//*Label 343*/ 7077, // Rule ID 1909 //
3703
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3704
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3705
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3706
13
      // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] })
3707
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3708
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
3709
13
      // GIR_Coverage, 1909,
3710
13
      GIR_Done,
3711
13
    // Label 343: @7077
3712
13
    GIM_Try, /*On fail goto*//*Label 344*/ 7098, // Rule ID 1910 //
3713
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3714
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3715
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3716
13
      // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] })
3717
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3718
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
3719
13
      // GIR_Coverage, 1910,
3720
13
      GIR_Done,
3721
13
    // Label 344: @7098
3722
13
    GIM_Try, /*On fail goto*//*Label 345*/ 7163, // Rule ID 1931 //
3723
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3724
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3725
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3726
13
      // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3727
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3728
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3729
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3730
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3731
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3732
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3733
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3734
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3735
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3736
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3737
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3738
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3739
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3740
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3741
13
      GIR_EraseFromParent, /*InsnID*/0,
3742
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
3743
13
      // GIR_Coverage, 1931,
3744
13
      GIR_Done,
3745
13
    // Label 345: @7163
3746
13
    GIM_Try, /*On fail goto*//*Label 346*/ 7228, // Rule ID 1932 //
3747
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3748
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3749
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3750
13
      // (bitconvert:{ *:[v8f16] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3751
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3752
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3753
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3754
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3755
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3756
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3757
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3758
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3759
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3760
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3761
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3762
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3763
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3764
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3765
13
      GIR_EraseFromParent, /*InsnID*/0,
3766
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
3767
13
      // GIR_Coverage, 1932,
3768
13
      GIR_Done,
3769
13
    // Label 346: @7228
3770
13
    GIM_Try, /*On fail goto*//*Label 347*/ 7293, // Rule ID 1948 //
3771
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3772
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3773
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3774
13
      // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3775
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3776
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3777
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3778
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3779
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3780
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3781
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3782
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3783
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3784
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3785
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3786
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3787
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3788
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3789
13
      GIR_EraseFromParent, /*InsnID*/0,
3790
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
3791
13
      // GIR_Coverage, 1948,
3792
13
      GIR_Done,
3793
13
    // Label 347: @7293
3794
13
    GIM_Try, /*On fail goto*//*Label 348*/ 7358, // Rule ID 1949 //
3795
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3796
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3797
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3798
13
      // (bitconvert:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3799
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3800
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3801
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3802
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3803
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3804
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3805
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3806
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3807
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3808
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3809
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3810
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3811
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3812
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3813
13
      GIR_EraseFromParent, /*InsnID*/0,
3814
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
3815
13
      // GIR_Coverage, 1949,
3816
13
      GIR_Done,
3817
13
    // Label 348: @7358
3818
13
    GIM_Try, /*On fail goto*//*Label 349*/ 7423, // Rule ID 1953 //
3819
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3820
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3821
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3822
13
      // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3823
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3824
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3825
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3826
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3827
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3828
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3829
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3830
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3831
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3832
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3833
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3834
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3835
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3836
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3837
13
      GIR_EraseFromParent, /*InsnID*/0,
3838
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
3839
13
      // GIR_Coverage, 1953,
3840
13
      GIR_Done,
3841
13
    // Label 349: @7423
3842
13
    GIM_Try, /*On fail goto*//*Label 350*/ 7488, // Rule ID 1954 //
3843
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3844
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3845
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3846
13
      // (bitconvert:{ *:[v8f16] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3847
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3848
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3849
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3850
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3851
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3852
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3853
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3854
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3855
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3856
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3857
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3858
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3859
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3860
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3861
13
      GIR_EraseFromParent, /*InsnID*/0,
3862
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
3863
13
      // GIR_Coverage, 1954,
3864
13
      GIR_Done,
3865
13
    // Label 350: @7488
3866
13
    GIM_Try, /*On fail goto*//*Label 351*/ 7553, // Rule ID 1958 //
3867
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3868
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3869
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3870
13
      // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3871
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3872
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3873
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3874
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3875
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3876
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3877
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3878
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3879
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3880
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3881
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3882
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3883
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3884
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3885
13
      GIR_EraseFromParent, /*InsnID*/0,
3886
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
3887
13
      // GIR_Coverage, 1958,
3888
13
      GIR_Done,
3889
13
    // Label 351: @7553
3890
13
    GIM_Try, /*On fail goto*//*Label 352*/ 7618, // Rule ID 1959 //
3891
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3892
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3893
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3894
13
      // (bitconvert:{ *:[v8f16] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3895
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3896
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3897
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3898
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3899
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3900
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3901
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3902
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3903
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3904
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3905
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3906
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3907
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3908
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3909
13
      GIR_EraseFromParent, /*InsnID*/0,
3910
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
3911
13
      // GIR_Coverage, 1959,
3912
13
      GIR_Done,
3913
13
    // Label 352: @7618
3914
13
    GIM_Try, /*On fail goto*//*Label 353*/ 7683, // Rule ID 1963 //
3915
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3916
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3917
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3918
13
      // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3919
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3920
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3921
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3922
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3923
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3924
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3925
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3926
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3927
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3928
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3929
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3930
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3931
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3932
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3933
13
      GIR_EraseFromParent, /*InsnID*/0,
3934
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
3935
13
      // GIR_Coverage, 1963,
3936
13
      GIR_Done,
3937
13
    // Label 353: @7683
3938
13
    GIM_Try, /*On fail goto*//*Label 354*/ 7748, // Rule ID 1964 //
3939
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3940
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3941
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3942
13
      // (bitconvert:{ *:[v8f16] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3943
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3944
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3945
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3946
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3947
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3948
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3949
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3950
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3951
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3952
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3953
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3954
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3955
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3956
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3957
13
      GIR_EraseFromParent, /*InsnID*/0,
3958
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
3959
13
      // GIR_Coverage, 1964,
3960
13
      GIR_Done,
3961
13
    // Label 354: @7748
3962
13
    GIM_Reject,
3963
13
    // Label 273: @7749
3964
13
    GIM_Try, /*On fail goto*//*Label 355*/ 7770, // Rule ID 1900 //
3965
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3966
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3967
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
3968
13
      // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] })
3969
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3970
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66,
3971
13
      // GIR_Coverage, 1900,
3972
13
      GIR_Done,
3973
13
    // Label 355: @7770
3974
13
    GIM_Try, /*On fail goto*//*Label 356*/ 7791, // Rule ID 1901 //
3975
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3976
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3977
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
3978
13
      // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] })
3979
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3980
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66,
3981
13
      // GIR_Coverage, 1901,
3982
13
      GIR_Done,
3983
13
    // Label 356: @7791
3984
13
    GIM_Try, /*On fail goto*//*Label 357*/ 7812, // Rule ID 1902 //
3985
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3986
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3987
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
3988
13
      // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] })
3989
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3990
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66,
3991
13
      // GIR_Coverage, 1902,
3992
13
      GIR_Done,
3993
13
    // Label 357: @7812
3994
13
    GIM_Try, /*On fail goto*//*Label 358*/ 7833, // Rule ID 1903 //
3995
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3996
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3997
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
3998
13
      // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] })
3999
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4000
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66,
4001
13
      // GIR_Coverage, 1903,
4002
13
      GIR_Done,
4003
13
    // Label 358: @7833
4004
13
    GIM_Try, /*On fail goto*//*Label 359*/ 7854, // Rule ID 1904 //
4005
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4006
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4007
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4008
13
      // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] })
4009
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4010
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66,
4011
13
      // GIR_Coverage, 1904,
4012
13
      GIR_Done,
4013
13
    // Label 359: @7854
4014
13
    GIM_Try, /*On fail goto*//*Label 360*/ 7875, // Rule ID 1905 //
4015
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4016
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4017
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4018
13
      // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] })
4019
13
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4020
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66,
4021
13
      // GIR_Coverage, 1905,
4022
13
      GIR_Done,
4023
13
    // Label 360: @7875
4024
13
    GIM_Try, /*On fail goto*//*Label 361*/ 7940, // Rule ID 1937 //
4025
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4026
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4027
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4028
13
      // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4029
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4030
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4031
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4032
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4033
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4034
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4035
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4036
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4037
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4038
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4039
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4040
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4041
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4042
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4043
13
      GIR_EraseFromParent, /*InsnID*/0,
4044
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66,
4045
13
      // GIR_Coverage, 1937,
4046
13
      GIR_Done,
4047
13
    // Label 361: @7940
4048
13
    GIM_Try, /*On fail goto*//*Label 362*/ 8005, // Rule ID 1942 //
4049
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4050
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4051
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4052
13
      // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4053
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4054
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4055
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4056
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4057
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4058
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4059
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4060
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4061
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4062
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4063
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4064
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4065
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4066
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4067
13
      GIR_EraseFromParent, /*InsnID*/0,
4068
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66,
4069
13
      // GIR_Coverage, 1942,
4070
13
      GIR_Done,
4071
13
    // Label 362: @8005
4072
13
    GIM_Try, /*On fail goto*//*Label 363*/ 8070, // Rule ID 1947 //
4073
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4074
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4075
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4076
13
      // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
4077
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4078
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4079
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4080
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4081
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4082
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4083
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4084
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4085
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4086
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
4087
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4088
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4089
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4090
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4091
13
      GIR_EraseFromParent, /*InsnID*/0,
4092
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66,
4093
13
      // GIR_Coverage, 1947,
4094
13
      GIR_Done,
4095
13
    // Label 363: @8070
4096
13
    GIM_Try, /*On fail goto*//*Label 364*/ 8135, // Rule ID 1952 //
4097
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4098
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4099
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4100
13
      // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
4101
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4102
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4103
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4104
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4105
13
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4106
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4107
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4108
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4109
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4110
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
4111
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4112
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4113
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4114
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4115
13
      GIR_EraseFromParent, /*InsnID*/0,
4116
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66,
4117
13
      // GIR_Coverage, 1952,
4118
13
      GIR_Done,
4119
13
    // Label 364: @8135
4120
13
    GIM_Try, /*On fail goto*//*Label 365*/ 8235, // Rule ID 1957 //
4121
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4122
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4123
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4124
13
      // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4125
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4126
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4127
13
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4128
13
      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4129
13
      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
4130
13
      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
4131
13
      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4132
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
4133
13
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
4134
13
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
4135
13
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
4136
13
      GIR_AddImm, /*InsnID*/3, /*Imm*/27,
4137
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4138
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4139
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4140
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
4141
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4142
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
4143
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4144
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4145
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4146
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4147
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4148
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4149
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4150
13
      GIR_EraseFromParent, /*InsnID*/0,
4151
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66,
4152
13
      // GIR_Coverage, 1957,
4153
13
      GIR_Done,
4154
13
    // Label 365: @8235
4155
13
    GIM_Try, /*On fail goto*//*Label 366*/ 8335, // Rule ID 1962 //
4156
13
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4157
13
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4158
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4159
13
      // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4160
13
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4161
13
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4162
13
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4163
13
      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4164
13
      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
4165
13
      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
4166
13
      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4167
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
4168
13
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
4169
13
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
4170
13
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
4171
13
      GIR_AddImm, /*InsnID*/3, /*Imm*/27,
4172
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4173
13
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4174
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4175
13
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
4176
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4177
13
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
4178
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4179
13
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4180
13
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4181
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4182
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4183
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4184
13
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4185
13
      GIR_EraseFromParent, /*InsnID*/0,
4186
13
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66,
4187
13
      // GIR_Coverage, 1962,
4188
13
      GIR_Done,
4189
13
    // Label 366: @8335
4190
13
    GIM_Reject,
4191
13
    // Label 274: @8336
4192
13
    GIM_Reject,
4193
13
    // Label 11: @8337
4194
13
    GIM_Try, /*On fail goto*//*Label 367*/ 8402, // Rule ID 1885 //
4195
13
      GIM_CheckFeatures, GIFBS_HasDSP,
4196
13
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4197
13
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
4198
13
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
4199
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4200
13
      // MIs[0] Operand 1
4201
13
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4202
13
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4203
13
      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4204
13
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4205
13
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4206
13
      GIM_CheckIsSafeToFold, /*InsnID*/1,
4207
13
      // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LWX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4208
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LWX,
4209
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4210
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4211
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4212
13
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
4213
13
      GIR_EraseFromParent, /*InsnID*/0,
4214
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4215
13
      // GIR_Coverage, 1885,
4216
13
      GIR_Done,
4217
13
    // Label 367: @8402
4218
13
    GIM_Reject,
4219
13
    // Label 12: @8403
4220
13
    GIM_Try, /*On fail goto*//*Label 368*/ 8468, // Rule ID 1884 //
4221
13
      GIM_CheckFeatures, GIFBS_HasDSP,
4222
13
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4223
13
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
4224
13
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
4225
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4226
13
      // MIs[0] Operand 1
4227
13
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4228
13
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4229
13
      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4230
13
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4231
13
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4232
13
      GIM_CheckIsSafeToFold, /*InsnID*/1,
4233
13
      // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LHX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4234
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LHX,
4235
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4236
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4237
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4238
13
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
4239
13
      GIR_EraseFromParent, /*InsnID*/0,
4240
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4241
13
      // GIR_Coverage, 1884,
4242
13
      GIR_Done,
4243
13
    // Label 368: @8468
4244
13
    GIM_Reject,
4245
13
    // Label 13: @8469
4246
13
    GIM_Try, /*On fail goto*//*Label 369*/ 8534, // Rule ID 1883 //
4247
13
      GIM_CheckFeatures, GIFBS_HasDSP,
4248
13
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4249
13
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
4250
13
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
4251
13
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4252
13
      // MIs[0] Operand 1
4253
13
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4254
13
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4255
13
      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4256
13
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4257
13
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4258
13
      GIM_CheckIsSafeToFold, /*InsnID*/1,
4259
13
      // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (LBUX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4260
13
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LBUX,
4261
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4262
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4263
13
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4264
13
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
4265
13
      GIR_EraseFromParent, /*InsnID*/0,
4266
13
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4267
13
      // GIR_Coverage, 1883,
4268
13
      GIR_Done,
4269
13
    // Label 369: @8534
4270
13
    GIM_Reject,
4271
13
    // Label 14: @8535
4272
13
    GIM_Try, /*On fail goto*//*Label 370*/ 10729,
4273
13
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
4274
13
      GIM_Try, /*On fail goto*//*Label 371*/ 8587, // Rule ID 400 //
4275
13
        GIM_CheckFeatures, GIFBS_HasDSP,
4276
13
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
4277
13
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
4278
13
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4279
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4280
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4281
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4282
13
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt8,
4283
13
        // MIs[1] Operand 1
4284
13
        // No operand predicates
4285
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4286
13
        // (intrinsic_wo_chain:{ *:[v4i8] } 3471:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm)  =>  (REPL_QB:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
4287
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_QB,
4288
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4289
13
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4290
13
        GIR_EraseFromParent, /*InsnID*/0,
4291
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4292
13
        // GIR_Coverage, 400,
4293
13
        GIR_Done,
4294
13
      // Label 371: @8587
4295
13
      GIM_Try, /*On fail goto*//*Label 372*/ 8634, // Rule ID 401 //
4296
13
        GIM_CheckFeatures, GIFBS_HasDSP,
4297
13
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
4298
13
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4299
13
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4300
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4301
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4302
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4303
13
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExt10,
4304
13
        // MIs[1] Operand 1
4305
13
        // No operand predicates
4306
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4307
13
        // (intrinsic_wo_chain:{ *:[v2i16] } 3470:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm)  =>  (REPL_PH:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
4308
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_PH,
4309
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4310
13
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4311
13
        GIR_EraseFromParent, /*InsnID*/0,
4312
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4313
13
        // GIR_Coverage, 401,
4314
13
        GIR_Done,
4315
13
      // Label 372: @8634
4316
13
      GIM_Try, /*On fail goto*//*Label 373*/ 8681, // Rule ID 1245 //
4317
13
        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
4318
13
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
4319
13
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4320
13
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4321
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4322
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4323
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4324
13
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExt10,
4325
13
        // MIs[1] Operand 1
4326
13
        // No operand predicates
4327
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4328
13
        // (intrinsic_wo_chain:{ *:[v2i16] } 3470:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm)  =>  (REPL_PH_MM:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
4329
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_PH_MM,
4330
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4331
13
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4332
13
        GIR_EraseFromParent, /*InsnID*/0,
4333
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4334
13
        // GIR_Coverage, 1245,
4335
13
        GIR_Done,
4336
13
      // Label 373: @8681
4337
13
      GIM_Try, /*On fail goto*//*Label 374*/ 8728, // Rule ID 1246 //
4338
13
        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
4339
13
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
4340
13
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
4341
13
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4342
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4343
13
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4344
13
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4345
13
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt8,
4346
13
        // MIs[1] Operand 1
4347
13
        // No operand predicates
4348
13
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4349
13
        // (intrinsic_wo_chain:{ *:[v4i8] } 3471:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm)  =>  (REPL_QB_MM:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
4350
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_QB_MM,
4351
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
4352
13
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4353
13
        GIR_EraseFromParent, /*InsnID*/0,
4354
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4355
13
        // GIR_Coverage, 1246,
4356
13
        GIR_Done,
4357
13
      // Label 374: @8728
4358
13
      GIM_Try, /*On fail goto*//*Label 375*/ 8768, // Rule ID 334 //
4359
13
        GIM_CheckFeatures, GIFBS_HasDSP,
4360
13
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_raddu_w_qb,
4361
13
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4362
13
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4363
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4364
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4365
13
        // (intrinsic_wo_chain:{ *:[i32] } 3468:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (RADDU_W_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
4366
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RADDU_W_QB,
4367
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4368
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
4369
13
        GIR_EraseFromParent, /*InsnID*/0,
4370
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4371
13
        // GIR_Coverage, 334,
4372
13
        GIR_Done,
4373
13
      // Label 375: @8768
4374
13
      GIM_Try, /*On fail goto*//*Label 376*/ 8808, // Rule ID 341 //
4375
13
        GIM_CheckFeatures, GIFBS_HasDSP,
4376
13
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phl,
4377
13
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4378
13
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
4379
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4380
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4381
13
        // (intrinsic_wo_chain:{ *:[i32] } 3450:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECEQ_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
4382
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHL,
4383
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4384
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4385
13
        GIR_EraseFromParent, /*InsnID*/0,
4386
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4387
13
        // GIR_Coverage, 341,
4388
13
        GIR_Done,
4389
13
      // Label 376: @8808
4390
13
      GIM_Try, /*On fail goto*//*Label 377*/ 8848, // Rule ID 342 //
4391
13
        GIM_CheckFeatures, GIFBS_HasDSP,
4392
13
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phr,
4393
13
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4394
13
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
4395
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4396
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4397
13
        // (intrinsic_wo_chain:{ *:[i32] } 3451:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECEQ_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
4398
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHR,
4399
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4400
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4401
13
        GIR_EraseFromParent, /*InsnID*/0,
4402
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4403
13
        // GIR_Coverage, 342,
4404
13
        GIR_Done,
4405
13
      // Label 377: @8848
4406
13
      GIM_Try, /*On fail goto*//*Label 378*/ 8888, // Rule ID 343 //
4407
13
        GIM_CheckFeatures, GIFBS_HasDSP,
4408
13
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbl,
4409
13
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4410
13
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4411
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4412
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4413
13
        // (intrinsic_wo_chain:{ *:[v2i16] } 3452:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4414
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBL,
4415
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4416
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4417
13
        GIR_EraseFromParent, /*InsnID*/0,
4418
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4419
13
        // GIR_Coverage, 343,
4420
13
        GIR_Done,
4421
13
      // Label 378: @8888
4422
13
      GIM_Try, /*On fail goto*//*Label 379*/ 8928, // Rule ID 344 //
4423
13
        GIM_CheckFeatures, GIFBS_HasDSP,
4424
13
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbr,
4425
13
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4426
13
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4427
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4428
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4429
13
        // (intrinsic_wo_chain:{ *:[v2i16] } 3454:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4430
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBR,
4431
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4432
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4433
13
        GIR_EraseFromParent, /*InsnID*/0,
4434
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4435
13
        // GIR_Coverage, 344,
4436
13
        GIR_Done,
4437
13
      // Label 379: @8928
4438
13
      GIM_Try, /*On fail goto*//*Label 380*/ 8968, // Rule ID 345 //
4439
13
        GIM_CheckFeatures, GIFBS_HasDSP,
4440
13
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbla,
4441
13
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4442
13
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4443
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4444
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4445
13
        // (intrinsic_wo_chain:{ *:[v2i16] } 3453:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4446
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBLA,
4447
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4448
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4449
13
        GIR_EraseFromParent, /*InsnID*/0,
4450
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4451
13
        // GIR_Coverage, 345,
4452
13
        GIR_Done,
4453
13
      // Label 380: @8968
4454
13
      GIM_Try, /*On fail goto*//*Label 381*/ 9008, // Rule ID 346 //
4455
13
        GIM_CheckFeatures, GIFBS_HasDSP,
4456
13
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbra,
4457
13
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4458
13
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4459
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4460
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4461
13
        // (intrinsic_wo_chain:{ *:[v2i16] } 3455:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4462
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBRA,
4463
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4464
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4465
13
        GIR_EraseFromParent, /*InsnID*/0,
4466
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4467
13
        // GIR_Coverage, 346,
4468
13
        GIR_Done,
4469
13
      // Label 381: @9008
4470
13
      GIM_Try, /*On fail goto*//*Label 382*/ 9048, // Rule ID 347 //
4471
13
        GIM_CheckFeatures, GIFBS_HasDSP,
4472
13
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbl,
4473
13
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4474
13
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4475
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4476
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4477
13
        // (intrinsic_wo_chain:{ *:[v2i16] } 3456:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4478
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBL,
4479
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4480
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4481
13
        GIR_EraseFromParent, /*InsnID*/0,
4482
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4483
13
        // GIR_Coverage, 347,
4484
13
        GIR_Done,
4485
13
      // Label 382: @9048
4486
13
      GIM_Try, /*On fail goto*//*Label 383*/ 9088, // Rule ID 348 //
4487
13
        GIM_CheckFeatures, GIFBS_HasDSP,
4488
13
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbr,
4489
13
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4490
13
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4491
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4492
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4493
13
        // (intrinsic_wo_chain:{ *:[v2i16] } 3458:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4494
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBR,
4495
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4496
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4497
13
        GIR_EraseFromParent, /*InsnID*/0,
4498
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4499
13
        // GIR_Coverage, 348,
4500
13
        GIR_Done,
4501
13
      // Label 383: @9088
4502
13
      GIM_Try, /*On fail goto*//*Label 384*/ 9128, // Rule ID 349 //
4503
13
        GIM_CheckFeatures, GIFBS_HasDSP,
4504
13
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbla,
4505
13
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4506
13
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4507
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4508
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4509
13
        // (intrinsic_wo_chain:{ *:[v2i16] } 3457:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4510
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBLA,
4511
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4512
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4513
13
        GIR_EraseFromParent, /*InsnID*/0,
4514
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4515
13
        // GIR_Coverage, 349,
4516
13
        GIR_Done,
4517
13
      // Label 384: @9128
4518
13
      GIM_Try, /*On fail goto*//*Label 385*/ 9168, // Rule ID 350 //
4519
13
        GIM_CheckFeatures, GIFBS_HasDSP,
4520
13
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbra,
4521
13
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4522
13
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4523
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4524
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4525
13
        // (intrinsic_wo_chain:{ *:[v2i16] } 3459:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4526
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBRA,
4527
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4528
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4529
13
        GIR_EraseFromParent, /*InsnID*/0,
4530
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4531
13
        // GIR_Coverage, 350,
4532
13
        GIR_Done,
4533
13
      // Label 385: @9168
4534
13
      GIM_Try, /*On fail goto*//*Label 386*/ 9208, // Rule ID 398 //
4535
13
        GIM_CheckFeatures, GIFBS_HasDSP,
4536
13
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_bitrev,
4537
13
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4538
13
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4539
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4540
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
4541
13
        // (intrinsic_wo_chain:{ *:[i32] } 3026:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (BITREV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
4542
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BITREV,
4543
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4544
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4545
13
        GIR_EraseFromParent, /*InsnID*/0,
4546
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4547
13
        // GIR_Coverage, 398,
4548
13
        GIR_Done,
4549
13
      // Label 386: @9208
4550
13
      GIM_Try, /*On fail goto*//*Label 387*/ 9248, // Rule ID 402 //
4551
13
        GIM_CheckFeatures, GIFBS_HasDSP,
4552
13
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
4553
13
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
4554
13
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4555
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4556
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
4557
13
        // (intrinsic_wo_chain:{ *:[v4i8] } 3471:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (REPLV_QB:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rt)
4558
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_QB,
4559
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4560
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4561
13
        GIR_EraseFromParent, /*InsnID*/0,
4562
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4563
13
        // GIR_Coverage, 402,
4564
13
        GIR_Done,
4565
13
      // Label 387: @9248
4566
13
      GIM_Try, /*On fail goto*//*Label 388*/ 9288, // Rule ID 403 //
4567
13
        GIM_CheckFeatures, GIFBS_HasDSP,
4568
13
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
4569
13
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4570
13
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4571
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4572
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
4573
13
        // (intrinsic_wo_chain:{ *:[v2i16] } 3470:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (REPLV_PH:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rt)
4574
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_PH,
4575
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4576
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4577
13
        GIR_EraseFromParent, /*InsnID*/0,
4578
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4579
13
        // GIR_Coverage, 403,
4580
13
        GIR_Done,
4581
13
      // Label 388: @9288
4582
13
      GIM_Try, /*On fail goto*//*Label 389*/ 9328, // Rule ID 648 //
4583
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4584
13
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fclass_w,
4585
13
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4586
13
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4587
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4588
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4589
13
        // (intrinsic_wo_chain:{ *:[v4i32] } 3178:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FCLASS_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
4590
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCLASS_W,
4591
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4592
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4593
13
        GIR_EraseFromParent, /*InsnID*/0,
4594
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4595
13
        // GIR_Coverage, 648,
4596
13
        GIR_Done,
4597
13
      // Label 389: @9328
4598
13
      GIM_Try, /*On fail goto*//*Label 390*/ 9368, // Rule ID 649 //
4599
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4600
13
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fclass_d,
4601
13
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4602
13
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
4603
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4604
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
4605
13
        // (intrinsic_wo_chain:{ *:[v2i64] } 3177:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FCLASS_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
4606
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCLASS_D,
4607
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4608
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4609
13
        GIR_EraseFromParent, /*InsnID*/0,
4610
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4611
13
        // GIR_Coverage, 649,
4612
13
        GIR_Done,
4613
13
      // Label 390: @9368
4614
13
      GIM_Try, /*On fail goto*//*Label 391*/ 9408, // Rule ID 672 //
4615
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4616
13
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupl_w,
4617
13
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4618
13
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4619
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4620
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
4621
13
        // (intrinsic_wo_chain:{ *:[v4f32] } 3204:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws)  =>  (FEXUPL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
4622
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPL_W,
4623
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4624
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4625
13
        GIR_EraseFromParent, /*InsnID*/0,
4626
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4627
13
        // GIR_Coverage, 672,
4628
13
        GIR_Done,
4629
13
      // Label 391: @9408
4630
13
      GIM_Try, /*On fail goto*//*Label 392*/ 9448, // Rule ID 673 //
4631
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4632
13
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupl_d,
4633
13
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4634
13
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4635
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4636
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4637
13
        // (intrinsic_wo_chain:{ *:[v2f64] } 3203:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FEXUPL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
4638
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPL_D,
4639
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4640
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4641
13
        GIR_EraseFromParent, /*InsnID*/0,
4642
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4643
13
        // GIR_Coverage, 673,
4644
13
        GIR_Done,
4645
13
      // Label 392: @9448
4646
13
      GIM_Try, /*On fail goto*//*Label 393*/ 9488, // Rule ID 674 //
4647
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4648
13
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupr_w,
4649
13
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4650
13
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4651
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4652
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
4653
13
        // (intrinsic_wo_chain:{ *:[v4f32] } 3206:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws)  =>  (FEXUPR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
4654
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPR_W,
4655
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4656
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4657
13
        GIR_EraseFromParent, /*InsnID*/0,
4658
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4659
13
        // GIR_Coverage, 674,
4660
13
        GIR_Done,
4661
13
      // Label 393: @9488
4662
13
      GIM_Try, /*On fail goto*//*Label 394*/ 9528, // Rule ID 675 //
4663
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4664
13
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupr_d,
4665
13
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4666
13
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4667
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4668
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4669
13
        // (intrinsic_wo_chain:{ *:[v2f64] } 3205:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FEXUPR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
4670
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPR_D,
4671
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4672
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4673
13
        GIR_EraseFromParent, /*InsnID*/0,
4674
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4675
13
        // GIR_Coverage, 675,
4676
13
        GIR_Done,
4677
13
      // Label 394: @9528
4678
13
      GIM_Try, /*On fail goto*//*Label 395*/ 9568, // Rule ID 680 //
4679
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4680
13
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffql_w,
4681
13
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4682
13
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4683
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4684
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
4685
13
        // (intrinsic_wo_chain:{ *:[v4f32] } 3212:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws)  =>  (FFQL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
4686
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQL_W,
4687
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4688
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4689
13
        GIR_EraseFromParent, /*InsnID*/0,
4690
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4691
13
        // GIR_Coverage, 680,
4692
13
        GIR_Done,
4693
13
      // Label 395: @9568
4694
13
      GIM_Try, /*On fail goto*//*Label 396*/ 9608, // Rule ID 681 //
4695
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4696
13
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffql_d,
4697
13
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4698
13
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4699
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4700
13
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4701
13
        // (intrinsic_wo_chain:{ *:[v2f64] } 3211:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws)  =>  (FFQL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
4702
13
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQL_D,
4703
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4704
13
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4705
13
        GIR_EraseFromParent, /*InsnID*/0,
4706
13
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4707
13
        // GIR_Coverage, 681,
4708
13
        GIR_Done,
4709
13
      // Label 396: @9608
4710
13
      GIM_Try, /*On fail goto*//*Label 397*/ 9648, // Rule ID 682 //
4711
13
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4712
13
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffqr_w,
4713
13
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4714