Coverage Report

Created: 2018-09-23 22:08

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Mips/MipsGenGlobalISel.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Global Instruction Selector for the Mips target                            *|
4
|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10
const unsigned MAX_SUBTARGET_PREDICATES = 41;
11
using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
12
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
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#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15
  mutable MatcherState State;
16
  typedef ComplexRendererFns(MipsInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17
  typedef void(MipsInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const;
18
  const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
19
  static MipsInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20
  static MipsInstructionSelector::CustomRendererFn CustomRenderers[];
21
  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22
  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23
  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24
  const int64_t *getMatchTable() const override;
25
  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
26
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
27
28
#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
29
, State(0),
30
ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
31
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
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#ifdef GET_GLOBALISEL_IMPL
34
// Bits for subtarget features that participate in instruction matching.
35
enum SubtargetFeatureBits : uint8_t {
36
  Feature_HasMips2Bit = 7,
37
  Feature_HasMips3Bit = 16,
38
  Feature_HasMips4_32Bit = 26,
39
  Feature_NotMips4_32Bit = 27,
40
  Feature_HasMips4_32r2Bit = 17,
41
  Feature_HasMips32Bit = 3,
42
  Feature_HasMips32r2Bit = 6,
43
  Feature_HasMips32r6Bit = 28,
44
  Feature_NotMips32r6Bit = 4,
45
  Feature_IsGP64bitBit = 21,
46
  Feature_IsPTR64bitBit = 23,
47
  Feature_HasMips64Bit = 24,
48
  Feature_HasMips64r2Bit = 22,
49
  Feature_HasMips64r6Bit = 29,
50
  Feature_NotMips64r6Bit = 5,
51
  Feature_InMips16ModeBit = 30,
52
  Feature_NotInMips16ModeBit = 0,
53
  Feature_HasCnMipsBit = 25,
54
  Feature_NotCnMipsBit = 8,
55
  Feature_IsN64Bit = 37,
56
  Feature_RelocNotPICBit = 9,
57
  Feature_RelocPICBit = 36,
58
  Feature_NoNaNsFPMathBit = 20,
59
  Feature_HasStdEncBit = 1,
60
  Feature_NotDSPBit = 11,
61
  Feature_InMicroMipsBit = 34,
62
  Feature_NotInMicroMipsBit = 2,
63
  Feature_IsLEBit = 39,
64
  Feature_IsBEBit = 40,
65
  Feature_IsNotNaClBit = 18,
66
  Feature_HasEVABit = 35,
67
  Feature_HasMSABit = 33,
68
  Feature_HasMadd4Bit = 19,
69
  Feature_UseIndirectJumpsHazardBit = 12,
70
  Feature_NoIndirectJumpGuardsBit = 10,
71
  Feature_AllowFPOpFusionBit = 38,
72
  Feature_IsFP64bitBit = 15,
73
  Feature_NotFP64bitBit = 14,
74
  Feature_IsNotSoftFloatBit = 13,
75
  Feature_HasDSPBit = 31,
76
  Feature_HasDSPR2Bit = 32,
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};
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PredicateBitset MipsInstructionSelector::
80
10.1k
computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const {
81
10.1k
  PredicateBitset Features;
82
10.1k
  if (Subtarget->hasMips2())
83
10.1k
    Features[Feature_HasMips2Bit] = 1;
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10.1k
  if (Subtarget->hasMips3())
85
3.49k
    Features[Feature_HasMips3Bit] = 1;
86
10.1k
  if (Subtarget->hasMips4_32())
87
9.87k
    Features[Feature_HasMips4_32Bit] = 1;
88
10.1k
  if (!Subtarget->hasMips4_32())
89
271
    Features[Feature_NotMips4_32Bit] = 1;
90
10.1k
  if (Subtarget->hasMips4_32r2())
91
5.83k
    Features[Feature_HasMips4_32r2Bit] = 1;
92
10.1k
  if (Subtarget->hasMips32())
93
9.53k
    Features[Feature_HasMips32Bit] = 1;
94
10.1k
  if (Subtarget->hasMips32r2())
95
4.10k
    Features[Feature_HasMips32r2Bit] = 1;
96
10.1k
  if (Subtarget->hasMips32r6())
97
1.25k
    Features[Feature_HasMips32r6Bit] = 1;
98
10.1k
  if (!Subtarget->hasMips32r6())
99
8.89k
    Features[Feature_NotMips32r6Bit] = 1;
100
10.1k
  if (Subtarget->isGP64bit())
101
3.49k
    Features[Feature_IsGP64bitBit] = 1;
102
10.1k
  if (Subtarget->isABI_N64())
103
3.02k
    Features[Feature_IsPTR64bitBit] = 1;
104
10.1k
  if (Subtarget->hasMips64())
105
3.00k
    Features[Feature_HasMips64Bit] = 1;
106
10.1k
  if (Subtarget->hasMips64r2())
107
1.62k
    Features[Feature_HasMips64r2Bit] = 1;
108
10.1k
  if (Subtarget->hasMips64r6())
109
431
    Features[Feature_HasMips64r6Bit] = 1;
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10.1k
  if (!Subtarget->hasMips64r6())
111
9.71k
    Features[Feature_NotMips64r6Bit] = 1;
112
10.1k
  if (Subtarget->inMips16Mode())
113
2.63k
    Features[Feature_InMips16ModeBit] = 1;
114
10.1k
  if (!Subtarget->inMips16Mode())
115
7.51k
    Features[Feature_NotInMips16ModeBit] = 1;
116
10.1k
  if (Subtarget->hasCnMips())
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20
    Features[Feature_HasCnMipsBit] = 1;
118
10.1k
  if (!Subtarget->hasCnMips())
119
10.1k
    Features[Feature_NotCnMipsBit] = 1;
120
10.1k
  if (Subtarget->isABI_N64())
121
3.02k
    Features[Feature_IsN64Bit] = 1;
122
10.1k
  if (!TM.isPositionIndependent())
123
6.10k
    Features[Feature_RelocNotPICBit] = 1;
124
10.1k
  if (TM.isPositionIndependent())
125
4.04k
    Features[Feature_RelocPICBit] = 1;
126
10.1k
  if (TM.Options.NoNaNsFPMath)
127
130
    Features[Feature_NoNaNsFPMathBit] = 1;
128
10.1k
  if (Subtarget->hasStandardEncoding())
129
6.82k
    Features[Feature_HasStdEncBit] = 1;
130
10.1k
  if (!Subtarget->hasDSP())
131
10.0k
    Features[Feature_NotDSPBit] = 1;
132
10.1k
  if (Subtarget->inMicroMipsMode())
133
690
    Features[Feature_InMicroMipsBit] = 1;
134
10.1k
  if (!Subtarget->inMicroMipsMode())
135
9.45k
    Features[Feature_NotInMicroMipsBit] = 1;
136
10.1k
  if (Subtarget->isLittle())
137
4.96k
    Features[Feature_IsLEBit] = 1;
138
10.1k
  if (!Subtarget->isLittle())
139
5.17k
    Features[Feature_IsBEBit] = 1;
140
10.1k
  if (!Subtarget->isTargetNaCl())
141
10.1k
    Features[Feature_IsNotNaClBit] = 1;
142
10.1k
  if (Subtarget->hasEVA())
143
10
    Features[Feature_HasEVABit] = 1;
144
10.1k
  if (Subtarget->hasMSA())
145
947
    Features[Feature_HasMSABit] = 1;
146
10.1k
  if (!Subtarget->disableMadd4())
147
10.1k
    Features[Feature_HasMadd4Bit] = 1;
148
10.1k
  if (Subtarget->useIndirectJumpsHazard())
149
143
    Features[Feature_UseIndirectJumpsHazardBit] = 1;
150
10.1k
  if (!Subtarget->useIndirectJumpsHazard())
151
10.0k
    Features[Feature_NoIndirectJumpGuardsBit] = 1;
152
10.1k
  if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast)
153
5
    Features[Feature_AllowFPOpFusionBit] = 1;
154
10.1k
  if (Subtarget->isFP64bit())
155
5.24k
    Features[Feature_IsFP64bitBit] = 1;
156
10.1k
  if (!Subtarget->isFP64bit())
157
4.90k
    Features[Feature_NotFP64bitBit] = 1;
158
10.1k
  if (!Subtarget->useSoftFloat())
159
9.83k
    Features[Feature_IsNotSoftFloatBit] = 1;
160
10.1k
  if (Subtarget->hasDSP())
161
102
    Features[Feature_HasDSPBit] = 1;
162
10.1k
  if (Subtarget->hasDSPR2())
163
26
    Features[Feature_HasDSPR2Bit] = 1;
164
10.1k
  return Features;
165
10.1k
}
166
167
PredicateBitset MipsInstructionSelector::
168
119
computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget, const MachineFunction *MF) const {
169
119
  PredicateBitset Features;
170
119
  return Features;
171
119
}
172
173
// LLT Objects.
174
enum {
175
  GILLT_s16,
176
  GILLT_s32,
177
  GILLT_s64,
178
  GILLT_v2s16,
179
  GILLT_v2s64,
180
  GILLT_v4s8,
181
  GILLT_v4s32,
182
  GILLT_v8s16,
183
  GILLT_v16s8,
184
};
185
const static size_t NumTypeObjects = 9;
186
const static LLT TypeObjects[] = {
187
  LLT::scalar(16),
188
  LLT::scalar(32),
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  LLT::scalar(64),
190
  LLT::vector(2, 16),
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  LLT::vector(2, 64),
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  LLT::vector(4, 8),
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  LLT::vector(4, 32),
194
  LLT::vector(8, 16),
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  LLT::vector(16, 8),
196
};
197
198
// Feature bitsets.
199
enum {
200
  GIFBS_Invalid,
201
  GIFBS_HasCnMips,
202
  GIFBS_HasDSP,
203
  GIFBS_HasDSPR2,
204
  GIFBS_HasMSA,
205
  GIFBS_InMicroMips,
206
  GIFBS_InMips16Mode,
207
  GIFBS_IsFP64bit,
208
  GIFBS_NotFP64bit,
209
  GIFBS_HasDSP_InMicroMips,
210
  GIFBS_HasDSP_NotInMicroMips,
211
  GIFBS_HasDSPR2_InMicroMips,
212
  GIFBS_HasMSA_HasStdEnc,
213
  GIFBS_HasMSA_IsBE,
214
  GIFBS_HasMSA_IsLE,
215
  GIFBS_HasMips32r6_HasStdEnc,
216
  GIFBS_HasMips32r6_InMicroMips,
217
  GIFBS_HasMips64r2_HasStdEnc,
218
  GIFBS_HasMips64r6_HasStdEnc,
219
  GIFBS_HasStdEnc_IsNotSoftFloat,
220
  GIFBS_HasStdEnc_NotInMicroMips,
221
  GIFBS_HasStdEnc_NotMips4_32,
222
  GIFBS_InMicroMips_IsFP64bit,
223
  GIFBS_InMicroMips_IsNotSoftFloat,
224
  GIFBS_InMicroMips_NotFP64bit,
225
  GIFBS_InMicroMips_NotMips32r6,
226
  GIFBS_IsGP64bit_NotInMips16Mode,
227
  GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
228
  GIFBS_HasMSA_HasMips64_HasStdEnc,
229
  GIFBS_HasMips3_HasStdEnc_IsGP64bit,
230
  GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
231
  GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips,
232
  GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
233
  GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
234
  GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
235
  GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips,
236
  GIFBS_HasStdEnc_IsFP64bit_NotMips4_32,
237
  GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
238
  GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips,
239
  GIFBS_HasStdEnc_NotFP64bit_NotMips4_32,
240
  GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC,
241
  GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
242
  GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
243
  GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
244
  GIFBS_InMicroMips_NotMips32r6_RelocNotPIC,
245
  GIFBS_InMicroMips_NotMips32r6_RelocPIC,
246
  GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
247
  GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
248
  GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
249
  GIFBS_HasMips64_HasStdEnc_NotInMicroMips_NotMips64r6,
250
  GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips,
251
  GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
252
  GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
253
  GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
254
  GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
255
  GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotMips32r6_NotMips32r6,
256
  GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
257
  GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
258
  GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
259
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
260
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
261
  GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6_NotMips32r6,
262
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
263
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
264
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
265
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
266
};
267
const static PredicateBitset FeatureBitsets[] {
268
  {}, // GIFBS_Invalid
269
  {Feature_HasCnMipsBit, },
270
  {Feature_HasDSPBit, },
271
  {Feature_HasDSPR2Bit, },
272
  {Feature_HasMSABit, },
273
  {Feature_InMicroMipsBit, },
274
  {Feature_InMips16ModeBit, },
275
  {Feature_IsFP64bitBit, },
276
  {Feature_NotFP64bitBit, },
277
  {Feature_HasDSPBit, Feature_InMicroMipsBit, },
278
  {Feature_HasDSPBit, Feature_NotInMicroMipsBit, },
279
  {Feature_HasDSPR2Bit, Feature_InMicroMipsBit, },
280
  {Feature_HasMSABit, Feature_HasStdEncBit, },
281
  {Feature_HasMSABit, Feature_IsBEBit, },
282
  {Feature_HasMSABit, Feature_IsLEBit, },
283
  {Feature_HasMips32r6Bit, Feature_HasStdEncBit, },
284
  {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, },
285
  {Feature_HasMips64r2Bit, Feature_HasStdEncBit, },
286
  {Feature_HasMips64r6Bit, Feature_HasStdEncBit, },
287
  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },
288
  {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
289
  {Feature_HasStdEncBit, Feature_NotMips4_32Bit, },
290
  {Feature_InMicroMipsBit, Feature_IsFP64bitBit, },
291
  {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
292
  {Feature_InMicroMipsBit, Feature_NotFP64bitBit, },
293
  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },
294
  {Feature_IsGP64bitBit, Feature_NotInMips16ModeBit, },
295
  {Feature_AllowFPOpFusionBit, Feature_HasMSABit, Feature_HasStdEncBit, },
296
  {Feature_HasMSABit, Feature_HasMips64Bit, Feature_HasStdEncBit, },
297
  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, },
298
  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
299
  {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
300
  {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
301
  {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
302
  {Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
303
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, },
304
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, },
305
  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
306
  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
307
  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, },
308
  {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_RelocNotPICBit, },
309
  {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },
310
  {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, },
311
  {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, },
312
  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocNotPICBit, },
313
  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocPICBit, },
314
  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
315
  {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
316
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
317
  {Feature_HasMips64Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips64r6Bit, },
318
  {Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
319
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
320
  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
321
  {Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
322
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
323
  {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotMips32r6Bit, Feature_NotMips32r6Bit, },
324
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
325
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
326
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
327
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
328
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
329
  {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips32r6Bit, },
330
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
331
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
332
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
333
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
334
};
335
336
// ComplexPattern predicates.
337
enum {
338
  GICP_Invalid,
339
};
340
// See constructor for table contents
341
342
// PatFrag predicates.
343
enum {
344
  GIPFP_I64_Predicate_immLi16 = GIPFP_I64_Invalid + 1,
345
  GIPFP_I64_Predicate_immSExt10,
346
  GIPFP_I64_Predicate_immSExt6,
347
  GIPFP_I64_Predicate_immSExtAddiur2,
348
  GIPFP_I64_Predicate_immSExtAddius5,
349
  GIPFP_I64_Predicate_immZExt1,
350
  GIPFP_I64_Predicate_immZExt10,
351
  GIPFP_I64_Predicate_immZExt1Ptr,
352
  GIPFP_I64_Predicate_immZExt2,
353
  GIPFP_I64_Predicate_immZExt2Lsa,
354
  GIPFP_I64_Predicate_immZExt2Ptr,
355
  GIPFP_I64_Predicate_immZExt2Shift,
356
  GIPFP_I64_Predicate_immZExt3,
357
  GIPFP_I64_Predicate_immZExt3Ptr,
358
  GIPFP_I64_Predicate_immZExt4,
359
  GIPFP_I64_Predicate_immZExt4Ptr,
360
  GIPFP_I64_Predicate_immZExt5,
361
  GIPFP_I64_Predicate_immZExt5_64,
362
  GIPFP_I64_Predicate_immZExt6,
363
  GIPFP_I64_Predicate_immZExt8,
364
  GIPFP_I64_Predicate_immZExtAndi16,
365
  GIPFP_I64_Predicate_immi32Cst15,
366
  GIPFP_I64_Predicate_immi32Cst31,
367
  GIPFP_I64_Predicate_immi32Cst7,
368
};
369
10
bool MipsInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
370
10
  switch (PredicateID) {
371
10
  case GIPFP_I64_Predicate_immLi16: {
372
0
    return Imm >= -1 && Imm <= 126;
373
10
    
llvm_unreachable0
("ImmediateCode should have returned");
374
10
    
return false0
;
375
10
  }
376
10
  case GIPFP_I64_Predicate_immSExt10: {
377
0
    return isInt<10>(Imm);
378
10
    
llvm_unreachable0
("ImmediateCode should have returned");
379
10
    
return false0
;
380
10
  }
381
10
  case GIPFP_I64_Predicate_immSExt6: {
382
0
    return isInt<6>(Imm);
383
10
    
llvm_unreachable0
("ImmediateCode should have returned");
384
10
    
return false0
;
385
10
  }
386
10
  case GIPFP_I64_Predicate_immSExtAddiur2: {
387
0
    return Imm == 1 || Imm == -1 ||
388
0
                                           ((Imm % 4 == 0) &&
389
0
                                            Imm < 28 && Imm > 0);
390
10
    
llvm_unreachable0
("ImmediateCode should have returned");
391
10
    
return false0
;
392
10
  }
393
10
  case GIPFP_I64_Predicate_immSExtAddius5: {
394
0
    return Imm >= -8 && Imm <= 7;
395
10
    
llvm_unreachable0
("ImmediateCode should have returned");
396
10
    
return false0
;
397
10
  }
398
10
  case GIPFP_I64_Predicate_immZExt1: {
399
0
    return isUInt<1>(Imm);
400
10
    
llvm_unreachable0
("ImmediateCode should have returned");
401
10
    
return false0
;
402
10
  }
403
10
  case GIPFP_I64_Predicate_immZExt10: {
404
0
    return isUInt<10>(Imm);
405
10
    
llvm_unreachable0
("ImmediateCode should have returned");
406
10
    
return false0
;
407
10
  }
408
10
  case GIPFP_I64_Predicate_immZExt1Ptr: {
409
0
    return isUInt<1>(Imm);
410
10
    
llvm_unreachable0
("ImmediateCode should have returned");
411
10
    
return false0
;
412
10
  }
413
10
  case GIPFP_I64_Predicate_immZExt2: {
414
0
    return isUInt<2>(Imm);
415
10
    
llvm_unreachable0
("ImmediateCode should have returned");
416
10
    
return false0
;
417
10
  }
418
10
  case GIPFP_I64_Predicate_immZExt2Lsa: {
419
0
    return isUInt<2>(Imm - 1);
420
10
    
llvm_unreachable0
("ImmediateCode should have returned");
421
10
    
return false0
;
422
10
  }
423
10
  case GIPFP_I64_Predicate_immZExt2Ptr: {
424
0
    return isUInt<2>(Imm);
425
10
    
llvm_unreachable0
("ImmediateCode should have returned");
426
10
    
return false0
;
427
10
  }
428
10
  case GIPFP_I64_Predicate_immZExt2Shift: {
429
0
    return Imm >= 1 && Imm <= 8;
430
10
    
llvm_unreachable0
("ImmediateCode should have returned");
431
10
    
return false0
;
432
10
  }
433
10
  case GIPFP_I64_Predicate_immZExt3: {
434
0
    return isUInt<3>(Imm);
435
10
    
llvm_unreachable0
("ImmediateCode should have returned");
436
10
    
return false0
;
437
10
  }
438
10
  case GIPFP_I64_Predicate_immZExt3Ptr: {
439
0
    return isUInt<3>(Imm);
440
10
    
llvm_unreachable0
("ImmediateCode should have returned");
441
10
    
return false0
;
442
10
  }
443
10
  case GIPFP_I64_Predicate_immZExt4: {
444
0
    return isUInt<4>(Imm);
445
10
    
llvm_unreachable0
("ImmediateCode should have returned");
446
10
    
return false0
;
447
10
  }
448
10
  case GIPFP_I64_Predicate_immZExt4Ptr: {
449
0
    return isUInt<4>(Imm);
450
10
    
llvm_unreachable0
("ImmediateCode should have returned");
451
10
    
return false0
;
452
10
  }
453
10
  case GIPFP_I64_Predicate_immZExt5: {
454
10
    return Imm == (Imm & 0x1f);
455
10
    
llvm_unreachable0
("ImmediateCode should have returned");
456
10
    
return false0
;
457
10
  }
458
10
  case GIPFP_I64_Predicate_immZExt5_64: {
459
0
     return Imm == (Imm & 0x1f); 
460
10
    
llvm_unreachable0
("ImmediateCode should have returned");
461
10
    
return false0
;
462
10
  }
463
10
  case GIPFP_I64_Predicate_immZExt6: {
464
0
    return Imm == (Imm & 0x3f);
465
10
    
llvm_unreachable0
("ImmediateCode should have returned");
466
10
    
return false0
;
467
10
  }
468
10
  case GIPFP_I64_Predicate_immZExt8: {
469
0
    return isUInt<8>(Imm);
470
10
    
llvm_unreachable0
("ImmediateCode should have returned");
471
10
    
return false0
;
472
10
  }
473
10
  case GIPFP_I64_Predicate_immZExtAndi16: {
474
0
    return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
475
0
            Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
476
0
            Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
477
10
    
llvm_unreachable0
("ImmediateCode should have returned");
478
10
    
return false0
;
479
10
  }
480
10
  case GIPFP_I64_Predicate_immi32Cst15: {
481
0
    return isUInt<32>(Imm) && Imm == 15;
482
10
    
llvm_unreachable0
("ImmediateCode should have returned");
483
10
    
return false0
;
484
10
  }
485
10
  case GIPFP_I64_Predicate_immi32Cst31: {
486
0
    return isUInt<32>(Imm) && Imm == 31;
487
10
    
llvm_unreachable0
("ImmediateCode should have returned");
488
10
    
return false0
;
489
10
  }
490
10
  case GIPFP_I64_Predicate_immi32Cst7: {
491
0
    return isUInt<32>(Imm) && Imm == 7;
492
10
    
llvm_unreachable0
("ImmediateCode should have returned");
493
10
    
return false0
;
494
0
  }
495
0
  }
496
0
  llvm_unreachable("Unknown predicate");
497
0
  return false;
498
0
}
499
0
bool MipsInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
500
0
  llvm_unreachable("Unknown predicate");
501
0
  return false;
502
0
}
503
0
bool MipsInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
504
0
  llvm_unreachable("Unknown predicate");
505
0
  return false;
506
0
}
507
0
bool MipsInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
508
0
  const MachineFunction &MF = *MI.getParent()->getParent();
509
0
  const MachineRegisterInfo &MRI = MF.getRegInfo();
510
0
  (void)MRI;
511
0
  llvm_unreachable("Unknown predicate");
512
0
  return false;
513
0
}
514
515
MipsInstructionSelector::ComplexMatcherMemFn
516
MipsInstructionSelector::ComplexPredicateFns[] = {
517
  nullptr, // GICP_Invalid
518
};
519
520
// Custom renderers.
521
enum {
522
  GICR_Invalid,
523
};
524
MipsInstructionSelector::CustomRendererFn
525
MipsInstructionSelector::CustomRenderers[] = {
526
  nullptr, // GICP_Invalid
527
};
528
529
119
bool MipsInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
530
119
  MachineFunction &MF = *I.getParent()->getParent();
531
119
  MachineRegisterInfo &MRI = MF.getRegInfo();
532
119
  // FIXME: This should be computed on a per-function basis rather than per-insn.
533
119
  AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
534
119
  const PredicateBitset AvailableFeatures = getAvailableFeatures();
535
119
  NewMIVector OutMIs;
536
119
  State.MIs.clear();
537
119
  State.MIs.push_back(&I);
538
119
539
119
  if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
540
53
    return true;
541
53
  }
542
66
543
66
  return false;
544
66
}
545
546
119
const int64_t *MipsInstructionSelector::getMatchTable() const {
547
119
  constexpr static int64_t MatchTable0[] = {
548
119
    GIM_SwitchOpcode, /*MI*/0, /*[*/34, 135, /*)*//*default:*//*Label 42*/ 38274,
549
119
    /*TargetOpcode::G_ADD*//*Label 0*/ 106,
550
119
    /*TargetOpcode::G_SUB*//*Label 1*/ 1283,
551
119
    /*TargetOpcode::G_MUL*//*Label 2*/ 1895,
552
119
    /*TargetOpcode::G_SDIV*//*Label 3*/ 2271,
553
119
    /*TargetOpcode::G_UDIV*//*Label 4*/ 2492,
554
119
    /*TargetOpcode::G_SREM*//*Label 5*/ 2713,
555
119
    /*TargetOpcode::G_UREM*//*Label 6*/ 2934,
556
119
    /*TargetOpcode::G_AND*//*Label 7*/ 3155,
557
119
    /*TargetOpcode::G_OR*//*Label 8*/ 3599,
558
119
    /*TargetOpcode::G_XOR*//*Label 9*/ 3901, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
559
119
    /*TargetOpcode::G_BITCAST*//*Label 10*/ 4695, 0, 0,
560
119
    /*TargetOpcode::G_LOAD*//*Label 11*/ 8348,
561
119
    /*TargetOpcode::G_SEXTLOAD*//*Label 12*/ 8414,
562
119
    /*TargetOpcode::G_ZEXTLOAD*//*Label 13*/ 8480, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
563
119
    /*TargetOpcode::G_INTRINSIC*//*Label 14*/ 8546,
564
119
    /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 15*/ 25057, 0,
565
119
    /*TargetOpcode::G_TRUNC*//*Label 16*/ 29981,
566
119
    /*TargetOpcode::G_CONSTANT*//*Label 17*/ 30038, 0, 0, 0,
567
119
    /*TargetOpcode::G_SEXT*//*Label 18*/ 30098,
568
119
    /*TargetOpcode::G_ZEXT*//*Label 19*/ 30126,
569
119
    /*TargetOpcode::G_SHL*//*Label 20*/ 30211,
570
119
    /*TargetOpcode::G_LSHR*//*Label 21*/ 30735,
571
119
    /*TargetOpcode::G_ASHR*//*Label 22*/ 31259, 0, 0,
572
119
    /*TargetOpcode::G_SELECT*//*Label 23*/ 31740, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
573
119
    /*TargetOpcode::G_FADD*//*Label 24*/ 33194,
574
119
    /*TargetOpcode::G_FSUB*//*Label 25*/ 34073,
575
119
    /*TargetOpcode::G_FMUL*//*Label 26*/ 34649,
576
119
    /*TargetOpcode::G_FMA*//*Label 27*/ 35086,
577
119
    /*TargetOpcode::G_FDIV*//*Label 28*/ 35176, 0, 0, 0,
578
119
    /*TargetOpcode::G_FEXP2*//*Label 29*/ 35427, 0,
579
119
    /*TargetOpcode::G_FLOG2*//*Label 30*/ 35485,
580
119
    /*TargetOpcode::G_FNEG*//*Label 31*/ 35543,
581
119
    /*TargetOpcode::G_FPEXT*//*Label 32*/ 36839,
582
119
    /*TargetOpcode::G_FPTRUNC*//*Label 33*/ 36988,
583
119
    /*TargetOpcode::G_FPTOSI*//*Label 34*/ 37116,
584
119
    /*TargetOpcode::G_FPTOUI*//*Label 35*/ 37174,
585
119
    /*TargetOpcode::G_SITOFP*//*Label 36*/ 37232,
586
119
    /*TargetOpcode::G_UITOFP*//*Label 37*/ 37385, 0, 0, 0,
587
119
    /*TargetOpcode::G_BR*//*Label 38*/ 37443, 0, 0, 0, 0, 0,
588
119
    /*TargetOpcode::G_CTLZ*//*Label 39*/ 37528, 0,
589
119
    /*TargetOpcode::G_CTPOP*//*Label 40*/ 37963,
590
119
    /*TargetOpcode::G_BSWAP*//*Label 41*/ 38122,
591
119
    // Label 0: @106
592
119
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 51*/ 1282,
593
119
    /*GILLT_s32*//*Label 43*/ 120,
594
119
    /*GILLT_s64*//*Label 44*/ 469,
595
119
    /*GILLT_v2s16*//*Label 45*/ 632,
596
119
    /*GILLT_v2s64*//*Label 46*/ 659,
597
119
    /*GILLT_v4s8*//*Label 47*/ 808,
598
119
    /*GILLT_v4s32*//*Label 48*/ 835,
599
119
    /*GILLT_v8s16*//*Label 49*/ 984,
600
119
    /*GILLT_v16s8*//*Label 50*/ 1133,
601
119
    // Label 43: @120
602
119
    GIM_Try, /*On fail goto*//*Label 52*/ 468,
603
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
604
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
605
119
      GIM_Try, /*On fail goto*//*Label 53*/ 198, // Rule ID 2308 //
606
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
607
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
608
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
609
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
610
119
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
611
119
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
612
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
613
119
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
614
119
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
615
119
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
616
119
        // MIs[2] Operand 1
617
119
        // No operand predicates
618
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
619
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
620
119
        GIM_CheckIsSafeToFold, /*InsnID*/2,
621
119
        // (add:{ *:[i32] } (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR32Opnd:{ *:[i32] }:$rt)  =>  (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
622
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA,
623
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
624
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
625
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
626
119
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
627
119
        GIR_EraseFromParent, /*InsnID*/0,
628
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
629
119
        // GIR_Coverage, 2308,
630
119
        GIR_Done,
631
119
      // Label 53: @198
632
119
      GIM_Try, /*On fail goto*//*Label 54*/ 266, // Rule ID 802 //
633
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
634
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
635
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
636
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
637
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
638
119
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
639
119
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
640
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
641
119
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
642
119
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
643
119
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
644
119
        // MIs[2] Operand 1
645
119
        // No operand predicates
646
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
647
119
        GIM_CheckIsSafeToFold, /*InsnID*/2,
648
119
        // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa))  =>  (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
649
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA,
650
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
651
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
652
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
653
119
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
654
119
        GIR_EraseFromParent, /*InsnID*/0,
655
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
656
119
        // GIR_Coverage, 802,
657
119
        GIR_Done,
658
119
      // Label 54: @266
659
119
      GIM_Try, /*On fail goto*//*Label 55*/ 309, // Rule ID 2083 //
660
119
        GIM_CheckFeatures, GIFBS_InMicroMips,
661
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
662
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
663
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
664
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
665
119
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExtAddiur2,
666
119
        // MIs[1] Operand 1
667
119
        // No operand predicates
668
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
669
119
        // (add:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)  =>  (ADDIUR2_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)
670
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUR2_MM,
671
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
672
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
673
119
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
674
119
        GIR_EraseFromParent, /*InsnID*/0,
675
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
676
119
        // GIR_Coverage, 2083,
677
119
        GIR_Done,
678
119
      // Label 55: @309
679
119
      GIM_Try, /*On fail goto*//*Label 56*/ 352, // Rule ID 2084 //
680
119
        GIM_CheckFeatures, GIFBS_InMicroMips,
681
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
682
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
683
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
684
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
685
119
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExtAddius5,
686
119
        // MIs[1] Operand 1
687
119
        // No operand predicates
688
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
689
119
        // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)  =>  (ADDIUS5_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)
690
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUS5_MM,
691
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
692
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
693
119
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
694
119
        GIR_EraseFromParent, /*InsnID*/0,
695
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
696
119
        // GIR_Coverage, 2084,
697
119
        GIR_Done,
698
119
      // Label 56: @352
699
119
      GIM_Try, /*On fail goto*//*Label 57*/ 375, // Rule ID 1174 //
700
119
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
701
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
702
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
703
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
704
119
        // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (ADDU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
705
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU16_MMR6,
706
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
707
119
        // GIR_Coverage, 1174,
708
119
        GIR_Done,
709
119
      // Label 57: @375
710
119
      GIM_Try, /*On fail goto*//*Label 58*/ 398, // Rule ID 34 //
711
119
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
712
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
713
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
714
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
715
119
        // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
716
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDu,
717
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
718
119
        // GIR_Coverage, 34,
719
119
        GIR_Done,
720
119
      // Label 58: @398
721
119
      GIM_Try, /*On fail goto*//*Label 59*/ 421, // Rule ID 1028 //
722
119
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
723
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
724
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
725
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
726
119
        // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (ADDU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
727
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU16_MM,
728
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
729
119
        // GIR_Coverage, 1028,
730
119
        GIR_Done,
731
119
      // Label 59: @421
732
119
      GIM_Try, /*On fail goto*//*Label 60*/ 444, // Rule ID 1040 //
733
119
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
734
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
735
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
736
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
737
119
        // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
738
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDu_MM,
739
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
740
119
        // GIR_Coverage, 1040,
741
119
        GIR_Done,
742
119
      // Label 60: @444
743
119
      GIM_Try, /*On fail goto*//*Label 61*/ 467, // Rule ID 1744 //
744
119
        GIM_CheckFeatures, GIFBS_InMips16Mode,
745
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
746
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
747
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
748
119
        // (add:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (AdduRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
749
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AdduRxRyRz16,
750
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
751
119
        // GIR_Coverage, 1744,
752
119
        GIR_Done,
753
119
      // Label 61: @467
754
119
      GIM_Reject,
755
119
    // Label 52: @468
756
119
    GIM_Reject,
757
119
    // Label 44: @469
758
119
    GIM_Try, /*On fail goto*//*Label 62*/ 631,
759
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
760
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
761
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
762
119
      GIM_Try, /*On fail goto*//*Label 63*/ 547, // Rule ID 2309 //
763
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc,
764
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
765
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
766
119
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
767
119
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
768
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
769
119
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
770
119
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
771
119
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
772
119
        // MIs[2] Operand 1
773
119
        // No operand predicates
774
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
775
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
776
119
        GIM_CheckIsSafeToFold, /*InsnID*/2,
777
119
        // (add:{ *:[i64] } (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR64Opnd:{ *:[i64] }:$rt)  =>  (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
778
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA,
779
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
780
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
781
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
782
119
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
783
119
        GIR_EraseFromParent, /*InsnID*/0,
784
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
785
119
        // GIR_Coverage, 2309,
786
119
        GIR_Done,
787
119
      // Label 63: @547
788
119
      GIM_Try, /*On fail goto*//*Label 64*/ 611, // Rule ID 803 //
789
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc,
790
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
791
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
792
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
793
119
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
794
119
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
795
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
796
119
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
797
119
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
798
119
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
799
119
        // MIs[2] Operand 1
800
119
        // No operand predicates
801
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
802
119
        GIM_CheckIsSafeToFold, /*InsnID*/2,
803
119
        // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa))  =>  (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
804
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA,
805
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
806
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
807
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
808
119
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
809
119
        GIR_EraseFromParent, /*InsnID*/0,
810
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
811
119
        // GIR_Coverage, 803,
812
119
        GIR_Done,
813
119
      // Label 64: @611
814
119
      GIM_Try, /*On fail goto*//*Label 65*/ 630, // Rule ID 180 //
815
119
        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
816
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
817
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
818
119
        // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
819
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DADDu,
820
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
821
119
        // GIR_Coverage, 180,
822
119
        GIR_Done,
823
119
      // Label 65: @630
824
119
      GIM_Reject,
825
119
    // Label 62: @631
826
119
    GIM_Reject,
827
119
    // Label 45: @632
828
119
    GIM_Try, /*On fail goto*//*Label 66*/ 658, // Rule ID 1843 //
829
119
      GIM_CheckFeatures, GIFBS_HasDSP,
830
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
831
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
832
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
833
119
      // (add:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
834
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDQ_PH,
835
119
      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
836
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
837
119
      // GIR_Coverage, 1843,
838
119
      GIR_Done,
839
119
    // Label 66: @658
840
119
    GIM_Reject,
841
119
    // Label 46: @659
842
119
    GIM_Try, /*On fail goto*//*Label 67*/ 807,
843
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
844
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
845
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
846
119
      GIM_Try, /*On fail goto*//*Label 68*/ 730, // Rule ID 2313 //
847
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
848
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
849
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
850
119
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
851
119
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
852
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
853
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
854
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
855
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
856
119
        // (add:{ *:[v2i64] } (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt), MSA128DOpnd:{ *:[v2i64] }:$wd_in)  =>  (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
857
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D,
858
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
859
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
860
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
861
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
862
119
        GIR_EraseFromParent, /*InsnID*/0,
863
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
864
119
        // GIR_Coverage, 2313,
865
119
        GIR_Done,
866
119
      // Label 68: @730
867
119
      GIM_Try, /*On fail goto*//*Label 69*/ 787, // Rule ID 811 //
868
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
869
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
870
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
871
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
872
119
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
873
119
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
874
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
875
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
876
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
877
119
        // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt))  =>  (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
878
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D,
879
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
880
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
881
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
882
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
883
119
        GIR_EraseFromParent, /*InsnID*/0,
884
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
885
119
        // GIR_Coverage, 811,
886
119
        GIR_Done,
887
119
      // Label 69: @787
888
119
      GIM_Try, /*On fail goto*//*Label 70*/ 806, // Rule ID 478 //
889
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
890
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
891
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
892
119
        // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
893
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_D,
894
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
895
119
        // GIR_Coverage, 478,
896
119
        GIR_Done,
897
119
      // Label 70: @806
898
119
      GIM_Reject,
899
119
    // Label 67: @807
900
119
    GIM_Reject,
901
119
    // Label 47: @808
902
119
    GIM_Try, /*On fail goto*//*Label 71*/ 834, // Rule ID 1849 //
903
119
      GIM_CheckFeatures, GIFBS_HasDSP,
904
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
905
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
906
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
907
119
      // (add:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)  =>  (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
908
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU_QB,
909
119
      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
910
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
911
119
      // GIR_Coverage, 1849,
912
119
      GIR_Done,
913
119
    // Label 71: @834
914
119
    GIM_Reject,
915
119
    // Label 48: @835
916
119
    GIM_Try, /*On fail goto*//*Label 72*/ 983,
917
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
918
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
919
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
920
119
      GIM_Try, /*On fail goto*//*Label 73*/ 906, // Rule ID 2312 //
921
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
922
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
923
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
924
119
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
925
119
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
926
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
927
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
928
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
929
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
930
119
        // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt), MSA128WOpnd:{ *:[v4i32] }:$wd_in)  =>  (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
931
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W,
932
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
933
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
934
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
935
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
936
119
        GIR_EraseFromParent, /*InsnID*/0,
937
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
938
119
        // GIR_Coverage, 2312,
939
119
        GIR_Done,
940
119
      // Label 73: @906
941
119
      GIM_Try, /*On fail goto*//*Label 74*/ 963, // Rule ID 810 //
942
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
943
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
944
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
945
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
946
119
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
947
119
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
948
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
949
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
950
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
951
119
        // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt))  =>  (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
952
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W,
953
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
954
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
955
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
956
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
957
119
        GIR_EraseFromParent, /*InsnID*/0,
958
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
959
119
        // GIR_Coverage, 810,
960
119
        GIR_Done,
961
119
      // Label 74: @963
962
119
      GIM_Try, /*On fail goto*//*Label 75*/ 982, // Rule ID 477 //
963
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
964
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
965
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
966
119
        // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
967
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_W,
968
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
969
119
        // GIR_Coverage, 477,
970
119
        GIR_Done,
971
119
      // Label 75: @982
972
119
      GIM_Reject,
973
119
    // Label 72: @983
974
119
    GIM_Reject,
975
119
    // Label 49: @984
976
119
    GIM_Try, /*On fail goto*//*Label 76*/ 1132,
977
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
978
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
979
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
980
119
      GIM_Try, /*On fail goto*//*Label 77*/ 1055, // Rule ID 2311 //
981
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
982
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
983
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
984
119
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
985
119
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
986
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
987
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
988
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
989
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
990
119
        // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt), MSA128HOpnd:{ *:[v8i16] }:$wd_in)  =>  (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
991
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H,
992
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
993
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
994
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
995
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
996
119
        GIR_EraseFromParent, /*InsnID*/0,
997
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
998
119
        // GIR_Coverage, 2311,
999
119
        GIR_Done,
1000
119
      // Label 77: @1055
1001
119
      GIM_Try, /*On fail goto*//*Label 78*/ 1112, // Rule ID 809 //
1002
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1003
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1004
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1005
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1006
119
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1007
119
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1008
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1009
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1010
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1011
119
        // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt))  =>  (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1012
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H,
1013
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1014
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1015
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1016
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1017
119
        GIR_EraseFromParent, /*InsnID*/0,
1018
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1019
119
        // GIR_Coverage, 809,
1020
119
        GIR_Done,
1021
119
      // Label 78: @1112
1022
119
      GIM_Try, /*On fail goto*//*Label 79*/ 1131, // Rule ID 476 //
1023
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1024
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1025
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1026
119
        // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1027
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_H,
1028
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1029
119
        // GIR_Coverage, 476,
1030
119
        GIR_Done,
1031
119
      // Label 79: @1131
1032
119
      GIM_Reject,
1033
119
    // Label 76: @1132
1034
119
    GIM_Reject,
1035
119
    // Label 50: @1133
1036
119
    GIM_Try, /*On fail goto*//*Label 80*/ 1281,
1037
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1038
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1039
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1040
119
      GIM_Try, /*On fail goto*//*Label 81*/ 1204, // Rule ID 2310 //
1041
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1042
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1043
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1044
119
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1045
119
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1046
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1047
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1048
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1049
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1050
119
        // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt), MSA128BOpnd:{ *:[v16i8] }:$wd_in)  =>  (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1051
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B,
1052
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1053
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
1054
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1055
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1056
119
        GIR_EraseFromParent, /*InsnID*/0,
1057
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1058
119
        // GIR_Coverage, 2310,
1059
119
        GIR_Done,
1060
119
      // Label 81: @1204
1061
119
      GIM_Try, /*On fail goto*//*Label 82*/ 1261, // Rule ID 808 //
1062
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1063
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1064
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1065
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1066
119
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1067
119
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1068
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1069
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1070
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1071
119
        // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt))  =>  (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1072
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B,
1073
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1074
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1075
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1076
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1077
119
        GIR_EraseFromParent, /*InsnID*/0,
1078
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1079
119
        // GIR_Coverage, 808,
1080
119
        GIR_Done,
1081
119
      // Label 82: @1261
1082
119
      GIM_Try, /*On fail goto*//*Label 83*/ 1280, // Rule ID 475 //
1083
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1084
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1085
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1086
119
        // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1087
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_B,
1088
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1089
119
        // GIR_Coverage, 475,
1090
119
        GIR_Done,
1091
119
      // Label 83: @1280
1092
119
      GIM_Reject,
1093
119
    // Label 80: @1281
1094
119
    GIM_Reject,
1095
119
    // Label 51: @1282
1096
119
    GIM_Reject,
1097
119
    // Label 1: @1283
1098
119
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 92*/ 1894,
1099
119
    /*GILLT_s32*//*Label 84*/ 1297,
1100
119
    /*GILLT_s64*//*Label 85*/ 1456,
1101
119
    /*GILLT_v2s16*//*Label 86*/ 1488,
1102
119
    /*GILLT_v2s64*//*Label 87*/ 1515,
1103
119
    /*GILLT_v4s8*//*Label 88*/ 1603,
1104
119
    /*GILLT_v4s32*//*Label 89*/ 1630,
1105
119
    /*GILLT_v8s16*//*Label 90*/ 1718,
1106
119
    /*GILLT_v16s8*//*Label 91*/ 1806,
1107
119
    // Label 84: @1297
1108
119
    GIM_Try, /*On fail goto*//*Label 93*/ 1455,
1109
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1110
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1111
119
      GIM_Try, /*On fail goto*//*Label 94*/ 1339, // Rule ID 1743 //
1112
119
        GIM_CheckFeatures, GIFBS_InMips16Mode,
1113
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
1114
119
        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
1115
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
1116
119
        // (sub:{ *:[i32] } 0:{ *:[i32] }, CPU16Regs:{ *:[i32] }:$r)  =>  (NegRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
1117
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NegRxRy16,
1118
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
1119
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // r
1120
119
        GIR_EraseFromParent, /*InsnID*/0,
1121
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1122
119
        // GIR_Coverage, 1743,
1123
119
        GIR_Done,
1124
119
      // Label 94: @1339
1125
119
      GIM_Try, /*On fail goto*//*Label 95*/ 1362, // Rule ID 1176 //
1126
119
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1127
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
1128
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
1129
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
1130
119
        // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (SUBU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1131
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU16_MMR6,
1132
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1133
119
        // GIR_Coverage, 1176,
1134
119
        GIR_Done,
1135
119
      // Label 95: @1362
1136
119
      GIM_Try, /*On fail goto*//*Label 96*/ 1385, // Rule ID 35 //
1137
119
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
1138
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1139
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1140
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1141
119
        // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1142
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBu,
1143
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1144
119
        // GIR_Coverage, 35,
1145
119
        GIR_Done,
1146
119
      // Label 96: @1385
1147
119
      GIM_Try, /*On fail goto*//*Label 97*/ 1408, // Rule ID 1032 //
1148
119
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
1149
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
1150
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
1151
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
1152
119
        // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (SUBU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1153
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU16_MM,
1154
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1155
119
        // GIR_Coverage, 1032,
1156
119
        GIR_Done,
1157
119
      // Label 97: @1408
1158
119
      GIM_Try, /*On fail goto*//*Label 98*/ 1431, // Rule ID 1041 //
1159
119
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
1160
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1161
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1162
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1163
119
        // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1164
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBu_MM,
1165
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1166
119
        // GIR_Coverage, 1041,
1167
119
        GIR_Done,
1168
119
      // Label 98: @1431
1169
119
      GIM_Try, /*On fail goto*//*Label 99*/ 1454, // Rule ID 1748 //
1170
119
        GIM_CheckFeatures, GIFBS_InMips16Mode,
1171
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
1172
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
1173
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
1174
119
        // (sub:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (SubuRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1175
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SubuRxRyRz16,
1176
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1177
119
        // GIR_Coverage, 1748,
1178
119
        GIR_Done,
1179
119
      // Label 99: @1454
1180
119
      GIM_Reject,
1181
119
    // Label 93: @1455
1182
119
    GIM_Reject,
1183
119
    // Label 85: @1456
1184
119
    GIM_Try, /*On fail goto*//*Label 100*/ 1487, // Rule ID 181 //
1185
119
      GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
1186
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1187
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1188
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1189
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1190
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1191
119
      // (sub:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DSUBu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1192
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSUBu,
1193
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1194
119
      // GIR_Coverage, 181,
1195
119
      GIR_Done,
1196
119
    // Label 100: @1487
1197
119
    GIM_Reject,
1198
119
    // Label 86: @1488
1199
119
    GIM_Try, /*On fail goto*//*Label 101*/ 1514, // Rule ID 1845 //
1200
119
      GIM_CheckFeatures, GIFBS_HasDSP,
1201
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1202
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
1203
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
1204
119
      // (sub:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1205
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBQ_PH,
1206
119
      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
1207
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1208
119
      // GIR_Coverage, 1845,
1209
119
      GIR_Done,
1210
119
    // Label 101: @1514
1211
119
    GIM_Reject,
1212
119
    // Label 87: @1515
1213
119
    GIM_Try, /*On fail goto*//*Label 102*/ 1602,
1214
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1215
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1216
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1217
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1218
119
      GIM_Try, /*On fail goto*//*Label 103*/ 1586, // Rule ID 867 //
1219
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1220
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1221
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1222
119
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
1223
119
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
1224
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1225
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1226
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1227
119
        // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt))  =>  (MSUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1228
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_D,
1229
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1230
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1231
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1232
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1233
119
        GIR_EraseFromParent, /*InsnID*/0,
1234
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1235
119
        // GIR_Coverage, 867,
1236
119
        GIR_Done,
1237
119
      // Label 103: @1586
1238
119
      GIM_Try, /*On fail goto*//*Label 104*/ 1601, // Rule ID 996 //
1239
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1240
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1241
119
        // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1242
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_D,
1243
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1244
119
        // GIR_Coverage, 996,
1245
119
        GIR_Done,
1246
119
      // Label 104: @1601
1247
119
      GIM_Reject,
1248
119
    // Label 102: @1602
1249
119
    GIM_Reject,
1250
119
    // Label 88: @1603
1251
119
    GIM_Try, /*On fail goto*//*Label 105*/ 1629, // Rule ID 1851 //
1252
119
      GIM_CheckFeatures, GIFBS_HasDSP,
1253
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
1254
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
1255
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
1256
119
      // (sub:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)  =>  (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
1257
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU_QB,
1258
119
      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
1259
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1260
119
      // GIR_Coverage, 1851,
1261
119
      GIR_Done,
1262
119
    // Label 105: @1629
1263
119
    GIM_Reject,
1264
119
    // Label 89: @1630
1265
119
    GIM_Try, /*On fail goto*//*Label 106*/ 1717,
1266
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1267
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1268
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1269
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1270
119
      GIM_Try, /*On fail goto*//*Label 107*/ 1701, // Rule ID 866 //
1271
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1272
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1273
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1274
119
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1275
119
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1276
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1277
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1278
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1279
119
        // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt))  =>  (MSUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1280
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_W,
1281
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1282
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1283
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1284
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1285
119
        GIR_EraseFromParent, /*InsnID*/0,
1286
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1287
119
        // GIR_Coverage, 866,
1288
119
        GIR_Done,
1289
119
      // Label 107: @1701
1290
119
      GIM_Try, /*On fail goto*//*Label 108*/ 1716, // Rule ID 995 //
1291
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1292
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1293
119
        // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1294
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_W,
1295
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1296
119
        // GIR_Coverage, 995,
1297
119
        GIR_Done,
1298
119
      // Label 108: @1716
1299
119
      GIM_Reject,
1300
119
    // Label 106: @1717
1301
119
    GIM_Reject,
1302
119
    // Label 90: @1718
1303
119
    GIM_Try, /*On fail goto*//*Label 109*/ 1805,
1304
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1305
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1306
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1307
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1308
119
      GIM_Try, /*On fail goto*//*Label 110*/ 1789, // Rule ID 865 //
1309
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1310
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1311
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1312
119
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1313
119
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1314
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1315
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1316
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1317
119
        // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt))  =>  (MSUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1318
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_H,
1319
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1320
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1321
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1322
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1323
119
        GIR_EraseFromParent, /*InsnID*/0,
1324
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1325
119
        // GIR_Coverage, 865,
1326
119
        GIR_Done,
1327
119
      // Label 110: @1789
1328
119
      GIM_Try, /*On fail goto*//*Label 111*/ 1804, // Rule ID 994 //
1329
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1330
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1331
119
        // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1332
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_H,
1333
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1334
119
        // GIR_Coverage, 994,
1335
119
        GIR_Done,
1336
119
      // Label 111: @1804
1337
119
      GIM_Reject,
1338
119
    // Label 109: @1805
1339
119
    GIM_Reject,
1340
119
    // Label 91: @1806
1341
119
    GIM_Try, /*On fail goto*//*Label 112*/ 1893,
1342
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1343
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1344
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1345
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1346
119
      GIM_Try, /*On fail goto*//*Label 113*/ 1877, // Rule ID 864 //
1347
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1348
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1349
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1350
119
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1351
119
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1352
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1353
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1354
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
1355
119
        // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt))  =>  (MSUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1356
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_B,
1357
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
1358
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
1359
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1360
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1361
119
        GIR_EraseFromParent, /*InsnID*/0,
1362
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1363
119
        // GIR_Coverage, 864,
1364
119
        GIR_Done,
1365
119
      // Label 113: @1877
1366
119
      GIM_Try, /*On fail goto*//*Label 114*/ 1892, // Rule ID 993 //
1367
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1368
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1369
119
        // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1370
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_B,
1371
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1372
119
        // GIR_Coverage, 993,
1373
119
        GIR_Done,
1374
119
      // Label 114: @1892
1375
119
      GIM_Reject,
1376
119
    // Label 112: @1893
1377
119
    GIM_Reject,
1378
119
    // Label 92: @1894
1379
119
    GIM_Reject,
1380
119
    // Label 2: @1895
1381
119
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 122*/ 2270,
1382
119
    /*GILLT_s32*//*Label 115*/ 1909,
1383
119
    /*GILLT_s64*//*Label 116*/ 2054,
1384
119
    /*GILLT_v2s16*//*Label 117*/ 2115,
1385
119
    /*GILLT_v2s64*//*Label 118*/ 2142, 0,
1386
119
    /*GILLT_v4s32*//*Label 119*/ 2174,
1387
119
    /*GILLT_v8s16*//*Label 120*/ 2206,
1388
119
    /*GILLT_v16s8*//*Label 121*/ 2238,
1389
119
    // Label 115: @1909
1390
119
    GIM_Try, /*On fail goto*//*Label 123*/ 2053,
1391
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1392
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1393
119
      GIM_Try, /*On fail goto*//*Label 124*/ 1948, // Rule ID 36 //
1394
119
        GIM_CheckFeatures, GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
1395
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1396
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1397
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1398
119
        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1399
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL,
1400
119
        GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1401
119
        GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1402
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1403
119
        // GIR_Coverage, 36,
1404
119
        GIR_Done,
1405
119
      // Label 124: @1948
1406
119
      GIM_Try, /*On fail goto*//*Label 125*/ 1971, // Rule ID 304 //
1407
119
        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1408
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1409
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1410
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1411
119
        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1412
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_R6,
1413
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1414
119
        // GIR_Coverage, 304,
1415
119
        GIR_Done,
1416
119
      // Label 125: @1971
1417
119
      GIM_Try, /*On fail goto*//*Label 126*/ 2000, // Rule ID 1042 //
1418
119
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
1419
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1420
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1421
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1422
119
        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL_MM:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1423
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_MM,
1424
119
        GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1425
119
        GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1426
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1427
119
        // GIR_Coverage, 1042,
1428
119
        GIR_Done,
1429
119
      // Label 126: @2000
1430
119
      GIM_Try, /*On fail goto*//*Label 127*/ 2023, // Rule ID 1145 //
1431
119
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1432
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1433
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1434
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1435
119
        // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1436
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_MMR6,
1437
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1438
119
        // GIR_Coverage, 1145,
1439
119
        GIR_Done,
1440
119
      // Label 127: @2023
1441
119
      GIM_Try, /*On fail goto*//*Label 128*/ 2052, // Rule ID 1746 //
1442
119
        GIM_CheckFeatures, GIFBS_InMips16Mode,
1443
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
1444
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
1445
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
1446
119
        // (mul:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (MultRxRyRz16:{ *:[i32] }:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1447
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MultRxRyRz16,
1448
119
        GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1449
119
        GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1450
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1451
119
        // GIR_Coverage, 1746,
1452
119
        GIR_Done,
1453
119
      // Label 128: @2052
1454
119
      GIM_Reject,
1455
119
    // Label 123: @2053
1456
119
    GIM_Reject,
1457
119
    // Label 116: @2054
1458
119
    GIM_Try, /*On fail goto*//*Label 129*/ 2114,
1459
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1460
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1461
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1462
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1463
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1464
119
      GIM_Try, /*On fail goto*//*Label 130*/ 2102, // Rule ID 246 //
1465
119
        GIM_CheckFeatures, GIFBS_HasCnMips,
1466
119
        // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMUL:{ *:[i64] }:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1467
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUL,
1468
119
        GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
1469
119
        GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
1470
119
        GIR_AddImplicitDef, /*InsnID*/0, Mips::P0,
1471
119
        GIR_AddImplicitDef, /*InsnID*/0, Mips::P1,
1472
119
        GIR_AddImplicitDef, /*InsnID*/0, Mips::P2,
1473
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1474
119
        // GIR_Coverage, 246,
1475
119
        GIR_Done,
1476
119
      // Label 130: @2102
1477
119
      GIM_Try, /*On fail goto*//*Label 131*/ 2113, // Rule ID 319 //
1478
119
        GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1479
119
        // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMUL_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1480
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUL_R6,
1481
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1482
119
        // GIR_Coverage, 319,
1483
119
        GIR_Done,
1484
119
      // Label 131: @2113
1485
119
      GIM_Reject,
1486
119
    // Label 129: @2114
1487
119
    GIM_Reject,
1488
119
    // Label 117: @2115
1489
119
    GIM_Try, /*On fail goto*//*Label 132*/ 2141, // Rule ID 1847 //
1490
119
      GIM_CheckFeatures, GIFBS_HasDSPR2,
1491
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
1492
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
1493
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
1494
119
      // (mul:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1495
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_PH,
1496
119
      GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag21,
1497
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1498
119
      // GIR_Coverage, 1847,
1499
119
      GIR_Done,
1500
119
    // Label 132: @2141
1501
119
    GIM_Reject,
1502
119
    // Label 118: @2142
1503
119
    GIM_Try, /*On fail goto*//*Label 133*/ 2173, // Rule ID 875 //
1504
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1505
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1506
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1507
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1508
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1509
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1510
119
      // (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MULV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1511
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_D,
1512
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1513
119
      // GIR_Coverage, 875,
1514
119
      GIR_Done,
1515
119
    // Label 133: @2173
1516
119
    GIM_Reject,
1517
119
    // Label 119: @2174
1518
119
    GIM_Try, /*On fail goto*//*Label 134*/ 2205, // Rule ID 874 //
1519
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1520
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1521
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1522
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1523
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1524
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1525
119
      // (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MULV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1526
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_W,
1527
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1528
119
      // GIR_Coverage, 874,
1529
119
      GIR_Done,
1530
119
    // Label 134: @2205
1531
119
    GIM_Reject,
1532
119
    // Label 120: @2206
1533
119
    GIM_Try, /*On fail goto*//*Label 135*/ 2237, // Rule ID 873 //
1534
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1535
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1536
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1537
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1538
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1539
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1540
119
      // (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MULV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1541
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_H,
1542
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1543
119
      // GIR_Coverage, 873,
1544
119
      GIR_Done,
1545
119
    // Label 135: @2237
1546
119
    GIM_Reject,
1547
119
    // Label 121: @2238
1548
119
    GIM_Try, /*On fail goto*//*Label 136*/ 2269, // Rule ID 872 //
1549
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1550
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1551
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1552
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1553
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1554
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1555
119
      // (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MULV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1556
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_B,
1557
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1558
119
      // GIR_Coverage, 872,
1559
119
      GIR_Done,
1560
119
    // Label 136: @2269
1561
119
    GIM_Reject,
1562
119
    // Label 122: @2270
1563
119
    GIM_Reject,
1564
119
    // Label 3: @2271
1565
119
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 143*/ 2491,
1566
119
    /*GILLT_s32*//*Label 137*/ 2285,
1567
119
    /*GILLT_s64*//*Label 138*/ 2331, 0,
1568
119
    /*GILLT_v2s64*//*Label 139*/ 2363, 0,
1569
119
    /*GILLT_v4s32*//*Label 140*/ 2395,
1570
119
    /*GILLT_v8s16*//*Label 141*/ 2427,
1571
119
    /*GILLT_v16s8*//*Label 142*/ 2459,
1572
119
    // Label 137: @2285
1573
119
    GIM_Try, /*On fail goto*//*Label 144*/ 2330,
1574
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1575
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1576
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1577
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1578
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1579
119
      GIM_Try, /*On fail goto*//*Label 145*/ 2318, // Rule ID 298 //
1580
119
        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1581
119
        // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1582
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV,
1583
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1584
119
        // GIR_Coverage, 298,
1585
119
        GIR_Done,
1586
119
      // Label 145: @2318
1587
119
      GIM_Try, /*On fail goto*//*Label 146*/ 2329, // Rule ID 1138 //
1588
119
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1589
119
        // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIV_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1590
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_MMR6,
1591
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1592
119
        // GIR_Coverage, 1138,
1593
119
        GIR_Done,
1594
119
      // Label 146: @2329
1595
119
      GIM_Reject,
1596
119
    // Label 144: @2330
1597
119
    GIM_Reject,
1598
119
    // Label 138: @2331
1599
119
    GIM_Try, /*On fail goto*//*Label 147*/ 2362, // Rule ID 313 //
1600
119
      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1601
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1602
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1603
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1604
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1605
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1606
119
      // (sdiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DDIV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1607
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DDIV,
1608
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1609
119
      // GIR_Coverage, 313,
1610
119
      GIR_Done,
1611
119
    // Label 147: @2362
1612
119
    GIM_Reject,
1613
119
    // Label 139: @2363
1614
119
    GIM_Try, /*On fail goto*//*Label 148*/ 2394, // Rule ID 615 //
1615
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1616
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1617
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1618
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1619
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1620
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1621
119
      // (sdiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (DIV_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1622
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_D,
1623
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1624
119
      // GIR_Coverage, 615,
1625
119
      GIR_Done,
1626
119
    // Label 148: @2394
1627
119
    GIM_Reject,
1628
119
    // Label 140: @2395
1629
119
    GIM_Try, /*On fail goto*//*Label 149*/ 2426, // Rule ID 614 //
1630
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1631
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1632
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1633
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1634
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1635
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1636
119
      // (sdiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DIV_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1637
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_W,
1638
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1639
119
      // GIR_Coverage, 614,
1640
119
      GIR_Done,
1641
119
    // Label 149: @2426
1642
119
    GIM_Reject,
1643
119
    // Label 141: @2427
1644
119
    GIM_Try, /*On fail goto*//*Label 150*/ 2458, // Rule ID 613 //
1645
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1646
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1647
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1648
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1649
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1650
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1651
119
      // (sdiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DIV_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1652
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_H,
1653
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1654
119
      // GIR_Coverage, 613,
1655
119
      GIR_Done,
1656
119
    // Label 150: @2458
1657
119
    GIM_Reject,
1658
119
    // Label 142: @2459
1659
119
    GIM_Try, /*On fail goto*//*Label 151*/ 2490, // Rule ID 612 //
1660
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1661
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1662
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1663
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1664
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1665
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1666
119
      // (sdiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DIV_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1667
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_B,
1668
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1669
119
      // GIR_Coverage, 612,
1670
119
      GIR_Done,
1671
119
    // Label 151: @2490
1672
119
    GIM_Reject,
1673
119
    // Label 143: @2491
1674
119
    GIM_Reject,
1675
119
    // Label 4: @2492
1676
119
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 158*/ 2712,
1677
119
    /*GILLT_s32*//*Label 152*/ 2506,
1678
119
    /*GILLT_s64*//*Label 153*/ 2552, 0,
1679
119
    /*GILLT_v2s64*//*Label 154*/ 2584, 0,
1680
119
    /*GILLT_v4s32*//*Label 155*/ 2616,
1681
119
    /*GILLT_v8s16*//*Label 156*/ 2648,
1682
119
    /*GILLT_v16s8*//*Label 157*/ 2680,
1683
119
    // Label 152: @2506
1684
119
    GIM_Try, /*On fail goto*//*Label 159*/ 2551,
1685
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1686
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1687
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1688
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1689
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1690
119
      GIM_Try, /*On fail goto*//*Label 160*/ 2539, // Rule ID 299 //
1691
119
        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1692
119
        // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIVU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1693
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIVU,
1694
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1695
119
        // GIR_Coverage, 299,
1696
119
        GIR_Done,
1697
119
      // Label 160: @2539
1698
119
      GIM_Try, /*On fail goto*//*Label 161*/ 2550, // Rule ID 1139 //
1699
119
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1700
119
        // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIVU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1701
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIVU_MMR6,
1702
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1703
119
        // GIR_Coverage, 1139,
1704
119
        GIR_Done,
1705
119
      // Label 161: @2550
1706
119
      GIM_Reject,
1707
119
    // Label 159: @2551
1708
119
    GIM_Reject,
1709
119
    // Label 153: @2552
1710
119
    GIM_Try, /*On fail goto*//*Label 162*/ 2583, // Rule ID 314 //
1711
119
      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1712
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1713
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1714
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1715
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1716
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1717
119
      // (udiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DDIVU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1718
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DDIVU,
1719
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1720
119
      // GIR_Coverage, 314,
1721
119
      GIR_Done,
1722
119
    // Label 162: @2583
1723
119
    GIM_Reject,
1724
119
    // Label 154: @2584
1725
119
    GIM_Try, /*On fail goto*//*Label 163*/ 2615, // Rule ID 619 //
1726
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1727
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1728
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1729
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1730
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1731
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1732
119
      // (udiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (DIV_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1733
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_D,
1734
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1735
119
      // GIR_Coverage, 619,
1736
119
      GIR_Done,
1737
119
    // Label 163: @2615
1738
119
    GIM_Reject,
1739
119
    // Label 155: @2616
1740
119
    GIM_Try, /*On fail goto*//*Label 164*/ 2647, // Rule ID 618 //
1741
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1742
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1743
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1744
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1745
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1746
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1747
119
      // (udiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DIV_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1748
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_W,
1749
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1750
119
      // GIR_Coverage, 618,
1751
119
      GIR_Done,
1752
119
    // Label 164: @2647
1753
119
    GIM_Reject,
1754
119
    // Label 156: @2648
1755
119
    GIM_Try, /*On fail goto*//*Label 165*/ 2679, // Rule ID 617 //
1756
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1757
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1758
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1759
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1760
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1761
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1762
119
      // (udiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DIV_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1763
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_H,
1764
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1765
119
      // GIR_Coverage, 617,
1766
119
      GIR_Done,
1767
119
    // Label 165: @2679
1768
119
    GIM_Reject,
1769
119
    // Label 157: @2680
1770
119
    GIM_Try, /*On fail goto*//*Label 166*/ 2711, // Rule ID 616 //
1771
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1772
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1773
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1774
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1775
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1776
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1777
119
      // (udiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DIV_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1778
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_B,
1779
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1780
119
      // GIR_Coverage, 616,
1781
119
      GIR_Done,
1782
119
    // Label 166: @2711
1783
119
    GIM_Reject,
1784
119
    // Label 158: @2712
1785
119
    GIM_Reject,
1786
119
    // Label 5: @2713
1787
119
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 173*/ 2933,
1788
119
    /*GILLT_s32*//*Label 167*/ 2727,
1789
119
    /*GILLT_s64*//*Label 168*/ 2773, 0,
1790
119
    /*GILLT_v2s64*//*Label 169*/ 2805, 0,
1791
119
    /*GILLT_v4s32*//*Label 170*/ 2837,
1792
119
    /*GILLT_v8s16*//*Label 171*/ 2869,
1793
119
    /*GILLT_v16s8*//*Label 172*/ 2901,
1794
119
    // Label 167: @2727
1795
119
    GIM_Try, /*On fail goto*//*Label 174*/ 2772,
1796
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1797
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1798
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1799
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1800
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1801
119
      GIM_Try, /*On fail goto*//*Label 175*/ 2760, // Rule ID 300 //
1802
119
        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1803
119
        // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MOD:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1804
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD,
1805
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1806
119
        // GIR_Coverage, 300,
1807
119
        GIR_Done,
1808
119
      // Label 175: @2760
1809
119
      GIM_Try, /*On fail goto*//*Label 176*/ 2771, // Rule ID 1143 //
1810
119
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1811
119
        // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MOD_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1812
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_MMR6,
1813
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1814
119
        // GIR_Coverage, 1143,
1815
119
        GIR_Done,
1816
119
      // Label 176: @2771
1817
119
      GIM_Reject,
1818
119
    // Label 174: @2772
1819
119
    GIM_Reject,
1820
119
    // Label 168: @2773
1821
119
    GIM_Try, /*On fail goto*//*Label 177*/ 2804, // Rule ID 315 //
1822
119
      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1823
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1824
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1825
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1826
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1827
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1828
119
      // (srem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMOD:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1829
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMOD,
1830
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1831
119
      // GIR_Coverage, 315,
1832
119
      GIR_Done,
1833
119
    // Label 177: @2804
1834
119
    GIM_Reject,
1835
119
    // Label 169: @2805
1836
119
    GIM_Try, /*On fail goto*//*Label 178*/ 2836, // Rule ID 855 //
1837
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1838
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1839
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1840
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1841
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1842
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1843
119
      // (srem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MOD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1844
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_D,
1845
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1846
119
      // GIR_Coverage, 855,
1847
119
      GIR_Done,
1848
119
    // Label 178: @2836
1849
119
    GIM_Reject,
1850
119
    // Label 170: @2837
1851
119
    GIM_Try, /*On fail goto*//*Label 179*/ 2868, // Rule ID 854 //
1852
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1853
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1854
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1855
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1856
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1857
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1858
119
      // (srem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MOD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1859
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_W,
1860
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1861
119
      // GIR_Coverage, 854,
1862
119
      GIR_Done,
1863
119
    // Label 179: @2868
1864
119
    GIM_Reject,
1865
119
    // Label 171: @2869
1866
119
    GIM_Try, /*On fail goto*//*Label 180*/ 2900, // Rule ID 853 //
1867
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1868
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1869
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1870
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1871
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1872
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1873
119
      // (srem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MOD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1874
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_H,
1875
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1876
119
      // GIR_Coverage, 853,
1877
119
      GIR_Done,
1878
119
    // Label 180: @2900
1879
119
    GIM_Reject,
1880
119
    // Label 172: @2901
1881
119
    GIM_Try, /*On fail goto*//*Label 181*/ 2932, // Rule ID 852 //
1882
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1883
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1884
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1885
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1886
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1887
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1888
119
      // (srem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MOD_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1889
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_B,
1890
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1891
119
      // GIR_Coverage, 852,
1892
119
      GIR_Done,
1893
119
    // Label 181: @2932
1894
119
    GIM_Reject,
1895
119
    // Label 173: @2933
1896
119
    GIM_Reject,
1897
119
    // Label 6: @2934
1898
119
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 188*/ 3154,
1899
119
    /*GILLT_s32*//*Label 182*/ 2948,
1900
119
    /*GILLT_s64*//*Label 183*/ 2994, 0,
1901
119
    /*GILLT_v2s64*//*Label 184*/ 3026, 0,
1902
119
    /*GILLT_v4s32*//*Label 185*/ 3058,
1903
119
    /*GILLT_v8s16*//*Label 186*/ 3090,
1904
119
    /*GILLT_v16s8*//*Label 187*/ 3122,
1905
119
    // Label 182: @2948
1906
119
    GIM_Try, /*On fail goto*//*Label 189*/ 2993,
1907
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1908
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1909
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
1910
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
1911
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
1912
119
      GIM_Try, /*On fail goto*//*Label 190*/ 2981, // Rule ID 301 //
1913
119
        GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
1914
119
        // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MODU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1915
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MODU,
1916
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1917
119
        // GIR_Coverage, 301,
1918
119
        GIR_Done,
1919
119
      // Label 190: @2981
1920
119
      GIM_Try, /*On fail goto*//*Label 191*/ 2992, // Rule ID 1144 //
1921
119
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
1922
119
        // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MODU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1923
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MODU_MMR6,
1924
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1925
119
        // GIR_Coverage, 1144,
1926
119
        GIR_Done,
1927
119
      // Label 191: @2992
1928
119
      GIM_Reject,
1929
119
    // Label 189: @2993
1930
119
    GIM_Reject,
1931
119
    // Label 183: @2994
1932
119
    GIM_Try, /*On fail goto*//*Label 192*/ 3025, // Rule ID 316 //
1933
119
      GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
1934
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1935
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1936
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
1937
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
1938
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
1939
119
      // (urem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMODU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1940
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMODU,
1941
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1942
119
      // GIR_Coverage, 316,
1943
119
      GIR_Done,
1944
119
    // Label 192: @3025
1945
119
    GIM_Reject,
1946
119
    // Label 184: @3026
1947
119
    GIM_Try, /*On fail goto*//*Label 193*/ 3057, // Rule ID 859 //
1948
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1949
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1950
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1951
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
1952
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
1953
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
1954
119
      // (urem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MOD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1955
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_D,
1956
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1957
119
      // GIR_Coverage, 859,
1958
119
      GIR_Done,
1959
119
    // Label 193: @3057
1960
119
    GIM_Reject,
1961
119
    // Label 185: @3058
1962
119
    GIM_Try, /*On fail goto*//*Label 194*/ 3089, // Rule ID 858 //
1963
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1964
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
1965
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
1966
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
1967
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
1968
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
1969
119
      // (urem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MOD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1970
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_W,
1971
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1972
119
      // GIR_Coverage, 858,
1973
119
      GIR_Done,
1974
119
    // Label 194: @3089
1975
119
    GIM_Reject,
1976
119
    // Label 186: @3090
1977
119
    GIM_Try, /*On fail goto*//*Label 195*/ 3121, // Rule ID 857 //
1978
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1979
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
1980
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
1981
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
1982
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
1983
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
1984
119
      // (urem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MOD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1985
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_H,
1986
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1987
119
      // GIR_Coverage, 857,
1988
119
      GIR_Done,
1989
119
    // Label 195: @3121
1990
119
    GIM_Reject,
1991
119
    // Label 187: @3122
1992
119
    GIM_Try, /*On fail goto*//*Label 196*/ 3153, // Rule ID 856 //
1993
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
1994
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
1995
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
1996
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
1997
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
1998
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
1999
119
      // (urem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MOD_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2000
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_B,
2001
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2002
119
      // GIR_Coverage, 856,
2003
119
      GIR_Done,
2004
119
    // Label 196: @3153
2005
119
    GIM_Reject,
2006
119
    // Label 188: @3154
2007
119
    GIM_Reject,
2008
119
    // Label 7: @3155
2009
119
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 203*/ 3598,
2010
119
    /*GILLT_s32*//*Label 197*/ 3169,
2011
119
    /*GILLT_s64*//*Label 198*/ 3382, 0,
2012
119
    /*GILLT_v2s64*//*Label 199*/ 3470, 0,
2013
119
    /*GILLT_v4s32*//*Label 200*/ 3502,
2014
119
    /*GILLT_v8s16*//*Label 201*/ 3534,
2015
119
    /*GILLT_v16s8*//*Label 202*/ 3566,
2016
119
    // Label 197: @3169
2017
119
    GIM_Try, /*On fail goto*//*Label 204*/ 3381,
2018
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2019
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2020
119
      GIM_Try, /*On fail goto*//*Label 205*/ 3222, // Rule ID 2086 //
2021
119
        GIM_CheckFeatures, GIFBS_InMicroMips,
2022
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2023
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2024
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2025
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2026
119
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExtAndi16,
2027
119
        // MIs[1] Operand 1
2028
119
        // No operand predicates
2029
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2030
119
        // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)  =>  (ANDI16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2031
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MM,
2032
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2033
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
2034
119
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2035
119
        GIR_EraseFromParent, /*InsnID*/0,
2036
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2037
119
        // GIR_Coverage, 2086,
2038
119
        GIR_Done,
2039
119
      // Label 205: @3222
2040
119
      GIM_Try, /*On fail goto*//*Label 206*/ 3265, // Rule ID 2239 //
2041
119
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2042
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2043
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2044
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2045
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
2046
119
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExtAndi16,
2047
119
        // MIs[1] Operand 1
2048
119
        // No operand predicates
2049
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2050
119
        // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)  =>  (ANDI16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2051
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MMR6,
2052
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2053
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
2054
119
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2055
119
        GIR_EraseFromParent, /*InsnID*/0,
2056
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2057
119
        // GIR_Coverage, 2239,
2058
119
        GIR_Done,
2059
119
      // Label 206: @3265
2060
119
      GIM_Try, /*On fail goto*//*Label 207*/ 3288, // Rule ID 39 //
2061
119
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2062
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2063
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2064
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2065
119
        // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (AND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2066
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND,
2067
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2068
119
        // GIR_Coverage, 39,
2069
119
        GIR_Done,
2070
119
      // Label 207: @3288
2071
119
      GIM_Try, /*On fail goto*//*Label 208*/ 3311, // Rule ID 1029 //
2072
119
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2073
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2074
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2075
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
2076
119
        // (and:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (AND16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2077
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND16_MM,
2078
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2079
119
        // GIR_Coverage, 1029,
2080
119
        GIR_Done,
2081
119
      // Label 208: @3311
2082
119
      GIM_Try, /*On fail goto*//*Label 209*/ 3334, // Rule ID 1045 //
2083
119
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2084
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2085
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2086
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2087
119
        // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (AND_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2088
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_MM,
2089
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2090
119
        // GIR_Coverage, 1045,
2091
119
        GIR_Done,
2092
119
      // Label 209: @3334
2093
119
      GIM_Try, /*On fail goto*//*Label 210*/ 3357, // Rule ID 1136 //
2094
119
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2095
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2096
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2097
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2098
119
        // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (AND_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2099
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_MMR6,
2100
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2101
119
        // GIR_Coverage, 1136,
2102
119
        GIR_Done,
2103
119
      // Label 210: @3357
2104
119
      GIM_Try, /*On fail goto*//*Label 211*/ 3380, // Rule ID 1745 //
2105
119
        GIM_CheckFeatures, GIFBS_InMips16Mode,
2106
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2107
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2108
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
2109
119
        // (and:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (AndRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2110
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AndRxRxRy16,
2111
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2112
119
        // GIR_Coverage, 1745,
2113
119
        GIR_Done,
2114
119
      // Label 211: @3380
2115
119
      GIM_Reject,
2116
119
    // Label 204: @3381
2117
119
    GIM_Reject,
2118
119
    // Label 198: @3382
2119
119
    GIM_Try, /*On fail goto*//*Label 212*/ 3469,
2120
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2121
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2122
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2123
119
      GIM_Try, /*On fail goto*//*Label 213*/ 3449, // Rule ID 241 //
2124
119
        GIM_CheckFeatures, GIFBS_HasCnMips,
2125
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2126
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
2127
119
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2128
119
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2129
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2130
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2131
119
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
2132
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2133
119
        // (and:{ *:[i64] } (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), 255:{ *:[i64] })  =>  (BADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2134
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BADDu,
2135
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2136
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2137
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2138
119
        GIR_EraseFromParent, /*InsnID*/0,
2139
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2140
119
        // GIR_Coverage, 241,
2141
119
        GIR_Done,
2142
119
      // Label 213: @3449
2143
119
      GIM_Try, /*On fail goto*//*Label 214*/ 3468, // Rule ID 184 //
2144
119
        GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2145
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2146
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2147
119
        // (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (AND64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2148
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND64,
2149
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2150
119
        // GIR_Coverage, 184,
2151
119
        GIR_Done,
2152
119
      // Label 214: @3468
2153
119
      GIM_Reject,
2154
119
    // Label 212: @3469
2155
119
    GIM_Reject,
2156
119
    // Label 199: @3470
2157
119
    GIM_Try, /*On fail goto*//*Label 215*/ 3501, // Rule ID 486 //
2158
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2159
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2160
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2161
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2162
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
2163
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
2164
119
      // (and:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (AND_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2165
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_D_PSEUDO,
2166
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2167
119
      // GIR_Coverage, 486,
2168
119
      GIR_Done,
2169
119
    // Label 215: @3501
2170
119
    GIM_Reject,
2171
119
    // Label 200: @3502
2172
119
    GIM_Try, /*On fail goto*//*Label 216*/ 3533, // Rule ID 485 //
2173
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2174
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2175
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2176
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2177
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2178
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2179
119
      // (and:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (AND_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2180
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_W_PSEUDO,
2181
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2182
119
      // GIR_Coverage, 485,
2183
119
      GIR_Done,
2184
119
    // Label 216: @3533
2185
119
    GIM_Reject,
2186
119
    // Label 201: @3534
2187
119
    GIM_Try, /*On fail goto*//*Label 217*/ 3565, // Rule ID 484 //
2188
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2189
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2190
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2191
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2192
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2193
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2194
119
      // (and:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (AND_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2195
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_H_PSEUDO,
2196
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2197
119
      // GIR_Coverage, 484,
2198
119
      GIR_Done,
2199
119
    // Label 217: @3565
2200
119
    GIM_Reject,
2201
119
    // Label 202: @3566
2202
119
    GIM_Try, /*On fail goto*//*Label 218*/ 3597, // Rule ID 483 //
2203
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2204
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2205
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2206
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2207
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2208
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2209
119
      // (and:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (AND_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2210
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V,
2211
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2212
119
      // GIR_Coverage, 483,
2213
119
      GIR_Done,
2214
119
    // Label 218: @3597
2215
119
    GIM_Reject,
2216
119
    // Label 203: @3598
2217
119
    GIM_Reject,
2218
119
    // Label 8: @3599
2219
119
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 225*/ 3900,
2220
119
    /*GILLT_s32*//*Label 219*/ 3613,
2221
119
    /*GILLT_s64*//*Label 220*/ 3740, 0,
2222
119
    /*GILLT_v2s64*//*Label 221*/ 3772, 0,
2223
119
    /*GILLT_v4s32*//*Label 222*/ 3804,
2224
119
    /*GILLT_v8s16*//*Label 223*/ 3836,
2225
119
    /*GILLT_v16s8*//*Label 224*/ 3868,
2226
119
    // Label 219: @3613
2227
119
    GIM_Try, /*On fail goto*//*Label 226*/ 3739,
2228
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2229
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2230
119
      GIM_Try, /*On fail goto*//*Label 227*/ 3646, // Rule ID 40 //
2231
119
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2232
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2233
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2234
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2235
119
        // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (OR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2236
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR,
2237
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2238
119
        // GIR_Coverage, 40,
2239
119
        GIR_Done,
2240
119
      // Label 227: @3646
2241
119
      GIM_Try, /*On fail goto*//*Label 228*/ 3669, // Rule ID 1031 //
2242
119
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2243
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2244
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2245
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
2246
119
        // (or:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (OR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2247
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR16_MM,
2248
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2249
119
        // GIR_Coverage, 1031,
2250
119
        GIR_Done,
2251
119
      // Label 228: @3669
2252
119
      GIM_Try, /*On fail goto*//*Label 229*/ 3692, // Rule ID 1046 //
2253
119
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2254
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2255
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2256
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2257
119
        // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (OR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2258
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_MM,
2259
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2260
119
        // GIR_Coverage, 1046,
2261
119
        GIR_Done,
2262
119
      // Label 229: @3692
2263
119
      GIM_Try, /*On fail goto*//*Label 230*/ 3715, // Rule ID 1149 //
2264
119
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2265
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2266
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2267
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2268
119
        // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (OR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2269
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_MMR6,
2270
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2271
119
        // GIR_Coverage, 1149,
2272
119
        GIR_Done,
2273
119
      // Label 230: @3715
2274
119
      GIM_Try, /*On fail goto*//*Label 231*/ 3738, // Rule ID 1747 //
2275
119
        GIM_CheckFeatures, GIFBS_InMips16Mode,
2276
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2277
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2278
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
2279
119
        // (or:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (OrRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2280
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OrRxRxRy16,
2281
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2282
119
        // GIR_Coverage, 1747,
2283
119
        GIR_Done,
2284
119
      // Label 231: @3738
2285
119
      GIM_Reject,
2286
119
    // Label 226: @3739
2287
119
    GIM_Reject,
2288
119
    // Label 220: @3740
2289
119
    GIM_Try, /*On fail goto*//*Label 232*/ 3771, // Rule ID 185 //
2290
119
      GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2291
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2292
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2293
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2294
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2295
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2296
119
      // (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (OR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2297
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR64,
2298
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2299
119
      // GIR_Coverage, 185,
2300
119
      GIR_Done,
2301
119
    // Label 232: @3771
2302
119
    GIM_Reject,
2303
119
    // Label 221: @3772
2304
119
    GIM_Try, /*On fail goto*//*Label 233*/ 3803, // Rule ID 892 //
2305
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2306
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2307
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2308
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2309
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
2310
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
2311
119
      // (or:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (OR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2312
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_D_PSEUDO,
2313
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2314
119
      // GIR_Coverage, 892,
2315
119
      GIR_Done,
2316
119
    // Label 233: @3803
2317
119
    GIM_Reject,
2318
119
    // Label 222: @3804
2319
119
    GIM_Try, /*On fail goto*//*Label 234*/ 3835, // Rule ID 891 //
2320
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2321
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2322
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2323
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2324
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2325
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2326
119
      // (or:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (OR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2327
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_W_PSEUDO,
2328
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2329
119
      // GIR_Coverage, 891,
2330
119
      GIR_Done,
2331
119
    // Label 234: @3835
2332
119
    GIM_Reject,
2333
119
    // Label 223: @3836
2334
119
    GIM_Try, /*On fail goto*//*Label 235*/ 3867, // Rule ID 890 //
2335
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2336
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2337
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2338
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2339
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2340
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2341
119
      // (or:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (OR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2342
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_H_PSEUDO,
2343
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2344
119
      // GIR_Coverage, 890,
2345
119
      GIR_Done,
2346
119
    // Label 235: @3867
2347
119
    GIM_Reject,
2348
119
    // Label 224: @3868
2349
119
    GIM_Try, /*On fail goto*//*Label 236*/ 3899, // Rule ID 889 //
2350
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2351
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2352
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2353
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2354
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2355
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2356
119
      // (or:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (OR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2357
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V,
2358
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2359
119
      // GIR_Coverage, 889,
2360
119
      GIR_Done,
2361
119
    // Label 236: @3899
2362
119
    GIM_Reject,
2363
119
    // Label 225: @3900
2364
119
    GIM_Reject,
2365
119
    // Label 9: @3901
2366
119
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 243*/ 4694,
2367
119
    /*GILLT_s32*//*Label 237*/ 3915,
2368
119
    /*GILLT_s64*//*Label 238*/ 4478, 0,
2369
119
    /*GILLT_v2s64*//*Label 239*/ 4566, 0,
2370
119
    /*GILLT_v4s32*//*Label 240*/ 4598,
2371
119
    /*GILLT_v8s16*//*Label 241*/ 4630,
2372
119
    /*GILLT_v16s8*//*Label 242*/ 4662,
2373
119
    // Label 237: @3915
2374
119
    GIM_Try, /*On fail goto*//*Label 244*/ 4477,
2375
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2376
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
2377
119
      GIM_Try, /*On fail goto*//*Label 245*/ 3982, // Rule ID 42 //
2378
119
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2379
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2380
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2381
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2382
119
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2383
119
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2384
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2385
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2386
119
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2387
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2388
119
        // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] })  =>  (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2389
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
2390
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2391
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2392
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2393
119
        GIR_EraseFromParent, /*InsnID*/0,
2394
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2395
119
        // GIR_Coverage, 42,
2396
119
        GIR_Done,
2397
119
      // Label 245: @3982
2398
119
      GIM_Try, /*On fail goto*//*Label 246*/ 4039, // Rule ID 1048 //
2399
119
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2400
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2401
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2402
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2403
119
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2404
119
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2405
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2406
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2407
119
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2408
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2409
119
        // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] })  =>  (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2410
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MM,
2411
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2412
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2413
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2414
119
        GIR_EraseFromParent, /*InsnID*/0,
2415
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2416
119
        // GIR_Coverage, 1048,
2417
119
        GIR_Done,
2418
119
      // Label 246: @4039
2419
119
      GIM_Try, /*On fail goto*//*Label 247*/ 4096, // Rule ID 1148 //
2420
119
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2421
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2422
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2423
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2424
119
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2425
119
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2426
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2427
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2428
119
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2429
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2430
119
        // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] })  =>  (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2431
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
2432
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2433
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2434
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2435
119
        GIR_EraseFromParent, /*InsnID*/0,
2436
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2437
119
        // GIR_Coverage, 1148,
2438
119
        GIR_Done,
2439
119
      // Label 247: @4096
2440
119
      GIM_Try, /*On fail goto*//*Label 248*/ 4128, // Rule ID 1175 //
2441
119
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2442
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2443
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2444
119
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2445
119
        // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })  =>  (NOT16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2446
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MMR6,
2447
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2448
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
2449
119
        GIR_EraseFromParent, /*InsnID*/0,
2450
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2451
119
        // GIR_Coverage, 1175,
2452
119
        GIR_Done,
2453
119
      // Label 248: @4128
2454
119
      GIM_Try, /*On fail goto*//*Label 249*/ 4160, // Rule ID 1030 //
2455
119
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2456
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2457
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2458
119
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2459
119
        // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })  =>  (NOT16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2460
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MM,
2461
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2462
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
2463
119
        GIR_EraseFromParent, /*InsnID*/0,
2464
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2465
119
        // GIR_Coverage, 1030,
2466
119
        GIR_Done,
2467
119
      // Label 249: @4160
2468
119
      GIM_Try, /*On fail goto*//*Label 250*/ 4195, // Rule ID 1362 //
2469
119
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2470
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2471
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2472
119
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2473
119
        // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2474
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
2475
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2476
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2477
119
        GIR_AddRegister, /*InsnID*/0, Mips::ZERO,
2478
119
        GIR_EraseFromParent, /*InsnID*/0,
2479
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2480
119
        // GIR_Coverage, 1362,
2481
119
        GIR_Done,
2482
119
      // Label 250: @4195
2483
119
      GIM_Try, /*On fail goto*//*Label 251*/ 4227, // Rule ID 1742 //
2484
119
        GIM_CheckFeatures, GIFBS_InMips16Mode,
2485
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2486
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2487
119
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2488
119
        // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, -1:{ *:[i32] })  =>  (NotRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
2489
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NotRxRy16,
2490
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
2491
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // r
2492
119
        GIR_EraseFromParent, /*InsnID*/0,
2493
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2494
119
        // GIR_Coverage, 1742,
2495
119
        GIR_Done,
2496
119
      // Label 251: @4227
2497
119
      GIM_Try, /*On fail goto*//*Label 252*/ 4259, // Rule ID 2081 //
2498
119
        GIM_CheckFeatures, GIFBS_InMicroMips,
2499
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2500
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2501
119
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2502
119
        // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOT16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2503
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MM,
2504
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2505
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2506
119
        GIR_EraseFromParent, /*InsnID*/0,
2507
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2508
119
        // GIR_Coverage, 2081,
2509
119
        GIR_Done,
2510
119
      // Label 252: @4259
2511
119
      GIM_Try, /*On fail goto*//*Label 253*/ 4294, // Rule ID 2082 //
2512
119
        GIM_CheckFeatures, GIFBS_InMicroMips,
2513
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2514
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2515
119
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2516
119
        // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2517
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MM,
2518
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2519
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2520
119
        GIR_AddRegister, /*InsnID*/0, Mips::ZERO,
2521
119
        GIR_EraseFromParent, /*InsnID*/0,
2522
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2523
119
        // GIR_Coverage, 2082,
2524
119
        GIR_Done,
2525
119
      // Label 253: @4294
2526
119
      GIM_Try, /*On fail goto*//*Label 254*/ 4326, // Rule ID 2242 //
2527
119
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2528
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2529
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2530
119
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2531
119
        // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOT16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2532
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MMR6,
2533
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
2534
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2535
119
        GIR_EraseFromParent, /*InsnID*/0,
2536
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2537
119
        // GIR_Coverage, 2242,
2538
119
        GIR_Done,
2539
119
      // Label 254: @4326
2540
119
      GIM_Try, /*On fail goto*//*Label 255*/ 4361, // Rule ID 2243 //
2541
119
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2542
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2543
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2544
119
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2545
119
        // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2546
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
2547
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2548
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
2549
119
        GIR_AddRegister, /*InsnID*/0, Mips::ZERO,
2550
119
        GIR_EraseFromParent, /*InsnID*/0,
2551
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2552
119
        // GIR_Coverage, 2243,
2553
119
        GIR_Done,
2554
119
      // Label 255: @4361
2555
119
      GIM_Try, /*On fail goto*//*Label 256*/ 4384, // Rule ID 41 //
2556
119
        GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
2557
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2558
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2559
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2560
119
        // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (XOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2561
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR,
2562
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2563
119
        // GIR_Coverage, 41,
2564
119
        GIR_Done,
2565
119
      // Label 256: @4384
2566
119
      GIM_Try, /*On fail goto*//*Label 257*/ 4407, // Rule ID 1033 //
2567
119
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2568
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
2569
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
2570
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
2571
119
        // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (XOR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2572
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR16_MM,
2573
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2574
119
        // GIR_Coverage, 1033,
2575
119
        GIR_Done,
2576
119
      // Label 257: @4407
2577
119
      GIM_Try, /*On fail goto*//*Label 258*/ 4430, // Rule ID 1047 //
2578
119
        GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
2579
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2580
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2581
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2582
119
        // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (XOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2583
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_MM,
2584
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2585
119
        // GIR_Coverage, 1047,
2586
119
        GIR_Done,
2587
119
      // Label 258: @4430
2588
119
      GIM_Try, /*On fail goto*//*Label 259*/ 4453, // Rule ID 1152 //
2589
119
        GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
2590
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2591
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2592
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
2593
119
        // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (XOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2594
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_MMR6,
2595
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2596
119
        // GIR_Coverage, 1152,
2597
119
        GIR_Done,
2598
119
      // Label 259: @4453
2599
119
      GIM_Try, /*On fail goto*//*Label 260*/ 4476, // Rule ID 1749 //
2600
119
        GIM_CheckFeatures, GIFBS_InMips16Mode,
2601
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
2602
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
2603
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
2604
119
        // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2605
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XorRxRxRy16,
2606
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2607
119
        // GIR_Coverage, 1749,
2608
119
        GIR_Done,
2609
119
      // Label 260: @4476
2610
119
      GIM_Reject,
2611
119
    // Label 244: @4477
2612
119
    GIM_Reject,
2613
119
    // Label 238: @4478
2614
119
    GIM_Try, /*On fail goto*//*Label 261*/ 4565,
2615
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2616
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
2617
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2618
119
      GIM_Try, /*On fail goto*//*Label 262*/ 4545, // Rule ID 187 //
2619
119
        GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2620
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2621
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
2622
119
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2623
119
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2624
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2625
119
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2626
119
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
2627
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
2628
119
        // (xor:{ *:[i64] } (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), -1:{ *:[i64] })  =>  (NOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2629
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR64,
2630
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
2631
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2632
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2633
119
        GIR_EraseFromParent, /*InsnID*/0,
2634
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2635
119
        // GIR_Coverage, 187,
2636
119
        GIR_Done,
2637
119
      // Label 262: @4545
2638
119
      GIM_Try, /*On fail goto*//*Label 263*/ 4564, // Rule ID 186 //
2639
119
        GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
2640
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2641
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
2642
119
        // (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (XOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2643
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR64,
2644
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2645
119
        // GIR_Coverage, 186,
2646
119
        GIR_Done,
2647
119
      // Label 263: @4564
2648
119
      GIM_Reject,
2649
119
    // Label 261: @4565
2650
119
    GIM_Reject,
2651
119
    // Label 239: @4566
2652
119
    GIM_Try, /*On fail goto*//*Label 264*/ 4597, // Rule ID 1008 //
2653
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2654
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2655
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
2656
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2657
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
2658
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
2659
119
      // (xor:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (XOR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2660
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_D_PSEUDO,
2661
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2662
119
      // GIR_Coverage, 1008,
2663
119
      GIR_Done,
2664
119
    // Label 264: @4597
2665
119
    GIM_Reject,
2666
119
    // Label 240: @4598
2667
119
    GIM_Try, /*On fail goto*//*Label 265*/ 4629, // Rule ID 1007 //
2668
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2669
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2670
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2671
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
2672
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
2673
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
2674
119
      // (xor:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (XOR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2675
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_W_PSEUDO,
2676
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2677
119
      // GIR_Coverage, 1007,
2678
119
      GIR_Done,
2679
119
    // Label 265: @4629
2680
119
    GIM_Reject,
2681
119
    // Label 241: @4630
2682
119
    GIM_Try, /*On fail goto*//*Label 266*/ 4661, // Rule ID 1006 //
2683
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2684
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2685
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2686
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
2687
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
2688
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
2689
119
      // (xor:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (XOR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2690
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_H_PSEUDO,
2691
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2692
119
      // GIR_Coverage, 1006,
2693
119
      GIR_Done,
2694
119
    // Label 266: @4661
2695
119
    GIM_Reject,
2696
119
    // Label 242: @4662
2697
119
    GIM_Try, /*On fail goto*//*Label 267*/ 4693, // Rule ID 1005 //
2698
119
      GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
2699
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2700
119
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
2701
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
2702
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
2703
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
2704
119
      // (xor:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (XOR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2705
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V,
2706
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2707
119
      // GIR_Coverage, 1005,
2708
119
      GIR_Done,
2709
119
    // Label 267: @4693
2710
119
    GIM_Reject,
2711
119
    // Label 243: @4694
2712
119
    GIM_Reject,
2713
119
    // Label 10: @4695
2714
119
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 276*/ 8347,
2715
119
    /*GILLT_s32*//*Label 268*/ 4709,
2716
119
    /*GILLT_s64*//*Label 269*/ 4948,
2717
119
    /*GILLT_v2s16*//*Label 270*/ 4994,
2718
119
    /*GILLT_v2s64*//*Label 271*/ 5040,
2719
119
    /*GILLT_v4s8*//*Label 272*/ 6013,
2720
119
    /*GILLT_v4s32*//*Label 273*/ 6059,
2721
119
    /*GILLT_v8s16*//*Label 274*/ 6962,
2722
119
    /*GILLT_v16s8*//*Label 275*/ 7760,
2723
119
    // Label 268: @4709
2724
119
    GIM_Try, /*On fail goto*//*Label 277*/ 4732, // Rule ID 117 //
2725
119
      GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
2726
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2727
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2728
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
2729
119
      // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (MFC1:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
2730
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1,
2731
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2732
119
      // GIR_Coverage, 117,
2733
119
      GIR_Done,
2734
119
    // Label 277: @4732
2735
119
    GIM_Try, /*On fail goto*//*Label 278*/ 4755, // Rule ID 118 //
2736
119
      GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
2737
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2738
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2739
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2740
119
      // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)  =>  (MTC1:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
2741
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1,
2742
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2743
119
      // GIR_Coverage, 118,
2744
119
      GIR_Done,
2745
119
    // Label 278: @4755
2746
119
    GIM_Try, /*On fail goto*//*Label 279*/ 4778, // Rule ID 1128 //
2747
119
      GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
2748
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2749
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2750
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
2751
119
      // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (MFC1_MM:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
2752
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1_MM,
2753
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2754
119
      // GIR_Coverage, 1128,
2755
119
      GIR_Done,
2756
119
    // Label 279: @4778
2757
119
    GIM_Try, /*On fail goto*//*Label 280*/ 4801, // Rule ID 1129 //
2758
119
      GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
2759
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2760
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2761
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2762
119
      // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)  =>  (MTC1_MM:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
2763
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1_MM,
2764
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2765
119
      // GIR_Coverage, 1129,
2766
119
      GIR_Done,
2767
119
    // Label 280: @4801
2768
119
    GIM_Try, /*On fail goto*//*Label 281*/ 4824, // Rule ID 1141 //
2769
119
      GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
2770
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2771
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2772
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2773
119
      // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)  =>  (MTC1_MMR6:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
2774
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1_MMR6,
2775
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2776
119
      // GIR_Coverage, 1141,
2777
119
      GIR_Done,
2778
119
    // Label 281: @4824
2779
119
    GIM_Try, /*On fail goto*//*Label 282*/ 4847, // Rule ID 1142 //
2780
119
      GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
2781
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2782
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2783
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
2784
119
      // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (MFC1_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
2785
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1_MMR6,
2786
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2787
119
      // GIR_Coverage, 1142,
2788
119
      GIR_Done,
2789
119
    // Label 282: @4847
2790
119
    GIM_Try, /*On fail goto*//*Label 283*/ 4872, // Rule ID 1830 //
2791
119
      GIM_CheckFeatures, GIFBS_HasDSP,
2792
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
2793
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2794
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
2795
119
      // (bitconvert:{ *:[i32] } DSPR:{ *:[v2i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v2i16] }:$src, GPR32:{ *:[i32] })
2796
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2797
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR32*/11,
2798
119
      // GIR_Coverage, 1830,
2799
119
      GIR_Done,
2800
119
    // Label 283: @4872
2801
119
    GIM_Try, /*On fail goto*//*Label 284*/ 4897, // Rule ID 1831 //
2802
119
      GIM_CheckFeatures, GIFBS_HasDSP,
2803
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
2804
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
2805
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
2806
119
      // (bitconvert:{ *:[i32] } DSPR:{ *:[v4i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v4i8] }:$src, GPR32:{ *:[i32] })
2807
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2808
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR32*/11,
2809
119
      // GIR_Coverage, 1831,
2810
119
      GIR_Done,
2811
119
    // Label 284: @4897
2812
119
    GIM_Try, /*On fail goto*//*Label 285*/ 4922, // Rule ID 1834 //
2813
119
      GIM_CheckFeatures, GIFBS_HasDSP,
2814
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
2815
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2816
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
2817
119
      // (bitconvert:{ *:[f32] } DSPR:{ *:[v2i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v2i16] }:$src, FGR32:{ *:[i32] })
2818
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2819
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FGR32*/8,
2820
119
      // GIR_Coverage, 1834,
2821
119
      GIR_Done,
2822
119
    // Label 285: @4922
2823
119
    GIM_Try, /*On fail goto*//*Label 286*/ 4947, // Rule ID 1835 //
2824
119
      GIM_CheckFeatures, GIFBS_HasDSP,
2825
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
2826
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
2827
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
2828
119
      // (bitconvert:{ *:[f32] } DSPR:{ *:[v4i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v4i8] }:$src, FGR32:{ *:[i32] })
2829
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2830
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FGR32*/8,
2831
119
      // GIR_Coverage, 1835,
2832
119
      GIR_Done,
2833
119
    // Label 286: @4947
2834
119
    GIM_Reject,
2835
119
    // Label 269: @4948
2836
119
    GIM_Try, /*On fail goto*//*Label 287*/ 4993,
2837
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
2838
119
      GIM_Try, /*On fail goto*//*Label 288*/ 4973, // Rule ID 119 //
2839
119
        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
2840
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
2841
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
2842
119
        // (bitconvert:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMTC1:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt)
2843
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMTC1,
2844
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2845
119
        // GIR_Coverage, 119,
2846
119
        GIR_Done,
2847
119
      // Label 288: @4973
2848
119
      GIM_Try, /*On fail goto*//*Label 289*/ 4992, // Rule ID 120 //
2849
119
        GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
2850
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
2851
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
2852
119
        // (bitconvert:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (DMFC1:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs)
2853
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMFC1,
2854
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2855
119
        // GIR_Coverage, 120,
2856
119
        GIR_Done,
2857
119
      // Label 289: @4992
2858
119
      GIM_Reject,
2859
119
    // Label 287: @4993
2860
119
    GIM_Reject,
2861
119
    // Label 270: @4994
2862
119
    GIM_Try, /*On fail goto*//*Label 290*/ 5039,
2863
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
2864
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
2865
119
      GIM_Try, /*On fail goto*//*Label 291*/ 5021, // Rule ID 1832 //
2866
119
        GIM_CheckFeatures, GIFBS_HasDSP,
2867
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
2868
119
        // (bitconvert:{ *:[v2i16] } GPR32:{ *:[i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i16] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
2869
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2870
119
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
2871
119
        // GIR_Coverage, 1832,
2872
119
        GIR_Done,
2873
119
      // Label 291: @5021
2874
119
      GIM_Try, /*On fail goto*//*Label 292*/ 5038, // Rule ID 1836 //
2875
119
        GIM_CheckFeatures, GIFBS_HasDSP,
2876
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
2877
119
        // (bitconvert:{ *:[v2i16] } FGR32:{ *:[f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i16] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
2878
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2879
119
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
2880
119
        // GIR_Coverage, 1836,
2881
119
        GIR_Done,
2882
119
      // Label 292: @5038
2883
119
      GIM_Reject,
2884
119
    // Label 290: @5039
2885
119
    GIM_Reject,
2886
119
    // Label 271: @5040
2887
119
    GIM_Try, /*On fail goto*//*Label 293*/ 5061, // Rule ID 1917 //
2888
119
      GIM_CheckFeatures, GIFBS_HasMSA,
2889
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2890
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2891
119
      // (bitconvert:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src, MSA128D:{ *:[i32] })
2892
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2893
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2894
119
      // GIR_Coverage, 1917,
2895
119
      GIR_Done,
2896
119
    // Label 293: @5061
2897
119
    GIM_Try, /*On fail goto*//*Label 294*/ 5082, // Rule ID 1920 //
2898
119
      GIM_CheckFeatures, GIFBS_HasMSA,
2899
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
2900
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2901
119
      // (bitconvert:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src, MSA128D:{ *:[i32] })
2902
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2903
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2904
119
      // GIR_Coverage, 1920,
2905
119
      GIR_Done,
2906
119
    // Label 294: @5082
2907
119
    GIM_Try, /*On fail goto*//*Label 295*/ 5103, // Rule ID 1937 //
2908
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2909
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2910
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2911
119
      // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
2912
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2913
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2914
119
      // GIR_Coverage, 1937,
2915
119
      GIR_Done,
2916
119
    // Label 295: @5103
2917
119
    GIM_Try, /*On fail goto*//*Label 296*/ 5124, // Rule ID 1938 //
2918
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2919
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2920
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2921
119
      // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
2922
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2923
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2924
119
      // GIR_Coverage, 1938,
2925
119
      GIR_Done,
2926
119
    // Label 296: @5124
2927
119
    GIM_Try, /*On fail goto*//*Label 297*/ 5145, // Rule ID 1939 //
2928
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2929
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2930
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2931
119
      // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
2932
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2933
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2934
119
      // GIR_Coverage, 1939,
2935
119
      GIR_Done,
2936
119
    // Label 297: @5145
2937
119
    GIM_Try, /*On fail goto*//*Label 298*/ 5166, // Rule ID 1940 //
2938
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2939
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2940
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2941
119
      // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
2942
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2943
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2944
119
      // GIR_Coverage, 1940,
2945
119
      GIR_Done,
2946
119
    // Label 298: @5166
2947
119
    GIM_Try, /*On fail goto*//*Label 299*/ 5187, // Rule ID 1941 //
2948
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2949
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2950
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2951
119
      // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
2952
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2953
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2954
119
      // GIR_Coverage, 1941,
2955
119
      GIR_Done,
2956
119
    // Label 299: @5187
2957
119
    GIM_Try, /*On fail goto*//*Label 300*/ 5208, // Rule ID 1947 //
2958
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2959
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
2960
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2961
119
      // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
2962
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2963
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2964
119
      // GIR_Coverage, 1947,
2965
119
      GIR_Done,
2966
119
    // Label 300: @5208
2967
119
    GIM_Try, /*On fail goto*//*Label 301*/ 5229, // Rule ID 1948 //
2968
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2969
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2970
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2971
119
      // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
2972
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2973
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2974
119
      // GIR_Coverage, 1948,
2975
119
      GIR_Done,
2976
119
    // Label 301: @5229
2977
119
    GIM_Try, /*On fail goto*//*Label 302*/ 5250, // Rule ID 1949 //
2978
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2979
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2980
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2981
119
      // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
2982
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2983
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2984
119
      // GIR_Coverage, 1949,
2985
119
      GIR_Done,
2986
119
    // Label 302: @5250
2987
119
    GIM_Try, /*On fail goto*//*Label 303*/ 5271, // Rule ID 1950 //
2988
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2989
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2990
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
2991
119
      // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
2992
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2993
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
2994
119
      // GIR_Coverage, 1950,
2995
119
      GIR_Done,
2996
119
    // Label 303: @5271
2997
119
    GIM_Try, /*On fail goto*//*Label 304*/ 5292, // Rule ID 1951 //
2998
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
2999
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3000
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3001
119
      // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
3002
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3003
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3004
119
      // GIR_Coverage, 1951,
3005
119
      GIR_Done,
3006
119
    // Label 304: @5292
3007
119
    GIM_Try, /*On fail goto*//*Label 305*/ 5392, // Rule ID 1956 //
3008
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3009
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3010
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3011
119
      // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3012
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3013
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3014
119
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3015
119
      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3016
119
      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
3017
119
      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
3018
119
      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3019
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
3020
119
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
3021
119
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3022
119
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
3023
119
      GIR_AddImm, /*InsnID*/3, /*Imm*/27,
3024
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3025
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3026
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3027
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
3028
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3029
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3030
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3031
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3032
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3033
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3034
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3035
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3036
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3037
119
      GIR_EraseFromParent, /*InsnID*/0,
3038
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3039
119
      // GIR_Coverage, 1956,
3040
119
      GIR_Done,
3041
119
    // Label 305: @5392
3042
119
    GIM_Try, /*On fail goto*//*Label 306*/ 5492, // Rule ID 1957 //
3043
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3044
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3045
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3046
119
      // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3047
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3048
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3049
119
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3050
119
      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3051
119
      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
3052
119
      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
3053
119
      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3054
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
3055
119
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
3056
119
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3057
119
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
3058
119
      GIR_AddImm, /*InsnID*/3, /*Imm*/27,
3059
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3060
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3061
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3062
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
3063
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3064
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3065
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3066
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3067
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3068
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3069
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3070
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3071
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3072
119
      GIR_EraseFromParent, /*InsnID*/0,
3073
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3074
119
      // GIR_Coverage, 1957,
3075
119
      GIR_Done,
3076
119
    // Label 306: @5492
3077
119
    GIM_Try, /*On fail goto*//*Label 307*/ 5557, // Rule ID 1961 //
3078
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3079
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3080
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3081
119
      // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3082
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3083
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3084
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3085
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3086
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3087
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3088
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3089
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3090
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3091
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3092
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3093
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3094
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3095
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3096
119
      GIR_EraseFromParent, /*InsnID*/0,
3097
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3098
119
      // GIR_Coverage, 1961,
3099
119
      GIR_Done,
3100
119
    // Label 307: @5557
3101
119
    GIM_Try, /*On fail goto*//*Label 308*/ 5622, // Rule ID 1962 //
3102
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3103
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3104
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3105
119
      // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3106
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3107
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3108
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3109
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3110
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3111
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3112
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3113
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3114
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3115
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3116
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3117
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3118
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3119
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3120
119
      GIR_EraseFromParent, /*InsnID*/0,
3121
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3122
119
      // GIR_Coverage, 1962,
3123
119
      GIR_Done,
3124
119
    // Label 308: @5622
3125
119
    GIM_Try, /*On fail goto*//*Label 309*/ 5687, // Rule ID 1966 //
3126
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3127
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3128
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3129
119
      // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3130
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3131
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3132
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3133
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3134
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3135
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3136
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3137
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3138
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3139
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3140
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3141
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3142
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3143
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3144
119
      GIR_EraseFromParent, /*InsnID*/0,
3145
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3146
119
      // GIR_Coverage, 1966,
3147
119
      GIR_Done,
3148
119
    // Label 309: @5687
3149
119
    GIM_Try, /*On fail goto*//*Label 310*/ 5752, // Rule ID 1967 //
3150
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3151
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3152
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3153
119
      // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3154
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3155
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3156
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3157
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3158
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3159
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3160
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3161
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3162
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3163
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3164
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3165
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3166
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3167
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3168
119
      GIR_EraseFromParent, /*InsnID*/0,
3169
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3170
119
      // GIR_Coverage, 1967,
3171
119
      GIR_Done,
3172
119
    // Label 310: @5752
3173
119
    GIM_Try, /*On fail goto*//*Label 311*/ 5817, // Rule ID 1971 //
3174
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3175
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3176
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3177
119
      // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3178
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3179
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3180
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3181
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3182
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3183
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3184
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3185
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3186
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3187
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3188
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3189
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3190
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3191
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3192
119
      GIR_EraseFromParent, /*InsnID*/0,
3193
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3194
119
      // GIR_Coverage, 1971,
3195
119
      GIR_Done,
3196
119
    // Label 311: @5817
3197
119
    GIM_Try, /*On fail goto*//*Label 312*/ 5882, // Rule ID 1972 //
3198
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3199
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3200
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3201
119
      // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3202
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3203
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3204
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3205
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3206
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3207
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3208
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3209
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3210
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3211
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3212
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3213
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3214
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3215
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3216
119
      GIR_EraseFromParent, /*InsnID*/0,
3217
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3218
119
      // GIR_Coverage, 1972,
3219
119
      GIR_Done,
3220
119
    // Label 312: @5882
3221
119
    GIM_Try, /*On fail goto*//*Label 313*/ 5947, // Rule ID 1976 //
3222
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3223
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3224
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3225
119
      // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3226
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3227
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3228
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3229
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3230
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3231
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3232
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3233
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3234
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3235
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3236
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3237
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3238
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3239
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3240
119
      GIR_EraseFromParent, /*InsnID*/0,
3241
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3242
119
      // GIR_Coverage, 1976,
3243
119
      GIR_Done,
3244
119
    // Label 313: @5947
3245
119
    GIM_Try, /*On fail goto*//*Label 314*/ 6012, // Rule ID 1977 //
3246
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3247
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3248
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
3249
119
      // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3250
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3251
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3252
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3253
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3254
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3255
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3256
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3257
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3258
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3259
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3260
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3261
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3262
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3263
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3264
119
      GIR_EraseFromParent, /*InsnID*/0,
3265
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/75,
3266
119
      // GIR_Coverage, 1977,
3267
119
      GIR_Done,
3268
119
    // Label 314: @6012
3269
119
    GIM_Reject,
3270
119
    // Label 272: @6013
3271
119
    GIM_Try, /*On fail goto*//*Label 315*/ 6058,
3272
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3273
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
3274
119
      GIM_Try, /*On fail goto*//*Label 316*/ 6040, // Rule ID 1833 //
3275
119
        GIM_CheckFeatures, GIFBS_HasDSP,
3276
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
3277
119
        // (bitconvert:{ *:[v4i8] } GPR32:{ *:[i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i8] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
3278
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3279
119
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
3280
119
        // GIR_Coverage, 1833,
3281
119
        GIR_Done,
3282
119
      // Label 316: @6040
3283
119
      GIM_Try, /*On fail goto*//*Label 317*/ 6057, // Rule ID 1837 //
3284
119
        GIM_CheckFeatures, GIFBS_HasDSP,
3285
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
3286
119
        // (bitconvert:{ *:[v4i8] } FGR32:{ *:[f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i8] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
3287
119
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3288
119
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
3289
119
        // GIR_Coverage, 1837,
3290
119
        GIR_Done,
3291
119
      // Label 317: @6057
3292
119
      GIM_Reject,
3293
119
    // Label 315: @6058
3294
119
    GIM_Reject,
3295
119
    // Label 273: @6059
3296
119
    GIM_Try, /*On fail goto*//*Label 318*/ 6080, // Rule ID 1916 //
3297
119
      GIM_CheckFeatures, GIFBS_HasMSA,
3298
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3299
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3300
119
      // (bitconvert:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] })
3301
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3302
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3303
119
      // GIR_Coverage, 1916,
3304
119
      GIR_Done,
3305
119
    // Label 318: @6080
3306
119
    GIM_Try, /*On fail goto*//*Label 319*/ 6101, // Rule ID 1919 //
3307
119
      GIM_CheckFeatures, GIFBS_HasMSA,
3308
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3309
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3310
119
      // (bitconvert:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] })
3311
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3312
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3313
119
      // GIR_Coverage, 1919,
3314
119
      GIR_Done,
3315
119
    // Label 319: @6101
3316
119
    GIM_Try, /*On fail goto*//*Label 320*/ 6122, // Rule ID 1932 //
3317
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3318
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3319
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3320
119
      // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3321
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3322
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3323
119
      // GIR_Coverage, 1932,
3324
119
      GIR_Done,
3325
119
    // Label 320: @6122
3326
119
    GIM_Try, /*On fail goto*//*Label 321*/ 6143, // Rule ID 1933 //
3327
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3328
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3329
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3330
119
      // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3331
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3332
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3333
119
      // GIR_Coverage, 1933,
3334
119
      GIR_Done,
3335
119
    // Label 321: @6143
3336
119
    GIM_Try, /*On fail goto*//*Label 322*/ 6164, // Rule ID 1934 //
3337
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3338
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3339
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3340
119
      // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3341
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3342
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3343
119
      // GIR_Coverage, 1934,
3344
119
      GIR_Done,
3345
119
    // Label 322: @6164
3346
119
    GIM_Try, /*On fail goto*//*Label 323*/ 6185, // Rule ID 1935 //
3347
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3348
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3349
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3350
119
      // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3351
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3352
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3353
119
      // GIR_Coverage, 1935,
3354
119
      GIR_Done,
3355
119
    // Label 323: @6185
3356
119
    GIM_Try, /*On fail goto*//*Label 324*/ 6206, // Rule ID 1936 //
3357
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3358
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3359
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3360
119
      // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3361
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3362
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3363
119
      // GIR_Coverage, 1936,
3364
119
      GIR_Done,
3365
119
    // Label 324: @6206
3366
119
    GIM_Try, /*On fail goto*//*Label 325*/ 6227, // Rule ID 1942 //
3367
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3368
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3369
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3370
119
      // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3371
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3372
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3373
119
      // GIR_Coverage, 1942,
3374
119
      GIR_Done,
3375
119
    // Label 325: @6227
3376
119
    GIM_Try, /*On fail goto*//*Label 326*/ 6248, // Rule ID 1943 //
3377
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3378
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3379
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3380
119
      // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3381
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3382
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3383
119
      // GIR_Coverage, 1943,
3384
119
      GIR_Done,
3385
119
    // Label 326: @6248
3386
119
    GIM_Try, /*On fail goto*//*Label 327*/ 6269, // Rule ID 1944 //
3387
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3388
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3389
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3390
119
      // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3391
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3392
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3393
119
      // GIR_Coverage, 1944,
3394
119
      GIR_Done,
3395
119
    // Label 327: @6269
3396
119
    GIM_Try, /*On fail goto*//*Label 328*/ 6290, // Rule ID 1945 //
3397
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3398
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3399
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3400
119
      // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3401
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3402
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3403
119
      // GIR_Coverage, 1945,
3404
119
      GIR_Done,
3405
119
    // Label 328: @6290
3406
119
    GIM_Try, /*On fail goto*//*Label 329*/ 6311, // Rule ID 1946 //
3407
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3408
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3409
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3410
119
      // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3411
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3412
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3413
119
      // GIR_Coverage, 1946,
3414
119
      GIR_Done,
3415
119
    // Label 329: @6311
3416
119
    GIM_Try, /*On fail goto*//*Label 330*/ 6376, // Rule ID 1954 //
3417
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3418
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3419
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3420
119
      // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3421
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3422
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3423
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3424
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3425
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3426
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3427
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3428
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3429
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3430
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3431
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3432
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3433
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3434
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3435
119
      GIR_EraseFromParent, /*InsnID*/0,
3436
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3437
119
      // GIR_Coverage, 1954,
3438
119
      GIR_Done,
3439
119
    // Label 330: @6376
3440
119
    GIM_Try, /*On fail goto*//*Label 331*/ 6441, // Rule ID 1955 //
3441
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3442
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3443
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3444
119
      // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3445
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3446
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3447
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3448
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3449
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3450
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3451
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3452
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3453
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3454
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3455
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3456
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3457
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3458
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3459
119
      GIR_EraseFromParent, /*InsnID*/0,
3460
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3461
119
      // GIR_Coverage, 1955,
3462
119
      GIR_Done,
3463
119
    // Label 331: @6441
3464
119
    GIM_Try, /*On fail goto*//*Label 332*/ 6506, // Rule ID 1959 //
3465
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3466
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3467
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3468
119
      // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3469
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3470
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3471
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3472
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3473
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3474
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3475
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3476
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3477
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3478
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3479
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3480
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3481
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3482
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3483
119
      GIR_EraseFromParent, /*InsnID*/0,
3484
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3485
119
      // GIR_Coverage, 1959,
3486
119
      GIR_Done,
3487
119
    // Label 332: @6506
3488
119
    GIM_Try, /*On fail goto*//*Label 333*/ 6571, // Rule ID 1960 //
3489
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3490
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3491
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3492
119
      // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3493
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3494
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3495
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3496
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3497
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3498
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3499
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3500
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3501
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3502
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3503
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3504
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3505
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3506
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3507
119
      GIR_EraseFromParent, /*InsnID*/0,
3508
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3509
119
      // GIR_Coverage, 1960,
3510
119
      GIR_Done,
3511
119
    // Label 333: @6571
3512
119
    GIM_Try, /*On fail goto*//*Label 334*/ 6636, // Rule ID 1964 //
3513
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3514
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3515
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3516
119
      // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3517
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3518
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3519
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3520
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3521
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3522
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3523
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3524
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3525
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3526
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3527
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3528
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3529
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3530
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3531
119
      GIR_EraseFromParent, /*InsnID*/0,
3532
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3533
119
      // GIR_Coverage, 1964,
3534
119
      GIR_Done,
3535
119
    // Label 334: @6636
3536
119
    GIM_Try, /*On fail goto*//*Label 335*/ 6701, // Rule ID 1965 //
3537
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3538
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3539
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3540
119
      // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3541
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3542
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3543
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3544
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3545
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3546
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3547
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3548
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3549
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3550
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3551
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3552
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3553
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3554
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3555
119
      GIR_EraseFromParent, /*InsnID*/0,
3556
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3557
119
      // GIR_Coverage, 1965,
3558
119
      GIR_Done,
3559
119
    // Label 335: @6701
3560
119
    GIM_Try, /*On fail goto*//*Label 336*/ 6766, // Rule ID 1981 //
3561
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3562
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3563
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3564
119
      // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3565
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3566
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3567
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3568
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3569
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3570
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3571
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3572
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3573
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3574
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3575
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3576
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3577
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3578
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3579
119
      GIR_EraseFromParent, /*InsnID*/0,
3580
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3581
119
      // GIR_Coverage, 1981,
3582
119
      GIR_Done,
3583
119
    // Label 336: @6766
3584
119
    GIM_Try, /*On fail goto*//*Label 337*/ 6831, // Rule ID 1982 //
3585
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3586
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3587
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3588
119
      // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3589
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3590
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3591
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3592
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3593
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3594
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3595
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3596
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3597
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3598
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3599
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3600
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3601
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3602
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3603
119
      GIR_EraseFromParent, /*InsnID*/0,
3604
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3605
119
      // GIR_Coverage, 1982,
3606
119
      GIR_Done,
3607
119
    // Label 337: @6831
3608
119
    GIM_Try, /*On fail goto*//*Label 338*/ 6896, // Rule ID 1986 //
3609
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3610
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3611
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3612
119
      // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3613
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3614
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3615
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3616
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3617
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3618
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3619
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3620
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3621
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3622
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3623
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3624
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3625
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3626
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3627
119
      GIR_EraseFromParent, /*InsnID*/0,
3628
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3629
119
      // GIR_Coverage, 1986,
3630
119
      GIR_Done,
3631
119
    // Label 338: @6896
3632
119
    GIM_Try, /*On fail goto*//*Label 339*/ 6961, // Rule ID 1987 //
3633
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3634
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3635
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
3636
119
      // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3637
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3638
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3639
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3640
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3641
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3642
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3643
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
3644
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3645
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3646
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3647
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3648
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3649
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3650
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3651
119
      GIR_EraseFromParent, /*InsnID*/0,
3652
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/77,
3653
119
      // GIR_Coverage, 1987,
3654
119
      GIR_Done,
3655
119
    // Label 339: @6961
3656
119
    GIM_Reject,
3657
119
    // Label 274: @6962
3658
119
    GIM_Try, /*On fail goto*//*Label 340*/ 6983, // Rule ID 1915 //
3659
119
      GIM_CheckFeatures, GIFBS_HasMSA,
3660
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3661
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3662
119
      // (bitconvert:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] })
3663
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3664
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3665
119
      // GIR_Coverage, 1915,
3666
119
      GIR_Done,
3667
119
    // Label 340: @6983
3668
119
    GIM_Try, /*On fail goto*//*Label 341*/ 7004, // Rule ID 1918 //
3669
119
      GIM_CheckFeatures, GIFBS_HasMSA,
3670
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3671
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3672
119
      // (bitconvert:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] })
3673
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3674
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3675
119
      // GIR_Coverage, 1918,
3676
119
      GIR_Done,
3677
119
    // Label 341: @7004
3678
119
    GIM_Try, /*On fail goto*//*Label 342*/ 7025, // Rule ID 1927 //
3679
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3680
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3681
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3682
119
      // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src, MSA128H:{ *:[i32] })
3683
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3684
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3685
119
      // GIR_Coverage, 1927,
3686
119
      GIR_Done,
3687
119
    // Label 342: @7025
3688
119
    GIM_Try, /*On fail goto*//*Label 343*/ 7046, // Rule ID 1928 //
3689
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3690
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3691
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3692
119
      // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] })
3693
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3694
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3695
119
      // GIR_Coverage, 1928,
3696
119
      GIR_Done,
3697
119
    // Label 343: @7046
3698
119
    GIM_Try, /*On fail goto*//*Label 344*/ 7067, // Rule ID 1929 //
3699
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3700
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3701
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3702
119
      // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] })
3703
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3704
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3705
119
      // GIR_Coverage, 1929,
3706
119
      GIR_Done,
3707
119
    // Label 344: @7067
3708
119
    GIM_Try, /*On fail goto*//*Label 345*/ 7088, // Rule ID 1930 //
3709
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3710
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3711
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3712
119
      // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] })
3713
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3714
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3715
119
      // GIR_Coverage, 1930,
3716
119
      GIR_Done,
3717
119
    // Label 345: @7088
3718
119
    GIM_Try, /*On fail goto*//*Label 346*/ 7109, // Rule ID 1931 //
3719
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3720
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3721
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3722
119
      // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] })
3723
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3724
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3725
119
      // GIR_Coverage, 1931,
3726
119
      GIR_Done,
3727
119
    // Label 346: @7109
3728
119
    GIM_Try, /*On fail goto*//*Label 347*/ 7174, // Rule ID 1952 //
3729
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3730
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3731
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3732
119
      // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3733
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3734
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3735
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3736
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3737
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3738
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3739
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3740
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3741
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3742
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3743
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3744
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3745
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3746
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3747
119
      GIR_EraseFromParent, /*InsnID*/0,
3748
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3749
119
      // GIR_Coverage, 1952,
3750
119
      GIR_Done,
3751
119
    // Label 347: @7174
3752
119
    GIM_Try, /*On fail goto*//*Label 348*/ 7239, // Rule ID 1953 //
3753
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3754
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3755
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3756
119
      // (bitconvert:{ *:[v8f16] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3757
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3758
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3759
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3760
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3761
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3762
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3763
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
3764
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3765
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3766
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3767
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3768
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3769
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3770
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3771
119
      GIR_EraseFromParent, /*InsnID*/0,
3772
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3773
119
      // GIR_Coverage, 1953,
3774
119
      GIR_Done,
3775
119
    // Label 348: @7239
3776
119
    GIM_Try, /*On fail goto*//*Label 349*/ 7304, // Rule ID 1969 //
3777
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3778
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3779
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3780
119
      // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3781
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3782
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3783
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3784
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3785
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3786
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3787
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3788
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3789
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3790
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3791
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3792
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3793
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3794
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3795
119
      GIR_EraseFromParent, /*InsnID*/0,
3796
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3797
119
      // GIR_Coverage, 1969,
3798
119
      GIR_Done,
3799
119
    // Label 349: @7304
3800
119
    GIM_Try, /*On fail goto*//*Label 350*/ 7369, // Rule ID 1970 //
3801
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3802
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3803
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3804
119
      // (bitconvert:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3805
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3806
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3807
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3808
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3809
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3810
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3811
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3812
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3813
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3814
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3815
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3816
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3817
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3818
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3819
119
      GIR_EraseFromParent, /*InsnID*/0,
3820
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3821
119
      // GIR_Coverage, 1970,
3822
119
      GIR_Done,
3823
119
    // Label 350: @7369
3824
119
    GIM_Try, /*On fail goto*//*Label 351*/ 7434, // Rule ID 1974 //
3825
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3826
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3827
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3828
119
      // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3829
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3830
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3831
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3832
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3833
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3834
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3835
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3836
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3837
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3838
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3839
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3840
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3841
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3842
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3843
119
      GIR_EraseFromParent, /*InsnID*/0,
3844
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3845
119
      // GIR_Coverage, 1974,
3846
119
      GIR_Done,
3847
119
    // Label 351: @7434
3848
119
    GIM_Try, /*On fail goto*//*Label 352*/ 7499, // Rule ID 1975 //
3849
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3850
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3851
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3852
119
      // (bitconvert:{ *:[v8f16] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3853
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3854
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3855
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3856
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3857
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3858
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3859
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3860
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3861
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3862
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
3863
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3864
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3865
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3866
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3867
119
      GIR_EraseFromParent, /*InsnID*/0,
3868
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3869
119
      // GIR_Coverage, 1975,
3870
119
      GIR_Done,
3871
119
    // Label 352: @7499
3872
119
    GIM_Try, /*On fail goto*//*Label 353*/ 7564, // Rule ID 1979 //
3873
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3874
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3875
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3876
119
      // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3877
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3878
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3879
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3880
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3881
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3882
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3883
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3884
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3885
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3886
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3887
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3888
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3889
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3890
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3891
119
      GIR_EraseFromParent, /*InsnID*/0,
3892
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3893
119
      // GIR_Coverage, 1979,
3894
119
      GIR_Done,
3895
119
    // Label 353: @7564
3896
119
    GIM_Try, /*On fail goto*//*Label 354*/ 7629, // Rule ID 1980 //
3897
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3898
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3899
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3900
119
      // (bitconvert:{ *:[v8f16] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3901
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3902
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3903
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3904
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3905
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3906
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3907
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3908
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3909
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3910
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3911
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3912
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3913
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3914
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3915
119
      GIR_EraseFromParent, /*InsnID*/0,
3916
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3917
119
      // GIR_Coverage, 1980,
3918
119
      GIR_Done,
3919
119
    // Label 354: @7629
3920
119
    GIM_Try, /*On fail goto*//*Label 355*/ 7694, // Rule ID 1984 //
3921
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3922
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3923
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3924
119
      // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3925
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3926
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3927
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3928
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3929
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3930
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3931
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3932
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3933
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3934
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3935
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3936
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3937
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3938
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3939
119
      GIR_EraseFromParent, /*InsnID*/0,
3940
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3941
119
      // GIR_Coverage, 1984,
3942
119
      GIR_Done,
3943
119
    // Label 355: @7694
3944
119
    GIM_Try, /*On fail goto*//*Label 356*/ 7759, // Rule ID 1985 //
3945
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
3946
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3947
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
3948
119
      // (bitconvert:{ *:[v8f16] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3949
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3950
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3951
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3952
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3953
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3954
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3955
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
3956
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
3957
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
3958
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
3959
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3960
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3961
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
3962
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3963
119
      GIR_EraseFromParent, /*InsnID*/0,
3964
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/76,
3965
119
      // GIR_Coverage, 1985,
3966
119
      GIR_Done,
3967
119
    // Label 356: @7759
3968
119
    GIM_Reject,
3969
119
    // Label 275: @7760
3970
119
    GIM_Try, /*On fail goto*//*Label 357*/ 7781, // Rule ID 1921 //
3971
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3972
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3973
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
3974
119
      // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] })
3975
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3976
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
3977
119
      // GIR_Coverage, 1921,
3978
119
      GIR_Done,
3979
119
    // Label 357: @7781
3980
119
    GIM_Try, /*On fail goto*//*Label 358*/ 7802, // Rule ID 1922 //
3981
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3982
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3983
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
3984
119
      // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] })
3985
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3986
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
3987
119
      // GIR_Coverage, 1922,
3988
119
      GIR_Done,
3989
119
    // Label 358: @7802
3990
119
    GIM_Try, /*On fail goto*//*Label 359*/ 7823, // Rule ID 1923 //
3991
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
3992
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3993
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
3994
119
      // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] })
3995
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3996
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
3997
119
      // GIR_Coverage, 1923,
3998
119
      GIR_Done,
3999
119
    // Label 359: @7823
4000
119
    GIM_Try, /*On fail goto*//*Label 360*/ 7844, // Rule ID 1924 //
4001
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4002
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4003
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4004
119
      // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] })
4005
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4006
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4007
119
      // GIR_Coverage, 1924,
4008
119
      GIR_Done,
4009
119
    // Label 360: @7844
4010
119
    GIM_Try, /*On fail goto*//*Label 361*/ 7865, // Rule ID 1925 //
4011
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4012
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4013
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4014
119
      // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] })
4015
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4016
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4017
119
      // GIR_Coverage, 1925,
4018
119
      GIR_Done,
4019
119
    // Label 361: @7865
4020
119
    GIM_Try, /*On fail goto*//*Label 362*/ 7886, // Rule ID 1926 //
4021
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
4022
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4023
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4024
119
      // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] })
4025
119
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4026
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4027
119
      // GIR_Coverage, 1926,
4028
119
      GIR_Done,
4029
119
    // Label 362: @7886
4030
119
    GIM_Try, /*On fail goto*//*Label 363*/ 7951, // Rule ID 1958 //
4031
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4032
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4033
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4034
119
      // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4035
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4036
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4037
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4038
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4039
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4040
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4041
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4042
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4043
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4044
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4045
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4046
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4047
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4048
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4049
119
      GIR_EraseFromParent, /*InsnID*/0,
4050
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4051
119
      // GIR_Coverage, 1958,
4052
119
      GIR_Done,
4053
119
    // Label 363: @7951
4054
119
    GIM_Try, /*On fail goto*//*Label 364*/ 8016, // Rule ID 1963 //
4055
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4056
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4057
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4058
119
      // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4059
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4060
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4061
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4062
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4063
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4064
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4065
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4066
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4067
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4068
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4069
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4070
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4071
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4072
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4073
119
      GIR_EraseFromParent, /*InsnID*/0,
4074
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4075
119
      // GIR_Coverage, 1963,
4076
119
      GIR_Done,
4077
119
    // Label 364: @8016
4078
119
    GIM_Try, /*On fail goto*//*Label 365*/ 8081, // Rule ID 1968 //
4079
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4080
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4081
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4082
119
      // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
4083
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4084
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4085
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4086
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4087
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4088
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4089
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4090
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4091
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4092
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
4093
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4094
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4095
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4096
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4097
119
      GIR_EraseFromParent, /*InsnID*/0,
4098
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4099
119
      // GIR_Coverage, 1968,
4100
119
      GIR_Done,
4101
119
    // Label 365: @8081
4102
119
    GIM_Try, /*On fail goto*//*Label 366*/ 8146, // Rule ID 1973 //
4103
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4104
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4105
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4106
119
      // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
4107
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4108
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4109
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4110
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4111
119
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4112
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4113
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
4114
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4115
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4116
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/27,
4117
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4118
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4119
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4120
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4121
119
      GIR_EraseFromParent, /*InsnID*/0,
4122
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4123
119
      // GIR_Coverage, 1973,
4124
119
      GIR_Done,
4125
119
    // Label 366: @8146
4126
119
    GIM_Try, /*On fail goto*//*Label 367*/ 8246, // Rule ID 1978 //
4127
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4128
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4129
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4130
119
      // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4131
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4132
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4133
119
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4134
119
      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4135
119
      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
4136
119
      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
4137
119
      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4138
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
4139
119
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
4140
119
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
4141
119
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
4142
119
      GIR_AddImm, /*InsnID*/3, /*Imm*/27,
4143
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4144
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4145
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4146
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
4147
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4148
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
4149
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4150
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4151
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4152
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4153
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4154
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4155
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4156
119
      GIR_EraseFromParent, /*InsnID*/0,
4157
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4158
119
      // GIR_Coverage, 1978,
4159
119
      GIR_Done,
4160
119
    // Label 367: @8246
4161
119
    GIM_Try, /*On fail goto*//*Label 368*/ 8346, // Rule ID 1983 //
4162
119
      GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
4163
119
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4164
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
4165
119
      // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4166
119
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4167
119
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4168
119
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4169
119
      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4170
119
      GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
4171
119
      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
4172
119
      GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4173
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
4174
119
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
4175
119
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
4176
119
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
4177
119
      GIR_AddImm, /*InsnID*/3, /*Imm*/27,
4178
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4179
119
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4180
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
4181
119
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
4182
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4183
119
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
4184
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
4185
119
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
4186
119
      GIR_AddImm, /*InsnID*/1, /*Imm*/177,
4187
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4188
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4189
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
4190
119
      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4191
119
      GIR_EraseFromParent, /*InsnID*/0,
4192
119
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/74,
4193
119
      // GIR_Coverage, 1983,
4194
119
      GIR_Done,
4195
119
    // Label 368: @8346
4196
119
    GIM_Reject,
4197
119
    // Label 276: @8347
4198
119
    GIM_Reject,
4199
119
    // Label 11: @8348
4200
119
    GIM_Try, /*On fail goto*//*Label 369*/ 8413, // Rule ID 1906 //
4201
119
      GIM_CheckFeatures, GIFBS_HasDSP,
4202
119
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4203
119
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
4204
119
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
4205
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4206
119
      // MIs[0] Operand 1
4207
119
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4208
119
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4209
119
      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4210
119
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4211
119
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4212
119
      GIM_CheckIsSafeToFold, /*InsnID*/1,
4213
119
      // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LWX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4214
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LWX,
4215
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4216
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4217
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4218
119
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
4219
119
      GIR_EraseFromParent, /*InsnID*/0,
4220
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4221
119
      // GIR_Coverage, 1906,
4222
119
      GIR_Done,
4223
119
    // Label 369: @8413
4224
119
    GIM_Reject,
4225
119
    // Label 12: @8414
4226
119
    GIM_Try, /*On fail goto*//*Label 370*/ 8479, // Rule ID 1905 //
4227
119
      GIM_CheckFeatures, GIFBS_HasDSP,
4228
119
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4229
119
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
4230
119
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
4231
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4232
119
      // MIs[0] Operand 1
4233
119
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4234
119
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4235
119
      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4236
119
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4237
119
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4238
119
      GIM_CheckIsSafeToFold, /*InsnID*/1,
4239
119
      // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LHX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4240
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LHX,
4241
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4242
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4243
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4244
119
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
4245
119
      GIR_EraseFromParent, /*InsnID*/0,
4246
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4247
119
      // GIR_Coverage, 1905,
4248
119
      GIR_Done,
4249
119
    // Label 370: @8479
4250
119
    GIM_Reject,
4251
119
    // Label 13: @8480
4252
119
    GIM_Try, /*On fail goto*//*Label 371*/ 8545, // Rule ID 1904 //
4253
119
      GIM_CheckFeatures, GIFBS_HasDSP,
4254
119
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4255
119
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
4256
119
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
4257
119
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4258
119
      // MIs[0] Operand 1
4259
119
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4260
119
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4261
119
      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
4262
119
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4263
119
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4264
119
      GIM_CheckIsSafeToFold, /*InsnID*/1,
4265
119
      // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (LBUX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4266
119
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LBUX,
4267
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4268
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4269
119
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4270
119
      GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
4271
119
      GIR_EraseFromParent, /*InsnID*/0,
4272
119
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4273
119
      // GIR_Coverage, 1904,
4274
119
      GIR_Done,
4275
119
    // Label 371: @8545
4276
119
    GIM_Reject,
4277
119
    // Label 14: @8546
4278
119
    GIM_Try, /*On fail goto*//*Label 372*/ 10740,
4279
119
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
4280
119
      GIM_Try, /*On fail goto*//*Label 373*/ 8598, // Rule ID 400 //
4281
119
        GIM_CheckFeatures, GIFBS_HasDSP,
4282
119
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
4283
119
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
4284
119
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4285
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4286
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4287
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4288
119
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt8,
4289
119
        // MIs[1] Operand 1
4290
119
        // No operand predicates
4291
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4292
119
        // (intrinsic_wo_chain:{ *:[v4i8] } 3506:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm)  =>  (REPL_QB:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
4293
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_QB,
4294
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4295
119
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4296
119
        GIR_EraseFromParent, /*InsnID*/0,
4297
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4298
119
        // GIR_Coverage, 400,
4299
119
        GIR_Done,
4300
119
      // Label 373: @8598
4301
119
      GIM_Try, /*On fail goto*//*Label 374*/ 8645, // Rule ID 401 //
4302
119
        GIM_CheckFeatures, GIFBS_HasDSP,
4303
119
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
4304
119
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4305
119
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4306
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4307
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4308
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4309
119
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExt10,
4310
119
        // MIs[1] Operand 1
4311
119
        // No operand predicates
4312
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4313
119
        // (intrinsic_wo_chain:{ *:[v2i16] } 3505:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm)  =>  (REPL_PH:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
4314
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_PH,
4315
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4316
119
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4317
119
        GIR_EraseFromParent, /*InsnID*/0,
4318
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4319
119
        // GIR_Coverage, 401,
4320
119
        GIR_Done,
4321
119
      // Label 374: @8645
4322
119
      GIM_Try, /*On fail goto*//*Label 375*/ 8692, // Rule ID 1254 //
4323
119
        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
4324
119
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
4325
119
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4326
119
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4327
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4328
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4329
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4330
119
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExt10,
4331
119
        // MIs[1] Operand 1
4332
119
        // No operand predicates
4333
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4334
119
        // (intrinsic_wo_chain:{ *:[v2i16] } 3505:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm)  =>  (REPL_PH_MM:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
4335
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_PH_MM,
4336
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4337
119
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4338
119
        GIR_EraseFromParent, /*InsnID*/0,
4339
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4340
119
        // GIR_Coverage, 1254,
4341
119
        GIR_Done,
4342
119
      // Label 375: @8692
4343
119
      GIM_Try, /*On fail goto*//*Label 376*/ 8739, // Rule ID 1255 //
4344
119
        GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
4345
119
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
4346
119
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
4347
119
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4348
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4349
119
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4350
119
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4351
119
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt8,
4352
119
        // MIs[1] Operand 1
4353
119
        // No operand predicates
4354
119
        GIM_CheckIsSafeToFold, /*InsnID*/1,
4355
119
        // (intrinsic_wo_chain:{ *:[v4i8] } 3506:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm)  =>  (REPL_QB_MM:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
4356
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_QB_MM,
4357
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
4358
119
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4359
119
        GIR_EraseFromParent, /*InsnID*/0,
4360
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4361
119
        // GIR_Coverage, 1255,
4362
119
        GIR_Done,
4363
119
      // Label 376: @8739
4364
119
      GIM_Try, /*On fail goto*//*Label 377*/ 8779, // Rule ID 334 //
4365
119
        GIM_CheckFeatures, GIFBS_HasDSP,
4366
119
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_raddu_w_qb,
4367
119
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4368
119
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4369
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4370
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4371
119
        // (intrinsic_wo_chain:{ *:[i32] } 3503:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (RADDU_W_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
4372
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RADDU_W_QB,
4373
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4374
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
4375
119
        GIR_EraseFromParent, /*InsnID*/0,
4376
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4377
119
        // GIR_Coverage, 334,
4378
119
        GIR_Done,
4379
119
      // Label 377: @8779
4380
119
      GIM_Try, /*On fail goto*//*Label 378*/ 8819, // Rule ID 341 //
4381
119
        GIM_CheckFeatures, GIFBS_HasDSP,
4382
119
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phl,
4383
119
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4384
119
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
4385
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4386
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4387
119
        // (intrinsic_wo_chain:{ *:[i32] } 3485:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECEQ_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
4388
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHL,
4389
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4390
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4391
119
        GIR_EraseFromParent, /*InsnID*/0,
4392
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4393
119
        // GIR_Coverage, 341,
4394
119
        GIR_Done,
4395
119
      // Label 378: @8819
4396
119
      GIM_Try, /*On fail goto*//*Label 379*/ 8859, // Rule ID 342 //
4397
119
        GIM_CheckFeatures, GIFBS_HasDSP,
4398
119
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phr,
4399
119
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4400
119
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
4401
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4402
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4403
119
        // (intrinsic_wo_chain:{ *:[i32] } 3486:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECEQ_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
4404
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHR,
4405
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4406
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4407
119
        GIR_EraseFromParent, /*InsnID*/0,
4408
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4409
119
        // GIR_Coverage, 342,
4410
119
        GIR_Done,
4411
119
      // Label 379: @8859
4412
119
      GIM_Try, /*On fail goto*//*Label 380*/ 8899, // Rule ID 343 //
4413
119
        GIM_CheckFeatures, GIFBS_HasDSP,
4414
119
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbl,
4415
119
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4416
119
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4417
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4418
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4419
119
        // (intrinsic_wo_chain:{ *:[v2i16] } 3487:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4420
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBL,
4421
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4422
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4423
119
        GIR_EraseFromParent, /*InsnID*/0,
4424
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4425
119
        // GIR_Coverage, 343,
4426
119
        GIR_Done,
4427
119
      // Label 380: @8899
4428
119
      GIM_Try, /*On fail goto*//*Label 381*/ 8939, // Rule ID 344 //
4429
119
        GIM_CheckFeatures, GIFBS_HasDSP,
4430
119
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbr,
4431
119
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4432
119
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4433
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4434
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4435
119
        // (intrinsic_wo_chain:{ *:[v2i16] } 3489:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4436
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBR,
4437
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4438
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4439
119
        GIR_EraseFromParent, /*InsnID*/0,
4440
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4441
119
        // GIR_Coverage, 344,
4442
119
        GIR_Done,
4443
119
      // Label 381: @8939
4444
119
      GIM_Try, /*On fail goto*//*Label 382*/ 8979, // Rule ID 345 //
4445
119
        GIM_CheckFeatures, GIFBS_HasDSP,
4446
119
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbla,
4447
119
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4448
119
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4449
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4450
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4451
119
        // (intrinsic_wo_chain:{ *:[v2i16] } 3488:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4452
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBLA,
4453
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4454
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4455
119
        GIR_EraseFromParent, /*InsnID*/0,
4456
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4457
119
        // GIR_Coverage, 345,
4458
119
        GIR_Done,
4459
119
      // Label 382: @8979
4460
119
      GIM_Try, /*On fail goto*//*Label 383*/ 9019, // Rule ID 346 //
4461
119
        GIM_CheckFeatures, GIFBS_HasDSP,
4462
119
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbra,
4463
119
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4464
119
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4465
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4466
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4467
119
        // (intrinsic_wo_chain:{ *:[v2i16] } 3490:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4468
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBRA,
4469
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4470
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4471
119
        GIR_EraseFromParent, /*InsnID*/0,
4472
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4473
119
        // GIR_Coverage, 346,
4474
119
        GIR_Done,
4475
119
      // Label 383: @9019
4476
119
      GIM_Try, /*On fail goto*//*Label 384*/ 9059, // Rule ID 347 //
4477
119
        GIM_CheckFeatures, GIFBS_HasDSP,
4478
119
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbl,
4479
119
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4480
119
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4481
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4482
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4483
119
        // (intrinsic_wo_chain:{ *:[v2i16] } 3491:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4484
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBL,
4485
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4486
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4487
119
        GIR_EraseFromParent, /*InsnID*/0,
4488
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4489
119
        // GIR_Coverage, 347,
4490
119
        GIR_Done,
4491
119
      // Label 384: @9059
4492
119
      GIM_Try, /*On fail goto*//*Label 385*/ 9099, // Rule ID 348 //
4493
119
        GIM_CheckFeatures, GIFBS_HasDSP,
4494
119
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbr,
4495
119
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4496
119
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4497
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4498
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4499
119
        // (intrinsic_wo_chain:{ *:[v2i16] } 3493:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4500
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBR,
4501
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4502
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4503
119
        GIR_EraseFromParent, /*InsnID*/0,
4504
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4505
119
        // GIR_Coverage, 348,
4506
119
        GIR_Done,
4507
119
      // Label 385: @9099
4508
119
      GIM_Try, /*On fail goto*//*Label 386*/ 9139, // Rule ID 349 //
4509
119
        GIM_CheckFeatures, GIFBS_HasDSP,
4510
119
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbla,
4511
119
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4512
119
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4513
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4514
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4515
119
        // (intrinsic_wo_chain:{ *:[v2i16] } 3492:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4516
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBLA,
4517
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4518
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4519
119
        GIR_EraseFromParent, /*InsnID*/0,
4520
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4521
119
        // GIR_Coverage, 349,
4522
119
        GIR_Done,
4523
119
      // Label 386: @9139
4524
119
      GIM_Try, /*On fail goto*//*Label 387*/ 9179, // Rule ID 350 //
4525
119
        GIM_CheckFeatures, GIFBS_HasDSP,
4526
119
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbra,
4527
119
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4528
119
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
4529
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4530
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
4531
119
        // (intrinsic_wo_chain:{ *:[v2i16] } 3494:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
4532
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBRA,
4533
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4534
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4535
119
        GIR_EraseFromParent, /*InsnID*/0,
4536
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4537
119
        // GIR_Coverage, 350,
4538
119
        GIR_Done,
4539
119
      // Label 387: @9179
4540
119
      GIM_Try, /*On fail goto*//*Label 388*/ 9219, // Rule ID 398 //
4541
119
        GIM_CheckFeatures, GIFBS_HasDSP,
4542
119
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_bitrev,
4543
119
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4544
119
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4545
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
4546
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
4547
119
        // (intrinsic_wo_chain:{ *:[i32] } 3061:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (BITREV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
4548
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BITREV,
4549
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4550
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4551
119
        GIR_EraseFromParent, /*InsnID*/0,
4552
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4553
119
        // GIR_Coverage, 398,
4554
119
        GIR_Done,
4555
119
      // Label 388: @9219
4556
119
      GIM_Try, /*On fail goto*//*Label 389*/ 9259, // Rule ID 402 //
4557
119
        GIM_CheckFeatures, GIFBS_HasDSP,
4558
119
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
4559
119
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
4560
119
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4561
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4562
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
4563
119
        // (intrinsic_wo_chain:{ *:[v4i8] } 3506:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (REPLV_QB:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rt)
4564
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_QB,
4565
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4566
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4567
119
        GIR_EraseFromParent, /*InsnID*/0,
4568
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4569
119
        // GIR_Coverage, 402,
4570
119
        GIR_Done,
4571
119
      // Label 389: @9259
4572
119
      GIM_Try, /*On fail goto*//*Label 390*/ 9299, // Rule ID 403 //
4573
119
        GIM_CheckFeatures, GIFBS_HasDSP,
4574
119
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
4575
119
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
4576
119
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4577
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
4578
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
4579
119
        // (intrinsic_wo_chain:{ *:[v2i16] } 3505:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (REPLV_PH:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rt)
4580
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_PH,
4581
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
4582
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
4583
119
        GIR_EraseFromParent, /*InsnID*/0,
4584
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4585
119
        // GIR_Coverage, 403,
4586
119
        GIR_Done,
4587
119
      // Label 390: @9299
4588
119
      GIM_Try, /*On fail goto*//*Label 391*/ 9339, // Rule ID 648 //
4589
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4590
119
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fclass_w,
4591
119
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4592
119
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4593
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4594
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4595
119
        // (intrinsic_wo_chain:{ *:[v4i32] } 3213:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FCLASS_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
4596
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCLASS_W,
4597
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4598
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4599
119
        GIR_EraseFromParent, /*InsnID*/0,
4600
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4601
119
        // GIR_Coverage, 648,
4602
119
        GIR_Done,
4603
119
      // Label 391: @9339
4604
119
      GIM_Try, /*On fail goto*//*Label 392*/ 9379, // Rule ID 649 //
4605
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4606
119
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fclass_d,
4607
119
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4608
119
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
4609
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4610
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
4611
119
        // (intrinsic_wo_chain:{ *:[v2i64] } 3212:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FCLASS_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
4612
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCLASS_D,
4613
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4614
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4615
119
        GIR_EraseFromParent, /*InsnID*/0,
4616
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4617
119
        // GIR_Coverage, 649,
4618
119
        GIR_Done,
4619
119
      // Label 392: @9379
4620
119
      GIM_Try, /*On fail goto*//*Label 393*/ 9419, // Rule ID 672 //
4621
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4622
119
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupl_w,
4623
119
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4624
119
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4625
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4626
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
4627
119
        // (intrinsic_wo_chain:{ *:[v4f32] } 3239:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws)  =>  (FEXUPL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
4628
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPL_W,
4629
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4630
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4631
119
        GIR_EraseFromParent, /*InsnID*/0,
4632
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4633
119
        // GIR_Coverage, 672,
4634
119
        GIR_Done,
4635
119
      // Label 393: @9419
4636
119
      GIM_Try, /*On fail goto*//*Label 394*/ 9459, // Rule ID 673 //
4637
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4638
119
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupl_d,
4639
119
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4640
119
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4641
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4642
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4643
119
        // (intrinsic_wo_chain:{ *:[v2f64] } 3238:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FEXUPL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
4644
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPL_D,
4645
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4646
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4647
119
        GIR_EraseFromParent, /*InsnID*/0,
4648
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4649
119
        // GIR_Coverage, 673,
4650
119
        GIR_Done,
4651
119
      // Label 394: @9459
4652
119
      GIM_Try, /*On fail goto*//*Label 395*/ 9499, // Rule ID 674 //
4653
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4654
119
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupr_w,
4655
119
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4656
119
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4657
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4658
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
4659
119
        // (intrinsic_wo_chain:{ *:[v4f32] } 3241:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws)  =>  (FEXUPR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
4660
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPR_W,
4661
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4662
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4663
119
        GIR_EraseFromParent, /*InsnID*/0,
4664
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4665
119
        // GIR_Coverage, 674,
4666
119
        GIR_Done,
4667
119
      // Label 395: @9499
4668
119
      GIM_Try, /*On fail goto*//*Label 396*/ 9539, // Rule ID 675 //
4669
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4670
119
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupr_d,
4671
119
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
4672
119
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4673
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
4674
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
4675
119
        // (intrinsic_wo_chain:{ *:[v2f64] } 3240:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FEXUPR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
4676
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPR_D,
4677
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4678
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4679
119
        GIR_EraseFromParent, /*InsnID*/0,
4680
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4681
119
        // GIR_Coverage, 675,
4682
119
        GIR_Done,
4683
119
      // Label 396: @9539
4684
119
      GIM_Try, /*On fail goto*//*Label 397*/ 9579, // Rule ID 680 //
4685
119
        GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
4686
119
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffql_w,
4687
119
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
4688
119
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4689
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
4690
119
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
4691
119
        // (intrinsic_wo_chain:{ *:[v4f32] } 3247:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws)  =>  (FFQL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
4692
119
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQL_W,
4693
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
4694
119
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
4695
119
        GIR_EraseFromParent, /*InsnID*/0,
4696
119
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4697
119
        // GIR_Coverage, 680,
4698
119
        GIR_Done,
4699
119
      // Label 397: @9579
4700
119
      GIM_Try, /*On fail goto*//*Label 398*/ 9619, // Rule ID 681 //
4701
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