Coverage Report

Created: 2019-02-20 07:29

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Mips/MipsGenInstrInfo.inc
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1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Instruction Enum Values and Descriptors                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_INSTRINFO_ENUM
10
#undef GET_INSTRINFO_ENUM
11
namespace llvm {
12
13
namespace Mips {
14
  enum {
15
    PHI = 0,
16
    INLINEASM = 1,
17
    INLINEASM_BR  = 2,
18
    CFI_INSTRUCTION = 3,
19
    EH_LABEL  = 4,
20
    GC_LABEL  = 5,
21
    ANNOTATION_LABEL  = 6,
22
    KILL  = 7,
23
    EXTRACT_SUBREG  = 8,
24
    INSERT_SUBREG = 9,
25
    IMPLICIT_DEF  = 10,
26
    SUBREG_TO_REG = 11,
27
    COPY_TO_REGCLASS  = 12,
28
    DBG_VALUE = 13,
29
    DBG_LABEL = 14,
30
    REG_SEQUENCE  = 15,
31
    COPY  = 16,
32
    BUNDLE  = 17,
33
    LIFETIME_START  = 18,
34
    LIFETIME_END  = 19,
35
    STACKMAP  = 20,
36
    FENTRY_CALL = 21,
37
    PATCHPOINT  = 22,
38
    LOAD_STACK_GUARD  = 23,
39
    STATEPOINT  = 24,
40
    LOCAL_ESCAPE  = 25,
41
    FAULTING_OP = 26,
42
    PATCHABLE_OP  = 27,
43
    PATCHABLE_FUNCTION_ENTER  = 28,
44
    PATCHABLE_RET = 29,
45
    PATCHABLE_FUNCTION_EXIT = 30,
46
    PATCHABLE_TAIL_CALL = 31,
47
    PATCHABLE_EVENT_CALL  = 32,
48
    PATCHABLE_TYPED_EVENT_CALL  = 33,
49
    ICALL_BRANCH_FUNNEL = 34,
50
    G_ADD = 35,
51
    G_SUB = 36,
52
    G_MUL = 37,
53
    G_SDIV  = 38,
54
    G_UDIV  = 39,
55
    G_SREM  = 40,
56
    G_UREM  = 41,
57
    G_AND = 42,
58
    G_OR  = 43,
59
    G_XOR = 44,
60
    G_IMPLICIT_DEF  = 45,
61
    G_PHI = 46,
62
    G_FRAME_INDEX = 47,
63
    G_GLOBAL_VALUE  = 48,
64
    G_EXTRACT = 49,
65
    G_UNMERGE_VALUES  = 50,
66
    G_INSERT  = 51,
67
    G_MERGE_VALUES  = 52,
68
    G_BUILD_VECTOR  = 53,
69
    G_BUILD_VECTOR_TRUNC  = 54,
70
    G_CONCAT_VECTORS  = 55,
71
    G_PTRTOINT  = 56,
72
    G_INTTOPTR  = 57,
73
    G_BITCAST = 58,
74
    G_INTRINSIC_TRUNC = 59,
75
    G_INTRINSIC_ROUND = 60,
76
    G_LOAD  = 61,
77
    G_SEXTLOAD  = 62,
78
    G_ZEXTLOAD  = 63,
79
    G_STORE = 64,
80
    G_ATOMIC_CMPXCHG_WITH_SUCCESS = 65,
81
    G_ATOMIC_CMPXCHG  = 66,
82
    G_ATOMICRMW_XCHG  = 67,
83
    G_ATOMICRMW_ADD = 68,
84
    G_ATOMICRMW_SUB = 69,
85
    G_ATOMICRMW_AND = 70,
86
    G_ATOMICRMW_NAND  = 71,
87
    G_ATOMICRMW_OR  = 72,
88
    G_ATOMICRMW_XOR = 73,
89
    G_ATOMICRMW_MAX = 74,
90
    G_ATOMICRMW_MIN = 75,
91
    G_ATOMICRMW_UMAX  = 76,
92
    G_ATOMICRMW_UMIN  = 77,
93
    G_BRCOND  = 78,
94
    G_BRINDIRECT  = 79,
95
    G_INTRINSIC = 80,
96
    G_INTRINSIC_W_SIDE_EFFECTS  = 81,
97
    G_ANYEXT  = 82,
98
    G_TRUNC = 83,
99
    G_CONSTANT  = 84,
100
    G_FCONSTANT = 85,
101
    G_VASTART = 86,
102
    G_VAARG = 87,
103
    G_SEXT  = 88,
104
    G_ZEXT  = 89,
105
    G_SHL = 90,
106
    G_LSHR  = 91,
107
    G_ASHR  = 92,
108
    G_ICMP  = 93,
109
    G_FCMP  = 94,
110
    G_SELECT  = 95,
111
    G_UADDO = 96,
112
    G_UADDE = 97,
113
    G_USUBO = 98,
114
    G_USUBE = 99,
115
    G_SADDO = 100,
116
    G_SADDE = 101,
117
    G_SSUBO = 102,
118
    G_SSUBE = 103,
119
    G_UMULO = 104,
120
    G_SMULO = 105,
121
    G_UMULH = 106,
122
    G_SMULH = 107,
123
    G_FADD  = 108,
124
    G_FSUB  = 109,
125
    G_FMUL  = 110,
126
    G_FMA = 111,
127
    G_FDIV  = 112,
128
    G_FREM  = 113,
129
    G_FPOW  = 114,
130
    G_FEXP  = 115,
131
    G_FEXP2 = 116,
132
    G_FLOG  = 117,
133
    G_FLOG2 = 118,
134
    G_FLOG10  = 119,
135
    G_FNEG  = 120,
136
    G_FPEXT = 121,
137
    G_FPTRUNC = 122,
138
    G_FPTOSI  = 123,
139
    G_FPTOUI  = 124,
140
    G_SITOFP  = 125,
141
    G_UITOFP  = 126,
142
    G_FABS  = 127,
143
    G_FCANONICALIZE = 128,
144
    G_GEP = 129,
145
    G_PTR_MASK  = 130,
146
    G_BR  = 131,
147
    G_INSERT_VECTOR_ELT = 132,
148
    G_EXTRACT_VECTOR_ELT  = 133,
149
    G_SHUFFLE_VECTOR  = 134,
150
    G_CTTZ  = 135,
151
    G_CTTZ_ZERO_UNDEF = 136,
152
    G_CTLZ  = 137,
153
    G_CTLZ_ZERO_UNDEF = 138,
154
    G_CTPOP = 139,
155
    G_BSWAP = 140,
156
    G_FCEIL = 141,
157
    G_FCOS  = 142,
158
    G_FSIN  = 143,
159
    G_FSQRT = 144,
160
    G_FFLOOR  = 145,
161
    G_ADDRSPACE_CAST  = 146,
162
    G_BLOCK_ADDR  = 147,
163
    ABSMacro  = 148,
164
    ADJCALLSTACKDOWN  = 149,
165
    ADJCALLSTACKUP  = 150,
166
    AND_V_D_PSEUDO  = 151,
167
    AND_V_H_PSEUDO  = 152,
168
    AND_V_W_PSEUDO  = 153,
169
    ATOMIC_CMP_SWAP_I16 = 154,
170
    ATOMIC_CMP_SWAP_I16_POSTRA  = 155,
171
    ATOMIC_CMP_SWAP_I32 = 156,
172
    ATOMIC_CMP_SWAP_I32_POSTRA  = 157,
173
    ATOMIC_CMP_SWAP_I64 = 158,
174
    ATOMIC_CMP_SWAP_I64_POSTRA  = 159,
175
    ATOMIC_CMP_SWAP_I8  = 160,
176
    ATOMIC_CMP_SWAP_I8_POSTRA = 161,
177
    ATOMIC_LOAD_ADD_I16 = 162,
178
    ATOMIC_LOAD_ADD_I16_POSTRA  = 163,
179
    ATOMIC_LOAD_ADD_I32 = 164,
180
    ATOMIC_LOAD_ADD_I32_POSTRA  = 165,
181
    ATOMIC_LOAD_ADD_I64 = 166,
182
    ATOMIC_LOAD_ADD_I64_POSTRA  = 167,
183
    ATOMIC_LOAD_ADD_I8  = 168,
184
    ATOMIC_LOAD_ADD_I8_POSTRA = 169,
185
    ATOMIC_LOAD_AND_I16 = 170,
186
    ATOMIC_LOAD_AND_I16_POSTRA  = 171,
187
    ATOMIC_LOAD_AND_I32 = 172,
188
    ATOMIC_LOAD_AND_I32_POSTRA  = 173,
189
    ATOMIC_LOAD_AND_I64 = 174,
190
    ATOMIC_LOAD_AND_I64_POSTRA  = 175,
191
    ATOMIC_LOAD_AND_I8  = 176,
192
    ATOMIC_LOAD_AND_I8_POSTRA = 177,
193
    ATOMIC_LOAD_NAND_I16  = 178,
194
    ATOMIC_LOAD_NAND_I16_POSTRA = 179,
195
    ATOMIC_LOAD_NAND_I32  = 180,
196
    ATOMIC_LOAD_NAND_I32_POSTRA = 181,
197
    ATOMIC_LOAD_NAND_I64  = 182,
198
    ATOMIC_LOAD_NAND_I64_POSTRA = 183,
199
    ATOMIC_LOAD_NAND_I8 = 184,
200
    ATOMIC_LOAD_NAND_I8_POSTRA  = 185,
201
    ATOMIC_LOAD_OR_I16  = 186,
202
    ATOMIC_LOAD_OR_I16_POSTRA = 187,
203
    ATOMIC_LOAD_OR_I32  = 188,
204
    ATOMIC_LOAD_OR_I32_POSTRA = 189,
205
    ATOMIC_LOAD_OR_I64  = 190,
206
    ATOMIC_LOAD_OR_I64_POSTRA = 191,
207
    ATOMIC_LOAD_OR_I8 = 192,
208
    ATOMIC_LOAD_OR_I8_POSTRA  = 193,
209
    ATOMIC_LOAD_SUB_I16 = 194,
210
    ATOMIC_LOAD_SUB_I16_POSTRA  = 195,
211
    ATOMIC_LOAD_SUB_I32 = 196,
212
    ATOMIC_LOAD_SUB_I32_POSTRA  = 197,
213
    ATOMIC_LOAD_SUB_I64 = 198,
214
    ATOMIC_LOAD_SUB_I64_POSTRA  = 199,
215
    ATOMIC_LOAD_SUB_I8  = 200,
216
    ATOMIC_LOAD_SUB_I8_POSTRA = 201,
217
    ATOMIC_LOAD_XOR_I16 = 202,
218
    ATOMIC_LOAD_XOR_I16_POSTRA  = 203,
219
    ATOMIC_LOAD_XOR_I32 = 204,
220
    ATOMIC_LOAD_XOR_I32_POSTRA  = 205,
221
    ATOMIC_LOAD_XOR_I64 = 206,
222
    ATOMIC_LOAD_XOR_I64_POSTRA  = 207,
223
    ATOMIC_LOAD_XOR_I8  = 208,
224
    ATOMIC_LOAD_XOR_I8_POSTRA = 209,
225
    ATOMIC_SWAP_I16 = 210,
226
    ATOMIC_SWAP_I16_POSTRA  = 211,
227
    ATOMIC_SWAP_I32 = 212,
228
    ATOMIC_SWAP_I32_POSTRA  = 213,
229
    ATOMIC_SWAP_I64 = 214,
230
    ATOMIC_SWAP_I64_POSTRA  = 215,
231
    ATOMIC_SWAP_I8  = 216,
232
    ATOMIC_SWAP_I8_POSTRA = 217,
233
    B = 218,
234
    BAL_BR  = 219,
235
    BAL_BR_MM = 220,
236
    BEQLImmMacro  = 221,
237
    BGE = 222,
238
    BGEImmMacro = 223,
239
    BGEL  = 224,
240
    BGELImmMacro  = 225,
241
    BGEU  = 226,
242
    BGEUImmMacro  = 227,
243
    BGEUL = 228,
244
    BGEULImmMacro = 229,
245
    BGT = 230,
246
    BGTImmMacro = 231,
247
    BGTL  = 232,
248
    BGTLImmMacro  = 233,
249
    BGTU  = 234,
250
    BGTUImmMacro  = 235,
251
    BGTUL = 236,
252
    BGTULImmMacro = 237,
253
    BLE = 238,
254
    BLEImmMacro = 239,
255
    BLEL  = 240,
256
    BLELImmMacro  = 241,
257
    BLEU  = 242,
258
    BLEUImmMacro  = 243,
259
    BLEUL = 244,
260
    BLEULImmMacro = 245,
261
    BLT = 246,
262
    BLTImmMacro = 247,
263
    BLTL  = 248,
264
    BLTLImmMacro  = 249,
265
    BLTU  = 250,
266
    BLTUImmMacro  = 251,
267
    BLTUL = 252,
268
    BLTULImmMacro = 253,
269
    BNELImmMacro  = 254,
270
    BPOSGE32_PSEUDO = 255,
271
    BSEL_D_PSEUDO = 256,
272
    BSEL_FD_PSEUDO  = 257,
273
    BSEL_FW_PSEUDO  = 258,
274
    BSEL_H_PSEUDO = 259,
275
    BSEL_W_PSEUDO = 260,
276
    B_MM  = 261,
277
    B_MMR6_Pseudo = 262,
278
    B_MM_Pseudo = 263,
279
    BeqImm  = 264,
280
    BneImm  = 265,
281
    BteqzT8CmpX16 = 266,
282
    BteqzT8CmpiX16  = 267,
283
    BteqzT8SltX16 = 268,
284
    BteqzT8SltiX16  = 269,
285
    BteqzT8SltiuX16 = 270,
286
    BteqzT8SltuX16  = 271,
287
    BtnezT8CmpX16 = 272,
288
    BtnezT8CmpiX16  = 273,
289
    BtnezT8SltX16 = 274,
290
    BtnezT8SltiX16  = 275,
291
    BtnezT8SltiuX16 = 276,
292
    BtnezT8SltuX16  = 277,
293
    BuildPairF64  = 278,
294
    BuildPairF64_64 = 279,
295
    CFTC1 = 280,
296
    CONSTPOOL_ENTRY = 281,
297
    COPY_FD_PSEUDO  = 282,
298
    COPY_FW_PSEUDO  = 283,
299
    CTTC1 = 284,
300
    Constant32  = 285,
301
    DMULImmMacro  = 286,
302
    DMULMacro = 287,
303
    DMULOMacro  = 288,
304
    DMULOUMacro = 289,
305
    DROL  = 290,
306
    DROLImm = 291,
307
    DROR  = 292,
308
    DRORImm = 293,
309
    DSDivIMacro = 294,
310
    DSDivMacro  = 295,
311
    DSRemIMacro = 296,
312
    DSRemMacro  = 297,
313
    DUDivIMacro = 298,
314
    DUDivMacro  = 299,
315
    DURemIMacro = 300,
316
    DURemMacro  = 301,
317
    ERet  = 302,
318
    ExtractElementF64 = 303,
319
    ExtractElementF64_64  = 304,
320
    FABS_D  = 305,
321
    FABS_W  = 306,
322
    FEXP2_D_1_PSEUDO  = 307,
323
    FEXP2_W_1_PSEUDO  = 308,
324
    FILL_FD_PSEUDO  = 309,
325
    FILL_FW_PSEUDO  = 310,
326
    GotPrologue16 = 311,
327
    INSERT_B_VIDX64_PSEUDO  = 312,
328
    INSERT_B_VIDX_PSEUDO  = 313,
329
    INSERT_D_VIDX64_PSEUDO  = 314,
330
    INSERT_D_VIDX_PSEUDO  = 315,
331
    INSERT_FD_PSEUDO  = 316,
332
    INSERT_FD_VIDX64_PSEUDO = 317,
333
    INSERT_FD_VIDX_PSEUDO = 318,
334
    INSERT_FW_PSEUDO  = 319,
335
    INSERT_FW_VIDX64_PSEUDO = 320,
336
    INSERT_FW_VIDX_PSEUDO = 321,
337
    INSERT_H_VIDX64_PSEUDO  = 322,
338
    INSERT_H_VIDX_PSEUDO  = 323,
339
    INSERT_W_VIDX64_PSEUDO  = 324,
340
    INSERT_W_VIDX_PSEUDO  = 325,
341
    JALR64Pseudo  = 326,
342
    JALRHB64Pseudo  = 327,
343
    JALRHBPseudo  = 328,
344
    JALRPseudo  = 329,
345
    JalOneReg = 330,
346
    JalTwoReg = 331,
347
    LDMacro = 332,
348
    LD_F16  = 333,
349
    LOAD_ACC128 = 334,
350
    LOAD_ACC64  = 335,
351
    LOAD_ACC64DSP = 336,
352
    LOAD_CCOND_DSP  = 337,
353
    LONG_BRANCH_ADDiu = 338,
354
    LONG_BRANCH_ADDiu2Op  = 339,
355
    LONG_BRANCH_DADDiu  = 340,
356
    LONG_BRANCH_DADDiu2Op = 341,
357
    LONG_BRANCH_LUi = 342,
358
    LONG_BRANCH_LUi2Op  = 343,
359
    LONG_BRANCH_LUi2Op_64 = 344,
360
    LWM_MM  = 345,
361
    LoadAddrImm32 = 346,
362
    LoadAddrImm64 = 347,
363
    LoadAddrReg32 = 348,
364
    LoadAddrReg64 = 349,
365
    LoadImm32 = 350,
366
    LoadImm64 = 351,
367
    LoadImmDoubleFGR  = 352,
368
    LoadImmDoubleFGR_32 = 353,
369
    LoadImmDoubleGPR  = 354,
370
    LoadImmSingleFGR  = 355,
371
    LoadImmSingleGPR  = 356,
372
    LwConstant32  = 357,
373
    MFTACX  = 358,
374
    MFTC0 = 359,
375
    MFTC1 = 360,
376
    MFTDSP  = 361,
377
    MFTGPR  = 362,
378
    MFTHC1  = 363,
379
    MFTHI = 364,
380
    MFTLO = 365,
381
    MIPSeh_return32 = 366,
382
    MIPSeh_return64 = 367,
383
    MSA_FP_EXTEND_D_PSEUDO  = 368,
384
    MSA_FP_EXTEND_W_PSEUDO  = 369,
385
    MSA_FP_ROUND_D_PSEUDO = 370,
386
    MSA_FP_ROUND_W_PSEUDO = 371,
387
    MTTACX  = 372,
388
    MTTC0 = 373,
389
    MTTC1 = 374,
390
    MTTDSP  = 375,
391
    MTTGPR  = 376,
392
    MTTHC1  = 377,
393
    MTTHI = 378,
394
    MTTLO = 379,
395
    MULImmMacro = 380,
396
    MULOMacro = 381,
397
    MULOUMacro  = 382,
398
    MultRxRy16  = 383,
399
    MultRxRyRz16  = 384,
400
    MultuRxRy16 = 385,
401
    MultuRxRyRz16 = 386,
402
    NOP = 387,
403
    NORImm  = 388,
404
    NORImm64  = 389,
405
    NOR_V_D_PSEUDO  = 390,
406
    NOR_V_H_PSEUDO  = 391,
407
    NOR_V_W_PSEUDO  = 392,
408
    OR_V_D_PSEUDO = 393,
409
    OR_V_H_PSEUDO = 394,
410
    OR_V_W_PSEUDO = 395,
411
    PseudoCMPU_EQ_QB  = 396,
412
    PseudoCMPU_LE_QB  = 397,
413
    PseudoCMPU_LT_QB  = 398,
414
    PseudoCMP_EQ_PH = 399,
415
    PseudoCMP_LE_PH = 400,
416
    PseudoCMP_LT_PH = 401,
417
    PseudoCVT_D32_W = 402,
418
    PseudoCVT_D64_L = 403,
419
    PseudoCVT_D64_W = 404,
420
    PseudoCVT_S_L = 405,
421
    PseudoCVT_S_W = 406,
422
    PseudoDMULT = 407,
423
    PseudoDMULTu  = 408,
424
    PseudoDSDIV = 409,
425
    PseudoDUDIV = 410,
426
    PseudoD_SELECT_I  = 411,
427
    PseudoD_SELECT_I64  = 412,
428
    PseudoIndirectBranch  = 413,
429
    PseudoIndirectBranch64  = 414,
430
    PseudoIndirectBranch64R6  = 415,
431
    PseudoIndirectBranchR6  = 416,
432
    PseudoIndirectBranch_MM = 417,
433
    PseudoIndirectBranch_MMR6 = 418,
434
    PseudoIndirectHazardBranch  = 419,
435
    PseudoIndirectHazardBranch64  = 420,
436
    PseudoIndrectHazardBranch64R6 = 421,
437
    PseudoIndrectHazardBranchR6 = 422,
438
    PseudoMADD  = 423,
439
    PseudoMADDU = 424,
440
    PseudoMADDU_MM  = 425,
441
    PseudoMADD_MM = 426,
442
    PseudoMFHI  = 427,
443
    PseudoMFHI64  = 428,
444
    PseudoMFHI_MM = 429,
445
    PseudoMFLO  = 430,
446
    PseudoMFLO64  = 431,
447
    PseudoMFLO_MM = 432,
448
    PseudoMSUB  = 433,
449
    PseudoMSUBU = 434,
450
    PseudoMSUBU_MM  = 435,
451
    PseudoMSUB_MM = 436,
452
    PseudoMTLOHI  = 437,
453
    PseudoMTLOHI64  = 438,
454
    PseudoMTLOHI_DSP  = 439,
455
    PseudoMTLOHI_MM = 440,
456
    PseudoMULT  = 441,
457
    PseudoMULT_MM = 442,
458
    PseudoMULTu = 443,
459
    PseudoMULTu_MM  = 444,
460
    PseudoPICK_PH = 445,
461
    PseudoPICK_QB = 446,
462
    PseudoReturn  = 447,
463
    PseudoReturn64  = 448,
464
    PseudoSDIV  = 449,
465
    PseudoSELECTFP_F_D32  = 450,
466
    PseudoSELECTFP_F_D64  = 451,
467
    PseudoSELECTFP_F_I  = 452,
468
    PseudoSELECTFP_F_I64  = 453,
469
    PseudoSELECTFP_F_S  = 454,
470
    PseudoSELECTFP_T_D32  = 455,
471
    PseudoSELECTFP_T_D64  = 456,
472
    PseudoSELECTFP_T_I  = 457,
473
    PseudoSELECTFP_T_I64  = 458,
474
    PseudoSELECTFP_T_S  = 459,
475
    PseudoSELECT_D32  = 460,
476
    PseudoSELECT_D64  = 461,
477
    PseudoSELECT_I  = 462,
478
    PseudoSELECT_I64  = 463,
479
    PseudoSELECT_S  = 464,
480
    PseudoTRUNC_W_D = 465,
481
    PseudoTRUNC_W_D32 = 466,
482
    PseudoTRUNC_W_S = 467,
483
    PseudoUDIV  = 468,
484
    ROL = 469,
485
    ROLImm  = 470,
486
    ROR = 471,
487
    RORImm  = 472,
488
    RetRA = 473,
489
    RetRA16 = 474,
490
    SDIV_MM_Pseudo  = 475,
491
    SDMacro = 476,
492
    SDivIMacro  = 477,
493
    SDivMacro = 478,
494
    SEQIMacro = 479,
495
    SEQMacro  = 480,
496
    SLTImm64  = 481,
497
    SLTUImm64 = 482,
498
    SNZ_B_PSEUDO  = 483,
499
    SNZ_D_PSEUDO  = 484,
500
    SNZ_H_PSEUDO  = 485,
501
    SNZ_V_PSEUDO  = 486,
502
    SNZ_W_PSEUDO  = 487,
503
    SRemIMacro  = 488,
504
    SRemMacro = 489,
505
    STORE_ACC128  = 490,
506
    STORE_ACC64 = 491,
507
    STORE_ACC64DSP  = 492,
508
    STORE_CCOND_DSP = 493,
509
    ST_F16  = 494,
510
    SWM_MM  = 495,
511
    SZ_B_PSEUDO = 496,
512
    SZ_D_PSEUDO = 497,
513
    SZ_H_PSEUDO = 498,
514
    SZ_V_PSEUDO = 499,
515
    SZ_W_PSEUDO = 500,
516
    SelBeqZ = 501,
517
    SelBneZ = 502,
518
    SelTBteqZCmp  = 503,
519
    SelTBteqZCmpi = 504,
520
    SelTBteqZSlt  = 505,
521
    SelTBteqZSlti = 506,
522
    SelTBteqZSltiu  = 507,
523
    SelTBteqZSltu = 508,
524
    SelTBtneZCmp  = 509,
525
    SelTBtneZCmpi = 510,
526
    SelTBtneZSlt  = 511,
527
    SelTBtneZSlti = 512,
528
    SelTBtneZSltiu  = 513,
529
    SelTBtneZSltu = 514,
530
    SltCCRxRy16 = 515,
531
    SltiCCRxImmX16  = 516,
532
    SltiuCCRxImmX16 = 517,
533
    SltuCCRxRy16  = 518,
534
    SltuRxRyRz16  = 519,
535
    TAILCALL  = 520,
536
    TAILCALL64R6REG = 521,
537
    TAILCALLHB64R6REG = 522,
538
    TAILCALLHBR6REG = 523,
539
    TAILCALLR6REG = 524,
540
    TAILCALLREG = 525,
541
    TAILCALLREG64 = 526,
542
    TAILCALLREGHB = 527,
543
    TAILCALLREGHB64 = 528,
544
    TAILCALLREG_MM  = 529,
545
    TAILCALLREG_MMR6  = 530,
546
    TAILCALL_MM = 531,
547
    TAILCALL_MMR6 = 532,
548
    TRAP  = 533,
549
    TRAP_MM = 534,
550
    UDIV_MM_Pseudo  = 535,
551
    UDivIMacro  = 536,
552
    UDivMacro = 537,
553
    URemIMacro  = 538,
554
    URemMacro = 539,
555
    Ulh = 540,
556
    Ulhu  = 541,
557
    Ulw = 542,
558
    Ush = 543,
559
    Usw = 544,
560
    XOR_V_D_PSEUDO  = 545,
561
    XOR_V_H_PSEUDO  = 546,
562
    XOR_V_W_PSEUDO  = 547,
563
    ABSQ_S_PH = 548,
564
    ABSQ_S_PH_MM  = 549,
565
    ABSQ_S_QB = 550,
566
    ABSQ_S_QB_MMR2  = 551,
567
    ABSQ_S_W  = 552,
568
    ABSQ_S_W_MM = 553,
569
    ADD = 554,
570
    ADDIUPC = 555,
571
    ADDIUPC_MM  = 556,
572
    ADDIUPC_MMR6  = 557,
573
    ADDIUR1SP_MM  = 558,
574
    ADDIUR2_MM  = 559,
575
    ADDIUS5_MM  = 560,
576
    ADDIUSP_MM  = 561,
577
    ADDIU_MMR6  = 562,
578
    ADDQH_PH  = 563,
579
    ADDQH_PH_MMR2 = 564,
580
    ADDQH_R_PH  = 565,
581
    ADDQH_R_PH_MMR2 = 566,
582
    ADDQH_R_W = 567,
583
    ADDQH_R_W_MMR2  = 568,
584
    ADDQH_W = 569,
585
    ADDQH_W_MMR2  = 570,
586
    ADDQ_PH = 571,
587
    ADDQ_PH_MM  = 572,
588
    ADDQ_S_PH = 573,
589
    ADDQ_S_PH_MM  = 574,
590
    ADDQ_S_W  = 575,
591
    ADDQ_S_W_MM = 576,
592
    ADDSC = 577,
593
    ADDSC_MM  = 578,
594
    ADDS_A_B  = 579,
595
    ADDS_A_D  = 580,
596
    ADDS_A_H  = 581,
597
    ADDS_A_W  = 582,
598
    ADDS_S_B  = 583,
599
    ADDS_S_D  = 584,
600
    ADDS_S_H  = 585,
601
    ADDS_S_W  = 586,
602
    ADDS_U_B  = 587,
603
    ADDS_U_D  = 588,
604
    ADDS_U_H  = 589,
605
    ADDS_U_W  = 590,
606
    ADDU16_MM = 591,
607
    ADDU16_MMR6 = 592,
608
    ADDUH_QB  = 593,
609
    ADDUH_QB_MMR2 = 594,
610
    ADDUH_R_QB  = 595,
611
    ADDUH_R_QB_MMR2 = 596,
612
    ADDU_MMR6 = 597,
613
    ADDU_PH = 598,
614
    ADDU_PH_MMR2  = 599,
615
    ADDU_QB = 600,
616
    ADDU_QB_MM  = 601,
617
    ADDU_S_PH = 602,
618
    ADDU_S_PH_MMR2  = 603,
619
    ADDU_S_QB = 604,
620
    ADDU_S_QB_MM  = 605,
621
    ADDVI_B = 606,
622
    ADDVI_D = 607,
623
    ADDVI_H = 608,
624
    ADDVI_W = 609,
625
    ADDV_B  = 610,
626
    ADDV_D  = 611,
627
    ADDV_H  = 612,
628
    ADDV_W  = 613,
629
    ADDWC = 614,
630
    ADDWC_MM  = 615,
631
    ADD_A_B = 616,
632
    ADD_A_D = 617,
633
    ADD_A_H = 618,
634
    ADD_A_W = 619,
635
    ADD_MM  = 620,
636
    ADD_MMR6  = 621,
637
    ADDi  = 622,
638
    ADDi_MM = 623,
639
    ADDiu = 624,
640
    ADDiu_MM  = 625,
641
    ADDu  = 626,
642
    ADDu_MM = 627,
643
    ALIGN = 628,
644
    ALIGN_MMR6  = 629,
645
    ALUIPC  = 630,
646
    ALUIPC_MMR6 = 631,
647
    AND = 632,
648
    AND16_MM  = 633,
649
    AND16_MMR6  = 634,
650
    AND64 = 635,
651
    ANDI16_MM = 636,
652
    ANDI16_MMR6 = 637,
653
    ANDI_B  = 638,
654
    ANDI_MMR6 = 639,
655
    AND_MM  = 640,
656
    AND_MMR6  = 641,
657
    AND_V = 642,
658
    ANDi  = 643,
659
    ANDi64  = 644,
660
    ANDi_MM = 645,
661
    APPEND  = 646,
662
    APPEND_MMR2 = 647,
663
    ASUB_S_B  = 648,
664
    ASUB_S_D  = 649,
665
    ASUB_S_H  = 650,
666
    ASUB_S_W  = 651,
667
    ASUB_U_B  = 652,
668
    ASUB_U_D  = 653,
669
    ASUB_U_H  = 654,
670
    ASUB_U_W  = 655,
671
    AUI = 656,
672
    AUIPC = 657,
673
    AUIPC_MMR6  = 658,
674
    AUI_MMR6  = 659,
675
    AVER_S_B  = 660,
676
    AVER_S_D  = 661,
677
    AVER_S_H  = 662,
678
    AVER_S_W  = 663,
679
    AVER_U_B  = 664,
680
    AVER_U_D  = 665,
681
    AVER_U_H  = 666,
682
    AVER_U_W  = 667,
683
    AVE_S_B = 668,
684
    AVE_S_D = 669,
685
    AVE_S_H = 670,
686
    AVE_S_W = 671,
687
    AVE_U_B = 672,
688
    AVE_U_D = 673,
689
    AVE_U_H = 674,
690
    AVE_U_W = 675,
691
    AddiuRxImmX16 = 676,
692
    AddiuRxPcImmX16 = 677,
693
    AddiuRxRxImm16  = 678,
694
    AddiuRxRxImmX16 = 679,
695
    AddiuRxRyOffMemX16  = 680,
696
    AddiuSpImm16  = 681,
697
    AddiuSpImmX16 = 682,
698
    AdduRxRyRz16  = 683,
699
    AndRxRxRy16 = 684,
700
    B16_MM  = 685,
701
    BADDu = 686,
702
    BAL = 687,
703
    BALC  = 688,
704
    BALC_MMR6 = 689,
705
    BALIGN  = 690,
706
    BALIGN_MMR2 = 691,
707
    BBIT0 = 692,
708
    BBIT032 = 693,
709
    BBIT1 = 694,
710
    BBIT132 = 695,
711
    BC  = 696,
712
    BC16_MMR6 = 697,
713
    BC1EQZ  = 698,
714
    BC1EQZC_MMR6  = 699,
715
    BC1F  = 700,
716
    BC1FL = 701,
717
    BC1F_MM = 702,
718
    BC1NEZ  = 703,
719
    BC1NEZC_MMR6  = 704,
720
    BC1T  = 705,
721
    BC1TL = 706,
722
    BC1T_MM = 707,
723
    BC2EQZ  = 708,
724
    BC2EQZC_MMR6  = 709,
725
    BC2NEZ  = 710,
726
    BC2NEZC_MMR6  = 711,
727
    BCLRI_B = 712,
728
    BCLRI_D = 713,
729
    BCLRI_H = 714,
730
    BCLRI_W = 715,
731
    BCLR_B  = 716,
732
    BCLR_D  = 717,
733
    BCLR_H  = 718,
734
    BCLR_W  = 719,
735
    BC_MMR6 = 720,
736
    BEQ = 721,
737
    BEQ64 = 722,
738
    BEQC  = 723,
739
    BEQC64  = 724,
740
    BEQC_MMR6 = 725,
741
    BEQL  = 726,
742
    BEQZ16_MM = 727,
743
    BEQZALC = 728,
744
    BEQZALC_MMR6  = 729,
745
    BEQZC = 730,
746
    BEQZC16_MMR6  = 731,
747
    BEQZC64 = 732,
748
    BEQZC_MM  = 733,
749
    BEQZC_MMR6  = 734,
750
    BEQ_MM  = 735,
751
    BGEC  = 736,
752
    BGEC64  = 737,
753
    BGEC_MMR6 = 738,
754
    BGEUC = 739,
755
    BGEUC64 = 740,
756
    BGEUC_MMR6  = 741,
757
    BGEZ  = 742,
758
    BGEZ64  = 743,
759
    BGEZAL  = 744,
760
    BGEZALC = 745,
761
    BGEZALC_MMR6  = 746,
762
    BGEZALL = 747,
763
    BGEZALS_MM  = 748,
764
    BGEZAL_MM = 749,
765
    BGEZC = 750,
766
    BGEZC64 = 751,
767
    BGEZC_MMR6  = 752,
768
    BGEZL = 753,
769
    BGEZ_MM = 754,
770
    BGTZ  = 755,
771
    BGTZ64  = 756,
772
    BGTZALC = 757,
773
    BGTZALC_MMR6  = 758,
774
    BGTZC = 759,
775
    BGTZC64 = 760,
776
    BGTZC_MMR6  = 761,
777
    BGTZL = 762,
778
    BGTZ_MM = 763,
779
    BINSLI_B  = 764,
780
    BINSLI_D  = 765,
781
    BINSLI_H  = 766,
782
    BINSLI_W  = 767,
783
    BINSL_B = 768,
784
    BINSL_D = 769,
785
    BINSL_H = 770,
786
    BINSL_W = 771,
787
    BINSRI_B  = 772,
788
    BINSRI_D  = 773,
789
    BINSRI_H  = 774,
790
    BINSRI_W  = 775,
791
    BINSR_B = 776,
792
    BINSR_D = 777,
793
    BINSR_H = 778,
794
    BINSR_W = 779,
795
    BITREV  = 780,
796
    BITREV_MM = 781,
797
    BITSWAP = 782,
798
    BITSWAP_MMR6  = 783,
799
    BLEZ  = 784,
800
    BLEZ64  = 785,
801
    BLEZALC = 786,
802
    BLEZALC_MMR6  = 787,
803
    BLEZC = 788,
804
    BLEZC64 = 789,
805
    BLEZC_MMR6  = 790,
806
    BLEZL = 791,
807
    BLEZ_MM = 792,
808
    BLTC  = 793,
809
    BLTC64  = 794,
810
    BLTC_MMR6 = 795,
811
    BLTUC = 796,
812
    BLTUC64 = 797,
813
    BLTUC_MMR6  = 798,
814
    BLTZ  = 799,
815
    BLTZ64  = 800,
816
    BLTZAL  = 801,
817
    BLTZALC = 802,
818
    BLTZALC_MMR6  = 803,
819
    BLTZALL = 804,
820
    BLTZALS_MM  = 805,
821
    BLTZAL_MM = 806,
822
    BLTZC = 807,
823
    BLTZC64 = 808,
824
    BLTZC_MMR6  = 809,
825
    BLTZL = 810,
826
    BLTZ_MM = 811,
827
    BMNZI_B = 812,
828
    BMNZ_V  = 813,
829
    BMZI_B  = 814,
830
    BMZ_V = 815,
831
    BNE = 816,
832
    BNE64 = 817,
833
    BNEC  = 818,
834
    BNEC64  = 819,
835
    BNEC_MMR6 = 820,
836
    BNEGI_B = 821,
837
    BNEGI_D = 822,
838
    BNEGI_H = 823,
839
    BNEGI_W = 824,
840
    BNEG_B  = 825,
841
    BNEG_D  = 826,
842
    BNEG_H  = 827,
843
    BNEG_W  = 828,
844
    BNEL  = 829,
845
    BNEZ16_MM = 830,
846
    BNEZALC = 831,
847
    BNEZALC_MMR6  = 832,
848
    BNEZC = 833,
849
    BNEZC16_MMR6  = 834,
850
    BNEZC64 = 835,
851
    BNEZC_MM  = 836,
852
    BNEZC_MMR6  = 837,
853
    BNE_MM  = 838,
854
    BNVC  = 839,
855
    BNVC_MMR6 = 840,
856
    BNZ_B = 841,
857
    BNZ_D = 842,
858
    BNZ_H = 843,
859
    BNZ_V = 844,
860
    BNZ_W = 845,
861
    BOVC  = 846,
862
    BOVC_MMR6 = 847,
863
    BPOSGE32  = 848,
864
    BPOSGE32C_MMR3  = 849,
865
    BPOSGE32_MM = 850,
866
    BREAK = 851,
867
    BREAK16_MM  = 852,
868
    BREAK16_MMR6  = 853,
869
    BREAK_MM  = 854,
870
    BREAK_MMR6  = 855,
871
    BSELI_B = 856,
872
    BSEL_V  = 857,
873
    BSETI_B = 858,
874
    BSETI_D = 859,
875
    BSETI_H = 860,
876
    BSETI_W = 861,
877
    BSET_B  = 862,
878
    BSET_D  = 863,
879
    BSET_H  = 864,
880
    BSET_W  = 865,
881
    BZ_B  = 866,
882
    BZ_D  = 867,
883
    BZ_H  = 868,
884
    BZ_V  = 869,
885
    BZ_W  = 870,
886
    BeqzRxImm16 = 871,
887
    BeqzRxImmX16  = 872,
888
    Bimm16  = 873,
889
    BimmX16 = 874,
890
    BnezRxImm16 = 875,
891
    BnezRxImmX16  = 876,
892
    Break16 = 877,
893
    Bteqz16 = 878,
894
    BteqzX16  = 879,
895
    Btnez16 = 880,
896
    BtnezX16  = 881,
897
    CACHE = 882,
898
    CACHEE  = 883,
899
    CACHEE_MM = 884,
900
    CACHE_MM  = 885,
901
    CACHE_MMR6  = 886,
902
    CACHE_R6  = 887,
903
    CEIL_L_D64  = 888,
904
    CEIL_L_D_MMR6 = 889,
905
    CEIL_L_S  = 890,
906
    CEIL_L_S_MMR6 = 891,
907
    CEIL_W_D32  = 892,
908
    CEIL_W_D64  = 893,
909
    CEIL_W_D_MMR6 = 894,
910
    CEIL_W_MM = 895,
911
    CEIL_W_S  = 896,
912
    CEIL_W_S_MM = 897,
913
    CEIL_W_S_MMR6 = 898,
914
    CEQI_B  = 899,
915
    CEQI_D  = 900,
916
    CEQI_H  = 901,
917
    CEQI_W  = 902,
918
    CEQ_B = 903,
919
    CEQ_D = 904,
920
    CEQ_H = 905,
921
    CEQ_W = 906,
922
    CFC1  = 907,
923
    CFC1_MM = 908,
924
    CFC2_MM = 909,
925
    CFCMSA  = 910,
926
    CINS  = 911,
927
    CINS32  = 912,
928
    CINS64_32 = 913,
929
    CINS_i32  = 914,
930
    CLASS_D = 915,
931
    CLASS_D_MMR6  = 916,
932
    CLASS_S = 917,
933
    CLASS_S_MMR6  = 918,
934
    CLEI_S_B  = 919,
935
    CLEI_S_D  = 920,
936
    CLEI_S_H  = 921,
937
    CLEI_S_W  = 922,
938
    CLEI_U_B  = 923,
939
    CLEI_U_D  = 924,
940
    CLEI_U_H  = 925,
941
    CLEI_U_W  = 926,
942
    CLE_S_B = 927,
943
    CLE_S_D = 928,
944
    CLE_S_H = 929,
945
    CLE_S_W = 930,
946
    CLE_U_B = 931,
947
    CLE_U_D = 932,
948
    CLE_U_H = 933,
949
    CLE_U_W = 934,
950
    CLO = 935,
951
    CLO_MM  = 936,
952
    CLO_MMR6  = 937,
953
    CLO_R6  = 938,
954
    CLTI_S_B  = 939,
955
    CLTI_S_D  = 940,
956
    CLTI_S_H  = 941,
957
    CLTI_S_W  = 942,
958
    CLTI_U_B  = 943,
959
    CLTI_U_D  = 944,
960
    CLTI_U_H  = 945,
961
    CLTI_U_W  = 946,
962
    CLT_S_B = 947,
963
    CLT_S_D = 948,
964
    CLT_S_H = 949,
965
    CLT_S_W = 950,
966
    CLT_U_B = 951,
967
    CLT_U_D = 952,
968
    CLT_U_H = 953,
969
    CLT_U_W = 954,
970
    CLZ = 955,
971
    CLZ_MM  = 956,
972
    CLZ_MMR6  = 957,
973
    CLZ_R6  = 958,
974
    CMPGDU_EQ_QB  = 959,
975
    CMPGDU_EQ_QB_MMR2 = 960,
976
    CMPGDU_LE_QB  = 961,
977
    CMPGDU_LE_QB_MMR2 = 962,
978
    CMPGDU_LT_QB  = 963,
979
    CMPGDU_LT_QB_MMR2 = 964,
980
    CMPGU_EQ_QB = 965,
981
    CMPGU_EQ_QB_MM  = 966,
982
    CMPGU_LE_QB = 967,
983
    CMPGU_LE_QB_MM  = 968,
984
    CMPGU_LT_QB = 969,
985
    CMPGU_LT_QB_MM  = 970,
986
    CMPU_EQ_QB  = 971,
987
    CMPU_EQ_QB_MM = 972,
988
    CMPU_LE_QB  = 973,
989
    CMPU_LE_QB_MM = 974,
990
    CMPU_LT_QB  = 975,
991
    CMPU_LT_QB_MM = 976,
992
    CMP_AF_D_MMR6 = 977,
993
    CMP_AF_S_MMR6 = 978,
994
    CMP_EQ_D  = 979,
995
    CMP_EQ_D_MMR6 = 980,
996
    CMP_EQ_PH = 981,
997
    CMP_EQ_PH_MM  = 982,
998
    CMP_EQ_S  = 983,
999
    CMP_EQ_S_MMR6 = 984,
1000
    CMP_F_D = 985,
1001
    CMP_F_S = 986,
1002
    CMP_LE_D  = 987,
1003
    CMP_LE_D_MMR6 = 988,
1004
    CMP_LE_PH = 989,
1005
    CMP_LE_PH_MM  = 990,
1006
    CMP_LE_S  = 991,
1007
    CMP_LE_S_MMR6 = 992,
1008
    CMP_LT_D  = 993,
1009
    CMP_LT_D_MMR6 = 994,
1010
    CMP_LT_PH = 995,
1011
    CMP_LT_PH_MM  = 996,
1012
    CMP_LT_S  = 997,
1013
    CMP_LT_S_MMR6 = 998,
1014
    CMP_SAF_D = 999,
1015
    CMP_SAF_D_MMR6  = 1000,
1016
    CMP_SAF_S = 1001,
1017
    CMP_SAF_S_MMR6  = 1002,
1018
    CMP_SEQ_D = 1003,
1019
    CMP_SEQ_D_MMR6  = 1004,
1020
    CMP_SEQ_S = 1005,
1021
    CMP_SEQ_S_MMR6  = 1006,
1022
    CMP_SLE_D = 1007,
1023
    CMP_SLE_D_MMR6  = 1008,
1024
    CMP_SLE_S = 1009,
1025
    CMP_SLE_S_MMR6  = 1010,
1026
    CMP_SLT_D = 1011,
1027
    CMP_SLT_D_MMR6  = 1012,
1028
    CMP_SLT_S = 1013,
1029
    CMP_SLT_S_MMR6  = 1014,
1030
    CMP_SUEQ_D  = 1015,
1031
    CMP_SUEQ_D_MMR6 = 1016,
1032
    CMP_SUEQ_S  = 1017,
1033
    CMP_SUEQ_S_MMR6 = 1018,
1034
    CMP_SULE_D  = 1019,
1035
    CMP_SULE_D_MMR6 = 1020,
1036
    CMP_SULE_S  = 1021,
1037
    CMP_SULE_S_MMR6 = 1022,
1038
    CMP_SULT_D  = 1023,
1039
    CMP_SULT_D_MMR6 = 1024,
1040
    CMP_SULT_S  = 1025,
1041
    CMP_SULT_S_MMR6 = 1026,
1042
    CMP_SUN_D = 1027,
1043
    CMP_SUN_D_MMR6  = 1028,
1044
    CMP_SUN_S = 1029,
1045
    CMP_SUN_S_MMR6  = 1030,
1046
    CMP_UEQ_D = 1031,
1047
    CMP_UEQ_D_MMR6  = 1032,
1048
    CMP_UEQ_S = 1033,
1049
    CMP_UEQ_S_MMR6  = 1034,
1050
    CMP_ULE_D = 1035,
1051
    CMP_ULE_D_MMR6  = 1036,
1052
    CMP_ULE_S = 1037,
1053
    CMP_ULE_S_MMR6  = 1038,
1054
    CMP_ULT_D = 1039,
1055
    CMP_ULT_D_MMR6  = 1040,
1056
    CMP_ULT_S = 1041,
1057
    CMP_ULT_S_MMR6  = 1042,
1058
    CMP_UN_D  = 1043,
1059
    CMP_UN_D_MMR6 = 1044,
1060
    CMP_UN_S  = 1045,
1061
    CMP_UN_S_MMR6 = 1046,
1062
    COPY_S_B  = 1047,
1063
    COPY_S_D  = 1048,
1064
    COPY_S_H  = 1049,
1065
    COPY_S_W  = 1050,
1066
    COPY_U_B  = 1051,
1067
    COPY_U_H  = 1052,
1068
    COPY_U_W  = 1053,
1069
    CRC32B  = 1054,
1070
    CRC32CB = 1055,
1071
    CRC32CD = 1056,
1072
    CRC32CH = 1057,
1073
    CRC32CW = 1058,
1074
    CRC32D  = 1059,
1075
    CRC32H  = 1060,
1076
    CRC32W  = 1061,
1077
    CTC1  = 1062,
1078
    CTC1_MM = 1063,
1079
    CTC2_MM = 1064,
1080
    CTCMSA  = 1065,
1081
    CVT_D32_S = 1066,
1082
    CVT_D32_S_MM  = 1067,
1083
    CVT_D32_W = 1068,
1084
    CVT_D32_W_MM  = 1069,
1085
    CVT_D64_L = 1070,
1086
    CVT_D64_S = 1071,
1087
    CVT_D64_S_MM  = 1072,
1088
    CVT_D64_W = 1073,
1089
    CVT_D64_W_MM  = 1074,
1090
    CVT_D_L_MMR6  = 1075,
1091
    CVT_L_D64 = 1076,
1092
    CVT_L_D64_MM  = 1077,
1093
    CVT_L_D_MMR6  = 1078,
1094
    CVT_L_S = 1079,
1095
    CVT_L_S_MM  = 1080,
1096
    CVT_L_S_MMR6  = 1081,
1097
    CVT_PS_S64  = 1082,
1098
    CVT_S_D32 = 1083,
1099
    CVT_S_D32_MM  = 1084,
1100
    CVT_S_D64 = 1085,
1101
    CVT_S_D64_MM  = 1086,
1102
    CVT_S_L = 1087,
1103
    CVT_S_L_MMR6  = 1088,
1104
    CVT_S_PL64  = 1089,
1105
    CVT_S_PU64  = 1090,
1106
    CVT_S_W = 1091,
1107
    CVT_S_W_MM  = 1092,
1108
    CVT_S_W_MMR6  = 1093,
1109
    CVT_W_D32 = 1094,
1110
    CVT_W_D32_MM  = 1095,
1111
    CVT_W_D64 = 1096,
1112
    CVT_W_D64_MM  = 1097,
1113
    CVT_W_S = 1098,
1114
    CVT_W_S_MM  = 1099,
1115
    CVT_W_S_MMR6  = 1100,
1116
    C_EQ_D32  = 1101,
1117
    C_EQ_D32_MM = 1102,
1118
    C_EQ_D64  = 1103,
1119
    C_EQ_D64_MM = 1104,
1120
    C_EQ_S  = 1105,
1121
    C_EQ_S_MM = 1106,
1122
    C_F_D32 = 1107,
1123
    C_F_D32_MM  = 1108,
1124
    C_F_D64 = 1109,
1125
    C_F_D64_MM  = 1110,
1126
    C_F_S = 1111,
1127
    C_F_S_MM  = 1112,
1128
    C_LE_D32  = 1113,
1129
    C_LE_D32_MM = 1114,
1130
    C_LE_D64  = 1115,
1131
    C_LE_D64_MM = 1116,
1132
    C_LE_S  = 1117,
1133
    C_LE_S_MM = 1118,
1134
    C_LT_D32  = 1119,
1135
    C_LT_D32_MM = 1120,
1136
    C_LT_D64  = 1121,
1137
    C_LT_D64_MM = 1122,
1138
    C_LT_S  = 1123,
1139
    C_LT_S_MM = 1124,
1140
    C_NGE_D32 = 1125,
1141
    C_NGE_D32_MM  = 1126,
1142
    C_NGE_D64 = 1127,
1143
    C_NGE_D64_MM  = 1128,
1144
    C_NGE_S = 1129,
1145
    C_NGE_S_MM  = 1130,
1146
    C_NGLE_D32  = 1131,
1147
    C_NGLE_D32_MM = 1132,
1148
    C_NGLE_D64  = 1133,
1149
    C_NGLE_D64_MM = 1134,
1150
    C_NGLE_S  = 1135,
1151
    C_NGLE_S_MM = 1136,
1152
    C_NGL_D32 = 1137,
1153
    C_NGL_D32_MM  = 1138,
1154
    C_NGL_D64 = 1139,
1155
    C_NGL_D64_MM  = 1140,
1156
    C_NGL_S = 1141,
1157
    C_NGL_S_MM  = 1142,
1158
    C_NGT_D32 = 1143,
1159
    C_NGT_D32_MM  = 1144,
1160
    C_NGT_D64 = 1145,
1161
    C_NGT_D64_MM  = 1146,
1162
    C_NGT_S = 1147,
1163
    C_NGT_S_MM  = 1148,
1164
    C_OLE_D32 = 1149,
1165
    C_OLE_D32_MM  = 1150,
1166
    C_OLE_D64 = 1151,
1167
    C_OLE_D64_MM  = 1152,
1168
    C_OLE_S = 1153,
1169
    C_OLE_S_MM  = 1154,
1170
    C_OLT_D32 = 1155,
1171
    C_OLT_D32_MM  = 1156,
1172
    C_OLT_D64 = 1157,
1173
    C_OLT_D64_MM  = 1158,
1174
    C_OLT_S = 1159,
1175
    C_OLT_S_MM  = 1160,
1176
    C_SEQ_D32 = 1161,
1177
    C_SEQ_D32_MM  = 1162,
1178
    C_SEQ_D64 = 1163,
1179
    C_SEQ_D64_MM  = 1164,
1180
    C_SEQ_S = 1165,
1181
    C_SEQ_S_MM  = 1166,
1182
    C_SF_D32  = 1167,
1183
    C_SF_D32_MM = 1168,
1184
    C_SF_D64  = 1169,
1185
    C_SF_D64_MM = 1170,
1186
    C_SF_S  = 1171,
1187
    C_SF_S_MM = 1172,
1188
    C_UEQ_D32 = 1173,
1189
    C_UEQ_D32_MM  = 1174,
1190
    C_UEQ_D64 = 1175,
1191
    C_UEQ_D64_MM  = 1176,
1192
    C_UEQ_S = 1177,
1193
    C_UEQ_S_MM  = 1178,
1194
    C_ULE_D32 = 1179,
1195
    C_ULE_D32_MM  = 1180,
1196
    C_ULE_D64 = 1181,
1197
    C_ULE_D64_MM  = 1182,
1198
    C_ULE_S = 1183,
1199
    C_ULE_S_MM  = 1184,
1200
    C_ULT_D32 = 1185,
1201
    C_ULT_D32_MM  = 1186,
1202
    C_ULT_D64 = 1187,
1203
    C_ULT_D64_MM  = 1188,
1204
    C_ULT_S = 1189,
1205
    C_ULT_S_MM  = 1190,
1206
    C_UN_D32  = 1191,
1207
    C_UN_D32_MM = 1192,
1208
    C_UN_D64  = 1193,
1209
    C_UN_D64_MM = 1194,
1210
    C_UN_S  = 1195,
1211
    C_UN_S_MM = 1196,
1212
    CmpRxRy16 = 1197,
1213
    CmpiRxImm16 = 1198,
1214
    CmpiRxImmX16  = 1199,
1215
    DADD  = 1200,
1216
    DADDi = 1201,
1217
    DADDiu  = 1202,
1218
    DADDu = 1203,
1219
    DAHI  = 1204,
1220
    DALIGN  = 1205,
1221
    DATI  = 1206,
1222
    DAUI  = 1207,
1223
    DBITSWAP  = 1208,
1224
    DCLO  = 1209,
1225
    DCLO_R6 = 1210,
1226
    DCLZ  = 1211,
1227
    DCLZ_R6 = 1212,
1228
    DDIV  = 1213,
1229
    DDIVU = 1214,
1230
    DERET = 1215,
1231
    DERET_MM  = 1216,
1232
    DERET_MMR6  = 1217,
1233
    DEXT  = 1218,
1234
    DEXT64_32 = 1219,
1235
    DEXTM = 1220,
1236
    DEXTU = 1221,
1237
    DI  = 1222,
1238
    DINS  = 1223,
1239
    DINSM = 1224,
1240
    DINSU = 1225,
1241
    DIV = 1226,
1242
    DIVU  = 1227,
1243
    DIVU_MMR6 = 1228,
1244
    DIV_MMR6  = 1229,
1245
    DIV_S_B = 1230,
1246
    DIV_S_D = 1231,
1247
    DIV_S_H = 1232,
1248
    DIV_S_W = 1233,
1249
    DIV_U_B = 1234,
1250
    DIV_U_D = 1235,
1251
    DIV_U_H = 1236,
1252
    DIV_U_W = 1237,
1253
    DI_MM = 1238,
1254
    DI_MMR6 = 1239,
1255
    DLSA  = 1240,
1256
    DLSA_R6 = 1241,
1257
    DMFC0 = 1242,
1258
    DMFC1 = 1243,
1259
    DMFC2 = 1244,
1260
    DMFC2_OCTEON  = 1245,
1261
    DMFGC0  = 1246,
1262
    DMOD  = 1247,
1263
    DMODU = 1248,
1264
    DMT = 1249,
1265
    DMTC0 = 1250,
1266
    DMTC1 = 1251,
1267
    DMTC2 = 1252,
1268
    DMTC2_OCTEON  = 1253,
1269
    DMTGC0  = 1254,
1270
    DMUH  = 1255,
1271
    DMUHU = 1256,
1272
    DMUL  = 1257,
1273
    DMULT = 1258,
1274
    DMULTu  = 1259,
1275
    DMULU = 1260,
1276
    DMUL_R6 = 1261,
1277
    DOTP_S_D  = 1262,
1278
    DOTP_S_H  = 1263,
1279
    DOTP_S_W  = 1264,
1280
    DOTP_U_D  = 1265,
1281
    DOTP_U_H  = 1266,
1282
    DOTP_U_W  = 1267,
1283
    DPADD_S_D = 1268,
1284
    DPADD_S_H = 1269,
1285
    DPADD_S_W = 1270,
1286
    DPADD_U_D = 1271,
1287
    DPADD_U_H = 1272,
1288
    DPADD_U_W = 1273,
1289
    DPAQX_SA_W_PH = 1274,
1290
    DPAQX_SA_W_PH_MMR2  = 1275,
1291
    DPAQX_S_W_PH  = 1276,
1292
    DPAQX_S_W_PH_MMR2 = 1277,
1293
    DPAQ_SA_L_W = 1278,
1294
    DPAQ_SA_L_W_MM  = 1279,
1295
    DPAQ_S_W_PH = 1280,
1296
    DPAQ_S_W_PH_MM  = 1281,
1297
    DPAU_H_QBL  = 1282,
1298
    DPAU_H_QBL_MM = 1283,
1299
    DPAU_H_QBR  = 1284,
1300
    DPAU_H_QBR_MM = 1285,
1301
    DPAX_W_PH = 1286,
1302
    DPAX_W_PH_MMR2  = 1287,
1303
    DPA_W_PH  = 1288,
1304
    DPA_W_PH_MMR2 = 1289,
1305
    DPOP  = 1290,
1306
    DPSQX_SA_W_PH = 1291,
1307
    DPSQX_SA_W_PH_MMR2  = 1292,
1308
    DPSQX_S_W_PH  = 1293,
1309
    DPSQX_S_W_PH_MMR2 = 1294,
1310
    DPSQ_SA_L_W = 1295,
1311
    DPSQ_SA_L_W_MM  = 1296,
1312
    DPSQ_S_W_PH = 1297,
1313
    DPSQ_S_W_PH_MM  = 1298,
1314
    DPSUB_S_D = 1299,
1315
    DPSUB_S_H = 1300,
1316
    DPSUB_S_W = 1301,
1317
    DPSUB_U_D = 1302,
1318
    DPSUB_U_H = 1303,
1319
    DPSUB_U_W = 1304,
1320
    DPSU_H_QBL  = 1305,
1321
    DPSU_H_QBL_MM = 1306,
1322
    DPSU_H_QBR  = 1307,
1323
    DPSU_H_QBR_MM = 1308,
1324
    DPSX_W_PH = 1309,
1325
    DPSX_W_PH_MMR2  = 1310,
1326
    DPS_W_PH  = 1311,
1327
    DPS_W_PH_MMR2 = 1312,
1328
    DROTR = 1313,
1329
    DROTR32 = 1314,
1330
    DROTRV  = 1315,
1331
    DSBH  = 1316,
1332
    DSDIV = 1317,
1333
    DSHD  = 1318,
1334
    DSLL  = 1319,
1335
    DSLL32  = 1320,
1336
    DSLL64_32 = 1321,
1337
    DSLLV = 1322,
1338
    DSRA  = 1323,
1339
    DSRA32  = 1324,
1340
    DSRAV = 1325,
1341
    DSRL  = 1326,
1342
    DSRL32  = 1327,
1343
    DSRLV = 1328,
1344
    DSUB  = 1329,
1345
    DSUBu = 1330,
1346
    DUDIV = 1331,
1347
    DVP = 1332,
1348
    DVPE  = 1333,
1349
    DVP_MMR6  = 1334,
1350
    DivRxRy16 = 1335,
1351
    DivuRxRy16  = 1336,
1352
    EHB = 1337,
1353
    EHB_MM  = 1338,
1354
    EHB_MMR6  = 1339,
1355
    EI  = 1340,
1356
    EI_MM = 1341,
1357
    EI_MMR6 = 1342,
1358
    EMT = 1343,
1359
    ERET  = 1344,
1360
    ERETNC  = 1345,
1361
    ERETNC_MMR6 = 1346,
1362
    ERET_MM = 1347,
1363
    ERET_MMR6 = 1348,
1364
    EVP = 1349,
1365
    EVPE  = 1350,
1366
    EVP_MMR6  = 1351,
1367
    EXT = 1352,
1368
    EXTP  = 1353,
1369
    EXTPDP  = 1354,
1370
    EXTPDPV = 1355,
1371
    EXTPDPV_MM  = 1356,
1372
    EXTPDP_MM = 1357,
1373
    EXTPV = 1358,
1374
    EXTPV_MM  = 1359,
1375
    EXTP_MM = 1360,
1376
    EXTRV_RS_W  = 1361,
1377
    EXTRV_RS_W_MM = 1362,
1378
    EXTRV_R_W = 1363,
1379
    EXTRV_R_W_MM  = 1364,
1380
    EXTRV_S_H = 1365,
1381
    EXTRV_S_H_MM  = 1366,
1382
    EXTRV_W = 1367,
1383
    EXTRV_W_MM  = 1368,
1384
    EXTR_RS_W = 1369,
1385
    EXTR_RS_W_MM  = 1370,
1386
    EXTR_R_W  = 1371,
1387
    EXTR_R_W_MM = 1372,
1388
    EXTR_S_H  = 1373,
1389
    EXTR_S_H_MM = 1374,
1390
    EXTR_W  = 1375,
1391
    EXTR_W_MM = 1376,
1392
    EXTS  = 1377,
1393
    EXTS32  = 1378,
1394
    EXT_MM  = 1379,
1395
    EXT_MMR6  = 1380,
1396
    FABS_D32  = 1381,
1397
    FABS_D32_MM = 1382,
1398
    FABS_D64  = 1383,
1399
    FABS_D64_MM = 1384,
1400
    FABS_S  = 1385,
1401
    FABS_S_MM = 1386,
1402
    FADD_D  = 1387,
1403
    FADD_D32  = 1388,
1404
    FADD_D32_MM = 1389,
1405
    FADD_D64  = 1390,
1406
    FADD_D64_MM = 1391,
1407
    FADD_S  = 1392,
1408
    FADD_S_MM = 1393,
1409
    FADD_S_MMR6 = 1394,
1410
    FADD_W  = 1395,
1411
    FCAF_D  = 1396,
1412
    FCAF_W  = 1397,
1413
    FCEQ_D  = 1398,
1414
    FCEQ_W  = 1399,
1415
    FCLASS_D  = 1400,
1416
    FCLASS_W  = 1401,
1417
    FCLE_D  = 1402,
1418
    FCLE_W  = 1403,
1419
    FCLT_D  = 1404,
1420
    FCLT_W  = 1405,
1421
    FCMP_D32  = 1406,
1422
    FCMP_D32_MM = 1407,
1423
    FCMP_D64  = 1408,
1424
    FCMP_S32  = 1409,
1425
    FCMP_S32_MM = 1410,
1426
    FCNE_D  = 1411,
1427
    FCNE_W  = 1412,
1428
    FCOR_D  = 1413,
1429
    FCOR_W  = 1414,
1430
    FCUEQ_D = 1415,
1431
    FCUEQ_W = 1416,
1432
    FCULE_D = 1417,
1433
    FCULE_W = 1418,
1434
    FCULT_D = 1419,
1435
    FCULT_W = 1420,
1436
    FCUNE_D = 1421,
1437
    FCUNE_W = 1422,
1438
    FCUN_D  = 1423,
1439
    FCUN_W  = 1424,
1440
    FDIV_D  = 1425,
1441
    FDIV_D32  = 1426,
1442
    FDIV_D32_MM = 1427,
1443
    FDIV_D64  = 1428,
1444
    FDIV_D64_MM = 1429,
1445
    FDIV_S  = 1430,
1446
    FDIV_S_MM = 1431,
1447
    FDIV_S_MMR6 = 1432,
1448
    FDIV_W  = 1433,
1449
    FEXDO_H = 1434,
1450
    FEXDO_W = 1435,
1451
    FEXP2_D = 1436,
1452
    FEXP2_W = 1437,
1453
    FEXUPL_D  = 1438,
1454
    FEXUPL_W  = 1439,
1455
    FEXUPR_D  = 1440,
1456
    FEXUPR_W  = 1441,
1457
    FFINT_S_D = 1442,
1458
    FFINT_S_W = 1443,
1459
    FFINT_U_D = 1444,
1460
    FFINT_U_W = 1445,
1461
    FFQL_D  = 1446,
1462
    FFQL_W  = 1447,
1463
    FFQR_D  = 1448,
1464
    FFQR_W  = 1449,
1465
    FILL_B  = 1450,
1466
    FILL_D  = 1451,
1467
    FILL_H  = 1452,
1468
    FILL_W  = 1453,
1469
    FLOG2_D = 1454,
1470
    FLOG2_W = 1455,
1471
    FLOOR_L_D64 = 1456,
1472
    FLOOR_L_D_MMR6  = 1457,
1473
    FLOOR_L_S = 1458,
1474
    FLOOR_L_S_MMR6  = 1459,
1475
    FLOOR_W_D32 = 1460,
1476
    FLOOR_W_D64 = 1461,
1477
    FLOOR_W_D_MMR6  = 1462,
1478
    FLOOR_W_MM  = 1463,
1479
    FLOOR_W_S = 1464,
1480
    FLOOR_W_S_MM  = 1465,
1481
    FLOOR_W_S_MMR6  = 1466,
1482
    FMADD_D = 1467,
1483
    FMADD_W = 1468,
1484
    FMAX_A_D  = 1469,
1485
    FMAX_A_W  = 1470,
1486
    FMAX_D  = 1471,
1487
    FMAX_W  = 1472,
1488
    FMIN_A_D  = 1473,
1489
    FMIN_A_W  = 1474,
1490
    FMIN_D  = 1475,
1491
    FMIN_W  = 1476,
1492
    FMOV_D32  = 1477,
1493
    FMOV_D32_MM = 1478,
1494
    FMOV_D64  = 1479,
1495
    FMOV_D64_MM = 1480,
1496
    FMOV_S  = 1481,
1497
    FMOV_S_MM = 1482,
1498
    FMOV_S_MMR6 = 1483,
1499
    FMSUB_D = 1484,
1500
    FMSUB_W = 1485,
1501
    FMUL_D  = 1486,
1502
    FMUL_D32  = 1487,
1503
    FMUL_D32_MM = 1488,
1504
    FMUL_D64  = 1489,
1505
    FMUL_D64_MM = 1490,
1506
    FMUL_S  = 1491,
1507
    FMUL_S_MM = 1492,
1508
    FMUL_S_MMR6 = 1493,
1509
    FMUL_W  = 1494,
1510
    FNEG_D32  = 1495,
1511
    FNEG_D32_MM = 1496,
1512
    FNEG_D64  = 1497,
1513
    FNEG_D64_MM = 1498,
1514
    FNEG_S  = 1499,
1515
    FNEG_S_MM = 1500,
1516
    FNEG_S_MMR6 = 1501,
1517
    FORK  = 1502,
1518
    FRCP_D  = 1503,
1519
    FRCP_W  = 1504,
1520
    FRINT_D = 1505,
1521
    FRINT_W = 1506,
1522
    FRSQRT_D  = 1507,
1523
    FRSQRT_W  = 1508,
1524
    FSAF_D  = 1509,
1525
    FSAF_W  = 1510,
1526
    FSEQ_D  = 1511,
1527
    FSEQ_W  = 1512,
1528
    FSLE_D  = 1513,
1529
    FSLE_W  = 1514,
1530
    FSLT_D  = 1515,
1531
    FSLT_W  = 1516,
1532
    FSNE_D  = 1517,
1533
    FSNE_W  = 1518,
1534
    FSOR_D  = 1519,
1535
    FSOR_W  = 1520,
1536
    FSQRT_D = 1521,
1537
    FSQRT_D32 = 1522,
1538
    FSQRT_D32_MM  = 1523,
1539
    FSQRT_D64 = 1524,
1540
    FSQRT_D64_MM  = 1525,
1541
    FSQRT_S = 1526,
1542
    FSQRT_S_MM  = 1527,
1543
    FSQRT_W = 1528,
1544
    FSUB_D  = 1529,
1545
    FSUB_D32  = 1530,
1546
    FSUB_D32_MM = 1531,
1547
    FSUB_D64  = 1532,
1548
    FSUB_D64_MM = 1533,
1549
    FSUB_S  = 1534,
1550
    FSUB_S_MM = 1535,
1551
    FSUB_S_MMR6 = 1536,
1552
    FSUB_W  = 1537,
1553
    FSUEQ_D = 1538,
1554
    FSUEQ_W = 1539,
1555
    FSULE_D = 1540,
1556
    FSULE_W = 1541,
1557
    FSULT_D = 1542,
1558
    FSULT_W = 1543,
1559
    FSUNE_D = 1544,
1560
    FSUNE_W = 1545,
1561
    FSUN_D  = 1546,
1562
    FSUN_W  = 1547,
1563
    FTINT_S_D = 1548,
1564
    FTINT_S_W = 1549,
1565
    FTINT_U_D = 1550,
1566
    FTINT_U_W = 1551,
1567
    FTQ_H = 1552,
1568
    FTQ_W = 1553,
1569
    FTRUNC_S_D  = 1554,
1570
    FTRUNC_S_W  = 1555,
1571
    FTRUNC_U_D  = 1556,
1572
    FTRUNC_U_W  = 1557,
1573
    GINVI = 1558,
1574
    GINVI_MMR6  = 1559,
1575
    GINVT = 1560,
1576
    GINVT_MMR6  = 1561,
1577
    HADD_S_D  = 1562,
1578
    HADD_S_H  = 1563,
1579
    HADD_S_W  = 1564,
1580
    HADD_U_D  = 1565,
1581
    HADD_U_H  = 1566,
1582
    HADD_U_W  = 1567,
1583
    HSUB_S_D  = 1568,
1584
    HSUB_S_H  = 1569,
1585
    HSUB_S_W  = 1570,
1586
    HSUB_U_D  = 1571,
1587
    HSUB_U_H  = 1572,
1588
    HSUB_U_W  = 1573,
1589
    HYPCALL = 1574,
1590
    HYPCALL_MM  = 1575,
1591
    ILVEV_B = 1576,
1592
    ILVEV_D = 1577,
1593
    ILVEV_H = 1578,
1594
    ILVEV_W = 1579,
1595
    ILVL_B  = 1580,
1596
    ILVL_D  = 1581,
1597
    ILVL_H  = 1582,
1598
    ILVL_W  = 1583,
1599
    ILVOD_B = 1584,
1600
    ILVOD_D = 1585,
1601
    ILVOD_H = 1586,
1602
    ILVOD_W = 1587,
1603
    ILVR_B  = 1588,
1604
    ILVR_D  = 1589,
1605
    ILVR_H  = 1590,
1606
    ILVR_W  = 1591,
1607
    INS = 1592,
1608
    INSERT_B  = 1593,
1609
    INSERT_D  = 1594,
1610
    INSERT_H  = 1595,
1611
    INSERT_W  = 1596,
1612
    INSV  = 1597,
1613
    INSVE_B = 1598,
1614
    INSVE_D = 1599,
1615
    INSVE_H = 1600,
1616
    INSVE_W = 1601,
1617
    INSV_MM = 1602,
1618
    INS_MM  = 1603,
1619
    INS_MMR6  = 1604,
1620
    J = 1605,
1621
    JAL = 1606,
1622
    JALR  = 1607,
1623
    JALR16_MM = 1608,
1624
    JALR64  = 1609,
1625
    JALRC16_MMR6  = 1610,
1626
    JALRC_HB_MMR6 = 1611,
1627
    JALRC_MMR6  = 1612,
1628
    JALRS16_MM  = 1613,
1629
    JALRS_MM  = 1614,
1630
    JALR_HB = 1615,
1631
    JALR_HB64 = 1616,
1632
    JALR_MM = 1617,
1633
    JALS_MM = 1618,
1634
    JALX  = 1619,
1635
    JALX_MM = 1620,
1636
    JAL_MM  = 1621,
1637
    JIALC = 1622,
1638
    JIALC64 = 1623,
1639
    JIALC_MMR6  = 1624,
1640
    JIC = 1625,
1641
    JIC64 = 1626,
1642
    JIC_MMR6  = 1627,
1643
    JR  = 1628,
1644
    JR16_MM = 1629,
1645
    JR64  = 1630,
1646
    JRADDIUSP = 1631,
1647
    JRC16_MM  = 1632,
1648
    JRC16_MMR6  = 1633,
1649
    JRCADDIUSP_MMR6 = 1634,
1650
    JR_HB = 1635,
1651
    JR_HB64 = 1636,
1652
    JR_HB64_R6  = 1637,
1653
    JR_HB_R6  = 1638,
1654
    JR_MM = 1639,
1655
    J_MM  = 1640,
1656
    Jal16 = 1641,
1657
    JalB16  = 1642,
1658
    JrRa16  = 1643,
1659
    JrcRa16 = 1644,
1660
    JrcRx16 = 1645,
1661
    JumpLinkReg16 = 1646,
1662
    LB  = 1647,
1663
    LB64  = 1648,
1664
    LBE = 1649,
1665
    LBE_MM  = 1650,
1666
    LBU16_MM  = 1651,
1667
    LBUX  = 1652,
1668
    LBUX_MM = 1653,
1669
    LBU_MMR6  = 1654,
1670
    LB_MM = 1655,
1671
    LB_MMR6 = 1656,
1672
    LBu = 1657,
1673
    LBu64 = 1658,
1674
    LBuE  = 1659,
1675
    LBuE_MM = 1660,
1676
    LBu_MM  = 1661,
1677
    LD  = 1662,
1678
    LDC1  = 1663,
1679
    LDC164  = 1664,
1680
    LDC1_D64_MMR6 = 1665,
1681
    LDC1_MM = 1666,
1682
    LDC2  = 1667,
1683
    LDC2_MMR6 = 1668,
1684
    LDC2_R6 = 1669,
1685
    LDC3  = 1670,
1686
    LDI_B = 1671,
1687
    LDI_D = 1672,
1688
    LDI_H = 1673,
1689
    LDI_W = 1674,
1690
    LDL = 1675,
1691
    LDPC  = 1676,
1692
    LDR = 1677,
1693
    LDXC1 = 1678,
1694
    LDXC164 = 1679,
1695
    LD_B  = 1680,
1696
    LD_D  = 1681,
1697
    LD_H  = 1682,
1698
    LD_W  = 1683,
1699
    LEA_ADDiu = 1684,
1700
    LEA_ADDiu64 = 1685,
1701
    LEA_ADDiu_MM  = 1686,
1702
    LH  = 1687,
1703
    LH64  = 1688,
1704
    LHE = 1689,
1705
    LHE_MM  = 1690,
1706
    LHU16_MM  = 1691,
1707
    LHX = 1692,
1708
    LHX_MM  = 1693,
1709
    LH_MM = 1694,
1710
    LHu = 1695,
1711
    LHu64 = 1696,
1712
    LHuE  = 1697,
1713
    LHuE_MM = 1698,
1714
    LHu_MM  = 1699,
1715
    LI16_MM = 1700,
1716
    LI16_MMR6 = 1701,
1717
    LL  = 1702,
1718
    LL64  = 1703,
1719
    LL64_R6 = 1704,
1720
    LLD = 1705,
1721
    LLD_R6  = 1706,
1722
    LLE = 1707,
1723
    LLE_MM  = 1708,
1724
    LL_MM = 1709,
1725
    LL_MMR6 = 1710,
1726
    LL_R6 = 1711,
1727
    LSA = 1712,
1728
    LSA_MMR6  = 1713,
1729
    LSA_R6  = 1714,
1730
    LUI_MMR6  = 1715,
1731
    LUXC1 = 1716,
1732
    LUXC164 = 1717,
1733
    LUXC1_MM  = 1718,
1734
    LUi = 1719,
1735
    LUi64 = 1720,
1736
    LUi_MM  = 1721,
1737
    LW  = 1722,
1738
    LW16_MM = 1723,
1739
    LW64  = 1724,
1740
    LWC1  = 1725,
1741
    LWC1_MM = 1726,
1742
    LWC2  = 1727,
1743
    LWC2_MMR6 = 1728,
1744
    LWC2_R6 = 1729,
1745
    LWC3  = 1730,
1746
    LWDSP = 1731,
1747
    LWDSP_MM  = 1732,
1748
    LWE = 1733,
1749
    LWE_MM  = 1734,
1750
    LWGP_MM = 1735,
1751
    LWL = 1736,
1752
    LWL64 = 1737,
1753
    LWLE  = 1738,
1754
    LWLE_MM = 1739,
1755
    LWL_MM  = 1740,
1756
    LWM16_MM  = 1741,
1757
    LWM16_MMR6  = 1742,
1758
    LWM32_MM  = 1743,
1759
    LWPC  = 1744,
1760
    LWPC_MMR6 = 1745,
1761
    LWP_MM  = 1746,
1762
    LWR = 1747,
1763
    LWR64 = 1748,
1764
    LWRE  = 1749,
1765
    LWRE_MM = 1750,
1766
    LWR_MM  = 1751,
1767
    LWSP_MM = 1752,
1768
    LWUPC = 1753,
1769
    LWU_MM  = 1754,
1770
    LWX = 1755,
1771
    LWXC1 = 1756,
1772
    LWXC1_MM  = 1757,
1773
    LWXS_MM = 1758,
1774
    LWX_MM  = 1759,
1775
    LW_MM = 1760,
1776
    LW_MMR6 = 1761,
1777
    LWu = 1762,
1778
    LbRxRyOffMemX16 = 1763,
1779
    LbuRxRyOffMemX16  = 1764,
1780
    LhRxRyOffMemX16 = 1765,
1781
    LhuRxRyOffMemX16  = 1766,
1782
    LiRxImm16 = 1767,
1783
    LiRxImmAlignX16 = 1768,
1784
    LiRxImmX16  = 1769,
1785
    LwRxPcTcp16 = 1770,
1786
    LwRxPcTcpX16  = 1771,
1787
    LwRxRyOffMemX16 = 1772,
1788
    LwRxSpImmX16  = 1773,
1789
    MADD  = 1774,
1790
    MADDF_D = 1775,
1791
    MADDF_D_MMR6  = 1776,
1792
    MADDF_S = 1777,
1793
    MADDF_S_MMR6  = 1778,
1794
    MADDR_Q_H = 1779,
1795
    MADDR_Q_W = 1780,
1796
    MADDU = 1781,
1797
    MADDU_DSP = 1782,
1798
    MADDU_DSP_MM  = 1783,
1799
    MADDU_MM  = 1784,
1800
    MADDV_B = 1785,
1801
    MADDV_D = 1786,
1802
    MADDV_H = 1787,
1803
    MADDV_W = 1788,
1804
    MADD_D32  = 1789,
1805
    MADD_D32_MM = 1790,
1806
    MADD_D64  = 1791,
1807
    MADD_DSP  = 1792,
1808
    MADD_DSP_MM = 1793,
1809
    MADD_MM = 1794,
1810
    MADD_Q_H  = 1795,
1811
    MADD_Q_W  = 1796,
1812
    MADD_S  = 1797,
1813
    MADD_S_MM = 1798,
1814
    MAQ_SA_W_PHL  = 1799,
1815
    MAQ_SA_W_PHL_MM = 1800,
1816
    MAQ_SA_W_PHR  = 1801,
1817
    MAQ_SA_W_PHR_MM = 1802,
1818
    MAQ_S_W_PHL = 1803,
1819
    MAQ_S_W_PHL_MM  = 1804,
1820
    MAQ_S_W_PHR = 1805,
1821
    MAQ_S_W_PHR_MM  = 1806,
1822
    MAXA_D  = 1807,
1823
    MAXA_D_MMR6 = 1808,
1824
    MAXA_S  = 1809,
1825
    MAXA_S_MMR6 = 1810,
1826
    MAXI_S_B  = 1811,
1827
    MAXI_S_D  = 1812,
1828
    MAXI_S_H  = 1813,
1829
    MAXI_S_W  = 1814,
1830
    MAXI_U_B  = 1815,
1831
    MAXI_U_D  = 1816,
1832
    MAXI_U_H  = 1817,
1833
    MAXI_U_W  = 1818,
1834
    MAX_A_B = 1819,
1835
    MAX_A_D = 1820,
1836
    MAX_A_H = 1821,
1837
    MAX_A_W = 1822,
1838
    MAX_D = 1823,
1839
    MAX_D_MMR6  = 1824,
1840
    MAX_S = 1825,
1841
    MAX_S_B = 1826,
1842
    MAX_S_D = 1827,
1843
    MAX_S_H = 1828,
1844
    MAX_S_MMR6  = 1829,
1845
    MAX_S_W = 1830,
1846
    MAX_U_B = 1831,
1847
    MAX_U_D = 1832,
1848
    MAX_U_H = 1833,
1849
    MAX_U_W = 1834,
1850
    MFC0  = 1835,
1851
    MFC0_MMR6 = 1836,
1852
    MFC1  = 1837,
1853
    MFC1_D64  = 1838,
1854
    MFC1_MM = 1839,
1855
    MFC1_MMR6 = 1840,
1856
    MFC2  = 1841,
1857
    MFC2_MMR6 = 1842,
1858
    MFGC0 = 1843,
1859
    MFGC0_MM  = 1844,
1860
    MFHC0_MMR6  = 1845,
1861
    MFHC1_D32 = 1846,
1862
    MFHC1_D32_MM  = 1847,
1863
    MFHC1_D64 = 1848,
1864
    MFHC1_D64_MM  = 1849,
1865
    MFHC2_MMR6  = 1850,
1866
    MFHGC0  = 1851,
1867
    MFHGC0_MM = 1852,
1868
    MFHI  = 1853,
1869
    MFHI16_MM = 1854,
1870
    MFHI64  = 1855,
1871
    MFHI_DSP  = 1856,
1872
    MFHI_DSP_MM = 1857,
1873
    MFHI_MM = 1858,
1874
    MFLO  = 1859,
1875
    MFLO16_MM = 1860,
1876
    MFLO64  = 1861,
1877
    MFLO_DSP  = 1862,
1878
    MFLO_DSP_MM = 1863,
1879
    MFLO_MM = 1864,
1880
    MFTR  = 1865,
1881
    MINA_D  = 1866,
1882
    MINA_D_MMR6 = 1867,
1883
    MINA_S  = 1868,
1884
    MINA_S_MMR6 = 1869,
1885
    MINI_S_B  = 1870,
1886
    MINI_S_D  = 1871,
1887
    MINI_S_H  = 1872,
1888
    MINI_S_W  = 1873,
1889
    MINI_U_B  = 1874,
1890
    MINI_U_D  = 1875,
1891
    MINI_U_H  = 1876,
1892
    MINI_U_W  = 1877,
1893
    MIN_A_B = 1878,
1894
    MIN_A_D = 1879,
1895
    MIN_A_H = 1880,
1896
    MIN_A_W = 1881,
1897
    MIN_D = 1882,
1898
    MIN_D_MMR6  = 1883,
1899
    MIN_S = 1884,
1900
    MIN_S_B = 1885,
1901
    MIN_S_D = 1886,
1902
    MIN_S_H = 1887,
1903
    MIN_S_MMR6  = 1888,
1904
    MIN_S_W = 1889,
1905
    MIN_U_B = 1890,
1906
    MIN_U_D = 1891,
1907
    MIN_U_H = 1892,
1908
    MIN_U_W = 1893,
1909
    MOD = 1894,
1910
    MODSUB  = 1895,
1911
    MODSUB_MM = 1896,
1912
    MODU  = 1897,
1913
    MODU_MMR6 = 1898,
1914
    MOD_MMR6  = 1899,
1915
    MOD_S_B = 1900,
1916
    MOD_S_D = 1901,
1917
    MOD_S_H = 1902,
1918
    MOD_S_W = 1903,
1919
    MOD_U_B = 1904,
1920
    MOD_U_D = 1905,
1921
    MOD_U_H = 1906,
1922
    MOD_U_W = 1907,
1923
    MOVE16_MM = 1908,
1924
    MOVE16_MMR6 = 1909,
1925
    MOVEP_MM  = 1910,
1926
    MOVEP_MMR6  = 1911,
1927
    MOVE_V  = 1912,
1928
    MOVF_D32  = 1913,
1929
    MOVF_D32_MM = 1914,
1930
    MOVF_D64  = 1915,
1931
    MOVF_I  = 1916,
1932
    MOVF_I64  = 1917,
1933
    MOVF_I_MM = 1918,
1934
    MOVF_S  = 1919,
1935
    MOVF_S_MM = 1920,
1936
    MOVN_I64_D64  = 1921,
1937
    MOVN_I64_I  = 1922,
1938
    MOVN_I64_I64  = 1923,
1939
    MOVN_I64_S  = 1924,
1940
    MOVN_I_D32  = 1925,
1941
    MOVN_I_D32_MM = 1926,
1942
    MOVN_I_D64  = 1927,
1943
    MOVN_I_I  = 1928,
1944
    MOVN_I_I64  = 1929,
1945
    MOVN_I_MM = 1930,
1946
    MOVN_I_S  = 1931,
1947
    MOVN_I_S_MM = 1932,
1948
    MOVT_D32  = 1933,
1949
    MOVT_D32_MM = 1934,
1950
    MOVT_D64  = 1935,
1951
    MOVT_I  = 1936,
1952
    MOVT_I64  = 1937,
1953
    MOVT_I_MM = 1938,
1954
    MOVT_S  = 1939,
1955
    MOVT_S_MM = 1940,
1956
    MOVZ_I64_D64  = 1941,
1957
    MOVZ_I64_I  = 1942,
1958
    MOVZ_I64_I64  = 1943,
1959
    MOVZ_I64_S  = 1944,
1960
    MOVZ_I_D32  = 1945,
1961
    MOVZ_I_D32_MM = 1946,
1962
    MOVZ_I_D64  = 1947,
1963
    MOVZ_I_I  = 1948,
1964
    MOVZ_I_I64  = 1949,
1965
    MOVZ_I_MM = 1950,
1966
    MOVZ_I_S  = 1951,
1967
    MOVZ_I_S_MM = 1952,
1968
    MSUB  = 1953,
1969
    MSUBF_D = 1954,
1970
    MSUBF_D_MMR6  = 1955,
1971
    MSUBF_S = 1956,
1972
    MSUBF_S_MMR6  = 1957,
1973
    MSUBR_Q_H = 1958,
1974
    MSUBR_Q_W = 1959,
1975
    MSUBU = 1960,
1976
    MSUBU_DSP = 1961,
1977
    MSUBU_DSP_MM  = 1962,
1978
    MSUBU_MM  = 1963,
1979
    MSUBV_B = 1964,
1980
    MSUBV_D = 1965,
1981
    MSUBV_H = 1966,
1982
    MSUBV_W = 1967,
1983
    MSUB_D32  = 1968,
1984
    MSUB_D32_MM = 1969,
1985
    MSUB_D64  = 1970,
1986
    MSUB_DSP  = 1971,
1987
    MSUB_DSP_MM = 1972,
1988
    MSUB_MM = 1973,
1989
    MSUB_Q_H  = 1974,
1990
    MSUB_Q_W  = 1975,
1991
    MSUB_S  = 1976,
1992
    MSUB_S_MM = 1977,
1993
    MTC0  = 1978,
1994
    MTC0_MMR6 = 1979,
1995
    MTC1  = 1980,
1996
    MTC1_D64  = 1981,
1997
    MTC1_D64_MM = 1982,
1998
    MTC1_MM = 1983,
1999
    MTC1_MMR6 = 1984,
2000
    MTC2  = 1985,
2001
    MTC2_MMR6 = 1986,
2002
    MTGC0 = 1987,
2003
    MTGC0_MM  = 1988,
2004
    MTHC0_MMR6  = 1989,
2005
    MTHC1_D32 = 1990,
2006
    MTHC1_D32_MM  = 1991,
2007
    MTHC1_D64 = 1992,
2008
    MTHC1_D64_MM  = 1993,
2009
    MTHC2_MMR6  = 1994,
2010
    MTHGC0  = 1995,
2011
    MTHGC0_MM = 1996,
2012
    MTHI  = 1997,
2013
    MTHI64  = 1998,
2014
    MTHI_DSP  = 1999,
2015
    MTHI_DSP_MM = 2000,
2016
    MTHI_MM = 2001,
2017
    MTHLIP  = 2002,
2018
    MTHLIP_MM = 2003,
2019
    MTLO  = 2004,
2020
    MTLO64  = 2005,
2021
    MTLO_DSP  = 2006,
2022
    MTLO_DSP_MM = 2007,
2023
    MTLO_MM = 2008,
2024
    MTM0  = 2009,
2025
    MTM1  = 2010,
2026
    MTM2  = 2011,
2027
    MTP0  = 2012,
2028
    MTP1  = 2013,
2029
    MTP2  = 2014,
2030
    MTTR  = 2015,
2031
    MUH = 2016,
2032
    MUHU  = 2017,
2033
    MUHU_MMR6 = 2018,
2034
    MUH_MMR6  = 2019,
2035
    MUL = 2020,
2036
    MULEQ_S_W_PHL = 2021,
2037
    MULEQ_S_W_PHL_MM  = 2022,
2038
    MULEQ_S_W_PHR = 2023,
2039
    MULEQ_S_W_PHR_MM  = 2024,
2040
    MULEU_S_PH_QBL  = 2025,
2041
    MULEU_S_PH_QBL_MM = 2026,
2042
    MULEU_S_PH_QBR  = 2027,
2043
    MULEU_S_PH_QBR_MM = 2028,
2044
    MULQ_RS_PH  = 2029,
2045
    MULQ_RS_PH_MM = 2030,
2046
    MULQ_RS_W = 2031,
2047
    MULQ_RS_W_MMR2  = 2032,
2048
    MULQ_S_PH = 2033,
2049
    MULQ_S_PH_MMR2  = 2034,
2050
    MULQ_S_W  = 2035,
2051
    MULQ_S_W_MMR2 = 2036,
2052
    MULR_Q_H  = 2037,
2053
    MULR_Q_W  = 2038,
2054
    MULSAQ_S_W_PH = 2039,
2055
    MULSAQ_S_W_PH_MM  = 2040,
2056
    MULSA_W_PH  = 2041,
2057
    MULSA_W_PH_MMR2 = 2042,
2058
    MULT  = 2043,
2059
    MULTU_DSP = 2044,
2060
    MULTU_DSP_MM  = 2045,
2061
    MULT_DSP  = 2046,
2062
    MULT_DSP_MM = 2047,
2063
    MULT_MM = 2048,
2064
    MULTu = 2049,
2065
    MULTu_MM  = 2050,
2066
    MULU  = 2051,
2067
    MULU_MMR6 = 2052,
2068
    MULV_B  = 2053,
2069
    MULV_D  = 2054,
2070
    MULV_H  = 2055,
2071
    MULV_W  = 2056,
2072
    MUL_MM  = 2057,
2073
    MUL_MMR6  = 2058,
2074
    MUL_PH  = 2059,
2075
    MUL_PH_MMR2 = 2060,
2076
    MUL_Q_H = 2061,
2077
    MUL_Q_W = 2062,
2078
    MUL_R6  = 2063,
2079
    MUL_S_PH  = 2064,
2080
    MUL_S_PH_MMR2 = 2065,
2081
    Mfhi16  = 2066,
2082
    Mflo16  = 2067,
2083
    Move32R16 = 2068,
2084
    MoveR3216 = 2069,
2085
    NLOC_B  = 2070,
2086
    NLOC_D  = 2071,
2087
    NLOC_H  = 2072,
2088
    NLOC_W  = 2073,
2089
    NLZC_B  = 2074,
2090
    NLZC_D  = 2075,
2091
    NLZC_H  = 2076,
2092
    NLZC_W  = 2077,
2093
    NMADD_D32 = 2078,
2094
    NMADD_D32_MM  = 2079,
2095
    NMADD_D64 = 2080,
2096
    NMADD_S = 2081,
2097
    NMADD_S_MM  = 2082,
2098
    NMSUB_D32 = 2083,
2099
    NMSUB_D32_MM  = 2084,
2100
    NMSUB_D64 = 2085,
2101
    NMSUB_S = 2086,
2102
    NMSUB_S_MM  = 2087,
2103
    NOR = 2088,
2104
    NOR64 = 2089,
2105
    NORI_B  = 2090,
2106
    NOR_MM  = 2091,
2107
    NOR_MMR6  = 2092,
2108
    NOR_V = 2093,
2109
    NOT16_MM  = 2094,
2110
    NOT16_MMR6  = 2095,
2111
    NegRxRy16 = 2096,
2112
    NotRxRy16 = 2097,
2113
    OR  = 2098,
2114
    OR16_MM = 2099,
2115
    OR16_MMR6 = 2100,
2116
    OR64  = 2101,
2117
    ORI_B = 2102,
2118
    ORI_MMR6  = 2103,
2119
    OR_MM = 2104,
2120
    OR_MMR6 = 2105,
2121
    OR_V  = 2106,
2122
    ORi = 2107,
2123
    ORi64 = 2108,
2124
    ORi_MM  = 2109,
2125
    OrRxRxRy16  = 2110,
2126
    PACKRL_PH = 2111,
2127
    PACKRL_PH_MM  = 2112,
2128
    PAUSE = 2113,
2129
    PAUSE_MM  = 2114,
2130
    PAUSE_MMR6  = 2115,
2131
    PCKEV_B = 2116,
2132
    PCKEV_D = 2117,
2133
    PCKEV_H = 2118,
2134
    PCKEV_W = 2119,
2135
    PCKOD_B = 2120,
2136
    PCKOD_D = 2121,
2137
    PCKOD_H = 2122,
2138
    PCKOD_W = 2123,
2139
    PCNT_B  = 2124,
2140
    PCNT_D  = 2125,
2141
    PCNT_H  = 2126,
2142
    PCNT_W  = 2127,
2143
    PICK_PH = 2128,
2144
    PICK_PH_MM  = 2129,
2145
    PICK_QB = 2130,
2146
    PICK_QB_MM  = 2131,
2147
    PLL_PS64  = 2132,
2148
    PLU_PS64  = 2133,
2149
    POP = 2134,
2150
    PRECEQU_PH_QBL  = 2135,
2151
    PRECEQU_PH_QBLA = 2136,
2152
    PRECEQU_PH_QBLA_MM  = 2137,
2153
    PRECEQU_PH_QBL_MM = 2138,
2154
    PRECEQU_PH_QBR  = 2139,
2155
    PRECEQU_PH_QBRA = 2140,
2156
    PRECEQU_PH_QBRA_MM  = 2141,
2157
    PRECEQU_PH_QBR_MM = 2142,
2158
    PRECEQ_W_PHL  = 2143,
2159
    PRECEQ_W_PHL_MM = 2144,
2160
    PRECEQ_W_PHR  = 2145,
2161
    PRECEQ_W_PHR_MM = 2146,
2162
    PRECEU_PH_QBL = 2147,
2163
    PRECEU_PH_QBLA  = 2148,
2164
    PRECEU_PH_QBLA_MM = 2149,
2165
    PRECEU_PH_QBL_MM  = 2150,
2166
    PRECEU_PH_QBR = 2151,
2167
    PRECEU_PH_QBRA  = 2152,
2168
    PRECEU_PH_QBRA_MM = 2153,
2169
    PRECEU_PH_QBR_MM  = 2154,
2170
    PRECRQU_S_QB_PH = 2155,
2171
    PRECRQU_S_QB_PH_MM  = 2156,
2172
    PRECRQ_PH_W = 2157,
2173
    PRECRQ_PH_W_MM  = 2158,
2174
    PRECRQ_QB_PH  = 2159,
2175
    PRECRQ_QB_PH_MM = 2160,
2176
    PRECRQ_RS_PH_W  = 2161,
2177
    PRECRQ_RS_PH_W_MM = 2162,
2178
    PRECR_QB_PH = 2163,
2179
    PRECR_QB_PH_MMR2  = 2164,
2180
    PRECR_SRA_PH_W  = 2165,
2181
    PRECR_SRA_PH_W_MMR2 = 2166,
2182
    PRECR_SRA_R_PH_W  = 2167,
2183
    PRECR_SRA_R_PH_W_MMR2 = 2168,
2184
    PREF  = 2169,
2185
    PREFE = 2170,
2186
    PREFE_MM  = 2171,
2187
    PREFX_MM  = 2172,
2188
    PREF_MM = 2173,
2189
    PREF_MMR6 = 2174,
2190
    PREF_R6 = 2175,
2191
    PREPEND = 2176,
2192
    PREPEND_MMR2  = 2177,
2193
    RADDU_W_QB  = 2178,
2194
    RADDU_W_QB_MM = 2179,
2195
    RDDSP = 2180,
2196
    RDDSP_MM  = 2181,
2197
    RDHWR = 2182,
2198
    RDHWR64 = 2183,
2199
    RDHWR_MM  = 2184,
2200
    RDHWR_MMR6  = 2185,
2201
    RDPGPR_MMR6 = 2186,
2202
    RECIP_D32 = 2187,
2203
    RECIP_D32_MM  = 2188,
2204
    RECIP_D64 = 2189,
2205
    RECIP_D64_MM  = 2190,
2206
    RECIP_S = 2191,
2207
    RECIP_S_MM  = 2192,
2208
    REPLV_PH  = 2193,
2209
    REPLV_PH_MM = 2194,
2210
    REPLV_QB  = 2195,
2211
    REPLV_QB_MM = 2196,
2212
    REPL_PH = 2197,
2213
    REPL_PH_MM  = 2198,
2214
    REPL_QB = 2199,
2215
    REPL_QB_MM  = 2200,
2216
    RINT_D  = 2201,
2217
    RINT_D_MMR6 = 2202,
2218
    RINT_S  = 2203,
2219
    RINT_S_MMR6 = 2204,
2220
    ROTR  = 2205,
2221
    ROTRV = 2206,
2222
    ROTRV_MM  = 2207,
2223
    ROTR_MM = 2208,
2224
    ROUND_L_D64 = 2209,
2225
    ROUND_L_D_MMR6  = 2210,
2226
    ROUND_L_S = 2211,
2227
    ROUND_L_S_MMR6  = 2212,
2228
    ROUND_W_D32 = 2213,
2229
    ROUND_W_D64 = 2214,
2230
    ROUND_W_D_MMR6  = 2215,
2231
    ROUND_W_MM  = 2216,
2232
    ROUND_W_S = 2217,
2233
    ROUND_W_S_MM  = 2218,
2234
    ROUND_W_S_MMR6  = 2219,
2235
    RSQRT_D32 = 2220,
2236
    RSQRT_D32_MM  = 2221,
2237
    RSQRT_D64 = 2222,
2238
    RSQRT_D64_MM  = 2223,
2239
    RSQRT_S = 2224,
2240
    RSQRT_S_MM  = 2225,
2241
    Restore16 = 2226,
2242
    RestoreX16  = 2227,
2243
    SAT_S_B = 2228,
2244
    SAT_S_D = 2229,
2245
    SAT_S_H = 2230,
2246
    SAT_S_W = 2231,
2247
    SAT_U_B = 2232,
2248
    SAT_U_D = 2233,
2249
    SAT_U_H = 2234,
2250
    SAT_U_W = 2235,
2251
    SB  = 2236,
2252
    SB16_MM = 2237,
2253
    SB16_MMR6 = 2238,
2254
    SB64  = 2239,
2255
    SBE = 2240,
2256
    SBE_MM  = 2241,
2257
    SB_MM = 2242,
2258
    SB_MMR6 = 2243,
2259
    SC  = 2244,
2260
    SC64  = 2245,
2261
    SC64_R6 = 2246,
2262
    SCD = 2247,
2263
    SCD_R6  = 2248,
2264
    SCE = 2249,
2265
    SCE_MM  = 2250,
2266
    SC_MM = 2251,
2267
    SC_MMR6 = 2252,
2268
    SC_R6 = 2253,
2269
    SD  = 2254,
2270
    SDBBP = 2255,
2271
    SDBBP16_MM  = 2256,
2272
    SDBBP16_MMR6  = 2257,
2273
    SDBBP_MM  = 2258,
2274
    SDBBP_MMR6  = 2259,
2275
    SDBBP_R6  = 2260,
2276
    SDC1  = 2261,
2277
    SDC164  = 2262,
2278
    SDC1_D64_MMR6 = 2263,
2279
    SDC1_MM = 2264,
2280
    SDC2  = 2265,
2281
    SDC2_MMR6 = 2266,
2282
    SDC2_R6 = 2267,
2283
    SDC3  = 2268,
2284
    SDIV  = 2269,
2285
    SDIV_MM = 2270,
2286
    SDL = 2271,
2287
    SDR = 2272,
2288
    SDXC1 = 2273,
2289
    SDXC164 = 2274,
2290
    SEB = 2275,
2291
    SEB64 = 2276,
2292
    SEB_MM  = 2277,
2293
    SEH = 2278,
2294
    SEH64 = 2279,
2295
    SEH_MM  = 2280,
2296
    SELEQZ  = 2281,
2297
    SELEQZ64  = 2282,
2298
    SELEQZ_D  = 2283,
2299
    SELEQZ_D_MMR6 = 2284,
2300
    SELEQZ_MMR6 = 2285,
2301
    SELEQZ_S  = 2286,
2302
    SELEQZ_S_MMR6 = 2287,
2303
    SELNEZ  = 2288,
2304
    SELNEZ64  = 2289,
2305
    SELNEZ_D  = 2290,
2306
    SELNEZ_D_MMR6 = 2291,
2307
    SELNEZ_MMR6 = 2292,
2308
    SELNEZ_S  = 2293,
2309
    SELNEZ_S_MMR6 = 2294,
2310
    SEL_D = 2295,
2311
    SEL_D_MMR6  = 2296,
2312
    SEL_S = 2297,
2313
    SEL_S_MMR6  = 2298,
2314
    SEQ = 2299,
2315
    SEQi  = 2300,
2316
    SH  = 2301,
2317
    SH16_MM = 2302,
2318
    SH16_MMR6 = 2303,
2319
    SH64  = 2304,
2320
    SHE = 2305,
2321
    SHE_MM  = 2306,
2322
    SHF_B = 2307,
2323
    SHF_H = 2308,
2324
    SHF_W = 2309,
2325
    SHILO = 2310,
2326
    SHILOV  = 2311,
2327
    SHILOV_MM = 2312,
2328
    SHILO_MM  = 2313,
2329
    SHLLV_PH  = 2314,
2330
    SHLLV_PH_MM = 2315,
2331
    SHLLV_QB  = 2316,
2332
    SHLLV_QB_MM = 2317,
2333
    SHLLV_S_PH  = 2318,
2334
    SHLLV_S_PH_MM = 2319,
2335
    SHLLV_S_W = 2320,
2336
    SHLLV_S_W_MM  = 2321,
2337
    SHLL_PH = 2322,
2338
    SHLL_PH_MM  = 2323,
2339
    SHLL_QB = 2324,
2340
    SHLL_QB_MM  = 2325,
2341
    SHLL_S_PH = 2326,
2342
    SHLL_S_PH_MM  = 2327,
2343
    SHLL_S_W  = 2328,
2344
    SHLL_S_W_MM = 2329,
2345
    SHRAV_PH  = 2330,
2346
    SHRAV_PH_MM = 2331,
2347
    SHRAV_QB  = 2332,
2348
    SHRAV_QB_MMR2 = 2333,
2349
    SHRAV_R_PH  = 2334,
2350
    SHRAV_R_PH_MM = 2335,
2351
    SHRAV_R_QB  = 2336,
2352
    SHRAV_R_QB_MMR2 = 2337,
2353
    SHRAV_R_W = 2338,
2354
    SHRAV_R_W_MM  = 2339,
2355
    SHRA_PH = 2340,
2356
    SHRA_PH_MM  = 2341,
2357
    SHRA_QB = 2342,
2358
    SHRA_QB_MMR2  = 2343,
2359
    SHRA_R_PH = 2344,
2360
    SHRA_R_PH_MM  = 2345,
2361
    SHRA_R_QB = 2346,
2362
    SHRA_R_QB_MMR2  = 2347,
2363
    SHRA_R_W  = 2348,
2364
    SHRA_R_W_MM = 2349,
2365
    SHRLV_PH  = 2350,
2366
    SHRLV_PH_MMR2 = 2351,
2367
    SHRLV_QB  = 2352,
2368
    SHRLV_QB_MM = 2353,
2369
    SHRL_PH = 2354,
2370
    SHRL_PH_MMR2  = 2355,
2371
    SHRL_QB = 2356,
2372
    SHRL_QB_MM  = 2357,
2373
    SH_MM = 2358,
2374
    SH_MMR6 = 2359,
2375
    SIGRIE  = 2360,
2376
    SIGRIE_MMR6 = 2361,
2377
    SLDI_B  = 2362,
2378
    SLDI_D  = 2363,
2379
    SLDI_H  = 2364,
2380
    SLDI_W  = 2365,
2381
    SLD_B = 2366,
2382
    SLD_D = 2367,
2383
    SLD_H = 2368,
2384
    SLD_W = 2369,
2385
    SLL = 2370,
2386
    SLL16_MM  = 2371,
2387
    SLL16_MMR6  = 2372,
2388
    SLL64_32  = 2373,
2389
    SLL64_64  = 2374,
2390
    SLLI_B  = 2375,
2391
    SLLI_D  = 2376,
2392
    SLLI_H  = 2377,
2393
    SLLI_W  = 2378,
2394
    SLLV  = 2379,
2395
    SLLV_MM = 2380,
2396
    SLL_B = 2381,
2397
    SLL_D = 2382,
2398
    SLL_H = 2383,
2399
    SLL_MM  = 2384,
2400
    SLL_MMR6  = 2385,
2401
    SLL_W = 2386,
2402
    SLT = 2387,
2403
    SLT64 = 2388,
2404
    SLT_MM  = 2389,
2405
    SLTi  = 2390,
2406
    SLTi64  = 2391,
2407
    SLTi_MM = 2392,
2408
    SLTiu = 2393,
2409
    SLTiu64 = 2394,
2410
    SLTiu_MM  = 2395,
2411
    SLTu  = 2396,
2412
    SLTu64  = 2397,
2413
    SLTu_MM = 2398,
2414
    SNE = 2399,
2415
    SNEi  = 2400,
2416
    SPLATI_B  = 2401,
2417
    SPLATI_D  = 2402,
2418
    SPLATI_H  = 2403,
2419
    SPLATI_W  = 2404,
2420
    SPLAT_B = 2405,
2421
    SPLAT_D = 2406,
2422
    SPLAT_H = 2407,
2423
    SPLAT_W = 2408,
2424
    SRA = 2409,
2425
    SRAI_B  = 2410,
2426
    SRAI_D  = 2411,
2427
    SRAI_H  = 2412,
2428
    SRAI_W  = 2413,
2429
    SRARI_B = 2414,
2430
    SRARI_D = 2415,
2431
    SRARI_H = 2416,
2432
    SRARI_W = 2417,
2433
    SRAR_B  = 2418,
2434
    SRAR_D  = 2419,
2435
    SRAR_H  = 2420,
2436
    SRAR_W  = 2421,
2437
    SRAV  = 2422,
2438
    SRAV_MM = 2423,
2439
    SRA_B = 2424,
2440
    SRA_D = 2425,
2441
    SRA_H = 2426,
2442
    SRA_MM  = 2427,
2443
    SRA_W = 2428,
2444
    SRL = 2429,
2445
    SRL16_MM  = 2430,
2446
    SRL16_MMR6  = 2431,
2447
    SRLI_B  = 2432,
2448
    SRLI_D  = 2433,
2449
    SRLI_H  = 2434,
2450
    SRLI_W  = 2435,
2451
    SRLRI_B = 2436,
2452
    SRLRI_D = 2437,
2453
    SRLRI_H = 2438,
2454
    SRLRI_W = 2439,
2455
    SRLR_B  = 2440,
2456
    SRLR_D  = 2441,
2457
    SRLR_H  = 2442,
2458
    SRLR_W  = 2443,
2459
    SRLV  = 2444,
2460
    SRLV_MM = 2445,
2461
    SRL_B = 2446,
2462
    SRL_D = 2447,
2463
    SRL_H = 2448,
2464
    SRL_MM  = 2449,
2465
    SRL_W = 2450,
2466
    SSNOP = 2451,
2467
    SSNOP_MM  = 2452,
2468
    SSNOP_MMR6  = 2453,
2469
    ST_B  = 2454,
2470
    ST_D  = 2455,
2471
    ST_H  = 2456,
2472
    ST_W  = 2457,
2473
    SUB = 2458,
2474
    SUBQH_PH  = 2459,
2475
    SUBQH_PH_MMR2 = 2460,
2476
    SUBQH_R_PH  = 2461,
2477
    SUBQH_R_PH_MMR2 = 2462,
2478
    SUBQH_R_W = 2463,
2479
    SUBQH_R_W_MMR2  = 2464,
2480
    SUBQH_W = 2465,
2481
    SUBQH_W_MMR2  = 2466,
2482
    SUBQ_PH = 2467,
2483
    SUBQ_PH_MM  = 2468,
2484
    SUBQ_S_PH = 2469,
2485
    SUBQ_S_PH_MM  = 2470,
2486
    SUBQ_S_W  = 2471,
2487
    SUBQ_S_W_MM = 2472,
2488
    SUBSUS_U_B  = 2473,
2489
    SUBSUS_U_D  = 2474,
2490
    SUBSUS_U_H  = 2475,
2491
    SUBSUS_U_W  = 2476,
2492
    SUBSUU_S_B  = 2477,
2493
    SUBSUU_S_D  = 2478,
2494
    SUBSUU_S_H  = 2479,
2495
    SUBSUU_S_W  = 2480,
2496
    SUBS_S_B  = 2481,
2497
    SUBS_S_D  = 2482,
2498
    SUBS_S_H  = 2483,
2499
    SUBS_S_W  = 2484,
2500
    SUBS_U_B  = 2485,
2501
    SUBS_U_D  = 2486,
2502
    SUBS_U_H  = 2487,
2503
    SUBS_U_W  = 2488,
2504
    SUBU16_MM = 2489,
2505
    SUBU16_MMR6 = 2490,
2506
    SUBUH_QB  = 2491,
2507
    SUBUH_QB_MMR2 = 2492,
2508
    SUBUH_R_QB  = 2493,
2509
    SUBUH_R_QB_MMR2 = 2494,
2510
    SUBU_MMR6 = 2495,
2511
    SUBU_PH = 2496,
2512
    SUBU_PH_MMR2  = 2497,
2513
    SUBU_QB = 2498,
2514
    SUBU_QB_MM  = 2499,
2515
    SUBU_S_PH = 2500,
2516
    SUBU_S_PH_MMR2  = 2501,
2517
    SUBU_S_QB = 2502,
2518
    SUBU_S_QB_MM  = 2503,
2519
    SUBVI_B = 2504,
2520
    SUBVI_D = 2505,
2521
    SUBVI_H = 2506,
2522
    SUBVI_W = 2507,
2523
    SUBV_B  = 2508,
2524
    SUBV_D  = 2509,
2525
    SUBV_H  = 2510,
2526
    SUBV_W  = 2511,
2527
    SUB_MM  = 2512,
2528
    SUB_MMR6  = 2513,
2529
    SUBu  = 2514,
2530
    SUBu_MM = 2515,
2531
    SUXC1 = 2516,
2532
    SUXC164 = 2517,
2533
    SUXC1_MM  = 2518,
2534
    SW  = 2519,
2535
    SW16_MM = 2520,
2536
    SW16_MMR6 = 2521,
2537
    SW64  = 2522,
2538
    SWC1  = 2523,
2539
    SWC1_MM = 2524,
2540
    SWC2  = 2525,
2541
    SWC2_MMR6 = 2526,
2542
    SWC2_R6 = 2527,
2543
    SWC3  = 2528,
2544
    SWDSP = 2529,
2545
    SWDSP_MM  = 2530,
2546
    SWE = 2531,
2547
    SWE_MM  = 2532,
2548
    SWL = 2533,
2549
    SWL64 = 2534,
2550
    SWLE  = 2535,
2551
    SWLE_MM = 2536,
2552
    SWL_MM  = 2537,
2553
    SWM16_MM  = 2538,
2554
    SWM16_MMR6  = 2539,
2555
    SWM32_MM  = 2540,
2556
    SWP_MM  = 2541,
2557
    SWR = 2542,
2558
    SWR64 = 2543,
2559
    SWRE  = 2544,
2560
    SWRE_MM = 2545,
2561
    SWR_MM  = 2546,
2562
    SWSP_MM = 2547,
2563
    SWSP_MMR6 = 2548,
2564
    SWXC1 = 2549,
2565
    SWXC1_MM  = 2550,
2566
    SW_MM = 2551,
2567
    SW_MMR6 = 2552,
2568
    SYNC  = 2553,
2569
    SYNCI = 2554,
2570
    SYNCI_MM  = 2555,
2571
    SYNCI_MMR6  = 2556,
2572
    SYNC_MM = 2557,
2573
    SYNC_MMR6 = 2558,
2574
    SYSCALL = 2559,
2575
    SYSCALL_MM  = 2560,
2576
    Save16  = 2561,
2577
    SaveX16 = 2562,
2578
    SbRxRyOffMemX16 = 2563,
2579
    SebRx16 = 2564,
2580
    SehRx16 = 2565,
2581
    ShRxRyOffMemX16 = 2566,
2582
    SllX16  = 2567,
2583
    SllvRxRy16  = 2568,
2584
    SltRxRy16 = 2569,
2585
    SltiRxImm16 = 2570,
2586
    SltiRxImmX16  = 2571,
2587
    SltiuRxImm16  = 2572,
2588
    SltiuRxImmX16 = 2573,
2589
    SltuRxRy16  = 2574,
2590
    SraX16  = 2575,
2591
    SravRxRy16  = 2576,
2592
    SrlX16  = 2577,
2593
    SrlvRxRy16  = 2578,
2594
    SubuRxRyRz16  = 2579,
2595
    SwRxRyOffMemX16 = 2580,
2596
    SwRxSpImmX16  = 2581,
2597
    TEQ = 2582,
2598
    TEQI  = 2583,
2599
    TEQI_MM = 2584,
2600
    TEQ_MM  = 2585,
2601
    TGE = 2586,
2602
    TGEI  = 2587,
2603
    TGEIU = 2588,
2604
    TGEIU_MM  = 2589,
2605
    TGEI_MM = 2590,
2606
    TGEU  = 2591,
2607
    TGEU_MM = 2592,
2608
    TGE_MM  = 2593,
2609
    TLBGINV = 2594,
2610
    TLBGINVF  = 2595,
2611
    TLBGINVF_MM = 2596,
2612
    TLBGINV_MM  = 2597,
2613
    TLBGP = 2598,
2614
    TLBGP_MM  = 2599,
2615
    TLBGR = 2600,
2616
    TLBGR_MM  = 2601,
2617
    TLBGWI  = 2602,
2618
    TLBGWI_MM = 2603,
2619
    TLBGWR  = 2604,
2620
    TLBGWR_MM = 2605,
2621
    TLBINV  = 2606,
2622
    TLBINVF = 2607,
2623
    TLBINVF_MMR6  = 2608,
2624
    TLBINV_MMR6 = 2609,
2625
    TLBP  = 2610,
2626
    TLBP_MM = 2611,
2627
    TLBR  = 2612,
2628
    TLBR_MM = 2613,
2629
    TLBWI = 2614,
2630
    TLBWI_MM  = 2615,
2631
    TLBWR = 2616,
2632
    TLBWR_MM  = 2617,
2633
    TLT = 2618,
2634
    TLTI  = 2619,
2635
    TLTIU_MM  = 2620,
2636
    TLTI_MM = 2621,
2637
    TLTU  = 2622,
2638
    TLTU_MM = 2623,
2639
    TLT_MM  = 2624,
2640
    TNE = 2625,
2641
    TNEI  = 2626,
2642
    TNEI_MM = 2627,
2643
    TNE_MM  = 2628,
2644
    TRUNC_L_D64 = 2629,
2645
    TRUNC_L_D_MMR6  = 2630,
2646
    TRUNC_L_S = 2631,
2647
    TRUNC_L_S_MMR6  = 2632,
2648
    TRUNC_W_D32 = 2633,
2649
    TRUNC_W_D64 = 2634,
2650
    TRUNC_W_D_MMR6  = 2635,
2651
    TRUNC_W_MM  = 2636,
2652
    TRUNC_W_S = 2637,
2653
    TRUNC_W_S_MM  = 2638,
2654
    TRUNC_W_S_MMR6  = 2639,
2655
    TTLTIU  = 2640,
2656
    UDIV  = 2641,
2657
    UDIV_MM = 2642,
2658
    V3MULU  = 2643,
2659
    VMM0  = 2644,
2660
    VMULU = 2645,
2661
    VSHF_B  = 2646,
2662
    VSHF_D  = 2647,
2663
    VSHF_H  = 2648,
2664
    VSHF_W  = 2649,
2665
    WAIT  = 2650,
2666
    WAIT_MM = 2651,
2667
    WAIT_MMR6 = 2652,
2668
    WRDSP = 2653,
2669
    WRDSP_MM  = 2654,
2670
    WRPGPR_MMR6 = 2655,
2671
    WSBH  = 2656,
2672
    WSBH_MM = 2657,
2673
    WSBH_MMR6 = 2658,
2674
    XOR = 2659,
2675
    XOR16_MM  = 2660,
2676
    XOR16_MMR6  = 2661,
2677
    XOR64 = 2662,
2678
    XORI_B  = 2663,
2679
    XORI_MMR6 = 2664,
2680
    XOR_MM  = 2665,
2681
    XOR_MMR6  = 2666,
2682
    XOR_V = 2667,
2683
    XORi  = 2668,
2684
    XORi64  = 2669,
2685
    XORi_MM = 2670,
2686
    XorRxRxRy16 = 2671,
2687
    YIELD = 2672,
2688
    INSTRUCTION_LIST_END = 2673
2689
  };
2690
2691
} // end Mips namespace
2692
} // end llvm namespace
2693
#endif // GET_INSTRINFO_ENUM
2694
2695
#ifdef GET_INSTRINFO_SCHED_ENUM
2696
#undef GET_INSTRINFO_SCHED_ENUM
2697
namespace llvm {
2698
2699
namespace Mips {
2700
namespace Sched {
2701
  enum {
2702
    NoInstrModel  = 0,
2703
    IIPseudo  = 1,
2704
    II_B  = 2,
2705
    II_BCCZAL = 3,
2706
    II_MTC1 = 4,
2707
    II_MFC1 = 5,
2708
    II_JALR = 6,
2709
    II_CVT  = 7,
2710
    II_DMULT  = 8,
2711
    II_DMULTU = 9,
2712
    II_DDIV = 10,
2713
    II_DDIVU  = 11,
2714
    II_IndirectBranchPseudo = 12,
2715
    II_MADD = 13,
2716
    II_MADDU  = 14,
2717
    II_MFHI_MFLO  = 15,
2718
    II_MSUB = 16,
2719
    II_MSUBU  = 17,
2720
    II_MTHI_MTLO  = 18,
2721
    II_MULT = 19,
2722
    II_MULTU  = 20,
2723
    II_ReturnPseudo = 21,
2724
    II_DIV  = 22,
2725
    II_DIVU = 23,
2726
    II_J  = 24,
2727
    II_JR = 25,
2728
    II_TRAP = 26,
2729
    II_ADD  = 27,
2730
    II_ADDIUPC  = 28,
2731
    II_ADDIU  = 29,
2732
    II_ADDU = 30,
2733
    II_ADDI = 31,
2734
    II_ALIGN  = 32,
2735
    II_ALUIPC = 33,
2736
    II_AND  = 34,
2737
    II_ANDI = 35,
2738
    II_AUI  = 36,
2739
    II_AUIPC  = 37,
2740
    IIM16Alu  = 38,
2741
    II_BADDU  = 39,
2742
    II_BC = 40,
2743
    II_BALC = 41,
2744
    II_BBIT = 42,
2745
    II_BC1CCZ = 43,
2746
    II_BC1F = 44,
2747
    II_BC1FL  = 45,
2748
    II_BC1T = 46,
2749
    II_BC1TL  = 47,
2750
    II_BC2CCZ = 48,
2751
    II_BCC  = 49,
2752
    II_BCCC = 50,
2753
    II_BCCZ = 51,
2754
    II_BCCZC  = 52,
2755
    II_BCCZALS  = 53,
2756
    II_BITSWAP  = 54,
2757
    II_BREAK  = 55,
2758
    II_CACHE  = 56,
2759
    II_CACHEE = 57,
2760
    II_CEIL = 58,
2761
    II_CFC1 = 59,
2762
    II_CFC2 = 60,
2763
    II_INS  = 61,
2764
    II_CLASS_D  = 62,
2765
    II_CLASS_S  = 63,
2766
    II_CLO  = 64,
2767
    II_CLZ  = 65,
2768
    II_CMP_CC_D = 66,
2769
    II_CMP_CC_S = 67,
2770
    II_CRC32B = 68,
2771
    II_CRC32CB  = 69,
2772
    II_CRC32CD  = 70,
2773
    II_CRC32CH  = 71,
2774
    II_CRC32CW  = 72,
2775
    II_CRC32D = 73,
2776
    II_CRC32H = 74,
2777
    II_CRC32W = 75,
2778
    II_CTC1 = 76,
2779
    II_CTC2 = 77,
2780
    II_C_CC_D = 78,
2781
    II_C_CC_S = 79,
2782
    II_DADD = 80,
2783
    II_DADDI  = 81,
2784
    II_DADDIU = 82,
2785
    II_DADDU  = 83,
2786
    II_DAHI = 84,
2787
    II_DALIGN = 85,
2788
    II_DATI = 86,
2789
    II_DAUI = 87,
2790
    II_DBITSWAP = 88,
2791
    II_DCLO = 89,
2792
    II_DCLZ = 90,
2793
    II_DERET  = 91,
2794
    II_EXT  = 92,
2795
    II_DI = 93,
2796
    II_DLSA = 94,
2797
    II_DMFC0  = 95,
2798
    II_DMFC1  = 96,
2799
    II_DMFC2  = 97,
2800
    II_DMFGC0 = 98,
2801
    II_DMOD = 99,
2802
    II_DMODU  = 100,
2803
    II_DMT  = 101,
2804
    II_DMTC0  = 102,
2805
    II_DMTC1  = 103,
2806
    II_DMTC2  = 104,
2807
    II_DMTGC0 = 105,
2808
    II_DMUH = 106,
2809
    II_DMUHU  = 107,
2810
    II_DMUL = 108,
2811
    II_POP  = 109,
2812
    II_DROTR  = 110,
2813
    II_DROTR32  = 111,
2814
    II_DROTRV = 112,
2815
    II_DSBH = 113,
2816
    II_DSHD = 114,
2817
    II_DSLL = 115,
2818
    II_DSLL32 = 116,
2819
    II_DSLLV  = 117,
2820
    II_DSRA = 118,
2821
    II_DSRA32 = 119,
2822
    II_DSRAV  = 120,
2823
    II_DSRL = 121,
2824
    II_DSRL32 = 122,
2825
    II_DSRLV  = 123,
2826
    II_DSUB = 124,
2827
    II_DSUBU  = 125,
2828
    II_DVP  = 126,
2829
    II_DVPE = 127,
2830
    II_EHB  = 128,
2831
    II_EI = 129,
2832
    II_EMT  = 130,
2833
    II_ERET = 131,
2834
    II_ERETNC = 132,
2835
    II_EVP  = 133,
2836
    II_EVPE = 134,
2837
    II_ABS  = 135,
2838
    II_SQRT_D = 136,
2839
    II_ADD_D  = 137,
2840
    II_ADD_S  = 138,
2841
    II_DIV_D  = 139,
2842
    II_DIV_S  = 140,
2843
    II_FLOOR  = 141,
2844
    II_MOV_D  = 142,
2845
    II_MOV_S  = 143,
2846
    II_MUL_D  = 144,
2847
    II_MUL_S  = 145,
2848
    II_NEG  = 146,
2849
    II_FORK = 147,
2850
    II_SQRT_S = 148,
2851
    II_SUB_D  = 149,
2852
    II_SUB_S  = 150,
2853
    II_GINVI  = 151,
2854
    II_GINVT  = 152,
2855
    II_HYPCALL  = 153,
2856
    II_JAL  = 154,
2857
    II_JALR_HB  = 155,
2858
    II_JALRC  = 156,
2859
    II_JALRS  = 157,
2860
    II_JALS = 158,
2861
    II_JIALC  = 159,
2862
    II_JIC  = 160,
2863
    II_JRADDIUSP  = 161,
2864
    II_JRC  = 162,
2865
    II_JR_HB  = 163,
2866
    II_LB = 164,
2867
    II_LBE  = 165,
2868
    II_LBU  = 166,
2869
    II_LBUE = 167,
2870
    II_LD = 168,
2871
    II_LDC1 = 169,
2872
    II_LDC2 = 170,
2873
    II_LDC3 = 171,
2874
    II_LDL  = 172,
2875
    II_LDPC = 173,
2876
    II_LDR  = 174,
2877
    II_LDXC1  = 175,
2878
    II_LH = 176,
2879
    II_LHE  = 177,
2880
    II_LHU  = 178,
2881
    II_LHUE = 179,
2882
    II_LI = 180,
2883
    II_LL = 181,
2884
    II_LLD  = 182,
2885
    II_LLE  = 183,
2886
    II_LSA  = 184,
2887
    II_LUI  = 185,
2888
    II_LUXC1  = 186,
2889
    II_LW = 187,
2890
    II_LWC1 = 188,
2891
    II_LWC2 = 189,
2892
    II_LWC3 = 190,
2893
    II_LWE  = 191,
2894
    II_LWL  = 192,
2895
    II_LWLE = 193,
2896
    II_LWM  = 194,
2897
    II_LWPC = 195,
2898
    II_LWP  = 196,
2899
    II_LWR  = 197,
2900
    II_LWRE = 198,
2901
    II_LWUPC  = 199,
2902
    II_LWU  = 200,
2903
    II_LWXC1  = 201,
2904
    II_LWXS = 202,
2905
    II_MADDF_D  = 203,
2906
    II_MADDF_S  = 204,
2907
    II_MADD_D = 205,
2908
    II_MADD_S = 206,
2909
    II_MAX_D  = 207,
2910
    II_MAXA_D = 208,
2911
    II_MAX_S  = 209,
2912
    II_MAXA_S = 210,
2913
    II_MFC0 = 211,
2914
    II_MFC2 = 212,
2915
    II_MFGC0  = 213,
2916
    II_MFHC0  = 214,
2917
    II_MFHC1  = 215,
2918
    II_MFHGC0 = 216,
2919
    II_MFTR = 217,
2920
    II_MIN_S  = 218,
2921
    II_MINA_D = 219,
2922
    II_MIN_D  = 220,
2923
    II_MINA_S = 221,
2924
    II_MOD  = 222,
2925
    II_MODU = 223,
2926
    II_MOVE = 224,
2927
    II_MOVF_D = 225,
2928
    II_MOVF = 226,
2929
    II_MOVF_S = 227,
2930
    II_MOVN_D = 228,
2931
    II_MOVN = 229,
2932
    II_MOVN_S = 230,
2933
    II_MOVT_D = 231,
2934
    II_MOVT = 232,
2935
    II_MOVT_S = 233,
2936
    II_MOVZ_D = 234,
2937
    II_MOVZ = 235,
2938
    II_MOVZ_S = 236,
2939
    II_MSUBF_D  = 237,
2940
    II_MSUBF_S  = 238,
2941
    II_MSUB_D = 239,
2942
    II_MSUB_S = 240,
2943
    II_MTC0 = 241,
2944
    II_MTC2 = 242,
2945
    II_MTGC0  = 243,
2946
    II_MTHC0  = 244,
2947
    II_MTHC1  = 245,
2948
    II_MTHGC0 = 246,
2949
    II_MTTR = 247,
2950
    II_MUH  = 248,
2951
    II_MUHU = 249,
2952
    II_MUL  = 250,
2953
    II_MULU = 251,
2954
    II_NMADD_D  = 252,
2955
    II_NMADD_S  = 253,
2956
    II_NMSUB_D  = 254,
2957
    II_NMSUB_S  = 255,
2958
    II_NOR  = 256,
2959
    II_NOT  = 257,
2960
    II_OR = 258,
2961
    II_ORI  = 259,
2962
    II_PAUSE  = 260,
2963
    II_PREF = 261,
2964
    II_PREFE  = 262,
2965
    II_RDHWR  = 263,
2966
    II_RDPGPR = 264,
2967
    II_RECIP_D  = 265,
2968
    II_RECIP_S  = 266,
2969
    II_RINT_D = 267,
2970
    II_RINT_S = 268,
2971
    II_ROTR = 269,
2972
    II_ROTRV  = 270,
2973
    II_ROUND  = 271,
2974
    II_RSQRT_D  = 272,
2975
    II_RSQRT_S  = 273,
2976
    II_RESTORE  = 274,
2977
    II_SB = 275,
2978
    II_SBE  = 276,
2979
    II_SC = 277,
2980
    II_SCD  = 278,
2981
    II_SCE  = 279,
2982
    II_SD = 280,
2983
    II_SDBBP  = 281,
2984
    II_SDC1 = 282,
2985
    II_SDC2 = 283,
2986
    II_SDC3 = 284,
2987
    II_SDL  = 285,
2988
    II_SDR  = 286,
2989
    II_SDXC1  = 287,
2990
    II_SEB  = 288,
2991
    II_SEH  = 289,
2992
    II_SELCCZ = 290,
2993
    II_SELCCZ_D = 291,
2994
    II_SELCCZ_S = 292,
2995
    II_SEL_D  = 293,
2996
    II_SEL_S  = 294,
2997
    II_SEQ_SNE  = 295,
2998
    II_SEQI_SNEI  = 296,
2999
    II_SH = 297,
3000
    II_SHE  = 298,
3001
    II_SIGRIE = 299,
3002
    II_SLL  = 300,
3003
    II_SLLV = 301,
3004
    II_SLT_SLTU = 302,
3005
    II_SLTI_SLTIU = 303,
3006
    II_SRA  = 304,
3007
    II_SRAV = 305,
3008
    II_SRL  = 306,
3009
    II_SRLV = 307,
3010
    II_SSNOP  = 308,
3011
    II_SUB  = 309,
3012
    II_SUBU = 310,
3013
    II_SUXC1  = 311,
3014
    II_SW = 312,
3015
    II_SWC1 = 313,
3016
    II_SWC2 = 314,
3017
    II_SWC3 = 315,
3018
    II_SWE  = 316,
3019
    II_SWL  = 317,
3020
    II_SWLE = 318,
3021
    II_SWM  = 319,
3022
    II_SWP  = 320,
3023
    II_SWR  = 321,
3024
    II_SWRE = 322,
3025
    II_SWXC1  = 323,
3026
    II_SYNC = 324,
3027
    II_SYNCI  = 325,
3028
    II_SYSCALL  = 326,
3029
    II_SAVE = 327,
3030
    II_TEQ  = 328,
3031
    II_TEQI = 329,
3032
    II_TGE  = 330,
3033
    II_TGEI = 331,
3034
    II_TGEIU  = 332,
3035
    II_TGEU = 333,
3036
    II_TLBGINV  = 334,
3037
    II_TLBGINVF = 335,
3038
    II_TLBGP  = 336,
3039
    II_TLBGR  = 337,
3040
    II_TLBGWI = 338,
3041
    II_TLBGWR = 339,
3042
    II_TLBINV = 340,
3043
    II_TLBINVF  = 341,
3044
    II_TLBP = 342,
3045
    II_TLBR = 343,
3046
    II_TLBWI  = 344,
3047
    II_TLBWR  = 345,
3048
    II_TLT  = 346,
3049
    II_TLTI = 347,
3050
    II_TTLTIU = 348,
3051
    II_TLTU = 349,
3052
    II_TNE  = 350,
3053
    II_TNEI = 351,
3054
    II_TRUNC  = 352,
3055
    II_WAIT = 353,
3056
    II_WRPGPR = 354,
3057
    II_WSBH = 355,
3058
    II_XOR  = 356,
3059
    II_XORI = 357,
3060
    II_YIELD  = 358,
3061
    AND = 359,
3062
    LUi = 360,
3063
    NOR = 361,
3064
    OR  = 362,
3065
    SLTi_SLTiu  = 363,
3066
    SUB = 364,
3067
    SUBu  = 365,
3068
    XOR = 366,
3069
    B = 367,
3070
    BAL = 368,
3071
    BAL_BR_BGEZAL_BGEZALL_BLTZAL_BLTZALL  = 369,
3072
    BEQ_BEQL_BNE_BNEL = 370,
3073
    BGEZ_BGEZL_BGTZ_BGTZL_BLEZ_BLEZL_BLTZ_BLTZL = 371,
3074
    BREAK = 372,
3075
    DERET = 373,
3076
    ERET  = 374,
3077
    ERETNC  = 375,
3078
    J_TAILCALL  = 376,
3079
    JR_TAILCALLREG_TAILCALLREGHB  = 377,
3080
    JR_HB = 378,
3081
    PseudoIndirectBranch_PseudoIndirectHazardBranch = 379,
3082
    PseudoReturn  = 380,
3083
    SDBBP = 381,
3084
    SSNOP = 382,
3085
    SYSCALL = 383,
3086
    TEQ = 384,
3087
    TEQI  = 385,
3088
    TGE = 386,
3089
    TGEI  = 387,
3090
    TGEIU = 388,
3091
    TGEU  = 389,
3092
    TLT = 390,
3093
    TLTI  = 391,
3094
    TLTU  = 392,
3095
    TNE = 393,
3096
    TNEI  = 394,
3097
    TRAP  = 395,
3098
    TTLTIU  = 396,
3099
    WAIT  = 397,
3100
    PAUSE = 398,
3101
    JAL = 399,
3102
    JALR_JALRHBPseudo_JALRPseudo  = 400,
3103
    JALR_HB = 401,
3104
    JALX  = 402,
3105
    TLBINV  = 403,
3106
    TLBINVF = 404,
3107
    TLBP  = 405,
3108
    TLBR  = 406,
3109
    TLBWI = 407,
3110
    TLBWR = 408,
3111
    MFC0  = 409,
3112
    MTC0  = 410,
3113
    MFC2  = 411,
3114
    MTC2  = 412,
3115
    LB  = 413,
3116
    LBu = 414,
3117
    LH  = 415,
3118
    LHu = 416,
3119
    LW  = 417,
3120
    LL  = 418,
3121
    LWC2  = 419,
3122
    LWC3  = 420,
3123
    LDC2  = 421,
3124
    LDC3  = 422,
3125
    LBE = 423,
3126
    LBuE  = 424,
3127
    LHE = 425,
3128
    LHuE  = 426,
3129
    LWE = 427,
3130
    LLE = 428,
3131
    LWPC  = 429,
3132
    LWL = 430,
3133
    LWR = 431,
3134
    LWLE  = 432,
3135
    LWRE  = 433,
3136
    SB  = 434,
3137
    SH  = 435,
3138
    SW  = 436,
3139
    SWC2  = 437,
3140
    SWC3  = 438,
3141
    SDC2  = 439,
3142
    SDC3  = 440,
3143
    SC  = 441,
3144
    SBE = 442,
3145
    SHE = 443,
3146
    SWE = 444,
3147
    SCE = 445,
3148
    SWL = 446,
3149
    SWR = 447,
3150
    SWLE  = 448,
3151
    SWRE  = 449,
3152
    PREF  = 450,
3153
    PREFE = 451,
3154
    CACHE = 452,
3155
    CACHEE  = 453,
3156
    SYNC  = 454,
3157
    SYNCI = 455,
3158
    CLO = 456,
3159
    CLZ = 457,
3160
    DI  = 458,
3161
    EI  = 459,
3162
    MFHI_MFLO_PseudoMFHI_PseudoMFLO = 460,
3163
    EHB = 461,
3164
    RDHWR = 462,
3165
    WSBH  = 463,
3166
    MOVN_I_I  = 464,
3167
    MOVZ_I_I  = 465,
3168
    DIV_PseudoSDIV_SDIV = 466,
3169
    DIVU_PseudoUDIV_UDIV  = 467,
3170
    MUL = 468,
3171
    MULT_PseudoMULT = 469,
3172
    MULTu_PseudoMULTu = 470,
3173
    MADD_PseudoMADD = 471,
3174
    MADDU_PseudoMADDU = 472,
3175
    MSUB_PseudoMSUB = 473,
3176
    MSUBU_PseudoMSUBU = 474,
3177
    MTHI_MTLO_PseudoMTLOHI  = 475,
3178
    EXT = 476,
3179
    INS = 477,
3180
    ADD = 478,
3181
    ADDi  = 479,
3182
    ADDiu = 480,
3183
    ANDi  = 481,
3184
    ORi = 482,
3185
    ROTR  = 483,
3186
    SEB = 484,
3187
    SEH = 485,
3188
    SLT_SLTu  = 486,
3189
    SLL = 487,
3190
    SRA = 488,
3191
    SRL = 489,
3192
    XORi  = 490,
3193
    ADDu  = 491,
3194
    SLLV  = 492,
3195
    SRAV  = 493,
3196
    SRLV  = 494,
3197
    LSA = 495,
3198
    COPY  = 496,
3199
    VSHF_B_VSHF_D_VSHF_H_VSHF_W = 497,
3200
    BINSLI_B_BINSLI_D_BINSLI_H_BINSLI_W_BINSL_B_BINSL_D_BINSL_H_BINSL_W = 498,
3201
    BINSRI_B_BINSRI_D_BINSRI_H_BINSRI_W_BINSR_B_BINSR_D_BINSR_H_BINSR_W = 499,
3202
    INSERT_B_INSERT_D_INSERT_H_INSERT_W = 500,
3203
    SLDI_B_SLDI_D_SLDI_H_SLDI_W_SLD_B_SLD_D_SLD_H_SLD_W = 501,
3204
    BSETI_B_BSETI_D_BSETI_H_BSETI_W_BSET_B_BSET_D_BSET_H_BSET_W = 502,
3205
    BCLRI_B_BCLRI_D_BCLRI_H_BCLRI_W_BCLR_B_BCLR_D_BCLR_H_BCLR_W = 503,
3206
    BNEGI_B_BNEGI_D_BNEGI_H_BNEGI_W_BNEG_B_BNEG_D_BNEG_H_BNEG_W = 504,
3207
    BSELI_B_BSEL_V  = 505,
3208
    BMNZI_B_BMNZ_V_BMZI_B_BMZ_V = 506,
3209
    PCNT_B_PCNT_D_PCNT_H_PCNT_W = 507,
3210
    SAT_S_B_SAT_S_D_SAT_S_H_SAT_S_W_SAT_U_B_SAT_U_D_SAT_U_H_SAT_U_W = 508,
3211
    BNZ_B_BNZ_D_BNZ_H_BNZ_V_BNZ_W_BZ_B_BZ_D_BZ_H_BZ_V_BZ_W  = 509,
3212
    CFCMSA_CTCMSA = 510,
3213
    FABS_S_FABS_D32_FABS_D64  = 511,
3214
    MOVF_D32_MOVF_D64 = 512,
3215
    MOVF_S  = 513,
3216
    MOVT_D32_MOVT_D64 = 514,
3217
    MOVT_S  = 515,
3218
    FMOV_D32_FMOV_D64 = 516,
3219
    FMOV_S  = 517,
3220
    FNEG_S_FNEG_D32_FNEG_D64  = 518,
3221
    ADD_A_B_ADD_A_D_ADD_A_H_ADD_A_W = 519,
3222
    ADDS_A_B_ADDS_A_D_ADDS_A_H_ADDS_A_W_ADDS_S_B_ADDS_S_D_ADDS_S_H_ADDS_S_W_ADDS_U_B_ADDS_U_D_ADDS_U_H_ADDS_U_W = 520,
3223
    ADDVI_B_ADDVI_D_ADDVI_H_ADDVI_W_ADDV_B_ADDV_D_ADDV_H_ADDV_W = 521,
3224
    ASUB_S_B_ASUB_S_D_ASUB_S_H_ASUB_S_W_ASUB_U_B_ASUB_U_D_ASUB_U_H_ASUB_U_W = 522,
3225
    AVER_S_B_AVER_S_D_AVER_S_H_AVER_S_W_AVER_U_B_AVER_U_D_AVER_U_H_AVER_U_W_AVE_S_B_AVE_S_D_AVE_S_H_AVE_S_W_AVE_U_B_AVE_U_D_AVE_U_H_AVE_U_W = 523,
3226
    SHF_B_SHF_H_SHF_W = 524,
3227
    FILL_B_FILL_D_FILL_H_FILL_W = 525,
3228
    SPLATI_B_SPLATI_D_SPLATI_H_SPLATI_W_SPLAT_B_SPLAT_D_SPLAT_H_SPLAT_W = 526,
3229
    MOVE_V  = 527,
3230
    LDI_B_LDI_D_LDI_H_LDI_W = 528,
3231
    AND_V_NOR_V_OR_V_XOR_V  = 529,
3232
    ANDI_B_NORI_B_ORI_B_XORI_B  = 530,
3233
    FEXP2_D_FEXP2_W = 531,
3234
    CLTI_S_B_CLTI_S_D_CLTI_S_H_CLTI_S_W_CLTI_U_B_CLTI_U_D_CLTI_U_H_CLTI_U_W_CLT_S_B_CLT_S_D_CLT_S_H_CLT_S_W_CLT_U_B_CLT_U_D_CLT_U_H_CLT_U_W = 532,
3235
    CLEI_S_B_CLEI_S_D_CLEI_S_H_CLEI_S_W_CLEI_U_B_CLEI_U_D_CLEI_U_H_CLEI_U_W_CLE_S_B_CLE_S_D_CLE_S_H_CLE_S_W_CLE_U_B_CLE_U_D_CLE_U_H_CLE_U_W = 533,
3236
    CEQI_B_CEQI_D_CEQI_H_CEQI_W_CEQ_B_CEQ_D_CEQ_H_CEQ_W = 534,
3237
    CMP_UN_D  = 535,
3238
    CMP_UN_S  = 536,
3239
    CMP_UEQ_D = 537,
3240
    CMP_UEQ_S = 538,
3241
    CMP_EQ_D  = 539,
3242
    CMP_EQ_S  = 540,
3243
    CMP_LT_D  = 541,
3244
    CMP_LT_S  = 542,
3245
    CMP_ULT_D = 543,
3246
    CMP_ULT_S = 544,
3247
    CMP_LE_D  = 545,
3248
    CMP_LE_S  = 546,
3249
    CMP_ULE_D = 547,
3250
    CMP_ULE_S = 548,
3251
    FSAF_D_FSAF_W_FSEQ_D_FSEQ_W_FSLE_D_FSLE_W_FSLT_D_FSLT_W_FSNE_D_FSNE_W_FSOR_D_FSOR_W = 549,
3252
    FSUEQ_D_FSUEQ_W = 550,
3253
    FSULE_D_FSULE_W = 551,
3254
    FSULT_D_FSULT_W = 552,
3255
    FSUNE_D_FSUNE_W = 553,
3256
    FSUN_D_FSUN_W = 554,
3257
    FCAF_D_FCAF_W = 555,
3258
    FCEQ_D_FCEQ_W = 556,
3259
    FCLE_D_FCLE_W = 557,
3260
    FCLT_D_FCLT_W = 558,
3261
    FCNE_D_FCNE_W = 559,
3262
    FCOR_D_FCOR_W = 560,
3263
    FCUEQ_D_FCUEQ_W = 561,
3264
    FCULE_D_FCULE_W = 562,
3265
    FCULT_D_FCULT_W = 563,
3266
    FCUNE_D_FCUNE_W = 564,
3267
    FCUN_D_FCUN_W = 565,
3268
    FABS_D_FABS_W = 566,
3269
    FFINT_S_D_FFINT_S_W_FFINT_U_D_FFINT_U_W = 567,
3270
    FFQL_D_FFQL_W = 568,
3271
    FFQR_D_FFQR_W = 569,
3272
    FTINT_S_D_FTINT_S_W_FTINT_U_D_FTINT_U_W = 570,
3273
    FRINT_D_FRINT_W = 571,
3274
    FTQ_H_FTQ_W = 572,
3275
    FTRUNC_S_D_FTRUNC_S_W_FTRUNC_U_D_FTRUNC_U_W = 573,
3276
    FEXDO_H_FEXDO_W = 574,
3277
    FEXUPL_D_FEXUPL_W = 575,
3278
    FEXUPR_D_FEXUPR_W = 576,
3279
    FCLASS_D_FCLASS_W = 577,
3280
    FMAX_A_D_FMAX_A_W = 578,
3281
    FMAX_D_FMAX_W = 579,
3282
    FMIN_A_D_FMIN_A_W = 580,
3283
    FMIN_D_FMIN_W = 581,
3284
    FLOG2_D_FLOG2_W = 582,
3285
    ILVL_B_ILVL_D_ILVL_H_ILVL_W_ILVR_B_ILVR_D_ILVR_H_ILVR_W = 583,
3286
    ILVEV_B_ILVEV_D_ILVEV_H_ILVEV_W_ILVOD_B_ILVOD_D_ILVOD_H_ILVOD_W = 584,
3287
    INSVE_B_INSVE_D_INSVE_H_INSVE_W = 585,
3288
    SUBS_S_B_SUBS_S_D_SUBS_S_H_SUBS_S_W_SUBS_U_B_SUBS_U_D_SUBS_U_H_SUBS_U_W = 586,
3289
    SUBSUS_U_B_SUBSUS_U_D_SUBSUS_U_H_SUBSUS_U_W = 587,
3290
    SUBSUU_S_B_SUBSUU_S_D_SUBSUU_S_H_SUBSUU_S_W = 588,
3291
    SUBVI_B_SUBVI_D_SUBVI_H_SUBVI_W = 589,
3292
    SUBV_B_SUBV_D_SUBV_H_SUBV_W = 590,
3293
    MOD_S_B_MOD_S_D_MOD_S_H_MOD_S_W_MOD_U_B_MOD_U_D_MOD_U_H_MOD_U_W = 591,
3294
    DIV_S_B_DIV_S_D_DIV_S_H_DIV_S_W_DIV_U_B_DIV_U_D_DIV_U_H_DIV_U_W = 592,
3295
    HADD_S_D_HADD_S_H_HADD_S_W_HADD_U_D_HADD_U_H_HADD_U_W = 593,
3296
    HSUB_S_D_HSUB_S_H_HSUB_S_W_HSUB_U_D_HSUB_U_H_HSUB_U_W = 594,
3297
    MAX_S_B_MAX_S_D_MAX_S_H_MAX_S_W_MIN_S_B_MIN_S_D_MIN_S_H_MIN_S_W = 595,
3298
    MAX_U_B_MAX_U_D_MAX_U_H_MAX_U_W_MIN_U_B_MIN_U_D_MIN_U_H_MIN_U_W = 596,
3299
    MAX_A_B_MAX_A_D_MAX_A_H_MAX_A_W_MIN_A_B_MIN_A_D_MIN_A_H_MIN_A_W = 597,
3300
    MAXI_S_B_MAXI_S_D_MAXI_S_H_MAXI_S_W_MAXI_U_B_MAXI_U_D_MAXI_U_H_MAXI_U_W_MINI_S_B_MINI_S_D_MINI_S_H_MINI_S_W_MINI_U_B_MINI_U_D_MINI_U_H_MINI_U_W = 598,
3301
    SRAI_B_SRAI_D_SRAI_H_SRAI_W_SRA_B_SRA_D_SRA_H_SRA_W = 599,
3302
    SRLI_B_SRLI_D_SRLI_H_SRLI_W_SRL_B_SRL_D_SRL_H_SRL_W = 600,
3303
    SRARI_B_SRARI_D_SRARI_H_SRARI_W_SRAR_B_SRAR_D_SRAR_H_SRAR_W = 601,
3304
    SRLRI_B_SRLRI_D_SRLRI_H_SRLRI_W_SRLR_B_SRLR_D_SRLR_H_SRLR_W = 602,
3305
    SLLI_B_SLLI_D_SLLI_H_SLLI_W_SLL_B_SLL_D_SLL_H_SLL_W = 603,
3306
    PCKEV_B_PCKEV_D_PCKEV_H_PCKEV_W_PCKOD_B_PCKOD_D_PCKOD_H_PCKOD_W = 604,
3307
    NLOC_B_NLOC_D_NLOC_H_NLOC_W_NLZC_B_NLZC_D_NLZC_H_NLZC_W = 605,
3308
    FADD_D32_FADD_D64 = 606,
3309
    FADD_S  = 607,
3310
    FMUL_D32_FMUL_D64 = 608,
3311
    FMUL_S  = 609,
3312
    FSUB_D32_FSUB_D64 = 610,
3313
    FSUB_S  = 611,
3314
    TRUNC_L_D64_TRUNC_L_S_TRUNC_W_D32_TRUNC_W_D64_TRUNC_W_S = 612,
3315
    CVT_D32_S_CVT_D32_W_CVT_D64_L_CVT_D64_S_CVT_D64_W_CVT_L_D64_CVT_L_S_CVT_S_D32_CVT_S_D64_CVT_S_L_CVT_S_W_CVT_W_D32_CVT_W_D64_CVT_W_S = 613,
3316
    C_EQ_D32_C_EQ_D64_C_F_D32_C_F_D64_C_LE_D32_C_LE_D64_C_LT_D32_C_LT_D64_C_NGE_D32_C_NGE_D64_C_NGLE_D32_C_NGLE_D64_C_NGL_D32_C_NGL_D64_C_NGT_D32_C_NGT_D64_C_OLE_D32_C_OLE_D64_C_OLT_D32_C_OLT_D64_C_SEQ_D32_C_SEQ_D64_C_SF_D32_C_SF_D64_C_UEQ_D32_C_UEQ_D64_C_ULE_D32_C_ULE_D64_C_ULT_D32_C_ULT_D64_C_UN_D32_C_UN_D64 = 614,
3317
    C_EQ_S_C_F_S_C_LE_S_C_LT_S_C_NGE_S_C_NGLE_S_C_NGL_S_C_NGT_S_C_OLE_S_C_OLT_S_C_SEQ_S_C_SF_S_C_UEQ_S_C_ULE_S_C_ULT_S_C_UN_S = 615,
3318
    FCMP_D32_FCMP_D64 = 616,
3319
    FCMP_S32  = 617,
3320
    PseudoCVT_D32_W_PseudoCVT_D64_L_PseudoCVT_D64_W_PseudoCVT_S_L_PseudoCVT_S_W = 618,
3321
    FDIV_S  = 619,
3322
    FDIV_D32_FDIV_D64 = 620,
3323
    FSQRT_S = 621,
3324
    FSQRT_D32_FSQRT_D64 = 622,
3325
    FRCP_D_FRCP_W = 623,
3326
    FRSQRT_D_FRSQRT_W = 624,
3327
    RECIP_D32_RECIP_D64 = 625,
3328
    RSQRT_D32_RSQRT_D64 = 626,
3329
    RECIP_S = 627,
3330
    RSQRT_S = 628,
3331
    FMADD_D_FMADD_W = 629,
3332
    FMSUB_D_FMSUB_W = 630,
3333
    FDIV_W  = 631,
3334
    FDIV_D  = 632,
3335
    FSQRT_W = 633,
3336
    FSQRT_D = 634,
3337
    FMUL_D_FMUL_W = 635,
3338
    FADD_D_FADD_W = 636,
3339
    FSUB_D_FSUB_W = 637,
3340
    DPADD_S_D_DPADD_S_H_DPADD_S_W_DPADD_U_D_DPADD_U_H_DPADD_U_W = 638,
3341
    DPSUB_S_D_DPSUB_S_H_DPSUB_S_W_DPSUB_U_D_DPSUB_U_H_DPSUB_U_W = 639,
3342
    DOTP_S_D_DOTP_S_H_DOTP_S_W_DOTP_U_D_DOTP_U_H_DOTP_U_W = 640,
3343
    MSUBV_B_MSUBV_D_MSUBV_H_MSUBV_W = 641,
3344
    MADDV_B_MADDV_D_MADDV_H_MADDV_W = 642,
3345
    MULV_B_MULV_D_MULV_H_MULV_W = 643,
3346
    MADDR_Q_H_MADDR_Q_W = 644,
3347
    MADD_Q_H_MADD_Q_W = 645,
3348
    MSUBR_Q_H_MSUBR_Q_W = 646,
3349
    MSUB_Q_H_MSUB_Q_W = 647,
3350
    MULR_Q_H_MULR_Q_W = 648,
3351
    MUL_Q_H_MUL_Q_W = 649,
3352
    MADD_D32_MADD_D64 = 650,
3353
    MADD_S  = 651,
3354
    MSUB_D32_MSUB_D64 = 652,
3355
    MSUB_S  = 653,
3356
    NMADD_D32_NMADD_D64 = 654,
3357
    NMADD_S = 655,
3358
    NMSUB_D32_NMSUB_D64 = 656,
3359
    NMSUB_S = 657,
3360
    CTC1  = 658,
3361
    MTC1_MTC1_D64_BuildPairF64_BuildPairF64_64  = 659,
3362
    MTHC1_D32_MTHC1_D64 = 660,
3363
    COPY_U_B_COPY_U_H_COPY_U_W  = 661,
3364
    COPY_S_B_COPY_S_D_COPY_S_H_COPY_S_W = 662,
3365
    BC1F  = 663,
3366
    BC1FL = 664,
3367
    BC1T  = 665,
3368
    BC1TL = 666,
3369
    CFC1  = 667,
3370
    MFC1_MFC1_D64_ExtractElementF64_ExtractElementF64_64  = 668,
3371
    MFHC1_D32_MFHC1_D64 = 669,
3372
    MOVF_I  = 670,
3373
    MOVT_I  = 671,
3374
    SDC1  = 672,
3375
    SDXC1 = 673,
3376
    SUXC1 = 674,
3377
    SWC1  = 675,
3378
    SWXC1 = 676,
3379
    ST_B_ST_D_ST_H_ST_W = 677,
3380
    MOVN_I_D32_MOVN_I_D64 = 678,
3381
    MOVN_I_S  = 679,
3382
    MOVZ_I_D32_MOVZ_I_D64 = 680,
3383
    MOVZ_I_S  = 681,
3384
    LDC1  = 682,
3385
    LDXC1 = 683,
3386
    LWC1  = 684,
3387
    LWXC1 = 685,
3388
    LUXC1 = 686,
3389
    LD_B_LD_D_LD_H_LD_W = 687,
3390
    CEIL_L_D64_CEIL_L_S_CEIL_W_D32_CEIL_W_D64_CEIL_W_S  = 688,
3391
    FLOOR_L_D64_FLOOR_L_S_FLOOR_W_D32_FLOOR_W_D64_FLOOR_W_S = 689,
3392
    ROUND_L_D64_ROUND_L_S_ROUND_W_D32_ROUND_W_D64_ROUND_W_S = 690,
3393
    ROTRV = 691,
3394
    EXTRV_RS_W  = 692,
3395
    EXTRV_R_W = 693,
3396
    EXTRV_S_H = 694,
3397
    EXTRV_W = 695,
3398
    EXTR_RS_W = 696,
3399
    EXTR_R_W  = 697,
3400
    EXTR_S_H  = 698,
3401
    EXTR_W  = 699,
3402
    INSV  = 700,
3403
    MTHLIP  = 701,
3404
    MTHI_DSP  = 702,
3405
    MTLO_DSP  = 703,
3406
    ABSQ_S_PH = 704,
3407
    ABSQ_S_W  = 705,
3408
    ADDQ_PH = 706,
3409
    ADDQ_S_PH = 707,
3410
    ADDQ_S_W  = 708,
3411
    ADDSC = 709,
3412
    ADDU_QB = 710,
3413
    ADDU_S_QB = 711,
3414
    ADDWC = 712,
3415
    BITREV  = 713,
3416
    BPOSGE32  = 714,
3417
    CMPGU_EQ_QB = 715,
3418
    CMPGU_LE_QB = 716,
3419
    CMPGU_LT_QB = 717,
3420
    CMPU_EQ_QB  = 718,
3421
    CMPU_LE_QB  = 719,
3422
    CMPU_LT_QB  = 720,
3423
    CMP_EQ_PH = 721,
3424
    CMP_LE_PH = 722,
3425
    CMP_LT_PH = 723,
3426
    DPAQ_SA_L_W = 724,
3427
    DPAQ_S_W_PH = 725,
3428
    DPAU_H_QBL  = 726,
3429
    DPAU_H_QBR  = 727,
3430
    DPSQ_SA_L_W = 728,
3431
    DPSQ_S_W_PH = 729,
3432
    DPSU_H_QBL  = 730,
3433
    DPSU_H_QBR  = 731,
3434
    EXTPDPV = 732,
3435
    EXTPDP  = 733,
3436
    EXTPV = 734,
3437
    EXTP  = 735,
3438
    LBUX  = 736,
3439
    LHX = 737,
3440
    LWX = 738,
3441
    MADDU_DSP = 739,
3442
    MADD_DSP  = 740,
3443
    MAQ_SA_W_PHL  = 741,
3444
    MAQ_SA_W_PHR  = 742,
3445
    MAQ_S_W_PHL = 743,
3446
    MAQ_S_W_PHR = 744,
3447
    MFHI_DSP  = 745,
3448
    MFLO_DSP  = 746,
3449
    MODSUB  = 747,
3450
    MSUBU_DSP = 748,
3451
    MSUB_DSP  = 749,
3452
    MULEQ_S_W_PHL = 750,
3453
    MULEQ_S_W_PHR = 751,
3454
    MULEU_S_PH_QBL  = 752,
3455
    MULEU_S_PH_QBR  = 753,
3456
    MULQ_RS_PH  = 754,
3457
    MULSAQ_S_W_PH = 755,
3458
    MULTU_DSP = 756,
3459
    MULT_DSP  = 757,
3460
    PACKRL_PH = 758,
3461
    PICK_PH = 759,
3462
    PICK_QB = 760,
3463
    PRECEQU_PH_QBLA = 761,
3464
    PRECEQU_PH_QBL  = 762,
3465
    PRECEQU_PH_QBRA = 763,
3466
    PRECEQU_PH_QBR  = 764,
3467
    PRECEQ_W_PHL  = 765,
3468
    PRECEQ_W_PHR  = 766,
3469
    PRECEU_PH_QBLA  = 767,
3470
    PRECEU_PH_QBL = 768,
3471
    PRECEU_PH_QBRA  = 769,
3472
    PRECEU_PH_QBR = 770,
3473
    PRECRQU_S_QB_PH = 771,
3474
    PRECRQ_PH_W = 772,
3475
    PRECRQ_QB_PH  = 773,
3476
    PRECRQ_RS_PH_W  = 774,
3477
    RADDU_W_QB  = 775,
3478
    RDDSP = 776,
3479
    REPLV_PH  = 777,
3480
    REPLV_QB  = 778,
3481
    REPL_PH = 779,
3482
    REPL_QB = 780,
3483
    SHILOV  = 781,
3484
    SHILO = 782,
3485
    SHLLV_PH  = 783,
3486
    SHLLV_QB  = 784,
3487
    SHLLV_S_PH  = 785,
3488
    SHLLV_S_W = 786,
3489
    SHLL_PH = 787,
3490
    SHLL_QB = 788,
3491
    SHLL_S_PH = 789,
3492
    SHLL_S_W  = 790,
3493
    SHRAV_PH  = 791,
3494
    SHRAV_R_PH  = 792,
3495
    SHRAV_R_W = 793,
3496
    SHRA_PH = 794,
3497
    SHRA_R_PH = 795,
3498
    SHRA_R_W  = 796,
3499
    SHRLV_QB  = 797,
3500
    SHRL_QB = 798,
3501
    SUBQ_PH = 799,
3502
    SUBQ_S_PH = 800,
3503
    SUBQ_S_W  = 801,
3504
    SUBU_QB = 802,
3505
    SUBU_S_QB = 803,
3506
    WRDSP = 804,
3507
    ABSQ_S_QB = 805,
3508
    ADDQH_PH  = 806,
3509
    ADDQH_R_PH  = 807,
3510
    ADDQH_R_W = 808,
3511
    ADDQH_W = 809,
3512
    ADDUH_QB  = 810,
3513
    ADDUH_R_QB  = 811,
3514
    ADDU_PH = 812,
3515
    ADDU_S_PH = 813,
3516
    APPEND  = 814,
3517
    BALIGN  = 815,
3518
    CMPGDU_EQ_QB  = 816,
3519
    CMPGDU_LE_QB  = 817,
3520
    CMPGDU_LT_QB  = 818,
3521
    DPA_W_PH  = 819,
3522
    DPAQX_SA_W_PH = 820,
3523
    DPAQX_S_W_PH  = 821,
3524
    DPAX_W_PH = 822,
3525
    DPS_W_PH  = 823,
3526
    DPSQX_S_W_PH  = 824,
3527
    DPSQX_SA_W_PH = 825,
3528
    DPSX_W_PH = 826,
3529
    MUL_PH  = 827,
3530
    MUL_S_PH  = 828,
3531
    MULQ_RS_W = 829,
3532
    MULQ_S_PH = 830,
3533
    MULQ_S_W  = 831,
3534
    MULSA_W_PH  = 832,
3535
    PRECR_QB_PH = 833,
3536
    PRECR_SRA_PH_W  = 834,
3537
    PRECR_SRA_R_PH_W  = 835,
3538
    PREPEND = 836,
3539
    SHRA_QB = 837,
3540
    SHRA_R_QB = 838,
3541
    SHRAV_QB  = 839,
3542
    SHRAV_R_QB  = 840,
3543
    SHRL_PH = 841,
3544
    SHRLV_PH  = 842,
3545
    SUBQH_PH  = 843,
3546
    SUBQH_R_PH  = 844,
3547
    SUBQH_W = 845,
3548
    SUBQH_R_W = 846,
3549
    SUBU_PH = 847,
3550
    SUBU_S_PH = 848,
3551
    SUBUH_QB  = 849,
3552
    SUBUH_R_QB  = 850,
3553
    ABSQ_S_PH_MM  = 851,
3554
    ABSQ_S_W_MM = 852,
3555
    ADDQ_PH_MM  = 853,
3556
    ADDQ_S_PH_MM  = 854,
3557
    ADDQ_S_W_MM = 855,
3558
    ADDSC_MM  = 856,
3559
    ADDU_QB_MM  = 857,
3560
    ADDU_S_QB_MM  = 858,
3561
    ADDWC_MM  = 859,
3562
    BITREV_MM = 860,
3563
    BPOSGE32_MM = 861,
3564
    CMPGU_EQ_QB_MM  = 862,
3565
    CMPGU_LE_QB_MM  = 863,
3566
    CMPGU_LT_QB_MM  = 864,
3567
    CMPU_EQ_QB_MM = 865,
3568
    CMPU_LE_QB_MM = 866,
3569
    CMPU_LT_QB_MM = 867,
3570
    CMP_EQ_PH_MM  = 868,
3571
    CMP_LE_PH_MM  = 869,
3572
    CMP_LT_PH_MM  = 870,
3573
    DPAQ_SA_L_W_MM  = 871,
3574
    DPAQ_S_W_PH_MM  = 872,
3575
    DPAU_H_QBL_MM = 873,
3576
    DPAU_H_QBR_MM = 874,
3577
    DPSQ_SA_L_W_MM  = 875,
3578
    DPSQ_S_W_PH_MM  = 876,
3579
    DPSU_H_QBL_MM = 877,
3580
    DPSU_H_QBR_MM = 878,
3581
    EXTPDPV_MM  = 879,
3582
    EXTPDP_MM = 880,
3583
    EXTPV_MM  = 881,
3584
    EXTP_MM = 882,
3585
    EXTRV_RS_W_MM = 883,
3586
    EXTRV_R_W_MM  = 884,
3587
    EXTRV_S_H_MM  = 885,
3588
    EXTRV_W_MM  = 886,
3589
    EXTR_RS_W_MM  = 887,
3590
    EXTR_R_W_MM = 888,
3591
    EXTR_S_H_MM = 889,
3592
    EXTR_W_MM = 890,
3593
    INSV_MM = 891,
3594
    LBUX_MM = 892,
3595
    LHX_MM  = 893,
3596
    LWX_MM  = 894,
3597
    MADDU_DSP_MM  = 895,
3598
    MADD_DSP_MM = 896,
3599
    MAQ_SA_W_PHL_MM = 897,
3600
    MAQ_SA_W_PHR_MM = 898,
3601
    MAQ_S_W_PHL_MM  = 899,
3602
    MAQ_S_W_PHR_MM  = 900,
3603
    MFHI_DSP_MM = 901,
3604
    MFLO_DSP_MM = 902,
3605
    MODSUB_MM = 903,
3606
    MOVEP_MM  = 904,
3607
    MOVEP_MMR6  = 905,
3608
    MOVN_I_MM = 906,
3609
    MOVZ_I_MM = 907,
3610
    MSUBU_DSP_MM  = 908,
3611
    MSUB_DSP_MM = 909,
3612
    MTHI_DSP_MM = 910,
3613
    MTHLIP_MM = 911,
3614
    MTLO_DSP_MM = 912,
3615
    MULEQ_S_W_PHL_MM  = 913,
3616
    MULEQ_S_W_PHR_MM  = 914,
3617
    MULEU_S_PH_QBL_MM = 915,
3618
    MULEU_S_PH_QBR_MM = 916,
3619
    MULQ_RS_PH_MM = 917,
3620
    MULSAQ_S_W_PH_MM  = 918,
3621
    MULTU_DSP_MM  = 919,
3622
    MULT_DSP_MM = 920,
3623
    PACKRL_PH_MM  = 921,
3624
    PICK_PH_MM  = 922,
3625
    PICK_QB_MM  = 923,
3626
    PRECEQU_PH_QBLA_MM  = 924,
3627
    PRECEQU_PH_QBL_MM = 925,
3628
    PRECEQU_PH_QBRA_MM  = 926,
3629
    PRECEQU_PH_QBR_MM = 927,
3630
    PRECEQ_W_PHL_MM = 928,
3631
    PRECEQ_W_PHR_MM = 929,
3632
    PRECEU_PH_QBLA_MM = 930,
3633
    PRECEU_PH_QBL_MM  = 931,
3634
    PRECEU_PH_QBRA_MM = 932,
3635
    PRECEU_PH_QBR_MM  = 933,
3636
    PRECRQU_S_QB_PH_MM  = 934,
3637
    PRECRQ_PH_W_MM  = 935,
3638
    PRECRQ_QB_PH_MM = 936,
3639
    PRECRQ_RS_PH_W_MM = 937,
3640
    RADDU_W_QB_MM = 938,
3641
    RDDSP_MM  = 939,
3642
    REPLV_PH_MM = 940,
3643
    REPLV_QB_MM = 941,
3644
    REPL_PH_MM  = 942,
3645
    REPL_QB_MM  = 943,
3646
    SHILOV_MM = 944,
3647
    SHILO_MM  = 945,
3648
    SHLLV_PH_MM = 946,
3649
    SHLLV_QB_MM = 947,
3650
    SHLLV_S_PH_MM = 948,
3651
    SHLLV_S_W_MM  = 949,
3652
    SHLL_PH_MM  = 950,
3653
    SHLL_QB_MM  = 951,
3654
    SHLL_S_PH_MM  = 952,
3655
    SHLL_S_W_MM = 953,
3656
    SHRAV_PH_MM = 954,
3657
    SHRAV_R_PH_MM = 955,
3658
    SHRAV_R_W_MM  = 956,
3659
    SHRA_PH_MM  = 957,
3660
    SHRA_R_PH_MM  = 958,
3661
    SHRA_R_W_MM = 959,
3662
    SHRLV_QB_MM = 960,
3663
    SHRL_QB_MM  = 961,
3664
    SUBQ_PH_MM  = 962,
3665
    SUBQ_S_PH_MM  = 963,
3666
    SUBQ_S_W_MM = 964,
3667
    SUBU_QB_MM  = 965,
3668
    SUBU_S_QB_MM  = 966,
3669
    WRDSP_MM  = 967,
3670
    ABSQ_S_QB_MMR2  = 968,
3671
    ADDQH_PH_MMR2 = 969,
3672
    ADDQH_R_PH_MMR2 = 970,
3673
    ADDQH_R_W_MMR2  = 971,
3674
    ADDQH_W_MMR2  = 972,
3675
    ADDUH_QB_MMR2 = 973,
3676
    ADDUH_R_QB_MMR2 = 974,
3677
    ADDU_PH_MMR2  = 975,
3678
    ADDU_S_PH_MMR2  = 976,
3679
    APPEND_MMR2 = 977,
3680
    BALIGN_MMR2 = 978,
3681
    CMPGDU_EQ_QB_MMR2 = 979,
3682
    CMPGDU_LE_QB_MMR2 = 980,
3683
    CMPGDU_LT_QB_MMR2 = 981,
3684
    DPA_W_PH_MMR2 = 982,
3685
    DPAQX_SA_W_PH_MMR2  = 983,
3686
    DPAQX_S_W_PH_MMR2 = 984,
3687
    DPAX_W_PH_MMR2  = 985,
3688
    DPS_W_PH_MMR2 = 986,
3689
    DPSQX_S_W_PH_MMR2 = 987,
3690
    DPSQX_SA_W_PH_MMR2  = 988,
3691
    DPSX_W_PH_MMR2  = 989,
3692
    MUL_PH_MMR2 = 990,
3693
    MUL_S_PH_MMR2 = 991,
3694
    MULQ_RS_W_MMR2  = 992,
3695
    MULQ_S_PH_MMR2  = 993,
3696
    MULQ_S_W_MMR2 = 994,
3697
    MULSA_W_PH_MMR2 = 995,
3698
    PRECR_QB_PH_MMR2  = 996,
3699
    PRECR_SRA_PH_W_MMR2 = 997,
3700
    PRECR_SRA_R_PH_W_MMR2 = 998,
3701
    PREPEND_MMR2  = 999,
3702
    SHRA_QB_MMR2  = 1000,
3703
    SHRA_R_QB_MMR2  = 1001,
3704
    SHRAV_QB_MMR2 = 1002,
3705
    SHRAV_R_QB_MMR2 = 1003,
3706
    SHRL_PH_MMR2  = 1004,
3707
    SHRLV_PH_MMR2 = 1005,
3708
    SUBQH_PH_MMR2 = 1006,
3709
    SUBQH_R_PH_MMR2 = 1007,
3710
    SUBQH_W_MMR2  = 1008,
3711
    SUBQH_R_W_MMR2  = 1009,
3712
    SUBU_PH_MMR2  = 1010,
3713
    SUBU_S_PH_MMR2  = 1011,
3714
    SUBUH_QB_MMR2 = 1012,
3715
    SUBUH_R_QB_MMR2 = 1013,
3716
    BPOSGE32C_MMR3  = 1014,
3717
    SCHED_LIST_END = 1015
3718
  };
3719
} // end Sched namespace
3720
} // end Mips namespace
3721
} // end llvm namespace
3722
#endif // GET_INSTRINFO_SCHED_ENUM
3723
3724
#ifdef GET_INSTRINFO_MC_DESC
3725
#undef GET_INSTRINFO_MC_DESC
3726
namespace llvm {
3727
3728
static const MCPhysReg ImplicitList1[] = { Mips::SP, 0 };
3729
static const MCPhysReg ImplicitList2[] = { Mips::AT, 0 };
3730
static const MCPhysReg ImplicitList3[] = { Mips::RA, 0 };
3731
static const MCPhysReg ImplicitList4[] = { Mips::DSPPos, 0 };
3732
static const MCPhysReg ImplicitList5[] = { Mips::V0, Mips::V1, 0 };
3733
static const MCPhysReg ImplicitList6[] = { Mips::HI0, Mips::LO0, 0 };
3734
static const MCPhysReg ImplicitList7[] = { Mips::T8, 0 };
3735
static const MCPhysReg ImplicitList8[] = { Mips::DSPOutFlag20, 0 };
3736
static const MCPhysReg ImplicitList9[] = { Mips::DSPCarry, 0 };
3737
static const MCPhysReg ImplicitList10[] = { Mips::DSPCCond, 0 };
3738
static const MCPhysReg ImplicitList11[] = { Mips::HI0, Mips::LO0, Mips::P0, Mips::P1, Mips::P2, 0 };
3739
static const MCPhysReg ImplicitList12[] = { Mips::HI0_64, Mips::LO0_64, 0 };
3740
static const MCPhysReg ImplicitList13[] = { Mips::DSPOutFlag16_19, 0 };
3741
static const MCPhysReg ImplicitList14[] = { Mips::DSPEFI, 0 };
3742
static const MCPhysReg ImplicitList15[] = { Mips::DSPPos, Mips::DSPEFI, 0 };
3743
static const MCPhysReg ImplicitList16[] = { Mips::DSPOutFlag23, 0 };
3744
static const MCPhysReg ImplicitList17[] = { Mips::FCC0, 0 };
3745
static const MCPhysReg ImplicitList18[] = { Mips::DSPPos, Mips::DSPSCount, 0 };
3746
static const MCPhysReg ImplicitList19[] = { Mips::AC0, 0 };
3747
static const MCPhysReg ImplicitList20[] = { Mips::AC0_64, 0 };
3748
static const MCPhysReg ImplicitList21[] = { Mips::HI0, 0 };
3749
static const MCPhysReg ImplicitList22[] = { Mips::HI0_64, 0 };
3750
static const MCPhysReg ImplicitList23[] = { Mips::LO0, 0 };
3751
static const MCPhysReg ImplicitList24[] = { Mips::LO0_64, 0 };
3752
static const MCPhysReg ImplicitList25[] = { Mips::MPL0, Mips::P0, Mips::P1, Mips::P2, 0 };
3753
static const MCPhysReg ImplicitList26[] = { Mips::MPL1, Mips::P0, Mips::P1, Mips::P2, 0 };
3754
static const MCPhysReg ImplicitList27[] = { Mips::MPL2, Mips::P0, Mips::P1, Mips::P2, 0 };
3755
static const MCPhysReg ImplicitList28[] = { Mips::P0, 0 };
3756
static const MCPhysReg ImplicitList29[] = { Mips::P1, 0 };
3757
static const MCPhysReg ImplicitList30[] = { Mips::P2, 0 };
3758
static const MCPhysReg ImplicitList31[] = { Mips::DSPOutFlag21, 0 };
3759
static const MCPhysReg ImplicitList32[] = { Mips::DSPOutFlag22, 0 };
3760
static const MCPhysReg ImplicitList33[] = { Mips::P0, Mips::P1, Mips::P2, 0 };
3761
static const MCPhysReg ImplicitList34[] = { Mips::MPL1, Mips::MPL2, Mips::P0, Mips::P1, Mips::P2, 0 };
3762
3763
static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3764
static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3765
static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3766
static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3767
static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3768
static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3769
static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3770
static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3771
static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
3772
static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3773
static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3774
static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3775
static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3776
static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3777
static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3778
static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
3779
static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3780
static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3781
static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3782
static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3783
static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3784
static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
3785
static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
3786
static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
3787
static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3788
static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3789
static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
3790
static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
3791
static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
3792
static const MCOperandInfo OperandInfo31[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3793
static const MCOperandInfo OperandInfo32[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3794
static const MCOperandInfo OperandInfo33[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3795
static const MCOperandInfo OperandInfo34[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3796
static const MCOperandInfo OperandInfo35[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3797
static const MCOperandInfo OperandInfo36[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3798
static const MCOperandInfo OperandInfo37[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3799
static const MCOperandInfo OperandInfo38[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3800
static const MCOperandInfo OperandInfo39[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3801
static const MCOperandInfo OperandInfo40[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3802
static const MCOperandInfo OperandInfo41[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3803
static const MCOperandInfo OperandInfo42[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3804
static const MCOperandInfo OperandInfo43[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3805
static const MCOperandInfo OperandInfo44[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3806
static const MCOperandInfo OperandInfo45[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3807
static const MCOperandInfo OperandInfo46[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3808
static const MCOperandInfo OperandInfo47[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3809
static const MCOperandInfo OperandInfo48[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3810
static const MCOperandInfo OperandInfo49[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3811
static const MCOperandInfo OperandInfo50[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3812
static const MCOperandInfo OperandInfo51[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3813
static const MCOperandInfo OperandInfo52[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3814
static const MCOperandInfo OperandInfo53[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3815
static const MCOperandInfo OperandInfo54[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3816
static const MCOperandInfo OperandInfo55[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3817
static const MCOperandInfo OperandInfo56[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3818
static const MCOperandInfo OperandInfo57[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3819
static const MCOperandInfo OperandInfo58[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3820
static const MCOperandInfo OperandInfo59[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3821
static const MCOperandInfo OperandInfo60[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3822
static const MCOperandInfo OperandInfo61[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3823
static const MCOperandInfo OperandInfo62[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3824
static const MCOperandInfo OperandInfo63[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3825
static const MCOperandInfo OperandInfo64[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3826
static const MCOperandInfo OperandInfo65[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3827
static const MCOperandInfo OperandInfo66[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3828
static const MCOperandInfo OperandInfo67[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3829
static const MCOperandInfo OperandInfo68[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3830
static const MCOperandInfo OperandInfo69[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3831
static const MCOperandInfo OperandInfo70[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3832
static const MCOperandInfo OperandInfo71[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3833
static const MCOperandInfo OperandInfo72[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3834
static const MCOperandInfo OperandInfo73[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3835
static const MCOperandInfo OperandInfo74[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3836
static const MCOperandInfo OperandInfo75[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3837
static const MCOperandInfo OperandInfo76[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3838
static const MCOperandInfo OperandInfo77[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3839
static const MCOperandInfo OperandInfo78[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3840
static const MCOperandInfo OperandInfo79[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3841
static const MCOperandInfo OperandInfo80[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3842
static const MCOperandInfo OperandInfo81[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3843
static const MCOperandInfo OperandInfo82[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3844
static const MCOperandInfo OperandInfo83[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3845
static const MCOperandInfo OperandInfo84[] = { { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3846
static const MCOperandInfo OperandInfo85[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3847
static const MCOperandInfo OperandInfo86[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3848
static const MCOperandInfo OperandInfo87[] = { { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3849
static const MCOperandInfo OperandInfo88[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3850
static const MCOperandInfo OperandInfo89[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3851
static const MCOperandInfo OperandInfo90[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3852
static const MCOperandInfo OperandInfo91[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3853
static const MCOperandInfo OperandInfo92[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3854
static const MCOperandInfo OperandInfo93[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3855
static const MCOperandInfo OperandInfo94[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3856
static const MCOperandInfo OperandInfo95[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3857
static const MCOperandInfo OperandInfo96[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3858
static const MCOperandInfo OperandInfo97[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3859
static const MCOperandInfo OperandInfo98[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3860
static const MCOperandInfo OperandInfo99[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3861
static const MCOperandInfo OperandInfo100[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3862
static const MCOperandInfo OperandInfo101[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3863
static const MCOperandInfo OperandInfo102[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3864
static const MCOperandInfo OperandInfo103[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3865
static const MCOperandInfo OperandInfo104[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3866
static const MCOperandInfo OperandInfo105[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3867
static const MCOperandInfo OperandInfo106[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3868
static const MCOperandInfo OperandInfo107[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3869
static const MCOperandInfo OperandInfo108[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3870
static const MCOperandInfo OperandInfo109[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3871
static const MCOperandInfo OperandInfo110[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3872
static const MCOperandInfo OperandInfo111[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3873
static const MCOperandInfo OperandInfo112[] = { { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3874
static const MCOperandInfo OperandInfo113[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3875
static const MCOperandInfo OperandInfo114[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3876
static const MCOperandInfo OperandInfo115[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3877
static const MCOperandInfo OperandInfo116[] = { { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3878
static const MCOperandInfo OperandInfo117[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3879
static const MCOperandInfo OperandInfo118[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3880
static const MCOperandInfo OperandInfo119[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3881
static const MCOperandInfo OperandInfo120[] = { { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3882
static const MCOperandInfo OperandInfo121[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3883
static const MCOperandInfo OperandInfo122[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3884
static const MCOperandInfo OperandInfo123[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
3885
static const MCOperandInfo OperandInfo124[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3886
static const MCOperandInfo OperandInfo125[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3887
static const MCOperandInfo OperandInfo126[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3888
static const MCOperandInfo OperandInfo127[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3889
static const MCOperandInfo OperandInfo128[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3890
static const MCOperandInfo OperandInfo129[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3891
static const MCOperandInfo OperandInfo130[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3892
static const MCOperandInfo OperandInfo131[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3893
static const MCOperandInfo OperandInfo132[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3894
static const MCOperandInfo OperandInfo133[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3895
static const MCOperandInfo OperandInfo134[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3896
static const MCOperandInfo OperandInfo135[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3897
static const MCOperandInfo OperandInfo136[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3898
static const MCOperandInfo OperandInfo137[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3899
static const MCOperandInfo OperandInfo138[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3900
static const MCOperandInfo OperandInfo139[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3901
static const MCOperandInfo OperandInfo140[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3902
static const MCOperandInfo OperandInfo141[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3903
static const MCOperandInfo OperandInfo142[] = { { Mips::GPR32NONZERORegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3904
static const MCOperandInfo OperandInfo143[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3905
static const MCOperandInfo OperandInfo144[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3906
static const MCOperandInfo OperandInfo145[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3907
static const MCOperandInfo OperandInfo146[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3908
static const MCOperandInfo OperandInfo147[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3909
static const MCOperandInfo OperandInfo148[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3910
static const MCOperandInfo OperandInfo149[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3911
static const MCOperandInfo OperandInfo150[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3912
static const MCOperandInfo OperandInfo151[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3913
static const MCOperandInfo OperandInfo152[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3914
static const MCOperandInfo OperandInfo153[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3915
static const MCOperandInfo OperandInfo154[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3916
static const MCOperandInfo OperandInfo155[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3917
static const MCOperandInfo OperandInfo156[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3918
static const MCOperandInfo OperandInfo157[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3919
static const MCOperandInfo OperandInfo158[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3920
static const MCOperandInfo OperandInfo159[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3921
static const MCOperandInfo OperandInfo160[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3922
static const MCOperandInfo OperandInfo161[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3923
static const MCOperandInfo OperandInfo162[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3924
static const MCOperandInfo OperandInfo163[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
3925
static const MCOperandInfo OperandInfo164[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
3926
static const MCOperandInfo OperandInfo165[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3927
static const MCOperandInfo OperandInfo166[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3928
static const MCOperandInfo OperandInfo167[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsPlusSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3929
static const MCOperandInfo OperandInfo168[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3930
static const MCOperandInfo OperandInfo169[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3931
static const MCOperandInfo OperandInfo170[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3932
static const MCOperandInfo OperandInfo171[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3933
static const MCOperandInfo OperandInfo172[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3934
static const MCOperandInfo OperandInfo173[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3935
static const MCOperandInfo OperandInfo174[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3936
static const MCOperandInfo OperandInfo175[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3937
static const MCOperandInfo OperandInfo176[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3938
static const MCOperandInfo OperandInfo177[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3939
static const MCOperandInfo OperandInfo178[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3940
static const MCOperandInfo OperandInfo179[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3941
static const MCOperandInfo OperandInfo180[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3942
static const MCOperandInfo OperandInfo181[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3943
static const MCOperandInfo OperandInfo182[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3944
static const MCOperandInfo OperandInfo183[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3945
static const MCOperandInfo OperandInfo184[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3946
static const MCOperandInfo OperandInfo185[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3947
static const MCOperandInfo OperandInfo186[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3948
static const MCOperandInfo OperandInfo187[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3949
static const MCOperandInfo OperandInfo188[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3950
static const MCOperandInfo OperandInfo189[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3951
static const MCOperandInfo OperandInfo190[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3952
static const MCOperandInfo OperandInfo191[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3953
static const MCOperandInfo OperandInfo192[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3954
static const MCOperandInfo OperandInfo193[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3955
static const MCOperandInfo OperandInfo194[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3956
static const MCOperandInfo OperandInfo195[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3957
static const MCOperandInfo OperandInfo196[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3958
static const MCOperandInfo OperandInfo197[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3959
static const MCOperandInfo OperandInfo198[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3960
static const MCOperandInfo OperandInfo199[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3961
static const MCOperandInfo OperandInfo200[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3962
static const MCOperandInfo OperandInfo201[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3963
static const MCOperandInfo OperandInfo202[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3964
static const MCOperandInfo OperandInfo203[] = { { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3965
static const MCOperandInfo OperandInfo204[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3966
static const MCOperandInfo OperandInfo205[] = { { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3967
static const MCOperandInfo OperandInfo206[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3968
static const MCOperandInfo OperandInfo207[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3969
static const MCOperandInfo OperandInfo208[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3970
static const MCOperandInfo OperandInfo209[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3971
static const MCOperandInfo OperandInfo210[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3972
static const MCOperandInfo OperandInfo211[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3973
static const MCOperandInfo OperandInfo212[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3974
static const MCOperandInfo OperandInfo213[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
3975
static const MCOperandInfo OperandInfo214[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3976
static const MCOperandInfo OperandInfo215[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3977
static const MCOperandInfo OperandInfo216[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3978
static const MCOperandInfo OperandInfo217[] = { { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3979
static const MCOperandInfo OperandInfo218[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3980
static const MCOperandInfo OperandInfo219[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3981
static const MCOperandInfo OperandInfo220[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3982
static const MCOperandInfo OperandInfo221[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3983
static const MCOperandInfo OperandInfo222[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3984
static const MCOperandInfo OperandInfo223[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3985
static const MCOperandInfo OperandInfo224[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3986
static const MCOperandInfo OperandInfo225[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
3987
static const MCOperandInfo OperandInfo226[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3988
static const MCOperandInfo OperandInfo227[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3989
static const MCOperandInfo OperandInfo228[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3990
static const MCOperandInfo OperandInfo229[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3991
static const MCOperandInfo OperandInfo230[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3992
static const MCOperandInfo OperandInfo231[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3993
static const MCOperandInfo OperandInfo232[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3994
static const MCOperandInfo OperandInfo233[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3995
static const MCOperandInfo OperandInfo234[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3996
static const MCOperandInfo OperandInfo235[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3997
static const MCOperandInfo OperandInfo236[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3998
static const MCOperandInfo OperandInfo237[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3999
static const MCOperandInfo OperandInfo238[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4000
static const MCOperandInfo OperandInfo239[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4001
static const MCOperandInfo OperandInfo240[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4002
static const MCOperandInfo OperandInfo241[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4003
static const MCOperandInfo OperandInfo242[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4004
static const MCOperandInfo OperandInfo243[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4005
static const MCOperandInfo OperandInfo244[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4006
static const MCOperandInfo OperandInfo245[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4007
static const MCOperandInfo OperandInfo246[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4008
static const MCOperandInfo OperandInfo247[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4009
static const MCOperandInfo OperandInfo248[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4010
static const MCOperandInfo OperandInfo249[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4011
static const MCOperandInfo OperandInfo250[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4012
static const MCOperandInfo OperandInfo251[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4013
static const MCOperandInfo OperandInfo252[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4014
static const MCOperandInfo OperandInfo253[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4015
static const MCOperandInfo OperandInfo254[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4016
static const MCOperandInfo OperandInfo255[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4017
static const MCOperandInfo OperandInfo256[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4018
static const MCOperandInfo OperandInfo257[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
4019
static const MCOperandInfo OperandInfo258[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4020
static const MCOperandInfo OperandInfo259[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4021
static const MCOperandInfo OperandInfo260[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4022
static const MCOperandInfo OperandInfo261[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4023
static const MCOperandInfo OperandInfo262[] = { { Mips::COP3RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4024
static const MCOperandInfo OperandInfo263[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4025
static const MCOperandInfo OperandInfo264[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4026
static const MCOperandInfo OperandInfo265[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4027
static const MCOperandInfo OperandInfo266[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4028
static const MCOperandInfo OperandInfo267[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4029
static const MCOperandInfo OperandInfo268[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
4030
static const MCOperandInfo OperandInfo269[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
4031
static const MCOperandInfo OperandInfo270[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4032
static const MCOperandInfo OperandInfo271[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4033
static const MCOperandInfo OperandInfo272[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4034
static const MCOperandInfo OperandInfo273[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4035
static const MCOperandInfo OperandInfo274[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4036
static const MCOperandInfo OperandInfo275[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4037
static const MCOperandInfo OperandInfo276[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 3, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4038
static const MCOperandInfo OperandInfo277[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4039
static const MCOperandInfo OperandInfo278[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 2, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4040
static const MCOperandInfo OperandInfo279[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4041
static const MCOperandInfo OperandInfo280[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 2, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4042
static const MCOperandInfo OperandInfo281[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
4043
static const MCOperandInfo OperandInfo282[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4044
static const MCOperandInfo OperandInfo283[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4045
static const MCOperandInfo OperandInfo284[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4046
static const MCOperandInfo OperandInfo285[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4047
static const MCOperandInfo OperandInfo286[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4048
static const MCOperandInfo OperandInfo287[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4049
static const MCOperandInfo OperandInfo288[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4050
static const MCOperandInfo OperandInfo289[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4051
static const MCOperandInfo OperandInfo290[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4052
static const MCOperandInfo OperandInfo291[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4053
static const MCOperandInfo OperandInfo292[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4054
static const MCOperandInfo OperandInfo293[] = { { Mips::GPRMM16MovePPairFirstRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePPairSecondRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4055
static const MCOperandInfo OperandInfo294[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4056
static const MCOperandInfo OperandInfo295[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4057
static const MCOperandInfo OperandInfo296[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4058
static const MCOperandInfo OperandInfo297[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4059
static const MCOperandInfo OperandInfo298[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4060
static const MCOperandInfo OperandInfo299[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4061
static const MCOperandInfo OperandInfo300[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4062
static const MCOperandInfo OperandInfo301[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4063
static const MCOperandInfo OperandInfo302[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4064
static const MCOperandInfo OperandInfo303[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4065
static const MCOperandInfo OperandInfo304[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4066
static const MCOperandInfo OperandInfo305[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4067
static const MCOperandInfo OperandInfo306[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4068
static const MCOperandInfo OperandInfo307[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4069
static const MCOperandInfo OperandInfo308[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4070
static const MCOperandInfo OperandInfo309[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4071
static const MCOperandInfo OperandInfo310[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4072
static const MCOperandInfo OperandInfo311[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4073
static const MCOperandInfo OperandInfo312[] = { { Mips::HI32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4074
static const MCOperandInfo OperandInfo313[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4075
static const MCOperandInfo OperandInfo314[] = { { Mips::LO32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4076
static const MCOperandInfo OperandInfo315[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4077
static const MCOperandInfo OperandInfo316[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4078
static const MCOperandInfo OperandInfo317[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4079
static const MCOperandInfo OperandInfo318[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4080
static const MCOperandInfo OperandInfo319[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4081
static const MCOperandInfo OperandInfo320[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4082
static const MCOperandInfo OperandInfo321[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4083
static const MCOperandInfo OperandInfo322[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4084
static const MCOperandInfo OperandInfo323[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4085
static const MCOperandInfo OperandInfo324[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4086
static const MCOperandInfo OperandInfo325[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4087
static const MCOperandInfo OperandInfo326[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4088
static const MCOperandInfo OperandInfo327[] = { { Mips::GPRMM16ZeroRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4089
static const MCOperandInfo OperandInfo328[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4090
static const MCOperandInfo OperandInfo329[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4091
static const MCOperandInfo OperandInfo330[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4092
static const MCOperandInfo OperandInfo331[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4093
static const MCOperandInfo OperandInfo332[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4094
static const MCOperandInfo OperandInfo333[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4095
static const MCOperandInfo OperandInfo334[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4096
static const MCOperandInfo OperandInfo335[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4097
static const MCOperandInfo OperandInfo336[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4098
static const MCOperandInfo OperandInfo337[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4099
static const MCOperandInfo OperandInfo338[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4100
static const MCOperandInfo OperandInfo339[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4101
static const MCOperandInfo OperandInfo340[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4102
static const MCOperandInfo OperandInfo341[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4103
static const MCOperandInfo OperandInfo342[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4104
static const MCOperandInfo OperandInfo343[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4105
static const MCOperandInfo OperandInfo344[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4106
static const MCOperandInfo OperandInfo345[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4107
4108
extern const MCInstrDesc MipsInsts[] = {
4109
  { 0,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
4110
  { 1,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
4111
  { 2,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2 = INLINEASM_BR
4112
  { 3,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = CFI_INSTRUCTION
4113
  { 4,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = EH_LABEL
4114
  { 5,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = GC_LABEL
4115
  { 6,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #6 = ANNOTATION_LABEL
4116
  { 7,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #7 = KILL
4117
  { 8,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #8 = EXTRACT_SUBREG
4118
  { 9,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #9 = INSERT_SUBREG
4119
  { 10, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #10 = IMPLICIT_DEF
4120
  { 11, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #11 = SUBREG_TO_REG
4121
  { 12, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #12 = COPY_TO_REGCLASS
4122
  { 13, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #13 = DBG_VALUE
4123
  { 14, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #14 = DBG_LABEL
4124
  { 15, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #15 = REG_SEQUENCE
4125
  { 16, 2,  1,  0,  496,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #16 = COPY
4126
  { 17, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #17 = BUNDLE
4127
  { 18, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #18 = LIFETIME_START
4128
  { 19, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #19 = LIFETIME_END
4129
  { 20, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #20 = STACKMAP
4130
  { 21, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #21 = FENTRY_CALL
4131
  { 22, 6,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #22 = PATCHPOINT
4132
  { 23, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #23 = LOAD_STACK_GUARD
4133
  { 24, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #24 = STATEPOINT
4134
  { 25, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #25 = LOCAL_ESCAPE
4135
  { 26, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #26 = FAULTING_OP
4136
  { 27, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #27 = PATCHABLE_OP
4137
  { 28, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #28 = PATCHABLE_FUNCTION_ENTER
4138
  { 29, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #29 = PATCHABLE_RET
4139
  { 30, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #30 = PATCHABLE_FUNCTION_EXIT
4140
  { 31, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #31 = PATCHABLE_TAIL_CALL
4141
  { 32, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #32 = PATCHABLE_EVENT_CALL
4142
  { 33, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
4143
  { 34, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #34 = ICALL_BRANCH_FUNNEL
4144
  { 35, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #35 = G_ADD
4145
  { 36, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #36 = G_SUB
4146
  { 37, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #37 = G_MUL
4147
  { 38, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #38 = G_SDIV
4148
  { 39, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #39 = G_UDIV
4149
  { 40, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #40 = G_SREM
4150
  { 41, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_UREM
4151
  { 42, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_AND
4152
  { 43, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #43 = G_OR
4153
  { 44, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #44 = G_XOR
4154
  { 45, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #45 = G_IMPLICIT_DEF
4155
  { 46, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #46 = G_PHI
4156
  { 47, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #47 = G_FRAME_INDEX
4157
  { 48, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #48 = G_GLOBAL_VALUE
4158
  { 49, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #49 = G_EXTRACT
4159
  { 50, 2,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #50 = G_UNMERGE_VALUES
4160
  { 51, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #51 = G_INSERT
4161
  { 52, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #52 = G_MERGE_VALUES
4162
  { 53, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = G_BUILD_VECTOR
4163
  { 54, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #54 = G_BUILD_VECTOR_TRUNC
4164
  { 55, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #55 = G_CONCAT_VECTORS
4165
  { 56, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #56 = G_PTRTOINT
4166
  { 57, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #57 = G_INTTOPTR
4167
  { 58, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #58 = G_BITCAST
4168
  { 59, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #59 = G_INTRINSIC_TRUNC
4169
  { 60, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #60 = G_INTRINSIC_ROUND
4170
  { 61, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #61 = G_LOAD
4171
  { 62, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #62 = G_SEXTLOAD
4172
  { 63, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #63 = G_ZEXTLOAD
4173
  { 64, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #64 = G_STORE
4174
  { 65, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #65 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
4175
  { 66, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #66 = G_ATOMIC_CMPXCHG
4176
  { 67, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #67 = G_ATOMICRMW_XCHG
4177
  { 68, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #68 = G_ATOMICRMW_ADD
4178
  { 69, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #69 = G_ATOMICRMW_SUB
4179
  { 70, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #70 = G_ATOMICRMW_AND
4180
  { 71, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #71 = G_ATOMICRMW_NAND
4181
  { 72, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #72 = G_ATOMICRMW_OR
4182
  { 73, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #73 = G_ATOMICRMW_XOR
4183
  { 74, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #74 = G_ATOMICRMW_MAX
4184
  { 75, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #75 = G_ATOMICRMW_MIN
4185
  { 76, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #76 = G_ATOMICRMW_UMAX
4186
  { 77, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #77 = G_ATOMICRMW_UMIN
4187
  { 78, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #78 = G_BRCOND
4188
  { 79, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #79 = G_BRINDIRECT
4189
  { 80, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #80 = G_INTRINSIC
4190
  { 81, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #81 = G_INTRINSIC_W_SIDE_EFFECTS
4191
  { 82, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #82 = G_ANYEXT
4192
  { 83, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #83 = G_TRUNC
4193
  { 84, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #84 = G_CONSTANT
4194
  { 85, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #85 = G_FCONSTANT
4195
  { 86, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #86 = G_VASTART
4196
  { 87, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #87 = G_VAARG
4197
  { 88, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #88 = G_SEXT
4198
  { 89, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #89 = G_ZEXT
4199
  { 90, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #90 = G_SHL
4200
  { 91, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #91 = G_LSHR
4201
  { 92, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #92 = G_ASHR
4202
  { 93, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #93 = G_ICMP
4203
  { 94, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #94 = G_FCMP
4204
  { 95, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #95 = G_SELECT
4205
  { 96, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #96 = G_UADDO
4206
  { 97, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #97 = G_UADDE
4207
  { 98, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #98 = G_USUBO
4208
  { 99, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #99 = G_USUBE
4209
  { 100,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #100 = G_SADDO
4210
  { 101,  5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #101 = G_SADDE
4211
  { 102,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #102 = G_SSUBO
4212
  { 103,  5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #103 = G_SSUBE
4213
  { 104,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #104 = G_UMULO
4214
  { 105,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #105 = G_SMULO
4215
  { 106,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #106 = G_UMULH
4216
  { 107,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #107 = G_SMULH
4217
  { 108,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #108 = G_FADD
4218
  { 109,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #109 = G_FSUB
4219
  { 110,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #110 = G_FMUL
4220
  { 111,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #111 = G_FMA
4221
  { 112,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #112 = G_FDIV
4222
  { 113,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #113 = G_FREM
4223
  { 114,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #114 = G_FPOW
4224
  { 115,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #115 = G_FEXP
4225
  { 116,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #116 = G_FEXP2
4226
  { 117,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #117 = G_FLOG
4227
  { 118,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #118 = G_FLOG2
4228
  { 119,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #119 = G_FLOG10
4229
  { 120,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #120 = G_FNEG
4230
  { 121,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #121 = G_FPEXT
4231
  { 122,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #122 = G_FPTRUNC
4232
  { 123,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #123 = G_FPTOSI
4233
  { 124,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #124 = G_FPTOUI
4234
  { 125,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #125 = G_SITOFP
4235
  { 126,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #126 = G_UITOFP
4236
  { 127,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #127 = G_FABS
4237
  { 128,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #128 = G_FCANONICALIZE
4238
  { 129,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #129 = G_GEP
4239
  { 130,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #130 = G_PTR_MASK
4240
  { 131,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #131 = G_BR
4241
  { 132,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #132 = G_INSERT_VECTOR_ELT
4242
  { 133,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #133 = G_EXTRACT_VECTOR_ELT
4243
  { 134,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #134 = G_SHUFFLE_VECTOR
4244
  { 135,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #135 = G_CTTZ
4245
  { 136,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #136 = G_CTTZ_ZERO_UNDEF
4246
  { 137,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #137 = G_CTLZ
4247
  { 138,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #138 = G_CTLZ_ZERO_UNDEF
4248
  { 139,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #139 = G_CTPOP
4249
  { 140,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #140 = G_BSWAP
4250
  { 141,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #141 = G_FCEIL
4251
  { 142,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #142 = G_FCOS
4252
  { 143,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #143 = G_FSIN
4253
  { 144,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #144 = G_FSQRT
4254
  { 145,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #145 = G_FFLOOR
4255
  { 146,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #146 = G_ADDRSPACE_CAST
4256
  { 147,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #147 = G_BLOCK_ADDR
4257
  { 148,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #148 = ABSMacro
4258
  { 149,  2,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr },  // Inst #149 = ADJCALLSTACKDOWN
4259
  { 150,  2,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr },  // Inst #150 = ADJCALLSTACKUP
4260
  { 151,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #151 = AND_V_D_PSEUDO
4261
  { 152,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #152 = AND_V_H_PSEUDO
4262
  { 153,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #153 = AND_V_W_PSEUDO
4263
  { 154,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #154 = ATOMIC_CMP_SWAP_I16
4264
  { 155,  7,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #155 = ATOMIC_CMP_SWAP_I16_POSTRA
4265
  { 156,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #156 = ATOMIC_CMP_SWAP_I32
4266
  { 157,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #157 = ATOMIC_CMP_SWAP_I32_POSTRA
4267
  { 158,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #158 = ATOMIC_CMP_SWAP_I64
4268
  { 159,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #159 = ATOMIC_CMP_SWAP_I64_POSTRA
4269
  { 160,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #160 = ATOMIC_CMP_SWAP_I8
4270
  { 161,  7,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #161 = ATOMIC_CMP_SWAP_I8_POSTRA
4271
  { 162,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #162 = ATOMIC_LOAD_ADD_I16
4272
  { 163,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #163 = ATOMIC_LOAD_ADD_I16_POSTRA
4273
  { 164,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #164 = ATOMIC_LOAD_ADD_I32
4274
  { 165,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #165 = ATOMIC_LOAD_ADD_I32_POSTRA
4275
  { 166,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #166 = ATOMIC_LOAD_ADD_I64
4276
  { 167,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #167 = ATOMIC_LOAD_ADD_I64_POSTRA
4277
  { 168,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #168 = ATOMIC_LOAD_ADD_I8
4278
  { 169,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #169 = ATOMIC_LOAD_ADD_I8_POSTRA
4279
  { 170,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #170 = ATOMIC_LOAD_AND_I16
4280
  { 171,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #171 = ATOMIC_LOAD_AND_I16_POSTRA
4281
  { 172,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #172 = ATOMIC_LOAD_AND_I32
4282
  { 173,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #173 = ATOMIC_LOAD_AND_I32_POSTRA
4283
  { 174,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #174 = ATOMIC_LOAD_AND_I64
4284
  { 175,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #175 = ATOMIC_LOAD_AND_I64_POSTRA
4285
  { 176,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #176 = ATOMIC_LOAD_AND_I8
4286
  { 177,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #177 = ATOMIC_LOAD_AND_I8_POSTRA
4287
  { 178,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #178 = ATOMIC_LOAD_NAND_I16
4288
  { 179,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #179 = ATOMIC_LOAD_NAND_I16_POSTRA
4289
  { 180,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #180 = ATOMIC_LOAD_NAND_I32
4290
  { 181,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #181 = ATOMIC_LOAD_NAND_I32_POSTRA
4291
  { 182,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #182 = ATOMIC_LOAD_NAND_I64
4292
  { 183,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #183 = ATOMIC_LOAD_NAND_I64_POSTRA
4293
  { 184,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #184 = ATOMIC_LOAD_NAND_I8
4294
  { 185,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #185 = ATOMIC_LOAD_NAND_I8_POSTRA
4295
  { 186,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #186 = ATOMIC_LOAD_OR_I16
4296
  { 187,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #187 = ATOMIC_LOAD_OR_I16_POSTRA
4297
  { 188,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #188 = ATOMIC_LOAD_OR_I32
4298
  { 189,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #189 = ATOMIC_LOAD_OR_I32_POSTRA
4299
  { 190,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #190 = ATOMIC_LOAD_OR_I64
4300
  { 191,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #191 = ATOMIC_LOAD_OR_I64_POSTRA
4301
  { 192,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #192 = ATOMIC_LOAD_OR_I8
4302
  { 193,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #193 = ATOMIC_LOAD_OR_I8_POSTRA
4303
  { 194,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #194 = ATOMIC_LOAD_SUB_I16
4304
  { 195,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #195 = ATOMIC_LOAD_SUB_I16_POSTRA
4305
  { 196,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #196 = ATOMIC_LOAD_SUB_I32
4306
  { 197,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #197 = ATOMIC_LOAD_SUB_I32_POSTRA
4307
  { 198,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #198 = ATOMIC_LOAD_SUB_I64
4308
  { 199,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #199 = ATOMIC_LOAD_SUB_I64_POSTRA
4309
  { 200,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #200 = ATOMIC_LOAD_SUB_I8
4310
  { 201,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #201 = ATOMIC_LOAD_SUB_I8_POSTRA
4311
  { 202,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #202 = ATOMIC_LOAD_XOR_I16
4312
  { 203,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #203 = ATOMIC_LOAD_XOR_I16_POSTRA
4313
  { 204,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #204 = ATOMIC_LOAD_XOR_I32
4314
  { 205,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #205 = ATOMIC_LOAD_XOR_I32_POSTRA
4315
  { 206,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #206 = ATOMIC_LOAD_XOR_I64
4316
  { 207,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #207 = ATOMIC_LOAD_XOR_I64_POSTRA
4317
  { 208,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #208 = ATOMIC_LOAD_XOR_I8
4318
  { 209,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #209 = ATOMIC_LOAD_XOR_I8_POSTRA
4319
  { 210,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #210 = ATOMIC_SWAP_I16
4320
  { 211,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #211 = ATOMIC_SWAP_I16_POSTRA
4321
  { 212,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #212 = ATOMIC_SWAP_I32
4322
  { 213,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #213 = ATOMIC_SWAP_I32_POSTRA
4323
  { 214,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #214 = ATOMIC_SWAP_I64
4324
  { 215,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #215 = ATOMIC_SWAP_I64_POSTRA
4325
  { 216,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #216 = ATOMIC_SWAP_I8
4326
  { 217,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #217 = ATOMIC_SWAP_I8_POSTRA
4327
  { 218,  1,  0,  4,  367,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, ImplicitList2, OperandInfo41, -1 ,nullptr },  // Inst #218 = B
4328
  { 219,  1,  0,  4,  369,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, ImplicitList3, OperandInfo41, -1 ,nullptr },  // Inst #219 = BAL_BR
4329
  { 220,  1,  0,  4,  3,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, ImplicitList3, OperandInfo41, -1 ,nullptr },  // Inst #220 = BAL_BR_MM
4330
  { 221,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #221 = BEQLImmMacro
4331
  { 222,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #222 = BGE
4332
  { 223,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #223 = BGEImmMacro
4333
  { 224,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #224 = BGEL
4334
  { 225,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #225 = BGELImmMacro
4335
  { 226,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #226 = BGEU
4336
  { 227,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #227 = BGEUImmMacro
4337
  { 228,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #228 = BGEUL
4338
  { 229,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #229 = BGEULImmMacro
4339
  { 230,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #230 = BGT
4340
  { 231,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #231 = BGTImmMacro
4341
  { 232,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #232 = BGTL
4342
  { 233,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #233 = BGTLImmMacro
4343
  { 234,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #234 = BGTU
4344
  { 235,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #235 = BGTUImmMacro
4345
  { 236,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #236 = BGTUL
4346
  { 237,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #237 = BGTULImmMacro
4347
  { 238,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #238 = BLE
4348
  { 239,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #239 = BLEImmMacro
4349
  { 240,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #240 = BLEL
4350
  { 241,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #241 = BLELImmMacro
4351
  { 242,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #242 = BLEU
4352
  { 243,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #243 = BLEUImmMacro
4353
  { 244,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #244 = BLEUL
4354
  { 245,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #245 = BLEULImmMacro
4355
  { 246,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #246 = BLT
4356
  { 247,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #247 = BLTImmMacro
4357
  { 248,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #248 = BLTL
4358
  { 249,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #249 = BLTLImmMacro
4359
  { 250,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #250 = BLTU
4360
  { 251,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #251 = BLTUImmMacro
4361
  { 252,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #252 = BLTUL
4362
  { 253,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #253 = BLTULImmMacro
4363
  { 254,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #254 = BNELImmMacro
4364
  { 255,  1,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList4, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #255 = BPOSGE32_PSEUDO
4365
  { 256,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #256 = BSEL_D_PSEUDO
4366
  { 257,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #257 = BSEL_FD_PSEUDO
4367
  { 258,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #258 = BSEL_FW_PSEUDO
4368
  { 259,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #259 = BSEL_H_PSEUDO
4369
  { 260,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #260 = BSEL_W_PSEUDO
4370
  { 261,  1,  0,  4,  2,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, ImplicitList2, OperandInfo41, -1 ,nullptr },  // Inst #261 = B_MM
4371
  { 262,  1,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #262 = B_MMR6_Pseudo
4372
  { 263,  1,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #263 = B_MM_Pseudo
4373
  { 264,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #264 = BeqImm
4374
  { 265,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #265 = BneImm
4375
  { 266,  3,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #266 = BteqzT8CmpX16
4376
  { 267,  3,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #267 = BteqzT8CmpiX16
4377
  { 268,  3,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #268 = BteqzT8SltX16
4378
  { 269,  3,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #269 = BteqzT8SltiX16
4379
  { 270,  3,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #270 = BteqzT8SltiuX16
4380
  { 271,  3,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #271 = BteqzT8SltuX16
4381
  { 272,  3,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #272 = BtnezT8CmpX16
4382
  { 273,  3,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #273 = BtnezT8CmpiX16
4383
  { 274,  3,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #274 = BtnezT8SltX16
4384
  { 275,  3,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #275 = BtnezT8SltiX16
4385
  { 276,  3,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #276 = BtnezT8SltiuX16
4386
  { 277,  3,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #277 = BtnezT8SltuX16
4387
  { 278,  3,  1,  4,  659,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #278 = BuildPairF64
4388
  { 279,  3,  1,  4,  659,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #279 = BuildPairF64_64
4389
  { 280,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #280 = CFTC1
4390
  { 281,  3,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #281 = CONSTPOOL_ENTRY
4391
  { 282,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #282 = COPY_FD_PSEUDO
4392
  { 283,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #283 = COPY_FW_PSEUDO
4393
  { 284,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #284 = CTTC1
4394
  { 285,  1,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #285 = Constant32
4395
  { 286,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #286 = DMULImmMacro
4396
  { 287,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #287 = DMULMacro
4397
  { 288,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #288 = DMULOMacro
4398
  { 289,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #289 = DMULOUMacro
4399
  { 290,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #290 = DROL
4400
  { 291,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #291 = DROLImm
4401
  { 292,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #292 = DROR
4402
  { 293,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #293 = DRORImm
4403
  { 294,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #294 = DSDivIMacro
4404
  { 295,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #295 = DSDivMacro
4405
  { 296,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #296 = DSRemIMacro
4406
  { 297,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #297 = DSRemMacro
4407
  { 298,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #298 = DUDivIMacro
4408
  { 299,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #299 = DUDivMacro
4409
  { 300,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #300 = DURemIMacro
4410
  { 301,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #301 = DURemMacro
4411
  { 302,  0,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #302 = ERet
4412
  { 303,  3,  1,  4,  668,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #303 = ExtractElementF64
4413
  { 304,  3,  1,  4,  668,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #304 = ExtractElementF64_64
4414
  { 305,  2,  1,  4,  566,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #305 = FABS_D
4415
  { 306,  2,  1,  4,  566,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #306 = FABS_W
4416
  { 307,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #307 = FEXP2_D_1_PSEUDO
4417
  { 308,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #308 = FEXP2_W_1_PSEUDO
4418
  { 309,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr },  // Inst #309 = FILL_FD_PSEUDO
4419
  { 310,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr },  // Inst #310 = FILL_FW_PSEUDO
4420
  { 311,  4,  2,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #311 = GotPrologue16
4421
  { 312,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #312 = INSERT_B_VIDX64_PSEUDO
4422
  { 313,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #313 = INSERT_B_VIDX_PSEUDO
4423
  { 314,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #314 = INSERT_D_VIDX64_PSEUDO
4424
  { 315,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #315 = INSERT_D_VIDX_PSEUDO
4425
  { 316,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #316 = INSERT_FD_PSEUDO
4426
  { 317,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #317 = INSERT_FD_VIDX64_PSEUDO
4427
  { 318,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr },  // Inst #318 = INSERT_FD_VIDX_PSEUDO
4428
  { 319,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr },  // Inst #319 = INSERT_FW_PSEUDO
4429
  { 320,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr },  // Inst #320 = INSERT_FW_VIDX64_PSEUDO
4430
  { 321,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr },  // Inst #321 = INSERT_FW_VIDX_PSEUDO
4431
  { 322,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr },  // Inst #322 = INSERT_H_VIDX64_PSEUDO
4432
  { 323,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr },  // Inst #323 = INSERT_H_VIDX_PSEUDO
4433
  { 324,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #324 = INSERT_W_VIDX64_PSEUDO
4434
  { 325,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #325 = INSERT_W_VIDX_PSEUDO
4435
  { 326,  1,  0,  4,  6,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, nullptr, ImplicitList3, OperandInfo81, -1 ,nullptr },  // Inst #326 = JALR64Pseudo
4436
  { 327,  1,  0,  4,  6,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, nullptr, ImplicitList3, OperandInfo81, -1 ,nullptr },  // Inst #327 = JALRHB64Pseudo
4437
  { 328,  1,  0,  4,  400,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, nullptr, ImplicitList3, OperandInfo44, -1 ,nullptr },  // Inst #328 = JALRHBPseudo
4438
  { 329,  1,  0,  4,  400,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, nullptr, ImplicitList3, OperandInfo44, -1 ,nullptr },  // Inst #329 = JALRPseudo
4439
  { 330,  1,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #330 = JalOneReg
4440
  { 331,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #331 = JalTwoReg
4441
  { 332,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #332 = LDMacro
4442
  { 333,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #333 = LD_F16
4443
  { 334,  3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr },  // Inst #334 = LOAD_ACC128
4444
  { 335,  3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr },  // Inst #335 = LOAD_ACC64
4445
  { 336,  3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #336 = LOAD_ACC64DSP
4446
  { 337,  3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #337 = LOAD_CCOND_DSP
4447
  { 338,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #338 = LONG_BRANCH_ADDiu
4448
  { 339,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #339 = LONG_BRANCH_ADDiu2Op
4449
  { 340,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #340 = LONG_BRANCH_DADDiu
4450
  { 341,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #341 = LONG_BRANCH_DADDiu2Op
4451
  { 342,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #342 = LONG_BRANCH_LUi
4452
  { 343,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #343 = LONG_BRANCH_LUi2Op
4453
  { 344,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #344 = LONG_BRANCH_LUi2Op_64
4454
  { 345,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #345 = LWM_MM
4455
  { 346,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #346 = LoadAddrImm32
4456
  { 347,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr },  // Inst #347 = LoadAddrImm64
4457
  { 348,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #348 = LoadAddrReg32
4458
  { 349,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #349 = LoadAddrReg64
4459
  { 350,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr },  // Inst #350 = LoadImm32
4460
  { 351,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr },  // Inst #351 = LoadImm64
4461
  { 352,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr },  // Inst #352 = LoadImmDoubleFGR
4462
  { 353,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #353 = LoadImmDoubleFGR_32
4463
  { 354,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr },  // Inst #354 = LoadImmDoubleGPR
4464
  { 355,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #355 = LoadImmSingleFGR
4465
  { 356,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr },  // Inst #356 = LoadImmSingleGPR
4466
  { 357,  3,  1,  2,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #357 = LwConstant32
4467
  { 358,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr },  // Inst #358 = MFTACX
4468
  { 359,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr },  // Inst #359 = MFTC0
4469
  { 360,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #360 = MFTC1
4470
  { 361,  1,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #361 = MFTDSP
4471
  { 362,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #362 = MFTGPR
4472
  { 363,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #363 = MFTHC1
4473
  { 364,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr },  // Inst #364 = MFTHI
4474
  { 365,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr },  // Inst #365 = MFTLO
4475
  { 366,  2,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList5, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #366 = MIPSeh_return32
4476
  { 367,  2,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList5, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #367 = MIPSeh_return64
4477
  { 368,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #368 = MSA_FP_EXTEND_D_PSEUDO
4478
  { 369,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #369 = MSA_FP_EXTEND_W_PSEUDO
4479
  { 370,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #370 = MSA_FP_ROUND_D_PSEUDO
4480
  { 371,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr },  // Inst #371 = MSA_FP_ROUND_W_PSEUDO
4481
  { 372,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #372 = MTTACX
4482
  { 373,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr },  // Inst #373 = MTTC0
4483
  { 374,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr },  // Inst #374 = MTTC1
4484
  { 375,  1,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #375 = MTTDSP
4485
  { 376,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #376 = MTTGPR
4486
  { 377,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr },  // Inst #377 = MTTHC1
4487
  { 378,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #378 = MTTHI
4488
  { 379,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #379 = MTTLO
4489
  { 380,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #380 = MULImmMacro
4490
  { 381,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #381 = MULOMacro
4491
  { 382,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #382 = MULOUMacro
4492
  { 383,  2,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo114, -1 ,nullptr },  // Inst #383 = MultRxRy16
4493
  { 384,  3,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo115, -1 ,nullptr },  // Inst #384 = MultRxRyRz16
4494
  { 385,  2,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo114, -1 ,nullptr },  // Inst #385 = MultuRxRy16
4495
  { 386,  3,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo115, -1 ,nullptr },  // Inst #386 = MultuRxRyRz16
4496
  { 387,  0,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #387 = NOP
4497
  { 388,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #388 = NORImm
4498
  { 389,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #389 = NORImm64
4499
  { 390,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #390 = NOR_V_D_PSEUDO
4500
  { 391,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #391 = NOR_V_H_PSEUDO
4501
  { 392,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #392 = NOR_V_W_PSEUDO
4502
  { 393,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #393 = OR_V_D_PSEUDO
4503
  { 394,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #394 = OR_V_H_PSEUDO
4504
  { 395,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #395 = OR_V_W_PSEUDO
4505
  { 396,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #396 = PseudoCMPU_EQ_QB
4506
  { 397,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #397 = PseudoCMPU_LE_QB
4507
  { 398,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #398 = PseudoCMPU_LT_QB
4508
  { 399,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #399 = PseudoCMP_EQ_PH
4509
  { 400,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #400 = PseudoCMP_LE_PH
4510
  { 401,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #401 = PseudoCMP_LT_PH
4511
  { 402,  2,  1,  4,  618,  0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr },  // Inst #402 = PseudoCVT_D32_W
4512
  { 403,  2,  1,  4,  618,  0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #403 = PseudoCVT_D64_L
4513
  { 404,  2,  1,  4,  618,  0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #404 = PseudoCVT_D64_W
4514
  { 405,  2,  1,  4,  618,  0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #405 = PseudoCVT_S_L
4515
  { 406,  2,  1,  4,  618,  0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr },  // Inst #406 = PseudoCVT_S_W
4516
  { 407,  3,  1,  4,  8,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #407 = PseudoDMULT
4517
  { 408,  3,  1,  4,  9,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #408 = PseudoDMULTu
4518
  { 409,  3,  1,  4,  10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #409 = PseudoDSDIV
4519
  { 410,  3,  1,  4,  11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #410 = PseudoDUDIV
4520
  { 411,  7,  2,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #411 = PseudoD_SELECT_I
4521
  { 412,  7,  2,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #412 = PseudoD_SELECT_I64
4522
  { 413,  1,  0,  4,  379,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #413 = PseudoIndirectBranch
4523
  { 414,  1,  0,  4,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #414 = PseudoIndirectBranch64
4524
  { 415,  1,  0,  4,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #415 = PseudoIndirectBranch64R6
4525
  { 416,  1,  0,  4,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #416 = PseudoIndirectBranchR6
4526
  { 417,  1,  0,  4,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #417 = PseudoIndirectBranch_MM
4527
  { 418,  1,  0,  4,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #418 = PseudoIndirectBranch_MMR6
4528
  { 419,  1,  0,  4,  379,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #419 = PseudoIndirectHazardBranch
4529
  { 420,  1,  0,  4,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #420 = PseudoIndirectHazardBranch64
4530
  { 421,  1,  0,  4,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #421 = PseudoIndrectHazardBranch64R6
4531
  { 422,  1,  0,  4,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #422 = PseudoIndrectHazardBranchR6
4532
  { 423,  4,  1,  4,  471,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #423 = PseudoMADD
4533
  { 424,  4,  1,  4,  472,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #424 = PseudoMADDU
4534
  { 425,  4,  1,  4,  14, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #425 = PseudoMADDU_MM
4535
  { 426,  4,  1,  4,  13, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #426 = PseudoMADD_MM
4536
  { 427,  2,  1,  4,  460,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr },  // Inst #427 = PseudoMFHI
4537
  { 428,  2,  1,  4,  15, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #428 = PseudoMFHI64
4538
  { 429,  2,  1,  4,  15, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr },  // Inst #429 = PseudoMFHI_MM
4539
  { 430,  2,  1,  4,  460,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr },  // Inst #430 = PseudoMFLO
4540
  { 431,  2,  1,  4,  15, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #431 = PseudoMFLO64
4541
  { 432,  2,  1,  4,  15, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr },  // Inst #432 = PseudoMFLO_MM
4542
  { 433,  4,  1,  4,  473,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #433 = PseudoMSUB
4543
  { 434,  4,  1,  4,  474,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #434 = PseudoMSUBU
4544
  { 435,  4,  1,  4,  17, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #435 = PseudoMSUBU_MM
4545
  { 436,  4,  1,  4,  16, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #436 = PseudoMSUB_MM
4546
  { 437,  3,  1,  4,  475,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr },  // Inst #437 = PseudoMTLOHI
4547
  { 438,  3,  1,  4,  18, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #438 = PseudoMTLOHI64
4548
  { 439,  3,  1,  4,  18, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr },  // Inst #439 = PseudoMTLOHI_DSP
4549
  { 440,  3,  1,  4,  18, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr },  // Inst #440 = PseudoMTLOHI_MM
4550
  { 441,  3,  1,  4,  469,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr },  // Inst #441 = PseudoMULT
4551
  { 442,  3,  1,  4,  19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr },  // Inst #442 = PseudoMULT_MM
4552
  { 443,  3,  1,  4,  470,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr },  // Inst #443 = PseudoMULTu
4553
  { 444,  3,  1,  4,  20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr },  // Inst #444 = PseudoMULTu_MM
4554
  { 445,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr },  // Inst #445 = PseudoPICK_PH
4555
  { 446,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr },  // Inst #446 = PseudoPICK_QB
4556
  { 447,  1,  0,  4,  380,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #447 = PseudoReturn
4557
  { 448,  1,  0,  4,  21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #448 = PseudoReturn64
4558
  { 449,  3,  1,  4,  466,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr },  // Inst #449 = PseudoSDIV
4559
  { 450,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #450 = PseudoSELECTFP_F_D32
4560
  { 451,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr },  // Inst #451 = PseudoSELECTFP_F_D64
4561
  { 452,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #452 = PseudoSELECTFP_F_I
4562
  { 453,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr },  // Inst #453 = PseudoSELECTFP_F_I64
4563
  { 454,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr },  // Inst #454 = PseudoSELECTFP_F_S
4564
  { 455,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #455 = PseudoSELECTFP_T_D32
4565
  { 456,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr },  // Inst #456 = PseudoSELECTFP_T_D64
4566
  { 457,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #457 = PseudoSELECTFP_T_I
4567
  { 458,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr },  // Inst #458 = PseudoSELECTFP_T_I64
4568
  { 459,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr },  // Inst #459 = PseudoSELECTFP_T_S
4569
  { 460,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #460 = PseudoSELECT_D32
4570
  { 461,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #461 = PseudoSELECT_D64
4571
  { 462,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #462 = PseudoSELECT_I
4572
  { 463,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #463 = PseudoSELECT_I64
4573
  { 464,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr },  // Inst #464 = PseudoSELECT_S
4574
  { 465,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr },  // Inst #465 = PseudoTRUNC_W_D
4575
  { 466,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #466 = PseudoTRUNC_W_D32
4576
  { 467,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr },  // Inst #467 = PseudoTRUNC_W_S
4577
  { 468,  3,  1,  4,  467,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr },  // Inst #468 = PseudoUDIV
4578
  { 469,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #469 = ROL
4579
  { 470,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #470 = ROLImm
4580
  { 471,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #471 = ROR
4581
  { 472,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #472 = RORImm
4582
  { 473,  0,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #473 = RetRA
4583
  { 474,  0,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #474 = RetRA16
4584
  { 475,  3,  1,  4,  22, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr },  // Inst #475 = SDIV_MM_Pseudo
4585
  { 476,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #476 = SDMacro
4586
  { 477,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #477 = SDivIMacro
4587
  { 478,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #478 = SDivMacro
4588
  { 479,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #479 = SEQIMacro
4589
  { 480,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #480 = SEQMacro
4590
  { 481,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #481 = SLTImm64
4591
  { 482,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #482 = SLTUImm64
4592
  { 483,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #483 = SNZ_B_PSEUDO
4593
  { 484,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #484 = SNZ_D_PSEUDO
4594
  { 485,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #485 = SNZ_H_PSEUDO
4595
  { 486,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #486 = SNZ_V_PSEUDO
4596
  { 487,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #487 = SNZ_W_PSEUDO
4597
  { 488,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #488 = SRemIMacro
4598
  { 489,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #489 = SRemMacro
4599
  { 490,  3,  0,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr },  // Inst #490 = STORE_ACC128
4600
  { 491,  3,  0,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr },  // Inst #491 = STORE_ACC64
4601
  { 492,  3,  0,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #492 = STORE_ACC64DSP
4602
  { 493,  3,  0,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #493 = STORE_CCOND_DSP
4603
  { 494,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #494 = ST_F16
4604
  { 495,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #495 = SWM_MM
4605
  { 496,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #496 = SZ_B_PSEUDO
4606
  { 497,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #497 = SZ_D_PSEUDO
4607
  { 498,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #498 = SZ_H_PSEUDO
4608
  { 499,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #499 = SZ_V_PSEUDO
4609
  { 500,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #500 = SZ_W_PSEUDO
4610
  { 501,  4,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #501 = SelBeqZ
4611
  { 502,  4,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #502 = SelBneZ
4612
  { 503,  5,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #503 = SelTBteqZCmp
4613
  { 504,  5,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #504 = SelTBteqZCmpi
4614
  { 505,  5,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #505 = SelTBteqZSlt
4615
  { 506,  5,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #506 = SelTBteqZSlti
4616
  { 507,  5,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #507 = SelTBteqZSltiu
4617
  { 508,  5,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #508 = SelTBteqZSltu
4618
  { 509,  5,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #509 = SelTBtneZCmp
4619
  { 510,  5,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #510 = SelTBtneZCmpi
4620
  { 511,  5,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #511 = SelTBtneZSlt
4621
  { 512,  5,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #512 = SelTBtneZSlti
4622
  { 513,  5,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #513 = SelTBtneZSltiu
4623
  { 514,  5,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #514 = SelTBtneZSltu
4624
  { 515,  3,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #515 = SltCCRxRy16
4625
  { 516,  3,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #516 = SltiCCRxImmX16
4626
  { 517,  3,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #517 = SltiuCCRxImmX16
4627
  { 518,  3,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #518 = SltuCCRxRy16
4628
  { 519,  3,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo115, -1 ,nullptr },  // Inst #519 = SltuRxRyRz16
4629
  { 520,  1,  0,  4,  376,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr },  // Inst #520 = TAILCALL
4630
  { 521,  1,  0,  4,  25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo81, -1 ,nullptr },  // Inst #521 = TAILCALL64R6REG
4631
  { 522,  1,  0,  4,  25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo81, -1 ,nullptr },  // Inst #522 = TAILCALLHB64R6REG
4632
  { 523,  1,  0,  4,  25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #523 = TAILCALLHBR6REG
4633
  { 524,  1,  0,  4,  25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #524 = TAILCALLR6REG
4634
  { 525,  1,  0,  4,  377,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #525 = TAILCALLREG
4635
  { 526,  1,  0,  4,  25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo81, -1 ,nullptr },  // Inst #526 = TAILCALLREG64
4636
  { 527,  1,  0,  4,  377,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #527 = TAILCALLREGHB
4637
  { 528,  1,  0,  4,  25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo81, -1 ,nullptr },  // Inst #528 = TAILCALLREGHB64
4638
  { 529,  1,  0,  4,  25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #529 = TAILCALLREG_MM
4639
  { 530,  1,  0,  4,  25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #530 = TAILCALLREG_MMR6
4640
  { 531,  1,  0,  4,  24, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr },  // Inst #531 = TAILCALL_MM
4641
  { 532,  1,  0,  4,  24, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr },  // Inst #532 = TAILCALL_MMR6
4642
  { 533,  0,  0,  4,  395,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #533 = TRAP
4643
  { 534,  0,  0,  4,  26, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #534 = TRAP_MM
4644
  { 535,  3,  1,  4,  23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr },  // Inst #535 = UDIV_MM_Pseudo
4645
  { 536,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #536 = UDivIMacro
4646
  { 537,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #537 = UDivMacro
4647
  { 538,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #538 = URemIMacro
4648
  { 539,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #539 = URemMacro
4649
  { 540,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #540 = Ulh
4650
  { 541,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #541 = Ulhu
4651
  { 542,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #542 = Ulw
4652
  { 543,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #543 = Ush
4653
  { 544,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #544 = Usw
4654
  { 545,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #545 = XOR_V_D_PSEUDO
4655
  { 546,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #546 = XOR_V_H_PSEUDO
4656
  { 547,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #547 = XOR_V_W_PSEUDO
4657
  { 548,  2,  1,  4,  704,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo151, -1 ,nullptr },  // Inst #548 = ABSQ_S_PH
4658
  { 549,  2,  1,  4,  851,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo151, -1 ,nullptr },  // Inst #549 = ABSQ_S_PH_MM
4659
  { 550,  2,  1,  4,  805,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo151, -1 ,nullptr },  // Inst #550 = ABSQ_S_QB
4660
  { 551,  2,  1,  4,  968,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo151, -1 ,nullptr },  // Inst #551 = ABSQ_S_QB_MMR2
4661
  { 552,  2,  1,  4,  705,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo31, -1 ,nullptr },  // Inst #552 = ABSQ_S_W
4662
  { 553,  2,  1,  4,  852,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo31, -1 ,nullptr },  // Inst #553 = ABSQ_S_W_MM
4663
  { 554,  3,  1,  4,  478,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #554 = ADD
4664
  { 555,  2,  1,  4,  28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr },  // Inst #555 = ADDIUPC
4665
  { 556,  2,  1,  4,  29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #556 = ADDIUPC_MM
4666
  { 557,  2,  1,  4,  28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr },  // Inst #557 = ADDIUPC_MMR6
4667
  { 558,  2,  1,  2,  29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #558 = ADDIUR1SP_MM
4668
  { 559,  3,  1,  2,  29, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #559 = ADDIUR2_MM
4669
  { 560,  3,  1,  2,  29, 0, 0x0ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr },  // Inst #560 = ADDIUS5_MM
4670
  { 561,  1,  0,  2,  29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #561 = ADDIUSP_MM
4671
  { 562,  3,  1,  4,  29, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #562 = ADDIU_MMR6
4672
  { 563,  3,  1,  4,  806,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr },  // Inst #563 = ADDQH_PH
4673
  { 564,  3,  1,  4,  969,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr },  // Inst #564 = ADDQH_PH_MMR2
4674
  { 565,  3,  1,  4,  807,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr },  // Inst #565 = ADDQH_R_PH
4675
  { 566,  3,  1,  4,  970,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr },  // Inst #566 = ADDQH_R_PH_MMR2
4676
  { 567,  3,  1,  4,  808,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #567 = ADDQH_R_W
4677
  { 568,  3,  1,  4,  971,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #568 = ADDQH_R_W_MMR2
4678
  { 569,  3,  1,  4,  809,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #569 = ADDQH_W
4679
  { 570,  3,  1,  4,  972,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #570 = ADDQH_W_MMR2
4680
  { 571,  3,  1,  4,  706,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo155, -1 ,nullptr },  // Inst #571 = ADDQ_PH
4681
  { 572,  3,  1,  4,  853,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo155, -1 ,nullptr },  // Inst #572 = ADDQ_PH_MM
4682
  { 573,  3,  1,  4,  707,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo155, -1 ,nullptr },  // Inst #573 = ADDQ_S_PH
4683
  { 574,  3,  1,  4,  854,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo155, -1 ,nullptr },  // Inst #574 = ADDQ_S_PH_MM
4684
  { 575,  3,  1,  4,  708,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo58, -1 ,nullptr },  // Inst #575 = ADDQ_S_W
4685
  { 576,  3,  1,  4,  855,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo58, -1 ,nullptr },  // Inst #576 = ADDQ_S_W_MM
4686
  { 577,  3,  1,  4,  709,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList9, OperandInfo58, -1 ,nullptr },  // Inst #577 = ADDSC
4687
  { 578,  3,  1,  4,  856,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList9, OperandInfo58, -1 ,nullptr },  // Inst #578 = ADDSC_MM
4688
  { 579,  3,  1,  4,  520,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #579 = ADDS_A_B
4689
  { 580,  3,  1,  4,  520,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #580 = ADDS_A_D
4690
  { 581,  3,  1,  4,  520,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #581 = ADDS_A_H
4691
  { 582,  3,  1,  4,  520,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #582 = ADDS_A_W
4692
  { 583,  3,  1,  4,  520,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #583 = ADDS_S_B
4693
  { 584,  3,  1,  4,  520,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #584 = ADDS_S_D
4694
  { 585,  3,  1,  4,  520,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #585 = ADDS_S_H
4695
  { 586,  3,  1,  4,  520,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #586 = ADDS_S_W
4696
  { 587,  3,  1,  4,  520,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #587 = ADDS_U_B
4697
  { 588,  3,  1,  4,  520,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #588 = ADDS_U_D
4698
  { 589,  3,  1,  4,  520,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #589 = ADDS_U_H
4699
  { 590,  3,  1,  4,  520,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #590 = ADDS_U_W
4700
  { 591,  3,  1,  2,  30, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr },  // Inst #591 = ADDU16_MM
4701
  { 592,  3,  1,  2,  30, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr },  // Inst #592 = ADDU16_MMR6
4702
  { 593,  3,  1,  4,  810,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr },  // Inst #593 = ADDUH_QB
4703
  { 594,  3,  1,  4,  973,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr },  // Inst #594 = ADDUH_QB_MMR2
4704
  { 595,  3,  1,  4,  811,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr },  // Inst #595 = ADDUH_R_QB
4705
  { 596,  3,  1,  4,  974,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr },  // Inst #596 = ADDUH_R_QB_MMR2
4706
  { 597,  3,  1,  4,  30, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #597 = ADDU_MMR6
4707
  { 598,  3,  1,  4,  812,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo155, -1 ,nullptr },  // Inst #598 = ADDU_PH
4708
  { 599,  3,  1,  4,  975,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo155, -1 ,nullptr },  // Inst #599 = ADDU_PH_MMR2
4709
  { 600,  3,  1,  4,  710,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo155, -1 ,nullptr },  // Inst #600 = ADDU_QB
4710
  { 601,  3,  1,  4,  857,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo155, -1 ,nullptr },  // Inst #601 = ADDU_QB_MM
4711
  { 602,  3,  1,  4,  813,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo155, -1 ,nullptr },  // Inst #602 = ADDU_S_PH
4712
  { 603,  3,  1,  4,  976,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo155, -1 ,nullptr },  // Inst #603 = ADDU_S_PH_MMR2
4713
  { 604,  3,  1,  4,  711,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo155, -1 ,nullptr },  // Inst #604 = ADDU_S_QB
4714
  { 605,  3,  1,  4,  858,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo155, -1 ,nullptr },  // Inst #605 = ADDU_S_QB_MM
4715
  { 606,  3,  1,  4,  521,  0, 0x6ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr },  // Inst #606 = ADDVI_B
4716
  { 607,  3,  1,  4,  521,  0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr },  // Inst #607 = ADDVI_D
4717
  { 608,  3,  1,  4,  521,  0, 0x6ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr },  // Inst #608 = ADDVI_H
4718
  { 609,  3,  1,  4,  521,  0, 0x6ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #609 = ADDVI_W
4719
  { 610,  3,  1,  4,  521,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #610 = ADDV_B
4720
  { 611,  3,  1,  4,  521,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #611 = ADDV_D
4721
  { 612,  3,  1,  4,  521,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #612 = ADDV_H
4722
  { 613,  3,  1,  4,  521,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #613 = ADDV_W
4723
  { 614,  3,  1,  4,  712,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList9, ImplicitList8, OperandInfo58, -1 ,nullptr },  // Inst #614 = ADDWC
4724
  { 615,  3,  1,  4,  859,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList9, ImplicitList8, OperandInfo58, -1 ,nullptr },  // Inst #615 = ADDWC_MM
4725
  { 616,  3,  1,  4,  519,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #616 = ADD_A_B
4726
  { 617,  3,  1,  4,  519,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #617 = ADD_A_D
4727
  { 618,  3,  1,  4,  519,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #618 = ADD_A_H
4728
  { 619,  3,  1,  4,  519,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #619 = ADD_A_W
4729
  { 620,  3,  1,  4,  27, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #620 = ADD_MM
4730
  { 621,  3,  1,  4,  27, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #621 = ADD_MMR6
4731
  { 622,  3,  1,  4,  479,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #622 = ADDi
4732
  { 623,  3,  1,  4,  31, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #623 = ADDi_MM
4733
  { 624,  3,  1,  4,  480,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #624 = ADDiu
4734
  { 625,  3,  1,  4,  29, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #625 = ADDiu_MM
4735
  { 626,  3,  1,  4,  491,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #626 = ADDu
4736
  { 627,  3,  1,  4,  30, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #627 = ADDu_MM
4737
  { 628,  4,  1,  4,  32, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr },  // Inst #628 = ALIGN
4738
  { 629,  4,  1,  4,  32, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr },  // Inst #629 = ALIGN_MMR6
4739
  { 630,  2,  1,  4,  33, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr },  // Inst #630 = ALUIPC
4740
  { 631,  2,  1,  4,  33, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr },  // Inst #631 = ALUIPC_MMR6
4741
  { 632,  3,  1,  4,  359,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #632 = AND
4742
  { 633,  3,  1,  2,  34, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr },  // Inst #633 = AND16_MM
4743
  { 634,  3,  1,  2,  34, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr },  // Inst #634 = AND16_MMR6
4744
  { 635,  3,  1,  4,  34, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #635 = AND64
4745
  { 636,  3,  1,  2,  34, 0, 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #636 = ANDI16_MM
4746
  { 637,  3,  1,  2,  34, 0, 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #637 = ANDI16_MMR6
4747
  { 638,  3,  1,  4,  530,  0, 0x6ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr },  // Inst #638 = ANDI_B
4748
  { 639,  3,  1,  4,  35, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #639 = ANDI_MMR6
4749
  { 640,  3,  1,  4,  34, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #640 = AND_MM
4750
  { 641,  3,  1,  4,  34, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #641 = AND_MMR6
4751
  { 642,  3,  1,  4,  529,  0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #642 = AND_V
4752
  { 643,  3,  1,  4,  481,  0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #643 = ANDi
4753
  { 644,  3,  1,  4,  34, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #644 = ANDi64
4754
  { 645,  3,  1,  4,  35, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #645 = ANDi_MM
4755
  { 646,  4,  1,  4,  814,  0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #646 = APPEND
4756
  { 647,  4,  1,  4,  977,  0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #647 = APPEND_MMR2
4757
  { 648,  3,  1,  4,  522,  0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #648 = ASUB_S_B
4758
  { 649,  3,  1,  4,  522,  0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #649 = ASUB_S_D
4759
  { 650,  3,  1,  4,  522,  0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #650 = ASUB_S_H
4760
  { 651,  3,  1,  4,  522,  0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #651 = ASUB_S_W
4761
  { 652,  3,  1,  4,  522,  0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #652 = ASUB_U_B
4762
  { 653,  3,  1,  4,  522,  0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #653 = ASUB_U_D
4763
  { 654,  3,  1,  4,  522,  0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #654 = ASUB_U_H
4764
  { 655,  3,  1,  4,  522,  0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #655 = ASUB_U_W
4765
  { 656,  3,  1,  4,  36, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #656 = AUI
4766
  { 657,  2,  1,  4,  37, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr },  // Inst #657 = AUIPC
4767
  { 658,  2,  1,  4,  37, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr },  // Inst #658 = AUIPC_MMR6
4768
  { 659,  3,  1,  4,  36, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #659 = AUI_MMR6
4769
  { 660,  3,  1,  4,  523,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #660 = AVER_S_B
4770
  { 661,  3,  1,  4,  523,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #661 = AVER_S_D
4771
  { 662,  3,  1,  4,  523,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #662 = AVER_S_H
4772
  { 663,  3,  1,  4,  523,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #663 = AVER_S_W
4773
  { 664,  3,  1,  4,  523,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #664 = AVER_U_B
4774
  { 665,  3,  1,  4,  523,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #665 = AVER_U_D
4775
  { 666,  3,  1,  4,  523,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #666 = AVER_U_H
4776
  { 667,  3,  1,  4,  523,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #667 = AVER_U_W
4777
  { 668,  3,  1,  4,  523,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #668 = AVE_S_B
4778
  { 669,  3,  1,  4,  523,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #669 = AVE_S_D
4779
  { 670,  3,  1,  4,  523,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #670 = AVE_S_H
4780
  { 671,  3,  1,  4,  523,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #671 = AVE_S_W
4781
  { 672,  3,  1,  4,  523,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #672 = AVE_U_B
4782
  { 673,  3,  1,  4,  523,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #673 = AVE_U_D
4783
  { 674,  3,  1,  4,  523,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #674 = AVE_U_H
4784
  { 675,  3,  1,  4,  523,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #675 = AVE_U_W
4785
  { 676,  2,  1,  4,  38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr },  // Inst #676 = AddiuRxImmX16
4786
  { 677,  2,  1,  4,  38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr },  // Inst #677 = AddiuRxPcImmX16
4787
  { 678,  3,  1,  2,  38, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr },  // Inst #678 = AddiuRxRxImm16
4788
  { 679,  3,  1,  4,  38, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr },  // Inst #679 = AddiuRxRxImmX16
4789
  { 680,  3,  1,  4,  38, 0, 0x0ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr },  // Inst #680 = AddiuRxRyOffMemX16
4790
  { 681,  1,  0,  2,  38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo2, -1 ,nullptr },  // Inst #681 = AddiuSpImm16
4791
  { 682,  1,  0,  4,  38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo2, -1 ,nullptr },  // Inst #682 = AddiuSpImmX16
4792
  { 683,  3,  1,  2,  38, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #683 = AdduRxRyRz16
4793
  { 684,  3,  1,  2,  38, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr },  // Inst #684 = AndRxRxRy16
4794
  { 685,  1,  0,  2,  2,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo41, -1 ,nullptr },  // Inst #685 = B16_MM
4795
  { 686,  3,  1,  4,  39, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #686 = BADDu
4796
  { 687,  1,  0,  4,  368,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo41, -1 ,nullptr },  // Inst #687 = BAL
4797
  { 688,  1,  0,  4,  41, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo41, -1 ,nullptr },  // Inst #688 = BALC
4798
  { 689,  1,  0,  4,  41, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo41, -1 ,nullptr },  // Inst #689 = BALC_MMR6
4799
  { 690,  4,  1,  4,  815,  0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #690 = BALIGN
4800
  { 691,  4,  1,  4,  978,  0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #691 = BALIGN_MMR2
4801
  { 692,  3,  0,  4,  42, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo169, -1 ,nullptr },  // Inst #692 = BBIT0
4802
  { 693,  3,  0,  4,  42, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo169, -1 ,nullptr },  // Inst #693 = BBIT032
4803
  { 694,  3,  0,  4,  42, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo169, -1 ,nullptr },  // Inst #694 = BBIT1
4804
  { 695,  3,  0,  4,  42, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo169, -1 ,nullptr },  // Inst #695 = BBIT132
4805
  { 696,  1,  0,  4,  40, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #696 = BC
4806
  { 697,  1,  0,  2,  40, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo41, -1 ,nullptr },  // Inst #697 = BC16_MMR6
4807
  { 698,  2,  0,  4,  43, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo170, -1 ,nullptr },  // Inst #698 = BC1EQZ
4808
  { 699,  2,  0,  4,  43, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr },  // Inst #699 = BC1EQZC_MMR6
4809
  { 700,  2,  0,  4,  663,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x85ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr },  // Inst #700 = BC1F
4810
  { 701,  2,  0,  4,  664,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x85ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr },  // Inst #701 = BC1FL
4811
  { 702,  2,  0,  4,  44, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x85ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr },  // Inst #702 = BC1F_MM
4812
  { 703,  2,  0,  4,  43, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo170, -1 ,nullptr },  // Inst #703 = BC1NEZ
4813
  { 704,  2,  0,  4,  43, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr },  // Inst #704 = BC1NEZC_MMR6
4814
  { 705,  2,  0,  4,  665,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x85ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr },  // Inst #705 = BC1T
4815
  { 706,  2,  0,  4,  666,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x85ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr },  // Inst #706 = BC1TL
4816
  { 707,  2,  0,  4,  46, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x85ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr },  // Inst #707 = BC1T_MM
4817
  { 708,  2,  0,  4,  48, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #708 = BC2EQZ
4818
  { 709,  2,  0,  4,  48, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo172, -1 ,nullptr },  // Inst #709 = BC2EQZC_MMR6
4819
  { 710,  2,  0,  4,  48, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #710 = BC2NEZ
4820
  { 711,  2,  0,  4,  48, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo172, -1 ,nullptr },  // Inst #711 = BC2NEZC_MMR6
4821
  { 712,  3,  1,  4,  503,  0, 0x6ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr },  // Inst #712 = BCLRI_B
4822
  { 713,  3,  1,  4,  503,  0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr },  // Inst #713 = BCLRI_D
4823
  { 714,  3,  1,  4,  503,  0, 0x6ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr },  // Inst #714 = BCLRI_H
4824
  { 715,  3,  1,  4,  503,  0, 0x6ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #715 = BCLRI_W
4825
  { 716,  3,  1,  4,  503,  0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #716 = BCLR_B
4826
  { 717,  3,  1,  4,  503,  0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #717 = BCLR_D
4827
  { 718,  3,  1,  4,  503,  0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #718 = BCLR_H
4828
  { 719,  3,  1,  4,  503,  0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #719 = BCLR_W
4829
  { 720,  1,  0,  4,  40, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x16ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #720 = BC_MMR6
4830
  { 721,  3,  0,  4,  370,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #721 = BEQ
4831
  { 722,  3,  0,  4,  49, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo90, -1 ,nullptr },  // Inst #722 = BEQ64
4832
  { 723,  3,  0,  4,  50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #723 = BEQC
4833
  { 724,  3,  0,  4,  50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo90, -1 ,nullptr },  // Inst #724 = BEQC64
4834
  { 725,  3,  0,  4,  50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #725 = BEQC_MMR6
4835
  { 726,  3,  0,  4,  370,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #726 = BEQL
4836
  { 727,  2,  0,  2,  51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo173, -1 ,nullptr },  // Inst #727 = BEQZ16_MM
4837
  { 728,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo92, -1 ,nullptr },  // Inst #728 = BEQZALC
4838
  { 729,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo92, -1 ,nullptr },  // Inst #729 = BEQZALC_MMR6
4839
  { 730,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo92, -1 ,nullptr },  // Inst #730 = BEQZC
4840
  { 731,  2,  0,  2,  51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo173, -1 ,nullptr },  // Inst #731 = BEQZC16_MMR6
4841
  { 732,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo93, -1 ,nullptr },  // Inst #732 = BEQZC64
4842
  { 733,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList2, OperandInfo92, -1 ,nullptr },  // Inst #733 = BEQZC_MM
4843
  { 734,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL, nullptr, ImplicitList2, OperandInfo92, -1 ,nullptr },  // Inst #734 = BEQZC_MMR6
4844
  { 735,  3,  0,  4,  49, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #735 = BEQ_MM
4845
  { 736,  3,  0,  4,  50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #736 = BGEC
4846
  { 737,  3,  0,  4,  50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo90, -1 ,nullptr },  // Inst #737 = BGEC64
4847
  { 738,  3,  0,  4,  50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #738 = BGEC_MMR6
4848
  { 739,  3,  0,  4,  50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #739 = BGEUC
4849
  { 740,  3,  0,  4,  50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo90, -1 ,nullptr },  // Inst #740 = BGEUC64
4850
  { 741,  3,  0,  4,  50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #741 = BGEUC_MMR6
4851
  { 742,  2,  0,  4,  371,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo92, -1 ,nullptr },  // Inst #742 = BGEZ
4852
  { 743,  2,  0,  4,  51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo93, -1 ,nullptr },  // Inst #743 = BGEZ64
4853
  { 744,  2,  0,  4,  369,  0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo92, -1 ,nullptr },  // Inst #744 = BGEZAL
4854
  { 745,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo92, -1 ,nullptr },  // Inst #745 = BGEZALC
4855
  { 746,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo92, -1 ,nullptr },  // Inst #746 = BGEZALC_MMR6
4856
  { 747,  2,  0,  4,  369,  0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo92, -1 ,nullptr },  // Inst #747 = BGEZALL
4857
  { 748,  2,  0,  4,  53, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList3, OperandInfo92, -1 ,nullptr },  // Inst #748 = BGEZALS_MM
4858
  { 749,  2,  0,  4,  3,  0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo92, -1 ,nullptr },  // Inst #749 = BGEZAL_MM
4859
  { 750,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo92, -1 ,nullptr },  // Inst #750 = BGEZC
4860
  { 751,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo93, -1 ,nullptr },  // Inst #751 = BGEZC64
4861
  { 752,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo92, -1 ,nullptr },  // Inst #752 = BGEZC_MMR6
4862
  { 753,  2,  0,  4,  371,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo92, -1 ,nullptr },  // Inst #753 = BGEZL
4863
  { 754,  2,  0,  4,  51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo92, -1 ,nullptr },  // Inst #754 = BGEZ_MM
4864
  { 755,  2,  0,  4,  371,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo92, -1 ,nullptr },  // Inst #755 = BGTZ
4865
  { 756,  2,  0,  4,  51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo93, -1 ,nullptr },  // Inst #756 = BGTZ64
4866
  { 757,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo92, -1 ,nullptr },  // Inst #757 = BGTZALC
4867
  { 758,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo92, -1 ,nullptr },  // Inst #758 = BGTZALC_MMR6
4868
  { 759,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo92, -1 ,nullptr },  // Inst #759 = BGTZC
4869
  { 760,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo93, -1 ,nullptr },  // Inst #760 = BGTZC64
4870
  { 761,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo92, -1 ,nullptr },  // Inst #761 = BGTZC_MMR6
4871
  { 762,  2,  0,  4,  371,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo92, -1 ,nullptr },  // Inst #762 = BGTZL
4872
  { 763,  2,  0,  4,  51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo92, -1 ,nullptr },  // Inst #763 = BGTZ_MM
4873
  { 764,  4,  1,  4,  498,  0, 0x6ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr },  // Inst #764 = BINSLI_B
4874
  { 765,  4,  1,  4,  498,  0, 0x6ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #765 = BINSLI_D
4875
  { 766,  4,  1,  4,  498,  0, 0x6ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr },  // Inst #766 = BINSLI_H
4876
  { 767,  4,  1,  4,  498,  0, 0x6ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr },  // Inst #767 = BINSLI_W
4877
  { 768,  4,  1,  4,  498,  0, 0x6ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr },  // Inst #768 = BINSL_B
4878
  { 769,  4,  1,  4,  498,  0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #769 = BINSL_D
4879
  { 770,  4,  1,  4,  498,  0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #770 = BINSL_H
4880
  { 771,  4,  1,  4,  498,  0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #771 = BINSL_W
4881
  { 772,  4,  1,  4,  499,  0, 0x6ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr },  // Inst #772 = BINSRI_B
4882
  { 773,  4,  1,  4,  499,  0, 0x6ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #773 = BINSRI_D
4883
  { 774,  4,  1,  4,  499,  0, 0x6ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr },  // Inst #774 = BINSRI_H
4884
  { 775,  4,  1,  4,  499,  0, 0x6ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr },  // Inst #775 = BINSRI_W
4885
  { 776,  4,  1,  4,  499,  0, 0x6ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr },  // Inst #776 = BINSR_B
4886
  { 777,  4,  1,  4,  499,  0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #777 = BINSR_D
4887
  { 778,  4,  1,  4,  499,  0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #778 = BINSR_H
4888
  { 779,  4,  1,  4,  499,  0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #779 = BINSR_W
4889
  { 780,  2,  1,  4,  713,  0, 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #780 = BITREV
4890
  { 781,  2,  1,  4,  860,  0, 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #781 = BITREV_MM
4891
  { 782,  2,  1,  4,  54, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #782 = BITSWAP
4892
  { 783,  2,  1,  4,  54, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #783 = BITSWAP_MMR6
4893
  { 784,  2,  0,  4,  371,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo92, -1 ,nullptr },  // Inst #784 = BLEZ
4894
  { 785,  2,  0,  4,  51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo93, -1 ,nullptr },  // Inst #785 = BLEZ64