Coverage Report

Created: 2018-09-17 19:50

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Mips/MipsGenInstrInfo.inc
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1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Instruction Enum Values and Descriptors                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_INSTRINFO_ENUM
10
#undef GET_INSTRINFO_ENUM
11
namespace llvm {
12
13
namespace Mips {
14
  enum {
15
    PHI = 0,
16
    INLINEASM = 1,
17
    CFI_INSTRUCTION = 2,
18
    EH_LABEL  = 3,
19
    GC_LABEL  = 4,
20
    ANNOTATION_LABEL  = 5,
21
    KILL  = 6,
22
    EXTRACT_SUBREG  = 7,
23
    INSERT_SUBREG = 8,
24
    IMPLICIT_DEF  = 9,
25
    SUBREG_TO_REG = 10,
26
    COPY_TO_REGCLASS  = 11,
27
    DBG_VALUE = 12,
28
    DBG_LABEL = 13,
29
    REG_SEQUENCE  = 14,
30
    COPY  = 15,
31
    BUNDLE  = 16,
32
    LIFETIME_START  = 17,
33
    LIFETIME_END  = 18,
34
    STACKMAP  = 19,
35
    FENTRY_CALL = 20,
36
    PATCHPOINT  = 21,
37
    LOAD_STACK_GUARD  = 22,
38
    STATEPOINT  = 23,
39
    LOCAL_ESCAPE  = 24,
40
    FAULTING_OP = 25,
41
    PATCHABLE_OP  = 26,
42
    PATCHABLE_FUNCTION_ENTER  = 27,
43
    PATCHABLE_RET = 28,
44
    PATCHABLE_FUNCTION_EXIT = 29,
45
    PATCHABLE_TAIL_CALL = 30,
46
    PATCHABLE_EVENT_CALL  = 31,
47
    PATCHABLE_TYPED_EVENT_CALL  = 32,
48
    ICALL_BRANCH_FUNNEL = 33,
49
    G_ADD = 34,
50
    G_SUB = 35,
51
    G_MUL = 36,
52
    G_SDIV  = 37,
53
    G_UDIV  = 38,
54
    G_SREM  = 39,
55
    G_UREM  = 40,
56
    G_AND = 41,
57
    G_OR  = 42,
58
    G_XOR = 43,
59
    G_IMPLICIT_DEF  = 44,
60
    G_PHI = 45,
61
    G_FRAME_INDEX = 46,
62
    G_GLOBAL_VALUE  = 47,
63
    G_EXTRACT = 48,
64
    G_UNMERGE_VALUES  = 49,
65
    G_INSERT  = 50,
66
    G_MERGE_VALUES  = 51,
67
    G_PTRTOINT  = 52,
68
    G_INTTOPTR  = 53,
69
    G_BITCAST = 54,
70
    G_INTRINSIC_TRUNC = 55,
71
    G_INTRINSIC_ROUND = 56,
72
    G_LOAD  = 57,
73
    G_SEXTLOAD  = 58,
74
    G_ZEXTLOAD  = 59,
75
    G_STORE = 60,
76
    G_ATOMIC_CMPXCHG_WITH_SUCCESS = 61,
77
    G_ATOMIC_CMPXCHG  = 62,
78
    G_ATOMICRMW_XCHG  = 63,
79
    G_ATOMICRMW_ADD = 64,
80
    G_ATOMICRMW_SUB = 65,
81
    G_ATOMICRMW_AND = 66,
82
    G_ATOMICRMW_NAND  = 67,
83
    G_ATOMICRMW_OR  = 68,
84
    G_ATOMICRMW_XOR = 69,
85
    G_ATOMICRMW_MAX = 70,
86
    G_ATOMICRMW_MIN = 71,
87
    G_ATOMICRMW_UMAX  = 72,
88
    G_ATOMICRMW_UMIN  = 73,
89
    G_BRCOND  = 74,
90
    G_BRINDIRECT  = 75,
91
    G_INTRINSIC = 76,
92
    G_INTRINSIC_W_SIDE_EFFECTS  = 77,
93
    G_ANYEXT  = 78,
94
    G_TRUNC = 79,
95
    G_CONSTANT  = 80,
96
    G_FCONSTANT = 81,
97
    G_VASTART = 82,
98
    G_VAARG = 83,
99
    G_SEXT  = 84,
100
    G_ZEXT  = 85,
101
    G_SHL = 86,
102
    G_LSHR  = 87,
103
    G_ASHR  = 88,
104
    G_ICMP  = 89,
105
    G_FCMP  = 90,
106
    G_SELECT  = 91,
107
    G_UADDO = 92,
108
    G_UADDE = 93,
109
    G_USUBO = 94,
110
    G_USUBE = 95,
111
    G_SADDO = 96,
112
    G_SADDE = 97,
113
    G_SSUBO = 98,
114
    G_SSUBE = 99,
115
    G_UMULO = 100,
116
    G_SMULO = 101,
117
    G_UMULH = 102,
118
    G_SMULH = 103,
119
    G_FADD  = 104,
120
    G_FSUB  = 105,
121
    G_FMUL  = 106,
122
    G_FMA = 107,
123
    G_FDIV  = 108,
124
    G_FREM  = 109,
125
    G_FPOW  = 110,
126
    G_FEXP  = 111,
127
    G_FEXP2 = 112,
128
    G_FLOG  = 113,
129
    G_FLOG2 = 114,
130
    G_FNEG  = 115,
131
    G_FPEXT = 116,
132
    G_FPTRUNC = 117,
133
    G_FPTOSI  = 118,
134
    G_FPTOUI  = 119,
135
    G_SITOFP  = 120,
136
    G_UITOFP  = 121,
137
    G_FABS  = 122,
138
    G_GEP = 123,
139
    G_PTR_MASK  = 124,
140
    G_BR  = 125,
141
    G_INSERT_VECTOR_ELT = 126,
142
    G_EXTRACT_VECTOR_ELT  = 127,
143
    G_SHUFFLE_VECTOR  = 128,
144
    G_CTTZ  = 129,
145
    G_CTTZ_ZERO_UNDEF = 130,
146
    G_CTLZ  = 131,
147
    G_CTLZ_ZERO_UNDEF = 132,
148
    G_CTPOP = 133,
149
    G_BSWAP = 134,
150
    G_ADDRSPACE_CAST  = 135,
151
    G_BLOCK_ADDR  = 136,
152
    ABSMacro  = 137,
153
    ADJCALLSTACKDOWN  = 138,
154
    ADJCALLSTACKUP  = 139,
155
    AND_V_D_PSEUDO  = 140,
156
    AND_V_H_PSEUDO  = 141,
157
    AND_V_W_PSEUDO  = 142,
158
    ATOMIC_CMP_SWAP_I16 = 143,
159
    ATOMIC_CMP_SWAP_I16_POSTRA  = 144,
160
    ATOMIC_CMP_SWAP_I32 = 145,
161
    ATOMIC_CMP_SWAP_I32_POSTRA  = 146,
162
    ATOMIC_CMP_SWAP_I64 = 147,
163
    ATOMIC_CMP_SWAP_I64_POSTRA  = 148,
164
    ATOMIC_CMP_SWAP_I8  = 149,
165
    ATOMIC_CMP_SWAP_I8_POSTRA = 150,
166
    ATOMIC_LOAD_ADD_I16 = 151,
167
    ATOMIC_LOAD_ADD_I16_POSTRA  = 152,
168
    ATOMIC_LOAD_ADD_I32 = 153,
169
    ATOMIC_LOAD_ADD_I32_POSTRA  = 154,
170
    ATOMIC_LOAD_ADD_I64 = 155,
171
    ATOMIC_LOAD_ADD_I64_POSTRA  = 156,
172
    ATOMIC_LOAD_ADD_I8  = 157,
173
    ATOMIC_LOAD_ADD_I8_POSTRA = 158,
174
    ATOMIC_LOAD_AND_I16 = 159,
175
    ATOMIC_LOAD_AND_I16_POSTRA  = 160,
176
    ATOMIC_LOAD_AND_I32 = 161,
177
    ATOMIC_LOAD_AND_I32_POSTRA  = 162,
178
    ATOMIC_LOAD_AND_I64 = 163,
179
    ATOMIC_LOAD_AND_I64_POSTRA  = 164,
180
    ATOMIC_LOAD_AND_I8  = 165,
181
    ATOMIC_LOAD_AND_I8_POSTRA = 166,
182
    ATOMIC_LOAD_NAND_I16  = 167,
183
    ATOMIC_LOAD_NAND_I16_POSTRA = 168,
184
    ATOMIC_LOAD_NAND_I32  = 169,
185
    ATOMIC_LOAD_NAND_I32_POSTRA = 170,
186
    ATOMIC_LOAD_NAND_I64  = 171,
187
    ATOMIC_LOAD_NAND_I64_POSTRA = 172,
188
    ATOMIC_LOAD_NAND_I8 = 173,
189
    ATOMIC_LOAD_NAND_I8_POSTRA  = 174,
190
    ATOMIC_LOAD_OR_I16  = 175,
191
    ATOMIC_LOAD_OR_I16_POSTRA = 176,
192
    ATOMIC_LOAD_OR_I32  = 177,
193
    ATOMIC_LOAD_OR_I32_POSTRA = 178,
194
    ATOMIC_LOAD_OR_I64  = 179,
195
    ATOMIC_LOAD_OR_I64_POSTRA = 180,
196
    ATOMIC_LOAD_OR_I8 = 181,
197
    ATOMIC_LOAD_OR_I8_POSTRA  = 182,
198
    ATOMIC_LOAD_SUB_I16 = 183,
199
    ATOMIC_LOAD_SUB_I16_POSTRA  = 184,
200
    ATOMIC_LOAD_SUB_I32 = 185,
201
    ATOMIC_LOAD_SUB_I32_POSTRA  = 186,
202
    ATOMIC_LOAD_SUB_I64 = 187,
203
    ATOMIC_LOAD_SUB_I64_POSTRA  = 188,
204
    ATOMIC_LOAD_SUB_I8  = 189,
205
    ATOMIC_LOAD_SUB_I8_POSTRA = 190,
206
    ATOMIC_LOAD_XOR_I16 = 191,
207
    ATOMIC_LOAD_XOR_I16_POSTRA  = 192,
208
    ATOMIC_LOAD_XOR_I32 = 193,
209
    ATOMIC_LOAD_XOR_I32_POSTRA  = 194,
210
    ATOMIC_LOAD_XOR_I64 = 195,
211
    ATOMIC_LOAD_XOR_I64_POSTRA  = 196,
212
    ATOMIC_LOAD_XOR_I8  = 197,
213
    ATOMIC_LOAD_XOR_I8_POSTRA = 198,
214
    ATOMIC_SWAP_I16 = 199,
215
    ATOMIC_SWAP_I16_POSTRA  = 200,
216
    ATOMIC_SWAP_I32 = 201,
217
    ATOMIC_SWAP_I32_POSTRA  = 202,
218
    ATOMIC_SWAP_I64 = 203,
219
    ATOMIC_SWAP_I64_POSTRA  = 204,
220
    ATOMIC_SWAP_I8  = 205,
221
    ATOMIC_SWAP_I8_POSTRA = 206,
222
    B = 207,
223
    BAL_BR  = 208,
224
    BAL_BR_MM = 209,
225
    BEQLImmMacro  = 210,
226
    BGE = 211,
227
    BGEImmMacro = 212,
228
    BGEL  = 213,
229
    BGELImmMacro  = 214,
230
    BGEU  = 215,
231
    BGEUImmMacro  = 216,
232
    BGEUL = 217,
233
    BGEULImmMacro = 218,
234
    BGT = 219,
235
    BGTImmMacro = 220,
236
    BGTL  = 221,
237
    BGTLImmMacro  = 222,
238
    BGTU  = 223,
239
    BGTUImmMacro  = 224,
240
    BGTUL = 225,
241
    BGTULImmMacro = 226,
242
    BLE = 227,
243
    BLEImmMacro = 228,
244
    BLEL  = 229,
245
    BLELImmMacro  = 230,
246
    BLEU  = 231,
247
    BLEUImmMacro  = 232,
248
    BLEUL = 233,
249
    BLEULImmMacro = 234,
250
    BLT = 235,
251
    BLTImmMacro = 236,
252
    BLTL  = 237,
253
    BLTLImmMacro  = 238,
254
    BLTU  = 239,
255
    BLTUImmMacro  = 240,
256
    BLTUL = 241,
257
    BLTULImmMacro = 242,
258
    BNELImmMacro  = 243,
259
    BPOSGE32_PSEUDO = 244,
260
    BSEL_D_PSEUDO = 245,
261
    BSEL_FD_PSEUDO  = 246,
262
    BSEL_FW_PSEUDO  = 247,
263
    BSEL_H_PSEUDO = 248,
264
    BSEL_W_PSEUDO = 249,
265
    B_MM  = 250,
266
    B_MMR6_Pseudo = 251,
267
    B_MM_Pseudo = 252,
268
    BeqImm  = 253,
269
    BneImm  = 254,
270
    BteqzT8CmpX16 = 255,
271
    BteqzT8CmpiX16  = 256,
272
    BteqzT8SltX16 = 257,
273
    BteqzT8SltiX16  = 258,
274
    BteqzT8SltiuX16 = 259,
275
    BteqzT8SltuX16  = 260,
276
    BtnezT8CmpX16 = 261,
277
    BtnezT8CmpiX16  = 262,
278
    BtnezT8SltX16 = 263,
279
    BtnezT8SltiX16  = 264,
280
    BtnezT8SltiuX16 = 265,
281
    BtnezT8SltuX16  = 266,
282
    BuildPairF64  = 267,
283
    BuildPairF64_64 = 268,
284
    CFTC1 = 269,
285
    CONSTPOOL_ENTRY = 270,
286
    COPY_FD_PSEUDO  = 271,
287
    COPY_FW_PSEUDO  = 272,
288
    CTTC1 = 273,
289
    Constant32  = 274,
290
    DMULImmMacro  = 275,
291
    DMULMacro = 276,
292
    DMULOMacro  = 277,
293
    DMULOUMacro = 278,
294
    DROL  = 279,
295
    DROLImm = 280,
296
    DROR  = 281,
297
    DRORImm = 282,
298
    DSDivIMacro = 283,
299
    DSDivMacro  = 284,
300
    DSRemIMacro = 285,
301
    DSRemMacro  = 286,
302
    DUDivIMacro = 287,
303
    DUDivMacro  = 288,
304
    DURemIMacro = 289,
305
    DURemMacro  = 290,
306
    ERet  = 291,
307
    ExtractElementF64 = 292,
308
    ExtractElementF64_64  = 293,
309
    FABS_D  = 294,
310
    FABS_W  = 295,
311
    FEXP2_D_1_PSEUDO  = 296,
312
    FEXP2_W_1_PSEUDO  = 297,
313
    FILL_FD_PSEUDO  = 298,
314
    FILL_FW_PSEUDO  = 299,
315
    GotPrologue16 = 300,
316
    INSERT_B_VIDX64_PSEUDO  = 301,
317
    INSERT_B_VIDX_PSEUDO  = 302,
318
    INSERT_D_VIDX64_PSEUDO  = 303,
319
    INSERT_D_VIDX_PSEUDO  = 304,
320
    INSERT_FD_PSEUDO  = 305,
321
    INSERT_FD_VIDX64_PSEUDO = 306,
322
    INSERT_FD_VIDX_PSEUDO = 307,
323
    INSERT_FW_PSEUDO  = 308,
324
    INSERT_FW_VIDX64_PSEUDO = 309,
325
    INSERT_FW_VIDX_PSEUDO = 310,
326
    INSERT_H_VIDX64_PSEUDO  = 311,
327
    INSERT_H_VIDX_PSEUDO  = 312,
328
    INSERT_W_VIDX64_PSEUDO  = 313,
329
    INSERT_W_VIDX_PSEUDO  = 314,
330
    JALR64Pseudo  = 315,
331
    JALRHB64Pseudo  = 316,
332
    JALRHBPseudo  = 317,
333
    JALRPseudo  = 318,
334
    JalOneReg = 319,
335
    JalTwoReg = 320,
336
    LDMacro = 321,
337
    LD_F16  = 322,
338
    LOAD_ACC128 = 323,
339
    LOAD_ACC64  = 324,
340
    LOAD_ACC64DSP = 325,
341
    LOAD_CCOND_DSP  = 326,
342
    LONG_BRANCH_ADDiu = 327,
343
    LONG_BRANCH_DADDiu  = 328,
344
    LONG_BRANCH_LUi = 329,
345
    LWM_MM  = 330,
346
    LoadAddrImm32 = 331,
347
    LoadAddrImm64 = 332,
348
    LoadAddrReg32 = 333,
349
    LoadAddrReg64 = 334,
350
    LoadImm32 = 335,
351
    LoadImm64 = 336,
352
    LoadImmDoubleFGR  = 337,
353
    LoadImmDoubleFGR_32 = 338,
354
    LoadImmDoubleGPR  = 339,
355
    LoadImmSingleFGR  = 340,
356
    LoadImmSingleGPR  = 341,
357
    LwConstant32  = 342,
358
    MFTACX  = 343,
359
    MFTC0 = 344,
360
    MFTC1 = 345,
361
    MFTDSP  = 346,
362
    MFTGPR  = 347,
363
    MFTHC1  = 348,
364
    MFTHI = 349,
365
    MFTLO = 350,
366
    MIPSeh_return32 = 351,
367
    MIPSeh_return64 = 352,
368
    MSA_FP_EXTEND_D_PSEUDO  = 353,
369
    MSA_FP_EXTEND_W_PSEUDO  = 354,
370
    MSA_FP_ROUND_D_PSEUDO = 355,
371
    MSA_FP_ROUND_W_PSEUDO = 356,
372
    MTTACX  = 357,
373
    MTTC0 = 358,
374
    MTTC1 = 359,
375
    MTTDSP  = 360,
376
    MTTGPR  = 361,
377
    MTTHC1  = 362,
378
    MTTHI = 363,
379
    MTTLO = 364,
380
    MULImmMacro = 365,
381
    MULOMacro = 366,
382
    MULOUMacro  = 367,
383
    MultRxRy16  = 368,
384
    MultRxRyRz16  = 369,
385
    MultuRxRy16 = 370,
386
    MultuRxRyRz16 = 371,
387
    NOP = 372,
388
    NORImm  = 373,
389
    NORImm64  = 374,
390
    NOR_V_D_PSEUDO  = 375,
391
    NOR_V_H_PSEUDO  = 376,
392
    NOR_V_W_PSEUDO  = 377,
393
    OR_V_D_PSEUDO = 378,
394
    OR_V_H_PSEUDO = 379,
395
    OR_V_W_PSEUDO = 380,
396
    PseudoCMPU_EQ_QB  = 381,
397
    PseudoCMPU_LE_QB  = 382,
398
    PseudoCMPU_LT_QB  = 383,
399
    PseudoCMP_EQ_PH = 384,
400
    PseudoCMP_LE_PH = 385,
401
    PseudoCMP_LT_PH = 386,
402
    PseudoCVT_D32_W = 387,
403
    PseudoCVT_D64_L = 388,
404
    PseudoCVT_D64_W = 389,
405
    PseudoCVT_S_L = 390,
406
    PseudoCVT_S_W = 391,
407
    PseudoDMULT = 392,
408
    PseudoDMULTu  = 393,
409
    PseudoDSDIV = 394,
410
    PseudoDUDIV = 395,
411
    PseudoIndirectBranch  = 396,
412
    PseudoIndirectBranch64  = 397,
413
    PseudoIndirectBranch64R6  = 398,
414
    PseudoIndirectBranchR6  = 399,
415
    PseudoIndirectBranch_MM = 400,
416
    PseudoIndirectBranch_MMR6 = 401,
417
    PseudoIndirectHazardBranch  = 402,
418
    PseudoIndirectHazardBranch64  = 403,
419
    PseudoIndrectHazardBranch64R6 = 404,
420
    PseudoIndrectHazardBranchR6 = 405,
421
    PseudoMADD  = 406,
422
    PseudoMADDU = 407,
423
    PseudoMADDU_MM  = 408,
424
    PseudoMADD_MM = 409,
425
    PseudoMFHI  = 410,
426
    PseudoMFHI64  = 411,
427
    PseudoMFHI_MM = 412,
428
    PseudoMFLO  = 413,
429
    PseudoMFLO64  = 414,
430
    PseudoMFLO_MM = 415,
431
    PseudoMSUB  = 416,
432
    PseudoMSUBU = 417,
433
    PseudoMSUBU_MM  = 418,
434
    PseudoMSUB_MM = 419,
435
    PseudoMTLOHI  = 420,
436
    PseudoMTLOHI64  = 421,
437
    PseudoMTLOHI_DSP  = 422,
438
    PseudoMTLOHI_MM = 423,
439
    PseudoMULT  = 424,
440
    PseudoMULT_MM = 425,
441
    PseudoMULTu = 426,
442
    PseudoMULTu_MM  = 427,
443
    PseudoPICK_PH = 428,
444
    PseudoPICK_QB = 429,
445
    PseudoReturn  = 430,
446
    PseudoReturn64  = 431,
447
    PseudoSDIV  = 432,
448
    PseudoSELECTFP_F_D32  = 433,
449
    PseudoSELECTFP_F_D64  = 434,
450
    PseudoSELECTFP_F_I  = 435,
451
    PseudoSELECTFP_F_I64  = 436,
452
    PseudoSELECTFP_F_S  = 437,
453
    PseudoSELECTFP_T_D32  = 438,
454
    PseudoSELECTFP_T_D64  = 439,
455
    PseudoSELECTFP_T_I  = 440,
456
    PseudoSELECTFP_T_I64  = 441,
457
    PseudoSELECTFP_T_S  = 442,
458
    PseudoSELECT_D32  = 443,
459
    PseudoSELECT_D64  = 444,
460
    PseudoSELECT_I  = 445,
461
    PseudoSELECT_I64  = 446,
462
    PseudoSELECT_S  = 447,
463
    PseudoTRUNC_W_D = 448,
464
    PseudoTRUNC_W_D32 = 449,
465
    PseudoTRUNC_W_S = 450,
466
    PseudoUDIV  = 451,
467
    ROL = 452,
468
    ROLImm  = 453,
469
    ROR = 454,
470
    RORImm  = 455,
471
    RetRA = 456,
472
    RetRA16 = 457,
473
    SDIV_MM_Pseudo  = 458,
474
    SDMacro = 459,
475
    SDivIMacro  = 460,
476
    SDivMacro = 461,
477
    SEQIMacro = 462,
478
    SEQMacro  = 463,
479
    SLTImm64  = 464,
480
    SLTUImm64 = 465,
481
    SNZ_B_PSEUDO  = 466,
482
    SNZ_D_PSEUDO  = 467,
483
    SNZ_H_PSEUDO  = 468,
484
    SNZ_V_PSEUDO  = 469,
485
    SNZ_W_PSEUDO  = 470,
486
    SRemIMacro  = 471,
487
    SRemMacro = 472,
488
    STORE_ACC128  = 473,
489
    STORE_ACC64 = 474,
490
    STORE_ACC64DSP  = 475,
491
    STORE_CCOND_DSP = 476,
492
    ST_F16  = 477,
493
    SWM_MM  = 478,
494
    SZ_B_PSEUDO = 479,
495
    SZ_D_PSEUDO = 480,
496
    SZ_H_PSEUDO = 481,
497
    SZ_V_PSEUDO = 482,
498
    SZ_W_PSEUDO = 483,
499
    SelBeqZ = 484,
500
    SelBneZ = 485,
501
    SelTBteqZCmp  = 486,
502
    SelTBteqZCmpi = 487,
503
    SelTBteqZSlt  = 488,
504
    SelTBteqZSlti = 489,
505
    SelTBteqZSltiu  = 490,
506
    SelTBteqZSltu = 491,
507
    SelTBtneZCmp  = 492,
508
    SelTBtneZCmpi = 493,
509
    SelTBtneZSlt  = 494,
510
    SelTBtneZSlti = 495,
511
    SelTBtneZSltiu  = 496,
512
    SelTBtneZSltu = 497,
513
    SltCCRxRy16 = 498,
514
    SltiCCRxImmX16  = 499,
515
    SltiuCCRxImmX16 = 500,
516
    SltuCCRxRy16  = 501,
517
    SltuRxRyRz16  = 502,
518
    TAILCALL  = 503,
519
    TAILCALL64R6REG = 504,
520
    TAILCALLHB64R6REG = 505,
521
    TAILCALLHBR6REG = 506,
522
    TAILCALLR6REG = 507,
523
    TAILCALLREG = 508,
524
    TAILCALLREG64 = 509,
525
    TAILCALLREGHB = 510,
526
    TAILCALLREGHB64 = 511,
527
    TAILCALLREG_MM  = 512,
528
    TAILCALLREG_MMR6  = 513,
529
    TAILCALL_MM = 514,
530
    TAILCALL_MMR6 = 515,
531
    TRAP  = 516,
532
    TRAP_MM = 517,
533
    UDIV_MM_Pseudo  = 518,
534
    UDivIMacro  = 519,
535
    UDivMacro = 520,
536
    URemIMacro  = 521,
537
    URemMacro = 522,
538
    Ulh = 523,
539
    Ulhu  = 524,
540
    Ulw = 525,
541
    Ush = 526,
542
    Usw = 527,
543
    XOR_V_D_PSEUDO  = 528,
544
    XOR_V_H_PSEUDO  = 529,
545
    XOR_V_W_PSEUDO  = 530,
546
    ABSQ_S_PH = 531,
547
    ABSQ_S_PH_MM  = 532,
548
    ABSQ_S_QB = 533,
549
    ABSQ_S_QB_MMR2  = 534,
550
    ABSQ_S_W  = 535,
551
    ABSQ_S_W_MM = 536,
552
    ADD = 537,
553
    ADDIUPC = 538,
554
    ADDIUPC_MM  = 539,
555
    ADDIUPC_MMR6  = 540,
556
    ADDIUR1SP_MM  = 541,
557
    ADDIUR2_MM  = 542,
558
    ADDIUS5_MM  = 543,
559
    ADDIUSP_MM  = 544,
560
    ADDIU_MMR6  = 545,
561
    ADDQH_PH  = 546,
562
    ADDQH_PH_MMR2 = 547,
563
    ADDQH_R_PH  = 548,
564
    ADDQH_R_PH_MMR2 = 549,
565
    ADDQH_R_W = 550,
566
    ADDQH_R_W_MMR2  = 551,
567
    ADDQH_W = 552,
568
    ADDQH_W_MMR2  = 553,
569
    ADDQ_PH = 554,
570
    ADDQ_PH_MM  = 555,
571
    ADDQ_S_PH = 556,
572
    ADDQ_S_PH_MM  = 557,
573
    ADDQ_S_W  = 558,
574
    ADDQ_S_W_MM = 559,
575
    ADDSC = 560,
576
    ADDSC_MM  = 561,
577
    ADDS_A_B  = 562,
578
    ADDS_A_D  = 563,
579
    ADDS_A_H  = 564,
580
    ADDS_A_W  = 565,
581
    ADDS_S_B  = 566,
582
    ADDS_S_D  = 567,
583
    ADDS_S_H  = 568,
584
    ADDS_S_W  = 569,
585
    ADDS_U_B  = 570,
586
    ADDS_U_D  = 571,
587
    ADDS_U_H  = 572,
588
    ADDS_U_W  = 573,
589
    ADDU16_MM = 574,
590
    ADDU16_MMR6 = 575,
591
    ADDUH_QB  = 576,
592
    ADDUH_QB_MMR2 = 577,
593
    ADDUH_R_QB  = 578,
594
    ADDUH_R_QB_MMR2 = 579,
595
    ADDU_MMR6 = 580,
596
    ADDU_PH = 581,
597
    ADDU_PH_MMR2  = 582,
598
    ADDU_QB = 583,
599
    ADDU_QB_MM  = 584,
600
    ADDU_S_PH = 585,
601
    ADDU_S_PH_MMR2  = 586,
602
    ADDU_S_QB = 587,
603
    ADDU_S_QB_MM  = 588,
604
    ADDVI_B = 589,
605
    ADDVI_D = 590,
606
    ADDVI_H = 591,
607
    ADDVI_W = 592,
608
    ADDV_B  = 593,
609
    ADDV_D  = 594,
610
    ADDV_H  = 595,
611
    ADDV_W  = 596,
612
    ADDWC = 597,
613
    ADDWC_MM  = 598,
614
    ADD_A_B = 599,
615
    ADD_A_D = 600,
616
    ADD_A_H = 601,
617
    ADD_A_W = 602,
618
    ADD_MM  = 603,
619
    ADD_MMR6  = 604,
620
    ADDi  = 605,
621
    ADDi_MM = 606,
622
    ADDiu = 607,
623
    ADDiu_MM  = 608,
624
    ADDu  = 609,
625
    ADDu_MM = 610,
626
    ALIGN = 611,
627
    ALIGN_MMR6  = 612,
628
    ALUIPC  = 613,
629
    ALUIPC_MMR6 = 614,
630
    AND = 615,
631
    AND16_MM  = 616,
632
    AND16_MMR6  = 617,
633
    AND64 = 618,
634
    ANDI16_MM = 619,
635
    ANDI16_MMR6 = 620,
636
    ANDI_B  = 621,
637
    ANDI_MMR6 = 622,
638
    AND_MM  = 623,
639
    AND_MMR6  = 624,
640
    AND_V = 625,
641
    ANDi  = 626,
642
    ANDi64  = 627,
643
    ANDi_MM = 628,
644
    APPEND  = 629,
645
    APPEND_MMR2 = 630,
646
    ASUB_S_B  = 631,
647
    ASUB_S_D  = 632,
648
    ASUB_S_H  = 633,
649
    ASUB_S_W  = 634,
650
    ASUB_U_B  = 635,
651
    ASUB_U_D  = 636,
652
    ASUB_U_H  = 637,
653
    ASUB_U_W  = 638,
654
    AUI = 639,
655
    AUIPC = 640,
656
    AUIPC_MMR6  = 641,
657
    AUI_MMR6  = 642,
658
    AVER_S_B  = 643,
659
    AVER_S_D  = 644,
660
    AVER_S_H  = 645,
661
    AVER_S_W  = 646,
662
    AVER_U_B  = 647,
663
    AVER_U_D  = 648,
664
    AVER_U_H  = 649,
665
    AVER_U_W  = 650,
666
    AVE_S_B = 651,
667
    AVE_S_D = 652,
668
    AVE_S_H = 653,
669
    AVE_S_W = 654,
670
    AVE_U_B = 655,
671
    AVE_U_D = 656,
672
    AVE_U_H = 657,
673
    AVE_U_W = 658,
674
    AddiuRxImmX16 = 659,
675
    AddiuRxPcImmX16 = 660,
676
    AddiuRxRxImm16  = 661,
677
    AddiuRxRxImmX16 = 662,
678
    AddiuRxRyOffMemX16  = 663,
679
    AddiuSpImm16  = 664,
680
    AddiuSpImmX16 = 665,
681
    AdduRxRyRz16  = 666,
682
    AndRxRxRy16 = 667,
683
    B16_MM  = 668,
684
    BADDu = 669,
685
    BAL = 670,
686
    BALC  = 671,
687
    BALC_MMR6 = 672,
688
    BALIGN  = 673,
689
    BALIGN_MMR2 = 674,
690
    BBIT0 = 675,
691
    BBIT032 = 676,
692
    BBIT1 = 677,
693
    BBIT132 = 678,
694
    BC  = 679,
695
    BC16_MMR6 = 680,
696
    BC1EQZ  = 681,
697
    BC1EQZC_MMR6  = 682,
698
    BC1F  = 683,
699
    BC1FL = 684,
700
    BC1F_MM = 685,
701
    BC1NEZ  = 686,
702
    BC1NEZC_MMR6  = 687,
703
    BC1T  = 688,
704
    BC1TL = 689,
705
    BC1T_MM = 690,
706
    BC2EQZ  = 691,
707
    BC2EQZC_MMR6  = 692,
708
    BC2NEZ  = 693,
709
    BC2NEZC_MMR6  = 694,
710
    BCLRI_B = 695,
711
    BCLRI_D = 696,
712
    BCLRI_H = 697,
713
    BCLRI_W = 698,
714
    BCLR_B  = 699,
715
    BCLR_D  = 700,
716
    BCLR_H  = 701,
717
    BCLR_W  = 702,
718
    BC_MMR6 = 703,
719
    BEQ = 704,
720
    BEQ64 = 705,
721
    BEQC  = 706,
722
    BEQC64  = 707,
723
    BEQC_MMR6 = 708,
724
    BEQL  = 709,
725
    BEQZ16_MM = 710,
726
    BEQZALC = 711,
727
    BEQZALC_MMR6  = 712,
728
    BEQZC = 713,
729
    BEQZC16_MMR6  = 714,
730
    BEQZC64 = 715,
731
    BEQZC_MM  = 716,
732
    BEQZC_MMR6  = 717,
733
    BEQ_MM  = 718,
734
    BGEC  = 719,
735
    BGEC64  = 720,
736
    BGEC_MMR6 = 721,
737
    BGEUC = 722,
738
    BGEUC64 = 723,
739
    BGEUC_MMR6  = 724,
740
    BGEZ  = 725,
741
    BGEZ64  = 726,
742
    BGEZAL  = 727,
743
    BGEZALC = 728,
744
    BGEZALC_MMR6  = 729,
745
    BGEZALL = 730,
746
    BGEZALS_MM  = 731,
747
    BGEZAL_MM = 732,
748
    BGEZC = 733,
749
    BGEZC64 = 734,
750
    BGEZC_MMR6  = 735,
751
    BGEZL = 736,
752
    BGEZ_MM = 737,
753
    BGTZ  = 738,
754
    BGTZ64  = 739,
755
    BGTZALC = 740,
756
    BGTZALC_MMR6  = 741,
757
    BGTZC = 742,
758
    BGTZC64 = 743,
759
    BGTZC_MMR6  = 744,
760
    BGTZL = 745,
761
    BGTZ_MM = 746,
762
    BINSLI_B  = 747,
763
    BINSLI_D  = 748,
764
    BINSLI_H  = 749,
765
    BINSLI_W  = 750,
766
    BINSL_B = 751,
767
    BINSL_D = 752,
768
    BINSL_H = 753,
769
    BINSL_W = 754,
770
    BINSRI_B  = 755,
771
    BINSRI_D  = 756,
772
    BINSRI_H  = 757,
773
    BINSRI_W  = 758,
774
    BINSR_B = 759,
775
    BINSR_D = 760,
776
    BINSR_H = 761,
777
    BINSR_W = 762,
778
    BITREV  = 763,
779
    BITREV_MM = 764,
780
    BITSWAP = 765,
781
    BITSWAP_MMR6  = 766,
782
    BLEZ  = 767,
783
    BLEZ64  = 768,
784
    BLEZALC = 769,
785
    BLEZALC_MMR6  = 770,
786
    BLEZC = 771,
787
    BLEZC64 = 772,
788
    BLEZC_MMR6  = 773,
789
    BLEZL = 774,
790
    BLEZ_MM = 775,
791
    BLTC  = 776,
792
    BLTC64  = 777,
793
    BLTC_MMR6 = 778,
794
    BLTUC = 779,
795
    BLTUC64 = 780,
796
    BLTUC_MMR6  = 781,
797
    BLTZ  = 782,
798
    BLTZ64  = 783,
799
    BLTZAL  = 784,
800
    BLTZALC = 785,
801
    BLTZALC_MMR6  = 786,
802
    BLTZALL = 787,
803
    BLTZALS_MM  = 788,
804
    BLTZAL_MM = 789,
805
    BLTZC = 790,
806
    BLTZC64 = 791,
807
    BLTZC_MMR6  = 792,
808
    BLTZL = 793,
809
    BLTZ_MM = 794,
810
    BMNZI_B = 795,
811
    BMNZ_V  = 796,
812
    BMZI_B  = 797,
813
    BMZ_V = 798,
814
    BNE = 799,
815
    BNE64 = 800,
816
    BNEC  = 801,
817
    BNEC64  = 802,
818
    BNEC_MMR6 = 803,
819
    BNEGI_B = 804,
820
    BNEGI_D = 805,
821
    BNEGI_H = 806,
822
    BNEGI_W = 807,
823
    BNEG_B  = 808,
824
    BNEG_D  = 809,
825
    BNEG_H  = 810,
826
    BNEG_W  = 811,
827
    BNEL  = 812,
828
    BNEZ16_MM = 813,
829
    BNEZALC = 814,
830
    BNEZALC_MMR6  = 815,
831
    BNEZC = 816,
832
    BNEZC16_MMR6  = 817,
833
    BNEZC64 = 818,
834
    BNEZC_MM  = 819,
835
    BNEZC_MMR6  = 820,
836
    BNE_MM  = 821,
837
    BNVC  = 822,
838
    BNVC_MMR6 = 823,
839
    BNZ_B = 824,
840
    BNZ_D = 825,
841
    BNZ_H = 826,
842
    BNZ_V = 827,
843
    BNZ_W = 828,
844
    BOVC  = 829,
845
    BOVC_MMR6 = 830,
846
    BPOSGE32  = 831,
847
    BPOSGE32C_MMR3  = 832,
848
    BPOSGE32_MM = 833,
849
    BREAK = 834,
850
    BREAK16_MM  = 835,
851
    BREAK16_MMR6  = 836,
852
    BREAK_MM  = 837,
853
    BREAK_MMR6  = 838,
854
    BSELI_B = 839,
855
    BSEL_V  = 840,
856
    BSETI_B = 841,
857
    BSETI_D = 842,
858
    BSETI_H = 843,
859
    BSETI_W = 844,
860
    BSET_B  = 845,
861
    BSET_D  = 846,
862
    BSET_H  = 847,
863
    BSET_W  = 848,
864
    BZ_B  = 849,
865
    BZ_D  = 850,
866
    BZ_H  = 851,
867
    BZ_V  = 852,
868
    BZ_W  = 853,
869
    BeqzRxImm16 = 854,
870
    BeqzRxImmX16  = 855,
871
    Bimm16  = 856,
872
    BimmX16 = 857,
873
    BnezRxImm16 = 858,
874
    BnezRxImmX16  = 859,
875
    Break16 = 860,
876
    Bteqz16 = 861,
877
    BteqzX16  = 862,
878
    Btnez16 = 863,
879
    BtnezX16  = 864,
880
    CACHE = 865,
881
    CACHEE  = 866,
882
    CACHEE_MM = 867,
883
    CACHE_MM  = 868,
884
    CACHE_MMR6  = 869,
885
    CACHE_R6  = 870,
886
    CEIL_L_D64  = 871,
887
    CEIL_L_D_MMR6 = 872,
888
    CEIL_L_S  = 873,
889
    CEIL_L_S_MMR6 = 874,
890
    CEIL_W_D32  = 875,
891
    CEIL_W_D64  = 876,
892
    CEIL_W_D_MMR6 = 877,
893
    CEIL_W_MM = 878,
894
    CEIL_W_S  = 879,
895
    CEIL_W_S_MM = 880,
896
    CEIL_W_S_MMR6 = 881,
897
    CEQI_B  = 882,
898
    CEQI_D  = 883,
899
    CEQI_H  = 884,
900
    CEQI_W  = 885,
901
    CEQ_B = 886,
902
    CEQ_D = 887,
903
    CEQ_H = 888,
904
    CEQ_W = 889,
905
    CFC1  = 890,
906
    CFC1_MM = 891,
907
    CFC2_MM = 892,
908
    CFCMSA  = 893,
909
    CINS  = 894,
910
    CINS32  = 895,
911
    CINS64_32 = 896,
912
    CINS_i32  = 897,
913
    CLASS_D = 898,
914
    CLASS_D_MMR6  = 899,
915
    CLASS_S = 900,
916
    CLASS_S_MMR6  = 901,
917
    CLEI_S_B  = 902,
918
    CLEI_S_D  = 903,
919
    CLEI_S_H  = 904,
920
    CLEI_S_W  = 905,
921
    CLEI_U_B  = 906,
922
    CLEI_U_D  = 907,
923
    CLEI_U_H  = 908,
924
    CLEI_U_W  = 909,
925
    CLE_S_B = 910,
926
    CLE_S_D = 911,
927
    CLE_S_H = 912,
928
    CLE_S_W = 913,
929
    CLE_U_B = 914,
930
    CLE_U_D = 915,
931
    CLE_U_H = 916,
932
    CLE_U_W = 917,
933
    CLO = 918,
934
    CLO_MM  = 919,
935
    CLO_MMR6  = 920,
936
    CLO_R6  = 921,
937
    CLTI_S_B  = 922,
938
    CLTI_S_D  = 923,
939
    CLTI_S_H  = 924,
940
    CLTI_S_W  = 925,
941
    CLTI_U_B  = 926,
942
    CLTI_U_D  = 927,
943
    CLTI_U_H  = 928,
944
    CLTI_U_W  = 929,
945
    CLT_S_B = 930,
946
    CLT_S_D = 931,
947
    CLT_S_H = 932,
948
    CLT_S_W = 933,
949
    CLT_U_B = 934,
950
    CLT_U_D = 935,
951
    CLT_U_H = 936,
952
    CLT_U_W = 937,
953
    CLZ = 938,
954
    CLZ_MM  = 939,
955
    CLZ_MMR6  = 940,
956
    CLZ_R6  = 941,
957
    CMPGDU_EQ_QB  = 942,
958
    CMPGDU_EQ_QB_MMR2 = 943,
959
    CMPGDU_LE_QB  = 944,
960
    CMPGDU_LE_QB_MMR2 = 945,
961
    CMPGDU_LT_QB  = 946,
962
    CMPGDU_LT_QB_MMR2 = 947,
963
    CMPGU_EQ_QB = 948,
964
    CMPGU_EQ_QB_MM  = 949,
965
    CMPGU_LE_QB = 950,
966
    CMPGU_LE_QB_MM  = 951,
967
    CMPGU_LT_QB = 952,
968
    CMPGU_LT_QB_MM  = 953,
969
    CMPU_EQ_QB  = 954,
970
    CMPU_EQ_QB_MM = 955,
971
    CMPU_LE_QB  = 956,
972
    CMPU_LE_QB_MM = 957,
973
    CMPU_LT_QB  = 958,
974
    CMPU_LT_QB_MM = 959,
975
    CMP_AF_D_MMR6 = 960,
976
    CMP_AF_S_MMR6 = 961,
977
    CMP_EQ_D  = 962,
978
    CMP_EQ_D_MMR6 = 963,
979
    CMP_EQ_PH = 964,
980
    CMP_EQ_PH_MM  = 965,
981
    CMP_EQ_S  = 966,
982
    CMP_EQ_S_MMR6 = 967,
983
    CMP_F_D = 968,
984
    CMP_F_S = 969,
985
    CMP_LE_D  = 970,
986
    CMP_LE_D_MMR6 = 971,
987
    CMP_LE_PH = 972,
988
    CMP_LE_PH_MM  = 973,
989
    CMP_LE_S  = 974,
990
    CMP_LE_S_MMR6 = 975,
991
    CMP_LT_D  = 976,
992
    CMP_LT_D_MMR6 = 977,
993
    CMP_LT_PH = 978,
994
    CMP_LT_PH_MM  = 979,
995
    CMP_LT_S  = 980,
996
    CMP_LT_S_MMR6 = 981,
997
    CMP_SAF_D = 982,
998
    CMP_SAF_D_MMR6  = 983,
999
    CMP_SAF_S = 984,
1000
    CMP_SAF_S_MMR6  = 985,
1001
    CMP_SEQ_D = 986,
1002
    CMP_SEQ_D_MMR6  = 987,
1003
    CMP_SEQ_S = 988,
1004
    CMP_SEQ_S_MMR6  = 989,
1005
    CMP_SLE_D = 990,
1006
    CMP_SLE_D_MMR6  = 991,
1007
    CMP_SLE_S = 992,
1008
    CMP_SLE_S_MMR6  = 993,
1009
    CMP_SLT_D = 994,
1010
    CMP_SLT_D_MMR6  = 995,
1011
    CMP_SLT_S = 996,
1012
    CMP_SLT_S_MMR6  = 997,
1013
    CMP_SUEQ_D  = 998,
1014
    CMP_SUEQ_D_MMR6 = 999,
1015
    CMP_SUEQ_S  = 1000,
1016
    CMP_SUEQ_S_MMR6 = 1001,
1017
    CMP_SULE_D  = 1002,
1018
    CMP_SULE_D_MMR6 = 1003,
1019
    CMP_SULE_S  = 1004,
1020
    CMP_SULE_S_MMR6 = 1005,
1021
    CMP_SULT_D  = 1006,
1022
    CMP_SULT_D_MMR6 = 1007,
1023
    CMP_SULT_S  = 1008,
1024
    CMP_SULT_S_MMR6 = 1009,
1025
    CMP_SUN_D = 1010,
1026
    CMP_SUN_D_MMR6  = 1011,
1027
    CMP_SUN_S = 1012,
1028
    CMP_SUN_S_MMR6  = 1013,
1029
    CMP_UEQ_D = 1014,
1030
    CMP_UEQ_D_MMR6  = 1015,
1031
    CMP_UEQ_S = 1016,
1032
    CMP_UEQ_S_MMR6  = 1017,
1033
    CMP_ULE_D = 1018,
1034
    CMP_ULE_D_MMR6  = 1019,
1035
    CMP_ULE_S = 1020,
1036
    CMP_ULE_S_MMR6  = 1021,
1037
    CMP_ULT_D = 1022,
1038
    CMP_ULT_D_MMR6  = 1023,
1039
    CMP_ULT_S = 1024,
1040
    CMP_ULT_S_MMR6  = 1025,
1041
    CMP_UN_D  = 1026,
1042
    CMP_UN_D_MMR6 = 1027,
1043
    CMP_UN_S  = 1028,
1044
    CMP_UN_S_MMR6 = 1029,
1045
    COPY_S_B  = 1030,
1046
    COPY_S_D  = 1031,
1047
    COPY_S_H  = 1032,
1048
    COPY_S_W  = 1033,
1049
    COPY_U_B  = 1034,
1050
    COPY_U_H  = 1035,
1051
    COPY_U_W  = 1036,
1052
    CRC32B  = 1037,
1053
    CRC32CB = 1038,
1054
    CRC32CD = 1039,
1055
    CRC32CH = 1040,
1056
    CRC32CW = 1041,
1057
    CRC32D  = 1042,
1058
    CRC32H  = 1043,
1059
    CRC32W  = 1044,
1060
    CTC1  = 1045,
1061
    CTC1_MM = 1046,
1062
    CTC2_MM = 1047,
1063
    CTCMSA  = 1048,
1064
    CVT_D32_S = 1049,
1065
    CVT_D32_S_MM  = 1050,
1066
    CVT_D32_W = 1051,
1067
    CVT_D32_W_MM  = 1052,
1068
    CVT_D64_L = 1053,
1069
    CVT_D64_S = 1054,
1070
    CVT_D64_S_MM  = 1055,
1071
    CVT_D64_W = 1056,
1072
    CVT_D64_W_MM  = 1057,
1073
    CVT_D_L_MMR6  = 1058,
1074
    CVT_L_D64 = 1059,
1075
    CVT_L_D64_MM  = 1060,
1076
    CVT_L_D_MMR6  = 1061,
1077
    CVT_L_S = 1062,
1078
    CVT_L_S_MM  = 1063,
1079
    CVT_L_S_MMR6  = 1064,
1080
    CVT_PS_S64  = 1065,
1081
    CVT_S_D32 = 1066,
1082
    CVT_S_D32_MM  = 1067,
1083
    CVT_S_D64 = 1068,
1084
    CVT_S_D64_MM  = 1069,
1085
    CVT_S_L = 1070,
1086
    CVT_S_L_MMR6  = 1071,
1087
    CVT_S_PL64  = 1072,
1088
    CVT_S_PU64  = 1073,
1089
    CVT_S_W = 1074,
1090
    CVT_S_W_MM  = 1075,
1091
    CVT_S_W_MMR6  = 1076,
1092
    CVT_W_D32 = 1077,
1093
    CVT_W_D32_MM  = 1078,
1094
    CVT_W_D64 = 1079,
1095
    CVT_W_D64_MM  = 1080,
1096
    CVT_W_S = 1081,
1097
    CVT_W_S_MM  = 1082,
1098
    CVT_W_S_MMR6  = 1083,
1099
    C_EQ_D32  = 1084,
1100
    C_EQ_D32_MM = 1085,
1101
    C_EQ_D64  = 1086,
1102
    C_EQ_D64_MM = 1087,
1103
    C_EQ_S  = 1088,
1104
    C_EQ_S_MM = 1089,
1105
    C_F_D32 = 1090,
1106
    C_F_D32_MM  = 1091,
1107
    C_F_D64 = 1092,
1108
    C_F_D64_MM  = 1093,
1109
    C_F_S = 1094,
1110
    C_F_S_MM  = 1095,
1111
    C_LE_D32  = 1096,
1112
    C_LE_D32_MM = 1097,
1113
    C_LE_D64  = 1098,
1114
    C_LE_D64_MM = 1099,
1115
    C_LE_S  = 1100,
1116
    C_LE_S_MM = 1101,
1117
    C_LT_D32  = 1102,
1118
    C_LT_D32_MM = 1103,
1119
    C_LT_D64  = 1104,
1120
    C_LT_D64_MM = 1105,
1121
    C_LT_S  = 1106,
1122
    C_LT_S_MM = 1107,
1123
    C_NGE_D32 = 1108,
1124
    C_NGE_D32_MM  = 1109,
1125
    C_NGE_D64 = 1110,
1126
    C_NGE_D64_MM  = 1111,
1127
    C_NGE_S = 1112,
1128
    C_NGE_S_MM  = 1113,
1129
    C_NGLE_D32  = 1114,
1130
    C_NGLE_D32_MM = 1115,
1131
    C_NGLE_D64  = 1116,
1132
    C_NGLE_D64_MM = 1117,
1133
    C_NGLE_S  = 1118,
1134
    C_NGLE_S_MM = 1119,
1135
    C_NGL_D32 = 1120,
1136
    C_NGL_D32_MM  = 1121,
1137
    C_NGL_D64 = 1122,
1138
    C_NGL_D64_MM  = 1123,
1139
    C_NGL_S = 1124,
1140
    C_NGL_S_MM  = 1125,
1141
    C_NGT_D32 = 1126,
1142
    C_NGT_D32_MM  = 1127,
1143
    C_NGT_D64 = 1128,
1144
    C_NGT_D64_MM  = 1129,
1145
    C_NGT_S = 1130,
1146
    C_NGT_S_MM  = 1131,
1147
    C_OLE_D32 = 1132,
1148
    C_OLE_D32_MM  = 1133,
1149
    C_OLE_D64 = 1134,
1150
    C_OLE_D64_MM  = 1135,
1151
    C_OLE_S = 1136,
1152
    C_OLE_S_MM  = 1137,
1153
    C_OLT_D32 = 1138,
1154
    C_OLT_D32_MM  = 1139,
1155
    C_OLT_D64 = 1140,
1156
    C_OLT_D64_MM  = 1141,
1157
    C_OLT_S = 1142,
1158
    C_OLT_S_MM  = 1143,
1159
    C_SEQ_D32 = 1144,
1160
    C_SEQ_D32_MM  = 1145,
1161
    C_SEQ_D64 = 1146,
1162
    C_SEQ_D64_MM  = 1147,
1163
    C_SEQ_S = 1148,
1164
    C_SEQ_S_MM  = 1149,
1165
    C_SF_D32  = 1150,
1166
    C_SF_D32_MM = 1151,
1167
    C_SF_D64  = 1152,
1168
    C_SF_D64_MM = 1153,
1169
    C_SF_S  = 1154,
1170
    C_SF_S_MM = 1155,
1171
    C_UEQ_D32 = 1156,
1172
    C_UEQ_D32_MM  = 1157,
1173
    C_UEQ_D64 = 1158,
1174
    C_UEQ_D64_MM  = 1159,
1175
    C_UEQ_S = 1160,
1176
    C_UEQ_S_MM  = 1161,
1177
    C_ULE_D32 = 1162,
1178
    C_ULE_D32_MM  = 1163,
1179
    C_ULE_D64 = 1164,
1180
    C_ULE_D64_MM  = 1165,
1181
    C_ULE_S = 1166,
1182
    C_ULE_S_MM  = 1167,
1183
    C_ULT_D32 = 1168,
1184
    C_ULT_D32_MM  = 1169,
1185
    C_ULT_D64 = 1170,
1186
    C_ULT_D64_MM  = 1171,
1187
    C_ULT_S = 1172,
1188
    C_ULT_S_MM  = 1173,
1189
    C_UN_D32  = 1174,
1190
    C_UN_D32_MM = 1175,
1191
    C_UN_D64  = 1176,
1192
    C_UN_D64_MM = 1177,
1193
    C_UN_S  = 1178,
1194
    C_UN_S_MM = 1179,
1195
    CmpRxRy16 = 1180,
1196
    CmpiRxImm16 = 1181,
1197
    CmpiRxImmX16  = 1182,
1198
    DADD  = 1183,
1199
    DADDi = 1184,
1200
    DADDiu  = 1185,
1201
    DADDu = 1186,
1202
    DAHI  = 1187,
1203
    DALIGN  = 1188,
1204
    DATI  = 1189,
1205
    DAUI  = 1190,
1206
    DBITSWAP  = 1191,
1207
    DCLO  = 1192,
1208
    DCLO_R6 = 1193,
1209
    DCLZ  = 1194,
1210
    DCLZ_R6 = 1195,
1211
    DDIV  = 1196,
1212
    DDIVU = 1197,
1213
    DERET = 1198,
1214
    DERET_MM  = 1199,
1215
    DERET_MMR6  = 1200,
1216
    DEXT  = 1201,
1217
    DEXT64_32 = 1202,
1218
    DEXTM = 1203,
1219
    DEXTU = 1204,
1220
    DI  = 1205,
1221
    DINS  = 1206,
1222
    DINSM = 1207,
1223
    DINSU = 1208,
1224
    DIV = 1209,
1225
    DIVU  = 1210,
1226
    DIVU_MMR6 = 1211,
1227
    DIV_MMR6  = 1212,
1228
    DIV_S_B = 1213,
1229
    DIV_S_D = 1214,
1230
    DIV_S_H = 1215,
1231
    DIV_S_W = 1216,
1232
    DIV_U_B = 1217,
1233
    DIV_U_D = 1218,
1234
    DIV_U_H = 1219,
1235
    DIV_U_W = 1220,
1236
    DI_MM = 1221,
1237
    DI_MMR6 = 1222,
1238
    DLSA  = 1223,
1239
    DLSA_R6 = 1224,
1240
    DMFC0 = 1225,
1241
    DMFC1 = 1226,
1242
    DMFC2 = 1227,
1243
    DMFC2_OCTEON  = 1228,
1244
    DMFGC0  = 1229,
1245
    DMOD  = 1230,
1246
    DMODU = 1231,
1247
    DMT = 1232,
1248
    DMTC0 = 1233,
1249
    DMTC1 = 1234,
1250
    DMTC2 = 1235,
1251
    DMTC2_OCTEON  = 1236,
1252
    DMTGC0  = 1237,
1253
    DMUH  = 1238,
1254
    DMUHU = 1239,
1255
    DMUL  = 1240,
1256
    DMULT = 1241,
1257
    DMULTu  = 1242,
1258
    DMULU = 1243,
1259
    DMUL_R6 = 1244,
1260
    DOTP_S_D  = 1245,
1261
    DOTP_S_H  = 1246,
1262
    DOTP_S_W  = 1247,
1263
    DOTP_U_D  = 1248,
1264
    DOTP_U_H  = 1249,
1265
    DOTP_U_W  = 1250,
1266
    DPADD_S_D = 1251,
1267
    DPADD_S_H = 1252,
1268
    DPADD_S_W = 1253,
1269
    DPADD_U_D = 1254,
1270
    DPADD_U_H = 1255,
1271
    DPADD_U_W = 1256,
1272
    DPAQX_SA_W_PH = 1257,
1273
    DPAQX_SA_W_PH_MMR2  = 1258,
1274
    DPAQX_S_W_PH  = 1259,
1275
    DPAQX_S_W_PH_MMR2 = 1260,
1276
    DPAQ_SA_L_W = 1261,
1277
    DPAQ_SA_L_W_MM  = 1262,
1278
    DPAQ_S_W_PH = 1263,
1279
    DPAQ_S_W_PH_MM  = 1264,
1280
    DPAU_H_QBL  = 1265,
1281
    DPAU_H_QBL_MM = 1266,
1282
    DPAU_H_QBR  = 1267,
1283
    DPAU_H_QBR_MM = 1268,
1284
    DPAX_W_PH = 1269,
1285
    DPAX_W_PH_MMR2  = 1270,
1286
    DPA_W_PH  = 1271,
1287
    DPA_W_PH_MMR2 = 1272,
1288
    DPOP  = 1273,
1289
    DPSQX_SA_W_PH = 1274,
1290
    DPSQX_SA_W_PH_MMR2  = 1275,
1291
    DPSQX_S_W_PH  = 1276,
1292
    DPSQX_S_W_PH_MMR2 = 1277,
1293
    DPSQ_SA_L_W = 1278,
1294
    DPSQ_SA_L_W_MM  = 1279,
1295
    DPSQ_S_W_PH = 1280,
1296
    DPSQ_S_W_PH_MM  = 1281,
1297
    DPSUB_S_D = 1282,
1298
    DPSUB_S_H = 1283,
1299
    DPSUB_S_W = 1284,
1300
    DPSUB_U_D = 1285,
1301
    DPSUB_U_H = 1286,
1302
    DPSUB_U_W = 1287,
1303
    DPSU_H_QBL  = 1288,
1304
    DPSU_H_QBL_MM = 1289,
1305
    DPSU_H_QBR  = 1290,
1306
    DPSU_H_QBR_MM = 1291,
1307
    DPSX_W_PH = 1292,
1308
    DPSX_W_PH_MMR2  = 1293,
1309
    DPS_W_PH  = 1294,
1310
    DPS_W_PH_MMR2 = 1295,
1311
    DROTR = 1296,
1312
    DROTR32 = 1297,
1313
    DROTRV  = 1298,
1314
    DSBH  = 1299,
1315
    DSDIV = 1300,
1316
    DSHD  = 1301,
1317
    DSLL  = 1302,
1318
    DSLL32  = 1303,
1319
    DSLL64_32 = 1304,
1320
    DSLLV = 1305,
1321
    DSRA  = 1306,
1322
    DSRA32  = 1307,
1323
    DSRAV = 1308,
1324
    DSRL  = 1309,
1325
    DSRL32  = 1310,
1326
    DSRLV = 1311,
1327
    DSUB  = 1312,
1328
    DSUBu = 1313,
1329
    DUDIV = 1314,
1330
    DVP = 1315,
1331
    DVPE  = 1316,
1332
    DVP_MMR6  = 1317,
1333
    DivRxRy16 = 1318,
1334
    DivuRxRy16  = 1319,
1335
    EHB = 1320,
1336
    EHB_MM  = 1321,
1337
    EHB_MMR6  = 1322,
1338
    EI  = 1323,
1339
    EI_MM = 1324,
1340
    EI_MMR6 = 1325,
1341
    EMT = 1326,
1342
    ERET  = 1327,
1343
    ERETNC  = 1328,
1344
    ERETNC_MMR6 = 1329,
1345
    ERET_MM = 1330,
1346
    ERET_MMR6 = 1331,
1347
    EVP = 1332,
1348
    EVPE  = 1333,
1349
    EVP_MMR6  = 1334,
1350
    EXT = 1335,
1351
    EXTP  = 1336,
1352
    EXTPDP  = 1337,
1353
    EXTPDPV = 1338,
1354
    EXTPDPV_MM  = 1339,
1355
    EXTPDP_MM = 1340,
1356
    EXTPV = 1341,
1357
    EXTPV_MM  = 1342,
1358
    EXTP_MM = 1343,
1359
    EXTRV_RS_W  = 1344,
1360
    EXTRV_RS_W_MM = 1345,
1361
    EXTRV_R_W = 1346,
1362
    EXTRV_R_W_MM  = 1347,
1363
    EXTRV_S_H = 1348,
1364
    EXTRV_S_H_MM  = 1349,
1365
    EXTRV_W = 1350,
1366
    EXTRV_W_MM  = 1351,
1367
    EXTR_RS_W = 1352,
1368
    EXTR_RS_W_MM  = 1353,
1369
    EXTR_R_W  = 1354,
1370
    EXTR_R_W_MM = 1355,
1371
    EXTR_S_H  = 1356,
1372
    EXTR_S_H_MM = 1357,
1373
    EXTR_W  = 1358,
1374
    EXTR_W_MM = 1359,
1375
    EXTS  = 1360,
1376
    EXTS32  = 1361,
1377
    EXT_MM  = 1362,
1378
    EXT_MMR6  = 1363,
1379
    FABS_D32  = 1364,
1380
    FABS_D32_MM = 1365,
1381
    FABS_D64  = 1366,
1382
    FABS_D64_MM = 1367,
1383
    FABS_S  = 1368,
1384
    FABS_S_MM = 1369,
1385
    FADD_D  = 1370,
1386
    FADD_D32  = 1371,
1387
    FADD_D32_MM = 1372,
1388
    FADD_D64  = 1373,
1389
    FADD_D64_MM = 1374,
1390
    FADD_S  = 1375,
1391
    FADD_S_MM = 1376,
1392
    FADD_S_MMR6 = 1377,
1393
    FADD_W  = 1378,
1394
    FCAF_D  = 1379,
1395
    FCAF_W  = 1380,
1396
    FCEQ_D  = 1381,
1397
    FCEQ_W  = 1382,
1398
    FCLASS_D  = 1383,
1399
    FCLASS_W  = 1384,
1400
    FCLE_D  = 1385,
1401
    FCLE_W  = 1386,
1402
    FCLT_D  = 1387,
1403
    FCLT_W  = 1388,
1404
    FCMP_D32  = 1389,
1405
    FCMP_D32_MM = 1390,
1406
    FCMP_D64  = 1391,
1407
    FCMP_S32  = 1392,
1408
    FCMP_S32_MM = 1393,
1409
    FCNE_D  = 1394,
1410
    FCNE_W  = 1395,
1411
    FCOR_D  = 1396,
1412
    FCOR_W  = 1397,
1413
    FCUEQ_D = 1398,
1414
    FCUEQ_W = 1399,
1415
    FCULE_D = 1400,
1416
    FCULE_W = 1401,
1417
    FCULT_D = 1402,
1418
    FCULT_W = 1403,
1419
    FCUNE_D = 1404,
1420
    FCUNE_W = 1405,
1421
    FCUN_D  = 1406,
1422
    FCUN_W  = 1407,
1423
    FDIV_D  = 1408,
1424
    FDIV_D32  = 1409,
1425
    FDIV_D32_MM = 1410,
1426
    FDIV_D64  = 1411,
1427
    FDIV_D64_MM = 1412,
1428
    FDIV_S  = 1413,
1429
    FDIV_S_MM = 1414,
1430
    FDIV_S_MMR6 = 1415,
1431
    FDIV_W  = 1416,
1432
    FEXDO_H = 1417,
1433
    FEXDO_W = 1418,
1434
    FEXP2_D = 1419,
1435
    FEXP2_W = 1420,
1436
    FEXUPL_D  = 1421,
1437
    FEXUPL_W  = 1422,
1438
    FEXUPR_D  = 1423,
1439
    FEXUPR_W  = 1424,
1440
    FFINT_S_D = 1425,
1441
    FFINT_S_W = 1426,
1442
    FFINT_U_D = 1427,
1443
    FFINT_U_W = 1428,
1444
    FFQL_D  = 1429,
1445
    FFQL_W  = 1430,
1446
    FFQR_D  = 1431,
1447
    FFQR_W  = 1432,
1448
    FILL_B  = 1433,
1449
    FILL_D  = 1434,
1450
    FILL_H  = 1435,
1451
    FILL_W  = 1436,
1452
    FLOG2_D = 1437,
1453
    FLOG2_W = 1438,
1454
    FLOOR_L_D64 = 1439,
1455
    FLOOR_L_D_MMR6  = 1440,
1456
    FLOOR_L_S = 1441,
1457
    FLOOR_L_S_MMR6  = 1442,
1458
    FLOOR_W_D32 = 1443,
1459
    FLOOR_W_D64 = 1444,
1460
    FLOOR_W_D_MMR6  = 1445,
1461
    FLOOR_W_MM  = 1446,
1462
    FLOOR_W_S = 1447,
1463
    FLOOR_W_S_MM  = 1448,
1464
    FLOOR_W_S_MMR6  = 1449,
1465
    FMADD_D = 1450,
1466
    FMADD_W = 1451,
1467
    FMAX_A_D  = 1452,
1468
    FMAX_A_W  = 1453,
1469
    FMAX_D  = 1454,
1470
    FMAX_W  = 1455,
1471
    FMIN_A_D  = 1456,
1472
    FMIN_A_W  = 1457,
1473
    FMIN_D  = 1458,
1474
    FMIN_W  = 1459,
1475
    FMOV_D32  = 1460,
1476
    FMOV_D32_MM = 1461,
1477
    FMOV_D64  = 1462,
1478
    FMOV_D64_MM = 1463,
1479
    FMOV_S  = 1464,
1480
    FMOV_S_MM = 1465,
1481
    FMOV_S_MMR6 = 1466,
1482
    FMSUB_D = 1467,
1483
    FMSUB_W = 1468,
1484
    FMUL_D  = 1469,
1485
    FMUL_D32  = 1470,
1486
    FMUL_D32_MM = 1471,
1487
    FMUL_D64  = 1472,
1488
    FMUL_D64_MM = 1473,
1489
    FMUL_S  = 1474,
1490
    FMUL_S_MM = 1475,
1491
    FMUL_S_MMR6 = 1476,
1492
    FMUL_W  = 1477,
1493
    FNEG_D32  = 1478,
1494
    FNEG_D32_MM = 1479,
1495
    FNEG_D64  = 1480,
1496
    FNEG_D64_MM = 1481,
1497
    FNEG_S  = 1482,
1498
    FNEG_S_MM = 1483,
1499
    FNEG_S_MMR6 = 1484,
1500
    FORK  = 1485,
1501
    FRCP_D  = 1486,
1502
    FRCP_W  = 1487,
1503
    FRINT_D = 1488,
1504
    FRINT_W = 1489,
1505
    FRSQRT_D  = 1490,
1506
    FRSQRT_W  = 1491,
1507
    FSAF_D  = 1492,
1508
    FSAF_W  = 1493,
1509
    FSEQ_D  = 1494,
1510
    FSEQ_W  = 1495,
1511
    FSLE_D  = 1496,
1512
    FSLE_W  = 1497,
1513
    FSLT_D  = 1498,
1514
    FSLT_W  = 1499,
1515
    FSNE_D  = 1500,
1516
    FSNE_W  = 1501,
1517
    FSOR_D  = 1502,
1518
    FSOR_W  = 1503,
1519
    FSQRT_D = 1504,
1520
    FSQRT_D32 = 1505,
1521
    FSQRT_D32_MM  = 1506,
1522
    FSQRT_D64 = 1507,
1523
    FSQRT_D64_MM  = 1508,
1524
    FSQRT_S = 1509,
1525
    FSQRT_S_MM  = 1510,
1526
    FSQRT_W = 1511,
1527
    FSUB_D  = 1512,
1528
    FSUB_D32  = 1513,
1529
    FSUB_D32_MM = 1514,
1530
    FSUB_D64  = 1515,
1531
    FSUB_D64_MM = 1516,
1532
    FSUB_S  = 1517,
1533
    FSUB_S_MM = 1518,
1534
    FSUB_S_MMR6 = 1519,
1535
    FSUB_W  = 1520,
1536
    FSUEQ_D = 1521,
1537
    FSUEQ_W = 1522,
1538
    FSULE_D = 1523,
1539
    FSULE_W = 1524,
1540
    FSULT_D = 1525,
1541
    FSULT_W = 1526,
1542
    FSUNE_D = 1527,
1543
    FSUNE_W = 1528,
1544
    FSUN_D  = 1529,
1545
    FSUN_W  = 1530,
1546
    FTINT_S_D = 1531,
1547
    FTINT_S_W = 1532,
1548
    FTINT_U_D = 1533,
1549
    FTINT_U_W = 1534,
1550
    FTQ_H = 1535,
1551
    FTQ_W = 1536,
1552
    FTRUNC_S_D  = 1537,
1553
    FTRUNC_S_W  = 1538,
1554
    FTRUNC_U_D  = 1539,
1555
    FTRUNC_U_W  = 1540,
1556
    GINVI = 1541,
1557
    GINVI_MMR6  = 1542,
1558
    GINVT = 1543,
1559
    GINVT_MMR6  = 1544,
1560
    HADD_S_D  = 1545,
1561
    HADD_S_H  = 1546,
1562
    HADD_S_W  = 1547,
1563
    HADD_U_D  = 1548,
1564
    HADD_U_H  = 1549,
1565
    HADD_U_W  = 1550,
1566
    HSUB_S_D  = 1551,
1567
    HSUB_S_H  = 1552,
1568
    HSUB_S_W  = 1553,
1569
    HSUB_U_D  = 1554,
1570
    HSUB_U_H  = 1555,
1571
    HSUB_U_W  = 1556,
1572
    HYPCALL = 1557,
1573
    HYPCALL_MM  = 1558,
1574
    ILVEV_B = 1559,
1575
    ILVEV_D = 1560,
1576
    ILVEV_H = 1561,
1577
    ILVEV_W = 1562,
1578
    ILVL_B  = 1563,
1579
    ILVL_D  = 1564,
1580
    ILVL_H  = 1565,
1581
    ILVL_W  = 1566,
1582
    ILVOD_B = 1567,
1583
    ILVOD_D = 1568,
1584
    ILVOD_H = 1569,
1585
    ILVOD_W = 1570,
1586
    ILVR_B  = 1571,
1587
    ILVR_D  = 1572,
1588
    ILVR_H  = 1573,
1589
    ILVR_W  = 1574,
1590
    INS = 1575,
1591
    INSERT_B  = 1576,
1592
    INSERT_D  = 1577,
1593
    INSERT_H  = 1578,
1594
    INSERT_W  = 1579,
1595
    INSV  = 1580,
1596
    INSVE_B = 1581,
1597
    INSVE_D = 1582,
1598
    INSVE_H = 1583,
1599
    INSVE_W = 1584,
1600
    INSV_MM = 1585,
1601
    INS_MM  = 1586,
1602
    INS_MMR6  = 1587,
1603
    J = 1588,
1604
    JAL = 1589,
1605
    JALR  = 1590,
1606
    JALR16_MM = 1591,
1607
    JALR64  = 1592,
1608
    JALRC16_MMR6  = 1593,
1609
    JALRC_HB_MMR6 = 1594,
1610
    JALRC_MMR6  = 1595,
1611
    JALRS16_MM  = 1596,
1612
    JALRS_MM  = 1597,
1613
    JALR_HB = 1598,
1614
    JALR_HB64 = 1599,
1615
    JALR_MM = 1600,
1616
    JALS_MM = 1601,
1617
    JALX  = 1602,
1618
    JALX_MM = 1603,
1619
    JAL_MM  = 1604,
1620
    JIALC = 1605,
1621
    JIALC64 = 1606,
1622
    JIALC_MMR6  = 1607,
1623
    JIC = 1608,
1624
    JIC64 = 1609,
1625
    JIC_MMR6  = 1610,
1626
    JR  = 1611,
1627
    JR16_MM = 1612,
1628
    JR64  = 1613,
1629
    JRADDIUSP = 1614,
1630
    JRC16_MM  = 1615,
1631
    JRC16_MMR6  = 1616,
1632
    JRCADDIUSP_MMR6 = 1617,
1633
    JR_HB = 1618,
1634
    JR_HB64 = 1619,
1635
    JR_HB64_R6  = 1620,
1636
    JR_HB_R6  = 1621,
1637
    JR_MM = 1622,
1638
    J_MM  = 1623,
1639
    Jal16 = 1624,
1640
    JalB16  = 1625,
1641
    JrRa16  = 1626,
1642
    JrcRa16 = 1627,
1643
    JrcRx16 = 1628,
1644
    JumpLinkReg16 = 1629,
1645
    LB  = 1630,
1646
    LB64  = 1631,
1647
    LBE = 1632,
1648
    LBE_MM  = 1633,
1649
    LBU16_MM  = 1634,
1650
    LBUX  = 1635,
1651
    LBUX_MM = 1636,
1652
    LBU_MMR6  = 1637,
1653
    LB_MM = 1638,
1654
    LB_MMR6 = 1639,
1655
    LBu = 1640,
1656
    LBu64 = 1641,
1657
    LBuE  = 1642,
1658
    LBuE_MM = 1643,
1659
    LBu_MM  = 1644,
1660
    LD  = 1645,
1661
    LDC1  = 1646,
1662
    LDC164  = 1647,
1663
    LDC1_D64_MMR6 = 1648,
1664
    LDC1_MM = 1649,
1665
    LDC2  = 1650,
1666
    LDC2_MMR6 = 1651,
1667
    LDC2_R6 = 1652,
1668
    LDC3  = 1653,
1669
    LDI_B = 1654,
1670
    LDI_D = 1655,
1671
    LDI_H = 1656,
1672
    LDI_W = 1657,
1673
    LDL = 1658,
1674
    LDPC  = 1659,
1675
    LDR = 1660,
1676
    LDXC1 = 1661,
1677
    LDXC164 = 1662,
1678
    LD_B  = 1663,
1679
    LD_D  = 1664,
1680
    LD_H  = 1665,
1681
    LD_W  = 1666,
1682
    LEA_ADDiu = 1667,
1683
    LEA_ADDiu64 = 1668,
1684
    LEA_ADDiu_MM  = 1669,
1685
    LH  = 1670,
1686
    LH64  = 1671,
1687
    LHE = 1672,
1688
    LHE_MM  = 1673,
1689
    LHU16_MM  = 1674,
1690
    LHX = 1675,
1691
    LHX_MM  = 1676,
1692
    LH_MM = 1677,
1693
    LHu = 1678,
1694
    LHu64 = 1679,
1695
    LHuE  = 1680,
1696
    LHuE_MM = 1681,
1697
    LHu_MM  = 1682,
1698
    LI16_MM = 1683,
1699
    LI16_MMR6 = 1684,
1700
    LL  = 1685,
1701
    LL64  = 1686,
1702
    LL64_R6 = 1687,
1703
    LLD = 1688,
1704
    LLD_R6  = 1689,
1705
    LLE = 1690,
1706
    LLE_MM  = 1691,
1707
    LL_MM = 1692,
1708
    LL_MMR6 = 1693,
1709
    LL_R6 = 1694,
1710
    LSA = 1695,
1711
    LSA_MMR6  = 1696,
1712
    LSA_R6  = 1697,
1713
    LUI_MMR6  = 1698,
1714
    LUXC1 = 1699,
1715
    LUXC164 = 1700,
1716
    LUXC1_MM  = 1701,
1717
    LUi = 1702,
1718
    LUi64 = 1703,
1719
    LUi_MM  = 1704,
1720
    LW  = 1705,
1721
    LW16_MM = 1706,
1722
    LW64  = 1707,
1723
    LWC1  = 1708,
1724
    LWC1_MM = 1709,
1725
    LWC2  = 1710,
1726
    LWC2_MMR6 = 1711,
1727
    LWC2_R6 = 1712,
1728
    LWC3  = 1713,
1729
    LWDSP = 1714,
1730
    LWDSP_MM  = 1715,
1731
    LWE = 1716,
1732
    LWE_MM  = 1717,
1733
    LWGP_MM = 1718,
1734
    LWL = 1719,
1735
    LWL64 = 1720,
1736
    LWLE  = 1721,
1737
    LWLE_MM = 1722,
1738
    LWL_MM  = 1723,
1739
    LWM16_MM  = 1724,
1740
    LWM16_MMR6  = 1725,
1741
    LWM32_MM  = 1726,
1742
    LWPC  = 1727,
1743
    LWPC_MMR6 = 1728,
1744
    LWP_MM  = 1729,
1745
    LWR = 1730,
1746
    LWR64 = 1731,
1747
    LWRE  = 1732,
1748
    LWRE_MM = 1733,
1749
    LWR_MM  = 1734,
1750
    LWSP_MM = 1735,
1751
    LWUPC = 1736,
1752
    LWU_MM  = 1737,
1753
    LWX = 1738,
1754
    LWXC1 = 1739,
1755
    LWXC1_MM  = 1740,
1756
    LWXS_MM = 1741,
1757
    LWX_MM  = 1742,
1758
    LW_MM = 1743,
1759
    LW_MMR6 = 1744,
1760
    LWu = 1745,
1761
    LbRxRyOffMemX16 = 1746,
1762
    LbuRxRyOffMemX16  = 1747,
1763
    LhRxRyOffMemX16 = 1748,
1764
    LhuRxRyOffMemX16  = 1749,
1765
    LiRxImm16 = 1750,
1766
    LiRxImmAlignX16 = 1751,
1767
    LiRxImmX16  = 1752,
1768
    LwRxPcTcp16 = 1753,
1769
    LwRxPcTcpX16  = 1754,
1770
    LwRxRyOffMemX16 = 1755,
1771
    LwRxSpImmX16  = 1756,
1772
    MADD  = 1757,
1773
    MADDF_D = 1758,
1774
    MADDF_D_MMR6  = 1759,
1775
    MADDF_S = 1760,
1776
    MADDF_S_MMR6  = 1761,
1777
    MADDR_Q_H = 1762,
1778
    MADDR_Q_W = 1763,
1779
    MADDU = 1764,
1780
    MADDU_DSP = 1765,
1781
    MADDU_DSP_MM  = 1766,
1782
    MADDU_MM  = 1767,
1783
    MADDV_B = 1768,
1784
    MADDV_D = 1769,
1785
    MADDV_H = 1770,
1786
    MADDV_W = 1771,
1787
    MADD_D32  = 1772,
1788
    MADD_D32_MM = 1773,
1789
    MADD_D64  = 1774,
1790
    MADD_DSP  = 1775,
1791
    MADD_DSP_MM = 1776,
1792
    MADD_MM = 1777,
1793
    MADD_Q_H  = 1778,
1794
    MADD_Q_W  = 1779,
1795
    MADD_S  = 1780,
1796
    MADD_S_MM = 1781,
1797
    MAQ_SA_W_PHL  = 1782,
1798
    MAQ_SA_W_PHL_MM = 1783,
1799
    MAQ_SA_W_PHR  = 1784,
1800
    MAQ_SA_W_PHR_MM = 1785,
1801
    MAQ_S_W_PHL = 1786,
1802
    MAQ_S_W_PHL_MM  = 1787,
1803
    MAQ_S_W_PHR = 1788,
1804
    MAQ_S_W_PHR_MM  = 1789,
1805
    MAXA_D  = 1790,
1806
    MAXA_D_MMR6 = 1791,
1807
    MAXA_S  = 1792,
1808
    MAXA_S_MMR6 = 1793,
1809
    MAXI_S_B  = 1794,
1810
    MAXI_S_D  = 1795,
1811
    MAXI_S_H  = 1796,
1812
    MAXI_S_W  = 1797,
1813
    MAXI_U_B  = 1798,
1814
    MAXI_U_D  = 1799,
1815
    MAXI_U_H  = 1800,
1816
    MAXI_U_W  = 1801,
1817
    MAX_A_B = 1802,
1818
    MAX_A_D = 1803,
1819
    MAX_A_H = 1804,
1820
    MAX_A_W = 1805,
1821
    MAX_D = 1806,
1822
    MAX_D_MMR6  = 1807,
1823
    MAX_S = 1808,
1824
    MAX_S_B = 1809,
1825
    MAX_S_D = 1810,
1826
    MAX_S_H = 1811,
1827
    MAX_S_MMR6  = 1812,
1828
    MAX_S_W = 1813,
1829
    MAX_U_B = 1814,
1830
    MAX_U_D = 1815,
1831
    MAX_U_H = 1816,
1832
    MAX_U_W = 1817,
1833
    MFC0  = 1818,
1834
    MFC0_MMR6 = 1819,
1835
    MFC1  = 1820,
1836
    MFC1_D64  = 1821,
1837
    MFC1_MM = 1822,
1838
    MFC1_MMR6 = 1823,
1839
    MFC2  = 1824,
1840
    MFC2_MMR6 = 1825,
1841
    MFGC0 = 1826,
1842
    MFGC0_MM  = 1827,
1843
    MFHC0_MMR6  = 1828,
1844
    MFHC1_D32 = 1829,
1845
    MFHC1_D32_MM  = 1830,
1846
    MFHC1_D64 = 1831,
1847
    MFHC1_D64_MM  = 1832,
1848
    MFHC2_MMR6  = 1833,
1849
    MFHGC0  = 1834,
1850
    MFHGC0_MM = 1835,
1851
    MFHI  = 1836,
1852
    MFHI16_MM = 1837,
1853
    MFHI64  = 1838,
1854
    MFHI_DSP  = 1839,
1855
    MFHI_DSP_MM = 1840,
1856
    MFHI_MM = 1841,
1857
    MFLO  = 1842,
1858
    MFLO16_MM = 1843,
1859
    MFLO64  = 1844,
1860
    MFLO_DSP  = 1845,
1861
    MFLO_DSP_MM = 1846,
1862
    MFLO_MM = 1847,
1863
    MFTR  = 1848,
1864
    MINA_D  = 1849,
1865
    MINA_D_MMR6 = 1850,
1866
    MINA_S  = 1851,
1867
    MINA_S_MMR6 = 1852,
1868
    MINI_S_B  = 1853,
1869
    MINI_S_D  = 1854,
1870
    MINI_S_H  = 1855,
1871
    MINI_S_W  = 1856,
1872
    MINI_U_B  = 1857,
1873
    MINI_U_D  = 1858,
1874
    MINI_U_H  = 1859,
1875
    MINI_U_W  = 1860,
1876
    MIN_A_B = 1861,
1877
    MIN_A_D = 1862,
1878
    MIN_A_H = 1863,
1879
    MIN_A_W = 1864,
1880
    MIN_D = 1865,
1881
    MIN_D_MMR6  = 1866,
1882
    MIN_S = 1867,
1883
    MIN_S_B = 1868,
1884
    MIN_S_D = 1869,
1885
    MIN_S_H = 1870,
1886
    MIN_S_MMR6  = 1871,
1887
    MIN_S_W = 1872,
1888
    MIN_U_B = 1873,
1889
    MIN_U_D = 1874,
1890
    MIN_U_H = 1875,
1891
    MIN_U_W = 1876,
1892
    MOD = 1877,
1893
    MODSUB  = 1878,
1894
    MODSUB_MM = 1879,
1895
    MODU  = 1880,
1896
    MODU_MMR6 = 1881,
1897
    MOD_MMR6  = 1882,
1898
    MOD_S_B = 1883,
1899
    MOD_S_D = 1884,
1900
    MOD_S_H = 1885,
1901
    MOD_S_W = 1886,
1902
    MOD_U_B = 1887,
1903
    MOD_U_D = 1888,
1904
    MOD_U_H = 1889,
1905
    MOD_U_W = 1890,
1906
    MOVE16_MM = 1891,
1907
    MOVE16_MMR6 = 1892,
1908
    MOVEP_MM  = 1893,
1909
    MOVEP_MMR6  = 1894,
1910
    MOVE_V  = 1895,
1911
    MOVF_D32  = 1896,
1912
    MOVF_D32_MM = 1897,
1913
    MOVF_D64  = 1898,
1914
    MOVF_I  = 1899,
1915
    MOVF_I64  = 1900,
1916
    MOVF_I_MM = 1901,
1917
    MOVF_S  = 1902,
1918
    MOVF_S_MM = 1903,
1919
    MOVN_I64_D64  = 1904,
1920
    MOVN_I64_I  = 1905,
1921
    MOVN_I64_I64  = 1906,
1922
    MOVN_I64_S  = 1907,
1923
    MOVN_I_D32  = 1908,
1924
    MOVN_I_D32_MM = 1909,
1925
    MOVN_I_D64  = 1910,
1926
    MOVN_I_I  = 1911,
1927
    MOVN_I_I64  = 1912,
1928
    MOVN_I_MM = 1913,
1929
    MOVN_I_S  = 1914,
1930
    MOVN_I_S_MM = 1915,
1931
    MOVT_D32  = 1916,
1932
    MOVT_D32_MM = 1917,
1933
    MOVT_D64  = 1918,
1934
    MOVT_I  = 1919,
1935
    MOVT_I64  = 1920,
1936
    MOVT_I_MM = 1921,
1937
    MOVT_S  = 1922,
1938
    MOVT_S_MM = 1923,
1939
    MOVZ_I64_D64  = 1924,
1940
    MOVZ_I64_I  = 1925,
1941
    MOVZ_I64_I64  = 1926,
1942
    MOVZ_I64_S  = 1927,
1943
    MOVZ_I_D32  = 1928,
1944
    MOVZ_I_D32_MM = 1929,
1945
    MOVZ_I_D64  = 1930,
1946
    MOVZ_I_I  = 1931,
1947
    MOVZ_I_I64  = 1932,
1948
    MOVZ_I_MM = 1933,
1949
    MOVZ_I_S  = 1934,
1950
    MOVZ_I_S_MM = 1935,
1951
    MSUB  = 1936,
1952
    MSUBF_D = 1937,
1953
    MSUBF_D_MMR6  = 1938,
1954
    MSUBF_S = 1939,
1955
    MSUBF_S_MMR6  = 1940,
1956
    MSUBR_Q_H = 1941,
1957
    MSUBR_Q_W = 1942,
1958
    MSUBU = 1943,
1959
    MSUBU_DSP = 1944,
1960
    MSUBU_DSP_MM  = 1945,
1961
    MSUBU_MM  = 1946,
1962
    MSUBV_B = 1947,
1963
    MSUBV_D = 1948,
1964
    MSUBV_H = 1949,
1965
    MSUBV_W = 1950,
1966
    MSUB_D32  = 1951,
1967
    MSUB_D32_MM = 1952,
1968
    MSUB_D64  = 1953,
1969
    MSUB_DSP  = 1954,
1970
    MSUB_DSP_MM = 1955,
1971
    MSUB_MM = 1956,
1972
    MSUB_Q_H  = 1957,
1973
    MSUB_Q_W  = 1958,
1974
    MSUB_S  = 1959,
1975
    MSUB_S_MM = 1960,
1976
    MTC0  = 1961,
1977
    MTC0_MMR6 = 1962,
1978
    MTC1  = 1963,
1979
    MTC1_D64  = 1964,
1980
    MTC1_D64_MM = 1965,
1981
    MTC1_MM = 1966,
1982
    MTC1_MMR6 = 1967,
1983
    MTC2  = 1968,
1984
    MTC2_MMR6 = 1969,
1985
    MTGC0 = 1970,
1986
    MTGC0_MM  = 1971,
1987
    MTHC0_MMR6  = 1972,
1988
    MTHC1_D32 = 1973,
1989
    MTHC1_D32_MM  = 1974,
1990
    MTHC1_D64 = 1975,
1991
    MTHC1_D64_MM  = 1976,
1992
    MTHC2_MMR6  = 1977,
1993
    MTHGC0  = 1978,
1994
    MTHGC0_MM = 1979,
1995
    MTHI  = 1980,
1996
    MTHI64  = 1981,
1997
    MTHI_DSP  = 1982,
1998
    MTHI_DSP_MM = 1983,
1999
    MTHI_MM = 1984,
2000
    MTHLIP  = 1985,
2001
    MTHLIP_MM = 1986,
2002
    MTLO  = 1987,
2003
    MTLO64  = 1988,
2004
    MTLO_DSP  = 1989,
2005
    MTLO_DSP_MM = 1990,
2006
    MTLO_MM = 1991,
2007
    MTM0  = 1992,
2008
    MTM1  = 1993,
2009
    MTM2  = 1994,
2010
    MTP0  = 1995,
2011
    MTP1  = 1996,
2012
    MTP2  = 1997,
2013
    MTTR  = 1998,
2014
    MUH = 1999,
2015
    MUHU  = 2000,
2016
    MUHU_MMR6 = 2001,
2017
    MUH_MMR6  = 2002,
2018
    MUL = 2003,
2019
    MULEQ_S_W_PHL = 2004,
2020
    MULEQ_S_W_PHL_MM  = 2005,
2021
    MULEQ_S_W_PHR = 2006,
2022
    MULEQ_S_W_PHR_MM  = 2007,
2023
    MULEU_S_PH_QBL  = 2008,
2024
    MULEU_S_PH_QBL_MM = 2009,
2025
    MULEU_S_PH_QBR  = 2010,
2026
    MULEU_S_PH_QBR_MM = 2011,
2027
    MULQ_RS_PH  = 2012,
2028
    MULQ_RS_PH_MM = 2013,
2029
    MULQ_RS_W = 2014,
2030
    MULQ_RS_W_MMR2  = 2015,
2031
    MULQ_S_PH = 2016,
2032
    MULQ_S_PH_MMR2  = 2017,
2033
    MULQ_S_W  = 2018,
2034
    MULQ_S_W_MMR2 = 2019,
2035
    MULR_Q_H  = 2020,
2036
    MULR_Q_W  = 2021,
2037
    MULSAQ_S_W_PH = 2022,
2038
    MULSAQ_S_W_PH_MM  = 2023,
2039
    MULSA_W_PH  = 2024,
2040
    MULSA_W_PH_MMR2 = 2025,
2041
    MULT  = 2026,
2042
    MULTU_DSP = 2027,
2043
    MULTU_DSP_MM  = 2028,
2044
    MULT_DSP  = 2029,
2045
    MULT_DSP_MM = 2030,
2046
    MULT_MM = 2031,
2047
    MULTu = 2032,
2048
    MULTu_MM  = 2033,
2049
    MULU  = 2034,
2050
    MULU_MMR6 = 2035,
2051
    MULV_B  = 2036,
2052
    MULV_D  = 2037,
2053
    MULV_H  = 2038,
2054
    MULV_W  = 2039,
2055
    MUL_MM  = 2040,
2056
    MUL_MMR6  = 2041,
2057
    MUL_PH  = 2042,
2058
    MUL_PH_MMR2 = 2043,
2059
    MUL_Q_H = 2044,
2060
    MUL_Q_W = 2045,
2061
    MUL_R6  = 2046,
2062
    MUL_S_PH  = 2047,
2063
    MUL_S_PH_MMR2 = 2048,
2064
    Mfhi16  = 2049,
2065
    Mflo16  = 2050,
2066
    Move32R16 = 2051,
2067
    MoveR3216 = 2052,
2068
    NLOC_B  = 2053,
2069
    NLOC_D  = 2054,
2070
    NLOC_H  = 2055,
2071
    NLOC_W  = 2056,
2072
    NLZC_B  = 2057,
2073
    NLZC_D  = 2058,
2074
    NLZC_H  = 2059,
2075
    NLZC_W  = 2060,
2076
    NMADD_D32 = 2061,
2077
    NMADD_D32_MM  = 2062,
2078
    NMADD_D64 = 2063,
2079
    NMADD_S = 2064,
2080
    NMADD_S_MM  = 2065,
2081
    NMSUB_D32 = 2066,
2082
    NMSUB_D32_MM  = 2067,
2083
    NMSUB_D64 = 2068,
2084
    NMSUB_S = 2069,
2085
    NMSUB_S_MM  = 2070,
2086
    NOR = 2071,
2087
    NOR64 = 2072,
2088
    NORI_B  = 2073,
2089
    NOR_MM  = 2074,
2090
    NOR_MMR6  = 2075,
2091
    NOR_V = 2076,
2092
    NOT16_MM  = 2077,
2093
    NOT16_MMR6  = 2078,
2094
    NegRxRy16 = 2079,
2095
    NotRxRy16 = 2080,
2096
    OR  = 2081,
2097
    OR16_MM = 2082,
2098
    OR16_MMR6 = 2083,
2099
    OR64  = 2084,
2100
    ORI_B = 2085,
2101
    ORI_MMR6  = 2086,
2102
    OR_MM = 2087,
2103
    OR_MMR6 = 2088,
2104
    OR_V  = 2089,
2105
    ORi = 2090,
2106
    ORi64 = 2091,
2107
    ORi_MM  = 2092,
2108
    OrRxRxRy16  = 2093,
2109
    PACKRL_PH = 2094,
2110
    PACKRL_PH_MM  = 2095,
2111
    PAUSE = 2096,
2112
    PAUSE_MM  = 2097,
2113
    PAUSE_MMR6  = 2098,
2114
    PCKEV_B = 2099,
2115
    PCKEV_D = 2100,
2116
    PCKEV_H = 2101,
2117
    PCKEV_W = 2102,
2118
    PCKOD_B = 2103,
2119
    PCKOD_D = 2104,
2120
    PCKOD_H = 2105,
2121
    PCKOD_W = 2106,
2122
    PCNT_B  = 2107,
2123
    PCNT_D  = 2108,
2124
    PCNT_H  = 2109,
2125
    PCNT_W  = 2110,
2126
    PICK_PH = 2111,
2127
    PICK_PH_MM  = 2112,
2128
    PICK_QB = 2113,
2129
    PICK_QB_MM  = 2114,
2130
    PLL_PS64  = 2115,
2131
    PLU_PS64  = 2116,
2132
    POP = 2117,
2133
    PRECEQU_PH_QBL  = 2118,
2134
    PRECEQU_PH_QBLA = 2119,
2135
    PRECEQU_PH_QBLA_MM  = 2120,
2136
    PRECEQU_PH_QBL_MM = 2121,
2137
    PRECEQU_PH_QBR  = 2122,
2138
    PRECEQU_PH_QBRA = 2123,
2139
    PRECEQU_PH_QBRA_MM  = 2124,
2140
    PRECEQU_PH_QBR_MM = 2125,
2141
    PRECEQ_W_PHL  = 2126,
2142
    PRECEQ_W_PHL_MM = 2127,
2143
    PRECEQ_W_PHR  = 2128,
2144
    PRECEQ_W_PHR_MM = 2129,
2145
    PRECEU_PH_QBL = 2130,
2146
    PRECEU_PH_QBLA  = 2131,
2147
    PRECEU_PH_QBLA_MM = 2132,
2148
    PRECEU_PH_QBL_MM  = 2133,
2149
    PRECEU_PH_QBR = 2134,
2150
    PRECEU_PH_QBRA  = 2135,
2151
    PRECEU_PH_QBRA_MM = 2136,
2152
    PRECEU_PH_QBR_MM  = 2137,
2153
    PRECRQU_S_QB_PH = 2138,
2154
    PRECRQU_S_QB_PH_MM  = 2139,
2155
    PRECRQ_PH_W = 2140,
2156
    PRECRQ_PH_W_MM  = 2141,
2157
    PRECRQ_QB_PH  = 2142,
2158
    PRECRQ_QB_PH_MM = 2143,
2159
    PRECRQ_RS_PH_W  = 2144,
2160
    PRECRQ_RS_PH_W_MM = 2145,
2161
    PRECR_QB_PH = 2146,
2162
    PRECR_QB_PH_MMR2  = 2147,
2163
    PRECR_SRA_PH_W  = 2148,
2164
    PRECR_SRA_PH_W_MMR2 = 2149,
2165
    PRECR_SRA_R_PH_W  = 2150,
2166
    PRECR_SRA_R_PH_W_MMR2 = 2151,
2167
    PREF  = 2152,
2168
    PREFE = 2153,
2169
    PREFE_MM  = 2154,
2170
    PREFX_MM  = 2155,
2171
    PREF_MM = 2156,
2172
    PREF_MMR6 = 2157,
2173
    PREF_R6 = 2158,
2174
    PREPEND = 2159,
2175
    PREPEND_MMR2  = 2160,
2176
    RADDU_W_QB  = 2161,
2177
    RADDU_W_QB_MM = 2162,
2178
    RDDSP = 2163,
2179
    RDDSP_MM  = 2164,
2180
    RDHWR = 2165,
2181
    RDHWR64 = 2166,
2182
    RDHWR_MM  = 2167,
2183
    RDHWR_MMR6  = 2168,
2184
    RDPGPR_MMR6 = 2169,
2185
    RECIP_D32 = 2170,
2186
    RECIP_D32_MM  = 2171,
2187
    RECIP_D64 = 2172,
2188
    RECIP_D64_MM  = 2173,
2189
    RECIP_S = 2174,
2190
    RECIP_S_MM  = 2175,
2191
    REPLV_PH  = 2176,
2192
    REPLV_PH_MM = 2177,
2193
    REPLV_QB  = 2178,
2194
    REPLV_QB_MM = 2179,
2195
    REPL_PH = 2180,
2196
    REPL_PH_MM  = 2181,
2197
    REPL_QB = 2182,
2198
    REPL_QB_MM  = 2183,
2199
    RINT_D  = 2184,
2200
    RINT_D_MMR6 = 2185,
2201
    RINT_S  = 2186,
2202
    RINT_S_MMR6 = 2187,
2203
    ROTR  = 2188,
2204
    ROTRV = 2189,
2205
    ROTRV_MM  = 2190,
2206
    ROTR_MM = 2191,
2207
    ROUND_L_D64 = 2192,
2208
    ROUND_L_D_MMR6  = 2193,
2209
    ROUND_L_S = 2194,
2210
    ROUND_L_S_MMR6  = 2195,
2211
    ROUND_W_D32 = 2196,
2212
    ROUND_W_D64 = 2197,
2213
    ROUND_W_D_MMR6  = 2198,
2214
    ROUND_W_MM  = 2199,
2215
    ROUND_W_S = 2200,
2216
    ROUND_W_S_MM  = 2201,
2217
    ROUND_W_S_MMR6  = 2202,
2218
    RSQRT_D32 = 2203,
2219
    RSQRT_D32_MM  = 2204,
2220
    RSQRT_D64 = 2205,
2221
    RSQRT_D64_MM  = 2206,
2222
    RSQRT_S = 2207,
2223
    RSQRT_S_MM  = 2208,
2224
    Restore16 = 2209,
2225
    RestoreX16  = 2210,
2226
    SAT_S_B = 2211,
2227
    SAT_S_D = 2212,
2228
    SAT_S_H = 2213,
2229
    SAT_S_W = 2214,
2230
    SAT_U_B = 2215,
2231
    SAT_U_D = 2216,
2232
    SAT_U_H = 2217,
2233
    SAT_U_W = 2218,
2234
    SB  = 2219,
2235
    SB16_MM = 2220,
2236
    SB16_MMR6 = 2221,
2237
    SB64  = 2222,
2238
    SBE = 2223,
2239
    SBE_MM  = 2224,
2240
    SB_MM = 2225,
2241
    SB_MMR6 = 2226,
2242
    SC  = 2227,
2243
    SC64  = 2228,
2244
    SC64_R6 = 2229,
2245
    SCD = 2230,
2246
    SCD_R6  = 2231,
2247
    SCE = 2232,
2248
    SCE_MM  = 2233,
2249
    SC_MM = 2234,
2250
    SC_MMR6 = 2235,
2251
    SC_R6 = 2236,
2252
    SD  = 2237,
2253
    SDBBP = 2238,
2254
    SDBBP16_MM  = 2239,
2255
    SDBBP16_MMR6  = 2240,
2256
    SDBBP_MM  = 2241,
2257
    SDBBP_MMR6  = 2242,
2258
    SDBBP_R6  = 2243,
2259
    SDC1  = 2244,
2260
    SDC164  = 2245,
2261
    SDC1_D64_MMR6 = 2246,
2262
    SDC1_MM = 2247,
2263
    SDC2  = 2248,
2264
    SDC2_MMR6 = 2249,
2265
    SDC2_R6 = 2250,
2266
    SDC3  = 2251,
2267
    SDIV  = 2252,
2268
    SDIV_MM = 2253,
2269
    SDL = 2254,
2270
    SDR = 2255,
2271
    SDXC1 = 2256,
2272
    SDXC164 = 2257,
2273
    SEB = 2258,
2274
    SEB64 = 2259,
2275
    SEB_MM  = 2260,
2276
    SEH = 2261,
2277
    SEH64 = 2262,
2278
    SEH_MM  = 2263,
2279
    SELEQZ  = 2264,
2280
    SELEQZ64  = 2265,
2281
    SELEQZ_D  = 2266,
2282
    SELEQZ_D_MMR6 = 2267,
2283
    SELEQZ_MMR6 = 2268,
2284
    SELEQZ_S  = 2269,
2285
    SELEQZ_S_MMR6 = 2270,
2286
    SELNEZ  = 2271,
2287
    SELNEZ64  = 2272,
2288
    SELNEZ_D  = 2273,
2289
    SELNEZ_D_MMR6 = 2274,
2290
    SELNEZ_MMR6 = 2275,
2291
    SELNEZ_S  = 2276,
2292
    SELNEZ_S_MMR6 = 2277,
2293
    SEL_D = 2278,
2294
    SEL_D_MMR6  = 2279,
2295
    SEL_S = 2280,
2296
    SEL_S_MMR6  = 2281,
2297
    SEQ = 2282,
2298
    SEQi  = 2283,
2299
    SH  = 2284,
2300
    SH16_MM = 2285,
2301
    SH16_MMR6 = 2286,
2302
    SH64  = 2287,
2303
    SHE = 2288,
2304
    SHE_MM  = 2289,
2305
    SHF_B = 2290,
2306
    SHF_H = 2291,
2307
    SHF_W = 2292,
2308
    SHILO = 2293,
2309
    SHILOV  = 2294,
2310
    SHILOV_MM = 2295,
2311
    SHILO_MM  = 2296,
2312
    SHLLV_PH  = 2297,
2313
    SHLLV_PH_MM = 2298,
2314
    SHLLV_QB  = 2299,
2315
    SHLLV_QB_MM = 2300,
2316
    SHLLV_S_PH  = 2301,
2317
    SHLLV_S_PH_MM = 2302,
2318
    SHLLV_S_W = 2303,
2319
    SHLLV_S_W_MM  = 2304,
2320
    SHLL_PH = 2305,
2321
    SHLL_PH_MM  = 2306,
2322
    SHLL_QB = 2307,
2323
    SHLL_QB_MM  = 2308,
2324
    SHLL_S_PH = 2309,
2325
    SHLL_S_PH_MM  = 2310,
2326
    SHLL_S_W  = 2311,
2327
    SHLL_S_W_MM = 2312,
2328
    SHRAV_PH  = 2313,
2329
    SHRAV_PH_MM = 2314,
2330
    SHRAV_QB  = 2315,
2331
    SHRAV_QB_MMR2 = 2316,
2332
    SHRAV_R_PH  = 2317,
2333
    SHRAV_R_PH_MM = 2318,
2334
    SHRAV_R_QB  = 2319,
2335
    SHRAV_R_QB_MMR2 = 2320,
2336
    SHRAV_R_W = 2321,
2337
    SHRAV_R_W_MM  = 2322,
2338
    SHRA_PH = 2323,
2339
    SHRA_PH_MM  = 2324,
2340
    SHRA_QB = 2325,
2341
    SHRA_QB_MMR2  = 2326,
2342
    SHRA_R_PH = 2327,
2343
    SHRA_R_PH_MM  = 2328,
2344
    SHRA_R_QB = 2329,
2345
    SHRA_R_QB_MMR2  = 2330,
2346
    SHRA_R_W  = 2331,
2347
    SHRA_R_W_MM = 2332,
2348
    SHRLV_PH  = 2333,
2349
    SHRLV_PH_MMR2 = 2334,
2350
    SHRLV_QB  = 2335,
2351
    SHRLV_QB_MM = 2336,
2352
    SHRL_PH = 2337,
2353
    SHRL_PH_MMR2  = 2338,
2354
    SHRL_QB = 2339,
2355
    SHRL_QB_MM  = 2340,
2356
    SH_MM = 2341,
2357
    SH_MMR6 = 2342,
2358
    SLDI_B  = 2343,
2359
    SLDI_D  = 2344,
2360
    SLDI_H  = 2345,
2361
    SLDI_W  = 2346,
2362
    SLD_B = 2347,
2363
    SLD_D = 2348,
2364
    SLD_H = 2349,
2365
    SLD_W = 2350,
2366
    SLL = 2351,
2367
    SLL16_MM  = 2352,
2368
    SLL16_MMR6  = 2353,
2369
    SLL64_32  = 2354,
2370
    SLL64_64  = 2355,
2371
    SLLI_B  = 2356,
2372
    SLLI_D  = 2357,
2373
    SLLI_H  = 2358,
2374
    SLLI_W  = 2359,
2375
    SLLV  = 2360,
2376
    SLLV_MM = 2361,
2377
    SLL_B = 2362,
2378
    SLL_D = 2363,
2379
    SLL_H = 2364,
2380
    SLL_MM  = 2365,
2381
    SLL_MMR6  = 2366,
2382
    SLL_W = 2367,
2383
    SLT = 2368,
2384
    SLT64 = 2369,
2385
    SLT_MM  = 2370,
2386
    SLTi  = 2371,
2387
    SLTi64  = 2372,
2388
    SLTi_MM = 2373,
2389
    SLTiu = 2374,
2390
    SLTiu64 = 2375,
2391
    SLTiu_MM  = 2376,
2392
    SLTu  = 2377,
2393
    SLTu64  = 2378,
2394
    SLTu_MM = 2379,
2395
    SNE = 2380,
2396
    SNEi  = 2381,
2397
    SPLATI_B  = 2382,
2398
    SPLATI_D  = 2383,
2399
    SPLATI_H  = 2384,
2400
    SPLATI_W  = 2385,
2401
    SPLAT_B = 2386,
2402
    SPLAT_D = 2387,
2403
    SPLAT_H = 2388,
2404
    SPLAT_W = 2389,
2405
    SRA = 2390,
2406
    SRAI_B  = 2391,
2407
    SRAI_D  = 2392,
2408
    SRAI_H  = 2393,
2409
    SRAI_W  = 2394,
2410
    SRARI_B = 2395,
2411
    SRARI_D = 2396,
2412
    SRARI_H = 2397,
2413
    SRARI_W = 2398,
2414
    SRAR_B  = 2399,
2415
    SRAR_D  = 2400,
2416
    SRAR_H  = 2401,
2417
    SRAR_W  = 2402,
2418
    SRAV  = 2403,
2419
    SRAV_MM = 2404,
2420
    SRA_B = 2405,
2421
    SRA_D = 2406,
2422
    SRA_H = 2407,
2423
    SRA_MM  = 2408,
2424
    SRA_W = 2409,
2425
    SRL = 2410,
2426
    SRL16_MM  = 2411,
2427
    SRL16_MMR6  = 2412,
2428
    SRLI_B  = 2413,
2429
    SRLI_D  = 2414,
2430
    SRLI_H  = 2415,
2431
    SRLI_W  = 2416,
2432
    SRLRI_B = 2417,
2433
    SRLRI_D = 2418,
2434
    SRLRI_H = 2419,
2435
    SRLRI_W = 2420,
2436
    SRLR_B  = 2421,
2437
    SRLR_D  = 2422,
2438
    SRLR_H  = 2423,
2439
    SRLR_W  = 2424,
2440
    SRLV  = 2425,
2441
    SRLV_MM = 2426,
2442
    SRL_B = 2427,
2443
    SRL_D = 2428,
2444
    SRL_H = 2429,
2445
    SRL_MM  = 2430,
2446
    SRL_W = 2431,
2447
    SSNOP = 2432,
2448
    SSNOP_MM  = 2433,
2449
    SSNOP_MMR6  = 2434,
2450
    ST_B  = 2435,
2451
    ST_D  = 2436,
2452
    ST_H  = 2437,
2453
    ST_W  = 2438,
2454
    SUB = 2439,
2455
    SUBQH_PH  = 2440,
2456
    SUBQH_PH_MMR2 = 2441,
2457
    SUBQH_R_PH  = 2442,
2458
    SUBQH_R_PH_MMR2 = 2443,
2459
    SUBQH_R_W = 2444,
2460
    SUBQH_R_W_MMR2  = 2445,
2461
    SUBQH_W = 2446,
2462
    SUBQH_W_MMR2  = 2447,
2463
    SUBQ_PH = 2448,
2464
    SUBQ_PH_MM  = 2449,
2465
    SUBQ_S_PH = 2450,
2466
    SUBQ_S_PH_MM  = 2451,
2467
    SUBQ_S_W  = 2452,
2468
    SUBQ_S_W_MM = 2453,
2469
    SUBSUS_U_B  = 2454,
2470
    SUBSUS_U_D  = 2455,
2471
    SUBSUS_U_H  = 2456,
2472
    SUBSUS_U_W  = 2457,
2473
    SUBSUU_S_B  = 2458,
2474
    SUBSUU_S_D  = 2459,
2475
    SUBSUU_S_H  = 2460,
2476
    SUBSUU_S_W  = 2461,
2477
    SUBS_S_B  = 2462,
2478
    SUBS_S_D  = 2463,
2479
    SUBS_S_H  = 2464,
2480
    SUBS_S_W  = 2465,
2481
    SUBS_U_B  = 2466,
2482
    SUBS_U_D  = 2467,
2483
    SUBS_U_H  = 2468,
2484
    SUBS_U_W  = 2469,
2485
    SUBU16_MM = 2470,
2486
    SUBU16_MMR6 = 2471,
2487
    SUBUH_QB  = 2472,
2488
    SUBUH_QB_MMR2 = 2473,
2489
    SUBUH_R_QB  = 2474,
2490
    SUBUH_R_QB_MMR2 = 2475,
2491
    SUBU_MMR6 = 2476,
2492
    SUBU_PH = 2477,
2493
    SUBU_PH_MMR2  = 2478,
2494
    SUBU_QB = 2479,
2495
    SUBU_QB_MM  = 2480,
2496
    SUBU_S_PH = 2481,
2497
    SUBU_S_PH_MMR2  = 2482,
2498
    SUBU_S_QB = 2483,
2499
    SUBU_S_QB_MM  = 2484,
2500
    SUBVI_B = 2485,
2501
    SUBVI_D = 2486,
2502
    SUBVI_H = 2487,
2503
    SUBVI_W = 2488,
2504
    SUBV_B  = 2489,
2505
    SUBV_D  = 2490,
2506
    SUBV_H  = 2491,
2507
    SUBV_W  = 2492,
2508
    SUB_MM  = 2493,
2509
    SUB_MMR6  = 2494,
2510
    SUBu  = 2495,
2511
    SUBu_MM = 2496,
2512
    SUXC1 = 2497,
2513
    SUXC164 = 2498,
2514
    SUXC1_MM  = 2499,
2515
    SW  = 2500,
2516
    SW16_MM = 2501,
2517
    SW16_MMR6 = 2502,
2518
    SW64  = 2503,
2519
    SWC1  = 2504,
2520
    SWC1_MM = 2505,
2521
    SWC2  = 2506,
2522
    SWC2_MMR6 = 2507,
2523
    SWC2_R6 = 2508,
2524
    SWC3  = 2509,
2525
    SWDSP = 2510,
2526
    SWDSP_MM  = 2511,
2527
    SWE = 2512,
2528
    SWE_MM  = 2513,
2529
    SWL = 2514,
2530
    SWL64 = 2515,
2531
    SWLE  = 2516,
2532
    SWLE_MM = 2517,
2533
    SWL_MM  = 2518,
2534
    SWM16_MM  = 2519,
2535
    SWM16_MMR6  = 2520,
2536
    SWM32_MM  = 2521,
2537
    SWP_MM  = 2522,
2538
    SWR = 2523,
2539
    SWR64 = 2524,
2540
    SWRE  = 2525,
2541
    SWRE_MM = 2526,
2542
    SWR_MM  = 2527,
2543
    SWSP_MM = 2528,
2544
    SWSP_MMR6 = 2529,
2545
    SWXC1 = 2530,
2546
    SWXC1_MM  = 2531,
2547
    SW_MM = 2532,
2548
    SW_MMR6 = 2533,
2549
    SYNC  = 2534,
2550
    SYNCI = 2535,
2551
    SYNCI_MM  = 2536,
2552
    SYNCI_MMR6  = 2537,
2553
    SYNC_MM = 2538,
2554
    SYNC_MMR6 = 2539,
2555
    SYSCALL = 2540,
2556
    SYSCALL_MM  = 2541,
2557
    Save16  = 2542,
2558
    SaveX16 = 2543,
2559
    SbRxRyOffMemX16 = 2544,
2560
    SebRx16 = 2545,
2561
    SehRx16 = 2546,
2562
    ShRxRyOffMemX16 = 2547,
2563
    SllX16  = 2548,
2564
    SllvRxRy16  = 2549,
2565
    SltRxRy16 = 2550,
2566
    SltiRxImm16 = 2551,
2567
    SltiRxImmX16  = 2552,
2568
    SltiuRxImm16  = 2553,
2569
    SltiuRxImmX16 = 2554,
2570
    SltuRxRy16  = 2555,
2571
    SraX16  = 2556,
2572
    SravRxRy16  = 2557,
2573
    SrlX16  = 2558,
2574
    SrlvRxRy16  = 2559,
2575
    SubuRxRyRz16  = 2560,
2576
    SwRxRyOffMemX16 = 2561,
2577
    SwRxSpImmX16  = 2562,
2578
    TEQ = 2563,
2579
    TEQI  = 2564,
2580
    TEQI_MM = 2565,
2581
    TEQ_MM  = 2566,
2582
    TGE = 2567,
2583
    TGEI  = 2568,
2584
    TGEIU = 2569,
2585
    TGEIU_MM  = 2570,
2586
    TGEI_MM = 2571,
2587
    TGEU  = 2572,
2588
    TGEU_MM = 2573,
2589
    TGE_MM  = 2574,
2590
    TLBGINV = 2575,
2591
    TLBGINVF  = 2576,
2592
    TLBGINVF_MM = 2577,
2593
    TLBGINV_MM  = 2578,
2594
    TLBGP = 2579,
2595
    TLBGP_MM  = 2580,
2596
    TLBGR = 2581,
2597
    TLBGR_MM  = 2582,
2598
    TLBGWI  = 2583,
2599
    TLBGWI_MM = 2584,
2600
    TLBGWR  = 2585,
2601
    TLBGWR_MM = 2586,
2602
    TLBINV  = 2587,
2603
    TLBINVF = 2588,
2604
    TLBINVF_MMR6  = 2589,
2605
    TLBINV_MMR6 = 2590,
2606
    TLBP  = 2591,
2607
    TLBP_MM = 2592,
2608
    TLBR  = 2593,
2609
    TLBR_MM = 2594,
2610
    TLBWI = 2595,
2611
    TLBWI_MM  = 2596,
2612
    TLBWR = 2597,
2613
    TLBWR_MM  = 2598,
2614
    TLT = 2599,
2615
    TLTI  = 2600,
2616
    TLTIU_MM  = 2601,
2617
    TLTI_MM = 2602,
2618
    TLTU  = 2603,
2619
    TLTU_MM = 2604,
2620
    TLT_MM  = 2605,
2621
    TNE = 2606,
2622
    TNEI  = 2607,
2623
    TNEI_MM = 2608,
2624
    TNE_MM  = 2609,
2625
    TRUNC_L_D64 = 2610,
2626
    TRUNC_L_D_MMR6  = 2611,
2627
    TRUNC_L_S = 2612,
2628
    TRUNC_L_S_MMR6  = 2613,
2629
    TRUNC_W_D32 = 2614,
2630
    TRUNC_W_D64 = 2615,
2631
    TRUNC_W_D_MMR6  = 2616,
2632
    TRUNC_W_MM  = 2617,
2633
    TRUNC_W_S = 2618,
2634
    TRUNC_W_S_MM  = 2619,
2635
    TRUNC_W_S_MMR6  = 2620,
2636
    TTLTIU  = 2621,
2637
    UDIV  = 2622,
2638
    UDIV_MM = 2623,
2639
    V3MULU  = 2624,
2640
    VMM0  = 2625,
2641
    VMULU = 2626,
2642
    VSHF_B  = 2627,
2643
    VSHF_D  = 2628,
2644
    VSHF_H  = 2629,
2645
    VSHF_W  = 2630,
2646
    WAIT  = 2631,
2647
    WAIT_MM = 2632,
2648
    WAIT_MMR6 = 2633,
2649
    WRDSP = 2634,
2650
    WRDSP_MM  = 2635,
2651
    WRPGPR_MMR6 = 2636,
2652
    WSBH  = 2637,
2653
    WSBH_MM = 2638,
2654
    WSBH_MMR6 = 2639,
2655
    XOR = 2640,
2656
    XOR16_MM  = 2641,
2657
    XOR16_MMR6  = 2642,
2658
    XOR64 = 2643,
2659
    XORI_B  = 2644,
2660
    XORI_MMR6 = 2645,
2661
    XOR_MM  = 2646,
2662
    XOR_MMR6  = 2647,
2663
    XOR_V = 2648,
2664
    XORi  = 2649,
2665
    XORi64  = 2650,
2666
    XORi_MM = 2651,
2667
    XorRxRxRy16 = 2652,
2668
    YIELD = 2653,
2669
    INSTRUCTION_LIST_END = 2654
2670
  };
2671
2672
} // end Mips namespace
2673
} // end llvm namespace
2674
#endif // GET_INSTRINFO_ENUM
2675
2676
#ifdef GET_INSTRINFO_SCHED_ENUM
2677
#undef GET_INSTRINFO_SCHED_ENUM
2678
namespace llvm {
2679
2680
namespace Mips {
2681
namespace Sched {
2682
  enum {
2683
    NoInstrModel  = 0,
2684
    IIPseudo  = 1,
2685
    II_B  = 2,
2686
    II_BCCZAL = 3,
2687
    II_MTC1 = 4,
2688
    II_MFC1 = 5,
2689
    II_JALR = 6,
2690
    II_CVT  = 7,
2691
    II_DMULT  = 8,
2692
    II_DMULTU = 9,
2693
    II_DDIV = 10,
2694
    II_DDIVU  = 11,
2695
    II_IndirectBranchPseudo = 12,
2696
    II_MADD = 13,
2697
    II_MADDU  = 14,
2698
    II_MFHI_MFLO  = 15,
2699
    II_MSUB = 16,
2700
    II_MSUBU  = 17,
2701
    II_MTHI_MTLO  = 18,
2702
    II_MULT = 19,
2703
    II_MULTU  = 20,
2704
    II_ReturnPseudo = 21,
2705
    II_DIV  = 22,
2706
    II_DIVU = 23,
2707
    II_J  = 24,
2708
    II_JR = 25,
2709
    II_TRAP = 26,
2710
    II_ADD  = 27,
2711
    II_ADDIUPC  = 28,
2712
    II_ADDIU  = 29,
2713
    II_ADDU = 30,
2714
    II_ADDI = 31,
2715
    II_ALIGN  = 32,
2716
    II_ALUIPC = 33,
2717
    II_AND  = 34,
2718
    II_ANDI = 35,
2719
    II_AUI  = 36,
2720
    II_AUIPC  = 37,
2721
    IIM16Alu  = 38,
2722
    II_BADDU  = 39,
2723
    II_BC = 40,
2724
    II_BALC = 41,
2725
    II_BBIT = 42,
2726
    II_BC1CCZ = 43,
2727
    II_BC1F = 44,
2728
    II_BC1FL  = 45,
2729
    II_BC1T = 46,
2730
    II_BC1TL  = 47,
2731
    II_BC2CCZ = 48,
2732
    II_BCC  = 49,
2733
    II_BCCC = 50,
2734
    II_BCCZ = 51,
2735
    II_BCCZC  = 52,
2736
    II_BCCZALS  = 53,
2737
    II_BITSWAP  = 54,
2738
    II_BREAK  = 55,
2739
    II_CACHE  = 56,
2740
    II_CACHEE = 57,
2741
    II_CEIL = 58,
2742
    II_CFC1 = 59,
2743
    II_CFC2 = 60,
2744
    II_INS  = 61,
2745
    II_CLASS_D  = 62,
2746
    II_CLASS_S  = 63,
2747
    II_CLO  = 64,
2748
    II_CLZ  = 65,
2749
    II_CMP_CC_D = 66,
2750
    II_CMP_CC_S = 67,
2751
    II_CRC32B = 68,
2752
    II_CRC32CB  = 69,
2753
    II_CRC32CD  = 70,
2754
    II_CRC32CH  = 71,
2755
    II_CRC32CW  = 72,
2756
    II_CRC32D = 73,
2757
    II_CRC32H = 74,
2758
    II_CRC32W = 75,
2759
    II_CTC1 = 76,
2760
    II_CTC2 = 77,
2761
    II_C_CC_D = 78,
2762
    II_C_CC_S = 79,
2763
    II_DADD = 80,
2764
    II_DADDI  = 81,
2765
    II_DADDIU = 82,
2766
    II_DADDU  = 83,
2767
    II_DAHI = 84,
2768
    II_DALIGN = 85,
2769
    II_DATI = 86,
2770
    II_DAUI = 87,
2771
    II_DBITSWAP = 88,
2772
    II_DCLO = 89,
2773
    II_DCLZ = 90,
2774
    II_DERET  = 91,
2775
    II_EXT  = 92,
2776
    II_DI = 93,
2777
    II_DLSA = 94,
2778
    II_DMFC0  = 95,
2779
    II_DMFC1  = 96,
2780
    II_DMFC2  = 97,
2781
    II_DMFGC0 = 98,
2782
    II_DMOD = 99,
2783
    II_DMODU  = 100,
2784
    II_DMT  = 101,
2785
    II_DMTC0  = 102,
2786
    II_DMTC1  = 103,
2787
    II_DMTC2  = 104,
2788
    II_DMTGC0 = 105,
2789
    II_DMUH = 106,
2790
    II_DMUHU  = 107,
2791
    II_DMUL = 108,
2792
    II_POP  = 109,
2793
    II_DROTR  = 110,
2794
    II_DROTR32  = 111,
2795
    II_DROTRV = 112,
2796
    II_DSBH = 113,
2797
    II_DSHD = 114,
2798
    II_DSLL = 115,
2799
    II_DSLL32 = 116,
2800
    II_DSLLV  = 117,
2801
    II_DSRA = 118,
2802
    II_DSRA32 = 119,
2803
    II_DSRAV  = 120,
2804
    II_DSRL = 121,
2805
    II_DSRL32 = 122,
2806
    II_DSRLV  = 123,
2807
    II_DSUB = 124,
2808
    II_DSUBU  = 125,
2809
    II_DVP  = 126,
2810
    II_DVPE = 127,
2811
    II_EHB  = 128,
2812
    II_EI = 129,
2813
    II_EMT  = 130,
2814
    II_ERET = 131,
2815
    II_ERETNC = 132,
2816
    II_EVP  = 133,
2817
    II_EVPE = 134,
2818
    II_ABS  = 135,
2819
    II_SQRT_D = 136,
2820
    II_ADD_D  = 137,
2821
    II_ADD_S  = 138,
2822
    II_DIV_D  = 139,
2823
    II_DIV_S  = 140,
2824
    II_FLOOR  = 141,
2825
    II_MOV_D  = 142,
2826
    II_MOV_S  = 143,
2827
    II_MUL_D  = 144,
2828
    II_MUL_S  = 145,
2829
    II_NEG  = 146,
2830
    II_FORK = 147,
2831
    II_SQRT_S = 148,
2832
    II_SUB_D  = 149,
2833
    II_SUB_S  = 150,
2834
    II_GINVI  = 151,
2835
    II_GINVT  = 152,
2836
    II_HYPCALL  = 153,
2837
    II_JAL  = 154,
2838
    II_JALR_HB  = 155,
2839
    II_JALRC  = 156,
2840
    II_JALRS  = 157,
2841
    II_JALS = 158,
2842
    II_JIALC  = 159,
2843
    II_JIC  = 160,
2844
    II_JRADDIUSP  = 161,
2845
    II_JRC  = 162,
2846
    II_JR_HB  = 163,
2847
    II_LB = 164,
2848
    II_LBE  = 165,
2849
    II_LBU  = 166,
2850
    II_LBUE = 167,
2851
    II_LD = 168,
2852
    II_LDC1 = 169,
2853
    II_LDC2 = 170,
2854
    II_LDC3 = 171,
2855
    II_LDL  = 172,
2856
    II_LDPC = 173,
2857
    II_LDR  = 174,
2858
    II_LDXC1  = 175,
2859
    II_LH = 176,
2860
    II_LHE  = 177,
2861
    II_LHU  = 178,
2862
    II_LHUE = 179,
2863
    II_LI = 180,
2864
    II_LL = 181,
2865
    II_LLD  = 182,
2866
    II_LLE  = 183,
2867
    II_LSA  = 184,
2868
    II_LUI  = 185,
2869
    II_LUXC1  = 186,
2870
    II_LW = 187,
2871
    II_LWC1 = 188,
2872
    II_LWC2 = 189,
2873
    II_LWC3 = 190,
2874
    II_LWE  = 191,
2875
    II_LWL  = 192,
2876
    II_LWLE = 193,
2877
    II_LWM  = 194,
2878
    II_LWPC = 195,
2879
    II_LWP  = 196,
2880
    II_LWR  = 197,
2881
    II_LWRE = 198,
2882
    II_LWUPC  = 199,
2883
    II_LWU  = 200,
2884
    II_LWXC1  = 201,
2885
    II_LWXS = 202,
2886
    II_MADDF_D  = 203,
2887
    II_MADDF_S  = 204,
2888
    II_MADD_D = 205,
2889
    II_MADD_S = 206,
2890
    II_MAX_D  = 207,
2891
    II_MAXA_D = 208,
2892
    II_MAX_S  = 209,
2893
    II_MAXA_S = 210,
2894
    II_MFC0 = 211,
2895
    II_MFC2 = 212,
2896
    II_MFGC0  = 213,
2897
    II_MFHC0  = 214,
2898
    II_MFHC1  = 215,
2899
    II_MFHGC0 = 216,
2900
    II_MFTR = 217,
2901
    II_MIN_S  = 218,
2902
    II_MINA_D = 219,
2903
    II_MIN_D  = 220,
2904
    II_MINA_S = 221,
2905
    II_MOD  = 222,
2906
    II_MODU = 223,
2907
    II_MOVE = 224,
2908
    II_MOVF_D = 225,
2909
    II_MOVF = 226,
2910
    II_MOVF_S = 227,
2911
    II_MOVN_D = 228,
2912
    II_MOVN = 229,
2913
    II_MOVN_S = 230,
2914
    II_MOVT_D = 231,
2915
    II_MOVT = 232,
2916
    II_MOVT_S = 233,
2917
    II_MOVZ_D = 234,
2918
    II_MOVZ = 235,
2919
    II_MOVZ_S = 236,
2920
    II_MSUBF_D  = 237,
2921
    II_MSUBF_S  = 238,
2922
    II_MSUB_D = 239,
2923
    II_MSUB_S = 240,
2924
    II_MTC0 = 241,
2925
    II_MTC2 = 242,
2926
    II_MTGC0  = 243,
2927
    II_MTHC0  = 244,
2928
    II_MTHC1  = 245,
2929
    II_MTHGC0 = 246,
2930
    II_MTTR = 247,
2931
    II_MUH  = 248,
2932
    II_MUHU = 249,
2933
    II_MUL  = 250,
2934
    II_MULU = 251,
2935
    II_NMADD_D  = 252,
2936
    II_NMADD_S  = 253,
2937
    II_NMSUB_D  = 254,
2938
    II_NMSUB_S  = 255,
2939
    II_NOR  = 256,
2940
    II_NOT  = 257,
2941
    II_OR = 258,
2942
    II_ORI  = 259,
2943
    II_PAUSE  = 260,
2944
    II_PREF = 261,
2945
    II_PREFE  = 262,
2946
    II_RDHWR  = 263,
2947
    II_RDPGPR = 264,
2948
    II_RECIP_D  = 265,
2949
    II_RECIP_S  = 266,
2950
    II_RINT_D = 267,
2951
    II_RINT_S = 268,
2952
    II_ROTR = 269,
2953
    II_ROTRV  = 270,
2954
    II_ROUND  = 271,
2955
    II_RSQRT_D  = 272,
2956
    II_RSQRT_S  = 273,
2957
    II_RESTORE  = 274,
2958
    II_SB = 275,
2959
    II_SBE  = 276,
2960
    II_SC = 277,
2961
    II_SCD  = 278,
2962
    II_SCE  = 279,
2963
    II_SD = 280,
2964
    II_SDBBP  = 281,
2965
    II_SDC1 = 282,
2966
    II_SDC2 = 283,
2967
    II_SDC3 = 284,
2968
    II_SDL  = 285,
2969
    II_SDR  = 286,
2970
    II_SDXC1  = 287,
2971
    II_SEB  = 288,
2972
    II_SEH  = 289,
2973
    II_SELCCZ = 290,
2974
    II_SELCCZ_D = 291,
2975
    II_SELCCZ_S = 292,
2976
    II_SEL_D  = 293,
2977
    II_SEL_S  = 294,
2978
    II_SEQ_SNE  = 295,
2979
    II_SEQI_SNEI  = 296,
2980
    II_SH = 297,
2981
    II_SHE  = 298,
2982
    II_SLL  = 299,
2983
    II_SLLV = 300,
2984
    II_SLT_SLTU = 301,
2985
    II_SLTI_SLTIU = 302,
2986
    II_SRA  = 303,
2987
    II_SRAV = 304,
2988
    II_SRL  = 305,
2989
    II_SRLV = 306,
2990
    II_SSNOP  = 307,
2991
    II_SUB  = 308,
2992
    II_SUBU = 309,
2993
    II_SUXC1  = 310,
2994
    II_SW = 311,
2995
    II_SWC1 = 312,
2996
    II_SWC2 = 313,
2997
    II_SWC3 = 314,
2998
    II_SWE  = 315,
2999
    II_SWL  = 316,
3000
    II_SWLE = 317,
3001
    II_SWM  = 318,
3002
    II_SWP  = 319,
3003
    II_SWR  = 320,
3004
    II_SWRE = 321,
3005
    II_SWXC1  = 322,
3006
    II_SYNC = 323,
3007
    II_SYNCI  = 324,
3008
    II_SYSCALL  = 325,
3009
    II_SAVE = 326,
3010
    II_TEQ  = 327,
3011
    II_TEQI = 328,
3012
    II_TGE  = 329,
3013
    II_TGEI = 330,
3014
    II_TGEIU  = 331,
3015
    II_TGEU = 332,
3016
    II_TLBGINV  = 333,
3017
    II_TLBGINVF = 334,
3018
    II_TLBGP  = 335,
3019
    II_TLBGR  = 336,
3020
    II_TLBGWI = 337,
3021
    II_TLBGWR = 338,
3022
    II_TLBINV = 339,
3023
    II_TLBINVF  = 340,
3024
    II_TLBP = 341,
3025
    II_TLBR = 342,
3026
    II_TLBWI  = 343,
3027
    II_TLBWR  = 344,
3028
    II_TLT  = 345,
3029
    II_TLTI = 346,
3030
    II_TTLTIU = 347,
3031
    II_TLTU = 348,
3032
    II_TNE  = 349,
3033
    II_TNEI = 350,
3034
    II_TRUNC  = 351,
3035
    II_WAIT = 352,
3036
    II_WRPGPR = 353,
3037
    II_WSBH = 354,
3038
    II_XOR  = 355,
3039
    II_XORI = 356,
3040
    II_YIELD  = 357,
3041
    AND = 358,
3042
    LUi = 359,
3043
    NOR = 360,
3044
    OR  = 361,
3045
    SLTi_SLTiu  = 362,
3046
    SUB = 363,
3047
    SUBu  = 364,
3048
    XOR = 365,
3049
    B = 366,
3050
    BAL = 367,
3051
    BAL_BR_BGEZAL_BGEZALL_BLTZAL_BLTZALL  = 368,
3052
    BEQ_BEQL_BNE_BNEL = 369,
3053
    BGEZ_BGEZL_BGTZ_BGTZL_BLEZ_BLEZL_BLTZ_BLTZL = 370,
3054
    BREAK = 371,
3055
    DERET = 372,
3056
    ERET  = 373,
3057
    ERETNC  = 374,
3058
    J_TAILCALL  = 375,
3059
    JR_TAILCALLREG_TAILCALLREGHB  = 376,
3060
    JR_HB = 377,
3061
    PseudoIndirectBranch_PseudoIndirectHazardBranch = 378,
3062
    PseudoReturn  = 379,
3063
    SDBBP = 380,
3064
    SSNOP = 381,
3065
    SYSCALL = 382,
3066
    TEQ = 383,
3067
    TEQI  = 384,
3068
    TGE = 385,
3069
    TGEI  = 386,
3070
    TGEIU = 387,
3071
    TGEU  = 388,
3072
    TLT = 389,
3073
    TLTI  = 390,
3074
    TLTU  = 391,
3075
    TNE = 392,
3076
    TNEI  = 393,
3077
    TRAP  = 394,
3078
    TTLTIU  = 395,
3079
    WAIT  = 396,
3080
    PAUSE = 397,
3081
    JAL = 398,
3082
    JALR_JALRHBPseudo_JALRPseudo  = 399,
3083
    JALR_HB = 400,
3084
    JALX  = 401,
3085
    TLBINV  = 402,
3086
    TLBINVF = 403,
3087
    TLBP  = 404,
3088
    TLBR  = 405,
3089
    TLBWI = 406,
3090
    TLBWR = 407,
3091
    MFC0  = 408,
3092
    MTC0  = 409,
3093
    MFC2  = 410,
3094
    MTC2  = 411,
3095
    LB  = 412,
3096
    LBu = 413,
3097
    LH  = 414,
3098
    LHu = 415,
3099
    LW  = 416,
3100
    LL  = 417,
3101
    LWC2  = 418,
3102
    LWC3  = 419,
3103
    LDC2  = 420,
3104
    LDC3  = 421,
3105
    LBE = 422,
3106
    LBuE  = 423,
3107
    LHE = 424,
3108
    LHuE  = 425,
3109
    LWE = 426,
3110
    LLE = 427,
3111
    LWPC  = 428,
3112
    LWL = 429,
3113
    LWR = 430,
3114
    LWLE  = 431,
3115
    LWRE  = 432,
3116
    SB  = 433,
3117
    SH  = 434,
3118
    SW  = 435,
3119
    SWC2  = 436,
3120
    SWC3  = 437,
3121
    SDC2  = 438,
3122
    SDC3  = 439,
3123
    SC  = 440,
3124
    SBE = 441,
3125
    SHE = 442,
3126
    SWE = 443,
3127
    SCE = 444,
3128
    SWL = 445,
3129
    SWR = 446,
3130
    SWLE  = 447,
3131
    SWRE  = 448,
3132
    PREF  = 449,
3133
    PREFE = 450,
3134
    CACHE = 451,
3135
    CACHEE  = 452,
3136
    SYNC  = 453,
3137
    SYNCI = 454,
3138
    CLO = 455,
3139
    CLZ = 456,
3140
    DI  = 457,
3141
    EI  = 458,
3142
    MFHI_MFLO_PseudoMFHI_PseudoMFLO = 459,
3143
    EHB = 460,
3144
    RDHWR = 461,
3145
    WSBH  = 462,
3146
    MOVN_I_I  = 463,
3147
    MOVZ_I_I  = 464,
3148
    DIV_PseudoSDIV_SDIV = 465,
3149
    DIVU_PseudoUDIV_UDIV  = 466,
3150
    MUL = 467,
3151
    MULT_PseudoMULT = 468,
3152
    MULTu_PseudoMULTu = 469,
3153
    MADD_PseudoMADD = 470,
3154
    MADDU_PseudoMADDU = 471,
3155
    MSUB_PseudoMSUB = 472,
3156
    MSUBU_PseudoMSUBU = 473,
3157
    MTHI_MTLO_PseudoMTLOHI  = 474,
3158
    EXT = 475,
3159
    INS = 476,
3160
    ADD = 477,
3161
    ADDi  = 478,
3162
    ADDiu = 479,
3163
    ANDi  = 480,
3164
    ORi = 481,
3165
    ROTR  = 482,
3166
    SEB = 483,
3167
    SEH = 484,
3168
    SLT_SLTu  = 485,
3169
    SLL = 486,
3170
    SRA = 487,
3171
    SRL = 488,
3172
    XORi  = 489,
3173
    ADDu  = 490,
3174
    SLLV  = 491,
3175
    SRAV  = 492,
3176
    SRLV  = 493,
3177
    LSA = 494,
3178
    COPY  = 495,
3179
    VSHF_B_VSHF_D_VSHF_H_VSHF_W = 496,
3180
    BINSLI_B_BINSLI_D_BINSLI_H_BINSLI_W_BINSL_B_BINSL_D_BINSL_H_BINSL_W = 497,
3181
    BINSRI_B_BINSRI_D_BINSRI_H_BINSRI_W_BINSR_B_BINSR_D_BINSR_H_BINSR_W = 498,
3182
    INSERT_B_INSERT_D_INSERT_H_INSERT_W = 499,
3183
    SLDI_B_SLDI_D_SLDI_H_SLDI_W_SLD_B_SLD_D_SLD_H_SLD_W = 500,
3184
    BSETI_B_BSETI_D_BSETI_H_BSETI_W_BSET_B_BSET_D_BSET_H_BSET_W = 501,
3185
    BCLRI_B_BCLRI_D_BCLRI_H_BCLRI_W_BCLR_B_BCLR_D_BCLR_H_BCLR_W = 502,
3186
    BNEGI_B_BNEGI_D_BNEGI_H_BNEGI_W_BNEG_B_BNEG_D_BNEG_H_BNEG_W = 503,
3187
    BSELI_B_BSEL_V  = 504,
3188
    BMNZI_B_BMNZ_V_BMZI_B_BMZ_V = 505,
3189
    PCNT_B_PCNT_D_PCNT_H_PCNT_W = 506,
3190
    SAT_S_B_SAT_S_D_SAT_S_H_SAT_S_W_SAT_U_B_SAT_U_D_SAT_U_H_SAT_U_W = 507,
3191
    BNZ_B_BNZ_D_BNZ_H_BNZ_V_BNZ_W_BZ_B_BZ_D_BZ_H_BZ_V_BZ_W  = 508,
3192
    CFCMSA_CTCMSA = 509,
3193
    FABS_S_FABS_D32_FABS_D64  = 510,
3194
    MOVF_D32_MOVF_D64 = 511,
3195
    MOVF_S  = 512,
3196
    MOVT_D32_MOVT_D64 = 513,
3197
    MOVT_S  = 514,
3198
    FMOV_D32_FMOV_D64 = 515,
3199
    FMOV_S  = 516,
3200
    FNEG_S_FNEG_D32_FNEG_D64  = 517,
3201
    ADD_A_B_ADD_A_D_ADD_A_H_ADD_A_W = 518,
3202
    ADDS_A_B_ADDS_A_D_ADDS_A_H_ADDS_A_W_ADDS_S_B_ADDS_S_D_ADDS_S_H_ADDS_S_W_ADDS_U_B_ADDS_U_D_ADDS_U_H_ADDS_U_W = 519,
3203
    ADDVI_B_ADDVI_D_ADDVI_H_ADDVI_W_ADDV_B_ADDV_D_ADDV_H_ADDV_W = 520,
3204
    ASUB_S_B_ASUB_S_D_ASUB_S_H_ASUB_S_W_ASUB_U_B_ASUB_U_D_ASUB_U_H_ASUB_U_W = 521,
3205
    AVER_S_B_AVER_S_D_AVER_S_H_AVER_S_W_AVER_U_B_AVER_U_D_AVER_U_H_AVER_U_W_AVE_S_B_AVE_S_D_AVE_S_H_AVE_S_W_AVE_U_B_AVE_U_D_AVE_U_H_AVE_U_W = 522,
3206
    SHF_B_SHF_H_SHF_W = 523,
3207
    FILL_B_FILL_D_FILL_H_FILL_W = 524,
3208
    SPLATI_B_SPLATI_D_SPLATI_H_SPLATI_W_SPLAT_B_SPLAT_D_SPLAT_H_SPLAT_W = 525,
3209
    MOVE_V  = 526,
3210
    LDI_B_LDI_D_LDI_H_LDI_W = 527,
3211
    AND_V_NOR_V_OR_V_XOR_V  = 528,
3212
    ANDI_B_NORI_B_ORI_B_XORI_B  = 529,
3213
    FEXP2_D_FEXP2_W = 530,
3214
    CLTI_S_B_CLTI_S_D_CLTI_S_H_CLTI_S_W_CLTI_U_B_CLTI_U_D_CLTI_U_H_CLTI_U_W_CLT_S_B_CLT_S_D_CLT_S_H_CLT_S_W_CLT_U_B_CLT_U_D_CLT_U_H_CLT_U_W = 531,
3215
    CLEI_S_B_CLEI_S_D_CLEI_S_H_CLEI_S_W_CLEI_U_B_CLEI_U_D_CLEI_U_H_CLEI_U_W_CLE_S_B_CLE_S_D_CLE_S_H_CLE_S_W_CLE_U_B_CLE_U_D_CLE_U_H_CLE_U_W = 532,
3216
    CEQI_B_CEQI_D_CEQI_H_CEQI_W_CEQ_B_CEQ_D_CEQ_H_CEQ_W = 533,
3217
    CMP_UN_D  = 534,
3218
    CMP_UN_S  = 535,
3219
    CMP_UEQ_D = 536,
3220
    CMP_UEQ_S = 537,
3221
    CMP_EQ_D  = 538,
3222
    CMP_EQ_S  = 539,
3223
    CMP_LT_D  = 540,
3224
    CMP_LT_S  = 541,
3225
    CMP_ULT_D = 542,
3226
    CMP_ULT_S = 543,
3227
    CMP_LE_D  = 544,
3228
    CMP_LE_S  = 545,
3229
    CMP_ULE_D = 546,
3230
    CMP_ULE_S = 547,
3231
    FSAF_D_FSAF_W_FSEQ_D_FSEQ_W_FSLE_D_FSLE_W_FSLT_D_FSLT_W_FSNE_D_FSNE_W_FSOR_D_FSOR_W = 548,
3232
    FSUEQ_D_FSUEQ_W = 549,
3233
    FSULE_D_FSULE_W = 550,
3234
    FSULT_D_FSULT_W = 551,
3235
    FSUNE_D_FSUNE_W = 552,
3236
    FSUN_D_FSUN_W = 553,
3237
    FCAF_D_FCAF_W = 554,
3238
    FCEQ_D_FCEQ_W = 555,
3239
    FCLE_D_FCLE_W = 556,
3240
    FCLT_D_FCLT_W = 557,
3241
    FCNE_D_FCNE_W = 558,
3242
    FCOR_D_FCOR_W = 559,
3243
    FCUEQ_D_FCUEQ_W = 560,
3244
    FCULE_D_FCULE_W = 561,
3245
    FCULT_D_FCULT_W = 562,
3246
    FCUNE_D_FCUNE_W = 563,
3247
    FCUN_D_FCUN_W = 564,
3248
    FABS_D_FABS_W = 565,
3249
    FFINT_S_D_FFINT_S_W_FFINT_U_D_FFINT_U_W = 566,
3250
    FFQL_D_FFQL_W = 567,
3251
    FFQR_D_FFQR_W = 568,
3252
    FTINT_S_D_FTINT_S_W_FTINT_U_D_FTINT_U_W = 569,
3253
    FRINT_D_FRINT_W = 570,
3254
    FTQ_H_FTQ_W = 571,
3255
    FTRUNC_S_D_FTRUNC_S_W_FTRUNC_U_D_FTRUNC_U_W = 572,
3256
    FEXDO_H_FEXDO_W = 573,
3257
    FEXUPL_D_FEXUPL_W = 574,
3258
    FEXUPR_D_FEXUPR_W = 575,
3259
    FCLASS_D_FCLASS_W = 576,
3260
    FMAX_A_D_FMAX_A_W = 577,
3261
    FMAX_D_FMAX_W = 578,
3262
    FMIN_A_D_FMIN_A_W = 579,
3263
    FMIN_D_FMIN_W = 580,
3264
    FLOG2_D_FLOG2_W = 581,
3265
    ILVL_B_ILVL_D_ILVL_H_ILVL_W_ILVR_B_ILVR_D_ILVR_H_ILVR_W = 582,
3266
    ILVEV_B_ILVEV_D_ILVEV_H_ILVEV_W_ILVOD_B_ILVOD_D_ILVOD_H_ILVOD_W = 583,
3267
    INSVE_B_INSVE_D_INSVE_H_INSVE_W = 584,
3268
    SUBS_S_B_SUBS_S_D_SUBS_S_H_SUBS_S_W_SUBS_U_B_SUBS_U_D_SUBS_U_H_SUBS_U_W = 585,
3269
    SUBSUS_U_B_SUBSUS_U_D_SUBSUS_U_H_SUBSUS_U_W = 586,
3270
    SUBSUU_S_B_SUBSUU_S_D_SUBSUU_S_H_SUBSUU_S_W = 587,
3271
    SUBVI_B_SUBVI_D_SUBVI_H_SUBVI_W = 588,
3272
    SUBV_B_SUBV_D_SUBV_H_SUBV_W = 589,
3273
    MOD_S_B_MOD_S_D_MOD_S_H_MOD_S_W_MOD_U_B_MOD_U_D_MOD_U_H_MOD_U_W = 590,
3274
    DIV_S_B_DIV_S_D_DIV_S_H_DIV_S_W_DIV_U_B_DIV_U_D_DIV_U_H_DIV_U_W = 591,
3275
    HADD_S_D_HADD_S_H_HADD_S_W_HADD_U_D_HADD_U_H_HADD_U_W = 592,
3276
    HSUB_S_D_HSUB_S_H_HSUB_S_W_HSUB_U_D_HSUB_U_H_HSUB_U_W = 593,
3277
    MAX_S_B_MAX_S_D_MAX_S_H_MAX_S_W_MIN_S_B_MIN_S_D_MIN_S_H_MIN_S_W = 594,
3278
    MAX_U_B_MAX_U_D_MAX_U_H_MAX_U_W_MIN_U_B_MIN_U_D_MIN_U_H_MIN_U_W = 595,
3279
    MAX_A_B_MAX_A_D_MAX_A_H_MAX_A_W_MIN_A_B_MIN_A_D_MIN_A_H_MIN_A_W = 596,
3280
    MAXI_S_B_MAXI_S_D_MAXI_S_H_MAXI_S_W_MAXI_U_B_MAXI_U_D_MAXI_U_H_MAXI_U_W_MINI_S_B_MINI_S_D_MINI_S_H_MINI_S_W_MINI_U_B_MINI_U_D_MINI_U_H_MINI_U_W = 597,
3281
    SRAI_B_SRAI_D_SRAI_H_SRAI_W_SRA_B_SRA_D_SRA_H_SRA_W = 598,
3282
    SRLI_B_SRLI_D_SRLI_H_SRLI_W_SRL_B_SRL_D_SRL_H_SRL_W = 599,
3283
    SRARI_B_SRARI_D_SRARI_H_SRARI_W_SRAR_B_SRAR_D_SRAR_H_SRAR_W = 600,
3284
    SRLRI_B_SRLRI_D_SRLRI_H_SRLRI_W_SRLR_B_SRLR_D_SRLR_H_SRLR_W = 601,
3285
    SLLI_B_SLLI_D_SLLI_H_SLLI_W_SLL_B_SLL_D_SLL_H_SLL_W = 602,
3286
    PCKEV_B_PCKEV_D_PCKEV_H_PCKEV_W_PCKOD_B_PCKOD_D_PCKOD_H_PCKOD_W = 603,
3287
    NLOC_B_NLOC_D_NLOC_H_NLOC_W_NLZC_B_NLZC_D_NLZC_H_NLZC_W = 604,
3288
    FADD_D32_FADD_D64 = 605,
3289
    FADD_S  = 606,
3290
    FMUL_D32_FMUL_D64 = 607,
3291
    FMUL_S  = 608,
3292
    FSUB_D32_FSUB_D64 = 609,
3293
    FSUB_S  = 610,
3294
    TRUNC_L_D64_TRUNC_L_S_TRUNC_W_D32_TRUNC_W_D64_TRUNC_W_S = 611,
3295
    CVT_D32_S_CVT_D32_W_CVT_D64_L_CVT_D64_S_CVT_D64_W_CVT_L_D64_CVT_L_S_CVT_S_D32_CVT_S_D64_CVT_S_L_CVT_S_W_CVT_W_D32_CVT_W_D64_CVT_W_S = 612,
3296
    C_EQ_D32_C_EQ_D64_C_F_D32_C_F_D64_C_LE_D32_C_LE_D64_C_LT_D32_C_LT_D64_C_NGE_D32_C_NGE_D64_C_NGLE_D32_C_NGLE_D64_C_NGL_D32_C_NGL_D64_C_NGT_D32_C_NGT_D64_C_OLE_D32_C_OLE_D64_C_OLT_D32_C_OLT_D64_C_SEQ_D32_C_SEQ_D64_C_SF_D32_C_SF_D64_C_UEQ_D32_C_UEQ_D64_C_ULE_D32_C_ULE_D64_C_ULT_D32_C_ULT_D64_C_UN_D32_C_UN_D64 = 613,
3297
    C_EQ_S_C_F_S_C_LE_S_C_LT_S_C_NGE_S_C_NGLE_S_C_NGL_S_C_NGT_S_C_OLE_S_C_OLT_S_C_SEQ_S_C_SF_S_C_UEQ_S_C_ULE_S_C_ULT_S_C_UN_S = 614,
3298
    FCMP_D32_FCMP_D64 = 615,
3299
    FCMP_S32  = 616,
3300
    PseudoCVT_D32_W_PseudoCVT_D64_L_PseudoCVT_D64_W_PseudoCVT_S_L_PseudoCVT_S_W = 617,
3301
    FDIV_S  = 618,
3302
    FDIV_D32_FDIV_D64 = 619,
3303
    FSQRT_S = 620,
3304
    FSQRT_D32_FSQRT_D64 = 621,
3305
    FRCP_D_FRCP_W = 622,
3306
    FRSQRT_D_FRSQRT_W = 623,
3307
    RECIP_D32_RECIP_D64 = 624,
3308
    RSQRT_D32_RSQRT_D64 = 625,
3309
    RECIP_S = 626,
3310
    RSQRT_S = 627,
3311
    FMADD_D_FMADD_W = 628,
3312
    FMSUB_D_FMSUB_W = 629,
3313
    FDIV_W  = 630,
3314
    FDIV_D  = 631,
3315
    FSQRT_W = 632,
3316
    FSQRT_D = 633,
3317
    FMUL_D_FMUL_W = 634,
3318
    FADD_D_FADD_W = 635,
3319
    FSUB_D_FSUB_W = 636,
3320
    DPADD_S_D_DPADD_S_H_DPADD_S_W_DPADD_U_D_DPADD_U_H_DPADD_U_W = 637,
3321
    DPSUB_S_D_DPSUB_S_H_DPSUB_S_W_DPSUB_U_D_DPSUB_U_H_DPSUB_U_W = 638,
3322
    DOTP_S_D_DOTP_S_H_DOTP_S_W_DOTP_U_D_DOTP_U_H_DOTP_U_W = 639,
3323
    MSUBV_B_MSUBV_D_MSUBV_H_MSUBV_W = 640,
3324
    MADDV_B_MADDV_D_MADDV_H_MADDV_W = 641,
3325
    MULV_B_MULV_D_MULV_H_MULV_W = 642,
3326
    MADDR_Q_H_MADDR_Q_W = 643,
3327
    MADD_Q_H_MADD_Q_W = 644,
3328
    MSUBR_Q_H_MSUBR_Q_W = 645,
3329
    MSUB_Q_H_MSUB_Q_W = 646,
3330
    MULR_Q_H_MULR_Q_W = 647,
3331
    MUL_Q_H_MUL_Q_W = 648,
3332
    MADD_D32_MADD_D64 = 649,
3333
    MADD_S  = 650,
3334
    MSUB_D32_MSUB_D64 = 651,
3335
    MSUB_S  = 652,
3336
    NMADD_D32_NMADD_D64 = 653,
3337
    NMADD_S = 654,
3338
    NMSUB_D32_NMSUB_D64 = 655,
3339
    NMSUB_S = 656,
3340
    CTC1  = 657,
3341
    MTC1_MTC1_D64_BuildPairF64_BuildPairF64_64  = 658,
3342
    MTHC1_D32_MTHC1_D64 = 659,
3343
    COPY_U_B_COPY_U_H_COPY_U_W  = 660,
3344
    COPY_S_B_COPY_S_D_COPY_S_H_COPY_S_W = 661,
3345
    BC1F  = 662,
3346
    BC1FL = 663,
3347
    BC1T  = 664,
3348
    BC1TL = 665,
3349
    CFC1  = 666,
3350
    MFC1_MFC1_D64_ExtractElementF64_ExtractElementF64_64  = 667,
3351
    MFHC1_D32_MFHC1_D64 = 668,
3352
    MOVF_I  = 669,
3353
    MOVT_I  = 670,
3354
    SDC1  = 671,
3355
    SDXC1 = 672,
3356
    SUXC1 = 673,
3357
    SWC1  = 674,
3358
    SWXC1 = 675,
3359
    ST_B_ST_D_ST_H_ST_W = 676,
3360
    MOVN_I_D32_MOVN_I_D64 = 677,
3361
    MOVN_I_S  = 678,
3362
    MOVZ_I_D32_MOVZ_I_D64 = 679,
3363
    MOVZ_I_S  = 680,
3364
    LDC1  = 681,
3365
    LDXC1 = 682,
3366
    LWC1  = 683,
3367
    LWXC1 = 684,
3368
    LUXC1 = 685,
3369
    LD_B_LD_D_LD_H_LD_W = 686,
3370
    CEIL_L_D64_CEIL_L_S_CEIL_W_D32_CEIL_W_D64_CEIL_W_S  = 687,
3371
    FLOOR_L_D64_FLOOR_L_S_FLOOR_W_D32_FLOOR_W_D64_FLOOR_W_S = 688,
3372
    ROUND_L_D64_ROUND_L_S_ROUND_W_D32_ROUND_W_D64_ROUND_W_S = 689,
3373
    ROTRV = 690,
3374
    EXTRV_RS_W  = 691,
3375
    EXTRV_R_W = 692,
3376
    EXTRV_S_H = 693,
3377
    EXTRV_W = 694,
3378
    EXTR_RS_W = 695,
3379
    EXTR_R_W  = 696,
3380
    EXTR_S_H  = 697,
3381
    EXTR_W  = 698,
3382
    INSV  = 699,
3383
    MTHLIP  = 700,
3384
    MTHI_DSP  = 701,
3385
    MTLO_DSP  = 702,
3386
    ABSQ_S_PH = 703,
3387
    ABSQ_S_W  = 704,
3388
    ADDQ_PH = 705,
3389
    ADDQ_S_PH = 706,
3390
    ADDQ_S_W  = 707,
3391
    ADDSC = 708,
3392
    ADDU_QB = 709,
3393
    ADDU_S_QB = 710,
3394
    ADDWC = 711,
3395
    BITREV  = 712,
3396
    BPOSGE32  = 713,
3397
    CMPGU_EQ_QB = 714,
3398
    CMPGU_LE_QB = 715,
3399
    CMPGU_LT_QB = 716,
3400
    CMPU_EQ_QB  = 717,
3401
    CMPU_LE_QB  = 718,
3402
    CMPU_LT_QB  = 719,
3403
    CMP_EQ_PH = 720,
3404
    CMP_LE_PH = 721,
3405
    CMP_LT_PH = 722,
3406
    DPAQ_SA_L_W = 723,
3407
    DPAQ_S_W_PH = 724,
3408
    DPAU_H_QBL  = 725,
3409
    DPAU_H_QBR  = 726,
3410
    DPSQ_SA_L_W = 727,
3411
    DPSQ_S_W_PH = 728,
3412
    DPSU_H_QBL  = 729,
3413
    DPSU_H_QBR  = 730,
3414
    EXTPDPV = 731,
3415
    EXTPDP  = 732,
3416
    EXTPV = 733,
3417
    EXTP  = 734,
3418
    LBUX  = 735,
3419
    LHX = 736,
3420
    LWX = 737,
3421
    MADDU_DSP = 738,
3422
    MADD_DSP  = 739,
3423
    MAQ_SA_W_PHL  = 740,
3424
    MAQ_SA_W_PHR  = 741,
3425
    MAQ_S_W_PHL = 742,
3426
    MAQ_S_W_PHR = 743,
3427
    MFHI_DSP  = 744,
3428
    MFLO_DSP  = 745,
3429
    MODSUB  = 746,
3430
    MSUBU_DSP = 747,
3431
    MSUB_DSP  = 748,
3432
    MULEQ_S_W_PHL = 749,
3433
    MULEQ_S_W_PHR = 750,
3434
    MULEU_S_PH_QBL  = 751,
3435
    MULEU_S_PH_QBR  = 752,
3436
    MULQ_RS_PH  = 753,
3437
    MULSAQ_S_W_PH = 754,
3438
    MULTU_DSP = 755,
3439
    MULT_DSP  = 756,
3440
    PACKRL_PH = 757,
3441
    PICK_PH = 758,
3442
    PICK_QB = 759,
3443
    PRECEQU_PH_QBLA = 760,
3444
    PRECEQU_PH_QBL  = 761,
3445
    PRECEQU_PH_QBRA = 762,
3446
    PRECEQU_PH_QBR  = 763,
3447
    PRECEQ_W_PHL  = 764,
3448
    PRECEQ_W_PHR  = 765,
3449
    PRECEU_PH_QBLA  = 766,
3450
    PRECEU_PH_QBL = 767,
3451
    PRECEU_PH_QBRA  = 768,
3452
    PRECEU_PH_QBR = 769,
3453
    PRECRQU_S_QB_PH = 770,
3454
    PRECRQ_PH_W = 771,
3455
    PRECRQ_QB_PH  = 772,
3456
    PRECRQ_RS_PH_W  = 773,
3457
    RADDU_W_QB  = 774,
3458
    RDDSP = 775,
3459
    REPLV_PH  = 776,
3460
    REPLV_QB  = 777,
3461
    REPL_PH = 778,
3462
    REPL_QB = 779,
3463
    SHILOV  = 780,
3464
    SHILO = 781,
3465
    SHLLV_PH  = 782,
3466
    SHLLV_QB  = 783,
3467
    SHLLV_S_PH  = 784,
3468
    SHLLV_S_W = 785,
3469
    SHLL_PH = 786,
3470
    SHLL_QB = 787,
3471
    SHLL_S_PH = 788,
3472
    SHLL_S_W  = 789,
3473
    SHRAV_PH  = 790,
3474
    SHRAV_R_PH  = 791,
3475
    SHRAV_R_W = 792,
3476
    SHRA_PH = 793,
3477
    SHRA_R_PH = 794,
3478
    SHRA_R_W  = 795,
3479
    SHRLV_QB  = 796,
3480
    SHRL_QB = 797,
3481
    SUBQ_PH = 798,
3482
    SUBQ_S_PH = 799,
3483
    SUBQ_S_W  = 800,
3484
    SUBU_QB = 801,
3485
    SUBU_S_QB = 802,
3486
    WRDSP = 803,
3487
    ABSQ_S_QB = 804,
3488
    ADDQH_PH  = 805,
3489
    ADDQH_R_PH  = 806,
3490
    ADDQH_R_W = 807,
3491
    ADDQH_W = 808,
3492
    ADDUH_QB  = 809,
3493
    ADDUH_R_QB  = 810,
3494
    ADDU_PH = 811,
3495
    ADDU_S_PH = 812,
3496
    APPEND  = 813,
3497
    BALIGN  = 814,
3498
    CMPGDU_EQ_QB  = 815,
3499
    CMPGDU_LE_QB  = 816,
3500
    CMPGDU_LT_QB  = 817,
3501
    DPA_W_PH  = 818,
3502
    DPAQX_SA_W_PH = 819,
3503
    DPAQX_S_W_PH  = 820,
3504
    DPAX_W_PH = 821,
3505
    DPS_W_PH  = 822,
3506
    DPSQX_S_W_PH  = 823,
3507
    DPSQX_SA_W_PH = 824,
3508
    DPSX_W_PH = 825,
3509
    MUL_PH  = 826,
3510
    MUL_S_PH  = 827,
3511
    MULQ_RS_W = 828,
3512
    MULQ_S_PH = 829,
3513
    MULQ_S_W  = 830,
3514
    MULSA_W_PH  = 831,
3515
    PRECR_QB_PH = 832,
3516
    PRECR_SRA_PH_W  = 833,
3517
    PRECR_SRA_R_PH_W  = 834,
3518
    PREPEND = 835,
3519
    SHRA_QB = 836,
3520
    SHRA_R_QB = 837,
3521
    SHRAV_QB  = 838,
3522
    SHRAV_R_QB  = 839,
3523
    SHRL_PH = 840,
3524
    SHRLV_PH  = 841,
3525
    SUBQH_PH  = 842,
3526
    SUBQH_R_PH  = 843,
3527
    SUBQH_W = 844,
3528
    SUBQH_R_W = 845,
3529
    SUBU_PH = 846,
3530
    SUBU_S_PH = 847,
3531
    SUBUH_QB  = 848,
3532
    SUBUH_R_QB  = 849,
3533
    ABSQ_S_PH_MM  = 850,
3534
    ABSQ_S_W_MM = 851,
3535
    ADDQ_PH_MM  = 852,
3536
    ADDQ_S_PH_MM  = 853,
3537
    ADDQ_S_W_MM = 854,
3538
    ADDSC_MM  = 855,
3539
    ADDU_QB_MM  = 856,
3540
    ADDU_S_QB_MM  = 857,
3541
    ADDWC_MM  = 858,
3542
    BITREV_MM = 859,
3543
    BPOSGE32_MM = 860,
3544
    CMPGU_EQ_QB_MM  = 861,
3545
    CMPGU_LE_QB_MM  = 862,
3546
    CMPGU_LT_QB_MM  = 863,
3547
    CMPU_EQ_QB_MM = 864,
3548
    CMPU_LE_QB_MM = 865,
3549
    CMPU_LT_QB_MM = 866,
3550
    CMP_EQ_PH_MM  = 867,
3551
    CMP_LE_PH_MM  = 868,
3552
    CMP_LT_PH_MM  = 869,
3553
    DPAQ_SA_L_W_MM  = 870,
3554
    DPAQ_S_W_PH_MM  = 871,
3555
    DPAU_H_QBL_MM = 872,
3556
    DPAU_H_QBR_MM = 873,
3557
    DPSQ_SA_L_W_MM  = 874,
3558
    DPSQ_S_W_PH_MM  = 875,
3559
    DPSU_H_QBL_MM = 876,
3560
    DPSU_H_QBR_MM = 877,
3561
    EXTPDPV_MM  = 878,
3562
    EXTPDP_MM = 879,
3563
    EXTPV_MM  = 880,
3564
    EXTP_MM = 881,
3565
    EXTRV_RS_W_MM = 882,
3566
    EXTRV_R_W_MM  = 883,
3567
    EXTRV_S_H_MM  = 884,
3568
    EXTRV_W_MM  = 885,
3569
    EXTR_RS_W_MM  = 886,
3570
    EXTR_R_W_MM = 887,
3571
    EXTR_S_H_MM = 888,
3572
    EXTR_W_MM = 889,
3573
    INSV_MM = 890,
3574
    LBUX_MM = 891,
3575
    LHX_MM  = 892,
3576
    LWX_MM  = 893,
3577
    MADDU_DSP_MM  = 894,
3578
    MADD_DSP_MM = 895,
3579
    MAQ_SA_W_PHL_MM = 896,
3580
    MAQ_SA_W_PHR_MM = 897,
3581
    MAQ_S_W_PHL_MM  = 898,
3582
    MAQ_S_W_PHR_MM  = 899,
3583
    MFHI_DSP_MM = 900,
3584
    MFLO_DSP_MM = 901,
3585
    MODSUB_MM = 902,
3586
    MOVEP_MM  = 903,
3587
    MOVEP_MMR6  = 904,
3588
    MOVN_I_MM = 905,
3589
    MOVZ_I_MM = 906,
3590
    MSUBU_DSP_MM  = 907,
3591
    MSUB_DSP_MM = 908,
3592
    MTHI_DSP_MM = 909,
3593
    MTHLIP_MM = 910,
3594
    MTLO_DSP_MM = 911,
3595
    MULEQ_S_W_PHL_MM  = 912,
3596
    MULEQ_S_W_PHR_MM  = 913,
3597
    MULEU_S_PH_QBL_MM = 914,
3598
    MULEU_S_PH_QBR_MM = 915,
3599
    MULQ_RS_PH_MM = 916,
3600
    MULSAQ_S_W_PH_MM  = 917,
3601
    MULTU_DSP_MM  = 918,
3602
    MULT_DSP_MM = 919,
3603
    PACKRL_PH_MM  = 920,
3604
    PICK_PH_MM  = 921,
3605
    PICK_QB_MM  = 922,
3606
    PRECEQU_PH_QBLA_MM  = 923,
3607
    PRECEQU_PH_QBL_MM = 924,
3608
    PRECEQU_PH_QBRA_MM  = 925,
3609
    PRECEQU_PH_QBR_MM = 926,
3610
    PRECEQ_W_PHL_MM = 927,
3611
    PRECEQ_W_PHR_MM = 928,
3612
    PRECEU_PH_QBLA_MM = 929,
3613
    PRECEU_PH_QBL_MM  = 930,
3614
    PRECEU_PH_QBRA_MM = 931,
3615
    PRECEU_PH_QBR_MM  = 932,
3616
    PRECRQU_S_QB_PH_MM  = 933,
3617
    PRECRQ_PH_W_MM  = 934,
3618
    PRECRQ_QB_PH_MM = 935,
3619
    PRECRQ_RS_PH_W_MM = 936,
3620
    RADDU_W_QB_MM = 937,
3621
    RDDSP_MM  = 938,
3622
    REPLV_PH_MM = 939,
3623
    REPLV_QB_MM = 940,
3624
    REPL_PH_MM  = 941,
3625
    REPL_QB_MM  = 942,
3626
    SHILOV_MM = 943,
3627
    SHILO_MM  = 944,
3628
    SHLLV_PH_MM = 945,
3629
    SHLLV_QB_MM = 946,
3630
    SHLLV_S_PH_MM = 947,
3631
    SHLLV_S_W_MM  = 948,
3632
    SHLL_PH_MM  = 949,
3633
    SHLL_QB_MM  = 950,
3634
    SHLL_S_PH_MM  = 951,
3635
    SHLL_S_W_MM = 952,
3636
    SHRAV_PH_MM = 953,
3637
    SHRAV_R_PH_MM = 954,
3638
    SHRAV_R_W_MM  = 955,
3639
    SHRA_PH_MM  = 956,
3640
    SHRA_R_PH_MM  = 957,
3641
    SHRA_R_W_MM = 958,
3642
    SHRLV_QB_MM = 959,
3643
    SHRL_QB_MM  = 960,
3644
    SUBQ_PH_MM  = 961,
3645
    SUBQ_S_PH_MM  = 962,
3646
    SUBQ_S_W_MM = 963,
3647
    SUBU_QB_MM  = 964,
3648
    SUBU_S_QB_MM  = 965,
3649
    WRDSP_MM  = 966,
3650
    ABSQ_S_QB_MMR2  = 967,
3651
    ADDQH_PH_MMR2 = 968,
3652
    ADDQH_R_PH_MMR2 = 969,
3653
    ADDQH_R_W_MMR2  = 970,
3654
    ADDQH_W_MMR2  = 971,
3655
    ADDUH_QB_MMR2 = 972,
3656
    ADDUH_R_QB_MMR2 = 973,
3657
    ADDU_PH_MMR2  = 974,
3658
    ADDU_S_PH_MMR2  = 975,
3659
    APPEND_MMR2 = 976,
3660
    BALIGN_MMR2 = 977,
3661
    CMPGDU_EQ_QB_MMR2 = 978,
3662
    CMPGDU_LE_QB_MMR2 = 979,
3663
    CMPGDU_LT_QB_MMR2 = 980,
3664
    DPA_W_PH_MMR2 = 981,
3665
    DPAQX_SA_W_PH_MMR2  = 982,
3666
    DPAQX_S_W_PH_MMR2 = 983,
3667
    DPAX_W_PH_MMR2  = 984,
3668
    DPS_W_PH_MMR2 = 985,
3669
    DPSQX_S_W_PH_MMR2 = 986,
3670
    DPSQX_SA_W_PH_MMR2  = 987,
3671
    DPSX_W_PH_MMR2  = 988,
3672
    MUL_PH_MMR2 = 989,
3673
    MUL_S_PH_MMR2 = 990,
3674
    MULQ_RS_W_MMR2  = 991,
3675
    MULQ_S_PH_MMR2  = 992,
3676
    MULQ_S_W_MMR2 = 993,
3677
    MULSA_W_PH_MMR2 = 994,
3678
    PRECR_QB_PH_MMR2  = 995,
3679
    PRECR_SRA_PH_W_MMR2 = 996,
3680
    PRECR_SRA_R_PH_W_MMR2 = 997,
3681
    PREPEND_MMR2  = 998,
3682
    SHRA_QB_MMR2  = 999,
3683
    SHRA_R_QB_MMR2  = 1000,
3684
    SHRAV_QB_MMR2 = 1001,
3685
    SHRAV_R_QB_MMR2 = 1002,
3686
    SHRL_PH_MMR2  = 1003,
3687
    SHRLV_PH_MMR2 = 1004,
3688
    SUBQH_PH_MMR2 = 1005,
3689
    SUBQH_R_PH_MMR2 = 1006,
3690
    SUBQH_W_MMR2  = 1007,
3691
    SUBQH_R_W_MMR2  = 1008,
3692
    SUBU_PH_MMR2  = 1009,
3693
    SUBU_S_PH_MMR2  = 1010,
3694
    SUBUH_QB_MMR2 = 1011,
3695
    SUBUH_R_QB_MMR2 = 1012,
3696
    BPOSGE32C_MMR3  = 1013,
3697
    SCHED_LIST_END = 1014
3698
  };
3699
} // end Sched namespace
3700
} // end Mips namespace
3701
} // end llvm namespace
3702
#endif // GET_INSTRINFO_SCHED_ENUM
3703
3704
#ifdef GET_INSTRINFO_MC_DESC
3705
#undef GET_INSTRINFO_MC_DESC
3706
namespace llvm {
3707
3708
static const MCPhysReg ImplicitList1[] = { Mips::SP, 0 };
3709
static const MCPhysReg ImplicitList2[] = { Mips::AT, 0 };
3710
static const MCPhysReg ImplicitList3[] = { Mips::RA, 0 };
3711
static const MCPhysReg ImplicitList4[] = { Mips::DSPPos, 0 };
3712
static const MCPhysReg ImplicitList5[] = { Mips::V0, Mips::V1, 0 };
3713
static const MCPhysReg ImplicitList6[] = { Mips::HI0, Mips::LO0, 0 };
3714
static const MCPhysReg ImplicitList7[] = { Mips::T8, 0 };
3715
static const MCPhysReg ImplicitList8[] = { Mips::DSPOutFlag20, 0 };
3716
static const MCPhysReg ImplicitList9[] = { Mips::DSPCarry, 0 };
3717
static const MCPhysReg ImplicitList10[] = { Mips::DSPCCond, 0 };
3718
static const MCPhysReg ImplicitList11[] = { Mips::HI0, Mips::LO0, Mips::P0, Mips::P1, Mips::P2, 0 };
3719
static const MCPhysReg ImplicitList12[] = { Mips::HI0_64, Mips::LO0_64, 0 };
3720
static const MCPhysReg ImplicitList13[] = { Mips::DSPOutFlag16_19, 0 };
3721
static const MCPhysReg ImplicitList14[] = { Mips::DSPEFI, 0 };
3722
static const MCPhysReg ImplicitList15[] = { Mips::DSPPos, Mips::DSPEFI, 0 };
3723
static const MCPhysReg ImplicitList16[] = { Mips::DSPOutFlag23, 0 };
3724
static const MCPhysReg ImplicitList17[] = { Mips::FCC0, 0 };
3725
static const MCPhysReg ImplicitList18[] = { Mips::DSPPos, Mips::DSPSCount, 0 };
3726
static const MCPhysReg ImplicitList19[] = { Mips::AC0, 0 };
3727
static const MCPhysReg ImplicitList20[] = { Mips::AC0_64, 0 };
3728
static const MCPhysReg ImplicitList21[] = { Mips::HI0, 0 };
3729
static const MCPhysReg ImplicitList22[] = { Mips::HI0_64, 0 };
3730
static const MCPhysReg ImplicitList23[] = { Mips::LO0, 0 };
3731
static const MCPhysReg ImplicitList24[] = { Mips::LO0_64, 0 };
3732
static const MCPhysReg ImplicitList25[] = { Mips::MPL0, Mips::P0, Mips::P1, Mips::P2, 0 };
3733
static const MCPhysReg ImplicitList26[] = { Mips::MPL1, Mips::P0, Mips::P1, Mips::P2, 0 };
3734
static const MCPhysReg ImplicitList27[] = { Mips::MPL2, Mips::P0, Mips::P1, Mips::P2, 0 };
3735
static const MCPhysReg ImplicitList28[] = { Mips::P0, 0 };
3736
static const MCPhysReg ImplicitList29[] = { Mips::P1, 0 };
3737
static const MCPhysReg ImplicitList30[] = { Mips::P2, 0 };
3738
static const MCPhysReg ImplicitList31[] = { Mips::DSPOutFlag21, 0 };
3739
static const MCPhysReg ImplicitList32[] = { Mips::DSPOutFlag22, 0 };
3740
static const MCPhysReg ImplicitList33[] = { Mips::P0, Mips::P1, Mips::P2, 0 };
3741
static const MCPhysReg ImplicitList34[] = { Mips::MPL1, Mips::MPL2, Mips::P0, Mips::P1, Mips::P2, 0 };
3742
3743
static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3744
static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3745
static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3746
static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3747
static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3748
static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3749
static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3750
static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3751
static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
3752
static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3753
static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3754
static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3755
static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3756
static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3757
static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3758
static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
3759
static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3760
static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3761
static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3762
static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3763
static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3764
static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
3765
static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
3766
static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
3767
static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
3768
static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3769
static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
3770
static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
3771
static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
3772
static const MCOperandInfo OperandInfo31[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3773
static const MCOperandInfo OperandInfo32[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3774
static const MCOperandInfo OperandInfo33[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3775
static const MCOperandInfo OperandInfo34[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3776
static const MCOperandInfo OperandInfo35[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3777
static const MCOperandInfo OperandInfo36[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3778
static const MCOperandInfo OperandInfo37[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3779
static const MCOperandInfo OperandInfo38[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3780
static const MCOperandInfo OperandInfo39[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3781
static const MCOperandInfo OperandInfo40[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3782
static const MCOperandInfo OperandInfo41[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3783
static const MCOperandInfo OperandInfo42[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3784
static const MCOperandInfo OperandInfo43[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3785
static const MCOperandInfo OperandInfo44[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3786
static const MCOperandInfo OperandInfo45[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3787
static const MCOperandInfo OperandInfo46[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3788
static const MCOperandInfo OperandInfo47[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3789
static const MCOperandInfo OperandInfo48[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3790
static const MCOperandInfo OperandInfo49[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3791
static const MCOperandInfo OperandInfo50[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3792
static const MCOperandInfo OperandInfo51[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3793
static const MCOperandInfo OperandInfo52[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3794
static const MCOperandInfo OperandInfo53[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3795
static const MCOperandInfo OperandInfo54[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3796
static const MCOperandInfo OperandInfo55[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3797
static const MCOperandInfo OperandInfo56[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3798
static const MCOperandInfo OperandInfo57[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3799
static const MCOperandInfo OperandInfo58[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3800
static const MCOperandInfo OperandInfo59[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3801
static const MCOperandInfo OperandInfo60[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3802
static const MCOperandInfo OperandInfo61[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3803
static const MCOperandInfo OperandInfo62[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3804
static const MCOperandInfo OperandInfo63[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3805
static const MCOperandInfo OperandInfo64[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3806
static const MCOperandInfo OperandInfo65[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3807
static const MCOperandInfo OperandInfo66[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3808
static const MCOperandInfo OperandInfo67[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3809
static const MCOperandInfo OperandInfo68[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3810
static const MCOperandInfo OperandInfo69[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3811
static const MCOperandInfo OperandInfo70[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3812
static const MCOperandInfo OperandInfo71[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3813
static const MCOperandInfo OperandInfo72[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3814
static const MCOperandInfo OperandInfo73[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3815
static const MCOperandInfo OperandInfo74[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3816
static const MCOperandInfo OperandInfo75[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3817
static const MCOperandInfo OperandInfo76[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3818
static const MCOperandInfo OperandInfo77[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3819
static const MCOperandInfo OperandInfo78[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3820
static const MCOperandInfo OperandInfo79[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3821
static const MCOperandInfo OperandInfo80[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3822
static const MCOperandInfo OperandInfo81[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3823
static const MCOperandInfo OperandInfo82[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3824
static const MCOperandInfo OperandInfo83[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3825
static const MCOperandInfo OperandInfo84[] = { { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3826
static const MCOperandInfo OperandInfo85[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3827
static const MCOperandInfo OperandInfo86[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3828
static const MCOperandInfo OperandInfo87[] = { { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3829
static const MCOperandInfo OperandInfo88[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3830
static const MCOperandInfo OperandInfo89[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3831
static const MCOperandInfo OperandInfo90[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3832
static const MCOperandInfo OperandInfo91[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3833
static const MCOperandInfo OperandInfo92[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
3834
static const MCOperandInfo OperandInfo93[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3835
static const MCOperandInfo OperandInfo94[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3836
static const MCOperandInfo OperandInfo95[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3837
static const MCOperandInfo OperandInfo96[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3838
static const MCOperandInfo OperandInfo97[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3839
static const MCOperandInfo OperandInfo98[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3840
static const MCOperandInfo OperandInfo99[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3841
static const MCOperandInfo OperandInfo100[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3842
static const MCOperandInfo OperandInfo101[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3843
static const MCOperandInfo OperandInfo102[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3844
static const MCOperandInfo OperandInfo103[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3845
static const MCOperandInfo OperandInfo104[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3846
static const MCOperandInfo OperandInfo105[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3847
static const MCOperandInfo OperandInfo106[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3848
static const MCOperandInfo OperandInfo107[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3849
static const MCOperandInfo OperandInfo108[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3850
static const MCOperandInfo OperandInfo109[] = { { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3851
static const MCOperandInfo OperandInfo110[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3852
static const MCOperandInfo OperandInfo111[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3853
static const MCOperandInfo OperandInfo112[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3854
static const MCOperandInfo OperandInfo113[] = { { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3855
static const MCOperandInfo OperandInfo114[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3856
static const MCOperandInfo OperandInfo115[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3857
static const MCOperandInfo OperandInfo116[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3858
static const MCOperandInfo OperandInfo117[] = { { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3859
static const MCOperandInfo OperandInfo118[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
3860
static const MCOperandInfo OperandInfo119[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3861
static const MCOperandInfo OperandInfo120[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3862
static const MCOperandInfo OperandInfo121[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3863
static const MCOperandInfo OperandInfo122[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3864
static const MCOperandInfo OperandInfo123[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3865
static const MCOperandInfo OperandInfo124[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3866
static const MCOperandInfo OperandInfo125[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3867
static const MCOperandInfo OperandInfo126[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3868
static const MCOperandInfo OperandInfo127[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3869
static const MCOperandInfo OperandInfo128[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3870
static const MCOperandInfo OperandInfo129[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3871
static const MCOperandInfo OperandInfo130[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3872
static const MCOperandInfo OperandInfo131[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3873
static const MCOperandInfo OperandInfo132[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3874
static const MCOperandInfo OperandInfo133[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3875
static const MCOperandInfo OperandInfo134[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3876
static const MCOperandInfo OperandInfo135[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3877
static const MCOperandInfo OperandInfo136[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3878
static const MCOperandInfo OperandInfo137[] = { { Mips::GPR32NONZERORegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3879
static const MCOperandInfo OperandInfo138[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3880
static const MCOperandInfo OperandInfo139[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3881
static const MCOperandInfo OperandInfo140[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3882
static const MCOperandInfo OperandInfo141[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3883
static const MCOperandInfo OperandInfo142[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3884
static const MCOperandInfo OperandInfo143[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3885
static const MCOperandInfo OperandInfo144[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3886
static const MCOperandInfo OperandInfo145[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3887
static const MCOperandInfo OperandInfo146[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3888
static const MCOperandInfo OperandInfo147[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3889
static const MCOperandInfo OperandInfo148[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3890
static const MCOperandInfo OperandInfo149[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3891
static const MCOperandInfo OperandInfo150[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3892
static const MCOperandInfo OperandInfo151[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3893
static const MCOperandInfo OperandInfo152[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3894
static const MCOperandInfo OperandInfo153[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3895
static const MCOperandInfo OperandInfo154[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3896
static const MCOperandInfo OperandInfo155[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3897
static const MCOperandInfo OperandInfo156[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3898
static const MCOperandInfo OperandInfo157[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3899
static const MCOperandInfo OperandInfo158[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
3900
static const MCOperandInfo OperandInfo159[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
3901
static const MCOperandInfo OperandInfo160[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3902
static const MCOperandInfo OperandInfo161[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3903
static const MCOperandInfo OperandInfo162[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsPlusSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3904
static const MCOperandInfo OperandInfo163[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3905
static const MCOperandInfo OperandInfo164[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3906
static const MCOperandInfo OperandInfo165[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3907
static const MCOperandInfo OperandInfo166[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3908
static const MCOperandInfo OperandInfo167[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3909
static const MCOperandInfo OperandInfo168[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3910
static const MCOperandInfo OperandInfo169[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3911
static const MCOperandInfo OperandInfo170[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3912
static const MCOperandInfo OperandInfo171[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3913
static const MCOperandInfo OperandInfo172[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3914
static const MCOperandInfo OperandInfo173[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3915
static const MCOperandInfo OperandInfo174[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3916
static const MCOperandInfo OperandInfo175[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3917
static const MCOperandInfo OperandInfo176[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3918
static const MCOperandInfo OperandInfo177[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3919
static const MCOperandInfo OperandInfo178[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3920
static const MCOperandInfo OperandInfo179[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3921
static const MCOperandInfo OperandInfo180[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3922
static const MCOperandInfo OperandInfo181[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
3923
static const MCOperandInfo OperandInfo182[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3924
static const MCOperandInfo OperandInfo183[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3925
static const MCOperandInfo OperandInfo184[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3926
static const MCOperandInfo OperandInfo185[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3927
static const MCOperandInfo OperandInfo186[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3928
static const MCOperandInfo OperandInfo187[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3929
static const MCOperandInfo OperandInfo188[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3930
static const MCOperandInfo OperandInfo189[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3931
static const MCOperandInfo OperandInfo190[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3932
static const MCOperandInfo OperandInfo191[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3933
static const MCOperandInfo OperandInfo192[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3934
static const MCOperandInfo OperandInfo193[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3935
static const MCOperandInfo OperandInfo194[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3936
static const MCOperandInfo OperandInfo195[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3937
static const MCOperandInfo OperandInfo196[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3938
static const MCOperandInfo OperandInfo197[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3939
static const MCOperandInfo OperandInfo198[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3940
static const MCOperandInfo OperandInfo199[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3941
static const MCOperandInfo OperandInfo200[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3942
static const MCOperandInfo OperandInfo201[] = { { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3943
static const MCOperandInfo OperandInfo202[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3944
static const MCOperandInfo OperandInfo203[] = { { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3945
static const MCOperandInfo OperandInfo204[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3946
static const MCOperandInfo OperandInfo205[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3947
static const MCOperandInfo OperandInfo206[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3948
static const MCOperandInfo OperandInfo207[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3949
static const MCOperandInfo OperandInfo208[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3950
static const MCOperandInfo OperandInfo209[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3951
static const MCOperandInfo OperandInfo210[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3952
static const MCOperandInfo OperandInfo211[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
3953
static const MCOperandInfo OperandInfo212[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3954
static const MCOperandInfo OperandInfo213[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3955
static const MCOperandInfo OperandInfo214[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3956
static const MCOperandInfo OperandInfo215[] = { { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3957
static const MCOperandInfo OperandInfo216[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3958
static const MCOperandInfo OperandInfo217[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3959
static const MCOperandInfo OperandInfo218[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3960
static const MCOperandInfo OperandInfo219[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3961
static const MCOperandInfo OperandInfo220[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3962
static const MCOperandInfo OperandInfo221[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3963
static const MCOperandInfo OperandInfo222[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3964
static const MCOperandInfo OperandInfo223[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
3965
static const MCOperandInfo OperandInfo224[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3966
static const MCOperandInfo OperandInfo225[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3967
static const MCOperandInfo OperandInfo226[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3968
static const MCOperandInfo OperandInfo227[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3969
static const MCOperandInfo OperandInfo228[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3970
static const MCOperandInfo OperandInfo229[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3971
static const MCOperandInfo OperandInfo230[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3972
static const MCOperandInfo OperandInfo231[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3973
static const MCOperandInfo OperandInfo232[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3974
static const MCOperandInfo OperandInfo233[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3975
static const MCOperandInfo OperandInfo234[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3976
static const MCOperandInfo OperandInfo235[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3977
static const MCOperandInfo OperandInfo236[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3978
static const MCOperandInfo OperandInfo237[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3979
static const MCOperandInfo OperandInfo238[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3980
static const MCOperandInfo OperandInfo239[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3981
static const MCOperandInfo OperandInfo240[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3982
static const MCOperandInfo OperandInfo241[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3983
static const MCOperandInfo OperandInfo242[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3984
static const MCOperandInfo OperandInfo243[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
3985
static const MCOperandInfo OperandInfo244[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3986
static const MCOperandInfo OperandInfo245[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3987
static const MCOperandInfo OperandInfo246[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3988
static const MCOperandInfo OperandInfo247[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3989
static const MCOperandInfo OperandInfo248[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3990
static const MCOperandInfo OperandInfo249[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3991
static const MCOperandInfo OperandInfo250[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3992
static const MCOperandInfo OperandInfo251[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3993
static const MCOperandInfo OperandInfo252[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
3994
static const MCOperandInfo OperandInfo253[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
3995
static const MCOperandInfo OperandInfo254[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3996
static const MCOperandInfo OperandInfo255[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
3997
static const MCOperandInfo OperandInfo256[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3998
static const MCOperandInfo OperandInfo257[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
3999
static const MCOperandInfo OperandInfo258[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4000
static const MCOperandInfo OperandInfo259[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4001
static const MCOperandInfo OperandInfo260[] = { { Mips::COP3RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4002
static const MCOperandInfo OperandInfo261[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4003
static const MCOperandInfo OperandInfo262[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4004
static const MCOperandInfo OperandInfo263[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4005
static const MCOperandInfo OperandInfo264[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4006
static const MCOperandInfo OperandInfo265[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4007
static const MCOperandInfo OperandInfo266[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
4008
static const MCOperandInfo OperandInfo267[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
4009
static const MCOperandInfo OperandInfo268[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4010
static const MCOperandInfo OperandInfo269[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4011
static const MCOperandInfo OperandInfo270[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4012
static const MCOperandInfo OperandInfo271[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4013
static const MCOperandInfo OperandInfo272[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4014
static const MCOperandInfo OperandInfo273[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4015
static const MCOperandInfo OperandInfo274[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 3, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4016
static const MCOperandInfo OperandInfo275[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4017
static const MCOperandInfo OperandInfo276[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 2, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4018
static const MCOperandInfo OperandInfo277[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4019
static const MCOperandInfo OperandInfo278[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 2, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4020
static const MCOperandInfo OperandInfo279[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
4021
static const MCOperandInfo OperandInfo280[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4022
static const MCOperandInfo OperandInfo281[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4023
static const MCOperandInfo OperandInfo282[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4024
static const MCOperandInfo OperandInfo283[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4025
static const MCOperandInfo OperandInfo284[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4026
static const MCOperandInfo OperandInfo285[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4027
static const MCOperandInfo OperandInfo286[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4028
static const MCOperandInfo OperandInfo287[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4029
static const MCOperandInfo OperandInfo288[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4030
static const MCOperandInfo OperandInfo289[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4031
static const MCOperandInfo OperandInfo290[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4032
static const MCOperandInfo OperandInfo291[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4033
static const MCOperandInfo OperandInfo292[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4034
static const MCOperandInfo OperandInfo293[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4035
static const MCOperandInfo OperandInfo294[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4036
static const MCOperandInfo OperandInfo295[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4037
static const MCOperandInfo OperandInfo296[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4038
static const MCOperandInfo OperandInfo297[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4039
static const MCOperandInfo OperandInfo298[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4040
static const MCOperandInfo OperandInfo299[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4041
static const MCOperandInfo OperandInfo300[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4042
static const MCOperandInfo OperandInfo301[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4043
static const MCOperandInfo OperandInfo302[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4044
static const MCOperandInfo OperandInfo303[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4045
static const MCOperandInfo OperandInfo304[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4046
static const MCOperandInfo OperandInfo305[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4047
static const MCOperandInfo OperandInfo306[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4048
static const MCOperandInfo OperandInfo307[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4049
static const MCOperandInfo OperandInfo308[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4050
static const MCOperandInfo OperandInfo309[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4051
static const MCOperandInfo OperandInfo310[] = { { Mips::HI32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4052
static const MCOperandInfo OperandInfo311[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4053
static const MCOperandInfo OperandInfo312[] = { { Mips::LO32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4054
static const MCOperandInfo OperandInfo313[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4055
static const MCOperandInfo OperandInfo314[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4056
static const MCOperandInfo OperandInfo315[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4057
static const MCOperandInfo OperandInfo316[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4058
static const MCOperandInfo OperandInfo317[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4059
static const MCOperandInfo OperandInfo318[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4060
static const MCOperandInfo OperandInfo319[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4061
static const MCOperandInfo OperandInfo320[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4062
static const MCOperandInfo OperandInfo321[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4063
static const MCOperandInfo OperandInfo322[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4064
static const MCOperandInfo OperandInfo323[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4065
static const MCOperandInfo OperandInfo324[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4066
static const MCOperandInfo OperandInfo325[] = { { Mips::GPRMM16ZeroRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4067
static const MCOperandInfo OperandInfo326[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4068
static const MCOperandInfo OperandInfo327[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4069
static const MCOperandInfo OperandInfo328[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4070
static const MCOperandInfo OperandInfo329[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4071
static const MCOperandInfo OperandInfo330[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4072
static const MCOperandInfo OperandInfo331[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4073
static const MCOperandInfo OperandInfo332[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4074
static const MCOperandInfo OperandInfo333[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4075
static const MCOperandInfo OperandInfo334[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4076
static const MCOperandInfo OperandInfo335[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4077
static const MCOperandInfo OperandInfo336[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4078
static const MCOperandInfo OperandInfo337[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4079
static const MCOperandInfo OperandInfo338[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4080
static const MCOperandInfo OperandInfo339[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4081
static const MCOperandInfo OperandInfo340[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4082
static const MCOperandInfo OperandInfo341[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4083
static const MCOperandInfo OperandInfo342[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
4084
static const MCOperandInfo OperandInfo343[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
4085
4086
extern const MCInstrDesc MipsInsts[] = {
4087
  { 0,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
4088
  { 1,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
4089
  { 2,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #2 = CFI_INSTRUCTION
4090
  { 3,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = EH_LABEL
4091
  { 4,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = GC_LABEL
4092
  { 5,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = ANNOTATION_LABEL
4093
  { 6,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #6 = KILL
4094
  { 7,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #7 = EXTRACT_SUBREG
4095
  { 8,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #8 = INSERT_SUBREG
4096
  { 9,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #9 = IMPLICIT_DEF
4097
  { 10, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #10 = SUBREG_TO_REG
4098
  { 11, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #11 = COPY_TO_REGCLASS
4099
  { 12, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #12 = DBG_VALUE
4100
  { 13, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #13 = DBG_LABEL
4101
  { 14, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #14 = REG_SEQUENCE
4102
  { 15, 2,  1,  0,  495,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #15 = COPY
4103
  { 16, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #16 = BUNDLE
4104
  { 17, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #17 = LIFETIME_START
4105
  { 18, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #18 = LIFETIME_END
4106
  { 19, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #19 = STACKMAP
4107
  { 20, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #20 = FENTRY_CALL
4108
  { 21, 6,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #21 = PATCHPOINT
4109
  { 22, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #22 = LOAD_STACK_GUARD
4110
  { 23, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #23 = STATEPOINT
4111
  { 24, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #24 = LOCAL_ESCAPE
4112
  { 25, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #25 = FAULTING_OP
4113
  { 26, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #26 = PATCHABLE_OP
4114
  { 27, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #27 = PATCHABLE_FUNCTION_ENTER
4115
  { 28, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #28 = PATCHABLE_RET
4116
  { 29, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #29 = PATCHABLE_FUNCTION_EXIT
4117
  { 30, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #30 = PATCHABLE_TAIL_CALL
4118
  { 31, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #31 = PATCHABLE_EVENT_CALL
4119
  { 32, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #32 = PATCHABLE_TYPED_EVENT_CALL
4120
  { 33, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #33 = ICALL_BRANCH_FUNNEL
4121
  { 34, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #34 = G_ADD
4122
  { 35, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #35 = G_SUB
4123
  { 36, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #36 = G_MUL
4124
  { 37, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #37 = G_SDIV
4125
  { 38, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #38 = G_UDIV
4126
  { 39, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #39 = G_SREM
4127
  { 40, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #40 = G_UREM
4128
  { 41, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_AND
4129
  { 42, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_OR
4130
  { 43, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #43 = G_XOR
4131
  { 44, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #44 = G_IMPLICIT_DEF
4132
  { 45, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #45 = G_PHI
4133
  { 46, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #46 = G_FRAME_INDEX
4134
  { 47, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #47 = G_GLOBAL_VALUE
4135
  { 48, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #48 = G_EXTRACT
4136
  { 49, 2,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #49 = G_UNMERGE_VALUES
4137
  { 50, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #50 = G_INSERT
4138
  { 51, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #51 = G_MERGE_VALUES
4139
  { 52, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #52 = G_PTRTOINT
4140
  { 53, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = G_INTTOPTR
4141
  { 54, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #54 = G_BITCAST
4142
  { 55, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #55 = G_INTRINSIC_TRUNC
4143
  { 56, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #56 = G_INTRINSIC_ROUND
4144
  { 57, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #57 = G_LOAD
4145
  { 58, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #58 = G_SEXTLOAD
4146
  { 59, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #59 = G_ZEXTLOAD
4147
  { 60, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #60 = G_STORE
4148
  { 61, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #61 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
4149
  { 62, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #62 = G_ATOMIC_CMPXCHG
4150
  { 63, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #63 = G_ATOMICRMW_XCHG
4151
  { 64, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #64 = G_ATOMICRMW_ADD
4152
  { 65, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #65 = G_ATOMICRMW_SUB
4153
  { 66, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #66 = G_ATOMICRMW_AND
4154
  { 67, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #67 = G_ATOMICRMW_NAND
4155
  { 68, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #68 = G_ATOMICRMW_OR
4156
  { 69, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #69 = G_ATOMICRMW_XOR
4157
  { 70, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #70 = G_ATOMICRMW_MAX
4158
  { 71, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #71 = G_ATOMICRMW_MIN
4159
  { 72, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #72 = G_ATOMICRMW_UMAX
4160
  { 73, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #73 = G_ATOMICRMW_UMIN
4161
  { 74, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #74 = G_BRCOND
4162
  { 75, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #75 = G_BRINDIRECT
4163
  { 76, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #76 = G_INTRINSIC
4164
  { 77, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #77 = G_INTRINSIC_W_SIDE_EFFECTS
4165
  { 78, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #78 = G_ANYEXT
4166
  { 79, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #79 = G_TRUNC
4167
  { 80, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #80 = G_CONSTANT
4168
  { 81, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #81 = G_FCONSTANT
4169
  { 82, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #82 = G_VASTART
4170
  { 83, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #83 = G_VAARG
4171
  { 84, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #84 = G_SEXT
4172
  { 85, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #85 = G_ZEXT
4173
  { 86, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #86 = G_SHL
4174
  { 87, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #87 = G_LSHR
4175
  { 88, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #88 = G_ASHR
4176
  { 89, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #89 = G_ICMP
4177
  { 90, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #90 = G_FCMP
4178
  { 91, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #91 = G_SELECT
4179
  { 92, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #92 = G_UADDO
4180
  { 93, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #93 = G_UADDE
4181
  { 94, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #94 = G_USUBO
4182
  { 95, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #95 = G_USUBE
4183
  { 96, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #96 = G_SADDO
4184
  { 97, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #97 = G_SADDE
4185
  { 98, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #98 = G_SSUBO
4186
  { 99, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #99 = G_SSUBE
4187
  { 100,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #100 = G_UMULO
4188
  { 101,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #101 = G_SMULO
4189
  { 102,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #102 = G_UMULH
4190
  { 103,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #103 = G_SMULH
4191
  { 104,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #104 = G_FADD
4192
  { 105,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #105 = G_FSUB
4193
  { 106,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #106 = G_FMUL
4194
  { 107,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #107 = G_FMA
4195
  { 108,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #108 = G_FDIV
4196
  { 109,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #109 = G_FREM
4197
  { 110,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #110 = G_FPOW
4198
  { 111,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #111 = G_FEXP
4199
  { 112,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #112 = G_FEXP2
4200
  { 113,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #113 = G_FLOG
4201
  { 114,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #114 = G_FLOG2
4202
  { 115,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #115 = G_FNEG
4203
  { 116,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #116 = G_FPEXT
4204
  { 117,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #117 = G_FPTRUNC
4205
  { 118,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #118 = G_FPTOSI
4206
  { 119,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #119 = G_FPTOUI
4207
  { 120,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #120 = G_SITOFP
4208
  { 121,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #121 = G_UITOFP
4209
  { 122,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #122 = G_FABS
4210
  { 123,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #123 = G_GEP
4211
  { 124,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #124 = G_PTR_MASK
4212
  { 125,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #125 = G_BR
4213
  { 126,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #126 = G_INSERT_VECTOR_ELT
4214
  { 127,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #127 = G_EXTRACT_VECTOR_ELT
4215
  { 128,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #128 = G_SHUFFLE_VECTOR
4216
  { 129,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #129 = G_CTTZ
4217
  { 130,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #130 = G_CTTZ_ZERO_UNDEF
4218
  { 131,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #131 = G_CTLZ
4219
  { 132,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #132 = G_CTLZ_ZERO_UNDEF
4220
  { 133,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #133 = G_CTPOP
4221
  { 134,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #134 = G_BSWAP
4222
  { 135,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #135 = G_ADDRSPACE_CAST
4223
  { 136,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #136 = G_BLOCK_ADDR
4224
  { 137,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #137 = ABSMacro
4225
  { 138,  2,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr },  // Inst #138 = ADJCALLSTACKDOWN
4226
  { 139,  2,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr },  // Inst #139 = ADJCALLSTACKUP
4227
  { 140,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #140 = AND_V_D_PSEUDO
4228
  { 141,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #141 = AND_V_H_PSEUDO
4229
  { 142,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #142 = AND_V_W_PSEUDO
4230
  { 143,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #143 = ATOMIC_CMP_SWAP_I16
4231
  { 144,  7,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #144 = ATOMIC_CMP_SWAP_I16_POSTRA
4232
  { 145,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #145 = ATOMIC_CMP_SWAP_I32
4233
  { 146,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #146 = ATOMIC_CMP_SWAP_I32_POSTRA
4234
  { 147,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #147 = ATOMIC_CMP_SWAP_I64
4235
  { 148,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #148 = ATOMIC_CMP_SWAP_I64_POSTRA
4236
  { 149,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #149 = ATOMIC_CMP_SWAP_I8
4237
  { 150,  7,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #150 = ATOMIC_CMP_SWAP_I8_POSTRA
4238
  { 151,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #151 = ATOMIC_LOAD_ADD_I16
4239
  { 152,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #152 = ATOMIC_LOAD_ADD_I16_POSTRA
4240
  { 153,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #153 = ATOMIC_LOAD_ADD_I32
4241
  { 154,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #154 = ATOMIC_LOAD_ADD_I32_POSTRA
4242
  { 155,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #155 = ATOMIC_LOAD_ADD_I64
4243
  { 156,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #156 = ATOMIC_LOAD_ADD_I64_POSTRA
4244
  { 157,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #157 = ATOMIC_LOAD_ADD_I8
4245
  { 158,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #158 = ATOMIC_LOAD_ADD_I8_POSTRA
4246
  { 159,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #159 = ATOMIC_LOAD_AND_I16
4247
  { 160,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #160 = ATOMIC_LOAD_AND_I16_POSTRA
4248
  { 161,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #161 = ATOMIC_LOAD_AND_I32
4249
  { 162,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #162 = ATOMIC_LOAD_AND_I32_POSTRA
4250
  { 163,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #163 = ATOMIC_LOAD_AND_I64
4251
  { 164,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #164 = ATOMIC_LOAD_AND_I64_POSTRA
4252
  { 165,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #165 = ATOMIC_LOAD_AND_I8
4253
  { 166,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #166 = ATOMIC_LOAD_AND_I8_POSTRA
4254
  { 167,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #167 = ATOMIC_LOAD_NAND_I16
4255
  { 168,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #168 = ATOMIC_LOAD_NAND_I16_POSTRA
4256
  { 169,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #169 = ATOMIC_LOAD_NAND_I32
4257
  { 170,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #170 = ATOMIC_LOAD_NAND_I32_POSTRA
4258
  { 171,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #171 = ATOMIC_LOAD_NAND_I64
4259
  { 172,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #172 = ATOMIC_LOAD_NAND_I64_POSTRA
4260
  { 173,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #173 = ATOMIC_LOAD_NAND_I8
4261
  { 174,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #174 = ATOMIC_LOAD_NAND_I8_POSTRA
4262
  { 175,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #175 = ATOMIC_LOAD_OR_I16
4263
  { 176,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #176 = ATOMIC_LOAD_OR_I16_POSTRA
4264
  { 177,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #177 = ATOMIC_LOAD_OR_I32
4265
  { 178,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #178 = ATOMIC_LOAD_OR_I32_POSTRA
4266
  { 179,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #179 = ATOMIC_LOAD_OR_I64
4267
  { 180,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #180 = ATOMIC_LOAD_OR_I64_POSTRA
4268
  { 181,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #181 = ATOMIC_LOAD_OR_I8
4269
  { 182,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #182 = ATOMIC_LOAD_OR_I8_POSTRA
4270
  { 183,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #183 = ATOMIC_LOAD_SUB_I16
4271
  { 184,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #184 = ATOMIC_LOAD_SUB_I16_POSTRA
4272
  { 185,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #185 = ATOMIC_LOAD_SUB_I32
4273
  { 186,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #186 = ATOMIC_LOAD_SUB_I32_POSTRA
4274
  { 187,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #187 = ATOMIC_LOAD_SUB_I64
4275
  { 188,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #188 = ATOMIC_LOAD_SUB_I64_POSTRA
4276
  { 189,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #189 = ATOMIC_LOAD_SUB_I8
4277
  { 190,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #190 = ATOMIC_LOAD_SUB_I8_POSTRA
4278
  { 191,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #191 = ATOMIC_LOAD_XOR_I16
4279
  { 192,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #192 = ATOMIC_LOAD_XOR_I16_POSTRA
4280
  { 193,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #193 = ATOMIC_LOAD_XOR_I32
4281
  { 194,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #194 = ATOMIC_LOAD_XOR_I32_POSTRA
4282
  { 195,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #195 = ATOMIC_LOAD_XOR_I64
4283
  { 196,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #196 = ATOMIC_LOAD_XOR_I64_POSTRA
4284
  { 197,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #197 = ATOMIC_LOAD_XOR_I8
4285
  { 198,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #198 = ATOMIC_LOAD_XOR_I8_POSTRA
4286
  { 199,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #199 = ATOMIC_SWAP_I16
4287
  { 200,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #200 = ATOMIC_SWAP_I16_POSTRA
4288
  { 201,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #201 = ATOMIC_SWAP_I32
4289
  { 202,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #202 = ATOMIC_SWAP_I32_POSTRA
4290
  { 203,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #203 = ATOMIC_SWAP_I64
4291
  { 204,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #204 = ATOMIC_SWAP_I64_POSTRA
4292
  { 205,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #205 = ATOMIC_SWAP_I8
4293
  { 206,  6,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #206 = ATOMIC_SWAP_I8_POSTRA
4294
  { 207,  1,  0,  4,  366,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, ImplicitList2, OperandInfo41, -1 ,nullptr },  // Inst #207 = B
4295
  { 208,  1,  0,  4,  368,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, ImplicitList3, OperandInfo41, -1 ,nullptr },  // Inst #208 = BAL_BR
4296
  { 209,  1,  0,  4,  3,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, ImplicitList3, OperandInfo41, -1 ,nullptr },  // Inst #209 = BAL_BR_MM
4297
  { 210,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #210 = BEQLImmMacro
4298
  { 211,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #211 = BGE
4299
  { 212,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #212 = BGEImmMacro
4300
  { 213,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #213 = BGEL
4301
  { 214,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #214 = BGELImmMacro
4302
  { 215,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #215 = BGEU
4303
  { 216,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #216 = BGEUImmMacro
4304
  { 217,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #217 = BGEUL
4305
  { 218,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #218 = BGEULImmMacro
4306
  { 219,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #219 = BGT
4307
  { 220,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #220 = BGTImmMacro
4308
  { 221,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #221 = BGTL
4309
  { 222,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #222 = BGTLImmMacro
4310
  { 223,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #223 = BGTU
4311
  { 224,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #224 = BGTUImmMacro
4312
  { 225,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #225 = BGTUL
4313
  { 226,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #226 = BGTULImmMacro
4314
  { 227,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #227 = BLE
4315
  { 228,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #228 = BLEImmMacro
4316
  { 229,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #229 = BLEL
4317
  { 230,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #230 = BLELImmMacro
4318
  { 231,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #231 = BLEU
4319
  { 232,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #232 = BLEUImmMacro
4320
  { 233,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #233 = BLEUL
4321
  { 234,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #234 = BLEULImmMacro
4322
  { 235,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #235 = BLT
4323
  { 236,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #236 = BLTImmMacro
4324
  { 237,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #237 = BLTL
4325
  { 238,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #238 = BLTLImmMacro
4326
  { 239,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #239 = BLTU
4327
  { 240,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #240 = BLTUImmMacro
4328
  { 241,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #241 = BLTUL
4329
  { 242,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #242 = BLTULImmMacro
4330
  { 243,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #243 = BNELImmMacro
4331
  { 244,  1,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList4, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #244 = BPOSGE32_PSEUDO
4332
  { 245,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #245 = BSEL_D_PSEUDO
4333
  { 246,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #246 = BSEL_FD_PSEUDO
4334
  { 247,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #247 = BSEL_FW_PSEUDO
4335
  { 248,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #248 = BSEL_H_PSEUDO
4336
  { 249,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #249 = BSEL_W_PSEUDO
4337
  { 250,  1,  0,  4,  2,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, ImplicitList2, OperandInfo41, -1 ,nullptr },  // Inst #250 = B_MM
4338
  { 251,  1,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #251 = B_MMR6_Pseudo
4339
  { 252,  1,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #252 = B_MM_Pseudo
4340
  { 253,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #253 = BeqImm
4341
  { 254,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #254 = BneImm
4342
  { 255,  3,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #255 = BteqzT8CmpX16
4343
  { 256,  3,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #256 = BteqzT8CmpiX16
4344
  { 257,  3,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #257 = BteqzT8SltX16
4345
  { 258,  3,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #258 = BteqzT8SltiX16
4346
  { 259,  3,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #259 = BteqzT8SltiuX16
4347
  { 260,  3,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #260 = BteqzT8SltuX16
4348
  { 261,  3,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #261 = BtnezT8CmpX16
4349
  { 262,  3,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #262 = BtnezT8CmpiX16
4350
  { 263,  3,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #263 = BtnezT8SltX16
4351
  { 264,  3,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #264 = BtnezT8SltiX16
4352
  { 265,  3,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #265 = BtnezT8SltiuX16
4353
  { 266,  3,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #266 = BtnezT8SltuX16
4354
  { 267,  3,  1,  4,  658,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #267 = BuildPairF64
4355
  { 268,  3,  1,  4,  658,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #268 = BuildPairF64_64
4356
  { 269,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #269 = CFTC1
4357
  { 270,  3,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #270 = CONSTPOOL_ENTRY
4358
  { 271,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #271 = COPY_FD_PSEUDO
4359
  { 272,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #272 = COPY_FW_PSEUDO
4360
  { 273,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #273 = CTTC1
4361
  { 274,  1,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #274 = Constant32
4362
  { 275,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #275 = DMULImmMacro
4363
  { 276,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #276 = DMULMacro
4364
  { 277,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #277 = DMULOMacro
4365
  { 278,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #278 = DMULOUMacro
4366
  { 279,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #279 = DROL
4367
  { 280,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #280 = DROLImm
4368
  { 281,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #281 = DROR
4369
  { 282,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #282 = DRORImm
4370
  { 283,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #283 = DSDivIMacro
4371
  { 284,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #284 = DSDivMacro
4372
  { 285,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #285 = DSRemIMacro
4373
  { 286,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #286 = DSRemMacro
4374
  { 287,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #287 = DUDivIMacro
4375
  { 288,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #288 = DUDivMacro
4376
  { 289,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #289 = DURemIMacro
4377
  { 290,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #290 = DURemMacro
4378
  { 291,  0,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #291 = ERet
4379
  { 292,  3,  1,  4,  667,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #292 = ExtractElementF64
4380
  { 293,  3,  1,  4,  667,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #293 = ExtractElementF64_64
4381
  { 294,  2,  1,  4,  565,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #294 = FABS_D
4382
  { 295,  2,  1,  4,  565,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #295 = FABS_W
4383
  { 296,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #296 = FEXP2_D_1_PSEUDO
4384
  { 297,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #297 = FEXP2_W_1_PSEUDO
4385
  { 298,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr },  // Inst #298 = FILL_FD_PSEUDO
4386
  { 299,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr },  // Inst #299 = FILL_FW_PSEUDO
4387
  { 300,  4,  2,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #300 = GotPrologue16
4388
  { 301,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #301 = INSERT_B_VIDX64_PSEUDO
4389
  { 302,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #302 = INSERT_B_VIDX_PSEUDO
4390
  { 303,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #303 = INSERT_D_VIDX64_PSEUDO
4391
  { 304,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #304 = INSERT_D_VIDX_PSEUDO
4392
  { 305,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #305 = INSERT_FD_PSEUDO
4393
  { 306,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #306 = INSERT_FD_VIDX64_PSEUDO
4394
  { 307,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr },  // Inst #307 = INSERT_FD_VIDX_PSEUDO
4395
  { 308,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr },  // Inst #308 = INSERT_FW_PSEUDO
4396
  { 309,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr },  // Inst #309 = INSERT_FW_VIDX64_PSEUDO
4397
  { 310,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr },  // Inst #310 = INSERT_FW_VIDX_PSEUDO
4398
  { 311,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr },  // Inst #311 = INSERT_H_VIDX64_PSEUDO
4399
  { 312,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr },  // Inst #312 = INSERT_H_VIDX_PSEUDO
4400
  { 313,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #313 = INSERT_W_VIDX64_PSEUDO
4401
  { 314,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #314 = INSERT_W_VIDX_PSEUDO
4402
  { 315,  1,  0,  4,  6,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x10ULL, nullptr, ImplicitList3, OperandInfo81, -1 ,nullptr },  // Inst #315 = JALR64Pseudo
4403
  { 316,  1,  0,  4,  6,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x10ULL, nullptr, ImplicitList3, OperandInfo81, -1 ,nullptr },  // Inst #316 = JALRHB64Pseudo
4404
  { 317,  1,  0,  4,  399,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x10ULL, nullptr, ImplicitList3, OperandInfo44, -1 ,nullptr },  // Inst #317 = JALRHBPseudo
4405
  { 318,  1,  0,  4,  399,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x10ULL, nullptr, ImplicitList3, OperandInfo44, -1 ,nullptr },  // Inst #318 = JALRPseudo
4406
  { 319,  1,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #319 = JalOneReg
4407
  { 320,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #320 = JalTwoReg
4408
  { 321,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #321 = LDMacro
4409
  { 322,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #322 = LD_F16
4410
  { 323,  3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr },  // Inst #323 = LOAD_ACC128
4411
  { 324,  3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr },  // Inst #324 = LOAD_ACC64
4412
  { 325,  3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #325 = LOAD_ACC64DSP
4413
  { 326,  3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #326 = LOAD_CCOND_DSP
4414
  { 327,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #327 = LONG_BRANCH_ADDiu
4415
  { 328,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #328 = LONG_BRANCH_DADDiu
4416
  { 329,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #329 = LONG_BRANCH_LUi
4417
  { 330,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #330 = LWM_MM
4418
  { 331,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #331 = LoadAddrImm32
4419
  { 332,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #332 = LoadAddrImm64
4420
  { 333,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #333 = LoadAddrReg32
4421
  { 334,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #334 = LoadAddrReg64
4422
  { 335,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #335 = LoadImm32
4423
  { 336,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #336 = LoadImm64
4424
  { 337,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr },  // Inst #337 = LoadImmDoubleFGR
4425
  { 338,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #338 = LoadImmDoubleFGR_32
4426
  { 339,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #339 = LoadImmDoubleGPR
4427
  { 340,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr },  // Inst #340 = LoadImmSingleFGR
4428
  { 341,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #341 = LoadImmSingleGPR
4429
  { 342,  3,  1,  2,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr },  // Inst #342 = LwConstant32
4430
  { 343,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #343 = MFTACX
4431
  { 344,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #344 = MFTC0
4432
  { 345,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #345 = MFTC1
4433
  { 346,  1,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #346 = MFTDSP
4434
  { 347,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #347 = MFTGPR
4435
  { 348,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #348 = MFTHC1
4436
  { 349,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #349 = MFTHI
4437
  { 350,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #350 = MFTLO
4438
  { 351,  2,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList5, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #351 = MIPSeh_return32
4439
  { 352,  2,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList5, nullptr, OperandInfo103, -1 ,nullptr },  // Inst #352 = MIPSeh_return64
4440
  { 353,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr },  // Inst #353 = MSA_FP_EXTEND_D_PSEUDO
4441
  { 354,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #354 = MSA_FP_EXTEND_W_PSEUDO
4442
  { 355,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #355 = MSA_FP_ROUND_D_PSEUDO
4443
  { 356,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #356 = MSA_FP_ROUND_W_PSEUDO
4444
  { 357,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #357 = MTTACX
4445
  { 358,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #358 = MTTC0
4446
  { 359,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr },  // Inst #359 = MTTC1
4447
  { 360,  1,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #360 = MTTDSP
4448
  { 361,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #361 = MTTGPR
4449
  { 362,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr },  // Inst #362 = MTTHC1
4450
  { 363,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #363 = MTTHI
4451
  { 364,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #364 = MTTLO
4452
  { 365,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #365 = MULImmMacro
4453
  { 366,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #366 = MULOMacro
4454
  { 367,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #367 = MULOUMacro
4455
  { 368,  2,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo111, -1 ,nullptr },  // Inst #368 = MultRxRy16
4456
  { 369,  3,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo112, -1 ,nullptr },  // Inst #369 = MultRxRyRz16
4457
  { 370,  2,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo111, -1 ,nullptr },  // Inst #370 = MultuRxRy16
4458
  { 371,  3,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo112, -1 ,nullptr },  // Inst #371 = MultuRxRyRz16
4459
  { 372,  0,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #372 = NOP
4460
  { 373,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #373 = NORImm
4461
  { 374,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #374 = NORImm64
4462
  { 375,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #375 = NOR_V_D_PSEUDO
4463
  { 376,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #376 = NOR_V_H_PSEUDO
4464
  { 377,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #377 = NOR_V_W_PSEUDO
4465
  { 378,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #378 = OR_V_D_PSEUDO
4466
  { 379,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #379 = OR_V_H_PSEUDO
4467
  { 380,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #380 = OR_V_W_PSEUDO
4468
  { 381,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr },  // Inst #381 = PseudoCMPU_EQ_QB
4469
  { 382,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr },  // Inst #382 = PseudoCMPU_LE_QB
4470
  { 383,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr },  // Inst #383 = PseudoCMPU_LT_QB
4471
  { 384,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr },  // Inst #384 = PseudoCMP_EQ_PH
4472
  { 385,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr },  // Inst #385 = PseudoCMP_LE_PH
4473
  { 386,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr },  // Inst #386 = PseudoCMP_LT_PH
4474
  { 387,  2,  1,  4,  617,  0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #387 = PseudoCVT_D32_W
4475
  { 388,  2,  1,  4,  617,  0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #388 = PseudoCVT_D64_L
4476
  { 389,  2,  1,  4,  617,  0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #389 = PseudoCVT_D64_W
4477
  { 390,  2,  1,  4,  617,  0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #390 = PseudoCVT_S_L
4478
  { 391,  2,  1,  4,  617,  0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr },  // Inst #391 = PseudoCVT_S_W
4479
  { 392,  3,  1,  4,  8,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr },  // Inst #392 = PseudoDMULT
4480
  { 393,  3,  1,  4,  9,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr },  // Inst #393 = PseudoDMULTu
4481
  { 394,  3,  1,  4,  10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr },  // Inst #394 = PseudoDSDIV
4482
  { 395,  3,  1,  4,  11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr },  // Inst #395 = PseudoDUDIV
4483
  { 396,  1,  0,  4,  378,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #396 = PseudoIndirectBranch
4484
  { 397,  1,  0,  4,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #397 = PseudoIndirectBranch64
4485
  { 398,  1,  0,  4,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #398 = PseudoIndirectBranch64R6
4486
  { 399,  1,  0,  4,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #399 = PseudoIndirectBranchR6
4487
  { 400,  1,  0,  4,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #400 = PseudoIndirectBranch_MM
4488
  { 401,  1,  0,  4,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #401 = PseudoIndirectBranch_MMR6
4489
  { 402,  1,  0,  4,  378,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #402 = PseudoIndirectHazardBranch
4490
  { 403,  1,  0,  4,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #403 = PseudoIndirectHazardBranch64
4491
  { 404,  1,  0,  4,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #404 = PseudoIndrectHazardBranch64R6
4492
  { 405,  1,  0,  4,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #405 = PseudoIndrectHazardBranchR6
4493
  { 406,  4,  1,  4,  470,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #406 = PseudoMADD
4494
  { 407,  4,  1,  4,  471,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #407 = PseudoMADDU
4495
  { 408,  4,  1,  4,  14, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #408 = PseudoMADDU_MM
4496
  { 409,  4,  1,  4,  13, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #409 = PseudoMADD_MM
4497
  { 410,  2,  1,  4,  459,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #410 = PseudoMFHI
4498
  { 411,  2,  1,  4,  15, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #411 = PseudoMFHI64
4499
  { 412,  2,  1,  4,  15, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #412 = PseudoMFHI_MM
4500
  { 413,  2,  1,  4,  459,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #413 = PseudoMFLO
4501
  { 414,  2,  1,  4,  15, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #414 = PseudoMFLO64
4502
  { 415,  2,  1,  4,  15, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #415 = PseudoMFLO_MM
4503
  { 416,  4,  1,  4,  472,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #416 = PseudoMSUB
4504
  { 417,  4,  1,  4,  473,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #417 = PseudoMSUBU
4505
  { 418,  4,  1,  4,  17, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #418 = PseudoMSUBU_MM
4506
  { 419,  4,  1,  4,  16, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #419 = PseudoMSUB_MM
4507
  { 420,  3,  1,  4,  474,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #420 = PseudoMTLOHI
4508
  { 421,  3,  1,  4,  18, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr },  // Inst #421 = PseudoMTLOHI64
4509
  { 422,  3,  1,  4,  18, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #422 = PseudoMTLOHI_DSP
4510
  { 423,  3,  1,  4,  18, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #423 = PseudoMTLOHI_MM
4511
  { 424,  3,  1,  4,  468,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #424 = PseudoMULT
4512
  { 425,  3,  1,  4,  19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #425 = PseudoMULT_MM
4513
  { 426,  3,  1,  4,  469,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #426 = PseudoMULTu
4514
  { 427,  3,  1,  4,  20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #427 = PseudoMULTu_MM
4515
  { 428,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #428 = PseudoPICK_PH
4516
  { 429,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #429 = PseudoPICK_QB
4517
  { 430,  1,  0,  4,  379,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #430 = PseudoReturn
4518
  { 431,  1,  0,  4,  21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #431 = PseudoReturn64
4519
  { 432,  3,  1,  4,  465,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #432 = PseudoSDIV
4520
  { 433,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr },  // Inst #433 = PseudoSELECTFP_F_D32
4521
  { 434,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #434 = PseudoSELECTFP_F_D64
4522
  { 435,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr },  // Inst #435 = PseudoSELECTFP_F_I
4523
  { 436,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr },  // Inst #436 = PseudoSELECTFP_F_I64
4524
  { 437,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr },  // Inst #437 = PseudoSELECTFP_F_S
4525
  { 438,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr },  // Inst #438 = PseudoSELECTFP_T_D32
4526
  { 439,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #439 = PseudoSELECTFP_T_D64
4527
  { 440,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr },  // Inst #440 = PseudoSELECTFP_T_I
4528
  { 441,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr },  // Inst #441 = PseudoSELECTFP_T_I64
4529
  { 442,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr },  // Inst #442 = PseudoSELECTFP_T_S
4530
  { 443,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #443 = PseudoSELECT_D32
4531
  { 444,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr },  // Inst #444 = PseudoSELECT_D64
4532
  { 445,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #445 = PseudoSELECT_I
4533
  { 446,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr },  // Inst #446 = PseudoSELECT_I64
4534
  { 447,  4,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr },  // Inst #447 = PseudoSELECT_S
4535
  { 448,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #448 = PseudoTRUNC_W_D
4536
  { 449,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #449 = PseudoTRUNC_W_D32
4537
  { 450,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #450 = PseudoTRUNC_W_S
4538
  { 451,  3,  1,  4,  466,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #451 = PseudoUDIV
4539
  { 452,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #452 = ROL
4540
  { 453,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #453 = ROLImm
4541
  { 454,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #454 = ROR
4542
  { 455,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #455 = RORImm
4543
  { 456,  0,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #456 = RetRA
4544
  { 457,  0,  0,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #457 = RetRA16
4545
  { 458,  3,  1,  4,  22, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #458 = SDIV_MM_Pseudo
4546
  { 459,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #459 = SDMacro
4547
  { 460,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #460 = SDivIMacro
4548
  { 461,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #461 = SDivMacro
4549
  { 462,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #462 = SEQIMacro
4550
  { 463,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #463 = SEQMacro
4551
  { 464,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #464 = SLTImm64
4552
  { 465,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #465 = SLTUImm64
4553
  { 466,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr },  // Inst #466 = SNZ_B_PSEUDO
4554
  { 467,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr },  // Inst #467 = SNZ_D_PSEUDO
4555
  { 468,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #468 = SNZ_H_PSEUDO
4556
  { 469,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr },  // Inst #469 = SNZ_V_PSEUDO
4557
  { 470,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr },  // Inst #470 = SNZ_W_PSEUDO
4558
  { 471,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #471 = SRemIMacro
4559
  { 472,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #472 = SRemMacro
4560
  { 473,  3,  0,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr },  // Inst #473 = STORE_ACC128
4561
  { 474,  3,  0,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr },  // Inst #474 = STORE_ACC64
4562
  { 475,  3,  0,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #475 = STORE_ACC64DSP
4563
  { 476,  3,  0,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #476 = STORE_CCOND_DSP
4564
  { 477,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #477 = ST_F16
4565
  { 478,  3,  0,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #478 = SWM_MM
4566
  { 479,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr },  // Inst #479 = SZ_B_PSEUDO
4567
  { 480,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr },  // Inst #480 = SZ_D_PSEUDO
4568
  { 481,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #481 = SZ_H_PSEUDO
4569
  { 482,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr },  // Inst #482 = SZ_V_PSEUDO
4570
  { 483,  2,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr },  // Inst #483 = SZ_W_PSEUDO
4571
  { 484,  4,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #484 = SelBeqZ
4572
  { 485,  4,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #485 = SelBneZ
4573
  { 486,  5,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #486 = SelTBteqZCmp
4574
  { 487,  5,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #487 = SelTBteqZCmpi
4575
  { 488,  5,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #488 = SelTBteqZSlt
4576
  { 489,  5,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #489 = SelTBteqZSlti
4577
  { 490,  5,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #490 = SelTBteqZSltiu
4578
  { 491,  5,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #491 = SelTBteqZSltu
4579
  { 492,  5,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #492 = SelTBtneZCmp
4580
  { 493,  5,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #493 = SelTBtneZCmpi
4581
  { 494,  5,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #494 = SelTBtneZSlt
4582
  { 495,  5,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #495 = SelTBtneZSlti
4583
  { 496,  5,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #496 = SelTBtneZSltiu
4584
  { 497,  5,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #497 = SelTBtneZSltu
4585
  { 498,  3,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr },  // Inst #498 = SltCCRxRy16
4586
  { 499,  3,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #499 = SltiCCRxImmX16
4587
  { 500,  3,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #500 = SltiuCCRxImmX16
4588
  { 501,  3,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr },  // Inst #501 = SltuCCRxRy16
4589
  { 502,  3,  1,  2,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo112, -1 ,nullptr },  // Inst #502 = SltuRxRyRz16
4590
  { 503,  1,  0,  4,  375,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr },  // Inst #503 = TAILCALL
4591
  { 504,  1,  0,  4,  25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo81, -1 ,nullptr },  // Inst #504 = TAILCALL64R6REG
4592
  { 505,  1,  0,  4,  25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo81, -1 ,nullptr },  // Inst #505 = TAILCALLHB64R6REG
4593
  { 506,  1,  0,  4,  25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #506 = TAILCALLHBR6REG
4594
  { 507,  1,  0,  4,  25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #507 = TAILCALLR6REG
4595
  { 508,  1,  0,  4,  376,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #508 = TAILCALLREG
4596
  { 509,  1,  0,  4,  25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo81, -1 ,nullptr },  // Inst #509 = TAILCALLREG64
4597
  { 510,  1,  0,  4,  376,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #510 = TAILCALLREGHB
4598
  { 511,  1,  0,  4,  25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo81, -1 ,nullptr },  // Inst #511 = TAILCALLREGHB64
4599
  { 512,  1,  0,  4,  25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #512 = TAILCALLREG_MM
4600
  { 513,  1,  0,  4,  25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr },  // Inst #513 = TAILCALLREG_MMR6
4601
  { 514,  1,  0,  4,  24, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr },  // Inst #514 = TAILCALL_MM
4602
  { 515,  1,  0,  4,  24, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr },  // Inst #515 = TAILCALL_MMR6
4603
  { 516,  0,  0,  4,  394,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #516 = TRAP
4604
  { 517,  0,  0,  4,  26, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #517 = TRAP_MM
4605
  { 518,  3,  1,  4,  23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #518 = UDIV_MM_Pseudo
4606
  { 519,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #519 = UDivIMacro
4607
  { 520,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #520 = UDivMacro
4608
  { 521,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #521 = URemIMacro
4609
  { 522,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #522 = URemMacro
4610
  { 523,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #523 = Ulh
4611
  { 524,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #524 = Ulhu
4612
  { 525,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #525 = Ulw
4613
  { 526,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #526 = Ush
4614
  { 527,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #527 = Usw
4615
  { 528,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #528 = XOR_V_D_PSEUDO
4616
  { 529,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #529 = XOR_V_H_PSEUDO
4617
  { 530,  3,  1,  4,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #530 = XOR_V_W_PSEUDO
4618
  { 531,  2,  1,  4,  703,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo146, -1 ,nullptr },  // Inst #531 = ABSQ_S_PH
4619
  { 532,  2,  1,  4,  850,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo146, -1 ,nullptr },  // Inst #532 = ABSQ_S_PH_MM
4620
  { 533,  2,  1,  4,  804,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo146, -1 ,nullptr },  // Inst #533 = ABSQ_S_QB
4621
  { 534,  2,  1,  4,  967,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo146, -1 ,nullptr },  // Inst #534 = ABSQ_S_QB_MMR2
4622
  { 535,  2,  1,  4,  704,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo31, -1 ,nullptr },  // Inst #535 = ABSQ_S_W
4623
  { 536,  2,  1,  4,  851,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo31, -1 ,nullptr },  // Inst #536 = ABSQ_S_W_MM
4624
  { 537,  3,  1,  4,  477,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #537 = ADD
4625
  { 538,  2,  1,  4,  28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #538 = ADDIUPC
4626
  { 539,  2,  1,  4,  29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #539 = ADDIUPC_MM
4627
  { 540,  2,  1,  4,  28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #540 = ADDIUPC_MMR6
4628
  { 541,  2,  1,  2,  29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #541 = ADDIUR1SP_MM
4629
  { 542,  3,  1,  2,  29, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #542 = ADDIUR2_MM
4630
  { 543,  3,  1,  2,  29, 0, 0x0ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #543 = ADDIUS5_MM
4631
  { 544,  1,  0,  2,  29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #544 = ADDIUSP_MM
4632
  { 545,  3,  1,  4,  29, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #545 = ADDIU_MMR6
4633
  { 546,  3,  1,  4,  805,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #546 = ADDQH_PH
4634
  { 547,  3,  1,  4,  968,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #547 = ADDQH_PH_MMR2
4635
  { 548,  3,  1,  4,  806,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #548 = ADDQH_R_PH
4636
  { 549,  3,  1,  4,  969,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #549 = ADDQH_R_PH_MMR2
4637
  { 550,  3,  1,  4,  807,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #550 = ADDQH_R_W
4638
  { 551,  3,  1,  4,  970,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #551 = ADDQH_R_W_MMR2
4639
  { 552,  3,  1,  4,  808,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #552 = ADDQH_W
4640
  { 553,  3,  1,  4,  971,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #553 = ADDQH_W_MMR2
4641
  { 554,  3,  1,  4,  705,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr },  // Inst #554 = ADDQ_PH
4642
  { 555,  3,  1,  4,  852,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr },  // Inst #555 = ADDQ_PH_MM
4643
  { 556,  3,  1,  4,  706,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr },  // Inst #556 = ADDQ_S_PH
4644
  { 557,  3,  1,  4,  853,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr },  // Inst #557 = ADDQ_S_PH_MM
4645
  { 558,  3,  1,  4,  707,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo58, -1 ,nullptr },  // Inst #558 = ADDQ_S_W
4646
  { 559,  3,  1,  4,  854,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo58, -1 ,nullptr },  // Inst #559 = ADDQ_S_W_MM
4647
  { 560,  3,  1,  4,  708,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList9, OperandInfo58, -1 ,nullptr },  // Inst #560 = ADDSC
4648
  { 561,  3,  1,  4,  855,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList9, OperandInfo58, -1 ,nullptr },  // Inst #561 = ADDSC_MM
4649
  { 562,  3,  1,  4,  519,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #562 = ADDS_A_B
4650
  { 563,  3,  1,  4,  519,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #563 = ADDS_A_D
4651
  { 564,  3,  1,  4,  519,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #564 = ADDS_A_H
4652
  { 565,  3,  1,  4,  519,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #565 = ADDS_A_W
4653
  { 566,  3,  1,  4,  519,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #566 = ADDS_S_B
4654
  { 567,  3,  1,  4,  519,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #567 = ADDS_S_D
4655
  { 568,  3,  1,  4,  519,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #568 = ADDS_S_H
4656
  { 569,  3,  1,  4,  519,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #569 = ADDS_S_W
4657
  { 570,  3,  1,  4,  519,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #570 = ADDS_U_B
4658
  { 571,  3,  1,  4,  519,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #571 = ADDS_U_D
4659
  { 572,  3,  1,  4,  519,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #572 = ADDS_U_H
4660
  { 573,  3,  1,  4,  519,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #573 = ADDS_U_W
4661
  { 574,  3,  1,  2,  30, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #574 = ADDU16_MM
4662
  { 575,  3,  1,  2,  30, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #575 = ADDU16_MMR6
4663
  { 576,  3,  1,  4,  809,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #576 = ADDUH_QB
4664
  { 577,  3,  1,  4,  972,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #577 = ADDUH_QB_MMR2
4665
  { 578,  3,  1,  4,  810,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #578 = ADDUH_R_QB
4666
  { 579,  3,  1,  4,  973,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #579 = ADDUH_R_QB_MMR2
4667
  { 580,  3,  1,  4,  30, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #580 = ADDU_MMR6
4668
  { 581,  3,  1,  4,  811,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr },  // Inst #581 = ADDU_PH
4669
  { 582,  3,  1,  4,  974,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr },  // Inst #582 = ADDU_PH_MMR2
4670
  { 583,  3,  1,  4,  709,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr },  // Inst #583 = ADDU_QB
4671
  { 584,  3,  1,  4,  856,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr },  // Inst #584 = ADDU_QB_MM
4672
  { 585,  3,  1,  4,  812,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr },  // Inst #585 = ADDU_S_PH
4673
  { 586,  3,  1,  4,  975,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr },  // Inst #586 = ADDU_S_PH_MMR2
4674
  { 587,  3,  1,  4,  710,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr },  // Inst #587 = ADDU_S_QB
4675
  { 588,  3,  1,  4,  857,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr },  // Inst #588 = ADDU_S_QB_MM
4676
  { 589,  3,  1,  4,  520,  0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #589 = ADDVI_B
4677
  { 590,  3,  1,  4,  520,  0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr },  // Inst #590 = ADDVI_D
4678
  { 591,  3,  1,  4,  520,  0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr },  // Inst #591 = ADDVI_H
4679
  { 592,  3,  1,  4,  520,  0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #592 = ADDVI_W
4680
  { 593,  3,  1,  4,  520,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #593 = ADDV_B
4681
  { 594,  3,  1,  4,  520,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #594 = ADDV_D
4682
  { 595,  3,  1,  4,  520,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #595 = ADDV_H
4683
  { 596,  3,  1,  4,  520,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #596 = ADDV_W
4684
  { 597,  3,  1,  4,  711,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList9, ImplicitList8, OperandInfo58, -1 ,nullptr },  // Inst #597 = ADDWC
4685
  { 598,  3,  1,  4,  858,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList9, ImplicitList8, OperandInfo58, -1 ,nullptr },  // Inst #598 = ADDWC_MM
4686
  { 599,  3,  1,  4,  518,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #599 = ADD_A_B
4687
  { 600,  3,  1,  4,  518,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #600 = ADD_A_D
4688
  { 601,  3,  1,  4,  518,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #601 = ADD_A_H
4689
  { 602,  3,  1,  4,  518,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #602 = ADD_A_W
4690
  { 603,  3,  1,  4,  27, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #603 = ADD_MM
4691
  { 604,  3,  1,  4,  27, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #604 = ADD_MMR6
4692
  { 605,  3,  1,  4,  478,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #605 = ADDi
4693
  { 606,  3,  1,  4,  31, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #606 = ADDi_MM
4694
  { 607,  3,  1,  4,  479,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #607 = ADDiu
4695
  { 608,  3,  1,  4,  29, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #608 = ADDiu_MM
4696
  { 609,  3,  1,  4,  490,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #609 = ADDu
4697
  { 610,  3,  1,  4,  30, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #610 = ADDu_MM
4698
  { 611,  4,  1,  4,  32, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr },  // Inst #611 = ALIGN
4699
  { 612,  4,  1,  4,  32, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr },  // Inst #612 = ALIGN_MMR6
4700
  { 613,  2,  1,  4,  33, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #613 = ALUIPC
4701
  { 614,  2,  1,  4,  33, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #614 = ALUIPC_MMR6
4702
  { 615,  3,  1,  4,  358,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #615 = AND
4703
  { 616,  3,  1,  2,  34, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr },  // Inst #616 = AND16_MM
4704
  { 617,  3,  1,  2,  34, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr },  // Inst #617 = AND16_MMR6
4705
  { 618,  3,  1,  4,  34, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #618 = AND64
4706
  { 619,  3,  1,  2,  34, 0, 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #619 = ANDI16_MM
4707
  { 620,  3,  1,  2,  34, 0, 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #620 = ANDI16_MMR6
4708
  { 621,  3,  1,  4,  529,  0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #621 = ANDI_B
4709
  { 622,  3,  1,  4,  35, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #622 = ANDI_MMR6
4710
  { 623,  3,  1,  4,  34, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #623 = AND_MM
4711
  { 624,  3,  1,  4,  34, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #624 = AND_MMR6
4712
  { 625,  3,  1,  4,  528,  0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #625 = AND_V
4713
  { 626,  3,  1,  4,  480,  0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #626 = ANDi
4714
  { 627,  3,  1,  4,  34, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #627 = ANDi64
4715
  { 628,  3,  1,  4,  35, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #628 = ANDi_MM
4716
  { 629,  4,  1,  4,  813,  0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr },  // Inst #629 = APPEND
4717
  { 630,  4,  1,  4,  976,  0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr },  // Inst #630 = APPEND_MMR2
4718
  { 631,  3,  1,  4,  521,  0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #631 = ASUB_S_B
4719
  { 632,  3,  1,  4,  521,  0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #632 = ASUB_S_D
4720
  { 633,  3,  1,  4,  521,  0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #633 = ASUB_S_H
4721
  { 634,  3,  1,  4,  521,  0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #634 = ASUB_S_W
4722
  { 635,  3,  1,  4,  521,  0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #635 = ASUB_U_B
4723
  { 636,  3,  1,  4,  521,  0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #636 = ASUB_U_D
4724
  { 637,  3,  1,  4,  521,  0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #637 = ASUB_U_H
4725
  { 638,  3,  1,  4,  521,  0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #638 = ASUB_U_W
4726
  { 639,  3,  1,  4,  36, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #639 = AUI
4727
  { 640,  2,  1,  4,  37, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #640 = AUIPC
4728
  { 641,  2,  1,  4,  37, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #641 = AUIPC_MMR6
4729
  { 642,  3,  1,  4,  36, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #642 = AUI_MMR6
4730
  { 643,  3,  1,  4,  522,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #643 = AVER_S_B
4731
  { 644,  3,  1,  4,  522,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #644 = AVER_S_D
4732
  { 645,  3,  1,  4,  522,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #645 = AVER_S_H
4733
  { 646,  3,  1,  4,  522,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #646 = AVER_S_W
4734
  { 647,  3,  1,  4,  522,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #647 = AVER_U_B
4735
  { 648,  3,  1,  4,  522,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #648 = AVER_U_D
4736
  { 649,  3,  1,  4,  522,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #649 = AVER_U_H
4737
  { 650,  3,  1,  4,  522,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #650 = AVER_U_W
4738
  { 651,  3,  1,  4,  522,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #651 = AVE_S_B
4739
  { 652,  3,  1,  4,  522,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #652 = AVE_S_D
4740
  { 653,  3,  1,  4,  522,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #653 = AVE_S_H
4741
  { 654,  3,  1,  4,  522,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #654 = AVE_S_W
4742
  { 655,  3,  1,  4,  522,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #655 = AVE_U_B
4743
  { 656,  3,  1,  4,  522,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #656 = AVE_U_D
4744
  { 657,  3,  1,  4,  522,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #657 = AVE_U_H
4745
  { 658,  3,  1,  4,  522,  0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #658 = AVE_U_W
4746
  { 659,  2,  1,  4,  38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr },  // Inst #659 = AddiuRxImmX16
4747
  { 660,  2,  1,  4,  38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr },  // Inst #660 = AddiuRxPcImmX16
4748
  { 661,  3,  1,  2,  38, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #661 = AddiuRxRxImm16
4749
  { 662,  3,  1,  4,  38, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #662 = AddiuRxRxImmX16
4750
  { 663,  3,  1,  4,  38, 0, 0x0ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr },  // Inst #663 = AddiuRxRyOffMemX16
4751
  { 664,  1,  0,  2,  38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo2, -1 ,nullptr },  // Inst #664 = AddiuSpImm16
4752
  { 665,  1,  0,  4,  38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo2, -1 ,nullptr },  // Inst #665 = AddiuSpImmX16
4753
  { 666,  3,  1,  2,  38, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr },  // Inst #666 = AdduRxRyRz16
4754
  { 667,  3,  1,  2,  38, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr },  // Inst #667 = AndRxRxRy16
4755
  { 668,  1,  0,  2,  2,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo41, -1 ,nullptr },  // Inst #668 = B16_MM
4756
  { 669,  3,  1,  4,  39, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #669 = BADDu
4757
  { 670,  1,  0,  4,  367,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo41, -1 ,nullptr },  // Inst #670 = BAL
4758
  { 671,  1,  0,  4,  41, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo41, -1 ,nullptr },  // Inst #671 = BALC
4759
  { 672,  1,  0,  4,  41, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo41, -1 ,nullptr },  // Inst #672 = BALC_MMR6
4760
  { 673,  4,  1,  4,  814,  0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr },  // Inst #673 = BALIGN
4761
  { 674,  4,  1,  4,  977,  0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr },  // Inst #674 = BALIGN_MMR2
4762
  { 675,  3,  0,  4,  42, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo164, -1 ,nullptr },  // Inst #675 = BBIT0
4763
  { 676,  3,  0,  4,  42, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo164, -1 ,nullptr },  // Inst #676 = BBIT032
4764
  { 677,  3,  0,  4,  42, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo164, -1 ,nullptr },  // Inst #677 = BBIT1
4765
  { 678,  3,  0,  4,  42, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo164, -1 ,nullptr },  // Inst #678 = BBIT132
4766
  { 679,  1,  0,  4,  40, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #679 = BC
4767
  { 680,  1,  0,  2,  40, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo41, -1 ,nullptr },  // Inst #680 = BC16_MMR6
4768
  { 681,  2,  0,  4,  43, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr },  // Inst #681 = BC1EQZ
4769
  { 682,  2,  0,  4,  43, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo165, -1 ,nullptr },  // Inst #682 = BC1EQZC_MMR6
4770
  { 683,  2,  0,  4,  662,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x85ULL, nullptr, ImplicitList2, OperandInfo166, -1 ,nullptr },  // Inst #683 = BC1F
4771
  { 684,  2,  0,  4,  663,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x85ULL, nullptr, ImplicitList2, OperandInfo166, -1 ,nullptr },  // Inst #684 = BC1FL
4772
  { 685,  2,  0,  4,  44, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x85ULL, nullptr, ImplicitList2, OperandInfo166, -1 ,nullptr },  // Inst #685 = BC1F_MM
4773
  { 686,  2,  0,  4,  43, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr },  // Inst #686 = BC1NEZ
4774
  { 687,  2,  0,  4,  43, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo165, -1 ,nullptr },  // Inst #687 = BC1NEZC_MMR6
4775
  { 688,  2,  0,  4,  664,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x85ULL, nullptr, ImplicitList2, OperandInfo166, -1 ,nullptr },  // Inst #688 = BC1T
4776
  { 689,  2,  0,  4,  665,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x85ULL, nullptr, ImplicitList2, OperandInfo166, -1 ,nullptr },  // Inst #689 = BC1TL
4777
  { 690,  2,  0,  4,  46, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x85ULL, nullptr, ImplicitList2, OperandInfo166, -1 ,nullptr },  // Inst #690 = BC1T_MM
4778
  { 691,  2,  0,  4,  48, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr },  // Inst #691 = BC2EQZ
4779
  { 692,  2,  0,  4,  48, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo167, -1 ,nullptr },  // Inst #692 = BC2EQZC_MMR6
4780
  { 693,  2,  0,  4,  48, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr },  // Inst #693 = BC2NEZ
4781
  { 694,  2,  0,  4,  48, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo167, -1 ,nullptr },  // Inst #694 = BC2NEZC_MMR6
4782
  { 695,  3,  1,  4,  502,  0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #695 = BCLRI_B
4783
  { 696,  3,  1,  4,  502,  0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr },  // Inst #696 = BCLRI_D
4784
  { 697,  3,  1,  4,  502,  0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr },  // Inst #697 = BCLRI_H
4785
  { 698,  3,  1,  4,  502,  0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #698 = BCLRI_W
4786
  { 699,  3,  1,  4,  502,  0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #699 = BCLR_B
4787
  { 700,  3,  1,  4,  502,  0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #700 = BCLR_D
4788
  { 701,  3,  1,  4,  502,  0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #701 = BCLR_H
4789
  { 702,  3,  1,  4,  502,  0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #702 = BCLR_W
4790
  { 703,  1,  0,  4,  40, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x16ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #703 = BC_MMR6
4791
  { 704,  3,  0,  4,  369,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #704 = BEQ
4792
  { 705,  3,  0,  4,  49, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo168, -1 ,nullptr },  // Inst #705 = BEQ64
4793
  { 706,  3,  0,  4,  50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #706 = BEQC
4794
  { 707,  3,  0,  4,  50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo168, -1 ,nullptr },  // Inst #707 = BEQC64
4795
  { 708,  3,  0,  4,  50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #708 = BEQC_MMR6
4796
  { 709,  3,  0,  4,  369,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #709 = BEQL
4797
  { 710,  2,  0,  2,  51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo169, -1 ,nullptr },  // Inst #710 = BEQZ16_MM
4798
  { 711,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr },  // Inst #711 = BEQZALC
4799
  { 712,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr },  // Inst #712 = BEQZALC_MMR6
4800
  { 713,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr },  // Inst #713 = BEQZC
4801
  { 714,  2,  0,  2,  51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo169, -1 ,nullptr },  // Inst #714 = BEQZC16_MMR6
4802
  { 715,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr },  // Inst #715 = BEQZC64
4803
  { 716,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr },  // Inst #716 = BEQZC_MM
4804
  { 717,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr },  // Inst #717 = BEQZC_MMR6
4805
  { 718,  3,  0,  4,  49, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #718 = BEQ_MM
4806
  { 719,  3,  0,  4,  50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #719 = BGEC
4807
  { 720,  3,  0,  4,  50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo168, -1 ,nullptr },  // Inst #720 = BGEC64
4808
  { 721,  3,  0,  4,  50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #721 = BGEC_MMR6
4809
  { 722,  3,  0,  4,  50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #722 = BGEUC
4810
  { 723,  3,  0,  4,  50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo168, -1 ,nullptr },  // Inst #723 = BGEUC64
4811
  { 724,  3,  0,  4,  50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #724 = BGEUC_MMR6
4812
  { 725,  2,  0,  4,  370,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr },  // Inst #725 = BGEZ
4813
  { 726,  2,  0,  4,  51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr },  // Inst #726 = BGEZ64
4814
  { 727,  2,  0,  4,  368,  0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr },  // Inst #727 = BGEZAL
4815
  { 728,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr },  // Inst #728 = BGEZALC
4816
  { 729,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr },  // Inst #729 = BGEZALC_MMR6
4817
  { 730,  2,  0,  4,  368,  0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr },  // Inst #730 = BGEZALL
4818
  { 731,  2,  0,  4,  53, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr },  // Inst #731 = BGEZALS_MM
4819
  { 732,  2,  0,  4,  3,  0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr },  // Inst #732 = BGEZAL_MM
4820
  { 733,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr },  // Inst #733 = BGEZC
4821
  { 734,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr },  // Inst #734 = BGEZC64
4822
  { 735,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr },  // Inst #735 = BGEZC_MMR6
4823
  { 736,  2,  0,  4,  370,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr },  // Inst #736 = BGEZL
4824
  { 737,  2,  0,  4,  51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr },  // Inst #737 = BGEZ_MM
4825
  { 738,  2,  0,  4,  370,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr },  // Inst #738 = BGTZ
4826
  { 739,  2,  0,  4,  51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr },  // Inst #739 = BGTZ64
4827
  { 740,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr },  // Inst #740 = BGTZALC
4828
  { 741,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr },  // Inst #741 = BGTZALC_MMR6
4829
  { 742,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr },  // Inst #742 = BGTZC
4830
  { 743,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr },  // Inst #743 = BGTZC64
4831
  { 744,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr },  // Inst #744 = BGTZC_MMR6
4832
  { 745,  2,  0,  4,  370,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr },  // Inst #745 = BGTZL
4833
  { 746,  2,  0,  4,  51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr },  // Inst #746 = BGTZ_MM
4834
  { 747,  4,  1,  4,  497,  0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #747 = BINSLI_B
4835
  { 748,  4,  1,  4,  497,  0, 0x6ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #748 = BINSLI_D
4836
  { 749,  4,  1,  4,  497,  0, 0x6ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr },  // Inst #749 = BINSLI_H
4837
  { 750,  4,  1,  4,  497,  0, 0x6ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #750 = BINSLI_W
4838
  { 751,  4,  1,  4,  497,  0, 0x6ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr },  // Inst #751 = BINSL_B
4839
  { 752,  4,  1,  4,  497,  0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #752 = BINSL_D
4840
  { 753,  4,  1,  4,  497,  0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #753 = BINSL_H
4841
  { 754,  4,  1,  4,  497,  0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #754 = BINSL_W
4842
  { 755,  4,  1,  4,  498,  0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #755 = BINSRI_B
4843
  { 756,  4,  1,  4,  498,  0, 0x6ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #756 = BINSRI_D
4844
  { 757,  4,  1,  4,  498,  0, 0x6ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr },  // Inst #757 = BINSRI_H
4845
  { 758,  4,  1,  4,  498,  0, 0x6ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #758 = BINSRI_W
4846
  { 759,  4,  1,  4,  498,  0, 0x6ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr },  // Inst #759 = BINSR_B
4847
  { 760,  4,  1,  4,  498,  0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #760 = BINSR_D
4848
  { 761,  4,  1,  4,  498,  0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #761 = BINSR_H
4849
  { 762,  4,  1,  4,  498,  0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #762 = BINSR_W
4850
  { 763,  2,  1,  4,  712,  0, 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #763 = BITREV
4851
  { 764,  2,  1,  4,  859,  0, 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #764 = BITREV_MM
4852
  { 765,  2,  1,  4,  54, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #765 = BITSWAP
4853
  { 766,  2,  1,  4,  54, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #766 = BITSWAP_MMR6
4854
  { 767,  2,  0,  4,  370,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr },  // Inst #767 = BLEZ
4855
  { 768,  2,  0,  4,  51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr },  // Inst #768 = BLEZ64
4856
  { 769,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr },  // Inst #769 = BLEZALC
4857
  { 770,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr },  // Inst #770 = BLEZALC_MMR6
4858
  { 771,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr },  // Inst #771 = BLEZC
4859
  { 772,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr },  // Inst #772 = BLEZC64
4860
  { 773,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr },  // Inst #773 = BLEZC_MMR6
4861
  { 774,  2,  0,  4,  370,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr },  // Inst #774 = BLEZL
4862
  { 775,  2,  0,  4,  51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr },  // Inst #775 = BLEZ_MM
4863
  { 776,  3,  0,  4,  50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #776 = BLTC
4864
  { 777,  3,  0,  4,  50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo168, -1 ,nullptr },  // Inst #777 = BLTC64
4865
  { 778,  3,  0,  4,  50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #778 = BLTC_MMR6
4866
  { 779,  3,  0,  4,  50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #779 = BLTUC
4867
  { 780,  3,  0,  4,  50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo168, -1 ,nullptr },  // Inst #780 = BLTUC64
4868
  { 781,  3,  0,  4,  50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr },  // Inst #781 = BLTUC_MMR6
4869
  { 782,  2,  0,  4,  370,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr },  // Inst #782 = BLTZ
4870
  { 783,  2,  0,  4,  51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr },  // Inst #783 = BLTZ64
4871
  { 784,  2,  0,  4,  368,  0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr },  // Inst #784 = BLTZAL
4872
  { 785,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr },  // Inst #785 = BLTZALC
4873
  { 786,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr },  // Inst #786 = BLTZALC_MMR6
4874
  { 787,  2,  0,  4,  368,  0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr },  // Inst #787 = BLTZALL
4875
  { 788,  2,  0,  4,  53, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr },  // Inst #788 = BLTZALS_MM
4876
  { 789,  2,  0,  4,  3,  0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr },  // Inst #789 = BLTZAL_MM
4877
  { 790,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr },  // Inst #790 = BLTZC
4878
  { 791,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr },  // Inst #791 = BLTZC64
4879
  { 792,  2,  0,  4,  52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr },  // Inst #792 = BLTZC_MMR6
4880
  { 793,  2,  0,  4,  370,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr },  // Inst #793 = BLTZL
4881
  { 794,  2,  0,  4,  51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr },  // Inst #794 = BLTZ_MM
4882
  { 795,  4,  1,  4,  505,  0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #795 = BMNZI_B
4883
  { 796,  4,  1,  4,  505,  0, 0x6ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr },  // Inst #796 = BMNZ_V
4884
  { 797,  4,  1,  4,  505,  0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #797 = BMZI_B
4885
  { 798,  4,  1,  4,  505,  0, 0x6ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr },  // Inst #798 = BMZ_V
4886
  { 799,  3,  0,  4,  369,  0|(1UL