Coverage Report

Created: 2019-02-20 00:17

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Mips/MipsGenMCCodeEmitter.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Machine Code Emitter                                                       *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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uint64_t MipsMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
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    SmallVectorImpl<MCFixup> &Fixups,
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    const MCSubtargetInfo &STI) const {
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  static const uint64_t InstBits[] = {
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428
42.9k
    UINT64_C(0),
429
42.9k
    UINT64_C(0),
430
42.9k
    UINT64_C(0),
431
42.9k
    UINT64_C(0),
432
42.9k
    UINT64_C(0),
433
42.9k
    UINT64_C(0),
434
42.9k
    UINT64_C(0),
435
42.9k
    UINT64_C(0),
436
42.9k
    UINT64_C(0),
437
42.9k
    UINT64_C(0),
438
42.9k
    UINT64_C(0),
439
42.9k
    UINT64_C(0),
440
42.9k
    UINT64_C(0),
441
42.9k
    UINT64_C(0),
442
42.9k
    UINT64_C(0),
443
42.9k
    UINT64_C(0),
444
42.9k
    UINT64_C(0),
445
42.9k
    UINT64_C(0),
446
42.9k
    UINT64_C(0),
447
42.9k
    UINT64_C(0),
448
42.9k
    UINT64_C(0),
449
42.9k
    UINT64_C(0),
450
42.9k
    UINT64_C(0),
451
42.9k
    UINT64_C(0),
452
42.9k
    UINT64_C(0),
453
42.9k
    UINT64_C(0),
454
42.9k
    UINT64_C(0),
455
42.9k
    UINT64_C(0),
456
42.9k
    UINT64_C(0),
457
42.9k
    UINT64_C(0),
458
42.9k
    UINT64_C(0),
459
42.9k
    UINT64_C(0),
460
42.9k
    UINT64_C(0),
461
42.9k
    UINT64_C(0),
462
42.9k
    UINT64_C(0),
463
42.9k
    UINT64_C(0),
464
42.9k
    UINT64_C(0),
465
42.9k
    UINT64_C(0),
466
42.9k
    UINT64_C(0),
467
42.9k
    UINT64_C(0),
468
42.9k
    UINT64_C(0),
469
42.9k
    UINT64_C(0),
470
42.9k
    UINT64_C(0),
471
42.9k
    UINT64_C(0),
472
42.9k
    UINT64_C(0),
473
42.9k
    UINT64_C(0),
474
42.9k
    UINT64_C(0),
475
42.9k
    UINT64_C(0),
476
42.9k
    UINT64_C(0),
477
42.9k
    UINT64_C(0),
478
42.9k
    UINT64_C(0),
479
42.9k
    UINT64_C(0),
480
42.9k
    UINT64_C(0),
481
42.9k
    UINT64_C(0),
482
42.9k
    UINT64_C(0),
483
42.9k
    UINT64_C(0),
484
42.9k
    UINT64_C(0),
485
42.9k
    UINT64_C(0),
486
42.9k
    UINT64_C(0),
487
42.9k
    UINT64_C(0),
488
42.9k
    UINT64_C(0),
489
42.9k
    UINT64_C(0),
490
42.9k
    UINT64_C(0),
491
42.9k
    UINT64_C(0),
492
42.9k
    UINT64_C(0),
493
42.9k
    UINT64_C(0),
494
42.9k
    UINT64_C(0),
495
42.9k
    UINT64_C(0),
496
42.9k
    UINT64_C(0),
497
42.9k
    UINT64_C(0),
498
42.9k
    UINT64_C(0),
499
42.9k
    UINT64_C(0),
500
42.9k
    UINT64_C(0),
501
42.9k
    UINT64_C(0),
502
42.9k
    UINT64_C(0),
503
42.9k
    UINT64_C(0),
504
42.9k
    UINT64_C(0),
505
42.9k
    UINT64_C(0),
506
42.9k
    UINT64_C(0),
507
42.9k
    UINT64_C(0),
508
42.9k
    UINT64_C(0),
509
42.9k
    UINT64_C(0),
510
42.9k
    UINT64_C(0),
511
42.9k
    UINT64_C(0),
512
42.9k
    UINT64_C(0),
513
42.9k
    UINT64_C(0),
514
42.9k
    UINT64_C(0),
515
42.9k
    UINT64_C(0),
516
42.9k
    UINT64_C(0),
517
42.9k
    UINT64_C(0),
518
42.9k
    UINT64_C(0),
519
42.9k
    UINT64_C(0),
520
42.9k
    UINT64_C(0),
521
42.9k
    UINT64_C(0),
522
42.9k
    UINT64_C(0),
523
42.9k
    UINT64_C(0),
524
42.9k
    UINT64_C(0),
525
42.9k
    UINT64_C(0),
526
42.9k
    UINT64_C(0),
527
42.9k
    UINT64_C(0),
528
42.9k
    UINT64_C(0),
529
42.9k
    UINT64_C(0),
530
42.9k
    UINT64_C(0),
531
42.9k
    UINT64_C(0),
532
42.9k
    UINT64_C(0),
533
42.9k
    UINT64_C(0),
534
42.9k
    UINT64_C(0),
535
42.9k
    UINT64_C(0),
536
42.9k
    UINT64_C(0),
537
42.9k
    UINT64_C(0),
538
42.9k
    UINT64_C(0),
539
42.9k
    UINT64_C(0),
540
42.9k
    UINT64_C(0),
541
42.9k
    UINT64_C(0),
542
42.9k
    UINT64_C(0),
543
42.9k
    UINT64_C(0),
544
42.9k
    UINT64_C(0),
545
42.9k
    UINT64_C(0),
546
42.9k
    UINT64_C(0),
547
42.9k
    UINT64_C(0),
548
42.9k
    UINT64_C(0),
549
42.9k
    UINT64_C(0),
550
42.9k
    UINT64_C(0),
551
42.9k
    UINT64_C(0),
552
42.9k
    UINT64_C(0),
553
42.9k
    UINT64_C(0),
554
42.9k
    UINT64_C(0),
555
42.9k
    UINT64_C(0),
556
42.9k
    UINT64_C(0),
557
42.9k
    UINT64_C(0),
558
42.9k
    UINT64_C(0),
559
42.9k
    UINT64_C(0),
560
42.9k
    UINT64_C(0),
561
42.9k
    UINT64_C(2080375378), // ABSQ_S_PH
562
42.9k
    UINT64_C(4412), // ABSQ_S_PH_MM
563
42.9k
    UINT64_C(2080374866), // ABSQ_S_QB
564
42.9k
    UINT64_C(316),  // ABSQ_S_QB_MMR2
565
42.9k
    UINT64_C(2080375890), // ABSQ_S_W
566
42.9k
    UINT64_C(8508), // ABSQ_S_W_MM
567
42.9k
    UINT64_C(32), // ADD
568
42.9k
    UINT64_C(3959422976), // ADDIUPC
569
42.9k
    UINT64_C(2013265920), // ADDIUPC_MM
570
42.9k
    UINT64_C(2013265920), // ADDIUPC_MMR6
571
42.9k
    UINT64_C(27649),  // ADDIUR1SP_MM
572
42.9k
    UINT64_C(27648),  // ADDIUR2_MM
573
42.9k
    UINT64_C(19456),  // ADDIUS5_MM
574
42.9k
    UINT64_C(19457),  // ADDIUSP_MM
575
42.9k
    UINT64_C(805306368),  // ADDIU_MMR6
576
42.9k
    UINT64_C(2080375320), // ADDQH_PH
577
42.9k
    UINT64_C(77), // ADDQH_PH_MMR2
578
42.9k
    UINT64_C(2080375448), // ADDQH_R_PH
579
42.9k
    UINT64_C(1101), // ADDQH_R_PH_MMR2
580
42.9k
    UINT64_C(2080375960), // ADDQH_R_W
581
42.9k
    UINT64_C(1165), // ADDQH_R_W_MMR2
582
42.9k
    UINT64_C(2080375832), // ADDQH_W
583
42.9k
    UINT64_C(141),  // ADDQH_W_MMR2
584
42.9k
    UINT64_C(2080375440), // ADDQ_PH
585
42.9k
    UINT64_C(13), // ADDQ_PH_MM
586
42.9k
    UINT64_C(2080375696), // ADDQ_S_PH
587
42.9k
    UINT64_C(1037), // ADDQ_S_PH_MM
588
42.9k
    UINT64_C(2080376208), // ADDQ_S_W
589
42.9k
    UINT64_C(773),  // ADDQ_S_W_MM
590
42.9k
    UINT64_C(2080375824), // ADDSC
591
42.9k
    UINT64_C(901),  // ADDSC_MM
592
42.9k
    UINT64_C(2021654544), // ADDS_A_B
593
42.9k
    UINT64_C(2027946000), // ADDS_A_D
594
42.9k
    UINT64_C(2023751696), // ADDS_A_H
595
42.9k
    UINT64_C(2025848848), // ADDS_A_W
596
42.9k
    UINT64_C(2030043152), // ADDS_S_B
597
42.9k
    UINT64_C(2036334608), // ADDS_S_D
598
42.9k
    UINT64_C(2032140304), // ADDS_S_H
599
42.9k
    UINT64_C(2034237456), // ADDS_S_W
600
42.9k
    UINT64_C(2038431760), // ADDS_U_B
601
42.9k
    UINT64_C(2044723216), // ADDS_U_D
602
42.9k
    UINT64_C(2040528912), // ADDS_U_H
603
42.9k
    UINT64_C(2042626064), // ADDS_U_W
604
42.9k
    UINT64_C(1024), // ADDU16_MM
605
42.9k
    UINT64_C(1024), // ADDU16_MMR6
606
42.9k
    UINT64_C(2080374808), // ADDUH_QB
607
42.9k
    UINT64_C(333),  // ADDUH_QB_MMR2
608
42.9k
    UINT64_C(2080374936), // ADDUH_R_QB
609
42.9k
    UINT64_C(1357), // ADDUH_R_QB_MMR2
610
42.9k
    UINT64_C(336),  // ADDU_MMR6
611
42.9k
    UINT64_C(2080375312), // ADDU_PH
612
42.9k
    UINT64_C(269),  // ADDU_PH_MMR2
613
42.9k
    UINT64_C(2080374800), // ADDU_QB
614
42.9k
    UINT64_C(205),  // ADDU_QB_MM
615
42.9k
    UINT64_C(2080375568), // ADDU_S_PH
616
42.9k
    UINT64_C(1293), // ADDU_S_PH_MMR2
617
42.9k
    UINT64_C(2080375056), // ADDU_S_QB
618
42.9k
    UINT64_C(1229), // ADDU_S_QB_MM
619
42.9k
    UINT64_C(2013265926), // ADDVI_B
620
42.9k
    UINT64_C(2019557382), // ADDVI_D
621
42.9k
    UINT64_C(2015363078), // ADDVI_H
622
42.9k
    UINT64_C(2017460230), // ADDVI_W
623
42.9k
    UINT64_C(2013265934), // ADDV_B
624
42.9k
    UINT64_C(2019557390), // ADDV_D
625
42.9k
    UINT64_C(2015363086), // ADDV_H
626
42.9k
    UINT64_C(2017460238), // ADDV_W
627
42.9k
    UINT64_C(2080375888), // ADDWC
628
42.9k
    UINT64_C(965),  // ADDWC_MM
629
42.9k
    UINT64_C(2013265936), // ADD_A_B
630
42.9k
    UINT64_C(2019557392), // ADD_A_D
631
42.9k
    UINT64_C(2015363088), // ADD_A_H
632
42.9k
    UINT64_C(2017460240), // ADD_A_W
633
42.9k
    UINT64_C(272),  // ADD_MM
634
42.9k
    UINT64_C(272),  // ADD_MMR6
635
42.9k
    UINT64_C(536870912),  // ADDi
636
42.9k
    UINT64_C(268435456),  // ADDi_MM
637
42.9k
    UINT64_C(603979776),  // ADDiu
638
42.9k
    UINT64_C(805306368),  // ADDiu_MM
639
42.9k
    UINT64_C(33), // ADDu
640
42.9k
    UINT64_C(336),  // ADDu_MM
641
42.9k
    UINT64_C(2080375328), // ALIGN
642
42.9k
    UINT64_C(31), // ALIGN_MMR6
643
42.9k
    UINT64_C(3961454592), // ALUIPC
644
42.9k
    UINT64_C(2015297536), // ALUIPC_MMR6
645
42.9k
    UINT64_C(36), // AND
646
42.9k
    UINT64_C(17536),  // AND16_MM
647
42.9k
    UINT64_C(17409),  // AND16_MMR6
648
42.9k
    UINT64_C(36), // AND64
649
42.9k
    UINT64_C(11264),  // ANDI16_MM
650
42.9k
    UINT64_C(11264),  // ANDI16_MMR6
651
42.9k
    UINT64_C(2013265920), // ANDI_B
652
42.9k
    UINT64_C(3489660928), // ANDI_MMR6
653
42.9k
    UINT64_C(592),  // AND_MM
654
42.9k
    UINT64_C(592),  // AND_MMR6
655
42.9k
    UINT64_C(2013265950), // AND_V
656
42.9k
    UINT64_C(805306368),  // ANDi
657
42.9k
    UINT64_C(805306368),  // ANDi64
658
42.9k
    UINT64_C(3489660928), // ANDi_MM
659
42.9k
    UINT64_C(2080374833), // APPEND
660
42.9k
    UINT64_C(533),  // APPEND_MMR2
661
42.9k
    UINT64_C(2046820369), // ASUB_S_B
662
42.9k
    UINT64_C(2053111825), // ASUB_S_D
663
42.9k
    UINT64_C(2048917521), // ASUB_S_H
664
42.9k
    UINT64_C(2051014673), // ASUB_S_W
665
42.9k
    UINT64_C(2055208977), // ASUB_U_B
666
42.9k
    UINT64_C(2061500433), // ASUB_U_D
667
42.9k
    UINT64_C(2057306129), // ASUB_U_H
668
42.9k
    UINT64_C(2059403281), // ASUB_U_W
669
42.9k
    UINT64_C(1006632960), // AUI
670
42.9k
    UINT64_C(3961389056), // AUIPC
671
42.9k
    UINT64_C(2015232000), // AUIPC_MMR6
672
42.9k
    UINT64_C(268435456),  // AUI_MMR6
673
42.9k
    UINT64_C(2063597584), // AVER_S_B
674
42.9k
    UINT64_C(2069889040), // AVER_S_D
675
42.9k
    UINT64_C(2065694736), // AVER_S_H
676
42.9k
    UINT64_C(2067791888), // AVER_S_W
677
42.9k
    UINT64_C(2071986192), // AVER_U_B
678
42.9k
    UINT64_C(2078277648), // AVER_U_D
679
42.9k
    UINT64_C(2074083344), // AVER_U_H
680
42.9k
    UINT64_C(2076180496), // AVER_U_W
681
42.9k
    UINT64_C(2046820368), // AVE_S_B
682
42.9k
    UINT64_C(2053111824), // AVE_S_D
683
42.9k
    UINT64_C(2048917520), // AVE_S_H
684
42.9k
    UINT64_C(2051014672), // AVE_S_W
685
42.9k
    UINT64_C(2055208976), // AVE_U_B
686
42.9k
    UINT64_C(2061500432), // AVE_U_D
687
42.9k
    UINT64_C(2057306128), // AVE_U_H
688
42.9k
    UINT64_C(2059403280), // AVE_U_W
689
42.9k
    UINT64_C(4026550272), // AddiuRxImmX16
690
42.9k
    UINT64_C(4026533888), // AddiuRxPcImmX16
691
42.9k
    UINT64_C(18432),  // AddiuRxRxImm16
692
42.9k
    UINT64_C(4026550272), // AddiuRxRxImmX16
693
42.9k
    UINT64_C(4026548224), // AddiuRxRyOffMemX16
694
42.9k
    UINT64_C(25344),  // AddiuSpImm16
695
42.9k
    UINT64_C(4026544896), // AddiuSpImmX16
696
42.9k
    UINT64_C(57345),  // AdduRxRyRz16
697
42.9k
    UINT64_C(59404),  // AndRxRxRy16
698
42.9k
    UINT64_C(52224),  // B16_MM
699
42.9k
    UINT64_C(1879048232), // BADDu
700
42.9k
    UINT64_C(68222976), // BAL
701
42.9k
    UINT64_C(3892314112), // BALC
702
42.9k
    UINT64_C(3019898880), // BALC_MMR6
703
42.9k
    UINT64_C(2080375857), // BALIGN
704
42.9k
    UINT64_C(2236), // BALIGN_MMR2
705
42.9k
    UINT64_C(3355443200), // BBIT0
706
42.9k
    UINT64_C(3623878656), // BBIT032
707
42.9k
    UINT64_C(3892314112), // BBIT1
708
42.9k
    UINT64_C(4160749568), // BBIT132
709
42.9k
    UINT64_C(3355443200), // BC
710
42.9k
    UINT64_C(52224),  // BC16_MMR6
711
42.9k
    UINT64_C(1159725056), // BC1EQZ
712
42.9k
    UINT64_C(1090519040), // BC1EQZC_MMR6
713
42.9k
    UINT64_C(1157627904), // BC1F
714
42.9k
    UINT64_C(1157758976), // BC1FL
715
42.9k
    UINT64_C(1132462080), // BC1F_MM
716
42.9k
    UINT64_C(1168113664), // BC1NEZ
717
42.9k
    UINT64_C(1092616192), // BC1NEZC_MMR6
718
42.9k
    UINT64_C(1157693440), // BC1T
719
42.9k
    UINT64_C(1157824512), // BC1TL
720
42.9k
    UINT64_C(1134559232), // BC1T_MM
721
42.9k
    UINT64_C(1226833920), // BC2EQZ
722
42.9k
    UINT64_C(1094713344), // BC2EQZC_MMR6
723
42.9k
    UINT64_C(1235222528), // BC2NEZ
724
42.9k
    UINT64_C(1096810496), // BC2NEZC_MMR6
725
42.9k
    UINT64_C(2045771785), // BCLRI_B
726
42.9k
    UINT64_C(2038431753), // BCLRI_D
727
42.9k
    UINT64_C(2044723209), // BCLRI_H
728
42.9k
    UINT64_C(2042626057), // BCLRI_W
729
42.9k
    UINT64_C(2038431757), // BCLR_B
730
42.9k
    UINT64_C(2044723213), // BCLR_D
731
42.9k
    UINT64_C(2040528909), // BCLR_H
732
42.9k
    UINT64_C(2042626061), // BCLR_W
733
42.9k
    UINT64_C(2483027968), // BC_MMR6
734
42.9k
    UINT64_C(268435456),  // BEQ
735
42.9k
    UINT64_C(268435456),  // BEQ64
736
42.9k
    UINT64_C(536870912),  // BEQC
737
42.9k
    UINT64_C(536870912),  // BEQC64
738
42.9k
    UINT64_C(1946157056), // BEQC_MMR6
739
42.9k
    UINT64_C(1342177280), // BEQL
740
42.9k
    UINT64_C(35840),  // BEQZ16_MM
741
42.9k
    UINT64_C(536870912),  // BEQZALC
742
42.9k
    UINT64_C(1946157056), // BEQZALC_MMR6
743
42.9k
    UINT64_C(3623878656), // BEQZC
744
42.9k
    UINT64_C(35840),  // BEQZC16_MMR6
745
42.9k
    UINT64_C(3623878656), // BEQZC64
746
42.9k
    UINT64_C(1088421888), // BEQZC_MM
747
42.9k
    UINT64_C(2147483648), // BEQZC_MMR6
748
42.9k
    UINT64_C(2483027968), // BEQ_MM
749
42.9k
    UINT64_C(1476395008), // BGEC
750
42.9k
    UINT64_C(1476395008), // BGEC64
751
42.9k
    UINT64_C(4093640704), // BGEC_MMR6
752
42.9k
    UINT64_C(402653184),  // BGEUC
753
42.9k
    UINT64_C(402653184),  // BGEUC64
754
42.9k
    UINT64_C(3221225472), // BGEUC_MMR6
755
42.9k
    UINT64_C(67174400), // BGEZ
756
42.9k
    UINT64_C(67174400), // BGEZ64
757
42.9k
    UINT64_C(68222976), // BGEZAL
758
42.9k
    UINT64_C(402653184),  // BGEZALC
759
42.9k
    UINT64_C(3221225472), // BGEZALC_MMR6
760
42.9k
    UINT64_C(68354048), // BGEZALL
761
42.9k
    UINT64_C(1113587712), // BGEZALS_MM
762
42.9k
    UINT64_C(1080033280), // BGEZAL_MM
763
42.9k
    UINT64_C(1476395008), // BGEZC
764
42.9k
    UINT64_C(1476395008), // BGEZC64
765
42.9k
    UINT64_C(4093640704), // BGEZC_MMR6
766
42.9k
    UINT64_C(67305472), // BGEZL
767
42.9k
    UINT64_C(1077936128), // BGEZ_MM
768
42.9k
    UINT64_C(469762048),  // BGTZ
769
42.9k
    UINT64_C(469762048),  // BGTZ64
770
42.9k
    UINT64_C(469762048),  // BGTZALC
771
42.9k
    UINT64_C(3758096384), // BGTZALC_MMR6
772
42.9k
    UINT64_C(1543503872), // BGTZC
773
42.9k
    UINT64_C(1543503872), // BGTZC64
774
42.9k
    UINT64_C(3556769792), // BGTZC_MMR6
775
42.9k
    UINT64_C(1543503872), // BGTZL
776
42.9k
    UINT64_C(1086324736), // BGTZ_MM
777
42.9k
    UINT64_C(2070937609), // BINSLI_B
778
42.9k
    UINT64_C(2063597577), // BINSLI_D
779
42.9k
    UINT64_C(2069889033), // BINSLI_H
780
42.9k
    UINT64_C(2067791881), // BINSLI_W
781
42.9k
    UINT64_C(2063597581), // BINSL_B
782
42.9k
    UINT64_C(2069889037), // BINSL_D
783
42.9k
    UINT64_C(2065694733), // BINSL_H
784
42.9k
    UINT64_C(2067791885), // BINSL_W
785
42.9k
    UINT64_C(2079326217), // BINSRI_B
786
42.9k
    UINT64_C(2071986185), // BINSRI_D
787
42.9k
    UINT64_C(2078277641), // BINSRI_H
788
42.9k
    UINT64_C(2076180489), // BINSRI_W
789
42.9k
    UINT64_C(2071986189), // BINSR_B
790
42.9k
    UINT64_C(2078277645), // BINSR_D
791
42.9k
    UINT64_C(2074083341), // BINSR_H
792
42.9k
    UINT64_C(2076180493), // BINSR_W
793
42.9k
    UINT64_C(2080376530), // BITREV
794
42.9k
    UINT64_C(12604),  // BITREV_MM
795
42.9k
    UINT64_C(2080374816), // BITSWAP
796
42.9k
    UINT64_C(2876), // BITSWAP_MMR6
797
42.9k
    UINT64_C(402653184),  // BLEZ
798
42.9k
    UINT64_C(402653184),  // BLEZ64
799
42.9k
    UINT64_C(402653184),  // BLEZALC
800
42.9k
    UINT64_C(3221225472), // BLEZALC_MMR6
801
42.9k
    UINT64_C(1476395008), // BLEZC
802
42.9k
    UINT64_C(1476395008), // BLEZC64
803
42.9k
    UINT64_C(4093640704), // BLEZC_MMR6
804
42.9k
    UINT64_C(1476395008), // BLEZL
805
42.9k
    UINT64_C(1082130432), // BLEZ_MM
806
42.9k
    UINT64_C(1543503872), // BLTC
807
42.9k
    UINT64_C(1543503872), // BLTC64
808
42.9k
    UINT64_C(3556769792), // BLTC_MMR6
809
42.9k
    UINT64_C(469762048),  // BLTUC
810
42.9k
    UINT64_C(469762048),  // BLTUC64
811
42.9k
    UINT64_C(3758096384), // BLTUC_MMR6
812
42.9k
    UINT64_C(67108864), // BLTZ
813
42.9k
    UINT64_C(67108864), // BLTZ64
814
42.9k
    UINT64_C(68157440), // BLTZAL
815
42.9k
    UINT64_C(469762048),  // BLTZALC
816
42.9k
    UINT64_C(3758096384), // BLTZALC_MMR6
817
42.9k
    UINT64_C(68288512), // BLTZALL
818
42.9k
    UINT64_C(1109393408), // BLTZALS_MM
819
42.9k
    UINT64_C(1075838976), // BLTZAL_MM
820
42.9k
    UINT64_C(1543503872), // BLTZC
821
42.9k
    UINT64_C(1543503872), // BLTZC64
822
42.9k
    UINT64_C(3556769792), // BLTZC_MMR6
823
42.9k
    UINT64_C(67239936), // BLTZL
824
42.9k
    UINT64_C(1073741824), // BLTZ_MM
825
42.9k
    UINT64_C(2013265921), // BMNZI_B
826
42.9k
    UINT64_C(2021654558), // BMNZ_V
827
42.9k
    UINT64_C(2030043137), // BMZI_B
828
42.9k
    UINT64_C(2023751710), // BMZ_V
829
42.9k
    UINT64_C(335544320),  // BNE
830
42.9k
    UINT64_C(335544320),  // BNE64
831
42.9k
    UINT64_C(1610612736), // BNEC
832
42.9k
    UINT64_C(1610612736), // BNEC64
833
42.9k
    UINT64_C(2080374784), // BNEC_MMR6
834
42.9k
    UINT64_C(2062549001), // BNEGI_B
835
42.9k
    UINT64_C(2055208969), // BNEGI_D
836
42.9k
    UINT64_C(2061500425), // BNEGI_H
837
42.9k
    UINT64_C(2059403273), // BNEGI_W
838
42.9k
    UINT64_C(2055208973), // BNEG_B
839
42.9k
    UINT64_C(2061500429), // BNEG_D
840
42.9k
    UINT64_C(2057306125), // BNEG_H
841
42.9k
    UINT64_C(2059403277), // BNEG_W
842
42.9k
    UINT64_C(1409286144), // BNEL
843
42.9k
    UINT64_C(44032),  // BNEZ16_MM
844
42.9k
    UINT64_C(1610612736), // BNEZALC
845
42.9k
    UINT64_C(2080374784), // BNEZALC_MMR6
846
42.9k
    UINT64_C(4160749568), // BNEZC
847
42.9k
    UINT64_C(44032),  // BNEZC16_MMR6
848
42.9k
    UINT64_C(4160749568), // BNEZC64
849
42.9k
    UINT64_C(1084227584), // BNEZC_MM
850
42.9k
    UINT64_C(2684354560), // BNEZC_MMR6
851
42.9k
    UINT64_C(3019898880), // BNE_MM
852
42.9k
    UINT64_C(1610612736), // BNVC
853
42.9k
    UINT64_C(2080374784), // BNVC_MMR6
854
42.9k
    UINT64_C(1199570944), // BNZ_B
855
42.9k
    UINT64_C(1205862400), // BNZ_D
856
42.9k
    UINT64_C(1201668096), // BNZ_H
857
42.9k
    UINT64_C(1172307968), // BNZ_V
858
42.9k
    UINT64_C(1203765248), // BNZ_W
859
42.9k
    UINT64_C(536870912),  // BOVC
860
42.9k
    UINT64_C(1946157056), // BOVC_MMR6
861
42.9k
    UINT64_C(68943872), // BPOSGE32
862
42.9k
    UINT64_C(1126170624), // BPOSGE32C_MMR3
863
42.9k
    UINT64_C(1130364928), // BPOSGE32_MM
864
42.9k
    UINT64_C(13), // BREAK
865
42.9k
    UINT64_C(18048),  // BREAK16_MM
866
42.9k
    UINT64_C(17435),  // BREAK16_MMR6
867
42.9k
    UINT64_C(7),  // BREAK_MM
868
42.9k
    UINT64_C(7),  // BREAK_MMR6
869
42.9k
    UINT64_C(2046820353), // BSELI_B
870
42.9k
    UINT64_C(2025848862), // BSEL_V
871
42.9k
    UINT64_C(2054160393), // BSETI_B
872
42.9k
    UINT64_C(2046820361), // BSETI_D
873
42.9k
    UINT64_C(2053111817), // BSETI_H
874
42.9k
    UINT64_C(2051014665), // BSETI_W
875
42.9k
    UINT64_C(2046820365), // BSET_B
876
42.9k
    UINT64_C(2053111821), // BSET_D
877
42.9k
    UINT64_C(2048917517), // BSET_H
878
42.9k
    UINT64_C(2051014669), // BSET_W
879
42.9k
    UINT64_C(1191182336), // BZ_B
880
42.9k
    UINT64_C(1197473792), // BZ_D
881
42.9k
    UINT64_C(1193279488), // BZ_H
882
42.9k
    UINT64_C(1163919360), // BZ_V
883
42.9k
    UINT64_C(1195376640), // BZ_W
884
42.9k
    UINT64_C(8192), // BeqzRxImm16
885
42.9k
    UINT64_C(4026540032), // BeqzRxImmX16
886
42.9k
    UINT64_C(4096), // Bimm16
887
42.9k
    UINT64_C(4026535936), // BimmX16
888
42.9k
    UINT64_C(10240),  // BnezRxImm16
889
42.9k
    UINT64_C(4026542080), // BnezRxImmX16
890
42.9k
    UINT64_C(59397),  // Break16
891
42.9k
    UINT64_C(24576),  // Bteqz16
892
42.9k
    UINT64_C(4026544128), // BteqzX16
893
42.9k
    UINT64_C(24832),  // Btnez16
894
42.9k
    UINT64_C(4026544384), // BtnezX16
895
42.9k
    UINT64_C(3154116608), // CACHE
896
42.9k
    UINT64_C(2080374811), // CACHEE
897
42.9k
    UINT64_C(1610655232), // CACHEE_MM
898
42.9k
    UINT64_C(536895488),  // CACHE_MM
899
42.9k
    UINT64_C(536895488),  // CACHE_MMR6
900
42.9k
    UINT64_C(2080374821), // CACHE_R6
901
42.9k
    UINT64_C(1176502282), // CEIL_L_D64
902
42.9k
    UINT64_C(1409307451), // CEIL_L_D_MMR6
903
42.9k
    UINT64_C(1174405130), // CEIL_L_S
904
42.9k
    UINT64_C(1409291067), // CEIL_L_S_MMR6
905
42.9k
    UINT64_C(1176502286), // CEIL_W_D32
906
42.9k
    UINT64_C(1176502286), // CEIL_W_D64
907
42.9k
    UINT64_C(1409309499), // CEIL_W_D_MMR6
908
42.9k
    UINT64_C(1409309499), // CEIL_W_MM
909
42.9k
    UINT64_C(1174405134), // CEIL_W_S
910
42.9k
    UINT64_C(1409293115), // CEIL_W_S_MM
911
42.9k
    UINT64_C(1409293115), // CEIL_W_S_MMR6
912
42.9k
    UINT64_C(2013265927), // CEQI_B
913
42.9k
    UINT64_C(2019557383), // CEQI_D
914
42.9k
    UINT64_C(2015363079), // CEQI_H
915
42.9k
    UINT64_C(2017460231), // CEQI_W
916
42.9k
    UINT64_C(2013265935), // CEQ_B
917
42.9k
    UINT64_C(2019557391), // CEQ_D
918
42.9k
    UINT64_C(2015363087), // CEQ_H
919
42.9k
    UINT64_C(2017460239), // CEQ_W
920
42.9k
    UINT64_C(1145044992), // CFC1
921
42.9k
    UINT64_C(1409290299), // CFC1_MM
922
42.9k
    UINT64_C(52540),  // CFC2_MM
923
42.9k
    UINT64_C(2021523481), // CFCMSA
924
42.9k
    UINT64_C(1879048242), // CINS
925
42.9k
    UINT64_C(1879048243), // CINS32
926
42.9k
    UINT64_C(1879048242), // CINS64_32
927
42.9k
    UINT64_C(1879048242), // CINS_i32
928
42.9k
    UINT64_C(1176502299), // CLASS_D
929
42.9k
    UINT64_C(1409286752), // CLASS_D_MMR6
930
42.9k
    UINT64_C(1174405147), // CLASS_S
931
42.9k
    UINT64_C(1409286240), // CLASS_S_MMR6
932
42.9k
    UINT64_C(2046820359), // CLEI_S_B
933
42.9k
    UINT64_C(2053111815), // CLEI_S_D
934
42.9k
    UINT64_C(2048917511), // CLEI_S_H
935
42.9k
    UINT64_C(2051014663), // CLEI_S_W
936
42.9k
    UINT64_C(2055208967), // CLEI_U_B
937
42.9k
    UINT64_C(2061500423), // CLEI_U_D
938
42.9k
    UINT64_C(2057306119), // CLEI_U_H
939
42.9k
    UINT64_C(2059403271), // CLEI_U_W
940
42.9k
    UINT64_C(2046820367), // CLE_S_B
941
42.9k
    UINT64_C(2053111823), // CLE_S_D
942
42.9k
    UINT64_C(2048917519), // CLE_S_H
943
42.9k
    UINT64_C(2051014671), // CLE_S_W
944
42.9k
    UINT64_C(2055208975), // CLE_U_B
945
42.9k
    UINT64_C(2061500431), // CLE_U_D
946
42.9k
    UINT64_C(2057306127), // CLE_U_H
947
42.9k
    UINT64_C(2059403279), // CLE_U_W
948
42.9k
    UINT64_C(1879048225), // CLO
949
42.9k
    UINT64_C(19260),  // CLO_MM
950
42.9k
    UINT64_C(19260),  // CLO_MMR6
951
42.9k
    UINT64_C(81), // CLO_R6
952
42.9k
    UINT64_C(2030043143), // CLTI_S_B
953
42.9k
    UINT64_C(2036334599), // CLTI_S_D
954
42.9k
    UINT64_C(2032140295), // CLTI_S_H
955
42.9k
    UINT64_C(2034237447), // CLTI_S_W
956
42.9k
    UINT64_C(2038431751), // CLTI_U_B
957
42.9k
    UINT64_C(2044723207), // CLTI_U_D
958
42.9k
    UINT64_C(2040528903), // CLTI_U_H
959
42.9k
    UINT64_C(2042626055), // CLTI_U_W
960
42.9k
    UINT64_C(2030043151), // CLT_S_B
961
42.9k
    UINT64_C(2036334607), // CLT_S_D
962
42.9k
    UINT64_C(2032140303), // CLT_S_H
963
42.9k
    UINT64_C(2034237455), // CLT_S_W
964
42.9k
    UINT64_C(2038431759), // CLT_U_B
965
42.9k
    UINT64_C(2044723215), // CLT_U_D
966
42.9k
    UINT64_C(2040528911), // CLT_U_H
967
42.9k
    UINT64_C(2042626063), // CLT_U_W
968
42.9k
    UINT64_C(1879048224), // CLZ
969
42.9k
    UINT64_C(23356),  // CLZ_MM
970
42.9k
    UINT64_C(80), // CLZ_MMR6
971
42.9k
    UINT64_C(80), // CLZ_R6
972
42.9k
    UINT64_C(2080376337), // CMPGDU_EQ_QB
973
42.9k
    UINT64_C(389),  // CMPGDU_EQ_QB_MMR2
974
42.9k
    UINT64_C(2080376465), // CMPGDU_LE_QB
975
42.9k
    UINT64_C(517),  // CMPGDU_LE_QB_MMR2
976
42.9k
    UINT64_C(2080376401), // CMPGDU_LT_QB
977
42.9k
    UINT64_C(453),  // CMPGDU_LT_QB_MMR2
978
42.9k
    UINT64_C(2080375057), // CMPGU_EQ_QB
979
42.9k
    UINT64_C(1476395205), // CMPGU_EQ_QB_MM
980
42.9k
    UINT64_C(2080375185), // CMPGU_LE_QB
981
42.9k
    UINT64_C(1476395333), // CMPGU_LE_QB_MM
982
42.9k
    UINT64_C(2080375121), // CMPGU_LT_QB
983
42.9k
    UINT64_C(1476395269), // CMPGU_LT_QB_MM
984
42.9k
    UINT64_C(2080374801), // CMPU_EQ_QB
985
42.9k
    UINT64_C(581),  // CMPU_EQ_QB_MM
986
42.9k
    UINT64_C(2080374929), // CMPU_LE_QB
987
42.9k
    UINT64_C(709),  // CMPU_LE_QB_MM
988
42.9k
    UINT64_C(2080374865), // CMPU_LT_QB
989
42.9k
    UINT64_C(645),  // CMPU_LT_QB_MM
990
42.9k
    UINT64_C(1409286165), // CMP_AF_D_MMR6
991
42.9k
    UINT64_C(1409286149), // CMP_AF_S_MMR6
992
42.9k
    UINT64_C(1184890882), // CMP_EQ_D
993
42.9k
    UINT64_C(1409286293), // CMP_EQ_D_MMR6
994
42.9k
    UINT64_C(2080375313), // CMP_EQ_PH
995
42.9k
    UINT64_C(5),  // CMP_EQ_PH_MM
996
42.9k
    UINT64_C(1182793730), // CMP_EQ_S
997
42.9k
    UINT64_C(1409286277), // CMP_EQ_S_MMR6
998
42.9k
    UINT64_C(1184890880), // CMP_F_D
999
42.9k
    UINT64_C(1182793728), // CMP_F_S
1000
42.9k
    UINT64_C(1184890886), // CMP_LE_D
1001
42.9k
    UINT64_C(1409286549), // CMP_LE_D_MMR6
1002
42.9k
    UINT64_C(2080375441), // CMP_LE_PH
1003
42.9k
    UINT64_C(133),  // CMP_LE_PH_MM
1004
42.9k
    UINT64_C(1182793734), // CMP_LE_S
1005
42.9k
    UINT64_C(1409286533), // CMP_LE_S_MMR6
1006
42.9k
    UINT64_C(1184890884), // CMP_LT_D
1007
42.9k
    UINT64_C(1409286421), // CMP_LT_D_MMR6
1008
42.9k
    UINT64_C(2080375377), // CMP_LT_PH
1009
42.9k
    UINT64_C(69), // CMP_LT_PH_MM
1010
42.9k
    UINT64_C(1182793732), // CMP_LT_S
1011
42.9k
    UINT64_C(1409286405), // CMP_LT_S_MMR6
1012
42.9k
    UINT64_C(1184890888), // CMP_SAF_D
1013
42.9k
    UINT64_C(1409286677), // CMP_SAF_D_MMR6
1014
42.9k
    UINT64_C(1182793736), // CMP_SAF_S
1015
42.9k
    UINT64_C(1409286661), // CMP_SAF_S_MMR6
1016
42.9k
    UINT64_C(1184890890), // CMP_SEQ_D
1017
42.9k
    UINT64_C(1409286805), // CMP_SEQ_D_MMR6
1018
42.9k
    UINT64_C(1182793738), // CMP_SEQ_S
1019
42.9k
    UINT64_C(1409286789), // CMP_SEQ_S_MMR6
1020
42.9k
    UINT64_C(1184890894), // CMP_SLE_D
1021
42.9k
    UINT64_C(1409287061), // CMP_SLE_D_MMR6
1022
42.9k
    UINT64_C(1182793742), // CMP_SLE_S
1023
42.9k
    UINT64_C(1409287045), // CMP_SLE_S_MMR6
1024
42.9k
    UINT64_C(1184890892), // CMP_SLT_D
1025
42.9k
    UINT64_C(1409286933), // CMP_SLT_D_MMR6
1026
42.9k
    UINT64_C(1182793740), // CMP_SLT_S
1027
42.9k
    UINT64_C(1409286917), // CMP_SLT_S_MMR6
1028
42.9k
    UINT64_C(1184890891), // CMP_SUEQ_D
1029
42.9k
    UINT64_C(1409286869), // CMP_SUEQ_D_MMR6
1030
42.9k
    UINT64_C(1182793739), // CMP_SUEQ_S
1031
42.9k
    UINT64_C(1409286853), // CMP_SUEQ_S_MMR6
1032
42.9k
    UINT64_C(1184890895), // CMP_SULE_D
1033
42.9k
    UINT64_C(1409287125), // CMP_SULE_D_MMR6
1034
42.9k
    UINT64_C(1182793743), // CMP_SULE_S
1035
42.9k
    UINT64_C(1409287109), // CMP_SULE_S_MMR6
1036
42.9k
    UINT64_C(1184890893), // CMP_SULT_D
1037
42.9k
    UINT64_C(1409286997), // CMP_SULT_D_MMR6
1038
42.9k
    UINT64_C(1182793741), // CMP_SULT_S
1039
42.9k
    UINT64_C(1409286981), // CMP_SULT_S_MMR6
1040
42.9k
    UINT64_C(1184890889), // CMP_SUN_D
1041
42.9k
    UINT64_C(1409286741), // CMP_SUN_D_MMR6
1042
42.9k
    UINT64_C(1182793737), // CMP_SUN_S
1043
42.9k
    UINT64_C(1409286725), // CMP_SUN_S_MMR6
1044
42.9k
    UINT64_C(1184890883), // CMP_UEQ_D
1045
42.9k
    UINT64_C(1409286357), // CMP_UEQ_D_MMR6
1046
42.9k
    UINT64_C(1182793731), // CMP_UEQ_S
1047
42.9k
    UINT64_C(1409286341), // CMP_UEQ_S_MMR6
1048
42.9k
    UINT64_C(1184890887), // CMP_ULE_D
1049
42.9k
    UINT64_C(1409286613), // CMP_ULE_D_MMR6
1050
42.9k
    UINT64_C(1182793735), // CMP_ULE_S
1051
42.9k
    UINT64_C(1409286597), // CMP_ULE_S_MMR6
1052
42.9k
    UINT64_C(1184890885), // CMP_ULT_D
1053
42.9k
    UINT64_C(1409286485), // CMP_ULT_D_MMR6
1054
42.9k
    UINT64_C(1182793733), // CMP_ULT_S
1055
42.9k
    UINT64_C(1409286469), // CMP_ULT_S_MMR6
1056
42.9k
    UINT64_C(1184890881), // CMP_UN_D
1057
42.9k
    UINT64_C(1409286229), // CMP_UN_D_MMR6
1058
42.9k
    UINT64_C(1182793729), // CMP_UN_S
1059
42.9k
    UINT64_C(1409286213), // CMP_UN_S_MMR6
1060
42.9k
    UINT64_C(2021654553), // COPY_S_B
1061
42.9k
    UINT64_C(2025324569), // COPY_S_D
1062
42.9k
    UINT64_C(2023751705), // COPY_S_H
1063
42.9k
    UINT64_C(2024800281), // COPY_S_W
1064
42.9k
    UINT64_C(2025848857), // COPY_U_B
1065
42.9k
    UINT64_C(2027946009), // COPY_U_H
1066
42.9k
    UINT64_C(2028994585), // COPY_U_W
1067
42.9k
    UINT64_C(2080374799), // CRC32B
1068
42.9k
    UINT64_C(2080375055), // CRC32CB
1069
42.9k
    UINT64_C(2080375247), // CRC32CD
1070
42.9k
    UINT64_C(2080375119), // CRC32CH
1071
42.9k
    UINT64_C(2080375183), // CRC32CW
1072
42.9k
    UINT64_C(2080374991), // CRC32D
1073
42.9k
    UINT64_C(2080374863), // CRC32H
1074
42.9k
    UINT64_C(2080374927), // CRC32W
1075
42.9k
    UINT64_C(1153433600), // CTC1
1076
42.9k
    UINT64_C(1409292347), // CTC1_MM
1077
42.9k
    UINT64_C(56636),  // CTC2_MM
1078
42.9k
    UINT64_C(2017329177), // CTCMSA
1079
42.9k
    UINT64_C(1174405153), // CVT_D32_S
1080
42.9k
    UINT64_C(1409291131), // CVT_D32_S_MM
1081
42.9k
    UINT64_C(1182793761), // CVT_D32_W
1082
42.9k
    UINT64_C(1409299323), // CVT_D32_W_MM
1083
42.9k
    UINT64_C(1184890913), // CVT_D64_L
1084
42.9k
    UINT64_C(1174405153), // CVT_D64_S
1085
42.9k
    UINT64_C(1409291131), // CVT_D64_S_MM
1086
42.9k
    UINT64_C(1182793761), // CVT_D64_W
1087
42.9k
    UINT64_C(1409299323), // CVT_D64_W_MM
1088
42.9k
    UINT64_C(1409307515), // CVT_D_L_MMR6
1089
42.9k
    UINT64_C(1176502309), // CVT_L_D64
1090
42.9k
    UINT64_C(1409302843), // CVT_L_D64_MM
1091
42.9k
    UINT64_C(1409302843), // CVT_L_D_MMR6
1092
42.9k
    UINT64_C(1174405157), // CVT_L_S
1093
42.9k
    UINT64_C(1409286459), // CVT_L_S_MM
1094
42.9k
    UINT64_C(1409286459), // CVT_L_S_MMR6
1095
42.9k
    UINT64_C(1174405158), // CVT_PS_S64
1096
42.9k
    UINT64_C(1176502304), // CVT_S_D32
1097
42.9k
    UINT64_C(1409293179), // CVT_S_D32_MM
1098
42.9k
    UINT64_C(1176502304), // CVT_S_D64
1099
42.9k
    UINT64_C(1409293179), // CVT_S_D64_MM
1100
42.9k
    UINT64_C(1184890912), // CVT_S_L
1101
42.9k
    UINT64_C(1409309563), // CVT_S_L_MMR6
1102
42.9k
    UINT64_C(1186988072), // CVT_S_PL64
1103
42.9k
    UINT64_C(1186988064), // CVT_S_PU64
1104
42.9k
    UINT64_C(1182793760), // CVT_S_W
1105
42.9k
    UINT64_C(1409301371), // CVT_S_W_MM
1106
42.9k
    UINT64_C(1409301371), // CVT_S_W_MMR6
1107
42.9k
    UINT64_C(1176502308), // CVT_W_D32
1108
42.9k
    UINT64_C(1409304891), // CVT_W_D32_MM
1109
42.9k
    UINT64_C(1176502308), // CVT_W_D64
1110
42.9k
    UINT64_C(1409304891), // CVT_W_D64_MM
1111
42.9k
    UINT64_C(1174405156), // CVT_W_S
1112
42.9k
    UINT64_C(1409288507), // CVT_W_S_MM
1113
42.9k
    UINT64_C(1409288507), // CVT_W_S_MMR6
1114
42.9k
    UINT64_C(1176502322), // C_EQ_D32
1115
42.9k
    UINT64_C(1409287356), // C_EQ_D32_MM
1116
42.9k
    UINT64_C(1176502322), // C_EQ_D64
1117
42.9k
    UINT64_C(1409287356), // C_EQ_D64_MM
1118
42.9k
    UINT64_C(1174405170), // C_EQ_S
1119
42.9k
    UINT64_C(1409286332), // C_EQ_S_MM
1120
42.9k
    UINT64_C(1176502320), // C_F_D32
1121
42.9k
    UINT64_C(1409287228), // C_F_D32_MM
1122
42.9k
    UINT64_C(1176502320), // C_F_D64
1123
42.9k
    UINT64_C(1409287228), // C_F_D64_MM
1124
42.9k
    UINT64_C(1174405168), // C_F_S
1125
42.9k
    UINT64_C(1409286204), // C_F_S_MM
1126
42.9k
    UINT64_C(1176502334), // C_LE_D32
1127
42.9k
    UINT64_C(1409288124), // C_LE_D32_MM
1128
42.9k
    UINT64_C(1176502334), // C_LE_D64
1129
42.9k
    UINT64_C(1409288124), // C_LE_D64_MM
1130
42.9k
    UINT64_C(1174405182), // C_LE_S
1131
42.9k
    UINT64_C(1409287100), // C_LE_S_MM
1132
42.9k
    UINT64_C(1176502332), // C_LT_D32
1133
42.9k
    UINT64_C(1409287996), // C_LT_D32_MM
1134
42.9k
    UINT64_C(1176502332), // C_LT_D64
1135
42.9k
    UINT64_C(1409287996), // C_LT_D64_MM
1136
42.9k
    UINT64_C(1174405180), // C_LT_S
1137
42.9k
    UINT64_C(1409286972), // C_LT_S_MM
1138
42.9k
    UINT64_C(1176502333), // C_NGE_D32
1139
42.9k
    UINT64_C(1409288060), // C_NGE_D32_MM
1140
42.9k
    UINT64_C(1176502333), // C_NGE_D64
1141
42.9k
    UINT64_C(1409288060), // C_NGE_D64_MM
1142
42.9k
    UINT64_C(1174405181), // C_NGE_S
1143
42.9k
    UINT64_C(1409287036), // C_NGE_S_MM
1144
42.9k
    UINT64_C(1176502329), // C_NGLE_D32
1145
42.9k
    UINT64_C(1409287804), // C_NGLE_D32_MM
1146
42.9k
    UINT64_C(1176502329), // C_NGLE_D64
1147
42.9k
    UINT64_C(1409287804), // C_NGLE_D64_MM
1148
42.9k
    UINT64_C(1174405177), // C_NGLE_S
1149
42.9k
    UINT64_C(1409286780), // C_NGLE_S_MM
1150
42.9k
    UINT64_C(1176502331), // C_NGL_D32
1151
42.9k
    UINT64_C(1409287932), // C_NGL_D32_MM
1152
42.9k
    UINT64_C(1176502331), // C_NGL_D64
1153
42.9k
    UINT64_C(1409287932), // C_NGL_D64_MM
1154
42.9k
    UINT64_C(1174405179), // C_NGL_S
1155
42.9k
    UINT64_C(1409286908), // C_NGL_S_MM
1156
42.9k
    UINT64_C(1176502335), // C_NGT_D32
1157
42.9k
    UINT64_C(1409288188), // C_NGT_D32_MM
1158
42.9k
    UINT64_C(1176502335), // C_NGT_D64
1159
42.9k
    UINT64_C(1409288188), // C_NGT_D64_MM
1160
42.9k
    UINT64_C(1174405183), // C_NGT_S
1161
42.9k
    UINT64_C(1409287164), // C_NGT_S_MM
1162
42.9k
    UINT64_C(1176502326), // C_OLE_D32
1163
42.9k
    UINT64_C(1409287612), // C_OLE_D32_MM
1164
42.9k
    UINT64_C(1176502326), // C_OLE_D64
1165
42.9k
    UINT64_C(1409287612), // C_OLE_D64_MM
1166
42.9k
    UINT64_C(1174405174), // C_OLE_S
1167
42.9k
    UINT64_C(1409286588), // C_OLE_S_MM
1168
42.9k
    UINT64_C(1176502324), // C_OLT_D32
1169
42.9k
    UINT64_C(1409287484), // C_OLT_D32_MM
1170
42.9k
    UINT64_C(1176502324), // C_OLT_D64
1171
42.9k
    UINT64_C(1409287484), // C_OLT_D64_MM
1172
42.9k
    UINT64_C(1174405172), // C_OLT_S
1173
42.9k
    UINT64_C(1409286460), // C_OLT_S_MM
1174
42.9k
    UINT64_C(1176502330), // C_SEQ_D32
1175
42.9k
    UINT64_C(1409287868), // C_SEQ_D32_MM
1176
42.9k
    UINT64_C(1176502330), // C_SEQ_D64
1177
42.9k
    UINT64_C(1409287868), // C_SEQ_D64_MM
1178
42.9k
    UINT64_C(1174405178), // C_SEQ_S
1179
42.9k
    UINT64_C(1409286844), // C_SEQ_S_MM
1180
42.9k
    UINT64_C(1176502328), // C_SF_D32
1181
42.9k
    UINT64_C(1409287740), // C_SF_D32_MM
1182
42.9k
    UINT64_C(1176502328), // C_SF_D64
1183
42.9k
    UINT64_C(1409287740), // C_SF_D64_MM
1184
42.9k
    UINT64_C(1174405176), // C_SF_S
1185
42.9k
    UINT64_C(1409286716), // C_SF_S_MM
1186
42.9k
    UINT64_C(1176502323), // C_UEQ_D32
1187
42.9k
    UINT64_C(1409287420), // C_UEQ_D32_MM
1188
42.9k
    UINT64_C(1176502323), // C_UEQ_D64
1189
42.9k
    UINT64_C(1409287420), // C_UEQ_D64_MM
1190
42.9k
    UINT64_C(1174405171), // C_UEQ_S
1191
42.9k
    UINT64_C(1409286396), // C_UEQ_S_MM
1192
42.9k
    UINT64_C(1176502327), // C_ULE_D32
1193
42.9k
    UINT64_C(1409287676), // C_ULE_D32_MM
1194
42.9k
    UINT64_C(1176502327), // C_ULE_D64
1195
42.9k
    UINT64_C(1409287676), // C_ULE_D64_MM
1196
42.9k
    UINT64_C(1174405175), // C_ULE_S
1197
42.9k
    UINT64_C(1409286652), // C_ULE_S_MM
1198
42.9k
    UINT64_C(1176502325), // C_ULT_D32
1199
42.9k
    UINT64_C(1409287548), // C_ULT_D32_MM
1200
42.9k
    UINT64_C(1176502325), // C_ULT_D64
1201
42.9k
    UINT64_C(1409287548), // C_ULT_D64_MM
1202
42.9k
    UINT64_C(1174405173), // C_ULT_S
1203
42.9k
    UINT64_C(1409286524), // C_ULT_S_MM
1204
42.9k
    UINT64_C(1176502321), // C_UN_D32
1205
42.9k
    UINT64_C(1409287292), // C_UN_D32_MM
1206
42.9k
    UINT64_C(1176502321), // C_UN_D64
1207
42.9k
    UINT64_C(1409287292), // C_UN_D64_MM
1208
42.9k
    UINT64_C(1174405169), // C_UN_S
1209
42.9k
    UINT64_C(1409286268), // C_UN_S_MM
1210
42.9k
    UINT64_C(59402),  // CmpRxRy16
1211
42.9k
    UINT64_C(28672),  // CmpiRxImm16
1212
42.9k
    UINT64_C(4026560512), // CmpiRxImmX16
1213
42.9k
    UINT64_C(44), // DADD
1214
42.9k
    UINT64_C(1610612736), // DADDi
1215
42.9k
    UINT64_C(1677721600), // DADDiu
1216
42.9k
    UINT64_C(45), // DADDu
1217
42.9k
    UINT64_C(67502080), // DAHI
1218
42.9k
    UINT64_C(2080375332), // DALIGN
1219
42.9k
    UINT64_C(69074944), // DATI
1220
42.9k
    UINT64_C(1946157056), // DAUI
1221
42.9k
    UINT64_C(2080374820), // DBITSWAP
1222
42.9k
    UINT64_C(1879048229), // DCLO
1223
42.9k
    UINT64_C(83), // DCLO_R6
1224
42.9k
    UINT64_C(1879048228), // DCLZ
1225
42.9k
    UINT64_C(82), // DCLZ_R6
1226
42.9k
    UINT64_C(158),  // DDIV
1227
42.9k
    UINT64_C(159),  // DDIVU
1228
42.9k
    UINT64_C(1107296287), // DERET
1229
42.9k
    UINT64_C(58236),  // DERET_MM
1230
42.9k
    UINT64_C(58236),  // DERET_MMR6
1231
42.9k
    UINT64_C(2080374787), // DEXT
1232
42.9k
    UINT64_C(2080374787), // DEXT64_32
1233
42.9k
    UINT64_C(2080374785), // DEXTM
1234
42.9k
    UINT64_C(2080374786), // DEXTU
1235
42.9k
    UINT64_C(1096835072), // DI
1236
42.9k
    UINT64_C(2080374791), // DINS
1237
42.9k
    UINT64_C(2080374789), // DINSM
1238
42.9k
    UINT64_C(2080374790), // DINSU
1239
42.9k
    UINT64_C(154),  // DIV
1240
42.9k
    UINT64_C(155),  // DIVU
1241
42.9k
    UINT64_C(408),  // DIVU_MMR6
1242
42.9k
    UINT64_C(280),  // DIV_MMR6
1243
42.9k
    UINT64_C(2046820370), // DIV_S_B
1244
42.9k
    UINT64_C(2053111826), // DIV_S_D
1245
42.9k
    UINT64_C(2048917522), // DIV_S_H
1246
42.9k
    UINT64_C(2051014674), // DIV_S_W
1247
42.9k
    UINT64_C(2055208978), // DIV_U_B
1248
42.9k
    UINT64_C(2061500434), // DIV_U_D
1249
42.9k
    UINT64_C(2057306130), // DIV_U_H
1250
42.9k
    UINT64_C(2059403282), // DIV_U_W
1251
42.9k
    UINT64_C(18300),  // DI_MM
1252
42.9k
    UINT64_C(18300),  // DI_MMR6
1253
42.9k
    UINT64_C(21), // DLSA
1254
42.9k
    UINT64_C(21), // DLSA_R6
1255
42.9k
    UINT64_C(1075838976), // DMFC0
1256
42.9k
    UINT64_C(1142947840), // DMFC1
1257
42.9k
    UINT64_C(1210056704), // DMFC2
1258
42.9k
    UINT64_C(1210056704), // DMFC2_OCTEON
1259
42.9k
    UINT64_C(1080033536), // DMFGC0
1260
42.9k
    UINT64_C(222),  // DMOD
1261
42.9k
    UINT64_C(223),  // DMODU
1262
42.9k
    UINT64_C(1096813505), // DMT
1263
42.9k
    UINT64_C(1084227584), // DMTC0
1264
42.9k
    UINT64_C(1151336448), // DMTC1
1265
42.9k
    UINT64_C(1218445312), // DMTC2
1266
42.9k
    UINT64_C(1218445312), // DMTC2_OCTEON
1267
42.9k
    UINT64_C(1080034048), // DMTGC0
1268
42.9k
    UINT64_C(220),  // DMUH
1269
42.9k
    UINT64_C(221),  // DMUHU
1270
42.9k
    UINT64_C(1879048195), // DMUL
1271
42.9k
    UINT64_C(28), // DMULT
1272
42.9k
    UINT64_C(29), // DMULTu
1273
42.9k
    UINT64_C(157),  // DMULU
1274
42.9k
    UINT64_C(156),  // DMUL_R6
1275
42.9k
    UINT64_C(2019557395), // DOTP_S_D
1276
42.9k
    UINT64_C(2015363091), // DOTP_S_H
1277
42.9k
    UINT64_C(2017460243), // DOTP_S_W
1278
42.9k
    UINT64_C(2027946003), // DOTP_U_D
1279
42.9k
    UINT64_C(2023751699), // DOTP_U_H
1280
42.9k
    UINT64_C(2025848851), // DOTP_U_W
1281
42.9k
    UINT64_C(2036334611), // DPADD_S_D
1282
42.9k
    UINT64_C(2032140307), // DPADD_S_H
1283
42.9k
    UINT64_C(2034237459), // DPADD_S_W
1284
42.9k
    UINT64_C(2044723219), // DPADD_U_D
1285
42.9k
    UINT64_C(2040528915), // DPADD_U_H
1286
42.9k
    UINT64_C(2042626067), // DPADD_U_W
1287
42.9k
    UINT64_C(2080376496), // DPAQX_SA_W_PH
1288
42.9k
    UINT64_C(12988),  // DPAQX_SA_W_PH_MMR2
1289
42.9k
    UINT64_C(2080376368), // DPAQX_S_W_PH
1290
42.9k
    UINT64_C(8892), // DPAQX_S_W_PH_MMR2
1291
42.9k
    UINT64_C(2080375600), // DPAQ_SA_L_W
1292
42.9k
    UINT64_C(4796), // DPAQ_SA_L_W_MM
1293
42.9k
    UINT64_C(2080375088), // DPAQ_S_W_PH
1294
42.9k
    UINT64_C(700),  // DPAQ_S_W_PH_MM
1295
42.9k
    UINT64_C(2080375024), // DPAU_H_QBL
1296
42.9k
    UINT64_C(8380), // DPAU_H_QBL_MM
1297
42.9k
    UINT64_C(2080375280), // DPAU_H_QBR
1298
42.9k
    UINT64_C(12476),  // DPAU_H_QBR_MM
1299
42.9k
    UINT64_C(2080375344), // DPAX_W_PH
1300
42.9k
    UINT64_C(4284), // DPAX_W_PH_MMR2
1301
42.9k
    UINT64_C(2080374832), // DPA_W_PH
1302
42.9k
    UINT64_C(188),  // DPA_W_PH_MMR2
1303
42.9k
    UINT64_C(1879048237), // DPOP
1304
42.9k
    UINT64_C(2080376560), // DPSQX_SA_W_PH
1305
42.9k
    UINT64_C(14012),  // DPSQX_SA_W_PH_MMR2
1306
42.9k
    UINT64_C(2080376432), // DPSQX_S_W_PH
1307
42.9k
    UINT64_C(9916), // DPSQX_S_W_PH_MMR2
1308
42.9k
    UINT64_C(2080375664), // DPSQ_SA_L_W
1309
42.9k
    UINT64_C(5820), // DPSQ_SA_L_W_MM
1310
42.9k
    UINT64_C(2080375152), // DPSQ_S_W_PH
1311
42.9k
    UINT64_C(1724), // DPSQ_S_W_PH_MM
1312
42.9k
    UINT64_C(2053111827), // DPSUB_S_D
1313
42.9k
    UINT64_C(2048917523), // DPSUB_S_H
1314
42.9k
    UINT64_C(2051014675), // DPSUB_S_W
1315
42.9k
    UINT64_C(2061500435), // DPSUB_U_D
1316
42.9k
    UINT64_C(2057306131), // DPSUB_U_H
1317
42.9k
    UINT64_C(2059403283), // DPSUB_U_W
1318
42.9k
    UINT64_C(2080375536), // DPSU_H_QBL
1319
42.9k
    UINT64_C(9404), // DPSU_H_QBL_MM
1320
42.9k
    UINT64_C(2080375792), // DPSU_H_QBR
1321
42.9k
    UINT64_C(13500),  // DPSU_H_QBR_MM
1322
42.9k
    UINT64_C(2080375408), // DPSX_W_PH
1323
42.9k
    UINT64_C(5308), // DPSX_W_PH_MMR2
1324
42.9k
    UINT64_C(2080374896), // DPS_W_PH
1325
42.9k
    UINT64_C(1212), // DPS_W_PH_MMR2
1326
42.9k
    UINT64_C(2097210),  // DROTR
1327
42.9k
    UINT64_C(2097214),  // DROTR32
1328
42.9k
    UINT64_C(86), // DROTRV
1329
42.9k
    UINT64_C(2080374948), // DSBH
1330
42.9k
    UINT64_C(30), // DSDIV
1331
42.9k
    UINT64_C(2080375140), // DSHD
1332
42.9k
    UINT64_C(56), // DSLL
1333
42.9k
    UINT64_C(60), // DSLL32
1334
42.9k
    UINT64_C(60), // DSLL64_32
1335
42.9k
    UINT64_C(20), // DSLLV
1336
42.9k
    UINT64_C(59), // DSRA
1337
42.9k
    UINT64_C(63), // DSRA32
1338
42.9k
    UINT64_C(23), // DSRAV
1339
42.9k
    UINT64_C(58), // DSRL
1340
42.9k
    UINT64_C(62), // DSRL32
1341
42.9k
    UINT64_C(22), // DSRLV
1342
42.9k
    UINT64_C(46), // DSUB
1343
42.9k
    UINT64_C(47), // DSUBu
1344
42.9k
    UINT64_C(31), // DUDIV
1345
42.9k
    UINT64_C(1096810532), // DVP
1346
42.9k
    UINT64_C(1096810497), // DVPE
1347
42.9k
    UINT64_C(6524), // DVP_MMR6
1348
42.9k
    UINT64_C(59418),  // DivRxRy16
1349
42.9k
    UINT64_C(59419),  // DivuRxRy16
1350
42.9k
    UINT64_C(192),  // EHB
1351
42.9k
    UINT64_C(6144), // EHB_MM
1352
42.9k
    UINT64_C(6144), // EHB_MMR6
1353
42.9k
    UINT64_C(1096835104), // EI
1354
42.9k
    UINT64_C(22396),  // EI_MM
1355
42.9k
    UINT64_C(22396),  // EI_MMR6
1356
42.9k
    UINT64_C(1096813537), // EMT
1357
42.9k
    UINT64_C(1107296280), // ERET
1358
42.9k
    UINT64_C(1107296344), // ERETNC
1359
42.9k
    UINT64_C(127868), // ERETNC_MMR6
1360
42.9k
    UINT64_C(62332),  // ERET_MM
1361
42.9k
    UINT64_C(62332),  // ERET_MMR6
1362
42.9k
    UINT64_C(1096810500), // EVP
1363
42.9k
    UINT64_C(1096810529), // EVPE
1364
42.9k
    UINT64_C(14716),  // EVP_MMR6
1365
42.9k
    UINT64_C(2080374784), // EXT
1366
42.9k
    UINT64_C(2080374968), // EXTP
1367
42.9k
    UINT64_C(2080375480), // EXTPDP
1368
42.9k
    UINT64_C(2080375544), // EXTPDPV
1369
42.9k
    UINT64_C(14524),  // EXTPDPV_MM
1370
42.9k
    UINT64_C(13948),  // EXTPDP_MM
1371
42.9k
    UINT64_C(2080375032), // EXTPV
1372
42.9k
    UINT64_C(10428),  // EXTPV_MM
1373
42.9k
    UINT64_C(9852), // EXTP_MM
1374
42.9k
    UINT64_C(2080375288), // EXTRV_RS_W
1375
42.9k
    UINT64_C(11964),  // EXTRV_RS_W_MM
1376
42.9k
    UINT64_C(2080375160), // EXTRV_R_W
1377
42.9k
    UINT64_C(7868), // EXTRV_R_W_MM
1378
42.9k
    UINT64_C(2080375800), // EXTRV_S_H
1379
42.9k
    UINT64_C(16060),  // EXTRV_S_H_MM
1380
42.9k
    UINT64_C(2080374904), // EXTRV_W
1381
42.9k
    UINT64_C(3772), // EXTRV_W_MM
1382
42.9k
    UINT64_C(2080375224), // EXTR_RS_W
1383
42.9k
    UINT64_C(11900),  // EXTR_RS_W_MM
1384
42.9k
    UINT64_C(2080375096), // EXTR_R_W
1385
42.9k
    UINT64_C(7804), // EXTR_R_W_MM
1386
42.9k
    UINT64_C(2080375736), // EXTR_S_H
1387
42.9k
    UINT64_C(15996),  // EXTR_S_H_MM
1388
42.9k
    UINT64_C(2080374840), // EXTR_W
1389
42.9k
    UINT64_C(3708), // EXTR_W_MM
1390
42.9k
    UINT64_C(1879048250), // EXTS
1391
42.9k
    UINT64_C(1879048251), // EXTS32
1392
42.9k
    UINT64_C(44), // EXT_MM
1393
42.9k
    UINT64_C(44), // EXT_MMR6
1394
42.9k
    UINT64_C(1176502277), // FABS_D32
1395
42.9k
    UINT64_C(1409295227), // FABS_D32_MM
1396
42.9k
    UINT64_C(1176502277), // FABS_D64
1397
42.9k
    UINT64_C(1409295227), // FABS_D64_MM
1398
42.9k
    UINT64_C(1174405125), // FABS_S
1399
42.9k
    UINT64_C(1409287035), // FABS_S_MM
1400
42.9k
    UINT64_C(2015363099), // FADD_D
1401
42.9k
    UINT64_C(1176502272), // FADD_D32
1402
42.9k
    UINT64_C(1409286448), // FADD_D32_MM
1403
42.9k
    UINT64_C(1176502272), // FADD_D64
1404
42.9k
    UINT64_C(1409286448), // FADD_D64_MM
1405
42.9k
    UINT64_C(1174405120), // FADD_S
1406
42.9k
    UINT64_C(1409286192), // FADD_S_MM
1407
42.9k
    UINT64_C(1409286192), // FADD_S_MMR6
1408
42.9k
    UINT64_C(2013265947), // FADD_W
1409
42.9k
    UINT64_C(2015363098), // FCAF_D
1410
42.9k
    UINT64_C(2013265946), // FCAF_W
1411
42.9k
    UINT64_C(2023751706), // FCEQ_D
1412
42.9k
    UINT64_C(2021654554), // FCEQ_W
1413
42.9k
    UINT64_C(2065760286), // FCLASS_D
1414
42.9k
    UINT64_C(2065694750), // FCLASS_W
1415
42.9k
    UINT64_C(2040528922), // FCLE_D
1416
42.9k
    UINT64_C(2038431770), // FCLE_W
1417
42.9k
    UINT64_C(2032140314), // FCLT_D
1418
42.9k
    UINT64_C(2030043162), // FCLT_W
1419
42.9k
    UINT64_C(1176502320), // FCMP_D32
1420
42.9k
    UINT64_C(1409287228), // FCMP_D32_MM
1421
42.9k
    UINT64_C(1176502320), // FCMP_D64
1422
42.9k
    UINT64_C(1174405168), // FCMP_S32
1423
42.9k
    UINT64_C(1409286204), // FCMP_S32_MM
1424
42.9k
    UINT64_C(2027946012), // FCNE_D
1425
42.9k
    UINT64_C(2025848860), // FCNE_W
1426
42.9k
    UINT64_C(2019557404), // FCOR_D
1427
42.9k
    UINT64_C(2017460252), // FCOR_W
1428
42.9k
    UINT64_C(2027946010), // FCUEQ_D
1429
42.9k
    UINT64_C(2025848858), // FCUEQ_W
1430
42.9k
    UINT64_C(2044723226), // FCULE_D
1431
42.9k
    UINT64_C(2042626074), // FCULE_W
1432
42.9k
    UINT64_C(2036334618), // FCULT_D
1433
42.9k
    UINT64_C(2034237466), // FCULT_W
1434
42.9k
    UINT64_C(2023751708), // FCUNE_D
1435
42.9k
    UINT64_C(2021654556), // FCUNE_W
1436
42.9k
    UINT64_C(2019557402), // FCUN_D
1437
42.9k
    UINT64_C(2017460250), // FCUN_W
1438
42.9k
    UINT64_C(2027946011), // FDIV_D
1439
42.9k
    UINT64_C(1176502275), // FDIV_D32
1440
42.9k
    UINT64_C(1409286640), // FDIV_D32_MM
1441
42.9k
    UINT64_C(1176502275), // FDIV_D64
1442
42.9k
    UINT64_C(1409286640), // FDIV_D64_MM
1443
42.9k
    UINT64_C(1174405123), // FDIV_S
1444
42.9k
    UINT64_C(1409286384), // FDIV_S_MM
1445
42.9k
    UINT64_C(1409286384), // FDIV_S_MMR6
1446
42.9k
    UINT64_C(2025848859), // FDIV_W
1447
42.9k
    UINT64_C(2046820379), // FEXDO_H
1448
42.9k
    UINT64_C(2048917531), // FEXDO_W
1449
42.9k
    UINT64_C(2044723227), // FEXP2_D
1450
42.9k
    UINT64_C(2042626075), // FEXP2_W
1451
42.9k
    UINT64_C(2066808862), // FEXUPL_D
1452
42.9k
    UINT64_C(2066743326), // FEXUPL_W
1453
42.9k
    UINT64_C(2066939934), // FEXUPR_D
1454
42.9k
    UINT64_C(2066874398), // FEXUPR_W
1455
42.9k
    UINT64_C(2067595294), // FFINT_S_D
1456
42.9k
    UINT64_C(2067529758), // FFINT_S_W
1457
42.9k
    UINT64_C(2067726366), // FFINT_U_D
1458
42.9k
    UINT64_C(2067660830), // FFINT_U_W
1459
42.9k
    UINT64_C(2067071006), // FFQL_D
1460
42.9k
    UINT64_C(2067005470), // FFQL_W
1461
42.9k
    UINT64_C(2067202078), // FFQR_D
1462
42.9k
    UINT64_C(2067136542), // FFQR_W
1463
42.9k
    UINT64_C(2063597598), // FILL_B
1464
42.9k
    UINT64_C(2063794206), // FILL_D
1465
42.9k
    UINT64_C(2063663134), // FILL_H
1466
42.9k
    UINT64_C(2063728670), // FILL_W
1467
42.9k
    UINT64_C(2066677790), // FLOG2_D
1468
42.9k
    UINT64_C(2066612254), // FLOG2_W
1469
42.9k
    UINT64_C(1176502283), // FLOOR_L_D64
1470
42.9k
    UINT64_C(1409303355), // FLOOR_L_D_MMR6
1471
42.9k
    UINT64_C(1174405131), // FLOOR_L_S
1472
42.9k
    UINT64_C(1409286971), // FLOOR_L_S_MMR6
1473
42.9k
    UINT64_C(1176502287), // FLOOR_W_D32
1474
42.9k
    UINT64_C(1176502287), // FLOOR_W_D64
1475
42.9k
    UINT64_C(1409305403), // FLOOR_W_D_MMR6
1476
42.9k
    UINT64_C(1409305403), // FLOOR_W_MM
1477
42.9k
    UINT64_C(1174405135), // FLOOR_W_S
1478
42.9k
    UINT64_C(1409289019), // FLOOR_W_S_MM
1479
42.9k
    UINT64_C(1409289019), // FLOOR_W_S_MMR6
1480
42.9k
    UINT64_C(2032140315), // FMADD_D
1481
42.9k
    UINT64_C(2030043163), // FMADD_W
1482
42.9k
    UINT64_C(2078277659), // FMAX_A_D
1483
42.9k
    UINT64_C(2076180507), // FMAX_A_W
1484
42.9k
    UINT64_C(2074083355), // FMAX_D
1485
42.9k
    UINT64_C(2071986203), // FMAX_W
1486
42.9k
    UINT64_C(2069889051), // FMIN_A_D
1487
42.9k
    UINT64_C(2067791899), // FMIN_A_W
1488
42.9k
    UINT64_C(2065694747), // FMIN_D
1489
42.9k
    UINT64_C(2063597595), // FMIN_W
1490
42.9k
    UINT64_C(1176502278), // FMOV_D32
1491
42.9k
    UINT64_C(1409294459), // FMOV_D32_MM
1492
42.9k
    UINT64_C(1176502278), // FMOV_D64
1493
42.9k
    UINT64_C(1409294459), // FMOV_D64_MM
1494
42.9k
    UINT64_C(1174405126), // FMOV_S
1495
42.9k
    UINT64_C(1409286267), // FMOV_S_MM
1496
42.9k
    UINT64_C(1409286267), // FMOV_S_MMR6
1497
42.9k
    UINT64_C(2036334619), // FMSUB_D
1498
42.9k
    UINT64_C(2034237467), // FMSUB_W
1499
42.9k
    UINT64_C(2023751707), // FMUL_D
1500
42.9k
    UINT64_C(1176502274), // FMUL_D32
1501
42.9k
    UINT64_C(1409286576), // FMUL_D32_MM
1502
42.9k
    UINT64_C(1176502274), // FMUL_D64
1503
42.9k
    UINT64_C(1409286576), // FMUL_D64_MM
1504
42.9k
    UINT64_C(1174405122), // FMUL_S
1505
42.9k
    UINT64_C(1409286320), // FMUL_S_MM
1506
42.9k
    UINT64_C(1409286320), // FMUL_S_MMR6
1507
42.9k
    UINT64_C(2021654555), // FMUL_W
1508
42.9k
    UINT64_C(1176502279), // FNEG_D32
1509
42.9k
    UINT64_C(1409297275), // FNEG_D32_MM
1510
42.9k
    UINT64_C(1176502279), // FNEG_D64
1511
42.9k
    UINT64_C(1409297275), // FNEG_D64_MM
1512
42.9k
    UINT64_C(1174405127), // FNEG_S
1513
42.9k
    UINT64_C(1409289083), // FNEG_S_MM
1514
42.9k
    UINT64_C(1409289083), // FNEG_S_MMR6
1515
42.9k
    UINT64_C(2080374792), // FORK
1516
42.9k
    UINT64_C(2066415646), // FRCP_D
1517
42.9k
    UINT64_C(2066350110), // FRCP_W
1518
42.9k
    UINT64_C(2066546718), // FRINT_D
1519
42.9k
    UINT64_C(2066481182), // FRINT_W
1520
42.9k
    UINT64_C(2066284574), // FRSQRT_D
1521
42.9k
    UINT64_C(2066219038), // FRSQRT_W
1522
42.9k
    UINT64_C(2048917530), // FSAF_D
1523
42.9k
    UINT64_C(2046820378), // FSAF_W
1524
42.9k
    UINT64_C(2057306138), // FSEQ_D
1525
42.9k
    UINT64_C(2055208986), // FSEQ_W
1526
42.9k
    UINT64_C(2074083354), // FSLE_D
1527
42.9k
    UINT64_C(2071986202), // FSLE_W
1528
42.9k
    UINT64_C(2065694746), // FSLT_D
1529
42.9k
    UINT64_C(2063597594), // FSLT_W
1530
42.9k
    UINT64_C(2061500444), // FSNE_D
1531
42.9k
    UINT64_C(2059403292), // FSNE_W
1532
42.9k
    UINT64_C(2053111836), // FSOR_D
1533
42.9k
    UINT64_C(2051014684), // FSOR_W
1534
42.9k
    UINT64_C(2066153502), // FSQRT_D
1535
42.9k
    UINT64_C(1176502276), // FSQRT_D32
1536
42.9k
    UINT64_C(1409305147), // FSQRT_D32_MM
1537
42.9k
    UINT64_C(1176502276), // FSQRT_D64
1538
42.9k
    UINT64_C(1409305147), // FSQRT_D64_MM
1539
42.9k
    UINT64_C(1174405124), // FSQRT_S
1540
42.9k
    UINT64_C(1409288763), // FSQRT_S_MM
1541
42.9k
    UINT64_C(2066087966), // FSQRT_W
1542
42.9k
    UINT64_C(2019557403), // FSUB_D
1543
42.9k
    UINT64_C(1176502273), // FSUB_D32
1544
42.9k
    UINT64_C(1409286512), // FSUB_D32_MM
1545
42.9k
    UINT64_C(1176502273), // FSUB_D64
1546
42.9k
    UINT64_C(1409286512), // FSUB_D64_MM
1547
42.9k
    UINT64_C(1174405121), // FSUB_S
1548
42.9k
    UINT64_C(1409286256), // FSUB_S_MM
1549
42.9k
    UINT64_C(1409286256), // FSUB_S_MMR6
1550
42.9k
    UINT64_C(2017460251), // FSUB_W
1551
42.9k
    UINT64_C(2061500442), // FSUEQ_D
1552
42.9k
    UINT64_C(2059403290), // FSUEQ_W
1553
42.9k
    UINT64_C(2078277658), // FSULE_D
1554
42.9k
    UINT64_C(2076180506), // FSULE_W
1555
42.9k
    UINT64_C(2069889050), // FSULT_D
1556
42.9k
    UINT64_C(2067791898), // FSULT_W
1557
42.9k
    UINT64_C(2057306140), // FSUNE_D
1558
42.9k
    UINT64_C(2055208988), // FSUNE_W
1559
42.9k
    UINT64_C(2053111834), // FSUN_D
1560
42.9k
    UINT64_C(2051014682), // FSUN_W
1561
42.9k
    UINT64_C(2067333150), // FTINT_S_D
1562
42.9k
    UINT64_C(2067267614), // FTINT_S_W
1563
42.9k
    UINT64_C(2067464222), // FTINT_U_D
1564
42.9k
    UINT64_C(2067398686), // FTINT_U_W
1565
42.9k
    UINT64_C(2055208987), // FTQ_H
1566
42.9k
    UINT64_C(2057306139), // FTQ_W
1567
42.9k
    UINT64_C(2065891358), // FTRUNC_S_D
1568
42.9k
    UINT64_C(2065825822), // FTRUNC_S_W
1569
42.9k
    UINT64_C(2066022430), // FTRUNC_U_D
1570
42.9k
    UINT64_C(2065956894), // FTRUNC_U_W
1571
42.9k
    UINT64_C(2080374845), // GINVI
1572
42.9k
    UINT64_C(24956),  // GINVI_MMR6
1573
42.9k
    UINT64_C(2080374973), // GINVT
1574
42.9k
    UINT64_C(29052),  // GINVT_MMR6
1575
42.9k
    UINT64_C(2053111829), // HADD_S_D
1576
42.9k
    UINT64_C(2048917525), // HADD_S_H
1577
42.9k
    UINT64_C(2051014677), // HADD_S_W
1578
42.9k
    UINT64_C(2061500437), // HADD_U_D
1579
42.9k
    UINT64_C(2057306133), // HADD_U_H
1580
42.9k
    UINT64_C(2059403285), // HADD_U_W
1581
42.9k
    UINT64_C(2069889045), // HSUB_S_D
1582
42.9k
    UINT64_C(2065694741), // HSUB_S_H
1583
42.9k
    UINT64_C(2067791893), // HSUB_S_W
1584
42.9k
    UINT64_C(2078277653), // HSUB_U_D
1585
42.9k
    UINT64_C(2074083349), // HSUB_U_H
1586
42.9k
    UINT64_C(2076180501), // HSUB_U_W
1587
42.9k
    UINT64_C(1107296296), // HYPCALL
1588
42.9k
    UINT64_C(50044),  // HYPCALL_MM
1589
42.9k
    UINT64_C(2063597588), // ILVEV_B
1590
42.9k
    UINT64_C(2069889044), // ILVEV_D
1591
42.9k
    UINT64_C(2065694740), // ILVEV_H
1592
42.9k
    UINT64_C(2067791892), // ILVEV_W
1593
42.9k
    UINT64_C(2046820372), // ILVL_B
1594
42.9k
    UINT64_C(2053111828), // ILVL_D
1595
42.9k
    UINT64_C(2048917524), // ILVL_H
1596
42.9k
    UINT64_C(2051014676), // ILVL_W
1597
42.9k
    UINT64_C(2071986196), // ILVOD_B
1598
42.9k
    UINT64_C(2078277652), // ILVOD_D
1599
42.9k
    UINT64_C(2074083348), // ILVOD_H
1600
42.9k
    UINT64_C(2076180500), // ILVOD_W
1601
42.9k
    UINT64_C(2055208980), // ILVR_B
1602
42.9k
    UINT64_C(2061500436), // ILVR_D
1603
42.9k
    UINT64_C(2057306132), // ILVR_H
1604
42.9k
    UINT64_C(2059403284), // ILVR_W
1605
42.9k
    UINT64_C(2080374788), // INS
1606
42.9k
    UINT64_C(2030043161), // INSERT_B
1607
42.9k
    UINT64_C(2033713177), // INSERT_D
1608
42.9k
    UINT64_C(2032140313), // INSERT_H
1609
42.9k
    UINT64_C(2033188889), // INSERT_W
1610
42.9k
    UINT64_C(2080374796), // INSV
1611
42.9k
    UINT64_C(2034237465), // INSVE_B
1612
42.9k
    UINT64_C(2037907481), // INSVE_D
1613
42.9k
    UINT64_C(2036334617), // INSVE_H
1614
42.9k
    UINT64_C(2037383193), // INSVE_W
1615
42.9k
    UINT64_C(16700),  // INSV_MM
1616
42.9k
    UINT64_C(12), // INS_MM
1617
42.9k
    UINT64_C(12), // INS_MMR6
1618
42.9k
    UINT64_C(134217728),  // J
1619
42.9k
    UINT64_C(201326592),  // JAL
1620
42.9k
    UINT64_C(9),  // JALR
1621
42.9k
    UINT64_C(17856),  // JALR16_MM
1622
42.9k
    UINT64_C(9),  // JALR64
1623
42.9k
    UINT64_C(17419),  // JALRC16_MMR6
1624
42.9k
    UINT64_C(7996), // JALRC_HB_MMR6
1625
42.9k
    UINT64_C(3900), // JALRC_MMR6
1626
42.9k
    UINT64_C(17888),  // JALRS16_MM
1627
42.9k
    UINT64_C(20284),  // JALRS_MM
1628
42.9k
    UINT64_C(1033), // JALR_HB
1629
42.9k
    UINT64_C(1033), // JALR_HB64
1630
42.9k
    UINT64_C(3900), // JALR_MM
1631
42.9k
    UINT64_C(1946157056), // JALS_MM
1632
42.9k
    UINT64_C(1946157056), // JALX
1633
42.9k
    UINT64_C(4026531840), // JALX_MM
1634
42.9k
    UINT64_C(4093640704), // JAL_MM
1635
42.9k
    UINT64_C(4160749568), // JIALC
1636
42.9k
    UINT64_C(4160749568), // JIALC64
1637
42.9k
    UINT64_C(2147483648), // JIALC_MMR6
1638
42.9k
    UINT64_C(3623878656), // JIC
1639
42.9k
    UINT64_C(3623878656), // JIC64
1640
42.9k
    UINT64_C(2684354560), // JIC_MMR6
1641
42.9k
    UINT64_C(8),  // JR
1642
42.9k
    UINT64_C(17792),  // JR16_MM
1643
42.9k
    UINT64_C(8),  // JR64
1644
42.9k
    UINT64_C(18176),  // JRADDIUSP
1645
42.9k
    UINT64_C(17824),  // JRC16_MM
1646
42.9k
    UINT64_C(17411),  // JRC16_MMR6
1647
42.9k
    UINT64_C(17427),  // JRCADDIUSP_MMR6
1648
42.9k
    UINT64_C(1032), // JR_HB
1649
42.9k
    UINT64_C(1032), // JR_HB64
1650
42.9k
    UINT64_C(1033), // JR_HB64_R6
1651
42.9k
    UINT64_C(1033), // JR_HB_R6
1652
42.9k
    UINT64_C(3900), // JR_MM
1653
42.9k
    UINT64_C(3556769792), // J_MM
1654
42.9k
    UINT64_C(402653184),  // Jal16
1655
42.9k
    UINT64_C(402653184),  // JalB16
1656
42.9k
    UINT64_C(59424),  // JrRa16
1657
42.9k
    UINT64_C(59616),  // JrcRa16
1658
42.9k
    UINT64_C(59584),  // JrcRx16
1659
42.9k
    UINT64_C(59392),  // JumpLinkReg16
1660
42.9k
    UINT64_C(2147483648), // LB
1661
42.9k
    UINT64_C(2147483648), // LB64
1662
42.9k
    UINT64_C(2080374828), // LBE
1663
42.9k
    UINT64_C(1610639360), // LBE_MM
1664
42.9k
    UINT64_C(2048), // LBU16_MM
1665
42.9k
    UINT64_C(2080375178), // LBUX
1666
42.9k
    UINT64_C(549),  // LBUX_MM
1667
42.9k
    UINT64_C(335544320),  // LBU_MMR6
1668
42.9k
    UINT64_C(469762048),  // LB_MM
1669
42.9k
    UINT64_C(469762048),  // LB_MMR6
1670
42.9k
    UINT64_C(2415919104), // LBu
1671
42.9k
    UINT64_C(2415919104), // LBu64
1672
42.9k
    UINT64_C(2080374824), // LBuE
1673
42.9k
    UINT64_C(1610637312), // LBuE_MM
1674
42.9k
    UINT64_C(335544320),  // LBu_MM
1675
42.9k
    UINT64_C(3690987520), // LD
1676
42.9k
    UINT64_C(3556769792), // LDC1
1677
42.9k
    UINT64_C(3556769792), // LDC164
1678
42.9k
    UINT64_C(3154116608), // LDC1_D64_MMR6
1679
42.9k
    UINT64_C(3154116608), // LDC1_MM
1680
42.9k
    UINT64_C(3623878656), // LDC2
1681
42.9k
    UINT64_C(536879104),  // LDC2_MMR6
1682
42.9k
    UINT64_C(1237319680), // LDC2_R6
1683
42.9k
    UINT64_C(3690987520), // LDC3
1684
42.9k
    UINT64_C(2063597575), // LDI_B
1685
42.9k
    UINT64_C(2069889031), // LDI_D
1686
42.9k
    UINT64_C(2065694727), // LDI_H
1687
42.9k
    UINT64_C(2067791879), // LDI_W
1688
42.9k
    UINT64_C(1744830464), // LDL
1689
42.9k
    UINT64_C(3960995840), // LDPC
1690
42.9k
    UINT64_C(1811939328), // LDR
1691
42.9k
    UINT64_C(1275068417), // LDXC1
1692
42.9k
    UINT64_C(1275068417), // LDXC164
1693
42.9k
    UINT64_C(2013265952), // LD_B
1694
42.9k
    UINT64_C(2013265955), // LD_D
1695
42.9k
    UINT64_C(2013265953), // LD_H
1696
42.9k
    UINT64_C(2013265954), // LD_W
1697
42.9k
    UINT64_C(603979776),  // LEA_ADDiu
1698
42.9k
    UINT64_C(1677721600), // LEA_ADDiu64
1699
42.9k
    UINT64_C(805306368),  // LEA_ADDiu_MM
1700
42.9k
    UINT64_C(2214592512), // LH
1701
42.9k
    UINT64_C(2214592512), // LH64
1702
42.9k
    UINT64_C(2080374829), // LHE
1703
42.9k
    UINT64_C(1610639872), // LHE_MM
1704
42.9k
    UINT64_C(10240),  // LHU16_MM
1705
42.9k
    UINT64_C(2080375050), // LHX
1706
42.9k
    UINT64_C(357),  // LHX_MM
1707
42.9k
    UINT64_C(1006632960), // LH_MM
1708
42.9k
    UINT64_C(2483027968), // LHu
1709
42.9k
    UINT64_C(2483027968), // LHu64
1710
42.9k
    UINT64_C(2080374825), // LHuE
1711
42.9k
    UINT64_C(1610637824), // LHuE_MM
1712
42.9k
    UINT64_C(872415232),  // LHu_MM
1713
42.9k
    UINT64_C(60416),  // LI16_MM
1714
42.9k
    UINT64_C(60416),  // LI16_MMR6
1715
42.9k
    UINT64_C(3221225472), // LL
1716
42.9k
    UINT64_C(3221225472), // LL64
1717
42.9k
    UINT64_C(2080374838), // LL64_R6
1718
42.9k
    UINT64_C(3489660928), // LLD
1719
42.9k
    UINT64_C(2080374839), // LLD_R6
1720
42.9k
    UINT64_C(2080374830), // LLE
1721
42.9k
    UINT64_C(1610640384), // LLE_MM
1722
42.9k
    UINT64_C(1610625024), // LL_MM
1723
42.9k
    UINT64_C(1610625024), // LL_MMR6
1724
42.9k
    UINT64_C(2080374838), // LL_R6
1725
42.9k
    UINT64_C(5),  // LSA
1726
42.9k
    UINT64_C(15), // LSA_MMR6
1727
42.9k
    UINT64_C(5),  // LSA_R6
1728
42.9k
    UINT64_C(268435456),  // LUI_MMR6
1729
42.9k
    UINT64_C(1275068421), // LUXC1
1730
42.9k
    UINT64_C(1275068421), // LUXC164
1731
42.9k
    UINT64_C(1409286472), // LUXC1_MM
1732
42.9k
    UINT64_C(1006632960), // LUi
1733
42.9k
    UINT64_C(1006632960), // LUi64
1734
42.9k
    UINT64_C(1101004800), // LUi_MM
1735
42.9k
    UINT64_C(2348810240), // LW
1736
42.9k
    UINT64_C(26624),  // LW16_MM
1737
42.9k
    UINT64_C(2348810240), // LW64
1738
42.9k
    UINT64_C(3288334336), // LWC1
1739
42.9k
    UINT64_C(2617245696), // LWC1_MM
1740
42.9k
    UINT64_C(3355443200), // LWC2
1741
42.9k
    UINT64_C(536870912),  // LWC2_MMR6
1742
42.9k
    UINT64_C(1228931072), // LWC2_R6
1743
42.9k
    UINT64_C(3422552064), // LWC3
1744
42.9k
    UINT64_C(2348810240), // LWDSP
1745
42.9k
    UINT64_C(4227858432), // LWDSP_MM
1746
42.9k
    UINT64_C(2080374831), // LWE
1747
42.9k
    UINT64_C(1610640896), // LWE_MM
1748
42.9k
    UINT64_C(25600),  // LWGP_MM
1749
42.9k
    UINT64_C(2281701376), // LWL
1750
42.9k
    UINT64_C(2281701376), // LWL64
1751
42.9k
    UINT64_C(2080374809), // LWLE
1752
42.9k
    UINT64_C(1610638336), // LWLE_MM
1753
42.9k
    UINT64_C(1610612736), // LWL_MM
1754
42.9k
    UINT64_C(17664),  // LWM16_MM
1755
42.9k
    UINT64_C(17410),  // LWM16_MMR6
1756
42.9k
    UINT64_C(536891392),  // LWM32_MM
1757
42.9k
    UINT64_C(3959947264), // LWPC
1758
42.9k
    UINT64_C(2013790208), // LWPC_MMR6
1759
42.9k
    UINT64_C(536875008),  // LWP_MM
1760
42.9k
    UINT64_C(2550136832), // LWR
1761
42.9k
    UINT64_C(2550136832), // LWR64
1762
42.9k
    UINT64_C(2080374810), // LWRE
1763
42.9k
    UINT64_C(1610638848), // LWRE_MM
1764
42.9k
    UINT64_C(1610616832), // LWR_MM
1765
42.9k
    UINT64_C(18432),  // LWSP_MM
1766
42.9k
    UINT64_C(3960471552), // LWUPC
1767
42.9k
    UINT64_C(1610670080), // LWU_MM
1768
42.9k
    UINT64_C(2080374794), // LWX
1769
42.9k
    UINT64_C(1275068416), // LWXC1
1770
42.9k
    UINT64_C(1409286216), // LWXC1_MM
1771
42.9k
    UINT64_C(280),  // LWXS_MM
1772
42.9k
    UINT64_C(421),  // LWX_MM
1773
42.9k
    UINT64_C(4227858432), // LW_MM
1774
42.9k
    UINT64_C(4227858432), // LW_MMR6
1775
42.9k
    UINT64_C(2617245696), // LWu
1776
42.9k
    UINT64_C(4026570752), // LbRxRyOffMemX16
1777
42.9k
    UINT64_C(4026572800), // LbuRxRyOffMemX16
1778
42.9k
    UINT64_C(4026572800), // LhRxRyOffMemX16
1779
42.9k
    UINT64_C(4026572800), // LhuRxRyOffMemX16
1780
42.9k
    UINT64_C(26624),  // LiRxImm16
1781
42.9k
    UINT64_C(4026558464), // LiRxImmAlignX16
1782
42.9k
    UINT64_C(4026558464), // LiRxImmX16
1783
42.9k
    UINT64_C(45056),  // LwRxPcTcp16
1784
42.9k
    UINT64_C(4026576896), // LwRxPcTcpX16
1785
42.9k
    UINT64_C(4026570752), // LwRxRyOffMemX16
1786
42.9k
    UINT64_C(4026568704), // LwRxSpImmX16
1787
42.9k
    UINT64_C(1879048192), // MADD
1788
42.9k
    UINT64_C(1176502296), // MADDF_D
1789
42.9k
    UINT64_C(1409287096), // MADDF_D_MMR6
1790
42.9k
    UINT64_C(1174405144), // MADDF_S
1791
42.9k
    UINT64_C(1409286584), // MADDF_S_MMR6
1792
42.9k
    UINT64_C(2067791900), // MADDR_Q_H
1793
42.9k
    UINT64_C(2069889052), // MADDR_Q_W
1794
42.9k
    UINT64_C(1879048193), // MADDU
1795
42.9k
    UINT64_C(1879048193), // MADDU_DSP
1796
42.9k
    UINT64_C(6844), // MADDU_DSP_MM
1797
42.9k
    UINT64_C(56124),  // MADDU_MM
1798
42.9k
    UINT64_C(2021654546), // MADDV_B
1799
42.9k
    UINT64_C(2027946002), // MADDV_D
1800
42.9k
    UINT64_C(2023751698), // MADDV_H
1801
42.9k
    UINT64_C(2025848850), // MADDV_W
1802
42.9k
    UINT64_C(1275068449), // MADD_D32
1803
42.9k
    UINT64_C(1409286153), // MADD_D32_MM
1804
42.9k
    UINT64_C(1275068449), // MADD_D64
1805
42.9k
    UINT64_C(1879048192), // MADD_DSP
1806
42.9k
    UINT64_C(2748), // MADD_DSP_MM
1807
42.9k
    UINT64_C(52028),  // MADD_MM
1808
42.9k
    UINT64_C(2034237468), // MADD_Q_H
1809
42.9k
    UINT64_C(2036334620), // MADD_Q_W
1810
42.9k
    UINT64_C(1275068448), // MADD_S
1811
42.9k
    UINT64_C(1409286145), // MADD_S_MM
1812
42.9k
    UINT64_C(2080375856), // MAQ_SA_W_PHL
1813
42.9k
    UINT64_C(14972),  // MAQ_SA_W_PHL_MM
1814
42.9k
    UINT64_C(2080375984), // MAQ_SA_W_PHR
1815
42.9k
    UINT64_C(10876),  // MAQ_SA_W_PHR_MM
1816
42.9k
    UINT64_C(2080376112), // MAQ_S_W_PHL
1817
42.9k
    UINT64_C(6780), // MAQ_S_W_PHL_MM
1818
42.9k
    UINT64_C(2080376240), // MAQ_S_W_PHR
1819
42.9k
    UINT64_C(2684), // MAQ_S_W_PHR_MM
1820
42.9k
    UINT64_C(1176502303), // MAXA_D
1821
42.9k
    UINT64_C(1409286699), // MAXA_D_MMR6
1822
42.9k
    UINT64_C(1174405151), // MAXA_S
1823
42.9k
    UINT64_C(1409286187), // MAXA_S_MMR6
1824
42.9k
    UINT64_C(2030043142), // MAXI_S_B
1825
42.9k
    UINT64_C(2036334598), // MAXI_S_D
1826
42.9k
    UINT64_C(2032140294), // MAXI_S_H
1827
42.9k
    UINT64_C(2034237446), // MAXI_S_W
1828
42.9k
    UINT64_C(2038431750), // MAXI_U_B
1829
42.9k
    UINT64_C(2044723206), // MAXI_U_D
1830
42.9k
    UINT64_C(2040528902), // MAXI_U_H
1831
42.9k
    UINT64_C(2042626054), // MAXI_U_W
1832
42.9k
    UINT64_C(2063597582), // MAX_A_B
1833
42.9k
    UINT64_C(2069889038), // MAX_A_D
1834
42.9k
    UINT64_C(2065694734), // MAX_A_H
1835
42.9k
    UINT64_C(2067791886), // MAX_A_W
1836
42.9k
    UINT64_C(1176502301), // MAX_D
1837
42.9k
    UINT64_C(1409286667), // MAX_D_MMR6
1838
42.9k
    UINT64_C(1174405149), // MAX_S
1839
42.9k
    UINT64_C(2030043150), // MAX_S_B
1840
42.9k
    UINT64_C(2036334606), // MAX_S_D
1841
42.9k
    UINT64_C(2032140302), // MAX_S_H
1842
42.9k
    UINT64_C(1409286155), // MAX_S_MMR6
1843
42.9k
    UINT64_C(2034237454), // MAX_S_W
1844
42.9k
    UINT64_C(2038431758), // MAX_U_B
1845
42.9k
    UINT64_C(2044723214), // MAX_U_D
1846
42.9k
    UINT64_C(2040528910), // MAX_U_H
1847
42.9k
    UINT64_C(2042626062), // MAX_U_W
1848
42.9k
    UINT64_C(1073741824), // MFC0
1849
42.9k
    UINT64_C(252),  // MFC0_MMR6
1850
42.9k
    UINT64_C(1140850688), // MFC1
1851
42.9k
    UINT64_C(1140850688), // MFC1_D64
1852
42.9k
    UINT64_C(1409294395), // MFC1_MM
1853
42.9k
    UINT64_C(1409294395), // MFC1_MMR6
1854
42.9k
    UINT64_C(1207959552), // MFC2
1855
42.9k
    UINT64_C(19772),  // MFC2_MMR6
1856
42.9k
    UINT64_C(1080033280), // MFGC0
1857
42.9k
    UINT64_C(1276), // MFGC0_MM
1858
42.9k
    UINT64_C(244),  // MFHC0_MMR6
1859
42.9k
    UINT64_C(1147142144), // MFHC1_D32
1860
42.9k
    UINT64_C(1409298491), // MFHC1_D32_MM
1861
42.9k
    UINT64_C(1147142144), // MFHC1_D64
1862
42.9k
    UINT64_C(1409298491), // MFHC1_D64_MM
1863
42.9k
    UINT64_C(36156),  // MFHC2_MMR6
1864
42.9k
    UINT64_C(1080034304), // MFHGC0
1865
42.9k
    UINT64_C(1268), // MFHGC0_MM
1866
42.9k
    UINT64_C(16), // MFHI
1867
42.9k
    UINT64_C(17920),  // MFHI16_MM
1868
42.9k
    UINT64_C(16), // MFHI64
1869
42.9k
    UINT64_C(16), // MFHI_DSP
1870
42.9k
    UINT64_C(124),  // MFHI_DSP_MM
1871
42.9k
    UINT64_C(3452), // MFHI_MM
1872
42.9k
    UINT64_C(18), // MFLO
1873
42.9k
    UINT64_C(17984),  // MFLO16_MM
1874
42.9k
    UINT64_C(18), // MFLO64
1875
42.9k
    UINT64_C(18), // MFLO_DSP
1876
42.9k
    UINT64_C(4220), // MFLO_DSP_MM
1877
42.9k
    UINT64_C(7548), // MFLO_MM
1878
42.9k
    UINT64_C(1090519040), // MFTR
1879
42.9k
    UINT64_C(1176502302), // MINA_D
1880
42.9k
    UINT64_C(1409286691), // MINA_D_MMR6
1881
42.9k
    UINT64_C(1174405150), // MINA_S
1882
42.9k
    UINT64_C(1409286179), // MINA_S_MMR6
1883
42.9k
    UINT64_C(2046820358), // MINI_S_B
1884
42.9k
    UINT64_C(2053111814), // MINI_S_D
1885
42.9k
    UINT64_C(2048917510), // MINI_S_H
1886
42.9k
    UINT64_C(2051014662), // MINI_S_W
1887
42.9k
    UINT64_C(2055208966), // MINI_U_B
1888
42.9k
    UINT64_C(2061500422), // MINI_U_D
1889
42.9k
    UINT64_C(2057306118), // MINI_U_H
1890
42.9k
    UINT64_C(2059403270), // MINI_U_W
1891
42.9k
    UINT64_C(2071986190), // MIN_A_B
1892
42.9k
    UINT64_C(2078277646), // MIN_A_D
1893
42.9k
    UINT64_C(2074083342), // MIN_A_H
1894
42.9k
    UINT64_C(2076180494), // MIN_A_W
1895
42.9k
    UINT64_C(1176502300), // MIN_D
1896
42.9k
    UINT64_C(1409286659), // MIN_D_MMR6
1897
42.9k
    UINT64_C(1174405148), // MIN_S
1898
42.9k
    UINT64_C(2046820366), // MIN_S_B
1899
42.9k
    UINT64_C(2053111822), // MIN_S_D
1900
42.9k
    UINT64_C(2048917518), // MIN_S_H
1901
42.9k
    UINT64_C(1409286147), // MIN_S_MMR6
1902
42.9k
    UINT64_C(2051014670), // MIN_S_W
1903
42.9k
    UINT64_C(2055208974), // MIN_U_B
1904
42.9k
    UINT64_C(2061500430), // MIN_U_D
1905
42.9k
    UINT64_C(2057306126), // MIN_U_H
1906
42.9k
    UINT64_C(2059403278), // MIN_U_W
1907
42.9k
    UINT64_C(218),  // MOD
1908
42.9k
    UINT64_C(2080375952), // MODSUB
1909
42.9k
    UINT64_C(661),  // MODSUB_MM
1910
42.9k
    UINT64_C(219),  // MODU
1911
42.9k
    UINT64_C(472),  // MODU_MMR6
1912
42.9k
    UINT64_C(344),  // MOD_MMR6
1913
42.9k
    UINT64_C(2063597586), // MOD_S_B
1914
42.9k
    UINT64_C(2069889042), // MOD_S_D
1915
42.9k
    UINT64_C(2065694738), // MOD_S_H
1916
42.9k
    UINT64_C(2067791890), // MOD_S_W
1917
42.9k
    UINT64_C(2071986194), // MOD_U_B
1918
42.9k
    UINT64_C(2078277650), // MOD_U_D
1919
42.9k
    UINT64_C(2074083346), // MOD_U_H
1920
42.9k
    UINT64_C(2076180498), // MOD_U_W
1921
42.9k
    UINT64_C(3072), // MOVE16_MM
1922
42.9k
    UINT64_C(3072), // MOVE16_MMR6
1923
42.9k
    UINT64_C(33792),  // MOVEP_MM
1924
42.9k
    UINT64_C(17412),  // MOVEP_MMR6
1925
42.9k
    UINT64_C(2025717785), // MOVE_V
1926
42.9k
    UINT64_C(1176502289), // MOVF_D32
1927
42.9k
    UINT64_C(1409286688), // MOVF_D32_MM
1928
42.9k
    UINT64_C(1176502289), // MOVF_D64
1929
42.9k
    UINT64_C(1),  // MOVF_I
1930
42.9k
    UINT64_C(1),  // MOVF_I64
1931
42.9k
    UINT64_C(1409286523), // MOVF_I_MM
1932
42.9k
    UINT64_C(1174405137), // MOVF_S
1933
42.9k
    UINT64_C(1409286176), // MOVF_S_MM
1934
42.9k
    UINT64_C(1176502291), // MOVN_I64_D64
1935
42.9k
    UINT64_C(11), // MOVN_I64_I
1936
42.9k
    UINT64_C(11), // MOVN_I64_I64
1937
42.9k
    UINT64_C(1174405139), // MOVN_I64_S
1938
42.9k
    UINT64_C(1176502291), // MOVN_I_D32
1939
42.9k
    UINT64_C(1409286456), // MOVN_I_D32_MM
1940
42.9k
    UINT64_C(1176502291), // MOVN_I_D64
1941
42.9k
    UINT64_C(11), // MOVN_I_I
1942
42.9k
    UINT64_C(11), // MOVN_I_I64
1943
42.9k
    UINT64_C(24), // MOVN_I_MM
1944
42.9k
    UINT64_C(1174405139), // MOVN_I_S
1945
42.9k
    UINT64_C(1409286200), // MOVN_I_S_MM
1946
42.9k
    UINT64_C(1176567825), // MOVT_D32
1947
42.9k
    UINT64_C(1409286752), // MOVT_D32_MM
1948
42.9k
    UINT64_C(1176567825), // MOVT_D64
1949
42.9k
    UINT64_C(65537),  // MOVT_I
1950
42.9k
    UINT64_C(65537),  // MOVT_I64
1951
42.9k
    UINT64_C(1409288571), // MOVT_I_MM
1952
42.9k
    UINT64_C(1174470673), // MOVT_S
1953
42.9k
    UINT64_C(1409286240), // MOVT_S_MM
1954
42.9k
    UINT64_C(1176502290), // MOVZ_I64_D64
1955
42.9k
    UINT64_C(10), // MOVZ_I64_I
1956
42.9k
    UINT64_C(10), // MOVZ_I64_I64
1957
42.9k
    UINT64_C(1174405138), // MOVZ_I64_S
1958
42.9k
    UINT64_C(1176502290), // MOVZ_I_D32
1959
42.9k
    UINT64_C(1409286520), // MOVZ_I_D32_MM
1960
42.9k
    UINT64_C(1176502290), // MOVZ_I_D64
1961
42.9k
    UINT64_C(10), // MOVZ_I_I
1962
42.9k
    UINT64_C(10), // MOVZ_I_I64
1963
42.9k
    UINT64_C(88), // MOVZ_I_MM
1964
42.9k
    UINT64_C(1174405138), // MOVZ_I_S
1965
42.9k
    UINT64_C(1409286264), // MOVZ_I_S_MM
1966
42.9k
    UINT64_C(1879048196), // MSUB
1967
42.9k
    UINT64_C(1176502297), // MSUBF_D
1968
42.9k
    UINT64_C(1409287160), // MSUBF_D_MMR6
1969
42.9k
    UINT64_C(1174405145), // MSUBF_S
1970
42.9k
    UINT64_C(1409286648), // MSUBF_S_MMR6
1971
42.9k
    UINT64_C(2071986204), // MSUBR_Q_H
1972
42.9k
    UINT64_C(2074083356), // MSUBR_Q_W
1973
42.9k
    UINT64_C(1879048197), // MSUBU
1974
42.9k
    UINT64_C(1879048197), // MSUBU_DSP
1975
42.9k
    UINT64_C(15036),  // MSUBU_DSP_MM
1976
42.9k
    UINT64_C(64316),  // MSUBU_MM
1977
42.9k
    UINT64_C(2030043154), // MSUBV_B
1978
42.9k
    UINT64_C(2036334610), // MSUBV_D
1979
42.9k
    UINT64_C(2032140306), // MSUBV_H
1980
42.9k
    UINT64_C(2034237458), // MSUBV_W
1981
42.9k
    UINT64_C(1275068457), // MSUB_D32
1982
42.9k
    UINT64_C(1409286185), // MSUB_D32_MM
1983
42.9k
    UINT64_C(1275068457), // MSUB_D64
1984
42.9k
    UINT64_C(1879048196), // MSUB_DSP
1985
42.9k
    UINT64_C(10940),  // MSUB_DSP_MM
1986
42.9k
    UINT64_C(60220),  // MSUB_MM
1987
42.9k
    UINT64_C(2038431772), // MSUB_Q_H
1988
42.9k
    UINT64_C(2040528924), // MSUB_Q_W
1989
42.9k
    UINT64_C(1275068456), // MSUB_S
1990
42.9k
    UINT64_C(1409286177), // MSUB_S_MM
1991
42.9k
    UINT64_C(1082130432), // MTC0
1992
42.9k
    UINT64_C(764),  // MTC0_MMR6
1993
42.9k
    UINT64_C(1149239296), // MTC1
1994
42.9k
    UINT64_C(1149239296), // MTC1_D64
1995
42.9k
    UINT64_C(1409296443), // MTC1_D64_MM
1996
42.9k
    UINT64_C(1409296443), // MTC1_MM
1997
42.9k
    UINT64_C(1409296443), // MTC1_MMR6
1998
42.9k
    UINT64_C(1216348160), // MTC2
1999
42.9k
    UINT64_C(23868),  // MTC2_MMR6
2000
42.9k
    UINT64_C(1080033792), // MTGC0
2001
42.9k
    UINT64_C(1788), // MTGC0_MM
2002
42.9k
    UINT64_C(756),  // MTHC0_MMR6
2003
42.9k
    UINT64_C(1155530752), // MTHC1_D32
2004
42.9k
    UINT64_C(1409300539), // MTHC1_D32_MM
2005
42.9k
    UINT64_C(1155530752), // MTHC1_D64
2006
42.9k
    UINT64_C(1409300539), // MTHC1_D64_MM
2007
42.9k
    UINT64_C(40252),  // MTHC2_MMR6
2008
42.9k
    UINT64_C(1080034816), // MTHGC0
2009
42.9k
    UINT64_C(1780), // MTHGC0_MM
2010
42.9k
    UINT64_C(17), // MTHI
2011
42.9k
    UINT64_C(17), // MTHI64
2012
42.9k
    UINT64_C(17), // MTHI_DSP
2013
42.9k
    UINT64_C(8316), // MTHI_DSP_MM
2014
42.9k
    UINT64_C(11644),  // MTHI_MM
2015
42.9k
    UINT64_C(2080376824), // MTHLIP
2016
42.9k
    UINT64_C(636),  // MTHLIP_MM
2017
42.9k
    UINT64_C(19), // MTLO
2018
42.9k
    UINT64_C(19), // MTLO64
2019
42.9k
    UINT64_C(19), // MTLO_DSP
2020
42.9k
    UINT64_C(12412),  // MTLO_DSP_MM
2021
42.9k
    UINT64_C(15740),  // MTLO_MM
2022
42.9k
    UINT64_C(1879048200), // MTM0
2023
42.9k
    UINT64_C(1879048204), // MTM1
2024
42.9k
    UINT64_C(1879048205), // MTM2
2025
42.9k
    UINT64_C(1879048201), // MTP0
2026
42.9k
    UINT64_C(1879048202), // MTP1
2027
42.9k
    UINT64_C(1879048203), // MTP2
2028
42.9k
    UINT64_C(1098907648), // MTTR
2029
42.9k
    UINT64_C(216),  // MUH
2030
42.9k
    UINT64_C(217),  // MUHU
2031
42.9k
    UINT64_C(216),  // MUHU_MMR6
2032
42.9k
    UINT64_C(88), // MUH_MMR6
2033
42.9k
    UINT64_C(1879048194), // MUL
2034
42.9k
    UINT64_C(2080376592), // MULEQ_S_W_PHL
2035
42.9k
    UINT64_C(37), // MULEQ_S_W_PHL_MM
2036
42.9k
    UINT64_C(2080376656), // MULEQ_S_W_PHR
2037
42.9k
    UINT64_C(101),  // MULEQ_S_W_PHR_MM
2038
42.9k
    UINT64_C(2080375184), // MULEU_S_PH_QBL
2039
42.9k
    UINT64_C(149),  // MULEU_S_PH_QBL_MM
2040
42.9k
    UINT64_C(2080375248), // MULEU_S_PH_QBR
2041
42.9k
    UINT64_C(213),  // MULEU_S_PH_QBR_MM
2042
42.9k
    UINT64_C(2080376784), // MULQ_RS_PH
2043
42.9k
    UINT64_C(277),  // MULQ_RS_PH_MM
2044
42.9k
    UINT64_C(2080376280), // MULQ_RS_W
2045
42.9k
    UINT64_C(405),  // MULQ_RS_W_MMR2
2046
42.9k
    UINT64_C(2080376720), // MULQ_S_PH
2047
42.9k
    UINT64_C(341),  // MULQ_S_PH_MMR2
2048
42.9k
    UINT64_C(2080376216), // MULQ_S_W
2049
42.9k
    UINT64_C(469),  // MULQ_S_W_MMR2
2050
42.9k
    UINT64_C(2063597596), // MULR_Q_H
2051
42.9k
    UINT64_C(2065694748), // MULR_Q_W
2052
42.9k
    UINT64_C(2080375216), // MULSAQ_S_W_PH
2053
42.9k
    UINT64_C(15548),  // MULSAQ_S_W_PH_MM
2054
42.9k
    UINT64_C(2080374960), // MULSA_W_PH
2055
42.9k
    UINT64_C(11452),  // MULSA_W_PH_MMR2
2056
42.9k
    UINT64_C(24), // MULT
2057
42.9k
    UINT64_C(25), // MULTU_DSP
2058
42.9k
    UINT64_C(7356), // MULTU_DSP_MM
2059
42.9k
    UINT64_C(24), // MULT_DSP
2060
42.9k
    UINT64_C(3260), // MULT_DSP_MM
2061
42.9k
    UINT64_C(35644),  // MULT_MM
2062
42.9k
    UINT64_C(25), // MULTu
2063
42.9k
    UINT64_C(39740),  // MULTu_MM
2064
42.9k
    UINT64_C(153),  // MULU
2065
42.9k
    UINT64_C(152),  // MULU_MMR6
2066
42.9k
    UINT64_C(2013265938), // MULV_B
2067
42.9k
    UINT64_C(2019557394), // MULV_D
2068
42.9k
    UINT64_C(2015363090), // MULV_H
2069
42.9k
    UINT64_C(2017460242), // MULV_W
2070
42.9k
    UINT64_C(528),  // MUL_MM
2071
42.9k
    UINT64_C(24), // MUL_MMR6
2072
42.9k
    UINT64_C(2080375576), // MUL_PH
2073
42.9k
    UINT64_C(45), // MUL_PH_MMR2
2074
42.9k
    UINT64_C(2030043164), // MUL_Q_H
2075
42.9k
    UINT64_C(2032140316), // MUL_Q_W
2076
42.9k
    UINT64_C(152),  // MUL_R6
2077
42.9k
    UINT64_C(2080375704), // MUL_S_PH
2078
42.9k
    UINT64_C(1069), // MUL_S_PH_MMR2
2079
42.9k
    UINT64_C(59408),  // Mfhi16
2080
42.9k
    UINT64_C(59410),  // Mflo16
2081
42.9k
    UINT64_C(25856),  // Move32R16
2082
42.9k
    UINT64_C(26368),  // MoveR3216
2083
42.9k
    UINT64_C(2064121886), // NLOC_B
2084
42.9k
    UINT64_C(2064318494), // NLOC_D
2085
42.9k
    UINT64_C(2064187422), // NLOC_H
2086
42.9k
    UINT64_C(2064252958), // NLOC_W
2087
42.9k
    UINT64_C(2064384030), // NLZC_B
2088
42.9k
    UINT64_C(2064580638), // NLZC_D
2089
42.9k
    UINT64_C(2064449566), // NLZC_H
2090
42.9k
    UINT64_C(2064515102), // NLZC_W
2091
42.9k
    UINT64_C(1275068465), // NMADD_D32
2092
42.9k
    UINT64_C(1409286154), // NMADD_D32_MM
2093
42.9k
    UINT64_C(1275068465), // NMADD_D64
2094
42.9k
    UINT64_C(1275068464), // NMADD_S
2095
42.9k
    UINT64_C(1409286146), // NMADD_S_MM
2096
42.9k
    UINT64_C(1275068473), // NMSUB_D32
2097
42.9k
    UINT64_C(1409286186), // NMSUB_D32_MM
2098
42.9k
    UINT64_C(1275068473), // NMSUB_D64
2099
42.9k
    UINT64_C(1275068472), // NMSUB_S
2100
42.9k
    UINT64_C(1409286178), // NMSUB_S_MM
2101
42.9k
    UINT64_C(39), // NOR
2102
42.9k
    UINT64_C(39), // NOR64
2103
42.9k
    UINT64_C(2046820352), // NORI_B
2104
42.9k
    UINT64_C(720),  // NOR_MM
2105
42.9k
    UINT64_C(720),  // NOR_MMR6
2106
42.9k
    UINT64_C(2017460254), // NOR_V
2107
42.9k
    UINT64_C(17408),  // NOT16_MM
2108
42.9k
    UINT64_C(17408),  // NOT16_MMR6
2109
42.9k
    UINT64_C(59421),  // NegRxRy16
2110
42.9k
    UINT64_C(59407),  // NotRxRy16
2111
42.9k
    UINT64_C(37), // OR
2112
42.9k
    UINT64_C(17600),  // OR16_MM
2113
42.9k
    UINT64_C(17417),  // OR16_MMR6
2114
42.9k
    UINT64_C(37), // OR64
2115
42.9k
    UINT64_C(2030043136), // ORI_B
2116
42.9k
    UINT64_C(1342177280), // ORI_MMR6
2117
42.9k
    UINT64_C(656),  // OR_MM
2118
42.9k
    UINT64_C(656),  // OR_MMR6
2119
42.9k
    UINT64_C(2015363102), // OR_V
2120
42.9k
    UINT64_C(872415232),  // ORi
2121
42.9k
    UINT64_C(872415232),  // ORi64
2122
42.9k
    UINT64_C(1342177280), // ORi_MM
2123
42.9k
    UINT64_C(59405),  // OrRxRxRy16
2124
42.9k
    UINT64_C(2080375697), // PACKRL_PH
2125
42.9k
    UINT64_C(429),  // PACKRL_PH_MM
2126
42.9k
    UINT64_C(320),  // PAUSE
2127
42.9k
    UINT64_C(10240),  // PAUSE_MM
2128
42.9k
    UINT64_C(10240),  // PAUSE_MMR6
2129
42.9k
    UINT64_C(2030043156), // PCKEV_B
2130
42.9k
    UINT64_C(2036334612), // PCKEV_D
2131
42.9k
    UINT64_C(2032140308), // PCKEV_H
2132
42.9k
    UINT64_C(2034237460), // PCKEV_W
2133
42.9k
    UINT64_C(2038431764), // PCKOD_B
2134
42.9k
    UINT64_C(2044723220), // PCKOD_D
2135
42.9k
    UINT64_C(2040528916), // PCKOD_H
2136
42.9k
    UINT64_C(2042626068), // PCKOD_W
2137
42.9k
    UINT64_C(2063859742), // PCNT_B
2138
42.9k
    UINT64_C(2064056350), // PCNT_D
2139
42.9k
    UINT64_C(2063925278), // PCNT_H
2140
42.9k
    UINT64_C(2063990814), // PCNT_W
2141
42.9k
    UINT64_C(2080375505), // PICK_PH
2142
42.9k
    UINT64_C(557),  // PICK_PH_MM
2143
42.9k
    UINT64_C(2080374993), // PICK_QB
2144
42.9k
    UINT64_C(493),  // PICK_QB_MM
2145
42.9k
    UINT64_C(1186988076), // PLL_PS64
2146
42.9k
    UINT64_C(1186988077), // PLU_PS64
2147
42.9k
    UINT64_C(1879048236), // POP
2148
42.9k
    UINT64_C(2080375058), // PRECEQU_PH_QBL
2149
42.9k
    UINT64_C(2080375186), // PRECEQU_PH_QBLA
2150
42.9k
    UINT64_C(29500),  // PRECEQU_PH_QBLA_MM
2151
42.9k
    UINT64_C(28988),  // PRECEQU_PH_QBL_MM
2152
42.9k
    UINT64_C(2080375122), // PRECEQU_PH_QBR
2153
42.9k
    UINT64_C(2080375250), // PRECEQU_PH_QBRA
2154
42.9k
    UINT64_C(37692),  // PRECEQU_PH_QBRA_MM
2155
42.9k
    UINT64_C(37180),  // PRECEQU_PH_QBR_MM
2156
42.9k
    UINT64_C(2080375570), // PRECEQ_W_PHL
2157
42.9k
    UINT64_C(20796),  // PRECEQ_W_PHL_MM
2158
42.9k
    UINT64_C(2080375634), // PRECEQ_W_PHR
2159
42.9k
    UINT64_C(24892),  // PRECEQ_W_PHR_MM
2160
42.9k
    UINT64_C(2080376594), // PRECEU_PH_QBL
2161
42.9k
    UINT64_C(2080376722), // PRECEU_PH_QBLA
2162
42.9k
    UINT64_C(45884),  // PRECEU_PH_QBLA_MM
2163
42.9k
    UINT64_C(45372),  // PRECEU_PH_QBL_MM
2164
42.9k
    UINT64_C(2080376658), // PRECEU_PH_QBR
2165
42.9k
    UINT64_C(2080376786), // PRECEU_PH_QBRA
2166
42.9k
    UINT64_C(54076),  // PRECEU_PH_QBRA_MM
2167
42.9k
    UINT64_C(53564),  // PRECEU_PH_QBR_MM
2168
42.9k
    UINT64_C(2080375761), // PRECRQU_S_QB_PH
2169
42.9k
    UINT64_C(365),  // PRECRQU_S_QB_PH_MM
2170
42.9k
    UINT64_C(2080376081), // PRECRQ_PH_W
2171
42.9k
    UINT64_C(237),  // PRECRQ_PH_W_MM
2172
42.9k
    UINT64_C(2080375569), // PRECRQ_QB_PH
2173
42.9k
    UINT64_C(173),  // PRECRQ_QB_PH_MM
2174
42.9k
    UINT64_C(2080376145), // PRECRQ_RS_PH_W
2175
42.9k
    UINT64_C(301),  // PRECRQ_RS_PH_W_MM
2176
42.9k
    UINT64_C(2080375633), // PRECR_QB_PH
2177
42.9k
    UINT64_C(109),  // PRECR_QB_PH_MMR2
2178
42.9k
    UINT64_C(2080376721), // PRECR_SRA_PH_W
2179
42.9k
    UINT64_C(973),  // PRECR_SRA_PH_W_MMR2
2180
42.9k
    UINT64_C(2080376785), // PRECR_SRA_R_PH_W
2181
42.9k
    UINT64_C(1997), // PRECR_SRA_R_PH_W_MMR2
2182
42.9k
    UINT64_C(3422552064), // PREF
2183
42.9k
    UINT64_C(2080374819), // PREFE
2184
42.9k
    UINT64_C(1610654720), // PREFE_MM
2185
42.9k
    UINT64_C(1409286560), // PREFX_MM
2186
42.9k
    UINT64_C(1610620928), // PREF_MM
2187
42.9k
    UINT64_C(1610620928), // PREF_MMR6
2188
42.9k
    UINT64_C(2080374837), // PREF_R6
2189
42.9k
    UINT64_C(2080374897), // PREPEND
2190
42.9k
    UINT64_C(597),  // PREPEND_MMR2
2191
42.9k
    UINT64_C(2080376080), // RADDU_W_QB
2192
42.9k
    UINT64_C(61756),  // RADDU_W_QB_MM
2193
42.9k
    UINT64_C(2080375992), // RDDSP
2194
42.9k
    UINT64_C(1660), // RDDSP_MM
2195
42.9k
    UINT64_C(2080374843), // RDHWR
2196
42.9k
    UINT64_C(2080374843), // RDHWR64
2197
42.9k
    UINT64_C(27452),  // RDHWR_MM
2198
42.9k
    UINT64_C(448),  // RDHWR_MMR6
2199
42.9k
    UINT64_C(57724),  // RDPGPR_MMR6
2200
42.9k
    UINT64_C(1176502293), // RECIP_D32
2201
42.9k
    UINT64_C(1409307195), // RECIP_D32_MM
2202
42.9k
    UINT64_C(1176502293), // RECIP_D64
2203
42.9k
    UINT64_C(1409307195), // RECIP_D64_MM
2204
42.9k
    UINT64_C(1174405141), // RECIP_S
2205
42.9k
    UINT64_C(1409290811), // RECIP_S_MM
2206
42.9k
    UINT64_C(2080375506), // REPLV_PH
2207
42.9k
    UINT64_C(828),  // REPLV_PH_MM
2208
42.9k
    UINT64_C(2080374994), // REPLV_QB
2209
42.9k
    UINT64_C(4924), // REPLV_QB_MM
2210
42.9k
    UINT64_C(2080375442), // REPL_PH
2211
42.9k
    UINT64_C(61), // REPL_PH_MM
2212
42.9k
    UINT64_C(2080374930), // REPL_QB
2213
42.9k
    UINT64_C(1532), // REPL_QB_MM
2214
42.9k
    UINT64_C(1176502298), // RINT_D
2215
42.9k
    UINT64_C(1409286688), // RINT_D_MMR6
2216
42.9k
    UINT64_C(1174405146), // RINT_S
2217
42.9k
    UINT64_C(1409286176), // RINT_S_MMR6
2218
42.9k
    UINT64_C(2097154),  // ROTR
2219
42.9k
    UINT64_C(70), // ROTRV
2220
42.9k
    UINT64_C(208),  // ROTRV_MM
2221
42.9k
    UINT64_C(192),  // ROTR_MM
2222
42.9k
    UINT64_C(1176502280), // ROUND_L_D64
2223
42.9k
    UINT64_C(1409315643), // ROUND_L_D_MMR6
2224
42.9k
    UINT64_C(1174405128), // ROUND_L_S
2225
42.9k
    UINT64_C(1409299259), // ROUND_L_S_MMR6
2226
42.9k
    UINT64_C(1176502284), // ROUND_W_D32
2227
42.9k
    UINT64_C(1176502284), // ROUND_W_D64
2228
42.9k
    UINT64_C(1409317691), // ROUND_W_D_MMR6
2229
42.9k
    UINT64_C(1409317691), // ROUND_W_MM
2230
42.9k
    UINT64_C(1174405132), // ROUND_W_S
2231
42.9k
    UINT64_C(1409301307), // ROUND_W_S_MM
2232
42.9k
    UINT64_C(1409301307), // ROUND_W_S_MMR6
2233
42.9k
    UINT64_C(1176502294), // RSQRT_D32
2234
42.9k
    UINT64_C(1409303099), // RSQRT_D32_MM
2235
42.9k
    UINT64_C(1176502294), // RSQRT_D64
2236
42.9k
    UINT64_C(1409303099), // RSQRT_D64_MM
2237
42.9k
    UINT64_C(1174405142), // RSQRT_S
2238
42.9k
    UINT64_C(1409286715), // RSQRT_S_MM
2239
42.9k
    UINT64_C(25728),  // Restore16
2240
42.9k
    UINT64_C(25728),  // RestoreX16
2241
42.9k
    UINT64_C(2020605962), // SAT_S_B
2242
42.9k
    UINT64_C(2013265930), // SAT_S_D
2243
42.9k
    UINT64_C(2019557386), // SAT_S_H
2244
42.9k
    UINT64_C(2017460234), // SAT_S_W
2245
42.9k
    UINT64_C(2028994570), // SAT_U_B
2246
42.9k
    UINT64_C(2021654538), // SAT_U_D
2247
42.9k
    UINT64_C(2027945994), // SAT_U_H
2248
42.9k
    UINT64_C(2025848842), // SAT_U_W
2249
42.9k
    UINT64_C(2684354560), // SB
2250
42.9k
    UINT64_C(34816),  // SB16_MM
2251
42.9k
    UINT64_C(34816),  // SB16_MMR6
2252
42.9k
    UINT64_C(2684354560), // SB64
2253
42.9k
    UINT64_C(2080374812), // SBE
2254
42.9k
    UINT64_C(1610655744), // SBE_MM
2255
42.9k
    UINT64_C(402653184),  // SB_MM
2256
42.9k
    UINT64_C(402653184),  // SB_MMR6
2257
42.9k
    UINT64_C(3758096384), // SC
2258
42.9k
    UINT64_C(3758096384), // SC64
2259
42.9k
    UINT64_C(2080374822), // SC64_R6
2260
42.9k
    UINT64_C(4026531840), // SCD
2261
42.9k
    UINT64_C(2080374823), // SCD_R6
2262
42.9k
    UINT64_C(2080374814), // SCE
2263
42.9k
    UINT64_C(1610656768), // SCE_MM
2264
42.9k
    UINT64_C(1610657792), // SC_MM
2265
42.9k
    UINT64_C(1610657792), // SC_MMR6
2266
42.9k
    UINT64_C(2080374822), // SC_R6
2267
42.9k
    UINT64_C(4227858432), // SD
2268
42.9k
    UINT64_C(1879048255), // SDBBP
2269
42.9k
    UINT64_C(18112),  // SDBBP16_MM
2270
42.9k
    UINT64_C(17467),  // SDBBP16_MMR6
2271
42.9k
    UINT64_C(56188),  // SDBBP_MM
2272
42.9k
    UINT64_C(56188),  // SDBBP_MMR6
2273
42.9k
    UINT64_C(14), // SDBBP_R6
2274
42.9k
    UINT64_C(4093640704), // SDC1
2275
42.9k
    UINT64_C(4093640704), // SDC164
2276
42.9k
    UINT64_C(3087007744), // SDC1_D64_MMR6
2277
42.9k
    UINT64_C(3087007744), // SDC1_MM
2278
42.9k
    UINT64_C(4160749568), // SDC2
2279
42.9k
    UINT64_C(536911872),  // SDC2_MMR6
2280
42.9k
    UINT64_C(1239416832), // SDC2_R6
2281
42.9k
    UINT64_C(4227858432), // SDC3
2282
42.9k
    UINT64_C(26), // SDIV
2283
42.9k
    UINT64_C(43836),  // SDIV_MM
2284
42.9k
    UINT64_C(2952790016), // SDL
2285
42.9k
    UINT64_C(3019898880), // SDR
2286
42.9k
    UINT64_C(1275068425), // SDXC1
2287
42.9k
    UINT64_C(1275068425), // SDXC164
2288
42.9k
    UINT64_C(2080375840), // SEB
2289
42.9k
    UINT64_C(2080375840), // SEB64
2290
42.9k
    UINT64_C(11068),  // SEB_MM
2291
42.9k
    UINT64_C(2080376352), // SEH
2292
42.9k
    UINT64_C(2080376352), // SEH64
2293
42.9k
    UINT64_C(15164),  // SEH_MM
2294
42.9k
    UINT64_C(53), // SELEQZ
2295
42.9k
    UINT64_C(53), // SELEQZ64
2296
42.9k
    UINT64_C(1176502292), // SELEQZ_D
2297
42.9k
    UINT64_C(1409286712), // SELEQZ_D_MMR6
2298
42.9k
    UINT64_C(320),  // SELEQZ_MMR6
2299
42.9k
    UINT64_C(1174405140), // SELEQZ_S
2300
42.9k
    UINT64_C(1409286200), // SELEQZ_S_MMR6
2301
42.9k
    UINT64_C(55), // SELNEZ
2302
42.9k
    UINT64_C(55), // SELNEZ64
2303
42.9k
    UINT64_C(1176502295), // SELNEZ_D
2304
42.9k
    UINT64_C(1409286776), // SELNEZ_D_MMR6
2305
42.9k
    UINT64_C(384),  // SELNEZ_MMR6
2306
42.9k
    UINT64_C(1174405143), // SELNEZ_S
2307
42.9k
    UINT64_C(1409286264), // SELNEZ_S_MMR6
2308
42.9k
    UINT64_C(1176502288), // SEL_D
2309
42.9k
    UINT64_C(1409286840), // SEL_D_MMR6
2310
42.9k
    UINT64_C(1174405136), // SEL_S
2311
42.9k
    UINT64_C(1409286328), // SEL_S_MMR6
2312
42.9k
    UINT64_C(1879048234), // SEQ
2313
42.9k
    UINT64_C(1879048238), // SEQi
2314
42.9k
    UINT64_C(2751463424), // SH
2315
42.9k
    UINT64_C(43008),  // SH16_MM
2316
42.9k
    UINT64_C(43008),  // SH16_MMR6
2317
42.9k
    UINT64_C(2751463424), // SH64
2318
42.9k
    UINT64_C(2080374813), // SHE
2319
42.9k
    UINT64_C(1610656256), // SHE_MM
2320
42.9k
    UINT64_C(2013265922), // SHF_B
2321
42.9k
    UINT64_C(2030043138), // SHF_H
2322
42.9k
    UINT64_C(2046820354), // SHF_W
2323
42.9k
    UINT64_C(2080376504), // SHILO
2324
42.9k
    UINT64_C(2080376568), // SHILOV
2325
42.9k
    UINT64_C(4732), // SHILOV_MM
2326
42.9k
    UINT64_C(29), // SHILO_MM
2327
42.9k
    UINT64_C(2080375443), // SHLLV_PH
2328
42.9k
    UINT64_C(14), // SHLLV_PH_MM
2329
42.9k
    UINT64_C(2080374931), // SHLLV_QB
2330
42.9k
    UINT64_C(917),  // SHLLV_QB_MM
2331
42.9k
    UINT64_C(2080375699), // SHLLV_S_PH
2332
42.9k
    UINT64_C(1038), // SHLLV_S_PH_MM
2333
42.9k
    UINT64_C(2080376211), // SHLLV_S_W
2334
42.9k
    UINT64_C(981),  // SHLLV_S_W_MM
2335
42.9k
    UINT64_C(2080375315), // SHLL_PH
2336
42.9k
    UINT64_C(949),  // SHLL_PH_MM
2337
42.9k
    UINT64_C(2080374803), // SHLL_QB
2338
42.9k
    UINT64_C(2172), // SHLL_QB_MM
2339
42.9k
    UINT64_C(2080375571), // SHLL_S_PH
2340
42.9k
    UINT64_C(2997), // SHLL_S_PH_MM
2341
42.9k
    UINT64_C(2080376083), // SHLL_S_W
2342
42.9k
    UINT64_C(1013), // SHLL_S_W_MM
2343
42.9k
    UINT64_C(2080375507), // SHRAV_PH
2344
42.9k
    UINT64_C(397),  // SHRAV_PH_MM
2345
42.9k
    UINT64_C(2080375187), // SHRAV_QB
2346
42.9k
    UINT64_C(461),  // SHRAV_QB_MMR2
2347
42.9k
    UINT64_C(2080375763), // SHRAV_R_PH
2348
42.9k
    UINT64_C(1421), // SHRAV_R_PH_MM
2349
42.9k
    UINT64_C(2080375251), // SHRAV_R_QB
2350
42.9k
    UINT64_C(1485), // SHRAV_R_QB_MMR2
2351
42.9k
    UINT64_C(2080376275), // SHRAV_R_W
2352
42.9k
    UINT64_C(725),  // SHRAV_R_W_MM
2353
42.9k
    UINT64_C(2080375379), // SHRA_PH
2354
42.9k
    UINT64_C(821),  // SHRA_PH_MM
2355
42.9k
    UINT64_C(2080375059), // SHRA_QB
2356
42.9k
    UINT64_C(508),  // SHRA_QB_MMR2
2357
42.9k
    UINT64_C(2080375635), // SHRA_R_PH
2358
42.9k
    UINT64_C(1845), // SHRA_R_PH_MM
2359
42.9k
    UINT64_C(2080375123), // SHRA_R_QB
2360
42.9k
    UINT64_C(4604), // SHRA_R_QB_MMR2
2361
42.9k
    UINT64_C(2080376147), // SHRA_R_W
2362
42.9k
    UINT64_C(757),  // SHRA_R_W_MM
2363
42.9k
    UINT64_C(2080376531), // SHRLV_PH
2364
42.9k
    UINT64_C(789),  // SHRLV_PH_MMR2
2365
42.9k
    UINT64_C(2080374995), // SHRLV_QB
2366
42.9k
    UINT64_C(853),  // SHRLV_QB_MM
2367
42.9k
    UINT64_C(2080376403), // SHRL_PH
2368
42.9k
    UINT64_C(1020), // SHRL_PH_MMR2
2369
42.9k
    UINT64_C(2080374867), // SHRL_QB
2370
42.9k
    UINT64_C(6268), // SHRL_QB_MM
2371
42.9k
    UINT64_C(939524096),  // SH_MM
2372
42.9k
    UINT64_C(939524096),  // SH_MMR6
2373
42.9k
    UINT64_C(68616192), // SIGRIE
2374
42.9k
    UINT64_C(63), // SIGRIE_MMR6
2375
42.9k
    UINT64_C(2013265945), // SLDI_B
2376
42.9k
    UINT64_C(2016935961), // SLDI_D
2377
42.9k
    UINT64_C(2015363097), // SLDI_H
2378
42.9k
    UINT64_C(2016411673), // SLDI_W
2379
42.9k
    UINT64_C(2013265940), // SLD_B
2380
42.9k
    UINT64_C(2019557396), // SLD_D
2381
42.9k
    UINT64_C(2015363092), // SLD_H
2382
42.9k
    UINT64_C(2017460244), // SLD_W
2383
42.9k
    UINT64_C(0),  // SLL
2384
42.9k
    UINT64_C(9216), // SLL16_MM
2385
42.9k
    UINT64_C(9216), // SLL16_MMR6
2386
42.9k
    UINT64_C(0),  // SLL64_32
2387
42.9k
    UINT64_C(0),  // SLL64_64
2388
42.9k
    UINT64_C(2020605961), // SLLI_B
2389
42.9k
    UINT64_C(2013265929), // SLLI_D
2390
42.9k
    UINT64_C(2019557385), // SLLI_H
2391
42.9k
    UINT64_C(2017460233), // SLLI_W
2392
42.9k
    UINT64_C(4),  // SLLV
2393
42.9k
    UINT64_C(16), // SLLV_MM
2394
42.9k
    UINT64_C(2013265933), // SLL_B
2395
42.9k
    UINT64_C(2019557389), // SLL_D
2396
42.9k
    UINT64_C(2015363085), // SLL_H
2397
42.9k
    UINT64_C(0),  // SLL_MM
2398
42.9k
    UINT64_C(0),  // SLL_MMR6
2399
42.9k
    UINT64_C(2017460237), // SLL_W
2400
42.9k
    UINT64_C(42), // SLT
2401
42.9k
    UINT64_C(42), // SLT64
2402
42.9k
    UINT64_C(848),  // SLT_MM
2403
42.9k
    UINT64_C(671088640),  // SLTi
2404
42.9k
    UINT64_C(671088640),  // SLTi64
2405
42.9k
    UINT64_C(2415919104), // SLTi_MM
2406
42.9k
    UINT64_C(738197504),  // SLTiu
2407
42.9k
    UINT64_C(738197504),  // SLTiu64
2408
42.9k
    UINT64_C(2952790016), // SLTiu_MM
2409
42.9k
    UINT64_C(43), // SLTu
2410
42.9k
    UINT64_C(43), // SLTu64
2411
42.9k
    UINT64_C(912),  // SLTu_MM
2412
42.9k
    UINT64_C(1879048235), // SNE
2413
42.9k
    UINT64_C(1879048239), // SNEi
2414
42.9k
    UINT64_C(2017460249), // SPLATI_B
2415
42.9k
    UINT64_C(2021130265), // SPLATI_D
2416
42.9k
    UINT64_C(2019557401), // SPLATI_H
2417
42.9k
    UINT64_C(2020605977), // SPLATI_W
2418
42.9k
    UINT64_C(2021654548), // SPLAT_B
2419
42.9k
    UINT64_C(2027946004), // SPLAT_D
2420
42.9k
    UINT64_C(2023751700), // SPLAT_H
2421
42.9k
    UINT64_C(2025848852), // SPLAT_W
2422
42.9k
    UINT64_C(3),  // SRA
2423
42.9k
    UINT64_C(2028994569), // SRAI_B
2424
42.9k
    UINT64_C(2021654537), // SRAI_D
2425
42.9k
    UINT64_C(2027945993), // SRAI_H
2426
42.9k
    UINT64_C(2025848841), // SRAI_W
2427
42.9k
    UINT64_C(2037383178), // SRARI_B
2428
42.9k
    UINT64_C(2030043146), // SRARI_D
2429
42.9k
    UINT64_C(2036334602), // SRARI_H
2430
42.9k
    UINT64_C(2034237450), // SRARI_W
2431
42.9k
    UINT64_C(2021654549), // SRAR_B
2432
42.9k
    UINT64_C(2027946005), // SRAR_D
2433
42.9k
    UINT64_C(2023751701), // SRAR_H
2434
42.9k
    UINT64_C(2025848853), // SRAR_W
2435
42.9k
    UINT64_C(7),  // SRAV
2436
42.9k
    UINT64_C(144),  // SRAV_MM
2437
42.9k
    UINT64_C(2021654541), // SRA_B
2438
42.9k
    UINT64_C(2027945997), // SRA_D
2439
42.9k
    UINT64_C(2023751693), // SRA_H
2440
42.9k
    UINT64_C(128),  // SRA_MM
2441
42.9k
    UINT64_C(2025848845), // SRA_W
2442
42.9k
    UINT64_C(2),  // SRL
2443
42.9k
    UINT64_C(9217), // SRL16_MM
2444
42.9k
    UINT64_C(9217), // SRL16_MMR6
2445
42.9k
    UINT64_C(2037383177), // SRLI_B
2446
42.9k
    UINT64_C(2030043145), // SRLI_D
2447
42.9k
    UINT64_C(2036334601), // SRLI_H
2448
42.9k
    UINT64_C(2034237449), // SRLI_W
2449
42.9k
    UINT64_C(2045771786), // SRLRI_B
2450
42.9k
    UINT64_C(2038431754), // SRLRI_D
2451
42.9k
    UINT64_C(2044723210), // SRLRI_H
2452
42.9k
    UINT64_C(2042626058), // SRLRI_W
2453
42.9k
    UINT64_C(2030043157), // SRLR_B
2454
42.9k
    UINT64_C(2036334613), // SRLR_D
2455
42.9k
    UINT64_C(2032140309), // SRLR_H
2456
42.9k
    UINT64_C(2034237461), // SRLR_W
2457
42.9k
    UINT64_C(6),  // SRLV
2458
42.9k
    UINT64_C(80), // SRLV_MM
2459
42.9k
    UINT64_C(2030043149), // SRL_B
2460
42.9k
    UINT64_C(2036334605), // SRL_D
2461
42.9k
    UINT64_C(2032140301), // SRL_H
2462
42.9k
    UINT64_C(64), // SRL_MM
2463
42.9k
    UINT64_C(2034237453), // SRL_W
2464
42.9k
    UINT64_C(64), // SSNOP
2465
42.9k
    UINT64_C(2048), // SSNOP_MM
2466
42.9k
    UINT64_C(2048), // SSNOP_MMR6
2467
42.9k
    UINT64_C(2013265956), // ST_B
2468
42.9k
    UINT64_C(2013265959), // ST_D
2469
42.9k
    UINT64_C(2013265957), // ST_H
2470
42.9k
    UINT64_C(2013265958), // ST_W
2471
42.9k
    UINT64_C(34), // SUB
2472
42.9k
    UINT64_C(2080375384), // SUBQH_PH
2473
42.9k
    UINT64_C(589),  // SUBQH_PH_MMR2
2474
42.9k
    UINT64_C(2080375512), // SUBQH_R_PH
2475
42.9k
    UINT64_C(1613), // SUBQH_R_PH_MMR2
2476
42.9k
    UINT64_C(2080376024), // SUBQH_R_W
2477
42.9k
    UINT64_C(1677), // SUBQH_R_W_MMR2
2478
42.9k
    UINT64_C(2080375896), // SUBQH_W
2479
42.9k
    UINT64_C(653),  // SUBQH_W_MMR2
2480
42.9k
    UINT64_C(2080375504), // SUBQ_PH
2481
42.9k
    UINT64_C(525),  // SUBQ_PH_MM
2482
42.9k
    UINT64_C(2080375760), // SUBQ_S_PH
2483
42.9k
    UINT64_C(1549), // SUBQ_S_PH_MM
2484
42.9k
    UINT64_C(2080376272), // SUBQ_S_W
2485
42.9k
    UINT64_C(837),  // SUBQ_S_W_MM
2486
42.9k
    UINT64_C(2030043153), // SUBSUS_U_B
2487
42.9k
    UINT64_C(2036334609), // SUBSUS_U_D
2488
42.9k
    UINT64_C(2032140305), // SUBSUS_U_H
2489
42.9k
    UINT64_C(2034237457), // SUBSUS_U_W
2490
42.9k
    UINT64_C(2038431761), // SUBSUU_S_B
2491
42.9k
    UINT64_C(2044723217), // SUBSUU_S_D
2492
42.9k
    UINT64_C(2040528913), // SUBSUU_S_H
2493
42.9k
    UINT64_C(2042626065), // SUBSUU_S_W
2494
42.9k
    UINT64_C(2013265937), // SUBS_S_B
2495
42.9k
    UINT64_C(2019557393), // SUBS_S_D
2496
42.9k
    UINT64_C(2015363089), // SUBS_S_H
2497
42.9k
    UINT64_C(2017460241), // SUBS_S_W
2498
42.9k
    UINT64_C(2021654545), // SUBS_U_B
2499
42.9k
    UINT64_C(2027946001), // SUBS_U_D
2500
42.9k
    UINT64_C(2023751697), // SUBS_U_H
2501
42.9k
    UINT64_C(2025848849), // SUBS_U_W
2502
42.9k
    UINT64_C(1025), // SUBU16_MM
2503
42.9k
    UINT64_C(1025), // SUBU16_MMR6
2504
42.9k
    UINT64_C(2080374872), // SUBUH_QB
2505
42.9k
    UINT64_C(845),  // SUBUH_QB_MMR2
2506
42.9k
    UINT64_C(2080375000), // SUBUH_R_QB
2507
42.9k
    UINT64_C(1869), // SUBUH_R_QB_MMR2
2508
42.9k
    UINT64_C(464),  // SUBU_MMR6
2509
42.9k
    UINT64_C(2080375376), // SUBU_PH
2510
42.9k
    UINT64_C(781),  // SUBU_PH_MMR2
2511
42.9k
    UINT64_C(2080374864), // SUBU_QB
2512
42.9k
    UINT64_C(717),  // SUBU_QB_MM
2513
42.9k
    UINT64_C(2080375632), // SUBU_S_PH
2514
42.9k
    UINT64_C(1805), // SUBU_S_PH_MMR2
2515
42.9k
    UINT64_C(2080375120), // SUBU_S_QB
2516
42.9k
    UINT64_C(1741), // SUBU_S_QB_MM
2517
42.9k
    UINT64_C(2021654534), // SUBVI_B
2518
42.9k
    UINT64_C(2027945990), // SUBVI_D
2519
42.9k
    UINT64_C(2023751686), // SUBVI_H
2520
42.9k
    UINT64_C(2025848838), // SUBVI_W
2521
42.9k
    UINT64_C(2021654542), // SUBV_B
2522
42.9k
    UINT64_C(2027945998), // SUBV_D
2523
42.9k
    UINT64_C(2023751694), // SUBV_H
2524
42.9k
    UINT64_C(2025848846), // SUBV_W
2525
42.9k
    UINT64_C(400),  // SUB_MM
2526
42.9k
    UINT64_C(400),  // SUB_MMR6
2527
42.9k
    UINT64_C(35), // SUBu
2528
42.9k
    UINT64_C(464),  // SUBu_MM
2529
42.9k
    UINT64_C(1275068429), // SUXC1
2530
42.9k
    UINT64_C(1275068429), // SUXC164
2531
42.9k
    UINT64_C(1409286536), // SUXC1_MM
2532
42.9k
    UINT64_C(2885681152), // SW
2533
42.9k
    UINT64_C(59392),  // SW16_MM
2534
42.9k
    UINT64_C(59392),  // SW16_MMR6
2535
42.9k
    UINT64_C(2885681152), // SW64
2536
42.9k
    UINT64_C(3825205248), // SWC1
2537
42.9k
    UINT64_C(2550136832), // SWC1_MM
2538
42.9k
    UINT64_C(3892314112), // SWC2
2539
42.9k
    UINT64_C(536903680),  // SWC2_MMR6
2540
42.9k
    UINT64_C(1231028224), // SWC2_R6
2541
42.9k
    UINT64_C(3959422976), // SWC3
2542
42.9k
    UINT64_C(2885681152), // SWDSP
2543
42.9k
    UINT64_C(4160749568), // SWDSP_MM
2544
42.9k
    UINT64_C(2080374815), // SWE
2545
42.9k
    UINT64_C(1610657280), // SWE_MM
2546
42.9k
    UINT64_C(2818572288), // SWL
2547
42.9k
    UINT64_C(2818572288), // SWL64
2548
42.9k
    UINT64_C(2080374817), // SWLE
2549
42.9k
    UINT64_C(1610653696), // SWLE_MM
2550
42.9k
    UINT64_C(1610645504), // SWL_MM
2551
42.9k
    UINT64_C(17728),  // SWM16_MM
2552
42.9k
    UINT64_C(17418),  // SWM16_MMR6
2553
42.9k
    UINT64_C(536924160),  // SWM32_MM
2554
42.9k
    UINT64_C(536907776),  // SWP_MM
2555
42.9k
    UINT64_C(3087007744), // SWR
2556
42.9k
    UINT64_C(3087007744), // SWR64
2557
42.9k
    UINT64_C(2080374818), // SWRE
2558
42.9k
    UINT64_C(1610654208), // SWRE_MM
2559
42.9k
    UINT64_C(1610649600), // SWR_MM
2560
42.9k
    UINT64_C(51200),  // SWSP_MM
2561
42.9k
    UINT64_C(51200),  // SWSP_MMR6
2562
42.9k
    UINT64_C(1275068424), // SWXC1
2563
42.9k
    UINT64_C(1409286280), // SWXC1_MM
2564
42.9k
    UINT64_C(4160749568), // SW_MM
2565
42.9k
    UINT64_C(4160749568), // SW_MMR6
2566
42.9k
    UINT64_C(15), // SYNC
2567
42.9k
    UINT64_C(69140480), // SYNCI
2568
42.9k
    UINT64_C(1107296256), // SYNCI_MM
2569
42.9k
    UINT64_C(1098907648), // SYNCI_MMR6
2570
42.9k
    UINT64_C(27516),  // SYNC_MM
2571
42.9k
    UINT64_C(27516),  // SYNC_MMR6
2572
42.9k
    UINT64_C(12), // SYSCALL
2573
42.9k
    UINT64_C(35708),  // SYSCALL_MM
2574
42.9k
    UINT64_C(25728),  // Save16
2575
42.9k
    UINT64_C(25728),  // SaveX16
2576
42.9k
    UINT64_C(4026580992), // SbRxRyOffMemX16
2577
42.9k
    UINT64_C(59537),  // SebRx16
2578
42.9k
    UINT64_C(59569),  // SehRx16
2579
42.9k
    UINT64_C(4026583040), // ShRxRyOffMemX16
2580
42.9k
    UINT64_C(4026544128), // SllX16
2581
42.9k
    UINT64_C(59396),  // SllvRxRy16
2582
42.9k
    UINT64_C(59394),  // SltRxRy16
2583
42.9k
    UINT64_C(20480),  // SltiRxImm16
2584
42.9k
    UINT64_C(4026552320), // SltiRxImmX16
2585
42.9k
    UINT64_C(22528),  // SltiuRxImm16
2586
42.9k
    UINT64_C(4026554368), // SltiuRxImmX16
2587
42.9k
    UINT64_C(59395),  // SltuRxRy16
2588
42.9k
    UINT64_C(4026544131), // SraX16
2589
42.9k
    UINT64_C(59399),  // SravRxRy16
2590
42.9k
    UINT64_C(4026544130), // SrlX16
2591
42.9k
    UINT64_C(59398),  // SrlvRxRy16
2592
42.9k
    UINT64_C(57347),  // SubuRxRyRz16
2593
42.9k
    UINT64_C(4026587136), // SwRxRyOffMemX16
2594
42.9k
    UINT64_C(4026585088), // SwRxSpImmX16
2595
42.9k
    UINT64_C(52), // TEQ
2596
42.9k
    UINT64_C(67895296), // TEQI
2597
42.9k
    UINT64_C(1103101952), // TEQI_MM
2598
42.9k
    UINT64_C(60), // TEQ_MM
2599
42.9k
    UINT64_C(48), // TGE
2600
42.9k
    UINT64_C(67633152), // TGEI
2601
42.9k
    UINT64_C(67698688), // TGEIU
2602
42.9k
    UINT64_C(1096810496), // TGEIU_MM
2603
42.9k
    UINT64_C(1092616192), // TGEI_MM
2604
42.9k
    UINT64_C(49), // TGEU
2605
42.9k
    UINT64_C(1084), // TGEU_MM
2606
42.9k
    UINT64_C(572),  // TGE_MM
2607
42.9k
    UINT64_C(1107296267), // TLBGINV
2608
42.9k
    UINT64_C(1107296268), // TLBGINVF
2609
42.9k
    UINT64_C(20860),  // TLBGINVF_MM
2610
42.9k
    UINT64_C(16764),  // TLBGINV_MM
2611
42.9k
    UINT64_C(1107296272), // TLBGP
2612
42.9k
    UINT64_C(380),  // TLBGP_MM
2613
42.9k
    UINT64_C(1107296265), // TLBGR
2614
42.9k
    UINT64_C(4476), // TLBGR_MM
2615
42.9k
    UINT64_C(1107296266), // TLBGWI
2616
42.9k
    UINT64_C(8572), // TLBGWI_MM
2617
42.9k
    UINT64_C(1107296270), // TLBGWR
2618
42.9k
    UINT64_C(12668),  // TLBGWR_MM
2619
42.9k
    UINT64_C(1107296259), // TLBINV
2620
42.9k
    UINT64_C(1107296260), // TLBINVF
2621
42.9k
    UINT64_C(21372),  // TLBINVF_MMR6
2622
42.9k
    UINT64_C(17276),  // TLBINV_MMR6
2623
42.9k
    UINT64_C(1107296264), // TLBP
2624
42.9k
    UINT64_C(892),  // TLBP_MM
2625
42.9k
    UINT64_C(1107296257), // TLBR
2626
42.9k
    UINT64_C(4988), // TLBR_MM
2627
42.9k
    UINT64_C(1107296258), // TLBWI
2628
42.9k
    UINT64_C(9084), // TLBWI_MM
2629
42.9k
    UINT64_C(1107296262), // TLBWR
2630
42.9k
    UINT64_C(13180),  // TLBWR_MM
2631
42.9k
    UINT64_C(50), // TLT
2632
42.9k
    UINT64_C(67764224), // TLTI
2633
42.9k
    UINT64_C(1094713344), // TLTIU_MM
2634
42.9k
    UINT64_C(1090519040), // TLTI_MM
2635
42.9k
    UINT64_C(51), // TLTU
2636
42.9k
    UINT64_C(2620), // TLTU_MM
2637
42.9k
    UINT64_C(2108), // TLT_MM
2638
42.9k
    UINT64_C(54), // TNE
2639
42.9k
    UINT64_C(68026368), // TNEI
2640
42.9k
    UINT64_C(1098907648), // TNEI_MM
2641
42.9k
    UINT64_C(3132), // TNE_MM
2642
42.9k
    UINT64_C(1176502281), // TRUNC_L_D64
2643
42.9k
    UINT64_C(1409311547), // TRUNC_L_D_MMR6
2644
42.9k
    UINT64_C(1174405129), // TRUNC_L_S
2645
42.9k
    UINT64_C(1409295163), // TRUNC_L_S_MMR6
2646
42.9k
    UINT64_C(1176502285), // TRUNC_W_D32
2647
42.9k
    UINT64_C(1176502285), // TRUNC_W_D64
2648
42.9k
    UINT64_C(1409313595), // TRUNC_W_D_MMR6
2649
42.9k
    UINT64_C(1409313595), // TRUNC_W_MM
2650
42.9k
    UINT64_C(1174405133), // TRUNC_W_S
2651
42.9k
    UINT64_C(1409297211), // TRUNC_W_S_MM
2652
42.9k
    UINT64_C(1409297211), // TRUNC_W_S_MMR6
2653
42.9k
    UINT64_C(67829760), // TTLTIU
2654
42.9k
    UINT64_C(27), // UDIV
2655
42.9k
    UINT64_C(47932),  // UDIV_MM
2656
42.9k
    UINT64_C(1879048209), // V3MULU
2657
42.9k
    UINT64_C(1879048208), // VMM0
2658
42.9k
    UINT64_C(1879048207), // VMULU
2659
42.9k
    UINT64_C(2013265941), // VSHF_B
2660
42.9k
    UINT64_C(2019557397), // VSHF_D
2661
42.9k
    UINT64_C(2015363093), // VSHF_H
2662
42.9k
    UINT64_C(2017460245), // VSHF_W
2663
42.9k
    UINT64_C(1107296288), // WAIT
2664
42.9k
    UINT64_C(37756),  // WAIT_MM
2665
42.9k
    UINT64_C(37756),  // WAIT_MMR6
2666
42.9k
    UINT64_C(2080376056), // WRDSP
2667
42.9k
    UINT64_C(5756), // WRDSP_MM
2668
42.9k
    UINT64_C(61820),  // WRPGPR_MMR6
2669
42.9k
    UINT64_C(2080374944), // WSBH
2670
42.9k
    UINT64_C(31548),  // WSBH_MM
2671
42.9k
    UINT64_C(31548),  // WSBH_MMR6
2672
42.9k
    UINT64_C(38), // XOR
2673
42.9k
    UINT64_C(17472),  // XOR16_MM
2674
42.9k
    UINT64_C(17416),  // XOR16_MMR6
2675
42.9k
    UINT64_C(38), // XOR64
2676
42.9k
    UINT64_C(2063597568), // XORI_B
2677
42.9k
    UINT64_C(1879048192), // XORI_MMR6
2678
42.9k
    UINT64_C(784),  // XOR_MM
2679
42.9k
    UINT64_C(784),  // XOR_MMR6
2680
42.9k
    UINT64_C(2019557406), // XOR_V
2681
42.9k
    UINT64_C(939524096),  // XORi
2682
42.9k
    UINT64_C(939524096),  // XORi64
2683
42.9k
    UINT64_C(1879048192), // XORi_MM
2684
42.9k
    UINT64_C(59406),  // XorRxRxRy16
2685
42.9k
    UINT64_C(2080374793), // YIELD
2686
42.9k
    UINT64_C(0)
2687
42.9k
  };
2688
42.9k
  const unsigned opcode = MI.getOpcode();
2689
42.9k
  uint64_t Value = InstBits[opcode];
2690
42.9k
  uint64_t op = 0;
2691
42.9k
  (void)op;  // suppress warning
2692
42.9k
  switch (opcode) {
2693
42.9k
    case Mips::Break16:
2694
195
    case Mips::DERET:
2695
195
    case Mips::DERET_MM:
2696
195
    case Mips::DERET_MMR6:
2697
195
    case Mips::EHB:
2698
195
    case Mips::EHB_MM:
2699
195
    case Mips::EHB_MMR6:
2700
195
    case Mips::ERET:
2701
195
    case Mips::ERETNC:
2702
195
    case Mips::ERETNC_MMR6:
2703
195
    case Mips::ERET_MM:
2704
195
    case Mips::ERET_MMR6:
2705
195
    case Mips::JrRa16:
2706
195
    case Mips::JrcRa16:
2707
195
    case Mips::PAUSE:
2708
195
    case Mips::PAUSE_MM:
2709
195
    case Mips::PAUSE_MMR6:
2710
195
    case Mips::Restore16:
2711
195
    case Mips::RestoreX16:
2712
195
    case Mips::SSNOP:
2713
195
    case Mips::SSNOP_MM:
2714
195
    case Mips::SSNOP_MMR6:
2715
195
    case Mips::Save16:
2716
195
    case Mips::SaveX16:
2717
195
    case Mips::TLBGINV:
2718
195
    case Mips::TLBGINVF:
2719
195
    case Mips::TLBGINVF_MM:
2720
195
    case Mips::TLBGINV_MM:
2721
195
    case Mips::TLBGP:
2722
195
    case Mips::TLBGP_MM:
2723
195
    case Mips::TLBGR:
2724
195
    case Mips::TLBGR_MM:
2725
195
    case Mips::TLBGWI:
2726
195
    case Mips::TLBGWI_MM:
2727
195
    case Mips::TLBGWR:
2728
195
    case Mips::TLBGWR_MM:
2729
195
    case Mips::TLBINV:
2730
195
    case Mips::TLBINVF:
2731
195
    case Mips::TLBINVF_MMR6:
2732
195
    case Mips::TLBINV_MMR6:
2733
195
    case Mips::TLBP:
2734
195
    case Mips::TLBP_MM:
2735
195
    case Mips::TLBR:
2736
195
    case Mips::TLBR_MM:
2737
195
    case Mips::TLBWI:
2738
195
    case Mips::TLBWI_MM:
2739
195
    case Mips::TLBWR:
2740
195
    case Mips::TLBWR_MM:
2741
195
    case Mips::WAIT: {
2742
195
      break;
2743
195
    }
2744
195
    case Mips::MTHLIP:
2745
4
    case Mips::SHILOV: {
2746
4
      // op: ac
2747
4
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2748
4
      Value |= (op & UINT64_C(3)) << 11;
2749
4
      // op: rs
2750
4
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
2751
4
      Value |= (op & UINT64_C(31)) << 21;
2752
4
      break;
2753
4
    }
2754
47
    case Mips::DPAQX_SA_W_PH:
2755
47
    case Mips::DPAQX_S_W_PH:
2756
47
    case Mips::DPAQ_SA_L_W:
2757
47
    case Mips::DPAQ_S_W_PH:
2758
47
    case Mips::DPAU_H_QBL:
2759
47
    case Mips::DPAU_H_QBR:
2760
47
    case Mips::DPAX_W_PH:
2761
47
    case Mips::DPA_W_PH:
2762
47
    case Mips::DPSQX_SA_W_PH:
2763
47
    case Mips::DPSQX_S_W_PH:
2764
47
    case Mips::DPSQ_SA_L_W:
2765
47
    case Mips::DPSQ_S_W_PH:
2766
47
    case Mips::DPSU_H_QBL:
2767
47
    case Mips::DPSU_H_QBR:
2768
47
    case Mips::DPSX_W_PH:
2769
47
    case Mips::DPS_W_PH:
2770
47
    case Mips::MADDU_DSP:
2771
47
    case Mips::MADD_DSP:
2772
47
    case Mips::MAQ_SA_W_PHL:
2773
47
    case Mips::MAQ_SA_W_PHR:
2774
47
    case Mips::MAQ_S_W_PHL:
2775
47
    case Mips::MAQ_S_W_PHR:
2776
47
    case Mips::MSUBU_DSP:
2777
47
    case Mips::MSUB_DSP:
2778
47
    case Mips::MULSAQ_S_W_PH:
2779
47
    case Mips::MULSA_W_PH:
2780
47
    case Mips::MULTU_DSP:
2781
47
    case Mips::MULT_DSP: {
2782
47
      // op: ac
2783
47
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2784
47
      Value |= (op & UINT64_C(3)) << 11;
2785
47
      // op: rs
2786
47
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
2787
47
      Value |= (op & UINT64_C(31)) << 21;
2788
47
      // op: rt
2789
47
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
2790
47
      Value |= (op & UINT64_C(31)) << 16;
2791
47
      break;
2792
47
    }
2793
47
    case Mips::SHILO: {
2794
4
      // op: ac
2795
4
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2796
4
      Value |= (op & UINT64_C(3)) << 11;
2797
4
      // op: shift
2798
4
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
2799
4
      Value |= (op & UINT64_C(63)) << 20;
2800
4
      break;
2801
47
    }
2802
54
    case Mips::CACHEE:
2803
54
    case Mips::CACHE_R6:
2804
54
    case Mips::PREFE:
2805
54
    case Mips::PREF_R6: {
2806
54
      // op: addr
2807
54
      op = getMemEncoding(MI, 0, Fixups, STI);
2808
54
      Value |= (op & UINT64_C(2031616)) << 5;
2809
54
      Value |= (op & UINT64_C(511)) << 7;
2810
54
      // op: hint
2811
54
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
2812
54
      Value |= (op & UINT64_C(31)) << 16;
2813
54
      break;
2814
54
    }
2815
54
    case Mips::SYNCI: {
2816
8
      // op: addr
2817
8
      op = getMemEncoding(MI, 0, Fixups, STI);
2818
8
      Value |= (op & UINT64_C(2031616)) << 5;
2819
8
      Value |= op & UINT64_C(65535);
2820
8
      break;
2821
54
    }
2822
54
    case Mips::CACHE:
2823
21
    case Mips::PREF: {
2824
21
      // op: addr
2825
21
      op = getMemEncoding(MI, 0, Fixups, STI);
2826
21
      Value |= (op & UINT64_C(2031616)) << 5;
2827
21
      Value |= op & UINT64_C(65535);
2828
21
      // op: hint
2829
21
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
2830
21
      Value |= (op & UINT64_C(31)) << 16;
2831
21
      break;
2832
21
    }
2833
21
    case Mips::LD_B:
2834
3
    case Mips::ST_B: {
2835
3
      // op: addr
2836
3
      op = getMemEncoding(MI, 1, Fixups, STI);
2837
3
      Value |= (op & UINT64_C(1023)) << 16;
2838
3
      Value |= (op & UINT64_C(2031616)) >> 5;
2839
3
      // op: wd
2840
3
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2841
3
      Value |= (op & UINT64_C(31)) << 6;
2842
3
      break;
2843
3
    }
2844
303
    case Mips::LBE:
2845
303
    case Mips::LBuE:
2846
303
    case Mips::LHE:
2847
303
    case Mips::LHuE:
2848
303
    case Mips::LLE:
2849
303
    case Mips::LWE:
2850
303
    case Mips::LWLE:
2851
303
    case Mips::LWRE:
2852
303
    case Mips::SBE:
2853
303
    case Mips::SHE:
2854
303
    case Mips::SWE:
2855
303
    case Mips::SWLE:
2856
303
    case Mips::SWRE: {
2857
303
      // op: addr
2858
303
      op = getMemEncoding(MI, 1, Fixups, STI);
2859
303
      Value |= (op & UINT64_C(2031616)) << 5;
2860
303
      Value |= (op & UINT64_C(511)) << 7;
2861
303
      // op: hint
2862
303
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2863
303
      Value |= (op & UINT64_C(31)) << 16;
2864
303
      break;
2865
303
    }
2866
303
    case Mips::SCE: {
2867
25
      // op: addr
2868
25
      op = getMemEncoding(MI, 2, Fixups, STI);
2869
25
      Value |= (op & UINT64_C(2031616)) << 5;
2870
25
      Value |= (op & UINT64_C(511)) << 7;
2871
25
      // op: hint
2872
25
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2873
25
      Value |= (op & UINT64_C(31)) << 16;
2874
25
      break;
2875
303
    }
2876
303
    case Mips::LD_H:
2877
5
    case Mips::ST_H: {
2878
5
      // op: addr
2879
5
      op = getMemEncoding<1>(MI, 1, Fixups, STI);
2880
5
      Value |= (op & UINT64_C(1023)) << 16;
2881
5
      Value |= (op & UINT64_C(2031616)) >> 5;
2882
5
      // op: wd
2883
5
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2884
5
      Value |= (op & UINT64_C(31)) << 6;
2885
5
      break;
2886
5
    }
2887
6
    case Mips::LD_W:
2888
6
    case Mips::ST_W: {
2889
6
      // op: addr
2890
6
      op = getMemEncoding<2>(MI, 1, Fixups, STI);
2891
6
      Value |= (op & UINT64_C(1023)) << 16;
2892
6
      Value |= (op & UINT64_C(2031616)) >> 5;
2893
6
      // op: wd
2894
6
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2895
6
      Value |= (op & UINT64_C(31)) << 6;
2896
6
      break;
2897
6
    }
2898
9
    case Mips::LD_D:
2899
9
    case Mips::ST_D: {
2900
9
      // op: addr
2901
9
      op = getMemEncoding<3>(MI, 1, Fixups, STI);
2902
9
      Value |= (op & UINT64_C(1023)) << 16;
2903
9
      Value |= (op & UINT64_C(2031616)) >> 5;
2904
9
      // op: wd
2905
9
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2906
9
      Value |= (op & UINT64_C(31)) << 6;
2907
9
      break;
2908
9
    }
2909
9
    case Mips::CACHE_MM:
2910
8
    case Mips::CACHE_MMR6:
2911
8
    case Mips::PREF_MM:
2912
8
    case Mips::PREF_MMR6: {
2913
8
      // op: addr
2914
8
      op = getMemEncodingMMImm12(MI, 0, Fixups, STI);
2915
8
      Value |= op & UINT64_C(2031616);
2916
8
      Value |= op & UINT64_C(4095);
2917
8
      // op: hint
2918
8
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
2919
8
      Value |= (op & UINT64_C(31)) << 21;
2920
8
      break;
2921
8
    }
2922
8
    case Mips::SYNCI_MM:
2923
2
    case Mips::SYNCI_MMR6: {
2924
2
      // op: addr
2925
2
      op = getMemEncodingMMImm16(MI, 0, Fixups, STI);
2926
2
      Value |= op & UINT64_C(2097151);
2927
2
      break;
2928
2
    }
2929
2
    case Mips::LBU_MMR6:
2930
2
    case Mips::LB_MMR6: {
2931
2
      // op: addr
2932
2
      op = getMemEncodingMMImm16(MI, 1, Fixups, STI);
2933
2
      Value |= op & UINT64_C(2097151);
2934
2
      // op: rt
2935
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2936
2
      Value |= (op & UINT64_C(31)) << 21;
2937
2
      break;
2938
2
    }
2939
12
    case Mips::CACHEE_MM:
2940
12
    case Mips::PREFE_MM: {
2941
12
      // op: addr
2942
12
      op = getMemEncodingMMImm9(MI, 0, Fixups, STI);
2943
12
      Value |= op & UINT64_C(2031616);
2944
12
      Value |= op & UINT64_C(511);
2945
12
      // op: hint
2946
12
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
2947
12
      Value |= (op & UINT64_C(31)) << 21;
2948
12
      break;
2949
12
    }
2950
12
    case Mips::HYPCALL: {
2951
7
      // op: code_
2952
7
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2953
7
      Value |= (op & UINT64_C(1023)) << 11;
2954
7
      break;
2955
12
    }
2956
22
    case Mips::HYPCALL_MM:
2957
22
    case Mips::SDBBP_MM:
2958
22
    case Mips::SDBBP_MMR6:
2959
22
    case Mips::SYSCALL_MM:
2960
22
    case Mips::WAIT_MM:
2961
22
    case Mips::WAIT_MMR6: {
2962
22
      // op: code_
2963
22
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2964
22
      Value |= (op & UINT64_C(1023)) << 16;
2965
22
      break;
2966
22
    }
2967
53
    case Mips::SDBBP:
2968
53
    case Mips::SDBBP_R6:
2969
53
    case Mips::SYSCALL: {
2970
53
      // op: code_
2971
53
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2972
53
      Value |= (op & UINT64_C(1048575)) << 6;
2973
53
      break;
2974
53
    }
2975
53
    case Mips::BREAK16_MMR6:
2976
2
    case Mips::SDBBP16_MMR6: {
2977
2
      // op: code_
2978
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2979
2
      Value |= (op & UINT64_C(15)) << 6;
2980
2
      break;
2981
2
    }
2982
2
    case Mips::SIGRIE_MMR6: {
2983
2
      // op: code_
2984
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2985
2
      Value |= (op & UINT64_C(65535)) << 6;
2986
2
      break;
2987
2
    }
2988
6
    case Mips::BREAK16_MM:
2989
6
    case Mips::SDBBP16_MM: {
2990
6
      // op: code_
2991
6
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2992
6
      Value |= op & UINT64_C(15);
2993
6
      break;
2994
6
    }
2995
6
    case Mips::SIGRIE: {
2996
4
      // op: code_
2997
4
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2998
4
      Value |= op & UINT64_C(65535);
2999
4
      break;
3000
6
    }
3001
142
    case Mips::BREAK:
3002
142
    case Mips::BREAK_MM:
3003
142
    case Mips::BREAK_MMR6: {
3004
142
      // op: code_1
3005
142
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3006
142
      Value |= (op & UINT64_C(1023)) << 16;
3007
142
      // op: code_2
3008
142
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3009
142
      Value |= (op & UINT64_C(1023)) << 6;
3010
142
      break;
3011
142
    }
3012
142
    case Mips::BC2EQZ:
3013
8
    case Mips::BC2NEZ: {
3014
8
      // op: ct
3015
8
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3016
8
      Value |= (op & UINT64_C(31)) << 16;
3017
8
      // op: offset
3018
8
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
3019
8
      Value |= op & UINT64_C(65535);
3020
8
      break;
3021
8
    }
3022
8
    case Mips::MOVEP_MMR6: {
3023
1
      // op: dst_regs
3024
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3025
1
      Value |= (op & UINT64_C(7)) << 7;
3026
1
      // op: rt
3027
1
      op = getMovePRegSingleOpValue(MI, 3, Fixups, STI);
3028
1
      Value |= (op & UINT64_C(7)) << 4;
3029
1
      // op: rs
3030
1
      op = getMovePRegSingleOpValue(MI, 2, Fixups, STI);
3031
1
      Value |= (op & UINT64_C(4)) << 1;
3032
1
      Value |= op & UINT64_C(3);
3033
1
      break;
3034
8
    }
3035
8
    case Mips::MOVEP_MM: {
3036
3
      // op: dst_regs
3037
3
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3038
3
      Value |= (op & UINT64_C(7)) << 7;
3039
3
      // op: rt
3040
3
      op = getMovePRegSingleOpValue(MI, 3, Fixups, STI);
3041
3
      Value |= (op & UINT64_C(7)) << 4;
3042
3
      // op: rs
3043
3
      op = getMovePRegSingleOpValue(MI, 2, Fixups, STI);
3044
3
      Value |= (op & UINT64_C(7)) << 1;
3045
3
      break;
3046
8
    }
3047
146
    case Mips::BC1F:
3048
146
    case Mips::BC1FL:
3049
146
    case Mips::BC1T:
3050
146
    case Mips::BC1TL: {
3051
146
      // op: fcc
3052
146
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3053
146
      Value |= (op & UINT64_C(7)) << 18;
3054
146
      // op: offset
3055
146
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
3056
146
      Value |= op & UINT64_C(65535);
3057
146
      break;
3058
146
    }
3059
146
    case Mips::BC1F_MM:
3060
9
    case Mips::BC1T_MM: {
3061
9
      // op: fcc
3062
9
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3063
9
      Value |= (op & UINT64_C(7)) << 18;
3064
9
      // op: offset
3065
9
      op = getBranchTargetOpValueMM(MI, 1, Fixups, STI);
3066
9
      Value |= op & UINT64_C(65535);
3067
9
      break;
3068
9
    }
3069
9
    case Mips::LUXC1_MM:
3070
2
    case Mips::LWXC1_MM: {
3071
2
      // op: fd
3072
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3073
2
      Value |= (op & UINT64_C(31)) << 11;
3074
2
      // op: base
3075
2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3076
2
      Value |= (op & UINT64_C(31)) << 16;
3077
2
      // op: index
3078
2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3079
2
      Value |= (op & UINT64_C(31)) << 21;
3080
2
      break;
3081
2
    }
3082
8
    case Mips::MOVN_I_D32_MM:
3083
8
    case Mips::MOVN_I_S_MM:
3084
8
    case Mips::MOVZ_I_D32_MM:
3085
8
    case Mips::MOVZ_I_S_MM: {
3086
8
      // op: fd
3087
8
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3088
8
      Value |= (op & UINT64_C(31)) << 11;
3089
8
      // op: fs
3090
8
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3091
8
      Value |= (op & UINT64_C(31)) << 16;
3092
8
      // op: rt
3093
8
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3094
8
      Value |= (op & UINT64_C(31)) << 21;
3095
8
      break;
3096
8
    }
3097
89
    case Mips::CEIL_W_MM:
3098
89
    case Mips::CEIL_W_S_MM:
3099
89
    case Mips::CVT_D32_S_MM:
3100
89
    case Mips::CVT_D32_W_MM:
3101
89
    case Mips::CVT_D64_S_MM:
3102
89
    case Mips::CVT_D64_W_MM:
3103
89
    case Mips::CVT_L_D64_MM:
3104
89
    case Mips::CVT_L_S_MM:
3105
89
    case Mips::CVT_S_D32_MM:
3106
89
    case Mips::CVT_S_D64_MM:
3107
89
    case Mips::CVT_S_W_MM:
3108
89
    case Mips::CVT_W_D32_MM:
3109
89
    case Mips::CVT_W_D64_MM:
3110
89
    case Mips::CVT_W_S_MM:
3111
89
    case Mips::FABS_D32_MM:
3112
89
    case Mips::FABS_D64_MM:
3113
89
    case Mips::FABS_S_MM:
3114
89
    case Mips::FLOOR_W_MM:
3115
89
    case Mips::FLOOR_W_S_MM:
3116
89
    case Mips::FMOV_D32_MM:
3117
89
    case Mips::FMOV_D64_MM:
3118
89
    case Mips::FMOV_S_MM:
3119
89
    case Mips::FNEG_D32_MM:
3120
89
    case Mips::FNEG_D64_MM:
3121
89
    case Mips::FNEG_S_MM:
3122
89
    case Mips::FSQRT_D32_MM:
3123
89
    case Mips::FSQRT_D64_MM:
3124
89
    case Mips::FSQRT_S_MM:
3125
89
    case Mips::RECIP_D32_MM:
3126
89
    case Mips::RECIP_D64_MM:
3127
89
    case Mips::RECIP_S_MM:
3128
89
    case Mips::ROUND_W_MM:
3129
89
    case Mips::ROUND_W_S_MM:
3130
89
    case Mips::RSQRT_D32_MM:
3131
89
    case Mips::RSQRT_D64_MM:
3132
89
    case Mips::RSQRT_S_MM:
3133
89
    case Mips::TRUNC_W_MM:
3134
89
    case Mips::TRUNC_W_S_MM: {
3135
89
      // op: fd
3136
89
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3137
89
      Value |= (op & UINT64_C(31)) << 21;
3138
89
      // op: fs
3139
89
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3140
89
      Value |= (op & UINT64_C(31)) << 16;
3141
89
      break;
3142
89
    }
3143
89
    case Mips::MOVF_D32_MM:
3144
9
    case Mips::MOVF_S_MM:
3145
9
    case Mips::MOVT_D32_MM:
3146
9
    case Mips::MOVT_S_MM: {
3147
9
      // op: fd
3148
9
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3149
9
      Value |= (op & UINT64_C(31)) << 21;
3150
9
      // op: fs
3151
9
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3152
9
      Value |= (op & UINT64_C(31)) << 16;
3153
9
      // op: fcc
3154
9
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3155
9
      Value |= (op & UINT64_C(7)) << 13;
3156
9
      break;
3157
9
    }
3158
36
    case Mips::LDXC1:
3159
36
    case Mips::LDXC164:
3160
36
    case Mips::LUXC1:
3161
36
    case Mips::LUXC164:
3162
36
    case Mips::LWXC1: {
3163
36
      // op: fd
3164
36
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3165
36
      Value |= (op & UINT64_C(31)) << 6;
3166
36
      // op: base
3167
36
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3168
36
      Value |= (op & UINT64_C(31)) << 21;
3169
36
      // op: index
3170
36
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3171
36
      Value |= (op & UINT64_C(31)) << 16;
3172
36
      break;
3173
36
    }
3174
60
    case Mips::MADD_D32:
3175
60
    case Mips::MADD_D64:
3176
60
    case Mips::MADD_S:
3177
60
    case Mips::MSUB_D32:
3178
60
    case Mips::MSUB_D64:
3179
60
    case Mips::MSUB_S:
3180
60
    case Mips::NMADD_D32:
3181
60
    case Mips::NMADD_D64:
3182
60
    case Mips::NMADD_S:
3183
60
    case Mips::NMSUB_D32:
3184
60
    case Mips::NMSUB_D64:
3185
60
    case Mips::NMSUB_S: {
3186
60
      // op: fd
3187
60
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3188
60
      Value |= (op & UINT64_C(31)) << 6;
3189
60
      // op: fr
3190
60
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3191
60
      Value |= (op & UINT64_C(31)) << 21;
3192
60
      // op: fs
3193
60
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3194
60
      Value |= (op & UINT64_C(31)) << 11;
3195
60
      // op: ft
3196
60
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
3197
60
      Value |= (op & UINT64_C(31)) << 16;
3198
60
      break;
3199
60
    }
3200
554
    case Mips::CEIL_L_D64:
3201
554
    case Mips::CEIL_L_S:
3202
554
    case Mips::CEIL_W_D32:
3203
554
    case Mips::CEIL_W_D64:
3204
554
    case Mips::CEIL_W_S:
3205
554
    case Mips::CVT_D32_S:
3206
554
    case Mips::CVT_D32_W:
3207
554
    case Mips::CVT_D64_L:
3208
554
    case Mips::CVT_D64_S:
3209
554
    case Mips::CVT_D64_W:
3210
554
    case Mips::CVT_L_D64:
3211
554
    case Mips::CVT_L_S:
3212
554
    case Mips::CVT_S_D32:
3213
554
    case Mips::CVT_S_D64:
3214
554
    case Mips::CVT_S_L:
3215
554
    case Mips::CVT_S_PL64:
3216
554
    case Mips::CVT_S_PU64:
3217
554
    case Mips::CVT_S_W:
3218
554
    case Mips::CVT_W_D32:
3219
554
    case Mips::CVT_W_D64:
3220
554
    case Mips::CVT_W_S:
3221
554
    case Mips::FABS_D32:
3222
554
    case Mips::FABS_D64:
3223
554
    case Mips::FABS_S:
3224
554
    case Mips::FLOOR_L_D64:
3225
554
    case Mips::FLOOR_L_S:
3226
554
    case Mips::FLOOR_W_D32:
3227
554
    case Mips::FLOOR_W_D64:
3228
554
    case Mips::FLOOR_W_S:
3229
554
    case Mips::FMOV_D32:
3230
554
    case Mips::FMOV_D64:
3231
554
    case Mips::FMOV_S:
3232
554
    case Mips::FNEG_D32:
3233
554
    case Mips::FNEG_D64:
3234
554
    case Mips::FNEG_S:
3235
554
    case Mips::FSQRT_D32:
3236
554
    case Mips::FSQRT_D64:
3237
554
    case Mips::FSQRT_S:
3238
554
    case Mips::RECIP_D32:
3239
554
    case Mips::RECIP_D64:
3240
554
    case Mips::RECIP_S:
3241
554
    case Mips::ROUND_L_D64:
3242
554
    case Mips::ROUND_L_S:
3243
554
    case Mips::ROUND_W_D32:
3244
554
    case Mips::ROUND_W_D64:
3245
554
    case Mips::ROUND_W_S:
3246
554
    case Mips::RSQRT_D32:
3247
554
    case Mips::RSQRT_D64:
3248
554
    case Mips::RSQRT_S:
3249
554
    case Mips::TRUNC_L_D64:
3250
554
    case Mips::TRUNC_L_S:
3251
554
    case Mips::TRUNC_W_D32:
3252
554
    case Mips::TRUNC_W_D64:
3253
554
    case Mips::TRUNC_W_S: {
3254
554
      // op: fd
3255
554
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3256
554
      Value |= (op & UINT64_C(31)) << 6;
3257
554
      // op: fs
3258
554
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3259
554
      Value |= (op & UINT64_C(31)) << 11;
3260
554
      break;
3261
554
    }
3262
554
    case Mips::MOVF_D32:
3263
44
    case Mips::MOVF_D64:
3264
44
    case Mips::MOVF_S:
3265
44
    case Mips::MOVT_D32:
3266
44
    case Mips::MOVT_D64:
3267
44
    case Mips::MOVT_S: {
3268
44
      // op: fd
3269
44
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3270
44
      Value |= (op & UINT64_C(31)) << 6;
3271
44
      // op: fs
3272
44
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3273
44
      Value |= (op & UINT64_C(31)) << 11;
3274
44
      // op: fcc
3275
44
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3276
44
      Value |= (op & UINT64_C(7)) << 18;
3277
44
      break;
3278
44
    }
3279
205
    case Mips::CMP_EQ_D:
3280
205
    case Mips::CMP_EQ_S:
3281
205
    case Mips::CMP_F_D:
3282
205
    case Mips::CMP_F_S:
3283
205
    case Mips::CMP_LE_D:
3284
205
    case Mips::CMP_LE_S:
3285
205
    case Mips::CMP_LT_D:
3286
205
    case Mips::CMP_LT_S:
3287
205
    case Mips::CMP_SAF_D:
3288
205
    case Mips::CMP_SAF_S:
3289
205
    case Mips::CMP_SEQ_D:
3290
205
    case Mips::CMP_SEQ_S:
3291
205
    case Mips::CMP_SLE_D:
3292
205
    case Mips::CMP_SLE_S:
3293
205
    case Mips::CMP_SLT_D:
3294
205
    case Mips::CMP_SLT_S:
3295
205
    case Mips::CMP_SUEQ_D:
3296
205
    case Mips::CMP_SUEQ_S:
3297
205
    case Mips::CMP_SULE_D:
3298
205
    case Mips::CMP_SULE_S:
3299
205
    case Mips::CMP_SULT_D:
3300
205
    case Mips::CMP_SULT_S:
3301
205
    case Mips::CMP_SUN_D:
3302
205
    case Mips::CMP_SUN_S:
3303
205
    case Mips::CMP_UEQ_D:
3304
205
    case Mips::CMP_UEQ_S:
3305
205
    case Mips::CMP_ULE_D:
3306
205
    case Mips::CMP_ULE_S:
3307
205
    case Mips::CMP_ULT_D:
3308
205
    case Mips::CMP_ULT_S:
3309
205
    case Mips::CMP_UN_D:
3310
205
    case Mips::CMP_UN_S:
3311
205
    case Mips::CVT_PS_S64:
3312
205
    case Mips::FADD_D32:
3313
205
    case Mips::FADD_D64:
3314
205
    case Mips::FADD_S:
3315
205
    case Mips::FDIV_D32:
3316
205
    case Mips::FDIV_D64:
3317
205
    case Mips::FDIV_S:
3318
205
    case Mips::FMUL_D32:
3319
205
    case Mips::FMUL_D64:
3320
205
    case Mips::FMUL_S:
3321
205
    case Mips::FSUB_D32:
3322
205
    case Mips::FSUB_D64:
3323
205
    case Mips::FSUB_S:
3324
205
    case Mips::PLL_PS64:
3325
205
    case Mips::PLU_PS64: {
3326
205
      // op: fd
3327
205
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3328
205
      Value |= (op & UINT64_C(31)) << 6;
3329
205
      // op: fs
3330
205
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3331
205
      Value |= (op & UINT64_C(31)) << 11;
3332
205
      // op: ft
3333
205
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3334
205
      Value |= (op & UINT64_C(31)) << 16;
3335
205
      break;
3336
205
    }
3337
205
    case Mips::MOVN_I64_D64:
3338
40
    case Mips::MOVN_I64_S:
3339
40
    case Mips::MOVN_I_D32:
3340
40
    case Mips::MOVN_I_D64:
3341
40
    case Mips::MOVN_I_S:
3342
40
    case Mips::MOVZ_I64_D64:
3343
40
    case Mips::MOVZ_I64_S:
3344
40
    case Mips::MOVZ_I_D32:
3345
40
    case Mips::MOVZ_I_D64:
3346
40
    case Mips::MOVZ_I_S: {
3347
40
      // op: fd
3348
40
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3349
40
      Value |= (op & UINT64_C(31)) << 6;
3350
40
      // op: fs
3351
40
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3352
40
      Value |= (op & UINT64_C(31)) << 11;
3353
40
      // op: rt
3354
40
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3355
40
      Value |= (op & UINT64_C(31)) << 16;
3356
40
      break;
3357
40
    }
3358
40
    case Mips::SUXC1_MM:
3359
2
    case Mips::SWXC1_MM: {
3360
2
      // op: fs
3361
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3362
2
      Value |= (op & UINT64_C(31)) << 11;
3363
2
      // op: base
3364
2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3365
2
      Value |= (op & UINT64_C(31)) << 16;
3366
2
      // op: index
3367
2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3368
2
      Value |= (op & UINT64_C(31)) << 21;
3369
2
      break;
3370
2
    }
3371
31
    case Mips::SDXC1:
3372
31
    case Mips::SDXC164:
3373
31
    case Mips::SUXC1:
3374
31
    case Mips::SUXC164:
3375
31
    case Mips::SWXC1: {
3376
31
      // op: fs
3377
31
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3378
31
      Value |= (op & UINT64_C(31)) << 11;
3379
31
      // op: base
3380
31
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3381
31
      Value |= (op & UINT64_C(31)) << 21;
3382
31
      // op: index
3383
31
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3384
31
      Value |= (op & UINT64_C(31)) << 16;
3385
31
      break;
3386
31
    }
3387
31
    case Mips::FCMP_D32:
3388
0
    case Mips::FCMP_D64:
3389
0
    case Mips::FCMP_S32: {
3390
0
      // op: fs
3391
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3392
0
      Value |= (op & UINT64_C(31)) << 11;
3393
0
      // op: ft
3394
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3395
0
      Value |= (op & UINT64_C(31)) << 16;
3396
0
      // op: cond
3397
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3398
0
      Value |= op & UINT64_C(15);
3399
0
      break;
3400
0
    }
3401
2
    case Mips::FCMP_D32_MM:
3402
2
    case Mips::FCMP_S32_MM: {
3403
2
      // op: fs
3404
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3405
2
      Value |= (op & UINT64_C(31)) << 16;
3406
2
      // op: ft
3407
2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3408
2
      Value |= (op & UINT64_C(31)) << 21;
3409
2
      // op: cond
3410
2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3411
2
      Value |= (op & UINT64_C(15)) << 6;
3412
2
      break;
3413
2
    }
3414
8
    case Mips::CLASS_D:
3415
8
    case Mips::CLASS_S:
3416
8
    case Mips::RINT_D:
3417
8
    case Mips::RINT_S: {
3418
8
      // op: fs
3419
8
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3420
8
      Value |= (op & UINT64_C(31)) << 11;
3421
8
      // op: fd
3422
8
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3423
8
      Value |= (op & UINT64_C(31)) << 6;
3424
8
      break;
3425
8
    }
3426
396
    case Mips::C_EQ_D32:
3427
396
    case Mips::C_EQ_D64:
3428
396
    case Mips::C_EQ_S:
3429
396
    case Mips::C_F_D32:
3430
396
    case Mips::C_F_D64:
3431
396
    case Mips::C_F_S:
3432
396
    case Mips::C_LE_D32:
3433
396
    case Mips::C_LE_D64:
3434
396
    case Mips::C_LE_S:
3435
396
    case Mips::C_LT_D32:
3436
396
    case Mips::C_LT_D64:
3437
396
    case Mips::C_LT_S:
3438
396
    case Mips::C_NGE_D32:
3439
396
    case Mips::C_NGE_D64:
3440
396
    case Mips::C_NGE_S:
3441
396
    case Mips::C_NGLE_D32:
3442
396
    case Mips::C_NGLE_D64:
3443
396
    case Mips::C_NGLE_S:
3444
396
    case Mips::C_NGL_D32:
3445
396
    case Mips::C_NGL_D64:
3446
396
    case Mips::C_NGL_S:
3447
396
    case Mips::C_NGT_D32:
3448
396
    case Mips::C_NGT_D64:
3449
396
    case Mips::C_NGT_S:
3450
396
    case Mips::C_OLE_D32:
3451
396
    case Mips::C_OLE_D64:
3452
396
    case Mips::C_OLE_S:
3453
396
    case Mips::C_OLT_D32:
3454
396
    case Mips::C_OLT_D64:
3455
396
    case Mips::C_OLT_S:
3456
396
    case Mips::C_SEQ_D32:
3457
396
    case Mips::C_SEQ_D64:
3458
396
    case Mips::C_SEQ_S:
3459
396
    case Mips::C_SF_D32:
3460
396
    case Mips::C_SF_D64:
3461
396
    case Mips::C_SF_S:
3462
396
    case Mips::C_UEQ_D32:
3463
396
    case Mips::C_UEQ_D64:
3464
396
    case Mips::C_UEQ_S:
3465
396
    case Mips::C_ULE_D32:
3466
396
    case Mips::C_ULE_D64:
3467
396
    case Mips::C_ULE_S:
3468
396
    case Mips::C_ULT_D32:
3469
396
    case Mips::C_ULT_D64:
3470
396
    case Mips::C_ULT_S:
3471
396
    case Mips::C_UN_D32:
3472
396
    case Mips::C_UN_D64:
3473
396
    case Mips::C_UN_S: {
3474
396
      // op: fs
3475
396
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3476
396
      Value |= (op & UINT64_C(31)) << 11;
3477
396
      // op: ft
3478
396
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3479
396
      Value |= (op & UINT64_C(31)) << 16;
3480
396
      // op: fcc
3481
396
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3482
396
      Value |= (op & UINT64_C(7)) << 8;
3483
396
      break;
3484
396
    }
3485
396
    case Mips::C_EQ_D32_MM:
3486
96
    case Mips::C_EQ_D64_MM:
3487
96
    case Mips::C_EQ_S_MM:
3488
96
    case Mips::C_F_D32_MM:
3489
96
    case Mips::C_F_D64_MM:
3490
96
    case Mips::C_F_S_MM:
3491
96
    case Mips::C_LE_D32_MM:
3492
96
    case Mips::C_LE_D64_MM:
3493
96
    case Mips::C_LE_S_MM:
3494
96
    case Mips::C_LT_D32_MM:
3495
96
    case Mips::C_LT_D64_MM:
3496
96
    case Mips::C_LT_S_MM:
3497
96
    case Mips::C_NGE_D32_MM:
3498
96
    case Mips::C_NGE_D64_MM:
3499
96
    case Mips::C_NGE_S_MM:
3500
96
    case Mips::C_NGLE_D32_MM:
3501
96
    case Mips::C_NGLE_D64_MM:
3502
96
    case Mips::C_NGLE_S_MM:
3503
96
    case Mips::C_NGL_D32_MM:
3504
96
    case Mips::C_NGL_D64_MM:
3505
96
    case Mips::C_NGL_S_MM:
3506
96
    case Mips::C_NGT_D32_MM:
3507
96
    case Mips::C_NGT_D64_MM:
3508
96
    case Mips::C_NGT_S_MM:
3509
96
    case Mips::C_OLE_D32_MM:
3510
96
    case Mips::C_OLE_D64_MM:
3511
96
    case Mips::C_OLE_S_MM:
3512
96
    case Mips::C_OLT_D32_MM:
3513
96
    case Mips::C_OLT_D64_MM:
3514
96
    case Mips::C_OLT_S_MM:
3515
96
    case Mips::C_SEQ_D32_MM:
3516
96
    case Mips::C_SEQ_D64_MM:
3517
96
    case Mips::C_SEQ_S_MM:
3518
96
    case Mips::C_SF_D32_MM:
3519
96
    case Mips::C_SF_D64_MM:
3520
96
    case Mips::C_SF_S_MM:
3521
96
    case Mips::C_UEQ_D32_MM:
3522
96
    case Mips::C_UEQ_D64_MM:
3523
96
    case Mips::C_UEQ_S_MM:
3524
96
    case Mips::C_ULE_D32_MM:
3525
96
    case Mips::C_ULE_D64_MM:
3526
96
    case Mips::C_ULE_S_MM:
3527
96
    case Mips::C_ULT_D32_MM:
3528
96
    case Mips::C_ULT_D64_MM:
3529
96
    case Mips::C_ULT_S_MM:
3530
96
    case Mips::C_UN_D32_MM:
3531
96
    case Mips::C_UN_D64_MM:
3532
96
    case Mips::C_UN_S_MM: {
3533
96
      // op: fs
3534
96
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3535
96
      Value |= (op & UINT64_C(31)) << 16;
3536
96
      // op: ft
3537
96
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3538
96
      Value |= (op & UINT64_C(31)) << 21;
3539
96
      // op: fcc
3540
96
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3541
96
      Value |= (op & UINT64_C(7)) << 13;
3542
96
      break;
3543
96
    }
3544
96
    case Mips::CLASS_D_MMR6:
3545
4
    case Mips::CLASS_S_MMR6:
3546
4
    case Mips::RINT_D_MMR6:
3547
4
    case Mips::RINT_S_MMR6: {
3548
4
      // op: fs
3549
4
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3550
4
      Value |= (op & UINT64_C(31)) << 21;
3551
4
      // op: fd
3552
4
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3553
4
      Value |= (op & UINT64_C(31)) << 16;
3554
4
      break;
3555
4
    }
3556
8
    case Mips::BC1EQZ:
3557
8
    case Mips::BC1NEZ: {
3558
8
      // op: ft
3559
8
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3560
8
      Value |= (op & UINT64_C(31)) << 16;
3561
8
      // op: offset
3562
8
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
3563
8
      Value |= op & UINT64_C(65535);
3564
8
      break;
3565
8
    }
3566
16
    case Mips::LDC1_D64_MMR6:
3567
16
    case Mips::SDC1_D64_MMR6: {
3568
16
      // op: ft
3569
16
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3570
16
      Value |= (op & UINT64_C(31)) << 21;
3571
16
      // op: addr
3572
16
      op = getMemEncodingMMImm16(MI, 1, Fixups, STI);
3573
16
      Value |= op & UINT64_C(2097151);
3574
16
      break;
3575
16
    }
3576
22
    case Mips::CEIL_L_D_MMR6:
3577
22
    case Mips::CEIL_L_S_MMR6:
3578
22
    case Mips::CEIL_W_D_MMR6:
3579
22
    case Mips::CEIL_W_S_MMR6:
3580
22
    case Mips::CVT_D_L_MMR6:
3581
22
    case Mips::CVT_L_D_MMR6:
3582
22
    case Mips::CVT_L_S_MMR6:
3583
22
    case Mips::CVT_S_L_MMR6:
3584
22
    case Mips::CVT_S_W_MMR6:
3585
22
    case Mips::CVT_W_S_MMR6:
3586
22
    case Mips::FLOOR_L_D_MMR6:
3587
22
    case Mips::FLOOR_L_S_MMR6:
3588
22
    case Mips::FLOOR_W_D_MMR6:
3589
22
    case Mips::FLOOR_W_S_MMR6:
3590
22
    case Mips::FMOV_S_MMR6:
3591
22
    case Mips::FNEG_S_MMR6:
3592
22
    case Mips::ROUND_L_D_MMR6:
3593
22
    case Mips::ROUND_L_S_MMR6:
3594
22
    case Mips::ROUND_W_D_MMR6:
3595
22
    case Mips::ROUND_W_S_MMR6:
3596
22
    case Mips::TRUNC_L_D_MMR6:
3597
22
    case Mips::TRUNC_L_S_MMR6:
3598
22
    case Mips::TRUNC_W_D_MMR6:
3599
22
    case Mips::TRUNC_W_S_MMR6: {
3600
22
      // op: ft
3601
22
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3602
22
      Value |= (op & UINT64_C(31)) << 21;
3603
22
      // op: fs
3604
22
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3605
22
      Value |= (op & UINT64_C(31)) << 16;
3606
22
      break;
3607
22
    }
3608
22
    case Mips::FADD_S_MMR6:
3609
4
    case Mips::FDIV_S_MMR6:
3610
4
    case Mips::FMUL_S_MMR6:
3611
4
    case Mips::FSUB_S_MMR6: {
3612
4
      // op: ft
3613
4
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3614
4
      Value |= (op & UINT64_C(31)) << 21;
3615
4
      // op: fs
3616
4
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3617
4
      Value |= (op & UINT64_C(31)) << 16;
3618
4
      // op: fd
3619
4
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3620
4
      Value |= (op & UINT64_C(31)) << 11;
3621
4
      break;
3622
4
    }
3623
24
    case Mips::MAXA_D:
3624
24
    case Mips::MAXA_S:
3625
24
    case Mips::MAX_D:
3626
24
    case Mips::MAX_S:
3627
24
    case Mips::MINA_D:
3628
24
    case Mips::MINA_S:
3629
24
    case Mips::MIN_D:
3630
24
    case Mips::MIN_S:
3631
24
    case Mips::SELEQZ_D:
3632
24
    case Mips::SELEQZ_S:
3633
24
    case Mips::SELNEZ_D:
3634
24
    case Mips::SELNEZ_S: {
3635
24
      // op: ft
3636
24
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3637
24
      Value |= (op & UINT64_C(31)) << 16;
3638
24
      // op: fs
3639
24
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3640
24
      Value |= (op & UINT64_C(31)) << 11;
3641
24
      // op: fd
3642
24
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3643
24
      Value |= (op & UINT64_C(31)) << 6;
3644
24
      break;
3645
24
    }
3646
82
    case Mips::CMP_AF_D_MMR6:
3647
82
    case Mips::CMP_AF_S_MMR6:
3648
82
    case Mips::CMP_EQ_D_MMR6:
3649
82
    case Mips::CMP_EQ_S_MMR6:
3650
82
    case Mips::CMP_LE_D_MMR6:
3651
82
    case Mips::CMP_LE_S_MMR6:
3652
82
    case Mips::CMP_LT_D_MMR6:
3653
82
    case Mips::CMP_LT_S_MMR6:
3654
82
    case Mips::CMP_SAF_D_MMR6:
3655
82
    case Mips::CMP_SAF_S_MMR6:
3656
82
    case Mips::CMP_SEQ_D_MMR6:
3657
82
    case Mips::CMP_SEQ_S_MMR6:
3658
82
    case Mips::CMP_SLE_D_MMR6:
3659
82
    case Mips::CMP_SLE_S_MMR6:
3660
82
    case Mips::CMP_SLT_D_MMR6:
3661
82
    case Mips::CMP_SLT_S_MMR6:
3662
82
    case Mips::CMP_SUEQ_D_MMR6:
3663
82
    case Mips::CMP_SUEQ_S_MMR6:
3664
82
    case Mips::CMP_SULE_D_MMR6:
3665
82
    case Mips::CMP_SULE_S_MMR6:
3666
82
    case Mips::CMP_SULT_D_MMR6:
3667
82
    case Mips::CMP_SULT_S_MMR6:
3668
82
    case Mips::CMP_SUN_D_MMR6:
3669
82
    case Mips::CMP_SUN_S_MMR6:
3670
82
    case Mips::CMP_UEQ_D_MMR6:
3671
82
    case Mips::CMP_UEQ_S_MMR6:
3672
82
    case Mips::CMP_ULE_D_MMR6:
3673
82
    case Mips::CMP_ULE_S_MMR6:
3674
82
    case Mips::CMP_ULT_D_MMR6:
3675
82
    case Mips::CMP_ULT_S_MMR6:
3676
82
    case Mips::CMP_UN_D_MMR6:
3677
82
    case Mips::CMP_UN_S_MMR6:
3678
82
    case Mips::FADD_D32_MM:
3679
82
    case Mips::FADD_D64_MM:
3680
82
    case Mips::FADD_S_MM:
3681
82
    case Mips::FDIV_D32_MM:
3682
82
    case Mips::FDIV_D64_MM:
3683
82
    case Mips::FDIV_S_MM:
3684
82
    case Mips::FMUL_D32_MM:
3685
82
    case Mips::FMUL_D64_MM:
3686
82
    case Mips::FMUL_S_MM:
3687
82
    case Mips::FSUB_D32_MM:
3688
82
    case Mips::FSUB_D64_MM:
3689
82
    case Mips::FSUB_S_MM:
3690
82
    case Mips::MAXA_D_MMR6:
3691
82
    case Mips::MAXA_S_MMR6:
3692
82
    case Mips::MAX_D_MMR6:
3693
82
    case Mips::MAX_S_MMR6:
3694
82
    case Mips::MINA_D_MMR6:
3695
82
    case Mips::MINA_S_MMR6:
3696
82
    case Mips::MIN_D_MMR6:
3697
82
    case Mips::MIN_S_MMR6:
3698
82
    case Mips::SELEQZ_D_MMR6:
3699
82
    case Mips::SELEQZ_S_MMR6:
3700
82
    case Mips::SELNEZ_D_MMR6:
3701
82
    case Mips::SELNEZ_S_MMR6: {
3702
82
      // op: ft
3703
82
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3704
82
      Value |= (op & UINT64_C(31)) << 21;
3705
82
      // op: fs
3706
82
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3707
82
      Value |= (op & UINT64_C(31)) << 16;
3708
82
      // op: fd
3709
82
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3710
82
      Value |= (op & UINT64_C(31)) << 11;
3711
82
      break;
3712
82
    }
3713
82
    case Mips::MADDF_D:
3714
12
    case Mips::MADDF_S:
3715
12
    case Mips::MSUBF_D:
3716
12
    case Mips::MSUBF_S:
3717
12
    case Mips::SEL_D:
3718
12
    case Mips::SEL_S: {
3719
12
      // op: ft
3720
12
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
3721
12
      Value |= (op & UINT64_C(31)) << 16;
3722
12
      // op: fs
3723
12
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3724
12
      Value |= (op & UINT64_C(31)) << 11;
3725
12
      // op: fd
3726
12
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3727
12
      Value |= (op & UINT64_C(31)) << 6;
3728
12
      break;
3729
12
    }
3730
12
    case Mips::MADDF_D_MMR6:
3731
7
    case Mips::MADDF_S_MMR6:
3732
7
    case Mips::MSUBF_D_MMR6:
3733
7
    case Mips::MSUBF_S_MMR6:
3734
7
    case Mips::SEL_D_MMR6:
3735
7
    case Mips::SEL_S_MMR6: {
3736
7
      // op: ft
3737
7
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
3738
7
      Value |= (op & UINT64_C(31)) << 21;
3739
7
      // op: fs
3740
7
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3741
7
      Value |= (op & UINT64_C(31)) << 16;
3742
7
      // op: fd
3743
7
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3744
7
      Value |= (op & UINT64_C(31)) << 11;
3745
7
      break;
3746
7
    }
3747
16
    case Mips::MADD_D32_MM:
3748
16
    case Mips::MADD_S_MM:
3749
16
    case Mips::MSUB_D32_MM:
3750
16
    case Mips::MSUB_S_MM:
3751
16
    case Mips::NMADD_D32_MM:
3752
16
    case Mips::NMADD_S_MM:
3753
16
    case Mips::NMSUB_D32_MM:
3754
16
    case Mips::NMSUB_S_MM: {
3755
16
      // op: ft
3756
16
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
3757
16
      Value |= (op & UINT64_C(31)) << 21;
3758
16
      // op: fs
3759
16
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3760
16
      Value |= (op & UINT64_C(31)) << 16;
3761
16
      // op: fd
3762
16
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3763
16
      Value |= (op & UINT64_C(31)) << 11;
3764
16
      // op: fr
3765
16
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3766
16
      Value |= (op & UINT64_C(31)) << 6;
3767
16
      break;
3768
16
    }
3769
44
    case Mips::ADDVI_B:
3770
44
    case Mips::ADDVI_D:
3771
44
    case Mips::ADDVI_H:
3772
44
    case Mips::ADDVI_W:
3773
44
    case Mips::CEQI_B:
3774
44
    case Mips::CEQI_D:
3775
44
    case Mips::CEQI_H:
3776
44
    case Mips::CEQI_W:
3777
44
    case Mips::CLEI_S_B:
3778
44
    case Mips::CLEI_S_D:
3779
44
    case Mips::CLEI_S_H:
3780
44
    case Mips::CLEI_S_W:
3781
44
    case Mips::CLEI_U_B:
3782
44
    case Mips::CLEI_U_D:
3783
44
    case Mips::CLEI_U_H:
3784
44
    case Mips::CLEI_U_W:
3785
44
    case Mips::CLTI_S_B:
3786
44
    case Mips::CLTI_S_D:
3787
44
    case Mips::CLTI_S_H:
3788
44
    case Mips::CLTI_S_W:
3789
44
    case Mips::CLTI_U_B:
3790
44
    case Mips::CLTI_U_D:
3791
44
    case Mips::CLTI_U_H:
3792
44
    case Mips::CLTI_U_W:
3793
44
    case Mips::MAXI_S_B:
3794
44
    case Mips::MAXI_S_D:
3795
44
    case Mips::MAXI_S_H:
3796
44
    case Mips::MAXI_S_W:
3797
44
    case Mips::MAXI_U_B:
3798
44
    case Mips::MAXI_U_D:
3799
44
    case Mips::MAXI_U_H:
3800
44
    case Mips::MAXI_U_W:
3801
44
    case Mips::MINI_S_B:
3802
44
    case Mips::MINI_S_D:
3803
44
    case Mips::MINI_S_H:
3804
44
    case Mips::MINI_S_W:
3805
44
    case Mips::MINI_U_B:
3806
44
    case Mips::MINI_U_D:
3807
44
    case Mips::MINI_U_H:
3808
44
    case Mips::MINI_U_W:
3809
44
    case Mips::SUBVI_B:
3810
44
    case Mips::SUBVI_D:
3811
44
    case Mips::SUBVI_H:
3812
44
    case Mips::SUBVI_W: {
3813
44
      // op: imm
3814
44
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3815
44
      Value |= (op & UINT64_C(31)) << 16;
3816
44
      // op: ws
3817
44
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3818
44
      Value |= (op & UINT64_C(31)) << 11;
3819
44
      // op: wd
3820
44
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3821
44
      Value |= (op & UINT64_C(31)) << 6;
3822
44
      break;
3823
44
    }
3824
44
    case Mips::ADDIUSP_MM: {
3825
24
      // op: imm
3826
24
      op = getSImm9AddiuspValue(MI, 0, Fixups, STI);
3827
24
      Value |= (op & UINT64_C(511)) << 1;
3828
24
      break;
3829
44
    }
3830
44
    case Mips::JRCADDIUSP_MMR6: {
3831
1
      // op: imm
3832
1
      op = getUImm5Lsl2Encoding(MI, 0, Fixups, STI);
3833
1
      Value |= (op & UINT64_C(31)) << 5;
3834
1
      break;
3835
44
    }
3836
44
    case Mips::JRADDIUSP: {
3837
3
      // op: imm
3838
3
      op = getUImm5Lsl2Encoding(MI, 0, Fixups, STI);
3839
3
      Value |= op & UINT64_C(31);
3840
3
      break;
3841
44
    }
3842
44
    case Mips::Bimm16: {
3843
0
      // op: imm11
3844
0
      op = getBranchTargetOpValue(MI, 0, Fixups, STI);
3845
0
      Value |= op & UINT64_C(2047);
3846
0
      break;
3847
44
    }
3848
44
    case Mips::AddiuRxRyOffMemX16: {
3849
0
      // op: imm15
3850
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3851
0
      Value |= (op & UINT64_C(2032)) << 16;
3852
0
      Value |= (op & UINT64_C(30720)) << 5;
3853
0
      Value |= op & UINT64_C(15);
3854
0
      // op: rx
3855
0
      op = getMemEncoding(MI, 1, Fixups, STI);
3856
0
      Value |= (op & UINT64_C(7)) << 8;
3857
0
      // op: ry
3858
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3859
0
      Value |= (op & UINT64_C(7)) << 5;
3860
0
      break;
3861
44
    }
3862
44
    case Mips::BimmX16: {
3863
0
      // op: imm16
3864
0
      op = getBranchTargetOpValue(MI, 0, Fixups, STI);
3865
0
      Value |= (op & UINT64_C(2016)) << 16;
3866
0
      Value |= (op & UINT64_C(63488)) << 5;
3867
0
      Value |= op & UINT64_C(31);
3868
0
      break;
3869
44
    }
3870
44
    case Mips::AddiuSpImmX16:
3871
0
    case Mips::BteqzX16:
3872
0
    case Mips::BtnezX16: {
3873
0
      // op: imm16
3874
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3875
0
      Value |= (op & UINT64_C(2016)) << 16;
3876
0
      Value |= (op & UINT64_C(63488)) << 5;
3877
0
      Value |= op & UINT64_C(31);
3878
0
      break;
3879
0
    }
3880
0
    case Mips::AddiuRxImmX16:
3881
0
    case Mips::AddiuRxPcImmX16:
3882
0
    case Mips::AddiuRxRxImmX16:
3883
0
    case Mips::BeqzRxImmX16:
3884
0
    case Mips::BnezRxImmX16:
3885
0
    case Mips::CmpiRxImmX16:
3886
0
    case Mips::LiRxImmAlignX16:
3887
0
    case Mips::LiRxImmX16:
3888
0
    case Mips::LwRxPcTcpX16:
3889
0
    case Mips::SltiRxImmX16:
3890
0
    case Mips::SltiuRxImmX16: {
3891
0
      // op: imm16
3892
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3893
0
      Value |= (op & UINT64_C(2016)) << 16;
3894
0
      Value |= (op & UINT64_C(63488)) << 5;
3895
0
      Value |= op & UINT64_C(31);
3896
0
      // op: rx
3897
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3898
0
      Value |= (op & UINT64_C(7)) << 8;
3899
0
      break;
3900
0
    }
3901
0
    case Mips::LbRxRyOffMemX16:
3902
0
    case Mips::LbuRxRyOffMemX16:
3903
0
    case Mips::LhRxRyOffMemX16:
3904
0
    case Mips::LhuRxRyOffMemX16:
3905
0
    case Mips::LwRxRyOffMemX16:
3906
0
    case Mips::LwRxSpImmX16:
3907
0
    case Mips::SbRxRyOffMemX16:
3908
0
    case Mips::ShRxRyOffMemX16:
3909
0
    case Mips::SwRxRyOffMemX16:
3910
0
    case Mips::SwRxSpImmX16: {
3911
0
      // op: imm16
3912
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3913
0
      Value |= (op & UINT64_C(2016)) << 16;
3914
0
      Value |= (op & UINT64_C(63488)) << 5;
3915
0
      Value |= op & UINT64_C(31);
3916
0
      // op: rx
3917
0
      op = getMemEncoding(MI, 1, Fixups, STI);
3918
0
      Value |= (op & UINT64_C(7)) << 8;
3919
0
      // op: ry
3920
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3921
0
      Value |= (op & UINT64_C(7)) << 5;
3922
0
      break;
3923
0
    }
3924
0
    case Mips::Jal16:
3925
0
    case Mips::JalB16: {
3926
0
      // op: imm26
3927
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3928
0
      Value |= (op & UINT64_C(2031616)) << 5;
3929
0
      Value |= (op & UINT64_C(65011712)) >> 5;
3930
0
      Value |= op & UINT64_C(65535);
3931
0
      break;
3932
0
    }
3933
0
    case Mips::AddiuSpImm16:
3934
0
    case Mips::Bteqz16:
3935
0
    case Mips::Btnez16: {
3936
0
      // op: imm8
3937
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3938
0
      Value |= op & UINT64_C(255);
3939
0
      break;
3940
0
    }
3941
3
    case Mips::PREFX_MM: {
3942
3
      // op: index
3943
3
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3944
3
      Value |= (op & UINT64_C(31)) << 21;
3945
3
      // op: base
3946
3
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3947
3
      Value |= (op & UINT64_C(31)) << 16;
3948
3
      // op: hint
3949
3
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3950
3
      Value |= (op & UINT64_C(31)) << 11;
3951
3
      break;
3952
0
    }
3953
3
    case Mips::LBUX_MM:
3954
3
    case Mips::LHX_MM:
3955
3
    case Mips::LWX_MM: {
3956
3
      // op: index
3957
3
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3958
3
      Value |= (op & UINT64_C(31)) << 21;
3959
3
      // op: base
3960
3
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3961
3
      Value |= (op & UINT64_C(31)) << 16;
3962
3
      // op: rd
3963
3
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3964
3
      Value |= (op & UINT64_C(31)) << 11;
3965
3
      break;
3966
3
    }
3967
3
    case Mips::COPY_S_D: {
3968
1
      // op: n
3969
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3970
1
      Value |= (op & UINT64_C(1)) << 16;
3971
1
      // op: ws
3972
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3973
1
      Value |= (op & UINT64_C(31)) << 11;
3974
1
      // op: rd
3975
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3976
1
      Value |= (op & UINT64_C(31)) << 6;
3977
1
      break;
3978
3
    }
3979
3
    case Mips::SPLATI_D: {
3980
1
      // op: n
3981
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3982
1
      Value |= (op & UINT64_C(1)) << 16;
3983
1
      // op: ws
3984
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3985
1
      Value |= (op & UINT64_C(31)) << 11;
3986
1
      // op: wd
3987
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3988
1
      Value |= (op & UINT64_C(31)) << 6;
3989
1
      break;
3990
3
    }
3991
3
    case Mips::INSVE_D: {
3992
1
      // op: n
3993
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3994
1
      Value |= (op & UINT64_C(1)) << 16;
3995
1
      // op: ws
3996
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
3997
1
      Value |= (op & UINT64_C(31)) << 11;
3998
1
      // op: wd
3999
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4000
1
      Value |= (op & UINT64_C(31)) << 6;
4001
1
      break;
4002
3
    }
4003
3
    case Mips::COPY_S_B:
4004
2
    case Mips::COPY_U_B: {
4005
2
      // op: n
4006
2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4007
2
      Value |= (op & UINT64_C(15)) << 16;
4008
2
      // op: ws
4009
2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4010
2
      Value |= (op & UINT64_C(31)) << 11;
4011
2
      // op: rd
4012
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4013
2
      Value |= (op & UINT64_C(31)) << 6;
4014
2
      break;
4015
2
    }
4016
2
    case Mips::SPLATI_B: {
4017
1
      // op: n
4018
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4019
1
      Value |= (op & UINT64_C(15)) << 16;
4020
1
      // op: ws
4021
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4022
1
      Value |= (op & UINT64_C(31)) << 11;
4023
1
      // op: wd
4024
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4025
1
      Value |= (op & UINT64_C(31)) << 6;
4026
1
      break;
4027
2
    }
4028
2
    case Mips::INSVE_B: {
4029
1
      // op: n
4030
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4031
1
      Value |= (op & UINT64_C(15)) << 16;
4032
1
      // op: ws
4033
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4034
1
      Value |= (op & UINT64_C(31)) << 11;
4035
1
      // op: wd
4036
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4037
1
      Value |= (op & UINT64_C(31)) << 6;
4038
1
      break;
4039
2
    }
4040
2
    case Mips::COPY_S_W:
4041
1
    case Mips::COPY_U_W: {
4042
1
      // op: n
4043
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4044
1
      Value |= (op & UINT64_C(3)) << 16;
4045
1
      // op: ws
4046
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4047
1
      Value |= (op & UINT64_C(31)) << 11;
4048
1
      // op: rd
4049
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4050
1
      Value |= (op & UINT64_C(31)) << 6;
4051
1
      break;
4052
1
    }
4053
1
    case Mips::SPLATI_W: {
4054
1
      // op: n
4055
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4056
1
      Value |= (op & UINT64_C(3)) << 16;
4057
1
      // op: ws
4058
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4059
1
      Value |= (op & UINT64_C(31)) << 11;
4060
1
      // op: wd
4061
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4062
1
      Value |= (op & UINT64_C(31)) << 6;
4063
1
      break;
4064
1
    }
4065
1
    case Mips::INSVE_W: {
4066
1
      // op: n
4067
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4068
1
      Value |= (op & UINT64_C(3)) << 16;
4069
1
      // op: ws
4070
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4071
1
      Value |= (op & UINT64_C(31)) << 11;
4072
1
      // op: wd
4073
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4074
1
      Value |= (op & UINT64_C(31)) << 6;
4075
1
      break;
4076
1
    }
4077
2
    case Mips::COPY_S_H:
4078
2
    case Mips::COPY_U_H: {
4079
2
      // op: n
4080
2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4081
2
      Value |= (op & UINT64_C(7)) << 16;
4082
2
      // op: ws
4083
2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4084
2
      Value |= (op & UINT64_C(31)) << 11;
4085
2
      // op: rd
4086
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4087
2
      Value |= (op & UINT64_C(31)) << 6;
4088
2
      break;
4089
2
    }
4090
2
    case Mips::SPLATI_H: {
4091
1
      // op: n
4092
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4093
1
      Value |= (op & UINT64_C(7)) << 16;
4094
1
      // op: ws
4095
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4096
1
      Value |= (op & UINT64_C(31)) << 11;
4097
1
      // op: wd
4098
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4099
1
      Value |= (op & UINT64_C(31)) << 6;
4100
1
      break;
4101
2
    }
4102
2
    case Mips::INSVE_H: {
4103
1
      // op: n
4104
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4105
1
      Value |= (op & UINT64_C(7)) << 16;
4106
1
      // op: ws
4107
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4108
1
      Value |= (op & UINT64_C(31)) << 11;
4109
1
      // op: wd
4110
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4111
1
      Value |= (op & UINT64_C(31)) << 6;
4112
1
      break;
4113
2
    }
4114
2
    case Mips::INSERT_D: {
4115
1
      // op: n
4116
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4117
1
      Value |= (op & UINT64_C(1)) << 16;
4118
1
      // op: rs
4119
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4120
1
      Value |= (op & UINT64_C(31)) << 11;
4121
1
      // op: wd
4122
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4123
1
      Value |= (op & UINT64_C(31)) << 6;
4124
1
      break;
4125
2
    }
4126
2
    case Mips::SLDI_D: {
4127
1
      // op: n
4128
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4129
1
      Value |= (op & UINT64_C(1)) << 16;
4130
1
      // op: ws
4131
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4132
1
      Value |= (op & UINT64_C(31)) << 11;
4133
1
      // op: wd
4134
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4135
1
      Value |= (op & UINT64_C(31)) << 6;
4136
1
      break;
4137
2
    }
4138
2
    case Mips::INSERT_B: {
4139
1
      // op: n
4140
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4141
1
      Value |= (op & UINT64_C(15)) << 16;
4142
1
      // op: rs
4143
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4144
1
      Value |= (op & UINT64_C(31)) << 11;
4145
1
      // op: wd
4146
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4147
1
      Value |= (op & UINT64_C(31)) << 6;
4148
1
      break;
4149
2
    }
4150
2
    case Mips::SLDI_B: {
4151
1
      // op: n
4152
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4153
1
      Value |= (op & UINT64_C(15)) << 16;
4154
1
      // op: ws
4155
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4156
1
      Value |= (op & UINT64_C(31)) << 11;
4157
1
      // op: wd
4158
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4159
1
      Value |= (op & UINT64_C(31)) << 6;
4160
1
      break;
4161
2
    }
4162
2
    case Mips::INSERT_W: {
4163
1
      // op: n
4164
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4165
1
      Value |= (op & UINT64_C(3)) << 16;
4166
1
      // op: rs
4167
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4168
1
      Value |= (op & UINT64_C(31)) << 11;
4169
1
      // op: wd
4170
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4171
1
      Value |= (op & UINT64_C(31)) << 6;
4172
1
      break;
4173
2
    }
4174
2
    case Mips::SLDI_W: {
4175
1
      // op: n
4176
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4177
1
      Value |= (op & UINT64_C(3)) << 16;
4178
1
      // op: ws
4179
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4180
1
      Value |= (op & UINT64_C(31)) << 11;
4181
1
      // op: wd
4182
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4183
1
      Value |= (op & UINT64_C(31)) << 6;
4184
1
      break;
4185
2
    }
4186
2
    case Mips::INSERT_H: {
4187
1
      // op: n
4188
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4189
1
      Value |= (op & UINT64_C(7)) << 16;
4190
1
      // op: rs
4191
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4192
1
      Value |= (op & UINT64_C(31)) << 11;
4193
1
      // op: wd
4194
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4195
1
      Value |= (op & UINT64_C(31)) << 6;
4196
1
      break;
4197
2
    }
4198
2
    case Mips::SLDI_H: {
4199
1
      // op: n
4200
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4201
1
      Value |= (op & UINT64_C(7)) << 16;
4202
1
      // op: ws
4203
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4204
1
      Value |= (op & UINT64_C(31)) << 11;
4205
1
      // op: wd
4206
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4207
1
      Value |= (op & UINT64_C(31)) << 6;
4208
1
      break;
4209
2
    }
4210
27
    case Mips::BALC:
4211
27
    case Mips::BC: {
4212
27
      // op: offset
4213
27
      op = getBranchTarget26OpValue(MI, 0, Fixups, STI);
4214
27
      Value |= op & UINT64_C(67108863);
4215
27
      break;
4216
27
    }
4217
27
    case Mips::BALC_MMR6:
4218
13
    case Mips::BC_MMR6: {
4219
13
      // op: offset
4220
13
      op = getBranchTarget26OpValueMM(MI, 0, Fixups, STI);
4221
13
      Value |= op & UINT64_C(67108863);
4222
13
      break;
4223
13
    }
4224
13
    case Mips::BAL:
4225
4
    case Mips::BPOSGE32: {
4226
4
      // op: offset
4227
4
      op = getBranchTargetOpValue(MI, 0, Fixups, STI);
4228
4
      Value |= op & UINT64_C(65535);
4229
4
      break;
4230
4
    }
4231
20
    case Mips::BNZ_B:
4232
20
    case Mips::BNZ_D:
4233
20
    case Mips::BNZ_H:
4234
20
    case Mips::BNZ_V:
4235
20
    case Mips::BNZ_W:
4236
20
    case Mips::BZ_B:
4237
20
    case Mips::BZ_D:
4238
20
    case Mips::BZ_H:
4239
20
    case Mips::BZ_V:
4240
20
    case Mips::BZ_W: {
4241
20
      // op: offset
4242
20
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
4243
20
      Value |= op & UINT64_C(65535);
4244
20
      // op: wt
4245
20
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4246
20
      Value |= (op & UINT64_C(31)) << 16;
4247
20
      break;
4248
20
    }
4249
20
    case Mips::BPOSGE32C_MMR3: {
4250
1
      // op: offset
4251
1
      op = getBranchTargetOpValue1SImm16(MI, 0, Fixups, STI);
4252
1
      Value |= op & UINT64_C(65535);
4253
1
      break;
4254
20
    }
4255
20
    case Mips::BPOSGE32_MM: {
4256
1
      // op: offset
4257
1
      op = getBranchTargetOpValueMM(MI, 0, Fixups, STI);
4258
1
      Value |= op & UINT64_C(65535);
4259
1
      break;
4260
20
    }
4261
20
    case Mips::B16_MM:
4262
13
    case Mips::BC16_MMR6: {
4263
13
      // op: offset
4264
13
      op = getBranchTargetOpValueMMPC10(MI, 0, Fixups, STI);
4265
13
      Value |= op & UINT64_C(1023);
4266
13
      break;
4267
13
    }
4268
13
    case Mips::Move32R16: {
4269
2
      // op: r32
4270
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4271
2
      Value |= (op & UINT64_C(7)) << 5;
4272
2
      Value |= op & UINT64_C(24);
4273
2
      // op: rz
4274
2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4275
2
      Value |= op & UINT64_C(7);
4276
2
      break;
4277
13
    }
4278
467
    case Mips::MFHI:
4279
467
    case Mips::MFHI64:
4280
467
    case Mips::MFLO:
4281
467
    case Mips::MFLO64: {
4282
467
      // op: rd
4283
467
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4284
467
      Value |= (op & UINT64_C(31)) << 11;
4285
467
      break;
4286
467
    }
4287
467
    case Mips::MFHI_DSP:
4288
4
    case Mips::MFLO_DSP: {
4289
4
      // op: rd
4290
4
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4291
4
      Value |= (op & UINT64_C(31)) << 11;
4292
4
      // op: ac
4293
4
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4294
4
      Value |= (op & UINT64_C(3)) << 21;
4295
4
      break;
4296
4
    }
4297
4
    case Mips::LWXS_MM: {
4298
3
      // op: rd
4299
3
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4300
3
      Value |= (op & UINT64_C(31)) << 11;
4301
3
      // op: base
4302
3
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4303
3
      Value |= (op & UINT64_C(31)) << 16;
4304
3
      // op: index
4305
3
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4306
3
      Value |= (op & UINT64_C(31)) << 21;
4307
3
      break;
4308
4
    }
4309
8
    case Mips::LBUX:
4310
8
    case Mips::LHX:
4311
8
    case Mips::LWX: {
4312
8
      // op: rd
4313
8
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4314
8
      Value |= (op & UINT64_C(31)) << 11;
4315
8
      // op: base
4316
8
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4317
8
      Value |= (op & UINT64_C(31)) << 21;
4318
8
      // op: index
4319
8
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4320
8
      Value |= (op & UINT64_C(31)) << 16;
4321
8
      break;
4322
8
    }
4323
8
    case Mips::REPL_PH:
4324
5
    case Mips::REPL_PH_MM:
4325
5
    case Mips::REPL_QB: {
4326
5
      // op: rd
4327
5
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4328
5
      Value |= (op & UINT64_C(31)) << 11;
4329
5
      // op: imm
4330
5
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4331
5
      Value |= (op & UINT64_C(1023)) << 16;
4332
5
      break;
4333
5
    }
4334
5
    case Mips::RDDSP: {
4335
2
      // op: rd
4336
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4337
2
      Value |= (op & UINT64_C(31)) << 11;
4338
2
      // op: mask
4339
2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4340
2
      Value |= (op & UINT64_C(1023)) << 16;
4341
2
      break;
4342
5
    }
4343
78
    case Mips::ADDQH_PH_MMR2:
4344
78
    case Mips::ADDQH_R_PH_MMR2:
4345
78
    case Mips::ADDQH_R_W_MMR2:
4346
78
    case Mips::ADDQH_W_MMR2:
4347
78
    case Mips::ADDQ_PH_MM:
4348
78
    case Mips::ADDQ_S_PH_MM:
4349
78
    case Mips::ADDQ_S_W_MM:
4350
78
    case Mips::ADDSC_MM:
4351
78
    case Mips::ADDUH_QB_MMR2:
4352
78
    case Mips::ADDUH_R_QB_MMR2:
4353
78
    case Mips::ADDU_PH_MMR2:
4354
78
    case Mips::ADDU_QB_MM:
4355
78
    case Mips::ADDU_S_PH_MMR2:
4356
78
    case Mips::ADDU_S_QB_MM:
4357
78
    case Mips::ADDWC_MM:
4358
78
    case Mips::CMPGDU_EQ_QB_MMR2:
4359
78
    case Mips::CMPGDU_LE_QB_MMR2:
4360
78
    case Mips::CMPGDU_LT_QB_MMR2:
4361
78
    case Mips::MODSUB_MM:
4362
78
    case Mips::MULEQ_S_W_PHL_MM:
4363
78
    case Mips::MULEQ_S_W_PHR_MM:
4364
78
    case Mips::MULEU_S_PH_QBL_MM:
4365
78
    case Mips::MULEU_S_PH_QBR_MM:
4366
78
    case Mips::MULQ_RS_PH_MM:
4367
78
    case Mips::MULQ_RS_W_MMR2:
4368
78
    case Mips::MULQ_S_PH_MMR2:
4369
78
    case Mips::MULQ_S_W_MMR2:
4370
78
    case Mips::MUL_PH_MMR2:
4371
78
    case Mips::MUL_S_PH_MMR2:
4372
78
    case Mips::PACKRL_PH_MM:
4373
78
    case Mips::PICK_PH_MM:
4374
78
    case Mips::PICK_QB_MM:
4375
78
    case Mips::PRECRQU_S_QB_PH_MM:
4376
78
    case Mips::PRECRQ_PH_W_MM:
4377
78
    case Mips::PRECRQ_QB_PH_MM:
4378
78
    case Mips::PRECRQ_RS_PH_W_MM:
4379
78
    case Mips::PRECR_QB_PH_MMR2:
4380
78
    case Mips::SELEQZ_MMR6:
4381
78
    case Mips::SELNEZ_MMR6:
4382
78
    case Mips::SUBQH_PH_MMR2:
4383
78
    case Mips::SUBQH_R_PH_MMR2:
4384
78
    case Mips::SUBQH_R_W_MMR2:
4385
78
    case Mips::SUBQH_W_MMR2:
4386
78
    case Mips::SUBQ_PH_MM:
4387
78
    case Mips::SUBQ_S_PH_MM:
4388
78
    case Mips::SUBQ_S_W_MM:
4389
78
    case Mips::SUBUH_QB_MMR2:
4390
78
    case Mips::SUBUH_R_QB_MMR2:
4391
78
    case Mips::SUBU_PH_MMR2:
4392
78
    case Mips::SUBU_QB_MM:
4393
78
    case Mips::SUBU_S_PH_MMR2:
4394
78
    case Mips::SUBU_S_QB_MM: {
4395
78
      // op: rd
4396
78
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4397
78
      Value |= (op & UINT64_C(31)) << 11;
4398
78
      // op: rs
4399
78
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4400
78
      Value |= (op & UINT64_C(31)) << 16;
4401
78
      // op: rt
4402
78
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4403
78
      Value |= (op & UINT64_C(31)) << 21;
4404
78
      break;
4405
78
    }
4406
78
    case Mips::LSA_MMR6: {
4407
1
      // op: rd
4408
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4409
1
      Value |= (op & UINT64_C(31)) << 11;
4410
1
      // op: rs
4411
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4412
1
      Value |= (op & UINT64_C(31)) << 16;
4413
1
      // op: rt
4414
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4415
1
      Value |= (op & UINT64_C(31)) << 21;
4416
1
      // op: imm2
4417
1
      op = getUImmWithOffsetEncoding<2, 1>(MI, 3, Fixups, STI);
4418
1
      Value |= (op & UINT64_C(3)) << 9;
4419
1
      break;
4420
78
    }
4421
150
    case Mips::CLO_R6:
4422
150
    case Mips::CLZ_R6:
4423
150
    case Mips::DCLO_R6:
4424
150
    case Mips::DCLZ_R6:
4425
150
    case Mips::DPOP:
4426
150
    case Mips::JALR:
4427
150
    case Mips::JALR64:
4428
150
    case Mips::JALR_HB:
4429
150
    case Mips::JALR_HB64:
4430
150
    case Mips::POP:
4431
150
    case Mips::RADDU_W_QB: {
4432
150
      // op: rd
4433
150
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4434
150
      Value |= (op & UINT64_C(31)) << 11;
4435
150
      // op: rs
4436
150
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4437
150
      Value |= (op & UINT64_C(31)) << 21;
4438
150
      break;
4439
150
    }
4440
150
    case Mips::MOVF_I:
4441
26
    case Mips::MOVF_I64:
4442
26
    case Mips::MOVT_I:
4443
26
    case Mips::MOVT_I64: {
4444
26
      // op: rd
4445
26
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4446
26
      Value |= (op & UINT64_C(31)) << 11;
4447
26
      // op: rs
4448
26
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4449
26
      Value |= (op & UINT64_C(31)) << 21;
4450
26
      // op: fcc
4451
26
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4452
26
      Value |= (op & UINT64_C(7)) << 18;
4453
26
      break;
4454
26
    }
4455
1.96k
    case Mips::ADD:
4456
1.96k
    case Mips::ADDQH_PH:
4457
1.96k
    case Mips::ADDQH_R_PH:
4458
1.96k
    case Mips::ADDQH_R_W:
4459
1.96k
    case Mips::ADDQH_W:
4460
1.96k
    case Mips::ADDQ_PH:
4461
1.96k
    case Mips::ADDQ_S_PH:
4462
1.96k
    case Mips::ADDQ_S_W:
4463
1.96k
    case Mips::ADDSC:
4464
1.96k
    case Mips::ADDUH_QB:
4465
1.96k
    case Mips::ADDUH_R_QB:
4466
1.96k
    case Mips::ADDU_PH:
4467
1.96k
    case Mips::ADDU_QB:
4468
1.96k
    case Mips::ADDU_S_PH:
4469
1.96k
    case Mips::ADDU_S_QB:
4470
1.96k
    case Mips::ADDWC:
4471
1.96k
    case Mips::ADDu:
4472
1.96k
    case Mips::AND:
4473
1.96k
    case Mips::AND64:
4474
1.96k
    case Mips::BADDu:
4475
1.96k
    case Mips::DADD:
4476
1.96k
    case Mips::DADDu:
4477
1.96k
    case Mips::DDIV:
4478
1.96k
    case Mips::DDIVU:
4479
1.96k
    case Mips::DIV:
4480
1.96k
    case Mips::DIVU:
4481
1.96k
    case Mips::DMOD:
4482
1.96k
    case Mips::DMODU:
4483
1.96k
    case Mips::DMUH:
4484
1.96k
    case Mips::DMUHU:
4485
1.96k
    case Mips::DMUL:
4486
1.96k
    case Mips::DMULU:
4487
1.96k
    case Mips::DMUL_R6:
4488
1.96k
    case Mips::DSUB:
4489
1.96k
    case Mips::DSUBu:
4490
1.96k
    case Mips::MOD:
4491
1.96k
    case Mips::MODSUB:
4492
1.96k
    case Mips::MODU:
4493
1.96k
    case Mips::MOVN_I64_I:
4494
1.96k
    case Mips::MOVN_I64_I64:
4495
1.96k
    case Mips::MOVN_I_I:
4496
1.96k
    case Mips::MOVN_I_I64:
4497
1.96k
    case Mips::MOVZ_I64_I:
4498
1.96k
    case Mips::MOVZ_I64_I64:
4499
1.96k
    case Mips::MOVZ_I_I:
4500
1.96k
    case Mips::MOVZ_I_I64:
4501
1.96k
    case Mips::MUH:
4502
1.96k
    case Mips::MUHU:
4503
1.96k
    case Mips::MUL:
4504
1.96k
    case Mips::MULEQ_S_W_PHL:
4505
1.96k
    case Mips::MULEQ_S_W_PHR:
4506
1.96k
    case Mips::MULEU_S_PH_QBL:
4507
1.96k
    case Mips::MULEU_S_PH_QBR:
4508
1.96k
    case Mips::MULQ_RS_PH:
4509
1.96k
    case Mips::MULQ_RS_W:
4510
1.96k
    case Mips::MULQ_S_PH:
4511
1.96k
    case Mips::MULQ_S_W:
4512
1.96k
    case Mips::MULU:
4513
1.96k
    case Mips::MUL_PH:
4514
1.96k
    case Mips::MUL_R6:
4515
1.96k
    case Mips::MUL_S_PH:
4516
1.96k
    case Mips::NOR:
4517
1.96k
    case Mips::NOR64:
4518
1.96k
    case Mips::OR:
4519
1.96k
    case Mips::OR64:
4520
1.96k
    case Mips::SELEQZ:
4521
1.96k
    case Mips::SELEQZ64:
4522
1.96k
    case Mips::SELNEZ:
4523
1.96k
    case Mips::SELNEZ64:
4524
1.96k
    case Mips::SEQ:
4525
1.96k
    case Mips::SLT:
4526
1.96k
    case Mips::SLT64:
4527
1.96k
    case Mips::SLTu:
4528
1.96k
    case Mips::SLTu64:
4529
1.96k
    case Mips::SNE:
4530
1.96k
    case Mips::SUB:
4531
1.96k
    case Mips::SUBQH_PH:
4532
1.96k
    case Mips::SUBQH_R_PH:
4533
1.96k
    case Mips::SUBQH_R_W:
4534
1.96k
    case Mips::SUBQH_W:
4535
1.96k
    case Mips::SUBQ_PH:
4536
1.96k
    case Mips::SUBQ_S_PH:
4537
1.96k
    case Mips::SUBQ_S_W:
4538
1.96k
    case Mips::SUBUH_QB:
4539
1.96k
    case Mips::SUBUH_R_QB:
4540
1.96k
    case Mips::SUBU_PH:
4541
1.96k
    case Mips::SUBU_QB:
4542
1.96k
    case Mips::SUBU_S_PH:
4543
1.96k
    case Mips::SUBU_S_QB:
4544
1.96k
    case Mips::SUBu:
4545
1.96k
    case Mips::V3MULU:
4546
1.96k
    case Mips::VMM0:
4547
1.96k
    case Mips::VMULU:
4548
1.96k
    case Mips::XOR:
4549
1.96k
    case Mips::XOR64: {
4550
1.96k
      // op: rd
4551
1.96k
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4552
1.96k
      Value |= (op & UINT64_C(31)) << 11;
4553
1.96k
      // op: rs
4554
1.96k
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4555
1.96k
      Value |= (op & UINT64_C(31)) << 21;
4556
1.96k
      // op: rt
4557
1.96k
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4558
1.96k
      Value |= (op & UINT64_C(31)) << 16;
4559
1.96k
      break;
4560
1.96k
    }
4561
1.96k
    case Mips::ALIGN: {
4562
3
      // op: rd
4563
3
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4564
3
      Value |= (op & UINT64_C(31)) << 11;
4565
3
      // op: rs
4566
3
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4567
3
      Value |= (op & UINT64_C(31)) << 21;
4568
3
      // op: rt
4569
3
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4570
3
      Value |= (op & UINT64_C(31)) << 16;
4571
3
      // op: bp
4572
3
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4573
3
      Value |= (op & UINT64_C(3)) << 6;
4574
3
      break;
4575
1.96k
    }
4576
1.96k
    case Mips::ALIGN_MMR6: {
4577
1
      // op: rd
4578
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4579
1
      Value |= (op & UINT64_C(31)) << 11;
4580
1
      // op: rs
4581
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4582
1
      Value |= (op & UINT64_C(31)) << 21;
4583
1
      // op: rt
4584
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4585
1
      Value |= (op & UINT64_C(31)) << 16;
4586
1
      // op: bp
4587
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4588
1
      Value |= (op & UINT64_C(3)) << 9;
4589
1
      break;
4590
1.96k
    }
4591
1.96k
    case Mips::DALIGN: {
4592
1
      // op: rd
4593
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4594
1
      Value |= (op & UINT64_C(31)) << 11;
4595
1
      // op: rs
4596
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4597
1
      Value |= (op & UINT64_C(31)) << 21;
4598
1
      // op: rt
4599
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4600
1
      Value |= (op & UINT64_C(31)) << 16;
4601
1
      // op: bp
4602
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4603
1
      Value |= (op & UINT64_C(7)) << 6;
4604
1
      break;
4605
1.96k
    }
4606
1.96k
    case Mips::DLSA_R6:
4607
3
    case Mips::LSA_R6: {
4608
3
      // op: rd
4609
3
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4610
3
      Value |= (op & UINT64_C(31)) << 11;
4611
3
      // op: rs
4612
3
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4613
3
      Value |= (op & UINT64_C(31)) << 21;
4614
3
      // op: rt
4615
3
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4616
3
      Value |= (op & UINT64_C(31)) << 16;
4617
3
      // op: imm2
4618
3
      op = getUImmWithOffsetEncoding<2, 1>(MI, 3, Fixups, STI);
4619
3
      Value |= (op & UINT64_C(3)) << 6;
4620
3
      break;
4621
3
    }
4622
19
    case Mips::SHLLV_PH_MM:
4623
19
    case Mips::SHLLV_QB_MM:
4624
19
    case Mips::SHLLV_S_PH_MM:
4625
19
    case Mips::SHLLV_S_W_MM:
4626
19
    case Mips::SHRAV_PH_MM:
4627
19
    case Mips::SHRAV_QB_MMR2:
4628
19
    case Mips::SHRAV_R_PH_MM:
4629
19
    case Mips::SHRAV_R_QB_MMR2:
4630
19
    case Mips::SHRAV_R_W_MM:
4631
19
    case Mips::SHRLV_PH_MMR2:
4632
19
    case Mips::SHRLV_QB_MM: {
4633
19
      // op: rd
4634
19
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4635
19
      Value |= (op & UINT64_C(31)) << 11;
4636
19
      // op: rs
4637
19
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4638
19
      Value |= (op & UINT64_C(31)) << 16;
4639
19
      // op: rt
4640
19
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4641
19
      Value |= (op & UINT64_C(31)) << 21;
4642
19
      break;
4643
19
    }
4644
82
    case Mips::ABSQ_S_PH:
4645
82
    case Mips::ABSQ_S_QB:
4646
82
    case Mips::ABSQ_S_W:
4647
82
    case Mips::BITREV:
4648
82
    case Mips::BITSWAP:
4649
82
    case Mips::DBITSWAP:
4650
82
    case Mips::DSBH:
4651
82
    case Mips::DSHD:
4652
82
    case Mips::DSLL64_32:
4653
82
    case Mips::PRECEQU_PH_QBL:
4654
82
    case Mips::PRECEQU_PH_QBLA:
4655
82
    case Mips::PRECEQU_PH_QBR:
4656
82
    case Mips::PRECEQU_PH_QBRA:
4657
82
    case Mips::PRECEQ_W_PHL:
4658
82
    case Mips::PRECEQ_W_PHR:
4659
82
    case Mips::PRECEU_PH_QBL:
4660
82
    case Mips::PRECEU_PH_QBLA:
4661
82
    case Mips::PRECEU_PH_QBR:
4662
82
    case Mips::PRECEU_PH_QBRA:
4663
82
    case Mips::REPLV_PH:
4664
82
    case Mips::REPLV_QB:
4665
82
    case Mips::SEB:
4666
82
    case Mips::SEB64:
4667
82
    case Mips::SEH:
4668
82
    case Mips::SEH64:
4669
82
    case Mips::SLL64_32:
4670
82
    case Mips::SLL64_64:
4671
82
    case Mips::WSBH: {
4672
82
      // op: rd
4673
82
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4674
82
      Value |= (op & UINT64_C(31)) << 11;
4675
82
      // op: rt
4676
82
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4677
82
      Value |= (op & UINT64_C(31)) << 16;
4678
82
      break;
4679
82
    }
4680
306
    case Mips::DROTRV:
4681
306
    case Mips::DSLLV:
4682
306
    case Mips::DSRAV:
4683
306
    case Mips::DSRLV:
4684
306
    case Mips::ROTRV:
4685
306
    case Mips::SLLV:
4686
306
    case Mips::SRAV:
4687
306
    case Mips::SRLV: {
4688
306
      // op: rd
4689
306
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4690
306
      Value |= (op & UINT64_C(31)) << 11;
4691
306
      // op: rt
4692
306
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4693
306
      Value |= (op & UINT64_C(31)) << 16;
4694
306
      // op: rs
4695
306
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4696
306
      Value |= (op & UINT64_C(31)) << 21;
4697
306
      break;
4698
306
    }
4699
306
    case Mips::SHLLV_PH:
4700
38
    case Mips::SHLLV_QB:
4701
38
    case Mips::SHLLV_S_PH:
4702
38
    case Mips::SHLLV_S_W:
4703
38
    case Mips::SHLL_PH:
4704
38
    case Mips::SHLL_QB:
4705
38
    case Mips::SHLL_S_PH:
4706
38
    case Mips::SHLL_S_W:
4707
38
    case Mips::SHRAV_PH:
4708
38
    case Mips::SHRAV_QB:
4709
38
    case Mips::SHRAV_R_PH:
4710
38
    case Mips::SHRAV_R_QB:
4711
38
    case Mips::SHRAV_R_W:
4712
38
    case Mips::SHRA_PH:
4713
38
    case Mips::SHRA_QB:
4714
38
    case Mips::SHRA_R_PH:
4715
38
    case Mips::SHRA_R_QB:
4716
38
    case Mips::SHRA_R_W:
4717
38
    case Mips::SHRLV_PH:
4718
38
    case Mips::SHRLV_QB:
4719
38
    case Mips::SHRL_PH:
4720
38
    case Mips::SHRL_QB: {
4721
38
      // op: rd
4722
38
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4723
38
      Value |= (op & UINT64_C(31)) << 11;
4724
38
      // op: rt
4725
38
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4726
38
      Value |= (op & UINT64_C(31)) << 16;
4727
38
      // op: rs_sa
4728
38
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4729
38
      Value |= (op & UINT64_C(31)) << 21;
4730
38
      break;
4731
38
    }
4732
13.5k
    case Mips::DROTR:
4733
13.5k
    case Mips::DROTR32:
4734
13.5k
    case Mips::DSLL:
4735
13.5k
    case Mips::DSLL32:
4736
13.5k
    case Mips::DSRA:
4737
13.5k
    case Mips::DSRA32:
4738
13.5k
    case Mips::DSRL:
4739
13.5k
    case Mips::DSRL32:
4740
13.5k
    case Mips::ROTR:
4741
13.5k
    case Mips::SLL:
4742
13.5k
    case Mips::SRA:
4743
13.5k
    case Mips::SRL: {
4744
13.5k
      // op: rd
4745
13.5k
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4746
13.5k
      Value |= (op & UINT64_C(31)) << 11;
4747
13.5k
      // op: rt
4748
13.5k
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4749
13.5k
      Value |= (op & UINT64_C(31)) << 16;
4750
13.5k
      // op: shamt
4751
13.5k
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4752
13.5k
      Value |= (op & UINT64_C(31)) << 6;
4753
13.5k
      break;
4754
13.5k
    }
4755
13.5k
    case Mips::ROTRV_MM:
4756
44
    case Mips::SLLV_MM:
4757
44
    case Mips::SRAV_MM:
4758
44
    case Mips::SRLV_MM: {
4759
44
      // op: rd
4760
44
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4761
44
      Value |= (op & UINT64_C(31)) << 11;
4762
44
      // op: rt
4763
44
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4764
44
      Value |= (op & UINT64_C(31)) << 21;
4765
44
      // op: rs
4766
44
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4767
44
      Value |= (op & UINT64_C(31)) << 16;
4768
44
      break;
4769
44
    }
4770
44
    case Mips::ADDU_MMR6:
4771
22
    case Mips::ADD_MMR6:
4772
22
    case Mips::AND_MMR6:
4773
22
    case Mips::DIVU_MMR6:
4774
22
    case Mips::DIV_MMR6:
4775
22
    case Mips::MODU_MMR6:
4776
22
    case Mips::MOD_MMR6:
4777
22
    case Mips::MUHU_MMR6:
4778
22
    case Mips::MUH_MMR6:
4779
22
    case Mips::MULU_MMR6:
4780
22
    case Mips::MUL_MMR6:
4781
22
    case Mips::NOR_MMR6:
4782
22
    case Mips::OR_MMR6:
4783
22
    case Mips::SUBU_MMR6:
4784
22
    case Mips::SUB_MMR6:
4785
22
    case Mips::XOR_MMR6: {
4786
22
      // op: rd
4787
22
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4788
22
      Value |= (op & UINT64_C(31)) << 11;
4789
22
      // op: rt
4790
22
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4791
22
      Value |= (op & UINT64_C(31)) << 21;
4792
22
      // op: rs
4793
22
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4794
22
      Value |= (op & UINT64_C(31)) << 16;
4795
22
      break;
4796
22
    }
4797
22
    case Mips::MFHI_MM:
4798
2
    case Mips::MFLO_MM: {
4799
2
      // op: rd
4800
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4801
2
      Value |= (op & UINT64_C(31)) << 16;
4802
2
      break;
4803
2
    }
4804
2
    case Mips::BITSWAP_MMR6: {
4805
1
      // op: rd
4806
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4807
1
      Value |= (op & UINT64_C(31)) << 16;
4808
1
      // op: rt
4809
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4810
1
      Value |= (op & UINT64_C(31)) << 21;
4811
1
      break;
4812
2
    }
4813
29
    case Mips::CLO:
4814
29
    case Mips::CLZ:
4815
29
    case Mips::DCLO:
4816
29
    case Mips::DCLZ: {
4817
29
      // op: rd
4818
29
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4819
29
      Value |= (op & UINT64_C(31)) << 16;
4820
29
      Value |= (op & UINT64_C(31)) << 11;
4821
29
      // op: rs
4822
29
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4823
29
      Value |= (op & UINT64_C(31)) << 21;
4824
29
      break;
4825
29
    }
4826
29
    case Mips::CLO_MM:
4827
2
    case Mips::CLZ_MM: {
4828
2
      // op: rd
4829
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4830
2
      Value |= (op & UINT64_C(31)) << 21;
4831
2
      // op: rs
4832
2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4833
2
      Value |= (op & UINT64_C(31)) << 16;
4834
2
      break;
4835
2
    }
4836
6
    case Mips::MOVF_I_MM:
4837
6
    case Mips::MOVT_I_MM: {
4838
6
      // op: rd
4839
6
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4840
6
      Value |= (op & UINT64_C(31)) << 21;
4841
6
      // op: rs
4842
6
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4843
6
      Value |= (op & UINT64_C(31)) << 16;
4844
6
      // op: fcc
4845
6
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4846
6
      Value |= (op & UINT64_C(7)) << 13;
4847
6
      break;
4848
6
    }
4849
9
    case Mips::SEB_MM:
4850
9
    case Mips::SEH_MM:
4851
9
    case Mips::WSBH_MM: {
4852
9
      // op: rd
4853
9
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4854
9
      Value |= (op & UINT64_C(31)) << 21;
4855
9
      // op: rt
4856
9
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4857
9
      Value |= (op & UINT64_C(31)) << 16;
4858
9
      break;
4859
9
    }
4860
199
    case Mips::ROTR_MM:
4861
199
    case Mips::SLL_MM:
4862
199
    case Mips::SLL_MMR6:
4863
199
    case Mips::SRA_MM:
4864
199
    case Mips::SRL_MM: {
4865
199
      // op: rd
4866
199
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4867
199
      Value |= (op & UINT64_C(31)) << 21;
4868
199
      // op: rt
4869
199
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4870
199
      Value |= (op & UINT64_C(31)) << 16;
4871
199
      // op: shamt
4872
199
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4873
199
      Value |= (op & UINT64_C(31)) << 11;
4874
199
      break;
4875
199
    }
4876
199
    case Mips::CFCMSA: {
4877
16
      // op: rd
4878
16
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4879
16
      Value |= (op & UINT64_C(31)) << 6;
4880
16
      // op: cs
4881
16
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4882
16
      Value |= (op & UINT64_C(31)) << 11;
4883
16
      break;
4884
199
    }
4885
199
    case Mips::LI16_MM:
4886
29
    case Mips::LI16_MMR6: {
4887
29
      // op: rd
4888
29
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4889
29
      Value |= (op & UINT64_C(7)) << 7;
4890
29
      // op: imm
4891
29
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4892
29
      Value |= op & UINT64_C(127);
4893
29
      break;
4894
29
    }
4895
29
    case Mips::ADDIUR1SP_MM: {
4896
4
      // op: rd
4897
4
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4898
4
      Value |= (op & UINT64_C(7)) << 7;
4899
4
      // op: imm
4900
4
      op = getUImm6Lsl2Encoding(MI, 1, Fixups, STI);
4901
4
      Value |= (op & UINT64_C(63)) << 1;
4902
4
      break;
4903
29
    }
4904
29
    case Mips::ADDIUR2_MM: {
4905
8
      // op: rd
4906
8
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4907
8
      Value |= (op & UINT64_C(7)) << 7;
4908
8
      // op: rs
4909
8
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4910
8
      Value |= (op & UINT64_C(7)) << 4;
4911
8
      // op: imm
4912
8
      op = getSImm3Lsa2Value(MI, 2, Fixups, STI);
4913
8
      Value |= (op & UINT64_C(7)) << 1;
4914
8
      break;
4915
29
    }
4916
29
    case Mips::ANDI16_MM:
4917
5
    case Mips::ANDI16_MMR6: {
4918
5
      // op: rd
4919
5
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4920
5
      Value |= (op & UINT64_C(7)) << 7;
4921
5
      // op: rs
4922
5
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4923
5
      Value |= (op & UINT64_C(7)) << 4;
4924
5
      // op: imm
4925
5
      op = getUImm4AndValue(MI, 2, Fixups, STI);
4926
5
      Value |= op & UINT64_C(15);
4927
5
      break;
4928
5
    }
4929
8
    case Mips::SLL16_MM:
4930
8
    case Mips::SLL16_MMR6:
4931
8
    case Mips::SRL16_MM:
4932
8
    case Mips::SRL16_MMR6: {
4933
8
      // op: rd
4934
8
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4935
8
      Value |= (op & UINT64_C(7)) << 7;
4936
8
      // op: rt
4937
8
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4938
8
      Value |= (op & UINT64_C(7)) << 4;
4939
8
      // op: shamt
4940
8
      op = getUImm3Mod8Encoding(MI, 2, Fixups, STI);
4941
8
      Value |= (op & UINT64_C(7)) << 1;
4942
8
      break;
4943
8
    }
4944
8
    case Mips::ADDU16_MM:
4945
7
    case Mips::SUBU16_MM: {
4946
7
      // op: rd
4947
7
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4948
7
      Value |= (op & UINT64_C(7)) << 7;
4949
7
      // op: rt
4950
7
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4951
7
      Value |= (op & UINT64_C(7)) << 4;
4952
7
      // op: rs
4953
7
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4954
7
      Value |= (op & UINT64_C(7)) << 1;
4955
7
      break;
4956
7
    }
4957
7
    case Mips::MFHI16_MM:
4958
6
    case Mips::MFLO16_MM: {
4959
6
      // op: rd
4960
6
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4961
6
      Value |= op & UINT64_C(31);
4962
6
      break;
4963
6
    }
4964
6
    case Mips::ADDIUS5_MM: {
4965
4
      // op: rd
4966
4
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4967
4
      Value |= (op & UINT64_C(31)) << 5;
4968
4
      // op: imm
4969
4
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4970
4
      Value |= (op & UINT64_C(15)) << 1;
4971
4
      break;
4972
6
    }
4973
24
    case Mips::DVP_MMR6:
4974
24
    case Mips::EVP_MMR6:
4975
24
    case Mips::JR_MM:
4976
24
    case Mips::MTHI_MM:
4977
24
    case Mips::MTLO_MM: {
4978
24
      // op: rs
4979
24
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4980
24
      Value |= (op & UINT64_C(31)) << 16;
4981
24
      break;
4982
24
    }
4983
24
    case Mips::MFHI_DSP_MM:
4984
2
    case Mips::MFLO_DSP_MM: {
4985
2
      // op: rs
4986
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4987
2
      Value |= (op & UINT64_C(31)) << 16;
4988
2
      // op: ac
4989
2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4990
2
      Value |= (op & UINT64_C(3)) << 14;
4991
2
      break;
4992
2
    }
4993
18
    case Mips::TEQI_MM:
4994
18
    case Mips::TGEIU_MM:
4995
18
    case Mips::TGEI_MM:
4996
18
    case Mips::TLTIU_MM:
4997
18
    case Mips::TLTI_MM:
4998
18
    case Mips::TNEI_MM: {
4999
18
      // op: rs
5000
18
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5001
18
      Value |= (op & UINT64_C(31)) << 16;
5002
18
      // op: imm16
5003
18
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5004
18
      Value |= op & UINT64_C(65535);
5005
18
      break;
5006
18
    }
5007
50
    case Mips::BEQZC_MM:
5008
50
    case Mips::BGEZALS_MM:
5009
50
    case Mips::BGEZAL_MM:
5010
50
    case Mips::BGEZ_MM:
5011
50
    case Mips::BGTZ_MM:
5012
50
    case Mips::BLEZ_MM:
5013
50
    case Mips::BLTZALS_MM:
5014
50
    case Mips::BLTZAL_MM:
5015
50
    case Mips::BLTZ_MM:
5016
50
    case Mips::BNEZC_MM: {
5017
50
      // op: rs
5018
50
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5019
50
      Value |= (op & UINT64_C(31)) << 16;
5020
50
      // op: offset
5021
50
      op = getBranchTargetOpValueMM(MI, 1, Fixups, STI);
5022
50
      Value |= op & UINT64_C(65535);
5023
50
      break;
5024
50
    }
5025
50
    case Mips::MADDU_MM:
5026
24
    case Mips::MADD_MM:
5027
24
    case Mips::MSUBU_MM:
5028
24
    case Mips::MSUB_MM:
5029
24
    case Mips::MULT_MM:
5030
24
    case Mips::MULTu_MM:
5031
24
    case Mips::SDIV_MM:
5032
24
    case Mips::UDIV_MM: {
5033
24
      // op: rs
5034
24
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5035
24
      Value |= (op & UINT64_C(31)) << 16;
5036
24
      // op: rt
5037
24
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5038
24
      Value |= (op & UINT64_C(31)) << 21;
5039
24
      break;
5040
24
    }
5041
30
    case Mips::TEQ_MM:
5042
30
    case Mips::TGEU_MM:
5043
30
    case Mips::TGE_MM:
5044
30
    case Mips::TLTU_MM:
5045
30
    case Mips::TLT_MM:
5046
30
    case Mips::TNE_MM: {
5047
30
      // op: rs
5048
30
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5049
30
      Value |= (op & UINT64_C(31)) << 16;
5050
30
      // op: rt
5051
30
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5052
30
      Value |= (op & UINT64_C(31)) << 21;
5053
30
      // op: code_
5054
30
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5055
30
      Value |= (op & UINT64_C(15)) << 12;
5056
30
      break;
5057
30
    }
5058
33
    case Mips::BEQ_MM:
5059
33
    case Mips::BNE_MM: {
5060
33
      // op: rs
5061
33
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5062
33
      Value |= (op & UINT64_C(31)) << 16;
5063
33
      // op: rt
5064
33
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5065
33
      Value |= (op & UINT64_C(31)) << 21;
5066
33
      // op: offset
5067
33
      op = getBranchTargetOpValueMM(MI, 2, Fixups, STI);
5068
33
      Value |= op & UINT64_C(65535);
5069
33
      break;
5070
33
    }
5071
33
    case Mips::GINVI_MMR6: {
5072
1
      // op: rs
5073
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5074
1
      Value |= (op & UINT64_C(31)) << 16;
5075
1
      // op: type
5076
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5077
1
      Value |= (op & UINT64_C(3)) << 9;
5078
1
      break;
5079
33
    }
5080
33
    case Mips::GINVT_MMR6: {
5081
1
      // op: rs
5082
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5083
1
      Value |= (op & UINT64_C(31)) << 16;
5084
1
      // op: type
5085
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5086
1
      Value |= (op & UINT64_C(3)) << 9;
5087
1
      break;
5088
33
    }
5089
185
    case Mips::JR:
5090
185
    case Mips::JR64:
5091
185
    case Mips::JR_HB:
5092
185
    case Mips::JR_HB64:
5093
185
    case Mips::JR_HB64_R6:
5094
185
    case Mips::JR_HB_R6:
5095
185
    case Mips::MTHI:
5096
185
    case Mips::MTHI64:
5097
185
    case Mips::MTLO:
5098
185
    case Mips::MTLO64:
5099
185
    case Mips::MTM0:
5100
185
    case Mips::MTM1:
5101
185
    case Mips::MTM2:
5102
185
    case Mips::MTP0:
5103
185
    case Mips::MTP1:
5104
185
    case Mips::MTP2: {
5105
185
      // op: rs
5106
185
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5107
185
      Value |= (op & UINT64_C(31)) << 21;
5108
185
      break;
5109
185
    }
5110
185
    case Mips::ALUIPC:
5111
15
    case Mips::AUIPC: {
5112
15
      // op: rs
5113
15
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5114
15
      Value |= (op & UINT64_C(31)) << 21;
5115
15
      // op: imm
5116
15
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5117
15
      Value |= op & UINT64_C(65535);
5118
15
      break;
5119
15
    }
5120
15
    case Mips::DAHI:
5121
2
    case Mips::DATI: {
5122
2
      // op: rs
5123
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5124
2
      Value |= (op & UINT64_C(31)) << 21;
5125
2
      // op: imm
5126
2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5127
2
      Value |= op & UINT64_C(65535);
5128
2
      break;
5129
2
    }
5130
9
    case Mips::LDPC: {
5131
9
      // op: rs
5132
9
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5133
9
      Value |= (op & UINT64_C(31)) << 21;
5134
9
      // op: imm
5135
9
      op = getSimm18Lsl3Encoding(MI, 1, Fixups, STI);
5136
9
      Value |= op & UINT64_C(262143);
5137
9
      break;
5138
2
    }
5139
46
    case Mips::ADDIUPC:
5140
46
    case Mips::LWPC:
5141
46
    case Mips::LWUPC: {
5142
46
      // op: rs
5143
46
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5144
46
      Value |= (op & UINT64_C(31)) << 21;
5145
46
      // op: imm
5146
46
      op = getSimm19Lsl2Encoding(MI, 1, Fixups, STI);
5147
46
      Value |= op & UINT64_C(524287);
5148
46
      break;
5149
46
    }
5150
84
    case Mips::TEQI:
5151
84
    case Mips::TGEI:
5152
84
    case Mips::TGEIU:
5153
84
    case Mips::TLTI:
5154
84
    case Mips::TNEI:
5155
84
    case Mips::TTLTIU: {
5156
84
      // op: rs
5157
84
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5158
84
      Value |= (op & UINT64_C(31)) << 21;
5159
84
      // op: imm16
5160
84
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5161
84
      Value |= op & UINT64_C(65535);
5162
84
      break;
5163
84
    }
5164
84
    case Mips::WRDSP: {
5165
8
      // op: rs
5166
8
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5167
8
      Value |= (op & UINT64_C(31)) << 21;
5168
8
      // op: mask
5169
8
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5170
8
      Value |= (op & UINT64_C(1023)) << 11;
5171
8
      break;
5172
84
    }
5173
84
    case Mips::BEQZC:
5174
26
    case Mips::BEQZC64:
5175
26
    case Mips::BNEZC:
5176
26
    case Mips::BNEZC64: {
5177
26
      // op: rs
5178
26
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5179
26
      Value |= (op & UINT64_C(31)) << 21;
5180
26
      // op: offset
5181
26
      op = getBranchTarget21OpValue(MI, 1, Fixups, STI);
5182
26
      Value |= op & UINT64_C(2097151);
5183
26
      break;
5184
26
    }
5185
26
    case Mips::BEQZC_MMR6:
5186
8
    case Mips::BNEZC_MMR6: {
5187
8
      // op: rs
5188
8
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5189
8
      Value |= (op & UINT64_C(31)) << 21;
5190
8
      // op: offset
5191
8
      op = getBranchTarget21OpValueMM(MI, 1, Fixups, STI);
5192
8
      Value |= op & UINT64_C(2097151);
5193
8
      break;
5194
8
    }
5195
168
    case Mips::BGEZ:
5196
168
    case Mips::BGEZ64:
5197
168
    case Mips::BGEZAL:
5198
168
    case Mips::BGEZALL:
5199
168
    case Mips::BGEZL:
5200
168
    case Mips::BGTZ:
5201
168
    case Mips::BGTZ64:
5202
168
    case Mips::BGTZL:
5203
168
    case Mips::BLEZ:
5204
168
    case Mips::BLEZ64:
5205
168
    case Mips::BLEZL:
5206
168
    case Mips::BLTZ:
5207
168
    case Mips::BLTZ64:
5208
168
    case Mips::BLTZAL:
5209
168
    case Mips::BLTZALL:
5210
168
    case Mips::BLTZL: {
5211
168
      // op: rs
5212
168
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5213
168
      Value |= (op & UINT64_C(31)) << 21;
5214
168
      // op: offset
5215
168
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
5216
168
      Value |= op & UINT64_C(65535);
5217
168
      break;
5218
168
    }
5219
168
    case Mips::BBIT0:
5220
6
    case Mips::BBIT032:
5221
6
    case Mips::BBIT1:
5222
6
    case Mips::BBIT132: {
5223
6
      // op: rs
5224
6
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5225
6
      Value |= (op & UINT64_C(31)) << 21;
5226
6
      // op: p
5227
6
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5228
6
      Value |= (op & UINT64_C(31)) << 16;
5229
6
      // op: offset
5230
6
      op = getBranchTargetOpValue(MI, 2, Fixups, STI);
5231
6
      Value |= op & UINT64_C(65535);
5232
6
      break;
5233
6
    }
5234
585
    case Mips::CMPU_EQ_QB:
5235
585
    case Mips::CMPU_LE_QB:
5236
585
    case Mips::CMPU_LT_QB:
5237
585
    case Mips::CMP_EQ_PH:
5238
585
    case Mips::CMP_LE_PH:
5239
585
    case Mips::CMP_LT_PH:
5240
585
    case Mips::DMULT:
5241
585
    case Mips::DMULTu:
5242
585
    case Mips::DSDIV:
5243
585
    case Mips::DUDIV:
5244
585
    case Mips::MADD:
5245
585
    case Mips::MADDU:
5246
585
    case Mips::MSUB:
5247
585
    case Mips::MSUBU:
5248
585
    case Mips::MULT:
5249
585
    case Mips::MULTu:
5250
585
    case Mips::SDIV:
5251
585
    case Mips::UDIV: {
5252
585
      // op: rs
5253
585
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5254
585
      Value |= (op & UINT64_C(31)) << 21;
5255
585
      // op: rt
5256
585
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5257
585
      Value |= (op & UINT64_C(31)) << 16;
5258
585
      break;
5259
585
    }
5260
585
    case Mips::TEQ:
5261
321
    case Mips::TGE:
5262
321
    case Mips::TGEU:
5263
321
    case Mips::TLT:
5264
321
    case Mips::TLTU:
5265
321
    case Mips::TNE: {
5266
321
      // op: rs
5267
321
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5268
321
      Value |= (op & UINT64_C(31)) << 21;
5269
321
      // op: rt
5270
321
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5271
321
      Value |= (op & UINT64_C(31)) << 16;
5272
321
      // op: code_
5273
321
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5274
321
      Value |= (op & UINT64_C(1023)) << 6;
5275
321
      break;
5276
321
    }
5277
360
    case Mips::BEQ:
5278
360
    case Mips::BEQ64:
5279
360
    case Mips::BEQC:
5280
360
    case Mips::BEQC64:
5281
360
    case Mips::BEQL:
5282
360
    case Mips::BGEC:
5283
360
    case Mips::BGEC64:
5284
360
    case Mips::BGEUC:
5285
360
    case Mips::BGEUC64:
5286
360
    case Mips::BLTC:
5287
360
    case Mips::BLTC64:
5288
360
    case Mips::BLTUC:
5289
360
    case Mips::BLTUC64:
5290
360
    case Mips::BNE:
5291
360
    case Mips::BNE64:
5292
360
    case Mips::BNEC:
5293
360
    case Mips::BNEC64:
5294
360
    case Mips::BNEL:
5295
360
    case Mips::BNVC:
5296
360
    case Mips::BOVC: {
5297
360
      // op: rs
5298
360
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5299
360
      Value |= (op & UINT64_C(31)) << 21;
5300
360
      // op: rt
5301
360
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5302
360
      Value |= (op & UINT64_C(31)) << 16;
5303
360
      // op: offset
5304
360
      op = getBranchTargetOpValue(MI, 2, Fixups, STI);
5305
360
      Value |= op & UINT64_C(65535);
5306
360
      break;
5307
360
    }
5308
360
    case Mips::FORK: {
5309
1
      // op: rs
5310
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5311
1
      Value |= (op & UINT64_C(31)) << 21;
5312
1
      // op: rt
5313
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5314
1
      Value |= (op & UINT64_C(31)) << 16;
5315
1
      // op: rd
5316
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5317
1
      Value |= (op & UINT64_C(31)) << 11;
5318
1
      break;
5319
360
    }
5320
360
    case Mips::GINVI: {
5321
5
      // op: rs
5322
5
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5323
5
      Value |= (op & UINT64_C(31)) << 21;
5324
5
      // op: type_
5325
5
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5326
5
      Value |= (op & UINT64_C(3)) << 8;
5327
5
      break;
5328
360
    }
5329
360
    case Mips::GINVT: {
5330
2
      // op: rs
5331
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5332
2
      Value |= (op & UINT64_C(31)) << 21;
5333
2
      // op: type_
5334
2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5335
2
      Value |= (op & UINT64_C(3)) << 8;
5336
2
      break;
5337
360
    }
5338
360
    case Mips::JALRC16_MMR6:
5339
2
    case Mips::JRC16_MMR6: {
5340
2
      // op: rs
5341
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5342
2
      Value |= (op & UINT64_C(31)) << 5;
5343
2
      break;
5344
2
    }
5345
9
    case Mips::ADDIUPC_MM: {
5346
9
      // op: rs
5347
9
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5348
9
      Value |= (op & UINT64_C(7)) << 23;
5349
9
      // op: imm
5350
9
      op = getSimm23Lsl2Encoding(MI, 1, Fixups, STI);
5351
9
      Value |= op & UINT64_C(8388607);
5352
9
      break;
5353
2
    }
5354
15
    case Mips::BEQZ16_MM: