Coverage Report

Created: 2018-11-13 17:19

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Mips/MipsGenMCCodeEmitter.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Machine Code Emitter                                                       *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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uint64_t MipsMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
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    SmallVectorImpl<MCFixup> &Fixups,
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    const MCSubtargetInfo &STI) const {
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  static const uint64_t InstBits[] = {
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42.7k
    UINT64_C(0),
429
42.7k
    UINT64_C(0),
430
42.7k
    UINT64_C(0),
431
42.7k
    UINT64_C(0),
432
42.7k
    UINT64_C(0),
433
42.7k
    UINT64_C(0),
434
42.7k
    UINT64_C(0),
435
42.7k
    UINT64_C(0),
436
42.7k
    UINT64_C(0),
437
42.7k
    UINT64_C(0),
438
42.7k
    UINT64_C(0),
439
42.7k
    UINT64_C(0),
440
42.7k
    UINT64_C(0),
441
42.7k
    UINT64_C(0),
442
42.7k
    UINT64_C(0),
443
42.7k
    UINT64_C(0),
444
42.7k
    UINT64_C(0),
445
42.7k
    UINT64_C(0),
446
42.7k
    UINT64_C(0),
447
42.7k
    UINT64_C(0),
448
42.7k
    UINT64_C(0),
449
42.7k
    UINT64_C(0),
450
42.7k
    UINT64_C(0),
451
42.7k
    UINT64_C(0),
452
42.7k
    UINT64_C(0),
453
42.7k
    UINT64_C(0),
454
42.7k
    UINT64_C(0),
455
42.7k
    UINT64_C(0),
456
42.7k
    UINT64_C(0),
457
42.7k
    UINT64_C(0),
458
42.7k
    UINT64_C(0),
459
42.7k
    UINT64_C(0),
460
42.7k
    UINT64_C(0),
461
42.7k
    UINT64_C(0),
462
42.7k
    UINT64_C(0),
463
42.7k
    UINT64_C(0),
464
42.7k
    UINT64_C(0),
465
42.7k
    UINT64_C(0),
466
42.7k
    UINT64_C(0),
467
42.7k
    UINT64_C(0),
468
42.7k
    UINT64_C(0),
469
42.7k
    UINT64_C(0),
470
42.7k
    UINT64_C(0),
471
42.7k
    UINT64_C(0),
472
42.7k
    UINT64_C(0),
473
42.7k
    UINT64_C(0),
474
42.7k
    UINT64_C(0),
475
42.7k
    UINT64_C(0),
476
42.7k
    UINT64_C(0),
477
42.7k
    UINT64_C(0),
478
42.7k
    UINT64_C(0),
479
42.7k
    UINT64_C(0),
480
42.7k
    UINT64_C(0),
481
42.7k
    UINT64_C(0),
482
42.7k
    UINT64_C(0),
483
42.7k
    UINT64_C(0),
484
42.7k
    UINT64_C(0),
485
42.7k
    UINT64_C(0),
486
42.7k
    UINT64_C(0),
487
42.7k
    UINT64_C(0),
488
42.7k
    UINT64_C(0),
489
42.7k
    UINT64_C(0),
490
42.7k
    UINT64_C(0),
491
42.7k
    UINT64_C(0),
492
42.7k
    UINT64_C(0),
493
42.7k
    UINT64_C(0),
494
42.7k
    UINT64_C(0),
495
42.7k
    UINT64_C(0),
496
42.7k
    UINT64_C(0),
497
42.7k
    UINT64_C(0),
498
42.7k
    UINT64_C(0),
499
42.7k
    UINT64_C(0),
500
42.7k
    UINT64_C(0),
501
42.7k
    UINT64_C(0),
502
42.7k
    UINT64_C(0),
503
42.7k
    UINT64_C(0),
504
42.7k
    UINT64_C(0),
505
42.7k
    UINT64_C(0),
506
42.7k
    UINT64_C(0),
507
42.7k
    UINT64_C(0),
508
42.7k
    UINT64_C(0),
509
42.7k
    UINT64_C(0),
510
42.7k
    UINT64_C(0),
511
42.7k
    UINT64_C(0),
512
42.7k
    UINT64_C(0),
513
42.7k
    UINT64_C(0),
514
42.7k
    UINT64_C(0),
515
42.7k
    UINT64_C(0),
516
42.7k
    UINT64_C(0),
517
42.7k
    UINT64_C(0),
518
42.7k
    UINT64_C(0),
519
42.7k
    UINT64_C(0),
520
42.7k
    UINT64_C(0),
521
42.7k
    UINT64_C(0),
522
42.7k
    UINT64_C(0),
523
42.7k
    UINT64_C(0),
524
42.7k
    UINT64_C(0),
525
42.7k
    UINT64_C(0),
526
42.7k
    UINT64_C(0),
527
42.7k
    UINT64_C(0),
528
42.7k
    UINT64_C(0),
529
42.7k
    UINT64_C(0),
530
42.7k
    UINT64_C(0),
531
42.7k
    UINT64_C(0),
532
42.7k
    UINT64_C(0),
533
42.7k
    UINT64_C(0),
534
42.7k
    UINT64_C(0),
535
42.7k
    UINT64_C(0),
536
42.7k
    UINT64_C(0),
537
42.7k
    UINT64_C(0),
538
42.7k
    UINT64_C(0),
539
42.7k
    UINT64_C(0),
540
42.7k
    UINT64_C(0),
541
42.7k
    UINT64_C(0),
542
42.7k
    UINT64_C(0),
543
42.7k
    UINT64_C(0),
544
42.7k
    UINT64_C(0),
545
42.7k
    UINT64_C(0),
546
42.7k
    UINT64_C(0),
547
42.7k
    UINT64_C(0),
548
42.7k
    UINT64_C(2080375378), // ABSQ_S_PH
549
42.7k
    UINT64_C(4412), // ABSQ_S_PH_MM
550
42.7k
    UINT64_C(2080374866), // ABSQ_S_QB
551
42.7k
    UINT64_C(316),  // ABSQ_S_QB_MMR2
552
42.7k
    UINT64_C(2080375890), // ABSQ_S_W
553
42.7k
    UINT64_C(8508), // ABSQ_S_W_MM
554
42.7k
    UINT64_C(32), // ADD
555
42.7k
    UINT64_C(3959422976), // ADDIUPC
556
42.7k
    UINT64_C(2013265920), // ADDIUPC_MM
557
42.7k
    UINT64_C(2013265920), // ADDIUPC_MMR6
558
42.7k
    UINT64_C(27649),  // ADDIUR1SP_MM
559
42.7k
    UINT64_C(27648),  // ADDIUR2_MM
560
42.7k
    UINT64_C(19456),  // ADDIUS5_MM
561
42.7k
    UINT64_C(19457),  // ADDIUSP_MM
562
42.7k
    UINT64_C(805306368),  // ADDIU_MMR6
563
42.7k
    UINT64_C(2080375320), // ADDQH_PH
564
42.7k
    UINT64_C(77), // ADDQH_PH_MMR2
565
42.7k
    UINT64_C(2080375448), // ADDQH_R_PH
566
42.7k
    UINT64_C(1101), // ADDQH_R_PH_MMR2
567
42.7k
    UINT64_C(2080375960), // ADDQH_R_W
568
42.7k
    UINT64_C(1165), // ADDQH_R_W_MMR2
569
42.7k
    UINT64_C(2080375832), // ADDQH_W
570
42.7k
    UINT64_C(141),  // ADDQH_W_MMR2
571
42.7k
    UINT64_C(2080375440), // ADDQ_PH
572
42.7k
    UINT64_C(13), // ADDQ_PH_MM
573
42.7k
    UINT64_C(2080375696), // ADDQ_S_PH
574
42.7k
    UINT64_C(1037), // ADDQ_S_PH_MM
575
42.7k
    UINT64_C(2080376208), // ADDQ_S_W
576
42.7k
    UINT64_C(773),  // ADDQ_S_W_MM
577
42.7k
    UINT64_C(2080375824), // ADDSC
578
42.7k
    UINT64_C(901),  // ADDSC_MM
579
42.7k
    UINT64_C(2021654544), // ADDS_A_B
580
42.7k
    UINT64_C(2027946000), // ADDS_A_D
581
42.7k
    UINT64_C(2023751696), // ADDS_A_H
582
42.7k
    UINT64_C(2025848848), // ADDS_A_W
583
42.7k
    UINT64_C(2030043152), // ADDS_S_B
584
42.7k
    UINT64_C(2036334608), // ADDS_S_D
585
42.7k
    UINT64_C(2032140304), // ADDS_S_H
586
42.7k
    UINT64_C(2034237456), // ADDS_S_W
587
42.7k
    UINT64_C(2038431760), // ADDS_U_B
588
42.7k
    UINT64_C(2044723216), // ADDS_U_D
589
42.7k
    UINT64_C(2040528912), // ADDS_U_H
590
42.7k
    UINT64_C(2042626064), // ADDS_U_W
591
42.7k
    UINT64_C(1024), // ADDU16_MM
592
42.7k
    UINT64_C(1024), // ADDU16_MMR6
593
42.7k
    UINT64_C(2080374808), // ADDUH_QB
594
42.7k
    UINT64_C(333),  // ADDUH_QB_MMR2
595
42.7k
    UINT64_C(2080374936), // ADDUH_R_QB
596
42.7k
    UINT64_C(1357), // ADDUH_R_QB_MMR2
597
42.7k
    UINT64_C(336),  // ADDU_MMR6
598
42.7k
    UINT64_C(2080375312), // ADDU_PH
599
42.7k
    UINT64_C(269),  // ADDU_PH_MMR2
600
42.7k
    UINT64_C(2080374800), // ADDU_QB
601
42.7k
    UINT64_C(205),  // ADDU_QB_MM
602
42.7k
    UINT64_C(2080375568), // ADDU_S_PH
603
42.7k
    UINT64_C(1293), // ADDU_S_PH_MMR2
604
42.7k
    UINT64_C(2080375056), // ADDU_S_QB
605
42.7k
    UINT64_C(1229), // ADDU_S_QB_MM
606
42.7k
    UINT64_C(2013265926), // ADDVI_B
607
42.7k
    UINT64_C(2019557382), // ADDVI_D
608
42.7k
    UINT64_C(2015363078), // ADDVI_H
609
42.7k
    UINT64_C(2017460230), // ADDVI_W
610
42.7k
    UINT64_C(2013265934), // ADDV_B
611
42.7k
    UINT64_C(2019557390), // ADDV_D
612
42.7k
    UINT64_C(2015363086), // ADDV_H
613
42.7k
    UINT64_C(2017460238), // ADDV_W
614
42.7k
    UINT64_C(2080375888), // ADDWC
615
42.7k
    UINT64_C(965),  // ADDWC_MM
616
42.7k
    UINT64_C(2013265936), // ADD_A_B
617
42.7k
    UINT64_C(2019557392), // ADD_A_D
618
42.7k
    UINT64_C(2015363088), // ADD_A_H
619
42.7k
    UINT64_C(2017460240), // ADD_A_W
620
42.7k
    UINT64_C(272),  // ADD_MM
621
42.7k
    UINT64_C(272),  // ADD_MMR6
622
42.7k
    UINT64_C(536870912),  // ADDi
623
42.7k
    UINT64_C(268435456),  // ADDi_MM
624
42.7k
    UINT64_C(603979776),  // ADDiu
625
42.7k
    UINT64_C(805306368),  // ADDiu_MM
626
42.7k
    UINT64_C(33), // ADDu
627
42.7k
    UINT64_C(336),  // ADDu_MM
628
42.7k
    UINT64_C(2080375328), // ALIGN
629
42.7k
    UINT64_C(31), // ALIGN_MMR6
630
42.7k
    UINT64_C(3961454592), // ALUIPC
631
42.7k
    UINT64_C(2015297536), // ALUIPC_MMR6
632
42.7k
    UINT64_C(36), // AND
633
42.7k
    UINT64_C(17536),  // AND16_MM
634
42.7k
    UINT64_C(17409),  // AND16_MMR6
635
42.7k
    UINT64_C(36), // AND64
636
42.7k
    UINT64_C(11264),  // ANDI16_MM
637
42.7k
    UINT64_C(11264),  // ANDI16_MMR6
638
42.7k
    UINT64_C(2013265920), // ANDI_B
639
42.7k
    UINT64_C(3489660928), // ANDI_MMR6
640
42.7k
    UINT64_C(592),  // AND_MM
641
42.7k
    UINT64_C(592),  // AND_MMR6
642
42.7k
    UINT64_C(2013265950), // AND_V
643
42.7k
    UINT64_C(805306368),  // ANDi
644
42.7k
    UINT64_C(805306368),  // ANDi64
645
42.7k
    UINT64_C(3489660928), // ANDi_MM
646
42.7k
    UINT64_C(2080374833), // APPEND
647
42.7k
    UINT64_C(533),  // APPEND_MMR2
648
42.7k
    UINT64_C(2046820369), // ASUB_S_B
649
42.7k
    UINT64_C(2053111825), // ASUB_S_D
650
42.7k
    UINT64_C(2048917521), // ASUB_S_H
651
42.7k
    UINT64_C(2051014673), // ASUB_S_W
652
42.7k
    UINT64_C(2055208977), // ASUB_U_B
653
42.7k
    UINT64_C(2061500433), // ASUB_U_D
654
42.7k
    UINT64_C(2057306129), // ASUB_U_H
655
42.7k
    UINT64_C(2059403281), // ASUB_U_W
656
42.7k
    UINT64_C(1006632960), // AUI
657
42.7k
    UINT64_C(3961389056), // AUIPC
658
42.7k
    UINT64_C(2015232000), // AUIPC_MMR6
659
42.7k
    UINT64_C(268435456),  // AUI_MMR6
660
42.7k
    UINT64_C(2063597584), // AVER_S_B
661
42.7k
    UINT64_C(2069889040), // AVER_S_D
662
42.7k
    UINT64_C(2065694736), // AVER_S_H
663
42.7k
    UINT64_C(2067791888), // AVER_S_W
664
42.7k
    UINT64_C(2071986192), // AVER_U_B
665
42.7k
    UINT64_C(2078277648), // AVER_U_D
666
42.7k
    UINT64_C(2074083344), // AVER_U_H
667
42.7k
    UINT64_C(2076180496), // AVER_U_W
668
42.7k
    UINT64_C(2046820368), // AVE_S_B
669
42.7k
    UINT64_C(2053111824), // AVE_S_D
670
42.7k
    UINT64_C(2048917520), // AVE_S_H
671
42.7k
    UINT64_C(2051014672), // AVE_S_W
672
42.7k
    UINT64_C(2055208976), // AVE_U_B
673
42.7k
    UINT64_C(2061500432), // AVE_U_D
674
42.7k
    UINT64_C(2057306128), // AVE_U_H
675
42.7k
    UINT64_C(2059403280), // AVE_U_W
676
42.7k
    UINT64_C(4026550272), // AddiuRxImmX16
677
42.7k
    UINT64_C(4026533888), // AddiuRxPcImmX16
678
42.7k
    UINT64_C(18432),  // AddiuRxRxImm16
679
42.7k
    UINT64_C(4026550272), // AddiuRxRxImmX16
680
42.7k
    UINT64_C(4026548224), // AddiuRxRyOffMemX16
681
42.7k
    UINT64_C(25344),  // AddiuSpImm16
682
42.7k
    UINT64_C(4026544896), // AddiuSpImmX16
683
42.7k
    UINT64_C(57345),  // AdduRxRyRz16
684
42.7k
    UINT64_C(59404),  // AndRxRxRy16
685
42.7k
    UINT64_C(52224),  // B16_MM
686
42.7k
    UINT64_C(1879048232), // BADDu
687
42.7k
    UINT64_C(68222976), // BAL
688
42.7k
    UINT64_C(3892314112), // BALC
689
42.7k
    UINT64_C(3019898880), // BALC_MMR6
690
42.7k
    UINT64_C(2080375857), // BALIGN
691
42.7k
    UINT64_C(2236), // BALIGN_MMR2
692
42.7k
    UINT64_C(3355443200), // BBIT0
693
42.7k
    UINT64_C(3623878656), // BBIT032
694
42.7k
    UINT64_C(3892314112), // BBIT1
695
42.7k
    UINT64_C(4160749568), // BBIT132
696
42.7k
    UINT64_C(3355443200), // BC
697
42.7k
    UINT64_C(52224),  // BC16_MMR6
698
42.7k
    UINT64_C(1159725056), // BC1EQZ
699
42.7k
    UINT64_C(1090519040), // BC1EQZC_MMR6
700
42.7k
    UINT64_C(1157627904), // BC1F
701
42.7k
    UINT64_C(1157758976), // BC1FL
702
42.7k
    UINT64_C(1132462080), // BC1F_MM
703
42.7k
    UINT64_C(1168113664), // BC1NEZ
704
42.7k
    UINT64_C(1092616192), // BC1NEZC_MMR6
705
42.7k
    UINT64_C(1157693440), // BC1T
706
42.7k
    UINT64_C(1157824512), // BC1TL
707
42.7k
    UINT64_C(1134559232), // BC1T_MM
708
42.7k
    UINT64_C(1226833920), // BC2EQZ
709
42.7k
    UINT64_C(1094713344), // BC2EQZC_MMR6
710
42.7k
    UINT64_C(1235222528), // BC2NEZ
711
42.7k
    UINT64_C(1096810496), // BC2NEZC_MMR6
712
42.7k
    UINT64_C(2045771785), // BCLRI_B
713
42.7k
    UINT64_C(2038431753), // BCLRI_D
714
42.7k
    UINT64_C(2044723209), // BCLRI_H
715
42.7k
    UINT64_C(2042626057), // BCLRI_W
716
42.7k
    UINT64_C(2038431757), // BCLR_B
717
42.7k
    UINT64_C(2044723213), // BCLR_D
718
42.7k
    UINT64_C(2040528909), // BCLR_H
719
42.7k
    UINT64_C(2042626061), // BCLR_W
720
42.7k
    UINT64_C(2483027968), // BC_MMR6
721
42.7k
    UINT64_C(268435456),  // BEQ
722
42.7k
    UINT64_C(268435456),  // BEQ64
723
42.7k
    UINT64_C(536870912),  // BEQC
724
42.7k
    UINT64_C(536870912),  // BEQC64
725
42.7k
    UINT64_C(1946157056), // BEQC_MMR6
726
42.7k
    UINT64_C(1342177280), // BEQL
727
42.7k
    UINT64_C(35840),  // BEQZ16_MM
728
42.7k
    UINT64_C(536870912),  // BEQZALC
729
42.7k
    UINT64_C(1946157056), // BEQZALC_MMR6
730
42.7k
    UINT64_C(3623878656), // BEQZC
731
42.7k
    UINT64_C(35840),  // BEQZC16_MMR6
732
42.7k
    UINT64_C(3623878656), // BEQZC64
733
42.7k
    UINT64_C(1088421888), // BEQZC_MM
734
42.7k
    UINT64_C(2147483648), // BEQZC_MMR6
735
42.7k
    UINT64_C(2483027968), // BEQ_MM
736
42.7k
    UINT64_C(1476395008), // BGEC
737
42.7k
    UINT64_C(1476395008), // BGEC64
738
42.7k
    UINT64_C(4093640704), // BGEC_MMR6
739
42.7k
    UINT64_C(402653184),  // BGEUC
740
42.7k
    UINT64_C(402653184),  // BGEUC64
741
42.7k
    UINT64_C(3221225472), // BGEUC_MMR6
742
42.7k
    UINT64_C(67174400), // BGEZ
743
42.7k
    UINT64_C(67174400), // BGEZ64
744
42.7k
    UINT64_C(68222976), // BGEZAL
745
42.7k
    UINT64_C(402653184),  // BGEZALC
746
42.7k
    UINT64_C(3221225472), // BGEZALC_MMR6
747
42.7k
    UINT64_C(68354048), // BGEZALL
748
42.7k
    UINT64_C(1113587712), // BGEZALS_MM
749
42.7k
    UINT64_C(1080033280), // BGEZAL_MM
750
42.7k
    UINT64_C(1476395008), // BGEZC
751
42.7k
    UINT64_C(1476395008), // BGEZC64
752
42.7k
    UINT64_C(4093640704), // BGEZC_MMR6
753
42.7k
    UINT64_C(67305472), // BGEZL
754
42.7k
    UINT64_C(1077936128), // BGEZ_MM
755
42.7k
    UINT64_C(469762048),  // BGTZ
756
42.7k
    UINT64_C(469762048),  // BGTZ64
757
42.7k
    UINT64_C(469762048),  // BGTZALC
758
42.7k
    UINT64_C(3758096384), // BGTZALC_MMR6
759
42.7k
    UINT64_C(1543503872), // BGTZC
760
42.7k
    UINT64_C(1543503872), // BGTZC64
761
42.7k
    UINT64_C(3556769792), // BGTZC_MMR6
762
42.7k
    UINT64_C(1543503872), // BGTZL
763
42.7k
    UINT64_C(1086324736), // BGTZ_MM
764
42.7k
    UINT64_C(2070937609), // BINSLI_B
765
42.7k
    UINT64_C(2063597577), // BINSLI_D
766
42.7k
    UINT64_C(2069889033), // BINSLI_H
767
42.7k
    UINT64_C(2067791881), // BINSLI_W
768
42.7k
    UINT64_C(2063597581), // BINSL_B
769
42.7k
    UINT64_C(2069889037), // BINSL_D
770
42.7k
    UINT64_C(2065694733), // BINSL_H
771
42.7k
    UINT64_C(2067791885), // BINSL_W
772
42.7k
    UINT64_C(2079326217), // BINSRI_B
773
42.7k
    UINT64_C(2071986185), // BINSRI_D
774
42.7k
    UINT64_C(2078277641), // BINSRI_H
775
42.7k
    UINT64_C(2076180489), // BINSRI_W
776
42.7k
    UINT64_C(2071986189), // BINSR_B
777
42.7k
    UINT64_C(2078277645), // BINSR_D
778
42.7k
    UINT64_C(2074083341), // BINSR_H
779
42.7k
    UINT64_C(2076180493), // BINSR_W
780
42.7k
    UINT64_C(2080376530), // BITREV
781
42.7k
    UINT64_C(12604),  // BITREV_MM
782
42.7k
    UINT64_C(2080374816), // BITSWAP
783
42.7k
    UINT64_C(2876), // BITSWAP_MMR6
784
42.7k
    UINT64_C(402653184),  // BLEZ
785
42.7k
    UINT64_C(402653184),  // BLEZ64
786
42.7k
    UINT64_C(402653184),  // BLEZALC
787
42.7k
    UINT64_C(3221225472), // BLEZALC_MMR6
788
42.7k
    UINT64_C(1476395008), // BLEZC
789
42.7k
    UINT64_C(1476395008), // BLEZC64
790
42.7k
    UINT64_C(4093640704), // BLEZC_MMR6
791
42.7k
    UINT64_C(1476395008), // BLEZL
792
42.7k
    UINT64_C(1082130432), // BLEZ_MM
793
42.7k
    UINT64_C(1543503872), // BLTC
794
42.7k
    UINT64_C(1543503872), // BLTC64
795
42.7k
    UINT64_C(3556769792), // BLTC_MMR6
796
42.7k
    UINT64_C(469762048),  // BLTUC
797
42.7k
    UINT64_C(469762048),  // BLTUC64
798
42.7k
    UINT64_C(3758096384), // BLTUC_MMR6
799
42.7k
    UINT64_C(67108864), // BLTZ
800
42.7k
    UINT64_C(67108864), // BLTZ64
801
42.7k
    UINT64_C(68157440), // BLTZAL
802
42.7k
    UINT64_C(469762048),  // BLTZALC
803
42.7k
    UINT64_C(3758096384), // BLTZALC_MMR6
804
42.7k
    UINT64_C(68288512), // BLTZALL
805
42.7k
    UINT64_C(1109393408), // BLTZALS_MM
806
42.7k
    UINT64_C(1075838976), // BLTZAL_MM
807
42.7k
    UINT64_C(1543503872), // BLTZC
808
42.7k
    UINT64_C(1543503872), // BLTZC64
809
42.7k
    UINT64_C(3556769792), // BLTZC_MMR6
810
42.7k
    UINT64_C(67239936), // BLTZL
811
42.7k
    UINT64_C(1073741824), // BLTZ_MM
812
42.7k
    UINT64_C(2013265921), // BMNZI_B
813
42.7k
    UINT64_C(2021654558), // BMNZ_V
814
42.7k
    UINT64_C(2030043137), // BMZI_B
815
42.7k
    UINT64_C(2023751710), // BMZ_V
816
42.7k
    UINT64_C(335544320),  // BNE
817
42.7k
    UINT64_C(335544320),  // BNE64
818
42.7k
    UINT64_C(1610612736), // BNEC
819
42.7k
    UINT64_C(1610612736), // BNEC64
820
42.7k
    UINT64_C(2080374784), // BNEC_MMR6
821
42.7k
    UINT64_C(2062549001), // BNEGI_B
822
42.7k
    UINT64_C(2055208969), // BNEGI_D
823
42.7k
    UINT64_C(2061500425), // BNEGI_H
824
42.7k
    UINT64_C(2059403273), // BNEGI_W
825
42.7k
    UINT64_C(2055208973), // BNEG_B
826
42.7k
    UINT64_C(2061500429), // BNEG_D
827
42.7k
    UINT64_C(2057306125), // BNEG_H
828
42.7k
    UINT64_C(2059403277), // BNEG_W
829
42.7k
    UINT64_C(1409286144), // BNEL
830
42.7k
    UINT64_C(44032),  // BNEZ16_MM
831
42.7k
    UINT64_C(1610612736), // BNEZALC
832
42.7k
    UINT64_C(2080374784), // BNEZALC_MMR6
833
42.7k
    UINT64_C(4160749568), // BNEZC
834
42.7k
    UINT64_C(44032),  // BNEZC16_MMR6
835
42.7k
    UINT64_C(4160749568), // BNEZC64
836
42.7k
    UINT64_C(1084227584), // BNEZC_MM
837
42.7k
    UINT64_C(2684354560), // BNEZC_MMR6
838
42.7k
    UINT64_C(3019898880), // BNE_MM
839
42.7k
    UINT64_C(1610612736), // BNVC
840
42.7k
    UINT64_C(2080374784), // BNVC_MMR6
841
42.7k
    UINT64_C(1199570944), // BNZ_B
842
42.7k
    UINT64_C(1205862400), // BNZ_D
843
42.7k
    UINT64_C(1201668096), // BNZ_H
844
42.7k
    UINT64_C(1172307968), // BNZ_V
845
42.7k
    UINT64_C(1203765248), // BNZ_W
846
42.7k
    UINT64_C(536870912),  // BOVC
847
42.7k
    UINT64_C(1946157056), // BOVC_MMR6
848
42.7k
    UINT64_C(68943872), // BPOSGE32
849
42.7k
    UINT64_C(1126170624), // BPOSGE32C_MMR3
850
42.7k
    UINT64_C(1130364928), // BPOSGE32_MM
851
42.7k
    UINT64_C(13), // BREAK
852
42.7k
    UINT64_C(18048),  // BREAK16_MM
853
42.7k
    UINT64_C(17435),  // BREAK16_MMR6
854
42.7k
    UINT64_C(7),  // BREAK_MM
855
42.7k
    UINT64_C(7),  // BREAK_MMR6
856
42.7k
    UINT64_C(2046820353), // BSELI_B
857
42.7k
    UINT64_C(2025848862), // BSEL_V
858
42.7k
    UINT64_C(2054160393), // BSETI_B
859
42.7k
    UINT64_C(2046820361), // BSETI_D
860
42.7k
    UINT64_C(2053111817), // BSETI_H
861
42.7k
    UINT64_C(2051014665), // BSETI_W
862
42.7k
    UINT64_C(2046820365), // BSET_B
863
42.7k
    UINT64_C(2053111821), // BSET_D
864
42.7k
    UINT64_C(2048917517), // BSET_H
865
42.7k
    UINT64_C(2051014669), // BSET_W
866
42.7k
    UINT64_C(1191182336), // BZ_B
867
42.7k
    UINT64_C(1197473792), // BZ_D
868
42.7k
    UINT64_C(1193279488), // BZ_H
869
42.7k
    UINT64_C(1163919360), // BZ_V
870
42.7k
    UINT64_C(1195376640), // BZ_W
871
42.7k
    UINT64_C(8192), // BeqzRxImm16
872
42.7k
    UINT64_C(4026540032), // BeqzRxImmX16
873
42.7k
    UINT64_C(4096), // Bimm16
874
42.7k
    UINT64_C(4026535936), // BimmX16
875
42.7k
    UINT64_C(10240),  // BnezRxImm16
876
42.7k
    UINT64_C(4026542080), // BnezRxImmX16
877
42.7k
    UINT64_C(59397),  // Break16
878
42.7k
    UINT64_C(24576),  // Bteqz16
879
42.7k
    UINT64_C(4026544128), // BteqzX16
880
42.7k
    UINT64_C(24832),  // Btnez16
881
42.7k
    UINT64_C(4026544384), // BtnezX16
882
42.7k
    UINT64_C(3154116608), // CACHE
883
42.7k
    UINT64_C(2080374811), // CACHEE
884
42.7k
    UINT64_C(1610655232), // CACHEE_MM
885
42.7k
    UINT64_C(536895488),  // CACHE_MM
886
42.7k
    UINT64_C(536895488),  // CACHE_MMR6
887
42.7k
    UINT64_C(2080374821), // CACHE_R6
888
42.7k
    UINT64_C(1176502282), // CEIL_L_D64
889
42.7k
    UINT64_C(1409307451), // CEIL_L_D_MMR6
890
42.7k
    UINT64_C(1174405130), // CEIL_L_S
891
42.7k
    UINT64_C(1409291067), // CEIL_L_S_MMR6
892
42.7k
    UINT64_C(1176502286), // CEIL_W_D32
893
42.7k
    UINT64_C(1176502286), // CEIL_W_D64
894
42.7k
    UINT64_C(1409309499), // CEIL_W_D_MMR6
895
42.7k
    UINT64_C(1409309499), // CEIL_W_MM
896
42.7k
    UINT64_C(1174405134), // CEIL_W_S
897
42.7k
    UINT64_C(1409293115), // CEIL_W_S_MM
898
42.7k
    UINT64_C(1409293115), // CEIL_W_S_MMR6
899
42.7k
    UINT64_C(2013265927), // CEQI_B
900
42.7k
    UINT64_C(2019557383), // CEQI_D
901
42.7k
    UINT64_C(2015363079), // CEQI_H
902
42.7k
    UINT64_C(2017460231), // CEQI_W
903
42.7k
    UINT64_C(2013265935), // CEQ_B
904
42.7k
    UINT64_C(2019557391), // CEQ_D
905
42.7k
    UINT64_C(2015363087), // CEQ_H
906
42.7k
    UINT64_C(2017460239), // CEQ_W
907
42.7k
    UINT64_C(1145044992), // CFC1
908
42.7k
    UINT64_C(1409290299), // CFC1_MM
909
42.7k
    UINT64_C(52540),  // CFC2_MM
910
42.7k
    UINT64_C(2021523481), // CFCMSA
911
42.7k
    UINT64_C(1879048242), // CINS
912
42.7k
    UINT64_C(1879048243), // CINS32
913
42.7k
    UINT64_C(1879048242), // CINS64_32
914
42.7k
    UINT64_C(1879048242), // CINS_i32
915
42.7k
    UINT64_C(1176502299), // CLASS_D
916
42.7k
    UINT64_C(1409286752), // CLASS_D_MMR6
917
42.7k
    UINT64_C(1174405147), // CLASS_S
918
42.7k
    UINT64_C(1409286240), // CLASS_S_MMR6
919
42.7k
    UINT64_C(2046820359), // CLEI_S_B
920
42.7k
    UINT64_C(2053111815), // CLEI_S_D
921
42.7k
    UINT64_C(2048917511), // CLEI_S_H
922
42.7k
    UINT64_C(2051014663), // CLEI_S_W
923
42.7k
    UINT64_C(2055208967), // CLEI_U_B
924
42.7k
    UINT64_C(2061500423), // CLEI_U_D
925
42.7k
    UINT64_C(2057306119), // CLEI_U_H
926
42.7k
    UINT64_C(2059403271), // CLEI_U_W
927
42.7k
    UINT64_C(2046820367), // CLE_S_B
928
42.7k
    UINT64_C(2053111823), // CLE_S_D
929
42.7k
    UINT64_C(2048917519), // CLE_S_H
930
42.7k
    UINT64_C(2051014671), // CLE_S_W
931
42.7k
    UINT64_C(2055208975), // CLE_U_B
932
42.7k
    UINT64_C(2061500431), // CLE_U_D
933
42.7k
    UINT64_C(2057306127), // CLE_U_H
934
42.7k
    UINT64_C(2059403279), // CLE_U_W
935
42.7k
    UINT64_C(1879048225), // CLO
936
42.7k
    UINT64_C(19260),  // CLO_MM
937
42.7k
    UINT64_C(19260),  // CLO_MMR6
938
42.7k
    UINT64_C(81), // CLO_R6
939
42.7k
    UINT64_C(2030043143), // CLTI_S_B
940
42.7k
    UINT64_C(2036334599), // CLTI_S_D
941
42.7k
    UINT64_C(2032140295), // CLTI_S_H
942
42.7k
    UINT64_C(2034237447), // CLTI_S_W
943
42.7k
    UINT64_C(2038431751), // CLTI_U_B
944
42.7k
    UINT64_C(2044723207), // CLTI_U_D
945
42.7k
    UINT64_C(2040528903), // CLTI_U_H
946
42.7k
    UINT64_C(2042626055), // CLTI_U_W
947
42.7k
    UINT64_C(2030043151), // CLT_S_B
948
42.7k
    UINT64_C(2036334607), // CLT_S_D
949
42.7k
    UINT64_C(2032140303), // CLT_S_H
950
42.7k
    UINT64_C(2034237455), // CLT_S_W
951
42.7k
    UINT64_C(2038431759), // CLT_U_B
952
42.7k
    UINT64_C(2044723215), // CLT_U_D
953
42.7k
    UINT64_C(2040528911), // CLT_U_H
954
42.7k
    UINT64_C(2042626063), // CLT_U_W
955
42.7k
    UINT64_C(1879048224), // CLZ
956
42.7k
    UINT64_C(23356),  // CLZ_MM
957
42.7k
    UINT64_C(80), // CLZ_MMR6
958
42.7k
    UINT64_C(80), // CLZ_R6
959
42.7k
    UINT64_C(2080376337), // CMPGDU_EQ_QB
960
42.7k
    UINT64_C(389),  // CMPGDU_EQ_QB_MMR2
961
42.7k
    UINT64_C(2080376465), // CMPGDU_LE_QB
962
42.7k
    UINT64_C(517),  // CMPGDU_LE_QB_MMR2
963
42.7k
    UINT64_C(2080376401), // CMPGDU_LT_QB
964
42.7k
    UINT64_C(453),  // CMPGDU_LT_QB_MMR2
965
42.7k
    UINT64_C(2080375057), // CMPGU_EQ_QB
966
42.7k
    UINT64_C(1476395205), // CMPGU_EQ_QB_MM
967
42.7k
    UINT64_C(2080375185), // CMPGU_LE_QB
968
42.7k
    UINT64_C(1476395333), // CMPGU_LE_QB_MM
969
42.7k
    UINT64_C(2080375121), // CMPGU_LT_QB
970
42.7k
    UINT64_C(1476395269), // CMPGU_LT_QB_MM
971
42.7k
    UINT64_C(2080374801), // CMPU_EQ_QB
972
42.7k
    UINT64_C(581),  // CMPU_EQ_QB_MM
973
42.7k
    UINT64_C(2080374929), // CMPU_LE_QB
974
42.7k
    UINT64_C(709),  // CMPU_LE_QB_MM
975
42.7k
    UINT64_C(2080374865), // CMPU_LT_QB
976
42.7k
    UINT64_C(645),  // CMPU_LT_QB_MM
977
42.7k
    UINT64_C(1409286165), // CMP_AF_D_MMR6
978
42.7k
    UINT64_C(1409286149), // CMP_AF_S_MMR6
979
42.7k
    UINT64_C(1184890882), // CMP_EQ_D
980
42.7k
    UINT64_C(1409286293), // CMP_EQ_D_MMR6
981
42.7k
    UINT64_C(2080375313), // CMP_EQ_PH
982
42.7k
    UINT64_C(5),  // CMP_EQ_PH_MM
983
42.7k
    UINT64_C(1182793730), // CMP_EQ_S
984
42.7k
    UINT64_C(1409286277), // CMP_EQ_S_MMR6
985
42.7k
    UINT64_C(1184890880), // CMP_F_D
986
42.7k
    UINT64_C(1182793728), // CMP_F_S
987
42.7k
    UINT64_C(1184890886), // CMP_LE_D
988
42.7k
    UINT64_C(1409286549), // CMP_LE_D_MMR6
989
42.7k
    UINT64_C(2080375441), // CMP_LE_PH
990
42.7k
    UINT64_C(133),  // CMP_LE_PH_MM
991
42.7k
    UINT64_C(1182793734), // CMP_LE_S
992
42.7k
    UINT64_C(1409286533), // CMP_LE_S_MMR6
993
42.7k
    UINT64_C(1184890884), // CMP_LT_D
994
42.7k
    UINT64_C(1409286421), // CMP_LT_D_MMR6
995
42.7k
    UINT64_C(2080375377), // CMP_LT_PH
996
42.7k
    UINT64_C(69), // CMP_LT_PH_MM
997
42.7k
    UINT64_C(1182793732), // CMP_LT_S
998
42.7k
    UINT64_C(1409286405), // CMP_LT_S_MMR6
999
42.7k
    UINT64_C(1184890888), // CMP_SAF_D
1000
42.7k
    UINT64_C(1409286677), // CMP_SAF_D_MMR6
1001
42.7k
    UINT64_C(1182793736), // CMP_SAF_S
1002
42.7k
    UINT64_C(1409286661), // CMP_SAF_S_MMR6
1003
42.7k
    UINT64_C(1184890890), // CMP_SEQ_D
1004
42.7k
    UINT64_C(1409286805), // CMP_SEQ_D_MMR6
1005
42.7k
    UINT64_C(1182793738), // CMP_SEQ_S
1006
42.7k
    UINT64_C(1409286789), // CMP_SEQ_S_MMR6
1007
42.7k
    UINT64_C(1184890894), // CMP_SLE_D
1008
42.7k
    UINT64_C(1409287061), // CMP_SLE_D_MMR6
1009
42.7k
    UINT64_C(1182793742), // CMP_SLE_S
1010
42.7k
    UINT64_C(1409287045), // CMP_SLE_S_MMR6
1011
42.7k
    UINT64_C(1184890892), // CMP_SLT_D
1012
42.7k
    UINT64_C(1409286933), // CMP_SLT_D_MMR6
1013
42.7k
    UINT64_C(1182793740), // CMP_SLT_S
1014
42.7k
    UINT64_C(1409286917), // CMP_SLT_S_MMR6
1015
42.7k
    UINT64_C(1184890891), // CMP_SUEQ_D
1016
42.7k
    UINT64_C(1409286869), // CMP_SUEQ_D_MMR6
1017
42.7k
    UINT64_C(1182793739), // CMP_SUEQ_S
1018
42.7k
    UINT64_C(1409286853), // CMP_SUEQ_S_MMR6
1019
42.7k
    UINT64_C(1184890895), // CMP_SULE_D
1020
42.7k
    UINT64_C(1409287125), // CMP_SULE_D_MMR6
1021
42.7k
    UINT64_C(1182793743), // CMP_SULE_S
1022
42.7k
    UINT64_C(1409287109), // CMP_SULE_S_MMR6
1023
42.7k
    UINT64_C(1184890893), // CMP_SULT_D
1024
42.7k
    UINT64_C(1409286997), // CMP_SULT_D_MMR6
1025
42.7k
    UINT64_C(1182793741), // CMP_SULT_S
1026
42.7k
    UINT64_C(1409286981), // CMP_SULT_S_MMR6
1027
42.7k
    UINT64_C(1184890889), // CMP_SUN_D
1028
42.7k
    UINT64_C(1409286741), // CMP_SUN_D_MMR6
1029
42.7k
    UINT64_C(1182793737), // CMP_SUN_S
1030
42.7k
    UINT64_C(1409286725), // CMP_SUN_S_MMR6
1031
42.7k
    UINT64_C(1184890883), // CMP_UEQ_D
1032
42.7k
    UINT64_C(1409286357), // CMP_UEQ_D_MMR6
1033
42.7k
    UINT64_C(1182793731), // CMP_UEQ_S
1034
42.7k
    UINT64_C(1409286341), // CMP_UEQ_S_MMR6
1035
42.7k
    UINT64_C(1184890887), // CMP_ULE_D
1036
42.7k
    UINT64_C(1409286613), // CMP_ULE_D_MMR6
1037
42.7k
    UINT64_C(1182793735), // CMP_ULE_S
1038
42.7k
    UINT64_C(1409286597), // CMP_ULE_S_MMR6
1039
42.7k
    UINT64_C(1184890885), // CMP_ULT_D
1040
42.7k
    UINT64_C(1409286485), // CMP_ULT_D_MMR6
1041
42.7k
    UINT64_C(1182793733), // CMP_ULT_S
1042
42.7k
    UINT64_C(1409286469), // CMP_ULT_S_MMR6
1043
42.7k
    UINT64_C(1184890881), // CMP_UN_D
1044
42.7k
    UINT64_C(1409286229), // CMP_UN_D_MMR6
1045
42.7k
    UINT64_C(1182793729), // CMP_UN_S
1046
42.7k
    UINT64_C(1409286213), // CMP_UN_S_MMR6
1047
42.7k
    UINT64_C(2021654553), // COPY_S_B
1048
42.7k
    UINT64_C(2025324569), // COPY_S_D
1049
42.7k
    UINT64_C(2023751705), // COPY_S_H
1050
42.7k
    UINT64_C(2024800281), // COPY_S_W
1051
42.7k
    UINT64_C(2025848857), // COPY_U_B
1052
42.7k
    UINT64_C(2027946009), // COPY_U_H
1053
42.7k
    UINT64_C(2028994585), // COPY_U_W
1054
42.7k
    UINT64_C(2080374799), // CRC32B
1055
42.7k
    UINT64_C(2080375055), // CRC32CB
1056
42.7k
    UINT64_C(2080375247), // CRC32CD
1057
42.7k
    UINT64_C(2080375119), // CRC32CH
1058
42.7k
    UINT64_C(2080375183), // CRC32CW
1059
42.7k
    UINT64_C(2080374991), // CRC32D
1060
42.7k
    UINT64_C(2080374863), // CRC32H
1061
42.7k
    UINT64_C(2080374927), // CRC32W
1062
42.7k
    UINT64_C(1153433600), // CTC1
1063
42.7k
    UINT64_C(1409292347), // CTC1_MM
1064
42.7k
    UINT64_C(56636),  // CTC2_MM
1065
42.7k
    UINT64_C(2017329177), // CTCMSA
1066
42.7k
    UINT64_C(1174405153), // CVT_D32_S
1067
42.7k
    UINT64_C(1409291131), // CVT_D32_S_MM
1068
42.7k
    UINT64_C(1182793761), // CVT_D32_W
1069
42.7k
    UINT64_C(1409299323), // CVT_D32_W_MM
1070
42.7k
    UINT64_C(1184890913), // CVT_D64_L
1071
42.7k
    UINT64_C(1174405153), // CVT_D64_S
1072
42.7k
    UINT64_C(1409291131), // CVT_D64_S_MM
1073
42.7k
    UINT64_C(1182793761), // CVT_D64_W
1074
42.7k
    UINT64_C(1409299323), // CVT_D64_W_MM
1075
42.7k
    UINT64_C(1409307515), // CVT_D_L_MMR6
1076
42.7k
    UINT64_C(1176502309), // CVT_L_D64
1077
42.7k
    UINT64_C(1409302843), // CVT_L_D64_MM
1078
42.7k
    UINT64_C(1409302843), // CVT_L_D_MMR6
1079
42.7k
    UINT64_C(1174405157), // CVT_L_S
1080
42.7k
    UINT64_C(1409286459), // CVT_L_S_MM
1081
42.7k
    UINT64_C(1409286459), // CVT_L_S_MMR6
1082
42.7k
    UINT64_C(1174405158), // CVT_PS_S64
1083
42.7k
    UINT64_C(1176502304), // CVT_S_D32
1084
42.7k
    UINT64_C(1409293179), // CVT_S_D32_MM
1085
42.7k
    UINT64_C(1176502304), // CVT_S_D64
1086
42.7k
    UINT64_C(1409293179), // CVT_S_D64_MM
1087
42.7k
    UINT64_C(1184890912), // CVT_S_L
1088
42.7k
    UINT64_C(1409309563), // CVT_S_L_MMR6
1089
42.7k
    UINT64_C(1186988072), // CVT_S_PL64
1090
42.7k
    UINT64_C(1186988064), // CVT_S_PU64
1091
42.7k
    UINT64_C(1182793760), // CVT_S_W
1092
42.7k
    UINT64_C(1409301371), // CVT_S_W_MM
1093
42.7k
    UINT64_C(1409301371), // CVT_S_W_MMR6
1094
42.7k
    UINT64_C(1176502308), // CVT_W_D32
1095
42.7k
    UINT64_C(1409304891), // CVT_W_D32_MM
1096
42.7k
    UINT64_C(1176502308), // CVT_W_D64
1097
42.7k
    UINT64_C(1409304891), // CVT_W_D64_MM
1098
42.7k
    UINT64_C(1174405156), // CVT_W_S
1099
42.7k
    UINT64_C(1409288507), // CVT_W_S_MM
1100
42.7k
    UINT64_C(1409288507), // CVT_W_S_MMR6
1101
42.7k
    UINT64_C(1176502322), // C_EQ_D32
1102
42.7k
    UINT64_C(1409287356), // C_EQ_D32_MM
1103
42.7k
    UINT64_C(1176502322), // C_EQ_D64
1104
42.7k
    UINT64_C(1409287356), // C_EQ_D64_MM
1105
42.7k
    UINT64_C(1174405170), // C_EQ_S
1106
42.7k
    UINT64_C(1409286332), // C_EQ_S_MM
1107
42.7k
    UINT64_C(1176502320), // C_F_D32
1108
42.7k
    UINT64_C(1409287228), // C_F_D32_MM
1109
42.7k
    UINT64_C(1176502320), // C_F_D64
1110
42.7k
    UINT64_C(1409287228), // C_F_D64_MM
1111
42.7k
    UINT64_C(1174405168), // C_F_S
1112
42.7k
    UINT64_C(1409286204), // C_F_S_MM
1113
42.7k
    UINT64_C(1176502334), // C_LE_D32
1114
42.7k
    UINT64_C(1409288124), // C_LE_D32_MM
1115
42.7k
    UINT64_C(1176502334), // C_LE_D64
1116
42.7k
    UINT64_C(1409288124), // C_LE_D64_MM
1117
42.7k
    UINT64_C(1174405182), // C_LE_S
1118
42.7k
    UINT64_C(1409287100), // C_LE_S_MM
1119
42.7k
    UINT64_C(1176502332), // C_LT_D32
1120
42.7k
    UINT64_C(1409287996), // C_LT_D32_MM
1121
42.7k
    UINT64_C(1176502332), // C_LT_D64
1122
42.7k
    UINT64_C(1409287996), // C_LT_D64_MM
1123
42.7k
    UINT64_C(1174405180), // C_LT_S
1124
42.7k
    UINT64_C(1409286972), // C_LT_S_MM
1125
42.7k
    UINT64_C(1176502333), // C_NGE_D32
1126
42.7k
    UINT64_C(1409288060), // C_NGE_D32_MM
1127
42.7k
    UINT64_C(1176502333), // C_NGE_D64
1128
42.7k
    UINT64_C(1409288060), // C_NGE_D64_MM
1129
42.7k
    UINT64_C(1174405181), // C_NGE_S
1130
42.7k
    UINT64_C(1409287036), // C_NGE_S_MM
1131
42.7k
    UINT64_C(1176502329), // C_NGLE_D32
1132
42.7k
    UINT64_C(1409287804), // C_NGLE_D32_MM
1133
42.7k
    UINT64_C(1176502329), // C_NGLE_D64
1134
42.7k
    UINT64_C(1409287804), // C_NGLE_D64_MM
1135
42.7k
    UINT64_C(1174405177), // C_NGLE_S
1136
42.7k
    UINT64_C(1409286780), // C_NGLE_S_MM
1137
42.7k
    UINT64_C(1176502331), // C_NGL_D32
1138
42.7k
    UINT64_C(1409287932), // C_NGL_D32_MM
1139
42.7k
    UINT64_C(1176502331), // C_NGL_D64
1140
42.7k
    UINT64_C(1409287932), // C_NGL_D64_MM
1141
42.7k
    UINT64_C(1174405179), // C_NGL_S
1142
42.7k
    UINT64_C(1409286908), // C_NGL_S_MM
1143
42.7k
    UINT64_C(1176502335), // C_NGT_D32
1144
42.7k
    UINT64_C(1409288188), // C_NGT_D32_MM
1145
42.7k
    UINT64_C(1176502335), // C_NGT_D64
1146
42.7k
    UINT64_C(1409288188), // C_NGT_D64_MM
1147
42.7k
    UINT64_C(1174405183), // C_NGT_S
1148
42.7k
    UINT64_C(1409287164), // C_NGT_S_MM
1149
42.7k
    UINT64_C(1176502326), // C_OLE_D32
1150
42.7k
    UINT64_C(1409287612), // C_OLE_D32_MM
1151
42.7k
    UINT64_C(1176502326), // C_OLE_D64
1152
42.7k
    UINT64_C(1409287612), // C_OLE_D64_MM
1153
42.7k
    UINT64_C(1174405174), // C_OLE_S
1154
42.7k
    UINT64_C(1409286588), // C_OLE_S_MM
1155
42.7k
    UINT64_C(1176502324), // C_OLT_D32
1156
42.7k
    UINT64_C(1409287484), // C_OLT_D32_MM
1157
42.7k
    UINT64_C(1176502324), // C_OLT_D64
1158
42.7k
    UINT64_C(1409287484), // C_OLT_D64_MM
1159
42.7k
    UINT64_C(1174405172), // C_OLT_S
1160
42.7k
    UINT64_C(1409286460), // C_OLT_S_MM
1161
42.7k
    UINT64_C(1176502330), // C_SEQ_D32
1162
42.7k
    UINT64_C(1409287868), // C_SEQ_D32_MM
1163
42.7k
    UINT64_C(1176502330), // C_SEQ_D64
1164
42.7k
    UINT64_C(1409287868), // C_SEQ_D64_MM
1165
42.7k
    UINT64_C(1174405178), // C_SEQ_S
1166
42.7k
    UINT64_C(1409286844), // C_SEQ_S_MM
1167
42.7k
    UINT64_C(1176502328), // C_SF_D32
1168
42.7k
    UINT64_C(1409287740), // C_SF_D32_MM
1169
42.7k
    UINT64_C(1176502328), // C_SF_D64
1170
42.7k
    UINT64_C(1409287740), // C_SF_D64_MM
1171
42.7k
    UINT64_C(1174405176), // C_SF_S
1172
42.7k
    UINT64_C(1409286716), // C_SF_S_MM
1173
42.7k
    UINT64_C(1176502323), // C_UEQ_D32
1174
42.7k
    UINT64_C(1409287420), // C_UEQ_D32_MM
1175
42.7k
    UINT64_C(1176502323), // C_UEQ_D64
1176
42.7k
    UINT64_C(1409287420), // C_UEQ_D64_MM
1177
42.7k
    UINT64_C(1174405171), // C_UEQ_S
1178
42.7k
    UINT64_C(1409286396), // C_UEQ_S_MM
1179
42.7k
    UINT64_C(1176502327), // C_ULE_D32
1180
42.7k
    UINT64_C(1409287676), // C_ULE_D32_MM
1181
42.7k
    UINT64_C(1176502327), // C_ULE_D64
1182
42.7k
    UINT64_C(1409287676), // C_ULE_D64_MM
1183
42.7k
    UINT64_C(1174405175), // C_ULE_S
1184
42.7k
    UINT64_C(1409286652), // C_ULE_S_MM
1185
42.7k
    UINT64_C(1176502325), // C_ULT_D32
1186
42.7k
    UINT64_C(1409287548), // C_ULT_D32_MM
1187
42.7k
    UINT64_C(1176502325), // C_ULT_D64
1188
42.7k
    UINT64_C(1409287548), // C_ULT_D64_MM
1189
42.7k
    UINT64_C(1174405173), // C_ULT_S
1190
42.7k
    UINT64_C(1409286524), // C_ULT_S_MM
1191
42.7k
    UINT64_C(1176502321), // C_UN_D32
1192
42.7k
    UINT64_C(1409287292), // C_UN_D32_MM
1193
42.7k
    UINT64_C(1176502321), // C_UN_D64
1194
42.7k
    UINT64_C(1409287292), // C_UN_D64_MM
1195
42.7k
    UINT64_C(1174405169), // C_UN_S
1196
42.7k
    UINT64_C(1409286268), // C_UN_S_MM
1197
42.7k
    UINT64_C(59402),  // CmpRxRy16
1198
42.7k
    UINT64_C(28672),  // CmpiRxImm16
1199
42.7k
    UINT64_C(4026560512), // CmpiRxImmX16
1200
42.7k
    UINT64_C(44), // DADD
1201
42.7k
    UINT64_C(1610612736), // DADDi
1202
42.7k
    UINT64_C(1677721600), // DADDiu
1203
42.7k
    UINT64_C(45), // DADDu
1204
42.7k
    UINT64_C(67502080), // DAHI
1205
42.7k
    UINT64_C(2080375332), // DALIGN
1206
42.7k
    UINT64_C(69074944), // DATI
1207
42.7k
    UINT64_C(1946157056), // DAUI
1208
42.7k
    UINT64_C(2080374820), // DBITSWAP
1209
42.7k
    UINT64_C(1879048229), // DCLO
1210
42.7k
    UINT64_C(83), // DCLO_R6
1211
42.7k
    UINT64_C(1879048228), // DCLZ
1212
42.7k
    UINT64_C(82), // DCLZ_R6
1213
42.7k
    UINT64_C(158),  // DDIV
1214
42.7k
    UINT64_C(159),  // DDIVU
1215
42.7k
    UINT64_C(1107296287), // DERET
1216
42.7k
    UINT64_C(58236),  // DERET_MM
1217
42.7k
    UINT64_C(58236),  // DERET_MMR6
1218
42.7k
    UINT64_C(2080374787), // DEXT
1219
42.7k
    UINT64_C(2080374787), // DEXT64_32
1220
42.7k
    UINT64_C(2080374785), // DEXTM
1221
42.7k
    UINT64_C(2080374786), // DEXTU
1222
42.7k
    UINT64_C(1096835072), // DI
1223
42.7k
    UINT64_C(2080374791), // DINS
1224
42.7k
    UINT64_C(2080374789), // DINSM
1225
42.7k
    UINT64_C(2080374790), // DINSU
1226
42.7k
    UINT64_C(154),  // DIV
1227
42.7k
    UINT64_C(155),  // DIVU
1228
42.7k
    UINT64_C(408),  // DIVU_MMR6
1229
42.7k
    UINT64_C(280),  // DIV_MMR6
1230
42.7k
    UINT64_C(2046820370), // DIV_S_B
1231
42.7k
    UINT64_C(2053111826), // DIV_S_D
1232
42.7k
    UINT64_C(2048917522), // DIV_S_H
1233
42.7k
    UINT64_C(2051014674), // DIV_S_W
1234
42.7k
    UINT64_C(2055208978), // DIV_U_B
1235
42.7k
    UINT64_C(2061500434), // DIV_U_D
1236
42.7k
    UINT64_C(2057306130), // DIV_U_H
1237
42.7k
    UINT64_C(2059403282), // DIV_U_W
1238
42.7k
    UINT64_C(18300),  // DI_MM
1239
42.7k
    UINT64_C(18300),  // DI_MMR6
1240
42.7k
    UINT64_C(21), // DLSA
1241
42.7k
    UINT64_C(21), // DLSA_R6
1242
42.7k
    UINT64_C(1075838976), // DMFC0
1243
42.7k
    UINT64_C(1142947840), // DMFC1
1244
42.7k
    UINT64_C(1210056704), // DMFC2
1245
42.7k
    UINT64_C(1210056704), // DMFC2_OCTEON
1246
42.7k
    UINT64_C(1080033536), // DMFGC0
1247
42.7k
    UINT64_C(222),  // DMOD
1248
42.7k
    UINT64_C(223),  // DMODU
1249
42.7k
    UINT64_C(1096813505), // DMT
1250
42.7k
    UINT64_C(1084227584), // DMTC0
1251
42.7k
    UINT64_C(1151336448), // DMTC1
1252
42.7k
    UINT64_C(1218445312), // DMTC2
1253
42.7k
    UINT64_C(1218445312), // DMTC2_OCTEON
1254
42.7k
    UINT64_C(1080034048), // DMTGC0
1255
42.7k
    UINT64_C(220),  // DMUH
1256
42.7k
    UINT64_C(221),  // DMUHU
1257
42.7k
    UINT64_C(1879048195), // DMUL
1258
42.7k
    UINT64_C(28), // DMULT
1259
42.7k
    UINT64_C(29), // DMULTu
1260
42.7k
    UINT64_C(157),  // DMULU
1261
42.7k
    UINT64_C(156),  // DMUL_R6
1262
42.7k
    UINT64_C(2019557395), // DOTP_S_D
1263
42.7k
    UINT64_C(2015363091), // DOTP_S_H
1264
42.7k
    UINT64_C(2017460243), // DOTP_S_W
1265
42.7k
    UINT64_C(2027946003), // DOTP_U_D
1266
42.7k
    UINT64_C(2023751699), // DOTP_U_H
1267
42.7k
    UINT64_C(2025848851), // DOTP_U_W
1268
42.7k
    UINT64_C(2036334611), // DPADD_S_D
1269
42.7k
    UINT64_C(2032140307), // DPADD_S_H
1270
42.7k
    UINT64_C(2034237459), // DPADD_S_W
1271
42.7k
    UINT64_C(2044723219), // DPADD_U_D
1272
42.7k
    UINT64_C(2040528915), // DPADD_U_H
1273
42.7k
    UINT64_C(2042626067), // DPADD_U_W
1274
42.7k
    UINT64_C(2080376496), // DPAQX_SA_W_PH
1275
42.7k
    UINT64_C(12988),  // DPAQX_SA_W_PH_MMR2
1276
42.7k
    UINT64_C(2080376368), // DPAQX_S_W_PH
1277
42.7k
    UINT64_C(8892), // DPAQX_S_W_PH_MMR2
1278
42.7k
    UINT64_C(2080375600), // DPAQ_SA_L_W
1279
42.7k
    UINT64_C(4796), // DPAQ_SA_L_W_MM
1280
42.7k
    UINT64_C(2080375088), // DPAQ_S_W_PH
1281
42.7k
    UINT64_C(700),  // DPAQ_S_W_PH_MM
1282
42.7k
    UINT64_C(2080375024), // DPAU_H_QBL
1283
42.7k
    UINT64_C(8380), // DPAU_H_QBL_MM
1284
42.7k
    UINT64_C(2080375280), // DPAU_H_QBR
1285
42.7k
    UINT64_C(12476),  // DPAU_H_QBR_MM
1286
42.7k
    UINT64_C(2080375344), // DPAX_W_PH
1287
42.7k
    UINT64_C(4284), // DPAX_W_PH_MMR2
1288
42.7k
    UINT64_C(2080374832), // DPA_W_PH
1289
42.7k
    UINT64_C(188),  // DPA_W_PH_MMR2
1290
42.7k
    UINT64_C(1879048237), // DPOP
1291
42.7k
    UINT64_C(2080376560), // DPSQX_SA_W_PH
1292
42.7k
    UINT64_C(14012),  // DPSQX_SA_W_PH_MMR2
1293
42.7k
    UINT64_C(2080376432), // DPSQX_S_W_PH
1294
42.7k
    UINT64_C(9916), // DPSQX_S_W_PH_MMR2
1295
42.7k
    UINT64_C(2080375664), // DPSQ_SA_L_W
1296
42.7k
    UINT64_C(5820), // DPSQ_SA_L_W_MM
1297
42.7k
    UINT64_C(2080375152), // DPSQ_S_W_PH
1298
42.7k
    UINT64_C(1724), // DPSQ_S_W_PH_MM
1299
42.7k
    UINT64_C(2053111827), // DPSUB_S_D
1300
42.7k
    UINT64_C(2048917523), // DPSUB_S_H
1301
42.7k
    UINT64_C(2051014675), // DPSUB_S_W
1302
42.7k
    UINT64_C(2061500435), // DPSUB_U_D
1303
42.7k
    UINT64_C(2057306131), // DPSUB_U_H
1304
42.7k
    UINT64_C(2059403283), // DPSUB_U_W
1305
42.7k
    UINT64_C(2080375536), // DPSU_H_QBL
1306
42.7k
    UINT64_C(9404), // DPSU_H_QBL_MM
1307
42.7k
    UINT64_C(2080375792), // DPSU_H_QBR
1308
42.7k
    UINT64_C(13500),  // DPSU_H_QBR_MM
1309
42.7k
    UINT64_C(2080375408), // DPSX_W_PH
1310
42.7k
    UINT64_C(5308), // DPSX_W_PH_MMR2
1311
42.7k
    UINT64_C(2080374896), // DPS_W_PH
1312
42.7k
    UINT64_C(1212), // DPS_W_PH_MMR2
1313
42.7k
    UINT64_C(2097210),  // DROTR
1314
42.7k
    UINT64_C(2097214),  // DROTR32
1315
42.7k
    UINT64_C(86), // DROTRV
1316
42.7k
    UINT64_C(2080374948), // DSBH
1317
42.7k
    UINT64_C(30), // DSDIV
1318
42.7k
    UINT64_C(2080375140), // DSHD
1319
42.7k
    UINT64_C(56), // DSLL
1320
42.7k
    UINT64_C(60), // DSLL32
1321
42.7k
    UINT64_C(60), // DSLL64_32
1322
42.7k
    UINT64_C(20), // DSLLV
1323
42.7k
    UINT64_C(59), // DSRA
1324
42.7k
    UINT64_C(63), // DSRA32
1325
42.7k
    UINT64_C(23), // DSRAV
1326
42.7k
    UINT64_C(58), // DSRL
1327
42.7k
    UINT64_C(62), // DSRL32
1328
42.7k
    UINT64_C(22), // DSRLV
1329
42.7k
    UINT64_C(46), // DSUB
1330
42.7k
    UINT64_C(47), // DSUBu
1331
42.7k
    UINT64_C(31), // DUDIV
1332
42.7k
    UINT64_C(1096810532), // DVP
1333
42.7k
    UINT64_C(1096810497), // DVPE
1334
42.7k
    UINT64_C(6524), // DVP_MMR6
1335
42.7k
    UINT64_C(59418),  // DivRxRy16
1336
42.7k
    UINT64_C(59419),  // DivuRxRy16
1337
42.7k
    UINT64_C(192),  // EHB
1338
42.7k
    UINT64_C(6144), // EHB_MM
1339
42.7k
    UINT64_C(6144), // EHB_MMR6
1340
42.7k
    UINT64_C(1096835104), // EI
1341
42.7k
    UINT64_C(22396),  // EI_MM
1342
42.7k
    UINT64_C(22396),  // EI_MMR6
1343
42.7k
    UINT64_C(1096813537), // EMT
1344
42.7k
    UINT64_C(1107296280), // ERET
1345
42.7k
    UINT64_C(1107296344), // ERETNC
1346
42.7k
    UINT64_C(127868), // ERETNC_MMR6
1347
42.7k
    UINT64_C(62332),  // ERET_MM
1348
42.7k
    UINT64_C(62332),  // ERET_MMR6
1349
42.7k
    UINT64_C(1096810500), // EVP
1350
42.7k
    UINT64_C(1096810529), // EVPE
1351
42.7k
    UINT64_C(14716),  // EVP_MMR6
1352
42.7k
    UINT64_C(2080374784), // EXT
1353
42.7k
    UINT64_C(2080374968), // EXTP
1354
42.7k
    UINT64_C(2080375480), // EXTPDP
1355
42.7k
    UINT64_C(2080375544), // EXTPDPV
1356
42.7k
    UINT64_C(14524),  // EXTPDPV_MM
1357
42.7k
    UINT64_C(13948),  // EXTPDP_MM
1358
42.7k
    UINT64_C(2080375032), // EXTPV
1359
42.7k
    UINT64_C(10428),  // EXTPV_MM
1360
42.7k
    UINT64_C(9852), // EXTP_MM
1361
42.7k
    UINT64_C(2080375288), // EXTRV_RS_W
1362
42.7k
    UINT64_C(11964),  // EXTRV_RS_W_MM
1363
42.7k
    UINT64_C(2080375160), // EXTRV_R_W
1364
42.7k
    UINT64_C(7868), // EXTRV_R_W_MM
1365
42.7k
    UINT64_C(2080375800), // EXTRV_S_H
1366
42.7k
    UINT64_C(16060),  // EXTRV_S_H_MM
1367
42.7k
    UINT64_C(2080374904), // EXTRV_W
1368
42.7k
    UINT64_C(3772), // EXTRV_W_MM
1369
42.7k
    UINT64_C(2080375224), // EXTR_RS_W
1370
42.7k
    UINT64_C(11900),  // EXTR_RS_W_MM
1371
42.7k
    UINT64_C(2080375096), // EXTR_R_W
1372
42.7k
    UINT64_C(7804), // EXTR_R_W_MM
1373
42.7k
    UINT64_C(2080375736), // EXTR_S_H
1374
42.7k
    UINT64_C(15996),  // EXTR_S_H_MM
1375
42.7k
    UINT64_C(2080374840), // EXTR_W
1376
42.7k
    UINT64_C(3708), // EXTR_W_MM
1377
42.7k
    UINT64_C(1879048250), // EXTS
1378
42.7k
    UINT64_C(1879048251), // EXTS32
1379
42.7k
    UINT64_C(44), // EXT_MM
1380
42.7k
    UINT64_C(44), // EXT_MMR6
1381
42.7k
    UINT64_C(1176502277), // FABS_D32
1382
42.7k
    UINT64_C(1409295227), // FABS_D32_MM
1383
42.7k
    UINT64_C(1176502277), // FABS_D64
1384
42.7k
    UINT64_C(1409295227), // FABS_D64_MM
1385
42.7k
    UINT64_C(1174405125), // FABS_S
1386
42.7k
    UINT64_C(1409287035), // FABS_S_MM
1387
42.7k
    UINT64_C(2015363099), // FADD_D
1388
42.7k
    UINT64_C(1176502272), // FADD_D32
1389
42.7k
    UINT64_C(1409286448), // FADD_D32_MM
1390
42.7k
    UINT64_C(1176502272), // FADD_D64
1391
42.7k
    UINT64_C(1409286448), // FADD_D64_MM
1392
42.7k
    UINT64_C(1174405120), // FADD_S
1393
42.7k
    UINT64_C(1409286192), // FADD_S_MM
1394
42.7k
    UINT64_C(1409286192), // FADD_S_MMR6
1395
42.7k
    UINT64_C(2013265947), // FADD_W
1396
42.7k
    UINT64_C(2015363098), // FCAF_D
1397
42.7k
    UINT64_C(2013265946), // FCAF_W
1398
42.7k
    UINT64_C(2023751706), // FCEQ_D
1399
42.7k
    UINT64_C(2021654554), // FCEQ_W
1400
42.7k
    UINT64_C(2065760286), // FCLASS_D
1401
42.7k
    UINT64_C(2065694750), // FCLASS_W
1402
42.7k
    UINT64_C(2040528922), // FCLE_D
1403
42.7k
    UINT64_C(2038431770), // FCLE_W
1404
42.7k
    UINT64_C(2032140314), // FCLT_D
1405
42.7k
    UINT64_C(2030043162), // FCLT_W
1406
42.7k
    UINT64_C(1176502320), // FCMP_D32
1407
42.7k
    UINT64_C(1409287228), // FCMP_D32_MM
1408
42.7k
    UINT64_C(1176502320), // FCMP_D64
1409
42.7k
    UINT64_C(1174405168), // FCMP_S32
1410
42.7k
    UINT64_C(1409286204), // FCMP_S32_MM
1411
42.7k
    UINT64_C(2027946012), // FCNE_D
1412
42.7k
    UINT64_C(2025848860), // FCNE_W
1413
42.7k
    UINT64_C(2019557404), // FCOR_D
1414
42.7k
    UINT64_C(2017460252), // FCOR_W
1415
42.7k
    UINT64_C(2027946010), // FCUEQ_D
1416
42.7k
    UINT64_C(2025848858), // FCUEQ_W
1417
42.7k
    UINT64_C(2044723226), // FCULE_D
1418
42.7k
    UINT64_C(2042626074), // FCULE_W
1419
42.7k
    UINT64_C(2036334618), // FCULT_D
1420
42.7k
    UINT64_C(2034237466), // FCULT_W
1421
42.7k
    UINT64_C(2023751708), // FCUNE_D
1422
42.7k
    UINT64_C(2021654556), // FCUNE_W
1423
42.7k
    UINT64_C(2019557402), // FCUN_D
1424
42.7k
    UINT64_C(2017460250), // FCUN_W
1425
42.7k
    UINT64_C(2027946011), // FDIV_D
1426
42.7k
    UINT64_C(1176502275), // FDIV_D32
1427
42.7k
    UINT64_C(1409286640), // FDIV_D32_MM
1428
42.7k
    UINT64_C(1176502275), // FDIV_D64
1429
42.7k
    UINT64_C(1409286640), // FDIV_D64_MM
1430
42.7k
    UINT64_C(1174405123), // FDIV_S
1431
42.7k
    UINT64_C(1409286384), // FDIV_S_MM
1432
42.7k
    UINT64_C(1409286384), // FDIV_S_MMR6
1433
42.7k
    UINT64_C(2025848859), // FDIV_W
1434
42.7k
    UINT64_C(2046820379), // FEXDO_H
1435
42.7k
    UINT64_C(2048917531), // FEXDO_W
1436
42.7k
    UINT64_C(2044723227), // FEXP2_D
1437
42.7k
    UINT64_C(2042626075), // FEXP2_W
1438
42.7k
    UINT64_C(2066808862), // FEXUPL_D
1439
42.7k
    UINT64_C(2066743326), // FEXUPL_W
1440
42.7k
    UINT64_C(2066939934), // FEXUPR_D
1441
42.7k
    UINT64_C(2066874398), // FEXUPR_W
1442
42.7k
    UINT64_C(2067595294), // FFINT_S_D
1443
42.7k
    UINT64_C(2067529758), // FFINT_S_W
1444
42.7k
    UINT64_C(2067726366), // FFINT_U_D
1445
42.7k
    UINT64_C(2067660830), // FFINT_U_W
1446
42.7k
    UINT64_C(2067071006), // FFQL_D
1447
42.7k
    UINT64_C(2067005470), // FFQL_W
1448
42.7k
    UINT64_C(2067202078), // FFQR_D
1449
42.7k
    UINT64_C(2067136542), // FFQR_W
1450
42.7k
    UINT64_C(2063597598), // FILL_B
1451
42.7k
    UINT64_C(2063794206), // FILL_D
1452
42.7k
    UINT64_C(2063663134), // FILL_H
1453
42.7k
    UINT64_C(2063728670), // FILL_W
1454
42.7k
    UINT64_C(2066677790), // FLOG2_D
1455
42.7k
    UINT64_C(2066612254), // FLOG2_W
1456
42.7k
    UINT64_C(1176502283), // FLOOR_L_D64
1457
42.7k
    UINT64_C(1409303355), // FLOOR_L_D_MMR6
1458
42.7k
    UINT64_C(1174405131), // FLOOR_L_S
1459
42.7k
    UINT64_C(1409286971), // FLOOR_L_S_MMR6
1460
42.7k
    UINT64_C(1176502287), // FLOOR_W_D32
1461
42.7k
    UINT64_C(1176502287), // FLOOR_W_D64
1462
42.7k
    UINT64_C(1409305403), // FLOOR_W_D_MMR6
1463
42.7k
    UINT64_C(1409305403), // FLOOR_W_MM
1464
42.7k
    UINT64_C(1174405135), // FLOOR_W_S
1465
42.7k
    UINT64_C(1409289019), // FLOOR_W_S_MM
1466
42.7k
    UINT64_C(1409289019), // FLOOR_W_S_MMR6
1467
42.7k
    UINT64_C(2032140315), // FMADD_D
1468
42.7k
    UINT64_C(2030043163), // FMADD_W
1469
42.7k
    UINT64_C(2078277659), // FMAX_A_D
1470
42.7k
    UINT64_C(2076180507), // FMAX_A_W
1471
42.7k
    UINT64_C(2074083355), // FMAX_D
1472
42.7k
    UINT64_C(2071986203), // FMAX_W
1473
42.7k
    UINT64_C(2069889051), // FMIN_A_D
1474
42.7k
    UINT64_C(2067791899), // FMIN_A_W
1475
42.7k
    UINT64_C(2065694747), // FMIN_D
1476
42.7k
    UINT64_C(2063597595), // FMIN_W
1477
42.7k
    UINT64_C(1176502278), // FMOV_D32
1478
42.7k
    UINT64_C(1409294459), // FMOV_D32_MM
1479
42.7k
    UINT64_C(1176502278), // FMOV_D64
1480
42.7k
    UINT64_C(1409294459), // FMOV_D64_MM
1481
42.7k
    UINT64_C(1174405126), // FMOV_S
1482
42.7k
    UINT64_C(1409286267), // FMOV_S_MM
1483
42.7k
    UINT64_C(1409286267), // FMOV_S_MMR6
1484
42.7k
    UINT64_C(2036334619), // FMSUB_D
1485
42.7k
    UINT64_C(2034237467), // FMSUB_W
1486
42.7k
    UINT64_C(2023751707), // FMUL_D
1487
42.7k
    UINT64_C(1176502274), // FMUL_D32
1488
42.7k
    UINT64_C(1409286576), // FMUL_D32_MM
1489
42.7k
    UINT64_C(1176502274), // FMUL_D64
1490
42.7k
    UINT64_C(1409286576), // FMUL_D64_MM
1491
42.7k
    UINT64_C(1174405122), // FMUL_S
1492
42.7k
    UINT64_C(1409286320), // FMUL_S_MM
1493
42.7k
    UINT64_C(1409286320), // FMUL_S_MMR6
1494
42.7k
    UINT64_C(2021654555), // FMUL_W
1495
42.7k
    UINT64_C(1176502279), // FNEG_D32
1496
42.7k
    UINT64_C(1409297275), // FNEG_D32_MM
1497
42.7k
    UINT64_C(1176502279), // FNEG_D64
1498
42.7k
    UINT64_C(1409297275), // FNEG_D64_MM
1499
42.7k
    UINT64_C(1174405127), // FNEG_S
1500
42.7k
    UINT64_C(1409289083), // FNEG_S_MM
1501
42.7k
    UINT64_C(1409289083), // FNEG_S_MMR6
1502
42.7k
    UINT64_C(2080374792), // FORK
1503
42.7k
    UINT64_C(2066415646), // FRCP_D
1504
42.7k
    UINT64_C(2066350110), // FRCP_W
1505
42.7k
    UINT64_C(2066546718), // FRINT_D
1506
42.7k
    UINT64_C(2066481182), // FRINT_W
1507
42.7k
    UINT64_C(2066284574), // FRSQRT_D
1508
42.7k
    UINT64_C(2066219038), // FRSQRT_W
1509
42.7k
    UINT64_C(2048917530), // FSAF_D
1510
42.7k
    UINT64_C(2046820378), // FSAF_W
1511
42.7k
    UINT64_C(2057306138), // FSEQ_D
1512
42.7k
    UINT64_C(2055208986), // FSEQ_W
1513
42.7k
    UINT64_C(2074083354), // FSLE_D
1514
42.7k
    UINT64_C(2071986202), // FSLE_W
1515
42.7k
    UINT64_C(2065694746), // FSLT_D
1516
42.7k
    UINT64_C(2063597594), // FSLT_W
1517
42.7k
    UINT64_C(2061500444), // FSNE_D
1518
42.7k
    UINT64_C(2059403292), // FSNE_W
1519
42.7k
    UINT64_C(2053111836), // FSOR_D
1520
42.7k
    UINT64_C(2051014684), // FSOR_W
1521
42.7k
    UINT64_C(2066153502), // FSQRT_D
1522
42.7k
    UINT64_C(1176502276), // FSQRT_D32
1523
42.7k
    UINT64_C(1409305147), // FSQRT_D32_MM
1524
42.7k
    UINT64_C(1176502276), // FSQRT_D64
1525
42.7k
    UINT64_C(1409305147), // FSQRT_D64_MM
1526
42.7k
    UINT64_C(1174405124), // FSQRT_S
1527
42.7k
    UINT64_C(1409288763), // FSQRT_S_MM
1528
42.7k
    UINT64_C(2066087966), // FSQRT_W
1529
42.7k
    UINT64_C(2019557403), // FSUB_D
1530
42.7k
    UINT64_C(1176502273), // FSUB_D32
1531
42.7k
    UINT64_C(1409286512), // FSUB_D32_MM
1532
42.7k
    UINT64_C(1176502273), // FSUB_D64
1533
42.7k
    UINT64_C(1409286512), // FSUB_D64_MM
1534
42.7k
    UINT64_C(1174405121), // FSUB_S
1535
42.7k
    UINT64_C(1409286256), // FSUB_S_MM
1536
42.7k
    UINT64_C(1409286256), // FSUB_S_MMR6
1537
42.7k
    UINT64_C(2017460251), // FSUB_W
1538
42.7k
    UINT64_C(2061500442), // FSUEQ_D
1539
42.7k
    UINT64_C(2059403290), // FSUEQ_W
1540
42.7k
    UINT64_C(2078277658), // FSULE_D
1541
42.7k
    UINT64_C(2076180506), // FSULE_W
1542
42.7k
    UINT64_C(2069889050), // FSULT_D
1543
42.7k
    UINT64_C(2067791898), // FSULT_W
1544
42.7k
    UINT64_C(2057306140), // FSUNE_D
1545
42.7k
    UINT64_C(2055208988), // FSUNE_W
1546
42.7k
    UINT64_C(2053111834), // FSUN_D
1547
42.7k
    UINT64_C(2051014682), // FSUN_W
1548
42.7k
    UINT64_C(2067333150), // FTINT_S_D
1549
42.7k
    UINT64_C(2067267614), // FTINT_S_W
1550
42.7k
    UINT64_C(2067464222), // FTINT_U_D
1551
42.7k
    UINT64_C(2067398686), // FTINT_U_W
1552
42.7k
    UINT64_C(2055208987), // FTQ_H
1553
42.7k
    UINT64_C(2057306139), // FTQ_W
1554
42.7k
    UINT64_C(2065891358), // FTRUNC_S_D
1555
42.7k
    UINT64_C(2065825822), // FTRUNC_S_W
1556
42.7k
    UINT64_C(2066022430), // FTRUNC_U_D
1557
42.7k
    UINT64_C(2065956894), // FTRUNC_U_W
1558
42.7k
    UINT64_C(2080374845), // GINVI
1559
42.7k
    UINT64_C(24956),  // GINVI_MMR6
1560
42.7k
    UINT64_C(2080374973), // GINVT
1561
42.7k
    UINT64_C(29052),  // GINVT_MMR6
1562
42.7k
    UINT64_C(2053111829), // HADD_S_D
1563
42.7k
    UINT64_C(2048917525), // HADD_S_H
1564
42.7k
    UINT64_C(2051014677), // HADD_S_W
1565
42.7k
    UINT64_C(2061500437), // HADD_U_D
1566
42.7k
    UINT64_C(2057306133), // HADD_U_H
1567
42.7k
    UINT64_C(2059403285), // HADD_U_W
1568
42.7k
    UINT64_C(2069889045), // HSUB_S_D
1569
42.7k
    UINT64_C(2065694741), // HSUB_S_H
1570
42.7k
    UINT64_C(2067791893), // HSUB_S_W
1571
42.7k
    UINT64_C(2078277653), // HSUB_U_D
1572
42.7k
    UINT64_C(2074083349), // HSUB_U_H
1573
42.7k
    UINT64_C(2076180501), // HSUB_U_W
1574
42.7k
    UINT64_C(1107296296), // HYPCALL
1575
42.7k
    UINT64_C(50044),  // HYPCALL_MM
1576
42.7k
    UINT64_C(2063597588), // ILVEV_B
1577
42.7k
    UINT64_C(2069889044), // ILVEV_D
1578
42.7k
    UINT64_C(2065694740), // ILVEV_H
1579
42.7k
    UINT64_C(2067791892), // ILVEV_W
1580
42.7k
    UINT64_C(2046820372), // ILVL_B
1581
42.7k
    UINT64_C(2053111828), // ILVL_D
1582
42.7k
    UINT64_C(2048917524), // ILVL_H
1583
42.7k
    UINT64_C(2051014676), // ILVL_W
1584
42.7k
    UINT64_C(2071986196), // ILVOD_B
1585
42.7k
    UINT64_C(2078277652), // ILVOD_D
1586
42.7k
    UINT64_C(2074083348), // ILVOD_H
1587
42.7k
    UINT64_C(2076180500), // ILVOD_W
1588
42.7k
    UINT64_C(2055208980), // ILVR_B
1589
42.7k
    UINT64_C(2061500436), // ILVR_D
1590
42.7k
    UINT64_C(2057306132), // ILVR_H
1591
42.7k
    UINT64_C(2059403284), // ILVR_W
1592
42.7k
    UINT64_C(2080374788), // INS
1593
42.7k
    UINT64_C(2030043161), // INSERT_B
1594
42.7k
    UINT64_C(2033713177), // INSERT_D
1595
42.7k
    UINT64_C(2032140313), // INSERT_H
1596
42.7k
    UINT64_C(2033188889), // INSERT_W
1597
42.7k
    UINT64_C(2080374796), // INSV
1598
42.7k
    UINT64_C(2034237465), // INSVE_B
1599
42.7k
    UINT64_C(2037907481), // INSVE_D
1600
42.7k
    UINT64_C(2036334617), // INSVE_H
1601
42.7k
    UINT64_C(2037383193), // INSVE_W
1602
42.7k
    UINT64_C(16700),  // INSV_MM
1603
42.7k
    UINT64_C(12), // INS_MM
1604
42.7k
    UINT64_C(12), // INS_MMR6
1605
42.7k
    UINT64_C(134217728),  // J
1606
42.7k
    UINT64_C(201326592),  // JAL
1607
42.7k
    UINT64_C(9),  // JALR
1608
42.7k
    UINT64_C(17856),  // JALR16_MM
1609
42.7k
    UINT64_C(9),  // JALR64
1610
42.7k
    UINT64_C(17419),  // JALRC16_MMR6
1611
42.7k
    UINT64_C(7996), // JALRC_HB_MMR6
1612
42.7k
    UINT64_C(3900), // JALRC_MMR6
1613
42.7k
    UINT64_C(17888),  // JALRS16_MM
1614
42.7k
    UINT64_C(20284),  // JALRS_MM
1615
42.7k
    UINT64_C(1033), // JALR_HB
1616
42.7k
    UINT64_C(1033), // JALR_HB64
1617
42.7k
    UINT64_C(3900), // JALR_MM
1618
42.7k
    UINT64_C(1946157056), // JALS_MM
1619
42.7k
    UINT64_C(1946157056), // JALX
1620
42.7k
    UINT64_C(4026531840), // JALX_MM
1621
42.7k
    UINT64_C(4093640704), // JAL_MM
1622
42.7k
    UINT64_C(4160749568), // JIALC
1623
42.7k
    UINT64_C(4160749568), // JIALC64
1624
42.7k
    UINT64_C(2147483648), // JIALC_MMR6
1625
42.7k
    UINT64_C(3623878656), // JIC
1626
42.7k
    UINT64_C(3623878656), // JIC64
1627
42.7k
    UINT64_C(2684354560), // JIC_MMR6
1628
42.7k
    UINT64_C(8),  // JR
1629
42.7k
    UINT64_C(17792),  // JR16_MM
1630
42.7k
    UINT64_C(8),  // JR64
1631
42.7k
    UINT64_C(18176),  // JRADDIUSP
1632
42.7k
    UINT64_C(17824),  // JRC16_MM
1633
42.7k
    UINT64_C(17411),  // JRC16_MMR6
1634
42.7k
    UINT64_C(17427),  // JRCADDIUSP_MMR6
1635
42.7k
    UINT64_C(1032), // JR_HB
1636
42.7k
    UINT64_C(1032), // JR_HB64
1637
42.7k
    UINT64_C(1033), // JR_HB64_R6
1638
42.7k
    UINT64_C(1033), // JR_HB_R6
1639
42.7k
    UINT64_C(3900), // JR_MM
1640
42.7k
    UINT64_C(3556769792), // J_MM
1641
42.7k
    UINT64_C(402653184),  // Jal16
1642
42.7k
    UINT64_C(402653184),  // JalB16
1643
42.7k
    UINT64_C(59424),  // JrRa16
1644
42.7k
    UINT64_C(59616),  // JrcRa16
1645
42.7k
    UINT64_C(59584),  // JrcRx16
1646
42.7k
    UINT64_C(59392),  // JumpLinkReg16
1647
42.7k
    UINT64_C(2147483648), // LB
1648
42.7k
    UINT64_C(2147483648), // LB64
1649
42.7k
    UINT64_C(2080374828), // LBE
1650
42.7k
    UINT64_C(1610639360), // LBE_MM
1651
42.7k
    UINT64_C(2048), // LBU16_MM
1652
42.7k
    UINT64_C(2080375178), // LBUX
1653
42.7k
    UINT64_C(549),  // LBUX_MM
1654
42.7k
    UINT64_C(335544320),  // LBU_MMR6
1655
42.7k
    UINT64_C(469762048),  // LB_MM
1656
42.7k
    UINT64_C(469762048),  // LB_MMR6
1657
42.7k
    UINT64_C(2415919104), // LBu
1658
42.7k
    UINT64_C(2415919104), // LBu64
1659
42.7k
    UINT64_C(2080374824), // LBuE
1660
42.7k
    UINT64_C(1610637312), // LBuE_MM
1661
42.7k
    UINT64_C(335544320),  // LBu_MM
1662
42.7k
    UINT64_C(3690987520), // LD
1663
42.7k
    UINT64_C(3556769792), // LDC1
1664
42.7k
    UINT64_C(3556769792), // LDC164
1665
42.7k
    UINT64_C(3154116608), // LDC1_D64_MMR6
1666
42.7k
    UINT64_C(3154116608), // LDC1_MM
1667
42.7k
    UINT64_C(3623878656), // LDC2
1668
42.7k
    UINT64_C(536879104),  // LDC2_MMR6
1669
42.7k
    UINT64_C(1237319680), // LDC2_R6
1670
42.7k
    UINT64_C(3690987520), // LDC3
1671
42.7k
    UINT64_C(2063597575), // LDI_B
1672
42.7k
    UINT64_C(2069889031), // LDI_D
1673
42.7k
    UINT64_C(2065694727), // LDI_H
1674
42.7k
    UINT64_C(2067791879), // LDI_W
1675
42.7k
    UINT64_C(1744830464), // LDL
1676
42.7k
    UINT64_C(3960995840), // LDPC
1677
42.7k
    UINT64_C(1811939328), // LDR
1678
42.7k
    UINT64_C(1275068417), // LDXC1
1679
42.7k
    UINT64_C(1275068417), // LDXC164
1680
42.7k
    UINT64_C(2013265952), // LD_B
1681
42.7k
    UINT64_C(2013265955), // LD_D
1682
42.7k
    UINT64_C(2013265953), // LD_H
1683
42.7k
    UINT64_C(2013265954), // LD_W
1684
42.7k
    UINT64_C(603979776),  // LEA_ADDiu
1685
42.7k
    UINT64_C(1677721600), // LEA_ADDiu64
1686
42.7k
    UINT64_C(805306368),  // LEA_ADDiu_MM
1687
42.7k
    UINT64_C(2214592512), // LH
1688
42.7k
    UINT64_C(2214592512), // LH64
1689
42.7k
    UINT64_C(2080374829), // LHE
1690
42.7k
    UINT64_C(1610639872), // LHE_MM
1691
42.7k
    UINT64_C(10240),  // LHU16_MM
1692
42.7k
    UINT64_C(2080375050), // LHX
1693
42.7k
    UINT64_C(357),  // LHX_MM
1694
42.7k
    UINT64_C(1006632960), // LH_MM
1695
42.7k
    UINT64_C(2483027968), // LHu
1696
42.7k
    UINT64_C(2483027968), // LHu64
1697
42.7k
    UINT64_C(2080374825), // LHuE
1698
42.7k
    UINT64_C(1610637824), // LHuE_MM
1699
42.7k
    UINT64_C(872415232),  // LHu_MM
1700
42.7k
    UINT64_C(60416),  // LI16_MM
1701
42.7k
    UINT64_C(60416),  // LI16_MMR6
1702
42.7k
    UINT64_C(3221225472), // LL
1703
42.7k
    UINT64_C(3221225472), // LL64
1704
42.7k
    UINT64_C(2080374838), // LL64_R6
1705
42.7k
    UINT64_C(3489660928), // LLD
1706
42.7k
    UINT64_C(2080374839), // LLD_R6
1707
42.7k
    UINT64_C(2080374830), // LLE
1708
42.7k
    UINT64_C(1610640384), // LLE_MM
1709
42.7k
    UINT64_C(1610625024), // LL_MM
1710
42.7k
    UINT64_C(1610625024), // LL_MMR6
1711
42.7k
    UINT64_C(2080374838), // LL_R6
1712
42.7k
    UINT64_C(5),  // LSA
1713
42.7k
    UINT64_C(15), // LSA_MMR6
1714
42.7k
    UINT64_C(5),  // LSA_R6
1715
42.7k
    UINT64_C(268435456),  // LUI_MMR6
1716
42.7k
    UINT64_C(1275068421), // LUXC1
1717
42.7k
    UINT64_C(1275068421), // LUXC164
1718
42.7k
    UINT64_C(1409286472), // LUXC1_MM
1719
42.7k
    UINT64_C(1006632960), // LUi
1720
42.7k
    UINT64_C(1006632960), // LUi64
1721
42.7k
    UINT64_C(1101004800), // LUi_MM
1722
42.7k
    UINT64_C(2348810240), // LW
1723
42.7k
    UINT64_C(26624),  // LW16_MM
1724
42.7k
    UINT64_C(2348810240), // LW64
1725
42.7k
    UINT64_C(3288334336), // LWC1
1726
42.7k
    UINT64_C(2617245696), // LWC1_MM
1727
42.7k
    UINT64_C(3355443200), // LWC2
1728
42.7k
    UINT64_C(536870912),  // LWC2_MMR6
1729
42.7k
    UINT64_C(1228931072), // LWC2_R6
1730
42.7k
    UINT64_C(3422552064), // LWC3
1731
42.7k
    UINT64_C(2348810240), // LWDSP
1732
42.7k
    UINT64_C(4227858432), // LWDSP_MM
1733
42.7k
    UINT64_C(2080374831), // LWE
1734
42.7k
    UINT64_C(1610640896), // LWE_MM
1735
42.7k
    UINT64_C(25600),  // LWGP_MM
1736
42.7k
    UINT64_C(2281701376), // LWL
1737
42.7k
    UINT64_C(2281701376), // LWL64
1738
42.7k
    UINT64_C(2080374809), // LWLE
1739
42.7k
    UINT64_C(1610638336), // LWLE_MM
1740
42.7k
    UINT64_C(1610612736), // LWL_MM
1741
42.7k
    UINT64_C(17664),  // LWM16_MM
1742
42.7k
    UINT64_C(17410),  // LWM16_MMR6
1743
42.7k
    UINT64_C(536891392),  // LWM32_MM
1744
42.7k
    UINT64_C(3959947264), // LWPC
1745
42.7k
    UINT64_C(2013790208), // LWPC_MMR6
1746
42.7k
    UINT64_C(536875008),  // LWP_MM
1747
42.7k
    UINT64_C(2550136832), // LWR
1748
42.7k
    UINT64_C(2550136832), // LWR64
1749
42.7k
    UINT64_C(2080374810), // LWRE
1750
42.7k
    UINT64_C(1610638848), // LWRE_MM
1751
42.7k
    UINT64_C(1610616832), // LWR_MM
1752
42.7k
    UINT64_C(18432),  // LWSP_MM
1753
42.7k
    UINT64_C(3960471552), // LWUPC
1754
42.7k
    UINT64_C(1610670080), // LWU_MM
1755
42.7k
    UINT64_C(2080374794), // LWX
1756
42.7k
    UINT64_C(1275068416), // LWXC1
1757
42.7k
    UINT64_C(1409286216), // LWXC1_MM
1758
42.7k
    UINT64_C(280),  // LWXS_MM
1759
42.7k
    UINT64_C(421),  // LWX_MM
1760
42.7k
    UINT64_C(4227858432), // LW_MM
1761
42.7k
    UINT64_C(4227858432), // LW_MMR6
1762
42.7k
    UINT64_C(2617245696), // LWu
1763
42.7k
    UINT64_C(4026570752), // LbRxRyOffMemX16
1764
42.7k
    UINT64_C(4026572800), // LbuRxRyOffMemX16
1765
42.7k
    UINT64_C(4026572800), // LhRxRyOffMemX16
1766
42.7k
    UINT64_C(4026572800), // LhuRxRyOffMemX16
1767
42.7k
    UINT64_C(26624),  // LiRxImm16
1768
42.7k
    UINT64_C(4026558464), // LiRxImmAlignX16
1769
42.7k
    UINT64_C(4026558464), // LiRxImmX16
1770
42.7k
    UINT64_C(45056),  // LwRxPcTcp16
1771
42.7k
    UINT64_C(4026576896), // LwRxPcTcpX16
1772
42.7k
    UINT64_C(4026570752), // LwRxRyOffMemX16
1773
42.7k
    UINT64_C(4026568704), // LwRxSpImmX16
1774
42.7k
    UINT64_C(1879048192), // MADD
1775
42.7k
    UINT64_C(1176502296), // MADDF_D
1776
42.7k
    UINT64_C(1409287096), // MADDF_D_MMR6
1777
42.7k
    UINT64_C(1174405144), // MADDF_S
1778
42.7k
    UINT64_C(1409286584), // MADDF_S_MMR6
1779
42.7k
    UINT64_C(2067791900), // MADDR_Q_H
1780
42.7k
    UINT64_C(2069889052), // MADDR_Q_W
1781
42.7k
    UINT64_C(1879048193), // MADDU
1782
42.7k
    UINT64_C(1879048193), // MADDU_DSP
1783
42.7k
    UINT64_C(6844), // MADDU_DSP_MM
1784
42.7k
    UINT64_C(56124),  // MADDU_MM
1785
42.7k
    UINT64_C(2021654546), // MADDV_B
1786
42.7k
    UINT64_C(2027946002), // MADDV_D
1787
42.7k
    UINT64_C(2023751698), // MADDV_H
1788
42.7k
    UINT64_C(2025848850), // MADDV_W
1789
42.7k
    UINT64_C(1275068449), // MADD_D32
1790
42.7k
    UINT64_C(1409286153), // MADD_D32_MM
1791
42.7k
    UINT64_C(1275068449), // MADD_D64
1792
42.7k
    UINT64_C(1879048192), // MADD_DSP
1793
42.7k
    UINT64_C(2748), // MADD_DSP_MM
1794
42.7k
    UINT64_C(52028),  // MADD_MM
1795
42.7k
    UINT64_C(2034237468), // MADD_Q_H
1796
42.7k
    UINT64_C(2036334620), // MADD_Q_W
1797
42.7k
    UINT64_C(1275068448), // MADD_S
1798
42.7k
    UINT64_C(1409286145), // MADD_S_MM
1799
42.7k
    UINT64_C(2080375856), // MAQ_SA_W_PHL
1800
42.7k
    UINT64_C(14972),  // MAQ_SA_W_PHL_MM
1801
42.7k
    UINT64_C(2080375984), // MAQ_SA_W_PHR
1802
42.7k
    UINT64_C(10876),  // MAQ_SA_W_PHR_MM
1803
42.7k
    UINT64_C(2080376112), // MAQ_S_W_PHL
1804
42.7k
    UINT64_C(6780), // MAQ_S_W_PHL_MM
1805
42.7k
    UINT64_C(2080376240), // MAQ_S_W_PHR
1806
42.7k
    UINT64_C(2684), // MAQ_S_W_PHR_MM
1807
42.7k
    UINT64_C(1176502303), // MAXA_D
1808
42.7k
    UINT64_C(1409286699), // MAXA_D_MMR6
1809
42.7k
    UINT64_C(1174405151), // MAXA_S
1810
42.7k
    UINT64_C(1409286187), // MAXA_S_MMR6
1811
42.7k
    UINT64_C(2030043142), // MAXI_S_B
1812
42.7k
    UINT64_C(2036334598), // MAXI_S_D
1813
42.7k
    UINT64_C(2032140294), // MAXI_S_H
1814
42.7k
    UINT64_C(2034237446), // MAXI_S_W
1815
42.7k
    UINT64_C(2038431750), // MAXI_U_B
1816
42.7k
    UINT64_C(2044723206), // MAXI_U_D
1817
42.7k
    UINT64_C(2040528902), // MAXI_U_H
1818
42.7k
    UINT64_C(2042626054), // MAXI_U_W
1819
42.7k
    UINT64_C(2063597582), // MAX_A_B
1820
42.7k
    UINT64_C(2069889038), // MAX_A_D
1821
42.7k
    UINT64_C(2065694734), // MAX_A_H
1822
42.7k
    UINT64_C(2067791886), // MAX_A_W
1823
42.7k
    UINT64_C(1176502301), // MAX_D
1824
42.7k
    UINT64_C(1409286667), // MAX_D_MMR6
1825
42.7k
    UINT64_C(1174405149), // MAX_S
1826
42.7k
    UINT64_C(2030043150), // MAX_S_B
1827
42.7k
    UINT64_C(2036334606), // MAX_S_D
1828
42.7k
    UINT64_C(2032140302), // MAX_S_H
1829
42.7k
    UINT64_C(1409286155), // MAX_S_MMR6
1830
42.7k
    UINT64_C(2034237454), // MAX_S_W
1831
42.7k
    UINT64_C(2038431758), // MAX_U_B
1832
42.7k
    UINT64_C(2044723214), // MAX_U_D
1833
42.7k
    UINT64_C(2040528910), // MAX_U_H
1834
42.7k
    UINT64_C(2042626062), // MAX_U_W
1835
42.7k
    UINT64_C(1073741824), // MFC0
1836
42.7k
    UINT64_C(252),  // MFC0_MMR6
1837
42.7k
    UINT64_C(1140850688), // MFC1
1838
42.7k
    UINT64_C(1140850688), // MFC1_D64
1839
42.7k
    UINT64_C(1409294395), // MFC1_MM
1840
42.7k
    UINT64_C(1409294395), // MFC1_MMR6
1841
42.7k
    UINT64_C(1207959552), // MFC2
1842
42.7k
    UINT64_C(19772),  // MFC2_MMR6
1843
42.7k
    UINT64_C(1080033280), // MFGC0
1844
42.7k
    UINT64_C(1276), // MFGC0_MM
1845
42.7k
    UINT64_C(244),  // MFHC0_MMR6
1846
42.7k
    UINT64_C(1147142144), // MFHC1_D32
1847
42.7k
    UINT64_C(1409298491), // MFHC1_D32_MM
1848
42.7k
    UINT64_C(1147142144), // MFHC1_D64
1849
42.7k
    UINT64_C(1409298491), // MFHC1_D64_MM
1850
42.7k
    UINT64_C(36156),  // MFHC2_MMR6
1851
42.7k
    UINT64_C(1080034304), // MFHGC0
1852
42.7k
    UINT64_C(1268), // MFHGC0_MM
1853
42.7k
    UINT64_C(16), // MFHI
1854
42.7k
    UINT64_C(17920),  // MFHI16_MM
1855
42.7k
    UINT64_C(16), // MFHI64
1856
42.7k
    UINT64_C(16), // MFHI_DSP
1857
42.7k
    UINT64_C(124),  // MFHI_DSP_MM
1858
42.7k
    UINT64_C(3452), // MFHI_MM
1859
42.7k
    UINT64_C(18), // MFLO
1860
42.7k
    UINT64_C(17984),  // MFLO16_MM
1861
42.7k
    UINT64_C(18), // MFLO64
1862
42.7k
    UINT64_C(18), // MFLO_DSP
1863
42.7k
    UINT64_C(4220), // MFLO_DSP_MM
1864
42.7k
    UINT64_C(7548), // MFLO_MM
1865
42.7k
    UINT64_C(1090519040), // MFTR
1866
42.7k
    UINT64_C(1176502302), // MINA_D
1867
42.7k
    UINT64_C(1409286691), // MINA_D_MMR6
1868
42.7k
    UINT64_C(1174405150), // MINA_S
1869
42.7k
    UINT64_C(1409286179), // MINA_S_MMR6
1870
42.7k
    UINT64_C(2046820358), // MINI_S_B
1871
42.7k
    UINT64_C(2053111814), // MINI_S_D
1872
42.7k
    UINT64_C(2048917510), // MINI_S_H
1873
42.7k
    UINT64_C(2051014662), // MINI_S_W
1874
42.7k
    UINT64_C(2055208966), // MINI_U_B
1875
42.7k
    UINT64_C(2061500422), // MINI_U_D
1876
42.7k
    UINT64_C(2057306118), // MINI_U_H
1877
42.7k
    UINT64_C(2059403270), // MINI_U_W
1878
42.7k
    UINT64_C(2071986190), // MIN_A_B
1879
42.7k
    UINT64_C(2078277646), // MIN_A_D
1880
42.7k
    UINT64_C(2074083342), // MIN_A_H
1881
42.7k
    UINT64_C(2076180494), // MIN_A_W
1882
42.7k
    UINT64_C(1176502300), // MIN_D
1883
42.7k
    UINT64_C(1409286659), // MIN_D_MMR6
1884
42.7k
    UINT64_C(1174405148), // MIN_S
1885
42.7k
    UINT64_C(2046820366), // MIN_S_B
1886
42.7k
    UINT64_C(2053111822), // MIN_S_D
1887
42.7k
    UINT64_C(2048917518), // MIN_S_H
1888
42.7k
    UINT64_C(1409286147), // MIN_S_MMR6
1889
42.7k
    UINT64_C(2051014670), // MIN_S_W
1890
42.7k
    UINT64_C(2055208974), // MIN_U_B
1891
42.7k
    UINT64_C(2061500430), // MIN_U_D
1892
42.7k
    UINT64_C(2057306126), // MIN_U_H
1893
42.7k
    UINT64_C(2059403278), // MIN_U_W
1894
42.7k
    UINT64_C(218),  // MOD
1895
42.7k
    UINT64_C(2080375952), // MODSUB
1896
42.7k
    UINT64_C(661),  // MODSUB_MM
1897
42.7k
    UINT64_C(219),  // MODU
1898
42.7k
    UINT64_C(472),  // MODU_MMR6
1899
42.7k
    UINT64_C(344),  // MOD_MMR6
1900
42.7k
    UINT64_C(2063597586), // MOD_S_B
1901
42.7k
    UINT64_C(2069889042), // MOD_S_D
1902
42.7k
    UINT64_C(2065694738), // MOD_S_H
1903
42.7k
    UINT64_C(2067791890), // MOD_S_W
1904
42.7k
    UINT64_C(2071986194), // MOD_U_B
1905
42.7k
    UINT64_C(2078277650), // MOD_U_D
1906
42.7k
    UINT64_C(2074083346), // MOD_U_H
1907
42.7k
    UINT64_C(2076180498), // MOD_U_W
1908
42.7k
    UINT64_C(3072), // MOVE16_MM
1909
42.7k
    UINT64_C(3072), // MOVE16_MMR6
1910
42.7k
    UINT64_C(33792),  // MOVEP_MM
1911
42.7k
    UINT64_C(17412),  // MOVEP_MMR6
1912
42.7k
    UINT64_C(2025717785), // MOVE_V
1913
42.7k
    UINT64_C(1176502289), // MOVF_D32
1914
42.7k
    UINT64_C(1409286688), // MOVF_D32_MM
1915
42.7k
    UINT64_C(1176502289), // MOVF_D64
1916
42.7k
    UINT64_C(1),  // MOVF_I
1917
42.7k
    UINT64_C(1),  // MOVF_I64
1918
42.7k
    UINT64_C(1409286523), // MOVF_I_MM
1919
42.7k
    UINT64_C(1174405137), // MOVF_S
1920
42.7k
    UINT64_C(1409286176), // MOVF_S_MM
1921
42.7k
    UINT64_C(1176502291), // MOVN_I64_D64
1922
42.7k
    UINT64_C(11), // MOVN_I64_I
1923
42.7k
    UINT64_C(11), // MOVN_I64_I64
1924
42.7k
    UINT64_C(1174405139), // MOVN_I64_S
1925
42.7k
    UINT64_C(1176502291), // MOVN_I_D32
1926
42.7k
    UINT64_C(1409286456), // MOVN_I_D32_MM
1927
42.7k
    UINT64_C(1176502291), // MOVN_I_D64
1928
42.7k
    UINT64_C(11), // MOVN_I_I
1929
42.7k
    UINT64_C(11), // MOVN_I_I64
1930
42.7k
    UINT64_C(24), // MOVN_I_MM
1931
42.7k
    UINT64_C(1174405139), // MOVN_I_S
1932
42.7k
    UINT64_C(1409286200), // MOVN_I_S_MM
1933
42.7k
    UINT64_C(1176567825), // MOVT_D32
1934
42.7k
    UINT64_C(1409286752), // MOVT_D32_MM
1935
42.7k
    UINT64_C(1176567825), // MOVT_D64
1936
42.7k
    UINT64_C(65537),  // MOVT_I
1937
42.7k
    UINT64_C(65537),  // MOVT_I64
1938
42.7k
    UINT64_C(1409288571), // MOVT_I_MM
1939
42.7k
    UINT64_C(1174470673), // MOVT_S
1940
42.7k
    UINT64_C(1409286240), // MOVT_S_MM
1941
42.7k
    UINT64_C(1176502290), // MOVZ_I64_D64
1942
42.7k
    UINT64_C(10), // MOVZ_I64_I
1943
42.7k
    UINT64_C(10), // MOVZ_I64_I64
1944
42.7k
    UINT64_C(1174405138), // MOVZ_I64_S
1945
42.7k
    UINT64_C(1176502290), // MOVZ_I_D32
1946
42.7k
    UINT64_C(1409286520), // MOVZ_I_D32_MM
1947
42.7k
    UINT64_C(1176502290), // MOVZ_I_D64
1948
42.7k
    UINT64_C(10), // MOVZ_I_I
1949
42.7k
    UINT64_C(10), // MOVZ_I_I64
1950
42.7k
    UINT64_C(88), // MOVZ_I_MM
1951
42.7k
    UINT64_C(1174405138), // MOVZ_I_S
1952
42.7k
    UINT64_C(1409286264), // MOVZ_I_S_MM
1953
42.7k
    UINT64_C(1879048196), // MSUB
1954
42.7k
    UINT64_C(1176502297), // MSUBF_D
1955
42.7k
    UINT64_C(1409287160), // MSUBF_D_MMR6
1956
42.7k
    UINT64_C(1174405145), // MSUBF_S
1957
42.7k
    UINT64_C(1409286648), // MSUBF_S_MMR6
1958
42.7k
    UINT64_C(2071986204), // MSUBR_Q_H
1959
42.7k
    UINT64_C(2074083356), // MSUBR_Q_W
1960
42.7k
    UINT64_C(1879048197), // MSUBU
1961
42.7k
    UINT64_C(1879048197), // MSUBU_DSP
1962
42.7k
    UINT64_C(15036),  // MSUBU_DSP_MM
1963
42.7k
    UINT64_C(64316),  // MSUBU_MM
1964
42.7k
    UINT64_C(2030043154), // MSUBV_B
1965
42.7k
    UINT64_C(2036334610), // MSUBV_D
1966
42.7k
    UINT64_C(2032140306), // MSUBV_H
1967
42.7k
    UINT64_C(2034237458), // MSUBV_W
1968
42.7k
    UINT64_C(1275068457), // MSUB_D32
1969
42.7k
    UINT64_C(1409286185), // MSUB_D32_MM
1970
42.7k
    UINT64_C(1275068457), // MSUB_D64
1971
42.7k
    UINT64_C(1879048196), // MSUB_DSP
1972
42.7k
    UINT64_C(10940),  // MSUB_DSP_MM
1973
42.7k
    UINT64_C(60220),  // MSUB_MM
1974
42.7k
    UINT64_C(2038431772), // MSUB_Q_H
1975
42.7k
    UINT64_C(2040528924), // MSUB_Q_W
1976
42.7k
    UINT64_C(1275068456), // MSUB_S
1977
42.7k
    UINT64_C(1409286177), // MSUB_S_MM
1978
42.7k
    UINT64_C(1082130432), // MTC0
1979
42.7k
    UINT64_C(764),  // MTC0_MMR6
1980
42.7k
    UINT64_C(1149239296), // MTC1
1981
42.7k
    UINT64_C(1149239296), // MTC1_D64
1982
42.7k
    UINT64_C(1409296443), // MTC1_D64_MM
1983
42.7k
    UINT64_C(1409296443), // MTC1_MM
1984
42.7k
    UINT64_C(1409296443), // MTC1_MMR6
1985
42.7k
    UINT64_C(1216348160), // MTC2
1986
42.7k
    UINT64_C(23868),  // MTC2_MMR6
1987
42.7k
    UINT64_C(1080033792), // MTGC0
1988
42.7k
    UINT64_C(1788), // MTGC0_MM
1989
42.7k
    UINT64_C(756),  // MTHC0_MMR6
1990
42.7k
    UINT64_C(1155530752), // MTHC1_D32
1991
42.7k
    UINT64_C(1409300539), // MTHC1_D32_MM
1992
42.7k
    UINT64_C(1155530752), // MTHC1_D64
1993
42.7k
    UINT64_C(1409300539), // MTHC1_D64_MM
1994
42.7k
    UINT64_C(40252),  // MTHC2_MMR6
1995
42.7k
    UINT64_C(1080034816), // MTHGC0
1996
42.7k
    UINT64_C(1780), // MTHGC0_MM
1997
42.7k
    UINT64_C(17), // MTHI
1998
42.7k
    UINT64_C(17), // MTHI64
1999
42.7k
    UINT64_C(17), // MTHI_DSP
2000
42.7k
    UINT64_C(8316), // MTHI_DSP_MM
2001
42.7k
    UINT64_C(11644),  // MTHI_MM
2002
42.7k
    UINT64_C(2080376824), // MTHLIP
2003
42.7k
    UINT64_C(636),  // MTHLIP_MM
2004
42.7k
    UINT64_C(19), // MTLO
2005
42.7k
    UINT64_C(19), // MTLO64
2006
42.7k
    UINT64_C(19), // MTLO_DSP
2007
42.7k
    UINT64_C(12412),  // MTLO_DSP_MM
2008
42.7k
    UINT64_C(15740),  // MTLO_MM
2009
42.7k
    UINT64_C(1879048200), // MTM0
2010
42.7k
    UINT64_C(1879048204), // MTM1
2011
42.7k
    UINT64_C(1879048205), // MTM2
2012
42.7k
    UINT64_C(1879048201), // MTP0
2013
42.7k
    UINT64_C(1879048202), // MTP1
2014
42.7k
    UINT64_C(1879048203), // MTP2
2015
42.7k
    UINT64_C(1098907648), // MTTR
2016
42.7k
    UINT64_C(216),  // MUH
2017
42.7k
    UINT64_C(217),  // MUHU
2018
42.7k
    UINT64_C(216),  // MUHU_MMR6
2019
42.7k
    UINT64_C(88), // MUH_MMR6
2020
42.7k
    UINT64_C(1879048194), // MUL
2021
42.7k
    UINT64_C(2080376592), // MULEQ_S_W_PHL
2022
42.7k
    UINT64_C(37), // MULEQ_S_W_PHL_MM
2023
42.7k
    UINT64_C(2080376656), // MULEQ_S_W_PHR
2024
42.7k
    UINT64_C(101),  // MULEQ_S_W_PHR_MM
2025
42.7k
    UINT64_C(2080375184), // MULEU_S_PH_QBL
2026
42.7k
    UINT64_C(149),  // MULEU_S_PH_QBL_MM
2027
42.7k
    UINT64_C(2080375248), // MULEU_S_PH_QBR
2028
42.7k
    UINT64_C(213),  // MULEU_S_PH_QBR_MM
2029
42.7k
    UINT64_C(2080376784), // MULQ_RS_PH
2030
42.7k
    UINT64_C(277),  // MULQ_RS_PH_MM
2031
42.7k
    UINT64_C(2080376280), // MULQ_RS_W
2032
42.7k
    UINT64_C(405),  // MULQ_RS_W_MMR2
2033
42.7k
    UINT64_C(2080376720), // MULQ_S_PH
2034
42.7k
    UINT64_C(341),  // MULQ_S_PH_MMR2
2035
42.7k
    UINT64_C(2080376216), // MULQ_S_W
2036
42.7k
    UINT64_C(469),  // MULQ_S_W_MMR2
2037
42.7k
    UINT64_C(2063597596), // MULR_Q_H
2038
42.7k
    UINT64_C(2065694748), // MULR_Q_W
2039
42.7k
    UINT64_C(2080375216), // MULSAQ_S_W_PH
2040
42.7k
    UINT64_C(15548),  // MULSAQ_S_W_PH_MM
2041
42.7k
    UINT64_C(2080374960), // MULSA_W_PH
2042
42.7k
    UINT64_C(11452),  // MULSA_W_PH_MMR2
2043
42.7k
    UINT64_C(24), // MULT
2044
42.7k
    UINT64_C(25), // MULTU_DSP
2045
42.7k
    UINT64_C(7356), // MULTU_DSP_MM
2046
42.7k
    UINT64_C(24), // MULT_DSP
2047
42.7k
    UINT64_C(3260), // MULT_DSP_MM
2048
42.7k
    UINT64_C(35644),  // MULT_MM
2049
42.7k
    UINT64_C(25), // MULTu
2050
42.7k
    UINT64_C(39740),  // MULTu_MM
2051
42.7k
    UINT64_C(153),  // MULU
2052
42.7k
    UINT64_C(152),  // MULU_MMR6
2053
42.7k
    UINT64_C(2013265938), // MULV_B
2054
42.7k
    UINT64_C(2019557394), // MULV_D
2055
42.7k
    UINT64_C(2015363090), // MULV_H
2056
42.7k
    UINT64_C(2017460242), // MULV_W
2057
42.7k
    UINT64_C(528),  // MUL_MM
2058
42.7k
    UINT64_C(24), // MUL_MMR6
2059
42.7k
    UINT64_C(2080375576), // MUL_PH
2060
42.7k
    UINT64_C(45), // MUL_PH_MMR2
2061
42.7k
    UINT64_C(2030043164), // MUL_Q_H
2062
42.7k
    UINT64_C(2032140316), // MUL_Q_W
2063
42.7k
    UINT64_C(152),  // MUL_R6
2064
42.7k
    UINT64_C(2080375704), // MUL_S_PH
2065
42.7k
    UINT64_C(1069), // MUL_S_PH_MMR2
2066
42.7k
    UINT64_C(59408),  // Mfhi16
2067
42.7k
    UINT64_C(59410),  // Mflo16
2068
42.7k
    UINT64_C(25856),  // Move32R16
2069
42.7k
    UINT64_C(26368),  // MoveR3216
2070
42.7k
    UINT64_C(2064121886), // NLOC_B
2071
42.7k
    UINT64_C(2064318494), // NLOC_D
2072
42.7k
    UINT64_C(2064187422), // NLOC_H
2073
42.7k
    UINT64_C(2064252958), // NLOC_W
2074
42.7k
    UINT64_C(2064384030), // NLZC_B
2075
42.7k
    UINT64_C(2064580638), // NLZC_D
2076
42.7k
    UINT64_C(2064449566), // NLZC_H
2077
42.7k
    UINT64_C(2064515102), // NLZC_W
2078
42.7k
    UINT64_C(1275068465), // NMADD_D32
2079
42.7k
    UINT64_C(1409286154), // NMADD_D32_MM
2080
42.7k
    UINT64_C(1275068465), // NMADD_D64
2081
42.7k
    UINT64_C(1275068464), // NMADD_S
2082
42.7k
    UINT64_C(1409286146), // NMADD_S_MM
2083
42.7k
    UINT64_C(1275068473), // NMSUB_D32
2084
42.7k
    UINT64_C(1409286186), // NMSUB_D32_MM
2085
42.7k
    UINT64_C(1275068473), // NMSUB_D64
2086
42.7k
    UINT64_C(1275068472), // NMSUB_S
2087
42.7k
    UINT64_C(1409286178), // NMSUB_S_MM
2088
42.7k
    UINT64_C(39), // NOR
2089
42.7k
    UINT64_C(39), // NOR64
2090
42.7k
    UINT64_C(2046820352), // NORI_B
2091
42.7k
    UINT64_C(720),  // NOR_MM
2092
42.7k
    UINT64_C(720),  // NOR_MMR6
2093
42.7k
    UINT64_C(2017460254), // NOR_V
2094
42.7k
    UINT64_C(17408),  // NOT16_MM
2095
42.7k
    UINT64_C(17408),  // NOT16_MMR6
2096
42.7k
    UINT64_C(59421),  // NegRxRy16
2097
42.7k
    UINT64_C(59407),  // NotRxRy16
2098
42.7k
    UINT64_C(37), // OR
2099
42.7k
    UINT64_C(17600),  // OR16_MM
2100
42.7k
    UINT64_C(17417),  // OR16_MMR6
2101
42.7k
    UINT64_C(37), // OR64
2102
42.7k
    UINT64_C(2030043136), // ORI_B
2103
42.7k
    UINT64_C(1342177280), // ORI_MMR6
2104
42.7k
    UINT64_C(656),  // OR_MM
2105
42.7k
    UINT64_C(656),  // OR_MMR6
2106
42.7k
    UINT64_C(2015363102), // OR_V
2107
42.7k
    UINT64_C(872415232),  // ORi
2108
42.7k
    UINT64_C(872415232),  // ORi64
2109
42.7k
    UINT64_C(1342177280), // ORi_MM
2110
42.7k
    UINT64_C(59405),  // OrRxRxRy16
2111
42.7k
    UINT64_C(2080375697), // PACKRL_PH
2112
42.7k
    UINT64_C(429),  // PACKRL_PH_MM
2113
42.7k
    UINT64_C(320),  // PAUSE
2114
42.7k
    UINT64_C(10240),  // PAUSE_MM
2115
42.7k
    UINT64_C(10240),  // PAUSE_MMR6
2116
42.7k
    UINT64_C(2030043156), // PCKEV_B
2117
42.7k
    UINT64_C(2036334612), // PCKEV_D
2118
42.7k
    UINT64_C(2032140308), // PCKEV_H
2119
42.7k
    UINT64_C(2034237460), // PCKEV_W
2120
42.7k
    UINT64_C(2038431764), // PCKOD_B
2121
42.7k
    UINT64_C(2044723220), // PCKOD_D
2122
42.7k
    UINT64_C(2040528916), // PCKOD_H
2123
42.7k
    UINT64_C(2042626068), // PCKOD_W
2124
42.7k
    UINT64_C(2063859742), // PCNT_B
2125
42.7k
    UINT64_C(2064056350), // PCNT_D
2126
42.7k
    UINT64_C(2063925278), // PCNT_H
2127
42.7k
    UINT64_C(2063990814), // PCNT_W
2128
42.7k
    UINT64_C(2080375505), // PICK_PH
2129
42.7k
    UINT64_C(557),  // PICK_PH_MM
2130
42.7k
    UINT64_C(2080374993), // PICK_QB
2131
42.7k
    UINT64_C(493),  // PICK_QB_MM
2132
42.7k
    UINT64_C(1186988076), // PLL_PS64
2133
42.7k
    UINT64_C(1186988077), // PLU_PS64
2134
42.7k
    UINT64_C(1879048236), // POP
2135
42.7k
    UINT64_C(2080375058), // PRECEQU_PH_QBL
2136
42.7k
    UINT64_C(2080375186), // PRECEQU_PH_QBLA
2137
42.7k
    UINT64_C(29500),  // PRECEQU_PH_QBLA_MM
2138
42.7k
    UINT64_C(28988),  // PRECEQU_PH_QBL_MM
2139
42.7k
    UINT64_C(2080375122), // PRECEQU_PH_QBR
2140
42.7k
    UINT64_C(2080375250), // PRECEQU_PH_QBRA
2141
42.7k
    UINT64_C(37692),  // PRECEQU_PH_QBRA_MM
2142
42.7k
    UINT64_C(37180),  // PRECEQU_PH_QBR_MM
2143
42.7k
    UINT64_C(2080375570), // PRECEQ_W_PHL
2144
42.7k
    UINT64_C(20796),  // PRECEQ_W_PHL_MM
2145
42.7k
    UINT64_C(2080375634), // PRECEQ_W_PHR
2146
42.7k
    UINT64_C(24892),  // PRECEQ_W_PHR_MM
2147
42.7k
    UINT64_C(2080376594), // PRECEU_PH_QBL
2148
42.7k
    UINT64_C(2080376722), // PRECEU_PH_QBLA
2149
42.7k
    UINT64_C(45884),  // PRECEU_PH_QBLA_MM
2150
42.7k
    UINT64_C(45372),  // PRECEU_PH_QBL_MM
2151
42.7k
    UINT64_C(2080376658), // PRECEU_PH_QBR
2152
42.7k
    UINT64_C(2080376786), // PRECEU_PH_QBRA
2153
42.7k
    UINT64_C(54076),  // PRECEU_PH_QBRA_MM
2154
42.7k
    UINT64_C(53564),  // PRECEU_PH_QBR_MM
2155
42.7k
    UINT64_C(2080375761), // PRECRQU_S_QB_PH
2156
42.7k
    UINT64_C(365),  // PRECRQU_S_QB_PH_MM
2157
42.7k
    UINT64_C(2080376081), // PRECRQ_PH_W
2158
42.7k
    UINT64_C(237),  // PRECRQ_PH_W_MM
2159
42.7k
    UINT64_C(2080375569), // PRECRQ_QB_PH
2160
42.7k
    UINT64_C(173),  // PRECRQ_QB_PH_MM
2161
42.7k
    UINT64_C(2080376145), // PRECRQ_RS_PH_W
2162
42.7k
    UINT64_C(301),  // PRECRQ_RS_PH_W_MM
2163
42.7k
    UINT64_C(2080375633), // PRECR_QB_PH
2164
42.7k
    UINT64_C(109),  // PRECR_QB_PH_MMR2
2165
42.7k
    UINT64_C(2080376721), // PRECR_SRA_PH_W
2166
42.7k
    UINT64_C(973),  // PRECR_SRA_PH_W_MMR2
2167
42.7k
    UINT64_C(2080376785), // PRECR_SRA_R_PH_W
2168
42.7k
    UINT64_C(1997), // PRECR_SRA_R_PH_W_MMR2
2169
42.7k
    UINT64_C(3422552064), // PREF
2170
42.7k
    UINT64_C(2080374819), // PREFE
2171
42.7k
    UINT64_C(1610654720), // PREFE_MM
2172
42.7k
    UINT64_C(1409286560), // PREFX_MM
2173
42.7k
    UINT64_C(1610620928), // PREF_MM
2174
42.7k
    UINT64_C(1610620928), // PREF_MMR6
2175
42.7k
    UINT64_C(2080374837), // PREF_R6
2176
42.7k
    UINT64_C(2080374897), // PREPEND
2177
42.7k
    UINT64_C(597),  // PREPEND_MMR2
2178
42.7k
    UINT64_C(2080376080), // RADDU_W_QB
2179
42.7k
    UINT64_C(61756),  // RADDU_W_QB_MM
2180
42.7k
    UINT64_C(2080375992), // RDDSP
2181
42.7k
    UINT64_C(1660), // RDDSP_MM
2182
42.7k
    UINT64_C(2080374843), // RDHWR
2183
42.7k
    UINT64_C(2080374843), // RDHWR64
2184
42.7k
    UINT64_C(27452),  // RDHWR_MM
2185
42.7k
    UINT64_C(448),  // RDHWR_MMR6
2186
42.7k
    UINT64_C(57724),  // RDPGPR_MMR6
2187
42.7k
    UINT64_C(1176502293), // RECIP_D32
2188
42.7k
    UINT64_C(1409307195), // RECIP_D32_MM
2189
42.7k
    UINT64_C(1176502293), // RECIP_D64
2190
42.7k
    UINT64_C(1409307195), // RECIP_D64_MM
2191
42.7k
    UINT64_C(1174405141), // RECIP_S
2192
42.7k
    UINT64_C(1409290811), // RECIP_S_MM
2193
42.7k
    UINT64_C(2080375506), // REPLV_PH
2194
42.7k
    UINT64_C(828),  // REPLV_PH_MM
2195
42.7k
    UINT64_C(2080374994), // REPLV_QB
2196
42.7k
    UINT64_C(4924), // REPLV_QB_MM
2197
42.7k
    UINT64_C(2080375442), // REPL_PH
2198
42.7k
    UINT64_C(61), // REPL_PH_MM
2199
42.7k
    UINT64_C(2080374930), // REPL_QB
2200
42.7k
    UINT64_C(1532), // REPL_QB_MM
2201
42.7k
    UINT64_C(1176502298), // RINT_D
2202
42.7k
    UINT64_C(1409286688), // RINT_D_MMR6
2203
42.7k
    UINT64_C(1174405146), // RINT_S
2204
42.7k
    UINT64_C(1409286176), // RINT_S_MMR6
2205
42.7k
    UINT64_C(2097154),  // ROTR
2206
42.7k
    UINT64_C(70), // ROTRV
2207
42.7k
    UINT64_C(208),  // ROTRV_MM
2208
42.7k
    UINT64_C(192),  // ROTR_MM
2209
42.7k
    UINT64_C(1176502280), // ROUND_L_D64
2210
42.7k
    UINT64_C(1409315643), // ROUND_L_D_MMR6
2211
42.7k
    UINT64_C(1174405128), // ROUND_L_S
2212
42.7k
    UINT64_C(1409299259), // ROUND_L_S_MMR6
2213
42.7k
    UINT64_C(1176502284), // ROUND_W_D32
2214
42.7k
    UINT64_C(1176502284), // ROUND_W_D64
2215
42.7k
    UINT64_C(1409317691), // ROUND_W_D_MMR6
2216
42.7k
    UINT64_C(1409317691), // ROUND_W_MM
2217
42.7k
    UINT64_C(1174405132), // ROUND_W_S
2218
42.7k
    UINT64_C(1409301307), // ROUND_W_S_MM
2219
42.7k
    UINT64_C(1409301307), // ROUND_W_S_MMR6
2220
42.7k
    UINT64_C(1176502294), // RSQRT_D32
2221
42.7k
    UINT64_C(1409303099), // RSQRT_D32_MM
2222
42.7k
    UINT64_C(1176502294), // RSQRT_D64
2223
42.7k
    UINT64_C(1409303099), // RSQRT_D64_MM
2224
42.7k
    UINT64_C(1174405142), // RSQRT_S
2225
42.7k
    UINT64_C(1409286715), // RSQRT_S_MM
2226
42.7k
    UINT64_C(25728),  // Restore16
2227
42.7k
    UINT64_C(25728),  // RestoreX16
2228
42.7k
    UINT64_C(2020605962), // SAT_S_B
2229
42.7k
    UINT64_C(2013265930), // SAT_S_D
2230
42.7k
    UINT64_C(2019557386), // SAT_S_H
2231
42.7k
    UINT64_C(2017460234), // SAT_S_W
2232
42.7k
    UINT64_C(2028994570), // SAT_U_B
2233
42.7k
    UINT64_C(2021654538), // SAT_U_D
2234
42.7k
    UINT64_C(2027945994), // SAT_U_H
2235
42.7k
    UINT64_C(2025848842), // SAT_U_W
2236
42.7k
    UINT64_C(2684354560), // SB
2237
42.7k
    UINT64_C(34816),  // SB16_MM
2238
42.7k
    UINT64_C(34816),  // SB16_MMR6
2239
42.7k
    UINT64_C(2684354560), // SB64
2240
42.7k
    UINT64_C(2080374812), // SBE
2241
42.7k
    UINT64_C(1610655744), // SBE_MM
2242
42.7k
    UINT64_C(402653184),  // SB_MM
2243
42.7k
    UINT64_C(402653184),  // SB_MMR6
2244
42.7k
    UINT64_C(3758096384), // SC
2245
42.7k
    UINT64_C(3758096384), // SC64
2246
42.7k
    UINT64_C(2080374822), // SC64_R6
2247
42.7k
    UINT64_C(4026531840), // SCD
2248
42.7k
    UINT64_C(2080374823), // SCD_R6
2249
42.7k
    UINT64_C(2080374814), // SCE
2250
42.7k
    UINT64_C(1610656768), // SCE_MM
2251
42.7k
    UINT64_C(1610657792), // SC_MM
2252
42.7k
    UINT64_C(1610657792), // SC_MMR6
2253
42.7k
    UINT64_C(2080374822), // SC_R6
2254
42.7k
    UINT64_C(4227858432), // SD
2255
42.7k
    UINT64_C(1879048255), // SDBBP
2256
42.7k
    UINT64_C(18112),  // SDBBP16_MM
2257
42.7k
    UINT64_C(17467),  // SDBBP16_MMR6
2258
42.7k
    UINT64_C(56188),  // SDBBP_MM
2259
42.7k
    UINT64_C(56188),  // SDBBP_MMR6
2260
42.7k
    UINT64_C(14), // SDBBP_R6
2261
42.7k
    UINT64_C(4093640704), // SDC1
2262
42.7k
    UINT64_C(4093640704), // SDC164
2263
42.7k
    UINT64_C(3087007744), // SDC1_D64_MMR6
2264
42.7k
    UINT64_C(3087007744), // SDC1_MM
2265
42.7k
    UINT64_C(4160749568), // SDC2
2266
42.7k
    UINT64_C(536911872),  // SDC2_MMR6
2267
42.7k
    UINT64_C(1239416832), // SDC2_R6
2268
42.7k
    UINT64_C(4227858432), // SDC3
2269
42.7k
    UINT64_C(26), // SDIV
2270
42.7k
    UINT64_C(43836),  // SDIV_MM
2271
42.7k
    UINT64_C(2952790016), // SDL
2272
42.7k
    UINT64_C(3019898880), // SDR
2273
42.7k
    UINT64_C(1275068425), // SDXC1
2274
42.7k
    UINT64_C(1275068425), // SDXC164
2275
42.7k
    UINT64_C(2080375840), // SEB
2276
42.7k
    UINT64_C(2080375840), // SEB64
2277
42.7k
    UINT64_C(11068),  // SEB_MM
2278
42.7k
    UINT64_C(2080376352), // SEH
2279
42.7k
    UINT64_C(2080376352), // SEH64
2280
42.7k
    UINT64_C(15164),  // SEH_MM
2281
42.7k
    UINT64_C(53), // SELEQZ
2282
42.7k
    UINT64_C(53), // SELEQZ64
2283
42.7k
    UINT64_C(1176502292), // SELEQZ_D
2284
42.7k
    UINT64_C(1409286712), // SELEQZ_D_MMR6
2285
42.7k
    UINT64_C(320),  // SELEQZ_MMR6
2286
42.7k
    UINT64_C(1174405140), // SELEQZ_S
2287
42.7k
    UINT64_C(1409286200), // SELEQZ_S_MMR6
2288
42.7k
    UINT64_C(55), // SELNEZ
2289
42.7k
    UINT64_C(55), // SELNEZ64
2290
42.7k
    UINT64_C(1176502295), // SELNEZ_D
2291
42.7k
    UINT64_C(1409286776), // SELNEZ_D_MMR6
2292
42.7k
    UINT64_C(384),  // SELNEZ_MMR6
2293
42.7k
    UINT64_C(1174405143), // SELNEZ_S
2294
42.7k
    UINT64_C(1409286264), // SELNEZ_S_MMR6
2295
42.7k
    UINT64_C(1176502288), // SEL_D
2296
42.7k
    UINT64_C(1409286840), // SEL_D_MMR6
2297
42.7k
    UINT64_C(1174405136), // SEL_S
2298
42.7k
    UINT64_C(1409286328), // SEL_S_MMR6
2299
42.7k
    UINT64_C(1879048234), // SEQ
2300
42.7k
    UINT64_C(1879048238), // SEQi
2301
42.7k
    UINT64_C(2751463424), // SH
2302
42.7k
    UINT64_C(43008),  // SH16_MM
2303
42.7k
    UINT64_C(43008),  // SH16_MMR6
2304
42.7k
    UINT64_C(2751463424), // SH64
2305
42.7k
    UINT64_C(2080374813), // SHE
2306
42.7k
    UINT64_C(1610656256), // SHE_MM
2307
42.7k
    UINT64_C(2013265922), // SHF_B
2308
42.7k
    UINT64_C(2030043138), // SHF_H
2309
42.7k
    UINT64_C(2046820354), // SHF_W
2310
42.7k
    UINT64_C(2080376504), // SHILO
2311
42.7k
    UINT64_C(2080376568), // SHILOV
2312
42.7k
    UINT64_C(4732), // SHILOV_MM
2313
42.7k
    UINT64_C(29), // SHILO_MM
2314
42.7k
    UINT64_C(2080375443), // SHLLV_PH
2315
42.7k
    UINT64_C(14), // SHLLV_PH_MM
2316
42.7k
    UINT64_C(2080374931), // SHLLV_QB
2317
42.7k
    UINT64_C(917),  // SHLLV_QB_MM
2318
42.7k
    UINT64_C(2080375699), // SHLLV_S_PH
2319
42.7k
    UINT64_C(1038), // SHLLV_S_PH_MM
2320
42.7k
    UINT64_C(2080376211), // SHLLV_S_W
2321
42.7k
    UINT64_C(981),  // SHLLV_S_W_MM
2322
42.7k
    UINT64_C(2080375315), // SHLL_PH
2323
42.7k
    UINT64_C(949),  // SHLL_PH_MM
2324
42.7k
    UINT64_C(2080374803), // SHLL_QB
2325
42.7k
    UINT64_C(2172), // SHLL_QB_MM
2326
42.7k
    UINT64_C(2080375571), // SHLL_S_PH
2327
42.7k
    UINT64_C(2997), // SHLL_S_PH_MM
2328
42.7k
    UINT64_C(2080376083), // SHLL_S_W
2329
42.7k
    UINT64_C(1013), // SHLL_S_W_MM
2330
42.7k
    UINT64_C(2080375507), // SHRAV_PH
2331
42.7k
    UINT64_C(397),  // SHRAV_PH_MM
2332
42.7k
    UINT64_C(2080375187), // SHRAV_QB
2333
42.7k
    UINT64_C(461),  // SHRAV_QB_MMR2
2334
42.7k
    UINT64_C(2080375763), // SHRAV_R_PH
2335
42.7k
    UINT64_C(1421), // SHRAV_R_PH_MM
2336
42.7k
    UINT64_C(2080375251), // SHRAV_R_QB
2337
42.7k
    UINT64_C(1485), // SHRAV_R_QB_MMR2
2338
42.7k
    UINT64_C(2080376275), // SHRAV_R_W
2339
42.7k
    UINT64_C(725),  // SHRAV_R_W_MM
2340
42.7k
    UINT64_C(2080375379), // SHRA_PH
2341
42.7k
    UINT64_C(821),  // SHRA_PH_MM
2342
42.7k
    UINT64_C(2080375059), // SHRA_QB
2343
42.7k
    UINT64_C(508),  // SHRA_QB_MMR2
2344
42.7k
    UINT64_C(2080375635), // SHRA_R_PH
2345
42.7k
    UINT64_C(1845), // SHRA_R_PH_MM
2346
42.7k
    UINT64_C(2080375123), // SHRA_R_QB
2347
42.7k
    UINT64_C(4604), // SHRA_R_QB_MMR2
2348
42.7k
    UINT64_C(2080376147), // SHRA_R_W
2349
42.7k
    UINT64_C(757),  // SHRA_R_W_MM
2350
42.7k
    UINT64_C(2080376531), // SHRLV_PH
2351
42.7k
    UINT64_C(789),  // SHRLV_PH_MMR2
2352
42.7k
    UINT64_C(2080374995), // SHRLV_QB
2353
42.7k
    UINT64_C(853),  // SHRLV_QB_MM
2354
42.7k
    UINT64_C(2080376403), // SHRL_PH
2355
42.7k
    UINT64_C(1020), // SHRL_PH_MMR2
2356
42.7k
    UINT64_C(2080374867), // SHRL_QB
2357
42.7k
    UINT64_C(6268), // SHRL_QB_MM
2358
42.7k
    UINT64_C(939524096),  // SH_MM
2359
42.7k
    UINT64_C(939524096),  // SH_MMR6
2360
42.7k
    UINT64_C(68616192), // SIGRIE
2361
42.7k
    UINT64_C(63), // SIGRIE_MMR6
2362
42.7k
    UINT64_C(2013265945), // SLDI_B
2363
42.7k
    UINT64_C(2016935961), // SLDI_D
2364
42.7k
    UINT64_C(2015363097), // SLDI_H
2365
42.7k
    UINT64_C(2016411673), // SLDI_W
2366
42.7k
    UINT64_C(2013265940), // SLD_B
2367
42.7k
    UINT64_C(2019557396), // SLD_D
2368
42.7k
    UINT64_C(2015363092), // SLD_H
2369
42.7k
    UINT64_C(2017460244), // SLD_W
2370
42.7k
    UINT64_C(0),  // SLL
2371
42.7k
    UINT64_C(9216), // SLL16_MM
2372
42.7k
    UINT64_C(9216), // SLL16_MMR6
2373
42.7k
    UINT64_C(0),  // SLL64_32
2374
42.7k
    UINT64_C(0),  // SLL64_64
2375
42.7k
    UINT64_C(2020605961), // SLLI_B
2376
42.7k
    UINT64_C(2013265929), // SLLI_D
2377
42.7k
    UINT64_C(2019557385), // SLLI_H
2378
42.7k
    UINT64_C(2017460233), // SLLI_W
2379
42.7k
    UINT64_C(4),  // SLLV
2380
42.7k
    UINT64_C(16), // SLLV_MM
2381
42.7k
    UINT64_C(2013265933), // SLL_B
2382
42.7k
    UINT64_C(2019557389), // SLL_D
2383
42.7k
    UINT64_C(2015363085), // SLL_H
2384
42.7k
    UINT64_C(0),  // SLL_MM
2385
42.7k
    UINT64_C(0),  // SLL_MMR6
2386
42.7k
    UINT64_C(2017460237), // SLL_W
2387
42.7k
    UINT64_C(42), // SLT
2388
42.7k
    UINT64_C(42), // SLT64
2389
42.7k
    UINT64_C(848),  // SLT_MM
2390
42.7k
    UINT64_C(671088640),  // SLTi
2391
42.7k
    UINT64_C(671088640),  // SLTi64
2392
42.7k
    UINT64_C(2415919104), // SLTi_MM
2393
42.7k
    UINT64_C(738197504),  // SLTiu
2394
42.7k
    UINT64_C(738197504),  // SLTiu64
2395
42.7k
    UINT64_C(2952790016), // SLTiu_MM
2396
42.7k
    UINT64_C(43), // SLTu
2397
42.7k
    UINT64_C(43), // SLTu64
2398
42.7k
    UINT64_C(912),  // SLTu_MM
2399
42.7k
    UINT64_C(1879048235), // SNE
2400
42.7k
    UINT64_C(1879048239), // SNEi
2401
42.7k
    UINT64_C(2017460249), // SPLATI_B
2402
42.7k
    UINT64_C(2021130265), // SPLATI_D
2403
42.7k
    UINT64_C(2019557401), // SPLATI_H
2404
42.7k
    UINT64_C(2020605977), // SPLATI_W
2405
42.7k
    UINT64_C(2021654548), // SPLAT_B
2406
42.7k
    UINT64_C(2027946004), // SPLAT_D
2407
42.7k
    UINT64_C(2023751700), // SPLAT_H
2408
42.7k
    UINT64_C(2025848852), // SPLAT_W
2409
42.7k
    UINT64_C(3),  // SRA
2410
42.7k
    UINT64_C(2028994569), // SRAI_B
2411
42.7k
    UINT64_C(2021654537), // SRAI_D
2412
42.7k
    UINT64_C(2027945993), // SRAI_H
2413
42.7k
    UINT64_C(2025848841), // SRAI_W
2414
42.7k
    UINT64_C(2037383178), // SRARI_B
2415
42.7k
    UINT64_C(2030043146), // SRARI_D
2416
42.7k
    UINT64_C(2036334602), // SRARI_H
2417
42.7k
    UINT64_C(2034237450), // SRARI_W
2418
42.7k
    UINT64_C(2021654549), // SRAR_B
2419
42.7k
    UINT64_C(2027946005), // SRAR_D
2420
42.7k
    UINT64_C(2023751701), // SRAR_H
2421
42.7k
    UINT64_C(2025848853), // SRAR_W
2422
42.7k
    UINT64_C(7),  // SRAV
2423
42.7k
    UINT64_C(144),  // SRAV_MM
2424
42.7k
    UINT64_C(2021654541), // SRA_B
2425
42.7k
    UINT64_C(2027945997), // SRA_D
2426
42.7k
    UINT64_C(2023751693), // SRA_H
2427
42.7k
    UINT64_C(128),  // SRA_MM
2428
42.7k
    UINT64_C(2025848845), // SRA_W
2429
42.7k
    UINT64_C(2),  // SRL
2430
42.7k
    UINT64_C(9217), // SRL16_MM
2431
42.7k
    UINT64_C(9217), // SRL16_MMR6
2432
42.7k
    UINT64_C(2037383177), // SRLI_B
2433
42.7k
    UINT64_C(2030043145), // SRLI_D
2434
42.7k
    UINT64_C(2036334601), // SRLI_H
2435
42.7k
    UINT64_C(2034237449), // SRLI_W
2436
42.7k
    UINT64_C(2045771786), // SRLRI_B
2437
42.7k
    UINT64_C(2038431754), // SRLRI_D
2438
42.7k
    UINT64_C(2044723210), // SRLRI_H
2439
42.7k
    UINT64_C(2042626058), // SRLRI_W
2440
42.7k
    UINT64_C(2030043157), // SRLR_B
2441
42.7k
    UINT64_C(2036334613), // SRLR_D
2442
42.7k
    UINT64_C(2032140309), // SRLR_H
2443
42.7k
    UINT64_C(2034237461), // SRLR_W
2444
42.7k
    UINT64_C(6),  // SRLV
2445
42.7k
    UINT64_C(80), // SRLV_MM
2446
42.7k
    UINT64_C(2030043149), // SRL_B
2447
42.7k
    UINT64_C(2036334605), // SRL_D
2448
42.7k
    UINT64_C(2032140301), // SRL_H
2449
42.7k
    UINT64_C(64), // SRL_MM
2450
42.7k
    UINT64_C(2034237453), // SRL_W
2451
42.7k
    UINT64_C(64), // SSNOP
2452
42.7k
    UINT64_C(2048), // SSNOP_MM
2453
42.7k
    UINT64_C(2048), // SSNOP_MMR6
2454
42.7k
    UINT64_C(2013265956), // ST_B
2455
42.7k
    UINT64_C(2013265959), // ST_D
2456
42.7k
    UINT64_C(2013265957), // ST_H
2457
42.7k
    UINT64_C(2013265958), // ST_W
2458
42.7k
    UINT64_C(34), // SUB
2459
42.7k
    UINT64_C(2080375384), // SUBQH_PH
2460
42.7k
    UINT64_C(589),  // SUBQH_PH_MMR2
2461
42.7k
    UINT64_C(2080375512), // SUBQH_R_PH
2462
42.7k
    UINT64_C(1613), // SUBQH_R_PH_MMR2
2463
42.7k
    UINT64_C(2080376024), // SUBQH_R_W
2464
42.7k
    UINT64_C(1677), // SUBQH_R_W_MMR2
2465
42.7k
    UINT64_C(2080375896), // SUBQH_W
2466
42.7k
    UINT64_C(653),  // SUBQH_W_MMR2
2467
42.7k
    UINT64_C(2080375504), // SUBQ_PH
2468
42.7k
    UINT64_C(525),  // SUBQ_PH_MM
2469
42.7k
    UINT64_C(2080375760), // SUBQ_S_PH
2470
42.7k
    UINT64_C(1549), // SUBQ_S_PH_MM
2471
42.7k
    UINT64_C(2080376272), // SUBQ_S_W
2472
42.7k
    UINT64_C(837),  // SUBQ_S_W_MM
2473
42.7k
    UINT64_C(2030043153), // SUBSUS_U_B
2474
42.7k
    UINT64_C(2036334609), // SUBSUS_U_D
2475
42.7k
    UINT64_C(2032140305), // SUBSUS_U_H
2476
42.7k
    UINT64_C(2034237457), // SUBSUS_U_W
2477
42.7k
    UINT64_C(2038431761), // SUBSUU_S_B
2478
42.7k
    UINT64_C(2044723217), // SUBSUU_S_D
2479
42.7k
    UINT64_C(2040528913), // SUBSUU_S_H
2480
42.7k
    UINT64_C(2042626065), // SUBSUU_S_W
2481
42.7k
    UINT64_C(2013265937), // SUBS_S_B
2482
42.7k
    UINT64_C(2019557393), // SUBS_S_D
2483
42.7k
    UINT64_C(2015363089), // SUBS_S_H
2484
42.7k
    UINT64_C(2017460241), // SUBS_S_W
2485
42.7k
    UINT64_C(2021654545), // SUBS_U_B
2486
42.7k
    UINT64_C(2027946001), // SUBS_U_D
2487
42.7k
    UINT64_C(2023751697), // SUBS_U_H
2488
42.7k
    UINT64_C(2025848849), // SUBS_U_W
2489
42.7k
    UINT64_C(1025), // SUBU16_MM
2490
42.7k
    UINT64_C(1025), // SUBU16_MMR6
2491
42.7k
    UINT64_C(2080374872), // SUBUH_QB
2492
42.7k
    UINT64_C(845),  // SUBUH_QB_MMR2
2493
42.7k
    UINT64_C(2080375000), // SUBUH_R_QB
2494
42.7k
    UINT64_C(1869), // SUBUH_R_QB_MMR2
2495
42.7k
    UINT64_C(464),  // SUBU_MMR6
2496
42.7k
    UINT64_C(2080375376), // SUBU_PH
2497
42.7k
    UINT64_C(781),  // SUBU_PH_MMR2
2498
42.7k
    UINT64_C(2080374864), // SUBU_QB
2499
42.7k
    UINT64_C(717),  // SUBU_QB_MM
2500
42.7k
    UINT64_C(2080375632), // SUBU_S_PH
2501
42.7k
    UINT64_C(1805), // SUBU_S_PH_MMR2
2502
42.7k
    UINT64_C(2080375120), // SUBU_S_QB
2503
42.7k
    UINT64_C(1741), // SUBU_S_QB_MM
2504
42.7k
    UINT64_C(2021654534), // SUBVI_B
2505
42.7k
    UINT64_C(2027945990), // SUBVI_D
2506
42.7k
    UINT64_C(2023751686), // SUBVI_H
2507
42.7k
    UINT64_C(2025848838), // SUBVI_W
2508
42.7k
    UINT64_C(2021654542), // SUBV_B
2509
42.7k
    UINT64_C(2027945998), // SUBV_D
2510
42.7k
    UINT64_C(2023751694), // SUBV_H
2511
42.7k
    UINT64_C(2025848846), // SUBV_W
2512
42.7k
    UINT64_C(400),  // SUB_MM
2513
42.7k
    UINT64_C(400),  // SUB_MMR6
2514
42.7k
    UINT64_C(35), // SUBu
2515
42.7k
    UINT64_C(464),  // SUBu_MM
2516
42.7k
    UINT64_C(1275068429), // SUXC1
2517
42.7k
    UINT64_C(1275068429), // SUXC164
2518
42.7k
    UINT64_C(1409286536), // SUXC1_MM
2519
42.7k
    UINT64_C(2885681152), // SW
2520
42.7k
    UINT64_C(59392),  // SW16_MM
2521
42.7k
    UINT64_C(59392),  // SW16_MMR6
2522
42.7k
    UINT64_C(2885681152), // SW64
2523
42.7k
    UINT64_C(3825205248), // SWC1
2524
42.7k
    UINT64_C(2550136832), // SWC1_MM
2525
42.7k
    UINT64_C(3892314112), // SWC2
2526
42.7k
    UINT64_C(536903680),  // SWC2_MMR6
2527
42.7k
    UINT64_C(1231028224), // SWC2_R6
2528
42.7k
    UINT64_C(3959422976), // SWC3
2529
42.7k
    UINT64_C(2885681152), // SWDSP
2530
42.7k
    UINT64_C(4160749568), // SWDSP_MM
2531
42.7k
    UINT64_C(2080374815), // SWE
2532
42.7k
    UINT64_C(1610657280), // SWE_MM
2533
42.7k
    UINT64_C(2818572288), // SWL
2534
42.7k
    UINT64_C(2818572288), // SWL64
2535
42.7k
    UINT64_C(2080374817), // SWLE
2536
42.7k
    UINT64_C(1610653696), // SWLE_MM
2537
42.7k
    UINT64_C(1610645504), // SWL_MM
2538
42.7k
    UINT64_C(17728),  // SWM16_MM
2539
42.7k
    UINT64_C(17418),  // SWM16_MMR6
2540
42.7k
    UINT64_C(536924160),  // SWM32_MM
2541
42.7k
    UINT64_C(536907776),  // SWP_MM
2542
42.7k
    UINT64_C(3087007744), // SWR
2543
42.7k
    UINT64_C(3087007744), // SWR64
2544
42.7k
    UINT64_C(2080374818), // SWRE
2545
42.7k
    UINT64_C(1610654208), // SWRE_MM
2546
42.7k
    UINT64_C(1610649600), // SWR_MM
2547
42.7k
    UINT64_C(51200),  // SWSP_MM
2548
42.7k
    UINT64_C(51200),  // SWSP_MMR6
2549
42.7k
    UINT64_C(1275068424), // SWXC1
2550
42.7k
    UINT64_C(1409286280), // SWXC1_MM
2551
42.7k
    UINT64_C(4160749568), // SW_MM
2552
42.7k
    UINT64_C(4160749568), // SW_MMR6
2553
42.7k
    UINT64_C(15), // SYNC
2554
42.7k
    UINT64_C(69140480), // SYNCI
2555
42.7k
    UINT64_C(1107296256), // SYNCI_MM
2556
42.7k
    UINT64_C(1098907648), // SYNCI_MMR6
2557
42.7k
    UINT64_C(27516),  // SYNC_MM
2558
42.7k
    UINT64_C(27516),  // SYNC_MMR6
2559
42.7k
    UINT64_C(12), // SYSCALL
2560
42.7k
    UINT64_C(35708),  // SYSCALL_MM
2561
42.7k
    UINT64_C(25728),  // Save16
2562
42.7k
    UINT64_C(25728),  // SaveX16
2563
42.7k
    UINT64_C(4026580992), // SbRxRyOffMemX16
2564
42.7k
    UINT64_C(59537),  // SebRx16
2565
42.7k
    UINT64_C(59569),  // SehRx16
2566
42.7k
    UINT64_C(4026583040), // ShRxRyOffMemX16
2567
42.7k
    UINT64_C(4026544128), // SllX16
2568
42.7k
    UINT64_C(59396),  // SllvRxRy16
2569
42.7k
    UINT64_C(59394),  // SltRxRy16
2570
42.7k
    UINT64_C(20480),  // SltiRxImm16
2571
42.7k
    UINT64_C(4026552320), // SltiRxImmX16
2572
42.7k
    UINT64_C(22528),  // SltiuRxImm16
2573
42.7k
    UINT64_C(4026554368), // SltiuRxImmX16
2574
42.7k
    UINT64_C(59395),  // SltuRxRy16
2575
42.7k
    UINT64_C(4026544131), // SraX16
2576
42.7k
    UINT64_C(59399),  // SravRxRy16
2577
42.7k
    UINT64_C(4026544130), // SrlX16
2578
42.7k
    UINT64_C(59398),  // SrlvRxRy16
2579
42.7k
    UINT64_C(57347),  // SubuRxRyRz16
2580
42.7k
    UINT64_C(4026587136), // SwRxRyOffMemX16
2581
42.7k
    UINT64_C(4026585088), // SwRxSpImmX16
2582
42.7k
    UINT64_C(52), // TEQ
2583
42.7k
    UINT64_C(67895296), // TEQI
2584
42.7k
    UINT64_C(1103101952), // TEQI_MM
2585
42.7k
    UINT64_C(60), // TEQ_MM
2586
42.7k
    UINT64_C(48), // TGE
2587
42.7k
    UINT64_C(67633152), // TGEI
2588
42.7k
    UINT64_C(67698688), // TGEIU
2589
42.7k
    UINT64_C(1096810496), // TGEIU_MM
2590
42.7k
    UINT64_C(1092616192), // TGEI_MM
2591
42.7k
    UINT64_C(49), // TGEU
2592
42.7k
    UINT64_C(1084), // TGEU_MM
2593
42.7k
    UINT64_C(572),  // TGE_MM
2594
42.7k
    UINT64_C(1107296267), // TLBGINV
2595
42.7k
    UINT64_C(1107296268), // TLBGINVF
2596
42.7k
    UINT64_C(20860),  // TLBGINVF_MM
2597
42.7k
    UINT64_C(16764),  // TLBGINV_MM
2598
42.7k
    UINT64_C(1107296272), // TLBGP
2599
42.7k
    UINT64_C(380),  // TLBGP_MM
2600
42.7k
    UINT64_C(1107296265), // TLBGR
2601
42.7k
    UINT64_C(4476), // TLBGR_MM
2602
42.7k
    UINT64_C(1107296266), // TLBGWI
2603
42.7k
    UINT64_C(8572), // TLBGWI_MM
2604
42.7k
    UINT64_C(1107296270), // TLBGWR
2605
42.7k
    UINT64_C(12668),  // TLBGWR_MM
2606
42.7k
    UINT64_C(1107296259), // TLBINV
2607
42.7k
    UINT64_C(1107296260), // TLBINVF
2608
42.7k
    UINT64_C(21372),  // TLBINVF_MMR6
2609
42.7k
    UINT64_C(17276),  // TLBINV_MMR6
2610
42.7k
    UINT64_C(1107296264), // TLBP
2611
42.7k
    UINT64_C(892),  // TLBP_MM
2612
42.7k
    UINT64_C(1107296257), // TLBR
2613
42.7k
    UINT64_C(4988), // TLBR_MM
2614
42.7k
    UINT64_C(1107296258), // TLBWI
2615
42.7k
    UINT64_C(9084), // TLBWI_MM
2616
42.7k
    UINT64_C(1107296262), // TLBWR
2617
42.7k
    UINT64_C(13180),  // TLBWR_MM
2618
42.7k
    UINT64_C(50), // TLT
2619
42.7k
    UINT64_C(67764224), // TLTI
2620
42.7k
    UINT64_C(1094713344), // TLTIU_MM
2621
42.7k
    UINT64_C(1090519040), // TLTI_MM
2622
42.7k
    UINT64_C(51), // TLTU
2623
42.7k
    UINT64_C(2620), // TLTU_MM
2624
42.7k
    UINT64_C(2108), // TLT_MM
2625
42.7k
    UINT64_C(54), // TNE
2626
42.7k
    UINT64_C(68026368), // TNEI
2627
42.7k
    UINT64_C(1098907648), // TNEI_MM
2628
42.7k
    UINT64_C(3132), // TNE_MM
2629
42.7k
    UINT64_C(1176502281), // TRUNC_L_D64
2630
42.7k
    UINT64_C(1409311547), // TRUNC_L_D_MMR6
2631
42.7k
    UINT64_C(1174405129), // TRUNC_L_S
2632
42.7k
    UINT64_C(1409295163), // TRUNC_L_S_MMR6
2633
42.7k
    UINT64_C(1176502285), // TRUNC_W_D32
2634
42.7k
    UINT64_C(1176502285), // TRUNC_W_D64
2635
42.7k
    UINT64_C(1409313595), // TRUNC_W_D_MMR6
2636
42.7k
    UINT64_C(1409313595), // TRUNC_W_MM
2637
42.7k
    UINT64_C(1174405133), // TRUNC_W_S
2638
42.7k
    UINT64_C(1409297211), // TRUNC_W_S_MM
2639
42.7k
    UINT64_C(1409297211), // TRUNC_W_S_MMR6
2640
42.7k
    UINT64_C(67829760), // TTLTIU
2641
42.7k
    UINT64_C(27), // UDIV
2642
42.7k
    UINT64_C(47932),  // UDIV_MM
2643
42.7k
    UINT64_C(1879048209), // V3MULU
2644
42.7k
    UINT64_C(1879048208), // VMM0
2645
42.7k
    UINT64_C(1879048207), // VMULU
2646
42.7k
    UINT64_C(2013265941), // VSHF_B
2647
42.7k
    UINT64_C(2019557397), // VSHF_D
2648
42.7k
    UINT64_C(2015363093), // VSHF_H
2649
42.7k
    UINT64_C(2017460245), // VSHF_W
2650
42.7k
    UINT64_C(1107296288), // WAIT
2651
42.7k
    UINT64_C(37756),  // WAIT_MM
2652
42.7k
    UINT64_C(37756),  // WAIT_MMR6
2653
42.7k
    UINT64_C(2080376056), // WRDSP
2654
42.7k
    UINT64_C(5756), // WRDSP_MM
2655
42.7k
    UINT64_C(61820),  // WRPGPR_MMR6
2656
42.7k
    UINT64_C(2080374944), // WSBH
2657
42.7k
    UINT64_C(31548),  // WSBH_MM
2658
42.7k
    UINT64_C(31548),  // WSBH_MMR6
2659
42.7k
    UINT64_C(38), // XOR
2660
42.7k
    UINT64_C(17472),  // XOR16_MM
2661
42.7k
    UINT64_C(17416),  // XOR16_MMR6
2662
42.7k
    UINT64_C(38), // XOR64
2663
42.7k
    UINT64_C(2063597568), // XORI_B
2664
42.7k
    UINT64_C(1879048192), // XORI_MMR6
2665
42.7k
    UINT64_C(784),  // XOR_MM
2666
42.7k
    UINT64_C(784),  // XOR_MMR6
2667
42.7k
    UINT64_C(2019557406), // XOR_V
2668
42.7k
    UINT64_C(939524096),  // XORi
2669
42.7k
    UINT64_C(939524096),  // XORi64
2670
42.7k
    UINT64_C(1879048192), // XORi_MM
2671
42.7k
    UINT64_C(59406),  // XorRxRxRy16
2672
42.7k
    UINT64_C(2080374793), // YIELD
2673
42.7k
    UINT64_C(0)
2674
42.7k
  };
2675
42.7k
  const unsigned opcode = MI.getOpcode();
2676
42.7k
  uint64_t Value = InstBits[opcode];
2677
42.7k
  uint64_t op = 0;
2678
42.7k
  (void)op;  // suppress warning
2679
42.7k
  switch (opcode) {
2680
42.7k
    case Mips::Break16:
2681
195
    case Mips::DERET:
2682
195
    case Mips::DERET_MM:
2683
195
    case Mips::DERET_MMR6:
2684
195
    case Mips::EHB:
2685
195
    case Mips::EHB_MM:
2686
195
    case Mips::EHB_MMR6:
2687
195
    case Mips::ERET:
2688
195
    case Mips::ERETNC:
2689
195
    case Mips::ERETNC_MMR6:
2690
195
    case Mips::ERET_MM:
2691
195
    case Mips::ERET_MMR6:
2692
195
    case Mips::JrRa16:
2693
195
    case Mips::JrcRa16:
2694
195
    case Mips::PAUSE:
2695
195
    case Mips::PAUSE_MM:
2696
195
    case Mips::PAUSE_MMR6:
2697
195
    case Mips::Restore16:
2698
195
    case Mips::RestoreX16:
2699
195
    case Mips::SSNOP:
2700
195
    case Mips::SSNOP_MM:
2701
195
    case Mips::SSNOP_MMR6:
2702
195
    case Mips::Save16:
2703
195
    case Mips::SaveX16:
2704
195
    case Mips::TLBGINV:
2705
195
    case Mips::TLBGINVF:
2706
195
    case Mips::TLBGINVF_MM:
2707
195
    case Mips::TLBGINV_MM:
2708
195
    case Mips::TLBGP:
2709
195
    case Mips::TLBGP_MM:
2710
195
    case Mips::TLBGR:
2711
195
    case Mips::TLBGR_MM:
2712
195
    case Mips::TLBGWI:
2713
195
    case Mips::TLBGWI_MM:
2714
195
    case Mips::TLBGWR:
2715
195
    case Mips::TLBGWR_MM:
2716
195
    case Mips::TLBINV:
2717
195
    case Mips::TLBINVF:
2718
195
    case Mips::TLBINVF_MMR6:
2719
195
    case Mips::TLBINV_MMR6:
2720
195
    case Mips::TLBP:
2721
195
    case Mips::TLBP_MM:
2722
195
    case Mips::TLBR:
2723
195
    case Mips::TLBR_MM:
2724
195
    case Mips::TLBWI:
2725
195
    case Mips::TLBWI_MM:
2726
195
    case Mips::TLBWR:
2727
195
    case Mips::TLBWR_MM:
2728
195
    case Mips::WAIT: {
2729
195
      break;
2730
195
    }
2731
195
    case Mips::MTHLIP:
2732
4
    case Mips::SHILOV: {
2733
4
      // op: ac
2734
4
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2735
4
      Value |= (op & UINT64_C(3)) << 11;
2736
4
      // op: rs
2737
4
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
2738
4
      Value |= (op & UINT64_C(31)) << 21;
2739
4
      break;
2740
4
    }
2741
47
    case Mips::DPAQX_SA_W_PH:
2742
47
    case Mips::DPAQX_S_W_PH:
2743
47
    case Mips::DPAQ_SA_L_W:
2744
47
    case Mips::DPAQ_S_W_PH:
2745
47
    case Mips::DPAU_H_QBL:
2746
47
    case Mips::DPAU_H_QBR:
2747
47
    case Mips::DPAX_W_PH:
2748
47
    case Mips::DPA_W_PH:
2749
47
    case Mips::DPSQX_SA_W_PH:
2750
47
    case Mips::DPSQX_S_W_PH:
2751
47
    case Mips::DPSQ_SA_L_W:
2752
47
    case Mips::DPSQ_S_W_PH:
2753
47
    case Mips::DPSU_H_QBL:
2754
47
    case Mips::DPSU_H_QBR:
2755
47
    case Mips::DPSX_W_PH:
2756
47
    case Mips::DPS_W_PH:
2757
47
    case Mips::MADDU_DSP:
2758
47
    case Mips::MADD_DSP:
2759
47
    case Mips::MAQ_SA_W_PHL:
2760
47
    case Mips::MAQ_SA_W_PHR:
2761
47
    case Mips::MAQ_S_W_PHL:
2762
47
    case Mips::MAQ_S_W_PHR:
2763
47
    case Mips::MSUBU_DSP:
2764
47
    case Mips::MSUB_DSP:
2765
47
    case Mips::MULSAQ_S_W_PH:
2766
47
    case Mips::MULSA_W_PH:
2767
47
    case Mips::MULTU_DSP:
2768
47
    case Mips::MULT_DSP: {
2769
47
      // op: ac
2770
47
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2771
47
      Value |= (op & UINT64_C(3)) << 11;
2772
47
      // op: rs
2773
47
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
2774
47
      Value |= (op & UINT64_C(31)) << 21;
2775
47
      // op: rt
2776
47
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
2777
47
      Value |= (op & UINT64_C(31)) << 16;
2778
47
      break;
2779
47
    }
2780
47
    case Mips::SHILO: {
2781
4
      // op: ac
2782
4
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2783
4
      Value |= (op & UINT64_C(3)) << 11;
2784
4
      // op: shift
2785
4
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
2786
4
      Value |= (op & UINT64_C(63)) << 20;
2787
4
      break;
2788
47
    }
2789
54
    case Mips::CACHEE:
2790
54
    case Mips::CACHE_R6:
2791
54
    case Mips::PREFE:
2792
54
    case Mips::PREF_R6: {
2793
54
      // op: addr
2794
54
      op = getMemEncoding(MI, 0, Fixups, STI);
2795
54
      Value |= (op & UINT64_C(2031616)) << 5;
2796
54
      Value |= (op & UINT64_C(511)) << 7;
2797
54
      // op: hint
2798
54
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
2799
54
      Value |= (op & UINT64_C(31)) << 16;
2800
54
      break;
2801
54
    }
2802
54
    case Mips::SYNCI: {
2803
8
      // op: addr
2804
8
      op = getMemEncoding(MI, 0, Fixups, STI);
2805
8
      Value |= (op & UINT64_C(2031616)) << 5;
2806
8
      Value |= op & UINT64_C(65535);
2807
8
      break;
2808
54
    }
2809
54
    case Mips::CACHE:
2810
21
    case Mips::PREF: {
2811
21
      // op: addr
2812
21
      op = getMemEncoding(MI, 0, Fixups, STI);
2813
21
      Value |= (op & UINT64_C(2031616)) << 5;
2814
21
      Value |= op & UINT64_C(65535);
2815
21
      // op: hint
2816
21
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
2817
21
      Value |= (op & UINT64_C(31)) << 16;
2818
21
      break;
2819
21
    }
2820
21
    case Mips::LD_B:
2821
3
    case Mips::ST_B: {
2822
3
      // op: addr
2823
3
      op = getMemEncoding(MI, 1, Fixups, STI);
2824
3
      Value |= (op & UINT64_C(1023)) << 16;
2825
3
      Value |= (op & UINT64_C(2031616)) >> 5;
2826
3
      // op: wd
2827
3
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2828
3
      Value |= (op & UINT64_C(31)) << 6;
2829
3
      break;
2830
3
    }
2831
303
    case Mips::LBE:
2832
303
    case Mips::LBuE:
2833
303
    case Mips::LHE:
2834
303
    case Mips::LHuE:
2835
303
    case Mips::LLE:
2836
303
    case Mips::LWE:
2837
303
    case Mips::LWLE:
2838
303
    case Mips::LWRE:
2839
303
    case Mips::SBE:
2840
303
    case Mips::SHE:
2841
303
    case Mips::SWE:
2842
303
    case Mips::SWLE:
2843
303
    case Mips::SWRE: {
2844
303
      // op: addr
2845
303
      op = getMemEncoding(MI, 1, Fixups, STI);
2846
303
      Value |= (op & UINT64_C(2031616)) << 5;
2847
303
      Value |= (op & UINT64_C(511)) << 7;
2848
303
      // op: hint
2849
303
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2850
303
      Value |= (op & UINT64_C(31)) << 16;
2851
303
      break;
2852
303
    }
2853
303
    case Mips::SCE: {
2854
25
      // op: addr
2855
25
      op = getMemEncoding(MI, 2, Fixups, STI);
2856
25
      Value |= (op & UINT64_C(2031616)) << 5;
2857
25
      Value |= (op & UINT64_C(511)) << 7;
2858
25
      // op: hint
2859
25
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2860
25
      Value |= (op & UINT64_C(31)) << 16;
2861
25
      break;
2862
303
    }
2863
303
    case Mips::LD_H:
2864
5
    case Mips::ST_H: {
2865
5
      // op: addr
2866
5
      op = getMemEncoding<1>(MI, 1, Fixups, STI);
2867
5
      Value |= (op & UINT64_C(1023)) << 16;
2868
5
      Value |= (op & UINT64_C(2031616)) >> 5;
2869
5
      // op: wd
2870
5
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2871
5
      Value |= (op & UINT64_C(31)) << 6;
2872
5
      break;
2873
5
    }
2874
6
    case Mips::LD_W:
2875
6
    case Mips::ST_W: {
2876
6
      // op: addr
2877
6
      op = getMemEncoding<2>(MI, 1, Fixups, STI);
2878
6
      Value |= (op & UINT64_C(1023)) << 16;
2879
6
      Value |= (op & UINT64_C(2031616)) >> 5;
2880
6
      // op: wd
2881
6
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2882
6
      Value |= (op & UINT64_C(31)) << 6;
2883
6
      break;
2884
6
    }
2885
9
    case Mips::LD_D:
2886
9
    case Mips::ST_D: {
2887
9
      // op: addr
2888
9
      op = getMemEncoding<3>(MI, 1, Fixups, STI);
2889
9
      Value |= (op & UINT64_C(1023)) << 16;
2890
9
      Value |= (op & UINT64_C(2031616)) >> 5;
2891
9
      // op: wd
2892
9
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2893
9
      Value |= (op & UINT64_C(31)) << 6;
2894
9
      break;
2895
9
    }
2896
9
    case Mips::CACHE_MM:
2897
8
    case Mips::CACHE_MMR6:
2898
8
    case Mips::PREF_MM:
2899
8
    case Mips::PREF_MMR6: {
2900
8
      // op: addr
2901
8
      op = getMemEncodingMMImm12(MI, 0, Fixups, STI);
2902
8
      Value |= op & UINT64_C(2031616);
2903
8
      Value |= op & UINT64_C(4095);
2904
8
      // op: hint
2905
8
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
2906
8
      Value |= (op & UINT64_C(31)) << 21;
2907
8
      break;
2908
8
    }
2909
8
    case Mips::SYNCI_MM:
2910
2
    case Mips::SYNCI_MMR6: {
2911
2
      // op: addr
2912
2
      op = getMemEncodingMMImm16(MI, 0, Fixups, STI);
2913
2
      Value |= op & UINT64_C(2097151);
2914
2
      break;
2915
2
    }
2916
2
    case Mips::LBU_MMR6:
2917
2
    case Mips::LB_MMR6: {
2918
2
      // op: addr
2919
2
      op = getMemEncodingMMImm16(MI, 1, Fixups, STI);
2920
2
      Value |= op & UINT64_C(2097151);
2921
2
      // op: rt
2922
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2923
2
      Value |= (op & UINT64_C(31)) << 21;
2924
2
      break;
2925
2
    }
2926
12
    case Mips::CACHEE_MM:
2927
12
    case Mips::PREFE_MM: {
2928
12
      // op: addr
2929
12
      op = getMemEncodingMMImm9(MI, 0, Fixups, STI);
2930
12
      Value |= op & UINT64_C(2031616);
2931
12
      Value |= op & UINT64_C(511);
2932
12
      // op: hint
2933
12
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
2934
12
      Value |= (op & UINT64_C(31)) << 21;
2935
12
      break;
2936
12
    }
2937
12
    case Mips::HYPCALL: {
2938
7
      // op: code_
2939
7
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2940
7
      Value |= (op & UINT64_C(1023)) << 11;
2941
7
      break;
2942
12
    }
2943
22
    case Mips::HYPCALL_MM:
2944
22
    case Mips::SDBBP_MM:
2945
22
    case Mips::SDBBP_MMR6:
2946
22
    case Mips::SYSCALL_MM:
2947
22
    case Mips::WAIT_MM:
2948
22
    case Mips::WAIT_MMR6: {
2949
22
      // op: code_
2950
22
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2951
22
      Value |= (op & UINT64_C(1023)) << 16;
2952
22
      break;
2953
22
    }
2954
53
    case Mips::SDBBP:
2955
53
    case Mips::SDBBP_R6:
2956
53
    case Mips::SYSCALL: {
2957
53
      // op: code_
2958
53
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2959
53
      Value |= (op & UINT64_C(1048575)) << 6;
2960
53
      break;
2961
53
    }
2962
53
    case Mips::BREAK16_MMR6:
2963
2
    case Mips::SDBBP16_MMR6: {
2964
2
      // op: code_
2965
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2966
2
      Value |= (op & UINT64_C(15)) << 6;
2967
2
      break;
2968
2
    }
2969
2
    case Mips::SIGRIE_MMR6: {
2970
2
      // op: code_
2971
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2972
2
      Value |= (op & UINT64_C(65535)) << 6;
2973
2
      break;
2974
2
    }
2975
6
    case Mips::BREAK16_MM:
2976
6
    case Mips::SDBBP16_MM: {
2977
6
      // op: code_
2978
6
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2979
6
      Value |= op & UINT64_C(15);
2980
6
      break;
2981
6
    }
2982
6
    case Mips::SIGRIE: {
2983
4
      // op: code_
2984
4
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2985
4
      Value |= op & UINT64_C(65535);
2986
4
      break;
2987
6
    }
2988
142
    case Mips::BREAK:
2989
142
    case Mips::BREAK_MM:
2990
142
    case Mips::BREAK_MMR6: {
2991
142
      // op: code_1
2992
142
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2993
142
      Value |= (op & UINT64_C(1023)) << 16;
2994
142
      // op: code_2
2995
142
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
2996
142
      Value |= (op & UINT64_C(1023)) << 6;
2997
142
      break;
2998
142
    }
2999
142
    case Mips::BC2EQZ:
3000
8
    case Mips::BC2NEZ: {
3001
8
      // op: ct
3002
8
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3003
8
      Value |= (op & UINT64_C(31)) << 16;
3004
8
      // op: offset
3005
8
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
3006
8
      Value |= op & UINT64_C(65535);
3007
8
      break;
3008
8
    }
3009
8
    case Mips::MOVEP_MMR6: {
3010
1
      // op: dst_regs
3011
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3012
1
      Value |= (op & UINT64_C(7)) << 7;
3013
1
      // op: rt
3014
1
      op = getMovePRegSingleOpValue(MI, 3, Fixups, STI);
3015
1
      Value |= (op & UINT64_C(7)) << 4;
3016
1
      // op: rs
3017
1
      op = getMovePRegSingleOpValue(MI, 2, Fixups, STI);
3018
1
      Value |= (op & UINT64_C(4)) << 1;
3019
1
      Value |= op & UINT64_C(3);
3020
1
      break;
3021
8
    }
3022
8
    case Mips::MOVEP_MM: {
3023
3
      // op: dst_regs
3024
3
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3025
3
      Value |= (op & UINT64_C(7)) << 7;
3026
3
      // op: rt
3027
3
      op = getMovePRegSingleOpValue(MI, 3, Fixups, STI);
3028
3
      Value |= (op & UINT64_C(7)) << 4;
3029
3
      // op: rs
3030
3
      op = getMovePRegSingleOpValue(MI, 2, Fixups, STI);
3031
3
      Value |= (op & UINT64_C(7)) << 1;
3032
3
      break;
3033
8
    }
3034
146
    case Mips::BC1F:
3035
146
    case Mips::BC1FL:
3036
146
    case Mips::BC1T:
3037
146
    case Mips::BC1TL: {
3038
146
      // op: fcc
3039
146
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3040
146
      Value |= (op & UINT64_C(7)) << 18;
3041
146
      // op: offset
3042
146
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
3043
146
      Value |= op & UINT64_C(65535);
3044
146
      break;
3045
146
    }
3046
146
    case Mips::BC1F_MM:
3047
9
    case Mips::BC1T_MM: {
3048
9
      // op: fcc
3049
9
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3050
9
      Value |= (op & UINT64_C(7)) << 18;
3051
9
      // op: offset
3052
9
      op = getBranchTargetOpValueMM(MI, 1, Fixups, STI);
3053
9
      Value |= op & UINT64_C(65535);
3054
9
      break;
3055
9
    }
3056
9
    case Mips::LUXC1_MM:
3057
2
    case Mips::LWXC1_MM: {
3058
2
      // op: fd
3059
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3060
2
      Value |= (op & UINT64_C(31)) << 11;
3061
2
      // op: base
3062
2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3063
2
      Value |= (op & UINT64_C(31)) << 16;
3064
2
      // op: index
3065
2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3066
2
      Value |= (op & UINT64_C(31)) << 21;
3067
2
      break;
3068
2
    }
3069
8
    case Mips::MOVN_I_D32_MM:
3070
8
    case Mips::MOVN_I_S_MM:
3071
8
    case Mips::MOVZ_I_D32_MM:
3072
8
    case Mips::MOVZ_I_S_MM: {
3073
8
      // op: fd
3074
8
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3075
8
      Value |= (op & UINT64_C(31)) << 11;
3076
8
      // op: fs
3077
8
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3078
8
      Value |= (op & UINT64_C(31)) << 16;
3079
8
      // op: rt
3080
8
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3081
8
      Value |= (op & UINT64_C(31)) << 21;
3082
8
      break;
3083
8
    }
3084
89
    case Mips::CEIL_W_MM:
3085
89
    case Mips::CEIL_W_S_MM:
3086
89
    case Mips::CVT_D32_S_MM:
3087
89
    case Mips::CVT_D32_W_MM:
3088
89
    case Mips::CVT_D64_S_MM:
3089
89
    case Mips::CVT_D64_W_MM:
3090
89
    case Mips::CVT_L_D64_MM:
3091
89
    case Mips::CVT_L_S_MM:
3092
89
    case Mips::CVT_S_D32_MM:
3093
89
    case Mips::CVT_S_D64_MM:
3094
89
    case Mips::CVT_S_W_MM:
3095
89
    case Mips::CVT_W_D32_MM:
3096
89
    case Mips::CVT_W_D64_MM:
3097
89
    case Mips::CVT_W_S_MM:
3098
89
    case Mips::FABS_D32_MM:
3099
89
    case Mips::FABS_D64_MM:
3100
89
    case Mips::FABS_S_MM:
3101
89
    case Mips::FLOOR_W_MM:
3102
89
    case Mips::FLOOR_W_S_MM:
3103
89
    case Mips::FMOV_D32_MM:
3104
89
    case Mips::FMOV_D64_MM:
3105
89
    case Mips::FMOV_S_MM:
3106
89
    case Mips::FNEG_D32_MM:
3107
89
    case Mips::FNEG_D64_MM:
3108
89
    case Mips::FNEG_S_MM:
3109
89
    case Mips::FSQRT_D32_MM:
3110
89
    case Mips::FSQRT_D64_MM:
3111
89
    case Mips::FSQRT_S_MM:
3112
89
    case Mips::RECIP_D32_MM:
3113
89
    case Mips::RECIP_D64_MM:
3114
89
    case Mips::RECIP_S_MM:
3115
89
    case Mips::ROUND_W_MM:
3116
89
    case Mips::ROUND_W_S_MM:
3117
89
    case Mips::RSQRT_D32_MM:
3118
89
    case Mips::RSQRT_D64_MM:
3119
89
    case Mips::RSQRT_S_MM:
3120
89
    case Mips::TRUNC_W_MM:
3121
89
    case Mips::TRUNC_W_S_MM: {
3122
89
      // op: fd
3123
89
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3124
89
      Value |= (op & UINT64_C(31)) << 21;
3125
89
      // op: fs
3126
89
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3127
89
      Value |= (op & UINT64_C(31)) << 16;
3128
89
      break;
3129
89
    }
3130
89
    case Mips::MOVF_D32_MM:
3131
9
    case Mips::MOVF_S_MM:
3132
9
    case Mips::MOVT_D32_MM:
3133
9
    case Mips::MOVT_S_MM: {
3134
9
      // op: fd
3135
9
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3136
9
      Value |= (op & UINT64_C(31)) << 21;
3137
9
      // op: fs
3138
9
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3139
9
      Value |= (op & UINT64_C(31)) << 16;
3140
9
      // op: fcc
3141
9
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3142
9
      Value |= (op & UINT64_C(7)) << 13;
3143
9
      break;
3144
9
    }
3145
36
    case Mips::LDXC1:
3146
36
    case Mips::LDXC164:
3147
36
    case Mips::LUXC1:
3148
36
    case Mips::LUXC164:
3149
36
    case Mips::LWXC1: {
3150
36
      // op: fd
3151
36
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3152
36
      Value |= (op & UINT64_C(31)) << 6;
3153
36
      // op: base
3154
36
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3155
36
      Value |= (op & UINT64_C(31)) << 21;
3156
36
      // op: index
3157
36
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3158
36
      Value |= (op & UINT64_C(31)) << 16;
3159
36
      break;
3160
36
    }
3161
60
    case Mips::MADD_D32:
3162
60
    case Mips::MADD_D64:
3163
60
    case Mips::MADD_S:
3164
60
    case Mips::MSUB_D32:
3165
60
    case Mips::MSUB_D64:
3166
60
    case Mips::MSUB_S:
3167
60
    case Mips::NMADD_D32:
3168
60
    case Mips::NMADD_D64:
3169
60
    case Mips::NMADD_S:
3170
60
    case Mips::NMSUB_D32:
3171
60
    case Mips::NMSUB_D64:
3172
60
    case Mips::NMSUB_S: {
3173
60
      // op: fd
3174
60
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3175
60
      Value |= (op & UINT64_C(31)) << 6;
3176
60
      // op: fr
3177
60
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3178
60
      Value |= (op & UINT64_C(31)) << 21;
3179
60
      // op: fs
3180
60
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3181
60
      Value |= (op & UINT64_C(31)) << 11;
3182
60
      // op: ft
3183
60
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
3184
60
      Value |= (op & UINT64_C(31)) << 16;
3185
60
      break;
3186
60
    }
3187
554
    case Mips::CEIL_L_D64:
3188
554
    case Mips::CEIL_L_S:
3189
554
    case Mips::CEIL_W_D32:
3190
554
    case Mips::CEIL_W_D64:
3191
554
    case Mips::CEIL_W_S:
3192
554
    case Mips::CVT_D32_S:
3193
554
    case Mips::CVT_D32_W:
3194
554
    case Mips::CVT_D64_L:
3195
554
    case Mips::CVT_D64_S:
3196
554
    case Mips::CVT_D64_W:
3197
554
    case Mips::CVT_L_D64:
3198
554
    case Mips::CVT_L_S:
3199
554
    case Mips::CVT_S_D32:
3200
554
    case Mips::CVT_S_D64:
3201
554
    case Mips::CVT_S_L:
3202
554
    case Mips::CVT_S_PL64:
3203
554
    case Mips::CVT_S_PU64:
3204
554
    case Mips::CVT_S_W:
3205
554
    case Mips::CVT_W_D32:
3206
554
    case Mips::CVT_W_D64:
3207
554
    case Mips::CVT_W_S:
3208
554
    case Mips::FABS_D32:
3209
554
    case Mips::FABS_D64:
3210
554
    case Mips::FABS_S:
3211
554
    case Mips::FLOOR_L_D64:
3212
554
    case Mips::FLOOR_L_S:
3213
554
    case Mips::FLOOR_W_D32:
3214
554
    case Mips::FLOOR_W_D64:
3215
554
    case Mips::FLOOR_W_S:
3216
554
    case Mips::FMOV_D32:
3217
554
    case Mips::FMOV_D64:
3218
554
    case Mips::FMOV_S:
3219
554
    case Mips::FNEG_D32:
3220
554
    case Mips::FNEG_D64:
3221
554
    case Mips::FNEG_S:
3222
554
    case Mips::FSQRT_D32:
3223
554
    case Mips::FSQRT_D64:
3224
554
    case Mips::FSQRT_S:
3225
554
    case Mips::RECIP_D32:
3226
554
    case Mips::RECIP_D64:
3227
554
    case Mips::RECIP_S:
3228
554
    case Mips::ROUND_L_D64:
3229
554
    case Mips::ROUND_L_S:
3230
554
    case Mips::ROUND_W_D32:
3231
554
    case Mips::ROUND_W_D64:
3232
554
    case Mips::ROUND_W_S:
3233
554
    case Mips::RSQRT_D32:
3234
554
    case Mips::RSQRT_D64:
3235
554
    case Mips::RSQRT_S:
3236
554
    case Mips::TRUNC_L_D64:
3237
554
    case Mips::TRUNC_L_S:
3238
554
    case Mips::TRUNC_W_D32:
3239
554
    case Mips::TRUNC_W_D64:
3240
554
    case Mips::TRUNC_W_S: {
3241
554
      // op: fd
3242
554
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3243
554
      Value |= (op & UINT64_C(31)) << 6;
3244
554
      // op: fs
3245
554
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3246
554
      Value |= (op & UINT64_C(31)) << 11;
3247
554
      break;
3248
554
    }
3249
554
    case Mips::MOVF_D32:
3250
44
    case Mips::MOVF_D64:
3251
44
    case Mips::MOVF_S:
3252
44
    case Mips::MOVT_D32:
3253
44
    case Mips::MOVT_D64:
3254
44
    case Mips::MOVT_S: {
3255
44
      // op: fd
3256
44
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3257
44
      Value |= (op & UINT64_C(31)) << 6;
3258
44
      // op: fs
3259
44
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3260
44
      Value |= (op & UINT64_C(31)) << 11;
3261
44
      // op: fcc
3262
44
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3263
44
      Value |= (op & UINT64_C(7)) << 18;
3264
44
      break;
3265
44
    }
3266
205
    case Mips::CMP_EQ_D:
3267
205
    case Mips::CMP_EQ_S:
3268
205
    case Mips::CMP_F_D:
3269
205
    case Mips::CMP_F_S:
3270
205
    case Mips::CMP_LE_D:
3271
205
    case Mips::CMP_LE_S:
3272
205
    case Mips::CMP_LT_D:
3273
205
    case Mips::CMP_LT_S:
3274
205
    case Mips::CMP_SAF_D:
3275
205
    case Mips::CMP_SAF_S:
3276
205
    case Mips::CMP_SEQ_D:
3277
205
    case Mips::CMP_SEQ_S:
3278
205
    case Mips::CMP_SLE_D:
3279
205
    case Mips::CMP_SLE_S:
3280
205
    case Mips::CMP_SLT_D:
3281
205
    case Mips::CMP_SLT_S:
3282
205
    case Mips::CMP_SUEQ_D:
3283
205
    case Mips::CMP_SUEQ_S:
3284
205
    case Mips::CMP_SULE_D:
3285
205
    case Mips::CMP_SULE_S:
3286
205
    case Mips::CMP_SULT_D:
3287
205
    case Mips::CMP_SULT_S:
3288
205
    case Mips::CMP_SUN_D:
3289
205
    case Mips::CMP_SUN_S:
3290
205
    case Mips::CMP_UEQ_D:
3291
205
    case Mips::CMP_UEQ_S:
3292
205
    case Mips::CMP_ULE_D:
3293
205
    case Mips::CMP_ULE_S:
3294
205
    case Mips::CMP_ULT_D:
3295
205
    case Mips::CMP_ULT_S:
3296
205
    case Mips::CMP_UN_D:
3297
205
    case Mips::CMP_UN_S:
3298
205
    case Mips::CVT_PS_S64:
3299
205
    case Mips::FADD_D32:
3300
205
    case Mips::FADD_D64:
3301
205
    case Mips::FADD_S:
3302
205
    case Mips::FDIV_D32:
3303
205
    case Mips::FDIV_D64:
3304
205
    case Mips::FDIV_S:
3305
205
    case Mips::FMUL_D32:
3306
205
    case Mips::FMUL_D64:
3307
205
    case Mips::FMUL_S:
3308
205
    case Mips::FSUB_D32:
3309
205
    case Mips::FSUB_D64:
3310
205
    case Mips::FSUB_S:
3311
205
    case Mips::PLL_PS64:
3312
205
    case Mips::PLU_PS64: {
3313
205
      // op: fd
3314
205
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3315
205
      Value |= (op & UINT64_C(31)) << 6;
3316
205
      // op: fs
3317
205
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3318
205
      Value |= (op & UINT64_C(31)) << 11;
3319
205
      // op: ft
3320
205
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3321
205
      Value |= (op & UINT64_C(31)) << 16;
3322
205
      break;
3323
205
    }
3324
205
    case Mips::MOVN_I64_D64:
3325
40
    case Mips::MOVN_I64_S:
3326
40
    case Mips::MOVN_I_D32:
3327
40
    case Mips::MOVN_I_D64:
3328
40
    case Mips::MOVN_I_S:
3329
40
    case Mips::MOVZ_I64_D64:
3330
40
    case Mips::MOVZ_I64_S:
3331
40
    case Mips::MOVZ_I_D32:
3332
40
    case Mips::MOVZ_I_D64:
3333
40
    case Mips::MOVZ_I_S: {
3334
40
      // op: fd
3335
40
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3336
40
      Value |= (op & UINT64_C(31)) << 6;
3337
40
      // op: fs
3338
40
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3339
40
      Value |= (op & UINT64_C(31)) << 11;
3340
40
      // op: rt
3341
40
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3342
40
      Value |= (op & UINT64_C(31)) << 16;
3343
40
      break;
3344
40
    }
3345
40
    case Mips::SUXC1_MM:
3346
2
    case Mips::SWXC1_MM: {
3347
2
      // op: fs
3348
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3349
2
      Value |= (op & UINT64_C(31)) << 11;
3350
2
      // op: base
3351
2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3352
2
      Value |= (op & UINT64_C(31)) << 16;
3353
2
      // op: index
3354
2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3355
2
      Value |= (op & UINT64_C(31)) << 21;
3356
2
      break;
3357
2
    }
3358
31
    case Mips::SDXC1:
3359
31
    case Mips::SDXC164:
3360
31
    case Mips::SUXC1:
3361
31
    case Mips::SUXC164:
3362
31
    case Mips::SWXC1: {
3363
31
      // op: fs
3364
31
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3365
31
      Value |= (op & UINT64_C(31)) << 11;
3366
31
      // op: base
3367
31
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3368
31
      Value |= (op & UINT64_C(31)) << 21;
3369
31
      // op: index
3370
31
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3371
31
      Value |= (op & UINT64_C(31)) << 16;
3372
31
      break;
3373
31
    }
3374
31
    case Mips::FCMP_D32:
3375
0
    case Mips::FCMP_D64:
3376
0
    case Mips::FCMP_S32: {
3377
0
      // op: fs
3378
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3379
0
      Value |= (op & UINT64_C(31)) << 11;
3380
0
      // op: ft
3381
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3382
0
      Value |= (op & UINT64_C(31)) << 16;
3383
0
      // op: cond
3384
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3385
0
      Value |= op & UINT64_C(15);
3386
0
      break;
3387
0
    }
3388
2
    case Mips::FCMP_D32_MM:
3389
2
    case Mips::FCMP_S32_MM: {
3390
2
      // op: fs
3391
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3392
2
      Value |= (op & UINT64_C(31)) << 16;
3393
2
      // op: ft
3394
2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3395
2
      Value |= (op & UINT64_C(31)) << 21;
3396
2
      // op: cond
3397
2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3398
2
      Value |= (op & UINT64_C(15)) << 6;
3399
2
      break;
3400
2
    }
3401
8
    case Mips::CLASS_D:
3402
8
    case Mips::CLASS_S:
3403
8
    case Mips::RINT_D:
3404
8
    case Mips::RINT_S: {
3405
8
      // op: fs
3406
8
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3407
8
      Value |= (op & UINT64_C(31)) << 11;
3408
8
      // op: fd
3409
8
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3410
8
      Value |= (op & UINT64_C(31)) << 6;
3411
8
      break;
3412
8
    }
3413
396
    case Mips::C_EQ_D32:
3414
396
    case Mips::C_EQ_D64:
3415
396
    case Mips::C_EQ_S:
3416
396
    case Mips::C_F_D32:
3417
396
    case Mips::C_F_D64:
3418
396
    case Mips::C_F_S:
3419
396
    case Mips::C_LE_D32:
3420
396
    case Mips::C_LE_D64:
3421
396
    case Mips::C_LE_S:
3422
396
    case Mips::C_LT_D32:
3423
396
    case Mips::C_LT_D64:
3424
396
    case Mips::C_LT_S:
3425
396
    case Mips::C_NGE_D32:
3426
396
    case Mips::C_NGE_D64:
3427
396
    case Mips::C_NGE_S:
3428
396
    case Mips::C_NGLE_D32:
3429
396
    case Mips::C_NGLE_D64:
3430
396
    case Mips::C_NGLE_S:
3431
396
    case Mips::C_NGL_D32:
3432
396
    case Mips::C_NGL_D64:
3433
396
    case Mips::C_NGL_S:
3434
396
    case Mips::C_NGT_D32:
3435
396
    case Mips::C_NGT_D64:
3436
396
    case Mips::C_NGT_S:
3437
396
    case Mips::C_OLE_D32:
3438
396
    case Mips::C_OLE_D64:
3439
396
    case Mips::C_OLE_S:
3440
396
    case Mips::C_OLT_D32:
3441
396
    case Mips::C_OLT_D64:
3442
396
    case Mips::C_OLT_S:
3443
396
    case Mips::C_SEQ_D32:
3444
396
    case Mips::C_SEQ_D64:
3445
396
    case Mips::C_SEQ_S:
3446
396
    case Mips::C_SF_D32:
3447
396
    case Mips::C_SF_D64:
3448
396
    case Mips::C_SF_S:
3449
396
    case Mips::C_UEQ_D32:
3450
396
    case Mips::C_UEQ_D64:
3451
396
    case Mips::C_UEQ_S:
3452
396
    case Mips::C_ULE_D32:
3453
396
    case Mips::C_ULE_D64:
3454
396
    case Mips::C_ULE_S:
3455
396
    case Mips::C_ULT_D32:
3456
396
    case Mips::C_ULT_D64:
3457
396
    case Mips::C_ULT_S:
3458
396
    case Mips::C_UN_D32:
3459
396
    case Mips::C_UN_D64:
3460
396
    case Mips::C_UN_S: {
3461
396
      // op: fs
3462
396
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3463
396
      Value |= (op & UINT64_C(31)) << 11;
3464
396
      // op: ft
3465
396
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3466
396
      Value |= (op & UINT64_C(31)) << 16;
3467
396
      // op: fcc
3468
396
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3469
396
      Value |= (op & UINT64_C(7)) << 8;
3470
396
      break;
3471
396
    }
3472
396
    case Mips::C_EQ_D32_MM:
3473
96
    case Mips::C_EQ_D64_MM:
3474
96
    case Mips::C_EQ_S_MM:
3475
96
    case Mips::C_F_D32_MM:
3476
96
    case Mips::C_F_D64_MM:
3477
96
    case Mips::C_F_S_MM:
3478
96
    case Mips::C_LE_D32_MM:
3479
96
    case Mips::C_LE_D64_MM:
3480
96
    case Mips::C_LE_S_MM:
3481
96
    case Mips::C_LT_D32_MM:
3482
96
    case Mips::C_LT_D64_MM:
3483
96
    case Mips::C_LT_S_MM:
3484
96
    case Mips::C_NGE_D32_MM:
3485
96
    case Mips::C_NGE_D64_MM:
3486
96
    case Mips::C_NGE_S_MM:
3487
96
    case Mips::C_NGLE_D32_MM:
3488
96
    case Mips::C_NGLE_D64_MM:
3489
96
    case Mips::C_NGLE_S_MM:
3490
96
    case Mips::C_NGL_D32_MM:
3491
96
    case Mips::C_NGL_D64_MM:
3492
96
    case Mips::C_NGL_S_MM:
3493
96
    case Mips::C_NGT_D32_MM:
3494
96
    case Mips::C_NGT_D64_MM:
3495
96
    case Mips::C_NGT_S_MM:
3496
96
    case Mips::C_OLE_D32_MM:
3497
96
    case Mips::C_OLE_D64_MM:
3498
96
    case Mips::C_OLE_S_MM:
3499
96
    case Mips::C_OLT_D32_MM:
3500
96
    case Mips::C_OLT_D64_MM:
3501
96
    case Mips::C_OLT_S_MM:
3502
96
    case Mips::C_SEQ_D32_MM:
3503
96
    case Mips::C_SEQ_D64_MM:
3504
96
    case Mips::C_SEQ_S_MM:
3505
96
    case Mips::C_SF_D32_MM:
3506
96
    case Mips::C_SF_D64_MM:
3507
96
    case Mips::C_SF_S_MM:
3508
96
    case Mips::C_UEQ_D32_MM:
3509
96
    case Mips::C_UEQ_D64_MM:
3510
96
    case Mips::C_UEQ_S_MM:
3511
96
    case Mips::C_ULE_D32_MM:
3512
96
    case Mips::C_ULE_D64_MM:
3513
96
    case Mips::C_ULE_S_MM:
3514
96
    case Mips::C_ULT_D32_MM:
3515
96
    case Mips::C_ULT_D64_MM:
3516
96
    case Mips::C_ULT_S_MM:
3517
96
    case Mips::C_UN_D32_MM:
3518
96
    case Mips::C_UN_D64_MM:
3519
96
    case Mips::C_UN_S_MM: {
3520
96
      // op: fs
3521
96
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3522
96
      Value |= (op & UINT64_C(31)) << 16;
3523
96
      // op: ft
3524
96
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3525
96
      Value |= (op & UINT64_C(31)) << 21;
3526
96
      // op: fcc
3527
96
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3528
96
      Value |= (op & UINT64_C(7)) << 13;
3529
96
      break;
3530
96
    }
3531
96
    case Mips::CLASS_D_MMR6:
3532
4
    case Mips::CLASS_S_MMR6:
3533
4
    case Mips::RINT_D_MMR6:
3534
4
    case Mips::RINT_S_MMR6: {
3535
4
      // op: fs
3536
4
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3537
4
      Value |= (op & UINT64_C(31)) << 21;
3538
4
      // op: fd
3539
4
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3540
4
      Value |= (op & UINT64_C(31)) << 16;
3541
4
      break;
3542
4
    }
3543
8
    case Mips::BC1EQZ:
3544
8
    case Mips::BC1NEZ: {
3545
8
      // op: ft
3546
8
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3547
8
      Value |= (op & UINT64_C(31)) << 16;
3548
8
      // op: offset
3549
8
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
3550
8
      Value |= op & UINT64_C(65535);
3551
8
      break;
3552
8
    }
3553
16
    case Mips::LDC1_D64_MMR6:
3554
16
    case Mips::SDC1_D64_MMR6: {
3555
16
      // op: ft
3556
16
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3557
16
      Value |= (op & UINT64_C(31)) << 21;
3558
16
      // op: addr
3559
16
      op = getMemEncodingMMImm16(MI, 1, Fixups, STI);
3560
16
      Value |= op & UINT64_C(2097151);
3561
16
      break;
3562
16
    }
3563
22
    case Mips::CEIL_L_D_MMR6:
3564
22
    case Mips::CEIL_L_S_MMR6:
3565
22
    case Mips::CEIL_W_D_MMR6:
3566
22
    case Mips::CEIL_W_S_MMR6:
3567
22
    case Mips::CVT_D_L_MMR6:
3568
22
    case Mips::CVT_L_D_MMR6:
3569
22
    case Mips::CVT_L_S_MMR6:
3570
22
    case Mips::CVT_S_L_MMR6:
3571
22
    case Mips::CVT_S_W_MMR6:
3572
22
    case Mips::CVT_W_S_MMR6:
3573
22
    case Mips::FLOOR_L_D_MMR6:
3574
22
    case Mips::FLOOR_L_S_MMR6:
3575
22
    case Mips::FLOOR_W_D_MMR6:
3576
22
    case Mips::FLOOR_W_S_MMR6:
3577
22
    case Mips::FMOV_S_MMR6:
3578
22
    case Mips::FNEG_S_MMR6:
3579
22
    case Mips::ROUND_L_D_MMR6:
3580
22
    case Mips::ROUND_L_S_MMR6:
3581
22
    case Mips::ROUND_W_D_MMR6:
3582
22
    case Mips::ROUND_W_S_MMR6:
3583
22
    case Mips::TRUNC_L_D_MMR6:
3584
22
    case Mips::TRUNC_L_S_MMR6:
3585
22
    case Mips::TRUNC_W_D_MMR6:
3586
22
    case Mips::TRUNC_W_S_MMR6: {
3587
22
      // op: ft
3588
22
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3589
22
      Value |= (op & UINT64_C(31)) << 21;
3590
22
      // op: fs
3591
22
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3592
22
      Value |= (op & UINT64_C(31)) << 16;
3593
22
      break;
3594
22
    }
3595
22
    case Mips::FADD_S_MMR6:
3596
4
    case Mips::FDIV_S_MMR6:
3597
4
    case Mips::FMUL_S_MMR6:
3598
4
    case Mips::FSUB_S_MMR6: {
3599
4
      // op: ft
3600
4
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3601
4
      Value |= (op & UINT64_C(31)) << 21;
3602
4
      // op: fs
3603
4
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3604
4
      Value |= (op & UINT64_C(31)) << 16;
3605
4
      // op: fd
3606
4
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3607
4
      Value |= (op & UINT64_C(31)) << 11;
3608
4
      break;
3609
4
    }
3610
24
    case Mips::MAXA_D:
3611
24
    case Mips::MAXA_S:
3612
24
    case Mips::MAX_D:
3613
24
    case Mips::MAX_S:
3614
24
    case Mips::MINA_D:
3615
24
    case Mips::MINA_S:
3616
24
    case Mips::MIN_D:
3617
24
    case Mips::MIN_S:
3618
24
    case Mips::SELEQZ_D:
3619
24
    case Mips::SELEQZ_S:
3620
24
    case Mips::SELNEZ_D:
3621
24
    case Mips::SELNEZ_S: {
3622
24
      // op: ft
3623
24
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3624
24
      Value |= (op & UINT64_C(31)) << 16;
3625
24
      // op: fs
3626
24
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3627
24
      Value |= (op & UINT64_C(31)) << 11;
3628
24
      // op: fd
3629
24
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3630
24
      Value |= (op & UINT64_C(31)) << 6;
3631
24
      break;
3632
24
    }
3633
82
    case Mips::CMP_AF_D_MMR6:
3634
82
    case Mips::CMP_AF_S_MMR6:
3635
82
    case Mips::CMP_EQ_D_MMR6:
3636
82
    case Mips::CMP_EQ_S_MMR6:
3637
82
    case Mips::CMP_LE_D_MMR6:
3638
82
    case Mips::CMP_LE_S_MMR6:
3639
82
    case Mips::CMP_LT_D_MMR6:
3640
82
    case Mips::CMP_LT_S_MMR6:
3641
82
    case Mips::CMP_SAF_D_MMR6:
3642
82
    case Mips::CMP_SAF_S_MMR6:
3643
82
    case Mips::CMP_SEQ_D_MMR6:
3644
82
    case Mips::CMP_SEQ_S_MMR6:
3645
82
    case Mips::CMP_SLE_D_MMR6:
3646
82
    case Mips::CMP_SLE_S_MMR6:
3647
82
    case Mips::CMP_SLT_D_MMR6:
3648
82
    case Mips::CMP_SLT_S_MMR6:
3649
82
    case Mips::CMP_SUEQ_D_MMR6:
3650
82
    case Mips::CMP_SUEQ_S_MMR6:
3651
82
    case Mips::CMP_SULE_D_MMR6:
3652
82
    case Mips::CMP_SULE_S_MMR6:
3653
82
    case Mips::CMP_SULT_D_MMR6:
3654
82
    case Mips::CMP_SULT_S_MMR6:
3655
82
    case Mips::CMP_SUN_D_MMR6:
3656
82
    case Mips::CMP_SUN_S_MMR6:
3657
82
    case Mips::CMP_UEQ_D_MMR6:
3658
82
    case Mips::CMP_UEQ_S_MMR6:
3659
82
    case Mips::CMP_ULE_D_MMR6:
3660
82
    case Mips::CMP_ULE_S_MMR6:
3661
82
    case Mips::CMP_ULT_D_MMR6:
3662
82
    case Mips::CMP_ULT_S_MMR6:
3663
82
    case Mips::CMP_UN_D_MMR6:
3664
82
    case Mips::CMP_UN_S_MMR6:
3665
82
    case Mips::FADD_D32_MM:
3666
82
    case Mips::FADD_D64_MM:
3667
82
    case Mips::FADD_S_MM:
3668
82
    case Mips::FDIV_D32_MM:
3669
82
    case Mips::FDIV_D64_MM:
3670
82
    case Mips::FDIV_S_MM:
3671
82
    case Mips::FMUL_D32_MM:
3672
82
    case Mips::FMUL_D64_MM:
3673
82
    case Mips::FMUL_S_MM:
3674
82
    case Mips::FSUB_D32_MM:
3675
82
    case Mips::FSUB_D64_MM:
3676
82
    case Mips::FSUB_S_MM:
3677
82
    case Mips::MAXA_D_MMR6:
3678
82
    case Mips::MAXA_S_MMR6:
3679
82
    case Mips::MAX_D_MMR6:
3680
82
    case Mips::MAX_S_MMR6:
3681
82
    case Mips::MINA_D_MMR6:
3682
82
    case Mips::MINA_S_MMR6:
3683
82
    case Mips::MIN_D_MMR6:
3684
82
    case Mips::MIN_S_MMR6:
3685
82
    case Mips::SELEQZ_D_MMR6:
3686
82
    case Mips::SELEQZ_S_MMR6:
3687
82
    case Mips::SELNEZ_D_MMR6:
3688
82
    case Mips::SELNEZ_S_MMR6: {
3689
82
      // op: ft
3690
82
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3691
82
      Value |= (op & UINT64_C(31)) << 21;
3692
82
      // op: fs
3693
82
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3694
82
      Value |= (op & UINT64_C(31)) << 16;
3695
82
      // op: fd
3696
82
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3697
82
      Value |= (op & UINT64_C(31)) << 11;
3698
82
      break;
3699
82
    }
3700
82
    case Mips::MADDF_D:
3701
12
    case Mips::MADDF_S:
3702
12
    case Mips::MSUBF_D:
3703
12
    case Mips::MSUBF_S:
3704
12
    case Mips::SEL_D:
3705
12
    case Mips::SEL_S: {
3706
12
      // op: ft
3707
12
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
3708
12
      Value |= (op & UINT64_C(31)) << 16;
3709
12
      // op: fs
3710
12
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3711
12
      Value |= (op & UINT64_C(31)) << 11;
3712
12
      // op: fd
3713
12
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3714
12
      Value |= (op & UINT64_C(31)) << 6;
3715
12
      break;
3716
12
    }
3717
12
    case Mips::MADDF_D_MMR6:
3718
7
    case Mips::MADDF_S_MMR6:
3719
7
    case Mips::MSUBF_D_MMR6:
3720
7
    case Mips::MSUBF_S_MMR6:
3721
7
    case Mips::SEL_D_MMR6:
3722
7
    case Mips::SEL_S_MMR6: {
3723
7
      // op: ft
3724
7
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
3725
7
      Value |= (op & UINT64_C(31)) << 21;
3726
7
      // op: fs
3727
7
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3728
7
      Value |= (op & UINT64_C(31)) << 16;
3729
7
      // op: fd
3730
7
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3731
7
      Value |= (op & UINT64_C(31)) << 11;
3732
7
      break;
3733
7
    }
3734
16
    case Mips::MADD_D32_MM:
3735
16
    case Mips::MADD_S_MM:
3736
16
    case Mips::MSUB_D32_MM:
3737
16
    case Mips::MSUB_S_MM:
3738
16
    case Mips::NMADD_D32_MM:
3739
16
    case Mips::NMADD_S_MM:
3740
16
    case Mips::NMSUB_D32_MM:
3741
16
    case Mips::NMSUB_S_MM: {
3742
16
      // op: ft
3743
16
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
3744
16
      Value |= (op & UINT64_C(31)) << 21;
3745
16
      // op: fs
3746
16
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3747
16
      Value |= (op & UINT64_C(31)) << 16;
3748
16
      // op: fd
3749
16
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3750
16
      Value |= (op & UINT64_C(31)) << 11;
3751
16
      // op: fr
3752
16
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3753
16
      Value |= (op & UINT64_C(31)) << 6;
3754
16
      break;
3755
16
    }
3756
44
    case Mips::ADDVI_B:
3757
44
    case Mips::ADDVI_D:
3758
44
    case Mips::ADDVI_H:
3759
44
    case Mips::ADDVI_W:
3760
44
    case Mips::CEQI_B:
3761
44
    case Mips::CEQI_D:
3762
44
    case Mips::CEQI_H:
3763
44
    case Mips::CEQI_W:
3764
44
    case Mips::CLEI_S_B:
3765
44
    case Mips::CLEI_S_D:
3766
44
    case Mips::CLEI_S_H:
3767
44
    case Mips::CLEI_S_W:
3768
44
    case Mips::CLEI_U_B:
3769
44
    case Mips::CLEI_U_D:
3770
44
    case Mips::CLEI_U_H:
3771
44
    case Mips::CLEI_U_W:
3772
44
    case Mips::CLTI_S_B:
3773
44
    case Mips::CLTI_S_D:
3774
44
    case Mips::CLTI_S_H:
3775
44
    case Mips::CLTI_S_W:
3776
44
    case Mips::CLTI_U_B:
3777
44
    case Mips::CLTI_U_D:
3778
44
    case Mips::CLTI_U_H:
3779
44
    case Mips::CLTI_U_W:
3780
44
    case Mips::MAXI_S_B:
3781
44
    case Mips::MAXI_S_D:
3782
44
    case Mips::MAXI_S_H:
3783
44
    case Mips::MAXI_S_W:
3784
44
    case Mips::MAXI_U_B:
3785
44
    case Mips::MAXI_U_D:
3786
44
    case Mips::MAXI_U_H:
3787
44
    case Mips::MAXI_U_W:
3788
44
    case Mips::MINI_S_B:
3789
44
    case Mips::MINI_S_D:
3790
44
    case Mips::MINI_S_H:
3791
44
    case Mips::MINI_S_W:
3792
44
    case Mips::MINI_U_B:
3793
44
    case Mips::MINI_U_D:
3794
44
    case Mips::MINI_U_H:
3795
44
    case Mips::MINI_U_W:
3796
44
    case Mips::SUBVI_B:
3797
44
    case Mips::SUBVI_D:
3798
44
    case Mips::SUBVI_H:
3799
44
    case Mips::SUBVI_W: {
3800
44
      // op: imm
3801
44
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3802
44
      Value |= (op & UINT64_C(31)) << 16;
3803
44
      // op: ws
3804
44
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3805
44
      Value |= (op & UINT64_C(31)) << 11;
3806
44
      // op: wd
3807
44
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3808
44
      Value |= (op & UINT64_C(31)) << 6;
3809
44
      break;
3810
44
    }
3811
44
    case Mips::ADDIUSP_MM: {
3812
24
      // op: imm
3813
24
      op = getSImm9AddiuspValue(MI, 0, Fixups, STI);
3814
24
      Value |= (op & UINT64_C(511)) << 1;
3815
24
      break;
3816
44
    }
3817
44
    case Mips::JRCADDIUSP_MMR6: {
3818
1
      // op: imm
3819
1
      op = getUImm5Lsl2Encoding(MI, 0, Fixups, STI);
3820
1
      Value |= (op & UINT64_C(31)) << 5;
3821
1
      break;
3822
44
    }
3823
44
    case Mips::JRADDIUSP: {
3824
3
      // op: imm
3825
3
      op = getUImm5Lsl2Encoding(MI, 0, Fixups, STI);
3826
3
      Value |= op & UINT64_C(31);
3827
3
      break;
3828
44
    }
3829
44
    case Mips::Bimm16: {
3830
0
      // op: imm11
3831
0
      op = getBranchTargetOpValue(MI, 0, Fixups, STI);
3832
0
      Value |= op & UINT64_C(2047);
3833
0
      break;
3834
44
    }
3835
44
    case Mips::AddiuRxRyOffMemX16: {
3836
0
      // op: imm15
3837
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3838
0
      Value |= (op & UINT64_C(2032)) << 16;
3839
0
      Value |= (op & UINT64_C(30720)) << 5;
3840
0
      Value |= op & UINT64_C(15);
3841
0
      // op: rx
3842
0
      op = getMemEncoding(MI, 1, Fixups, STI);
3843
0
      Value |= (op & UINT64_C(7)) << 8;
3844
0
      // op: ry
3845
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3846
0
      Value |= (op & UINT64_C(7)) << 5;
3847
0
      break;
3848
44
    }
3849
44
    case Mips::BimmX16: {
3850
0
      // op: imm16
3851
0
      op = getBranchTargetOpValue(MI, 0, Fixups, STI);
3852
0
      Value |= (op & UINT64_C(2016)) << 16;
3853
0
      Value |= (op & UINT64_C(63488)) << 5;
3854
0
      Value |= op & UINT64_C(31);
3855
0
      break;
3856
44
    }
3857
44
    case Mips::AddiuSpImmX16:
3858
0
    case Mips::BteqzX16:
3859
0
    case Mips::BtnezX16: {
3860
0
      // op: imm16
3861
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3862
0
      Value |= (op & UINT64_C(2016)) << 16;
3863
0
      Value |= (op & UINT64_C(63488)) << 5;
3864
0
      Value |= op & UINT64_C(31);
3865
0
      break;
3866
0
    }
3867
0
    case Mips::AddiuRxImmX16:
3868
0
    case Mips::AddiuRxPcImmX16:
3869
0
    case Mips::AddiuRxRxImmX16:
3870
0
    case Mips::BeqzRxImmX16:
3871
0
    case Mips::BnezRxImmX16:
3872
0
    case Mips::CmpiRxImmX16:
3873
0
    case Mips::LiRxImmAlignX16:
3874
0
    case Mips::LiRxImmX16:
3875
0
    case Mips::LwRxPcTcpX16:
3876
0
    case Mips::SltiRxImmX16:
3877
0
    case Mips::SltiuRxImmX16: {
3878
0
      // op: imm16
3879
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3880
0
      Value |= (op & UINT64_C(2016)) << 16;
3881
0
      Value |= (op & UINT64_C(63488)) << 5;
3882
0
      Value |= op & UINT64_C(31);
3883
0
      // op: rx
3884
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3885
0
      Value |= (op & UINT64_C(7)) << 8;
3886
0
      break;
3887
0
    }
3888
0
    case Mips::LbRxRyOffMemX16:
3889
0
    case Mips::LbuRxRyOffMemX16:
3890
0
    case Mips::LhRxRyOffMemX16:
3891
0
    case Mips::LhuRxRyOffMemX16:
3892
0
    case Mips::LwRxRyOffMemX16:
3893
0
    case Mips::LwRxSpImmX16:
3894
0
    case Mips::SbRxRyOffMemX16:
3895
0
    case Mips::ShRxRyOffMemX16:
3896
0
    case Mips::SwRxRyOffMemX16:
3897
0
    case Mips::SwRxSpImmX16: {
3898
0
      // op: imm16
3899
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3900
0
      Value |= (op & UINT64_C(2016)) << 16;
3901
0
      Value |= (op & UINT64_C(63488)) << 5;
3902
0
      Value |= op & UINT64_C(31);
3903
0
      // op: rx
3904
0
      op = getMemEncoding(MI, 1, Fixups, STI);
3905
0
      Value |= (op & UINT64_C(7)) << 8;
3906
0
      // op: ry
3907
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3908
0
      Value |= (op & UINT64_C(7)) << 5;
3909
0
      break;
3910
0
    }
3911
0
    case Mips::Jal16:
3912
0
    case Mips::JalB16: {
3913
0
      // op: imm26
3914
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3915
0
      Value |= (op & UINT64_C(2031616)) << 5;
3916
0
      Value |= (op & UINT64_C(65011712)) >> 5;
3917
0
      Value |= op & UINT64_C(65535);
3918
0
      break;
3919
0
    }
3920
0
    case Mips::AddiuSpImm16:
3921
0
    case Mips::Bteqz16:
3922
0
    case Mips::Btnez16: {
3923
0
      // op: imm8
3924
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3925
0
      Value |= op & UINT64_C(255);
3926
0
      break;
3927
0
    }
3928
3
    case Mips::PREFX_MM: {
3929
3
      // op: index
3930
3
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3931
3
      Value |= (op & UINT64_C(31)) << 21;
3932
3
      // op: base
3933
3
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3934
3
      Value |= (op & UINT64_C(31)) << 16;
3935
3
      // op: hint
3936
3
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3937
3
      Value |= (op & UINT64_C(31)) << 11;
3938
3
      break;
3939
0
    }
3940
3
    case Mips::LBUX_MM:
3941
3
    case Mips::LHX_MM:
3942
3
    case Mips::LWX_MM: {
3943
3
      // op: index
3944
3
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3945
3
      Value |= (op & UINT64_C(31)) << 21;
3946
3
      // op: base
3947
3
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3948
3
      Value |= (op & UINT64_C(31)) << 16;
3949
3
      // op: rd
3950
3
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3951
3
      Value |= (op & UINT64_C(31)) << 11;
3952
3
      break;
3953
3
    }
3954
3
    case Mips::COPY_S_D: {
3955
1
      // op: n
3956
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3957
1
      Value |= (op & UINT64_C(1)) << 16;
3958
1
      // op: ws
3959
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3960
1
      Value |= (op & UINT64_C(31)) << 11;
3961
1
      // op: rd
3962
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3963
1
      Value |= (op & UINT64_C(31)) << 6;
3964
1
      break;
3965
3
    }
3966
3
    case Mips::SPLATI_D: {
3967
1
      // op: n
3968
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3969
1
      Value |= (op & UINT64_C(1)) << 16;
3970
1
      // op: ws
3971
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3972
1
      Value |= (op & UINT64_C(31)) << 11;
3973
1
      // op: wd
3974
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3975
1
      Value |= (op & UINT64_C(31)) << 6;
3976
1
      break;
3977
3
    }
3978
3
    case Mips::INSVE_D: {
3979
1
      // op: n
3980
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3981
1
      Value |= (op & UINT64_C(1)) << 16;
3982
1
      // op: ws
3983
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
3984
1
      Value |= (op & UINT64_C(31)) << 11;
3985
1
      // op: wd
3986
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3987
1
      Value |= (op & UINT64_C(31)) << 6;
3988
1
      break;
3989
3
    }
3990
3
    case Mips::COPY_S_B:
3991
2
    case Mips::COPY_U_B: {
3992
2
      // op: n
3993
2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3994
2
      Value |= (op & UINT64_C(15)) << 16;
3995
2
      // op: ws
3996
2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3997
2
      Value |= (op & UINT64_C(31)) << 11;
3998
2
      // op: rd
3999
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4000
2
      Value |= (op & UINT64_C(31)) << 6;
4001
2
      break;
4002
2
    }
4003
2
    case Mips::SPLATI_B: {
4004
1
      // op: n
4005
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4006
1
      Value |= (op & UINT64_C(15)) << 16;
4007
1
      // op: ws
4008
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4009
1
      Value |= (op & UINT64_C(31)) << 11;
4010
1
      // op: wd
4011
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4012
1
      Value |= (op & UINT64_C(31)) << 6;
4013
1
      break;
4014
2
    }
4015
2
    case Mips::INSVE_B: {
4016
1
      // op: n
4017
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4018
1
      Value |= (op & UINT64_C(15)) << 16;
4019
1
      // op: ws
4020
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4021
1
      Value |= (op & UINT64_C(31)) << 11;
4022
1
      // op: wd
4023
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4024
1
      Value |= (op & UINT64_C(31)) << 6;
4025
1
      break;
4026
2
    }
4027
2
    case Mips::COPY_S_W:
4028
1
    case Mips::COPY_U_W: {
4029
1
      // op: n
4030
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4031
1
      Value |= (op & UINT64_C(3)) << 16;
4032
1
      // op: ws
4033
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4034
1
      Value |= (op & UINT64_C(31)) << 11;
4035
1
      // op: rd
4036
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4037
1
      Value |= (op & UINT64_C(31)) << 6;
4038
1
      break;
4039
1
    }
4040
1
    case Mips::SPLATI_W: {
4041
1
      // op: n
4042
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4043
1
      Value |= (op & UINT64_C(3)) << 16;
4044
1
      // op: ws
4045
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4046
1
      Value |= (op & UINT64_C(31)) << 11;
4047
1
      // op: wd
4048
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4049
1
      Value |= (op & UINT64_C(31)) << 6;
4050
1
      break;
4051
1
    }
4052
1
    case Mips::INSVE_W: {
4053
1
      // op: n
4054
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4055
1
      Value |= (op & UINT64_C(3)) << 16;
4056
1
      // op: ws
4057
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4058
1
      Value |= (op & UINT64_C(31)) << 11;
4059
1
      // op: wd
4060
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4061
1
      Value |= (op & UINT64_C(31)) << 6;
4062
1
      break;
4063
1
    }
4064
2
    case Mips::COPY_S_H:
4065
2
    case Mips::COPY_U_H: {
4066
2
      // op: n
4067
2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4068
2
      Value |= (op & UINT64_C(7)) << 16;
4069
2
      // op: ws
4070
2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4071
2
      Value |= (op & UINT64_C(31)) << 11;
4072
2
      // op: rd
4073
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4074
2
      Value |= (op & UINT64_C(31)) << 6;
4075
2
      break;
4076
2
    }
4077
2
    case Mips::SPLATI_H: {
4078
1
      // op: n
4079
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4080
1
      Value |= (op & UINT64_C(7)) << 16;
4081
1
      // op: ws
4082
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4083
1
      Value |= (op & UINT64_C(31)) << 11;
4084
1
      // op: wd
4085
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4086
1
      Value |= (op & UINT64_C(31)) << 6;
4087
1
      break;
4088
2
    }
4089
2
    case Mips::INSVE_H: {
4090
1
      // op: n
4091
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4092
1
      Value |= (op & UINT64_C(7)) << 16;
4093
1
      // op: ws
4094
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4095
1
      Value |= (op & UINT64_C(31)) << 11;
4096
1
      // op: wd
4097
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4098
1
      Value |= (op & UINT64_C(31)) << 6;
4099
1
      break;
4100
2
    }
4101
2
    case Mips::INSERT_D: {
4102
1
      // op: n
4103
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4104
1
      Value |= (op & UINT64_C(1)) << 16;
4105
1
      // op: rs
4106
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4107
1
      Value |= (op & UINT64_C(31)) << 11;
4108
1
      // op: wd
4109
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4110
1
      Value |= (op & UINT64_C(31)) << 6;
4111
1
      break;
4112
2
    }
4113
2
    case Mips::SLDI_D: {
4114
1
      // op: n
4115
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4116
1
      Value |= (op & UINT64_C(1)) << 16;
4117
1
      // op: ws
4118
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4119
1
      Value |= (op & UINT64_C(31)) << 11;
4120
1
      // op: wd
4121
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4122
1
      Value |= (op & UINT64_C(31)) << 6;
4123
1
      break;
4124
2
    }
4125
2
    case Mips::INSERT_B: {
4126
1
      // op: n
4127
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4128
1
      Value |= (op & UINT64_C(15)) << 16;
4129
1
      // op: rs
4130
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4131
1
      Value |= (op & UINT64_C(31)) << 11;
4132
1
      // op: wd
4133
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4134
1
      Value |= (op & UINT64_C(31)) << 6;
4135
1
      break;
4136
2
    }
4137
2
    case Mips::SLDI_B: {
4138
1
      // op: n
4139
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4140
1
      Value |= (op & UINT64_C(15)) << 16;
4141
1
      // op: ws
4142
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4143
1
      Value |= (op & UINT64_C(31)) << 11;
4144
1
      // op: wd
4145
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4146
1
      Value |= (op & UINT64_C(31)) << 6;
4147
1
      break;
4148
2
    }
4149
2
    case Mips::INSERT_W: {
4150
1
      // op: n
4151
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4152
1
      Value |= (op & UINT64_C(3)) << 16;
4153
1
      // op: rs
4154
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4155
1
      Value |= (op & UINT64_C(31)) << 11;
4156
1
      // op: wd
4157
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4158
1
      Value |= (op & UINT64_C(31)) << 6;
4159
1
      break;
4160
2
    }
4161
2
    case Mips::SLDI_W: {
4162
1
      // op: n
4163
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4164
1
      Value |= (op & UINT64_C(3)) << 16;
4165
1
      // op: ws
4166
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4167
1
      Value |= (op & UINT64_C(31)) << 11;
4168
1
      // op: wd
4169
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4170
1
      Value |= (op & UINT64_C(31)) << 6;
4171
1
      break;
4172
2
    }
4173
2
    case Mips::INSERT_H: {
4174
1
      // op: n
4175
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4176
1
      Value |= (op & UINT64_C(7)) << 16;
4177
1
      // op: rs
4178
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4179
1
      Value |= (op & UINT64_C(31)) << 11;
4180
1
      // op: wd
4181
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4182
1
      Value |= (op & UINT64_C(31)) << 6;
4183
1
      break;
4184
2
    }
4185
2
    case Mips::SLDI_H: {
4186
1
      // op: n
4187
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4188
1
      Value |= (op & UINT64_C(7)) << 16;
4189
1
      // op: ws
4190
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4191
1
      Value |= (op & UINT64_C(31)) << 11;
4192
1
      // op: wd
4193
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4194
1
      Value |= (op & UINT64_C(31)) << 6;
4195
1
      break;
4196
2
    }
4197
27
    case Mips::BALC:
4198
27
    case Mips::BC: {
4199
27
      // op: offset
4200
27
      op = getBranchTarget26OpValue(MI, 0, Fixups, STI);
4201
27
      Value |= op & UINT64_C(67108863);
4202
27
      break;
4203
27
    }
4204
27
    case Mips::BALC_MMR6:
4205
13
    case Mips::BC_MMR6: {
4206
13
      // op: offset
4207
13
      op = getBranchTarget26OpValueMM(MI, 0, Fixups, STI);
4208
13
      Value |= op & UINT64_C(67108863);
4209
13
      break;
4210
13
    }
4211
13
    case Mips::BAL:
4212
4
    case Mips::BPOSGE32: {
4213
4
      // op: offset
4214
4
      op = getBranchTargetOpValue(MI, 0, Fixups, STI);
4215
4
      Value |= op & UINT64_C(65535);
4216
4
      break;
4217
4
    }
4218
20
    case Mips::BNZ_B:
4219
20
    case Mips::BNZ_D:
4220
20
    case Mips::BNZ_H:
4221
20
    case Mips::BNZ_V:
4222
20
    case Mips::BNZ_W:
4223
20
    case Mips::BZ_B:
4224
20
    case Mips::BZ_D:
4225
20
    case Mips::BZ_H:
4226
20
    case Mips::BZ_V:
4227
20
    case Mips::BZ_W: {
4228
20
      // op: offset
4229
20
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
4230
20
      Value |= op & UINT64_C(65535);
4231
20
      // op: wt
4232
20
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4233
20
      Value |= (op & UINT64_C(31)) << 16;
4234
20
      break;
4235
20
    }
4236
20
    case Mips::BPOSGE32C_MMR3: {
4237
1
      // op: offset
4238
1
      op = getBranchTargetOpValue1SImm16(MI, 0, Fixups, STI);
4239
1
      Value |= op & UINT64_C(65535);
4240
1
      break;
4241
20
    }
4242
20
    case Mips::BPOSGE32_MM: {
4243
1
      // op: offset
4244
1
      op = getBranchTargetOpValueMM(MI, 0, Fixups, STI);
4245
1
      Value |= op & UINT64_C(65535);
4246
1
      break;
4247
20
    }
4248
20
    case Mips::B16_MM:
4249
12
    case Mips::BC16_MMR6: {
4250
12
      // op: offset
4251
12
      op = getBranchTargetOpValueMMPC10(MI, 0, Fixups, STI);
4252
12
      Value |= op & UINT64_C(1023);
4253
12
      break;
4254
12
    }
4255
12
    case Mips::Move32R16: {
4256
2
      // op: r32
4257
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4258
2
      Value |= (op & UINT64_C(7)) << 5;
4259
2
      Value |= op & UINT64_C(24);
4260
2
      // op: rz
4261
2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4262
2
      Value |= op & UINT64_C(7);
4263
2
      break;
4264
12
    }
4265
467
    case Mips::MFHI:
4266
467
    case Mips::MFHI64:
4267
467
    case Mips::MFLO:
4268
467
    case Mips::MFLO64: {
4269
467
      // op: rd
4270
467
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4271
467
      Value |= (op & UINT64_C(31)) << 11;
4272
467
      break;
4273
467
    }
4274
467
    case Mips::MFHI_DSP:
4275
4
    case Mips::MFLO_DSP: {
4276
4
      // op: rd
4277
4
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4278
4
      Value |= (op & UINT64_C(31)) << 11;
4279
4
      // op: ac
4280
4
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4281
4
      Value |= (op & UINT64_C(3)) << 21;
4282
4
      break;
4283
4
    }
4284
4
    case Mips::LWXS_MM: {
4285
3
      // op: rd
4286
3
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4287
3
      Value |= (op & UINT64_C(31)) << 11;
4288
3
      // op: base
4289
3
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4290
3
      Value |= (op & UINT64_C(31)) << 16;
4291
3
      // op: index
4292
3
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4293
3
      Value |= (op & UINT64_C(31)) << 21;
4294
3
      break;
4295
4
    }
4296
8
    case Mips::LBUX:
4297
8
    case Mips::LHX:
4298
8
    case Mips::LWX: {
4299
8
      // op: rd
4300
8
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4301
8
      Value |= (op & UINT64_C(31)) << 11;
4302
8
      // op: base
4303
8
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4304
8
      Value |= (op & UINT64_C(31)) << 21;
4305
8
      // op: index
4306
8
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4307
8
      Value |= (op & UINT64_C(31)) << 16;
4308
8
      break;
4309
8
    }
4310
8
    case Mips::REPL_PH:
4311
5
    case Mips::REPL_PH_MM:
4312
5
    case Mips::REPL_QB: {
4313
5
      // op: rd
4314
5
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4315
5
      Value |= (op & UINT64_C(31)) << 11;
4316
5
      // op: imm
4317
5
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4318
5
      Value |= (op & UINT64_C(1023)) << 16;
4319
5
      break;
4320
5
    }
4321
5
    case Mips::RDDSP: {
4322
2
      // op: rd
4323
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4324
2
      Value |= (op & UINT64_C(31)) << 11;
4325
2
      // op: mask
4326
2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4327
2
      Value |= (op & UINT64_C(1023)) << 16;
4328
2
      break;
4329
5
    }
4330
78
    case Mips::ADDQH_PH_MMR2:
4331
78
    case Mips::ADDQH_R_PH_MMR2:
4332
78
    case Mips::ADDQH_R_W_MMR2:
4333
78
    case Mips::ADDQH_W_MMR2:
4334
78
    case Mips::ADDQ_PH_MM:
4335
78
    case Mips::ADDQ_S_PH_MM:
4336
78
    case Mips::ADDQ_S_W_MM:
4337
78
    case Mips::ADDSC_MM:
4338
78
    case Mips::ADDUH_QB_MMR2:
4339
78
    case Mips::ADDUH_R_QB_MMR2:
4340
78
    case Mips::ADDU_PH_MMR2:
4341
78
    case Mips::ADDU_QB_MM:
4342
78
    case Mips::ADDU_S_PH_MMR2:
4343
78
    case Mips::ADDU_S_QB_MM:
4344
78
    case Mips::ADDWC_MM:
4345
78
    case Mips::CMPGDU_EQ_QB_MMR2:
4346
78
    case Mips::CMPGDU_LE_QB_MMR2:
4347
78
    case Mips::CMPGDU_LT_QB_MMR2:
4348
78
    case Mips::MODSUB_MM:
4349
78
    case Mips::MULEQ_S_W_PHL_MM:
4350
78
    case Mips::MULEQ_S_W_PHR_MM:
4351
78
    case Mips::MULEU_S_PH_QBL_MM:
4352
78
    case Mips::MULEU_S_PH_QBR_MM:
4353
78
    case Mips::MULQ_RS_PH_MM:
4354
78
    case Mips::MULQ_RS_W_MMR2:
4355
78
    case Mips::MULQ_S_PH_MMR2:
4356
78
    case Mips::MULQ_S_W_MMR2:
4357
78
    case Mips::MUL_PH_MMR2:
4358
78
    case Mips::MUL_S_PH_MMR2:
4359
78
    case Mips::PACKRL_PH_MM:
4360
78
    case Mips::PICK_PH_MM:
4361
78
    case Mips::PICK_QB_MM:
4362
78
    case Mips::PRECRQU_S_QB_PH_MM:
4363
78
    case Mips::PRECRQ_PH_W_MM:
4364
78
    case Mips::PRECRQ_QB_PH_MM:
4365
78
    case Mips::PRECRQ_RS_PH_W_MM:
4366
78
    case Mips::PRECR_QB_PH_MMR2:
4367
78
    case Mips::SELEQZ_MMR6:
4368
78
    case Mips::SELNEZ_MMR6:
4369
78
    case Mips::SUBQH_PH_MMR2:
4370
78
    case Mips::SUBQH_R_PH_MMR2:
4371
78
    case Mips::SUBQH_R_W_MMR2:
4372
78
    case Mips::SUBQH_W_MMR2:
4373
78
    case Mips::SUBQ_PH_MM:
4374
78
    case Mips::SUBQ_S_PH_MM:
4375
78
    case Mips::SUBQ_S_W_MM:
4376
78
    case Mips::SUBUH_QB_MMR2:
4377
78
    case Mips::SUBUH_R_QB_MMR2:
4378
78
    case Mips::SUBU_PH_MMR2:
4379
78
    case Mips::SUBU_QB_MM:
4380
78
    case Mips::SUBU_S_PH_MMR2:
4381
78
    case Mips::SUBU_S_QB_MM: {
4382
78
      // op: rd
4383
78
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4384
78
      Value |= (op & UINT64_C(31)) << 11;
4385
78
      // op: rs
4386
78
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4387
78
      Value |= (op & UINT64_C(31)) << 16;
4388
78
      // op: rt
4389
78
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4390
78
      Value |= (op & UINT64_C(31)) << 21;
4391
78
      break;
4392
78
    }
4393
78
    case Mips::LSA_MMR6: {
4394
1
      // op: rd
4395
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4396
1
      Value |= (op & UINT64_C(31)) << 11;
4397
1
      // op: rs
4398
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4399
1
      Value |= (op & UINT64_C(31)) << 16;
4400
1
      // op: rt
4401
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4402
1
      Value |= (op & UINT64_C(31)) << 21;
4403
1
      // op: imm2
4404
1
      op = getUImmWithOffsetEncoding<2, 1>(MI, 3, Fixups, STI);
4405
1
      Value |= (op & UINT64_C(3)) << 9;
4406
1
      break;
4407
78
    }
4408
150
    case Mips::CLO_R6:
4409
150
    case Mips::CLZ_R6:
4410
150
    case Mips::DCLO_R6:
4411
150
    case Mips::DCLZ_R6:
4412
150
    case Mips::DPOP:
4413
150
    case Mips::JALR:
4414
150
    case Mips::JALR64:
4415
150
    case Mips::JALR_HB:
4416
150
    case Mips::JALR_HB64:
4417
150
    case Mips::POP:
4418
150
    case Mips::RADDU_W_QB: {
4419
150
      // op: rd
4420
150
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4421
150
      Value |= (op & UINT64_C(31)) << 11;
4422
150
      // op: rs
4423
150
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4424
150
      Value |= (op & UINT64_C(31)) << 21;
4425
150
      break;
4426
150
    }
4427
150
    case Mips::MOVF_I:
4428
26
    case Mips::MOVF_I64:
4429
26
    case Mips::MOVT_I:
4430
26
    case Mips::MOVT_I64: {
4431
26
      // op: rd
4432
26
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4433
26
      Value |= (op & UINT64_C(31)) << 11;
4434
26
      // op: rs
4435
26
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4436
26
      Value |= (op & UINT64_C(31)) << 21;
4437
26
      // op: fcc
4438
26
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4439
26
      Value |= (op & UINT64_C(7)) << 18;
4440
26
      break;
4441
26
    }
4442
1.96k
    case Mips::ADD:
4443
1.96k
    case Mips::ADDQH_PH:
4444
1.96k
    case Mips::ADDQH_R_PH:
4445
1.96k
    case Mips::ADDQH_R_W:
4446
1.96k
    case Mips::ADDQH_W:
4447
1.96k
    case Mips::ADDQ_PH:
4448
1.96k
    case Mips::ADDQ_S_PH:
4449
1.96k
    case Mips::ADDQ_S_W:
4450
1.96k
    case Mips::ADDSC:
4451
1.96k
    case Mips::ADDUH_QB:
4452
1.96k
    case Mips::ADDUH_R_QB:
4453
1.96k
    case Mips::ADDU_PH:
4454
1.96k
    case Mips::ADDU_QB:
4455
1.96k
    case Mips::ADDU_S_PH:
4456
1.96k
    case Mips::ADDU_S_QB:
4457
1.96k
    case Mips::ADDWC:
4458
1.96k
    case Mips::ADDu:
4459
1.96k
    case Mips::AND:
4460
1.96k
    case Mips::AND64:
4461
1.96k
    case Mips::BADDu:
4462
1.96k
    case Mips::DADD:
4463
1.96k
    case Mips::DADDu:
4464
1.96k
    case Mips::DDIV:
4465
1.96k
    case Mips::DDIVU:
4466
1.96k
    case Mips::DIV:
4467
1.96k
    case Mips::DIVU:
4468
1.96k
    case Mips::DMOD:
4469
1.96k
    case Mips::DMODU:
4470
1.96k
    case Mips::DMUH:
4471
1.96k
    case Mips::DMUHU:
4472
1.96k
    case Mips::DMUL:
4473
1.96k
    case Mips::DMULU:
4474
1.96k
    case Mips::DMUL_R6:
4475
1.96k
    case Mips::DSUB:
4476
1.96k
    case Mips::DSUBu:
4477
1.96k
    case Mips::MOD:
4478
1.96k
    case Mips::MODSUB:
4479
1.96k
    case Mips::MODU:
4480
1.96k
    case Mips::MOVN_I64_I:
4481
1.96k
    case Mips::MOVN_I64_I64:
4482
1.96k
    case Mips::MOVN_I_I:
4483
1.96k
    case Mips::MOVN_I_I64:
4484
1.96k
    case Mips::MOVZ_I64_I:
4485
1.96k
    case Mips::MOVZ_I64_I64:
4486
1.96k
    case Mips::MOVZ_I_I:
4487
1.96k
    case Mips::MOVZ_I_I64:
4488
1.96k
    case Mips::MUH:
4489
1.96k
    case Mips::MUHU:
4490
1.96k
    case Mips::MUL:
4491
1.96k
    case Mips::MULEQ_S_W_PHL:
4492
1.96k
    case Mips::MULEQ_S_W_PHR:
4493
1.96k
    case Mips::MULEU_S_PH_QBL:
4494
1.96k
    case Mips::MULEU_S_PH_QBR:
4495
1.96k
    case Mips::MULQ_RS_PH:
4496
1.96k
    case Mips::MULQ_RS_W:
4497
1.96k
    case Mips::MULQ_S_PH:
4498
1.96k
    case Mips::MULQ_S_W:
4499
1.96k
    case Mips::MULU:
4500
1.96k
    case Mips::MUL_PH:
4501
1.96k
    case Mips::MUL_R6:
4502
1.96k
    case Mips::MUL_S_PH:
4503
1.96k
    case Mips::NOR:
4504
1.96k
    case Mips::NOR64:
4505
1.96k
    case Mips::OR:
4506
1.96k
    case Mips::OR64:
4507
1.96k
    case Mips::SELEQZ:
4508
1.96k
    case Mips::SELEQZ64:
4509
1.96k
    case Mips::SELNEZ:
4510
1.96k
    case Mips::SELNEZ64:
4511
1.96k
    case Mips::SEQ:
4512
1.96k
    case Mips::SLT:
4513
1.96k
    case Mips::SLT64:
4514
1.96k
    case Mips::SLTu:
4515
1.96k
    case Mips::SLTu64:
4516
1.96k
    case Mips::SNE:
4517
1.96k
    case Mips::SUB:
4518
1.96k
    case Mips::SUBQH_PH:
4519
1.96k
    case Mips::SUBQH_R_PH:
4520
1.96k
    case Mips::SUBQH_R_W:
4521
1.96k
    case Mips::SUBQH_W:
4522
1.96k
    case Mips::SUBQ_PH:
4523
1.96k
    case Mips::SUBQ_S_PH:
4524
1.96k
    case Mips::SUBQ_S_W:
4525
1.96k
    case Mips::SUBUH_QB:
4526
1.96k
    case Mips::SUBUH_R_QB:
4527
1.96k
    case Mips::SUBU_PH:
4528
1.96k
    case Mips::SUBU_QB:
4529
1.96k
    case Mips::SUBU_S_PH:
4530
1.96k
    case Mips::SUBU_S_QB:
4531
1.96k
    case Mips::SUBu:
4532
1.96k
    case Mips::V3MULU:
4533
1.96k
    case Mips::VMM0:
4534
1.96k
    case Mips::VMULU:
4535
1.96k
    case Mips::XOR:
4536
1.96k
    case Mips::XOR64: {
4537
1.96k
      // op: rd
4538
1.96k
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4539
1.96k
      Value |= (op & UINT64_C(31)) << 11;
4540
1.96k
      // op: rs
4541
1.96k
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4542
1.96k
      Value |= (op & UINT64_C(31)) << 21;
4543
1.96k
      // op: rt
4544
1.96k
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4545
1.96k
      Value |= (op & UINT64_C(31)) << 16;
4546
1.96k
      break;
4547
1.96k
    }
4548
1.96k
    case Mips::ALIGN: {
4549
3
      // op: rd
4550
3
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4551
3
      Value |= (op & UINT64_C(31)) << 11;
4552
3
      // op: rs
4553
3
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4554
3
      Value |= (op & UINT64_C(31)) << 21;
4555
3
      // op: rt
4556
3
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4557
3
      Value |= (op & UINT64_C(31)) << 16;
4558
3
      // op: bp
4559
3
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4560
3
      Value |= (op & UINT64_C(3)) << 6;
4561
3
      break;
4562
1.96k
    }
4563
1.96k
    case Mips::ALIGN_MMR6: {
4564
1
      // op: rd
4565
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4566
1
      Value |= (op & UINT64_C(31)) << 11;
4567
1
      // op: rs
4568
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4569
1
      Value |= (op & UINT64_C(31)) << 21;
4570
1
      // op: rt
4571
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4572
1
      Value |= (op & UINT64_C(31)) << 16;
4573
1
      // op: bp
4574
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4575
1
      Value |= (op & UINT64_C(3)) << 9;
4576
1
      break;
4577
1.96k
    }
4578
1.96k
    case Mips::DALIGN: {
4579
1
      // op: rd
4580
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4581
1
      Value |= (op & UINT64_C(31)) << 11;
4582
1
      // op: rs
4583
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4584
1
      Value |= (op & UINT64_C(31)) << 21;
4585
1
      // op: rt
4586
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4587
1
      Value |= (op & UINT64_C(31)) << 16;
4588
1
      // op: bp
4589
1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4590
1
      Value |= (op & UINT64_C(7)) << 6;
4591
1
      break;
4592
1.96k
    }
4593
1.96k
    case Mips::DLSA_R6:
4594
3
    case Mips::LSA_R6: {
4595
3
      // op: rd
4596
3
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4597
3
      Value |= (op & UINT64_C(31)) << 11;
4598
3
      // op: rs
4599
3
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4600
3
      Value |= (op & UINT64_C(31)) << 21;
4601
3
      // op: rt
4602
3
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4603
3
      Value |= (op & UINT64_C(31)) << 16;
4604
3
      // op: imm2
4605
3
      op = getUImmWithOffsetEncoding<2, 1>(MI, 3, Fixups, STI);
4606
3
      Value |= (op & UINT64_C(3)) << 6;
4607
3
      break;
4608
3
    }
4609
19
    case Mips::SHLLV_PH_MM:
4610
19
    case Mips::SHLLV_QB_MM:
4611
19
    case Mips::SHLLV_S_PH_MM:
4612
19
    case Mips::SHLLV_S_W_MM:
4613
19
    case Mips::SHRAV_PH_MM:
4614
19
    case Mips::SHRAV_QB_MMR2:
4615
19
    case Mips::SHRAV_R_PH_MM:
4616
19
    case Mips::SHRAV_R_QB_MMR2:
4617
19
    case Mips::SHRAV_R_W_MM:
4618
19
    case Mips::SHRLV_PH_MMR2:
4619
19
    case Mips::SHRLV_QB_MM: {
4620
19
      // op: rd
4621
19
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4622
19
      Value |= (op & UINT64_C(31)) << 11;
4623
19
      // op: rs
4624
19
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4625
19
      Value |= (op & UINT64_C(31)) << 16;
4626
19
      // op: rt
4627
19
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4628
19
      Value |= (op & UINT64_C(31)) << 21;
4629
19
      break;
4630
19
    }
4631
82
    case Mips::ABSQ_S_PH:
4632
82
    case Mips::ABSQ_S_QB:
4633
82
    case Mips::ABSQ_S_W:
4634
82
    case Mips::BITREV:
4635
82
    case Mips::BITSWAP:
4636
82
    case Mips::DBITSWAP:
4637
82
    case Mips::DSBH:
4638
82
    case Mips::DSHD:
4639
82
    case Mips::DSLL64_32:
4640
82
    case Mips::PRECEQU_PH_QBL:
4641
82
    case Mips::PRECEQU_PH_QBLA:
4642
82
    case Mips::PRECEQU_PH_QBR:
4643
82
    case Mips::PRECEQU_PH_QBRA:
4644
82
    case Mips::PRECEQ_W_PHL:
4645
82
    case Mips::PRECEQ_W_PHR:
4646
82
    case Mips::PRECEU_PH_QBL:
4647
82
    case Mips::PRECEU_PH_QBLA:
4648
82
    case Mips::PRECEU_PH_QBR:
4649
82
    case Mips::PRECEU_PH_QBRA:
4650
82
    case Mips::REPLV_PH:
4651
82
    case Mips::REPLV_QB:
4652
82
    case Mips::SEB:
4653
82
    case Mips::SEB64:
4654
82
    case Mips::SEH:
4655
82
    case Mips::SEH64:
4656
82
    case Mips::SLL64_32:
4657
82
    case Mips::SLL64_64:
4658
82
    case Mips::WSBH: {
4659
82
      // op: rd
4660
82
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4661
82
      Value |= (op & UINT64_C(31)) << 11;
4662
82
      // op: rt
4663
82
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4664
82
      Value |= (op & UINT64_C(31)) << 16;
4665
82
      break;
4666
82
    }
4667
306
    case Mips::DROTRV:
4668
306
    case Mips::DSLLV:
4669
306
    case Mips::DSRAV:
4670
306
    case Mips::DSRLV:
4671
306
    case Mips::ROTRV:
4672
306
    case Mips::SLLV:
4673
306
    case Mips::SRAV:
4674
306
    case Mips::SRLV: {
4675
306
      // op: rd
4676
306
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4677
306
      Value |= (op & UINT64_C(31)) << 11;
4678
306
      // op: rt
4679
306
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4680
306
      Value |= (op & UINT64_C(31)) << 16;
4681
306
      // op: rs
4682
306
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4683
306
      Value |= (op & UINT64_C(31)) << 21;
4684
306
      break;
4685
306
    }
4686
306
    case Mips::SHLLV_PH:
4687
38
    case Mips::SHLLV_QB:
4688
38
    case Mips::SHLLV_S_PH:
4689
38
    case Mips::SHLLV_S_W:
4690
38
    case Mips::SHLL_PH:
4691
38
    case Mips::SHLL_QB:
4692
38
    case Mips::SHLL_S_PH:
4693
38
    case Mips::SHLL_S_W:
4694
38
    case Mips::SHRAV_PH:
4695
38
    case Mips::SHRAV_QB:
4696
38
    case Mips::SHRAV_R_PH:
4697
38
    case Mips::SHRAV_R_QB:
4698
38
    case Mips::SHRAV_R_W:
4699
38
    case Mips::SHRA_PH:
4700
38
    case Mips::SHRA_QB:
4701
38
    case Mips::SHRA_R_PH:
4702
38
    case Mips::SHRA_R_QB:
4703
38
    case Mips::SHRA_R_W:
4704
38
    case Mips::SHRLV_PH:
4705
38
    case Mips::SHRLV_QB:
4706
38
    case Mips::SHRL_PH:
4707
38
    case Mips::SHRL_QB: {
4708
38
      // op: rd
4709
38
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4710
38
      Value |= (op & UINT64_C(31)) << 11;
4711
38
      // op: rt
4712
38
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4713
38
      Value |= (op & UINT64_C(31)) << 16;
4714
38
      // op: rs_sa
4715
38
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4716
38
      Value |= (op & UINT64_C(31)) << 21;
4717
38
      break;
4718
38
    }
4719
13.5k
    case Mips::DROTR:
4720
13.5k
    case Mips::DROTR32:
4721
13.5k
    case Mips::DSLL:
4722
13.5k
    case Mips::DSLL32:
4723
13.5k
    case Mips::DSRA:
4724
13.5k
    case Mips::DSRA32:
4725
13.5k
    case Mips::DSRL:
4726
13.5k
    case Mips::DSRL32:
4727
13.5k
    case Mips::ROTR:
4728
13.5k
    case Mips::SLL:
4729
13.5k
    case Mips::SRA:
4730
13.5k
    case Mips::SRL: {
4731
13.5k
      // op: rd
4732
13.5k
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4733
13.5k
      Value |= (op & UINT64_C(31)) << 11;
4734
13.5k
      // op: rt
4735
13.5k
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4736
13.5k
      Value |= (op & UINT64_C(31)) << 16;
4737
13.5k
      // op: shamt
4738
13.5k
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4739
13.5k
      Value |= (op & UINT64_C(31)) << 6;
4740
13.5k
      break;
4741
13.5k
    }
4742
13.5k
    case Mips::ROTRV_MM:
4743
44
    case Mips::SLLV_MM:
4744
44
    case Mips::SRAV_MM:
4745
44
    case Mips::SRLV_MM: {
4746
44
      // op: rd
4747
44
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4748
44
      Value |= (op & UINT64_C(31)) << 11;
4749
44
      // op: rt
4750
44
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4751
44
      Value |= (op & UINT64_C(31)) << 21;
4752
44
      // op: rs
4753
44
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4754
44
      Value |= (op & UINT64_C(31)) << 16;
4755
44
      break;
4756
44
    }
4757
44
    case Mips::ADDU_MMR6:
4758
22
    case Mips::ADD_MMR6:
4759
22
    case Mips::AND_MMR6:
4760
22
    case Mips::DIVU_MMR6:
4761
22
    case Mips::DIV_MMR6:
4762
22
    case Mips::MODU_MMR6:
4763
22
    case Mips::MOD_MMR6:
4764
22
    case Mips::MUHU_MMR6:
4765
22
    case Mips::MUH_MMR6:
4766
22
    case Mips::MULU_MMR6:
4767
22
    case Mips::MUL_MMR6:
4768
22
    case Mips::NOR_MMR6:
4769
22
    case Mips::OR_MMR6:
4770
22
    case Mips::SUBU_MMR6:
4771
22
    case Mips::SUB_MMR6:
4772
22
    case Mips::XOR_MMR6: {
4773
22
      // op: rd
4774
22
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4775
22
      Value |= (op & UINT64_C(31)) << 11;
4776
22
      // op: rt
4777
22
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4778
22
      Value |= (op & UINT64_C(31)) << 21;
4779
22
      // op: rs
4780
22
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4781
22
      Value |= (op & UINT64_C(31)) << 16;
4782
22
      break;
4783
22
    }
4784
22
    case Mips::MFHI_MM:
4785
2
    case Mips::MFLO_MM: {
4786
2
      // op: rd
4787
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4788
2
      Value |= (op & UINT64_C(31)) << 16;
4789
2
      break;
4790
2
    }
4791
2
    case Mips::BITSWAP_MMR6: {
4792
1
      // op: rd
4793
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4794
1
      Value |= (op & UINT64_C(31)) << 16;
4795
1
      // op: rt
4796
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4797
1
      Value |= (op & UINT64_C(31)) << 21;
4798
1
      break;
4799
2
    }
4800
29
    case Mips::CLO:
4801
29
    case Mips::CLZ:
4802
29
    case Mips::DCLO:
4803
29
    case Mips::DCLZ: {
4804
29
      // op: rd
4805
29
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4806
29
      Value |= (op & UINT64_C(31)) << 16;
4807
29
      Value |= (op & UINT64_C(31)) << 11;
4808
29
      // op: rs
4809
29
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4810
29
      Value |= (op & UINT64_C(31)) << 21;
4811
29
      break;
4812
29
    }
4813
29
    case Mips::CLO_MM:
4814
2
    case Mips::CLZ_MM: {
4815
2
      // op: rd
4816
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4817
2
      Value |= (op & UINT64_C(31)) << 21;
4818
2
      // op: rs
4819
2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4820
2
      Value |= (op & UINT64_C(31)) << 16;
4821
2
      break;
4822
2
    }
4823
6
    case Mips::MOVF_I_MM:
4824
6
    case Mips::MOVT_I_MM: {
4825
6
      // op: rd
4826
6
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4827
6
      Value |= (op & UINT64_C(31)) << 21;
4828
6
      // op: rs
4829
6
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4830
6
      Value |= (op & UINT64_C(31)) << 16;
4831
6
      // op: fcc
4832
6
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4833
6
      Value |= (op & UINT64_C(7)) << 13;
4834
6
      break;
4835
6
    }
4836
9
    case Mips::SEB_MM:
4837
9
    case Mips::SEH_MM:
4838
9
    case Mips::WSBH_MM: {
4839
9
      // op: rd
4840
9
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4841
9
      Value |= (op & UINT64_C(31)) << 21;
4842
9
      // op: rt
4843
9
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4844
9
      Value |= (op & UINT64_C(31)) << 16;
4845
9
      break;
4846
9
    }
4847
221
    case Mips::ROTR_MM:
4848
221
    case Mips::SLL_MM:
4849
221
    case Mips::SLL_MMR6:
4850
221
    case Mips::SRA_MM:
4851
221
    case Mips::SRL_MM: {
4852
221
      // op: rd
4853
221
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4854
221
      Value |= (op & UINT64_C(31)) << 21;
4855
221
      // op: rt
4856
221
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4857
221
      Value |= (op & UINT64_C(31)) << 16;
4858
221
      // op: shamt
4859
221
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4860
221
      Value |= (op & UINT64_C(31)) << 11;
4861
221
      break;
4862
221
    }
4863
221
    case Mips::CFCMSA: {
4864
16
      // op: rd
4865
16
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4866
16
      Value |= (op & UINT64_C(31)) << 6;
4867
16
      // op: cs
4868
16
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4869
16
      Value |= (op & UINT64_C(31)) << 11;
4870
16
      break;
4871
221
    }
4872
221
    case Mips::LI16_MM:
4873
17
    case Mips::LI16_MMR6: {
4874
17
      // op: rd
4875
17
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4876
17
      Value |= (op & UINT64_C(7)) << 7;
4877
17
      // op: imm
4878
17
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4879
17
      Value |= op & UINT64_C(127);
4880
17
      break;
4881
17
    }
4882
17
    case Mips::ADDIUR1SP_MM: {
4883
4
      // op: rd
4884
4
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4885
4
      Value |= (op & UINT64_C(7)) << 7;
4886
4
      // op: imm
4887
4
      op = getUImm6Lsl2Encoding(MI, 1, Fixups, STI);
4888
4
      Value |= (op & UINT64_C(63)) << 1;
4889
4
      break;
4890
17
    }
4891
17
    case Mips::ADDIUR2_MM: {
4892
8
      // op: rd
4893
8
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4894
8
      Value |= (op & UINT64_C(7)) << 7;
4895
8
      // op: rs
4896
8
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4897
8
      Value |= (op & UINT64_C(7)) << 4;
4898
8
      // op: imm
4899
8
      op = getSImm3Lsa2Value(MI, 2, Fixups, STI);
4900
8
      Value |= (op & UINT64_C(7)) << 1;
4901
8
      break;
4902
17
    }
4903
17
    case Mips::ANDI16_MM:
4904
5
    case Mips::ANDI16_MMR6: {
4905
5
      // op: rd
4906
5
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4907
5
      Value |= (op & UINT64_C(7)) << 7;
4908
5
      // op: rs
4909
5
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4910
5
      Value |= (op & UINT64_C(7)) << 4;
4911
5
      // op: imm
4912
5
      op = getUImm4AndValue(MI, 2, Fixups, STI);
4913
5
      Value |= op & UINT64_C(15);
4914
5
      break;
4915
5
    }
4916
8
    case Mips::SLL16_MM:
4917
8
    case Mips::SLL16_MMR6:
4918
8
    case Mips::SRL16_MM:
4919
8
    case Mips::SRL16_MMR6: {
4920
8
      // op: rd
4921
8
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4922
8
      Value |= (op & UINT64_C(7)) << 7;
4923
8
      // op: rt
4924
8
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4925
8
      Value |= (op & UINT64_C(7)) << 4;
4926
8
      // op: shamt
4927
8
      op = getUImm3Mod8Encoding(MI, 2, Fixups, STI);
4928
8
      Value |= (op & UINT64_C(7)) << 1;
4929
8
      break;
4930
8
    }
4931
8
    case Mips::ADDU16_MM:
4932
7
    case Mips::SUBU16_MM: {
4933
7
      // op: rd
4934
7
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4935
7
      Value |= (op & UINT64_C(7)) << 7;
4936
7
      // op: rt
4937
7
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4938
7
      Value |= (op & UINT64_C(7)) << 4;
4939
7
      // op: rs
4940
7
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4941
7
      Value |= (op & UINT64_C(7)) << 1;
4942
7
      break;
4943
7
    }
4944
7
    case Mips::MFHI16_MM:
4945
6
    case Mips::MFLO16_MM: {
4946
6
      // op: rd
4947
6
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4948
6
      Value |= op & UINT64_C(31);
4949
6
      break;
4950
6
    }
4951
6
    case Mips::ADDIUS5_MM: {
4952
4
      // op: rd
4953
4
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4954
4
      Value |= (op & UINT64_C(31)) << 5;
4955
4
      // op: imm
4956
4
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4957
4
      Value |= (op & UINT64_C(15)) << 1;
4958
4
      break;
4959
6
    }
4960
21
    case Mips::DVP_MMR6:
4961
21
    case Mips::EVP_MMR6:
4962
21
    case Mips::JR_MM:
4963
21
    case Mips::MTHI_MM:
4964
21
    case Mips::MTLO_MM: {
4965
21
      // op: rs
4966
21
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4967
21
      Value |= (op & UINT64_C(31)) << 16;
4968
21
      break;
4969
21
    }
4970
21
    case Mips::MFHI_DSP_MM:
4971
2
    case Mips::MFLO_DSP_MM: {
4972
2
      // op: rs
4973
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4974
2
      Value |= (op & UINT64_C(31)) << 16;
4975
2
      // op: ac
4976
2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4977
2
      Value |= (op & UINT64_C(3)) << 14;
4978
2
      break;
4979
2
    }
4980
18
    case Mips::TEQI_MM:
4981
18
    case Mips::TGEIU_MM:
4982
18
    case Mips::TGEI_MM:
4983
18
    case Mips::TLTIU_MM:
4984
18
    case Mips::TLTI_MM:
4985
18
    case Mips::TNEI_MM: {
4986
18
      // op: rs
4987
18
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4988
18
      Value |= (op & UINT64_C(31)) << 16;
4989
18
      // op: imm16
4990
18
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4991
18
      Value |= op & UINT64_C(65535);
4992
18
      break;
4993
18
    }
4994
50
    case Mips::BEQZC_MM:
4995
50
    case Mips::BGEZALS_MM:
4996
50
    case Mips::BGEZAL_MM:
4997
50
    case Mips::BGEZ_MM:
4998
50
    case Mips::BGTZ_MM:
4999
50
    case Mips::BLEZ_MM:
5000
50
    case Mips::BLTZALS_MM:
5001
50
    case Mips::BLTZAL_MM:
5002
50
    case Mips::BLTZ_MM:
5003
50
    case Mips::BNEZC_MM: {
5004
50
      // op: rs
5005
50
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5006
50
      Value |= (op & UINT64_C(31)) << 16;
5007
50
      // op: offset
5008
50
      op = getBranchTargetOpValueMM(MI, 1, Fixups, STI);
5009
50
      Value |= op & UINT64_C(65535);
5010
50
      break;
5011
50
    }
5012
50
    case Mips::MADDU_MM:
5013
24
    case Mips::MADD_MM:
5014
24
    case Mips::MSUBU_MM:
5015
24
    case Mips::MSUB_MM:
5016
24
    case Mips::MULT_MM:
5017
24
    case Mips::MULTu_MM:
5018
24
    case Mips::SDIV_MM:
5019
24
    case Mips::UDIV_MM: {
5020
24
      // op: rs
5021
24
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5022
24
      Value |= (op & UINT64_C(31)) << 16;
5023
24
      // op: rt
5024
24
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5025
24
      Value |= (op & UINT64_C(31)) << 21;
5026
24
      break;
5027
24
    }
5028
30
    case Mips::TEQ_MM:
5029
30
    case Mips::TGEU_MM:
5030
30
    case Mips::TGE_MM:
5031
30
    case Mips::TLTU_MM:
5032
30
    case Mips::TLT_MM:
5033
30
    case Mips::TNE_MM: {
5034
30
      // op: rs
5035
30
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5036
30
      Value |= (op & UINT64_C(31)) << 16;
5037
30
      // op: rt
5038
30
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5039
30
      Value |= (op & UINT64_C(31)) << 21;
5040
30
      // op: code_
5041
30
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5042
30
      Value |= (op & UINT64_C(15)) << 12;
5043
30
      break;
5044
30
    }
5045
33
    case Mips::BEQ_MM:
5046
33
    case Mips::BNE_MM: {
5047
33
      // op: rs
5048
33
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5049
33
      Value |= (op & UINT64_C(31)) << 16;
5050
33
      // op: rt
5051
33
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5052
33
      Value |= (op & UINT64_C(31)) << 21;
5053
33
      // op: offset
5054
33
      op = getBranchTargetOpValueMM(MI, 2, Fixups, STI);
5055
33
      Value |= op & UINT64_C(65535);
5056
33
      break;
5057
33
    }
5058
33
    case Mips::GINVI_MMR6: {
5059
1
      // op: rs
5060
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5061
1
      Value |= (op & UINT64_C(31)) << 16;
5062
1
      // op: type
5063
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5064
1
      Value |= (op & UINT64_C(3)) << 9;
5065
1
      break;
5066
33
    }
5067
33
    case Mips::GINVT_MMR6: {
5068
1
      // op: rs
5069
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5070
1
      Value |= (op & UINT64_C(31)) << 16;
5071
1
      // op: type
5072
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5073
1
      Value |= (op & UINT64_C(3)) << 9;
5074
1
      break;
5075
33
    }
5076
185
    case Mips::JR:
5077
185
    case Mips::JR64:
5078
185
    case Mips::JR_HB:
5079
185
    case Mips::JR_HB64:
5080
185
    case Mips::JR_HB64_R6:
5081
185
    case Mips::JR_HB_R6:
5082
185
    case Mips::MTHI:
5083
185
    case Mips::MTHI64:
5084
185
    case Mips::MTLO:
5085
185
    case Mips::MTLO64:
5086
185
    case Mips::MTM0:
5087
185
    case Mips::MTM1:
5088
185
    case Mips::MTM2:
5089
185
    case Mips::MTP0:
5090
185
    case Mips::MTP1:
5091
185
    case Mips::MTP2: {
5092
185
      // op: rs
5093
185
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5094
185
      Value |= (op & UINT64_C(31)) << 21;
5095
185
      break;
5096
185
    }
5097
185
    case Mips::ALUIPC:
5098
15
    case Mips::AUIPC: {
5099
15
      // op: rs
5100
15
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5101
15
      Value |= (op & UINT64_C(31)) << 21;
5102
15
      // op: imm
5103
15
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5104
15
      Value |= op & UINT64_C(65535);
5105
15
      break;
5106
15
    }
5107
15
    case Mips::DAHI:
5108
2
    case Mips::DATI: {
5109
2
      // op: rs
5110
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5111
2
      Value |= (op & UINT64_C(31)) << 21;
5112
2
      // op: imm
5113
2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5114
2
      Value |= op & UINT64_C(65535);
5115
2
      break;
5116
2
    }
5117
9
    case Mips::LDPC: {
5118
9
      // op: rs
5119
9
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5120
9
      Value |= (op & UINT64_C(31)) << 21;
5121
9
      // op: imm
5122
9
      op = getSimm18Lsl3Encoding(MI, 1, Fixups, STI);
5123
9
      Value |= op & UINT64_C(262143);
5124
9
      break;
5125
2
    }
5126
46
    case Mips::ADDIUPC:
5127
46
    case Mips::LWPC:
5128
46
    case Mips::LWUPC: {
5129
46
      // op: rs
5130
46
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5131
46
      Value |= (op & UINT64_C(31)) << 21;
5132
46
      // op: imm
5133
46
      op = getSimm19Lsl2Encoding(MI, 1, Fixups, STI);
5134
46
      Value |= op & UINT64_C(524287);
5135
46
      break;
5136
46
    }
5137
84
    case Mips::TEQI:
5138
84
    case Mips::TGEI:
5139
84
    case Mips::TGEIU:
5140
84
    case Mips::TLTI:
5141
84
    case Mips::TNEI:
5142
84
    case Mips::TTLTIU: {
5143
84
      // op: rs
5144
84
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5145
84
      Value |= (op & UINT64_C(31)) << 21;
5146
84
      // op: imm16
5147
84
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5148
84
      Value |= op & UINT64_C(65535);
5149
84
      break;
5150
84
    }
5151
84
    case Mips::WRDSP: {
5152
8
      // op: rs
5153
8
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5154
8
      Value |= (op & UINT64_C(31)) << 21;
5155
8
      // op: mask
5156
8
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5157
8
      Value |= (op & UINT64_C(1023)) << 11;
5158
8
      break;
5159
84
    }
5160
84
    case Mips::BEQZC:
5161
26
    case Mips::BEQZC64:
5162
26
    case Mips::BNEZC:
5163
26
    case Mips::BNEZC64: {
5164
26
      // op: rs
5165
26
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5166
26
      Value |= (op & UINT64_C(31)) << 21;
5167
26
      // op: offset
5168
26
      op = getBranchTarget21OpValue(MI, 1, Fixups, STI);
5169
26
      Value |= op & UINT64_C(2097151);
5170
26
      break;
5171
26
    }
5172
26
    case Mips::BEQZC_MMR6:
5173
8
    case Mips::BNEZC_MMR6: {
5174
8
      // op: rs
5175
8
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5176
8
      Value |= (op & UINT64_C(31)) << 21;
5177
8
      // op: offset
5178
8
      op = getBranchTarget21OpValueMM(MI, 1, Fixups, STI);
5179
8
      Value |= op & UINT64_C(2097151);
5180
8
      break;
5181
8
    }
5182
168
    case Mips::BGEZ:
5183
168
    case Mips::BGEZ64:
5184
168
    case Mips::BGEZAL:
5185
168
    case Mips::BGEZALL:
5186
168
    case Mips::BGEZL:
5187
168
    case Mips::BGTZ:
5188
168
    case Mips::BGTZ64:
5189
168
    case Mips::BGTZL:
5190
168
    case Mips::BLEZ:
5191
168
    case Mips::BLEZ64:
5192
168
    case Mips::BLEZL:
5193
168
    case Mips::BLTZ:
5194
168
    case Mips::BLTZ64:
5195
168
    case Mips::BLTZAL:
5196
168
    case Mips::BLTZALL:
5197
168
    case Mips::BLTZL: {
5198
168
      // op: rs
5199
168
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5200
168
      Value |= (op & UINT64_C(31)) << 21;
5201
168
      // op: offset
5202
168
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
5203
168
      Value |= op & UINT64_C(65535);
5204
168
      break;
5205
168
    }
5206
168
    case Mips::BBIT0:
5207
6
    case Mips::BBIT032:
5208
6
    case Mips::BBIT1:
5209
6
    case Mips::BBIT132: {
5210
6
      // op: rs
5211
6
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5212
6
      Value |= (op & UINT64_C(31)) << 21;
5213
6
      // op: p
5214
6
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5215
6
      Value |= (op & UINT64_C(31)) << 16;
5216
6
      // op: offset
5217
6
      op = getBranchTargetOpValue(MI, 2, Fixups, STI);
5218
6
      Value |= op & UINT64_C(65535);
5219
6
      break;
5220
6
    }
5221
585
    case Mips::CMPU_EQ_QB:
5222
585
    case Mips::CMPU_LE_QB:
5223
585
    case Mips::CMPU_LT_QB:
5224
585
    case Mips::CMP_EQ_PH:
5225
585
    case Mips::CMP_LE_PH:
5226
585
    case Mips::CMP_LT_PH:
5227
585
    case Mips::DMULT:
5228
585
    case Mips::DMULTu:
5229
585
    case Mips::DSDIV:
5230
585
    case Mips::DUDIV:
5231
585
    case Mips::MADD:
5232
585
    case Mips::MADDU:
5233
585
    case Mips::MSUB:
5234
585
    case Mips::MSUBU:
5235
585
    case Mips::MULT:
5236
585
    case Mips::MULTu:
5237
585
    case Mips::SDIV:
5238
585
    case Mips::UDIV: {
5239
585
      // op: rs
5240
585
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5241
585
      Value |= (op & UINT64_C(31)) << 21;
5242
585
      // op: rt
5243
585
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5244
585
      Value |= (op & UINT64_C(31)) << 16;
5245
585
      break;
5246
585
    }
5247
585
    case Mips::TEQ:
5248
321
    case Mips::TGE:
5249
321
    case Mips::TGEU:
5250
321
    case Mips::TLT:
5251
321
    case Mips::TLTU:
5252
321
    case Mips::TNE: {
5253
321
      // op: rs
5254
321
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5255
321
      Value |= (op & UINT64_C(31)) << 21;
5256
321
      // op: rt
5257
321
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5258
321
      Value |= (op & UINT64_C(31)) << 16;
5259
321
      // op: code_
5260
321
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5261
321
      Value |= (op & UINT64_C(1023)) << 6;
5262
321
      break;
5263
321
    }
5264
360
    case Mips::BEQ:
5265
360
    case Mips::BEQ64:
5266
360
    case Mips::BEQC:
5267
360
    case Mips::BEQC64:
5268
360
    case Mips::BEQL:
5269
360
    case Mips::BGEC:
5270
360
    case Mips::BGEC64:
5271
360
    case Mips::BGEUC:
5272
360
    case Mips::BGEUC64:
5273
360
    case Mips::BLTC:
5274
360
    case Mips::BLTC64:
5275
360
    case Mips::BLTUC:
5276
360
    case Mips::BLTUC64:
5277
360
    case Mips::BNE:
5278
360
    case Mips::BNE64:
5279
360
    case Mips::BNEC:
5280
360
    case Mips::BNEC64:
5281
360
    case Mips::BNEL:
5282
360
    case Mips::BNVC:
5283
360
    case Mips::BOVC: {
5284
360
      // op: rs
5285
360
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5286
360
      Value |= (op & UINT64_C(31)) << 21;
5287
360
      // op: rt
5288
360
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5289
360
      Value |= (op & UINT64_C(31)) << 16;
5290
360
      // op: offset
5291
360
      op = getBranchTargetOpValue(MI, 2, Fixups, STI);
5292
360
      Value |= op & UINT64_C(65535);
5293
360
      break;
5294
360
    }
5295
360
    case Mips::FORK: {
5296
1
      // op: rs
5297
1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5298
1
      Value |= (op & UINT64_C(31)) << 21;
5299
1
      // op: rt
5300
1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5301
1
      Value |= (op & UINT64_C(31)) << 16;
5302
1
      // op: rd
5303
1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5304
1
      Value |= (op & UINT64_C(31)) << 11;
5305
1
      break;
5306
360
    }
5307
360
    case Mips::GINVI: {
5308
5
      // op: rs
5309
5
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5310
5
      Value |= (op & UINT64_C(31)) << 21;
5311
5
      // op: type_
5312
5
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5313
5
      Value |= (op & UINT64_C(3)) << 8;
5314
5
      break;
5315
360
    }
5316
360
    case Mips::GINVT: {
5317
2
      // op: rs
5318
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5319
2
      Value |= (op & UINT64_C(31)) << 21;
5320
2
      // op: type_
5321
2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5322
2
      Value |= (op & UINT64_C(3)) << 8;
5323
2
      break;
5324
360
    }
5325
360
    case Mips::JALRC16_MMR6:
5326
2
    case Mips::JRC16_MMR6: {
5327
2
      // op: rs
5328
2
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5329
2
      Value |= (op & UINT64_C(31)) << 5;
5330
2
      break;
5331
2
    }
5332
9
    case Mips::ADDIUPC_MM: {
5333
9
      // op: rs
5334
9
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5335
9
      Value |= (op & UINT64_C(7)) << 23;
5336
9
      // op: imm
5337
9
      op = getSimm23Lsl2Encoding(MI, 1, Fixups, STI);
5338
9
      Value |= op & UINT64_C(8388607);
5339
9
      break;
5340
2
    }
5341
15
    case Mips::BEQZ16_MM:
5342
15
    case Mips::BEQZC16_MMR6:
5343
15
    case Mips::BNEZ16_MM:
5344
15
    case Mips::BNEZC16_MMR6: {
5345
15
      // op: rs
5346
15
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5347
15
      Value |= (op & UINT64_C(7)) << 7;
5348
15
      // op: offset
5349
15
      op = getBranchTarget7OpValueMM(MI, 1, Fixups, STI);
5350
15
      Value |= op & UINT64_C(127);
5351
15
      break;
5352
15
    }
5353
35
    case Mips::JALR16_MM: