Coverage Report

Created: 2018-09-25 17:16

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Mips/MipsGenMCPseudoLowering.inc
Line
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Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Pseudo-instruction MC lowering Source Fragment                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
bool MipsAsmPrinter::
10
emitPseudoExpansionLowering(MCStreamer &OutStreamer,
11
125k
                            const MachineInstr *MI) {
12
125k
  switch (MI->getOpcode()) {
13
125k
    
default: return false119k
;
14
125k
    case Mips::AND_V_D_PSEUDO: {
15
6
      MCInst TmpInst;
16
6
      MCOperand MCOp;
17
6
      TmpInst.setOpcode(Mips::AND_V);
18
6
      // Operand: wd
19
6
      lowerOperand(MI->getOperand(0), MCOp);
20
6
      TmpInst.addOperand(MCOp);
21
6
      // Operand: ws
22
6
      lowerOperand(MI->getOperand(1), MCOp);
23
6
      TmpInst.addOperand(MCOp);
24
6
      // Operand: wt
25
6
      lowerOperand(MI->getOperand(2), MCOp);
26
6
      TmpInst.addOperand(MCOp);
27
6
      EmitToStreamer(OutStreamer, TmpInst);
28
6
      break;
29
125k
    }
30
125k
    case Mips::AND_V_H_PSEUDO: {
31
6
      MCInst TmpInst;
32
6
      MCOperand MCOp;
33
6
      TmpInst.setOpcode(Mips::AND_V);
34
6
      // Operand: wd
35
6
      lowerOperand(MI->getOperand(0), MCOp);
36
6
      TmpInst.addOperand(MCOp);
37
6
      // Operand: ws
38
6
      lowerOperand(MI->getOperand(1), MCOp);
39
6
      TmpInst.addOperand(MCOp);
40
6
      // Operand: wt
41
6
      lowerOperand(MI->getOperand(2), MCOp);
42
6
      TmpInst.addOperand(MCOp);
43
6
      EmitToStreamer(OutStreamer, TmpInst);
44
6
      break;
45
125k
    }
46
125k
    case Mips::AND_V_W_PSEUDO: {
47
6
      MCInst TmpInst;
48
6
      MCOperand MCOp;
49
6
      TmpInst.setOpcode(Mips::AND_V);
50
6
      // Operand: wd
51
6
      lowerOperand(MI->getOperand(0), MCOp);
52
6
      TmpInst.addOperand(MCOp);
53
6
      // Operand: ws
54
6
      lowerOperand(MI->getOperand(1), MCOp);
55
6
      TmpInst.addOperand(MCOp);
56
6
      // Operand: wt
57
6
      lowerOperand(MI->getOperand(2), MCOp);
58
6
      TmpInst.addOperand(MCOp);
59
6
      EmitToStreamer(OutStreamer, TmpInst);
60
6
      break;
61
125k
    }
62
125k
    case Mips::B: {
63
66
      MCInst TmpInst;
64
66
      MCOperand MCOp;
65
66
      TmpInst.setOpcode(Mips::BEQ);
66
66
      // Operand: rs
67
66
      TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
68
66
      // Operand: rt
69
66
      TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
70
66
      // Operand: offset
71
66
      lowerOperand(MI->getOperand(0), MCOp);
72
66
      TmpInst.addOperand(MCOp);
73
66
      EmitToStreamer(OutStreamer, TmpInst);
74
66
      break;
75
125k
    }
76
125k
    case Mips::BAL_BR: {
77
10
      MCInst TmpInst;
78
10
      MCOperand MCOp;
79
10
      TmpInst.setOpcode(Mips::BGEZAL);
80
10
      // Operand: rs
81
10
      TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
82
10
      // Operand: offset
83
10
      lowerOperand(MI->getOperand(0), MCOp);
84
10
      TmpInst.addOperand(MCOp);
85
10
      EmitToStreamer(OutStreamer, TmpInst);
86
10
      break;
87
125k
    }
88
125k
    case Mips::BAL_BR_MM: {
89
6
      MCInst TmpInst;
90
6
      MCOperand MCOp;
91
6
      TmpInst.setOpcode(Mips::BGEZAL_MM);
92
6
      // Operand: rs
93
6
      TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
94
6
      // Operand: offset
95
6
      lowerOperand(MI->getOperand(0), MCOp);
96
6
      TmpInst.addOperand(MCOp);
97
6
      EmitToStreamer(OutStreamer, TmpInst);
98
6
      break;
99
125k
    }
100
125k
    case Mips::BSEL_D_PSEUDO: {
101
10
      MCInst TmpInst;
102
10
      MCOperand MCOp;
103
10
      TmpInst.setOpcode(Mips::BSEL_V);
104
10
      // Operand: wd
105
10
      lowerOperand(MI->getOperand(0), MCOp);
106
10
      TmpInst.addOperand(MCOp);
107
10
      // Operand: wd_in
108
10
      lowerOperand(MI->getOperand(1), MCOp);
109
10
      TmpInst.addOperand(MCOp);
110
10
      // Operand: ws
111
10
      lowerOperand(MI->getOperand(2), MCOp);
112
10
      TmpInst.addOperand(MCOp);
113
10
      // Operand: wt
114
10
      lowerOperand(MI->getOperand(3), MCOp);
115
10
      TmpInst.addOperand(MCOp);
116
10
      EmitToStreamer(OutStreamer, TmpInst);
117
10
      break;
118
125k
    }
119
125k
    case Mips::BSEL_FD_PSEUDO: {
120
4
      MCInst TmpInst;
121
4
      MCOperand MCOp;
122
4
      TmpInst.setOpcode(Mips::BSEL_V);
123
4
      // Operand: wd
124
4
      lowerOperand(MI->getOperand(0), MCOp);
125
4
      TmpInst.addOperand(MCOp);
126
4
      // Operand: wd_in
127
4
      lowerOperand(MI->getOperand(1), MCOp);
128
4
      TmpInst.addOperand(MCOp);
129
4
      // Operand: ws
130
4
      lowerOperand(MI->getOperand(2), MCOp);
131
4
      TmpInst.addOperand(MCOp);
132
4
      // Operand: wt
133
4
      lowerOperand(MI->getOperand(3), MCOp);
134
4
      TmpInst.addOperand(MCOp);
135
4
      EmitToStreamer(OutStreamer, TmpInst);
136
4
      break;
137
125k
    }
138
125k
    case Mips::BSEL_FW_PSEUDO: {
139
8
      MCInst TmpInst;
140
8
      MCOperand MCOp;
141
8
      TmpInst.setOpcode(Mips::BSEL_V);
142
8
      // Operand: wd
143
8
      lowerOperand(MI->getOperand(0), MCOp);
144
8
      TmpInst.addOperand(MCOp);
145
8
      // Operand: wd_in
146
8
      lowerOperand(MI->getOperand(1), MCOp);
147
8
      TmpInst.addOperand(MCOp);
148
8
      // Operand: ws
149
8
      lowerOperand(MI->getOperand(2), MCOp);
150
8
      TmpInst.addOperand(MCOp);
151
8
      // Operand: wt
152
8
      lowerOperand(MI->getOperand(3), MCOp);
153
8
      TmpInst.addOperand(MCOp);
154
8
      EmitToStreamer(OutStreamer, TmpInst);
155
8
      break;
156
125k
    }
157
125k
    case Mips::BSEL_H_PSEUDO: {
158
10
      MCInst TmpInst;
159
10
      MCOperand MCOp;
160
10
      TmpInst.setOpcode(Mips::BSEL_V);
161
10
      // Operand: wd
162
10
      lowerOperand(MI->getOperand(0), MCOp);
163
10
      TmpInst.addOperand(MCOp);
164
10
      // Operand: wd_in
165
10
      lowerOperand(MI->getOperand(1), MCOp);
166
10
      TmpInst.addOperand(MCOp);
167
10
      // Operand: ws
168
10
      lowerOperand(MI->getOperand(2), MCOp);
169
10
      TmpInst.addOperand(MCOp);
170
10
      // Operand: wt
171
10
      lowerOperand(MI->getOperand(3), MCOp);
172
10
      TmpInst.addOperand(MCOp);
173
10
      EmitToStreamer(OutStreamer, TmpInst);
174
10
      break;
175
125k
    }
176
125k
    case Mips::BSEL_W_PSEUDO: {
177
10
      MCInst TmpInst;
178
10
      MCOperand MCOp;
179
10
      TmpInst.setOpcode(Mips::BSEL_V);
180
10
      // Operand: wd
181
10
      lowerOperand(MI->getOperand(0), MCOp);
182
10
      TmpInst.addOperand(MCOp);
183
10
      // Operand: wd_in
184
10
      lowerOperand(MI->getOperand(1), MCOp);
185
10
      TmpInst.addOperand(MCOp);
186
10
      // Operand: ws
187
10
      lowerOperand(MI->getOperand(2), MCOp);
188
10
      TmpInst.addOperand(MCOp);
189
10
      // Operand: wt
190
10
      lowerOperand(MI->getOperand(3), MCOp);
191
10
      TmpInst.addOperand(MCOp);
192
10
      EmitToStreamer(OutStreamer, TmpInst);
193
10
      break;
194
125k
    }
195
125k
    case Mips::B_MM: {
196
4
      MCInst TmpInst;
197
4
      MCOperand MCOp;
198
4
      TmpInst.setOpcode(Mips::BEQ_MM);
199
4
      // Operand: rs
200
4
      TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
201
4
      // Operand: rt
202
4
      TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
203
4
      // Operand: offset
204
4
      lowerOperand(MI->getOperand(0), MCOp);
205
4
      TmpInst.addOperand(MCOp);
206
4
      EmitToStreamer(OutStreamer, TmpInst);
207
4
      break;
208
125k
    }
209
125k
    case Mips::FABS_D: {
210
2
      MCInst TmpInst;
211
2
      MCOperand MCOp;
212
2
      TmpInst.setOpcode(Mips::FMAX_A_D);
213
2
      // Operand: wd
214
2
      lowerOperand(MI->getOperand(0), MCOp);
215
2
      TmpInst.addOperand(MCOp);
216
2
      // Operand: ws
217
2
      lowerOperand(MI->getOperand(1), MCOp);
218
2
      TmpInst.addOperand(MCOp);
219
2
      // Operand: wt
220
2
      lowerOperand(MI->getOperand(1), MCOp);
221
2
      TmpInst.addOperand(MCOp);
222
2
      EmitToStreamer(OutStreamer, TmpInst);
223
2
      break;
224
125k
    }
225
125k
    case Mips::FABS_W: {
226
2
      MCInst TmpInst;
227
2
      MCOperand MCOp;
228
2
      TmpInst.setOpcode(Mips::FMAX_A_W);
229
2
      // Operand: wd
230
2
      lowerOperand(MI->getOperand(0), MCOp);
231
2
      TmpInst.addOperand(MCOp);
232
2
      // Operand: ws
233
2
      lowerOperand(MI->getOperand(1), MCOp);
234
2
      TmpInst.addOperand(MCOp);
235
2
      // Operand: wt
236
2
      lowerOperand(MI->getOperand(1), MCOp);
237
2
      TmpInst.addOperand(MCOp);
238
2
      EmitToStreamer(OutStreamer, TmpInst);
239
2
      break;
240
125k
    }
241
125k
    case Mips::JALR64Pseudo: {
242
453
      MCInst TmpInst;
243
453
      MCOperand MCOp;
244
453
      TmpInst.setOpcode(Mips::JALR);
245
453
      // Operand: rd
246
453
      TmpInst.addOperand(MCOperand::createReg(Mips::RA));
247
453
      // Operand: rs
248
453
      lowerOperand(MI->getOperand(0), MCOp);
249
453
      TmpInst.addOperand(MCOp);
250
453
      EmitToStreamer(OutStreamer, TmpInst);
251
453
      break;
252
125k
    }
253
125k
    case Mips::JALRHB64Pseudo: {
254
6
      MCInst TmpInst;
255
6
      MCOperand MCOp;
256
6
      TmpInst.setOpcode(Mips::JALR_HB64);
257
6
      // Operand: rd
258
6
      TmpInst.addOperand(MCOperand::createReg(Mips::RA_64));
259
6
      // Operand: rs
260
6
      lowerOperand(MI->getOperand(0), MCOp);
261
6
      TmpInst.addOperand(MCOp);
262
6
      EmitToStreamer(OutStreamer, TmpInst);
263
6
      break;
264
125k
    }
265
125k
    case Mips::JALRHBPseudo: {
266
8
      MCInst TmpInst;
267
8
      MCOperand MCOp;
268
8
      TmpInst.setOpcode(Mips::JALR_HB);
269
8
      // Operand: rd
270
8
      TmpInst.addOperand(MCOperand::createReg(Mips::RA));
271
8
      // Operand: rs
272
8
      lowerOperand(MI->getOperand(0), MCOp);
273
8
      TmpInst.addOperand(MCOp);
274
8
      EmitToStreamer(OutStreamer, TmpInst);
275
8
      break;
276
125k
    }
277
125k
    case Mips::JALRPseudo: {
278
501
      MCInst TmpInst;
279
501
      MCOperand MCOp;
280
501
      TmpInst.setOpcode(Mips::JALR);
281
501
      // Operand: rd
282
501
      TmpInst.addOperand(MCOperand::createReg(Mips::RA));
283
501
      // Operand: rs
284
501
      lowerOperand(MI->getOperand(0), MCOp);
285
501
      TmpInst.addOperand(MCOp);
286
501
      EmitToStreamer(OutStreamer, TmpInst);
287
501
      break;
288
125k
    }
289
125k
    case Mips::NOP: {
290
3.54k
      MCInst TmpInst;
291
3.54k
      MCOperand MCOp;
292
3.54k
      TmpInst.setOpcode(Mips::SLL);
293
3.54k
      // Operand: rd
294
3.54k
      TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
295
3.54k
      // Operand: rt
296
3.54k
      TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
297
3.54k
      // Operand: shamt
298
3.54k
      TmpInst.addOperand(MCOperand::createImm(0));
299
3.54k
      EmitToStreamer(OutStreamer, TmpInst);
300
3.54k
      break;
301
125k
    }
302
125k
    case Mips::NOR_V_D_PSEUDO: {
303
4
      MCInst TmpInst;
304
4
      MCOperand MCOp;
305
4
      TmpInst.setOpcode(Mips::NOR_V);
306
4
      // Operand: wd
307
4
      lowerOperand(MI->getOperand(0), MCOp);
308
4
      TmpInst.addOperand(MCOp);
309
4
      // Operand: ws
310
4
      lowerOperand(MI->getOperand(1), MCOp);
311
4
      TmpInst.addOperand(MCOp);
312
4
      // Operand: wt
313
4
      lowerOperand(MI->getOperand(2), MCOp);
314
4
      TmpInst.addOperand(MCOp);
315
4
      EmitToStreamer(OutStreamer, TmpInst);
316
4
      break;
317
125k
    }
318
125k
    case Mips::NOR_V_H_PSEUDO: {
319
4
      MCInst TmpInst;
320
4
      MCOperand MCOp;
321
4
      TmpInst.setOpcode(Mips::NOR_V);
322
4
      // Operand: wd
323
4
      lowerOperand(MI->getOperand(0), MCOp);
324
4
      TmpInst.addOperand(MCOp);
325
4
      // Operand: ws
326
4
      lowerOperand(MI->getOperand(1), MCOp);
327
4
      TmpInst.addOperand(MCOp);
328
4
      // Operand: wt
329
4
      lowerOperand(MI->getOperand(2), MCOp);
330
4
      TmpInst.addOperand(MCOp);
331
4
      EmitToStreamer(OutStreamer, TmpInst);
332
4
      break;
333
125k
    }
334
125k
    case Mips::NOR_V_W_PSEUDO: {
335
4
      MCInst TmpInst;
336
4
      MCOperand MCOp;
337
4
      TmpInst.setOpcode(Mips::NOR_V);
338
4
      // Operand: wd
339
4
      lowerOperand(MI->getOperand(0), MCOp);
340
4
      TmpInst.addOperand(MCOp);
341
4
      // Operand: ws
342
4
      lowerOperand(MI->getOperand(1), MCOp);
343
4
      TmpInst.addOperand(MCOp);
344
4
      // Operand: wt
345
4
      lowerOperand(MI->getOperand(2), MCOp);
346
4
      TmpInst.addOperand(MCOp);
347
4
      EmitToStreamer(OutStreamer, TmpInst);
348
4
      break;
349
125k
    }
350
125k
    case Mips::OR_V_D_PSEUDO: {
351
6
      MCInst TmpInst;
352
6
      MCOperand MCOp;
353
6
      TmpInst.setOpcode(Mips::OR_V);
354
6
      // Operand: wd
355
6
      lowerOperand(MI->getOperand(0), MCOp);
356
6
      TmpInst.addOperand(MCOp);
357
6
      // Operand: ws
358
6
      lowerOperand(MI->getOperand(1), MCOp);
359
6
      TmpInst.addOperand(MCOp);
360
6
      // Operand: wt
361
6
      lowerOperand(MI->getOperand(2), MCOp);
362
6
      TmpInst.addOperand(MCOp);
363
6
      EmitToStreamer(OutStreamer, TmpInst);
364
6
      break;
365
125k
    }
366
125k
    case Mips::OR_V_H_PSEUDO: {
367
6
      MCInst TmpInst;
368
6
      MCOperand MCOp;
369
6
      TmpInst.setOpcode(Mips::OR_V);
370
6
      // Operand: wd
371
6
      lowerOperand(MI->getOperand(0), MCOp);
372
6
      TmpInst.addOperand(MCOp);
373
6
      // Operand: ws
374
6
      lowerOperand(MI->getOperand(1), MCOp);
375
6
      TmpInst.addOperand(MCOp);
376
6
      // Operand: wt
377
6
      lowerOperand(MI->getOperand(2), MCOp);
378
6
      TmpInst.addOperand(MCOp);
379
6
      EmitToStreamer(OutStreamer, TmpInst);
380
6
      break;
381
125k
    }
382
125k
    case Mips::OR_V_W_PSEUDO: {
383
6
      MCInst TmpInst;
384
6
      MCOperand MCOp;
385
6
      TmpInst.setOpcode(Mips::OR_V);
386
6
      // Operand: wd
387
6
      lowerOperand(MI->getOperand(0), MCOp);
388
6
      TmpInst.addOperand(MCOp);
389
6
      // Operand: ws
390
6
      lowerOperand(MI->getOperand(1), MCOp);
391
6
      TmpInst.addOperand(MCOp);
392
6
      // Operand: wt
393
6
      lowerOperand(MI->getOperand(2), MCOp);
394
6
      TmpInst.addOperand(MCOp);
395
6
      EmitToStreamer(OutStreamer, TmpInst);
396
6
      break;
397
125k
    }
398
125k
    case Mips::PseudoCMPU_EQ_QB: {
399
4
      MCInst TmpInst;
400
4
      MCOperand MCOp;
401
4
      TmpInst.setOpcode(Mips::CMPU_EQ_QB);
402
4
      // Operand: rs
403
4
      lowerOperand(MI->getOperand(1), MCOp);
404
4
      TmpInst.addOperand(MCOp);
405
4
      // Operand: rt
406
4
      lowerOperand(MI->getOperand(2), MCOp);
407
4
      TmpInst.addOperand(MCOp);
408
4
      EmitToStreamer(OutStreamer, TmpInst);
409
4
      break;
410
125k
    }
411
125k
    case Mips::PseudoCMPU_LE_QB: {
412
4
      MCInst TmpInst;
413
4
      MCOperand MCOp;
414
4
      TmpInst.setOpcode(Mips::CMPU_LE_QB);
415
4
      // Operand: rs
416
4
      lowerOperand(MI->getOperand(1), MCOp);
417
4
      TmpInst.addOperand(MCOp);
418
4
      // Operand: rt
419
4
      lowerOperand(MI->getOperand(2), MCOp);
420
4
      TmpInst.addOperand(MCOp);
421
4
      EmitToStreamer(OutStreamer, TmpInst);
422
4
      break;
423
125k
    }
424
125k
    case Mips::PseudoCMPU_LT_QB: {
425
4
      MCInst TmpInst;
426
4
      MCOperand MCOp;
427
4
      TmpInst.setOpcode(Mips::CMPU_LT_QB);
428
4
      // Operand: rs
429
4
      lowerOperand(MI->getOperand(1), MCOp);
430
4
      TmpInst.addOperand(MCOp);
431
4
      // Operand: rt
432
4
      lowerOperand(MI->getOperand(2), MCOp);
433
4
      TmpInst.addOperand(MCOp);
434
4
      EmitToStreamer(OutStreamer, TmpInst);
435
4
      break;
436
125k
    }
437
125k
    case Mips::PseudoCMP_EQ_PH: {
438
4
      MCInst TmpInst;
439
4
      MCOperand MCOp;
440
4
      TmpInst.setOpcode(Mips::CMP_EQ_PH);
441
4
      // Operand: rs
442
4
      lowerOperand(MI->getOperand(1), MCOp);
443
4
      TmpInst.addOperand(MCOp);
444
4
      // Operand: rt
445
4
      lowerOperand(MI->getOperand(2), MCOp);
446
4
      TmpInst.addOperand(MCOp);
447
4
      EmitToStreamer(OutStreamer, TmpInst);
448
4
      break;
449
125k
    }
450
125k
    case Mips::PseudoCMP_LE_PH: {
451
4
      MCInst TmpInst;
452
4
      MCOperand MCOp;
453
4
      TmpInst.setOpcode(Mips::CMP_LE_PH);
454
4
      // Operand: rs
455
4
      lowerOperand(MI->getOperand(1), MCOp);
456
4
      TmpInst.addOperand(MCOp);
457
4
      // Operand: rt
458
4
      lowerOperand(MI->getOperand(2), MCOp);
459
4
      TmpInst.addOperand(MCOp);
460
4
      EmitToStreamer(OutStreamer, TmpInst);
461
4
      break;
462
125k
    }
463
125k
    case Mips::PseudoCMP_LT_PH: {
464
5
      MCInst TmpInst;
465
5
      MCOperand MCOp;
466
5
      TmpInst.setOpcode(Mips::CMP_LT_PH);
467
5
      // Operand: rs
468
5
      lowerOperand(MI->getOperand(1), MCOp);
469
5
      TmpInst.addOperand(MCOp);
470
5
      // Operand: rt
471
5
      lowerOperand(MI->getOperand(2), MCOp);
472
5
      TmpInst.addOperand(MCOp);
473
5
      EmitToStreamer(OutStreamer, TmpInst);
474
5
      break;
475
125k
    }
476
125k
    case Mips::PseudoDMULT: {
477
54
      MCInst TmpInst;
478
54
      MCOperand MCOp;
479
54
      TmpInst.setOpcode(Mips::DMULT);
480
54
      // Operand: rs
481
54
      lowerOperand(MI->getOperand(1), MCOp);
482
54
      TmpInst.addOperand(MCOp);
483
54
      // Operand: rt
484
54
      lowerOperand(MI->getOperand(2), MCOp);
485
54
      TmpInst.addOperand(MCOp);
486
54
      EmitToStreamer(OutStreamer, TmpInst);
487
54
      break;
488
125k
    }
489
125k
    case Mips::PseudoDMULTu: {
490
5
      MCInst TmpInst;
491
5
      MCOperand MCOp;
492
5
      TmpInst.setOpcode(Mips::DMULTu);
493
5
      // Operand: rs
494
5
      lowerOperand(MI->getOperand(1), MCOp);
495
5
      TmpInst.addOperand(MCOp);
496
5
      // Operand: rt
497
5
      lowerOperand(MI->getOperand(2), MCOp);
498
5
      TmpInst.addOperand(MCOp);
499
5
      EmitToStreamer(OutStreamer, TmpInst);
500
5
      break;
501
125k
    }
502
125k
    case Mips::PseudoDSDIV: {
503
36
      MCInst TmpInst;
504
36
      MCOperand MCOp;
505
36
      TmpInst.setOpcode(Mips::DSDIV);
506
36
      // Operand: rs
507
36
      lowerOperand(MI->getOperand(1), MCOp);
508
36
      TmpInst.addOperand(MCOp);
509
36
      // Operand: rt
510
36
      lowerOperand(MI->getOperand(2), MCOp);
511
36
      TmpInst.addOperand(MCOp);
512
36
      EmitToStreamer(OutStreamer, TmpInst);
513
36
      break;
514
125k
    }
515
125k
    case Mips::PseudoDUDIV: {
516
36
      MCInst TmpInst;
517
36
      MCOperand MCOp;
518
36
      TmpInst.setOpcode(Mips::DUDIV);
519
36
      // Operand: rs
520
36
      lowerOperand(MI->getOperand(1), MCOp);
521
36
      TmpInst.addOperand(MCOp);
522
36
      // Operand: rt
523
36
      lowerOperand(MI->getOperand(2), MCOp);
524
36
      TmpInst.addOperand(MCOp);
525
36
      EmitToStreamer(OutStreamer, TmpInst);
526
36
      break;
527
125k
    }
528
125k
    case Mips::PseudoIndirectBranch: {
529
16
      MCInst TmpInst;
530
16
      MCOperand MCOp;
531
16
      TmpInst.setOpcode(Mips::JR);
532
16
      // Operand: rs
533
16
      lowerOperand(MI->getOperand(0), MCOp);
534
16
      TmpInst.addOperand(MCOp);
535
16
      EmitToStreamer(OutStreamer, TmpInst);
536
16
      break;
537
125k
    }
538
125k
    case Mips::PseudoIndirectBranch64: {
539
13
      MCInst TmpInst;
540
13
      MCOperand MCOp;
541
13
      TmpInst.setOpcode(Mips::JR64);
542
13
      // Operand: rs
543
13
      lowerOperand(MI->getOperand(0), MCOp);
544
13
      TmpInst.addOperand(MCOp);
545
13
      EmitToStreamer(OutStreamer, TmpInst);
546
13
      break;
547
125k
    }
548
125k
    case Mips::PseudoIndirectBranch64R6: {
549
0
      MCInst TmpInst;
550
0
      MCOperand MCOp;
551
0
      TmpInst.setOpcode(Mips::JALR64);
552
0
      // Operand: rd
553
0
      TmpInst.addOperand(MCOperand::createReg(Mips::ZERO_64));
554
0
      // Operand: rs
555
0
      lowerOperand(MI->getOperand(0), MCOp);
556
0
      TmpInst.addOperand(MCOp);
557
0
      EmitToStreamer(OutStreamer, TmpInst);
558
0
      break;
559
125k
    }
560
125k
    case Mips::PseudoIndirectBranchR6: {
561
0
      MCInst TmpInst;
562
0
      MCOperand MCOp;
563
0
      TmpInst.setOpcode(Mips::JALR);
564
0
      // Operand: rd
565
0
      TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
566
0
      // Operand: rs
567
0
      lowerOperand(MI->getOperand(0), MCOp);
568
0
      TmpInst.addOperand(MCOp);
569
0
      EmitToStreamer(OutStreamer, TmpInst);
570
0
      break;
571
125k
    }
572
125k
    case Mips::PseudoIndirectBranch_MM: {
573
1
      MCInst TmpInst;
574
1
      MCOperand MCOp;
575
1
      TmpInst.setOpcode(Mips::JR_MM);
576
1
      // Operand: rs
577
1
      lowerOperand(MI->getOperand(0), MCOp);
578
1
      TmpInst.addOperand(MCOp);
579
1
      EmitToStreamer(OutStreamer, TmpInst);
580
1
      break;
581
125k
    }
582
125k
    case Mips::PseudoIndirectBranch_MMR6: {
583
0
      MCInst TmpInst;
584
0
      MCOperand MCOp;
585
0
      TmpInst.setOpcode(Mips::JRC16_MMR6);
586
0
      // Operand: rs
587
0
      lowerOperand(MI->getOperand(0), MCOp);
588
0
      TmpInst.addOperand(MCOp);
589
0
      EmitToStreamer(OutStreamer, TmpInst);
590
0
      break;
591
125k
    }
592
125k
    case Mips::PseudoIndirectHazardBranch: {
593
2
      MCInst TmpInst;
594
2
      MCOperand MCOp;
595
2
      TmpInst.setOpcode(Mips::JR_HB);
596
2
      // Operand: rs
597
2
      lowerOperand(MI->getOperand(0), MCOp);
598
2
      TmpInst.addOperand(MCOp);
599
2
      EmitToStreamer(OutStreamer, TmpInst);
600
2
      break;
601
125k
    }
602
125k
    case Mips::PseudoIndirectHazardBranch64: {
603
2
      MCInst TmpInst;
604
2
      MCOperand MCOp;
605
2
      TmpInst.setOpcode(Mips::JR_HB64);
606
2
      // Operand: rs
607
2
      lowerOperand(MI->getOperand(0), MCOp);
608
2
      TmpInst.addOperand(MCOp);
609
2
      EmitToStreamer(OutStreamer, TmpInst);
610
2
      break;
611
125k
    }
612
125k
    case Mips::PseudoIndrectHazardBranch64R6: {
613
2
      MCInst TmpInst;
614
2
      MCOperand MCOp;
615
2
      TmpInst.setOpcode(Mips::JR_HB64_R6);
616
2
      // Operand: rs
617
2
      lowerOperand(MI->getOperand(0), MCOp);
618
2
      TmpInst.addOperand(MCOp);
619
2
      EmitToStreamer(OutStreamer, TmpInst);
620
2
      break;
621
125k
    }
622
125k
    case Mips::PseudoIndrectHazardBranchR6: {
623
2
      MCInst TmpInst;
624
2
      MCOperand MCOp;
625
2
      TmpInst.setOpcode(Mips::JR_HB_R6);
626
2
      // Operand: rs
627
2
      lowerOperand(MI->getOperand(0), MCOp);
628
2
      TmpInst.addOperand(MCOp);
629
2
      EmitToStreamer(OutStreamer, TmpInst);
630
2
      break;
631
125k
    }
632
125k
    case Mips::PseudoMADD: {
633
4
      MCInst TmpInst;
634
4
      MCOperand MCOp;
635
4
      TmpInst.setOpcode(Mips::MADD);
636
4
      // Operand: rs
637
4
      lowerOperand(MI->getOperand(1), MCOp);
638
4
      TmpInst.addOperand(MCOp);
639
4
      // Operand: rt
640
4
      lowerOperand(MI->getOperand(2), MCOp);
641
4
      TmpInst.addOperand(MCOp);
642
4
      EmitToStreamer(OutStreamer, TmpInst);
643
4
      break;
644
125k
    }
645
125k
    case Mips::PseudoMADDU: {
646
2
      MCInst TmpInst;
647
2
      MCOperand MCOp;
648
2
      TmpInst.setOpcode(Mips::MADDU);
649
2
      // Operand: rs
650
2
      lowerOperand(MI->getOperand(1), MCOp);
651
2
      TmpInst.addOperand(MCOp);
652
2
      // Operand: rt
653
2
      lowerOperand(MI->getOperand(2), MCOp);
654
2
      TmpInst.addOperand(MCOp);
655
2
      EmitToStreamer(OutStreamer, TmpInst);
656
2
      break;
657
125k
    }
658
125k
    case Mips::PseudoMADDU_MM: {
659
0
      MCInst TmpInst;
660
0
      MCOperand MCOp;
661
0
      TmpInst.setOpcode(Mips::MADDU);
662
0
      // Operand: rs
663
0
      lowerOperand(MI->getOperand(1), MCOp);
664
0
      TmpInst.addOperand(MCOp);
665
0
      // Operand: rt
666
0
      lowerOperand(MI->getOperand(2), MCOp);
667
0
      TmpInst.addOperand(MCOp);
668
0
      EmitToStreamer(OutStreamer, TmpInst);
669
0
      break;
670
125k
    }
671
125k
    case Mips::PseudoMADD_MM: {
672
0
      MCInst TmpInst;
673
0
      MCOperand MCOp;
674
0
      TmpInst.setOpcode(Mips::MADD);
675
0
      // Operand: rs
676
0
      lowerOperand(MI->getOperand(1), MCOp);
677
0
      TmpInst.addOperand(MCOp);
678
0
      // Operand: rt
679
0
      lowerOperand(MI->getOperand(2), MCOp);
680
0
      TmpInst.addOperand(MCOp);
681
0
      EmitToStreamer(OutStreamer, TmpInst);
682
0
      break;
683
125k
    }
684
125k
    case Mips::PseudoMSUB: {
685
4
      MCInst TmpInst;
686
4
      MCOperand MCOp;
687
4
      TmpInst.setOpcode(Mips::MSUB);
688
4
      // Operand: rs
689
4
      lowerOperand(MI->getOperand(1), MCOp);
690
4
      TmpInst.addOperand(MCOp);
691
4
      // Operand: rt
692
4
      lowerOperand(MI->getOperand(2), MCOp);
693
4
      TmpInst.addOperand(MCOp);
694
4
      EmitToStreamer(OutStreamer, TmpInst);
695
4
      break;
696
125k
    }
697
125k
    case Mips::PseudoMSUBU: {
698
2
      MCInst TmpInst;
699
2
      MCOperand MCOp;
700
2
      TmpInst.setOpcode(Mips::MSUBU);
701
2
      // Operand: rs
702
2
      lowerOperand(MI->getOperand(1), MCOp);
703
2
      TmpInst.addOperand(MCOp);
704
2
      // Operand: rt
705
2
      lowerOperand(MI->getOperand(2), MCOp);
706
2
      TmpInst.addOperand(MCOp);
707
2
      EmitToStreamer(OutStreamer, TmpInst);
708
2
      break;
709
125k
    }
710
125k
    case Mips::PseudoMSUBU_MM: {
711
0
      MCInst TmpInst;
712
0
      MCOperand MCOp;
713
0
      TmpInst.setOpcode(Mips::MSUBU);
714
0
      // Operand: rs
715
0
      lowerOperand(MI->getOperand(1), MCOp);
716
0
      TmpInst.addOperand(MCOp);
717
0
      // Operand: rt
718
0
      lowerOperand(MI->getOperand(2), MCOp);
719
0
      TmpInst.addOperand(MCOp);
720
0
      EmitToStreamer(OutStreamer, TmpInst);
721
0
      break;
722
125k
    }
723
125k
    case Mips::PseudoMSUB_MM: {
724
0
      MCInst TmpInst;
725
0
      MCOperand MCOp;
726
0
      TmpInst.setOpcode(Mips::MSUB);
727
0
      // Operand: rs
728
0
      lowerOperand(MI->getOperand(1), MCOp);
729
0
      TmpInst.addOperand(MCOp);
730
0
      // Operand: rt
731
0
      lowerOperand(MI->getOperand(2), MCOp);
732
0
      TmpInst.addOperand(MCOp);
733
0
      EmitToStreamer(OutStreamer, TmpInst);
734
0
      break;
735
125k
    }
736
125k
    case Mips::PseudoMULT: {
737
11
      MCInst TmpInst;
738
11
      MCOperand MCOp;
739
11
      TmpInst.setOpcode(Mips::MULT);
740
11
      // Operand: rs
741
11
      lowerOperand(MI->getOperand(1), MCOp);
742
11
      TmpInst.addOperand(MCOp);
743
11
      // Operand: rt
744
11
      lowerOperand(MI->getOperand(2), MCOp);
745
11
      TmpInst.addOperand(MCOp);
746
11
      EmitToStreamer(OutStreamer, TmpInst);
747
11
      break;
748
125k
    }
749
125k
    case Mips::PseudoMULT_MM: {
750
0
      MCInst TmpInst;
751
0
      MCOperand MCOp;
752
0
      TmpInst.setOpcode(Mips::MULT);
753
0
      // Operand: rs
754
0
      lowerOperand(MI->getOperand(1), MCOp);
755
0
      TmpInst.addOperand(MCOp);
756
0
      // Operand: rt
757
0
      lowerOperand(MI->getOperand(2), MCOp);
758
0
      TmpInst.addOperand(MCOp);
759
0
      EmitToStreamer(OutStreamer, TmpInst);
760
0
      break;
761
125k
    }
762
125k
    case Mips::PseudoMULTu: {
763
8
      MCInst TmpInst;
764
8
      MCOperand MCOp;
765
8
      TmpInst.setOpcode(Mips::MULTu);
766
8
      // Operand: rs
767
8
      lowerOperand(MI->getOperand(1), MCOp);
768
8
      TmpInst.addOperand(MCOp);
769
8
      // Operand: rt
770
8
      lowerOperand(MI->getOperand(2), MCOp);
771
8
      TmpInst.addOperand(MCOp);
772
8
      EmitToStreamer(OutStreamer, TmpInst);
773
8
      break;
774
125k
    }
775
125k
    case Mips::PseudoMULTu_MM: {
776
1
      MCInst TmpInst;
777
1
      MCOperand MCOp;
778
1
      TmpInst.setOpcode(Mips::MULTu);
779
1
      // Operand: rs
780
1
      lowerOperand(MI->getOperand(1), MCOp);
781
1
      TmpInst.addOperand(MCOp);
782
1
      // Operand: rt
783
1
      lowerOperand(MI->getOperand(2), MCOp);
784
1
      TmpInst.addOperand(MCOp);
785
1
      EmitToStreamer(OutStreamer, TmpInst);
786
1
      break;
787
125k
    }
788
125k
    case Mips::PseudoPICK_PH: {
789
14
      MCInst TmpInst;
790
14
      MCOperand MCOp;
791
14
      TmpInst.setOpcode(Mips::PICK_PH);
792
14
      // Operand: rd
793
14
      lowerOperand(MI->getOperand(0), MCOp);
794
14
      TmpInst.addOperand(MCOp);
795
14
      // Operand: rs
796
14
      lowerOperand(MI->getOperand(2), MCOp);
797
14
      TmpInst.addOperand(MCOp);
798
14
      // Operand: rt
799
14
      lowerOperand(MI->getOperand(3), MCOp);
800
14
      TmpInst.addOperand(MCOp);
801
14
      EmitToStreamer(OutStreamer, TmpInst);
802
14
      break;
803
125k
    }
804
125k
    case Mips::PseudoPICK_QB: {
805
12
      MCInst TmpInst;
806
12
      MCOperand MCOp;
807
12
      TmpInst.setOpcode(Mips::PICK_QB);
808
12
      // Operand: rd
809
12
      lowerOperand(MI->getOperand(0), MCOp);
810
12
      TmpInst.addOperand(MCOp);
811
12
      // Operand: rs
812
12
      lowerOperand(MI->getOperand(2), MCOp);
813
12
      TmpInst.addOperand(MCOp);
814
12
      // Operand: rt
815
12
      lowerOperand(MI->getOperand(3), MCOp);
816
12
      TmpInst.addOperand(MCOp);
817
12
      EmitToStreamer(OutStreamer, TmpInst);
818
12
      break;
819
125k
    }
820
125k
    case Mips::PseudoSDIV: {
821
124
      MCInst TmpInst;
822
124
      MCOperand MCOp;
823
124
      TmpInst.setOpcode(Mips::SDIV);
824
124
      // Operand: rs
825
124
      lowerOperand(MI->getOperand(1), MCOp);
826
124
      TmpInst.addOperand(MCOp);
827
124
      // Operand: rt
828
124
      lowerOperand(MI->getOperand(2), MCOp);
829
124
      TmpInst.addOperand(MCOp);
830
124
      EmitToStreamer(OutStreamer, TmpInst);
831
124
      break;
832
125k
    }
833
125k
    case Mips::PseudoUDIV: {
834
122
      MCInst TmpInst;
835
122
      MCOperand MCOp;
836
122
      TmpInst.setOpcode(Mips::UDIV);
837
122
      // Operand: rs
838
122
      lowerOperand(MI->getOperand(1), MCOp);
839
122
      TmpInst.addOperand(MCOp);
840
122
      // Operand: rt
841
122
      lowerOperand(MI->getOperand(2), MCOp);
842
122
      TmpInst.addOperand(MCOp);
843
122
      EmitToStreamer(OutStreamer, TmpInst);
844
122
      break;
845
125k
    }
846
125k
    case Mips::SDIV_MM_Pseudo: {
847
8
      MCInst TmpInst;
848
8
      MCOperand MCOp;
849
8
      TmpInst.setOpcode(Mips::SDIV_MM);
850
8
      // Operand: rs
851
8
      lowerOperand(MI->getOperand(1), MCOp);
852
8
      TmpInst.addOperand(MCOp);
853
8
      // Operand: rt
854
8
      lowerOperand(MI->getOperand(2), MCOp);
855
8
      TmpInst.addOperand(MCOp);
856
8
      EmitToStreamer(OutStreamer, TmpInst);
857
8
      break;
858
125k
    }
859
125k
    case Mips::TAILCALL: {
860
13
      MCInst TmpInst;
861
13
      MCOperand MCOp;
862
13
      TmpInst.setOpcode(Mips::J);
863
13
      // Operand: target
864
13
      lowerOperand(MI->getOperand(0), MCOp);
865
13
      TmpInst.addOperand(MCOp);
866
13
      EmitToStreamer(OutStreamer, TmpInst);
867
13
      break;
868
125k
    }
869
125k
    case Mips::TAILCALL64R6REG: {
870
1
      MCInst TmpInst;
871
1
      MCOperand MCOp;
872
1
      TmpInst.setOpcode(Mips::JALR64);
873
1
      // Operand: rd
874
1
      TmpInst.addOperand(MCOperand::createReg(Mips::ZERO_64));
875
1
      // Operand: rs
876
1
      lowerOperand(MI->getOperand(0), MCOp);
877
1
      TmpInst.addOperand(MCOp);
878
1
      EmitToStreamer(OutStreamer, TmpInst);
879
1
      break;
880
125k
    }
881
125k
    case Mips::TAILCALLHB64R6REG: {
882
2
      MCInst TmpInst;
883
2
      MCOperand MCOp;
884
2
      TmpInst.setOpcode(Mips::JR_HB64_R6);
885
2
      // Operand: rs
886
2
      lowerOperand(MI->getOperand(0), MCOp);
887
2
      TmpInst.addOperand(MCOp);
888
2
      EmitToStreamer(OutStreamer, TmpInst);
889
2
      break;
890
125k
    }
891
125k
    case Mips::TAILCALLHBR6REG: {
892
2
      MCInst TmpInst;
893
2
      MCOperand MCOp;
894
2
      TmpInst.setOpcode(Mips::JR_HB_R6);
895
2
      // Operand: rs
896
2
      lowerOperand(MI->getOperand(0), MCOp);
897
2
      TmpInst.addOperand(MCOp);
898
2
      EmitToStreamer(OutStreamer, TmpInst);
899
2
      break;
900
125k
    }
901
125k
    case Mips::TAILCALLR6REG: {
902
1
      MCInst TmpInst;
903
1
      MCOperand MCOp;
904
1
      TmpInst.setOpcode(Mips::JALR);
905
1
      // Operand: rd
906
1
      TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
907
1
      // Operand: rs
908
1
      lowerOperand(MI->getOperand(0), MCOp);
909
1
      TmpInst.addOperand(MCOp);
910
1
      EmitToStreamer(OutStreamer, TmpInst);
911
1
      break;
912
125k
    }
913
125k
    case Mips::TAILCALLREG: {
914
48
      MCInst TmpInst;
915
48
      MCOperand MCOp;
916
48
      TmpInst.setOpcode(Mips::JR);
917
48
      // Operand: rs
918
48
      lowerOperand(MI->getOperand(0), MCOp);
919
48
      TmpInst.addOperand(MCOp);
920
48
      EmitToStreamer(OutStreamer, TmpInst);
921
48
      break;
922
125k
    }
923
125k
    case Mips::TAILCALLREG64: {
924
49
      MCInst TmpInst;
925
49
      MCOperand MCOp;
926
49
      TmpInst.setOpcode(Mips::JR64);
927
49
      // Operand: rs
928
49
      lowerOperand(MI->getOperand(0), MCOp);
929
49
      TmpInst.addOperand(MCOp);
930
49
      EmitToStreamer(OutStreamer, TmpInst);
931
49
      break;
932
125k
    }
933
125k
    case Mips::TAILCALLREGHB: {
934
2
      MCInst TmpInst;
935
2
      MCOperand MCOp;
936
2
      TmpInst.setOpcode(Mips::JR_HB);
937
2
      // Operand: rs
938
2
      lowerOperand(MI->getOperand(0), MCOp);
939
2
      TmpInst.addOperand(MCOp);
940
2
      EmitToStreamer(OutStreamer, TmpInst);
941
2
      break;
942
125k
    }
943
125k
    case Mips::TAILCALLREGHB64: {
944
2
      MCInst TmpInst;
945
2
      MCOperand MCOp;
946
2
      TmpInst.setOpcode(Mips::JR_HB64);
947
2
      // Operand: rs
948
2
      lowerOperand(MI->getOperand(0), MCOp);
949
2
      TmpInst.addOperand(MCOp);
950
2
      EmitToStreamer(OutStreamer, TmpInst);
951
2
      break;
952
125k
    }
953
125k
    case Mips::TAILCALLREG_MM: {
954
4
      MCInst TmpInst;
955
4
      MCOperand MCOp;
956
4
      TmpInst.setOpcode(Mips::JRC16_MM);
957
4
      // Operand: rs
958
4
      lowerOperand(MI->getOperand(0), MCOp);
959
4
      TmpInst.addOperand(MCOp);
960
4
      EmitToStreamer(OutStreamer, TmpInst);
961
4
      break;
962
125k
    }
963
125k
    case Mips::TAILCALLREG_MMR6: {
964
3
      MCInst TmpInst;
965
3
      MCOperand MCOp;
966
3
      TmpInst.setOpcode(Mips::JRC16_MM);
967
3
      // Operand: rs
968
3
      lowerOperand(MI->getOperand(0), MCOp);
969
3
      TmpInst.addOperand(MCOp);
970
3
      EmitToStreamer(OutStreamer, TmpInst);
971
3
      break;
972
125k
    }
973
125k
    case Mips::TAILCALL_MM: {
974
4
      MCInst TmpInst;
975
4
      MCOperand MCOp;
976
4
      TmpInst.setOpcode(Mips::J_MM);
977
4
      // Operand: target
978
4
      lowerOperand(MI->getOperand(0), MCOp);
979
4
      TmpInst.addOperand(MCOp);
980
4
      EmitToStreamer(OutStreamer, TmpInst);
981
4
      break;
982
125k
    }
983
125k
    case Mips::TAILCALL_MMR6: {
984
3
      MCInst TmpInst;
985
3
      MCOperand MCOp;
986
3
      TmpInst.setOpcode(Mips::BC_MMR6);
987
3
      // Operand: offset
988
3
      lowerOperand(MI->getOperand(0), MCOp);
989
3
      TmpInst.addOperand(MCOp);
990
3
      EmitToStreamer(OutStreamer, TmpInst);
991
3
      break;
992
125k
    }
993
125k
    case Mips::TRAP: {
994
13
      MCInst TmpInst;
995
13
      MCOperand MCOp;
996
13
      TmpInst.setOpcode(Mips::BREAK);
997
13
      // Operand: code_1
998
13
      TmpInst.addOperand(MCOperand::createImm(0));
999
13
      // Operand: code_2
1000
13
      TmpInst.addOperand(MCOperand::createImm(0));
1001
13
      EmitToStreamer(OutStreamer, TmpInst);
1002
13
      break;
1003
125k
    }
1004
125k
    case Mips::TRAP_MM: {
1005
2
      MCInst TmpInst;
1006
2
      MCOperand MCOp;
1007
2
      TmpInst.setOpcode(Mips::BREAK_MM);
1008
2
      // Operand: code_1
1009
2
      TmpInst.addOperand(MCOperand::createImm(0));
1010
2
      // Operand: code_2
1011
2
      TmpInst.addOperand(MCOperand::createImm(0));
1012
2
      EmitToStreamer(OutStreamer, TmpInst);
1013
2
      break;
1014
125k
    }
1015
125k
    case Mips::UDIV_MM_Pseudo: {
1016
8
      MCInst TmpInst;
1017
8
      MCOperand MCOp;
1018
8
      TmpInst.setOpcode(Mips::UDIV_MM);
1019
8
      // Operand: rs
1020
8
      lowerOperand(MI->getOperand(1), MCOp);
1021
8
      TmpInst.addOperand(MCOp);
1022
8
      // Operand: rt
1023
8
      lowerOperand(MI->getOperand(2), MCOp);
1024
8
      TmpInst.addOperand(MCOp);
1025
8
      EmitToStreamer(OutStreamer, TmpInst);
1026
8
      break;
1027
125k
    }
1028
125k
    case Mips::XOR_V_D_PSEUDO: {
1029
12
      MCInst TmpInst;
1030
12
      MCOperand MCOp;
1031
12
      TmpInst.setOpcode(Mips::XOR_V);
1032
12
      // Operand: wd
1033
12
      lowerOperand(MI->getOperand(0), MCOp);
1034
12
      TmpInst.addOperand(MCOp);
1035
12
      // Operand: ws
1036
12
      lowerOperand(MI->getOperand(1), MCOp);
1037
12
      TmpInst.addOperand(MCOp);
1038
12
      // Operand: wt
1039
12
      lowerOperand(MI->getOperand(2), MCOp);
1040
12
      TmpInst.addOperand(MCOp);
1041
12
      EmitToStreamer(OutStreamer, TmpInst);
1042
12
      break;
1043
125k
    }
1044
125k
    case Mips::XOR_V_H_PSEUDO: {
1045
8
      MCInst TmpInst;
1046
8
      MCOperand MCOp;
1047
8
      TmpInst.setOpcode(Mips::XOR_V);
1048
8
      // Operand: wd
1049
8
      lowerOperand(MI->getOperand(0), MCOp);
1050
8
      TmpInst.addOperand(MCOp);
1051
8
      // Operand: ws
1052
8
      lowerOperand(MI->getOperand(1), MCOp);
1053
8
      TmpInst.addOperand(MCOp);
1054
8
      // Operand: wt
1055
8
      lowerOperand(MI->getOperand(2), MCOp);
1056
8
      TmpInst.addOperand(MCOp);
1057
8
      EmitToStreamer(OutStreamer, TmpInst);
1058
8
      break;
1059
125k
    }
1060
125k
    case Mips::XOR_V_W_PSEUDO: {
1061
8
      MCInst TmpInst;
1062
8
      MCOperand MCOp;
1063
8
      TmpInst.setOpcode(Mips::XOR_V);
1064
8
      // Operand: wd
1065
8
      lowerOperand(MI->getOperand(0), MCOp);
1066
8
      TmpInst.addOperand(MCOp);
1067
8
      // Operand: ws
1068
8
      lowerOperand(MI->getOperand(1), MCOp);
1069
8
      TmpInst.addOperand(MCOp);
1070
8
      // Operand: wt
1071
8
      lowerOperand(MI->getOperand(2), MCOp);
1072
8
      TmpInst.addOperand(MCOp);
1073
8
      EmitToStreamer(OutStreamer, TmpInst);
1074
8
      break;
1075
5.38k
    }
1076
5.38k
  }
1077
5.38k
  return true;
1078
5.38k
}
1079