Coverage Report

Created: 2018-07-12 09:57

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Mips/MipsGenMCPseudoLowering.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Pseudo-instruction MC lowering Source Fragment                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
bool MipsAsmPrinter::
10
emitPseudoExpansionLowering(MCStreamer &OutStreamer,
11
124k
                            const MachineInstr *MI) {
12
124k
  switch (MI->getOpcode()) {
13
124k
    
default: return false118k
;
14
124k
    case Mips::AND_V_D_PSEUDO: {
15
6
      MCInst TmpInst;
16
6
      MCOperand MCOp;
17
6
      TmpInst.setOpcode(Mips::AND_V);
18
6
      // Operand: wd
19
6
      lowerOperand(MI->getOperand(0), MCOp);
20
6
      TmpInst.addOperand(MCOp);
21
6
      // Operand: ws
22
6
      lowerOperand(MI->getOperand(1), MCOp);
23
6
      TmpInst.addOperand(MCOp);
24
6
      // Operand: wt
25
6
      lowerOperand(MI->getOperand(2), MCOp);
26
6
      TmpInst.addOperand(MCOp);
27
6
      EmitToStreamer(OutStreamer, TmpInst);
28
6
      break;
29
124k
    }
30
124k
    case Mips::AND_V_H_PSEUDO: {
31
6
      MCInst TmpInst;
32
6
      MCOperand MCOp;
33
6
      TmpInst.setOpcode(Mips::AND_V);
34
6
      // Operand: wd
35
6
      lowerOperand(MI->getOperand(0), MCOp);
36
6
      TmpInst.addOperand(MCOp);
37
6
      // Operand: ws
38
6
      lowerOperand(MI->getOperand(1), MCOp);
39
6
      TmpInst.addOperand(MCOp);
40
6
      // Operand: wt
41
6
      lowerOperand(MI->getOperand(2), MCOp);
42
6
      TmpInst.addOperand(MCOp);
43
6
      EmitToStreamer(OutStreamer, TmpInst);
44
6
      break;
45
124k
    }
46
124k
    case Mips::AND_V_W_PSEUDO: {
47
6
      MCInst TmpInst;
48
6
      MCOperand MCOp;
49
6
      TmpInst.setOpcode(Mips::AND_V);
50
6
      // Operand: wd
51
6
      lowerOperand(MI->getOperand(0), MCOp);
52
6
      TmpInst.addOperand(MCOp);
53
6
      // Operand: ws
54
6
      lowerOperand(MI->getOperand(1), MCOp);
55
6
      TmpInst.addOperand(MCOp);
56
6
      // Operand: wt
57
6
      lowerOperand(MI->getOperand(2), MCOp);
58
6
      TmpInst.addOperand(MCOp);
59
6
      EmitToStreamer(OutStreamer, TmpInst);
60
6
      break;
61
124k
    }
62
124k
    case Mips::B: {
63
56
      MCInst TmpInst;
64
56
      MCOperand MCOp;
65
56
      TmpInst.setOpcode(Mips::BEQ);
66
56
      // Operand: rs
67
56
      TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
68
56
      // Operand: rt
69
56
      TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
70
56
      // Operand: offset
71
56
      lowerOperand(MI->getOperand(0), MCOp);
72
56
      TmpInst.addOperand(MCOp);
73
56
      EmitToStreamer(OutStreamer, TmpInst);
74
56
      break;
75
124k
    }
76
124k
    case Mips::BAL_BR: {
77
10
      MCInst TmpInst;
78
10
      MCOperand MCOp;
79
10
      TmpInst.setOpcode(Mips::BGEZAL);
80
10
      // Operand: rs
81
10
      TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
82
10
      // Operand: offset
83
10
      lowerOperand(MI->getOperand(0), MCOp);
84
10
      TmpInst.addOperand(MCOp);
85
10
      EmitToStreamer(OutStreamer, TmpInst);
86
10
      break;
87
124k
    }
88
124k
    case Mips::BAL_BR_MM: {
89
1
      MCInst TmpInst;
90
1
      MCOperand MCOp;
91
1
      TmpInst.setOpcode(Mips::BGEZAL_MM);
92
1
      // Operand: rs
93
1
      TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
94
1
      // Operand: offset
95
1
      lowerOperand(MI->getOperand(0), MCOp);
96
1
      TmpInst.addOperand(MCOp);
97
1
      EmitToStreamer(OutStreamer, TmpInst);
98
1
      break;
99
124k
    }
100
124k
    case Mips::BSEL_D_PSEUDO: {
101
10
      MCInst TmpInst;
102
10
      MCOperand MCOp;
103
10
      TmpInst.setOpcode(Mips::BSEL_V);
104
10
      // Operand: wd
105
10
      lowerOperand(MI->getOperand(0), MCOp);
106
10
      TmpInst.addOperand(MCOp);
107
10
      // Operand: wd_in
108
10
      lowerOperand(MI->getOperand(1), MCOp);
109
10
      TmpInst.addOperand(MCOp);
110
10
      // Operand: ws
111
10
      lowerOperand(MI->getOperand(2), MCOp);
112
10
      TmpInst.addOperand(MCOp);
113
10
      // Operand: wt
114
10
      lowerOperand(MI->getOperand(3), MCOp);
115
10
      TmpInst.addOperand(MCOp);
116
10
      EmitToStreamer(OutStreamer, TmpInst);
117
10
      break;
118
124k
    }
119
124k
    case Mips::BSEL_FD_PSEUDO: {
120
4
      MCInst TmpInst;
121
4
      MCOperand MCOp;
122
4
      TmpInst.setOpcode(Mips::BSEL_V);
123
4
      // Operand: wd
124
4
      lowerOperand(MI->getOperand(0), MCOp);
125
4
      TmpInst.addOperand(MCOp);
126
4
      // Operand: wd_in
127
4
      lowerOperand(MI->getOperand(1), MCOp);
128
4
      TmpInst.addOperand(MCOp);
129
4
      // Operand: ws
130
4
      lowerOperand(MI->getOperand(2), MCOp);
131
4
      TmpInst.addOperand(MCOp);
132
4
      // Operand: wt
133
4
      lowerOperand(MI->getOperand(3), MCOp);
134
4
      TmpInst.addOperand(MCOp);
135
4
      EmitToStreamer(OutStreamer, TmpInst);
136
4
      break;
137
124k
    }
138
124k
    case Mips::BSEL_FW_PSEUDO: {
139
8
      MCInst TmpInst;
140
8
      MCOperand MCOp;
141
8
      TmpInst.setOpcode(Mips::BSEL_V);
142
8
      // Operand: wd
143
8
      lowerOperand(MI->getOperand(0), MCOp);
144
8
      TmpInst.addOperand(MCOp);
145
8
      // Operand: wd_in
146
8
      lowerOperand(MI->getOperand(1), MCOp);
147
8
      TmpInst.addOperand(MCOp);
148
8
      // Operand: ws
149
8
      lowerOperand(MI->getOperand(2), MCOp);
150
8
      TmpInst.addOperand(MCOp);
151
8
      // Operand: wt
152
8
      lowerOperand(MI->getOperand(3), MCOp);
153
8
      TmpInst.addOperand(MCOp);
154
8
      EmitToStreamer(OutStreamer, TmpInst);
155
8
      break;
156
124k
    }
157
124k
    case Mips::BSEL_H_PSEUDO: {
158
10
      MCInst TmpInst;
159
10
      MCOperand MCOp;
160
10
      TmpInst.setOpcode(Mips::BSEL_V);
161
10
      // Operand: wd
162
10
      lowerOperand(MI->getOperand(0), MCOp);
163
10
      TmpInst.addOperand(MCOp);
164
10
      // Operand: wd_in
165
10
      lowerOperand(MI->getOperand(1), MCOp);
166
10
      TmpInst.addOperand(MCOp);
167
10
      // Operand: ws
168
10
      lowerOperand(MI->getOperand(2), MCOp);
169
10
      TmpInst.addOperand(MCOp);
170
10
      // Operand: wt
171
10
      lowerOperand(MI->getOperand(3), MCOp);
172
10
      TmpInst.addOperand(MCOp);
173
10
      EmitToStreamer(OutStreamer, TmpInst);
174
10
      break;
175
124k
    }
176
124k
    case Mips::BSEL_W_PSEUDO: {
177
10
      MCInst TmpInst;
178
10
      MCOperand MCOp;
179
10
      TmpInst.setOpcode(Mips::BSEL_V);
180
10
      // Operand: wd
181
10
      lowerOperand(MI->getOperand(0), MCOp);
182
10
      TmpInst.addOperand(MCOp);
183
10
      // Operand: wd_in
184
10
      lowerOperand(MI->getOperand(1), MCOp);
185
10
      TmpInst.addOperand(MCOp);
186
10
      // Operand: ws
187
10
      lowerOperand(MI->getOperand(2), MCOp);
188
10
      TmpInst.addOperand(MCOp);
189
10
      // Operand: wt
190
10
      lowerOperand(MI->getOperand(3), MCOp);
191
10
      TmpInst.addOperand(MCOp);
192
10
      EmitToStreamer(OutStreamer, TmpInst);
193
10
      break;
194
124k
    }
195
124k
    case Mips::B_MM: {
196
1
      MCInst TmpInst;
197
1
      MCOperand MCOp;
198
1
      TmpInst.setOpcode(Mips::BEQ_MM);
199
1
      // Operand: rs
200
1
      TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
201
1
      // Operand: rt
202
1
      TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
203
1
      // Operand: offset
204
1
      lowerOperand(MI->getOperand(0), MCOp);
205
1
      TmpInst.addOperand(MCOp);
206
1
      EmitToStreamer(OutStreamer, TmpInst);
207
1
      break;
208
124k
    }
209
124k
    case Mips::FABS_D: {
210
2
      MCInst TmpInst;
211
2
      MCOperand MCOp;
212
2
      TmpInst.setOpcode(Mips::FMAX_A_D);
213
2
      // Operand: wd
214
2
      lowerOperand(MI->getOperand(0), MCOp);
215
2
      TmpInst.addOperand(MCOp);
216
2
      // Operand: ws
217
2
      lowerOperand(MI->getOperand(1), MCOp);
218
2
      TmpInst.addOperand(MCOp);
219
2
      // Operand: wt
220
2
      lowerOperand(MI->getOperand(1), MCOp);
221
2
      TmpInst.addOperand(MCOp);
222
2
      EmitToStreamer(OutStreamer, TmpInst);
223
2
      break;
224
124k
    }
225
124k
    case Mips::FABS_W: {
226
2
      MCInst TmpInst;
227
2
      MCOperand MCOp;
228
2
      TmpInst.setOpcode(Mips::FMAX_A_W);
229
2
      // Operand: wd
230
2
      lowerOperand(MI->getOperand(0), MCOp);
231
2
      TmpInst.addOperand(MCOp);
232
2
      // Operand: ws
233
2
      lowerOperand(MI->getOperand(1), MCOp);
234
2
      TmpInst.addOperand(MCOp);
235
2
      // Operand: wt
236
2
      lowerOperand(MI->getOperand(1), MCOp);
237
2
      TmpInst.addOperand(MCOp);
238
2
      EmitToStreamer(OutStreamer, TmpInst);
239
2
      break;
240
124k
    }
241
124k
    case Mips::JALR64Pseudo: {
242
450
      MCInst TmpInst;
243
450
      MCOperand MCOp;
244
450
      TmpInst.setOpcode(Mips::JALR);
245
450
      // Operand: rd
246
450
      TmpInst.addOperand(MCOperand::createReg(Mips::RA));
247
450
      // Operand: rs
248
450
      lowerOperand(MI->getOperand(0), MCOp);
249
450
      TmpInst.addOperand(MCOp);
250
450
      EmitToStreamer(OutStreamer, TmpInst);
251
450
      break;
252
124k
    }
253
124k
    case Mips::JALRHB64Pseudo: {
254
6
      MCInst TmpInst;
255
6
      MCOperand MCOp;
256
6
      TmpInst.setOpcode(Mips::JALR_HB64);
257
6
      // Operand: rd
258
6
      TmpInst.addOperand(MCOperand::createReg(Mips::RA_64));
259
6
      // Operand: rs
260
6
      lowerOperand(MI->getOperand(0), MCOp);
261
6
      TmpInst.addOperand(MCOp);
262
6
      EmitToStreamer(OutStreamer, TmpInst);
263
6
      break;
264
124k
    }
265
124k
    case Mips::JALRHBPseudo: {
266
8
      MCInst TmpInst;
267
8
      MCOperand MCOp;
268
8
      TmpInst.setOpcode(Mips::JALR_HB);
269
8
      // Operand: rd
270
8
      TmpInst.addOperand(MCOperand::createReg(Mips::RA));
271
8
      // Operand: rs
272
8
      lowerOperand(MI->getOperand(0), MCOp);
273
8
      TmpInst.addOperand(MCOp);
274
8
      EmitToStreamer(OutStreamer, TmpInst);
275
8
      break;
276
124k
    }
277
124k
    case Mips::JALRPseudo: {
278
501
      MCInst TmpInst;
279
501
      MCOperand MCOp;
280
501
      TmpInst.setOpcode(Mips::JALR);
281
501
      // Operand: rd
282
501
      TmpInst.addOperand(MCOperand::createReg(Mips::RA));
283
501
      // Operand: rs
284
501
      lowerOperand(MI->getOperand(0), MCOp);
285
501
      TmpInst.addOperand(MCOp);
286
501
      EmitToStreamer(OutStreamer, TmpInst);
287
501
      break;
288
124k
    }
289
124k
    case Mips::NOP: {
290
3.37k
      MCInst TmpInst;
291
3.37k
      MCOperand MCOp;
292
3.37k
      TmpInst.setOpcode(Mips::SLL);
293
3.37k
      // Operand: rd
294
3.37k
      TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
295
3.37k
      // Operand: rt
296
3.37k
      TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
297
3.37k
      // Operand: shamt
298
3.37k
      TmpInst.addOperand(MCOperand::createImm(0));
299
3.37k
      EmitToStreamer(OutStreamer, TmpInst);
300
3.37k
      break;
301
124k
    }
302
124k
    case Mips::NOR_V_D_PSEUDO: {
303
4
      MCInst TmpInst;
304
4
      MCOperand MCOp;
305
4
      TmpInst.setOpcode(Mips::NOR_V);
306
4
      // Operand: wd
307
4
      lowerOperand(MI->getOperand(0), MCOp);
308
4
      TmpInst.addOperand(MCOp);
309
4
      // Operand: ws
310
4
      lowerOperand(MI->getOperand(1), MCOp);
311
4
      TmpInst.addOperand(MCOp);
312
4
      // Operand: wt
313
4
      lowerOperand(MI->getOperand(2), MCOp);
314
4
      TmpInst.addOperand(MCOp);
315
4
      EmitToStreamer(OutStreamer, TmpInst);
316
4
      break;
317
124k
    }
318
124k
    case Mips::NOR_V_H_PSEUDO: {
319
4
      MCInst TmpInst;
320
4
      MCOperand MCOp;
321
4
      TmpInst.setOpcode(Mips::NOR_V);
322
4
      // Operand: wd
323
4
      lowerOperand(MI->getOperand(0), MCOp);
324
4
      TmpInst.addOperand(MCOp);
325
4
      // Operand: ws
326
4
      lowerOperand(MI->getOperand(1), MCOp);
327
4
      TmpInst.addOperand(MCOp);
328
4
      // Operand: wt
329
4
      lowerOperand(MI->getOperand(2), MCOp);
330
4
      TmpInst.addOperand(MCOp);
331
4
      EmitToStreamer(OutStreamer, TmpInst);
332
4
      break;
333
124k
    }
334
124k
    case Mips::NOR_V_W_PSEUDO: {
335
4
      MCInst TmpInst;
336
4
      MCOperand MCOp;
337
4
      TmpInst.setOpcode(Mips::NOR_V);
338
4
      // Operand: wd
339
4
      lowerOperand(MI->getOperand(0), MCOp);
340
4
      TmpInst.addOperand(MCOp);
341
4
      // Operand: ws
342
4
      lowerOperand(MI->getOperand(1), MCOp);
343
4
      TmpInst.addOperand(MCOp);
344
4
      // Operand: wt
345
4
      lowerOperand(MI->getOperand(2), MCOp);
346
4
      TmpInst.addOperand(MCOp);
347
4
      EmitToStreamer(OutStreamer, TmpInst);
348
4
      break;
349
124k
    }
350
124k
    case Mips::OR_V_D_PSEUDO: {
351
6
      MCInst TmpInst;
352
6
      MCOperand MCOp;
353
6
      TmpInst.setOpcode(Mips::OR_V);
354
6
      // Operand: wd
355
6
      lowerOperand(MI->getOperand(0), MCOp);
356
6
      TmpInst.addOperand(MCOp);
357
6
      // Operand: ws
358
6
      lowerOperand(MI->getOperand(1), MCOp);
359
6
      TmpInst.addOperand(MCOp);
360
6
      // Operand: wt
361
6
      lowerOperand(MI->getOperand(2), MCOp);
362
6
      TmpInst.addOperand(MCOp);
363
6
      EmitToStreamer(OutStreamer, TmpInst);
364
6
      break;
365
124k
    }
366
124k
    case Mips::OR_V_H_PSEUDO: {
367
6
      MCInst TmpInst;
368
6
      MCOperand MCOp;
369
6
      TmpInst.setOpcode(Mips::OR_V);
370
6
      // Operand: wd
371
6
      lowerOperand(MI->getOperand(0), MCOp);
372
6
      TmpInst.addOperand(MCOp);
373
6
      // Operand: ws
374
6
      lowerOperand(MI->getOperand(1), MCOp);
375
6
      TmpInst.addOperand(MCOp);
376
6
      // Operand: wt
377
6
      lowerOperand(MI->getOperand(2), MCOp);
378
6
      TmpInst.addOperand(MCOp);
379
6
      EmitToStreamer(OutStreamer, TmpInst);
380
6
      break;
381
124k
    }
382
124k
    case Mips::OR_V_W_PSEUDO: {
383
6
      MCInst TmpInst;
384
6
      MCOperand MCOp;
385
6
      TmpInst.setOpcode(Mips::OR_V);
386
6
      // Operand: wd
387
6
      lowerOperand(MI->getOperand(0), MCOp);
388
6
      TmpInst.addOperand(MCOp);
389
6
      // Operand: ws
390
6
      lowerOperand(MI->getOperand(1), MCOp);
391
6
      TmpInst.addOperand(MCOp);
392
6
      // Operand: wt
393
6
      lowerOperand(MI->getOperand(2), MCOp);
394
6
      TmpInst.addOperand(MCOp);
395
6
      EmitToStreamer(OutStreamer, TmpInst);
396
6
      break;
397
124k
    }
398
124k
    case Mips::PseudoCMPU_EQ_QB: {
399
4
      MCInst TmpInst;
400
4
      MCOperand MCOp;
401
4
      TmpInst.setOpcode(Mips::CMPU_EQ_QB);
402
4
      // Operand: rs
403
4
      lowerOperand(MI->getOperand(1), MCOp);
404
4
      TmpInst.addOperand(MCOp);
405
4
      // Operand: rt
406
4
      lowerOperand(MI->getOperand(2), MCOp);
407
4
      TmpInst.addOperand(MCOp);
408
4
      EmitToStreamer(OutStreamer, TmpInst);
409
4
      break;
410
124k
    }
411
124k
    case Mips::PseudoCMPU_LE_QB: {
412
4
      MCInst TmpInst;
413
4
      MCOperand MCOp;
414
4
      TmpInst.setOpcode(Mips::CMPU_LE_QB);
415
4
      // Operand: rs
416
4
      lowerOperand(MI->getOperand(1), MCOp);
417
4
      TmpInst.addOperand(MCOp);
418
4
      // Operand: rt
419
4
      lowerOperand(MI->getOperand(2), MCOp);
420
4
      TmpInst.addOperand(MCOp);
421
4
      EmitToStreamer(OutStreamer, TmpInst);
422
4
      break;
423
124k
    }
424
124k
    case Mips::PseudoCMPU_LT_QB: {
425
4
      MCInst TmpInst;
426
4
      MCOperand MCOp;
427
4
      TmpInst.setOpcode(Mips::CMPU_LT_QB);
428
4
      // Operand: rs
429
4
      lowerOperand(MI->getOperand(1), MCOp);
430
4
      TmpInst.addOperand(MCOp);
431
4
      // Operand: rt
432
4
      lowerOperand(MI->getOperand(2), MCOp);
433
4
      TmpInst.addOperand(MCOp);
434
4
      EmitToStreamer(OutStreamer, TmpInst);
435
4
      break;
436
124k
    }
437
124k
    case Mips::PseudoCMP_EQ_PH: {
438
4
      MCInst TmpInst;
439
4
      MCOperand MCOp;
440
4
      TmpInst.setOpcode(Mips::CMP_EQ_PH);
441
4
      // Operand: rs
442
4
      lowerOperand(MI->getOperand(1), MCOp);
443
4
      TmpInst.addOperand(MCOp);
444
4
      // Operand: rt
445
4
      lowerOperand(MI->getOperand(2), MCOp);
446
4
      TmpInst.addOperand(MCOp);
447
4
      EmitToStreamer(OutStreamer, TmpInst);
448
4
      break;
449
124k
    }
450
124k
    case Mips::PseudoCMP_LE_PH: {
451
4
      MCInst TmpInst;
452
4
      MCOperand MCOp;
453
4
      TmpInst.setOpcode(Mips::CMP_LE_PH);
454
4
      // Operand: rs
455
4
      lowerOperand(MI->getOperand(1), MCOp);
456
4
      TmpInst.addOperand(MCOp);
457
4
      // Operand: rt
458
4
      lowerOperand(MI->getOperand(2), MCOp);
459
4
      TmpInst.addOperand(MCOp);
460
4
      EmitToStreamer(OutStreamer, TmpInst);
461
4
      break;
462
124k
    }
463
124k
    case Mips::PseudoCMP_LT_PH: {
464
5
      MCInst TmpInst;
465
5
      MCOperand MCOp;
466
5
      TmpInst.setOpcode(Mips::CMP_LT_PH);
467
5
      // Operand: rs
468
5
      lowerOperand(MI->getOperand(1), MCOp);
469
5
      TmpInst.addOperand(MCOp);
470
5
      // Operand: rt
471
5
      lowerOperand(MI->getOperand(2), MCOp);
472
5
      TmpInst.addOperand(MCOp);
473
5
      EmitToStreamer(OutStreamer, TmpInst);
474
5
      break;
475
124k
    }
476
124k
    case Mips::PseudoDMULT: {
477
54
      MCInst TmpInst;
478
54
      MCOperand MCOp;
479
54
      TmpInst.setOpcode(Mips::DMULT);
480
54
      // Operand: rs
481
54
      lowerOperand(MI->getOperand(1), MCOp);
482
54
      TmpInst.addOperand(MCOp);
483
54
      // Operand: rt
484
54
      lowerOperand(MI->getOperand(2), MCOp);
485
54
      TmpInst.addOperand(MCOp);
486
54
      EmitToStreamer(OutStreamer, TmpInst);
487
54
      break;
488
124k
    }
489
124k
    case Mips::PseudoDMULTu: {
490
5
      MCInst TmpInst;
491
5
      MCOperand MCOp;
492
5
      TmpInst.setOpcode(Mips::DMULTu);
493
5
      // Operand: rs
494
5
      lowerOperand(MI->getOperand(1), MCOp);
495
5
      TmpInst.addOperand(MCOp);
496
5
      // Operand: rt
497
5
      lowerOperand(MI->getOperand(2), MCOp);
498
5
      TmpInst.addOperand(MCOp);
499
5
      EmitToStreamer(OutStreamer, TmpInst);
500
5
      break;
501
124k
    }
502
124k
    case Mips::PseudoDSDIV: {
503
36
      MCInst TmpInst;
504
36
      MCOperand MCOp;
505
36
      TmpInst.setOpcode(Mips::DSDIV);
506
36
      // Operand: rs
507
36
      lowerOperand(MI->getOperand(1), MCOp);
508
36
      TmpInst.addOperand(MCOp);
509
36
      // Operand: rt
510
36
      lowerOperand(MI->getOperand(2), MCOp);
511
36
      TmpInst.addOperand(MCOp);
512
36
      EmitToStreamer(OutStreamer, TmpInst);
513
36
      break;
514
124k
    }
515
124k
    case Mips::PseudoDUDIV: {
516
36
      MCInst TmpInst;
517
36
      MCOperand MCOp;
518
36
      TmpInst.setOpcode(Mips::DUDIV);
519
36
      // Operand: rs
520
36
      lowerOperand(MI->getOperand(1), MCOp);
521
36
      TmpInst.addOperand(MCOp);
522
36
      // Operand: rt
523
36
      lowerOperand(MI->getOperand(2), MCOp);
524
36
      TmpInst.addOperand(MCOp);
525
36
      EmitToStreamer(OutStreamer, TmpInst);
526
36
      break;
527
124k
    }
528
124k
    case Mips::PseudoIndirectBranch: {
529
16
      MCInst TmpInst;
530
16
      MCOperand MCOp;
531
16
      TmpInst.setOpcode(Mips::JR);
532
16
      // Operand: rs
533
16
      lowerOperand(MI->getOperand(0), MCOp);
534
16
      TmpInst.addOperand(MCOp);
535
16
      EmitToStreamer(OutStreamer, TmpInst);
536
16
      break;
537
124k
    }
538
124k
    case Mips::PseudoIndirectBranch64: {
539
13
      MCInst TmpInst;
540
13
      MCOperand MCOp;
541
13
      TmpInst.setOpcode(Mips::JR64);
542
13
      // Operand: rs
543
13
      lowerOperand(MI->getOperand(0), MCOp);
544
13
      TmpInst.addOperand(MCOp);
545
13
      EmitToStreamer(OutStreamer, TmpInst);
546
13
      break;
547
124k
    }
548
124k
    case Mips::PseudoIndirectBranch64R6: {
549
0
      MCInst TmpInst;
550
0
      MCOperand MCOp;
551
0
      TmpInst.setOpcode(Mips::JALR64);
552
0
      // Operand: rd
553
0
      TmpInst.addOperand(MCOperand::createReg(Mips::ZERO_64));
554
0
      // Operand: rs
555
0
      lowerOperand(MI->getOperand(0), MCOp);
556
0
      TmpInst.addOperand(MCOp);
557
0
      EmitToStreamer(OutStreamer, TmpInst);
558
0
      break;
559
124k
    }
560
124k
    case Mips::PseudoIndirectBranchR6: {
561
0
      MCInst TmpInst;
562
0
      MCOperand MCOp;
563
0
      TmpInst.setOpcode(Mips::JALR);
564
0
      // Operand: rd
565
0
      TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
566
0
      // Operand: rs
567
0
      lowerOperand(MI->getOperand(0), MCOp);
568
0
      TmpInst.addOperand(MCOp);
569
0
      EmitToStreamer(OutStreamer, TmpInst);
570
0
      break;
571
124k
    }
572
124k
    case Mips::PseudoIndirectBranch_MM: {
573
1
      MCInst TmpInst;
574
1
      MCOperand MCOp;
575
1
      TmpInst.setOpcode(Mips::JR_MM);
576
1
      // Operand: rs
577
1
      lowerOperand(MI->getOperand(0), MCOp);
578
1
      TmpInst.addOperand(MCOp);
579
1
      EmitToStreamer(OutStreamer, TmpInst);
580
1
      break;
581
124k
    }
582
124k
    case Mips::PseudoIndirectBranch_MMR6: {
583
0
      MCInst TmpInst;
584
0
      MCOperand MCOp;
585
0
      TmpInst.setOpcode(Mips::JRC16_MMR6);
586
0
      // Operand: rs
587
0
      lowerOperand(MI->getOperand(0), MCOp);
588
0
      TmpInst.addOperand(MCOp);
589
0
      EmitToStreamer(OutStreamer, TmpInst);
590
0
      break;
591
124k
    }
592
124k
    case Mips::PseudoIndirectHazardBranch: {
593
2
      MCInst TmpInst;
594
2
      MCOperand MCOp;
595
2
      TmpInst.setOpcode(Mips::JR_HB);
596
2
      // Operand: rs
597
2
      lowerOperand(MI->getOperand(0), MCOp);
598
2
      TmpInst.addOperand(MCOp);
599
2
      EmitToStreamer(OutStreamer, TmpInst);
600
2
      break;
601
124k
    }
602
124k
    case Mips::PseudoIndirectHazardBranch64: {
603
2
      MCInst TmpInst;
604
2
      MCOperand MCOp;
605
2
      TmpInst.setOpcode(Mips::JR_HB64);
606
2
      // Operand: rs
607
2
      lowerOperand(MI->getOperand(0), MCOp);
608
2
      TmpInst.addOperand(MCOp);
609
2
      EmitToStreamer(OutStreamer, TmpInst);
610
2
      break;
611
124k
    }
612
124k
    case Mips::PseudoIndrectHazardBranch64R6: {
613
2
      MCInst TmpInst;
614
2
      MCOperand MCOp;
615
2
      TmpInst.setOpcode(Mips::JR_HB64_R6);
616
2
      // Operand: rs
617
2
      lowerOperand(MI->getOperand(0), MCOp);
618
2
      TmpInst.addOperand(MCOp);
619
2
      EmitToStreamer(OutStreamer, TmpInst);
620
2
      break;
621
124k
    }
622
124k
    case Mips::PseudoIndrectHazardBranchR6: {
623
2
      MCInst TmpInst;
624
2
      MCOperand MCOp;
625
2
      TmpInst.setOpcode(Mips::JR_HB_R6);
626
2
      // Operand: rs
627
2
      lowerOperand(MI->getOperand(0), MCOp);
628
2
      TmpInst.addOperand(MCOp);
629
2
      EmitToStreamer(OutStreamer, TmpInst);
630
2
      break;
631
124k
    }
632
124k
    case Mips::PseudoMADD: {
633
4
      MCInst TmpInst;
634
4
      MCOperand MCOp;
635
4
      TmpInst.setOpcode(Mips::MADD);
636
4
      // Operand: rs
637
4
      lowerOperand(MI->getOperand(1), MCOp);
638
4
      TmpInst.addOperand(MCOp);
639
4
      // Operand: rt
640
4
      lowerOperand(MI->getOperand(2), MCOp);
641
4
      TmpInst.addOperand(MCOp);
642
4
      EmitToStreamer(OutStreamer, TmpInst);
643
4
      break;
644
124k
    }
645
124k
    case Mips::PseudoMADDU: {
646
2
      MCInst TmpInst;
647
2
      MCOperand MCOp;
648
2
      TmpInst.setOpcode(Mips::MADDU);
649
2
      // Operand: rs
650
2
      lowerOperand(MI->getOperand(1), MCOp);
651
2
      TmpInst.addOperand(MCOp);
652
2
      // Operand: rt
653
2
      lowerOperand(MI->getOperand(2), MCOp);
654
2
      TmpInst.addOperand(MCOp);
655
2
      EmitToStreamer(OutStreamer, TmpInst);
656
2
      break;
657
124k
    }
658
124k
    case Mips::PseudoMSUB: {
659
4
      MCInst TmpInst;
660
4
      MCOperand MCOp;
661
4
      TmpInst.setOpcode(Mips::MSUB);
662
4
      // Operand: rs
663
4
      lowerOperand(MI->getOperand(1), MCOp);
664
4
      TmpInst.addOperand(MCOp);
665
4
      // Operand: rt
666
4
      lowerOperand(MI->getOperand(2), MCOp);
667
4
      TmpInst.addOperand(MCOp);
668
4
      EmitToStreamer(OutStreamer, TmpInst);
669
4
      break;
670
124k
    }
671
124k
    case Mips::PseudoMSUBU: {
672
2
      MCInst TmpInst;
673
2
      MCOperand MCOp;
674
2
      TmpInst.setOpcode(Mips::MSUBU);
675
2
      // Operand: rs
676
2
      lowerOperand(MI->getOperand(1), MCOp);
677
2
      TmpInst.addOperand(MCOp);
678
2
      // Operand: rt
679
2
      lowerOperand(MI->getOperand(2), MCOp);
680
2
      TmpInst.addOperand(MCOp);
681
2
      EmitToStreamer(OutStreamer, TmpInst);
682
2
      break;
683
124k
    }
684
124k
    case Mips::PseudoMULT: {
685
12
      MCInst TmpInst;
686
12
      MCOperand MCOp;
687
12
      TmpInst.setOpcode(Mips::MULT);
688
12
      // Operand: rs
689
12
      lowerOperand(MI->getOperand(1), MCOp);
690
12
      TmpInst.addOperand(MCOp);
691
12
      // Operand: rt
692
12
      lowerOperand(MI->getOperand(2), MCOp);
693
12
      TmpInst.addOperand(MCOp);
694
12
      EmitToStreamer(OutStreamer, TmpInst);
695
12
      break;
696
124k
    }
697
124k
    case Mips::PseudoMULTu: {
698
9
      MCInst TmpInst;
699
9
      MCOperand MCOp;
700
9
      TmpInst.setOpcode(Mips::MULTu);
701
9
      // Operand: rs
702
9
      lowerOperand(MI->getOperand(1), MCOp);
703
9
      TmpInst.addOperand(MCOp);
704
9
      // Operand: rt
705
9
      lowerOperand(MI->getOperand(2), MCOp);
706
9
      TmpInst.addOperand(MCOp);
707
9
      EmitToStreamer(OutStreamer, TmpInst);
708
9
      break;
709
124k
    }
710
124k
    case Mips::PseudoPICK_PH: {
711
14
      MCInst TmpInst;
712
14
      MCOperand MCOp;
713
14
      TmpInst.setOpcode(Mips::PICK_PH);
714
14
      // Operand: rd
715
14
      lowerOperand(MI->getOperand(0), MCOp);
716
14
      TmpInst.addOperand(MCOp);
717
14
      // Operand: rs
718
14
      lowerOperand(MI->getOperand(2), MCOp);
719
14
      TmpInst.addOperand(MCOp);
720
14
      // Operand: rt
721
14
      lowerOperand(MI->getOperand(3), MCOp);
722
14
      TmpInst.addOperand(MCOp);
723
14
      EmitToStreamer(OutStreamer, TmpInst);
724
14
      break;
725
124k
    }
726
124k
    case Mips::PseudoPICK_QB: {
727
12
      MCInst TmpInst;
728
12
      MCOperand MCOp;
729
12
      TmpInst.setOpcode(Mips::PICK_QB);
730
12
      // Operand: rd
731
12
      lowerOperand(MI->getOperand(0), MCOp);
732
12
      TmpInst.addOperand(MCOp);
733
12
      // Operand: rs
734
12
      lowerOperand(MI->getOperand(2), MCOp);
735
12
      TmpInst.addOperand(MCOp);
736
12
      // Operand: rt
737
12
      lowerOperand(MI->getOperand(3), MCOp);
738
12
      TmpInst.addOperand(MCOp);
739
12
      EmitToStreamer(OutStreamer, TmpInst);
740
12
      break;
741
124k
    }
742
124k
    case Mips::PseudoSDIV: {
743
124
      MCInst TmpInst;
744
124
      MCOperand MCOp;
745
124
      TmpInst.setOpcode(Mips::SDIV);
746
124
      // Operand: rs
747
124
      lowerOperand(MI->getOperand(1), MCOp);
748
124
      TmpInst.addOperand(MCOp);
749
124
      // Operand: rt
750
124
      lowerOperand(MI->getOperand(2), MCOp);
751
124
      TmpInst.addOperand(MCOp);
752
124
      EmitToStreamer(OutStreamer, TmpInst);
753
124
      break;
754
124k
    }
755
124k
    case Mips::PseudoUDIV: {
756
122
      MCInst TmpInst;
757
122
      MCOperand MCOp;
758
122
      TmpInst.setOpcode(Mips::UDIV);
759
122
      // Operand: rs
760
122
      lowerOperand(MI->getOperand(1), MCOp);
761
122
      TmpInst.addOperand(MCOp);
762
122
      // Operand: rt
763
122
      lowerOperand(MI->getOperand(2), MCOp);
764
122
      TmpInst.addOperand(MCOp);
765
122
      EmitToStreamer(OutStreamer, TmpInst);
766
122
      break;
767
124k
    }
768
124k
    case Mips::SDIV_MM_Pseudo: {
769
8
      MCInst TmpInst;
770
8
      MCOperand MCOp;
771
8
      TmpInst.setOpcode(Mips::SDIV_MM);
772
8
      // Operand: rs
773
8
      lowerOperand(MI->getOperand(1), MCOp);
774
8
      TmpInst.addOperand(MCOp);
775
8
      // Operand: rt
776
8
      lowerOperand(MI->getOperand(2), MCOp);
777
8
      TmpInst.addOperand(MCOp);
778
8
      EmitToStreamer(OutStreamer, TmpInst);
779
8
      break;
780
124k
    }
781
124k
    case Mips::TAILCALL: {
782
13
      MCInst TmpInst;
783
13
      MCOperand MCOp;
784
13
      TmpInst.setOpcode(Mips::J);
785
13
      // Operand: target
786
13
      lowerOperand(MI->getOperand(0), MCOp);
787
13
      TmpInst.addOperand(MCOp);
788
13
      EmitToStreamer(OutStreamer, TmpInst);
789
13
      break;
790
124k
    }
791
124k
    case Mips::TAILCALL64R6REG: {
792
1
      MCInst TmpInst;
793
1
      MCOperand MCOp;
794
1
      TmpInst.setOpcode(Mips::JALR64);
795
1
      // Operand: rd
796
1
      TmpInst.addOperand(MCOperand::createReg(Mips::ZERO_64));
797
1
      // Operand: rs
798
1
      lowerOperand(MI->getOperand(0), MCOp);
799
1
      TmpInst.addOperand(MCOp);
800
1
      EmitToStreamer(OutStreamer, TmpInst);
801
1
      break;
802
124k
    }
803
124k
    case Mips::TAILCALLHB64R6REG: {
804
2
      MCInst TmpInst;
805
2
      MCOperand MCOp;
806
2
      TmpInst.setOpcode(Mips::JR_HB64_R6);
807
2
      // Operand: rs
808
2
      lowerOperand(MI->getOperand(0), MCOp);
809
2
      TmpInst.addOperand(MCOp);
810
2
      EmitToStreamer(OutStreamer, TmpInst);
811
2
      break;
812
124k
    }
813
124k
    case Mips::TAILCALLHBR6REG: {
814
2
      MCInst TmpInst;
815
2
      MCOperand MCOp;
816
2
      TmpInst.setOpcode(Mips::JR_HB_R6);
817
2
      // Operand: rs
818
2
      lowerOperand(MI->getOperand(0), MCOp);
819
2
      TmpInst.addOperand(MCOp);
820
2
      EmitToStreamer(OutStreamer, TmpInst);
821
2
      break;
822
124k
    }
823
124k
    case Mips::TAILCALLR6REG: {
824
1
      MCInst TmpInst;
825
1
      MCOperand MCOp;
826
1
      TmpInst.setOpcode(Mips::JALR);
827
1
      // Operand: rd
828
1
      TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
829
1
      // Operand: rs
830
1
      lowerOperand(MI->getOperand(0), MCOp);
831
1
      TmpInst.addOperand(MCOp);
832
1
      EmitToStreamer(OutStreamer, TmpInst);
833
1
      break;
834
124k
    }
835
124k
    case Mips::TAILCALLREG: {
836
48
      MCInst TmpInst;
837
48
      MCOperand MCOp;
838
48
      TmpInst.setOpcode(Mips::JR);
839
48
      // Operand: rs
840
48
      lowerOperand(MI->getOperand(0), MCOp);
841
48
      TmpInst.addOperand(MCOp);
842
48
      EmitToStreamer(OutStreamer, TmpInst);
843
48
      break;
844
124k
    }
845
124k
    case Mips::TAILCALLREG64: {
846
49
      MCInst TmpInst;
847
49
      MCOperand MCOp;
848
49
      TmpInst.setOpcode(Mips::JR64);
849
49
      // Operand: rs
850
49
      lowerOperand(MI->getOperand(0), MCOp);
851
49
      TmpInst.addOperand(MCOp);
852
49
      EmitToStreamer(OutStreamer, TmpInst);
853
49
      break;
854
124k
    }
855
124k
    case Mips::TAILCALLREGHB: {
856
2
      MCInst TmpInst;
857
2
      MCOperand MCOp;
858
2
      TmpInst.setOpcode(Mips::JR_HB);
859
2
      // Operand: rs
860
2
      lowerOperand(MI->getOperand(0), MCOp);
861
2
      TmpInst.addOperand(MCOp);
862
2
      EmitToStreamer(OutStreamer, TmpInst);
863
2
      break;
864
124k
    }
865
124k
    case Mips::TAILCALLREGHB64: {
866
2
      MCInst TmpInst;
867
2
      MCOperand MCOp;
868
2
      TmpInst.setOpcode(Mips::JR_HB64);
869
2
      // Operand: rs
870
2
      lowerOperand(MI->getOperand(0), MCOp);
871
2
      TmpInst.addOperand(MCOp);
872
2
      EmitToStreamer(OutStreamer, TmpInst);
873
2
      break;
874
124k
    }
875
124k
    case Mips::TAILCALLREG_MM: {
876
4
      MCInst TmpInst;
877
4
      MCOperand MCOp;
878
4
      TmpInst.setOpcode(Mips::JRC16_MM);
879
4
      // Operand: rs
880
4
      lowerOperand(MI->getOperand(0), MCOp);
881
4
      TmpInst.addOperand(MCOp);
882
4
      EmitToStreamer(OutStreamer, TmpInst);
883
4
      break;
884
124k
    }
885
124k
    case Mips::TAILCALLREG_MMR6: {
886
3
      MCInst TmpInst;
887
3
      MCOperand MCOp;
888
3
      TmpInst.setOpcode(Mips::JRC16_MM);
889
3
      // Operand: rs
890
3
      lowerOperand(MI->getOperand(0), MCOp);
891
3
      TmpInst.addOperand(MCOp);
892
3
      EmitToStreamer(OutStreamer, TmpInst);
893
3
      break;
894
124k
    }
895
124k
    case Mips::TAILCALL_MM: {
896
4
      MCInst TmpInst;
897
4
      MCOperand MCOp;
898
4
      TmpInst.setOpcode(Mips::J_MM);
899
4
      // Operand: target
900
4
      lowerOperand(MI->getOperand(0), MCOp);
901
4
      TmpInst.addOperand(MCOp);
902
4
      EmitToStreamer(OutStreamer, TmpInst);
903
4
      break;
904
124k
    }
905
124k
    case Mips::TAILCALL_MMR6: {
906
3
      MCInst TmpInst;
907
3
      MCOperand MCOp;
908
3
      TmpInst.setOpcode(Mips::BC_MMR6);
909
3
      // Operand: offset
910
3
      lowerOperand(MI->getOperand(0), MCOp);
911
3
      TmpInst.addOperand(MCOp);
912
3
      EmitToStreamer(OutStreamer, TmpInst);
913
3
      break;
914
124k
    }
915
124k
    case Mips::TRAP: {
916
3
      MCInst TmpInst;
917
3
      MCOperand MCOp;
918
3
      TmpInst.setOpcode(Mips::BREAK);
919
3
      // Operand: code_1
920
3
      TmpInst.addOperand(MCOperand::createImm(0));
921
3
      // Operand: code_2
922
3
      TmpInst.addOperand(MCOperand::createImm(0));
923
3
      EmitToStreamer(OutStreamer, TmpInst);
924
3
      break;
925
124k
    }
926
124k
    case Mips::TRAP_MM: {
927
2
      MCInst TmpInst;
928
2
      MCOperand MCOp;
929
2
      TmpInst.setOpcode(Mips::BREAK_MM);
930
2
      // Operand: code_1
931
2
      TmpInst.addOperand(MCOperand::createImm(0));
932
2
      // Operand: code_2
933
2
      TmpInst.addOperand(MCOperand::createImm(0));
934
2
      EmitToStreamer(OutStreamer, TmpInst);
935
2
      break;
936
124k
    }
937
124k
    case Mips::UDIV_MM_Pseudo: {
938
8
      MCInst TmpInst;
939
8
      MCOperand MCOp;
940
8
      TmpInst.setOpcode(Mips::UDIV_MM);
941
8
      // Operand: rs
942
8
      lowerOperand(MI->getOperand(1), MCOp);
943
8
      TmpInst.addOperand(MCOp);
944
8
      // Operand: rt
945
8
      lowerOperand(MI->getOperand(2), MCOp);
946
8
      TmpInst.addOperand(MCOp);
947
8
      EmitToStreamer(OutStreamer, TmpInst);
948
8
      break;
949
124k
    }
950
124k
    case Mips::XOR_V_D_PSEUDO: {
951
12
      MCInst TmpInst;
952
12
      MCOperand MCOp;
953
12
      TmpInst.setOpcode(Mips::XOR_V);
954
12
      // Operand: wd
955
12
      lowerOperand(MI->getOperand(0), MCOp);
956
12
      TmpInst.addOperand(MCOp);
957
12
      // Operand: ws
958
12
      lowerOperand(MI->getOperand(1), MCOp);
959
12
      TmpInst.addOperand(MCOp);
960
12
      // Operand: wt
961
12
      lowerOperand(MI->getOperand(2), MCOp);
962
12
      TmpInst.addOperand(MCOp);
963
12
      EmitToStreamer(OutStreamer, TmpInst);
964
12
      break;
965
124k
    }
966
124k
    case Mips::XOR_V_H_PSEUDO: {
967
8
      MCInst TmpInst;
968
8
      MCOperand MCOp;
969
8
      TmpInst.setOpcode(Mips::XOR_V);
970
8
      // Operand: wd
971
8
      lowerOperand(MI->getOperand(0), MCOp);
972
8
      TmpInst.addOperand(MCOp);
973
8
      // Operand: ws
974
8
      lowerOperand(MI->getOperand(1), MCOp);
975
8
      TmpInst.addOperand(MCOp);
976
8
      // Operand: wt
977
8
      lowerOperand(MI->getOperand(2), MCOp);
978
8
      TmpInst.addOperand(MCOp);
979
8
      EmitToStreamer(OutStreamer, TmpInst);
980
8
      break;
981
124k
    }
982
124k
    case Mips::XOR_V_W_PSEUDO: {
983
8
      MCInst TmpInst;
984
8
      MCOperand MCOp;
985
8
      TmpInst.setOpcode(Mips::XOR_V);
986
8
      // Operand: wd
987
8
      lowerOperand(MI->getOperand(0), MCOp);
988
8
      TmpInst.addOperand(MCOp);
989
8
      // Operand: ws
990
8
      lowerOperand(MI->getOperand(1), MCOp);
991
8
      TmpInst.addOperand(MCOp);
992
8
      // Operand: wt
993
8
      lowerOperand(MI->getOperand(2), MCOp);
994
8
      TmpInst.addOperand(MCOp);
995
8
      EmitToStreamer(OutStreamer, TmpInst);
996
8
      break;
997
5.18k
    }
998
5.18k
  }
999
5.18k
  return true;
1000
5.18k
}
1001