Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Mips/MipsGenRegisterBank.inc
Line
Count
Source
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Register Bank Source Fragments                                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_REGBANK_DECLARATIONS
10
#undef GET_REGBANK_DECLARATIONS
11
namespace llvm {
12
namespace Mips {
13
enum {
14
  FPRBRegBankID,
15
  GPRBRegBankID,
16
  NumRegisterBanks,
17
};
18
} // end namespace Mips
19
} // end namespace llvm
20
#endif // GET_REGBANK_DECLARATIONS
21
22
#ifdef GET_TARGET_REGBANK_CLASS
23
#undef GET_TARGET_REGBANK_CLASS
24
private:
25
  static RegisterBank *RegBanks[];
26
27
protected:
28
  MipsGenRegisterBankInfo();
29
30
#endif // GET_TARGET_REGBANK_CLASS
31
32
#ifdef GET_TARGET_REGBANK_IMPL
33
#undef GET_TARGET_REGBANK_IMPL
34
namespace llvm {
35
namespace Mips {
36
const uint32_t FPRBRegBankCoverageData[] = {
37
    // 0-31
38
    (1u << (Mips::FGR32RegClassID - 0)) |
39
    (1u << (Mips::FGRCCRegClassID - 0)) |
40
    0,
41
    // 32-63
42
    (1u << (Mips::FGR64RegClassID - 32)) |
43
    (1u << (Mips::AFGR64RegClassID - 32)) |
44
    0,
45
    // 64-95
46
    0,
47
};
48
const uint32_t GPRBRegBankCoverageData[] = {
49
    // 0-31
50
    (1u << (Mips::GPR32RegClassID - 0)) |
51
    (1u << (Mips::GPR32NONZERORegClassID - 0)) |
52
    (1u << (Mips::CPU16RegsPlusSPRegClassID - 0)) |
53
    (1u << (Mips::CPU16RegsRegClassID - 0)) |
54
    (1u << (Mips::GPRMM16RegClassID - 0)) |
55
    (1u << (Mips::CPU16Regs_and_GPRMM16ZeroRegClassID - 0)) |
56
    (1u << (Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID - 0)) |
57
    (1u << (Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID - 0)) |
58
    (1u << (Mips::GPRMM16MovePPairFirstRegClassID - 0)) |
59
    (1u << (Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID - 0)) |
60
    (1u << (Mips::CPU16Regs_and_GPRMM16MovePRegClassID - 0)) |
61
    (1u << (Mips::CPUSPRegRegClassID - 0)) |
62
    (1u << (Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID - 0)) |
63
    (1u << (Mips::GPRMM16MovePPairSecondRegClassID - 0)) |
64
    (1u << (Mips::CPURARegRegClassID - 0)) |
65
    (1u << (Mips::GPRMM16MovePRegClassID - 0)) |
66
    (1u << (Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID - 0)) |
67
    (1u << (Mips::GPRMM16ZeroRegClassID - 0)) |
68
    0,
69
    // 32-63
70
    (1u << (Mips::SP32RegClassID - 32)) |
71
    (1u << (Mips::GP32RegClassID - 32)) |
72
    (1u << (Mips::GPR32ZERORegClassID - 32)) |
73
    0,
74
    // 64-95
75
    0,
76
};
77
78
RegisterBank FPRBRegBank(/* ID */ Mips::FPRBRegBankID, /* Name */ "FPRB", /* Size */ 64, /* CoveredRegClasses */ FPRBRegBankCoverageData, /* NumRegClasses */ 70);
79
RegisterBank GPRBRegBank(/* ID */ Mips::GPRBRegBankID, /* Name */ "GPRB", /* Size */ 32, /* CoveredRegClasses */ GPRBRegBankCoverageData, /* NumRegClasses */ 70);
80
} // end namespace Mips
81
82
RegisterBank *MipsGenRegisterBankInfo::RegBanks[] = {
83
    &Mips::FPRBRegBank,
84
    &Mips::GPRBRegBank,
85
};
86
87
MipsGenRegisterBankInfo::MipsGenRegisterBankInfo()
88
11.3k
    : RegisterBankInfo(RegBanks, Mips::NumRegisterBanks) {
89
11.3k
  // Assert that RegBank indices match their ID's
90
#ifndef NDEBUG
91
  unsigned Index = 0;
92
  for (const auto &RB : RegBanks)
93
    assert(Index++ == RB->getID() && "Index != ID");
94
#endif // NDEBUG
95
}
96
} // end namespace llvm
97
#endif // GET_TARGET_REGBANK_IMPL