Coverage Report

Created: 2018-09-25 17:16

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Mips/MipsGenRegisterBank.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Register Bank Source Fragments                                             *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_REGBANK_DECLARATIONS
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#undef GET_REGBANK_DECLARATIONS
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namespace llvm {
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namespace Mips {
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enum {
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  GPRBRegBankID,
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  NumRegisterBanks,
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};
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} // end namespace Mips
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} // end namespace llvm
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#endif // GET_REGBANK_DECLARATIONS
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#ifdef GET_TARGET_REGBANK_CLASS
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#undef GET_TARGET_REGBANK_CLASS
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private:
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  static RegisterBank *RegBanks[];
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protected:
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  MipsGenRegisterBankInfo();
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#endif // GET_TARGET_REGBANK_CLASS
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#ifdef GET_TARGET_REGBANK_IMPL
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#undef GET_TARGET_REGBANK_IMPL
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namespace llvm {
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namespace Mips {
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const uint32_t GPRBRegBankCoverageData[] = {
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    // 0-31
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    (1u << (Mips::GPR32RegClassID - 0)) |
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    (1u << (Mips::GPR32NONZERORegClassID - 0)) |
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    (1u << (Mips::CPU16RegsPlusSPRegClassID - 0)) |
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    (1u << (Mips::CPU16RegsRegClassID - 0)) |
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    (1u << (Mips::GPRMM16RegClassID - 0)) |
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    (1u << (Mips::CPU16Regs_and_GPRMM16ZeroRegClassID - 0)) |
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    (1u << (Mips::CPU16Regs_and_GPRMM16MovePRegClassID - 0)) |
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    (1u << (Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID - 0)) |
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    (1u << (Mips::GPRMM16MovePPairSecondRegClassID - 0)) |
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    (1u << (Mips::GPRMM16MovePRegClassID - 0)) |
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    (1u << (Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID - 0)) |
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    (1u << (Mips::GPRMM16ZeroRegClassID - 0)) |
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    0,
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    // 32-63
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    (1u << (Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID - 32)) |
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    (1u << (Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID - 32)) |
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    (1u << (Mips::GPRMM16MovePPairFirstRegClassID - 32)) |
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    (1u << (Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID - 32)) |
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    (1u << (Mips::CPUSPRegRegClassID - 32)) |
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    (1u << (Mips::SP32RegClassID - 32)) |
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    (1u << (Mips::CPURARegRegClassID - 32)) |
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    (1u << (Mips::GP32RegClassID - 32)) |
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    (1u << (Mips::GPR32ZERORegClassID - 32)) |
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    0,
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    // 64-95
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    0,
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};
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RegisterBank GPRBRegBank(/* ID */ Mips::GPRBRegBankID, /* Name */ "GPRB", /* Size */ 32, /* CoveredRegClasses */ GPRBRegBankCoverageData, /* NumRegClasses */ 81);
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} // end namespace Mips
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RegisterBank *MipsGenRegisterBankInfo::RegBanks[] = {
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    &Mips::GPRBRegBank,
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};
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MipsGenRegisterBankInfo::MipsGenRegisterBankInfo()
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10.1k
    : RegisterBankInfo(RegBanks, Mips::NumRegisterBanks) {
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10.1k
  // Assert that RegBank indices match their ID's
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#ifndef NDEBUG
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  unsigned Index = 0;
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  for (const auto &RB : RegBanks)
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    assert(Index++ == RB->getID() && "Index != ID");
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#endif // NDEBUG
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}
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} // end namespace llvm
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#endif // GET_TARGET_REGBANK_IMPL