Coverage Report

Created: 2018-11-16 02:38

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Mips/MipsGenRegisterInfo.inc
Line
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Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Register Enum Values                                                *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
#ifdef GET_REGINFO_ENUM
11
#undef GET_REGINFO_ENUM
12
13
namespace llvm {
14
15
class MCRegisterClass;
16
extern const MCRegisterClass MipsMCRegisterClasses[];
17
18
namespace Mips {
19
enum {
20
  NoRegister,
21
  AT = 1,
22
  DSPCCond = 2,
23
  DSPCarry = 3,
24
  DSPEFI = 4,
25
  DSPOutFlag = 5,
26
  DSPPos = 6,
27
  DSPSCount = 7,
28
  FP = 8,
29
  GP = 9,
30
  MSAAccess = 10,
31
  MSACSR = 11,
32
  MSAIR = 12,
33
  MSAMap = 13,
34
  MSAModify = 14,
35
  MSARequest = 15,
36
  MSASave = 16,
37
  MSAUnmap = 17,
38
  PC = 18,
39
  RA = 19,
40
  SP = 20,
41
  ZERO = 21,
42
  A0 = 22,
43
  A1 = 23,
44
  A2 = 24,
45
  A3 = 25,
46
  AC0 = 26,
47
  AC1 = 27,
48
  AC2 = 28,
49
  AC3 = 29,
50
  AT_64 = 30,
51
  COP00 = 31,
52
  COP01 = 32,
53
  COP02 = 33,
54
  COP03 = 34,
55
  COP04 = 35,
56
  COP05 = 36,
57
  COP06 = 37,
58
  COP07 = 38,
59
  COP08 = 39,
60
  COP09 = 40,
61
  COP20 = 41,
62
  COP21 = 42,
63
  COP22 = 43,
64
  COP23 = 44,
65
  COP24 = 45,
66
  COP25 = 46,
67
  COP26 = 47,
68
  COP27 = 48,
69
  COP28 = 49,
70
  COP29 = 50,
71
  COP30 = 51,
72
  COP31 = 52,
73
  COP32 = 53,
74
  COP33 = 54,
75
  COP34 = 55,
76
  COP35 = 56,
77
  COP36 = 57,
78
  COP37 = 58,
79
  COP38 = 59,
80
  COP39 = 60,
81
  COP010 = 61,
82
  COP011 = 62,
83
  COP012 = 63,
84
  COP013 = 64,
85
  COP014 = 65,
86
  COP015 = 66,
87
  COP016 = 67,
88
  COP017 = 68,
89
  COP018 = 69,
90
  COP019 = 70,
91
  COP020 = 71,
92
  COP021 = 72,
93
  COP022 = 73,
94
  COP023 = 74,
95
  COP024 = 75,
96
  COP025 = 76,
97
  COP026 = 77,
98
  COP027 = 78,
99
  COP028 = 79,
100
  COP029 = 80,
101
  COP030 = 81,
102
  COP031 = 82,
103
  COP210 = 83,
104
  COP211 = 84,
105
  COP212 = 85,
106
  COP213 = 86,
107
  COP214 = 87,
108
  COP215 = 88,
109
  COP216 = 89,
110
  COP217 = 90,
111
  COP218 = 91,
112
  COP219 = 92,
113
  COP220 = 93,
114
  COP221 = 94,
115
  COP222 = 95,
116
  COP223 = 96,
117
  COP224 = 97,
118
  COP225 = 98,
119
  COP226 = 99,
120
  COP227 = 100,
121
  COP228 = 101,
122
  COP229 = 102,
123
  COP230 = 103,
124
  COP231 = 104,
125
  COP310 = 105,
126
  COP311 = 106,
127
  COP312 = 107,
128
  COP313 = 108,
129
  COP314 = 109,
130
  COP315 = 110,
131
  COP316 = 111,
132
  COP317 = 112,
133
  COP318 = 113,
134
  COP319 = 114,
135
  COP320 = 115,
136
  COP321 = 116,
137
  COP322 = 117,
138
  COP323 = 118,
139
  COP324 = 119,
140
  COP325 = 120,
141
  COP326 = 121,
142
  COP327 = 122,
143
  COP328 = 123,
144
  COP329 = 124,
145
  COP330 = 125,
146
  COP331 = 126,
147
  D0 = 127,
148
  D1 = 128,
149
  D2 = 129,
150
  D3 = 130,
151
  D4 = 131,
152
  D5 = 132,
153
  D6 = 133,
154
  D7 = 134,
155
  D8 = 135,
156
  D9 = 136,
157
  D10 = 137,
158
  D11 = 138,
159
  D12 = 139,
160
  D13 = 140,
161
  D14 = 141,
162
  D15 = 142,
163
  DSPOutFlag20 = 143,
164
  DSPOutFlag21 = 144,
165
  DSPOutFlag22 = 145,
166
  DSPOutFlag23 = 146,
167
  F0 = 147,
168
  F1 = 148,
169
  F2 = 149,
170
  F3 = 150,
171
  F4 = 151,
172
  F5 = 152,
173
  F6 = 153,
174
  F7 = 154,
175
  F8 = 155,
176
  F9 = 156,
177
  F10 = 157,
178
  F11 = 158,
179
  F12 = 159,
180
  F13 = 160,
181
  F14 = 161,
182
  F15 = 162,
183
  F16 = 163,
184
  F17 = 164,
185
  F18 = 165,
186
  F19 = 166,
187
  F20 = 167,
188
  F21 = 168,
189
  F22 = 169,
190
  F23 = 170,
191
  F24 = 171,
192
  F25 = 172,
193
  F26 = 173,
194
  F27 = 174,
195
  F28 = 175,
196
  F29 = 176,
197
  F30 = 177,
198
  F31 = 178,
199
  FCC0 = 179,
200
  FCC1 = 180,
201
  FCC2 = 181,
202
  FCC3 = 182,
203
  FCC4 = 183,
204
  FCC5 = 184,
205
  FCC6 = 185,
206
  FCC7 = 186,
207
  FCR0 = 187,
208
  FCR1 = 188,
209
  FCR2 = 189,
210
  FCR3 = 190,
211
  FCR4 = 191,
212
  FCR5 = 192,
213
  FCR6 = 193,
214
  FCR7 = 194,
215
  FCR8 = 195,
216
  FCR9 = 196,
217
  FCR10 = 197,
218
  FCR11 = 198,
219
  FCR12 = 199,
220
  FCR13 = 200,
221
  FCR14 = 201,
222
  FCR15 = 202,
223
  FCR16 = 203,
224
  FCR17 = 204,
225
  FCR18 = 205,
226
  FCR19 = 206,
227
  FCR20 = 207,
228
  FCR21 = 208,
229
  FCR22 = 209,
230
  FCR23 = 210,
231
  FCR24 = 211,
232
  FCR25 = 212,
233
  FCR26 = 213,
234
  FCR27 = 214,
235
  FCR28 = 215,
236
  FCR29 = 216,
237
  FCR30 = 217,
238
  FCR31 = 218,
239
  FP_64 = 219,
240
  F_HI0 = 220,
241
  F_HI1 = 221,
242
  F_HI2 = 222,
243
  F_HI3 = 223,
244
  F_HI4 = 224,
245
  F_HI5 = 225,
246
  F_HI6 = 226,
247
  F_HI7 = 227,
248
  F_HI8 = 228,
249
  F_HI9 = 229,
250
  F_HI10 = 230,
251
  F_HI11 = 231,
252
  F_HI12 = 232,
253
  F_HI13 = 233,
254
  F_HI14 = 234,
255
  F_HI15 = 235,
256
  F_HI16 = 236,
257
  F_HI17 = 237,
258
  F_HI18 = 238,
259
  F_HI19 = 239,
260
  F_HI20 = 240,
261
  F_HI21 = 241,
262
  F_HI22 = 242,
263
  F_HI23 = 243,
264
  F_HI24 = 244,
265
  F_HI25 = 245,
266
  F_HI26 = 246,
267
  F_HI27 = 247,
268
  F_HI28 = 248,
269
  F_HI29 = 249,
270
  F_HI30 = 250,
271
  F_HI31 = 251,
272
  GP_64 = 252,
273
  HI0 = 253,
274
  HI1 = 254,
275
  HI2 = 255,
276
  HI3 = 256,
277
  HWR0 = 257,
278
  HWR1 = 258,
279
  HWR2 = 259,
280
  HWR3 = 260,
281
  HWR4 = 261,
282
  HWR5 = 262,
283
  HWR6 = 263,
284
  HWR7 = 264,
285
  HWR8 = 265,
286
  HWR9 = 266,
287
  HWR10 = 267,
288
  HWR11 = 268,
289
  HWR12 = 269,
290
  HWR13 = 270,
291
  HWR14 = 271,
292
  HWR15 = 272,
293
  HWR16 = 273,
294
  HWR17 = 274,
295
  HWR18 = 275,
296
  HWR19 = 276,
297
  HWR20 = 277,
298
  HWR21 = 278,
299
  HWR22 = 279,
300
  HWR23 = 280,
301
  HWR24 = 281,
302
  HWR25 = 282,
303
  HWR26 = 283,
304
  HWR27 = 284,
305
  HWR28 = 285,
306
  HWR29 = 286,
307
  HWR30 = 287,
308
  HWR31 = 288,
309
  K0 = 289,
310
  K1 = 290,
311
  LO0 = 291,
312
  LO1 = 292,
313
  LO2 = 293,
314
  LO3 = 294,
315
  MPL0 = 295,
316
  MPL1 = 296,
317
  MPL2 = 297,
318
  P0 = 298,
319
  P1 = 299,
320
  P2 = 300,
321
  RA_64 = 301,
322
  S0 = 302,
323
  S1 = 303,
324
  S2 = 304,
325
  S3 = 305,
326
  S4 = 306,
327
  S5 = 307,
328
  S6 = 308,
329
  S7 = 309,
330
  SP_64 = 310,
331
  T0 = 311,
332
  T1 = 312,
333
  T2 = 313,
334
  T3 = 314,
335
  T4 = 315,
336
  T5 = 316,
337
  T6 = 317,
338
  T7 = 318,
339
  T8 = 319,
340
  T9 = 320,
341
  V0 = 321,
342
  V1 = 322,
343
  W0 = 323,
344
  W1 = 324,
345
  W2 = 325,
346
  W3 = 326,
347
  W4 = 327,
348
  W5 = 328,
349
  W6 = 329,
350
  W7 = 330,
351
  W8 = 331,
352
  W9 = 332,
353
  W10 = 333,
354
  W11 = 334,
355
  W12 = 335,
356
  W13 = 336,
357
  W14 = 337,
358
  W15 = 338,
359
  W16 = 339,
360
  W17 = 340,
361
  W18 = 341,
362
  W19 = 342,
363
  W20 = 343,
364
  W21 = 344,
365
  W22 = 345,
366
  W23 = 346,
367
  W24 = 347,
368
  W25 = 348,
369
  W26 = 349,
370
  W27 = 350,
371
  W28 = 351,
372
  W29 = 352,
373
  W30 = 353,
374
  W31 = 354,
375
  ZERO_64 = 355,
376
  A0_64 = 356,
377
  A1_64 = 357,
378
  A2_64 = 358,
379
  A3_64 = 359,
380
  AC0_64 = 360,
381
  D0_64 = 361,
382
  D1_64 = 362,
383
  D2_64 = 363,
384
  D3_64 = 364,
385
  D4_64 = 365,
386
  D5_64 = 366,
387
  D6_64 = 367,
388
  D7_64 = 368,
389
  D8_64 = 369,
390
  D9_64 = 370,
391
  D10_64 = 371,
392
  D11_64 = 372,
393
  D12_64 = 373,
394
  D13_64 = 374,
395
  D14_64 = 375,
396
  D15_64 = 376,
397
  D16_64 = 377,
398
  D17_64 = 378,
399
  D18_64 = 379,
400
  D19_64 = 380,
401
  D20_64 = 381,
402
  D21_64 = 382,
403
  D22_64 = 383,
404
  D23_64 = 384,
405
  D24_64 = 385,
406
  D25_64 = 386,
407
  D26_64 = 387,
408
  D27_64 = 388,
409
  D28_64 = 389,
410
  D29_64 = 390,
411
  D30_64 = 391,
412
  D31_64 = 392,
413
  DSPOutFlag16_19 = 393,
414
  HI0_64 = 394,
415
  K0_64 = 395,
416
  K1_64 = 396,
417
  LO0_64 = 397,
418
  S0_64 = 398,
419
  S1_64 = 399,
420
  S2_64 = 400,
421
  S3_64 = 401,
422
  S4_64 = 402,
423
  S5_64 = 403,
424
  S6_64 = 404,
425
  S7_64 = 405,
426
  T0_64 = 406,
427
  T1_64 = 407,
428
  T2_64 = 408,
429
  T3_64 = 409,
430
  T4_64 = 410,
431
  T5_64 = 411,
432
  T6_64 = 412,
433
  T7_64 = 413,
434
  T8_64 = 414,
435
  T9_64 = 415,
436
  V0_64 = 416,
437
  V1_64 = 417,
438
  NUM_TARGET_REGS   // 418
439
};
440
} // end namespace Mips
441
442
// Register classes
443
444
namespace Mips {
445
enum {
446
  MSA128F16RegClassID = 0,
447
  MSA128F16_with_sub_64_in_OddSPRegClassID = 1,
448
  OddSPRegClassID = 2,
449
  CCRRegClassID = 3,
450
  COP0RegClassID = 4,
451
  COP2RegClassID = 5,
452
  COP3RegClassID = 6,
453
  DSPRRegClassID = 7,
454
  FGR32RegClassID = 8,
455
  FGRCCRegClassID = 9,
456
  FGRH32RegClassID = 10,
457
  GPR32RegClassID = 11,
458
  HWRegsRegClassID = 12,
459
  GPR32NONZERORegClassID = 13,
460
  OddSP_with_sub_hiRegClassID = 14,
461
  FGR32_and_OddSPRegClassID = 15,
462
  FGRH32_and_OddSPRegClassID = 16,
463
  OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID = 17,
464
  CPU16RegsPlusSPRegClassID = 18,
465
  CPU16RegsRegClassID = 19,
466
  FCCRegClassID = 20,
467
  GPRMM16RegClassID = 21,
468
  GPRMM16MovePRegClassID = 22,
469
  GPRMM16ZeroRegClassID = 23,
470
  MSACtrlRegClassID = 24,
471
  OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID = 25,
472
  CPU16Regs_and_GPRMM16ZeroRegClassID = 26,
473
  GPR32NONZERO_and_GPRMM16MovePRegClassID = 27,
474
  GPRMM16MovePPairSecondRegClassID = 28,
475
  CPU16Regs_and_GPRMM16MovePRegClassID = 29,
476
  GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 30,
477
  HI32DSPRegClassID = 31,
478
  LO32DSPRegClassID = 32,
479
  CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 33,
480
  GPRMM16MovePPairFirstRegClassID = 34,
481
  GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 35,
482
  GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 36,
483
  CPURARegRegClassID = 37,
484
  CPUSPRegRegClassID = 38,
485
  DSPCCRegClassID = 39,
486
  GP32RegClassID = 40,
487
  GPR32ZERORegClassID = 41,
488
  HI32RegClassID = 42,
489
  LO32RegClassID = 43,
490
  SP32RegClassID = 44,
491
  FGR64RegClassID = 45,
492
  GPR64RegClassID = 46,
493
  GPR64_with_sub_32_in_GPR32NONZERORegClassID = 47,
494
  AFGR64RegClassID = 48,
495
  FGR64_and_OddSPRegClassID = 49,
496
  GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 50,
497
  AFGR64_and_OddSPRegClassID = 51,
498
  GPR64_with_sub_32_in_CPU16RegsRegClassID = 52,
499
  GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 53,
500
  GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 54,
501
  GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 55,
502
  GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID = 56,
503
  GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID = 57,
504
  ACC64DSPRegClassID = 58,
505
  GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 59,
506
  GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 60,
507
  GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 61,
508
  GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID = 62,
509
  GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 63,
510
  OCTEON_MPLRegClassID = 64,
511
  OCTEON_PRegClassID = 65,
512
  GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 66,
513
  ACC64RegClassID = 67,
514
  GP64RegClassID = 68,
515
  GPR64_with_sub_32_in_CPURARegRegClassID = 69,
516
  GPR64_with_sub_32_in_GPR32ZERORegClassID = 70,
517
  HI64RegClassID = 71,
518
  LO64RegClassID = 72,
519
  SP64RegClassID = 73,
520
  MSA128BRegClassID = 74,
521
  MSA128DRegClassID = 75,
522
  MSA128HRegClassID = 76,
523
  MSA128WRegClassID = 77,
524
  MSA128B_with_sub_64_in_OddSPRegClassID = 78,
525
  MSA128WEvensRegClassID = 79,
526
  ACC128RegClassID = 80,
527
528
  };
529
} // end namespace Mips
530
531
532
// Subregister indices
533
534
namespace Mips {
535
enum {
536
  NoSubRegister,
537
  sub_32, // 1
538
  sub_64, // 2
539
  sub_dsp16_19, // 3
540
  sub_dsp20,  // 4
541
  sub_dsp21,  // 5
542
  sub_dsp22,  // 6
543
  sub_dsp23,  // 7
544
  sub_hi, // 8
545
  sub_lo, // 9
546
  sub_hi_then_sub_32, // 10
547
  sub_32_sub_hi_then_sub_32,  // 11
548
  NUM_TARGET_SUBREGS
549
};
550
} // end namespace Mips
551
552
} // end namespace llvm
553
554
#endif // GET_REGINFO_ENUM
555
556
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
557
|*                                                                            *|
558
|* MC Register Information                                                    *|
559
|*                                                                            *|
560
|* Automatically generated file, do not edit!                                 *|
561
|*                                                                            *|
562
\*===----------------------------------------------------------------------===*/
563
564
565
#ifdef GET_REGINFO_MC_DESC
566
#undef GET_REGINFO_MC_DESC
567
568
namespace llvm {
569
570
extern const MCPhysReg MipsRegDiffLists[] = {
571
  /* 0 */ 0, 0,
572
  /* 2 */ 4, 1, 1, 1, 1, 0,
573
  /* 8 */ 388, 65286, 1, 1, 1, 0,
574
  /* 14 */ 20, 1, 0,
575
  /* 17 */ 21, 1, 0,
576
  /* 20 */ 22, 1, 0,
577
  /* 23 */ 23, 1, 0,
578
  /* 26 */ 24, 1, 0,
579
  /* 29 */ 25, 1, 0,
580
  /* 32 */ 26, 1, 0,
581
  /* 35 */ 27, 1, 0,
582
  /* 38 */ 28, 1, 0,
583
  /* 41 */ 29, 1, 0,
584
  /* 44 */ 30, 1, 0,
585
  /* 47 */ 31, 1, 0,
586
  /* 50 */ 32, 1, 0,
587
  /* 53 */ 33, 1, 0,
588
  /* 56 */ 34, 1, 0,
589
  /* 59 */ 35, 1, 0,
590
  /* 62 */ 65415, 1, 0,
591
  /* 65 */ 65513, 1, 0,
592
  /* 68 */ 3, 0,
593
  /* 70 */ 4, 0,
594
  /* 72 */ 6, 0,
595
  /* 74 */ 11, 0,
596
  /* 76 */ 12, 0,
597
  /* 78 */ 22, 0,
598
  /* 80 */ 23, 0,
599
  /* 82 */ 29, 0,
600
  /* 84 */ 30, 0,
601
  /* 86 */ 65308, 72, 0,
602
  /* 89 */ 65346, 72, 0,
603
  /* 92 */ 38, 65322, 73, 0,
604
  /* 96 */ 95, 0,
605
  /* 98 */ 96, 0,
606
  /* 100 */ 106, 0,
607
  /* 102 */ 211, 0,
608
  /* 104 */ 243, 0,
609
  /* 106 */ 282, 0,
610
  /* 108 */ 290, 0,
611
  /* 110 */ 334, 0,
612
  /* 112 */ 64983, 0,
613
  /* 114 */ 65060, 0,
614
  /* 116 */ 65148, 0,
615
  /* 118 */ 65202, 0,
616
  /* 120 */ 65205, 0,
617
  /* 122 */ 65246, 0,
618
  /* 124 */ 65254, 0,
619
  /* 126 */ 65271, 0,
620
  /* 128 */ 65293, 0,
621
  /* 130 */ 37, 65430, 103, 65395, 65309, 0,
622
  /* 136 */ 65325, 0,
623
  /* 138 */ 65395, 0,
624
  /* 140 */ 65396, 0,
625
  /* 142 */ 65397, 0,
626
  /* 144 */ 65398, 0,
627
  /* 146 */ 65410, 0,
628
  /* 148 */ 65415, 0,
629
  /* 150 */ 65430, 0,
630
  /* 152 */ 65440, 0,
631
  /* 154 */ 65441, 0,
632
  /* 156 */ 141, 65498, 0,
633
  /* 159 */ 65516, 234, 65498, 0,
634
  /* 163 */ 65515, 235, 65498, 0,
635
  /* 167 */ 65514, 236, 65498, 0,
636
  /* 171 */ 65513, 237, 65498, 0,
637
  /* 175 */ 65512, 238, 65498, 0,
638
  /* 179 */ 65511, 239, 65498, 0,
639
  /* 183 */ 65510, 240, 65498, 0,
640
  /* 187 */ 65509, 241, 65498, 0,
641
  /* 191 */ 65508, 242, 65498, 0,
642
  /* 195 */ 65507, 243, 65498, 0,
643
  /* 199 */ 65506, 244, 65498, 0,
644
  /* 203 */ 65505, 245, 65498, 0,
645
  /* 207 */ 65504, 246, 65498, 0,
646
  /* 211 */ 65503, 247, 65498, 0,
647
  /* 215 */ 65502, 248, 65498, 0,
648
  /* 219 */ 65501, 249, 65498, 0,
649
  /* 223 */ 65500, 250, 65498, 0,
650
  /* 227 */ 265, 65498, 0,
651
  /* 230 */ 65271, 371, 65499, 0,
652
  /* 234 */ 65309, 368, 65502, 0,
653
  /* 238 */ 65507, 0,
654
  /* 240 */ 65510, 0,
655
  /* 242 */ 65511, 0,
656
  /* 244 */ 65512, 0,
657
  /* 246 */ 65516, 0,
658
  /* 248 */ 65521, 0,
659
  /* 250 */ 65522, 0,
660
  /* 252 */ 65535, 0,
661
};
662
663
extern const LaneBitmask MipsLaneMaskLists[] = {
664
  /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
665
  /* 2 */ LaneBitmask(0x00000001), LaneBitmask::getAll(),
666
  /* 4 */ LaneBitmask(0x00000002), LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask::getAll(),
667
  /* 10 */ LaneBitmask(0x00000001), LaneBitmask(0x00000040), LaneBitmask::getAll(),
668
};
669
670
extern const uint16_t MipsSubRegIdxLists[] = {
671
  /* 0 */ 1, 0,
672
  /* 2 */ 3, 4, 5, 6, 7, 0,
673
  /* 8 */ 2, 9, 8, 0,
674
  /* 12 */ 9, 1, 8, 10, 11, 0,
675
};
676
677
extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[] = {
678
  { 65535, 65535 },
679
  { 0, 32 },  // sub_32
680
  { 0, 64 },  // sub_64
681
  { 16, 4 },  // sub_dsp16_19
682
  { 20, 1 },  // sub_dsp20
683
  { 21, 1 },  // sub_dsp21
684
  { 22, 1 },  // sub_dsp22
685
  { 23, 1 },  // sub_dsp23
686
  { 32, 32 }, // sub_hi
687
  { 0, 32 },  // sub_lo
688
  { 32, 32 }, // sub_hi_then_sub_32
689
  { 0, 64 },  // sub_32_sub_hi_then_sub_32
690
};
691
692
extern const char MipsRegStrings[] = {
693
  /* 0 */ 'C', 'O', 'P', '0', '0', 0,
694
  /* 6 */ 'C', 'O', 'P', '0', '1', '0', 0,
695
  /* 13 */ 'C', 'O', 'P', '2', '1', '0', 0,
696
  /* 20 */ 'C', 'O', 'P', '3', '1', '0', 0,
697
  /* 27 */ 'D', '1', '0', 0,
698
  /* 31 */ 'F', '1', '0', 0,
699
  /* 35 */ 'F', '_', 'H', 'I', '1', '0', 0,
700
  /* 42 */ 'F', 'C', 'R', '1', '0', 0,
701
  /* 48 */ 'H', 'W', 'R', '1', '0', 0,
702
  /* 54 */ 'W', '1', '0', 0,
703
  /* 58 */ 'C', 'O', 'P', '0', '2', '0', 0,
704
  /* 65 */ 'C', 'O', 'P', '2', '2', '0', 0,
705
  /* 72 */ 'C', 'O', 'P', '3', '2', '0', 0,
706
  /* 79 */ 'F', '2', '0', 0,
707
  /* 83 */ 'F', '_', 'H', 'I', '2', '0', 0,
708
  /* 90 */ 'C', 'O', 'P', '2', '0', 0,
709
  /* 96 */ 'F', 'C', 'R', '2', '0', 0,
710
  /* 102 */ 'H', 'W', 'R', '2', '0', 0,
711
  /* 108 */ 'W', '2', '0', 0,
712
  /* 112 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '0', 0,
713
  /* 125 */ 'C', 'O', 'P', '0', '3', '0', 0,
714
  /* 132 */ 'C', 'O', 'P', '2', '3', '0', 0,
715
  /* 139 */ 'C', 'O', 'P', '3', '3', '0', 0,
716
  /* 146 */ 'F', '3', '0', 0,
717
  /* 150 */ 'F', '_', 'H', 'I', '3', '0', 0,
718
  /* 157 */ 'C', 'O', 'P', '3', '0', 0,
719
  /* 163 */ 'F', 'C', 'R', '3', '0', 0,
720
  /* 169 */ 'H', 'W', 'R', '3', '0', 0,
721
  /* 175 */ 'W', '3', '0', 0,
722
  /* 179 */ 'A', '0', 0,
723
  /* 182 */ 'A', 'C', '0', 0,
724
  /* 186 */ 'F', 'C', 'C', '0', 0,
725
  /* 191 */ 'D', '0', 0,
726
  /* 194 */ 'F', '0', 0,
727
  /* 197 */ 'F', '_', 'H', 'I', '0', 0,
728
  /* 203 */ 'K', '0', 0,
729
  /* 206 */ 'M', 'P', 'L', '0', 0,
730
  /* 211 */ 'L', 'O', '0', 0,
731
  /* 215 */ 'P', '0', 0,
732
  /* 218 */ 'F', 'C', 'R', '0', 0,
733
  /* 223 */ 'H', 'W', 'R', '0', 0,
734
  /* 228 */ 'S', '0', 0,
735
  /* 231 */ 'T', '0', 0,
736
  /* 234 */ 'V', '0', 0,
737
  /* 237 */ 'W', '0', 0,
738
  /* 240 */ 'C', 'O', 'P', '0', '1', 0,
739
  /* 246 */ 'C', 'O', 'P', '0', '1', '1', 0,
740
  /* 253 */ 'C', 'O', 'P', '2', '1', '1', 0,
741
  /* 260 */ 'C', 'O', 'P', '3', '1', '1', 0,
742
  /* 267 */ 'D', '1', '1', 0,
743
  /* 271 */ 'F', '1', '1', 0,
744
  /* 275 */ 'F', '_', 'H', 'I', '1', '1', 0,
745
  /* 282 */ 'F', 'C', 'R', '1', '1', 0,
746
  /* 288 */ 'H', 'W', 'R', '1', '1', 0,
747
  /* 294 */ 'W', '1', '1', 0,
748
  /* 298 */ 'C', 'O', 'P', '0', '2', '1', 0,
749
  /* 305 */ 'C', 'O', 'P', '2', '2', '1', 0,
750
  /* 312 */ 'C', 'O', 'P', '3', '2', '1', 0,
751
  /* 319 */ 'F', '2', '1', 0,
752
  /* 323 */ 'F', '_', 'H', 'I', '2', '1', 0,
753
  /* 330 */ 'C', 'O', 'P', '2', '1', 0,
754
  /* 336 */ 'F', 'C', 'R', '2', '1', 0,
755
  /* 342 */ 'H', 'W', 'R', '2', '1', 0,
756
  /* 348 */ 'W', '2', '1', 0,
757
  /* 352 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '1', 0,
758
  /* 365 */ 'C', 'O', 'P', '0', '3', '1', 0,
759
  /* 372 */ 'C', 'O', 'P', '2', '3', '1', 0,
760
  /* 379 */ 'C', 'O', 'P', '3', '3', '1', 0,
761
  /* 386 */ 'F', '3', '1', 0,
762
  /* 390 */ 'F', '_', 'H', 'I', '3', '1', 0,
763
  /* 397 */ 'C', 'O', 'P', '3', '1', 0,
764
  /* 403 */ 'F', 'C', 'R', '3', '1', 0,
765
  /* 409 */ 'H', 'W', 'R', '3', '1', 0,
766
  /* 415 */ 'W', '3', '1', 0,
767
  /* 419 */ 'A', '1', 0,
768
  /* 422 */ 'A', 'C', '1', 0,
769
  /* 426 */ 'F', 'C', 'C', '1', 0,
770
  /* 431 */ 'D', '1', 0,
771
  /* 434 */ 'F', '1', 0,
772
  /* 437 */ 'F', '_', 'H', 'I', '1', 0,
773
  /* 443 */ 'K', '1', 0,
774
  /* 446 */ 'M', 'P', 'L', '1', 0,
775
  /* 451 */ 'L', 'O', '1', 0,
776
  /* 455 */ 'P', '1', 0,
777
  /* 458 */ 'F', 'C', 'R', '1', 0,
778
  /* 463 */ 'H', 'W', 'R', '1', 0,
779
  /* 468 */ 'S', '1', 0,
780
  /* 471 */ 'T', '1', 0,
781
  /* 474 */ 'V', '1', 0,
782
  /* 477 */ 'W', '1', 0,
783
  /* 480 */ 'C', 'O', 'P', '0', '2', 0,
784
  /* 486 */ 'C', 'O', 'P', '0', '1', '2', 0,
785
  /* 493 */ 'C', 'O', 'P', '2', '1', '2', 0,
786
  /* 500 */ 'C', 'O', 'P', '3', '1', '2', 0,
787
  /* 507 */ 'D', '1', '2', 0,
788
  /* 511 */ 'F', '1', '2', 0,
789
  /* 515 */ 'F', '_', 'H', 'I', '1', '2', 0,
790
  /* 522 */ 'F', 'C', 'R', '1', '2', 0,
791
  /* 528 */ 'H', 'W', 'R', '1', '2', 0,
792
  /* 534 */ 'W', '1', '2', 0,
793
  /* 538 */ 'C', 'O', 'P', '0', '2', '2', 0,
794
  /* 545 */ 'C', 'O', 'P', '2', '2', '2', 0,
795
  /* 552 */ 'C', 'O', 'P', '3', '2', '2', 0,
796
  /* 559 */ 'F', '2', '2', 0,
797
  /* 563 */ 'F', '_', 'H', 'I', '2', '2', 0,
798
  /* 570 */ 'C', 'O', 'P', '2', '2', 0,
799
  /* 576 */ 'F', 'C', 'R', '2', '2', 0,
800
  /* 582 */ 'H', 'W', 'R', '2', '2', 0,
801
  /* 588 */ 'W', '2', '2', 0,
802
  /* 592 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '2', 0,
803
  /* 605 */ 'C', 'O', 'P', '3', '2', 0,
804
  /* 611 */ 'A', '2', 0,
805
  /* 614 */ 'A', 'C', '2', 0,
806
  /* 618 */ 'F', 'C', 'C', '2', 0,
807
  /* 623 */ 'D', '2', 0,
808
  /* 626 */ 'F', '2', 0,
809
  /* 629 */ 'F', '_', 'H', 'I', '2', 0,
810
  /* 635 */ 'M', 'P', 'L', '2', 0,
811
  /* 640 */ 'L', 'O', '2', 0,
812
  /* 644 */ 'P', '2', 0,
813
  /* 647 */ 'F', 'C', 'R', '2', 0,
814
  /* 652 */ 'H', 'W', 'R', '2', 0,
815
  /* 657 */ 'S', '2', 0,
816
  /* 660 */ 'T', '2', 0,
817
  /* 663 */ 'W', '2', 0,
818
  /* 666 */ 'C', 'O', 'P', '0', '3', 0,
819
  /* 672 */ 'C', 'O', 'P', '0', '1', '3', 0,
820
  /* 679 */ 'C', 'O', 'P', '2', '1', '3', 0,
821
  /* 686 */ 'C', 'O', 'P', '3', '1', '3', 0,
822
  /* 693 */ 'D', '1', '3', 0,
823
  /* 697 */ 'F', '1', '3', 0,
824
  /* 701 */ 'F', '_', 'H', 'I', '1', '3', 0,
825
  /* 708 */ 'F', 'C', 'R', '1', '3', 0,
826
  /* 714 */ 'H', 'W', 'R', '1', '3', 0,
827
  /* 720 */ 'W', '1', '3', 0,
828
  /* 724 */ 'C', 'O', 'P', '0', '2', '3', 0,
829
  /* 731 */ 'C', 'O', 'P', '2', '2', '3', 0,
830
  /* 738 */ 'C', 'O', 'P', '3', '2', '3', 0,
831
  /* 745 */ 'F', '2', '3', 0,
832
  /* 749 */ 'F', '_', 'H', 'I', '2', '3', 0,
833
  /* 756 */ 'C', 'O', 'P', '2', '3', 0,
834
  /* 762 */ 'F', 'C', 'R', '2', '3', 0,
835
  /* 768 */ 'H', 'W', 'R', '2', '3', 0,
836
  /* 774 */ 'W', '2', '3', 0,
837
  /* 778 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '3', 0,
838
  /* 791 */ 'C', 'O', 'P', '3', '3', 0,
839
  /* 797 */ 'A', '3', 0,
840
  /* 800 */ 'A', 'C', '3', 0,
841
  /* 804 */ 'F', 'C', 'C', '3', 0,
842
  /* 809 */ 'D', '3', 0,
843
  /* 812 */ 'F', '3', 0,
844
  /* 815 */ 'F', '_', 'H', 'I', '3', 0,
845
  /* 821 */ 'L', 'O', '3', 0,
846
  /* 825 */ 'F', 'C', 'R', '3', 0,
847
  /* 830 */ 'H', 'W', 'R', '3', 0,
848
  /* 835 */ 'S', '3', 0,
849
  /* 838 */ 'T', '3', 0,
850
  /* 841 */ 'W', '3', 0,
851
  /* 844 */ 'C', 'O', 'P', '0', '4', 0,
852
  /* 850 */ 'C', 'O', 'P', '0', '1', '4', 0,
853
  /* 857 */ 'C', 'O', 'P', '2', '1', '4', 0,
854
  /* 864 */ 'C', 'O', 'P', '3', '1', '4', 0,
855
  /* 871 */ 'D', '1', '4', 0,
856
  /* 875 */ 'F', '1', '4', 0,
857
  /* 879 */ 'F', '_', 'H', 'I', '1', '4', 0,
858
  /* 886 */ 'F', 'C', 'R', '1', '4', 0,
859
  /* 892 */ 'H', 'W', 'R', '1', '4', 0,
860
  /* 898 */ 'W', '1', '4', 0,
861
  /* 902 */ 'C', 'O', 'P', '0', '2', '4', 0,
862
  /* 909 */ 'C', 'O', 'P', '2', '2', '4', 0,
863
  /* 916 */ 'C', 'O', 'P', '3', '2', '4', 0,
864
  /* 923 */ 'F', '2', '4', 0,
865
  /* 927 */ 'F', '_', 'H', 'I', '2', '4', 0,
866
  /* 934 */ 'C', 'O', 'P', '2', '4', 0,
867
  /* 940 */ 'F', 'C', 'R', '2', '4', 0,
868
  /* 946 */ 'H', 'W', 'R', '2', '4', 0,
869
  /* 952 */ 'W', '2', '4', 0,
870
  /* 956 */ 'C', 'O', 'P', '3', '4', 0,
871
  /* 962 */ 'D', '1', '0', '_', '6', '4', 0,
872
  /* 969 */ 'D', '2', '0', '_', '6', '4', 0,
873
  /* 976 */ 'D', '3', '0', '_', '6', '4', 0,
874
  /* 983 */ 'A', '0', '_', '6', '4', 0,
875
  /* 989 */ 'A', 'C', '0', '_', '6', '4', 0,
876
  /* 996 */ 'D', '0', '_', '6', '4', 0,
877
  /* 1002 */ 'H', 'I', '0', '_', '6', '4', 0,
878
  /* 1009 */ 'K', '0', '_', '6', '4', 0,
879
  /* 1015 */ 'L', 'O', '0', '_', '6', '4', 0,
880
  /* 1022 */ 'S', '0', '_', '6', '4', 0,
881
  /* 1028 */ 'T', '0', '_', '6', '4', 0,
882
  /* 1034 */ 'V', '0', '_', '6', '4', 0,
883
  /* 1040 */ 'D', '1', '1', '_', '6', '4', 0,
884
  /* 1047 */ 'D', '2', '1', '_', '6', '4', 0,
885
  /* 1054 */ 'D', '3', '1', '_', '6', '4', 0,
886
  /* 1061 */ 'A', '1', '_', '6', '4', 0,
887
  /* 1067 */ 'D', '1', '_', '6', '4', 0,
888
  /* 1073 */ 'K', '1', '_', '6', '4', 0,
889
  /* 1079 */ 'S', '1', '_', '6', '4', 0,
890
  /* 1085 */ 'T', '1', '_', '6', '4', 0,
891
  /* 1091 */ 'V', '1', '_', '6', '4', 0,
892
  /* 1097 */ 'D', '1', '2', '_', '6', '4', 0,
893
  /* 1104 */ 'D', '2', '2', '_', '6', '4', 0,
894
  /* 1111 */ 'A', '2', '_', '6', '4', 0,
895
  /* 1117 */ 'D', '2', '_', '6', '4', 0,
896
  /* 1123 */ 'S', '2', '_', '6', '4', 0,
897
  /* 1129 */ 'T', '2', '_', '6', '4', 0,
898
  /* 1135 */ 'D', '1', '3', '_', '6', '4', 0,
899
  /* 1142 */ 'D', '2', '3', '_', '6', '4', 0,
900
  /* 1149 */ 'A', '3', '_', '6', '4', 0,
901
  /* 1155 */ 'D', '3', '_', '6', '4', 0,
902
  /* 1161 */ 'S', '3', '_', '6', '4', 0,
903
  /* 1167 */ 'T', '3', '_', '6', '4', 0,
904
  /* 1173 */ 'D', '1', '4', '_', '6', '4', 0,
905
  /* 1180 */ 'D', '2', '4', '_', '6', '4', 0,
906
  /* 1187 */ 'D', '4', '_', '6', '4', 0,
907
  /* 1193 */ 'S', '4', '_', '6', '4', 0,
908
  /* 1199 */ 'T', '4', '_', '6', '4', 0,
909
  /* 1205 */ 'D', '1', '5', '_', '6', '4', 0,
910
  /* 1212 */ 'D', '2', '5', '_', '6', '4', 0,
911
  /* 1219 */ 'D', '5', '_', '6', '4', 0,
912
  /* 1225 */ 'S', '5', '_', '6', '4', 0,
913
  /* 1231 */ 'T', '5', '_', '6', '4', 0,
914
  /* 1237 */ 'D', '1', '6', '_', '6', '4', 0,
915
  /* 1244 */ 'D', '2', '6', '_', '6', '4', 0,
916
  /* 1251 */ 'D', '6', '_', '6', '4', 0,
917
  /* 1257 */ 'S', '6', '_', '6', '4', 0,
918
  /* 1263 */ 'T', '6', '_', '6', '4', 0,
919
  /* 1269 */ 'D', '1', '7', '_', '6', '4', 0,
920
  /* 1276 */ 'D', '2', '7', '_', '6', '4', 0,
921
  /* 1283 */ 'D', '7', '_', '6', '4', 0,
922
  /* 1289 */ 'S', '7', '_', '6', '4', 0,
923
  /* 1295 */ 'T', '7', '_', '6', '4', 0,
924
  /* 1301 */ 'D', '1', '8', '_', '6', '4', 0,
925
  /* 1308 */ 'D', '2', '8', '_', '6', '4', 0,
926
  /* 1315 */ 'D', '8', '_', '6', '4', 0,
927
  /* 1321 */ 'T', '8', '_', '6', '4', 0,
928
  /* 1327 */ 'D', '1', '9', '_', '6', '4', 0,
929
  /* 1334 */ 'D', '2', '9', '_', '6', '4', 0,
930
  /* 1341 */ 'D', '9', '_', '6', '4', 0,
931
  /* 1347 */ 'T', '9', '_', '6', '4', 0,
932
  /* 1353 */ 'R', 'A', '_', '6', '4', 0,
933
  /* 1359 */ 'Z', 'E', 'R', 'O', '_', '6', '4', 0,
934
  /* 1367 */ 'F', 'P', '_', '6', '4', 0,
935
  /* 1373 */ 'G', 'P', '_', '6', '4', 0,
936
  /* 1379 */ 'S', 'P', '_', '6', '4', 0,
937
  /* 1385 */ 'A', 'T', '_', '6', '4', 0,
938
  /* 1391 */ 'F', 'C', 'C', '4', 0,
939
  /* 1396 */ 'D', '4', 0,
940
  /* 1399 */ 'F', '4', 0,
941
  /* 1402 */ 'F', '_', 'H', 'I', '4', 0,
942
  /* 1408 */ 'F', 'C', 'R', '4', 0,
943
  /* 1413 */ 'H', 'W', 'R', '4', 0,
944
  /* 1418 */ 'S', '4', 0,
945
  /* 1421 */ 'T', '4', 0,
946
  /* 1424 */ 'W', '4', 0,
947
  /* 1427 */ 'C', 'O', 'P', '0', '5', 0,
948
  /* 1433 */ 'C', 'O', 'P', '0', '1', '5', 0,
949
  /* 1440 */ 'C', 'O', 'P', '2', '1', '5', 0,
950
  /* 1447 */ 'C', 'O', 'P', '3', '1', '5', 0,
951
  /* 1454 */ 'D', '1', '5', 0,
952
  /* 1458 */ 'F', '1', '5', 0,
953
  /* 1462 */ 'F', '_', 'H', 'I', '1', '5', 0,
954
  /* 1469 */ 'F', 'C', 'R', '1', '5', 0,
955
  /* 1475 */ 'H', 'W', 'R', '1', '5', 0,
956
  /* 1481 */ 'W', '1', '5', 0,
957
  /* 1485 */ 'C', 'O', 'P', '0', '2', '5', 0,
958
  /* 1492 */ 'C', 'O', 'P', '2', '2', '5', 0,
959
  /* 1499 */ 'C', 'O', 'P', '3', '2', '5', 0,
960
  /* 1506 */ 'F', '2', '5', 0,
961
  /* 1510 */ 'F', '_', 'H', 'I', '2', '5', 0,
962
  /* 1517 */ 'C', 'O', 'P', '2', '5', 0,
963
  /* 1523 */ 'F', 'C', 'R', '2', '5', 0,
964
  /* 1529 */ 'H', 'W', 'R', '2', '5', 0,
965
  /* 1535 */ 'W', '2', '5', 0,
966
  /* 1539 */ 'C', 'O', 'P', '3', '5', 0,
967
  /* 1545 */ 'F', 'C', 'C', '5', 0,
968
  /* 1550 */ 'D', '5', 0,
969
  /* 1553 */ 'F', '5', 0,
970
  /* 1556 */ 'F', '_', 'H', 'I', '5', 0,
971
  /* 1562 */ 'F', 'C', 'R', '5', 0,
972
  /* 1567 */ 'H', 'W', 'R', '5', 0,
973
  /* 1572 */ 'S', '5', 0,
974
  /* 1575 */ 'T', '5', 0,
975
  /* 1578 */ 'W', '5', 0,
976
  /* 1581 */ 'C', 'O', 'P', '0', '6', 0,
977
  /* 1587 */ 'C', 'O', 'P', '0', '1', '6', 0,
978
  /* 1594 */ 'C', 'O', 'P', '2', '1', '6', 0,
979
  /* 1601 */ 'C', 'O', 'P', '3', '1', '6', 0,
980
  /* 1608 */ 'F', '1', '6', 0,
981
  /* 1612 */ 'F', '_', 'H', 'I', '1', '6', 0,
982
  /* 1619 */ 'F', 'C', 'R', '1', '6', 0,
983
  /* 1625 */ 'H', 'W', 'R', '1', '6', 0,
984
  /* 1631 */ 'W', '1', '6', 0,
985
  /* 1635 */ 'C', 'O', 'P', '0', '2', '6', 0,
986
  /* 1642 */ 'C', 'O', 'P', '2', '2', '6', 0,
987
  /* 1649 */ 'C', 'O', 'P', '3', '2', '6', 0,
988
  /* 1656 */ 'F', '2', '6', 0,
989
  /* 1660 */ 'F', '_', 'H', 'I', '2', '6', 0,
990
  /* 1667 */ 'C', 'O', 'P', '2', '6', 0,
991
  /* 1673 */ 'F', 'C', 'R', '2', '6', 0,
992
  /* 1679 */ 'H', 'W', 'R', '2', '6', 0,
993
  /* 1685 */ 'W', '2', '6', 0,
994
  /* 1689 */ 'C', 'O', 'P', '3', '6', 0,
995
  /* 1695 */ 'F', 'C', 'C', '6', 0,
996
  /* 1700 */ 'D', '6', 0,
997
  /* 1703 */ 'F', '6', 0,
998
  /* 1706 */ 'F', '_', 'H', 'I', '6', 0,
999
  /* 1712 */ 'F', 'C', 'R', '6', 0,
1000
  /* 1717 */ 'H', 'W', 'R', '6', 0,
1001
  /* 1722 */ 'S', '6', 0,
1002
  /* 1725 */ 'T', '6', 0,
1003
  /* 1728 */ 'W', '6', 0,
1004
  /* 1731 */ 'C', 'O', 'P', '0', '7', 0,
1005
  /* 1737 */ 'C', 'O', 'P', '0', '1', '7', 0,
1006
  /* 1744 */ 'C', 'O', 'P', '2', '1', '7', 0,
1007
  /* 1751 */ 'C', 'O', 'P', '3', '1', '7', 0,
1008
  /* 1758 */ 'F', '1', '7', 0,
1009
  /* 1762 */ 'F', '_', 'H', 'I', '1', '7', 0,
1010
  /* 1769 */ 'F', 'C', 'R', '1', '7', 0,
1011
  /* 1775 */ 'H', 'W', 'R', '1', '7', 0,
1012
  /* 1781 */ 'W', '1', '7', 0,
1013
  /* 1785 */ 'C', 'O', 'P', '0', '2', '7', 0,
1014
  /* 1792 */ 'C', 'O', 'P', '2', '2', '7', 0,
1015
  /* 1799 */ 'C', 'O', 'P', '3', '2', '7', 0,
1016
  /* 1806 */ 'F', '2', '7', 0,
1017
  /* 1810 */ 'F', '_', 'H', 'I', '2', '7', 0,
1018
  /* 1817 */ 'C', 'O', 'P', '2', '7', 0,
1019
  /* 1823 */ 'F', 'C', 'R', '2', '7', 0,
1020
  /* 1829 */ 'H', 'W', 'R', '2', '7', 0,
1021
  /* 1835 */ 'W', '2', '7', 0,
1022
  /* 1839 */ 'C', 'O', 'P', '3', '7', 0,
1023
  /* 1845 */ 'F', 'C', 'C', '7', 0,
1024
  /* 1850 */ 'D', '7', 0,
1025
  /* 1853 */ 'F', '7', 0,
1026
  /* 1856 */ 'F', '_', 'H', 'I', '7', 0,
1027
  /* 1862 */ 'F', 'C', 'R', '7', 0,
1028
  /* 1867 */ 'H', 'W', 'R', '7', 0,
1029
  /* 1872 */ 'S', '7', 0,
1030
  /* 1875 */ 'T', '7', 0,
1031
  /* 1878 */ 'W', '7', 0,
1032
  /* 1881 */ 'C', 'O', 'P', '0', '8', 0,
1033
  /* 1887 */ 'C', 'O', 'P', '0', '1', '8', 0,
1034
  /* 1894 */ 'C', 'O', 'P', '2', '1', '8', 0,
1035
  /* 1901 */ 'C', 'O', 'P', '3', '1', '8', 0,
1036
  /* 1908 */ 'F', '1', '8', 0,
1037
  /* 1912 */ 'F', '_', 'H', 'I', '1', '8', 0,
1038
  /* 1919 */ 'F', 'C', 'R', '1', '8', 0,
1039
  /* 1925 */ 'H', 'W', 'R', '1', '8', 0,
1040
  /* 1931 */ 'W', '1', '8', 0,
1041
  /* 1935 */ 'C', 'O', 'P', '0', '2', '8', 0,
1042
  /* 1942 */ 'C', 'O', 'P', '2', '2', '8', 0,
1043
  /* 1949 */ 'C', 'O', 'P', '3', '2', '8', 0,
1044
  /* 1956 */ 'F', '2', '8', 0,
1045
  /* 1960 */ 'F', '_', 'H', 'I', '2', '8', 0,
1046
  /* 1967 */ 'C', 'O', 'P', '2', '8', 0,
1047
  /* 1973 */ 'F', 'C', 'R', '2', '8', 0,
1048
  /* 1979 */ 'H', 'W', 'R', '2', '8', 0,
1049
  /* 1985 */ 'W', '2', '8', 0,
1050
  /* 1989 */ 'C', 'O', 'P', '3', '8', 0,
1051
  /* 1995 */ 'D', '8', 0,
1052
  /* 1998 */ 'F', '8', 0,
1053
  /* 2001 */ 'F', '_', 'H', 'I', '8', 0,
1054
  /* 2007 */ 'F', 'C', 'R', '8', 0,
1055
  /* 2012 */ 'H', 'W', 'R', '8', 0,
1056
  /* 2017 */ 'T', '8', 0,
1057
  /* 2020 */ 'W', '8', 0,
1058
  /* 2023 */ 'C', 'O', 'P', '0', '9', 0,
1059
  /* 2029 */ 'C', 'O', 'P', '0', '1', '9', 0,
1060
  /* 2036 */ 'C', 'O', 'P', '2', '1', '9', 0,
1061
  /* 2043 */ 'C', 'O', 'P', '3', '1', '9', 0,
1062
  /* 2050 */ 'F', '1', '9', 0,
1063
  /* 2054 */ 'F', '_', 'H', 'I', '1', '9', 0,
1064
  /* 2061 */ 'F', 'C', 'R', '1', '9', 0,
1065
  /* 2067 */ 'H', 'W', 'R', '1', '9', 0,
1066
  /* 2073 */ 'W', '1', '9', 0,
1067
  /* 2077 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '1', '6', '_', '1', '9', 0,
1068
  /* 2093 */ 'C', 'O', 'P', '0', '2', '9', 0,
1069
  /* 2100 */ 'C', 'O', 'P', '2', '2', '9', 0,
1070
  /* 2107 */ 'C', 'O', 'P', '3', '2', '9', 0,
1071
  /* 2114 */ 'F', '2', '9', 0,
1072
  /* 2118 */ 'F', '_', 'H', 'I', '2', '9', 0,
1073
  /* 2125 */ 'C', 'O', 'P', '2', '9', 0,
1074
  /* 2131 */ 'F', 'C', 'R', '2', '9', 0,
1075
  /* 2137 */ 'H', 'W', 'R', '2', '9', 0,
1076
  /* 2143 */ 'W', '2', '9', 0,
1077
  /* 2147 */ 'C', 'O', 'P', '3', '9', 0,
1078
  /* 2153 */ 'D', '9', 0,
1079
  /* 2156 */ 'F', '9', 0,
1080
  /* 2159 */ 'F', '_', 'H', 'I', '9', 0,
1081
  /* 2165 */ 'F', 'C', 'R', '9', 0,
1082
  /* 2170 */ 'H', 'W', 'R', '9', 0,
1083
  /* 2175 */ 'T', '9', 0,
1084
  /* 2178 */ 'W', '9', 0,
1085
  /* 2181 */ 'R', 'A', 0,
1086
  /* 2184 */ 'P', 'C', 0,
1087
  /* 2187 */ 'D', 'S', 'P', 'E', 'F', 'I', 0,
1088
  /* 2194 */ 'Z', 'E', 'R', 'O', 0,
1089
  /* 2199 */ 'F', 'P', 0,
1090
  /* 2202 */ 'G', 'P', 0,
1091
  /* 2205 */ 'S', 'P', 0,
1092
  /* 2208 */ 'M', 'S', 'A', 'I', 'R', 0,
1093
  /* 2214 */ 'M', 'S', 'A', 'C', 'S', 'R', 0,
1094
  /* 2221 */ 'A', 'T', 0,
1095
  /* 2224 */ 'D', 'S', 'P', 'C', 'C', 'o', 'n', 'd', 0,
1096
  /* 2233 */ 'M', 'S', 'A', 'S', 'a', 'v', 'e', 0,
1097
  /* 2241 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', 0,
1098
  /* 2252 */ 'M', 'S', 'A', 'M', 'a', 'p', 0,
1099
  /* 2259 */ 'M', 'S', 'A', 'U', 'n', 'm', 'a', 'p', 0,
1100
  /* 2268 */ 'D', 'S', 'P', 'P', 'o', 's', 0,
1101
  /* 2275 */ 'M', 'S', 'A', 'A', 'c', 'c', 'e', 's', 's', 0,
1102
  /* 2285 */ 'D', 'S', 'P', 'S', 'C', 'o', 'u', 'n', 't', 0,
1103
  /* 2295 */ 'M', 'S', 'A', 'R', 'e', 'q', 'u', 'e', 's', 't', 0,
1104
  /* 2306 */ 'M', 'S', 'A', 'M', 'o', 'd', 'i', 'f', 'y', 0,
1105
  /* 2316 */ 'D', 'S', 'P', 'C', 'a', 'r', 'r', 'y', 0,
1106
};
1107
1108
extern const MCRegisterDesc MipsRegDesc[] = { // Descriptors
1109
  { 5, 0, 0, 0, 0, 0 },
1110
  { 2221, 1, 82, 1, 4033, 0 },
1111
  { 2224, 1, 1, 1, 4033, 0 },
1112
  { 2316, 1, 1, 1, 4033, 0 },
1113
  { 2187, 1, 1, 1, 4033, 0 },
1114
  { 2241, 8, 1, 2, 32, 4 },
1115
  { 2268, 1, 1, 1, 1089, 0 },
1116
  { 2285, 1, 1, 1, 1089, 0 },
1117
  { 2199, 1, 102, 1, 1089, 0 },
1118
  { 2202, 1, 104, 1, 1089, 0 },
1119
  { 2275, 1, 1, 1, 1089, 0 },
1120
  { 2214, 1, 1, 1, 1089, 0 },
1121
  { 2208, 1, 1, 1, 1089, 0 },
1122
  { 2252, 1, 1, 1, 1089, 0 },
1123
  { 2306, 1, 1, 1, 1089, 0 },
1124
  { 2295, 1, 1, 1, 1089, 0 },
1125
  { 2233, 1, 1, 1, 1089, 0 },
1126
  { 2259, 1, 1, 1, 1089, 0 },
1127
  { 2184, 1, 1, 1, 1089, 0 },
1128
  { 2181, 1, 106, 1, 1089, 0 },
1129
  { 2205, 1, 108, 1, 1089, 0 },
1130
  { 2194, 1, 110, 1, 1089, 0 },
1131
  { 179, 1, 110, 1, 1089, 0 },
1132
  { 419, 1, 110, 1, 1089, 0 },
1133
  { 611, 1, 110, 1, 1089, 0 },
1134
  { 797, 1, 110, 1, 1089, 0 },
1135
  { 182, 227, 110, 9, 1042, 10 },
1136
  { 422, 227, 1, 9, 1042, 10 },
1137
  { 614, 227, 1, 9, 1042, 10 },
1138
  { 800, 227, 1, 9, 1042, 10 },
1139
  { 1385, 238, 1, 0, 0, 2 },
1140
  { 0, 1, 1, 1, 1153, 0 },
1141
  { 240, 1, 1, 1, 1153, 0 },
1142
  { 480, 1, 1, 1, 1153, 0 },
1143
  { 666, 1, 1, 1, 1153, 0 },
1144
  { 844, 1, 1, 1, 1153, 0 },
1145
  { 1427, 1, 1, 1, 1153, 0 },
1146
  { 1581, 1, 1, 1, 1153, 0 },
1147
  { 1731, 1, 1, 1, 1153, 0 },
1148
  { 1881, 1, 1, 1, 1153, 0 },
1149
  { 2023, 1, 1, 1, 1153, 0 },
1150
  { 90, 1, 1, 1, 1153, 0 },
1151
  { 330, 1, 1, 1, 1153, 0 },
1152
  { 570, 1, 1, 1, 1153, 0 },
1153
  { 756, 1, 1, 1, 1153, 0 },
1154
  { 934, 1, 1, 1, 1153, 0 },
1155
  { 1517, 1, 1, 1, 1153, 0 },
1156
  { 1667, 1, 1, 1, 1153, 0 },
1157
  { 1817, 1, 1, 1, 1153, 0 },
1158
  { 1967, 1, 1, 1, 1153, 0 },
1159
  { 2125, 1, 1, 1, 1153, 0 },
1160
  { 157, 1, 1, 1, 1153, 0 },
1161
  { 397, 1, 1, 1, 1153, 0 },
1162
  { 605, 1, 1, 1, 1153, 0 },
1163
  { 791, 1, 1, 1, 1153, 0 },
1164
  { 956, 1, 1, 1, 1153, 0 },
1165
  { 1539, 1, 1, 1, 1153, 0 },
1166
  { 1689, 1, 1, 1, 1153, 0 },
1167
  { 1839, 1, 1, 1, 1153, 0 },
1168
  { 1989, 1, 1, 1, 1153, 0 },
1169
  { 2147, 1, 1, 1, 1153, 0 },
1170
  { 6, 1, 1, 1, 1153, 0 },
1171
  { 246, 1, 1, 1, 1153, 0 },
1172
  { 486, 1, 1, 1, 1153, 0 },
1173
  { 672, 1, 1, 1, 1153, 0 },
1174
  { 850, 1, 1, 1, 1153, 0 },
1175
  { 1433, 1, 1, 1, 1153, 0 },
1176
  { 1587, 1, 1, 1, 1153, 0 },
1177
  { 1737, 1, 1, 1, 1153, 0 },
1178
  { 1887, 1, 1, 1, 1153, 0 },
1179
  { 2029, 1, 1, 1, 1153, 0 },
1180
  { 58, 1, 1, 1, 1153, 0 },
1181
  { 298, 1, 1, 1, 1153, 0 },
1182
  { 538, 1, 1, 1, 1153, 0 },
1183
  { 724, 1, 1, 1, 1153, 0 },
1184
  { 902, 1, 1, 1, 1153, 0 },
1185
  { 1485, 1, 1, 1, 1153, 0 },
1186
  { 1635, 1, 1, 1, 1153, 0 },
1187
  { 1785, 1, 1, 1, 1153, 0 },
1188
  { 1935, 1, 1, 1, 1153, 0 },
1189
  { 2093, 1, 1, 1, 1153, 0 },
1190
  { 125, 1, 1, 1, 1153, 0 },
1191
  { 365, 1, 1, 1, 1153, 0 },
1192
  { 13, 1, 1, 1, 1153, 0 },
1193
  { 253, 1, 1, 1, 1153, 0 },
1194
  { 493, 1, 1, 1, 1153, 0 },
1195
  { 679, 1, 1, 1, 1153, 0 },
1196
  { 857, 1, 1, 1, 1153, 0 },
1197
  { 1440, 1, 1, 1, 1153, 0 },
1198
  { 1594, 1, 1, 1, 1153, 0 },
1199
  { 1744, 1, 1, 1, 1153, 0 },
1200
  { 1894, 1, 1, 1, 1153, 0 },
1201
  { 2036, 1, 1, 1, 1153, 0 },
1202
  { 65, 1, 1, 1, 1153, 0 },
1203
  { 305, 1, 1, 1, 1153, 0 },
1204
  { 545, 1, 1, 1, 1153, 0 },
1205
  { 731, 1, 1, 1, 1153, 0 },
1206
  { 909, 1, 1, 1, 1153, 0 },
1207
  { 1492, 1, 1, 1, 1153, 0 },
1208
  { 1642, 1, 1, 1, 1153, 0 },
1209
  { 1792, 1, 1, 1, 1153, 0 },
1210
  { 1942, 1, 1, 1, 1153, 0 },
1211
  { 2100, 1, 1, 1, 1153, 0 },
1212
  { 132, 1, 1, 1, 1153, 0 },
1213
  { 372, 1, 1, 1, 1153, 0 },
1214
  { 20, 1, 1, 1, 1153, 0 },
1215
  { 260, 1, 1, 1, 1153, 0 },
1216
  { 500, 1, 1, 1, 1153, 0 },
1217
  { 686, 1, 1, 1, 1153, 0 },
1218
  { 864, 1, 1, 1, 1153, 0 },
1219
  { 1447, 1, 1, 1, 1153, 0 },
1220
  { 1601, 1, 1, 1, 1153, 0 },
1221
  { 1751, 1, 1, 1, 1153, 0 },
1222
  { 1901, 1, 1, 1, 1153, 0 },
1223
  { 2043, 1, 1, 1, 1153, 0 },
1224
  { 72, 1, 1, 1, 1153, 0 },
1225
  { 312, 1, 1, 1, 1153, 0 },
1226
  { 552, 1, 1, 1, 1153, 0 },
1227
  { 738, 1, 1, 1, 1153, 0 },
1228
  { 916, 1, 1, 1, 1153, 0 },
1229
  { 1499, 1, 1, 1, 1153, 0 },
1230
  { 1649, 1, 1, 1, 1153, 0 },
1231
  { 1799, 1, 1, 1, 1153, 0 },
1232
  { 1949, 1, 1, 1, 1153, 0 },
1233
  { 2107, 1, 1, 1, 1153, 0 },
1234
  { 139, 1, 1, 1, 1153, 0 },
1235
  { 379, 1, 1, 1, 1153, 0 },
1236
  { 191, 14, 1, 9, 994, 10 },
1237
  { 431, 17, 1, 9, 994, 10 },
1238
  { 623, 20, 1, 9, 994, 10 },
1239
  { 809, 23, 1, 9, 994, 10 },
1240
  { 1396, 26, 1, 9, 994, 10 },
1241
  { 1550, 29, 1, 9, 994, 10 },
1242
  { 1700, 32, 1, 9, 994, 10 },
1243
  { 1850, 35, 1, 9, 994, 10 },
1244
  { 1995, 38, 1, 9, 994, 10 },
1245
  { 2153, 41, 1, 9, 994, 10 },
1246
  { 27, 44, 1, 9, 994, 10 },
1247
  { 267, 47, 1, 9, 994, 10 },
1248
  { 507, 50, 1, 9, 994, 10 },
1249
  { 693, 53, 1, 9, 994, 10 },
1250
  { 871, 56, 1, 9, 994, 10 },
1251
  { 1454, 59, 1, 9, 994, 10 },
1252
  { 112, 1, 144, 1, 2305, 0 },
1253
  { 352, 1, 142, 1, 2305, 0 },
1254
  { 592, 1, 140, 1, 2305, 0 },
1255
  { 778, 1, 138, 1, 2305, 0 },
1256
  { 194, 1, 159, 1, 4001, 0 },
1257
  { 434, 1, 163, 1, 4001, 0 },
1258
  { 626, 1, 163, 1, 4001, 0 },
1259
  { 812, 1, 167, 1, 4001, 0 },
1260
  { 1399, 1, 167, 1, 4001, 0 },
1261
  { 1553, 1, 171, 1, 4001, 0 },
1262
  { 1703, 1, 171, 1, 4001, 0 },
1263
  { 1853, 1, 175, 1, 4001, 0 },
1264
  { 1998, 1, 175, 1, 4001, 0 },
1265
  { 2156, 1, 179, 1, 4001, 0 },
1266
  { 31, 1, 179, 1, 4001, 0 },
1267
  { 271, 1, 183, 1, 4001, 0 },
1268
  { 511, 1, 183, 1, 4001, 0 },
1269
  { 697, 1, 187, 1, 4001, 0 },
1270
  { 875, 1, 187, 1, 4001, 0 },
1271
  { 1458, 1, 191, 1, 4001, 0 },
1272
  { 1608, 1, 191, 1, 4001, 0 },
1273
  { 1758, 1, 195, 1, 4001, 0 },
1274
  { 1908, 1, 195, 1, 4001, 0 },
1275
  { 2050, 1, 199, 1, 4001, 0 },
1276
  { 79, 1, 199, 1, 4001, 0 },
1277
  { 319, 1, 203, 1, 4001, 0 },
1278
  { 559, 1, 203, 1, 4001, 0 },
1279
  { 745, 1, 207, 1, 4001, 0 },
1280
  { 923, 1, 207, 1, 4001, 0 },
1281
  { 1506, 1, 211, 1, 4001, 0 },
1282
  { 1656, 1, 211, 1, 4001, 0 },
1283
  { 1806, 1, 215, 1, 4001, 0 },
1284
  { 1956, 1, 215, 1, 4001, 0 },
1285
  { 2114, 1, 219, 1, 4001, 0 },
1286
  { 146, 1, 219, 1, 4001, 0 },
1287
  { 386, 1, 223, 1, 4001, 0 },
1288
  { 186, 1, 1, 1, 4001, 0 },
1289
  { 426, 1, 1, 1, 4001, 0 },
1290
  { 618, 1, 1, 1, 4001, 0 },
1291
  { 804, 1, 1, 1, 4001, 0 },
1292
  { 1391, 1, 1, 1, 4001, 0 },
1293
  { 1545, 1, 1, 1, 4001, 0 },
1294
  { 1695, 1, 1, 1, 4001, 0 },
1295
  { 1845, 1, 1, 1, 4001, 0 },
1296
  { 218, 1, 1, 1, 4001, 0 },
1297
  { 458, 1, 1, 1, 4001, 0 },
1298
  { 647, 1, 1, 1, 4001, 0 },
1299
  { 825, 1, 1, 1, 4001, 0 },
1300
  { 1408, 1, 1, 1, 4001, 0 },
1301
  { 1562, 1, 1, 1, 4001, 0 },
1302
  { 1712, 1, 1, 1, 4001, 0 },
1303
  { 1862, 1, 1, 1, 4001, 0 },
1304
  { 2007, 1, 1, 1, 4001, 0 },
1305
  { 2165, 1, 1, 1, 4001, 0 },
1306
  { 42, 1, 1, 1, 4001, 0 },
1307
  { 282, 1, 1, 1, 4001, 0 },
1308
  { 522, 1, 1, 1, 4001, 0 },
1309
  { 708, 1, 1, 1, 4001, 0 },
1310
  { 886, 1, 1, 1, 4001, 0 },
1311
  { 1469, 1, 1, 1, 4001, 0 },
1312
  { 1619, 1, 1, 1, 4001, 0 },
1313
  { 1769, 1, 1, 1, 4001, 0 },
1314
  { 1919, 1, 1, 1, 4001, 0 },
1315
  { 2061, 1, 1, 1, 4001, 0 },
1316
  { 96, 1, 1, 1, 4001, 0 },
1317
  { 336, 1, 1, 1, 4001, 0 },
1318
  { 576, 1, 1, 1, 4001, 0 },
1319
  { 762, 1, 1, 1, 4001, 0 },
1320
  { 940, 1, 1, 1, 4001, 0 },
1321
  { 1523, 1, 1, 1, 4001, 0 },
1322
  { 1673, 1, 1, 1, 4001, 0 },
1323
  { 1823, 1, 1, 1, 4001, 0 },
1324
  { 1973, 1, 1, 1, 4001, 0 },
1325
  { 2131, 1, 1, 1, 4001, 0 },
1326
  { 163, 1, 1, 1, 4001, 0 },
1327
  { 403, 1, 1, 1, 4001, 0 },
1328
  { 1367, 136, 1, 0, 1184, 2 },
1329
  { 197, 1, 156, 1, 3969, 0 },
1330
  { 437, 1, 156, 1, 3969, 0 },
1331
  { 629, 1, 156, 1, 3969, 0 },
1332
  { 815, 1, 156, 1, 3969, 0 },
1333
  { 1402, 1, 156, 1, 3969, 0 },
1334
  { 1556, 1, 156, 1, 3969, 0 },
1335
  { 1706, 1, 156, 1, 3969, 0 },
1336
  { 1856, 1, 156, 1, 3969, 0 },
1337
  { 2001, 1, 156, 1, 3969, 0 },
1338
  { 2159, 1, 156, 1, 3969, 0 },
1339
  { 35, 1, 156, 1, 3969, 0 },
1340
  { 275, 1, 156, 1, 3969, 0 },
1341
  { 515, 1, 156, 1, 3969, 0 },
1342
  { 701, 1, 156, 1, 3969, 0 },
1343
  { 879, 1, 156, 1, 3969, 0 },
1344
  { 1462, 1, 156, 1, 3969, 0 },
1345
  { 1612, 1, 156, 1, 3969, 0 },
1346
  { 1762, 1, 156, 1, 3969, 0 },
1347
  { 1912, 1, 156, 1, 3969, 0 },
1348
  { 2054, 1, 156, 1, 3969, 0 },
1349
  { 83, 1, 156, 1, 3969, 0 },
1350
  { 323, 1, 156, 1, 3969, 0 },
1351
  { 563, 1, 156, 1, 3969, 0 },
1352
  { 749, 1, 156, 1, 3969, 0 },
1353
  { 927, 1, 156, 1, 3969, 0 },
1354
  { 1510, 1, 156, 1, 3969, 0 },
1355
  { 1660, 1, 156, 1, 3969, 0 },
1356
  { 1810, 1, 156, 1, 3969, 0 },
1357
  { 1960, 1, 156, 1, 3969, 0 },
1358
  { 2118, 1, 156, 1, 3969, 0 },
1359
  { 150, 1, 156, 1, 3969, 0 },
1360
  { 390, 1, 156, 1, 3969, 0 },
1361
  { 1373, 128, 1, 0, 1216, 2 },
1362
  { 199, 1, 234, 1, 1826, 0 },
1363
  { 439, 1, 134, 1, 1826, 0 },
1364
  { 631, 1, 134, 1, 1826, 0 },
1365
  { 817, 1, 134, 1, 1826, 0 },
1366
  { 223, 1, 1, 1, 3937, 0 },
1367
  { 463, 1, 1, 1, 3937, 0 },
1368
  { 652, 1, 1, 1, 3937, 0 },
1369
  { 830, 1, 1, 1, 3937, 0 },
1370
  { 1413, 1, 1, 1, 3937, 0 },
1371
  { 1567, 1, 1, 1, 3937, 0 },
1372
  { 1717, 1, 1, 1, 3937, 0 },
1373
  { 1867, 1, 1, 1, 3937, 0 },
1374
  { 2012, 1, 1, 1, 3937, 0 },
1375
  { 2170, 1, 1, 1, 3937, 0 },
1376
  { 48, 1, 1, 1, 3937, 0 },
1377
  { 288, 1, 1, 1, 3937, 0 },
1378
  { 528, 1, 1, 1, 3937, 0 },
1379
  { 714, 1, 1, 1, 3937, 0 },
1380
  { 892, 1, 1, 1, 3937, 0 },
1381
  { 1475, 1, 1, 1, 3937, 0 },
1382
  { 1625, 1, 1, 1, 3937, 0 },
1383
  { 1775, 1, 1, 1, 3937, 0 },
1384
  { 1925, 1, 1, 1, 3937, 0 },
1385
  { 2067, 1, 1, 1, 3937, 0 },
1386
  { 102, 1, 1, 1, 3937, 0 },
1387
  { 342, 1, 1, 1, 3937, 0 },
1388
  { 582, 1, 1, 1, 3937, 0 },
1389
  { 768, 1, 1, 1, 3937, 0 },
1390
  { 946, 1, 1, 1, 3937, 0 },
1391
  { 1529, 1, 1, 1, 3937, 0 },
1392
  { 1679, 1, 1, 1, 3937, 0 },
1393
  { 1829, 1, 1, 1, 3937, 0 },
1394
  { 1979, 1, 1, 1, 3937, 0 },
1395
  { 2137, 1, 1, 1, 3937, 0 },
1396
  { 169, 1, 1, 1, 3937, 0 },
1397
  { 409, 1, 1, 1, 3937, 0 },
1398
  { 203, 1, 100, 1, 3937, 0 },
1399
  { 443, 1, 100, 1, 3937, 0 },
1400
  { 211, 1, 230, 1, 1794, 0 },
1401
  { 451, 1, 126, 1, 1794, 0 },
1402
  { 640, 1, 126, 1, 1794, 0 },
1403
  { 821, 1, 126, 1, 1794, 0 },
1404
  { 206, 1, 1, 1, 3905, 0 },
1405
  { 446, 1, 1, 1, 3905, 0 },
1406
  { 635, 1, 1, 1, 3905, 0 },
1407
  { 215, 1, 1, 1, 3905, 0 },
1408
  { 455, 1, 1, 1, 3905, 0 },
1409
  { 644, 1, 1, 1, 3905, 0 },
1410
  { 1353, 124, 1, 0, 1248, 2 },
1411
  { 228, 1, 98, 1, 3873, 0 },
1412
  { 468, 1, 98, 1, 3873, 0 },
1413
  { 657, 1, 98, 1, 3873, 0 },
1414
  { 835, 1, 98, 1, 3873, 0 },
1415
  { 1418, 1, 98, 1, 3873, 0 },
1416
  { 1572, 1, 98, 1, 3873, 0 },
1417
  { 1722, 1, 98, 1, 3873, 0 },
1418
  { 1872, 1, 98, 1, 3873, 0 },
1419
  { 1379, 122, 1, 0, 1280, 2 },
1420
  { 231, 1, 96, 1, 3841, 0 },
1421
  { 471, 1, 96, 1, 3841, 0 },
1422
  { 660, 1, 96, 1, 3841, 0 },
1423
  { 838, 1, 96, 1, 3841, 0 },
1424
  { 1421, 1, 96, 1, 3841, 0 },
1425
  { 1575, 1, 96, 1, 3841, 0 },
1426
  { 1725, 1, 96, 1, 3841, 0 },
1427
  { 1875, 1, 96, 1, 3841, 0 },
1428
  { 2017, 1, 96, 1, 3841, 0 },
1429
  { 2175, 1, 96, 1, 3841, 0 },
1430
  { 234, 1, 96, 1, 3841, 0 },
1431
  { 474, 1, 96, 1, 3841, 0 },
1432
  { 237, 92, 1, 8, 1425, 10 },
1433
  { 477, 92, 1, 8, 1425, 10 },
1434
  { 663, 92, 1, 8, 1425, 10 },
1435
  { 841, 92, 1, 8, 1425, 10 },
1436
  { 1424, 92, 1, 8, 1425, 10 },
1437
  { 1578, 92, 1, 8, 1425, 10 },
1438
  { 1728, 92, 1, 8, 1425, 10 },
1439
  { 1878, 92, 1, 8, 1425, 10 },
1440
  { 2020, 92, 1, 8, 1425, 10 },
1441
  { 2178, 92, 1, 8, 1425, 10 },
1442
  { 54, 92, 1, 8, 1425, 10 },
1443
  { 294, 92, 1, 8, 1425, 10 },
1444
  { 534, 92, 1, 8, 1425, 10 },
1445
  { 720, 92, 1, 8, 1425, 10 },
1446
  { 898, 92, 1, 8, 1425, 10 },
1447
  { 1481, 92, 1, 8, 1425, 10 },
1448
  { 1631, 92, 1, 8, 1425, 10 },
1449
  { 1781, 92, 1, 8, 1425, 10 },
1450
  { 1931, 92, 1, 8, 1425, 10 },
1451
  { 2073, 92, 1, 8, 1425, 10 },
1452
  { 108, 92, 1, 8, 1425, 10 },
1453
  { 348, 92, 1, 8, 1425, 10 },
1454
  { 588, 92, 1, 8, 1425, 10 },
1455
  { 774, 92, 1, 8, 1425, 10 },
1456
  { 952, 92, 1, 8, 1425, 10 },
1457
  { 1535, 92, 1, 8, 1425, 10 },
1458
  { 1685, 92, 1, 8, 1425, 10 },
1459
  { 1835, 92, 1, 8, 1425, 10 },
1460
  { 1985, 92, 1, 8, 1425, 10 },
1461
  { 2143, 92, 1, 8, 1425, 10 },
1462
  { 175, 92, 1, 8, 1425, 10 },
1463
  { 415, 92, 1, 8, 1425, 10 },
1464
  { 1359, 118, 1, 0, 1921, 2 },
1465
  { 983, 118, 1, 0, 1921, 2 },
1466
  { 1061, 118, 1, 0, 1921, 2 },
1467
  { 1111, 118, 1, 0, 1921, 2 },
1468
  { 1149, 118, 1, 0, 1921, 2 },
1469
  { 989, 130, 1, 12, 656, 10 },
1470
  { 996, 93, 157, 9, 1377, 10 },
1471
  { 1067, 93, 157, 9, 1377, 10 },
1472
  { 1117, 93, 157, 9, 1377, 10 },
1473
  { 1155, 93, 157, 9, 1377, 10 },
1474
  { 1187, 93, 157, 9, 1377, 10 },
1475
  { 1219, 93, 157, 9, 1377, 10 },
1476
  { 1251, 93, 157, 9, 1377, 10 },
1477
  { 1283, 93, 157, 9, 1377, 10 },
1478
  { 1315, 93, 157, 9, 1377, 10 },
1479
  { 1341, 93, 157, 9, 1377, 10 },
1480
  { 962, 93, 157, 9, 1377, 10 },
1481
  { 1040, 93, 157, 9, 1377, 10 },
1482
  { 1097, 93, 157, 9, 1377, 10 },
1483
  { 1135, 93, 157, 9, 1377, 10 },
1484
  { 1173, 93, 157, 9, 1377, 10 },
1485
  { 1205, 93, 157, 9, 1377, 10 },
1486
  { 1237, 93, 157, 9, 1377, 10 },
1487
  { 1269, 93, 157, 9, 1377, 10 },
1488
  { 1301, 93, 157, 9, 1377, 10 },
1489
  { 1327, 93, 157, 9, 1377, 10 },
1490
  { 969, 93, 157, 9, 1377, 10 },
1491
  { 1047, 93, 157, 9, 1377, 10 },
1492
  { 1104, 93, 157, 9, 1377, 10 },
1493
  { 1142, 93, 157, 9, 1377, 10 },
1494
  { 1180, 93, 157, 9, 1377, 10 },
1495
  { 1212, 93, 157, 9, 1377, 10 },
1496
  { 1244, 93, 157, 9, 1377, 10 },
1497
  { 1276, 93, 157, 9, 1377, 10 },
1498
  { 1308, 93, 157, 9, 1377, 10 },
1499
  { 1334, 93, 157, 9, 1377, 10 },
1500
  { 976, 93, 157, 9, 1377, 10 },
1501
  { 1054, 93, 157, 9, 1377, 10 },
1502
  { 2077, 1, 116, 1, 1120, 0 },
1503
  { 1002, 138, 236, 0, 1344, 2 },
1504
  { 1009, 150, 1, 0, 2337, 2 },
1505
  { 1073, 150, 1, 0, 2337, 2 },
1506
  { 1015, 150, 232, 0, 1312, 2 },
1507
  { 1022, 152, 1, 0, 2369, 2 },
1508
  { 1079, 152, 1, 0, 2369, 2 },
1509
  { 1123, 152, 1, 0, 2369, 2 },
1510
  { 1161, 152, 1, 0, 2369, 2 },
1511
  { 1193, 152, 1, 0, 2369, 2 },
1512
  { 1225, 152, 1, 0, 2369, 2 },
1513
  { 1257, 152, 1, 0, 2369, 2 },
1514
  { 1289, 152, 1, 0, 2369, 2 },
1515
  { 1028, 154, 1, 0, 2369, 2 },
1516
  { 1085, 154, 1, 0, 2369, 2 },
1517
  { 1129, 154, 1, 0, 2369, 2 },
1518
  { 1167, 154, 1, 0, 2369, 2 },
1519
  { 1199, 154, 1, 0, 2369, 2 },
1520
  { 1231, 154, 1, 0, 2369, 2 },
1521
  { 1263, 154, 1, 0, 2369, 2 },
1522
  { 1295, 154, 1, 0, 2369, 2 },
1523
  { 1321, 154, 1, 0, 2369, 2 },
1524
  { 1347, 154, 1, 0, 2369, 2 },
1525
  { 1034, 154, 1, 0, 2369, 2 },
1526
  { 1091, 154, 1, 0, 2369, 2 },
1527
};
1528
1529
extern const MCPhysReg MipsRegUnitRoots[][2] = {
1530
  { Mips::AT },
1531
  { Mips::DSPCCond },
1532
  { Mips::DSPCarry },
1533
  { Mips::DSPEFI },
1534
  { Mips::DSPOutFlag16_19 },
1535
  { Mips::DSPOutFlag20 },
1536
  { Mips::DSPOutFlag21 },
1537
  { Mips::DSPOutFlag22 },
1538
  { Mips::DSPOutFlag23 },
1539
  { Mips::DSPPos },
1540
  { Mips::DSPSCount },
1541
  { Mips::FP },
1542
  { Mips::GP },
1543
  { Mips::MSAAccess },
1544
  { Mips::MSACSR },
1545
  { Mips::MSAIR },
1546
  { Mips::MSAMap },
1547
  { Mips::MSAModify },
1548
  { Mips::MSARequest },
1549
  { Mips::MSASave },
1550
  { Mips::MSAUnmap },
1551
  { Mips::PC },
1552
  { Mips::RA },
1553
  { Mips::SP },
1554
  { Mips::ZERO },
1555
  { Mips::A0 },
1556
  { Mips::A1 },
1557
  { Mips::A2 },
1558
  { Mips::A3 },
1559
  { Mips::LO0 },
1560
  { Mips::HI0 },
1561
  { Mips::LO1 },
1562
  { Mips::HI1 },
1563
  { Mips::LO2 },
1564
  { Mips::HI2 },
1565
  { Mips::LO3 },
1566
  { Mips::HI3 },
1567
  { Mips::COP00 },
1568
  { Mips::COP01 },
1569
  { Mips::COP02 },
1570
  { Mips::COP03 },
1571
  { Mips::COP04 },
1572
  { Mips::COP05 },
1573
  { Mips::COP06 },
1574
  { Mips::COP07 },
1575
  { Mips::COP08 },
1576
  { Mips::COP09 },
1577
  { Mips::COP20 },
1578
  { Mips::COP21 },
1579
  { Mips::COP22 },
1580
  { Mips::COP23 },
1581
  { Mips::COP24 },
1582
  { Mips::COP25 },
1583
  { Mips::COP26 },
1584
  { Mips::COP27 },
1585
  { Mips::COP28 },
1586
  { Mips::COP29 },
1587
  { Mips::COP30 },
1588
  { Mips::COP31 },
1589
  { Mips::COP32 },
1590
  { Mips::COP33 },
1591
  { Mips::COP34 },
1592
  { Mips::COP35 },
1593
  { Mips::COP36 },
1594
  { Mips::COP37 },
1595
  { Mips::COP38 },
1596
  { Mips::COP39 },
1597
  { Mips::COP010 },
1598
  { Mips::COP011 },
1599
  { Mips::COP012 },
1600
  { Mips::COP013 },
1601
  { Mips::COP014 },
1602
  { Mips::COP015 },
1603
  { Mips::COP016 },
1604
  { Mips::COP017 },
1605
  { Mips::COP018 },
1606
  { Mips::COP019 },
1607
  { Mips::COP020 },
1608
  { Mips::COP021 },
1609
  { Mips::COP022 },
1610
  { Mips::COP023 },
1611
  { Mips::COP024 },
1612
  { Mips::COP025 },
1613
  { Mips::COP026 },
1614
  { Mips::COP027 },
1615
  { Mips::COP028 },
1616
  { Mips::COP029 },
1617
  { Mips::COP030 },
1618
  { Mips::COP031 },
1619
  { Mips::COP210 },
1620
  { Mips::COP211 },
1621
  { Mips::COP212 },
1622
  { Mips::COP213 },
1623
  { Mips::COP214 },
1624
  { Mips::COP215 },
1625
  { Mips::COP216 },
1626
  { Mips::COP217 },
1627
  { Mips::COP218 },
1628
  { Mips::COP219 },
1629
  { Mips::COP220 },
1630
  { Mips::COP221 },
1631
  { Mips::COP222 },
1632
  { Mips::COP223 },
1633
  { Mips::COP224 },
1634
  { Mips::COP225 },
1635
  { Mips::COP226 },
1636
  { Mips::COP227 },
1637
  { Mips::COP228 },
1638
  { Mips::COP229 },
1639
  { Mips::COP230 },
1640
  { Mips::COP231 },
1641
  { Mips::COP310 },
1642
  { Mips::COP311 },
1643
  { Mips::COP312 },
1644
  { Mips::COP313 },
1645
  { Mips::COP314 },
1646
  { Mips::COP315 },
1647
  { Mips::COP316 },
1648
  { Mips::COP317 },
1649
  { Mips::COP318 },
1650
  { Mips::COP319 },
1651
  { Mips::COP320 },
1652
  { Mips::COP321 },
1653
  { Mips::COP322 },
1654
  { Mips::COP323 },
1655
  { Mips::COP324 },
1656
  { Mips::COP325 },
1657
  { Mips::COP326 },
1658
  { Mips::COP327 },
1659
  { Mips::COP328 },
1660
  { Mips::COP329 },
1661
  { Mips::COP330 },
1662
  { Mips::COP331 },
1663
  { Mips::F0 },
1664
  { Mips::F1 },
1665
  { Mips::F2 },
1666
  { Mips::F3 },
1667
  { Mips::F4 },
1668
  { Mips::F5 },
1669
  { Mips::F6 },
1670
  { Mips::F7 },
1671
  { Mips::F8 },
1672
  { Mips::F9 },
1673
  { Mips::F10 },
1674
  { Mips::F11 },
1675
  { Mips::F12 },
1676
  { Mips::F13 },
1677
  { Mips::F14 },
1678
  { Mips::F15 },
1679
  { Mips::F16 },
1680
  { Mips::F17 },
1681
  { Mips::F18 },
1682
  { Mips::F19 },
1683
  { Mips::F20 },
1684
  { Mips::F21 },
1685
  { Mips::F22 },
1686
  { Mips::F23 },
1687
  { Mips::F24 },
1688
  { Mips::F25 },
1689
  { Mips::F26 },
1690
  { Mips::F27 },
1691
  { Mips::F28 },
1692
  { Mips::F29 },
1693
  { Mips::F30 },
1694
  { Mips::F31 },
1695
  { Mips::FCC0 },
1696
  { Mips::FCC1 },
1697
  { Mips::FCC2 },
1698
  { Mips::FCC3 },
1699
  { Mips::FCC4 },
1700
  { Mips::FCC5 },
1701
  { Mips::FCC6 },
1702
  { Mips::FCC7 },
1703
  { Mips::FCR0 },
1704
  { Mips::FCR1 },
1705
  { Mips::FCR2 },
1706
  { Mips::FCR3 },
1707
  { Mips::FCR4 },
1708
  { Mips::FCR5 },
1709
  { Mips::FCR6 },
1710
  { Mips::FCR7 },
1711
  { Mips::FCR8 },
1712
  { Mips::FCR9 },
1713
  { Mips::FCR10 },
1714
  { Mips::FCR11 },
1715
  { Mips::FCR12 },
1716
  { Mips::FCR13 },
1717
  { Mips::FCR14 },
1718
  { Mips::FCR15 },
1719
  { Mips::FCR16 },
1720
  { Mips::FCR17 },
1721
  { Mips::FCR18 },
1722
  { Mips::FCR19 },
1723
  { Mips::FCR20 },
1724
  { Mips::FCR21 },
1725
  { Mips::FCR22 },
1726
  { Mips::FCR23 },
1727
  { Mips::FCR24 },
1728
  { Mips::FCR25 },
1729
  { Mips::FCR26 },
1730
  { Mips::FCR27 },
1731
  { Mips::FCR28 },
1732
  { Mips::FCR29 },
1733
  { Mips::FCR30 },
1734
  { Mips::FCR31 },
1735
  { Mips::F_HI0 },
1736
  { Mips::F_HI1 },
1737
  { Mips::F_HI2 },
1738
  { Mips::F_HI3 },
1739
  { Mips::F_HI4 },
1740
  { Mips::F_HI5 },
1741
  { Mips::F_HI6 },
1742
  { Mips::F_HI7 },
1743
  { Mips::F_HI8 },
1744
  { Mips::F_HI9 },
1745
  { Mips::F_HI10 },
1746
  { Mips::F_HI11 },
1747
  { Mips::F_HI12 },
1748
  { Mips::F_HI13 },
1749
  { Mips::F_HI14 },
1750
  { Mips::F_HI15 },
1751
  { Mips::F_HI16 },
1752
  { Mips::F_HI17 },
1753
  { Mips::F_HI18 },
1754
  { Mips::F_HI19 },
1755
  { Mips::F_HI20 },
1756
  { Mips::F_HI21 },
1757
  { Mips::F_HI22 },
1758
  { Mips::F_HI23 },
1759
  { Mips::F_HI24 },
1760
  { Mips::F_HI25 },
1761
  { Mips::F_HI26 },
1762
  { Mips::F_HI27 },
1763
  { Mips::F_HI28 },
1764
  { Mips::F_HI29 },
1765
  { Mips::F_HI30 },
1766
  { Mips::F_HI31 },
1767
  { Mips::HWR0 },
1768
  { Mips::HWR1 },
1769
  { Mips::HWR2 },
1770
  { Mips::HWR3 },
1771
  { Mips::HWR4 },
1772
  { Mips::HWR5 },
1773
  { Mips::HWR6 },
1774
  { Mips::HWR7 },
1775
  { Mips::HWR8 },
1776
  { Mips::HWR9 },
1777
  { Mips::HWR10 },
1778
  { Mips::HWR11 },
1779
  { Mips::HWR12 },
1780
  { Mips::HWR13 },
1781
  { Mips::HWR14 },
1782
  { Mips::HWR15 },
1783
  { Mips::HWR16 },
1784
  { Mips::HWR17 },
1785
  { Mips::HWR18 },
1786
  { Mips::HWR19 },
1787
  { Mips::HWR20 },
1788
  { Mips::HWR21 },
1789
  { Mips::HWR22 },
1790
  { Mips::HWR23 },
1791
  { Mips::HWR24 },
1792
  { Mips::HWR25 },
1793
  { Mips::HWR26 },
1794
  { Mips::HWR27 },
1795
  { Mips::HWR28 },
1796
  { Mips::HWR29 },
1797
  { Mips::HWR30 },
1798
  { Mips::HWR31 },
1799
  { Mips::K0 },
1800
  { Mips::K1 },
1801
  { Mips::MPL0 },
1802
  { Mips::MPL1 },
1803
  { Mips::MPL2 },
1804
  { Mips::P0 },
1805
  { Mips::P1 },
1806
  { Mips::P2 },
1807
  { Mips::S0 },
1808
  { Mips::S1 },
1809
  { Mips::S2 },
1810
  { Mips::S3 },
1811
  { Mips::S4 },
1812
  { Mips::S5 },
1813
  { Mips::S6 },
1814
  { Mips::S7 },
1815
  { Mips::T0 },
1816
  { Mips::T1 },
1817
  { Mips::T2 },
1818
  { Mips::T3 },
1819
  { Mips::T4 },
1820
  { Mips::T5 },
1821
  { Mips::T6 },
1822
  { Mips::T7 },
1823
  { Mips::T8 },
1824
  { Mips::T9 },
1825
  { Mips::V0 },
1826
  { Mips::V1 },
1827
};
1828
1829
namespace {     // Register classes...
1830
  // MSA128F16 Register Class...
1831
  const MCPhysReg MSA128F16[] = {
1832
    Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31, 
1833
  };
1834
1835
  // MSA128F16 Bit set.
1836
  const uint8_t MSA128F16Bits[] = {
1837
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
1838
  };
1839
1840
  // MSA128F16_with_sub_64_in_OddSP Register Class...
1841
  const MCPhysReg MSA128F16_with_sub_64_in_OddSP[] = {
1842
    Mips::W1, Mips::W3, Mips::W5, Mips::W7, Mips::W9, Mips::W11, Mips::W13, Mips::W15, Mips::W17, Mips::W19, Mips::W21, Mips::W23, Mips::W25, Mips::W27, Mips::W29, Mips::W31, 
1843
  };
1844
1845
  // MSA128F16_with_sub_64_in_OddSP Bit set.
1846
  const uint8_t MSA128F16_with_sub_64_in_OddSPBits[] = {
1847
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05, 
1848
  };
1849
1850
  // OddSP Register Class...
1851
  const MCPhysReg OddSP[] = {
1852
    Mips::F1, Mips::F3, Mips::F5, Mips::F7, Mips::F9, Mips::F11, Mips::F13, Mips::F15, Mips::F17, Mips::F19, Mips::F21, Mips::F23, Mips::F25, Mips::F27, Mips::F29, Mips::F31, Mips::F_HI1, Mips::F_HI3, Mips::F_HI5, Mips::F_HI7, Mips::F_HI9, Mips::F_HI11, Mips::F_HI13, Mips::F_HI15, Mips::F_HI17, Mips::F_HI19, Mips::F_HI21, Mips::F_HI23, Mips::F_HI25, Mips::F_HI27, Mips::F_HI29, Mips::F_HI31, Mips::D1, Mips::D3, Mips::D5, Mips::D7, Mips::D9, Mips::D11, Mips::D13, Mips::D15, Mips::D1_64, Mips::D3_64, Mips::D5_64, Mips::D7_64, Mips::D9_64, Mips::D11_64, Mips::D13_64, Mips::D15_64, Mips::D17_64, Mips::D19_64, Mips::D21_64, Mips::D23_64, Mips::D25_64, Mips::D27_64, Mips::D29_64, Mips::D31_64, 
1853
  };
1854
1855
  // OddSP Bit set.
1856
  const uint8_t OddSPBits[] = {
1857
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x50, 0x55, 0x55, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, 
1858
  };
1859
1860
  // CCR Register Class...
1861
  const MCPhysReg CCR[] = {
1862
    Mips::FCR0, Mips::FCR1, Mips::FCR2, Mips::FCR3, Mips::FCR4, Mips::FCR5, Mips::FCR6, Mips::FCR7, Mips::FCR8, Mips::FCR9, Mips::FCR10, Mips::FCR11, Mips::FCR12, Mips::FCR13, Mips::FCR14, Mips::FCR15, Mips::FCR16, Mips::FCR17, Mips::FCR18, Mips::FCR19, Mips::FCR20, Mips::FCR21, Mips::FCR22, Mips::FCR23, Mips::FCR24, Mips::FCR25, Mips::FCR26, Mips::FCR27, Mips::FCR28, Mips::FCR29, Mips::FCR30, Mips::FCR31, 
1863
  };
1864
1865
  // CCR Bit set.
1866
  const uint8_t CCRBits[] = {
1867
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
1868
  };
1869
1870
  // COP0 Register Class...
1871
  const MCPhysReg COP0[] = {
1872
    Mips::COP00, Mips::COP01, Mips::COP02, Mips::COP03, Mips::COP04, Mips::COP05, Mips::COP06, Mips::COP07, Mips::COP08, Mips::COP09, Mips::COP010, Mips::COP011, Mips::COP012, Mips::COP013, Mips::COP014, Mips::COP015, Mips::COP016, Mips::COP017, Mips::COP018, Mips::COP019, Mips::COP020, Mips::COP021, Mips::COP022, Mips::COP023, Mips::COP024, Mips::COP025, Mips::COP026, Mips::COP027, Mips::COP028, Mips::COP029, Mips::COP030, Mips::COP031, 
1873
  };
1874
1875
  // COP0 Bit set.
1876
  const uint8_t COP0Bits[] = {
1877
    0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0x00, 0xe0, 0xff, 0xff, 0x07, 
1878
  };
1879
1880
  // COP2 Register Class...
1881
  const MCPhysReg COP2[] = {
1882
    Mips::COP20, Mips::COP21, Mips::COP22, Mips::COP23, Mips::COP24, Mips::COP25, Mips::COP26, Mips::COP27, Mips::COP28, Mips::COP29, Mips::COP210, Mips::COP211, Mips::COP212, Mips::COP213, Mips::COP214, Mips::COP215, Mips::COP216, Mips::COP217, Mips::COP218, Mips::COP219, Mips::COP220, Mips::COP221, Mips::COP222, Mips::COP223, Mips::COP224, Mips::COP225, Mips::COP226, Mips::COP227, Mips::COP228, Mips::COP229, Mips::COP230, Mips::COP231, 
1883
  };
1884
1885
  // COP2 Bit set.
1886
  const uint8_t COP2Bits[] = {
1887
    0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01, 
1888
  };
1889
1890
  // COP3 Register Class...
1891
  const MCPhysReg COP3[] = {
1892
    Mips::COP30, Mips::COP31, Mips::COP32, Mips::COP33, Mips::COP34, Mips::COP35, Mips::COP36, Mips::COP37, Mips::COP38, Mips::COP39, Mips::COP310, Mips::COP311, Mips::COP312, Mips::COP313, Mips::COP314, Mips::COP315, Mips::COP316, Mips::COP317, Mips::COP318, Mips::COP319, Mips::COP320, Mips::COP321, Mips::COP322, Mips::COP323, Mips::COP324, Mips::COP325, Mips::COP326, Mips::COP327, Mips::COP328, Mips::COP329, Mips::COP330, Mips::COP331, 
1893
  };
1894
1895
  // COP3 Bit set.
1896
  const uint8_t COP3Bits[] = {
1897
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x7f, 
1898
  };
1899
1900
  // DSPR Register Class...
1901
  const MCPhysReg DSPR[] = {
1902
    Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA, 
1903
  };
1904
1905
  // DSPR Bit set.
1906
  const uint8_t DSPRBits[] = {
1907
    0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07, 
1908
  };
1909
1910
  // FGR32 Register Class...
1911
  const MCPhysReg FGR32[] = {
1912
    Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31, 
1913
  };
1914
1915
  // FGR32 Bit set.
1916
  const uint8_t FGR32Bits[] = {
1917
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
1918
  };
1919
1920
  // FGRCC Register Class...
1921
  const MCPhysReg FGRCC[] = {
1922
    Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31, 
1923
  };
1924
1925
  // FGRCC Bit set.
1926
  const uint8_t FGRCCBits[] = {
1927
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
1928
  };
1929
1930
  // FGRH32 Register Class...
1931
  const MCPhysReg FGRH32[] = {
1932
    Mips::F_HI0, Mips::F_HI1, Mips::F_HI2, Mips::F_HI3, Mips::F_HI4, Mips::F_HI5, Mips::F_HI6, Mips::F_HI7, Mips::F_HI8, Mips::F_HI9, Mips::F_HI10, Mips::F_HI11, Mips::F_HI12, Mips::F_HI13, Mips::F_HI14, Mips::F_HI15, Mips::F_HI16, Mips::F_HI17, Mips::F_HI18, Mips::F_HI19, Mips::F_HI20, Mips::F_HI21, Mips::F_HI22, Mips::F_HI23, Mips::F_HI24, Mips::F_HI25, Mips::F_HI26, Mips::F_HI27, Mips::F_HI28, Mips::F_HI29, Mips::F_HI30, Mips::F_HI31, 
1933
  };
1934
1935
  // FGRH32 Bit set.
1936
  const uint8_t FGRH32Bits[] = {
1937
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
1938
  };
1939
1940
  // GPR32 Register Class...
1941
  const MCPhysReg GPR32[] = {
1942
    Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA, 
1943
  };
1944
1945
  // GPR32 Bit set.
1946
  const uint8_t GPR32Bits[] = {
1947
    0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07, 
1948
  };
1949
1950
  // HWRegs Register Class...
1951
  const MCPhysReg HWRegs[] = {
1952
    Mips::HWR0, Mips::HWR1, Mips::HWR2, Mips::HWR3, Mips::HWR4, Mips::HWR5, Mips::HWR6, Mips::HWR7, Mips::HWR8, Mips::HWR9, Mips::HWR10, Mips::HWR11, Mips::HWR12, Mips::HWR13, Mips::HWR14, Mips::HWR15, Mips::HWR16, Mips::HWR17, Mips::HWR18, Mips::HWR19, Mips::HWR20, Mips::HWR21, Mips::HWR22, Mips::HWR23, Mips::HWR24, Mips::HWR25, Mips::HWR26, Mips::HWR27, Mips::HWR28, Mips::HWR29, Mips::HWR30, Mips::HWR31, 
1953
  };
1954
1955
  // HWRegs Bit set.
1956
  const uint8_t HWRegsBits[] = {
1957
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
1958
  };
1959
1960
  // GPR32NONZERO Register Class...
1961
  const MCPhysReg GPR32NONZERO[] = {
1962
    Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA, 
1963
  };
1964
1965
  // GPR32NONZERO Bit set.
1966
  const uint8_t GPR32NONZEROBits[] = {
1967
    0x02, 0x03, 0xd8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07, 
1968
  };
1969
1970
  // OddSP_with_sub_hi Register Class...
1971
  const MCPhysReg OddSP_with_sub_hi[] = {
1972
    Mips::D1, Mips::D3, Mips::D5, Mips::D7, Mips::D9, Mips::D11, Mips::D13, Mips::D15, Mips::D1_64, Mips::D3_64, Mips::D5_64, Mips::D7_64, Mips::D9_64, Mips::D11_64, Mips::D13_64, Mips::D15_64, Mips::D17_64, Mips::D19_64, Mips::D21_64, Mips::D23_64, Mips::D25_64, Mips::D27_64, Mips::D29_64, Mips::D31_64, 
1973
  };
1974
1975
  // OddSP_with_sub_hi Bit set.
1976
  const uint8_t OddSP_with_sub_hiBits[] = {
1977
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, 
1978
  };
1979
1980
  // FGR32_and_OddSP Register Class...
1981
  const MCPhysReg FGR32_and_OddSP[] = {
1982
    Mips::F1, Mips::F3, Mips::F5, Mips::F7, Mips::F9, Mips::F11, Mips::F13, Mips::F15, Mips::F17, Mips::F19, Mips::F21, Mips::F23, Mips::F25, Mips::F27, Mips::F29, Mips::F31, 
1983
  };
1984
1985
  // FGR32_and_OddSP Bit set.
1986
  const uint8_t FGR32_and_OddSPBits[] = {
1987
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05, 
1988
  };
1989
1990
  // FGRH32_and_OddSP Register Class...
1991
  const MCPhysReg FGRH32_and_OddSP[] = {
1992
    Mips::F_HI1, Mips::F_HI3, Mips::F_HI5, Mips::F_HI7, Mips::F_HI9, Mips::F_HI11, Mips::F_HI13, Mips::F_HI15, Mips::F_HI17, Mips::F_HI19, Mips::F_HI21, Mips::F_HI23, Mips::F_HI25, Mips::F_HI27, Mips::F_HI29, Mips::F_HI31, 
1993
  };
1994
1995
  // FGRH32_and_OddSP Bit set.
1996
  const uint8_t FGRH32_and_OddSPBits[] = {
1997
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, 
1998
  };
1999
2000
  // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Register Class...
2001
  const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGRH32[] = {
2002
    Mips::D1_64, Mips::D3_64, Mips::D5_64, Mips::D7_64, Mips::D9_64, Mips::D11_64, Mips::D13_64, Mips::D15_64, Mips::D17_64, Mips::D19_64, Mips::D21_64, Mips::D23_64, Mips::D25_64, Mips::D27_64, Mips::D29_64, Mips::D31_64, 
2003
  };
2004
2005
  // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Bit set.
2006
  const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits[] = {
2007
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, 
2008
  };
2009
2010
  // CPU16RegsPlusSP Register Class...
2011
  const MCPhysReg CPU16RegsPlusSP[] = {
2012
    Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1, Mips::SP, 
2013
  };
2014
2015
  // CPU16RegsPlusSP Bit set.
2016
  const uint8_t CPU16RegsPlusSPBits[] = {
2017
    0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, 
2018
  };
2019
2020
  // CPU16Regs Register Class...
2021
  const MCPhysReg CPU16Regs[] = {
2022
    Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1, 
2023
  };
2024
2025
  // CPU16Regs Bit set.
2026
  const uint8_t CPU16RegsBits[] = {
2027
    0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, 
2028
  };
2029
2030
  // FCC Register Class...
2031
  const MCPhysReg FCC[] = {
2032
    Mips::FCC0, Mips::FCC1, Mips::FCC2, Mips::FCC3, Mips::FCC4, Mips::FCC5, Mips::FCC6, Mips::FCC7, 
2033
  };
2034
2035
  // FCC Bit set.
2036
  const uint8_t FCCBits[] = {
2037
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 
2038
  };
2039
2040
  // GPRMM16 Register Class...
2041
  const MCPhysReg GPRMM16[] = {
2042
    Mips::S0, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, 
2043
  };
2044
2045
  // GPRMM16 Bit set.
2046
  const uint8_t GPRMM16Bits[] = {
2047
    0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, 
2048
  };
2049
2050
  // GPRMM16MoveP Register Class...
2051
  const MCPhysReg GPRMM16MoveP[] = {
2052
    Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4, 
2053
  };
2054
2055
  // GPRMM16MoveP Bit set.
2056
  const uint8_t GPRMM16MovePBits[] = {
2057
    0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06, 
2058
  };
2059
2060
  // GPRMM16Zero Register Class...
2061
  const MCPhysReg GPRMM16Zero[] = {
2062
    Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, 
2063
  };
2064
2065
  // GPRMM16Zero Bit set.
2066
  const uint8_t GPRMM16ZeroBits[] = {
2067
    0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, 
2068
  };
2069
2070
  // MSACtrl Register Class...
2071
  const MCPhysReg MSACtrl[] = {
2072
    Mips::MSAIR, Mips::MSACSR, Mips::MSAAccess, Mips::MSASave, Mips::MSAModify, Mips::MSARequest, Mips::MSAMap, Mips::MSAUnmap, 
2073
  };
2074
2075
  // MSACtrl Bit set.
2076
  const uint8_t MSACtrlBits[] = {
2077
    0x00, 0xfc, 0x03, 
2078
  };
2079
2080
  // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Register Class...
2081
  const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGR32[] = {
2082
    Mips::D1, Mips::D3, Mips::D5, Mips::D7, Mips::D9, Mips::D11, Mips::D13, Mips::D15, 
2083
  };
2084
2085
  // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Bit set.
2086
  const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits[] = {
2087
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 
2088
  };
2089
2090
  // CPU16Regs_and_GPRMM16Zero Register Class...
2091
  const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = {
2092
    Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, 
2093
  };
2094
2095
  // CPU16Regs_and_GPRMM16Zero Bit set.
2096
  const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = {
2097
    0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, 
2098
  };
2099
2100
  // GPR32NONZERO_and_GPRMM16MoveP Register Class...
2101
  const MCPhysReg GPR32NONZERO_and_GPRMM16MoveP[] = {
2102
    Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4, 
2103
  };
2104
2105
  // GPR32NONZERO_and_GPRMM16MoveP Bit set.
2106
  const uint8_t GPR32NONZERO_and_GPRMM16MovePBits[] = {
2107
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06, 
2108
  };
2109
2110
  // GPRMM16MovePPairSecond Register Class...
2111
  const MCPhysReg GPRMM16MovePPairSecond[] = {
2112
    Mips::A1, Mips::A2, Mips::A3, Mips::S5, Mips::S6, 
2113
  };
2114
2115
  // GPRMM16MovePPairSecond Bit set.
2116
  const uint8_t GPRMM16MovePPairSecondBits[] = {
2117
    0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 
2118
  };
2119
2120
  // CPU16Regs_and_GPRMM16MoveP Register Class...
2121
  const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = {
2122
    Mips::S1, Mips::V0, Mips::V1, Mips::S0, 
2123
  };
2124
2125
  // CPU16Regs_and_GPRMM16MoveP Bit set.
2126
  const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = {
2127
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, 
2128
  };
2129
2130
  // GPRMM16MoveP_and_GPRMM16Zero Register Class...
2131
  const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = {
2132
    Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, 
2133
  };
2134
2135
  // GPRMM16MoveP_and_GPRMM16Zero Bit set.
2136
  const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
2137
    0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, 
2138
  };
2139
2140
  // HI32DSP Register Class...
2141
  const MCPhysReg HI32DSP[] = {
2142
    Mips::HI0, Mips::HI1, Mips::HI2, Mips::HI3, 
2143
  };
2144
2145
  // HI32DSP Bit set.
2146
  const uint8_t HI32DSPBits[] = {
2147
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 
2148
  };
2149
2150
  // LO32DSP Register Class...
2151
  const MCPhysReg LO32DSP[] = {
2152
    Mips::LO0, Mips::LO1, Mips::LO2, Mips::LO3, 
2153
  };
2154
2155
  // LO32DSP Bit set.
2156
  const uint8_t LO32DSPBits[] = {
2157
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 
2158
  };
2159
2160
  // CPU16Regs_and_GPRMM16MovePPairSecond Register Class...
2161
  const MCPhysReg CPU16Regs_and_GPRMM16MovePPairSecond[] = {
2162
    Mips::A1, Mips::A2, Mips::A3, 
2163
  };
2164
2165
  // CPU16Regs_and_GPRMM16MovePPairSecond Bit set.
2166
  const uint8_t CPU16Regs_and_GPRMM16MovePPairSecondBits[] = {
2167
    0x00, 0x00, 0x80, 0x03, 
2168
  };
2169
2170
  // GPRMM16MovePPairFirst Register Class...
2171
  const MCPhysReg GPRMM16MovePPairFirst[] = {
2172
    Mips::A0, Mips::A1, Mips::A2, 
2173
  };
2174
2175
  // GPRMM16MovePPairFirst Bit set.
2176
  const uint8_t GPRMM16MovePPairFirstBits[] = {
2177
    0x00, 0x00, 0xc0, 0x01, 
2178
  };
2179
2180
  // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
2181
  const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
2182
    Mips::S1, Mips::V0, Mips::V1, 
2183
  };
2184
2185
  // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
2186
  const uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
2187
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, 
2188
  };
2189
2190
  // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class...
2191
  const MCPhysReg GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = {
2192
    Mips::A1, Mips::A2, 
2193
  };
2194
2195
  // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set.
2196
  const uint8_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = {
2197
    0x00, 0x00, 0x80, 0x01, 
2198
  };
2199
2200
  // CPURAReg Register Class...
2201
  const MCPhysReg CPURAReg[] = {
2202
    Mips::RA, 
2203
  };
2204
2205
  // CPURAReg Bit set.
2206
  const uint8_t CPURARegBits[] = {
2207
    0x00, 0x00, 0x08, 
2208
  };
2209
2210
  // CPUSPReg Register Class...
2211
  const MCPhysReg CPUSPReg[] = {
2212
    Mips::SP, 
2213
  };
2214
2215
  // CPUSPReg Bit set.
2216
  const uint8_t CPUSPRegBits[] = {
2217
    0x00, 0x00, 0x10, 
2218
  };
2219
2220
  // DSPCC Register Class...
2221
  const MCPhysReg DSPCC[] = {
2222
    Mips::DSPCCond, 
2223
  };
2224
2225
  // DSPCC Bit set.
2226
  const uint8_t DSPCCBits[] = {
2227
    0x04, 
2228
  };
2229
2230
  // GP32 Register Class...
2231
  const MCPhysReg GP32[] = {
2232
    Mips::GP, 
2233
  };
2234
2235
  // GP32 Bit set.
2236
  const uint8_t GP32Bits[] = {
2237
    0x00, 0x02, 
2238
  };
2239
2240
  // GPR32ZERO Register Class...
2241
  const MCPhysReg GPR32ZERO[] = {
2242
    Mips::ZERO, 
2243
  };
2244
2245
  // GPR32ZERO Bit set.
2246
  const uint8_t GPR32ZEROBits[] = {
2247
    0x00, 0x00, 0x20, 
2248
  };
2249
2250
  // HI32 Register Class...
2251
  const MCPhysReg HI32[] = {
2252
    Mips::HI0, 
2253
  };
2254
2255
  // HI32 Bit set.
2256
  const uint8_t HI32Bits[] = {
2257
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 
2258
  };
2259
2260
  // LO32 Register Class...
2261
  const MCPhysReg LO32[] = {
2262
    Mips::LO0, 
2263
  };
2264
2265
  // LO32 Bit set.
2266
  const uint8_t LO32Bits[] = {
2267
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 
2268
  };
2269
2270
  // SP32 Register Class...
2271
  const MCPhysReg SP32[] = {
2272
    Mips::SP, 
2273
  };
2274
2275
  // SP32 Bit set.
2276
  const uint8_t SP32Bits[] = {
2277
    0x00, 0x00, 0x10, 
2278
  };
2279
2280
  // FGR64 Register Class...
2281
  const MCPhysReg FGR64[] = {
2282
    Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64, Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64, Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64, Mips::D20_64, Mips::D21_64, Mips::D22_64, Mips::D23_64, Mips::D24_64, Mips::D25_64, Mips::D26_64, Mips::D27_64, Mips::D28_64, Mips::D29_64, Mips::D30_64, Mips::D31_64, 
2283
  };
2284
2285
  // FGR64 Bit set.
2286
  const uint8_t FGR64Bits[] = {
2287
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
2288
  };
2289
2290
  // GPR64 Register Class...
2291
  const MCPhysReg GPR64[] = {
2292
    Mips::ZERO_64, Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64, 
2293
  };
2294
2295
  // GPR64 Bit set.
2296
  const uint8_t GPR64Bits[] = {
2297
    0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03, 
2298
  };
2299
2300
  // GPR64_with_sub_32_in_GPR32NONZERO Register Class...
2301
  const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO[] = {
2302
    Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64, 
2303
  };
2304
2305
  // GPR64_with_sub_32_in_GPR32NONZERO Bit set.
2306
  const uint8_t GPR64_with_sub_32_in_GPR32NONZEROBits[] = {
2307
    0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03, 
2308
  };
2309
2310
  // AFGR64 Register Class...
2311
  const MCPhysReg AFGR64[] = {
2312
    Mips::D0, Mips::D1, Mips::D2, Mips::D3, Mips::D4, Mips::D5, Mips::D6, Mips::D7, Mips::D8, Mips::D9, Mips::D10, Mips::D11, Mips::D12, Mips::D13, Mips::D14, Mips::D15, 
2313
  };
2314
2315
  // AFGR64 Bit set.
2316
  const uint8_t AFGR64Bits[] = {
2317
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 
2318
  };
2319
2320
  // FGR64_and_OddSP Register Class...
2321
  const MCPhysReg FGR64_and_OddSP[] = {
2322
    Mips::D1_64, Mips::D3_64, Mips::D5_64, Mips::D7_64, Mips::D9_64, Mips::D11_64, Mips::D13_64, Mips::D15_64, Mips::D17_64, Mips::D19_64, Mips::D21_64, Mips::D23_64, Mips::D25_64, Mips::D27_64, Mips::D29_64, Mips::D31_64, 
2323
  };
2324
2325
  // FGR64_and_OddSP Bit set.
2326
  const uint8_t FGR64_and_OddSPBits[] = {
2327
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, 
2328
  };
2329
2330
  // GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class...
2331
  const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = {
2332
    Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64, Mips::SP_64, 
2333
  };
2334
2335
  // GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set.
2336
  const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = {
2337
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, 
2338
  };
2339
2340
  // AFGR64_and_OddSP Register Class...
2341
  const MCPhysReg AFGR64_and_OddSP[] = {
2342
    Mips::D1, Mips::D3, Mips::D5, Mips::D7, Mips::D9, Mips::D11, Mips::D13, Mips::D15, 
2343
  };
2344
2345
  // AFGR64_and_OddSP Bit set.
2346
  const uint8_t AFGR64_and_OddSPBits[] = {
2347
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 
2348
  };
2349
2350
  // GPR64_with_sub_32_in_CPU16Regs Register Class...
2351
  const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = {
2352
    Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64, 
2353
  };
2354
2355
  // GPR64_with_sub_32_in_CPU16Regs Bit set.
2356
  const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = {
2357
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, 
2358
  };
2359
2360
  // GPR64_with_sub_32_in_GPRMM16MoveP Register Class...
2361
  const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = {
2362
    Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, 
2363
  };
2364
2365
  // GPR64_with_sub_32_in_GPRMM16MoveP Bit set.
2366
  const uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = {
2367
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03, 
2368
  };
2369
2370
  // GPR64_with_sub_32_in_GPRMM16Zero Register Class...
2371
  const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = {
2372
    Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64, 
2373
  };
2374
2375
  // GPR64_with_sub_32_in_GPRMM16Zero Bit set.
2376
  const uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = {
2377
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, 
2378
  };
2379
2380
  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class...
2381
  const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = {
2382
    Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64, 
2383
  };
2384
2385
  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set.
2386
  const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = {
2387
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, 
2388
  };
2389
2390
  // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Register Class...
2391
  const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP[] = {
2392
    Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, 
2393
  };
2394
2395
  // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Bit set.
2396
  const uint8_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits[] = {
2397
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03, 
2398
  };
2399
2400
  // GPR64_with_sub_32_in_GPRMM16MovePPairSecond Register Class...
2401
  const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairSecond[] = {
2402
    Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S5_64, Mips::S6_64, 
2403
  };
2404
2405
  // GPR64_with_sub_32_in_GPRMM16MovePPairSecond Bit set.
2406
  const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits[] = {
2407
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 
2408
  };
2409
2410
  // ACC64DSP Register Class...
2411
  const MCPhysReg ACC64DSP[] = {
2412
    Mips::AC0, Mips::AC1, Mips::AC2, Mips::AC3, 
2413
  };
2414
2415
  // ACC64DSP Bit set.
2416
  const uint8_t ACC64DSPBits[] = {
2417
    0x00, 0x00, 0x00, 0x3c, 
2418
  };
2419
2420
  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class...
2421
  const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = {
2422
    Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, 
2423
  };
2424
2425
  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set.
2426
  const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = {
2427
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, 
2428
  };
2429
2430
  // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class...
2431
  const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = {
2432
    Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S1_64, 
2433
  };
2434
2435
  // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set.
2436
  const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
2437
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, 
2438
  };
2439
2440
  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Register Class...
2441
  const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond[] = {
2442
    Mips::A1_64, Mips::A2_64, Mips::A3_64, 
2443
  };
2444
2445
  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Bit set.
2446
  const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits[] = {
2447
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 
2448
  };
2449
2450
  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst Register Class...
2451
  const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst[] = {
2452
    Mips::A0_64, Mips::A1_64, Mips::A2_64, 
2453
  };
2454
2455
  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst Bit set.
2456
  const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits[] = {
2457
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 
2458
  };
2459
2460
  // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
2461
  const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
2462
    Mips::V0_64, Mips::V1_64, Mips::S1_64, 
2463
  };
2464
2465
  // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
2466
  const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
2467
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, 
2468
  };
2469
2470
  // OCTEON_MPL Register Class...
2471
  const MCPhysReg OCTEON_MPL[] = {
2472
    Mips::MPL0, Mips::MPL1, Mips::MPL2, 
2473
  };
2474
2475
  // OCTEON_MPL Bit set.
2476
  const uint8_t OCTEON_MPLBits[] = {
2477
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, 
2478
  };
2479
2480
  // OCTEON_P Register Class...
2481
  const MCPhysReg OCTEON_P[] = {
2482
    Mips::P0, Mips::P1, Mips::P2, 
2483
  };
2484
2485
  // OCTEON_P Bit set.
2486
  const uint8_t OCTEON_PBits[] = {
2487
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 
2488
  };
2489
2490
  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class...
2491
  const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = {
2492
    Mips::A1_64, Mips::A2_64, 
2493
  };
2494
2495
  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set.
2496
  const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = {
2497
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 
2498
  };
2499
2500
  // ACC64 Register Class...
2501
  const MCPhysReg ACC64[] = {
2502
    Mips::AC0, 
2503
  };
2504
2505
  // ACC64 Bit set.
2506
  const uint8_t ACC64Bits[] = {
2507
    0x00, 0x00, 0x00, 0x04, 
2508
  };
2509
2510
  // GP64 Register Class...
2511
  const MCPhysReg GP64[] = {
2512
    Mips::GP_64, 
2513
  };
2514
2515
  // GP64 Bit set.
2516
  const uint8_t GP64Bits[] = {
2517
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 
2518
  };
2519
2520
  // GPR64_with_sub_32_in_CPURAReg Register Class...
2521
  const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = {
2522
    Mips::RA_64, 
2523
  };
2524
2525
  // GPR64_with_sub_32_in_CPURAReg Bit set.
2526
  const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = {
2527
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 
2528
  };
2529
2530
  // GPR64_with_sub_32_in_GPR32ZERO Register Class...
2531
  const MCPhysReg GPR64_with_sub_32_in_GPR32ZERO[] = {
2532
    Mips::ZERO_64, 
2533
  };
2534
2535
  // GPR64_with_sub_32_in_GPR32ZERO Bit set.
2536
  const uint8_t GPR64_with_sub_32_in_GPR32ZEROBits[] = {
2537
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 
2538
  };
2539
2540
  // HI64 Register Class...
2541
  const MCPhysReg HI64[] = {
2542
    Mips::HI0_64, 
2543
  };
2544
2545
  // HI64 Bit set.
2546
  const uint8_t HI64Bits[] = {
2547
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 
2548
  };
2549
2550
  // LO64 Register Class...
2551
  const MCPhysReg LO64[] = {
2552
    Mips::LO0_64, 
2553
  };
2554
2555
  // LO64 Bit set.
2556
  const uint8_t LO64Bits[] = {
2557
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 
2558
  };
2559
2560
  // SP64 Register Class...
2561
  const MCPhysReg SP64[] = {
2562
    Mips::SP_64, 
2563
  };
2564
2565
  // SP64 Bit set.
2566
  const uint8_t SP64Bits[] = {
2567
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 
2568
  };
2569
2570
  // MSA128B Register Class...
2571
  const MCPhysReg MSA128B[] = {
2572
    Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31, 
2573
  };
2574
2575
  // MSA128B Bit set.
2576
  const uint8_t MSA128BBits[] = {
2577
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
2578
  };
2579
2580
  // MSA128D Register Class...
2581
  const MCPhysReg MSA128D[] = {
2582
    Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31, 
2583
  };
2584
2585
  // MSA128D Bit set.
2586
  const uint8_t MSA128DBits[] = {
2587
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
2588
  };
2589
2590
  // MSA128H Register Class...
2591
  const MCPhysReg MSA128H[] = {
2592
    Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31, 
2593
  };
2594
2595
  // MSA128H Bit set.
2596
  const uint8_t MSA128HBits[] = {
2597
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
2598
  };
2599
2600
  // MSA128W Register Class...
2601
  const MCPhysReg MSA128W[] = {
2602
    Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31, 
2603
  };
2604
2605
  // MSA128W Bit set.
2606
  const uint8_t MSA128WBits[] = {
2607
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
2608
  };
2609
2610
  // MSA128B_with_sub_64_in_OddSP Register Class...
2611
  const MCPhysReg MSA128B_with_sub_64_in_OddSP[] = {
2612
    Mips::W1, Mips::W3, Mips::W5, Mips::W7, Mips::W9, Mips::W11, Mips::W13, Mips::W15, Mips::W17, Mips::W19, Mips::W21, Mips::W23, Mips::W25, Mips::W27, Mips::W29, Mips::W31, 
2613
  };
2614
2615
  // MSA128B_with_sub_64_in_OddSP Bit set.
2616
  const uint8_t MSA128B_with_sub_64_in_OddSPBits[] = {
2617
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05, 
2618
  };
2619
2620
  // MSA128WEvens Register Class...
2621
  const MCPhysReg MSA128WEvens[] = {
2622
    Mips::W0, Mips::W2, Mips::W4, Mips::W6, Mips::W8, Mips::W10, Mips::W12, Mips::W14, Mips::W16, Mips::W18, Mips::W20, Mips::W22, Mips::W24, Mips::W26, Mips::W28, Mips::W30, 
2623
  };
2624
2625
  // MSA128WEvens Bit set.
2626
  const uint8_t MSA128WEvensBits[] = {
2627
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02, 
2628
  };
2629
2630
  // ACC128 Register Class...
2631
  const MCPhysReg ACC128[] = {
2632
    Mips::AC0_64, 
2633
  };
2634
2635
  // ACC128 Bit set.
2636
  const uint8_t ACC128Bits[] = {
2637
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 
2638
  };
2639
2640
} // end anonymous namespace
2641
2642
extern const char MipsRegClassStrings[] = {
2643
  /* 0 */ 'C', 'O', 'P', '0', 0,
2644
  /* 5 */ 'O', 'd', 'd', 'S', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'i', 'n', '_', 'F', 'G', 'R', 'H', '3', '2', 0,
2645
  /* 45 */ 'H', 'I', '3', '2', 0,
2646
  /* 50 */ 'L', 'O', '3', '2', 0,
2647
  /* 55 */ 'G', 'P', '3', '2', 0,
2648
  /* 60 */ 'S', 'P', '3', '2', 0,
2649
  /* 65 */ 'O', 'd', 'd', 'S', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'i', 'n', '_', 'F', 'G', 'R', '3', '2', 0,
2650
  /* 104 */ 'G', 'P', 'R', '3', '2', 0,
2651
  /* 110 */ 'C', 'O', 'P', '2', 0,
2652
  /* 115 */ 'C', 'O', 'P', '3', 0,
2653
  /* 120 */ 'A', 'C', 'C', '6', '4', 0,
2654
  /* 126 */ 'H', 'I', '6', '4', 0,
2655
  /* 131 */ 'L', 'O', '6', '4', 0,
2656
  /* 136 */ 'G', 'P', '6', '4', 0,
2657
  /* 141 */ 'S', 'P', '6', '4', 0,
2658
  /* 146 */ 'A', 'F', 'G', 'R', '6', '4', 0,
2659
  /* 153 */ 'G', 'P', 'R', '6', '4', 0,
2660
  /* 159 */ 'M', 'S', 'A', '1', '2', '8', 'F', '1', '6', 0,
2661
  /* 169 */ 'G', 'P', 'R', 'M', 'M', '1', '6', 0,
2662
  /* 177 */ 'A', 'C', 'C', '1', '2', '8', 0,
2663
  /* 184 */ 'M', 'S', 'A', '1', '2', '8', 'B', 0,
2664
  /* 192 */ 'F', 'C', 'C', 0,
2665
  /* 196 */ 'D', 'S', 'P', 'C', 'C', 0,
2666
  /* 202 */ 'F', 'G', 'R', 'C', 'C', 0,
2667
  /* 208 */ 'M', 'S', 'A', '1', '2', '8', 'D', 0,
2668
  /* 216 */ 'M', 'S', 'A', '1', '2', '8', 'H', 0,
2669
  /* 224 */ 'O', 'C', 'T', 'E', 'O', 'N', '_', 'M', 'P', 'L', 0,
2670
  /* 235 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'Z', 'E', 'R', 'O', 0,
2671
  /* 266 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'N', 'O', 'N', 'Z', 'E', 'R', 'O', 0,
2672
  /* 300 */ 'H', 'I', '3', '2', 'D', 'S', 'P', 0,
2673
  /* 308 */ 'L', 'O', '3', '2', 'D', 'S', 'P', 0,
2674
  /* 316 */ 'A', 'C', 'C', '6', '4', 'D', 'S', 'P', 0,
2675
  /* 325 */ 'F', 'G', 'R', 'H', '3', '2', '_', 'a', 'n', 'd', '_', 'O', 'd', 'd', 'S', 'P', 0,
2676
  /* 342 */ 'F', 'G', 'R', '3', '2', '_', 'a', 'n', 'd', '_', 'O', 'd', 'd', 'S', 'P', 0,
2677
  /* 358 */ 'A', 'F', 'G', 'R', '6', '4', '_', 'a', 'n', 'd', '_', 'O', 'd', 'd', 'S', 'P', 0,
2678
  /* 375 */ 'M', 'S', 'A', '1', '2', '8', 'F', '1', '6', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '6', '4', '_', 'i', 'n', '_', 'O', 'd', 'd', 'S', 'P', 0,
2679
  /* 406 */ 'M', 'S', 'A', '1', '2', '8', 'B', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '6', '4', '_', 'i', 'n', '_', 'O', 'd', 'd', 'S', 'P', 0,
2680
  /* 435 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', 'P', 'l', 'u', 's', 'S', 'P', 0,
2681
  /* 472 */ 'O', 'C', 'T', 'E', 'O', 'N', '_', 'P', 0,
2682
  /* 481 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'N', 'O', 'N', 'Z', 'E', 'R', 'O', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 0,
2683
  /* 532 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 0,
2684
  /* 580 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 0,
2685
  /* 614 */ 'C', 'C', 'R', 0,
2686
  /* 618 */ 'D', 'S', 'P', 'R', 0,
2687
  /* 623 */ 'M', 'S', 'A', '1', '2', '8', 'W', 0,
2688
  /* 631 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 'P', 'a', 'i', 'r', 'S', 'e', 'c', 'o', 'n', 'd', 0,
2689
  /* 689 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 'P', 'a', 'i', 'r', 'F', 'i', 'r', 's', 't', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 'P', 'a', 'i', 'r', 'S', 'e', 'c', 'o', 'n', 'd', 0,
2690
  /* 759 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 'P', 'a', 'i', 'r', 'S', 'e', 'c', 'o', 'n', 'd', 0,
2691
  /* 803 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', 'R', 'A', 'R', 'e', 'g', 0,
2692
  /* 833 */ 'C', 'P', 'U', 'S', 'P', 'R', 'e', 'g', 0,
2693
  /* 842 */ 'O', 'd', 'd', 'S', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', 0,
2694
  /* 860 */ 'M', 'S', 'A', 'C', 't', 'r', 'l', 0,
2695
  /* 868 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
2696
  /* 918 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', '_', 'a', 'n', 'd', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
2697
  /* 982 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
2698
  /* 1029 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
2699
  /* 1062 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', 0,
2700
  /* 1093 */ 'H', 'W', 'R', 'e', 'g', 's', 0,
2701
  /* 1100 */ 'M', 'S', 'A', '1', '2', '8', 'W', 'E', 'v', 'e', 'n', 's', 0,
2702
  /* 1113 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 'P', 'a', 'i', 'r', 'F', 'i', 'r', 's', 't', 0,
2703
};
2704
2705
extern const MCRegisterClass MipsMCRegisterClasses[] = {
2706
  { MSA128F16, MSA128F16Bits, 159, 32, sizeof(MSA128F16Bits), Mips::MSA128F16RegClassID, 1, true },
2707
  { MSA128F16_with_sub_64_in_OddSP, MSA128F16_with_sub_64_in_OddSPBits, 375, 16, sizeof(MSA128F16_with_sub_64_in_OddSPBits), Mips::MSA128F16_with_sub_64_in_OddSPRegClassID, 1, true },
2708
  { OddSP, OddSPBits, 336, 56, sizeof(OddSPBits), Mips::OddSPRegClassID, 1, false },
2709
  { CCR, CCRBits, 614, 32, sizeof(CCRBits), Mips::CCRRegClassID, 1, false },
2710
  { COP0, COP0Bits, 0, 32, sizeof(COP0Bits), Mips::COP0RegClassID, 1, false },
2711
  { COP2, COP2Bits, 110, 32, sizeof(COP2Bits), Mips::COP2RegClassID, 1, false },
2712
  { COP3, COP3Bits, 115, 32, sizeof(COP3Bits), Mips::COP3RegClassID, 1, false },
2713
  { DSPR, DSPRBits, 618, 32, sizeof(DSPRBits), Mips::DSPRRegClassID, 1, true },
2714
  { FGR32, FGR32Bits, 98, 32, sizeof(FGR32Bits), Mips::FGR32RegClassID, 1, true },
2715
  { FGRCC, FGRCCBits, 202, 32, sizeof(FGRCCBits), Mips::FGRCCRegClassID, 1, true },
2716
  { FGRH32, FGRH32Bits, 38, 32, sizeof(FGRH32Bits), Mips::FGRH32RegClassID, 1, false },
2717
  { GPR32, GPR32Bits, 104, 32, sizeof(GPR32Bits), Mips::GPR32RegClassID, 1, true },
2718
  { HWRegs, HWRegsBits, 1093, 32, sizeof(HWRegsBits), Mips::HWRegsRegClassID, 1, false },
2719
  { GPR32NONZERO, GPR32NONZEROBits, 287, 31, sizeof(GPR32NONZEROBits), Mips::GPR32NONZERORegClassID, 1, true },
2720
  { OddSP_with_sub_hi, OddSP_with_sub_hiBits, 842, 24, sizeof(OddSP_with_sub_hiBits), Mips::OddSP_with_sub_hiRegClassID, 1, false },
2721
  { FGR32_and_OddSP, FGR32_and_OddSPBits, 342, 16, sizeof(FGR32_and_OddSPBits), Mips::FGR32_and_OddSPRegClassID, 1, true },
2722
  { FGRH32_and_OddSP, FGRH32_and_OddSPBits, 325, 16, sizeof(FGRH32_and_OddSPBits), Mips::FGRH32_and_OddSPRegClassID, 1, false },
2723
  { OddSP_with_sub_hi_with_sub_hi_in_FGRH32, OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits, 5, 16, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits), Mips::OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID, 1, false },
2724
  { CPU16RegsPlusSP, CPU16RegsPlusSPBits, 456, 9, sizeof(CPU16RegsPlusSPBits), Mips::CPU16RegsPlusSPRegClassID, 1, true },
2725
  { CPU16Regs, CPU16RegsBits, 1083, 8, sizeof(CPU16RegsBits), Mips::CPU16RegsRegClassID, 1, true },
2726
  { FCC, FCCBits, 192, 8, sizeof(FCCBits), Mips::FCCRegClassID, 1, false },
2727
  { GPRMM16, GPRMM16Bits, 169, 8, sizeof(GPRMM16Bits), Mips::GPRMM16RegClassID, 1, true },
2728
  { GPRMM16MoveP, GPRMM16MovePBits, 519, 8, sizeof(GPRMM16MovePBits), Mips::GPRMM16MovePRegClassID, 1, true },
2729
  { GPRMM16Zero, GPRMM16ZeroBits, 906, 8, sizeof(GPRMM16ZeroBits), Mips::GPRMM16ZeroRegClassID, 1, true },
2730
  { MSACtrl, MSACtrlBits, 860, 8, sizeof(MSACtrlBits), Mips::MSACtrlRegClassID, 1, true },
2731
  { OddSP_with_sub_hi_with_sub_hi_in_FGR32, OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits, 65, 8, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits), Mips::OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID, 1, false },
2732
  { CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, 956, 7, sizeof(CPU16Regs_and_GPRMM16ZeroBits), Mips::CPU16Regs_and_GPRMM16ZeroRegClassID, 1, true },
2733
  { GPR32NONZERO_and_GPRMM16MoveP, GPR32NONZERO_and_GPRMM16MovePBits, 502, 7, sizeof(GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID, 1, true },
2734
  { GPRMM16MovePPairSecond, GPRMM16MovePPairSecondBits, 666, 5, sizeof(GPRMM16MovePPairSecondBits), Mips::GPRMM16MovePPairSecondRegClassID, 1, true },
2735
  { CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, 553, 4, sizeof(CPU16Regs_and_GPRMM16MovePBits), Mips::CPU16Regs_and_GPRMM16MovePRegClassID, 1, true },
2736
  { GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, 889, 4, sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 1, true },
2737
  { HI32DSP, HI32DSPBits, 300, 4, sizeof(HI32DSPBits), Mips::HI32DSPRegClassID, 1, true },
2738
  { LO32DSP, LO32DSPBits, 308, 4, sizeof(LO32DSPBits), Mips::LO32DSPRegClassID, 1, true },
2739
  { CPU16Regs_and_GPRMM16MovePPairSecond, CPU16Regs_and_GPRMM16MovePPairSecondBits, 652, 3, sizeof(CPU16Regs_and_GPRMM16MovePPairSecondBits), Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, 1, true },
2740
  { GPRMM16MovePPairFirst, GPRMM16MovePPairFirstBits, 1134, 3, sizeof(GPRMM16MovePPairFirstBits), Mips::GPRMM16MovePPairFirstRegClassID, 1, true },
2741
  { GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 939, 3, sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 1, true },
2742
  { GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, 710, 2, sizeof(GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits), Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, 1, true },
2743
  { CPURAReg, CPURARegBits, 824, 1, sizeof(CPURARegBits), Mips::CPURARegRegClassID, 1, false },
2744
  { CPUSPReg, CPUSPRegBits, 833, 1, sizeof(CPUSPRegBits), Mips::CPUSPRegRegClassID, 1, false },
2745
  { DSPCC, DSPCCBits, 196, 1, sizeof(DSPCCBits), Mips::DSPCCRegClassID, 1, true },
2746
  { GP32, GP32Bits, 55, 1, sizeof(GP32Bits), Mips::GP32RegClassID, 1, false },
2747
  { GPR32ZERO, GPR32ZEROBits, 256, 1, sizeof(GPR32ZEROBits), Mips::GPR32ZERORegClassID, 1, true },
2748
  { HI32, HI32Bits, 45, 1, sizeof(HI32Bits), Mips::HI32RegClassID, 1, true },
2749
  { LO32, LO32Bits, 50, 1, sizeof(LO32Bits), Mips::LO32RegClassID, 1, true },
2750
  { SP32, SP32Bits, 60, 1, sizeof(SP32Bits), Mips::SP32RegClassID, 1, false },
2751
  { FGR64, FGR64Bits, 147, 32, sizeof(FGR64Bits), Mips::FGR64RegClassID, 1, true },
2752
  { GPR64, GPR64Bits, 153, 32, sizeof(GPR64Bits), Mips::GPR64RegClassID, 1, true },
2753
  { GPR64_with_sub_32_in_GPR32NONZERO, GPR64_with_sub_32_in_GPR32NONZEROBits, 266, 31, sizeof(GPR64_with_sub_32_in_GPR32NONZEROBits), Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, 1, true },
2754
  { AFGR64, AFGR64Bits, 146, 16, sizeof(AFGR64Bits), Mips::AFGR64RegClassID, 1, true },
2755
  { FGR64_and_OddSP, FGR64_and_OddSPBits, 359, 16, sizeof(FGR64_and_OddSPBits), Mips::FGR64_and_OddSPRegClassID, 1, true },
2756
  { GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, 435, 9, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits), Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID, 1, true },
2757
  { AFGR64_and_OddSP, AFGR64_and_OddSPBits, 358, 8, sizeof(AFGR64_and_OddSPBits), Mips::AFGR64_and_OddSPRegClassID, 1, true },
2758
  { GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, 1062, 8, sizeof(GPR64_with_sub_32_in_CPU16RegsBits), Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID, 1, true },
2759
  { GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, 580, 8, sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID, 1, true },
2760
  { GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, 1029, 8, sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID, 1, true },
2761
  { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, 982, 7, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID, 1, true },
2762
  { GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP, GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits, 481, 7, sizeof(GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID, 1, true },
2763
  { GPR64_with_sub_32_in_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits, 759, 5, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID, 1, true },
2764
  { ACC64DSP, ACC64DSPBits, 316, 4, sizeof(ACC64DSPBits), Mips::ACC64DSPRegClassID, 1, true },
2765
  { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, 532, 4, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID, 1, true },
2766
  { GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, 868, 4, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 1, true },
2767
  { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits, 631, 3, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, 1, true },
2768
  { GPR64_with_sub_32_in_GPRMM16MovePPairFirst, GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits, 1113, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID, 1, true },
2769
  { GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 918, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 1, true },
2770
  { OCTEON_MPL, OCTEON_MPLBits, 224, 3, sizeof(OCTEON_MPLBits), Mips::OCTEON_MPLRegClassID, 1, false },
2771
  { OCTEON_P, OCTEON_PBits, 472, 3, sizeof(OCTEON_PBits), Mips::OCTEON_PRegClassID, 1, false },
2772
  { GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, 689, 2, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, 1, true },
2773
  { ACC64, ACC64Bits, 120, 1, sizeof(ACC64Bits), Mips::ACC64RegClassID, 1, true },
2774
  { GP64, GP64Bits, 136, 1, sizeof(GP64Bits), Mips::GP64RegClassID, 1, false },
2775
  { GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, 803, 1, sizeof(GPR64_with_sub_32_in_CPURARegBits), Mips::GPR64_with_sub_32_in_CPURARegRegClassID, 1, true },
2776
  { GPR64_with_sub_32_in_GPR32ZERO, GPR64_with_sub_32_in_GPR32ZEROBits, 235, 1, sizeof(GPR64_with_sub_32_in_GPR32ZEROBits), Mips::GPR64_with_sub_32_in_GPR32ZERORegClassID, 1, true },
2777
  { HI64, HI64Bits, 126, 1, sizeof(HI64Bits), Mips::HI64RegClassID, 1, true },
2778
  { LO64, LO64Bits, 131, 1, sizeof(LO64Bits), Mips::LO64RegClassID, 1, true },
2779
  { SP64, SP64Bits, 141, 1, sizeof(SP64Bits), Mips::SP64RegClassID, 1, false },
2780
  { MSA128B, MSA128BBits, 184, 32, sizeof(MSA128BBits), Mips::MSA128BRegClassID, 1, true },
2781
  { MSA128D, MSA128DBits, 208, 32, sizeof(MSA128DBits), Mips::MSA128DRegClassID, 1, true },
2782
  { MSA128H, MSA128HBits, 216, 32, sizeof(MSA128HBits), Mips::MSA128HRegClassID, 1, true },
2783
  { MSA128W, MSA128WBits, 623, 32, sizeof(MSA128WBits), Mips::MSA128WRegClassID, 1, true },
2784
  { MSA128B_with_sub_64_in_OddSP, MSA128B_with_sub_64_in_OddSPBits, 406, 16, sizeof(MSA128B_with_sub_64_in_OddSPBits), Mips::MSA128B_with_sub_64_in_OddSPRegClassID, 1, true },
2785
  { MSA128WEvens, MSA128WEvensBits, 1100, 16, sizeof(MSA128WEvensBits), Mips::MSA128WEvensRegClassID, 1, true },
2786
  { ACC128, ACC128Bits, 177, 1, sizeof(ACC128Bits), Mips::ACC128RegClassID, 1, true },
2787
};
2788
2789
// Mips Dwarf<->LLVM register mappings.
2790
extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[] = {
2791
  { 0U, Mips::ZERO_64 },
2792
  { 1U, Mips::AT_64 },
2793
  { 2U, Mips::V0_64 },
2794
  { 3U, Mips::V1_64 },
2795
  { 4U, Mips::A0_64 },
2796
  { 5U, Mips::A1_64 },
2797
  { 6U, Mips::A2_64 },
2798
  { 7U, Mips::A3_64 },
2799
  { 8U, Mips::T0_64 },
2800
  { 9U, Mips::T1_64 },
2801
  { 10U, Mips::T2_64 },
2802
  { 11U, Mips::T3_64 },
2803
  { 12U, Mips::T4_64 },
2804
  { 13U, Mips::T5_64 },
2805
  { 14U, Mips::T6_64 },
2806
  { 15U, Mips::T7_64 },
2807
  { 16U, Mips::S0_64 },
2808
  { 17U, Mips::S1_64 },
2809
  { 18U, Mips::S2_64 },
2810
  { 19U, Mips::S3_64 },
2811
  { 20U, Mips::S4_64 },
2812
  { 21U, Mips::S5_64 },
2813
  { 22U, Mips::S6_64 },
2814
  { 23U, Mips::S7_64 },
2815
  { 24U, Mips::T8_64 },
2816
  { 25U, Mips::T9_64 },
2817
  { 26U, Mips::K0_64 },
2818
  { 27U, Mips::K1_64 },
2819
  { 28U, Mips::GP_64 },
2820
  { 29U, Mips::SP_64 },
2821
  { 30U, Mips::FP_64 },
2822
  { 31U, Mips::RA_64 },
2823
  { 32U, Mips::D0_64 },
2824
  { 33U, Mips::D1_64 },
2825
  { 34U, Mips::D2_64 },
2826
  { 35U, Mips::D3_64 },
2827
  { 36U, Mips::D4_64 },
2828
  { 37U, Mips::D5_64 },
2829
  { 38U, Mips::D6_64 },
2830
  { 39U, Mips::D7_64 },
2831
  { 40U, Mips::D8_64 },
2832
  { 41U, Mips::D9_64 },
2833
  { 42U, Mips::D10_64 },
2834
  { 43U, Mips::D11_64 },
2835
  { 44U, Mips::D12_64 },
2836
  { 45U, Mips::D13_64 },
2837
  { 46U, Mips::D14_64 },
2838
  { 47U, Mips::D15_64 },
2839
  { 48U, Mips::D16_64 },
2840
  { 49U, Mips::D17_64 },
2841
  { 50U, Mips::D18_64 },
2842
  { 51U, Mips::D19_64 },
2843
  { 52U, Mips::D20_64 },
2844
  { 53U, Mips::D21_64 },
2845
  { 54U, Mips::D22_64 },
2846
  { 55U, Mips::D23_64 },
2847
  { 56U, Mips::D24_64 },
2848
  { 57U, Mips::D25_64 },
2849
  { 58U, Mips::D26_64 },
2850
  { 59U, Mips::D27_64 },
2851
  { 60U, Mips::D28_64 },
2852
  { 61U, Mips::D29_64 },
2853
  { 62U, Mips::D30_64 },
2854
  { 63U, Mips::D31_64 },
2855
  { 64U, Mips::HI0 },
2856
  { 65U, Mips::LO0 },
2857
  { 176U, Mips::HI1 },
2858
  { 177U, Mips::LO1 },
2859
  { 178U, Mips::HI2 },
2860
  { 179U, Mips::LO2 },
2861
  { 180U, Mips::HI3 },
2862
  { 181U, Mips::LO3 },
2863
};
2864
extern const unsigned MipsDwarfFlavour0Dwarf2LSize = array_lengthof(MipsDwarfFlavour0Dwarf2L);
2865
2866
extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[] = {
2867
  { 0U, Mips::ZERO_64 },
2868
  { 1U, Mips::AT_64 },
2869
  { 2U, Mips::V0_64 },
2870
  { 3U, Mips::V1_64 },
2871
  { 4U, Mips::A0_64 },
2872
  { 5U, Mips::A1_64 },
2873
  { 6U, Mips::A2_64 },
2874
  { 7U, Mips::A3_64 },
2875
  { 8U, Mips::T0_64 },
2876
  { 9U, Mips::T1_64 },
2877
  { 10U, Mips::T2_64 },
2878
  { 11U, Mips::T3_64 },
2879
  { 12U, Mips::T4_64 },
2880
  { 13U, Mips::T5_64 },
2881
  { 14U, Mips::T6_64 },
2882
  { 15U, Mips::T7_64 },
2883
  { 16U, Mips::S0_64 },
2884
  { 17U, Mips::S1_64 },
2885
  { 18U, Mips::S2_64 },
2886
  { 19U, Mips::S3_64 },
2887
  { 20U, Mips::S4_64 },
2888
  { 21U, Mips::S5_64 },
2889
  { 22U, Mips::S6_64 },
2890
  { 23U, Mips::S7_64 },
2891
  { 24U, Mips::T8_64 },
2892
  { 25U, Mips::T9_64 },
2893
  { 26U, Mips::K0_64 },
2894
  { 27U, Mips::K1_64 },
2895
  { 28U, Mips::GP_64 },
2896
  { 29U, Mips::SP_64 },
2897
  { 30U, Mips::FP_64 },
2898
  { 31U, Mips::RA_64 },
2899
  { 32U, Mips::D0_64 },
2900
  { 33U, Mips::D1_64 },
2901
  { 34U, Mips::D2_64 },
2902
  { 35U, Mips::D3_64 },
2903
  { 36U, Mips::D4_64 },
2904
  { 37U, Mips::D5_64 },
2905
  { 38U, Mips::D6_64 },
2906
  { 39U, Mips::D7_64 },
2907
  { 40U, Mips::D8_64 },
2908
  { 41U, Mips::D9_64 },
2909
  { 42U, Mips::D10_64 },
2910
  { 43U, Mips::D11_64 },
2911
  { 44U, Mips::D12_64 },
2912
  { 45U, Mips::D13_64 },
2913
  { 46U, Mips::D14_64 },
2914
  { 47U, Mips::D15_64 },
2915
  { 48U, Mips::D16_64 },
2916
  { 49U, Mips::D17_64 },
2917
  { 50U, Mips::D18_64 },
2918
  { 51U, Mips::D19_64 },
2919
  { 52U, Mips::D20_64 },
2920
  { 53U, Mips::D21_64 },
2921
  { 54U, Mips::D22_64 },
2922
  { 55U, Mips::D23_64 },
2923
  { 56U, Mips::D24_64 },
2924
  { 57U, Mips::D25_64 },
2925
  { 58U, Mips::D26_64 },
2926
  { 59U, Mips::D27_64 },
2927
  { 60U, Mips::D28_64 },
2928
  { 61U, Mips::D29_64 },
2929
  { 62U, Mips::D30_64 },
2930
  { 63U, Mips::D31_64 },
2931
  { 64U, Mips::HI0 },
2932
  { 65U, Mips::LO0 },
2933
  { 176U, Mips::HI1 },
2934
  { 177U, Mips::LO1 },
2935
  { 178U, Mips::HI2 },
2936
  { 179U, Mips::LO2 },
2937
  { 180U, Mips::HI3 },
2938
  { 181U, Mips::LO3 },
2939
};
2940
extern const unsigned MipsEHFlavour0Dwarf2LSize = array_lengthof(MipsEHFlavour0Dwarf2L);
2941
2942
extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[] = {
2943
  { Mips::AT, 1U },
2944
  { Mips::FP, 30U },
2945
  { Mips::GP, 28U },
2946
  { Mips::RA, 31U },
2947
  { Mips::SP, 29U },
2948
  { Mips::ZERO, 0U },
2949
  { Mips::A0, 4U },
2950
  { Mips::A1, 5U },
2951
  { Mips::A2, 6U },
2952
  { Mips::A3, 7U },
2953
  { Mips::AT_64, 1U },
2954
  { Mips::F0, 32U },
2955
  { Mips::F1, 33U },
2956
  { Mips::F2, 34U },
2957
  { Mips::F3, 35U },
2958
  { Mips::F4, 36U },
2959
  { Mips::F5, 37U },
2960
  { Mips::F6, 38U },
2961
  { Mips::F7, 39U },
2962
  { Mips::F8, 40U },
2963
  { Mips::F9, 41U },
2964
  { Mips::F10, 42U },
2965
  { Mips::F11, 43U },
2966
  { Mips::F12, 44U },
2967
  { Mips::F13, 45U },
2968
  { Mips::F14, 46U },
2969
  { Mips::F15, 47U },
2970
  { Mips::F16, 48U },
2971
  { Mips::F17, 49U },
2972
  { Mips::F18, 50U },
2973
  { Mips::F19, 51U },
2974
  { Mips::F20, 52U },
2975
  { Mips::F21, 53U },
2976
  { Mips::F22, 54U },
2977
  { Mips::F23, 55U },
2978
  { Mips::F24, 56U },
2979
  { Mips::F25, 57U },
2980
  { Mips::F26, 58U },
2981
  { Mips::F27, 59U },
2982
  { Mips::F28, 60U },
2983
  { Mips::F29, 61U },
2984
  { Mips::F30, 62U },
2985
  { Mips::F31, 63U },
2986
  { Mips::FP_64, 30U },
2987
  { Mips::F_HI0, 32U },
2988
  { Mips::F_HI1, 33U },
2989
  { Mips::F_HI2, 34U },
2990
  { Mips::F_HI3, 35U },
2991
  { Mips::F_HI4, 36U },
2992
  { Mips::F_HI5, 37U },
2993
  { Mips::F_HI6, 38U },
2994
  { Mips::F_HI7, 39U },
2995
  { Mips::F_HI8, 40U },
2996
  { Mips::F_HI9, 41U },
2997
  { Mips::F_HI10, 42U },
2998
  { Mips::F_HI11, 43U },
2999
  { Mips::F_HI12, 44U },
3000
  { Mips::F_HI13, 45U },
3001
  { Mips::F_HI14, 46U },
3002
  { Mips::F_HI15, 47U },
3003
  { Mips::F_HI16, 48U },
3004
  { Mips::F_HI17, 49U },
3005
  { Mips::F_HI18, 50U },
3006
  { Mips::F_HI19, 51U },
3007
  { Mips::F_HI20, 52U },
3008
  { Mips::F_HI21, 53U },
3009
  { Mips::F_HI22, 54U },
3010
  { Mips::F_HI23, 55U },
3011
  { Mips::F_HI24, 56U },
3012
  { Mips::F_HI25, 57U },
3013
  { Mips::F_HI26, 58U },
3014
  { Mips::F_HI27, 59U },
3015
  { Mips::F_HI28, 60U },
3016
  { Mips::F_HI29, 61U },
3017
  { Mips::F_HI30, 62U },
3018
  { Mips::F_HI31, 63U },
3019
  { Mips::GP_64, 28U },
3020
  { Mips::HI0, 64U },
3021
  { Mips::HI1, 176U },
3022
  { Mips::HI2, 178U },
3023
  { Mips::HI3, 180U },
3024
  { Mips::K0, 26U },
3025
  { Mips::K1, 27U },
3026
  { Mips::LO0, 65U },
3027
  { Mips::LO1, 177U },
3028
  { Mips::LO2, 179U },
3029
  { Mips::LO3, 181U },
3030
  { Mips::RA_64, 31U },
3031
  { Mips::S0, 16U },
3032
  { Mips::S1, 17U },
3033
  { Mips::S2, 18U },
3034
  { Mips::S3, 19U },
3035
  { Mips::S4, 20U },
3036
  { Mips::S5, 21U },
3037
  { Mips::S6, 22U },
3038
  { Mips::S7, 23U },
3039
  { Mips::SP_64, 29U },
3040
  { Mips::T0, 8U },
3041
  { Mips::T1, 9U },
3042
  { Mips::T2, 10U },
3043
  { Mips::T3, 11U },
3044
  { Mips::T4, 12U },
3045
  { Mips::T5, 13U },
3046
  { Mips::T6, 14U },
3047
  { Mips::T7, 15U },
3048
  { Mips::T8, 24U },
3049
  { Mips::T9, 25U },
3050
  { Mips::V0, 2U },
3051
  { Mips::V1, 3U },
3052
  { Mips::W0, 32U },
3053
  { Mips::W1, 33U },
3054
  { Mips::W2, 34U },
3055
  { Mips::W3, 35U },
3056
  { Mips::W4, 36U },
3057
  { Mips::W5, 37U },
3058
  { Mips::W6, 38U },
3059
  { Mips::W7, 39U },
3060
  { Mips::W8, 40U },
3061
  { Mips::W9, 41U },
3062
  { Mips::W10, 42U },
3063
  { Mips::W11, 43U },
3064
  { Mips::W12, 44U },
3065
  { Mips::W13, 45U },
3066
  { Mips::W14, 46U },
3067
  { Mips::W15, 47U },
3068
  { Mips::W16, 48U },
3069
  { Mips::W17, 49U },
3070
  { Mips::W18, 50U },
3071
  { Mips::W19, 51U },
3072
  { Mips::W20, 52U },
3073
  { Mips::W21, 53U },
3074
  { Mips::W22, 54U },
3075
  { Mips::W23, 55U },
3076
  { Mips::W24, 56U },
3077
  { Mips::W25, 57U },
3078
  { Mips::W26, 58U },
3079
  { Mips::W27, 59U },
3080
  { Mips::W28, 60U },
3081
  { Mips::W29, 61U },
3082
  { Mips::W30, 62U },
3083
  { Mips::W31, 63U },
3084
  { Mips::ZERO_64, 0U },
3085
  { Mips::A0_64, 4U },
3086
  { Mips::A1_64, 5U },
3087
  { Mips::A2_64, 6U },
3088
  { Mips::A3_64, 7U },
3089
  { Mips::D0_64, 32U },
3090
  { Mips::D1_64, 33U },
3091
  { Mips::D2_64, 34U },
3092
  { Mips::D3_64, 35U },
3093
  { Mips::D4_64, 36U },
3094
  { Mips::D5_64, 37U },
3095
  { Mips::D6_64, 38U },
3096
  { Mips::D7_64, 39U },
3097
  { Mips::D8_64, 40U },
3098
  { Mips::D9_64, 41U },
3099
  { Mips::D10_64, 42U },
3100
  { Mips::D11_64, 43U },
3101
  { Mips::D12_64, 44U },
3102
  { Mips::D13_64, 45U },
3103
  { Mips::D14_64, 46U },
3104
  { Mips::D15_64, 47U },
3105
  { Mips::D16_64, 48U },
3106
  { Mips::D17_64, 49U },
3107
  { Mips::D18_64, 50U },
3108
  { Mips::D19_64, 51U },
3109
  { Mips::D20_64, 52U },
3110
  { Mips::D21_64, 53U },
3111
  { Mips::D22_64, 54U },
3112
  { Mips::D23_64, 55U },
3113
  { Mips::D24_64, 56U },
3114
  { Mips::D25_64, 57U },
3115
  { Mips::D26_64, 58U },
3116
  { Mips::D27_64, 59U },
3117
  { Mips::D28_64, 60U },
3118
  { Mips::D29_64, 61U },
3119
  { Mips::D30_64, 62U },
3120
  { Mips::D31_64, 63U },
3121
  { Mips::K0_64, 26U },
3122
  { Mips::K1_64, 27U },
3123
  { Mips::S0_64, 16U },
3124
  { Mips::S1_64, 17U },
3125
  { Mips::S2_64, 18U },
3126
  { Mips::S3_64, 19U },
3127
  { Mips::S4_64, 20U },
3128
  { Mips::S5_64, 21U },
3129
  { Mips::S6_64, 22U },
3130
  { Mips::S7_64, 23U },
3131
  { Mips::T0_64, 8U },
3132
  { Mips::T1_64, 9U },
3133
  { Mips::T2_64, 10U },
3134
  { Mips::T3_64, 11U },
3135
  { Mips::T4_64, 12U },
3136
  { Mips::T5_64, 13U },
3137
  { Mips::T6_64, 14U },
3138
  { Mips::T7_64, 15U },
3139
  { Mips::T8_64, 24U },
3140
  { Mips::T9_64, 25U },
3141
  { Mips::V0_64, 2U },
3142
  { Mips::V1_64, 3U },
3143
};
3144
extern const unsigned MipsDwarfFlavour0L2DwarfSize = array_lengthof(MipsDwarfFlavour0L2Dwarf);
3145
3146
extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[] = {
3147
  { Mips::AT, 1U },
3148
  { Mips::FP, 30U },
3149
  { Mips::GP, 28U },
3150
  { Mips::RA, 31U },
3151
  { Mips::SP, 29U },
3152
  { Mips::ZERO, 0U },
3153
  { Mips::A0, 4U },
3154
  { Mips::A1, 5U },
3155
  { Mips::A2, 6U },
3156
  { Mips::A3, 7U },
3157
  { Mips::AT_64, 1U },
3158
  { Mips::F0, 32U },
3159
  { Mips::F1, 33U },
3160
  { Mips::F2, 34U },
3161
  { Mips::F3, 35U },
3162
  { Mips::F4, 36U },
3163
  { Mips::F5, 37U },
3164
  { Mips::F6, 38U },
3165
  { Mips::F7, 39U },
3166
  { Mips::F8, 40U },
3167
  { Mips::F9, 41U },
3168
  { Mips::F10, 42U },
3169
  { Mips::F11, 43U },
3170
  { Mips::F12, 44U },
3171
  { Mips::F13, 45U },
3172
  { Mips::F14, 46U },
3173
  { Mips::F15, 47U },
3174
  { Mips::F16, 48U },
3175
  { Mips::F17, 49U },
3176
  { Mips::F18, 50U },
3177
  { Mips::F19, 51U },
3178
  { Mips::F20, 52U },
3179
  { Mips::F21, 53U },
3180
  { Mips::F22, 54U },
3181
  { Mips::F23, 55U },
3182
  { Mips::F24, 56U },
3183
  { Mips::F25, 57U },
3184
  { Mips::F26, 58U },
3185
  { Mips::F27, 59U },
3186
  { Mips::F28, 60U },
3187
  { Mips::F29, 61U },
3188
  { Mips::F30, 62U },
3189
  { Mips::F31, 63U },
3190
  { Mips::FP_64, 30U },
3191
  { Mips::F_HI0, 32U },
3192
  { Mips::F_HI1, 33U },
3193
  { Mips::F_HI2, 34U },
3194
  { Mips::F_HI3, 35U },
3195
  { Mips::F_HI4, 36U },
3196
  { Mips::F_HI5, 37U },
3197
  { Mips::F_HI6, 38U },
3198
  { Mips::F_HI7, 39U },
3199
  { Mips::F_HI8, 40U },
3200
  { Mips::F_HI9, 41U },
3201
  { Mips::F_HI10, 42U },
3202
  { Mips::F_HI11, 43U },
3203
  { Mips::F_HI12, 44U },
3204
  { Mips::F_HI13, 45U },
3205
  { Mips::F_HI14, 46U },
3206
  { Mips::F_HI15, 47U },
3207
  { Mips::F_HI16, 48U },
3208
  { Mips::F_HI17, 49U },
3209
  { Mips::F_HI18, 50U },
3210
  { Mips::F_HI19, 51U },
3211
  { Mips::F_HI20, 52U },
3212
  { Mips::F_HI21, 53U },
3213
  { Mips::F_HI22, 54U },
3214
  { Mips::F_HI23, 55U },
3215
  { Mips::F_HI24, 56U },
3216
  { Mips::F_HI25, 57U },
3217
  { Mips::F_HI26, 58U },
3218
  { Mips::F_HI27, 59U },
3219
  { Mips::F_HI28, 60U },
3220
  { Mips::F_HI29, 61U },
3221
  { Mips::F_HI30, 62U },
3222
  { Mips::F_HI31, 63U },
3223
  { Mips::GP_64, 28U },
3224
  { Mips::HI0, 64U },
3225
  { Mips::HI1, 176U },
3226
  { Mips::HI2, 178U },
3227
  { Mips::HI3, 180U },
3228
  { Mips::K0, 26U },
3229
  { Mips::K1, 27U },
3230
  { Mips::LO0, 65U },
3231
  { Mips::LO1, 177U },
3232
  { Mips::LO2, 179U },
3233
  { Mips::LO3, 181U },
3234
  { Mips::RA_64, 31U },
3235
  { Mips::S0, 16U },
3236
  { Mips::S1, 17U },
3237
  { Mips::S2, 18U },
3238
  { Mips::S3, 19U },
3239
  { Mips::S4, 20U },
3240
  { Mips::S5, 21U },
3241
  { Mips::S6, 22U },
3242
  { Mips::S7, 23U },
3243
  { Mips::SP_64, 29U },
3244
  { Mips::T0, 8U },
3245
  { Mips::T1, 9U },
3246
  { Mips::T2, 10U },
3247
  { Mips::T3, 11U },
3248
  { Mips::T4, 12U },
3249
  { Mips::T5, 13U },
3250
  { Mips::T6, 14U },
3251
  { Mips::T7, 15U },
3252
  { Mips::T8, 24U },
3253
  { Mips::T9, 25U },
3254
  { Mips::V0, 2U },
3255
  { Mips::V1, 3U },
3256
  { Mips::W0, 32U },
3257
  { Mips::W1, 33U },
3258
  { Mips::W2, 34U },
3259
  { Mips::W3, 35U },
3260
  { Mips::W4, 36U },
3261
  { Mips::W5, 37U },
3262
  { Mips::W6, 38U },
3263
  { Mips::W7, 39U },
3264
  { Mips::W8, 40U },
3265
  { Mips::W9, 41U },
3266
  { Mips::W10, 42U },
3267
  { Mips::W11, 43U },
3268
  { Mips::W12, 44U },
3269
  { Mips::W13, 45U },
3270
  { Mips::W14, 46U },
3271
  { Mips::W15, 47U },
3272
  { Mips::W16, 48U },
3273
  { Mips::W17, 49U },
3274
  { Mips::W18, 50U },
3275
  { Mips::W19, 51U },
3276
  { Mips::W20, 52U },
3277
  { Mips::W21, 53U },
3278
  { Mips::W22, 54U },
3279
  { Mips::W23, 55U },
3280
  { Mips::W24, 56U },
3281
  { Mips::W25, 57U },
3282
  { Mips::W26, 58U },
3283
  { Mips::W27, 59U },
3284
  { Mips::W28, 60U },
3285
  { Mips::W29, 61U },
3286
  { Mips::W30, 62U },
3287
  { Mips::W31, 63U },
3288
  { Mips::ZERO_64, 0U },
3289
  { Mips::A0_64, 4U },
3290
  { Mips::A1_64, 5U },
3291
  { Mips::A2_64, 6U },
3292
  { Mips::A3_64, 7U },
3293
  { Mips::D0_64, 32U },
3294
  { Mips::D1_64, 33U },
3295
  { Mips::D2_64, 34U },
3296
  { Mips::D3_64, 35U },
3297
  { Mips::D4_64, 36U },
3298
  { Mips::D5_64, 37U },
3299
  { Mips::D6_64, 38U },
3300
  { Mips::D7_64, 39U },
3301
  { Mips::D8_64, 40U },
3302
  { Mips::D9_64, 41U },
3303
  { Mips::D10_64, 42U },
3304
  { Mips::D11_64, 43U },
3305
  { Mips::D12_64, 44U },
3306
  { Mips::D13_64, 45U },
3307
  { Mips::D14_64, 46U },
3308
  { Mips::D15_64, 47U },
3309
  { Mips::D16_64, 48U },
3310
  { Mips::D17_64, 49U },
3311
  { Mips::D18_64, 50U },
3312
  { Mips::D19_64, 51U },
3313
  { Mips::D20_64, 52U },
3314
  { Mips::D21_64, 53U },
3315
  { Mips::D22_64, 54U },
3316
  { Mips::D23_64, 55U },
3317
  { Mips::D24_64, 56U },
3318
  { Mips::D25_64, 57U },
3319
  { Mips::D26_64, 58U },
3320
  { Mips::D27_64, 59U },
3321
  { Mips::D28_64, 60U },
3322
  { Mips::D29_64, 61U },
3323
  { Mips::D30_64, 62U },
3324
  { Mips::D31_64, 63U },
3325
  { Mips::K0_64, 26U },
3326
  { Mips::K1_64, 27U },
3327
  { Mips::S0_64, 16U },
3328
  { Mips::S1_64, 17U },
3329
  { Mips::S2_64, 18U },
3330
  { Mips::S3_64, 19U },
3331
  { Mips::S4_64, 20U },
3332
  { Mips::S5_64, 21U },
3333
  { Mips::S6_64, 22U },
3334
  { Mips::S7_64, 23U },
3335
  { Mips::T0_64, 8U },
3336
  { Mips::T1_64, 9U },
3337
  { Mips::T2_64, 10U },
3338
  { Mips::T3_64, 11U },
3339
  { Mips::T4_64, 12U },
3340
  { Mips::T5_64, 13U },
3341
  { Mips::T6_64, 14U },
3342
  { Mips::T7_64, 15U },
3343
  { Mips::T8_64, 24U },
3344
  { Mips::T9_64, 25U },
3345
  { Mips::V0_64, 2U },
3346
  { Mips::V1_64, 3U },
3347
};
3348
extern const unsigned MipsEHFlavour0L2DwarfSize = array_lengthof(MipsEHFlavour0L2Dwarf);
3349
3350
extern const uint16_t MipsRegEncodingTable[] = {
3351
  0,
3352
  1,
3353
  0,
3354
  0,
3355
  0,
3356
  0,
3357
  0,
3358
  0,
3359
  30,
3360
  28,
3361
  2,
3362
  1,
3363
  0,
3364
  6,
3365
  4,
3366
  5,
3367
  3,
3368
  7,
3369
  0,
3370
  31,
3371
  29,
3372
  0,
3373
  4,
3374
  5,
3375
  6,
3376
  7,
3377
  0,
3378
  1,
3379
  2,
3380
  3,
3381
  1,
3382
  0,
3383
  1,
3384
  2,
3385
  3,
3386
  4,
3387
  5,
3388
  6,
3389
  7,
3390
  8,
3391
  9,
3392
  0,
3393
  1,
3394
  2,
3395
  3,
3396
  4,
3397
  5,
3398
  6,
3399
  7,
3400
  8,
3401
  9,
3402
  0,
3403
  1,
3404
  2,
3405
  3,
3406
  4,
3407
  5,
3408
  6,
3409
  7,
3410
  8,
3411
  9,
3412
  10,
3413
  11,
3414
  12,
3415
  13,
3416
  14,
3417
  15,
3418
  16,
3419
  17,
3420
  18,
3421
  19,
3422
  20,
3423
  21,
3424
  22,
3425
  23,
3426
  24,
3427
  25,
3428
  26,
3429
  27,
3430
  28,
3431
  29,
3432
  30,
3433
  31,
3434
  10,
3435
  11,
3436
  12,
3437
  13,
3438
  14,
3439
  15,
3440
  16,
3441
  17,
3442
  18,
3443
  19,
3444
  20,
3445
  21,
3446
  22,
3447
  23,
3448
  24,
3449
  25,
3450
  26,
3451
  27,
3452
  28,
3453
  29,
3454
  30,
3455
  31,
3456
  10,
3457
  11,
3458
  12,
3459
  13,
3460
  14,
3461
  15,
3462
  16,
3463
  17,
3464
  18,
3465
  19,
3466
  20,
3467
  21,
3468
  22,
3469
  23,
3470
  24,
3471
  25,
3472
  26,
3473
  27,
3474
  28,
3475
  29,
3476
  30,
3477
  31,
3478
  0,
3479
  2,
3480
  4,
3481
  6,
3482
  8,
3483
  10,
3484
  12,
3485
  14,
3486
  16,
3487
  18,
3488
  20,
3489
  22,
3490
  24,
3491
  26,
3492
  28,
3493
  30,
3494
  0,
3495
  0,
3496
  0,
3497
  0,
3498
  0,
3499
  1,
3500
  2,
3501
  3,
3502
  4,
3503
  5,
3504
  6,
3505
  7,
3506
  8,
3507
  9,
3508
  10,
3509
  11,
3510
  12,
3511
  13,
3512
  14,
3513
  15,
3514
  16,
3515
  17,
3516
  18,
3517
  19,
3518
  20,
3519
  21,
3520
  22,
3521
  23,
3522
  24,
3523
  25,
3524
  26,
3525
  27,
3526
  28,
3527
  29,
3528
  30,
3529
  31,
3530
  0,
3531
  1,
3532
  2,
3533
  3,
3534
  4,
3535
  5,
3536
  6,
3537
  7,
3538
  0,
3539
  1,
3540
  2,
3541
  3,
3542
  4,
3543
  5,
3544
  6,
3545
  7,
3546
  8,
3547
  9,
3548
  10,
3549
  11,
3550
  12,
3551
  13,
3552
  14,
3553
  15,
3554
  16,
3555
  17,
3556
  18,
3557
  19,
3558
  20,
3559
  21,
3560
  22,
3561
  23,
3562
  24,
3563
  25,
3564
  26,
3565
  27,
3566
  28,
3567
  29,
3568
  30,
3569
  31,
3570
  30,
3571
  0,
3572
  1,
3573
  2,
3574
  3,
3575
  4,
3576
  5,
3577
  6,
3578
  7,
3579
  8,
3580
  9,
3581
  10,
3582
  11,
3583
  12,
3584
  13,
3585
  14,
3586
  15,
3587
  16,
3588
  17,
3589
  18,
3590
  19,
3591
  20,
3592
  21,
3593
  22,
3594
  23,
3595
  24,
3596
  25,
3597
  26,
3598
  27,
3599
  28,
3600
  29,
3601
  30,
3602
  31,
3603
  28,
3604
  0,
3605
  1,
3606
  2,
3607
  3,
3608
  0,
3609
  1,
3610
  2,
3611
  3,
3612
  4,
3613
  5,
3614
  6,
3615
  7,
3616
  8,
3617
  9,
3618
  10,
3619
  11,
3620
  12,
3621
  13,
3622
  14,
3623
  15,
3624
  16,
3625
  17,
3626
  18,
3627
  19,
3628
  20,
3629
  21,
3630
  22,
3631
  23,
3632
  24,
3633
  25,
3634
  26,
3635
  27,
3636
  28,
3637
  29,
3638
  30,
3639
  31,
3640
  26,
3641
  27,
3642
  0,
3643
  1,
3644
  2,
3645
  3,
3646
  0,
3647
  1,
3648
  2,
3649
  0,
3650
  1,
3651
  2,
3652
  31,
3653
  16,
3654
  17,
3655
  18,
3656
  19,
3657
  20,
3658
  21,
3659
  22,
3660
  23,
3661
  29,
3662
  8,
3663
  9,
3664
  10,
3665
  11,
3666
  12,
3667
  13,
3668
  14,
3669
  15,
3670
  24,
3671
  25,
3672
  2,
3673
  3,
3674
  0,
3675
  1,
3676
  2,
3677
  3,
3678
  4,
3679
  5,
3680
  6,
3681
  7,
3682
  8,
3683
  9,
3684
  10,
3685
  11,
3686
  12,
3687
  13,
3688
  14,
3689
  15,
3690
  16,
3691
  17,
3692
  18,
3693
  19,
3694
  20,
3695
  21,
3696
  22,
3697
  23,
3698
  24,
3699
  25,
3700
  26,
3701
  27,
3702
  28,
3703
  29,
3704
  30,
3705
  31,
3706
  0,
3707
  4,
3708
  5,
3709
  6,
3710
  7,
3711
  0,
3712
  0,
3713
  1,
3714
  2,
3715
  3,
3716
  4,
3717
  5,
3718
  6,
3719
  7,
3720
  8,
3721
  9,
3722
  10,
3723
  11,
3724
  12,
3725
  13,
3726
  14,
3727
  15,
3728
  16,
3729
  17,
3730
  18,
3731
  19,
3732
  20,
3733
  21,
3734
  22,
3735
  23,
3736
  24,
3737
  25,
3738
  26,
3739
  27,
3740
  28,
3741
  29,
3742
  30,
3743
  31,
3744
  0,
3745
  0,
3746
  26,
3747
  27,
3748
  0,
3749
  16,
3750
  17,
3751
  18,
3752
  19,
3753
  20,
3754
  21,
3755
  22,
3756
  23,
3757
  8,
3758
  9,
3759
  10,
3760
  11,
3761
  12,
3762
  13,
3763
  14,
3764
  15,
3765
  24,
3766
  25,
3767
  2,
3768
  3,
3769
};
3770
3.56k
static inline void InitMipsMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
3771
3.56k
  RI->InitMCRegisterInfo(MipsRegDesc, 418, RA, PC, MipsMCRegisterClasses, 81, MipsRegUnitRoots, 297, MipsRegDiffLists, MipsLaneMaskLists, MipsRegStrings, MipsRegClassStrings, MipsSubRegIdxLists, 12,
3772
3.56k
MipsSubRegIdxRanges, MipsRegEncodingTable);
3773
3.56k
3774
3.56k
  switch (DwarfFlavour) {
3775
3.56k
  default:
3776
0
    llvm_unreachable("Unknown DWARF flavour");
3777
3.56k
  case 0:
3778
3.56k
    RI->mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);
3779
3.56k
    break;
3780
3.56k
  }
3781
3.56k
  switch (EHFlavour) {
3782
3.56k
  default:
3783
0
    llvm_unreachable("Unknown DWARF flavour");
3784
3.56k
  case 0:
3785
3.56k
    RI->mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);
3786
3.56k
    break;
3787
3.56k
  }
3788
3.56k
  switch (DwarfFlavour) {
3789
3.56k
  default:
3790
0
    llvm_unreachable("Unknown DWARF flavour");
3791
3.56k
  case 0:
3792
3.56k
    RI->mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false);
3793
3.56k
    break;
3794
3.56k
  }
3795
3.56k
  switch (EHFlavour) {
3796
3.56k
  default:
3797
0
    llvm_unreachable("Unknown DWARF flavour");
3798
3.56k
  case 0:
3799
3.56k
    RI->mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true);
3800
3.56k
    break;
3801
3.56k
  }
3802
3.56k
}
3803
3804
} // end namespace llvm
3805
3806
#endif // GET_REGINFO_MC_DESC
3807
3808
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
3809
|*                                                                            *|
3810
|* Register Information Header Fragment                                       *|
3811
|*                                                                            *|
3812
|* Automatically generated file, do not edit!                                 *|
3813
|*                                                                            *|
3814
\*===----------------------------------------------------------------------===*/
3815
3816
3817
#ifdef GET_REGINFO_HEADER
3818
#undef GET_REGINFO_HEADER
3819
3820
#include "llvm/CodeGen/TargetRegisterInfo.h"
3821
3822
namespace llvm {
3823
3824
class MipsFrameLowering;
3825
3826
struct MipsGenRegisterInfo : public TargetRegisterInfo {
3827
  explicit MipsGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
3828
      unsigned PC = 0, unsigned HwMode = 0);
3829
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
3830
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
3831
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
3832
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
3833
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
3834
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
3835
  unsigned getNumRegPressureSets() const override;
3836
  const char *getRegPressureSetName(unsigned Idx) const override;
3837
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
3838
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
3839
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
3840
  ArrayRef<const char *> getRegMaskNames() const override;
3841
  ArrayRef<const uint32_t *> getRegMasks() const override;
3842
  /// Devirtualized TargetFrameLowering.
3843
  static const MipsFrameLowering *getFrameLowering(
3844
      const MachineFunction &MF);
3845
};
3846
3847
namespace Mips { // Register classes
3848
  extern const TargetRegisterClass MSA128F16RegClass;
3849
  extern const TargetRegisterClass MSA128F16_with_sub_64_in_OddSPRegClass;
3850
  extern const TargetRegisterClass OddSPRegClass;
3851
  extern const TargetRegisterClass CCRRegClass;
3852
  extern const TargetRegisterClass COP0RegClass;
3853
  extern const TargetRegisterClass COP2RegClass;
3854
  extern const TargetRegisterClass COP3RegClass;
3855
  extern const TargetRegisterClass DSPRRegClass;
3856
  extern const TargetRegisterClass FGR32RegClass;
3857
  extern const TargetRegisterClass FGRCCRegClass;
3858
  extern const TargetRegisterClass FGRH32RegClass;
3859
  extern const TargetRegisterClass GPR32RegClass;
3860
  extern const TargetRegisterClass HWRegsRegClass;
3861
  extern const TargetRegisterClass GPR32NONZERORegClass;
3862
  extern const TargetRegisterClass OddSP_with_sub_hiRegClass;
3863
  extern const TargetRegisterClass FGR32_and_OddSPRegClass;
3864
  extern const TargetRegisterClass FGRH32_and_OddSPRegClass;
3865
  extern const TargetRegisterClass OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClass;
3866
  extern const TargetRegisterClass CPU16RegsPlusSPRegClass;
3867
  extern const TargetRegisterClass CPU16RegsRegClass;
3868
  extern const TargetRegisterClass FCCRegClass;
3869
  extern const TargetRegisterClass GPRMM16RegClass;
3870
  extern const TargetRegisterClass GPRMM16MovePRegClass;
3871
  extern const TargetRegisterClass GPRMM16ZeroRegClass;
3872
  extern const TargetRegisterClass MSACtrlRegClass;
3873
  extern const TargetRegisterClass OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClass;
3874
  extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass;
3875
  extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass;
3876
  extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass;
3877
  extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass;
3878
  extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass;
3879
  extern const TargetRegisterClass HI32DSPRegClass;
3880
  extern const TargetRegisterClass LO32DSPRegClass;
3881
  extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass;
3882
  extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass;
3883
  extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;
3884
  extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass;
3885
  extern const TargetRegisterClass CPURARegRegClass;
3886
  extern const TargetRegisterClass CPUSPRegRegClass;
3887
  extern const TargetRegisterClass DSPCCRegClass;
3888
  extern const TargetRegisterClass GP32RegClass;
3889
  extern const TargetRegisterClass GPR32ZERORegClass;
3890
  extern const TargetRegisterClass HI32RegClass;
3891
  extern const TargetRegisterClass LO32RegClass;
3892
  extern const TargetRegisterClass SP32RegClass;
3893
  extern const TargetRegisterClass FGR64RegClass;
3894
  extern const TargetRegisterClass GPR64RegClass;
3895
  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass;
3896
  extern const TargetRegisterClass AFGR64RegClass;
3897
  extern const TargetRegisterClass FGR64_and_OddSPRegClass;
3898
  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass;
3899
  extern const TargetRegisterClass AFGR64_and_OddSPRegClass;
3900
  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass;
3901
  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass;
3902
  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass;
3903
  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass;
3904
  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass;
3905
  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass;
3906
  extern const TargetRegisterClass ACC64DSPRegClass;
3907
  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass;
3908
  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass;
3909
  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass;
3910
  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass;
3911
  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;
3912
  extern const TargetRegisterClass OCTEON_MPLRegClass;
3913
  extern const TargetRegisterClass OCTEON_PRegClass;
3914
  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass;
3915
  extern const TargetRegisterClass ACC64RegClass;
3916
  extern const TargetRegisterClass GP64RegClass;
3917
  extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass;
3918
  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass;
3919
  extern const TargetRegisterClass HI64RegClass;
3920
  extern const TargetRegisterClass LO64RegClass;
3921
  extern const TargetRegisterClass SP64RegClass;
3922
  extern const TargetRegisterClass MSA128BRegClass;
3923
  extern const TargetRegisterClass MSA128DRegClass;
3924
  extern const TargetRegisterClass MSA128HRegClass;
3925
  extern const TargetRegisterClass MSA128WRegClass;
3926
  extern const TargetRegisterClass MSA128B_with_sub_64_in_OddSPRegClass;
3927
  extern const TargetRegisterClass MSA128WEvensRegClass;
3928
  extern const TargetRegisterClass ACC128RegClass;
3929
} // end namespace Mips
3930
3931
} // end namespace llvm
3932
3933
#endif // GET_REGINFO_HEADER
3934
3935
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
3936
|*                                                                            *|
3937
|* Target Register and Register Classes Information                           *|
3938
|*                                                                            *|
3939
|* Automatically generated file, do not edit!                                 *|
3940
|*                                                                            *|
3941
\*===----------------------------------------------------------------------===*/
3942
3943
3944
#ifdef GET_REGINFO_TARGET_DESC
3945
#undef GET_REGINFO_TARGET_DESC
3946
3947
namespace llvm {
3948
3949
extern const MCRegisterClass MipsMCRegisterClasses[];
3950
3951
static const MVT::SimpleValueType VTLists[] = {
3952
  /* 0 */ MVT::i32, MVT::Other,
3953
  /* 2 */ MVT::i64, MVT::Other,
3954
  /* 4 */ MVT::f16, MVT::Other,
3955
  /* 6 */ MVT::f32, MVT::Other,
3956
  /* 8 */ MVT::f64, MVT::Other,
3957
  /* 10 */ MVT::v16i8, MVT::Other,
3958
  /* 12 */ MVT::v4i8, MVT::v2i16, MVT::Other,
3959
  /* 15 */ MVT::v8i16, MVT::v8f16, MVT::Other,
3960
  /* 18 */ MVT::v4i32, MVT::v4f32, MVT::Other,
3961
  /* 21 */ MVT::v2i64, MVT::v2f64, MVT::Other,
3962
  /* 24 */ MVT::Untyped, MVT::Other,
3963
};
3964
3965
static const char *const SubRegIndexNameTable[] = { "sub_32", "sub_64", "sub_dsp16_19", "sub_dsp20", "sub_dsp21", "sub_dsp22", "sub_dsp23", "sub_hi", "sub_lo", "sub_hi_then_sub_32", "sub_32_sub_hi_then_sub_32", "" };
3966
3967
3968
static const LaneBitmask SubRegIndexLaneMaskTable[] = {
3969
  LaneBitmask::getAll(),
3970
  LaneBitmask(0x00000001), // sub_32
3971
  LaneBitmask(0x00000041), // sub_64
3972
  LaneBitmask(0x00000002), // sub_dsp16_19
3973
  LaneBitmask(0x00000004), // sub_dsp20
3974
  LaneBitmask(0x00000008), // sub_dsp21
3975
  LaneBitmask(0x00000010), // sub_dsp22
3976
  LaneBitmask(0x00000020), // sub_dsp23
3977
  LaneBitmask(0x00000040), // sub_hi
3978
  LaneBitmask(0x00000001), // sub_lo
3979
  LaneBitmask(0x00000040), // sub_hi_then_sub_32
3980
  LaneBitmask(0x00000041), // sub_32_sub_hi_then_sub_32
3981
 };
3982
3983
3984
3985
static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
3986
  // Mode = 0 (Default)
3987
  { 16, 16, 128, VTLists+4 },    // MSA128F16
3988
  { 16, 16, 128, VTLists+4 },    // MSA128F16_with_sub_64_in_OddSP
3989
  { 32, 32, 32, VTLists+6 },    // OddSP
3990
  { 32, 32, 32, VTLists+0 },    // CCR
3991
  { 32, 32, 32, VTLists+0 },    // COP0
3992
  { 32, 32, 32, VTLists+0 },    // COP2
3993
  { 32, 32, 32, VTLists+0 },    // COP3
3994
  { 32, 32, 32, VTLists+12 },    // DSPR
3995
  { 32, 32, 32, VTLists+6 },    // FGR32
3996
  { 32, 32, 32, VTLists+0 },    // FGRCC
3997
  { 32, 32, 32, VTLists+6 },    // FGRH32
3998
  { 32, 32, 32, VTLists+0 },    // GPR32
3999
  { 32, 32, 32, VTLists+0 },    // HWRegs
4000
  { 32, 32, 32, VTLists+0 },    // GPR32NONZERO
4001
  { 32, 32, 32, VTLists+6 },    // OddSP_with_sub_hi
4002
  { 32, 32, 32, VTLists+0 },    // FGR32_and_OddSP
4003
  { 32, 32, 32, VTLists+6 },    // FGRH32_and_OddSP
4004
  { 32, 32, 32, VTLists+6 },    // OddSP_with_sub_hi_with_sub_hi_in_FGRH32
4005
  { 32, 32, 32, VTLists+0 },    // CPU16RegsPlusSP
4006
  { 32, 32, 32, VTLists+0 },    // CPU16Regs
4007
  { 32, 32, 32, VTLists+0 },    // FCC
4008
  { 32, 32, 32, VTLists+0 },    // GPRMM16
4009
  { 32, 32, 32, VTLists+0 },    // GPRMM16MoveP
4010
  { 32, 32, 32, VTLists+0 },    // GPRMM16Zero
4011
  { 32, 32, 32, VTLists+0 },    // MSACtrl
4012
  { 32, 32, 32, VTLists+6 },    // OddSP_with_sub_hi_with_sub_hi_in_FGR32
4013
  { 32, 32, 32, VTLists+0 },    // CPU16Regs_and_GPRMM16Zero
4014
  { 32, 32, 32, VTLists+0 },    // GPR32NONZERO_and_GPRMM16MoveP
4015
  { 32, 32, 32, VTLists+0 },    // GPRMM16MovePPairSecond
4016
  { 32, 32, 32, VTLists+0 },    // CPU16Regs_and_GPRMM16MoveP
4017
  { 32, 32, 32, VTLists+0 },    // GPRMM16MoveP_and_GPRMM16Zero
4018
  { 32, 32, 32, VTLists+0 },    // HI32DSP
4019
  { 32, 32, 32, VTLists+0 },    // LO32DSP
4020
  { 32, 32, 32, VTLists+0 },    // CPU16Regs_and_GPRMM16MovePPairSecond
4021
  { 32, 32, 32, VTLists+0 },    // GPRMM16MovePPairFirst
4022
  { 32, 32, 32, VTLists+0 },    // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
4023
  { 32, 32, 32, VTLists+0 },    // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
4024
  { 32, 32, 32, VTLists+0 },    // CPURAReg
4025
  { 32, 32, 32, VTLists+0 },    // CPUSPReg
4026
  { 32, 32, 32, VTLists+12 },    // DSPCC
4027
  { 32, 32, 32, VTLists+0 },    // GP32
4028
  { 32, 32, 32, VTLists+0 },    // GPR32ZERO
4029
  { 32, 32, 32, VTLists+0 },    // HI32
4030
  { 32, 32, 32, VTLists+0 },    // LO32
4031
  { 32, 32, 32, VTLists+0 },    // SP32
4032
  { 64, 64, 64, VTLists+8 },    // FGR64
4033
  { 64, 64, 64, VTLists+2 },    // GPR64
4034
  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPR32NONZERO
4035
  { 64, 64, 64, VTLists+8 },    // AFGR64
4036
  { 64, 64, 64, VTLists+8 },    // FGR64_and_OddSP
4037
  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_CPU16RegsPlusSP
4038
  { 64, 64, 64, VTLists+8 },    // AFGR64_and_OddSP
4039
  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_CPU16Regs
4040
  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPRMM16MoveP
4041
  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPRMM16Zero
4042
  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
4043
  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
4044
  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
4045
  { 64, 64, 64, VTLists+24 },    // ACC64DSP
4046
  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
4047
  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
4048
  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
4049
  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
4050
  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
4051
  { 64, 64, 64, VTLists+2 },    // OCTEON_MPL
4052
  { 64, 64, 64, VTLists+2 },    // OCTEON_P
4053
  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
4054
  { 64, 64, 64, VTLists+24 },    // ACC64
4055
  { 64, 64, 64, VTLists+2 },    // GP64
4056
  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_CPURAReg
4057
  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPR32ZERO
4058
  { 64, 64, 64, VTLists+2 },    // HI64
4059
  { 64, 64, 64, VTLists+2 },    // LO64
4060
  { 64, 64, 64, VTLists+2 },    // SP64
4061
  { 128, 128, 128, VTLists+10 },    // MSA128B
4062
  { 128, 128, 128, VTLists+21 },    // MSA128D
4063
  { 128, 128, 128, VTLists+15 },    // MSA128H
4064
  { 128, 128, 128, VTLists+18 },    // MSA128W
4065
  { 128, 128, 128, VTLists+18 },    // MSA128B_with_sub_64_in_OddSP
4066
  { 128, 128, 128, VTLists+18 },    // MSA128WEvens
4067
  { 128, 128, 128, VTLists+24 },    // ACC128
4068
};
4069
4070
static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
4071
4072
static const uint32_t MSA128F16SubClassMask[] = {
4073
  0x00000003, 0x00000000, 0x0000fc00, 
4074
};
4075
4076
static const uint32_t MSA128F16_with_sub_64_in_OddSPSubClassMask[] = {
4077
  0x00000002, 0x00000000, 0x00004000, 
4078
};
4079
4080
static const uint32_t OddSPSubClassMask[] = {
4081
  0x0203c004, 0x000a0000, 0x00000000, 
4082
  0x00000002, 0x00000000, 0x00004000, // sub_64
4083
  0x02024002, 0x000b0000, 0x00004000, // sub_hi
4084
  0x00020002, 0x00020000, 0x00004000, // sub_lo
4085
};
4086
4087
static const uint32_t CCRSubClassMask[] = {
4088
  0x00000008, 0x00000000, 0x00000000, 
4089
};
4090
4091
static const uint32_t COP0SubClassMask[] = {
4092
  0x00000010, 0x00000000, 0x00000000, 
4093
};
4094
4095
static const uint32_t COP2SubClassMask[] = {
4096
  0x00000020, 0x00000000, 0x00000000, 
4097
};
4098
4099
static const uint32_t COP3SubClassMask[] = {
4100
  0x00000040, 0x00000000, 0x00000000, 
4101
};
4102
4103
static const uint32_t DSPRSubClassMask[] = {
4104
  0x7cec2880, 0x0000137e, 0x00000000, 
4105
  0x00000000, 0xfbf4c000, 0x00000274, // sub_32
4106
};
4107
4108
static const uint32_t FGR32SubClassMask[] = {
4109
  0x00008300, 0x00000000, 0x00000000, 
4110
  0x02000000, 0x00090000, 0x00000000, // sub_hi
4111
  0x02024003, 0x000b2000, 0x0000fc00, // sub_lo
4112
};
4113
4114
static const uint32_t FGRCCSubClassMask[] = {
4115
  0x00008300, 0x00000000, 0x00000000, 
4116
  0x02000000, 0x00090000, 0x00000000, // sub_hi
4117
  0x02024003, 0x000b2000, 0x0000fc00, // sub_lo
4118
};
4119
4120
static const uint32_t FGRH32SubClassMask[] = {
4121
  0x00010400, 0x00000000, 0x00000000, 
4122
  0x00020003, 0x00022000, 0x0000fc00, // sub_hi
4123
};
4124
4125
static const uint32_t GPR32SubClassMask[] = {
4126
  0x7cec2800, 0x0000137e, 0x00000000, 
4127
  0x00000000, 0xfbf4c000, 0x00000274, // sub_32
4128
};
4129
4130
static const uint32_t HWRegsSubClassMask[] = {
4131
  0x00001000, 0x00000000, 0x00000000, 
4132
};
4133
4134
static const uint32_t GPR32NONZEROSubClassMask[] = {
4135
  0x3c2c2000, 0x0000117e, 0x00000000, 
4136
  0x00000000, 0xeb948000, 0x00000234, // sub_32
4137
};
4138
4139
static const uint32_t OddSP_with_sub_hiSubClassMask[] = {
4140
  0x02024000, 0x000a0000, 0x00000000, 
4141
  0x00000002, 0x00000000, 0x00004000, // sub_64
4142
};
4143
4144
static const uint32_t FGR32_and_OddSPSubClassMask[] = {
4145
  0x00008000, 0x00000000, 0x00000000, 
4146
  0x02000000, 0x00090000, 0x00000000, // sub_hi
4147
  0x00020002, 0x00020000, 0x00004000, // sub_lo
4148
};
4149
4150
static const uint32_t FGRH32_and_OddSPSubClassMask[] = {
4151
  0x00010000, 0x00000000, 0x00000000, 
4152
  0x00020002, 0x00020000, 0x00004000, // sub_hi
4153
};
4154
4155
static const uint32_t OddSP_with_sub_hi_with_sub_hi_in_FGRH32SubClassMask[] = {
4156
  0x00020000, 0x00020000, 0x00000000, 
4157
  0x00000002, 0x00000000, 0x00004000, // sub_64
4158
};
4159
4160
static const uint32_t CPU16RegsPlusSPSubClassMask[] = {
4161
  0x242c0000, 0x0000105e, 0x00000000, 
4162
  0x00000000, 0xe8940000, 0x00000204, // sub_32
4163
};
4164
4165
static const uint32_t CPU16RegsSubClassMask[] = {
4166
  0x24280000, 0x0000001e, 0x00000000, 
4167
  0x00000000, 0xe8900000, 0x00000004, // sub_32
4168
};
4169
4170
static const uint32_t FCCSubClassMask[] = {
4171
  0x00100000, 0x00000000, 0x00000000, 
4172
};
4173
4174
static const uint32_t GPRMM16SubClassMask[] = {
4175
  0x24200000, 0x0000001e, 0x00000000, 
4176
  0x00000000, 0xe8900000, 0x00000004, // sub_32
4177
};
4178
4179
static const uint32_t GPRMM16MovePSubClassMask[] = {
4180
  0x68400000, 0x00000208, 0x00000000, 
4181
  0x00000000, 0x99200000, 0x00000040, // sub_32
4182
};
4183
4184
static const uint32_t GPRMM16ZeroSubClassMask[] = {
4185
  0x44800000, 0x0000021e, 0x00000000, 
4186
  0x00000000, 0xf0c00000, 0x00000044, // sub_32
4187
};
4188
4189
static const uint32_t MSACtrlSubClassMask[] = {
4190
  0x01000000, 0x00000000, 0x00000000, 
4191
};
4192
4193
static const uint32_t OddSP_with_sub_hi_with_sub_hi_in_FGR32SubClassMask[] = {
4194
  0x02000000, 0x00080000, 0x00000000, 
4195
};
4196
4197
static const uint32_t CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4198
  0x04000000, 0x0000001e, 0x00000000, 
4199
  0x00000000, 0xe0800000, 0x00000004, // sub_32
4200
};
4201
4202
static const uint32_t GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {
4203
  0x28000000, 0x00000008, 0x00000000, 
4204
  0x00000000, 0x89000000, 0x00000000, // sub_32
4205
};
4206
4207
static const uint32_t GPRMM16MovePPairSecondSubClassMask[] = {
4208
  0x10000000, 0x00000012, 0x00000000, 
4209
  0x00000000, 0x22000000, 0x00000004, // sub_32
4210
};
4211
4212
static const uint32_t CPU16Regs_and_GPRMM16MovePSubClassMask[] = {
4213
  0x20000000, 0x00000008, 0x00000000, 
4214
  0x00000000, 0x88000000, 0x00000000, // sub_32
4215
};
4216
4217
static const uint32_t GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {
4218
  0x40000000, 0x00000208, 0x00000000, 
4219
  0x00000000, 0x90000000, 0x00000040, // sub_32
4220
};
4221
4222
static const uint32_t HI32DSPSubClassMask[] = {
4223
  0x80000000, 0x00000400, 0x00000000, 
4224
  0x00000000, 0x00000000, 0x00000080, // sub_32
4225
  0x00000000, 0x04000000, 0x00000008, // sub_hi
4226
  0x00000000, 0x00000000, 0x00010000, // sub_hi_then_sub_32
4227
};
4228
4229
static const uint32_t LO32DSPSubClassMask[] = {
4230
  0x00000000, 0x00000801, 0x00000000, 
4231
  0x00000000, 0x00000000, 0x00010100, // sub_32
4232
  0x00000000, 0x04000000, 0x00000008, // sub_lo
4233
};
4234
4235
static const uint32_t CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {
4236
  0x00000000, 0x00000012, 0x00000000, 
4237
  0x00000000, 0x20000000, 0x00000004, // sub_32
4238
};
4239
4240
static const uint32_t GPRMM16MovePPairFirstSubClassMask[] = {
4241
  0x00000000, 0x00000014, 0x00000000, 
4242
  0x00000000, 0x40000000, 0x00000004, // sub_32
4243
};
4244
4245
static const uint32_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4246
  0x00000000, 0x00000008, 0x00000000, 
4247
  0x00000000, 0x80000000, 0x00000000, // sub_32
4248
};
4249
4250
static const uint32_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {
4251
  0x00000000, 0x00000010, 0x00000000, 
4252
  0x00000000, 0x00000000, 0x00000004, // sub_32
4253
};
4254
4255
static const uint32_t CPURARegSubClassMask[] = {
4256
  0x00000000, 0x00000020, 0x00000000, 
4257
  0x00000000, 0x00000000, 0x00000020, // sub_32
4258
};
4259
4260
static const uint32_t CPUSPRegSubClassMask[] = {
4261
  0x00000000, 0x00001040, 0x00000000, 
4262
  0x00000000, 0x00000000, 0x00000200, // sub_32
4263
};
4264
4265
static const uint32_t DSPCCSubClassMask[] = {
4266
  0x00000000, 0x00000080, 0x00000000, 
4267
};
4268
4269
static const uint32_t GP32SubClassMask[] = {
4270
  0x00000000, 0x00000100, 0x00000000, 
4271
  0x00000000, 0x00000000, 0x00000010, // sub_32
4272
};
4273
4274
static const uint32_t GPR32ZEROSubClassMask[] = {
4275
  0x00000000, 0x00000200, 0x00000000, 
4276
  0x00000000, 0x00000000, 0x00000040, // sub_32
4277
};
4278
4279
static const uint32_t HI32SubClassMask[] = {
4280
  0x00000000, 0x00000400, 0x00000000, 
4281
  0x00000000, 0x00000000, 0x00000080, // sub_32
4282
  0x00000000, 0x00000000, 0x00000008, // sub_hi
4283
  0x00000000, 0x00000000, 0x00010000, // sub_hi_then_sub_32
4284
};
4285
4286
static const uint32_t LO32SubClassMask[] = {
4287
  0x00000000, 0x00000800, 0x00000000, 
4288
  0x00000000, 0x00000000, 0x00010100, // sub_32
4289
  0x00000000, 0x00000000, 0x00000008, // sub_lo
4290
};
4291
4292
static const uint32_t SP32SubClassMask[] = {
4293
  0x00000000, 0x00001000, 0x00000000, 
4294
  0x00000000, 0x00000000, 0x00000200, // sub_32
4295
};
4296
4297
static const uint32_t FGR64SubClassMask[] = {
4298
  0x00000000, 0x00022000, 0x00000000, 
4299
  0x00000003, 0x00000000, 0x0000fc00, // sub_64
4300
};
4301
4302
static const uint32_t GPR64SubClassMask[] = {
4303
  0x00000000, 0xfbf4c000, 0x00000274, 
4304
};
4305
4306
static const uint32_t GPR64_with_sub_32_in_GPR32NONZEROSubClassMask[] = {
4307
  0x00000000, 0xeb948000, 0x00000234, 
4308
};
4309
4310
static const uint32_t AFGR64SubClassMask[] = {
4311
  0x00000000, 0x00090000, 0x00000000, 
4312
};
4313
4314
static const uint32_t FGR64_and_OddSPSubClassMask[] = {
4315
  0x00000000, 0x00020000, 0x00000000, 
4316
  0x00000002, 0x00000000, 0x00004000, // sub_64
4317
};
4318
4319
static const uint32_t GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask[] = {
4320
  0x00000000, 0xe8940000, 0x00000204, 
4321
};
4322
4323
static const uint32_t AFGR64_and_OddSPSubClassMask[] = {
4324
  0x00000000, 0x00080000, 0x00000000, 
4325
};
4326
4327
static const uint32_t GPR64_with_sub_32_in_CPU16RegsSubClassMask[] = {
4328
  0x00000000, 0xe8900000, 0x00000004, 
4329
};
4330
4331
static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePSubClassMask[] = {
4332
  0x00000000, 0x99200000, 0x00000040, 
4333
};
4334
4335
static const uint32_t GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask[] = {
4336
  0x00000000, 0xf0c00000, 0x00000044, 
4337
};
4338
4339
static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4340
  0x00000000, 0xe0800000, 0x00000004, 
4341
};
4342
4343
static const uint32_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {
4344
  0x00000000, 0x89000000, 0x00000000, 
4345
};
4346
4347
static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask[] = {
4348
  0x00000000, 0x22000000, 0x00000004, 
4349
};
4350
4351
static const uint32_t ACC64DSPSubClassMask[] = {
4352
  0x00000000, 0x04000000, 0x00000008, 
4353
  0x00000000, 0x00000000, 0x00010000, // sub_32_sub_hi_then_sub_32
4354
};
4355
4356
static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask[] = {
4357
  0x00000000, 0x88000000, 0x00000000, 
4358
};
4359
4360
static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {
4361
  0x00000000, 0x90000000, 0x00000040, 
4362
};
4363
4364
static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {
4365
  0x00000000, 0x20000000, 0x00000004, 
4366
};
4367
4368
static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask[] = {
4369
  0x00000000, 0x40000000, 0x00000004, 
4370
};
4371
4372
static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4373
  0x00000000, 0x80000000, 0x00000000, 
4374
};
4375
4376
static const uint32_t OCTEON_MPLSubClassMask[] = {
4377
  0x00000000, 0x00000000, 0x00000001, 
4378
};
4379
4380
static const uint32_t OCTEON_PSubClassMask[] = {
4381
  0x00000000, 0x00000000, 0x00000002, 
4382
};
4383
4384
static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {
4385
  0x00000000, 0x00000000, 0x00000004, 
4386
};
4387
4388
static const uint32_t ACC64SubClassMask[] = {
4389
  0x00000000, 0x00000000, 0x00000008, 
4390
  0x00000000, 0x00000000, 0x00010000, // sub_32_sub_hi_then_sub_32
4391
};
4392
4393
static const uint32_t GP64SubClassMask[] = {
4394
  0x00000000, 0x00000000, 0x00000010, 
4395
};
4396
4397
static const uint32_t GPR64_with_sub_32_in_CPURARegSubClassMask[] = {
4398
  0x00000000, 0x00000000, 0x00000020, 
4399
};
4400
4401
static const uint32_t GPR64_with_sub_32_in_GPR32ZEROSubClassMask[] = {
4402
  0x00000000, 0x00000000, 0x00000040, 
4403
};
4404
4405
static const uint32_t HI64SubClassMask[] = {
4406
  0x00000000, 0x00000000, 0x00000080, 
4407
  0x00000000, 0x00000000, 0x00010000, // sub_hi
4408
};
4409
4410
static const uint32_t LO64SubClassMask[] = {
4411
  0x00000000, 0x00000000, 0x00000100, 
4412
  0x00000000, 0x00000000, 0x00010000, // sub_lo
4413
};
4414
4415
static const uint32_t SP64SubClassMask[] = {
4416
  0x00000000, 0x00000000, 0x00000200, 
4417
};
4418
4419
static const uint32_t MSA128BSubClassMask[] = {
4420
  0x00000000, 0x00000000, 0x0000fc00, 
4421
};
4422
4423
static const uint32_t MSA128DSubClassMask[] = {
4424
  0x00000000, 0x00000000, 0x0000fc00, 
4425
};
4426
4427
static const uint32_t MSA128HSubClassMask[] = {
4428
  0x00000000, 0x00000000, 0x0000fc00, 
4429
};
4430
4431
static const uint32_t MSA128WSubClassMask[] = {
4432
  0x00000000, 0x00000000, 0x0000fc00, 
4433
};
4434
4435
static const uint32_t MSA128B_with_sub_64_in_OddSPSubClassMask[] = {
4436
  0x00000000, 0x00000000, 0x00004000, 
4437
};
4438
4439
static const uint32_t MSA128WEvensSubClassMask[] = {
4440
  0x00000000, 0x00000000, 0x00008000, 
4441
};
4442
4443
static const uint32_t ACC128SubClassMask[] = {
4444
  0x00000000, 0x00000000, 0x00010000, 
4445
};
4446
4447
static const uint16_t SuperRegIdxSeqs[] = {
4448
  /* 0 */ 1, 0,
4449
  /* 2 */ 2, 0,
4450
  /* 4 */ 8, 0,
4451
  /* 6 */ 1, 9, 0,
4452
  /* 9 */ 2, 8, 9, 0,
4453
  /* 13 */ 1, 8, 10, 0,
4454
  /* 17 */ 11, 0,
4455
};
4456
4457
static const TargetRegisterClass *const MSA128F16_with_sub_64_in_OddSPSuperclasses[] = {
4458
  &Mips::MSA128F16RegClass,
4459
  nullptr
4460
};
4461
4462
static const TargetRegisterClass *const FGR32Superclasses[] = {
4463
  &Mips::FGRCCRegClass,
4464
  nullptr
4465
};
4466
4467
static const TargetRegisterClass *const FGRCCSuperclasses[] = {
4468
  &Mips::FGR32RegClass,
4469
  nullptr
4470
};
4471
4472
static const TargetRegisterClass *const GPR32Superclasses[] = {
4473
  &Mips::DSPRRegClass,
4474
  nullptr
4475
};
4476
4477
static const TargetRegisterClass *const GPR32NONZEROSuperclasses[] = {
4478
  &Mips::DSPRRegClass,
4479
  &Mips::GPR32RegClass,
4480
  nullptr
4481
};
4482
4483
static const TargetRegisterClass *const OddSP_with_sub_hiSuperclasses[] = {
4484
  &Mips::OddSPRegClass,
4485
  nullptr
4486
};
4487
4488
static const TargetRegisterClass *const FGR32_and_OddSPSuperclasses[] = {
4489
  &Mips::OddSPRegClass,
4490
  &Mips::FGR32RegClass,
4491
  &Mips::FGRCCRegClass,
4492
  nullptr
4493
};
4494
4495
static const TargetRegisterClass *const FGRH32_and_OddSPSuperclasses[] = {
4496
  &Mips::OddSPRegClass,
4497
  &Mips::FGRH32RegClass,
4498
  nullptr
4499
};
4500
4501
static const TargetRegisterClass *const OddSP_with_sub_hi_with_sub_hi_in_FGRH32Superclasses[] = {
4502
  &Mips::OddSPRegClass,
4503
  &Mips::OddSP_with_sub_hiRegClass,
4504
  nullptr
4505
};
4506
4507
static const TargetRegisterClass *const CPU16RegsPlusSPSuperclasses[] = {
4508
  &Mips::DSPRRegClass,
4509
  &Mips::GPR32RegClass,
4510
  &Mips::GPR32NONZERORegClass,
4511
  nullptr
4512
};
4513
4514
static const TargetRegisterClass *const CPU16RegsSuperclasses[] = {
4515
  &Mips::DSPRRegClass,
4516
  &Mips::GPR32RegClass,
4517
  &Mips::GPR32NONZERORegClass,
4518
  &Mips::CPU16RegsPlusSPRegClass,
4519
  nullptr
4520
};
4521
4522
static const TargetRegisterClass *const GPRMM16Superclasses[] = {
4523
  &Mips::DSPRRegClass,
4524
  &Mips::GPR32RegClass,
4525
  &Mips::GPR32NONZERORegClass,
4526
  &Mips::CPU16RegsPlusSPRegClass,
4527
  &Mips::CPU16RegsRegClass,
4528
  nullptr
4529
};
4530
4531
static const TargetRegisterClass *const GPRMM16MovePSuperclasses[] = {
4532
  &Mips::DSPRRegClass,
4533
  &Mips::GPR32RegClass,
4534
  nullptr
4535
};
4536
4537
static const TargetRegisterClass *const GPRMM16ZeroSuperclasses[] = {
4538
  &Mips::DSPRRegClass,
4539
  &Mips::GPR32RegClass,
4540
  nullptr
4541
};
4542
4543
static const TargetRegisterClass *const OddSP_with_sub_hi_with_sub_hi_in_FGR32Superclasses[] = {
4544
  &Mips::OddSPRegClass,
4545
  &Mips::OddSP_with_sub_hiRegClass,
4546
  nullptr
4547
};
4548
4549
static const TargetRegisterClass *const CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4550
  &Mips::DSPRRegClass,
4551
  &Mips::GPR32RegClass,
4552
  &Mips::GPR32NONZERORegClass,
4553
  &Mips::CPU16RegsPlusSPRegClass,
4554
  &Mips::CPU16RegsRegClass,
4555
  &Mips::GPRMM16RegClass,
4556
  &Mips::GPRMM16ZeroRegClass,
4557
  nullptr
4558
};
4559
4560
static const TargetRegisterClass *const GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
4561
  &Mips::DSPRRegClass,
4562
  &Mips::GPR32RegClass,
4563
  &Mips::GPR32NONZERORegClass,
4564
  &Mips::GPRMM16MovePRegClass,
4565
  nullptr
4566
};
4567
4568
static const TargetRegisterClass *const GPRMM16MovePPairSecondSuperclasses[] = {
4569
  &Mips::DSPRRegClass,
4570
  &Mips::GPR32RegClass,
4571
  &Mips::GPR32NONZERORegClass,
4572
  nullptr
4573
};
4574
4575
static const TargetRegisterClass *const CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
4576
  &Mips::DSPRRegClass,
4577
  &Mips::GPR32RegClass,
4578
  &Mips::GPR32NONZERORegClass,
4579
  &Mips::CPU16RegsPlusSPRegClass,
4580
  &Mips::CPU16RegsRegClass,
4581
  &Mips::GPRMM16RegClass,
4582
  &Mips::GPRMM16MovePRegClass,
4583
  &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
4584
  nullptr
4585
};
4586
4587
static const TargetRegisterClass *const GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
4588
  &Mips::DSPRRegClass,
4589
  &Mips::GPR32RegClass,
4590
  &Mips::GPRMM16MovePRegClass,
4591
  &Mips::GPRMM16ZeroRegClass,
4592
  nullptr
4593
};
4594
4595
static const TargetRegisterClass *const CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {
4596
  &Mips::DSPRRegClass,
4597
  &Mips::GPR32RegClass,
4598
  &Mips::GPR32NONZERORegClass,
4599
  &Mips::CPU16RegsPlusSPRegClass,
4600
  &Mips::CPU16RegsRegClass,
4601
  &Mips::GPRMM16RegClass,
4602
  &Mips::GPRMM16ZeroRegClass,
4603
  &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
4604
  &Mips::GPRMM16MovePPairSecondRegClass,
4605
  nullptr
4606
};
4607
4608
static const TargetRegisterClass *const GPRMM16MovePPairFirstSuperclasses[] = {
4609
  &Mips::DSPRRegClass,
4610
  &Mips::GPR32RegClass,
4611
  &Mips::GPR32NONZERORegClass,
4612
  &Mips::CPU16RegsPlusSPRegClass,
4613
  &Mips::CPU16RegsRegClass,
4614
  &Mips::GPRMM16RegClass,
4615
  &Mips::GPRMM16ZeroRegClass,
4616
  &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
4617
  nullptr
4618
};
4619
4620
static const TargetRegisterClass *const GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4621
  &Mips::DSPRRegClass,
4622
  &Mips::GPR32RegClass,
4623
  &Mips::GPR32NONZERORegClass,
4624
  &Mips::CPU16RegsPlusSPRegClass,
4625
  &Mips::CPU16RegsRegClass,
4626
  &Mips::GPRMM16RegClass,
4627
  &Mips::GPRMM16MovePRegClass,
4628
  &Mips::GPRMM16ZeroRegClass,
4629
  &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
4630
  &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
4631
  &Mips::CPU16Regs_and_GPRMM16MovePRegClass,
4632
  &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
4633
  nullptr
4634
};
4635
4636
static const TargetRegisterClass *const GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {
4637
  &Mips::DSPRRegClass,
4638
  &Mips::GPR32RegClass,
4639
  &Mips::GPR32NONZERORegClass,
4640
  &Mips::CPU16RegsPlusSPRegClass,
4641
  &Mips::CPU16RegsRegClass,
4642
  &Mips::GPRMM16RegClass,
4643
  &Mips::GPRMM16ZeroRegClass,
4644
  &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
4645
  &Mips::GPRMM16MovePPairSecondRegClass,
4646
  &Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
4647
  &Mips::GPRMM16MovePPairFirstRegClass,
4648
  nullptr
4649
};
4650
4651
static const TargetRegisterClass *const CPURARegSuperclasses[] = {
4652
  &Mips::DSPRRegClass,
4653
  &Mips::GPR32RegClass,
4654
  &Mips::GPR32NONZERORegClass,
4655
  nullptr
4656
};
4657
4658
static const TargetRegisterClass *const CPUSPRegSuperclasses[] = {
4659
  &Mips::DSPRRegClass,
4660
  &Mips::GPR32RegClass,
4661
  &Mips::GPR32NONZERORegClass,
4662
  &Mips::CPU16RegsPlusSPRegClass,
4663
  nullptr
4664
};
4665
4666
static const TargetRegisterClass *const GP32Superclasses[] = {
4667
  &Mips::DSPRRegClass,
4668
  &Mips::GPR32RegClass,
4669
  &Mips::GPR32NONZERORegClass,
4670
  nullptr
4671
};
4672
4673
static const TargetRegisterClass *const GPR32ZEROSuperclasses[] = {
4674
  &Mips::DSPRRegClass,
4675
  &Mips::GPR32RegClass,
4676
  &Mips::GPRMM16MovePRegClass,
4677
  &Mips::GPRMM16ZeroRegClass,
4678
  &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
4679
  nullptr
4680
};
4681
4682
static const TargetRegisterClass *const HI32Superclasses[] = {
4683
  &Mips::HI32DSPRegClass,
4684
  nullptr
4685
};
4686
4687
static const TargetRegisterClass *const LO32Superclasses[] = {
4688
  &Mips::LO32DSPRegClass,
4689
  nullptr
4690
};
4691
4692
static const TargetRegisterClass *const SP32Superclasses[] = {
4693
  &Mips::DSPRRegClass,
4694
  &Mips::GPR32RegClass,
4695
  &Mips::GPR32NONZERORegClass,
4696
  &Mips::CPU16RegsPlusSPRegClass,
4697
  &Mips::CPUSPRegRegClass,
4698
  nullptr
4699
};
4700
4701
static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZEROSuperclasses[] = {
4702
  &Mips::GPR64RegClass,
4703
  nullptr
4704
};
4705
4706
static const TargetRegisterClass *const FGR64_and_OddSPSuperclasses[] = {
4707
  &Mips::OddSPRegClass,
4708
  &Mips::OddSP_with_sub_hiRegClass,
4709
  &Mips::OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClass,
4710
  &Mips::FGR64RegClass,
4711
  nullptr
4712
};
4713
4714
static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses[] = {
4715
  &Mips::GPR64RegClass,
4716
  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4717
  nullptr
4718
};
4719
4720
static const TargetRegisterClass *const AFGR64_and_OddSPSuperclasses[] = {
4721
  &Mips::OddSPRegClass,
4722
  &Mips::OddSP_with_sub_hiRegClass,
4723
  &Mips::OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClass,
4724
  &Mips::AFGR64RegClass,
4725
  nullptr
4726
};
4727
4728
static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsSuperclasses[] = {
4729
  &Mips::GPR64RegClass,
4730
  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4731
  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4732
  nullptr
4733
};
4734
4735
static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePSuperclasses[] = {
4736
  &Mips::GPR64RegClass,
4737
  nullptr
4738
};
4739
4740
static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses[] = {
4741
  &Mips::GPR64RegClass,
4742
  nullptr
4743
};
4744
4745
static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4746
  &Mips::GPR64RegClass,
4747
  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4748
  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4749
  &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4750
  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4751
  nullptr
4752
};
4753
4754
static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
4755
  &Mips::GPR64RegClass,
4756
  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4757
  &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4758
  nullptr
4759
};
4760
4761
static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses[] = {
4762
  &Mips::GPR64RegClass,
4763
  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4764
  nullptr
4765
};
4766
4767
static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
4768
  &Mips::GPR64RegClass,
4769
  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4770
  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4771
  &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4772
  &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4773
  &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
4774
  nullptr
4775
};
4776
4777
static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
4778
  &Mips::GPR64RegClass,
4779
  &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4780
  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4781
  nullptr
4782
};
4783
4784
static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {
4785
  &Mips::GPR64RegClass,
4786
  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4787
  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4788
  &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4789
  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4790
  &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
4791
  &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,
4792
  nullptr
4793
};
4794
4795
static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses[] = {
4796
  &Mips::GPR64RegClass,
4797
  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4798
  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4799
  &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4800
  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4801
  &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
4802
  nullptr
4803
};
4804
4805
static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4806
  &Mips::GPR64RegClass,
4807
  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4808
  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4809
  &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4810
  &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4811
  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4812
  &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
4813
  &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
4814
  &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,
4815
  &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
4816
  nullptr
4817
};
4818
4819
static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {
4820
  &Mips::GPR64RegClass,
4821
  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4822
  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4823
  &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4824
  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4825
  &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
4826
  &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,
4827
  &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
4828
  &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass,
4829
  nullptr
4830
};
4831
4832
static const TargetRegisterClass *const ACC64Superclasses[] = {
4833
  &Mips::ACC64DSPRegClass,
4834
  nullptr
4835
};
4836
4837
static const TargetRegisterClass *const GP64Superclasses[] = {
4838
  &Mips::GPR64RegClass,
4839
  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4840
  nullptr
4841
};
4842
4843
static const TargetRegisterClass *const GPR64_with_sub_32_in_CPURARegSuperclasses[] = {
4844
  &Mips::GPR64RegClass,
4845
  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4846
  nullptr
4847
};
4848
4849
static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32ZEROSuperclasses[] = {
4850
  &Mips::GPR64RegClass,
4851
  &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4852
  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4853
  &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
4854
  nullptr
4855
};
4856
4857
static const TargetRegisterClass *const SP64Superclasses[] = {
4858
  &Mips::GPR64RegClass,
4859
  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4860
  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4861
  nullptr
4862
};
4863
4864
static const TargetRegisterClass *const MSA128BSuperclasses[] = {
4865
  &Mips::MSA128F16RegClass,
4866
  &Mips::MSA128DRegClass,
4867
  &Mips::MSA128HRegClass,
4868
  &Mips::MSA128WRegClass,
4869
  nullptr
4870
};
4871
4872
static const TargetRegisterClass *const MSA128DSuperclasses[] = {
4873
  &Mips::MSA128F16RegClass,
4874
  &Mips::MSA128BRegClass,
4875
  &Mips::MSA128HRegClass,
4876
  &Mips::MSA128WRegClass,
4877
  nullptr
4878
};
4879
4880
static const TargetRegisterClass *const MSA128HSuperclasses[] = {
4881
  &Mips::MSA128F16RegClass,
4882
  &Mips::MSA128BRegClass,
4883
  &Mips::MSA128DRegClass,
4884
  &Mips::MSA128WRegClass,
4885
  nullptr
4886
};
4887
4888
static const TargetRegisterClass *const MSA128WSuperclasses[] = {
4889
  &Mips::MSA128F16RegClass,
4890
  &Mips::MSA128BRegClass,
4891
  &Mips::MSA128DRegClass,
4892
  &Mips::MSA128HRegClass,
4893
  nullptr
4894
};
4895
4896
static const TargetRegisterClass *const MSA128B_with_sub_64_in_OddSPSuperclasses[] = {
4897
  &Mips::MSA128F16RegClass,
4898
  &Mips::MSA128F16_with_sub_64_in_OddSPRegClass,
4899
  &Mips::MSA128BRegClass,
4900
  &Mips::MSA128DRegClass,
4901
  &Mips::MSA128HRegClass,
4902
  &Mips::MSA128WRegClass,
4903
  nullptr
4904
};
4905
4906
static const TargetRegisterClass *const MSA128WEvensSuperclasses[] = {
4907
  &Mips::MSA128F16RegClass,
4908
  &Mips::MSA128BRegClass,
4909
  &Mips::MSA128DRegClass,
4910
  &Mips::MSA128HRegClass,
4911
  &Mips::MSA128WRegClass,
4912
  nullptr
4913
};
4914
4915
4916
namespace Mips {   // Register class instances
4917
  extern const TargetRegisterClass MSA128F16RegClass = {
4918
    &MipsMCRegisterClasses[MSA128F16RegClassID],
4919
    MSA128F16SubClassMask,
4920
    SuperRegIdxSeqs + 1,
4921
    LaneBitmask(0x00000041),
4922
    0,
4923
    true, /* HasDisjunctSubRegs */
4924
    false, /* CoveredBySubRegs */
4925
    NullRegClasses,
4926
    nullptr
4927
  };
4928
4929
  extern const TargetRegisterClass MSA128F16_with_sub_64_in_OddSPRegClass = {
4930
    &MipsMCRegisterClasses[MSA128F16_with_sub_64_in_OddSPRegClassID],
4931
    MSA128F16_with_sub_64_in_OddSPSubClassMask,
4932
    SuperRegIdxSeqs + 1,
4933
    LaneBitmask(0x00000041),
4934
    0,
4935
    true, /* HasDisjunctSubRegs */
4936
    false, /* CoveredBySubRegs */
4937
    MSA128F16_with_sub_64_in_OddSPSuperclasses,
4938
    nullptr
4939
  };
4940
4941
  extern const TargetRegisterClass OddSPRegClass = {
4942
    &MipsMCRegisterClasses[OddSPRegClassID],
4943
    OddSPSubClassMask,
4944
    SuperRegIdxSeqs + 9,
4945
    LaneBitmask(0x00000041),
4946
    0,
4947
    true, /* HasDisjunctSubRegs */
4948
    false, /* CoveredBySubRegs */
4949
    NullRegClasses,
4950
    nullptr
4951
  };
4952
4953
  extern const TargetRegisterClass CCRRegClass = {
4954
    &MipsMCRegisterClasses[CCRRegClassID],
4955
    CCRSubClassMask,
4956
    SuperRegIdxSeqs + 1,
4957
    LaneBitmask(0x00000001),
4958
    0,
4959
    false, /* HasDisjunctSubRegs */
4960
    false, /* CoveredBySubRegs */
4961
    NullRegClasses,
4962
    nullptr
4963
  };
4964
4965
  extern const TargetRegisterClass COP0RegClass = {
4966
    &MipsMCRegisterClasses[COP0RegClassID],
4967
    COP0SubClassMask,
4968
    SuperRegIdxSeqs + 1,
4969
    LaneBitmask(0x00000001),
4970
    0,
4971
    false, /* HasDisjunctSubRegs */
4972
    false, /* CoveredBySubRegs */
4973
    NullRegClasses,
4974
    nullptr
4975
  };
4976
4977
  extern const TargetRegisterClass COP2RegClass = {
4978
    &MipsMCRegisterClasses[COP2RegClassID],
4979
    COP2SubClassMask,
4980
    SuperRegIdxSeqs + 1,
4981
    LaneBitmask(0x00000001),
4982
    0,
4983
    false, /* HasDisjunctSubRegs */
4984
    false, /* CoveredBySubRegs */
4985
    NullRegClasses,
4986
    nullptr
4987
  };
4988
4989
  extern const TargetRegisterClass COP3RegClass = {
4990
    &MipsMCRegisterClasses[COP3RegClassID],
4991
    COP3SubClassMask,
4992
    SuperRegIdxSeqs + 1,
4993
    LaneBitmask(0x00000001),
4994
    0,
4995
    false, /* HasDisjunctSubRegs */
4996
    false, /* CoveredBySubRegs */
4997
    NullRegClasses,
4998
    nullptr
4999
  };
5000
5001
  extern const TargetRegisterClass DSPRRegClass = {
5002
    &MipsMCRegisterClasses[DSPRRegClassID],
5003
    DSPRSubClassMask,
5004
    SuperRegIdxSeqs + 0,
5005
    LaneBitmask(0x00000001),
5006
    0,
5007
    false, /* HasDisjunctSubRegs */
5008
    false, /* CoveredBySubRegs */
5009
    NullRegClasses,
5010
    nullptr
5011
  };
5012
5013
  extern const TargetRegisterClass FGR32RegClass = {
5014
    &MipsMCRegisterClasses[FGR32RegClassID],
5015
    FGR32SubClassMask,
5016
    SuperRegIdxSeqs + 10,
5017
    LaneBitmask(0x00000001),
5018
    0,
5019
    false, /* HasDisjunctSubRegs */
5020
    false, /* CoveredBySubRegs */
5021
    FGR32Superclasses,
5022
    nullptr
5023
  };
5024
5025
  extern const TargetRegisterClass FGRCCRegClass = {
5026
    &MipsMCRegisterClasses[FGRCCRegClassID],
5027
    FGRCCSubClassMask,
5028
    SuperRegIdxSeqs + 10,
5029
    LaneBitmask(0x00000001),
5030
    0,
5031
    false, /* HasDisjunctSubRegs */
5032
    false, /* CoveredBySubRegs */
5033
    FGRCCSuperclasses,
5034
    nullptr
5035
  };
5036
5037
  extern const TargetRegisterClass FGRH32RegClass = {
5038
    &MipsMCRegisterClasses[FGRH32RegClassID],
5039
    FGRH32SubClassMask,
5040
    SuperRegIdxSeqs + 4,
5041
    LaneBitmask(0x00000001),
5042
    0,
5043
    false, /* HasDisjunctSubRegs */
5044
    false, /* CoveredBySubRegs */
5045
    NullRegClasses,
5046
    nullptr
5047
  };
5048
5049
  extern const TargetRegisterClass GPR32RegClass = {
5050
    &MipsMCRegisterClasses[GPR32RegClassID],
5051
    GPR32SubClassMask,
5052
    SuperRegIdxSeqs + 0,
5053
    LaneBitmask(0x00000001),
5054
    0,
5055
    false, /* HasDisjunctSubRegs */
5056
    false, /* CoveredBySubRegs */
5057
    GPR32Superclasses,
5058
    nullptr
5059
  };
5060
5061
  extern const TargetRegisterClass HWRegsRegClass = {
5062
    &MipsMCRegisterClasses[HWRegsRegClassID],
5063
    HWRegsSubClassMask,
5064
    SuperRegIdxSeqs + 1,
5065
    LaneBitmask(0x00000001),
5066
    0,
5067
    false, /* HasDisjunctSubRegs */
5068
    false, /* CoveredBySubRegs */
5069
    NullRegClasses,
5070
    nullptr
5071
  };
5072
5073
  extern const TargetRegisterClass GPR32NONZERORegClass = {
5074
    &MipsMCRegisterClasses[GPR32NONZERORegClassID],
5075
    GPR32NONZEROSubClassMask,
5076
    SuperRegIdxSeqs + 0,
5077
    LaneBitmask(0x00000001),
5078
    0,
5079
    false, /* HasDisjunctSubRegs */
5080
    false, /* CoveredBySubRegs */
5081
    GPR32NONZEROSuperclasses,
5082
    nullptr
5083
  };
5084
5085
  extern const TargetRegisterClass OddSP_with_sub_hiRegClass = {
5086
    &MipsMCRegisterClasses[OddSP_with_sub_hiRegClassID],
5087
    OddSP_with_sub_hiSubClassMask,
5088
    SuperRegIdxSeqs + 2,
5089
    LaneBitmask(0x00000041),
5090
    0,
5091
    true, /* HasDisjunctSubRegs */
5092
    true, /* CoveredBySubRegs */
5093
    OddSP_with_sub_hiSuperclasses,
5094
    nullptr
5095
  };
5096
5097
  extern const TargetRegisterClass FGR32_and_OddSPRegClass = {
5098
    &MipsMCRegisterClasses[FGR32_and_OddSPRegClassID],
5099
    FGR32_and_OddSPSubClassMask,
5100
    SuperRegIdxSeqs + 10,
5101
    LaneBitmask(0x00000001),
5102
    0,
5103
    false, /* HasDisjunctSubRegs */
5104
    false, /* CoveredBySubRegs */
5105
    FGR32_and_OddSPSuperclasses,
5106
    nullptr
5107
  };
5108
5109
  extern const TargetRegisterClass FGRH32_and_OddSPRegClass = {
5110
    &MipsMCRegisterClasses[FGRH32_and_OddSPRegClassID],
5111
    FGRH32_and_OddSPSubClassMask,
5112
    SuperRegIdxSeqs + 4,
5113
    LaneBitmask(0x00000001),
5114
    0,
5115
    false, /* HasDisjunctSubRegs */
5116
    false, /* CoveredBySubRegs */
5117
    FGRH32_and_OddSPSuperclasses,
5118
    nullptr
5119
  };
5120
5121
  extern const TargetRegisterClass OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClass = {
5122
    &MipsMCRegisterClasses[OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID],
5123
    OddSP_with_sub_hi_with_sub_hi_in_FGRH32SubClassMask,
5124
    SuperRegIdxSeqs + 2,
5125
    LaneBitmask(0x00000041),
5126
    0,
5127
    true, /* HasDisjunctSubRegs */
5128
    true, /* CoveredBySubRegs */
5129
    OddSP_with_sub_hi_with_sub_hi_in_FGRH32Superclasses,
5130
    nullptr
5131
  };
5132
5133
  extern const TargetRegisterClass CPU16RegsPlusSPRegClass = {
5134
    &MipsMCRegisterClasses[CPU16RegsPlusSPRegClassID],
5135
    CPU16RegsPlusSPSubClassMask,
5136
    SuperRegIdxSeqs + 0,
5137
    LaneBitmask(0x00000001),
5138
    0,
5139
    false, /* HasDisjunctSubRegs */
5140
    false, /* CoveredBySubRegs */
5141
    CPU16RegsPlusSPSuperclasses,
5142
    nullptr
5143
  };
5144
5145
  extern const TargetRegisterClass CPU16RegsRegClass = {
5146
    &MipsMCRegisterClasses[CPU16RegsRegClassID],
5147
    CPU16RegsSubClassMask,
5148
    SuperRegIdxSeqs + 0,
5149
    LaneBitmask(0x00000001),
5150
    0,
5151
    false, /* HasDisjunctSubRegs */
5152
    false, /* CoveredBySubRegs */
5153
    CPU16RegsSuperclasses,
5154
    nullptr
5155
  };
5156
5157
  extern const TargetRegisterClass FCCRegClass = {
5158
    &MipsMCRegisterClasses[FCCRegClassID],
5159
    FCCSubClassMask,
5160
    SuperRegIdxSeqs + 1,
5161
    LaneBitmask(0x00000001),
5162
    0,
5163
    false, /* HasDisjunctSubRegs */
5164
    false, /* CoveredBySubRegs */
5165
    NullRegClasses,
5166
    nullptr
5167
  };
5168
5169
  extern const TargetRegisterClass GPRMM16RegClass = {
5170
    &MipsMCRegisterClasses[GPRMM16RegClassID],
5171
    GPRMM16SubClassMask,
5172
    SuperRegIdxSeqs + 0,
5173
    LaneBitmask(0x00000001),
5174
    0,
5175
    false, /* HasDisjunctSubRegs */
5176
    false, /* CoveredBySubRegs */
5177
    GPRMM16Superclasses,
5178
    nullptr
5179
  };
5180
5181
  extern const TargetRegisterClass GPRMM16MovePRegClass = {
5182
    &MipsMCRegisterClasses[GPRMM16MovePRegClassID],
5183
    GPRMM16MovePSubClassMask,
5184
    SuperRegIdxSeqs + 0,
5185
    LaneBitmask(0x00000001),
5186
    0,
5187
    false, /* HasDisjunctSubRegs */
5188
    false, /* CoveredBySubRegs */
5189
    GPRMM16MovePSuperclasses,
5190
    nullptr
5191
  };
5192
5193
  extern const TargetRegisterClass GPRMM16ZeroRegClass = {
5194
    &MipsMCRegisterClasses[GPRMM16ZeroRegClassID],
5195
    GPRMM16ZeroSubClassMask,
5196
    SuperRegIdxSeqs + 0,
5197
    LaneBitmask(0x00000001),
5198
    0,
5199
    false, /* HasDisjunctSubRegs */
5200
    false, /* CoveredBySubRegs */
5201
    GPRMM16ZeroSuperclasses,
5202
    nullptr
5203
  };
5204
5205
  extern const TargetRegisterClass MSACtrlRegClass = {
5206
    &MipsMCRegisterClasses[MSACtrlRegClassID],
5207
    MSACtrlSubClassMask,
5208
    SuperRegIdxSeqs + 1,
5209
    LaneBitmask(0x00000001),
5210
    0,
5211
    false, /* HasDisjunctSubRegs */
5212
    false, /* CoveredBySubRegs */
5213
    NullRegClasses,
5214
    nullptr
5215
  };
5216
5217
  extern const TargetRegisterClass OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClass = {
5218
    &MipsMCRegisterClasses[OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID],
5219
    OddSP_with_sub_hi_with_sub_hi_in_FGR32SubClassMask,
5220
    SuperRegIdxSeqs + 1,
5221
    LaneBitmask(0x00000041),
5222
    0,
5223
    true, /* HasDisjunctSubRegs */
5224
    true, /* CoveredBySubRegs */
5225
    OddSP_with_sub_hi_with_sub_hi_in_FGR32Superclasses,
5226
    nullptr
5227
  };
5228
5229
  extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass = {
5230
    &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16ZeroRegClassID],
5231
    CPU16Regs_and_GPRMM16ZeroSubClassMask,
5232
    SuperRegIdxSeqs + 0,
5233
    LaneBitmask(0x00000001),
5234
    0,
5235
    false, /* HasDisjunctSubRegs */
5236
    false, /* CoveredBySubRegs */
5237
    CPU16Regs_and_GPRMM16ZeroSuperclasses,
5238
    nullptr
5239
  };
5240
5241
  extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass = {
5242
    &MipsMCRegisterClasses[GPR32NONZERO_and_GPRMM16MovePRegClassID],
5243
    GPR32NONZERO_and_GPRMM16MovePSubClassMask,
5244
    SuperRegIdxSeqs + 0,
5245
    LaneBitmask(0x00000001),
5246
    0,
5247
    false, /* HasDisjunctSubRegs */
5248
    false, /* CoveredBySubRegs */
5249
    GPR32NONZERO_and_GPRMM16MovePSuperclasses,
5250
    nullptr
5251
  };
5252
5253
  extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass = {
5254
    &MipsMCRegisterClasses[GPRMM16MovePPairSecondRegClassID],
5255
    GPRMM16MovePPairSecondSubClassMask,
5256
    SuperRegIdxSeqs + 0,
5257
    LaneBitmask(0x00000001),
5258
    0,
5259
    false, /* HasDisjunctSubRegs */
5260
    false, /* CoveredBySubRegs */
5261
    GPRMM16MovePPairSecondSuperclasses,
5262
    nullptr
5263
  };
5264
5265
  extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass = {
5266
    &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePRegClassID],
5267
    CPU16Regs_and_GPRMM16MovePSubClassMask,
5268
    SuperRegIdxSeqs + 0,
5269
    LaneBitmask(0x00000001),
5270
    0,
5271
    false, /* HasDisjunctSubRegs */
5272
    false, /* CoveredBySubRegs */
5273
    CPU16Regs_and_GPRMM16MovePSuperclasses,
5274
    nullptr
5275
  };
5276
5277
  extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass = {
5278
    &MipsMCRegisterClasses[GPRMM16MoveP_and_GPRMM16ZeroRegClassID],
5279
    GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,
5280
    SuperRegIdxSeqs + 0,
5281
    LaneBitmask(0x00000001),
5282
    0,
5283
    false, /* HasDisjunctSubRegs */
5284
    false, /* CoveredBySubRegs */
5285
    GPRMM16MoveP_and_GPRMM16ZeroSuperclasses,
5286
    nullptr
5287
  };
5288
5289
  extern const TargetRegisterClass HI32DSPRegClass = {
5290
    &MipsMCRegisterClasses[HI32DSPRegClassID],
5291
    HI32DSPSubClassMask,
5292
    SuperRegIdxSeqs + 13,
5293
    LaneBitmask(0x00000001),
5294
    0,
5295
    false, /* HasDisjunctSubRegs */
5296
    false, /* CoveredBySubRegs */
5297
    NullRegClasses,
5298
    nullptr
5299
  };
5300
5301
  extern const TargetRegisterClass LO32DSPRegClass = {
5302
    &MipsMCRegisterClasses[LO32DSPRegClassID],
5303
    LO32DSPSubClassMask,
5304
    SuperRegIdxSeqs + 6,
5305
    LaneBitmask(0x00000001),
5306
    0,
5307
    false, /* HasDisjunctSubRegs */
5308
    false, /* CoveredBySubRegs */
5309
    NullRegClasses,
5310
    nullptr
5311
  };
5312
5313
  extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {
5314
    &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],
5315
    CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,
5316
    SuperRegIdxSeqs + 0,
5317
    LaneBitmask(0x00000001),
5318
    0,
5319
    false, /* HasDisjunctSubRegs */
5320
    false, /* CoveredBySubRegs */
5321
    CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses,
5322
    nullptr
5323
  };
5324
5325
  extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass = {
5326
    &MipsMCRegisterClasses[GPRMM16MovePPairFirstRegClassID],
5327
    GPRMM16MovePPairFirstSubClassMask,
5328
    SuperRegIdxSeqs + 0,
5329
    LaneBitmask(0x00000001),
5330
    0,
5331
    false, /* HasDisjunctSubRegs */
5332
    false, /* CoveredBySubRegs */
5333
    GPRMM16MovePPairFirstSuperclasses,
5334
    nullptr
5335
  };
5336
5337
  extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {
5338
    &MipsMCRegisterClasses[GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],
5339
    GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,
5340
    SuperRegIdxSeqs + 0,
5341
    LaneBitmask(0x00000001),
5342
    0,
5343
    false, /* HasDisjunctSubRegs */
5344
    false, /* CoveredBySubRegs */
5345
    GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses,
5346
    nullptr
5347
  };
5348
5349
  extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {
5350
    &MipsMCRegisterClasses[GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],
5351
    GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,
5352
    SuperRegIdxSeqs + 0,
5353
    LaneBitmask(0x00000001),
5354
    0,
5355
    false, /* HasDisjunctSubRegs */
5356
    false, /* CoveredBySubRegs */
5357
    GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses,
5358
    nullptr
5359
  };
5360
5361
  extern const TargetRegisterClass CPURARegRegClass = {
5362
    &MipsMCRegisterClasses[CPURARegRegClassID],
5363
    CPURARegSubClassMask,
5364
    SuperRegIdxSeqs + 0,
5365
    LaneBitmask(0x00000001),
5366
    0,
5367
    false, /* HasDisjunctSubRegs */
5368
    false, /* CoveredBySubRegs */
5369
    CPURARegSuperclasses,
5370
    nullptr
5371
  };
5372
5373
  extern const TargetRegisterClass CPUSPRegRegClass = {
5374
    &MipsMCRegisterClasses[CPUSPRegRegClassID],
5375
    CPUSPRegSubClassMask,
5376
    SuperRegIdxSeqs + 0,
5377
    LaneBitmask(0x00000001),
5378
    0,
5379
    false, /* HasDisjunctSubRegs */
5380
    false, /* CoveredBySubRegs */
5381
    CPUSPRegSuperclasses,
5382
    nullptr
5383
  };
5384
5385
  extern const TargetRegisterClass DSPCCRegClass = {
5386
    &MipsMCRegisterClasses[DSPCCRegClassID],
5387
    DSPCCSubClassMask,
5388
    SuperRegIdxSeqs + 1,
5389
    LaneBitmask(0x00000001),
5390
    0,
5391
    false, /* HasDisjunctSubRegs */
5392
    false, /* CoveredBySubRegs */
5393
    NullRegClasses,
5394
    nullptr
5395
  };
5396
5397
  extern const TargetRegisterClass GP32RegClass = {
5398
    &MipsMCRegisterClasses[GP32RegClassID],
5399
    GP32SubClassMask,
5400
    SuperRegIdxSeqs + 0,
5401
    LaneBitmask(0x00000001),
5402
    0,
5403
    false, /* HasDisjunctSubRegs */
5404
    false, /* CoveredBySubRegs */
5405
    GP32Superclasses,
5406
    nullptr
5407
  };
5408
5409
  extern const TargetRegisterClass GPR32ZERORegClass = {
5410
    &MipsMCRegisterClasses[GPR32ZERORegClassID],
5411
    GPR32ZEROSubClassMask,
5412
    SuperRegIdxSeqs + 0,
5413
    LaneBitmask(0x00000001),
5414
    0,
5415
    false, /* HasDisjunctSubRegs */
5416
    false, /* CoveredBySubRegs */
5417
    GPR32ZEROSuperclasses,
5418
    nullptr
5419
  };
5420
5421
  extern const TargetRegisterClass HI32RegClass = {
5422
    &MipsMCRegisterClasses[HI32RegClassID],
5423
    HI32SubClassMask,
5424
    SuperRegIdxSeqs + 13,
5425
    LaneBitmask(0x00000001),
5426
    0,
5427
    false, /* HasDisjunctSubRegs */
5428
    false, /* CoveredBySubRegs */
5429
    HI32Superclasses,
5430
    nullptr
5431
  };
5432
5433
  extern const TargetRegisterClass LO32RegClass = {
5434
    &MipsMCRegisterClasses[LO32RegClassID],
5435
    LO32SubClassMask,
5436
    SuperRegIdxSeqs + 6,
5437
    LaneBitmask(0x00000001),
5438
    0,
5439
    false, /* HasDisjunctSubRegs */
5440
    false, /* CoveredBySubRegs */
5441
    LO32Superclasses,
5442
    nullptr
5443
  };
5444
5445
  extern const TargetRegisterClass SP32RegClass = {
5446
    &MipsMCRegisterClasses[SP32RegClassID],
5447
    SP32SubClassMask,
5448
    SuperRegIdxSeqs + 0,
5449
    LaneBitmask(0x00000001),
5450
    0,
5451
    false, /* HasDisjunctSubRegs */
5452
    false, /* CoveredBySubRegs */
5453
    SP32Superclasses,
5454
    nullptr
5455
  };
5456
5457
  extern const TargetRegisterClass FGR64RegClass = {
5458
    &MipsMCRegisterClasses[FGR64RegClassID],
5459
    FGR64SubClassMask,
5460
    SuperRegIdxSeqs + 2,
5461
    LaneBitmask(0x00000041),
5462
    0,
5463
    true, /* HasDisjunctSubRegs */
5464
    true, /* CoveredBySubRegs */
5465
    NullRegClasses,
5466
    nullptr
5467
  };
5468
5469
  extern const TargetRegisterClass GPR64RegClass = {
5470
    &MipsMCRegisterClasses[GPR64RegClassID],
5471
    GPR64SubClassMask,
5472
    SuperRegIdxSeqs + 1,
5473
    LaneBitmask(0x00000001),
5474
    0,
5475
    false, /* HasDisjunctSubRegs */
5476
    false, /* CoveredBySubRegs */
5477
    NullRegClasses,
5478
    nullptr
5479
  };
5480
5481
  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass = {
5482
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERORegClassID],
5483
    GPR64_with_sub_32_in_GPR32NONZEROSubClassMask,
5484
    SuperRegIdxSeqs + 1,
5485
    LaneBitmask(0x00000001),
5486
    0,
5487
    false, /* HasDisjunctSubRegs */
5488
    false, /* CoveredBySubRegs */
5489
    GPR64_with_sub_32_in_GPR32NONZEROSuperclasses,
5490
    nullptr
5491
  };
5492
5493
  extern const TargetRegisterClass AFGR64RegClass = {
5494
    &MipsMCRegisterClasses[AFGR64RegClassID],
5495
    AFGR64SubClassMask,
5496
    SuperRegIdxSeqs + 1,
5497
    LaneBitmask(0x00000041),
5498
    0,
5499
    true, /* HasDisjunctSubRegs */
5500
    true, /* CoveredBySubRegs */
5501
    NullRegClasses,
5502
    nullptr
5503
  };
5504
5505
  extern const TargetRegisterClass FGR64_and_OddSPRegClass = {
5506
    &MipsMCRegisterClasses[FGR64_and_OddSPRegClassID],
5507
    FGR64_and_OddSPSubClassMask,
5508
    SuperRegIdxSeqs + 2,
5509
    LaneBitmask(0x00000041),
5510
    0,
5511
    true, /* HasDisjunctSubRegs */
5512
    true, /* CoveredBySubRegs */
5513
    FGR64_and_OddSPSuperclasses,
5514
    nullptr
5515
  };
5516
5517
  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass = {
5518
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID],
5519
    GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask,
5520
    SuperRegIdxSeqs + 1,
5521
    LaneBitmask(0x00000001),
5522
    0,
5523
    false, /* HasDisjunctSubRegs */
5524
    false, /* CoveredBySubRegs */
5525
    GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses,
5526
    nullptr
5527
  };
5528
5529
  extern const TargetRegisterClass AFGR64_and_OddSPRegClass = {
5530
    &MipsMCRegisterClasses[AFGR64_and_OddSPRegClassID],
5531
    AFGR64_and_OddSPSubClassMask,
5532
    SuperRegIdxSeqs + 1,
5533
    LaneBitmask(0x00000041),
5534
    0,
5535
    true, /* HasDisjunctSubRegs */
5536
    true, /* CoveredBySubRegs */
5537
    AFGR64_and_OddSPSuperclasses,
5538
    nullptr