Coverage Report

Created: 2018-12-14 11:24

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/NVPTX/NVPTXGenInstrInfo.inc
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1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Instruction Enum Values and Descriptors                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_INSTRINFO_ENUM
10
#undef GET_INSTRINFO_ENUM
11
namespace llvm {
12
13
namespace NVPTX {
14
  enum {
15
    PHI = 0,
16
    INLINEASM = 1,
17
    CFI_INSTRUCTION = 2,
18
    EH_LABEL  = 3,
19
    GC_LABEL  = 4,
20
    ANNOTATION_LABEL  = 5,
21
    KILL  = 6,
22
    EXTRACT_SUBREG  = 7,
23
    INSERT_SUBREG = 8,
24
    IMPLICIT_DEF  = 9,
25
    SUBREG_TO_REG = 10,
26
    COPY_TO_REGCLASS  = 11,
27
    DBG_VALUE = 12,
28
    DBG_LABEL = 13,
29
    REG_SEQUENCE  = 14,
30
    COPY  = 15,
31
    BUNDLE  = 16,
32
    LIFETIME_START  = 17,
33
    LIFETIME_END  = 18,
34
    STACKMAP  = 19,
35
    FENTRY_CALL = 20,
36
    PATCHPOINT  = 21,
37
    LOAD_STACK_GUARD  = 22,
38
    STATEPOINT  = 23,
39
    LOCAL_ESCAPE  = 24,
40
    FAULTING_OP = 25,
41
    PATCHABLE_OP  = 26,
42
    PATCHABLE_FUNCTION_ENTER  = 27,
43
    PATCHABLE_RET = 28,
44
    PATCHABLE_FUNCTION_EXIT = 29,
45
    PATCHABLE_TAIL_CALL = 30,
46
    PATCHABLE_EVENT_CALL  = 31,
47
    PATCHABLE_TYPED_EVENT_CALL  = 32,
48
    ICALL_BRANCH_FUNNEL = 33,
49
    G_ADD = 34,
50
    G_SUB = 35,
51
    G_MUL = 36,
52
    G_SDIV  = 37,
53
    G_UDIV  = 38,
54
    G_SREM  = 39,
55
    G_UREM  = 40,
56
    G_AND = 41,
57
    G_OR  = 42,
58
    G_XOR = 43,
59
    G_IMPLICIT_DEF  = 44,
60
    G_PHI = 45,
61
    G_FRAME_INDEX = 46,
62
    G_GLOBAL_VALUE  = 47,
63
    G_EXTRACT = 48,
64
    G_UNMERGE_VALUES  = 49,
65
    G_INSERT  = 50,
66
    G_MERGE_VALUES  = 51,
67
    G_BUILD_VECTOR  = 52,
68
    G_BUILD_VECTOR_TRUNC  = 53,
69
    G_CONCAT_VECTORS  = 54,
70
    G_PTRTOINT  = 55,
71
    G_INTTOPTR  = 56,
72
    G_BITCAST = 57,
73
    G_INTRINSIC_TRUNC = 58,
74
    G_INTRINSIC_ROUND = 59,
75
    G_LOAD  = 60,
76
    G_SEXTLOAD  = 61,
77
    G_ZEXTLOAD  = 62,
78
    G_STORE = 63,
79
    G_ATOMIC_CMPXCHG_WITH_SUCCESS = 64,
80
    G_ATOMIC_CMPXCHG  = 65,
81
    G_ATOMICRMW_XCHG  = 66,
82
    G_ATOMICRMW_ADD = 67,
83
    G_ATOMICRMW_SUB = 68,
84
    G_ATOMICRMW_AND = 69,
85
    G_ATOMICRMW_NAND  = 70,
86
    G_ATOMICRMW_OR  = 71,
87
    G_ATOMICRMW_XOR = 72,
88
    G_ATOMICRMW_MAX = 73,
89
    G_ATOMICRMW_MIN = 74,
90
    G_ATOMICRMW_UMAX  = 75,
91
    G_ATOMICRMW_UMIN  = 76,
92
    G_BRCOND  = 77,
93
    G_BRINDIRECT  = 78,
94
    G_INTRINSIC = 79,
95
    G_INTRINSIC_W_SIDE_EFFECTS  = 80,
96
    G_ANYEXT  = 81,
97
    G_TRUNC = 82,
98
    G_CONSTANT  = 83,
99
    G_FCONSTANT = 84,
100
    G_VASTART = 85,
101
    G_VAARG = 86,
102
    G_SEXT  = 87,
103
    G_ZEXT  = 88,
104
    G_SHL = 89,
105
    G_LSHR  = 90,
106
    G_ASHR  = 91,
107
    G_ICMP  = 92,
108
    G_FCMP  = 93,
109
    G_SELECT  = 94,
110
    G_UADDO = 95,
111
    G_UADDE = 96,
112
    G_USUBO = 97,
113
    G_USUBE = 98,
114
    G_SADDO = 99,
115
    G_SADDE = 100,
116
    G_SSUBO = 101,
117
    G_SSUBE = 102,
118
    G_UMULO = 103,
119
    G_SMULO = 104,
120
    G_UMULH = 105,
121
    G_SMULH = 106,
122
    G_FADD  = 107,
123
    G_FSUB  = 108,
124
    G_FMUL  = 109,
125
    G_FMA = 110,
126
    G_FDIV  = 111,
127
    G_FREM  = 112,
128
    G_FPOW  = 113,
129
    G_FEXP  = 114,
130
    G_FEXP2 = 115,
131
    G_FLOG  = 116,
132
    G_FLOG2 = 117,
133
    G_FLOG10  = 118,
134
    G_FNEG  = 119,
135
    G_FPEXT = 120,
136
    G_FPTRUNC = 121,
137
    G_FPTOSI  = 122,
138
    G_FPTOUI  = 123,
139
    G_SITOFP  = 124,
140
    G_UITOFP  = 125,
141
    G_FABS  = 126,
142
    G_GEP = 127,
143
    G_PTR_MASK  = 128,
144
    G_BR  = 129,
145
    G_INSERT_VECTOR_ELT = 130,
146
    G_EXTRACT_VECTOR_ELT  = 131,
147
    G_SHUFFLE_VECTOR  = 132,
148
    G_CTTZ  = 133,
149
    G_CTTZ_ZERO_UNDEF = 134,
150
    G_CTLZ  = 135,
151
    G_CTLZ_ZERO_UNDEF = 136,
152
    G_CTPOP = 137,
153
    G_BSWAP = 138,
154
    G_ADDRSPACE_CAST  = 139,
155
    G_BLOCK_ADDR  = 140,
156
    ADDCCCi32ri = 141,
157
    ADDCCCi32rr = 142,
158
    ADDCCi32ri  = 143,
159
    ADDCCi32rr  = 144,
160
    ADD_i1_ri = 145,
161
    ADD_i1_rr = 146,
162
    ADDi16ri  = 147,
163
    ADDi16rr  = 148,
164
    ADDi32ri  = 149,
165
    ADDi32rr  = 150,
166
    ADDi64ri  = 151,
167
    ADDi64rr  = 152,
168
    ANDb16ri  = 153,
169
    ANDb16rr  = 154,
170
    ANDb1ri = 155,
171
    ANDb1rr = 156,
172
    ANDb32ri  = 157,
173
    ANDb32rr  = 158,
174
    ANDb64ri  = 159,
175
    ANDb64rr  = 160,
176
    BFE_S32rii  = 161,
177
    BFE_S32rri  = 162,
178
    BFE_S32rrr  = 163,
179
    BFE_S64rii  = 164,
180
    BFE_S64rri  = 165,
181
    BFE_S64rrr  = 166,
182
    BFE_U32rii  = 167,
183
    BFE_U32rri  = 168,
184
    BFE_U32rrr  = 169,
185
    BFE_U64rii  = 170,
186
    BFE_U64rri  = 171,
187
    BFE_U64rrr  = 172,
188
    BITCONVERT_16_F2I = 173,
189
    BITCONVERT_16_I2F = 174,
190
    BITCONVERT_32_F16x22I = 175,
191
    BITCONVERT_32_F2I = 176,
192
    BITCONVERT_32_I2F = 177,
193
    BITCONVERT_32_I2F16x2 = 178,
194
    BITCONVERT_64_F2I = 179,
195
    BITCONVERT_64_I2F = 180,
196
    BREV32  = 181,
197
    BREV64  = 182,
198
    BuildF16x2  = 183,
199
    BuildF16x2i = 184,
200
    CALL  = 185,
201
    CALL_PROTOTYPE  = 186,
202
    CBranch = 187,
203
    CBranchOther  = 188,
204
    CLZr32  = 189,
205
    CLZr64  = 190,
206
    COSF  = 191,
207
    CVT_INREG_s16_s8  = 192,
208
    CVT_INREG_s32_s16 = 193,
209
    CVT_INREG_s32_s8  = 194,
210
    CVT_INREG_s64_s16 = 195,
211
    CVT_INREG_s64_s32 = 196,
212
    CVT_INREG_s64_s8  = 197,
213
    CVT_f16_f16 = 198,
214
    CVT_f16_f32 = 199,
215
    CVT_f16_f64 = 200,
216
    CVT_f16_s16 = 201,
217
    CVT_f16_s32 = 202,
218
    CVT_f16_s64 = 203,
219
    CVT_f16_s8  = 204,
220
    CVT_f16_u16 = 205,
221
    CVT_f16_u32 = 206,
222
    CVT_f16_u64 = 207,
223
    CVT_f16_u8  = 208,
224
    CVT_f32_f16 = 209,
225
    CVT_f32_f32 = 210,
226
    CVT_f32_f64 = 211,
227
    CVT_f32_s16 = 212,
228
    CVT_f32_s32 = 213,
229
    CVT_f32_s64 = 214,
230
    CVT_f32_s8  = 215,
231
    CVT_f32_u16 = 216,
232
    CVT_f32_u32 = 217,
233
    CVT_f32_u64 = 218,
234
    CVT_f32_u8  = 219,
235
    CVT_f64_f16 = 220,
236
    CVT_f64_f32 = 221,
237
    CVT_f64_f64 = 222,
238
    CVT_f64_s16 = 223,
239
    CVT_f64_s32 = 224,
240
    CVT_f64_s64 = 225,
241
    CVT_f64_s8  = 226,
242
    CVT_f64_u16 = 227,
243
    CVT_f64_u32 = 228,
244
    CVT_f64_u64 = 229,
245
    CVT_f64_u8  = 230,
246
    CVT_s16_f16 = 231,
247
    CVT_s16_f32 = 232,
248
    CVT_s16_f64 = 233,
249
    CVT_s16_s16 = 234,
250
    CVT_s16_s32 = 235,
251
    CVT_s16_s64 = 236,
252
    CVT_s16_s8  = 237,
253
    CVT_s16_u16 = 238,
254
    CVT_s16_u32 = 239,
255
    CVT_s16_u64 = 240,
256
    CVT_s16_u8  = 241,
257
    CVT_s32_f16 = 242,
258
    CVT_s32_f32 = 243,
259
    CVT_s32_f64 = 244,
260
    CVT_s32_s16 = 245,
261
    CVT_s32_s32 = 246,
262
    CVT_s32_s64 = 247,
263
    CVT_s32_s8  = 248,
264
    CVT_s32_u16 = 249,
265
    CVT_s32_u32 = 250,
266
    CVT_s32_u64 = 251,
267
    CVT_s32_u8  = 252,
268
    CVT_s64_f16 = 253,
269
    CVT_s64_f32 = 254,
270
    CVT_s64_f64 = 255,
271
    CVT_s64_s16 = 256,
272
    CVT_s64_s32 = 257,
273
    CVT_s64_s64 = 258,
274
    CVT_s64_s8  = 259,
275
    CVT_s64_u16 = 260,
276
    CVT_s64_u32 = 261,
277
    CVT_s64_u64 = 262,
278
    CVT_s64_u8  = 263,
279
    CVT_s8_f16  = 264,
280
    CVT_s8_f32  = 265,
281
    CVT_s8_f64  = 266,
282
    CVT_s8_s16  = 267,
283
    CVT_s8_s32  = 268,
284
    CVT_s8_s64  = 269,
285
    CVT_s8_s8 = 270,
286
    CVT_s8_u16  = 271,
287
    CVT_s8_u32  = 272,
288
    CVT_s8_u64  = 273,
289
    CVT_s8_u8 = 274,
290
    CVT_u16_f16 = 275,
291
    CVT_u16_f32 = 276,
292
    CVT_u16_f64 = 277,
293
    CVT_u16_s16 = 278,
294
    CVT_u16_s32 = 279,
295
    CVT_u16_s64 = 280,
296
    CVT_u16_s8  = 281,
297
    CVT_u16_u16 = 282,
298
    CVT_u16_u32 = 283,
299
    CVT_u16_u64 = 284,
300
    CVT_u16_u8  = 285,
301
    CVT_u32_f16 = 286,
302
    CVT_u32_f32 = 287,
303
    CVT_u32_f64 = 288,
304
    CVT_u32_s16 = 289,
305
    CVT_u32_s32 = 290,
306
    CVT_u32_s64 = 291,
307
    CVT_u32_s8  = 292,
308
    CVT_u32_u16 = 293,
309
    CVT_u32_u32 = 294,
310
    CVT_u32_u64 = 295,
311
    CVT_u32_u8  = 296,
312
    CVT_u64_f16 = 297,
313
    CVT_u64_f32 = 298,
314
    CVT_u64_f64 = 299,
315
    CVT_u64_s16 = 300,
316
    CVT_u64_s32 = 301,
317
    CVT_u64_s64 = 302,
318
    CVT_u64_s8  = 303,
319
    CVT_u64_u16 = 304,
320
    CVT_u64_u32 = 305,
321
    CVT_u64_u64 = 306,
322
    CVT_u64_u8  = 307,
323
    CVT_u8_f16  = 308,
324
    CVT_u8_f32  = 309,
325
    CVT_u8_f64  = 310,
326
    CVT_u8_s16  = 311,
327
    CVT_u8_s32  = 312,
328
    CVT_u8_s64  = 313,
329
    CVT_u8_s8 = 314,
330
    CVT_u8_u16  = 315,
331
    CVT_u8_u32  = 316,
332
    CVT_u8_u64  = 317,
333
    CVT_u8_u8 = 318,
334
    CallArgBeginInst  = 319,
335
    CallArgEndInst0 = 320,
336
    CallArgEndInst1 = 321,
337
    CallArgF32  = 322,
338
    CallArgF64  = 323,
339
    CallArgI16  = 324,
340
    CallArgI32  = 325,
341
    CallArgI32imm = 326,
342
    CallArgI64  = 327,
343
    CallArgParam  = 328,
344
    CallPrintCallNoRetInst  = 329,
345
    CallPrintCallRetInst1 = 330,
346
    CallPrintCallRetInst2 = 331,
347
    CallPrintCallRetInst3 = 332,
348
    CallPrintCallRetInst4 = 333,
349
    CallPrintCallRetInst5 = 334,
350
    CallPrintCallRetInst6 = 335,
351
    CallPrintCallRetInst7 = 336,
352
    CallPrintCallRetInst8 = 337,
353
    CallUniPrintCallNoRetInst = 338,
354
    CallUniPrintCallRetInst1  = 339,
355
    CallUniPrintCallRetInst2  = 340,
356
    CallUniPrintCallRetInst3  = 341,
357
    CallUniPrintCallRetInst4  = 342,
358
    CallUniPrintCallRetInst5  = 343,
359
    CallUniPrintCallRetInst6  = 344,
360
    CallUniPrintCallRetInst7  = 345,
361
    CallUniPrintCallRetInst8  = 346,
362
    CallVoidInst  = 347,
363
    CallVoidInstReg = 348,
364
    CallVoidInstReg64 = 349,
365
    Callseq_End = 350,
366
    Callseq_Start = 351,
367
    ConvergentCallPrintCallNoRetInst  = 352,
368
    ConvergentCallPrintCallRetInst1 = 353,
369
    ConvergentCallPrintCallRetInst2 = 354,
370
    ConvergentCallPrintCallRetInst3 = 355,
371
    ConvergentCallPrintCallRetInst4 = 356,
372
    ConvergentCallPrintCallRetInst5 = 357,
373
    ConvergentCallPrintCallRetInst6 = 358,
374
    ConvergentCallPrintCallRetInst7 = 359,
375
    ConvergentCallPrintCallRetInst8 = 360,
376
    ConvergentCallUniPrintCallNoRetInst = 361,
377
    ConvergentCallUniPrintCallRetInst1  = 362,
378
    ConvergentCallUniPrintCallRetInst2  = 363,
379
    ConvergentCallUniPrintCallRetInst3  = 364,
380
    ConvergentCallUniPrintCallRetInst4  = 365,
381
    ConvergentCallUniPrintCallRetInst5  = 366,
382
    ConvergentCallUniPrintCallRetInst6  = 367,
383
    ConvergentCallUniPrintCallRetInst7  = 368,
384
    ConvergentCallUniPrintCallRetInst8  = 369,
385
    DeclareParamInst  = 370,
386
    DeclareRetMemInst = 371,
387
    DeclareRetRegInst = 372,
388
    DeclareRetScalarInst  = 373,
389
    DeclareScalarParamInst  = 374,
390
    DeclareScalarRegInst  = 375,
391
    F16x2toF16_0  = 376,
392
    F16x2toF16_1  = 377,
393
    F64toV2F32  = 378,
394
    FABSf32 = 379,
395
    FABSf32_ftz = 380,
396
    FABSf64 = 381,
397
    FADD_rnf16rr  = 382,
398
    FADD_rnf16rr_ftz  = 383,
399
    FADD_rnf16x2rr  = 384,
400
    FADD_rnf16x2rr_ftz  = 385,
401
    FADD_rnf32ri  = 386,
402
    FADD_rnf32ri_ftz  = 387,
403
    FADD_rnf32rr  = 388,
404
    FADD_rnf32rr_ftz  = 389,
405
    FADD_rnf64ri  = 390,
406
    FADD_rnf64rr  = 391,
407
    FADDf16rr = 392,
408
    FADDf16rr_ftz = 393,
409
    FADDf16x2rr = 394,
410
    FADDf16x2rr_ftz = 395,
411
    FADDf32ri = 396,
412
    FADDf32ri_ftz = 397,
413
    FADDf32rr = 398,
414
    FADDf32rr_ftz = 399,
415
    FADDf64ri = 400,
416
    FADDf64rr = 401,
417
    FDIV321r  = 402,
418
    FDIV321r_approx = 403,
419
    FDIV321r_approx_ftz = 404,
420
    FDIV321r_ftz  = 405,
421
    FDIV321r_prec = 406,
422
    FDIV321r_prec_ftz = 407,
423
    FDIV32approxri  = 408,
424
    FDIV32approxri_ftz  = 409,
425
    FDIV32approxrr  = 410,
426
    FDIV32approxrr_ftz  = 411,
427
    FDIV32ri  = 412,
428
    FDIV32ri_ftz  = 413,
429
    FDIV32ri_prec = 414,
430
    FDIV32ri_prec_ftz = 415,
431
    FDIV32rr  = 416,
432
    FDIV32rr_ftz  = 417,
433
    FDIV32rr_prec = 418,
434
    FDIV32rr_prec_ftz = 419,
435
    FDIV641r  = 420,
436
    FDIV64ri  = 421,
437
    FDIV64rr  = 422,
438
    FMA16_ftzrrr  = 423,
439
    FMA16rrr  = 424,
440
    FMA16x2_ftzrrr  = 425,
441
    FMA16x2rrr  = 426,
442
    FMA32_ftzrii  = 427,
443
    FMA32_ftzrir  = 428,
444
    FMA32_ftzrri  = 429,
445
    FMA32_ftzrrr  = 430,
446
    FMA32rii  = 431,
447
    FMA32rir  = 432,
448
    FMA32rri  = 433,
449
    FMA32rrr  = 434,
450
    FMA64rii  = 435,
451
    FMA64rir  = 436,
452
    FMA64rri  = 437,
453
    FMA64rrr  = 438,
454
    FMAXf32ri = 439,
455
    FMAXf32ri_ftz = 440,
456
    FMAXf32rr = 441,
457
    FMAXf32rr_ftz = 442,
458
    FMAXf64ri = 443,
459
    FMAXf64rr = 444,
460
    FMINf32ri = 445,
461
    FMINf32ri_ftz = 446,
462
    FMINf32rr = 447,
463
    FMINf32rr_ftz = 448,
464
    FMINf64ri = 449,
465
    FMINf64rr = 450,
466
    FMOV16rr  = 451,
467
    FMOV32ri  = 452,
468
    FMOV32rr  = 453,
469
    FMOV64ri  = 454,
470
    FMOV64rr  = 455,
471
    FMUL_rnf16rr  = 456,
472
    FMUL_rnf16rr_ftz  = 457,
473
    FMUL_rnf16x2rr  = 458,
474
    FMUL_rnf16x2rr_ftz  = 459,
475
    FMUL_rnf32ri  = 460,
476
    FMUL_rnf32ri_ftz  = 461,
477
    FMUL_rnf32rr  = 462,
478
    FMUL_rnf32rr_ftz  = 463,
479
    FMUL_rnf64ri  = 464,
480
    FMUL_rnf64rr  = 465,
481
    FMULf16rr = 466,
482
    FMULf16rr_ftz = 467,
483
    FMULf16x2rr = 468,
484
    FMULf16x2rr_ftz = 469,
485
    FMULf32ri = 470,
486
    FMULf32ri_ftz = 471,
487
    FMULf32rr = 472,
488
    FMULf32rr_ftz = 473,
489
    FMULf64ri = 474,
490
    FMULf64rr = 475,
491
    FNEGf32 = 476,
492
    FNEGf32_ftz = 477,
493
    FNEGf64 = 478,
494
    FSQRTf32  = 479,
495
    FSQRTf32_ftz  = 480,
496
    FSQRTf64  = 481,
497
    FSUB_rnf16rr  = 482,
498
    FSUB_rnf16rr_ftz  = 483,
499
    FSUB_rnf16x2rr  = 484,
500
    FSUB_rnf16x2rr_ftz  = 485,
501
    FSUB_rnf32ri  = 486,
502
    FSUB_rnf32ri_ftz  = 487,
503
    FSUB_rnf32rr  = 488,
504
    FSUB_rnf32rr_ftz  = 489,
505
    FSUB_rnf64ri  = 490,
506
    FSUB_rnf64rr  = 491,
507
    FSUBf16rr = 492,
508
    FSUBf16rr_ftz = 493,
509
    FSUBf16x2rr = 494,
510
    FSUBf16x2rr_ftz = 495,
511
    FSUBf32ri = 496,
512
    FSUBf32ri_ftz = 497,
513
    FSUBf32rr = 498,
514
    FSUBf32rr_ftz = 499,
515
    FSUBf64ri = 500,
516
    FSUBf64rr = 501,
517
    FUNSHFLCLAMP  = 502,
518
    FUNSHFRCLAMP  = 503,
519
    GET_HI_INT64  = 504,
520
    GET_LO_INT64  = 505,
521
    GOTO  = 506,
522
    I32toV2I16  = 507,
523
    I64toV2I32  = 508,
524
    I64toV4I16  = 509,
525
    IMOV16ri  = 510,
526
    IMOV16rr  = 511,
527
    IMOV1ri = 512,
528
    IMOV1rr = 513,
529
    IMOV32ri  = 514,
530
    IMOV32rr  = 515,
531
    IMOV64i = 516,
532
    IMOV64rr  = 517,
533
    INEG16  = 518,
534
    INEG32  = 519,
535
    INEG64  = 520,
536
    INT_BARRIER = 521,
537
    INT_BARRIER0  = 522,
538
    INT_BARRIER0_AND  = 523,
539
    INT_BARRIER0_OR = 524,
540
    INT_BARRIER0_POPC = 525,
541
    INT_BARRIERN  = 526,
542
    INT_BARRIER_SYNC_CNT_II = 527,
543
    INT_BARRIER_SYNC_CNT_IR = 528,
544
    INT_BARRIER_SYNC_CNT_RI = 529,
545
    INT_BARRIER_SYNC_CNT_RR = 530,
546
    INT_BARRIER_SYNC_I  = 531,
547
    INT_BARRIER_SYNC_R  = 532,
548
    INT_BAR_SYNC  = 533,
549
    INT_BAR_WARP_SYNC_I = 534,
550
    INT_BAR_WARP_SYNC_R = 535,
551
    INT_FNS_iii = 536,
552
    INT_FNS_iir = 537,
553
    INT_FNS_iri = 538,
554
    INT_FNS_irr = 539,
555
    INT_FNS_rii = 540,
556
    INT_FNS_rir = 541,
557
    INT_FNS_rri = 542,
558
    INT_FNS_rrr = 543,
559
    INT_MEMBAR_CTA  = 544,
560
    INT_MEMBAR_GL = 545,
561
    INT_MEMBAR_SYS  = 546,
562
    INT_NVVM_ADD_RM_D = 547,
563
    INT_NVVM_ADD_RM_F = 548,
564
    INT_NVVM_ADD_RM_FTZ_F = 549,
565
    INT_NVVM_ADD_RN_D = 550,
566
    INT_NVVM_ADD_RN_F = 551,
567
    INT_NVVM_ADD_RN_FTZ_F = 552,
568
    INT_NVVM_ADD_RP_D = 553,
569
    INT_NVVM_ADD_RP_F = 554,
570
    INT_NVVM_ADD_RP_FTZ_F = 555,
571
    INT_NVVM_ADD_RZ_D = 556,
572
    INT_NVVM_ADD_RZ_F = 557,
573
    INT_NVVM_ADD_RZ_FTZ_F = 558,
574
    INT_NVVM_BITCAST_D2LL = 559,
575
    INT_NVVM_BITCAST_F2I  = 560,
576
    INT_NVVM_BITCAST_I2F  = 561,
577
    INT_NVVM_BITCAST_LL2D = 562,
578
    INT_NVVM_COMPILER_ERROR_32  = 563,
579
    INT_NVVM_COMPILER_ERROR_64  = 564,
580
    INT_NVVM_COMPILER_WARN_32 = 565,
581
    INT_NVVM_COMPILER_WARN_64 = 566,
582
    INT_NVVM_COS_APPROX_F = 567,
583
    INT_NVVM_COS_APPROX_FTZ_F = 568,
584
    INT_NVVM_D2I_HI = 569,
585
    INT_NVVM_D2I_LO = 570,
586
    INT_NVVM_DIV_APPROX_F = 571,
587
    INT_NVVM_DIV_APPROX_FTZ_F = 572,
588
    INT_NVVM_DIV_RM_D = 573,
589
    INT_NVVM_DIV_RM_F = 574,
590
    INT_NVVM_DIV_RM_FTZ_F = 575,
591
    INT_NVVM_DIV_RN_D = 576,
592
    INT_NVVM_DIV_RN_F = 577,
593
    INT_NVVM_DIV_RN_FTZ_F = 578,
594
    INT_NVVM_DIV_RP_D = 579,
595
    INT_NVVM_DIV_RP_F = 580,
596
    INT_NVVM_DIV_RP_FTZ_F = 581,
597
    INT_NVVM_DIV_RZ_D = 582,
598
    INT_NVVM_DIV_RZ_F = 583,
599
    INT_NVVM_DIV_RZ_FTZ_F = 584,
600
    INT_NVVM_EX2_APPROX_D = 585,
601
    INT_NVVM_EX2_APPROX_F = 586,
602
    INT_NVVM_EX2_APPROX_FTZ_F = 587,
603
    INT_NVVM_FABS_D = 588,
604
    INT_NVVM_FABS_F = 589,
605
    INT_NVVM_FABS_FTZ_F = 590,
606
    INT_NVVM_FMAX_D = 591,
607
    INT_NVVM_FMAX_F = 592,
608
    INT_NVVM_FMAX_FTZ_F = 593,
609
    INT_NVVM_FMA_RM_D = 594,
610
    INT_NVVM_FMA_RM_F = 595,
611
    INT_NVVM_FMA_RM_FTZ_F = 596,
612
    INT_NVVM_FMA_RN_D = 597,
613
    INT_NVVM_FMA_RN_F = 598,
614
    INT_NVVM_FMA_RN_FTZ_F = 599,
615
    INT_NVVM_FMA_RP_D = 600,
616
    INT_NVVM_FMA_RP_F = 601,
617
    INT_NVVM_FMA_RP_FTZ_F = 602,
618
    INT_NVVM_FMA_RZ_D = 603,
619
    INT_NVVM_FMA_RZ_F = 604,
620
    INT_NVVM_FMA_RZ_FTZ_F = 605,
621
    INT_NVVM_FMIN_D = 606,
622
    INT_NVVM_FMIN_F = 607,
623
    INT_NVVM_FMIN_FTZ_F = 608,
624
    INT_NVVM_LG2_APPROX_D = 609,
625
    INT_NVVM_LG2_APPROX_F = 610,
626
    INT_NVVM_LG2_APPROX_FTZ_F = 611,
627
    INT_NVVM_LOHI_I2D = 612,
628
    INT_NVVM_MUL24_I  = 613,
629
    INT_NVVM_MUL24_UI = 614,
630
    INT_NVVM_MULHI_I  = 615,
631
    INT_NVVM_MULHI_LL = 616,
632
    INT_NVVM_MULHI_UI = 617,
633
    INT_NVVM_MULHI_ULL  = 618,
634
    INT_NVVM_MUL_RM_D = 619,
635
    INT_NVVM_MUL_RM_F = 620,
636
    INT_NVVM_MUL_RM_FTZ_F = 621,
637
    INT_NVVM_MUL_RN_D = 622,
638
    INT_NVVM_MUL_RN_F = 623,
639
    INT_NVVM_MUL_RN_FTZ_F = 624,
640
    INT_NVVM_MUL_RP_D = 625,
641
    INT_NVVM_MUL_RP_F = 626,
642
    INT_NVVM_MUL_RP_FTZ_F = 627,
643
    INT_NVVM_MUL_RZ_D = 628,
644
    INT_NVVM_MUL_RZ_F = 629,
645
    INT_NVVM_MUL_RZ_FTZ_F = 630,
646
    INT_NVVM_PRMT = 631,
647
    INT_NVVM_RCP_APPROX_FTZ_D = 632,
648
    INT_NVVM_RCP_RM_D = 633,
649
    INT_NVVM_RCP_RM_F = 634,
650
    INT_NVVM_RCP_RM_FTZ_F = 635,
651
    INT_NVVM_RCP_RN_D = 636,
652
    INT_NVVM_RCP_RN_F = 637,
653
    INT_NVVM_RCP_RN_FTZ_F = 638,
654
    INT_NVVM_RCP_RP_D = 639,
655
    INT_NVVM_RCP_RP_F = 640,
656
    INT_NVVM_RCP_RP_FTZ_F = 641,
657
    INT_NVVM_RCP_RZ_D = 642,
658
    INT_NVVM_RCP_RZ_F = 643,
659
    INT_NVVM_RCP_RZ_FTZ_F = 644,
660
    INT_NVVM_RSQRT_APPROX_D = 645,
661
    INT_NVVM_RSQRT_APPROX_F = 646,
662
    INT_NVVM_RSQRT_APPROX_FTZ_F = 647,
663
    INT_NVVM_SAD_I  = 648,
664
    INT_NVVM_SAD_UI = 649,
665
    INT_NVVM_SIN_APPROX_F = 650,
666
    INT_NVVM_SIN_APPROX_FTZ_F = 651,
667
    INT_NVVM_SQRT_APPROX_F  = 652,
668
    INT_NVVM_SQRT_APPROX_FTZ_F  = 653,
669
    INT_NVVM_SQRT_RM_D  = 654,
670
    INT_NVVM_SQRT_RM_F  = 655,
671
    INT_NVVM_SQRT_RM_FTZ_F  = 656,
672
    INT_NVVM_SQRT_RN_D  = 657,
673
    INT_NVVM_SQRT_RN_F  = 658,
674
    INT_NVVM_SQRT_RN_FTZ_F  = 659,
675
    INT_NVVM_SQRT_RP_D  = 660,
676
    INT_NVVM_SQRT_RP_F  = 661,
677
    INT_NVVM_SQRT_RP_FTZ_F  = 662,
678
    INT_NVVM_SQRT_RZ_D  = 663,
679
    INT_NVVM_SQRT_RZ_F  = 664,
680
    INT_NVVM_SQRT_RZ_FTZ_F  = 665,
681
    INT_PTX_ATOM_ADD_GEN_32_USE_Gp32imm = 666,
682
    INT_PTX_ATOM_ADD_GEN_32_USE_Gp32reg = 667,
683
    INT_PTX_ATOM_ADD_GEN_32_USE_Gp64imm = 668,
684
    INT_PTX_ATOM_ADD_GEN_32_USE_Gp64reg = 669,
685
    INT_PTX_ATOM_ADD_GEN_32p32imm = 670,
686
    INT_PTX_ATOM_ADD_GEN_32p32reg = 671,
687
    INT_PTX_ATOM_ADD_GEN_32p64imm = 672,
688
    INT_PTX_ATOM_ADD_GEN_32p64reg = 673,
689
    INT_PTX_ATOM_ADD_GEN_64_USE_Gp32imm = 674,
690
    INT_PTX_ATOM_ADD_GEN_64_USE_Gp32reg = 675,
691
    INT_PTX_ATOM_ADD_GEN_64_USE_Gp64imm = 676,
692
    INT_PTX_ATOM_ADD_GEN_64_USE_Gp64reg = 677,
693
    INT_PTX_ATOM_ADD_GEN_64p32imm = 678,
694
    INT_PTX_ATOM_ADD_GEN_64p32reg = 679,
695
    INT_PTX_ATOM_ADD_GEN_64p64imm = 680,
696
    INT_PTX_ATOM_ADD_GEN_64p64reg = 681,
697
    INT_PTX_ATOM_ADD_GEN_F32p32imm  = 682,
698
    INT_PTX_ATOM_ADD_GEN_F32p32reg  = 683,
699
    INT_PTX_ATOM_ADD_GEN_F32p64imm  = 684,
700
    INT_PTX_ATOM_ADD_GEN_F32p64reg  = 685,
701
    INT_PTX_ATOM_ADD_GEN_F64p32imm  = 686,
702
    INT_PTX_ATOM_ADD_GEN_F64p32reg  = 687,
703
    INT_PTX_ATOM_ADD_GEN_F64p64imm  = 688,
704
    INT_PTX_ATOM_ADD_GEN_F64p64reg  = 689,
705
    INT_PTX_ATOM_ADD_G_32p32imm = 690,
706
    INT_PTX_ATOM_ADD_G_32p32reg = 691,
707
    INT_PTX_ATOM_ADD_G_32p64imm = 692,
708
    INT_PTX_ATOM_ADD_G_32p64reg = 693,
709
    INT_PTX_ATOM_ADD_G_64p32imm = 694,
710
    INT_PTX_ATOM_ADD_G_64p32reg = 695,
711
    INT_PTX_ATOM_ADD_G_64p64imm = 696,
712
    INT_PTX_ATOM_ADD_G_64p64reg = 697,
713
    INT_PTX_ATOM_ADD_G_F32p32imm  = 698,
714
    INT_PTX_ATOM_ADD_G_F32p32reg  = 699,
715
    INT_PTX_ATOM_ADD_G_F32p64imm  = 700,
716
    INT_PTX_ATOM_ADD_G_F32p64reg  = 701,
717
    INT_PTX_ATOM_ADD_G_F64p32imm  = 702,
718
    INT_PTX_ATOM_ADD_G_F64p32reg  = 703,
719
    INT_PTX_ATOM_ADD_G_F64p64imm  = 704,
720
    INT_PTX_ATOM_ADD_G_F64p64reg  = 705,
721
    INT_PTX_ATOM_ADD_S_32p32imm = 706,
722
    INT_PTX_ATOM_ADD_S_32p32reg = 707,
723
    INT_PTX_ATOM_ADD_S_32p64imm = 708,
724
    INT_PTX_ATOM_ADD_S_32p64reg = 709,
725
    INT_PTX_ATOM_ADD_S_64p32imm = 710,
726
    INT_PTX_ATOM_ADD_S_64p32reg = 711,
727
    INT_PTX_ATOM_ADD_S_64p64imm = 712,
728
    INT_PTX_ATOM_ADD_S_64p64reg = 713,
729
    INT_PTX_ATOM_ADD_S_F32p32imm  = 714,
730
    INT_PTX_ATOM_ADD_S_F32p32reg  = 715,
731
    INT_PTX_ATOM_ADD_S_F32p64imm  = 716,
732
    INT_PTX_ATOM_ADD_S_F32p64reg  = 717,
733
    INT_PTX_ATOM_ADD_S_F64p32imm  = 718,
734
    INT_PTX_ATOM_ADD_S_F64p32reg  = 719,
735
    INT_PTX_ATOM_ADD_S_F64p64imm  = 720,
736
    INT_PTX_ATOM_ADD_S_F64p64reg  = 721,
737
    INT_PTX_ATOM_AND_GEN_32_USE_Gp32imm = 722,
738
    INT_PTX_ATOM_AND_GEN_32_USE_Gp32reg = 723,
739
    INT_PTX_ATOM_AND_GEN_32_USE_Gp64imm = 724,
740
    INT_PTX_ATOM_AND_GEN_32_USE_Gp64reg = 725,
741
    INT_PTX_ATOM_AND_GEN_32p32imm = 726,
742
    INT_PTX_ATOM_AND_GEN_32p32reg = 727,
743
    INT_PTX_ATOM_AND_GEN_32p64imm = 728,
744
    INT_PTX_ATOM_AND_GEN_32p64reg = 729,
745
    INT_PTX_ATOM_AND_GEN_64_USE_Gp32imm = 730,
746
    INT_PTX_ATOM_AND_GEN_64_USE_Gp32reg = 731,
747
    INT_PTX_ATOM_AND_GEN_64_USE_Gp64imm = 732,
748
    INT_PTX_ATOM_AND_GEN_64_USE_Gp64reg = 733,
749
    INT_PTX_ATOM_AND_GEN_64p32imm = 734,
750
    INT_PTX_ATOM_AND_GEN_64p32reg = 735,
751
    INT_PTX_ATOM_AND_GEN_64p64imm = 736,
752
    INT_PTX_ATOM_AND_GEN_64p64reg = 737,
753
    INT_PTX_ATOM_AND_G_32p32imm = 738,
754
    INT_PTX_ATOM_AND_G_32p32reg = 739,
755
    INT_PTX_ATOM_AND_G_32p64imm = 740,
756
    INT_PTX_ATOM_AND_G_32p64reg = 741,
757
    INT_PTX_ATOM_AND_G_64p32imm = 742,
758
    INT_PTX_ATOM_AND_G_64p32reg = 743,
759
    INT_PTX_ATOM_AND_G_64p64imm = 744,
760
    INT_PTX_ATOM_AND_G_64p64reg = 745,
761
    INT_PTX_ATOM_AND_S_32p32imm = 746,
762
    INT_PTX_ATOM_AND_S_32p32reg = 747,
763
    INT_PTX_ATOM_AND_S_32p64imm = 748,
764
    INT_PTX_ATOM_AND_S_32p64reg = 749,
765
    INT_PTX_ATOM_AND_S_64p32imm = 750,
766
    INT_PTX_ATOM_AND_S_64p32reg = 751,
767
    INT_PTX_ATOM_AND_S_64p64imm = 752,
768
    INT_PTX_ATOM_AND_S_64p64reg = 753,
769
    INT_PTX_ATOM_CAS_GEN_32_USE_Gp32imm1  = 754,
770
    INT_PTX_ATOM_CAS_GEN_32_USE_Gp32imm2  = 755,
771
    INT_PTX_ATOM_CAS_GEN_32_USE_Gp32imm3  = 756,
772
    INT_PTX_ATOM_CAS_GEN_32_USE_Gp32reg = 757,
773
    INT_PTX_ATOM_CAS_GEN_32_USE_Gp64imm1  = 758,
774
    INT_PTX_ATOM_CAS_GEN_32_USE_Gp64imm2  = 759,
775
    INT_PTX_ATOM_CAS_GEN_32_USE_Gp64imm3  = 760,
776
    INT_PTX_ATOM_CAS_GEN_32_USE_Gp64reg = 761,
777
    INT_PTX_ATOM_CAS_GEN_32p32imm1  = 762,
778
    INT_PTX_ATOM_CAS_GEN_32p32imm2  = 763,
779
    INT_PTX_ATOM_CAS_GEN_32p32imm3  = 764,
780
    INT_PTX_ATOM_CAS_GEN_32p32reg = 765,
781
    INT_PTX_ATOM_CAS_GEN_32p64imm1  = 766,
782
    INT_PTX_ATOM_CAS_GEN_32p64imm2  = 767,
783
    INT_PTX_ATOM_CAS_GEN_32p64imm3  = 768,
784
    INT_PTX_ATOM_CAS_GEN_32p64reg = 769,
785
    INT_PTX_ATOM_CAS_GEN_64_USE_Gp32imm1  = 770,
786
    INT_PTX_ATOM_CAS_GEN_64_USE_Gp32imm2  = 771,
787
    INT_PTX_ATOM_CAS_GEN_64_USE_Gp32imm3  = 772,
788
    INT_PTX_ATOM_CAS_GEN_64_USE_Gp32reg = 773,
789
    INT_PTX_ATOM_CAS_GEN_64_USE_Gp64imm1  = 774,
790
    INT_PTX_ATOM_CAS_GEN_64_USE_Gp64imm2  = 775,
791
    INT_PTX_ATOM_CAS_GEN_64_USE_Gp64imm3  = 776,
792
    INT_PTX_ATOM_CAS_GEN_64_USE_Gp64reg = 777,
793
    INT_PTX_ATOM_CAS_GEN_64p32imm1  = 778,
794
    INT_PTX_ATOM_CAS_GEN_64p32imm2  = 779,
795
    INT_PTX_ATOM_CAS_GEN_64p32imm3  = 780,
796
    INT_PTX_ATOM_CAS_GEN_64p32reg = 781,
797
    INT_PTX_ATOM_CAS_GEN_64p64imm1  = 782,
798
    INT_PTX_ATOM_CAS_GEN_64p64imm2  = 783,
799
    INT_PTX_ATOM_CAS_GEN_64p64imm3  = 784,
800
    INT_PTX_ATOM_CAS_GEN_64p64reg = 785,
801
    INT_PTX_ATOM_CAS_G_32p32imm1  = 786,
802
    INT_PTX_ATOM_CAS_G_32p32imm2  = 787,
803
    INT_PTX_ATOM_CAS_G_32p32imm3  = 788,
804
    INT_PTX_ATOM_CAS_G_32p32reg = 789,
805
    INT_PTX_ATOM_CAS_G_32p64imm1  = 790,
806
    INT_PTX_ATOM_CAS_G_32p64imm2  = 791,
807
    INT_PTX_ATOM_CAS_G_32p64imm3  = 792,
808
    INT_PTX_ATOM_CAS_G_32p64reg = 793,
809
    INT_PTX_ATOM_CAS_G_64p32imm1  = 794,
810
    INT_PTX_ATOM_CAS_G_64p32imm2  = 795,
811
    INT_PTX_ATOM_CAS_G_64p32imm3  = 796,
812
    INT_PTX_ATOM_CAS_G_64p32reg = 797,
813
    INT_PTX_ATOM_CAS_G_64p64imm1  = 798,
814
    INT_PTX_ATOM_CAS_G_64p64imm2  = 799,
815
    INT_PTX_ATOM_CAS_G_64p64imm3  = 800,
816
    INT_PTX_ATOM_CAS_G_64p64reg = 801,
817
    INT_PTX_ATOM_CAS_S_32p32imm1  = 802,
818
    INT_PTX_ATOM_CAS_S_32p32imm2  = 803,
819
    INT_PTX_ATOM_CAS_S_32p32imm3  = 804,
820
    INT_PTX_ATOM_CAS_S_32p32reg = 805,
821
    INT_PTX_ATOM_CAS_S_32p64imm1  = 806,
822
    INT_PTX_ATOM_CAS_S_32p64imm2  = 807,
823
    INT_PTX_ATOM_CAS_S_32p64imm3  = 808,
824
    INT_PTX_ATOM_CAS_S_32p64reg = 809,
825
    INT_PTX_ATOM_CAS_S_64p32imm1  = 810,
826
    INT_PTX_ATOM_CAS_S_64p32imm2  = 811,
827
    INT_PTX_ATOM_CAS_S_64p32imm3  = 812,
828
    INT_PTX_ATOM_CAS_S_64p32reg = 813,
829
    INT_PTX_ATOM_CAS_S_64p64imm1  = 814,
830
    INT_PTX_ATOM_CAS_S_64p64imm2  = 815,
831
    INT_PTX_ATOM_CAS_S_64p64imm3  = 816,
832
    INT_PTX_ATOM_CAS_S_64p64reg = 817,
833
    INT_PTX_ATOM_DEC_GEN_32_USE_Gp32imm = 818,
834
    INT_PTX_ATOM_DEC_GEN_32_USE_Gp32reg = 819,
835
    INT_PTX_ATOM_DEC_GEN_32_USE_Gp64imm = 820,
836
    INT_PTX_ATOM_DEC_GEN_32_USE_Gp64reg = 821,
837
    INT_PTX_ATOM_DEC_GEN_32p32imm = 822,
838
    INT_PTX_ATOM_DEC_GEN_32p32reg = 823,
839
    INT_PTX_ATOM_DEC_GEN_32p64imm = 824,
840
    INT_PTX_ATOM_DEC_GEN_32p64reg = 825,
841
    INT_PTX_ATOM_DEC_G_32p32imm = 826,
842
    INT_PTX_ATOM_DEC_G_32p32reg = 827,
843
    INT_PTX_ATOM_DEC_G_32p64imm = 828,
844
    INT_PTX_ATOM_DEC_G_32p64reg = 829,
845
    INT_PTX_ATOM_DEC_S_32p32imm = 830,
846
    INT_PTX_ATOM_DEC_S_32p32reg = 831,
847
    INT_PTX_ATOM_DEC_S_32p64imm = 832,
848
    INT_PTX_ATOM_DEC_S_32p64reg = 833,
849
    INT_PTX_ATOM_INC_GEN_32_USE_Gp32imm = 834,
850
    INT_PTX_ATOM_INC_GEN_32_USE_Gp32reg = 835,
851
    INT_PTX_ATOM_INC_GEN_32_USE_Gp64imm = 836,
852
    INT_PTX_ATOM_INC_GEN_32_USE_Gp64reg = 837,
853
    INT_PTX_ATOM_INC_GEN_32p32imm = 838,
854
    INT_PTX_ATOM_INC_GEN_32p32reg = 839,
855
    INT_PTX_ATOM_INC_GEN_32p64imm = 840,
856
    INT_PTX_ATOM_INC_GEN_32p64reg = 841,
857
    INT_PTX_ATOM_INC_G_32p32imm = 842,
858
    INT_PTX_ATOM_INC_G_32p32reg = 843,
859
    INT_PTX_ATOM_INC_G_32p64imm = 844,
860
    INT_PTX_ATOM_INC_G_32p64reg = 845,
861
    INT_PTX_ATOM_INC_S_32p32imm = 846,
862
    INT_PTX_ATOM_INC_S_32p32reg = 847,
863
    INT_PTX_ATOM_INC_S_32p64imm = 848,
864
    INT_PTX_ATOM_INC_S_32p64reg = 849,
865
    INT_PTX_ATOM_LOAD_MAX_GEN_32_USE_Gp32imm  = 850,
866
    INT_PTX_ATOM_LOAD_MAX_GEN_32_USE_Gp32reg  = 851,
867
    INT_PTX_ATOM_LOAD_MAX_GEN_32_USE_Gp64imm  = 852,
868
    INT_PTX_ATOM_LOAD_MAX_GEN_32_USE_Gp64reg  = 853,
869
    INT_PTX_ATOM_LOAD_MAX_GEN_32p32imm  = 854,
870
    INT_PTX_ATOM_LOAD_MAX_GEN_32p32reg  = 855,
871
    INT_PTX_ATOM_LOAD_MAX_GEN_32p64imm  = 856,
872
    INT_PTX_ATOM_LOAD_MAX_GEN_32p64reg  = 857,
873
    INT_PTX_ATOM_LOAD_MAX_GEN_64_USE_Gp32imm  = 858,
874
    INT_PTX_ATOM_LOAD_MAX_GEN_64_USE_Gp32reg  = 859,
875
    INT_PTX_ATOM_LOAD_MAX_GEN_64_USE_Gp64imm  = 860,
876
    INT_PTX_ATOM_LOAD_MAX_GEN_64_USE_Gp64reg  = 861,
877
    INT_PTX_ATOM_LOAD_MAX_GEN_64p32imm  = 862,
878
    INT_PTX_ATOM_LOAD_MAX_GEN_64p32reg  = 863,
879
    INT_PTX_ATOM_LOAD_MAX_GEN_64p64imm  = 864,
880
    INT_PTX_ATOM_LOAD_MAX_GEN_64p64reg  = 865,
881
    INT_PTX_ATOM_LOAD_MAX_G_32p32imm  = 866,
882
    INT_PTX_ATOM_LOAD_MAX_G_32p32reg  = 867,
883
    INT_PTX_ATOM_LOAD_MAX_G_32p64imm  = 868,
884
    INT_PTX_ATOM_LOAD_MAX_G_32p64reg  = 869,
885
    INT_PTX_ATOM_LOAD_MAX_G_64p32imm  = 870,
886
    INT_PTX_ATOM_LOAD_MAX_G_64p32reg  = 871,
887
    INT_PTX_ATOM_LOAD_MAX_G_64p64imm  = 872,
888
    INT_PTX_ATOM_LOAD_MAX_G_64p64reg  = 873,
889
    INT_PTX_ATOM_LOAD_MAX_S_32p32imm  = 874,
890
    INT_PTX_ATOM_LOAD_MAX_S_32p32reg  = 875,
891
    INT_PTX_ATOM_LOAD_MAX_S_32p64imm  = 876,
892
    INT_PTX_ATOM_LOAD_MAX_S_32p64reg  = 877,
893
    INT_PTX_ATOM_LOAD_MAX_S_64p32imm  = 878,
894
    INT_PTX_ATOM_LOAD_MAX_S_64p32reg  = 879,
895
    INT_PTX_ATOM_LOAD_MAX_S_64p64imm  = 880,
896
    INT_PTX_ATOM_LOAD_MAX_S_64p64reg  = 881,
897
    INT_PTX_ATOM_LOAD_MIN_GEN_32_USE_Gp32imm  = 882,
898
    INT_PTX_ATOM_LOAD_MIN_GEN_32_USE_Gp32reg  = 883,
899
    INT_PTX_ATOM_LOAD_MIN_GEN_32_USE_Gp64imm  = 884,
900
    INT_PTX_ATOM_LOAD_MIN_GEN_32_USE_Gp64reg  = 885,
901
    INT_PTX_ATOM_LOAD_MIN_GEN_32p32imm  = 886,
902
    INT_PTX_ATOM_LOAD_MIN_GEN_32p32reg  = 887,
903
    INT_PTX_ATOM_LOAD_MIN_GEN_32p64imm  = 888,
904
    INT_PTX_ATOM_LOAD_MIN_GEN_32p64reg  = 889,
905
    INT_PTX_ATOM_LOAD_MIN_GEN_64_USE_Gp32imm  = 890,
906
    INT_PTX_ATOM_LOAD_MIN_GEN_64_USE_Gp32reg  = 891,
907
    INT_PTX_ATOM_LOAD_MIN_GEN_64_USE_Gp64imm  = 892,
908
    INT_PTX_ATOM_LOAD_MIN_GEN_64_USE_Gp64reg  = 893,
909
    INT_PTX_ATOM_LOAD_MIN_GEN_64p32imm  = 894,
910
    INT_PTX_ATOM_LOAD_MIN_GEN_64p32reg  = 895,
911
    INT_PTX_ATOM_LOAD_MIN_GEN_64p64imm  = 896,
912
    INT_PTX_ATOM_LOAD_MIN_GEN_64p64reg  = 897,
913
    INT_PTX_ATOM_LOAD_MIN_G_32p32imm  = 898,
914
    INT_PTX_ATOM_LOAD_MIN_G_32p32reg  = 899,
915
    INT_PTX_ATOM_LOAD_MIN_G_32p64imm  = 900,
916
    INT_PTX_ATOM_LOAD_MIN_G_32p64reg  = 901,
917
    INT_PTX_ATOM_LOAD_MIN_G_64p32imm  = 902,
918
    INT_PTX_ATOM_LOAD_MIN_G_64p32reg  = 903,
919
    INT_PTX_ATOM_LOAD_MIN_G_64p64imm  = 904,
920
    INT_PTX_ATOM_LOAD_MIN_G_64p64reg  = 905,
921
    INT_PTX_ATOM_LOAD_MIN_S_32p32imm  = 906,
922
    INT_PTX_ATOM_LOAD_MIN_S_32p32reg  = 907,
923
    INT_PTX_ATOM_LOAD_MIN_S_32p64imm  = 908,
924
    INT_PTX_ATOM_LOAD_MIN_S_32p64reg  = 909,
925
    INT_PTX_ATOM_LOAD_MIN_S_64p32imm  = 910,
926
    INT_PTX_ATOM_LOAD_MIN_S_64p32reg  = 911,
927
    INT_PTX_ATOM_LOAD_MIN_S_64p64imm  = 912,
928
    INT_PTX_ATOM_LOAD_MIN_S_64p64reg  = 913,
929
    INT_PTX_ATOM_LOAD_UMAX_GEN_32_USE_Gp32imm = 914,
930
    INT_PTX_ATOM_LOAD_UMAX_GEN_32_USE_Gp32reg = 915,
931
    INT_PTX_ATOM_LOAD_UMAX_GEN_32_USE_Gp64imm = 916,
932
    INT_PTX_ATOM_LOAD_UMAX_GEN_32_USE_Gp64reg = 917,
933
    INT_PTX_ATOM_LOAD_UMAX_GEN_32p32imm = 918,
934
    INT_PTX_ATOM_LOAD_UMAX_GEN_32p32reg = 919,
935
    INT_PTX_ATOM_LOAD_UMAX_GEN_32p64imm = 920,
936
    INT_PTX_ATOM_LOAD_UMAX_GEN_32p64reg = 921,
937
    INT_PTX_ATOM_LOAD_UMAX_GEN_64_USE_Gp32imm = 922,
938
    INT_PTX_ATOM_LOAD_UMAX_GEN_64_USE_Gp32reg = 923,
939
    INT_PTX_ATOM_LOAD_UMAX_GEN_64_USE_Gp64imm = 924,
940
    INT_PTX_ATOM_LOAD_UMAX_GEN_64_USE_Gp64reg = 925,
941
    INT_PTX_ATOM_LOAD_UMAX_GEN_64p32imm = 926,
942
    INT_PTX_ATOM_LOAD_UMAX_GEN_64p32reg = 927,
943
    INT_PTX_ATOM_LOAD_UMAX_GEN_64p64imm = 928,
944
    INT_PTX_ATOM_LOAD_UMAX_GEN_64p64reg = 929,
945
    INT_PTX_ATOM_LOAD_UMAX_G_32p32imm = 930,
946
    INT_PTX_ATOM_LOAD_UMAX_G_32p32reg = 931,
947
    INT_PTX_ATOM_LOAD_UMAX_G_32p64imm = 932,
948
    INT_PTX_ATOM_LOAD_UMAX_G_32p64reg = 933,
949
    INT_PTX_ATOM_LOAD_UMAX_G_64p32imm = 934,
950
    INT_PTX_ATOM_LOAD_UMAX_G_64p32reg = 935,
951
    INT_PTX_ATOM_LOAD_UMAX_G_64p64imm = 936,
952
    INT_PTX_ATOM_LOAD_UMAX_G_64p64reg = 937,
953
    INT_PTX_ATOM_LOAD_UMAX_S_32p32imm = 938,
954
    INT_PTX_ATOM_LOAD_UMAX_S_32p32reg = 939,
955
    INT_PTX_ATOM_LOAD_UMAX_S_32p64imm = 940,
956
    INT_PTX_ATOM_LOAD_UMAX_S_32p64reg = 941,
957
    INT_PTX_ATOM_LOAD_UMAX_S_64p32imm = 942,
958
    INT_PTX_ATOM_LOAD_UMAX_S_64p32reg = 943,
959
    INT_PTX_ATOM_LOAD_UMAX_S_64p64imm = 944,
960
    INT_PTX_ATOM_LOAD_UMAX_S_64p64reg = 945,
961
    INT_PTX_ATOM_LOAD_UMIN_GEN_32_USE_Gp32imm = 946,
962
    INT_PTX_ATOM_LOAD_UMIN_GEN_32_USE_Gp32reg = 947,
963
    INT_PTX_ATOM_LOAD_UMIN_GEN_32_USE_Gp64imm = 948,
964
    INT_PTX_ATOM_LOAD_UMIN_GEN_32_USE_Gp64reg = 949,
965
    INT_PTX_ATOM_LOAD_UMIN_GEN_32p32imm = 950,
966
    INT_PTX_ATOM_LOAD_UMIN_GEN_32p32reg = 951,
967
    INT_PTX_ATOM_LOAD_UMIN_GEN_32p64imm = 952,
968
    INT_PTX_ATOM_LOAD_UMIN_GEN_32p64reg = 953,
969
    INT_PTX_ATOM_LOAD_UMIN_GEN_64_USE_Gp32imm = 954,
970
    INT_PTX_ATOM_LOAD_UMIN_GEN_64_USE_Gp32reg = 955,
971
    INT_PTX_ATOM_LOAD_UMIN_GEN_64_USE_Gp64imm = 956,
972
    INT_PTX_ATOM_LOAD_UMIN_GEN_64_USE_Gp64reg = 957,
973
    INT_PTX_ATOM_LOAD_UMIN_GEN_64p32imm = 958,
974
    INT_PTX_ATOM_LOAD_UMIN_GEN_64p32reg = 959,
975
    INT_PTX_ATOM_LOAD_UMIN_GEN_64p64imm = 960,
976
    INT_PTX_ATOM_LOAD_UMIN_GEN_64p64reg = 961,
977
    INT_PTX_ATOM_LOAD_UMIN_G_32p32imm = 962,
978
    INT_PTX_ATOM_LOAD_UMIN_G_32p32reg = 963,
979
    INT_PTX_ATOM_LOAD_UMIN_G_32p64imm = 964,
980
    INT_PTX_ATOM_LOAD_UMIN_G_32p64reg = 965,
981
    INT_PTX_ATOM_LOAD_UMIN_G_64p32imm = 966,
982
    INT_PTX_ATOM_LOAD_UMIN_G_64p32reg = 967,
983
    INT_PTX_ATOM_LOAD_UMIN_G_64p64imm = 968,
984
    INT_PTX_ATOM_LOAD_UMIN_G_64p64reg = 969,
985
    INT_PTX_ATOM_LOAD_UMIN_S_32p32imm = 970,
986
    INT_PTX_ATOM_LOAD_UMIN_S_32p32reg = 971,
987
    INT_PTX_ATOM_LOAD_UMIN_S_32p64imm = 972,
988
    INT_PTX_ATOM_LOAD_UMIN_S_32p64reg = 973,
989
    INT_PTX_ATOM_LOAD_UMIN_S_64p32imm = 974,
990
    INT_PTX_ATOM_LOAD_UMIN_S_64p32reg = 975,
991
    INT_PTX_ATOM_LOAD_UMIN_S_64p64imm = 976,
992
    INT_PTX_ATOM_LOAD_UMIN_S_64p64reg = 977,
993
    INT_PTX_ATOM_OR_GEN_32_USE_Gp32imm  = 978,
994
    INT_PTX_ATOM_OR_GEN_32_USE_Gp32reg  = 979,
995
    INT_PTX_ATOM_OR_GEN_32_USE_Gp64imm  = 980,
996
    INT_PTX_ATOM_OR_GEN_32_USE_Gp64reg  = 981,
997
    INT_PTX_ATOM_OR_GEN_32p32imm  = 982,
998
    INT_PTX_ATOM_OR_GEN_32p32reg  = 983,
999
    INT_PTX_ATOM_OR_GEN_32p64imm  = 984,
1000
    INT_PTX_ATOM_OR_GEN_32p64reg  = 985,
1001
    INT_PTX_ATOM_OR_GEN_64_USE_Gp32imm  = 986,
1002
    INT_PTX_ATOM_OR_GEN_64_USE_Gp32reg  = 987,
1003
    INT_PTX_ATOM_OR_GEN_64_USE_Gp64imm  = 988,
1004
    INT_PTX_ATOM_OR_GEN_64_USE_Gp64reg  = 989,
1005
    INT_PTX_ATOM_OR_GEN_64p32imm  = 990,
1006
    INT_PTX_ATOM_OR_GEN_64p32reg  = 991,
1007
    INT_PTX_ATOM_OR_GEN_64p64imm  = 992,
1008
    INT_PTX_ATOM_OR_GEN_64p64reg  = 993,
1009
    INT_PTX_ATOM_OR_G_32p32imm  = 994,
1010
    INT_PTX_ATOM_OR_G_32p32reg  = 995,
1011
    INT_PTX_ATOM_OR_G_32p64imm  = 996,
1012
    INT_PTX_ATOM_OR_G_32p64reg  = 997,
1013
    INT_PTX_ATOM_OR_G_64p32imm  = 998,
1014
    INT_PTX_ATOM_OR_G_64p32reg  = 999,
1015
    INT_PTX_ATOM_OR_G_64p64imm  = 1000,
1016
    INT_PTX_ATOM_OR_G_64p64reg  = 1001,
1017
    INT_PTX_ATOM_OR_S_32p32imm  = 1002,
1018
    INT_PTX_ATOM_OR_S_32p32reg  = 1003,
1019
    INT_PTX_ATOM_OR_S_32p64imm  = 1004,
1020
    INT_PTX_ATOM_OR_S_32p64reg  = 1005,
1021
    INT_PTX_ATOM_OR_S_64p32imm  = 1006,
1022
    INT_PTX_ATOM_OR_S_64p32reg  = 1007,
1023
    INT_PTX_ATOM_OR_S_64p64imm  = 1008,
1024
    INT_PTX_ATOM_OR_S_64p64reg  = 1009,
1025
    INT_PTX_ATOM_SUB_GEN_32_USE_Gp32reg = 1010,
1026
    INT_PTX_ATOM_SUB_GEN_32_USE_Gp64reg = 1011,
1027
    INT_PTX_ATOM_SUB_GEN_32p32reg = 1012,
1028
    INT_PTX_ATOM_SUB_GEN_32p64reg = 1013,
1029
    INT_PTX_ATOM_SUB_GEN_64_USE_Gp32reg = 1014,
1030
    INT_PTX_ATOM_SUB_GEN_64_USE_Gp64reg = 1015,
1031
    INT_PTX_ATOM_SUB_GEN_64p32reg = 1016,
1032
    INT_PTX_ATOM_SUB_GEN_64p64reg = 1017,
1033
    INT_PTX_ATOM_SUB_G_32p32reg = 1018,
1034
    INT_PTX_ATOM_SUB_G_32p64reg = 1019,
1035
    INT_PTX_ATOM_SUB_G_64p32reg = 1020,
1036
    INT_PTX_ATOM_SUB_G_64p64reg = 1021,
1037
    INT_PTX_ATOM_SUB_S_32p32reg = 1022,
1038
    INT_PTX_ATOM_SUB_S_32p64reg = 1023,
1039
    INT_PTX_ATOM_SUB_S_64p32reg = 1024,
1040
    INT_PTX_ATOM_SUB_S_64p64reg = 1025,
1041
    INT_PTX_ATOM_SWAP_GEN_32_USE_Gp32imm  = 1026,
1042
    INT_PTX_ATOM_SWAP_GEN_32_USE_Gp32reg  = 1027,
1043
    INT_PTX_ATOM_SWAP_GEN_32_USE_Gp64imm  = 1028,
1044
    INT_PTX_ATOM_SWAP_GEN_32_USE_Gp64reg  = 1029,
1045
    INT_PTX_ATOM_SWAP_GEN_32p32imm  = 1030,
1046
    INT_PTX_ATOM_SWAP_GEN_32p32reg  = 1031,
1047
    INT_PTX_ATOM_SWAP_GEN_32p64imm  = 1032,
1048
    INT_PTX_ATOM_SWAP_GEN_32p64reg  = 1033,
1049
    INT_PTX_ATOM_SWAP_GEN_64_USE_Gp32imm  = 1034,
1050
    INT_PTX_ATOM_SWAP_GEN_64_USE_Gp32reg  = 1035,
1051
    INT_PTX_ATOM_SWAP_GEN_64_USE_Gp64imm  = 1036,
1052
    INT_PTX_ATOM_SWAP_GEN_64_USE_Gp64reg  = 1037,
1053
    INT_PTX_ATOM_SWAP_GEN_64p32imm  = 1038,
1054
    INT_PTX_ATOM_SWAP_GEN_64p32reg  = 1039,
1055
    INT_PTX_ATOM_SWAP_GEN_64p64imm  = 1040,
1056
    INT_PTX_ATOM_SWAP_GEN_64p64reg  = 1041,
1057
    INT_PTX_ATOM_SWAP_G_32p32imm  = 1042,
1058
    INT_PTX_ATOM_SWAP_G_32p32reg  = 1043,
1059
    INT_PTX_ATOM_SWAP_G_32p64imm  = 1044,
1060
    INT_PTX_ATOM_SWAP_G_32p64reg  = 1045,
1061
    INT_PTX_ATOM_SWAP_G_64p32imm  = 1046,
1062
    INT_PTX_ATOM_SWAP_G_64p32reg  = 1047,
1063
    INT_PTX_ATOM_SWAP_G_64p64imm  = 1048,
1064
    INT_PTX_ATOM_SWAP_G_64p64reg  = 1049,
1065
    INT_PTX_ATOM_SWAP_S_32p32imm  = 1050,
1066
    INT_PTX_ATOM_SWAP_S_32p32reg  = 1051,
1067
    INT_PTX_ATOM_SWAP_S_32p64imm  = 1052,
1068
    INT_PTX_ATOM_SWAP_S_32p64reg  = 1053,
1069
    INT_PTX_ATOM_SWAP_S_64p32imm  = 1054,
1070
    INT_PTX_ATOM_SWAP_S_64p32reg  = 1055,
1071
    INT_PTX_ATOM_SWAP_S_64p64imm  = 1056,
1072
    INT_PTX_ATOM_SWAP_S_64p64reg  = 1057,
1073
    INT_PTX_ATOM_XOR_GEN_32_USE_Gp32imm = 1058,
1074
    INT_PTX_ATOM_XOR_GEN_32_USE_Gp32reg = 1059,
1075
    INT_PTX_ATOM_XOR_GEN_32_USE_Gp64imm = 1060,
1076
    INT_PTX_ATOM_XOR_GEN_32_USE_Gp64reg = 1061,
1077
    INT_PTX_ATOM_XOR_GEN_32p32imm = 1062,
1078
    INT_PTX_ATOM_XOR_GEN_32p32reg = 1063,
1079
    INT_PTX_ATOM_XOR_GEN_32p64imm = 1064,
1080
    INT_PTX_ATOM_XOR_GEN_32p64reg = 1065,
1081
    INT_PTX_ATOM_XOR_GEN_64_USE_Gp32imm = 1066,
1082
    INT_PTX_ATOM_XOR_GEN_64_USE_Gp32reg = 1067,
1083
    INT_PTX_ATOM_XOR_GEN_64_USE_Gp64imm = 1068,
1084
    INT_PTX_ATOM_XOR_GEN_64_USE_Gp64reg = 1069,
1085
    INT_PTX_ATOM_XOR_GEN_64p32imm = 1070,
1086
    INT_PTX_ATOM_XOR_GEN_64p32reg = 1071,
1087
    INT_PTX_ATOM_XOR_GEN_64p64imm = 1072,
1088
    INT_PTX_ATOM_XOR_GEN_64p64reg = 1073,
1089
    INT_PTX_ATOM_XOR_G_32p32imm = 1074,
1090
    INT_PTX_ATOM_XOR_G_32p32reg = 1075,
1091
    INT_PTX_ATOM_XOR_G_32p64imm = 1076,
1092
    INT_PTX_ATOM_XOR_G_32p64reg = 1077,
1093
    INT_PTX_ATOM_XOR_G_64p32imm = 1078,
1094
    INT_PTX_ATOM_XOR_G_64p32reg = 1079,
1095
    INT_PTX_ATOM_XOR_G_64p64imm = 1080,
1096
    INT_PTX_ATOM_XOR_G_64p64reg = 1081,
1097
    INT_PTX_ATOM_XOR_S_32p32imm = 1082,
1098
    INT_PTX_ATOM_XOR_S_32p32reg = 1083,
1099
    INT_PTX_ATOM_XOR_S_32p64imm = 1084,
1100
    INT_PTX_ATOM_XOR_S_32p64reg = 1085,
1101
    INT_PTX_ATOM_XOR_S_64p32imm = 1086,
1102
    INT_PTX_ATOM_XOR_S_64p32reg = 1087,
1103
    INT_PTX_ATOM_XOR_S_64p64imm = 1088,
1104
    INT_PTX_ATOM_XOR_S_64p64reg = 1089,
1105
    INT_PTX_LDG_GLOBAL_f16areg  = 1090,
1106
    INT_PTX_LDG_GLOBAL_f16areg64  = 1091,
1107
    INT_PTX_LDG_GLOBAL_f16ari = 1092,
1108
    INT_PTX_LDG_GLOBAL_f16ari64 = 1093,
1109
    INT_PTX_LDG_GLOBAL_f16avar  = 1094,
1110
    INT_PTX_LDG_GLOBAL_f16x2areg  = 1095,
1111
    INT_PTX_LDG_GLOBAL_f16x2areg64  = 1096,
1112
    INT_PTX_LDG_GLOBAL_f16x2ari = 1097,
1113
    INT_PTX_LDG_GLOBAL_f16x2ari64 = 1098,
1114
    INT_PTX_LDG_GLOBAL_f16x2avar  = 1099,
1115
    INT_PTX_LDG_GLOBAL_f32areg  = 1100,
1116
    INT_PTX_LDG_GLOBAL_f32areg64  = 1101,
1117
    INT_PTX_LDG_GLOBAL_f32ari = 1102,
1118
    INT_PTX_LDG_GLOBAL_f32ari64 = 1103,
1119
    INT_PTX_LDG_GLOBAL_f32avar  = 1104,
1120
    INT_PTX_LDG_GLOBAL_f64areg  = 1105,
1121
    INT_PTX_LDG_GLOBAL_f64areg64  = 1106,
1122
    INT_PTX_LDG_GLOBAL_f64ari = 1107,
1123
    INT_PTX_LDG_GLOBAL_f64ari64 = 1108,
1124
    INT_PTX_LDG_GLOBAL_f64avar  = 1109,
1125
    INT_PTX_LDG_GLOBAL_i16areg  = 1110,
1126
    INT_PTX_LDG_GLOBAL_i16areg64  = 1111,
1127
    INT_PTX_LDG_GLOBAL_i16ari = 1112,
1128
    INT_PTX_LDG_GLOBAL_i16ari64 = 1113,
1129
    INT_PTX_LDG_GLOBAL_i16avar  = 1114,
1130
    INT_PTX_LDG_GLOBAL_i32areg  = 1115,
1131
    INT_PTX_LDG_GLOBAL_i32areg64  = 1116,
1132
    INT_PTX_LDG_GLOBAL_i32ari = 1117,
1133
    INT_PTX_LDG_GLOBAL_i32ari64 = 1118,
1134
    INT_PTX_LDG_GLOBAL_i32avar  = 1119,
1135
    INT_PTX_LDG_GLOBAL_i64areg  = 1120,
1136
    INT_PTX_LDG_GLOBAL_i64areg64  = 1121,
1137
    INT_PTX_LDG_GLOBAL_i64ari = 1122,
1138
    INT_PTX_LDG_GLOBAL_i64ari64 = 1123,
1139
    INT_PTX_LDG_GLOBAL_i64avar  = 1124,
1140
    INT_PTX_LDG_GLOBAL_i8areg = 1125,
1141
    INT_PTX_LDG_GLOBAL_i8areg64 = 1126,
1142
    INT_PTX_LDG_GLOBAL_i8ari  = 1127,
1143
    INT_PTX_LDG_GLOBAL_i8ari64  = 1128,
1144
    INT_PTX_LDG_GLOBAL_i8avar = 1129,
1145
    INT_PTX_LDG_GLOBAL_p32areg  = 1130,
1146
    INT_PTX_LDG_GLOBAL_p32areg64  = 1131,
1147
    INT_PTX_LDG_GLOBAL_p32ari = 1132,
1148
    INT_PTX_LDG_GLOBAL_p32ari64 = 1133,
1149
    INT_PTX_LDG_GLOBAL_p32avar  = 1134,
1150
    INT_PTX_LDG_GLOBAL_p64areg  = 1135,
1151
    INT_PTX_LDG_GLOBAL_p64areg64  = 1136,
1152
    INT_PTX_LDG_GLOBAL_p64ari = 1137,
1153
    INT_PTX_LDG_GLOBAL_p64ari64 = 1138,
1154
    INT_PTX_LDG_GLOBAL_p64avar  = 1139,
1155
    INT_PTX_LDG_G_v2f16_ELE_areg32  = 1140,
1156
    INT_PTX_LDG_G_v2f16_ELE_areg64  = 1141,
1157
    INT_PTX_LDG_G_v2f16_ELE_ari32 = 1142,
1158
    INT_PTX_LDG_G_v2f16_ELE_ari64 = 1143,
1159
    INT_PTX_LDG_G_v2f16_ELE_avar  = 1144,
1160
    INT_PTX_LDG_G_v2f16x2_ELE_areg32  = 1145,
1161
    INT_PTX_LDG_G_v2f16x2_ELE_areg64  = 1146,
1162
    INT_PTX_LDG_G_v2f16x2_ELE_ari32 = 1147,
1163
    INT_PTX_LDG_G_v2f16x2_ELE_ari64 = 1148,
1164
    INT_PTX_LDG_G_v2f16x2_ELE_avar  = 1149,
1165
    INT_PTX_LDG_G_v2f32_ELE_areg32  = 1150,
1166
    INT_PTX_LDG_G_v2f32_ELE_areg64  = 1151,
1167
    INT_PTX_LDG_G_v2f32_ELE_ari32 = 1152,
1168
    INT_PTX_LDG_G_v2f32_ELE_ari64 = 1153,
1169
    INT_PTX_LDG_G_v2f32_ELE_avar  = 1154,
1170
    INT_PTX_LDG_G_v2f64_ELE_areg32  = 1155,
1171
    INT_PTX_LDG_G_v2f64_ELE_areg64  = 1156,
1172
    INT_PTX_LDG_G_v2f64_ELE_ari32 = 1157,
1173
    INT_PTX_LDG_G_v2f64_ELE_ari64 = 1158,
1174
    INT_PTX_LDG_G_v2f64_ELE_avar  = 1159,
1175
    INT_PTX_LDG_G_v2i16_ELE_areg32  = 1160,
1176
    INT_PTX_LDG_G_v2i16_ELE_areg64  = 1161,
1177
    INT_PTX_LDG_G_v2i16_ELE_ari32 = 1162,
1178
    INT_PTX_LDG_G_v2i16_ELE_ari64 = 1163,
1179
    INT_PTX_LDG_G_v2i16_ELE_avar  = 1164,
1180
    INT_PTX_LDG_G_v2i32_ELE_areg32  = 1165,
1181
    INT_PTX_LDG_G_v2i32_ELE_areg64  = 1166,
1182
    INT_PTX_LDG_G_v2i32_ELE_ari32 = 1167,
1183
    INT_PTX_LDG_G_v2i32_ELE_ari64 = 1168,
1184
    INT_PTX_LDG_G_v2i32_ELE_avar  = 1169,
1185
    INT_PTX_LDG_G_v2i64_ELE_areg32  = 1170,
1186
    INT_PTX_LDG_G_v2i64_ELE_areg64  = 1171,
1187
    INT_PTX_LDG_G_v2i64_ELE_ari32 = 1172,
1188
    INT_PTX_LDG_G_v2i64_ELE_ari64 = 1173,
1189
    INT_PTX_LDG_G_v2i64_ELE_avar  = 1174,
1190
    INT_PTX_LDG_G_v2i8_ELE_areg32 = 1175,
1191
    INT_PTX_LDG_G_v2i8_ELE_areg64 = 1176,
1192
    INT_PTX_LDG_G_v2i8_ELE_ari32  = 1177,
1193
    INT_PTX_LDG_G_v2i8_ELE_ari64  = 1178,
1194
    INT_PTX_LDG_G_v2i8_ELE_avar = 1179,
1195
    INT_PTX_LDG_G_v4f16_ELE_areg32  = 1180,
1196
    INT_PTX_LDG_G_v4f16_ELE_areg64  = 1181,
1197
    INT_PTX_LDG_G_v4f16_ELE_ari32 = 1182,
1198
    INT_PTX_LDG_G_v4f16_ELE_ari64 = 1183,
1199
    INT_PTX_LDG_G_v4f16_ELE_avar  = 1184,
1200
    INT_PTX_LDG_G_v4f16x2_ELE_areg32  = 1185,
1201
    INT_PTX_LDG_G_v4f16x2_ELE_areg64  = 1186,
1202
    INT_PTX_LDG_G_v4f16x2_ELE_ari32 = 1187,
1203
    INT_PTX_LDG_G_v4f16x2_ELE_ari64 = 1188,
1204
    INT_PTX_LDG_G_v4f16x2_ELE_avar  = 1189,
1205
    INT_PTX_LDG_G_v4f32_ELE_areg32  = 1190,
1206
    INT_PTX_LDG_G_v4f32_ELE_areg64  = 1191,
1207
    INT_PTX_LDG_G_v4f32_ELE_ari32 = 1192,
1208
    INT_PTX_LDG_G_v4f32_ELE_ari64 = 1193,
1209
    INT_PTX_LDG_G_v4f32_ELE_avar  = 1194,
1210
    INT_PTX_LDG_G_v4i16_ELE_areg32  = 1195,
1211
    INT_PTX_LDG_G_v4i16_ELE_areg64  = 1196,
1212
    INT_PTX_LDG_G_v4i16_ELE_ari32 = 1197,
1213
    INT_PTX_LDG_G_v4i16_ELE_ari64 = 1198,
1214
    INT_PTX_LDG_G_v4i16_ELE_avar  = 1199,
1215
    INT_PTX_LDG_G_v4i32_ELE_areg32  = 1200,
1216
    INT_PTX_LDG_G_v4i32_ELE_areg64  = 1201,
1217
    INT_PTX_LDG_G_v4i32_ELE_ari32 = 1202,
1218
    INT_PTX_LDG_G_v4i32_ELE_ari64 = 1203,
1219
    INT_PTX_LDG_G_v4i32_ELE_avar  = 1204,
1220
    INT_PTX_LDG_G_v4i8_ELE_areg32 = 1205,
1221
    INT_PTX_LDG_G_v4i8_ELE_areg64 = 1206,
1222
    INT_PTX_LDG_G_v4i8_ELE_ari32  = 1207,
1223
    INT_PTX_LDG_G_v4i8_ELE_ari64  = 1208,
1224
    INT_PTX_LDG_G_v4i8_ELE_avar = 1209,
1225
    INT_PTX_LDU_GLOBAL_f16areg  = 1210,
1226
    INT_PTX_LDU_GLOBAL_f16areg64  = 1211,
1227
    INT_PTX_LDU_GLOBAL_f16ari = 1212,
1228
    INT_PTX_LDU_GLOBAL_f16ari64 = 1213,
1229
    INT_PTX_LDU_GLOBAL_f16avar  = 1214,
1230
    INT_PTX_LDU_GLOBAL_f16x2areg  = 1215,
1231
    INT_PTX_LDU_GLOBAL_f16x2areg64  = 1216,
1232
    INT_PTX_LDU_GLOBAL_f16x2ari = 1217,
1233
    INT_PTX_LDU_GLOBAL_f16x2ari64 = 1218,
1234
    INT_PTX_LDU_GLOBAL_f16x2avar  = 1219,
1235
    INT_PTX_LDU_GLOBAL_f32areg  = 1220,
1236
    INT_PTX_LDU_GLOBAL_f32areg64  = 1221,
1237
    INT_PTX_LDU_GLOBAL_f32ari = 1222,
1238
    INT_PTX_LDU_GLOBAL_f32ari64 = 1223,
1239
    INT_PTX_LDU_GLOBAL_f32avar  = 1224,
1240
    INT_PTX_LDU_GLOBAL_f64areg  = 1225,
1241
    INT_PTX_LDU_GLOBAL_f64areg64  = 1226,
1242
    INT_PTX_LDU_GLOBAL_f64ari = 1227,
1243
    INT_PTX_LDU_GLOBAL_f64ari64 = 1228,
1244
    INT_PTX_LDU_GLOBAL_f64avar  = 1229,
1245
    INT_PTX_LDU_GLOBAL_i16areg  = 1230,
1246
    INT_PTX_LDU_GLOBAL_i16areg64  = 1231,
1247
    INT_PTX_LDU_GLOBAL_i16ari = 1232,
1248
    INT_PTX_LDU_GLOBAL_i16ari64 = 1233,
1249
    INT_PTX_LDU_GLOBAL_i16avar  = 1234,
1250
    INT_PTX_LDU_GLOBAL_i32areg  = 1235,
1251
    INT_PTX_LDU_GLOBAL_i32areg64  = 1236,
1252
    INT_PTX_LDU_GLOBAL_i32ari = 1237,
1253
    INT_PTX_LDU_GLOBAL_i32ari64 = 1238,
1254
    INT_PTX_LDU_GLOBAL_i32avar  = 1239,
1255
    INT_PTX_LDU_GLOBAL_i64areg  = 1240,
1256
    INT_PTX_LDU_GLOBAL_i64areg64  = 1241,
1257
    INT_PTX_LDU_GLOBAL_i64ari = 1242,
1258
    INT_PTX_LDU_GLOBAL_i64ari64 = 1243,
1259
    INT_PTX_LDU_GLOBAL_i64avar  = 1244,
1260
    INT_PTX_LDU_GLOBAL_i8areg = 1245,
1261
    INT_PTX_LDU_GLOBAL_i8areg64 = 1246,
1262
    INT_PTX_LDU_GLOBAL_i8ari  = 1247,
1263
    INT_PTX_LDU_GLOBAL_i8ari64  = 1248,
1264
    INT_PTX_LDU_GLOBAL_i8avar = 1249,
1265
    INT_PTX_LDU_GLOBAL_p32areg  = 1250,
1266
    INT_PTX_LDU_GLOBAL_p32areg64  = 1251,
1267
    INT_PTX_LDU_GLOBAL_p32ari = 1252,
1268
    INT_PTX_LDU_GLOBAL_p32ari64 = 1253,
1269
    INT_PTX_LDU_GLOBAL_p32avar  = 1254,
1270
    INT_PTX_LDU_GLOBAL_p64areg  = 1255,
1271
    INT_PTX_LDU_GLOBAL_p64areg64  = 1256,
1272
    INT_PTX_LDU_GLOBAL_p64ari = 1257,
1273
    INT_PTX_LDU_GLOBAL_p64ari64 = 1258,
1274
    INT_PTX_LDU_GLOBAL_p64avar  = 1259,
1275
    INT_PTX_LDU_G_v2f16_ELE_areg32  = 1260,
1276
    INT_PTX_LDU_G_v2f16_ELE_areg64  = 1261,
1277
    INT_PTX_LDU_G_v2f16_ELE_ari32 = 1262,
1278
    INT_PTX_LDU_G_v2f16_ELE_ari64 = 1263,
1279
    INT_PTX_LDU_G_v2f16_ELE_avar  = 1264,
1280
    INT_PTX_LDU_G_v2f16x2_ELE_areg32  = 1265,
1281
    INT_PTX_LDU_G_v2f16x2_ELE_areg64  = 1266,
1282
    INT_PTX_LDU_G_v2f16x2_ELE_ari32 = 1267,
1283
    INT_PTX_LDU_G_v2f16x2_ELE_ari64 = 1268,
1284
    INT_PTX_LDU_G_v2f16x2_ELE_avar  = 1269,
1285
    INT_PTX_LDU_G_v2f32_ELE_areg32  = 1270,
1286
    INT_PTX_LDU_G_v2f32_ELE_areg64  = 1271,
1287
    INT_PTX_LDU_G_v2f32_ELE_ari32 = 1272,
1288
    INT_PTX_LDU_G_v2f32_ELE_ari64 = 1273,
1289
    INT_PTX_LDU_G_v2f32_ELE_avar  = 1274,
1290
    INT_PTX_LDU_G_v2f64_ELE_areg32  = 1275,
1291
    INT_PTX_LDU_G_v2f64_ELE_areg64  = 1276,
1292
    INT_PTX_LDU_G_v2f64_ELE_ari32 = 1277,
1293
    INT_PTX_LDU_G_v2f64_ELE_ari64 = 1278,
1294
    INT_PTX_LDU_G_v2f64_ELE_avar  = 1279,
1295
    INT_PTX_LDU_G_v2i16_ELE_areg32  = 1280,
1296
    INT_PTX_LDU_G_v2i16_ELE_areg64  = 1281,
1297
    INT_PTX_LDU_G_v2i16_ELE_ari32 = 1282,
1298
    INT_PTX_LDU_G_v2i16_ELE_ari64 = 1283,
1299
    INT_PTX_LDU_G_v2i16_ELE_avar  = 1284,
1300
    INT_PTX_LDU_G_v2i32_ELE_areg32  = 1285,
1301
    INT_PTX_LDU_G_v2i32_ELE_areg64  = 1286,
1302
    INT_PTX_LDU_G_v2i32_ELE_ari32 = 1287,
1303
    INT_PTX_LDU_G_v2i32_ELE_ari64 = 1288,
1304
    INT_PTX_LDU_G_v2i32_ELE_avar  = 1289,
1305
    INT_PTX_LDU_G_v2i64_ELE_areg32  = 1290,
1306
    INT_PTX_LDU_G_v2i64_ELE_areg64  = 1291,
1307
    INT_PTX_LDU_G_v2i64_ELE_ari32 = 1292,
1308
    INT_PTX_LDU_G_v2i64_ELE_ari64 = 1293,
1309
    INT_PTX_LDU_G_v2i64_ELE_avar  = 1294,
1310
    INT_PTX_LDU_G_v2i8_ELE_areg32 = 1295,
1311
    INT_PTX_LDU_G_v2i8_ELE_areg64 = 1296,
1312
    INT_PTX_LDU_G_v2i8_ELE_ari32  = 1297,
1313
    INT_PTX_LDU_G_v2i8_ELE_ari64  = 1298,
1314
    INT_PTX_LDU_G_v2i8_ELE_avar = 1299,
1315
    INT_PTX_LDU_G_v4f16_ELE_areg32  = 1300,
1316
    INT_PTX_LDU_G_v4f16_ELE_areg64  = 1301,
1317
    INT_PTX_LDU_G_v4f16_ELE_ari32 = 1302,
1318
    INT_PTX_LDU_G_v4f16_ELE_ari64 = 1303,
1319
    INT_PTX_LDU_G_v4f16_ELE_avar  = 1304,
1320
    INT_PTX_LDU_G_v4f16x2_ELE_areg32  = 1305,
1321
    INT_PTX_LDU_G_v4f16x2_ELE_areg64  = 1306,
1322
    INT_PTX_LDU_G_v4f16x2_ELE_ari32 = 1307,
1323
    INT_PTX_LDU_G_v4f16x2_ELE_ari64 = 1308,
1324
    INT_PTX_LDU_G_v4f16x2_ELE_avar  = 1309,
1325
    INT_PTX_LDU_G_v4f32_ELE_areg32  = 1310,
1326
    INT_PTX_LDU_G_v4f32_ELE_areg64  = 1311,
1327
    INT_PTX_LDU_G_v4f32_ELE_ari32 = 1312,
1328
    INT_PTX_LDU_G_v4f32_ELE_ari64 = 1313,
1329
    INT_PTX_LDU_G_v4f32_ELE_avar  = 1314,
1330
    INT_PTX_LDU_G_v4i16_ELE_areg32  = 1315,
1331
    INT_PTX_LDU_G_v4i16_ELE_areg64  = 1316,
1332
    INT_PTX_LDU_G_v4i16_ELE_ari32 = 1317,
1333
    INT_PTX_LDU_G_v4i16_ELE_ari64 = 1318,
1334
    INT_PTX_LDU_G_v4i16_ELE_avar  = 1319,
1335
    INT_PTX_LDU_G_v4i32_ELE_areg32  = 1320,
1336
    INT_PTX_LDU_G_v4i32_ELE_areg64  = 1321,
1337
    INT_PTX_LDU_G_v4i32_ELE_ari32 = 1322,
1338
    INT_PTX_LDU_G_v4i32_ELE_ari64 = 1323,
1339
    INT_PTX_LDU_G_v4i32_ELE_avar  = 1324,
1340
    INT_PTX_LDU_G_v4i8_ELE_areg32 = 1325,
1341
    INT_PTX_LDU_G_v4i8_ELE_areg64 = 1326,
1342
    INT_PTX_LDU_G_v4i8_ELE_ari32  = 1327,
1343
    INT_PTX_LDU_G_v4i8_ELE_ari64  = 1328,
1344
    INT_PTX_LDU_G_v4i8_ELE_avar = 1329,
1345
    INT_PTX_SREG_CLOCK  = 1330,
1346
    INT_PTX_SREG_CLOCK64  = 1331,
1347
    INT_PTX_SREG_CTAID_W  = 1332,
1348
    INT_PTX_SREG_CTAID_X  = 1333,
1349
    INT_PTX_SREG_CTAID_Y  = 1334,
1350
    INT_PTX_SREG_CTAID_Z  = 1335,
1351
    INT_PTX_SREG_GRIDID = 1336,
1352
    INT_PTX_SREG_LANEID = 1337,
1353
    INT_PTX_SREG_LANEMASK_EQ  = 1338,
1354
    INT_PTX_SREG_LANEMASK_GE  = 1339,
1355
    INT_PTX_SREG_LANEMASK_GT  = 1340,
1356
    INT_PTX_SREG_LANEMASK_LE  = 1341,
1357
    INT_PTX_SREG_LANEMASK_LT  = 1342,
1358
    INT_PTX_SREG_NCTAID_W = 1343,
1359
    INT_PTX_SREG_NCTAID_X = 1344,
1360
    INT_PTX_SREG_NCTAID_Y = 1345,
1361
    INT_PTX_SREG_NCTAID_Z = 1346,
1362
    INT_PTX_SREG_NSMID  = 1347,
1363
    INT_PTX_SREG_NTID_W = 1348,
1364
    INT_PTX_SREG_NTID_X = 1349,
1365
    INT_PTX_SREG_NTID_Y = 1350,
1366
    INT_PTX_SREG_NTID_Z = 1351,
1367
    INT_PTX_SREG_NWARPID  = 1352,
1368
    INT_PTX_SREG_PM0  = 1353,
1369
    INT_PTX_SREG_PM1  = 1354,
1370
    INT_PTX_SREG_PM2  = 1355,
1371
    INT_PTX_SREG_PM3  = 1356,
1372
    INT_PTX_SREG_SMID = 1357,
1373
    INT_PTX_SREG_TID_W  = 1358,
1374
    INT_PTX_SREG_TID_X  = 1359,
1375
    INT_PTX_SREG_TID_Y  = 1360,
1376
    INT_PTX_SREG_TID_Z  = 1361,
1377
    INT_PTX_SREG_WARPID = 1362,
1378
    INT_PTX_SREG_WARPSIZE = 1363,
1379
    INT_SHFL_BFLY_F32imm1 = 1364,
1380
    INT_SHFL_BFLY_F32imm2 = 1365,
1381
    INT_SHFL_BFLY_F32imm3 = 1366,
1382
    INT_SHFL_BFLY_F32reg  = 1367,
1383
    INT_SHFL_BFLY_I32imm1 = 1368,
1384
    INT_SHFL_BFLY_I32imm2 = 1369,
1385
    INT_SHFL_BFLY_I32imm3 = 1370,
1386
    INT_SHFL_BFLY_I32reg  = 1371,
1387
    INT_SHFL_DOWN_F32imm1 = 1372,
1388
    INT_SHFL_DOWN_F32imm2 = 1373,
1389
    INT_SHFL_DOWN_F32imm3 = 1374,
1390
    INT_SHFL_DOWN_F32reg  = 1375,
1391
    INT_SHFL_DOWN_I32imm1 = 1376,
1392
    INT_SHFL_DOWN_I32imm2 = 1377,
1393
    INT_SHFL_DOWN_I32imm3 = 1378,
1394
    INT_SHFL_DOWN_I32reg  = 1379,
1395
    INT_SHFL_IDX_F32imm1  = 1380,
1396
    INT_SHFL_IDX_F32imm2  = 1381,
1397
    INT_SHFL_IDX_F32imm3  = 1382,
1398
    INT_SHFL_IDX_F32reg = 1383,
1399
    INT_SHFL_IDX_I32imm1  = 1384,
1400
    INT_SHFL_IDX_I32imm2  = 1385,
1401
    INT_SHFL_IDX_I32imm3  = 1386,
1402
    INT_SHFL_IDX_I32reg = 1387,
1403
    INT_SHFL_SYNC_BFLY_F32iii = 1388,
1404
    INT_SHFL_SYNC_BFLY_F32iir = 1389,
1405
    INT_SHFL_SYNC_BFLY_F32iri = 1390,
1406
    INT_SHFL_SYNC_BFLY_F32irr = 1391,
1407
    INT_SHFL_SYNC_BFLY_F32rii = 1392,
1408
    INT_SHFL_SYNC_BFLY_F32rir = 1393,
1409
    INT_SHFL_SYNC_BFLY_F32rri = 1394,
1410
    INT_SHFL_SYNC_BFLY_F32rrr = 1395,
1411
    INT_SHFL_SYNC_BFLY_I32iii = 1396,
1412
    INT_SHFL_SYNC_BFLY_I32iir = 1397,
1413
    INT_SHFL_SYNC_BFLY_I32iri = 1398,
1414
    INT_SHFL_SYNC_BFLY_I32irr = 1399,
1415
    INT_SHFL_SYNC_BFLY_I32rii = 1400,
1416
    INT_SHFL_SYNC_BFLY_I32rir = 1401,
1417
    INT_SHFL_SYNC_BFLY_I32rri = 1402,
1418
    INT_SHFL_SYNC_BFLY_I32rrr = 1403,
1419
    INT_SHFL_SYNC_DOWN_F32iii = 1404,
1420
    INT_SHFL_SYNC_DOWN_F32iir = 1405,
1421
    INT_SHFL_SYNC_DOWN_F32iri = 1406,
1422
    INT_SHFL_SYNC_DOWN_F32irr = 1407,
1423
    INT_SHFL_SYNC_DOWN_F32rii = 1408,
1424
    INT_SHFL_SYNC_DOWN_F32rir = 1409,
1425
    INT_SHFL_SYNC_DOWN_F32rri = 1410,
1426
    INT_SHFL_SYNC_DOWN_F32rrr = 1411,
1427
    INT_SHFL_SYNC_DOWN_I32iii = 1412,
1428
    INT_SHFL_SYNC_DOWN_I32iir = 1413,
1429
    INT_SHFL_SYNC_DOWN_I32iri = 1414,
1430
    INT_SHFL_SYNC_DOWN_I32irr = 1415,
1431
    INT_SHFL_SYNC_DOWN_I32rii = 1416,
1432
    INT_SHFL_SYNC_DOWN_I32rir = 1417,
1433
    INT_SHFL_SYNC_DOWN_I32rri = 1418,
1434
    INT_SHFL_SYNC_DOWN_I32rrr = 1419,
1435
    INT_SHFL_SYNC_IDX_F32iii  = 1420,
1436
    INT_SHFL_SYNC_IDX_F32iir  = 1421,
1437
    INT_SHFL_SYNC_IDX_F32iri  = 1422,
1438
    INT_SHFL_SYNC_IDX_F32irr  = 1423,
1439
    INT_SHFL_SYNC_IDX_F32rii  = 1424,
1440
    INT_SHFL_SYNC_IDX_F32rir  = 1425,
1441
    INT_SHFL_SYNC_IDX_F32rri  = 1426,
1442
    INT_SHFL_SYNC_IDX_F32rrr  = 1427,
1443
    INT_SHFL_SYNC_IDX_I32iii  = 1428,
1444
    INT_SHFL_SYNC_IDX_I32iir  = 1429,
1445
    INT_SHFL_SYNC_IDX_I32iri  = 1430,
1446
    INT_SHFL_SYNC_IDX_I32irr  = 1431,
1447
    INT_SHFL_SYNC_IDX_I32rii  = 1432,
1448
    INT_SHFL_SYNC_IDX_I32rir  = 1433,
1449
    INT_SHFL_SYNC_IDX_I32rri  = 1434,
1450
    INT_SHFL_SYNC_IDX_I32rrr  = 1435,
1451
    INT_SHFL_SYNC_UP_F32iii = 1436,
1452
    INT_SHFL_SYNC_UP_F32iir = 1437,
1453
    INT_SHFL_SYNC_UP_F32iri = 1438,
1454
    INT_SHFL_SYNC_UP_F32irr = 1439,
1455
    INT_SHFL_SYNC_UP_F32rii = 1440,
1456
    INT_SHFL_SYNC_UP_F32rir = 1441,
1457
    INT_SHFL_SYNC_UP_F32rri = 1442,
1458
    INT_SHFL_SYNC_UP_F32rrr = 1443,
1459
    INT_SHFL_SYNC_UP_I32iii = 1444,
1460
    INT_SHFL_SYNC_UP_I32iir = 1445,
1461
    INT_SHFL_SYNC_UP_I32iri = 1446,
1462
    INT_SHFL_SYNC_UP_I32irr = 1447,
1463
    INT_SHFL_SYNC_UP_I32rii = 1448,
1464
    INT_SHFL_SYNC_UP_I32rir = 1449,
1465
    INT_SHFL_SYNC_UP_I32rri = 1450,
1466
    INT_SHFL_SYNC_UP_I32rrr = 1451,
1467
    INT_SHFL_UP_F32imm1 = 1452,
1468
    INT_SHFL_UP_F32imm2 = 1453,
1469
    INT_SHFL_UP_F32imm3 = 1454,
1470
    INT_SHFL_UP_F32reg  = 1455,
1471
    INT_SHFL_UP_I32imm1 = 1456,
1472
    INT_SHFL_UP_I32imm2 = 1457,
1473
    INT_SHFL_UP_I32imm3 = 1458,
1474
    INT_SHFL_UP_I32reg  = 1459,
1475
    INT_WMMA_MMA_m16n16k16_col_col_f16_f16  = 1460,
1476
    INT_WMMA_MMA_m16n16k16_col_col_f16_f16_satfinite  = 1461,
1477
    INT_WMMA_MMA_m16n16k16_col_col_f16_f32  = 1462,
1478
    INT_WMMA_MMA_m16n16k16_col_col_f16_f32_satfinite  = 1463,
1479
    INT_WMMA_MMA_m16n16k16_col_col_f32_f16  = 1464,
1480
    INT_WMMA_MMA_m16n16k16_col_col_f32_f16_satfinite  = 1465,
1481
    INT_WMMA_MMA_m16n16k16_col_col_f32_f32  = 1466,
1482
    INT_WMMA_MMA_m16n16k16_col_col_f32_f32_satfinite  = 1467,
1483
    INT_WMMA_MMA_m16n16k16_col_row_f16_f16  = 1468,
1484
    INT_WMMA_MMA_m16n16k16_col_row_f16_f16_satfinite  = 1469,
1485
    INT_WMMA_MMA_m16n16k16_col_row_f16_f32  = 1470,
1486
    INT_WMMA_MMA_m16n16k16_col_row_f16_f32_satfinite  = 1471,
1487
    INT_WMMA_MMA_m16n16k16_col_row_f32_f16  = 1472,
1488
    INT_WMMA_MMA_m16n16k16_col_row_f32_f16_satfinite  = 1473,
1489
    INT_WMMA_MMA_m16n16k16_col_row_f32_f32  = 1474,
1490
    INT_WMMA_MMA_m16n16k16_col_row_f32_f32_satfinite  = 1475,
1491
    INT_WMMA_MMA_m16n16k16_row_col_f16_f16  = 1476,
1492
    INT_WMMA_MMA_m16n16k16_row_col_f16_f16_satfinite  = 1477,
1493
    INT_WMMA_MMA_m16n16k16_row_col_f16_f32  = 1478,
1494
    INT_WMMA_MMA_m16n16k16_row_col_f16_f32_satfinite  = 1479,
1495
    INT_WMMA_MMA_m16n16k16_row_col_f32_f16  = 1480,
1496
    INT_WMMA_MMA_m16n16k16_row_col_f32_f16_satfinite  = 1481,
1497
    INT_WMMA_MMA_m16n16k16_row_col_f32_f32  = 1482,
1498
    INT_WMMA_MMA_m16n16k16_row_col_f32_f32_satfinite  = 1483,
1499
    INT_WMMA_MMA_m16n16k16_row_row_f16_f16  = 1484,
1500
    INT_WMMA_MMA_m16n16k16_row_row_f16_f16_satfinite  = 1485,
1501
    INT_WMMA_MMA_m16n16k16_row_row_f16_f32  = 1486,
1502
    INT_WMMA_MMA_m16n16k16_row_row_f16_f32_satfinite  = 1487,
1503
    INT_WMMA_MMA_m16n16k16_row_row_f32_f16  = 1488,
1504
    INT_WMMA_MMA_m16n16k16_row_row_f32_f16_satfinite  = 1489,
1505
    INT_WMMA_MMA_m16n16k16_row_row_f32_f32  = 1490,
1506
    INT_WMMA_MMA_m16n16k16_row_row_f32_f32_satfinite  = 1491,
1507
    INT_WMMA_MMA_m32n8k16_col_col_f16_f16 = 1492,
1508
    INT_WMMA_MMA_m32n8k16_col_col_f16_f16_satfinite = 1493,
1509
    INT_WMMA_MMA_m32n8k16_col_col_f16_f32 = 1494,
1510
    INT_WMMA_MMA_m32n8k16_col_col_f16_f32_satfinite = 1495,
1511
    INT_WMMA_MMA_m32n8k16_col_col_f32_f16 = 1496,
1512
    INT_WMMA_MMA_m32n8k16_col_col_f32_f16_satfinite = 1497,
1513
    INT_WMMA_MMA_m32n8k16_col_col_f32_f32 = 1498,
1514
    INT_WMMA_MMA_m32n8k16_col_col_f32_f32_satfinite = 1499,
1515
    INT_WMMA_MMA_m32n8k16_col_row_f16_f16 = 1500,
1516
    INT_WMMA_MMA_m32n8k16_col_row_f16_f16_satfinite = 1501,
1517
    INT_WMMA_MMA_m32n8k16_col_row_f16_f32 = 1502,
1518
    INT_WMMA_MMA_m32n8k16_col_row_f16_f32_satfinite = 1503,
1519
    INT_WMMA_MMA_m32n8k16_col_row_f32_f16 = 1504,
1520
    INT_WMMA_MMA_m32n8k16_col_row_f32_f16_satfinite = 1505,
1521
    INT_WMMA_MMA_m32n8k16_col_row_f32_f32 = 1506,
1522
    INT_WMMA_MMA_m32n8k16_col_row_f32_f32_satfinite = 1507,
1523
    INT_WMMA_MMA_m32n8k16_row_col_f16_f16 = 1508,
1524
    INT_WMMA_MMA_m32n8k16_row_col_f16_f16_satfinite = 1509,
1525
    INT_WMMA_MMA_m32n8k16_row_col_f16_f32 = 1510,
1526
    INT_WMMA_MMA_m32n8k16_row_col_f16_f32_satfinite = 1511,
1527
    INT_WMMA_MMA_m32n8k16_row_col_f32_f16 = 1512,
1528
    INT_WMMA_MMA_m32n8k16_row_col_f32_f16_satfinite = 1513,
1529
    INT_WMMA_MMA_m32n8k16_row_col_f32_f32 = 1514,
1530
    INT_WMMA_MMA_m32n8k16_row_col_f32_f32_satfinite = 1515,
1531
    INT_WMMA_MMA_m32n8k16_row_row_f16_f16 = 1516,
1532
    INT_WMMA_MMA_m32n8k16_row_row_f16_f16_satfinite = 1517,
1533
    INT_WMMA_MMA_m32n8k16_row_row_f16_f32 = 1518,
1534
    INT_WMMA_MMA_m32n8k16_row_row_f16_f32_satfinite = 1519,
1535
    INT_WMMA_MMA_m32n8k16_row_row_f32_f16 = 1520,
1536
    INT_WMMA_MMA_m32n8k16_row_row_f32_f16_satfinite = 1521,
1537
    INT_WMMA_MMA_m32n8k16_row_row_f32_f32 = 1522,
1538
    INT_WMMA_MMA_m32n8k16_row_row_f32_f32_satfinite = 1523,
1539
    INT_WMMA_MMA_m8n32k16_col_col_f16_f16 = 1524,
1540
    INT_WMMA_MMA_m8n32k16_col_col_f16_f16_satfinite = 1525,
1541
    INT_WMMA_MMA_m8n32k16_col_col_f16_f32 = 1526,
1542
    INT_WMMA_MMA_m8n32k16_col_col_f16_f32_satfinite = 1527,
1543
    INT_WMMA_MMA_m8n32k16_col_col_f32_f16 = 1528,
1544
    INT_WMMA_MMA_m8n32k16_col_col_f32_f16_satfinite = 1529,
1545
    INT_WMMA_MMA_m8n32k16_col_col_f32_f32 = 1530,
1546
    INT_WMMA_MMA_m8n32k16_col_col_f32_f32_satfinite = 1531,
1547
    INT_WMMA_MMA_m8n32k16_col_row_f16_f16 = 1532,
1548
    INT_WMMA_MMA_m8n32k16_col_row_f16_f16_satfinite = 1533,
1549
    INT_WMMA_MMA_m8n32k16_col_row_f16_f32 = 1534,
1550
    INT_WMMA_MMA_m8n32k16_col_row_f16_f32_satfinite = 1535,
1551
    INT_WMMA_MMA_m8n32k16_col_row_f32_f16 = 1536,
1552
    INT_WMMA_MMA_m8n32k16_col_row_f32_f16_satfinite = 1537,
1553
    INT_WMMA_MMA_m8n32k16_col_row_f32_f32 = 1538,
1554
    INT_WMMA_MMA_m8n32k16_col_row_f32_f32_satfinite = 1539,
1555
    INT_WMMA_MMA_m8n32k16_row_col_f16_f16 = 1540,
1556
    INT_WMMA_MMA_m8n32k16_row_col_f16_f16_satfinite = 1541,
1557
    INT_WMMA_MMA_m8n32k16_row_col_f16_f32 = 1542,
1558
    INT_WMMA_MMA_m8n32k16_row_col_f16_f32_satfinite = 1543,
1559
    INT_WMMA_MMA_m8n32k16_row_col_f32_f16 = 1544,
1560
    INT_WMMA_MMA_m8n32k16_row_col_f32_f16_satfinite = 1545,
1561
    INT_WMMA_MMA_m8n32k16_row_col_f32_f32 = 1546,
1562
    INT_WMMA_MMA_m8n32k16_row_col_f32_f32_satfinite = 1547,
1563
    INT_WMMA_MMA_m8n32k16_row_row_f16_f16 = 1548,
1564
    INT_WMMA_MMA_m8n32k16_row_row_f16_f16_satfinite = 1549,
1565
    INT_WMMA_MMA_m8n32k16_row_row_f16_f32 = 1550,
1566
    INT_WMMA_MMA_m8n32k16_row_row_f16_f32_satfinite = 1551,
1567
    INT_WMMA_MMA_m8n32k16_row_row_f32_f16 = 1552,
1568
    INT_WMMA_MMA_m8n32k16_row_row_f32_f16_satfinite = 1553,
1569
    INT_WMMA_MMA_m8n32k16_row_row_f32_f32 = 1554,
1570
    INT_WMMA_MMA_m8n32k16_row_row_f32_f32_satfinite = 1555,
1571
    INT_WMMA_m16n16k16_load_a_col_areg  = 1556,
1572
    INT_WMMA_m16n16k16_load_a_col_areg64  = 1557,
1573
    INT_WMMA_m16n16k16_load_a_col_ari = 1558,
1574
    INT_WMMA_m16n16k16_load_a_col_ari64 = 1559,
1575
    INT_WMMA_m16n16k16_load_a_col_avar  = 1560,
1576
    INT_WMMA_m16n16k16_load_a_col_global_areg = 1561,
1577
    INT_WMMA_m16n16k16_load_a_col_global_areg64 = 1562,
1578
    INT_WMMA_m16n16k16_load_a_col_global_ari  = 1563,
1579
    INT_WMMA_m16n16k16_load_a_col_global_ari64  = 1564,
1580
    INT_WMMA_m16n16k16_load_a_col_global_avar = 1565,
1581
    INT_WMMA_m16n16k16_load_a_col_global_stride_areg  = 1566,
1582
    INT_WMMA_m16n16k16_load_a_col_global_stride_areg64  = 1567,
1583
    INT_WMMA_m16n16k16_load_a_col_global_stride_ari = 1568,
1584
    INT_WMMA_m16n16k16_load_a_col_global_stride_ari64 = 1569,
1585
    INT_WMMA_m16n16k16_load_a_col_global_stride_avar  = 1570,
1586
    INT_WMMA_m16n16k16_load_a_col_shared_areg = 1571,
1587
    INT_WMMA_m16n16k16_load_a_col_shared_areg64 = 1572,
1588
    INT_WMMA_m16n16k16_load_a_col_shared_ari  = 1573,
1589
    INT_WMMA_m16n16k16_load_a_col_shared_ari64  = 1574,
1590
    INT_WMMA_m16n16k16_load_a_col_shared_avar = 1575,
1591
    INT_WMMA_m16n16k16_load_a_col_shared_stride_areg  = 1576,
1592
    INT_WMMA_m16n16k16_load_a_col_shared_stride_areg64  = 1577,
1593
    INT_WMMA_m16n16k16_load_a_col_shared_stride_ari = 1578,
1594
    INT_WMMA_m16n16k16_load_a_col_shared_stride_ari64 = 1579,
1595
    INT_WMMA_m16n16k16_load_a_col_shared_stride_avar  = 1580,
1596
    INT_WMMA_m16n16k16_load_a_col_stride_areg = 1581,
1597
    INT_WMMA_m16n16k16_load_a_col_stride_areg64 = 1582,
1598
    INT_WMMA_m16n16k16_load_a_col_stride_ari  = 1583,
1599
    INT_WMMA_m16n16k16_load_a_col_stride_ari64  = 1584,
1600
    INT_WMMA_m16n16k16_load_a_col_stride_avar = 1585,
1601
    INT_WMMA_m16n16k16_load_a_row_areg  = 1586,
1602
    INT_WMMA_m16n16k16_load_a_row_areg64  = 1587,
1603
    INT_WMMA_m16n16k16_load_a_row_ari = 1588,
1604
    INT_WMMA_m16n16k16_load_a_row_ari64 = 1589,
1605
    INT_WMMA_m16n16k16_load_a_row_avar  = 1590,
1606
    INT_WMMA_m16n16k16_load_a_row_global_areg = 1591,
1607
    INT_WMMA_m16n16k16_load_a_row_global_areg64 = 1592,
1608
    INT_WMMA_m16n16k16_load_a_row_global_ari  = 1593,
1609
    INT_WMMA_m16n16k16_load_a_row_global_ari64  = 1594,
1610
    INT_WMMA_m16n16k16_load_a_row_global_avar = 1595,
1611
    INT_WMMA_m16n16k16_load_a_row_global_stride_areg  = 1596,
1612
    INT_WMMA_m16n16k16_load_a_row_global_stride_areg64  = 1597,
1613
    INT_WMMA_m16n16k16_load_a_row_global_stride_ari = 1598,
1614
    INT_WMMA_m16n16k16_load_a_row_global_stride_ari64 = 1599,
1615
    INT_WMMA_m16n16k16_load_a_row_global_stride_avar  = 1600,
1616
    INT_WMMA_m16n16k16_load_a_row_shared_areg = 1601,
1617
    INT_WMMA_m16n16k16_load_a_row_shared_areg64 = 1602,
1618
    INT_WMMA_m16n16k16_load_a_row_shared_ari  = 1603,
1619
    INT_WMMA_m16n16k16_load_a_row_shared_ari64  = 1604,
1620
    INT_WMMA_m16n16k16_load_a_row_shared_avar = 1605,
1621
    INT_WMMA_m16n16k16_load_a_row_shared_stride_areg  = 1606,
1622
    INT_WMMA_m16n16k16_load_a_row_shared_stride_areg64  = 1607,
1623
    INT_WMMA_m16n16k16_load_a_row_shared_stride_ari = 1608,
1624
    INT_WMMA_m16n16k16_load_a_row_shared_stride_ari64 = 1609,
1625
    INT_WMMA_m16n16k16_load_a_row_shared_stride_avar  = 1610,
1626
    INT_WMMA_m16n16k16_load_a_row_stride_areg = 1611,
1627
    INT_WMMA_m16n16k16_load_a_row_stride_areg64 = 1612,
1628
    INT_WMMA_m16n16k16_load_a_row_stride_ari  = 1613,
1629
    INT_WMMA_m16n16k16_load_a_row_stride_ari64  = 1614,
1630
    INT_WMMA_m16n16k16_load_a_row_stride_avar = 1615,
1631
    INT_WMMA_m16n16k16_load_b_col_areg  = 1616,
1632
    INT_WMMA_m16n16k16_load_b_col_areg64  = 1617,
1633
    INT_WMMA_m16n16k16_load_b_col_ari = 1618,
1634
    INT_WMMA_m16n16k16_load_b_col_ari64 = 1619,
1635
    INT_WMMA_m16n16k16_load_b_col_avar  = 1620,
1636
    INT_WMMA_m16n16k16_load_b_col_global_areg = 1621,
1637
    INT_WMMA_m16n16k16_load_b_col_global_areg64 = 1622,
1638
    INT_WMMA_m16n16k16_load_b_col_global_ari  = 1623,
1639
    INT_WMMA_m16n16k16_load_b_col_global_ari64  = 1624,
1640
    INT_WMMA_m16n16k16_load_b_col_global_avar = 1625,
1641
    INT_WMMA_m16n16k16_load_b_col_global_stride_areg  = 1626,
1642
    INT_WMMA_m16n16k16_load_b_col_global_stride_areg64  = 1627,
1643
    INT_WMMA_m16n16k16_load_b_col_global_stride_ari = 1628,
1644
    INT_WMMA_m16n16k16_load_b_col_global_stride_ari64 = 1629,
1645
    INT_WMMA_m16n16k16_load_b_col_global_stride_avar  = 1630,
1646
    INT_WMMA_m16n16k16_load_b_col_shared_areg = 1631,
1647
    INT_WMMA_m16n16k16_load_b_col_shared_areg64 = 1632,
1648
    INT_WMMA_m16n16k16_load_b_col_shared_ari  = 1633,
1649
    INT_WMMA_m16n16k16_load_b_col_shared_ari64  = 1634,
1650
    INT_WMMA_m16n16k16_load_b_col_shared_avar = 1635,
1651
    INT_WMMA_m16n16k16_load_b_col_shared_stride_areg  = 1636,
1652
    INT_WMMA_m16n16k16_load_b_col_shared_stride_areg64  = 1637,
1653
    INT_WMMA_m16n16k16_load_b_col_shared_stride_ari = 1638,
1654
    INT_WMMA_m16n16k16_load_b_col_shared_stride_ari64 = 1639,
1655
    INT_WMMA_m16n16k16_load_b_col_shared_stride_avar  = 1640,
1656
    INT_WMMA_m16n16k16_load_b_col_stride_areg = 1641,
1657
    INT_WMMA_m16n16k16_load_b_col_stride_areg64 = 1642,
1658
    INT_WMMA_m16n16k16_load_b_col_stride_ari  = 1643,
1659
    INT_WMMA_m16n16k16_load_b_col_stride_ari64  = 1644,
1660
    INT_WMMA_m16n16k16_load_b_col_stride_avar = 1645,
1661
    INT_WMMA_m16n16k16_load_b_row_areg  = 1646,
1662
    INT_WMMA_m16n16k16_load_b_row_areg64  = 1647,
1663
    INT_WMMA_m16n16k16_load_b_row_ari = 1648,
1664
    INT_WMMA_m16n16k16_load_b_row_ari64 = 1649,
1665
    INT_WMMA_m16n16k16_load_b_row_avar  = 1650,
1666
    INT_WMMA_m16n16k16_load_b_row_global_areg = 1651,
1667
    INT_WMMA_m16n16k16_load_b_row_global_areg64 = 1652,
1668
    INT_WMMA_m16n16k16_load_b_row_global_ari  = 1653,
1669
    INT_WMMA_m16n16k16_load_b_row_global_ari64  = 1654,
1670
    INT_WMMA_m16n16k16_load_b_row_global_avar = 1655,
1671
    INT_WMMA_m16n16k16_load_b_row_global_stride_areg  = 1656,
1672
    INT_WMMA_m16n16k16_load_b_row_global_stride_areg64  = 1657,
1673
    INT_WMMA_m16n16k16_load_b_row_global_stride_ari = 1658,
1674
    INT_WMMA_m16n16k16_load_b_row_global_stride_ari64 = 1659,
1675
    INT_WMMA_m16n16k16_load_b_row_global_stride_avar  = 1660,
1676
    INT_WMMA_m16n16k16_load_b_row_shared_areg = 1661,
1677
    INT_WMMA_m16n16k16_load_b_row_shared_areg64 = 1662,
1678
    INT_WMMA_m16n16k16_load_b_row_shared_ari  = 1663,
1679
    INT_WMMA_m16n16k16_load_b_row_shared_ari64  = 1664,
1680
    INT_WMMA_m16n16k16_load_b_row_shared_avar = 1665,
1681
    INT_WMMA_m16n16k16_load_b_row_shared_stride_areg  = 1666,
1682
    INT_WMMA_m16n16k16_load_b_row_shared_stride_areg64  = 1667,
1683
    INT_WMMA_m16n16k16_load_b_row_shared_stride_ari = 1668,
1684
    INT_WMMA_m16n16k16_load_b_row_shared_stride_ari64 = 1669,
1685
    INT_WMMA_m16n16k16_load_b_row_shared_stride_avar  = 1670,
1686
    INT_WMMA_m16n16k16_load_b_row_stride_areg = 1671,
1687
    INT_WMMA_m16n16k16_load_b_row_stride_areg64 = 1672,
1688
    INT_WMMA_m16n16k16_load_b_row_stride_ari  = 1673,
1689
    INT_WMMA_m16n16k16_load_b_row_stride_ari64  = 1674,
1690
    INT_WMMA_m16n16k16_load_b_row_stride_avar = 1675,
1691
    INT_WMMA_m16n16k16_load_c_f16_col_areg  = 1676,
1692
    INT_WMMA_m16n16k16_load_c_f16_col_areg64  = 1677,
1693
    INT_WMMA_m16n16k16_load_c_f16_col_ari = 1678,
1694
    INT_WMMA_m16n16k16_load_c_f16_col_ari64 = 1679,
1695
    INT_WMMA_m16n16k16_load_c_f16_col_avar  = 1680,
1696
    INT_WMMA_m16n16k16_load_c_f16_col_global_areg = 1681,
1697
    INT_WMMA_m16n16k16_load_c_f16_col_global_areg64 = 1682,
1698
    INT_WMMA_m16n16k16_load_c_f16_col_global_ari  = 1683,
1699
    INT_WMMA_m16n16k16_load_c_f16_col_global_ari64  = 1684,
1700
    INT_WMMA_m16n16k16_load_c_f16_col_global_avar = 1685,
1701
    INT_WMMA_m16n16k16_load_c_f16_col_global_stride_areg  = 1686,
1702
    INT_WMMA_m16n16k16_load_c_f16_col_global_stride_areg64  = 1687,
1703
    INT_WMMA_m16n16k16_load_c_f16_col_global_stride_ari = 1688,
1704
    INT_WMMA_m16n16k16_load_c_f16_col_global_stride_ari64 = 1689,
1705
    INT_WMMA_m16n16k16_load_c_f16_col_global_stride_avar  = 1690,
1706
    INT_WMMA_m16n16k16_load_c_f16_col_shared_areg = 1691,
1707
    INT_WMMA_m16n16k16_load_c_f16_col_shared_areg64 = 1692,
1708
    INT_WMMA_m16n16k16_load_c_f16_col_shared_ari  = 1693,
1709
    INT_WMMA_m16n16k16_load_c_f16_col_shared_ari64  = 1694,
1710
    INT_WMMA_m16n16k16_load_c_f16_col_shared_avar = 1695,
1711
    INT_WMMA_m16n16k16_load_c_f16_col_shared_stride_areg  = 1696,
1712
    INT_WMMA_m16n16k16_load_c_f16_col_shared_stride_areg64  = 1697,
1713
    INT_WMMA_m16n16k16_load_c_f16_col_shared_stride_ari = 1698,
1714
    INT_WMMA_m16n16k16_load_c_f16_col_shared_stride_ari64 = 1699,
1715
    INT_WMMA_m16n16k16_load_c_f16_col_shared_stride_avar  = 1700,
1716
    INT_WMMA_m16n16k16_load_c_f16_col_stride_areg = 1701,
1717
    INT_WMMA_m16n16k16_load_c_f16_col_stride_areg64 = 1702,
1718
    INT_WMMA_m16n16k16_load_c_f16_col_stride_ari  = 1703,
1719
    INT_WMMA_m16n16k16_load_c_f16_col_stride_ari64  = 1704,
1720
    INT_WMMA_m16n16k16_load_c_f16_col_stride_avar = 1705,
1721
    INT_WMMA_m16n16k16_load_c_f16_row_areg  = 1706,
1722
    INT_WMMA_m16n16k16_load_c_f16_row_areg64  = 1707,
1723
    INT_WMMA_m16n16k16_load_c_f16_row_ari = 1708,
1724
    INT_WMMA_m16n16k16_load_c_f16_row_ari64 = 1709,
1725
    INT_WMMA_m16n16k16_load_c_f16_row_avar  = 1710,
1726
    INT_WMMA_m16n16k16_load_c_f16_row_global_areg = 1711,
1727
    INT_WMMA_m16n16k16_load_c_f16_row_global_areg64 = 1712,
1728
    INT_WMMA_m16n16k16_load_c_f16_row_global_ari  = 1713,
1729
    INT_WMMA_m16n16k16_load_c_f16_row_global_ari64  = 1714,
1730
    INT_WMMA_m16n16k16_load_c_f16_row_global_avar = 1715,
1731
    INT_WMMA_m16n16k16_load_c_f16_row_global_stride_areg  = 1716,
1732
    INT_WMMA_m16n16k16_load_c_f16_row_global_stride_areg64  = 1717,
1733
    INT_WMMA_m16n16k16_load_c_f16_row_global_stride_ari = 1718,
1734
    INT_WMMA_m16n16k16_load_c_f16_row_global_stride_ari64 = 1719,
1735
    INT_WMMA_m16n16k16_load_c_f16_row_global_stride_avar  = 1720,
1736
    INT_WMMA_m16n16k16_load_c_f16_row_shared_areg = 1721,
1737
    INT_WMMA_m16n16k16_load_c_f16_row_shared_areg64 = 1722,
1738
    INT_WMMA_m16n16k16_load_c_f16_row_shared_ari  = 1723,
1739
    INT_WMMA_m16n16k16_load_c_f16_row_shared_ari64  = 1724,
1740
    INT_WMMA_m16n16k16_load_c_f16_row_shared_avar = 1725,
1741
    INT_WMMA_m16n16k16_load_c_f16_row_shared_stride_areg  = 1726,
1742
    INT_WMMA_m16n16k16_load_c_f16_row_shared_stride_areg64  = 1727,
1743
    INT_WMMA_m16n16k16_load_c_f16_row_shared_stride_ari = 1728,
1744
    INT_WMMA_m16n16k16_load_c_f16_row_shared_stride_ari64 = 1729,
1745
    INT_WMMA_m16n16k16_load_c_f16_row_shared_stride_avar  = 1730,
1746
    INT_WMMA_m16n16k16_load_c_f16_row_stride_areg = 1731,
1747
    INT_WMMA_m16n16k16_load_c_f16_row_stride_areg64 = 1732,
1748
    INT_WMMA_m16n16k16_load_c_f16_row_stride_ari  = 1733,
1749
    INT_WMMA_m16n16k16_load_c_f16_row_stride_ari64  = 1734,
1750
    INT_WMMA_m16n16k16_load_c_f16_row_stride_avar = 1735,
1751
    INT_WMMA_m16n16k16_load_c_f32_col_areg  = 1736,
1752
    INT_WMMA_m16n16k16_load_c_f32_col_areg64  = 1737,
1753
    INT_WMMA_m16n16k16_load_c_f32_col_ari = 1738,
1754
    INT_WMMA_m16n16k16_load_c_f32_col_ari64 = 1739,
1755
    INT_WMMA_m16n16k16_load_c_f32_col_avar  = 1740,
1756
    INT_WMMA_m16n16k16_load_c_f32_col_global_areg = 1741,
1757
    INT_WMMA_m16n16k16_load_c_f32_col_global_areg64 = 1742,
1758
    INT_WMMA_m16n16k16_load_c_f32_col_global_ari  = 1743,
1759
    INT_WMMA_m16n16k16_load_c_f32_col_global_ari64  = 1744,
1760
    INT_WMMA_m16n16k16_load_c_f32_col_global_avar = 1745,
1761
    INT_WMMA_m16n16k16_load_c_f32_col_global_stride_areg  = 1746,
1762
    INT_WMMA_m16n16k16_load_c_f32_col_global_stride_areg64  = 1747,
1763
    INT_WMMA_m16n16k16_load_c_f32_col_global_stride_ari = 1748,
1764
    INT_WMMA_m16n16k16_load_c_f32_col_global_stride_ari64 = 1749,
1765
    INT_WMMA_m16n16k16_load_c_f32_col_global_stride_avar  = 1750,
1766
    INT_WMMA_m16n16k16_load_c_f32_col_shared_areg = 1751,
1767
    INT_WMMA_m16n16k16_load_c_f32_col_shared_areg64 = 1752,
1768
    INT_WMMA_m16n16k16_load_c_f32_col_shared_ari  = 1753,
1769
    INT_WMMA_m16n16k16_load_c_f32_col_shared_ari64  = 1754,
1770
    INT_WMMA_m16n16k16_load_c_f32_col_shared_avar = 1755,
1771
    INT_WMMA_m16n16k16_load_c_f32_col_shared_stride_areg  = 1756,
1772
    INT_WMMA_m16n16k16_load_c_f32_col_shared_stride_areg64  = 1757,
1773
    INT_WMMA_m16n16k16_load_c_f32_col_shared_stride_ari = 1758,
1774
    INT_WMMA_m16n16k16_load_c_f32_col_shared_stride_ari64 = 1759,
1775
    INT_WMMA_m16n16k16_load_c_f32_col_shared_stride_avar  = 1760,
1776
    INT_WMMA_m16n16k16_load_c_f32_col_stride_areg = 1761,
1777
    INT_WMMA_m16n16k16_load_c_f32_col_stride_areg64 = 1762,
1778
    INT_WMMA_m16n16k16_load_c_f32_col_stride_ari  = 1763,
1779
    INT_WMMA_m16n16k16_load_c_f32_col_stride_ari64  = 1764,
1780
    INT_WMMA_m16n16k16_load_c_f32_col_stride_avar = 1765,
1781
    INT_WMMA_m16n16k16_load_c_f32_row_areg  = 1766,
1782
    INT_WMMA_m16n16k16_load_c_f32_row_areg64  = 1767,
1783
    INT_WMMA_m16n16k16_load_c_f32_row_ari = 1768,
1784
    INT_WMMA_m16n16k16_load_c_f32_row_ari64 = 1769,
1785
    INT_WMMA_m16n16k16_load_c_f32_row_avar  = 1770,
1786
    INT_WMMA_m16n16k16_load_c_f32_row_global_areg = 1771,
1787
    INT_WMMA_m16n16k16_load_c_f32_row_global_areg64 = 1772,
1788
    INT_WMMA_m16n16k16_load_c_f32_row_global_ari  = 1773,
1789
    INT_WMMA_m16n16k16_load_c_f32_row_global_ari64  = 1774,
1790
    INT_WMMA_m16n16k16_load_c_f32_row_global_avar = 1775,
1791
    INT_WMMA_m16n16k16_load_c_f32_row_global_stride_areg  = 1776,
1792
    INT_WMMA_m16n16k16_load_c_f32_row_global_stride_areg64  = 1777,
1793
    INT_WMMA_m16n16k16_load_c_f32_row_global_stride_ari = 1778,
1794
    INT_WMMA_m16n16k16_load_c_f32_row_global_stride_ari64 = 1779,
1795
    INT_WMMA_m16n16k16_load_c_f32_row_global_stride_avar  = 1780,
1796
    INT_WMMA_m16n16k16_load_c_f32_row_shared_areg = 1781,
1797
    INT_WMMA_m16n16k16_load_c_f32_row_shared_areg64 = 1782,
1798
    INT_WMMA_m16n16k16_load_c_f32_row_shared_ari  = 1783,
1799
    INT_WMMA_m16n16k16_load_c_f32_row_shared_ari64  = 1784,
1800
    INT_WMMA_m16n16k16_load_c_f32_row_shared_avar = 1785,
1801
    INT_WMMA_m16n16k16_load_c_f32_row_shared_stride_areg  = 1786,
1802
    INT_WMMA_m16n16k16_load_c_f32_row_shared_stride_areg64  = 1787,
1803
    INT_WMMA_m16n16k16_load_c_f32_row_shared_stride_ari = 1788,
1804
    INT_WMMA_m16n16k16_load_c_f32_row_shared_stride_ari64 = 1789,
1805
    INT_WMMA_m16n16k16_load_c_f32_row_shared_stride_avar  = 1790,
1806
    INT_WMMA_m16n16k16_load_c_f32_row_stride_areg = 1791,
1807
    INT_WMMA_m16n16k16_load_c_f32_row_stride_areg64 = 1792,
1808
    INT_WMMA_m16n16k16_load_c_f32_row_stride_ari  = 1793,
1809
    INT_WMMA_m16n16k16_load_c_f32_row_stride_ari64  = 1794,
1810
    INT_WMMA_m16n16k16_load_c_f32_row_stride_avar = 1795,
1811
    INT_WMMA_m16n16k16_store_d_f16_col_areg = 1796,
1812
    INT_WMMA_m16n16k16_store_d_f16_col_areg64 = 1797,
1813
    INT_WMMA_m16n16k16_store_d_f16_col_ari  = 1798,
1814
    INT_WMMA_m16n16k16_store_d_f16_col_ari64  = 1799,
1815
    INT_WMMA_m16n16k16_store_d_f16_col_avar = 1800,
1816
    INT_WMMA_m16n16k16_store_d_f16_col_global_areg  = 1801,
1817
    INT_WMMA_m16n16k16_store_d_f16_col_global_areg64  = 1802,
1818
    INT_WMMA_m16n16k16_store_d_f16_col_global_ari = 1803,
1819
    INT_WMMA_m16n16k16_store_d_f16_col_global_ari64 = 1804,
1820
    INT_WMMA_m16n16k16_store_d_f16_col_global_avar  = 1805,
1821
    INT_WMMA_m16n16k16_store_d_f16_col_global_stride_areg = 1806,
1822
    INT_WMMA_m16n16k16_store_d_f16_col_global_stride_areg64 = 1807,
1823
    INT_WMMA_m16n16k16_store_d_f16_col_global_stride_ari  = 1808,
1824
    INT_WMMA_m16n16k16_store_d_f16_col_global_stride_ari64  = 1809,
1825
    INT_WMMA_m16n16k16_store_d_f16_col_global_stride_avar = 1810,
1826
    INT_WMMA_m16n16k16_store_d_f16_col_shared_areg  = 1811,
1827
    INT_WMMA_m16n16k16_store_d_f16_col_shared_areg64  = 1812,
1828
    INT_WMMA_m16n16k16_store_d_f16_col_shared_ari = 1813,
1829
    INT_WMMA_m16n16k16_store_d_f16_col_shared_ari64 = 1814,
1830
    INT_WMMA_m16n16k16_store_d_f16_col_shared_avar  = 1815,
1831
    INT_WMMA_m16n16k16_store_d_f16_col_shared_stride_areg = 1816,
1832
    INT_WMMA_m16n16k16_store_d_f16_col_shared_stride_areg64 = 1817,
1833
    INT_WMMA_m16n16k16_store_d_f16_col_shared_stride_ari  = 1818,
1834
    INT_WMMA_m16n16k16_store_d_f16_col_shared_stride_ari64  = 1819,
1835
    INT_WMMA_m16n16k16_store_d_f16_col_shared_stride_avar = 1820,
1836
    INT_WMMA_m16n16k16_store_d_f16_col_stride_areg  = 1821,
1837
    INT_WMMA_m16n16k16_store_d_f16_col_stride_areg64  = 1822,
1838
    INT_WMMA_m16n16k16_store_d_f16_col_stride_ari = 1823,
1839
    INT_WMMA_m16n16k16_store_d_f16_col_stride_ari64 = 1824,
1840
    INT_WMMA_m16n16k16_store_d_f16_col_stride_avar  = 1825,
1841
    INT_WMMA_m16n16k16_store_d_f16_row_areg = 1826,
1842
    INT_WMMA_m16n16k16_store_d_f16_row_areg64 = 1827,
1843
    INT_WMMA_m16n16k16_store_d_f16_row_ari  = 1828,
1844
    INT_WMMA_m16n16k16_store_d_f16_row_ari64  = 1829,
1845
    INT_WMMA_m16n16k16_store_d_f16_row_avar = 1830,
1846
    INT_WMMA_m16n16k16_store_d_f16_row_global_areg  = 1831,
1847
    INT_WMMA_m16n16k16_store_d_f16_row_global_areg64  = 1832,
1848
    INT_WMMA_m16n16k16_store_d_f16_row_global_ari = 1833,
1849
    INT_WMMA_m16n16k16_store_d_f16_row_global_ari64 = 1834,
1850
    INT_WMMA_m16n16k16_store_d_f16_row_global_avar  = 1835,
1851
    INT_WMMA_m16n16k16_store_d_f16_row_global_stride_areg = 1836,
1852
    INT_WMMA_m16n16k16_store_d_f16_row_global_stride_areg64 = 1837,
1853
    INT_WMMA_m16n16k16_store_d_f16_row_global_stride_ari  = 1838,
1854
    INT_WMMA_m16n16k16_store_d_f16_row_global_stride_ari64  = 1839,
1855
    INT_WMMA_m16n16k16_store_d_f16_row_global_stride_avar = 1840,
1856
    INT_WMMA_m16n16k16_store_d_f16_row_shared_areg  = 1841,
1857
    INT_WMMA_m16n16k16_store_d_f16_row_shared_areg64  = 1842,
1858
    INT_WMMA_m16n16k16_store_d_f16_row_shared_ari = 1843,
1859
    INT_WMMA_m16n16k16_store_d_f16_row_shared_ari64 = 1844,
1860
    INT_WMMA_m16n16k16_store_d_f16_row_shared_avar  = 1845,
1861
    INT_WMMA_m16n16k16_store_d_f16_row_shared_stride_areg = 1846,
1862
    INT_WMMA_m16n16k16_store_d_f16_row_shared_stride_areg64 = 1847,
1863
    INT_WMMA_m16n16k16_store_d_f16_row_shared_stride_ari  = 1848,
1864
    INT_WMMA_m16n16k16_store_d_f16_row_shared_stride_ari64  = 1849,
1865
    INT_WMMA_m16n16k16_store_d_f16_row_shared_stride_avar = 1850,
1866
    INT_WMMA_m16n16k16_store_d_f16_row_stride_areg  = 1851,
1867
    INT_WMMA_m16n16k16_store_d_f16_row_stride_areg64  = 1852,
1868
    INT_WMMA_m16n16k16_store_d_f16_row_stride_ari = 1853,
1869
    INT_WMMA_m16n16k16_store_d_f16_row_stride_ari64 = 1854,
1870
    INT_WMMA_m16n16k16_store_d_f16_row_stride_avar  = 1855,
1871
    INT_WMMA_m16n16k16_store_d_f32_col_areg = 1856,
1872
    INT_WMMA_m16n16k16_store_d_f32_col_areg64 = 1857,
1873
    INT_WMMA_m16n16k16_store_d_f32_col_ari  = 1858,
1874
    INT_WMMA_m16n16k16_store_d_f32_col_ari64  = 1859,
1875
    INT_WMMA_m16n16k16_store_d_f32_col_avar = 1860,
1876
    INT_WMMA_m16n16k16_store_d_f32_col_global_areg  = 1861,
1877
    INT_WMMA_m16n16k16_store_d_f32_col_global_areg64  = 1862,
1878
    INT_WMMA_m16n16k16_store_d_f32_col_global_ari = 1863,
1879
    INT_WMMA_m16n16k16_store_d_f32_col_global_ari64 = 1864,
1880
    INT_WMMA_m16n16k16_store_d_f32_col_global_avar  = 1865,
1881
    INT_WMMA_m16n16k16_store_d_f32_col_global_stride_areg = 1866,
1882
    INT_WMMA_m16n16k16_store_d_f32_col_global_stride_areg64 = 1867,
1883
    INT_WMMA_m16n16k16_store_d_f32_col_global_stride_ari  = 1868,
1884
    INT_WMMA_m16n16k16_store_d_f32_col_global_stride_ari64  = 1869,
1885
    INT_WMMA_m16n16k16_store_d_f32_col_global_stride_avar = 1870,
1886
    INT_WMMA_m16n16k16_store_d_f32_col_shared_areg  = 1871,
1887
    INT_WMMA_m16n16k16_store_d_f32_col_shared_areg64  = 1872,
1888
    INT_WMMA_m16n16k16_store_d_f32_col_shared_ari = 1873,
1889
    INT_WMMA_m16n16k16_store_d_f32_col_shared_ari64 = 1874,
1890
    INT_WMMA_m16n16k16_store_d_f32_col_shared_avar  = 1875,
1891
    INT_WMMA_m16n16k16_store_d_f32_col_shared_stride_areg = 1876,
1892
    INT_WMMA_m16n16k16_store_d_f32_col_shared_stride_areg64 = 1877,
1893
    INT_WMMA_m16n16k16_store_d_f32_col_shared_stride_ari  = 1878,
1894
    INT_WMMA_m16n16k16_store_d_f32_col_shared_stride_ari64  = 1879,
1895
    INT_WMMA_m16n16k16_store_d_f32_col_shared_stride_avar = 1880,
1896
    INT_WMMA_m16n16k16_store_d_f32_col_stride_areg  = 1881,
1897
    INT_WMMA_m16n16k16_store_d_f32_col_stride_areg64  = 1882,
1898
    INT_WMMA_m16n16k16_store_d_f32_col_stride_ari = 1883,
1899
    INT_WMMA_m16n16k16_store_d_f32_col_stride_ari64 = 1884,
1900
    INT_WMMA_m16n16k16_store_d_f32_col_stride_avar  = 1885,
1901
    INT_WMMA_m16n16k16_store_d_f32_row_areg = 1886,
1902
    INT_WMMA_m16n16k16_store_d_f32_row_areg64 = 1887,
1903
    INT_WMMA_m16n16k16_store_d_f32_row_ari  = 1888,
1904
    INT_WMMA_m16n16k16_store_d_f32_row_ari64  = 1889,
1905
    INT_WMMA_m16n16k16_store_d_f32_row_avar = 1890,
1906
    INT_WMMA_m16n16k16_store_d_f32_row_global_areg  = 1891,
1907
    INT_WMMA_m16n16k16_store_d_f32_row_global_areg64  = 1892,
1908
    INT_WMMA_m16n16k16_store_d_f32_row_global_ari = 1893,
1909
    INT_WMMA_m16n16k16_store_d_f32_row_global_ari64 = 1894,
1910
    INT_WMMA_m16n16k16_store_d_f32_row_global_avar  = 1895,
1911
    INT_WMMA_m16n16k16_store_d_f32_row_global_stride_areg = 1896,
1912
    INT_WMMA_m16n16k16_store_d_f32_row_global_stride_areg64 = 1897,
1913
    INT_WMMA_m16n16k16_store_d_f32_row_global_stride_ari  = 1898,
1914
    INT_WMMA_m16n16k16_store_d_f32_row_global_stride_ari64  = 1899,
1915
    INT_WMMA_m16n16k16_store_d_f32_row_global_stride_avar = 1900,
1916
    INT_WMMA_m16n16k16_store_d_f32_row_shared_areg  = 1901,
1917
    INT_WMMA_m16n16k16_store_d_f32_row_shared_areg64  = 1902,
1918
    INT_WMMA_m16n16k16_store_d_f32_row_shared_ari = 1903,
1919
    INT_WMMA_m16n16k16_store_d_f32_row_shared_ari64 = 1904,
1920
    INT_WMMA_m16n16k16_store_d_f32_row_shared_avar  = 1905,
1921
    INT_WMMA_m16n16k16_store_d_f32_row_shared_stride_areg = 1906,
1922
    INT_WMMA_m16n16k16_store_d_f32_row_shared_stride_areg64 = 1907,
1923
    INT_WMMA_m16n16k16_store_d_f32_row_shared_stride_ari  = 1908,
1924
    INT_WMMA_m16n16k16_store_d_f32_row_shared_stride_ari64  = 1909,
1925
    INT_WMMA_m16n16k16_store_d_f32_row_shared_stride_avar = 1910,
1926
    INT_WMMA_m16n16k16_store_d_f32_row_stride_areg  = 1911,
1927
    INT_WMMA_m16n16k16_store_d_f32_row_stride_areg64  = 1912,
1928
    INT_WMMA_m16n16k16_store_d_f32_row_stride_ari = 1913,
1929
    INT_WMMA_m16n16k16_store_d_f32_row_stride_ari64 = 1914,
1930
    INT_WMMA_m16n16k16_store_d_f32_row_stride_avar  = 1915,
1931
    INT_WMMA_m32n8k16_load_a_col_areg = 1916,
1932
    INT_WMMA_m32n8k16_load_a_col_areg64 = 1917,
1933
    INT_WMMA_m32n8k16_load_a_col_ari  = 1918,
1934
    INT_WMMA_m32n8k16_load_a_col_ari64  = 1919,
1935
    INT_WMMA_m32n8k16_load_a_col_avar = 1920,
1936
    INT_WMMA_m32n8k16_load_a_col_global_areg  = 1921,
1937
    INT_WMMA_m32n8k16_load_a_col_global_areg64  = 1922,
1938
    INT_WMMA_m32n8k16_load_a_col_global_ari = 1923,
1939
    INT_WMMA_m32n8k16_load_a_col_global_ari64 = 1924,
1940
    INT_WMMA_m32n8k16_load_a_col_global_avar  = 1925,
1941
    INT_WMMA_m32n8k16_load_a_col_global_stride_areg = 1926,
1942
    INT_WMMA_m32n8k16_load_a_col_global_stride_areg64 = 1927,
1943
    INT_WMMA_m32n8k16_load_a_col_global_stride_ari  = 1928,
1944
    INT_WMMA_m32n8k16_load_a_col_global_stride_ari64  = 1929,
1945
    INT_WMMA_m32n8k16_load_a_col_global_stride_avar = 1930,
1946
    INT_WMMA_m32n8k16_load_a_col_shared_areg  = 1931,
1947
    INT_WMMA_m32n8k16_load_a_col_shared_areg64  = 1932,
1948
    INT_WMMA_m32n8k16_load_a_col_shared_ari = 1933,
1949
    INT_WMMA_m32n8k16_load_a_col_shared_ari64 = 1934,
1950
    INT_WMMA_m32n8k16_load_a_col_shared_avar  = 1935,
1951
    INT_WMMA_m32n8k16_load_a_col_shared_stride_areg = 1936,
1952
    INT_WMMA_m32n8k16_load_a_col_shared_stride_areg64 = 1937,
1953
    INT_WMMA_m32n8k16_load_a_col_shared_stride_ari  = 1938,
1954
    INT_WMMA_m32n8k16_load_a_col_shared_stride_ari64  = 1939,
1955
    INT_WMMA_m32n8k16_load_a_col_shared_stride_avar = 1940,
1956
    INT_WMMA_m32n8k16_load_a_col_stride_areg  = 1941,
1957
    INT_WMMA_m32n8k16_load_a_col_stride_areg64  = 1942,
1958
    INT_WMMA_m32n8k16_load_a_col_stride_ari = 1943,
1959
    INT_WMMA_m32n8k16_load_a_col_stride_ari64 = 1944,
1960
    INT_WMMA_m32n8k16_load_a_col_stride_avar  = 1945,
1961
    INT_WMMA_m32n8k16_load_a_row_areg = 1946,
1962
    INT_WMMA_m32n8k16_load_a_row_areg64 = 1947,
1963
    INT_WMMA_m32n8k16_load_a_row_ari  = 1948,
1964
    INT_WMMA_m32n8k16_load_a_row_ari64  = 1949,
1965
    INT_WMMA_m32n8k16_load_a_row_avar = 1950,
1966
    INT_WMMA_m32n8k16_load_a_row_global_areg  = 1951,
1967
    INT_WMMA_m32n8k16_load_a_row_global_areg64  = 1952,
1968
    INT_WMMA_m32n8k16_load_a_row_global_ari = 1953,
1969
    INT_WMMA_m32n8k16_load_a_row_global_ari64 = 1954,
1970
    INT_WMMA_m32n8k16_load_a_row_global_avar  = 1955,
1971
    INT_WMMA_m32n8k16_load_a_row_global_stride_areg = 1956,
1972
    INT_WMMA_m32n8k16_load_a_row_global_stride_areg64 = 1957,
1973
    INT_WMMA_m32n8k16_load_a_row_global_stride_ari  = 1958,
1974
    INT_WMMA_m32n8k16_load_a_row_global_stride_ari64  = 1959,
1975
    INT_WMMA_m32n8k16_load_a_row_global_stride_avar = 1960,
1976
    INT_WMMA_m32n8k16_load_a_row_shared_areg  = 1961,
1977
    INT_WMMA_m32n8k16_load_a_row_shared_areg64  = 1962,
1978
    INT_WMMA_m32n8k16_load_a_row_shared_ari = 1963,
1979
    INT_WMMA_m32n8k16_load_a_row_shared_ari64 = 1964,
1980
    INT_WMMA_m32n8k16_load_a_row_shared_avar  = 1965,
1981
    INT_WMMA_m32n8k16_load_a_row_shared_stride_areg = 1966,
1982
    INT_WMMA_m32n8k16_load_a_row_shared_stride_areg64 = 1967,
1983
    INT_WMMA_m32n8k16_load_a_row_shared_stride_ari  = 1968,
1984
    INT_WMMA_m32n8k16_load_a_row_shared_stride_ari64  = 1969,
1985
    INT_WMMA_m32n8k16_load_a_row_shared_stride_avar = 1970,
1986
    INT_WMMA_m32n8k16_load_a_row_stride_areg  = 1971,
1987
    INT_WMMA_m32n8k16_load_a_row_stride_areg64  = 1972,
1988
    INT_WMMA_m32n8k16_load_a_row_stride_ari = 1973,
1989
    INT_WMMA_m32n8k16_load_a_row_stride_ari64 = 1974,
1990
    INT_WMMA_m32n8k16_load_a_row_stride_avar  = 1975,
1991
    INT_WMMA_m32n8k16_load_b_col_areg = 1976,
1992
    INT_WMMA_m32n8k16_load_b_col_areg64 = 1977,
1993
    INT_WMMA_m32n8k16_load_b_col_ari  = 1978,
1994
    INT_WMMA_m32n8k16_load_b_col_ari64  = 1979,
1995
    INT_WMMA_m32n8k16_load_b_col_avar = 1980,
1996
    INT_WMMA_m32n8k16_load_b_col_global_areg  = 1981,
1997
    INT_WMMA_m32n8k16_load_b_col_global_areg64  = 1982,
1998
    INT_WMMA_m32n8k16_load_b_col_global_ari = 1983,
1999
    INT_WMMA_m32n8k16_load_b_col_global_ari64 = 1984,
2000
    INT_WMMA_m32n8k16_load_b_col_global_avar  = 1985,
2001
    INT_WMMA_m32n8k16_load_b_col_global_stride_areg = 1986,
2002
    INT_WMMA_m32n8k16_load_b_col_global_stride_areg64 = 1987,
2003
    INT_WMMA_m32n8k16_load_b_col_global_stride_ari  = 1988,
2004
    INT_WMMA_m32n8k16_load_b_col_global_stride_ari64  = 1989,
2005
    INT_WMMA_m32n8k16_load_b_col_global_stride_avar = 1990,
2006
    INT_WMMA_m32n8k16_load_b_col_shared_areg  = 1991,
2007
    INT_WMMA_m32n8k16_load_b_col_shared_areg64  = 1992,
2008
    INT_WMMA_m32n8k16_load_b_col_shared_ari = 1993,
2009
    INT_WMMA_m32n8k16_load_b_col_shared_ari64 = 1994,
2010
    INT_WMMA_m32n8k16_load_b_col_shared_avar  = 1995,
2011
    INT_WMMA_m32n8k16_load_b_col_shared_stride_areg = 1996,
2012
    INT_WMMA_m32n8k16_load_b_col_shared_stride_areg64 = 1997,
2013
    INT_WMMA_m32n8k16_load_b_col_shared_stride_ari  = 1998,
2014
    INT_WMMA_m32n8k16_load_b_col_shared_stride_ari64  = 1999,
2015
    INT_WMMA_m32n8k16_load_b_col_shared_stride_avar = 2000,
2016
    INT_WMMA_m32n8k16_load_b_col_stride_areg  = 2001,
2017
    INT_WMMA_m32n8k16_load_b_col_stride_areg64  = 2002,
2018
    INT_WMMA_m32n8k16_load_b_col_stride_ari = 2003,
2019
    INT_WMMA_m32n8k16_load_b_col_stride_ari64 = 2004,
2020
    INT_WMMA_m32n8k16_load_b_col_stride_avar  = 2005,
2021
    INT_WMMA_m32n8k16_load_b_row_areg = 2006,
2022
    INT_WMMA_m32n8k16_load_b_row_areg64 = 2007,
2023
    INT_WMMA_m32n8k16_load_b_row_ari  = 2008,
2024
    INT_WMMA_m32n8k16_load_b_row_ari64  = 2009,
2025
    INT_WMMA_m32n8k16_load_b_row_avar = 2010,
2026
    INT_WMMA_m32n8k16_load_b_row_global_areg  = 2011,
2027
    INT_WMMA_m32n8k16_load_b_row_global_areg64  = 2012,
2028
    INT_WMMA_m32n8k16_load_b_row_global_ari = 2013,
2029
    INT_WMMA_m32n8k16_load_b_row_global_ari64 = 2014,
2030
    INT_WMMA_m32n8k16_load_b_row_global_avar  = 2015,
2031
    INT_WMMA_m32n8k16_load_b_row_global_stride_areg = 2016,
2032
    INT_WMMA_m32n8k16_load_b_row_global_stride_areg64 = 2017,
2033
    INT_WMMA_m32n8k16_load_b_row_global_stride_ari  = 2018,
2034
    INT_WMMA_m32n8k16_load_b_row_global_stride_ari64  = 2019,
2035
    INT_WMMA_m32n8k16_load_b_row_global_stride_avar = 2020,
2036
    INT_WMMA_m32n8k16_load_b_row_shared_areg  = 2021,
2037
    INT_WMMA_m32n8k16_load_b_row_shared_areg64  = 2022,
2038
    INT_WMMA_m32n8k16_load_b_row_shared_ari = 2023,
2039
    INT_WMMA_m32n8k16_load_b_row_shared_ari64 = 2024,
2040
    INT_WMMA_m32n8k16_load_b_row_shared_avar  = 2025,
2041
    INT_WMMA_m32n8k16_load_b_row_shared_stride_areg = 2026,
2042
    INT_WMMA_m32n8k16_load_b_row_shared_stride_areg64 = 2027,
2043
    INT_WMMA_m32n8k16_load_b_row_shared_stride_ari  = 2028,
2044
    INT_WMMA_m32n8k16_load_b_row_shared_stride_ari64  = 2029,
2045
    INT_WMMA_m32n8k16_load_b_row_shared_stride_avar = 2030,
2046
    INT_WMMA_m32n8k16_load_b_row_stride_areg  = 2031,
2047
    INT_WMMA_m32n8k16_load_b_row_stride_areg64  = 2032,
2048
    INT_WMMA_m32n8k16_load_b_row_stride_ari = 2033,
2049
    INT_WMMA_m32n8k16_load_b_row_stride_ari64 = 2034,
2050
    INT_WMMA_m32n8k16_load_b_row_stride_avar  = 2035,
2051
    INT_WMMA_m32n8k16_load_c_f16_col_areg = 2036,
2052
    INT_WMMA_m32n8k16_load_c_f16_col_areg64 = 2037,
2053
    INT_WMMA_m32n8k16_load_c_f16_col_ari  = 2038,
2054
    INT_WMMA_m32n8k16_load_c_f16_col_ari64  = 2039,
2055
    INT_WMMA_m32n8k16_load_c_f16_col_avar = 2040,
2056
    INT_WMMA_m32n8k16_load_c_f16_col_global_areg  = 2041,
2057
    INT_WMMA_m32n8k16_load_c_f16_col_global_areg64  = 2042,
2058
    INT_WMMA_m32n8k16_load_c_f16_col_global_ari = 2043,
2059
    INT_WMMA_m32n8k16_load_c_f16_col_global_ari64 = 2044,
2060
    INT_WMMA_m32n8k16_load_c_f16_col_global_avar  = 2045,
2061
    INT_WMMA_m32n8k16_load_c_f16_col_global_stride_areg = 2046,
2062
    INT_WMMA_m32n8k16_load_c_f16_col_global_stride_areg64 = 2047,
2063
    INT_WMMA_m32n8k16_load_c_f16_col_global_stride_ari  = 2048,
2064
    INT_WMMA_m32n8k16_load_c_f16_col_global_stride_ari64  = 2049,
2065
    INT_WMMA_m32n8k16_load_c_f16_col_global_stride_avar = 2050,
2066
    INT_WMMA_m32n8k16_load_c_f16_col_shared_areg  = 2051,
2067
    INT_WMMA_m32n8k16_load_c_f16_col_shared_areg64  = 2052,
2068
    INT_WMMA_m32n8k16_load_c_f16_col_shared_ari = 2053,
2069
    INT_WMMA_m32n8k16_load_c_f16_col_shared_ari64 = 2054,
2070
    INT_WMMA_m32n8k16_load_c_f16_col_shared_avar  = 2055,
2071
    INT_WMMA_m32n8k16_load_c_f16_col_shared_stride_areg = 2056,
2072
    INT_WMMA_m32n8k16_load_c_f16_col_shared_stride_areg64 = 2057,
2073
    INT_WMMA_m32n8k16_load_c_f16_col_shared_stride_ari  = 2058,
2074
    INT_WMMA_m32n8k16_load_c_f16_col_shared_stride_ari64  = 2059,
2075
    INT_WMMA_m32n8k16_load_c_f16_col_shared_stride_avar = 2060,
2076
    INT_WMMA_m32n8k16_load_c_f16_col_stride_areg  = 2061,
2077
    INT_WMMA_m32n8k16_load_c_f16_col_stride_areg64  = 2062,
2078
    INT_WMMA_m32n8k16_load_c_f16_col_stride_ari = 2063,
2079
    INT_WMMA_m32n8k16_load_c_f16_col_stride_ari64 = 2064,
2080
    INT_WMMA_m32n8k16_load_c_f16_col_stride_avar  = 2065,
2081
    INT_WMMA_m32n8k16_load_c_f16_row_areg = 2066,
2082
    INT_WMMA_m32n8k16_load_c_f16_row_areg64 = 2067,
2083
    INT_WMMA_m32n8k16_load_c_f16_row_ari  = 2068,
2084
    INT_WMMA_m32n8k16_load_c_f16_row_ari64  = 2069,
2085
    INT_WMMA_m32n8k16_load_c_f16_row_avar = 2070,
2086
    INT_WMMA_m32n8k16_load_c_f16_row_global_areg  = 2071,
2087
    INT_WMMA_m32n8k16_load_c_f16_row_global_areg64  = 2072,
2088
    INT_WMMA_m32n8k16_load_c_f16_row_global_ari = 2073,
2089
    INT_WMMA_m32n8k16_load_c_f16_row_global_ari64 = 2074,
2090
    INT_WMMA_m32n8k16_load_c_f16_row_global_avar  = 2075,
2091
    INT_WMMA_m32n8k16_load_c_f16_row_global_stride_areg = 2076,
2092
    INT_WMMA_m32n8k16_load_c_f16_row_global_stride_areg64 = 2077,
2093
    INT_WMMA_m32n8k16_load_c_f16_row_global_stride_ari  = 2078,
2094
    INT_WMMA_m32n8k16_load_c_f16_row_global_stride_ari64  = 2079,
2095
    INT_WMMA_m32n8k16_load_c_f16_row_global_stride_avar = 2080,
2096
    INT_WMMA_m32n8k16_load_c_f16_row_shared_areg  = 2081,
2097
    INT_WMMA_m32n8k16_load_c_f16_row_shared_areg64  = 2082,
2098
    INT_WMMA_m32n8k16_load_c_f16_row_shared_ari = 2083,
2099
    INT_WMMA_m32n8k16_load_c_f16_row_shared_ari64 = 2084,
2100
    INT_WMMA_m32n8k16_load_c_f16_row_shared_avar  = 2085,
2101
    INT_WMMA_m32n8k16_load_c_f16_row_shared_stride_areg = 2086,
2102
    INT_WMMA_m32n8k16_load_c_f16_row_shared_stride_areg64 = 2087,
2103
    INT_WMMA_m32n8k16_load_c_f16_row_shared_stride_ari  = 2088,
2104
    INT_WMMA_m32n8k16_load_c_f16_row_shared_stride_ari64  = 2089,
2105
    INT_WMMA_m32n8k16_load_c_f16_row_shared_stride_avar = 2090,
2106
    INT_WMMA_m32n8k16_load_c_f16_row_stride_areg  = 2091,
2107
    INT_WMMA_m32n8k16_load_c_f16_row_stride_areg64  = 2092,
2108
    INT_WMMA_m32n8k16_load_c_f16_row_stride_ari = 2093,
2109
    INT_WMMA_m32n8k16_load_c_f16_row_stride_ari64 = 2094,
2110
    INT_WMMA_m32n8k16_load_c_f16_row_stride_avar  = 2095,
2111
    INT_WMMA_m32n8k16_load_c_f32_col_areg = 2096,
2112
    INT_WMMA_m32n8k16_load_c_f32_col_areg64 = 2097,
2113
    INT_WMMA_m32n8k16_load_c_f32_col_ari  = 2098,
2114
    INT_WMMA_m32n8k16_load_c_f32_col_ari64  = 2099,
2115
    INT_WMMA_m32n8k16_load_c_f32_col_avar = 2100,
2116
    INT_WMMA_m32n8k16_load_c_f32_col_global_areg  = 2101,
2117
    INT_WMMA_m32n8k16_load_c_f32_col_global_areg64  = 2102,
2118
    INT_WMMA_m32n8k16_load_c_f32_col_global_ari = 2103,
2119
    INT_WMMA_m32n8k16_load_c_f32_col_global_ari64 = 2104,
2120
    INT_WMMA_m32n8k16_load_c_f32_col_global_avar  = 2105,
2121
    INT_WMMA_m32n8k16_load_c_f32_col_global_stride_areg = 2106,
2122
    INT_WMMA_m32n8k16_load_c_f32_col_global_stride_areg64 = 2107,
2123
    INT_WMMA_m32n8k16_load_c_f32_col_global_stride_ari  = 2108,
2124
    INT_WMMA_m32n8k16_load_c_f32_col_global_stride_ari64  = 2109,
2125
    INT_WMMA_m32n8k16_load_c_f32_col_global_stride_avar = 2110,
2126
    INT_WMMA_m32n8k16_load_c_f32_col_shared_areg  = 2111,
2127
    INT_WMMA_m32n8k16_load_c_f32_col_shared_areg64  = 2112,
2128
    INT_WMMA_m32n8k16_load_c_f32_col_shared_ari = 2113,
2129
    INT_WMMA_m32n8k16_load_c_f32_col_shared_ari64 = 2114,
2130
    INT_WMMA_m32n8k16_load_c_f32_col_shared_avar  = 2115,
2131
    INT_WMMA_m32n8k16_load_c_f32_col_shared_stride_areg = 2116,
2132
    INT_WMMA_m32n8k16_load_c_f32_col_shared_stride_areg64 = 2117,
2133
    INT_WMMA_m32n8k16_load_c_f32_col_shared_stride_ari  = 2118,
2134
    INT_WMMA_m32n8k16_load_c_f32_col_shared_stride_ari64  = 2119,
2135
    INT_WMMA_m32n8k16_load_c_f32_col_shared_stride_avar = 2120,
2136
    INT_WMMA_m32n8k16_load_c_f32_col_stride_areg  = 2121,
2137
    INT_WMMA_m32n8k16_load_c_f32_col_stride_areg64  = 2122,
2138
    INT_WMMA_m32n8k16_load_c_f32_col_stride_ari = 2123,
2139
    INT_WMMA_m32n8k16_load_c_f32_col_stride_ari64 = 2124,
2140
    INT_WMMA_m32n8k16_load_c_f32_col_stride_avar  = 2125,
2141
    INT_WMMA_m32n8k16_load_c_f32_row_areg = 2126,
2142
    INT_WMMA_m32n8k16_load_c_f32_row_areg64 = 2127,
2143
    INT_WMMA_m32n8k16_load_c_f32_row_ari  = 2128,
2144
    INT_WMMA_m32n8k16_load_c_f32_row_ari64  = 2129,
2145
    INT_WMMA_m32n8k16_load_c_f32_row_avar = 2130,
2146
    INT_WMMA_m32n8k16_load_c_f32_row_global_areg  = 2131,
2147
    INT_WMMA_m32n8k16_load_c_f32_row_global_areg64  = 2132,
2148
    INT_WMMA_m32n8k16_load_c_f32_row_global_ari = 2133,
2149
    INT_WMMA_m32n8k16_load_c_f32_row_global_ari64 = 2134,
2150
    INT_WMMA_m32n8k16_load_c_f32_row_global_avar  = 2135,
2151
    INT_WMMA_m32n8k16_load_c_f32_row_global_stride_areg = 2136,
2152
    INT_WMMA_m32n8k16_load_c_f32_row_global_stride_areg64 = 2137,
2153
    INT_WMMA_m32n8k16_load_c_f32_row_global_stride_ari  = 2138,
2154
    INT_WMMA_m32n8k16_load_c_f32_row_global_stride_ari64  = 2139,
2155
    INT_WMMA_m32n8k16_load_c_f32_row_global_stride_avar = 2140,
2156
    INT_WMMA_m32n8k16_load_c_f32_row_shared_areg  = 2141,
2157
    INT_WMMA_m32n8k16_load_c_f32_row_shared_areg64  = 2142,
2158
    INT_WMMA_m32n8k16_load_c_f32_row_shared_ari = 2143,
2159
    INT_WMMA_m32n8k16_load_c_f32_row_shared_ari64 = 2144,
2160
    INT_WMMA_m32n8k16_load_c_f32_row_shared_avar  = 2145,
2161
    INT_WMMA_m32n8k16_load_c_f32_row_shared_stride_areg = 2146,
2162
    INT_WMMA_m32n8k16_load_c_f32_row_shared_stride_areg64 = 2147,
2163
    INT_WMMA_m32n8k16_load_c_f32_row_shared_stride_ari  = 2148,
2164
    INT_WMMA_m32n8k16_load_c_f32_row_shared_stride_ari64  = 2149,
2165
    INT_WMMA_m32n8k16_load_c_f32_row_shared_stride_avar = 2150,
2166
    INT_WMMA_m32n8k16_load_c_f32_row_stride_areg  = 2151,
2167
    INT_WMMA_m32n8k16_load_c_f32_row_stride_areg64  = 2152,
2168
    INT_WMMA_m32n8k16_load_c_f32_row_stride_ari = 2153,
2169
    INT_WMMA_m32n8k16_load_c_f32_row_stride_ari64 = 2154,
2170
    INT_WMMA_m32n8k16_load_c_f32_row_stride_avar  = 2155,
2171
    INT_WMMA_m32n8k16_store_d_f16_col_areg  = 2156,
2172
    INT_WMMA_m32n8k16_store_d_f16_col_areg64  = 2157,
2173
    INT_WMMA_m32n8k16_store_d_f16_col_ari = 2158,
2174
    INT_WMMA_m32n8k16_store_d_f16_col_ari64 = 2159,
2175
    INT_WMMA_m32n8k16_store_d_f16_col_avar  = 2160,
2176
    INT_WMMA_m32n8k16_store_d_f16_col_global_areg = 2161,
2177
    INT_WMMA_m32n8k16_store_d_f16_col_global_areg64 = 2162,
2178
    INT_WMMA_m32n8k16_store_d_f16_col_global_ari  = 2163,
2179
    INT_WMMA_m32n8k16_store_d_f16_col_global_ari64  = 2164,
2180
    INT_WMMA_m32n8k16_store_d_f16_col_global_avar = 2165,
2181
    INT_WMMA_m32n8k16_store_d_f16_col_global_stride_areg  = 2166,
2182
    INT_WMMA_m32n8k16_store_d_f16_col_global_stride_areg64  = 2167,
2183
    INT_WMMA_m32n8k16_store_d_f16_col_global_stride_ari = 2168,
2184
    INT_WMMA_m32n8k16_store_d_f16_col_global_stride_ari64 = 2169,
2185
    INT_WMMA_m32n8k16_store_d_f16_col_global_stride_avar  = 2170,
2186
    INT_WMMA_m32n8k16_store_d_f16_col_shared_areg = 2171,
2187
    INT_WMMA_m32n8k16_store_d_f16_col_shared_areg64 = 2172,
2188
    INT_WMMA_m32n8k16_store_d_f16_col_shared_ari  = 2173,
2189
    INT_WMMA_m32n8k16_store_d_f16_col_shared_ari64  = 2174,
2190
    INT_WMMA_m32n8k16_store_d_f16_col_shared_avar = 2175,
2191
    INT_WMMA_m32n8k16_store_d_f16_col_shared_stride_areg  = 2176,
2192
    INT_WMMA_m32n8k16_store_d_f16_col_shared_stride_areg64  = 2177,
2193
    INT_WMMA_m32n8k16_store_d_f16_col_shared_stride_ari = 2178,
2194
    INT_WMMA_m32n8k16_store_d_f16_col_shared_stride_ari64 = 2179,
2195
    INT_WMMA_m32n8k16_store_d_f16_col_shared_stride_avar  = 2180,
2196
    INT_WMMA_m32n8k16_store_d_f16_col_stride_areg = 2181,
2197
    INT_WMMA_m32n8k16_store_d_f16_col_stride_areg64 = 2182,
2198
    INT_WMMA_m32n8k16_store_d_f16_col_stride_ari  = 2183,
2199
    INT_WMMA_m32n8k16_store_d_f16_col_stride_ari64  = 2184,
2200
    INT_WMMA_m32n8k16_store_d_f16_col_stride_avar = 2185,
2201
    INT_WMMA_m32n8k16_store_d_f16_row_areg  = 2186,
2202
    INT_WMMA_m32n8k16_store_d_f16_row_areg64  = 2187,
2203
    INT_WMMA_m32n8k16_store_d_f16_row_ari = 2188,
2204
    INT_WMMA_m32n8k16_store_d_f16_row_ari64 = 2189,
2205
    INT_WMMA_m32n8k16_store_d_f16_row_avar  = 2190,
2206
    INT_WMMA_m32n8k16_store_d_f16_row_global_areg = 2191,
2207
    INT_WMMA_m32n8k16_store_d_f16_row_global_areg64 = 2192,
2208
    INT_WMMA_m32n8k16_store_d_f16_row_global_ari  = 2193,
2209
    INT_WMMA_m32n8k16_store_d_f16_row_global_ari64  = 2194,
2210
    INT_WMMA_m32n8k16_store_d_f16_row_global_avar = 2195,
2211
    INT_WMMA_m32n8k16_store_d_f16_row_global_stride_areg  = 2196,
2212
    INT_WMMA_m32n8k16_store_d_f16_row_global_stride_areg64  = 2197,
2213
    INT_WMMA_m32n8k16_store_d_f16_row_global_stride_ari = 2198,
2214
    INT_WMMA_m32n8k16_store_d_f16_row_global_stride_ari64 = 2199,
2215
    INT_WMMA_m32n8k16_store_d_f16_row_global_stride_avar  = 2200,
2216
    INT_WMMA_m32n8k16_store_d_f16_row_shared_areg = 2201,
2217
    INT_WMMA_m32n8k16_store_d_f16_row_shared_areg64 = 2202,
2218
    INT_WMMA_m32n8k16_store_d_f16_row_shared_ari  = 2203,
2219
    INT_WMMA_m32n8k16_store_d_f16_row_shared_ari64  = 2204,
2220
    INT_WMMA_m32n8k16_store_d_f16_row_shared_avar = 2205,
2221
    INT_WMMA_m32n8k16_store_d_f16_row_shared_stride_areg  = 2206,
2222
    INT_WMMA_m32n8k16_store_d_f16_row_shared_stride_areg64  = 2207,
2223
    INT_WMMA_m32n8k16_store_d_f16_row_shared_stride_ari = 2208,
2224
    INT_WMMA_m32n8k16_store_d_f16_row_shared_stride_ari64 = 2209,
2225
    INT_WMMA_m32n8k16_store_d_f16_row_shared_stride_avar  = 2210,
2226
    INT_WMMA_m32n8k16_store_d_f16_row_stride_areg = 2211,
2227
    INT_WMMA_m32n8k16_store_d_f16_row_stride_areg64 = 2212,
2228
    INT_WMMA_m32n8k16_store_d_f16_row_stride_ari  = 2213,
2229
    INT_WMMA_m32n8k16_store_d_f16_row_stride_ari64  = 2214,
2230
    INT_WMMA_m32n8k16_store_d_f16_row_stride_avar = 2215,
2231
    INT_WMMA_m32n8k16_store_d_f32_col_areg  = 2216,
2232
    INT_WMMA_m32n8k16_store_d_f32_col_areg64  = 2217,
2233
    INT_WMMA_m32n8k16_store_d_f32_col_ari = 2218,
2234
    INT_WMMA_m32n8k16_store_d_f32_col_ari64 = 2219,
2235
    INT_WMMA_m32n8k16_store_d_f32_col_avar  = 2220,
2236
    INT_WMMA_m32n8k16_store_d_f32_col_global_areg = 2221,
2237
    INT_WMMA_m32n8k16_store_d_f32_col_global_areg64 = 2222,
2238
    INT_WMMA_m32n8k16_store_d_f32_col_global_ari  = 2223,
2239
    INT_WMMA_m32n8k16_store_d_f32_col_global_ari64  = 2224,
2240
    INT_WMMA_m32n8k16_store_d_f32_col_global_avar = 2225,
2241
    INT_WMMA_m32n8k16_store_d_f32_col_global_stride_areg  = 2226,
2242
    INT_WMMA_m32n8k16_store_d_f32_col_global_stride_areg64  = 2227,
2243
    INT_WMMA_m32n8k16_store_d_f32_col_global_stride_ari = 2228,
2244
    INT_WMMA_m32n8k16_store_d_f32_col_global_stride_ari64 = 2229,
2245
    INT_WMMA_m32n8k16_store_d_f32_col_global_stride_avar  = 2230,
2246
    INT_WMMA_m32n8k16_store_d_f32_col_shared_areg = 2231,
2247
    INT_WMMA_m32n8k16_store_d_f32_col_shared_areg64 = 2232,
2248
    INT_WMMA_m32n8k16_store_d_f32_col_shared_ari  = 2233,
2249
    INT_WMMA_m32n8k16_store_d_f32_col_shared_ari64  = 2234,
2250
    INT_WMMA_m32n8k16_store_d_f32_col_shared_avar = 2235,
2251
    INT_WMMA_m32n8k16_store_d_f32_col_shared_stride_areg  = 2236,
2252
    INT_WMMA_m32n8k16_store_d_f32_col_shared_stride_areg64  = 2237,
2253
    INT_WMMA_m32n8k16_store_d_f32_col_shared_stride_ari = 2238,
2254
    INT_WMMA_m32n8k16_store_d_f32_col_shared_stride_ari64 = 2239,
2255
    INT_WMMA_m32n8k16_store_d_f32_col_shared_stride_avar  = 2240,
2256
    INT_WMMA_m32n8k16_store_d_f32_col_stride_areg = 2241,
2257
    INT_WMMA_m32n8k16_store_d_f32_col_stride_areg64 = 2242,
2258
    INT_WMMA_m32n8k16_store_d_f32_col_stride_ari  = 2243,
2259
    INT_WMMA_m32n8k16_store_d_f32_col_stride_ari64  = 2244,
2260
    INT_WMMA_m32n8k16_store_d_f32_col_stride_avar = 2245,
2261
    INT_WMMA_m32n8k16_store_d_f32_row_areg  = 2246,
2262
    INT_WMMA_m32n8k16_store_d_f32_row_areg64  = 2247,
2263
    INT_WMMA_m32n8k16_store_d_f32_row_ari = 2248,
2264
    INT_WMMA_m32n8k16_store_d_f32_row_ari64 = 2249,
2265
    INT_WMMA_m32n8k16_store_d_f32_row_avar  = 2250,
2266
    INT_WMMA_m32n8k16_store_d_f32_row_global_areg = 2251,
2267
    INT_WMMA_m32n8k16_store_d_f32_row_global_areg64 = 2252,
2268
    INT_WMMA_m32n8k16_store_d_f32_row_global_ari  = 2253,
2269
    INT_WMMA_m32n8k16_store_d_f32_row_global_ari64  = 2254,
2270
    INT_WMMA_m32n8k16_store_d_f32_row_global_avar = 2255,
2271
    INT_WMMA_m32n8k16_store_d_f32_row_global_stride_areg  = 2256,
2272
    INT_WMMA_m32n8k16_store_d_f32_row_global_stride_areg64  = 2257,
2273
    INT_WMMA_m32n8k16_store_d_f32_row_global_stride_ari = 2258,
2274
    INT_WMMA_m32n8k16_store_d_f32_row_global_stride_ari64 = 2259,
2275
    INT_WMMA_m32n8k16_store_d_f32_row_global_stride_avar  = 2260,
2276
    INT_WMMA_m32n8k16_store_d_f32_row_shared_areg = 2261,
2277
    INT_WMMA_m32n8k16_store_d_f32_row_shared_areg64 = 2262,
2278
    INT_WMMA_m32n8k16_store_d_f32_row_shared_ari  = 2263,
2279
    INT_WMMA_m32n8k16_store_d_f32_row_shared_ari64  = 2264,
2280
    INT_WMMA_m32n8k16_store_d_f32_row_shared_avar = 2265,
2281
    INT_WMMA_m32n8k16_store_d_f32_row_shared_stride_areg  = 2266,
2282
    INT_WMMA_m32n8k16_store_d_f32_row_shared_stride_areg64  = 2267,
2283
    INT_WMMA_m32n8k16_store_d_f32_row_shared_stride_ari = 2268,
2284
    INT_WMMA_m32n8k16_store_d_f32_row_shared_stride_ari64 = 2269,
2285
    INT_WMMA_m32n8k16_store_d_f32_row_shared_stride_avar  = 2270,
2286
    INT_WMMA_m32n8k16_store_d_f32_row_stride_areg = 2271,
2287
    INT_WMMA_m32n8k16_store_d_f32_row_stride_areg64 = 2272,
2288
    INT_WMMA_m32n8k16_store_d_f32_row_stride_ari  = 2273,
2289
    INT_WMMA_m32n8k16_store_d_f32_row_stride_ari64  = 2274,
2290
    INT_WMMA_m32n8k16_store_d_f32_row_stride_avar = 2275,
2291
    INT_WMMA_m8n32k16_load_a_col_areg = 2276,
2292
    INT_WMMA_m8n32k16_load_a_col_areg64 = 2277,
2293
    INT_WMMA_m8n32k16_load_a_col_ari  = 2278,
2294
    INT_WMMA_m8n32k16_load_a_col_ari64  = 2279,
2295
    INT_WMMA_m8n32k16_load_a_col_avar = 2280,
2296
    INT_WMMA_m8n32k16_load_a_col_global_areg  = 2281,
2297
    INT_WMMA_m8n32k16_load_a_col_global_areg64  = 2282,
2298
    INT_WMMA_m8n32k16_load_a_col_global_ari = 2283,
2299
    INT_WMMA_m8n32k16_load_a_col_global_ari64 = 2284,
2300
    INT_WMMA_m8n32k16_load_a_col_global_avar  = 2285,
2301
    INT_WMMA_m8n32k16_load_a_col_global_stride_areg = 2286,
2302
    INT_WMMA_m8n32k16_load_a_col_global_stride_areg64 = 2287,
2303
    INT_WMMA_m8n32k16_load_a_col_global_stride_ari  = 2288,
2304
    INT_WMMA_m8n32k16_load_a_col_global_stride_ari64  = 2289,
2305
    INT_WMMA_m8n32k16_load_a_col_global_stride_avar = 2290,
2306
    INT_WMMA_m8n32k16_load_a_col_shared_areg  = 2291,
2307
    INT_WMMA_m8n32k16_load_a_col_shared_areg64  = 2292,
2308
    INT_WMMA_m8n32k16_load_a_col_shared_ari = 2293,
2309
    INT_WMMA_m8n32k16_load_a_col_shared_ari64 = 2294,
2310
    INT_WMMA_m8n32k16_load_a_col_shared_avar  = 2295,
2311
    INT_WMMA_m8n32k16_load_a_col_shared_stride_areg = 2296,
2312
    INT_WMMA_m8n32k16_load_a_col_shared_stride_areg64 = 2297,
2313
    INT_WMMA_m8n32k16_load_a_col_shared_stride_ari  = 2298,
2314
    INT_WMMA_m8n32k16_load_a_col_shared_stride_ari64  = 2299,
2315
    INT_WMMA_m8n32k16_load_a_col_shared_stride_avar = 2300,
2316
    INT_WMMA_m8n32k16_load_a_col_stride_areg  = 2301,
2317
    INT_WMMA_m8n32k16_load_a_col_stride_areg64  = 2302,
2318
    INT_WMMA_m8n32k16_load_a_col_stride_ari = 2303,
2319
    INT_WMMA_m8n32k16_load_a_col_stride_ari64 = 2304,
2320
    INT_WMMA_m8n32k16_load_a_col_stride_avar  = 2305,
2321
    INT_WMMA_m8n32k16_load_a_row_areg = 2306,
2322
    INT_WMMA_m8n32k16_load_a_row_areg64 = 2307,
2323
    INT_WMMA_m8n32k16_load_a_row_ari  = 2308,
2324
    INT_WMMA_m8n32k16_load_a_row_ari64  = 2309,
2325
    INT_WMMA_m8n32k16_load_a_row_avar = 2310,
2326
    INT_WMMA_m8n32k16_load_a_row_global_areg  = 2311,
2327
    INT_WMMA_m8n32k16_load_a_row_global_areg64  = 2312,
2328
    INT_WMMA_m8n32k16_load_a_row_global_ari = 2313,
2329
    INT_WMMA_m8n32k16_load_a_row_global_ari64 = 2314,
2330
    INT_WMMA_m8n32k16_load_a_row_global_avar  = 2315,
2331
    INT_WMMA_m8n32k16_load_a_row_global_stride_areg = 2316,
2332
    INT_WMMA_m8n32k16_load_a_row_global_stride_areg64 = 2317,
2333
    INT_WMMA_m8n32k16_load_a_row_global_stride_ari  = 2318,
2334
    INT_WMMA_m8n32k16_load_a_row_global_stride_ari64  = 2319,
2335
    INT_WMMA_m8n32k16_load_a_row_global_stride_avar = 2320,
2336
    INT_WMMA_m8n32k16_load_a_row_shared_areg  = 2321,
2337
    INT_WMMA_m8n32k16_load_a_row_shared_areg64  = 2322,
2338
    INT_WMMA_m8n32k16_load_a_row_shared_ari = 2323,
2339
    INT_WMMA_m8n32k16_load_a_row_shared_ari64 = 2324,
2340
    INT_WMMA_m8n32k16_load_a_row_shared_avar  = 2325,
2341
    INT_WMMA_m8n32k16_load_a_row_shared_stride_areg = 2326,
2342
    INT_WMMA_m8n32k16_load_a_row_shared_stride_areg64 = 2327,
2343
    INT_WMMA_m8n32k16_load_a_row_shared_stride_ari  = 2328,
2344
    INT_WMMA_m8n32k16_load_a_row_shared_stride_ari64  = 2329,
2345
    INT_WMMA_m8n32k16_load_a_row_shared_stride_avar = 2330,
2346
    INT_WMMA_m8n32k16_load_a_row_stride_areg  = 2331,
2347
    INT_WMMA_m8n32k16_load_a_row_stride_areg64  = 2332,
2348
    INT_WMMA_m8n32k16_load_a_row_stride_ari = 2333,
2349
    INT_WMMA_m8n32k16_load_a_row_stride_ari64 = 2334,
2350
    INT_WMMA_m8n32k16_load_a_row_stride_avar  = 2335,
2351
    INT_WMMA_m8n32k16_load_b_col_areg = 2336,
2352
    INT_WMMA_m8n32k16_load_b_col_areg64 = 2337,
2353
    INT_WMMA_m8n32k16_load_b_col_ari  = 2338,
2354
    INT_WMMA_m8n32k16_load_b_col_ari64  = 2339,
2355
    INT_WMMA_m8n32k16_load_b_col_avar = 2340,
2356
    INT_WMMA_m8n32k16_load_b_col_global_areg  = 2341,
2357
    INT_WMMA_m8n32k16_load_b_col_global_areg64  = 2342,
2358
    INT_WMMA_m8n32k16_load_b_col_global_ari = 2343,
2359
    INT_WMMA_m8n32k16_load_b_col_global_ari64 = 2344,
2360
    INT_WMMA_m8n32k16_load_b_col_global_avar  = 2345,
2361
    INT_WMMA_m8n32k16_load_b_col_global_stride_areg = 2346,
2362
    INT_WMMA_m8n32k16_load_b_col_global_stride_areg64 = 2347,
2363
    INT_WMMA_m8n32k16_load_b_col_global_stride_ari  = 2348,
2364
    INT_WMMA_m8n32k16_load_b_col_global_stride_ari64  = 2349,
2365
    INT_WMMA_m8n32k16_load_b_col_global_stride_avar = 2350,
2366
    INT_WMMA_m8n32k16_load_b_col_shared_areg  = 2351,
2367
    INT_WMMA_m8n32k16_load_b_col_shared_areg64  = 2352,
2368
    INT_WMMA_m8n32k16_load_b_col_shared_ari = 2353,
2369
    INT_WMMA_m8n32k16_load_b_col_shared_ari64 = 2354,
2370
    INT_WMMA_m8n32k16_load_b_col_shared_avar  = 2355,
2371
    INT_WMMA_m8n32k16_load_b_col_shared_stride_areg = 2356,
2372
    INT_WMMA_m8n32k16_load_b_col_shared_stride_areg64 = 2357,
2373
    INT_WMMA_m8n32k16_load_b_col_shared_stride_ari  = 2358,
2374
    INT_WMMA_m8n32k16_load_b_col_shared_stride_ari64  = 2359,
2375
    INT_WMMA_m8n32k16_load_b_col_shared_stride_avar = 2360,
2376
    INT_WMMA_m8n32k16_load_b_col_stride_areg  = 2361,
2377
    INT_WMMA_m8n32k16_load_b_col_stride_areg64  = 2362,
2378
    INT_WMMA_m8n32k16_load_b_col_stride_ari = 2363,
2379
    INT_WMMA_m8n32k16_load_b_col_stride_ari64 = 2364,
2380
    INT_WMMA_m8n32k16_load_b_col_stride_avar  = 2365,
2381
    INT_WMMA_m8n32k16_load_b_row_areg = 2366,
2382
    INT_WMMA_m8n32k16_load_b_row_areg64 = 2367,
2383
    INT_WMMA_m8n32k16_load_b_row_ari  = 2368,
2384
    INT_WMMA_m8n32k16_load_b_row_ari64  = 2369,
2385
    INT_WMMA_m8n32k16_load_b_row_avar = 2370,
2386
    INT_WMMA_m8n32k16_load_b_row_global_areg  = 2371,
2387
    INT_WMMA_m8n32k16_load_b_row_global_areg64  = 2372,
2388
    INT_WMMA_m8n32k16_load_b_row_global_ari = 2373,
2389
    INT_WMMA_m8n32k16_load_b_row_global_ari64 = 2374,
2390
    INT_WMMA_m8n32k16_load_b_row_global_avar  = 2375,
2391
    INT_WMMA_m8n32k16_load_b_row_global_stride_areg = 2376,
2392
    INT_WMMA_m8n32k16_load_b_row_global_stride_areg64 = 2377,
2393
    INT_WMMA_m8n32k16_load_b_row_global_stride_ari  = 2378,
2394
    INT_WMMA_m8n32k16_load_b_row_global_stride_ari64  = 2379,
2395
    INT_WMMA_m8n32k16_load_b_row_global_stride_avar = 2380,
2396
    INT_WMMA_m8n32k16_load_b_row_shared_areg  = 2381,
2397
    INT_WMMA_m8n32k16_load_b_row_shared_areg64  = 2382,
2398
    INT_WMMA_m8n32k16_load_b_row_shared_ari = 2383,
2399
    INT_WMMA_m8n32k16_load_b_row_shared_ari64 = 2384,
2400
    INT_WMMA_m8n32k16_load_b_row_shared_avar  = 2385,
2401
    INT_WMMA_m8n32k16_load_b_row_shared_stride_areg = 2386,
2402
    INT_WMMA_m8n32k16_load_b_row_shared_stride_areg64 = 2387,
2403
    INT_WMMA_m8n32k16_load_b_row_shared_stride_ari  = 2388,
2404
    INT_WMMA_m8n32k16_load_b_row_shared_stride_ari64  = 2389,
2405
    INT_WMMA_m8n32k16_load_b_row_shared_stride_avar = 2390,
2406
    INT_WMMA_m8n32k16_load_b_row_stride_areg  = 2391,
2407
    INT_WMMA_m8n32k16_load_b_row_stride_areg64  = 2392,
2408
    INT_WMMA_m8n32k16_load_b_row_stride_ari = 2393,
2409
    INT_WMMA_m8n32k16_load_b_row_stride_ari64 = 2394,
2410
    INT_WMMA_m8n32k16_load_b_row_stride_avar  = 2395,
2411
    INT_WMMA_m8n32k16_load_c_f16_col_areg = 2396,
2412
    INT_WMMA_m8n32k16_load_c_f16_col_areg64 = 2397,
2413
    INT_WMMA_m8n32k16_load_c_f16_col_ari  = 2398,
2414
    INT_WMMA_m8n32k16_load_c_f16_col_ari64  = 2399,
2415
    INT_WMMA_m8n32k16_load_c_f16_col_avar = 2400,
2416
    INT_WMMA_m8n32k16_load_c_f16_col_global_areg  = 2401,
2417
    INT_WMMA_m8n32k16_load_c_f16_col_global_areg64  = 2402,
2418
    INT_WMMA_m8n32k16_load_c_f16_col_global_ari = 2403,
2419
    INT_WMMA_m8n32k16_load_c_f16_col_global_ari64 = 2404,
2420
    INT_WMMA_m8n32k16_load_c_f16_col_global_avar  = 2405,
2421
    INT_WMMA_m8n32k16_load_c_f16_col_global_stride_areg = 2406,
2422
    INT_WMMA_m8n32k16_load_c_f16_col_global_stride_areg64 = 2407,
2423
    INT_WMMA_m8n32k16_load_c_f16_col_global_stride_ari  = 2408,
2424
    INT_WMMA_m8n32k16_load_c_f16_col_global_stride_ari64  = 2409,
2425
    INT_WMMA_m8n32k16_load_c_f16_col_global_stride_avar = 2410,
2426
    INT_WMMA_m8n32k16_load_c_f16_col_shared_areg  = 2411,
2427
    INT_WMMA_m8n32k16_load_c_f16_col_shared_areg64  = 2412,
2428
    INT_WMMA_m8n32k16_load_c_f16_col_shared_ari = 2413,
2429
    INT_WMMA_m8n32k16_load_c_f16_col_shared_ari64 = 2414,
2430
    INT_WMMA_m8n32k16_load_c_f16_col_shared_avar  = 2415,
2431
    INT_WMMA_m8n32k16_load_c_f16_col_shared_stride_areg = 2416,
2432
    INT_WMMA_m8n32k16_load_c_f16_col_shared_stride_areg64 = 2417,
2433
    INT_WMMA_m8n32k16_load_c_f16_col_shared_stride_ari  = 2418,
2434
    INT_WMMA_m8n32k16_load_c_f16_col_shared_stride_ari64  = 2419,
2435
    INT_WMMA_m8n32k16_load_c_f16_col_shared_stride_avar = 2420,
2436
    INT_WMMA_m8n32k16_load_c_f16_col_stride_areg  = 2421,
2437
    INT_WMMA_m8n32k16_load_c_f16_col_stride_areg64  = 2422,
2438
    INT_WMMA_m8n32k16_load_c_f16_col_stride_ari = 2423,
2439
    INT_WMMA_m8n32k16_load_c_f16_col_stride_ari64 = 2424,
2440
    INT_WMMA_m8n32k16_load_c_f16_col_stride_avar  = 2425,
2441
    INT_WMMA_m8n32k16_load_c_f16_row_areg = 2426,
2442
    INT_WMMA_m8n32k16_load_c_f16_row_areg64 = 2427,
2443
    INT_WMMA_m8n32k16_load_c_f16_row_ari  = 2428,
2444
    INT_WMMA_m8n32k16_load_c_f16_row_ari64  = 2429,
2445
    INT_WMMA_m8n32k16_load_c_f16_row_avar = 2430,
2446
    INT_WMMA_m8n32k16_load_c_f16_row_global_areg  = 2431,
2447
    INT_WMMA_m8n32k16_load_c_f16_row_global_areg64  = 2432,
2448
    INT_WMMA_m8n32k16_load_c_f16_row_global_ari = 2433,
2449
    INT_WMMA_m8n32k16_load_c_f16_row_global_ari64 = 2434,
2450
    INT_WMMA_m8n32k16_load_c_f16_row_global_avar  = 2435,
2451
    INT_WMMA_m8n32k16_load_c_f16_row_global_stride_areg = 2436,
2452
    INT_WMMA_m8n32k16_load_c_f16_row_global_stride_areg64 = 2437,
2453
    INT_WMMA_m8n32k16_load_c_f16_row_global_stride_ari  = 2438,
2454
    INT_WMMA_m8n32k16_load_c_f16_row_global_stride_ari64  = 2439,
2455
    INT_WMMA_m8n32k16_load_c_f16_row_global_stride_avar = 2440,
2456
    INT_WMMA_m8n32k16_load_c_f16_row_shared_areg  = 2441,
2457
    INT_WMMA_m8n32k16_load_c_f16_row_shared_areg64  = 2442,
2458
    INT_WMMA_m8n32k16_load_c_f16_row_shared_ari = 2443,
2459
    INT_WMMA_m8n32k16_load_c_f16_row_shared_ari64 = 2444,
2460
    INT_WMMA_m8n32k16_load_c_f16_row_shared_avar  = 2445,
2461
    INT_WMMA_m8n32k16_load_c_f16_row_shared_stride_areg = 2446,
2462
    INT_WMMA_m8n32k16_load_c_f16_row_shared_stride_areg64 = 2447,
2463
    INT_WMMA_m8n32k16_load_c_f16_row_shared_stride_ari  = 2448,
2464
    INT_WMMA_m8n32k16_load_c_f16_row_shared_stride_ari64  = 2449,
2465
    INT_WMMA_m8n32k16_load_c_f16_row_shared_stride_avar = 2450,
2466
    INT_WMMA_m8n32k16_load_c_f16_row_stride_areg  = 2451,
2467
    INT_WMMA_m8n32k16_load_c_f16_row_stride_areg64  = 2452,
2468
    INT_WMMA_m8n32k16_load_c_f16_row_stride_ari = 2453,
2469
    INT_WMMA_m8n32k16_load_c_f16_row_stride_ari64 = 2454,
2470
    INT_WMMA_m8n32k16_load_c_f16_row_stride_avar  = 2455,
2471
    INT_WMMA_m8n32k16_load_c_f32_col_areg = 2456,
2472
    INT_WMMA_m8n32k16_load_c_f32_col_areg64 = 2457,
2473
    INT_WMMA_m8n32k16_load_c_f32_col_ari  = 2458,
2474
    INT_WMMA_m8n32k16_load_c_f32_col_ari64  = 2459,
2475
    INT_WMMA_m8n32k16_load_c_f32_col_avar = 2460,
2476
    INT_WMMA_m8n32k16_load_c_f32_col_global_areg  = 2461,
2477
    INT_WMMA_m8n32k16_load_c_f32_col_global_areg64  = 2462,
2478
    INT_WMMA_m8n32k16_load_c_f32_col_global_ari = 2463,
2479
    INT_WMMA_m8n32k16_load_c_f32_col_global_ari64 = 2464,
2480
    INT_WMMA_m8n32k16_load_c_f32_col_global_avar  = 2465,
2481
    INT_WMMA_m8n32k16_load_c_f32_col_global_stride_areg = 2466,
2482
    INT_WMMA_m8n32k16_load_c_f32_col_global_stride_areg64 = 2467,
2483
    INT_WMMA_m8n32k16_load_c_f32_col_global_stride_ari  = 2468,
2484
    INT_WMMA_m8n32k16_load_c_f32_col_global_stride_ari64  = 2469,
2485
    INT_WMMA_m8n32k16_load_c_f32_col_global_stride_avar = 2470,
2486
    INT_WMMA_m8n32k16_load_c_f32_col_shared_areg  = 2471,
2487
    INT_WMMA_m8n32k16_load_c_f32_col_shared_areg64  = 2472,
2488
    INT_WMMA_m8n32k16_load_c_f32_col_shared_ari = 2473,
2489
    INT_WMMA_m8n32k16_load_c_f32_col_shared_ari64 = 2474,
2490
    INT_WMMA_m8n32k16_load_c_f32_col_shared_avar  = 2475,
2491
    INT_WMMA_m8n32k16_load_c_f32_col_shared_stride_areg = 2476,
2492
    INT_WMMA_m8n32k16_load_c_f32_col_shared_stride_areg64 = 2477,
2493
    INT_WMMA_m8n32k16_load_c_f32_col_shared_stride_ari  = 2478,
2494
    INT_WMMA_m8n32k16_load_c_f32_col_shared_stride_ari64  = 2479,
2495
    INT_WMMA_m8n32k16_load_c_f32_col_shared_stride_avar = 2480,
2496
    INT_WMMA_m8n32k16_load_c_f32_col_stride_areg  = 2481,
2497
    INT_WMMA_m8n32k16_load_c_f32_col_stride_areg64  = 2482,
2498
    INT_WMMA_m8n32k16_load_c_f32_col_stride_ari = 2483,
2499
    INT_WMMA_m8n32k16_load_c_f32_col_stride_ari64 = 2484,
2500
    INT_WMMA_m8n32k16_load_c_f32_col_stride_avar  = 2485,
2501
    INT_WMMA_m8n32k16_load_c_f32_row_areg = 2486,
2502
    INT_WMMA_m8n32k16_load_c_f32_row_areg64 = 2487,
2503
    INT_WMMA_m8n32k16_load_c_f32_row_ari  = 2488,
2504
    INT_WMMA_m8n32k16_load_c_f32_row_ari64  = 2489,
2505
    INT_WMMA_m8n32k16_load_c_f32_row_avar = 2490,
2506
    INT_WMMA_m8n32k16_load_c_f32_row_global_areg  = 2491,
2507
    INT_WMMA_m8n32k16_load_c_f32_row_global_areg64  = 2492,
2508
    INT_WMMA_m8n32k16_load_c_f32_row_global_ari = 2493,
2509
    INT_WMMA_m8n32k16_load_c_f32_row_global_ari64 = 2494,
2510
    INT_WMMA_m8n32k16_load_c_f32_row_global_avar  = 2495,
2511
    INT_WMMA_m8n32k16_load_c_f32_row_global_stride_areg = 2496,
2512
    INT_WMMA_m8n32k16_load_c_f32_row_global_stride_areg64 = 2497,
2513
    INT_WMMA_m8n32k16_load_c_f32_row_global_stride_ari  = 2498,
2514
    INT_WMMA_m8n32k16_load_c_f32_row_global_stride_ari64  = 2499,
2515
    INT_WMMA_m8n32k16_load_c_f32_row_global_stride_avar = 2500,
2516
    INT_WMMA_m8n32k16_load_c_f32_row_shared_areg  = 2501,
2517
    INT_WMMA_m8n32k16_load_c_f32_row_shared_areg64  = 2502,
2518
    INT_WMMA_m8n32k16_load_c_f32_row_shared_ari = 2503,
2519
    INT_WMMA_m8n32k16_load_c_f32_row_shared_ari64 = 2504,
2520
    INT_WMMA_m8n32k16_load_c_f32_row_shared_avar  = 2505,
2521
    INT_WMMA_m8n32k16_load_c_f32_row_shared_stride_areg = 2506,
2522
    INT_WMMA_m8n32k16_load_c_f32_row_shared_stride_areg64 = 2507,
2523
    INT_WMMA_m8n32k16_load_c_f32_row_shared_stride_ari  = 2508,
2524
    INT_WMMA_m8n32k16_load_c_f32_row_shared_stride_ari64  = 2509,
2525
    INT_WMMA_m8n32k16_load_c_f32_row_shared_stride_avar = 2510,
2526
    INT_WMMA_m8n32k16_load_c_f32_row_stride_areg  = 2511,
2527
    INT_WMMA_m8n32k16_load_c_f32_row_stride_areg64  = 2512,
2528
    INT_WMMA_m8n32k16_load_c_f32_row_stride_ari = 2513,
2529
    INT_WMMA_m8n32k16_load_c_f32_row_stride_ari64 = 2514,
2530
    INT_WMMA_m8n32k16_load_c_f32_row_stride_avar  = 2515,
2531
    INT_WMMA_m8n32k16_store_d_f16_col_areg  = 2516,
2532
    INT_WMMA_m8n32k16_store_d_f16_col_areg64  = 2517,
2533
    INT_WMMA_m8n32k16_store_d_f16_col_ari = 2518,
2534
    INT_WMMA_m8n32k16_store_d_f16_col_ari64 = 2519,
2535
    INT_WMMA_m8n32k16_store_d_f16_col_avar  = 2520,
2536
    INT_WMMA_m8n32k16_store_d_f16_col_global_areg = 2521,
2537
    INT_WMMA_m8n32k16_store_d_f16_col_global_areg64 = 2522,
2538
    INT_WMMA_m8n32k16_store_d_f16_col_global_ari  = 2523,
2539
    INT_WMMA_m8n32k16_store_d_f16_col_global_ari64  = 2524,
2540
    INT_WMMA_m8n32k16_store_d_f16_col_global_avar = 2525,
2541
    INT_WMMA_m8n32k16_store_d_f16_col_global_stride_areg  = 2526,
2542
    INT_WMMA_m8n32k16_store_d_f16_col_global_stride_areg64  = 2527,
2543
    INT_WMMA_m8n32k16_store_d_f16_col_global_stride_ari = 2528,
2544
    INT_WMMA_m8n32k16_store_d_f16_col_global_stride_ari64 = 2529,
2545
    INT_WMMA_m8n32k16_store_d_f16_col_global_stride_avar  = 2530,
2546
    INT_WMMA_m8n32k16_store_d_f16_col_shared_areg = 2531,
2547
    INT_WMMA_m8n32k16_store_d_f16_col_shared_areg64 = 2532,
2548
    INT_WMMA_m8n32k16_store_d_f16_col_shared_ari  = 2533,
2549
    INT_WMMA_m8n32k16_store_d_f16_col_shared_ari64  = 2534,
2550
    INT_WMMA_m8n32k16_store_d_f16_col_shared_avar = 2535,
2551
    INT_WMMA_m8n32k16_store_d_f16_col_shared_stride_areg  = 2536,
2552
    INT_WMMA_m8n32k16_store_d_f16_col_shared_stride_areg64  = 2537,
2553
    INT_WMMA_m8n32k16_store_d_f16_col_shared_stride_ari = 2538,
2554
    INT_WMMA_m8n32k16_store_d_f16_col_shared_stride_ari64 = 2539,
2555
    INT_WMMA_m8n32k16_store_d_f16_col_shared_stride_avar  = 2540,
2556
    INT_WMMA_m8n32k16_store_d_f16_col_stride_areg = 2541,
2557
    INT_WMMA_m8n32k16_store_d_f16_col_stride_areg64 = 2542,
2558
    INT_WMMA_m8n32k16_store_d_f16_col_stride_ari  = 2543,
2559
    INT_WMMA_m8n32k16_store_d_f16_col_stride_ari64  = 2544,
2560
    INT_WMMA_m8n32k16_store_d_f16_col_stride_avar = 2545,
2561
    INT_WMMA_m8n32k16_store_d_f16_row_areg  = 2546,
2562
    INT_WMMA_m8n32k16_store_d_f16_row_areg64  = 2547,
2563
    INT_WMMA_m8n32k16_store_d_f16_row_ari = 2548,
2564
    INT_WMMA_m8n32k16_store_d_f16_row_ari64 = 2549,
2565
    INT_WMMA_m8n32k16_store_d_f16_row_avar  = 2550,
2566
    INT_WMMA_m8n32k16_store_d_f16_row_global_areg = 2551,
2567
    INT_WMMA_m8n32k16_store_d_f16_row_global_areg64 = 2552,
2568
    INT_WMMA_m8n32k16_store_d_f16_row_global_ari  = 2553,
2569
    INT_WMMA_m8n32k16_store_d_f16_row_global_ari64  = 2554,
2570
    INT_WMMA_m8n32k16_store_d_f16_row_global_avar = 2555,
2571
    INT_WMMA_m8n32k16_store_d_f16_row_global_stride_areg  = 2556,
2572
    INT_WMMA_m8n32k16_store_d_f16_row_global_stride_areg64  = 2557,
2573
    INT_WMMA_m8n32k16_store_d_f16_row_global_stride_ari = 2558,
2574
    INT_WMMA_m8n32k16_store_d_f16_row_global_stride_ari64 = 2559,
2575
    INT_WMMA_m8n32k16_store_d_f16_row_global_stride_avar  = 2560,
2576
    INT_WMMA_m8n32k16_store_d_f16_row_shared_areg = 2561,
2577
    INT_WMMA_m8n32k16_store_d_f16_row_shared_areg64 = 2562,
2578
    INT_WMMA_m8n32k16_store_d_f16_row_shared_ari  = 2563,
2579
    INT_WMMA_m8n32k16_store_d_f16_row_shared_ari64  = 2564,
2580
    INT_WMMA_m8n32k16_store_d_f16_row_shared_avar = 2565,
2581
    INT_WMMA_m8n32k16_store_d_f16_row_shared_stride_areg  = 2566,
2582
    INT_WMMA_m8n32k16_store_d_f16_row_shared_stride_areg64  = 2567,
2583
    INT_WMMA_m8n32k16_store_d_f16_row_shared_stride_ari = 2568,
2584
    INT_WMMA_m8n32k16_store_d_f16_row_shared_stride_ari64 = 2569,
2585
    INT_WMMA_m8n32k16_store_d_f16_row_shared_stride_avar  = 2570,
2586
    INT_WMMA_m8n32k16_store_d_f16_row_stride_areg = 2571,
2587
    INT_WMMA_m8n32k16_store_d_f16_row_stride_areg64 = 2572,
2588
    INT_WMMA_m8n32k16_store_d_f16_row_stride_ari  = 2573,
2589
    INT_WMMA_m8n32k16_store_d_f16_row_stride_ari64  = 2574,
2590
    INT_WMMA_m8n32k16_store_d_f16_row_stride_avar = 2575,
2591
    INT_WMMA_m8n32k16_store_d_f32_col_areg  = 2576,
2592
    INT_WMMA_m8n32k16_store_d_f32_col_areg64  = 2577,
2593
    INT_WMMA_m8n32k16_store_d_f32_col_ari = 2578,
2594
    INT_WMMA_m8n32k16_store_d_f32_col_ari64 = 2579,
2595
    INT_WMMA_m8n32k16_store_d_f32_col_avar  = 2580,
2596
    INT_WMMA_m8n32k16_store_d_f32_col_global_areg = 2581,
2597
    INT_WMMA_m8n32k16_store_d_f32_col_global_areg64 = 2582,
2598
    INT_WMMA_m8n32k16_store_d_f32_col_global_ari  = 2583,
2599
    INT_WMMA_m8n32k16_store_d_f32_col_global_ari64  = 2584,
2600
    INT_WMMA_m8n32k16_store_d_f32_col_global_avar = 2585,
2601
    INT_WMMA_m8n32k16_store_d_f32_col_global_stride_areg  = 2586,
2602
    INT_WMMA_m8n32k16_store_d_f32_col_global_stride_areg64  = 2587,
2603
    INT_WMMA_m8n32k16_store_d_f32_col_global_stride_ari = 2588,
2604
    INT_WMMA_m8n32k16_store_d_f32_col_global_stride_ari64 = 2589,
2605
    INT_WMMA_m8n32k16_store_d_f32_col_global_stride_avar  = 2590,
2606
    INT_WMMA_m8n32k16_store_d_f32_col_shared_areg = 2591,
2607
    INT_WMMA_m8n32k16_store_d_f32_col_shared_areg64 = 2592,
2608
    INT_WMMA_m8n32k16_store_d_f32_col_shared_ari  = 2593,
2609
    INT_WMMA_m8n32k16_store_d_f32_col_shared_ari64  = 2594,
2610
    INT_WMMA_m8n32k16_store_d_f32_col_shared_avar = 2595,
2611
    INT_WMMA_m8n32k16_store_d_f32_col_shared_stride_areg  = 2596,
2612
    INT_WMMA_m8n32k16_store_d_f32_col_shared_stride_areg64  = 2597,
2613
    INT_WMMA_m8n32k16_store_d_f32_col_shared_stride_ari = 2598,
2614
    INT_WMMA_m8n32k16_store_d_f32_col_shared_stride_ari64 = 2599,
2615
    INT_WMMA_m8n32k16_store_d_f32_col_shared_stride_avar  = 2600,
2616
    INT_WMMA_m8n32k16_store_d_f32_col_stride_areg = 2601,
2617
    INT_WMMA_m8n32k16_store_d_f32_col_stride_areg64 = 2602,
2618
    INT_WMMA_m8n32k16_store_d_f32_col_stride_ari  = 2603,
2619
    INT_WMMA_m8n32k16_store_d_f32_col_stride_ari64  = 2604,
2620
    INT_WMMA_m8n32k16_store_d_f32_col_stride_avar = 2605,
2621
    INT_WMMA_m8n32k16_store_d_f32_row_areg  = 2606,
2622
    INT_WMMA_m8n32k16_store_d_f32_row_areg64  = 2607,
2623
    INT_WMMA_m8n32k16_store_d_f32_row_ari = 2608,
2624
    INT_WMMA_m8n32k16_store_d_f32_row_ari64 = 2609,
2625
    INT_WMMA_m8n32k16_store_d_f32_row_avar  = 2610,
2626
    INT_WMMA_m8n32k16_store_d_f32_row_global_areg = 2611,
2627
    INT_WMMA_m8n32k16_store_d_f32_row_global_areg64 = 2612,
2628
    INT_WMMA_m8n32k16_store_d_f32_row_global_ari  = 2613,
2629
    INT_WMMA_m8n32k16_store_d_f32_row_global_ari64  = 2614,
2630
    INT_WMMA_m8n32k16_store_d_f32_row_global_avar = 2615,
2631
    INT_WMMA_m8n32k16_store_d_f32_row_global_stride_areg  = 2616,
2632
    INT_WMMA_m8n32k16_store_d_f32_row_global_stride_areg64  = 2617,
2633
    INT_WMMA_m8n32k16_store_d_f32_row_global_stride_ari = 2618,
2634
    INT_WMMA_m8n32k16_store_d_f32_row_global_stride_ari64 = 2619,
2635
    INT_WMMA_m8n32k16_store_d_f32_row_global_stride_avar  = 2620,
2636
    INT_WMMA_m8n32k16_store_d_f32_row_shared_areg = 2621,
2637
    INT_WMMA_m8n32k16_store_d_f32_row_shared_areg64 = 2622,
2638
    INT_WMMA_m8n32k16_store_d_f32_row_shared_ari  = 2623,
2639
    INT_WMMA_m8n32k16_store_d_f32_row_shared_ari64  = 2624,
2640
    INT_WMMA_m8n32k16_store_d_f32_row_shared_avar = 2625,
2641
    INT_WMMA_m8n32k16_store_d_f32_row_shared_stride_areg  = 2626,
2642
    INT_WMMA_m8n32k16_store_d_f32_row_shared_stride_areg64  = 2627,
2643
    INT_WMMA_m8n32k16_store_d_f32_row_shared_stride_ari = 2628,
2644
    INT_WMMA_m8n32k16_store_d_f32_row_shared_stride_ari64 = 2629,
2645
    INT_WMMA_m8n32k16_store_d_f32_row_shared_stride_avar  = 2630,
2646
    INT_WMMA_m8n32k16_store_d_f32_row_stride_areg = 2631,
2647
    INT_WMMA_m8n32k16_store_d_f32_row_stride_areg64 = 2632,
2648
    INT_WMMA_m8n32k16_store_d_f32_row_stride_ari  = 2633,
2649
    INT_WMMA_m8n32k16_store_d_f32_row_stride_ari64  = 2634,
2650
    INT_WMMA_m8n32k16_store_d_f32_row_stride_avar = 2635,
2651
    ISSPACEP_CONST_32 = 2636,
2652
    ISSPACEP_CONST_64 = 2637,
2653
    ISSPACEP_GLOBAL_32  = 2638,
2654
    ISSPACEP_GLOBAL_64  = 2639,
2655
    ISSPACEP_LOCAL_32 = 2640,
2656
    ISSPACEP_LOCAL_64 = 2641,
2657
    ISSPACEP_SHARED_32  = 2642,
2658
    ISSPACEP_SHARED_64  = 2643,
2659
    ISTYPEP_SAMPLER = 2644,
2660
    ISTYPEP_SURFACE = 2645,
2661
    ISTYPEP_TEXTURE = 2646,
2662
    LDV_f16_v2_areg = 2647,
2663
    LDV_f16_v2_areg_64  = 2648,
2664
    LDV_f16_v2_ari  = 2649,
2665
    LDV_f16_v2_ari_64 = 2650,
2666
    LDV_f16_v2_asi  = 2651,
2667
    LDV_f16_v2_avar = 2652,
2668
    LDV_f16_v4_areg = 2653,
2669
    LDV_f16_v4_areg_64  = 2654,
2670
    LDV_f16_v4_ari  = 2655,
2671
    LDV_f16_v4_ari_64 = 2656,
2672
    LDV_f16_v4_asi  = 2657,
2673
    LDV_f16_v4_avar = 2658,
2674
    LDV_f16x2_v2_areg = 2659,
2675
    LDV_f16x2_v2_areg_64  = 2660,
2676
    LDV_f16x2_v2_ari  = 2661,
2677
    LDV_f16x2_v2_ari_64 = 2662,
2678
    LDV_f16x2_v2_asi  = 2663,
2679
    LDV_f16x2_v2_avar = 2664,
2680
    LDV_f16x2_v4_areg = 2665,
2681
    LDV_f16x2_v4_areg_64  = 2666,
2682
    LDV_f16x2_v4_ari  = 2667,
2683
    LDV_f16x2_v4_ari_64 = 2668,
2684
    LDV_f16x2_v4_asi  = 2669,
2685
    LDV_f16x2_v4_avar = 2670,
2686
    LDV_f32_v2_areg = 2671,
2687
    LDV_f32_v2_areg_64  = 2672,
2688
    LDV_f32_v2_ari  = 2673,
2689
    LDV_f32_v2_ari_64 = 2674,
2690
    LDV_f32_v2_asi  = 2675,
2691
    LDV_f32_v2_avar = 2676,
2692
    LDV_f32_v4_areg = 2677,
2693
    LDV_f32_v4_areg_64  = 2678,
2694
    LDV_f32_v4_ari  = 2679,
2695
    LDV_f32_v4_ari_64 = 2680,
2696
    LDV_f32_v4_asi  = 2681,
2697
    LDV_f32_v4_avar = 2682,
2698
    LDV_f64_v2_areg = 2683,
2699
    LDV_f64_v2_areg_64  = 2684,
2700
    LDV_f64_v2_ari  = 2685,
2701
    LDV_f64_v2_ari_64 = 2686,
2702
    LDV_f64_v2_asi  = 2687,
2703
    LDV_f64_v2_avar = 2688,
2704
    LDV_f64_v4_areg = 2689,
2705
    LDV_f64_v4_areg_64  = 2690,
2706
    LDV_f64_v4_ari  = 2691,
2707
    LDV_f64_v4_ari_64 = 2692,
2708
    LDV_f64_v4_asi  = 2693,
2709
    LDV_f64_v4_avar = 2694,
2710
    LDV_i16_v2_areg = 2695,
2711
    LDV_i16_v2_areg_64  = 2696,
2712
    LDV_i16_v2_ari  = 2697,
2713
    LDV_i16_v2_ari_64 = 2698,
2714
    LDV_i16_v2_asi  = 2699,
2715
    LDV_i16_v2_avar = 2700,
2716
    LDV_i16_v4_areg = 2701,
2717
    LDV_i16_v4_areg_64  = 2702,
2718
    LDV_i16_v4_ari  = 2703,
2719
    LDV_i16_v4_ari_64 = 2704,
2720
    LDV_i16_v4_asi  = 2705,
2721
    LDV_i16_v4_avar = 2706,
2722
    LDV_i32_v2_areg = 2707,
2723
    LDV_i32_v2_areg_64  = 2708,
2724
    LDV_i32_v2_ari  = 2709,
2725
    LDV_i32_v2_ari_64 = 2710,
2726
    LDV_i32_v2_asi  = 2711,
2727
    LDV_i32_v2_avar = 2712,
2728
    LDV_i32_v4_areg = 2713,
2729
    LDV_i32_v4_areg_64  = 2714,
2730
    LDV_i32_v4_ari  = 2715,
2731
    LDV_i32_v4_ari_64 = 2716,
2732
    LDV_i32_v4_asi  = 2717,
2733
    LDV_i32_v4_avar = 2718,
2734
    LDV_i64_v2_areg = 2719,
2735
    LDV_i64_v2_areg_64  = 2720,
2736
    LDV_i64_v2_ari  = 2721,
2737
    LDV_i64_v2_ari_64 = 2722,
2738
    LDV_i64_v2_asi  = 2723,
2739
    LDV_i64_v2_avar = 2724,
2740
    LDV_i64_v4_areg = 2725,
2741
    LDV_i64_v4_areg_64  = 2726,
2742
    LDV_i64_v4_ari  = 2727,
2743
    LDV_i64_v4_ari_64 = 2728,
2744
    LDV_i64_v4_asi  = 2729,
2745
    LDV_i64_v4_avar = 2730,
2746
    LDV_i8_v2_areg  = 2731,
2747
    LDV_i8_v2_areg_64 = 2732,
2748
    LDV_i8_v2_ari = 2733,
2749
    LDV_i8_v2_ari_64  = 2734,
2750
    LDV_i8_v2_asi = 2735,
2751
    LDV_i8_v2_avar  = 2736,
2752
    LDV_i8_v4_areg  = 2737,
2753
    LDV_i8_v4_areg_64 = 2738,
2754
    LDV_i8_v4_ari = 2739,
2755
    LDV_i8_v4_ari_64  = 2740,
2756
    LDV_i8_v4_asi = 2741,
2757
    LDV_i8_v4_avar  = 2742,
2758
    LD_f16_areg = 2743,
2759
    LD_f16_areg_64  = 2744,
2760
    LD_f16_ari  = 2745,
2761
    LD_f16_ari_64 = 2746,
2762
    LD_f16_asi  = 2747,
2763
    LD_f16_avar = 2748,
2764
    LD_f16x2_areg = 2749,
2765
    LD_f16x2_areg_64  = 2750,
2766
    LD_f16x2_ari  = 2751,
2767
    LD_f16x2_ari_64 = 2752,
2768
    LD_f16x2_asi  = 2753,
2769
    LD_f16x2_avar = 2754,
2770
    LD_f32_areg = 2755,
2771
    LD_f32_areg_64  = 2756,
2772
    LD_f32_ari  = 2757,
2773
    LD_f32_ari_64 = 2758,
2774
    LD_f32_asi  = 2759,
2775
    LD_f32_avar = 2760,
2776
    LD_f64_areg = 2761,
2777
    LD_f64_areg_64  = 2762,
2778
    LD_f64_ari  = 2763,
2779
    LD_f64_ari_64 = 2764,
2780
    LD_f64_asi  = 2765,
2781
    LD_f64_avar = 2766,
2782
    LD_i16_areg = 2767,
2783
    LD_i16_areg_64  = 2768,
2784
    LD_i16_ari  = 2769,
2785
    LD_i16_ari_64 = 2770,
2786
    LD_i16_asi  = 2771,
2787
    LD_i16_avar = 2772,
2788
    LD_i32_areg = 2773,
2789
    LD_i32_areg_64  = 2774,
2790
    LD_i32_ari  = 2775,
2791
    LD_i32_ari_64 = 2776,
2792
    LD_i32_asi  = 2777,
2793
    LD_i32_avar = 2778,
2794
    LD_i64_areg = 2779,
2795
    LD_i64_areg_64  = 2780,
2796
    LD_i64_ari  = 2781,
2797
    LD_i64_ari_64 = 2782,
2798
    LD_i64_asi  = 2783,
2799
    LD_i64_avar = 2784,
2800
    LD_i8_areg  = 2785,
2801
    LD_i8_areg_64 = 2786,
2802
    LD_i8_ari = 2787,
2803
    LD_i8_ari_64  = 2788,
2804
    LD_i8_asi = 2789,
2805
    LD_i8_avar  = 2790,
2806
    LEA_ADDRi = 2791,
2807
    LEA_ADDRi64 = 2792,
2808
    LOAD_CONST_F16  = 2793,
2809
    LastCallArgF32  = 2794,
2810
    LastCallArgF64  = 2795,
2811
    LastCallArgI16  = 2796,
2812
    LastCallArgI32  = 2797,
2813
    LastCallArgI32imm = 2798,
2814
    LastCallArgI64  = 2799,
2815
    LastCallArgParam  = 2800,
2816
    LoadParamMemF16 = 2801,
2817
    LoadParamMemF16x2 = 2802,
2818
    LoadParamMemF32 = 2803,
2819
    LoadParamMemF64 = 2804,
2820
    LoadParamMemI16 = 2805,
2821
    LoadParamMemI32 = 2806,
2822
    LoadParamMemI64 = 2807,
2823
    LoadParamMemI8  = 2808,
2824
    LoadParamMemV2F16 = 2809,
2825
    LoadParamMemV2F16x2 = 2810,
2826
    LoadParamMemV2F32 = 2811,
2827
    LoadParamMemV2F64 = 2812,
2828
    LoadParamMemV2I16 = 2813,
2829
    LoadParamMemV2I32 = 2814,
2830
    LoadParamMemV2I64 = 2815,
2831
    LoadParamMemV2I8  = 2816,
2832
    LoadParamMemV4F16 = 2817,
2833
    LoadParamMemV4F16x2 = 2818,
2834
    LoadParamMemV4F32 = 2819,
2835
    LoadParamMemV4I16 = 2820,
2836
    LoadParamMemV4I32 = 2821,
2837
    LoadParamMemV4I8  = 2822,
2838
    MAD16rii  = 2823,
2839
    MAD16rir  = 2824,
2840
    MAD16rri  = 2825,
2841
    MAD16rrr  = 2826,
2842
    MAD32rii  = 2827,
2843
    MAD32rir  = 2828,
2844
    MAD32rri  = 2829,
2845
    MAD32rrr  = 2830,
2846
    MAD64rii  = 2831,
2847
    MAD64rir  = 2832,
2848
    MAD64rri  = 2833,
2849
    MAD64rrr  = 2834,
2850
    MATCH_ALLP_SYNC_32ii  = 2835,
2851
    MATCH_ALLP_SYNC_32ir  = 2836,
2852
    MATCH_ALLP_SYNC_32ri  = 2837,
2853
    MATCH_ALLP_SYNC_32rr  = 2838,
2854
    MATCH_ALLP_SYNC_64ii  = 2839,
2855
    MATCH_ALLP_SYNC_64ir  = 2840,
2856
    MATCH_ALLP_SYNC_64ri  = 2841,
2857
    MATCH_ALLP_SYNC_64rr  = 2842,
2858
    MATCH_ANY_SYNC_32ii = 2843,
2859
    MATCH_ANY_SYNC_32ir = 2844,
2860
    MATCH_ANY_SYNC_32ri = 2845,
2861
    MATCH_ANY_SYNC_32rr = 2846,
2862
    MATCH_ANY_SYNC_64ii = 2847,
2863
    MATCH_ANY_SYNC_64ir = 2848,
2864
    MATCH_ANY_SYNC_64ri = 2849,
2865
    MATCH_ANY_SYNC_64rr = 2850,
2866
    MOV_ADDR  = 2851,
2867
    MOV_ADDR64  = 2852,
2868
    MOV_DEPOT_ADDR  = 2853,
2869
    MOV_DEPOT_ADDR_64 = 2854,
2870
    MOV_SPECIAL = 2855,
2871
    MULTHSi16ri = 2856,
2872
    MULTHSi16rr = 2857,
2873
    MULTHSi32ri = 2858,
2874
    MULTHSi32rr = 2859,
2875
    MULTHSi64ri = 2860,
2876
    MULTHSi64rr = 2861,
2877
    MULTHUi16ri = 2862,
2878
    MULTHUi16rr = 2863,
2879
    MULTHUi32ri = 2864,
2880
    MULTHUi32rr = 2865,
2881
    MULTHUi64ri = 2866,
2882
    MULTHUi64rr = 2867,
2883
    MULTi16ri = 2868,
2884
    MULTi16rr = 2869,
2885
    MULTi32ri = 2870,
2886
    MULTi32rr = 2871,
2887
    MULTi64ri = 2872,
2888
    MULTi64rr = 2873,
2889
    MULWIDES32  = 2874,
2890
    MULWIDES32Imm = 2875,
2891
    MULWIDES32Imm32 = 2876,
2892
    MULWIDES64  = 2877,
2893
    MULWIDES64Imm = 2878,
2894
    MULWIDES64Imm64 = 2879,
2895
    MULWIDEU32  = 2880,
2896
    MULWIDEU32Imm = 2881,
2897
    MULWIDEU32Imm32 = 2882,
2898
    MULWIDEU64  = 2883,
2899
    MULWIDEU64Imm = 2884,
2900
    MULWIDEU64Imm64 = 2885,
2901
    MoveParamF16  = 2886,
2902
    MoveParamF32  = 2887,
2903
    MoveParamF64  = 2888,
2904
    MoveParamI16  = 2889,
2905
    MoveParamI32  = 2890,
2906
    MoveParamI64  = 2891,
2907
    NOP = 2892,
2908
    NOT1  = 2893,
2909
    NOT16 = 2894,
2910
    NOT32 = 2895,
2911
    NOT64 = 2896,
2912
    ORb16ri = 2897,
2913
    ORb16rr = 2898,
2914
    ORb1ri  = 2899,
2915
    ORb1rr  = 2900,
2916
    ORb32ri = 2901,
2917
    ORb32rr = 2902,
2918
    ORb64ri = 2903,
2919
    ORb64rr = 2904,
2920
    PACK_TWO_INT32  = 2905,
2921
    POPCr32 = 2906,
2922
    POPCr64 = 2907,
2923
    PrototypeInst = 2908,
2924
    PseudoUseParamF32 = 2909,
2925
    PseudoUseParamF64 = 2910,
2926
    PseudoUseParamI16 = 2911,
2927
    PseudoUseParamI32 = 2912,
2928
    PseudoUseParamI64 = 2913,
2929
    RETURNInst  = 2914,
2930
    ROT32imm_sw = 2915,
2931
    ROT64imm_sw = 2916,
2932
    ROTATE_B32_HW_IMM = 2917,
2933
    ROTATE_B32_HW_REG = 2918,
2934
    ROTL32imm_hw  = 2919,
2935
    ROTL32reg_hw  = 2920,
2936
    ROTL32reg_sw  = 2921,
2937
    ROTL64reg_sw  = 2922,
2938
    ROTR32imm_hw  = 2923,
2939
    ROTR32reg_hw  = 2924,
2940
    ROTR32reg_sw  = 2925,
2941
    ROTR64reg_sw  = 2926,
2942
    Return  = 2927,
2943
    SDIVi16ri = 2928,
2944
    SDIVi16rr = 2929,
2945
    SDIVi32ri = 2930,
2946
    SDIVi32rr = 2931,
2947
    SDIVi64ri = 2932,
2948
    SDIVi64rr = 2933,
2949
    SELP_b16ii  = 2934,
2950
    SELP_b16ir  = 2935,
2951
    SELP_b16ri  = 2936,
2952
    SELP_b16rr  = 2937,
2953
    SELP_b32ii  = 2938,
2954
    SELP_b32ir  = 2939,
2955
    SELP_b32ri  = 2940,
2956
    SELP_b32rr  = 2941,
2957
    SELP_b64ii  = 2942,
2958
    SELP_b64ir  = 2943,
2959
    SELP_b64ri  = 2944,
2960
    SELP_b64rr  = 2945,
2961
    SELP_f16ii  = 2946,
2962
    SELP_f16ir  = 2947,
2963
    SELP_f16ri  = 2948,
2964
    SELP_f16rr  = 2949,
2965
    SELP_f16x2rr  = 2950,
2966
    SELP_f32ii  = 2951,
2967
    SELP_f32ir  = 2952,
2968
    SELP_f32ri  = 2953,
2969
    SELP_f32rr  = 2954,
2970
    SELP_f64ii  = 2955,
2971
    SELP_f64ir  = 2956,
2972
    SELP_f64ri  = 2957,
2973
    SELP_f64rr  = 2958,
2974
    SELP_s16ii  = 2959,
2975
    SELP_s16ir  = 2960,
2976
    SELP_s16ri  = 2961,
2977
    SELP_s16rr  = 2962,
2978
    SELP_s32ii  = 2963,
2979
    SELP_s32ir  = 2964,
2980
    SELP_s32ri  = 2965,
2981
    SELP_s32rr  = 2966,
2982
    SELP_s64ii  = 2967,
2983
    SELP_s64ir  = 2968,
2984
    SELP_s64ri  = 2969,
2985
    SELP_s64rr  = 2970,
2986
    SELP_u16ii  = 2971,
2987
    SELP_u16ir  = 2972,
2988
    SELP_u16ri  = 2973,
2989
    SELP_u16rr  = 2974,
2990
    SELP_u32ii  = 2975,
2991
    SELP_u32ir  = 2976,
2992
    SELP_u32ri  = 2977,
2993
    SELP_u32rr  = 2978,
2994
    SELP_u64ii  = 2979,
2995
    SELP_u64ir  = 2980,
2996
    SELP_u64ri  = 2981,
2997
    SELP_u64rr  = 2982,
2998
    SETP_b16ir  = 2983,
2999
    SETP_b16ri  = 2984,
3000
    SETP_b16rr  = 2985,
3001
    SETP_b32ir  = 2986,
3002
    SETP_b32ri  = 2987,
3003
    SETP_b32rr  = 2988,
3004
    SETP_b64ir  = 2989,
3005
    SETP_b64ri  = 2990,
3006
    SETP_b64rr  = 2991,
3007
    SETP_f16rr  = 2992,
3008
    SETP_f16x2rr  = 2993,
3009
    SETP_f32ir  = 2994,
3010
    SETP_f32ri  = 2995,
3011
    SETP_f32rr  = 2996,
3012
    SETP_f64ir  = 2997,
3013
    SETP_f64ri  = 2998,
3014
    SETP_f64rr  = 2999,
3015
    SETP_s16ir  = 3000,
3016
    SETP_s16ri  = 3001,
3017
    SETP_s16rr  = 3002,
3018
    SETP_s32ir  = 3003,
3019
    SETP_s32ri  = 3004,
3020
    SETP_s32rr  = 3005,
3021
    SETP_s64ir  = 3006,
3022
    SETP_s64ri  = 3007,
3023
    SETP_s64rr  = 3008,
3024
    SETP_u16ir  = 3009,
3025
    SETP_u16ri  = 3010,
3026
    SETP_u16rr  = 3011,
3027
    SETP_u32ir  = 3012,
3028
    SETP_u32ri  = 3013,
3029
    SETP_u32rr  = 3014,
3030
    SETP_u64ir  = 3015,
3031
    SETP_u64ri  = 3016,
3032
    SETP_u64rr  = 3017,
3033
    SET_b16ir = 3018,
3034
    SET_b16ri = 3019,
3035
    SET_b16rr = 3020,
3036
    SET_b32ir = 3021,
3037
    SET_b32ri = 3022,
3038
    SET_b32rr = 3023,
3039
    SET_b64ir = 3024,
3040
    SET_b64ri = 3025,
3041
    SET_b64rr = 3026,
3042
    SET_f16ir = 3027,
3043
    SET_f16ri = 3028,
3044
    SET_f16rr = 3029,
3045
    SET_f32ir = 3030,
3046
    SET_f32ri = 3031,
3047
    SET_f32rr = 3032,
3048
    SET_f64ir = 3033,
3049
    SET_f64ri = 3034,
3050
    SET_f64rr = 3035,
3051
    SET_s16ir = 3036,
3052
    SET_s16ri = 3037,
3053
    SET_s16rr = 3038,
3054
    SET_s32ir = 3039,
3055
    SET_s32ri = 3040,
3056
    SET_s32rr = 3041,
3057
    SET_s64ir = 3042,
3058
    SET_s64ri = 3043,
3059
    SET_s64rr = 3044,
3060
    SET_u16ir = 3045,
3061
    SET_u16ri = 3046,
3062
    SET_u16rr = 3047,
3063
    SET_u32ir = 3048,
3064
    SET_u32ri = 3049,
3065
    SET_u32rr = 3050,
3066
    SET_u64ir = 3051,
3067
    SET_u64ri = 3052,
3068
    SET_u64rr = 3053,
3069
    SHF_L_WRAP_B32_IMM  = 3054,
3070
    SHF_L_WRAP_B32_REG  = 3055,
3071
    SHF_R_WRAP_B32_IMM  = 3056,
3072
    SHF_R_WRAP_B32_REG  = 3057,
3073
    SHLi16ri  = 3058,
3074
    SHLi16rr  = 3059,
3075
    SHLi32ii  = 3060,
3076
    SHLi32ri  = 3061,
3077
    SHLi32rr  = 3062,
3078
    SHLi64ri  = 3063,
3079
    SHLi64rr  = 3064,
3080
    SINF  = 3065,
3081
    SMAXi16ri = 3066,
3082
    SMAXi16rr = 3067,
3083
    SMAXi32ri = 3068,
3084
    SMAXi32rr = 3069,
3085
    SMAXi64ri = 3070,
3086
    SMAXi64rr = 3071,
3087
    SMINi16ri = 3072,
3088
    SMINi16rr = 3073,
3089
    SMINi32ri = 3074,
3090
    SMINi32rr = 3075,
3091
    SMINi64ri = 3076,
3092
    SMINi64rr = 3077,
3093
    SRAi16ri  = 3078,
3094
    SRAi16rr  = 3079,
3095
    SRAi32ii  = 3080,
3096
    SRAi32ri  = 3081,
3097
    SRAi32rr  = 3082,
3098
    SRAi64ri  = 3083,
3099
    SRAi64rr  = 3084,
3100
    SREMi16ri = 3085,
3101
    SREMi16rr = 3086,
3102
    SREMi32ri = 3087,
3103
    SREMi32rr = 3088,
3104
    SREMi64ri = 3089,
3105
    SREMi64rr = 3090,
3106
    SRLi16ri  = 3091,
3107
    SRLi16rr  = 3092,
3108
    SRLi32ii  = 3093,
3109
    SRLi32ri  = 3094,
3110
    SRLi32rr  = 3095,
3111
    SRLi64ri  = 3096,
3112
    SRLi64rr  = 3097,
3113
    STV_f16_v2_areg = 3098,
3114
    STV_f16_v2_areg_64  = 3099,
3115
    STV_f16_v2_ari  = 3100,
3116
    STV_f16_v2_ari_64 = 3101,
3117
    STV_f16_v2_asi  = 3102,
3118
    STV_f16_v2_avar = 3103,
3119
    STV_f16_v4_areg = 3104,
3120
    STV_f16_v4_areg_64  = 3105,
3121
    STV_f16_v4_ari  = 3106,
3122
    STV_f16_v4_ari_64 = 3107,
3123
    STV_f16_v4_asi  = 3108,
3124
    STV_f16_v4_avar = 3109,
3125
    STV_f16x2_v2_areg = 3110,
3126
    STV_f16x2_v2_areg_64  = 3111,
3127
    STV_f16x2_v2_ari  = 3112,
3128
    STV_f16x2_v2_ari_64 = 3113,
3129
    STV_f16x2_v2_asi  = 3114,
3130
    STV_f16x2_v2_avar = 3115,
3131
    STV_f16x2_v4_areg = 3116,
3132
    STV_f16x2_v4_areg_64  = 3117,
3133
    STV_f16x2_v4_ari  = 3118,
3134
    STV_f16x2_v4_ari_64 = 3119,
3135
    STV_f16x2_v4_asi  = 3120,
3136
    STV_f16x2_v4_avar = 3121,
3137
    STV_f32_v2_areg = 3122,
3138
    STV_f32_v2_areg_64  = 3123,
3139
    STV_f32_v2_ari  = 3124,
3140
    STV_f32_v2_ari_64 = 3125,
3141
    STV_f32_v2_asi  = 3126,
3142
    STV_f32_v2_avar = 3127,
3143
    STV_f32_v4_areg = 3128,
3144
    STV_f32_v4_areg_64  = 3129,
3145
    STV_f32_v4_ari  = 3130,
3146
    STV_f32_v4_ari_64 = 3131,
3147
    STV_f32_v4_asi  = 3132,
3148
    STV_f32_v4_avar = 3133,
3149
    STV_f64_v2_areg = 3134,
3150
    STV_f64_v2_areg_64  = 3135,
3151
    STV_f64_v2_ari  = 3136,
3152
    STV_f64_v2_ari_64 = 3137,
3153
    STV_f64_v2_asi  = 3138,
3154
    STV_f64_v2_avar = 3139,
3155
    STV_f64_v4_areg = 3140,
3156
    STV_f64_v4_areg_64  = 3141,
3157
    STV_f64_v4_ari  = 3142,
3158
    STV_f64_v4_ari_64 = 3143,
3159
    STV_f64_v4_asi  = 3144,
3160
    STV_f64_v4_avar = 3145,
3161
    STV_i16_v2_areg = 3146,
3162
    STV_i16_v2_areg_64  = 3147,
3163
    STV_i16_v2_ari  = 3148,
3164
    STV_i16_v2_ari_64 = 3149,
3165
    STV_i16_v2_asi  = 3150,
3166
    STV_i16_v2_avar = 3151,
3167
    STV_i16_v4_areg = 3152,
3168
    STV_i16_v4_areg_64  = 3153,
3169
    STV_i16_v4_ari  = 3154,
3170
    STV_i16_v4_ari_64 = 3155,
3171
    STV_i16_v4_asi  = 3156,
3172
    STV_i16_v4_avar = 3157,
3173
    STV_i32_v2_areg = 3158,
3174
    STV_i32_v2_areg_64  = 3159,
3175
    STV_i32_v2_ari  = 3160,
3176
    STV_i32_v2_ari_64 = 3161,
3177
    STV_i32_v2_asi  = 3162,
3178
    STV_i32_v2_avar = 3163,
3179
    STV_i32_v4_areg = 3164,
3180
    STV_i32_v4_areg_64  = 3165,
3181
    STV_i32_v4_ari  = 3166,
3182
    STV_i32_v4_ari_64 = 3167,
3183
    STV_i32_v4_asi  = 3168,
3184
    STV_i32_v4_avar = 3169,
3185
    STV_i64_v2_areg = 3170,
3186
    STV_i64_v2_areg_64  = 3171,
3187
    STV_i64_v2_ari  = 3172,
3188
    STV_i64_v2_ari_64 = 3173,
3189
    STV_i64_v2_asi  = 3174,
3190
    STV_i64_v2_avar = 3175,
3191
    STV_i64_v4_areg = 3176,
3192
    STV_i64_v4_areg_64  = 3177,
3193
    STV_i64_v4_ari  = 3178,
3194
    STV_i64_v4_ari_64 = 3179,
3195
    STV_i64_v4_asi  = 3180,
3196
    STV_i64_v4_avar = 3181,
3197
    STV_i8_v2_areg  = 3182,
3198
    STV_i8_v2_areg_64 = 3183,
3199
    STV_i8_v2_ari = 3184,
3200
    STV_i8_v2_ari_64  = 3185,
3201
    STV_i8_v2_asi = 3186,
3202
    STV_i8_v2_avar  = 3187,
3203
    STV_i8_v4_areg  = 3188,
3204
    STV_i8_v4_areg_64 = 3189,
3205
    STV_i8_v4_ari = 3190,
3206
    STV_i8_v4_ari_64  = 3191,
3207
    STV_i8_v4_asi = 3192,
3208
    STV_i8_v4_avar  = 3193,
3209
    ST_f16_areg = 3194,
3210
    ST_f16_areg_64  = 3195,
3211
    ST_f16_ari  = 3196,
3212
    ST_f16_ari_64 = 3197,
3213
    ST_f16_asi  = 3198,
3214
    ST_f16_avar = 3199,
3215
    ST_f16x2_areg = 3200,
3216
    ST_f16x2_areg_64  = 3201,
3217
    ST_f16x2_ari  = 3202,
3218
    ST_f16x2_ari_64 = 3203,
3219
    ST_f16x2_asi  = 3204,
3220
    ST_f16x2_avar = 3205,
3221
    ST_f32_areg = 3206,
3222
    ST_f32_areg_64  = 3207,
3223
    ST_f32_ari  = 3208,
3224
    ST_f32_ari_64 = 3209,
3225
    ST_f32_asi  = 3210,
3226
    ST_f32_avar = 3211,
3227
    ST_f64_areg = 3212,
3228
    ST_f64_areg_64  = 3213,
3229
    ST_f64_ari  = 3214,
3230
    ST_f64_ari_64 = 3215,
3231
    ST_f64_asi  = 3216,
3232
    ST_f64_avar = 3217,
3233
    ST_i16_areg = 3218,
3234
    ST_i16_areg_64  = 3219,
3235
    ST_i16_ari  = 3220,
3236
    ST_i16_ari_64 = 3221,
3237
    ST_i16_asi  = 3222,
3238
    ST_i16_avar = 3223,
3239
    ST_i32_areg = 3224,
3240
    ST_i32_areg_64  = 3225,
3241
    ST_i32_ari  = 3226,
3242
    ST_i32_ari_64 = 3227,
3243
    ST_i32_asi  = 3228,
3244
    ST_i32_avar = 3229,
3245
    ST_i64_areg = 3230,
3246
    ST_i64_areg_64  = 3231,
3247
    ST_i64_ari  = 3232,
3248
    ST_i64_ari_64 = 3233,
3249
    ST_i64_asi  = 3234,
3250
    ST_i64_avar = 3235,
3251
    ST_i8_areg  = 3236,
3252
    ST_i8_areg_64 = 3237,
3253
    ST_i8_ari = 3238,
3254
    ST_i8_ari_64  = 3239,
3255
    ST_i8_asi = 3240,
3256
    ST_i8_avar  = 3241,
3257
    SUBCCCi32ri = 3242,
3258
    SUBCCCi32rr = 3243,
3259
    SUBCCi32ri  = 3244,
3260
    SUBCCi32rr  = 3245,
3261
    SUB_i1_ri = 3246,
3262
    SUB_i1_rr = 3247,
3263
    SUBi16ri  = 3248,
3264
    SUBi16rr  = 3249,
3265
    SUBi32ri  = 3250,
3266
    SUBi32rr  = 3251,
3267
    SUBi64ri  = 3252,
3268
    SUBi64rr  = 3253,
3269
    SULD_1D_ARRAY_I16_CLAMP = 3254,
3270
    SULD_1D_ARRAY_I16_TRAP  = 3255,
3271
    SULD_1D_ARRAY_I16_ZERO  = 3256,
3272
    SULD_1D_ARRAY_I32_CLAMP = 3257,
3273
    SULD_1D_ARRAY_I32_TRAP  = 3258,
3274
    SULD_1D_ARRAY_I32_ZERO  = 3259,
3275
    SULD_1D_ARRAY_I64_CLAMP = 3260,
3276
    SULD_1D_ARRAY_I64_TRAP  = 3261,
3277
    SULD_1D_ARRAY_I64_ZERO  = 3262,
3278
    SULD_1D_ARRAY_I8_CLAMP  = 3263,
3279
    SULD_1D_ARRAY_I8_TRAP = 3264,
3280
    SULD_1D_ARRAY_I8_ZERO = 3265,
3281
    SULD_1D_ARRAY_V2I16_CLAMP = 3266,
3282
    SULD_1D_ARRAY_V2I16_TRAP  = 3267,
3283
    SULD_1D_ARRAY_V2I16_ZERO  = 3268,
3284
    SULD_1D_ARRAY_V2I32_CLAMP = 3269,
3285
    SULD_1D_ARRAY_V2I32_TRAP  = 3270,
3286
    SULD_1D_ARRAY_V2I32_ZERO  = 3271,
3287
    SULD_1D_ARRAY_V2I64_CLAMP = 3272,
3288
    SULD_1D_ARRAY_V2I64_TRAP  = 3273,
3289
    SULD_1D_ARRAY_V2I64_ZERO  = 3274,
3290
    SULD_1D_ARRAY_V2I8_CLAMP  = 3275,
3291
    SULD_1D_ARRAY_V2I8_TRAP = 3276,
3292
    SULD_1D_ARRAY_V2I8_ZERO = 3277,
3293
    SULD_1D_ARRAY_V4I16_CLAMP = 3278,
3294
    SULD_1D_ARRAY_V4I16_TRAP  = 3279,
3295
    SULD_1D_ARRAY_V4I16_ZERO  = 3280,
3296
    SULD_1D_ARRAY_V4I32_CLAMP = 3281,
3297
    SULD_1D_ARRAY_V4I32_TRAP  = 3282,
3298
    SULD_1D_ARRAY_V4I32_ZERO  = 3283,
3299
    SULD_1D_ARRAY_V4I8_CLAMP  = 3284,
3300
    SULD_1D_ARRAY_V4I8_TRAP = 3285,
3301
    SULD_1D_ARRAY_V4I8_ZERO = 3286,
3302
    SULD_1D_I16_CLAMP = 3287,
3303
    SULD_1D_I16_TRAP  = 3288,
3304
    SULD_1D_I16_ZERO  = 3289,
3305
    SULD_1D_I32_CLAMP = 3290,
3306
    SULD_1D_I32_TRAP  = 3291,
3307
    SULD_1D_I32_ZERO  = 3292,
3308
    SULD_1D_I64_CLAMP = 3293,
3309
    SULD_1D_I64_TRAP  = 3294,
3310
    SULD_1D_I64_ZERO  = 3295,
3311
    SULD_1D_I8_CLAMP  = 3296,
3312
    SULD_1D_I8_TRAP = 3297,
3313
    SULD_1D_I8_ZERO = 3298,
3314
    SULD_1D_V2I16_CLAMP = 3299,
3315
    SULD_1D_V2I16_TRAP  = 3300,
3316
    SULD_1D_V2I16_ZERO  = 3301,
3317
    SULD_1D_V2I32_CLAMP = 3302,
3318
    SULD_1D_V2I32_TRAP  = 3303,
3319
    SULD_1D_V2I32_ZERO  = 3304,
3320
    SULD_1D_V2I64_CLAMP = 3305,
3321
    SULD_1D_V2I64_TRAP  = 3306,
3322
    SULD_1D_V2I64_ZERO  = 3307,
3323
    SULD_1D_V2I8_CLAMP  = 3308,
3324
    SULD_1D_V2I8_TRAP = 3309,
3325
    SULD_1D_V2I8_ZERO = 3310,
3326
    SULD_1D_V4I16_CLAMP = 3311,
3327
    SULD_1D_V4I16_TRAP  = 3312,
3328
    SULD_1D_V4I16_ZERO  = 3313,
3329
    SULD_1D_V4I32_CLAMP = 3314,
3330
    SULD_1D_V4I32_TRAP  = 3315,
3331
    SULD_1D_V4I32_ZERO  = 3316,
3332
    SULD_1D_V4I8_CLAMP  = 3317,
3333
    SULD_1D_V4I8_TRAP = 3318,
3334
    SULD_1D_V4I8_ZERO = 3319,
3335
    SULD_2D_ARRAY_I16_CLAMP = 3320,
3336
    SULD_2D_ARRAY_I16_TRAP  = 3321,
3337
    SULD_2D_ARRAY_I16_ZERO  = 3322,
3338
    SULD_2D_ARRAY_I32_CLAMP = 3323,
3339
    SULD_2D_ARRAY_I32_TRAP  = 3324,
3340
    SULD_2D_ARRAY_I32_ZERO  = 3325,
3341
    SULD_2D_ARRAY_I64_CLAMP = 3326,
3342
    SULD_2D_ARRAY_I64_TRAP  = 3327,
3343
    SULD_2D_ARRAY_I64_ZERO  = 3328,
3344
    SULD_2D_ARRAY_I8_CLAMP  = 3329,
3345
    SULD_2D_ARRAY_I8_TRAP = 3330,
3346
    SULD_2D_ARRAY_I8_ZERO = 3331,
3347
    SULD_2D_ARRAY_V2I16_CLAMP = 3332,
3348
    SULD_2D_ARRAY_V2I16_TRAP  = 3333,
3349
    SULD_2D_ARRAY_V2I16_ZERO  = 3334,
3350
    SULD_2D_ARRAY_V2I32_CLAMP = 3335,
3351
    SULD_2D_ARRAY_V2I32_TRAP  = 3336,
3352
    SULD_2D_ARRAY_V2I32_ZERO  = 3337,
3353
    SULD_2D_ARRAY_V2I64_CLAMP = 3338,
3354
    SULD_2D_ARRAY_V2I64_TRAP  = 3339,
3355
    SULD_2D_ARRAY_V2I64_ZERO  = 3340,
3356
    SULD_2D_ARRAY_V2I8_CLAMP  = 3341,
3357
    SULD_2D_ARRAY_V2I8_TRAP = 3342,
3358
    SULD_2D_ARRAY_V2I8_ZERO = 3343,
3359
    SULD_2D_ARRAY_V4I16_CLAMP = 3344,
3360
    SULD_2D_ARRAY_V4I16_TRAP  = 3345,
3361
    SULD_2D_ARRAY_V4I16_ZERO  = 3346,
3362
    SULD_2D_ARRAY_V4I32_CLAMP = 3347,
3363
    SULD_2D_ARRAY_V4I32_TRAP  = 3348,
3364
    SULD_2D_ARRAY_V4I32_ZERO  = 3349,
3365
    SULD_2D_ARRAY_V4I8_CLAMP  = 3350,
3366
    SULD_2D_ARRAY_V4I8_TRAP = 3351,
3367
    SULD_2D_ARRAY_V4I8_ZERO = 3352,
3368
    SULD_2D_I16_CLAMP = 3353,
3369
    SULD_2D_I16_TRAP  = 3354,
3370
    SULD_2D_I16_ZERO  = 3355,
3371
    SULD_2D_I32_CLAMP = 3356,
3372
    SULD_2D_I32_TRAP  = 3357,
3373
    SULD_2D_I32_ZERO  = 3358,
3374
    SULD_2D_I64_CLAMP = 3359,
3375
    SULD_2D_I64_TRAP  = 3360,
3376
    SULD_2D_I64_ZERO  = 3361,
3377
    SULD_2D_I8_CLAMP  = 3362,
3378
    SULD_2D_I8_TRAP = 3363,
3379
    SULD_2D_I8_ZERO = 3364,
3380
    SULD_2D_V2I16_CLAMP = 3365,
3381
    SULD_2D_V2I16_TRAP  = 3366,
3382
    SULD_2D_V2I16_ZERO  = 3367,
3383
    SULD_2D_V2I32_CLAMP = 3368,
3384
    SULD_2D_V2I32_TRAP  = 3369,
3385
    SULD_2D_V2I32_ZERO  = 3370,
3386
    SULD_2D_V2I64_CLAMP = 3371,
3387
    SULD_2D_V2I64_TRAP  = 3372,
3388
    SULD_2D_V2I64_ZERO  = 3373,
3389
    SULD_2D_V2I8_CLAMP  = 3374,
3390
    SULD_2D_V2I8_TRAP = 3375,
3391
    SULD_2D_V2I8_ZERO = 3376,
3392
    SULD_2D_V4I16_CLAMP = 3377,
3393
    SULD_2D_V4I16_TRAP  = 3378,
3394
    SULD_2D_V4I16_ZERO  = 3379,
3395
    SULD_2D_V4I32_CLAMP = 3380,
3396
    SULD_2D_V4I32_TRAP  = 3381,
3397
    SULD_2D_V4I32_ZERO  = 3382,
3398
    SULD_2D_V4I8_CLAMP  = 3383,
3399
    SULD_2D_V4I8_TRAP = 3384,
3400
    SULD_2D_V4I8_ZERO = 3385,
3401
    SULD_3D_I16_CLAMP = 3386,
3402
    SULD_3D_I16_TRAP  = 3387,
3403
    SULD_3D_I16_ZERO  = 3388,
3404
    SULD_3D_I32_CLAMP = 3389,
3405
    SULD_3D_I32_TRAP  = 3390,
3406
    SULD_3D_I32_ZERO  = 3391,
3407
    SULD_3D_I64_CLAMP = 3392,
3408
    SULD_3D_I64_TRAP  = 3393,
3409
    SULD_3D_I64_ZERO  = 3394,
3410
    SULD_3D_I8_CLAMP  = 3395,
3411
    SULD_3D_I8_TRAP = 3396,
3412
    SULD_3D_I8_ZERO = 3397,
3413
    SULD_3D_V2I16_CLAMP = 3398,
3414
    SULD_3D_V2I16_TRAP  = 3399,
3415
    SULD_3D_V2I16_ZERO  = 3400,
3416
    SULD_3D_V2I32_CLAMP = 3401,
3417
    SULD_3D_V2I32_TRAP  = 3402,
3418
    SULD_3D_V2I32_ZERO  = 3403,
3419
    SULD_3D_V2I64_CLAMP = 3404,
3420
    SULD_3D_V2I64_TRAP  = 3405,
3421
    SULD_3D_V2I64_ZERO  = 3406,
3422
    SULD_3D_V2I8_CLAMP  = 3407,
3423
    SULD_3D_V2I8_TRAP = 3408,
3424
    SULD_3D_V2I8_ZERO = 3409,
3425
    SULD_3D_V4I16_CLAMP = 3410,
3426
    SULD_3D_V4I16_TRAP  = 3411,
3427
    SULD_3D_V4I16_ZERO  = 3412,
3428
    SULD_3D_V4I32_CLAMP = 3413,
3429
    SULD_3D_V4I32_TRAP  = 3414,
3430
    SULD_3D_V4I32_ZERO  = 3415,
3431
    SULD_3D_V4I8_CLAMP  = 3416,
3432
    SULD_3D_V4I8_TRAP = 3417,
3433
    SULD_3D_V4I8_ZERO = 3418,
3434
    SUQ_ARRAY_SIZE  = 3419,
3435
    SUQ_CHANNEL_DATA_TYPE = 3420,
3436
    SUQ_CHANNEL_ORDER = 3421,
3437
    SUQ_DEPTH = 3422,
3438
    SUQ_HEIGHT  = 3423,
3439
    SUQ_WIDTH = 3424,
3440
    SUST_B_1D_ARRAY_B16_CLAMP = 3425,
3441
    SUST_B_1D_ARRAY_B16_TRAP  = 3426,
3442
    SUST_B_1D_ARRAY_B16_ZERO  = 3427,
3443
    SUST_B_1D_ARRAY_B32_CLAMP = 3428,
3444
    SUST_B_1D_ARRAY_B32_TRAP  = 3429,
3445
    SUST_B_1D_ARRAY_B32_ZERO  = 3430,
3446
    SUST_B_1D_ARRAY_B64_CLAMP = 3431,
3447
    SUST_B_1D_ARRAY_B64_TRAP  = 3432,
3448
    SUST_B_1D_ARRAY_B64_ZERO  = 3433,
3449
    SUST_B_1D_ARRAY_B8_CLAMP  = 3434,
3450
    SUST_B_1D_ARRAY_B8_TRAP = 3435,
3451
    SUST_B_1D_ARRAY_B8_ZERO = 3436,
3452
    SUST_B_1D_ARRAY_V2B16_CLAMP = 3437,
3453
    SUST_B_1D_ARRAY_V2B16_TRAP  = 3438,
3454
    SUST_B_1D_ARRAY_V2B16_ZERO  = 3439,
3455
    SUST_B_1D_ARRAY_V2B32_CLAMP = 3440,
3456
    SUST_B_1D_ARRAY_V2B32_TRAP  = 3441,
3457
    SUST_B_1D_ARRAY_V2B32_ZERO  = 3442,
3458
    SUST_B_1D_ARRAY_V2B64_CLAMP = 3443,
3459
    SUST_B_1D_ARRAY_V2B64_TRAP  = 3444,
3460
    SUST_B_1D_ARRAY_V2B64_ZERO  = 3445,
3461
    SUST_B_1D_ARRAY_V2B8_CLAMP  = 3446,
3462
    SUST_B_1D_ARRAY_V2B8_TRAP = 3447,
3463
    SUST_B_1D_ARRAY_V2B8_ZERO = 3448,
3464
    SUST_B_1D_ARRAY_V4B16_CLAMP = 3449,
3465
    SUST_B_1D_ARRAY_V4B16_TRAP  = 3450,
3466
    SUST_B_1D_ARRAY_V4B16_ZERO  = 3451,
3467
    SUST_B_1D_ARRAY_V4B32_CLAMP = 3452,
3468
    SUST_B_1D_ARRAY_V4B32_TRAP  = 3453,
3469
    SUST_B_1D_ARRAY_V4B32_ZERO  = 3454,
3470
    SUST_B_1D_ARRAY_V4B8_CLAMP  = 3455,
3471
    SUST_B_1D_ARRAY_V4B8_TRAP = 3456,
3472
    SUST_B_1D_ARRAY_V4B8_ZERO = 3457,
3473
    SUST_B_1D_B16_CLAMP = 3458,
3474
    SUST_B_1D_B16_TRAP  = 3459,
3475
    SUST_B_1D_B16_ZERO  = 3460,
3476
    SUST_B_1D_B32_CLAMP = 3461,
3477
    SUST_B_1D_B32_TRAP  = 3462,
3478
    SUST_B_1D_B32_ZERO  = 3463,
3479
    SUST_B_1D_B64_CLAMP = 3464,
3480
    SUST_B_1D_B64_TRAP  = 3465,
3481
    SUST_B_1D_B64_ZERO  = 3466,
3482
    SUST_B_1D_B8_CLAMP  = 3467,
3483
    SUST_B_1D_B8_TRAP = 3468,
3484
    SUST_B_1D_B8_ZERO = 3469,
3485
    SUST_B_1D_V2B16_CLAMP = 3470,
3486
    SUST_B_1D_V2B16_TRAP  = 3471,
3487
    SUST_B_1D_V2B16_ZERO  = 3472,
3488
    SUST_B_1D_V2B32_CLAMP = 3473,
3489
    SUST_B_1D_V2B32_TRAP  = 3474,
3490
    SUST_B_1D_V2B32_ZERO  = 3475,
3491
    SUST_B_1D_V2B64_CLAMP = 3476,
3492
    SUST_B_1D_V2B64_TRAP  = 3477,
3493
    SUST_B_1D_V2B64_ZERO  = 3478,
3494
    SUST_B_1D_V2B8_CLAMP  = 3479,
3495
    SUST_B_1D_V2B8_TRAP = 3480,
3496
    SUST_B_1D_V2B8_ZERO = 3481,
3497
    SUST_B_1D_V4B16_CLAMP = 3482,
3498
    SUST_B_1D_V4B16_TRAP  = 3483,
3499
    SUST_B_1D_V4B16_ZERO  = 3484,
3500
    SUST_B_1D_V4B32_CLAMP = 3485,
3501
    SUST_B_1D_V4B32_TRAP  = 3486,
3502
    SUST_B_1D_V4B32_ZERO  = 3487,
3503
    SUST_B_1D_V4B8_CLAMP  = 3488,
3504
    SUST_B_1D_V4B8_TRAP = 3489,
3505
    SUST_B_1D_V4B8_ZERO = 3490,
3506
    SUST_B_2D_ARRAY_B16_CLAMP = 3491,
3507
    SUST_B_2D_ARRAY_B16_TRAP  = 3492,
3508
    SUST_B_2D_ARRAY_B16_ZERO  = 3493,
3509
    SUST_B_2D_ARRAY_B32_CLAMP = 3494,
3510
    SUST_B_2D_ARRAY_B32_TRAP  = 3495,
3511
    SUST_B_2D_ARRAY_B32_ZERO  = 3496,
3512
    SUST_B_2D_ARRAY_B64_CLAMP = 3497,
3513
    SUST_B_2D_ARRAY_B64_TRAP  = 3498,
3514
    SUST_B_2D_ARRAY_B64_ZERO  = 3499,
3515
    SUST_B_2D_ARRAY_B8_CLAMP  = 3500,
3516
    SUST_B_2D_ARRAY_B8_TRAP = 3501,
3517
    SUST_B_2D_ARRAY_B8_ZERO = 3502,
3518
    SUST_B_2D_ARRAY_V2B16_CLAMP = 3503,
3519
    SUST_B_2D_ARRAY_V2B16_TRAP  = 3504,
3520
    SUST_B_2D_ARRAY_V2B16_ZERO  = 3505,
3521
    SUST_B_2D_ARRAY_V2B32_CLAMP = 3506,
3522
    SUST_B_2D_ARRAY_V2B32_TRAP  = 3507,
3523
    SUST_B_2D_ARRAY_V2B32_ZERO  = 3508,
3524
    SUST_B_2D_ARRAY_V2B64_CLAMP = 3509,
3525
    SUST_B_2D_ARRAY_V2B64_TRAP  = 3510,
3526
    SUST_B_2D_ARRAY_V2B64_ZERO  = 3511,
3527
    SUST_B_2D_ARRAY_V2B8_CLAMP  = 3512,
3528
    SUST_B_2D_ARRAY_V2B8_TRAP = 3513,
3529
    SUST_B_2D_ARRAY_V2B8_ZERO = 3514,
3530
    SUST_B_2D_ARRAY_V4B16_CLAMP = 3515,
3531
    SUST_B_2D_ARRAY_V4B16_TRAP  = 3516,
3532
    SUST_B_2D_ARRAY_V4B16_ZERO  = 3517,
3533
    SUST_B_2D_ARRAY_V4B32_CLAMP = 3518,
3534
    SUST_B_2D_ARRAY_V4B32_TRAP  = 3519,
3535
    SUST_B_2D_ARRAY_V4B32_ZERO  = 3520,
3536
    SUST_B_2D_ARRAY_V4B8_CLAMP  = 3521,
3537
    SUST_B_2D_ARRAY_V4B8_TRAP = 3522,
3538
    SUST_B_2D_ARRAY_V4B8_ZERO = 3523,
3539
    SUST_B_2D_B16_CLAMP = 3524,
3540
    SUST_B_2D_B16_TRAP  = 3525,
3541
    SUST_B_2D_B16_ZERO  = 3526,
3542
    SUST_B_2D_B32_CLAMP = 3527,
3543
    SUST_B_2D_B32_TRAP  = 3528,
3544
    SUST_B_2D_B32_ZERO  = 3529,
3545
    SUST_B_2D_B64_CLAMP = 3530,
3546
    SUST_B_2D_B64_TRAP  = 3531,
3547
    SUST_B_2D_B64_ZERO  = 3532,
3548
    SUST_B_2D_B8_CLAMP  = 3533,
3549
    SUST_B_2D_B8_TRAP = 3534,
3550
    SUST_B_2D_B8_ZERO = 3535,
3551
    SUST_B_2D_V2B16_CLAMP = 3536,
3552
    SUST_B_2D_V2B16_TRAP  = 3537,
3553
    SUST_B_2D_V2B16_ZERO  = 3538,
3554
    SUST_B_2D_V2B32_CLAMP = 3539,
3555
    SUST_B_2D_V2B32_TRAP  = 3540,
3556
    SUST_B_2D_V2B32_ZERO  = 3541,
3557
    SUST_B_2D_V2B64_CLAMP = 3542,
3558
    SUST_B_2D_V2B64_TRAP  = 3543,
3559
    SUST_B_2D_V2B64_ZERO  = 3544,
3560
    SUST_B_2D_V2B8_CLAMP  = 3545,
3561
    SUST_B_2D_V2B8_TRAP = 3546,
3562
    SUST_B_2D_V2B8_ZERO = 3547,
3563
    SUST_B_2D_V4B16_CLAMP = 3548,
3564
    SUST_B_2D_V4B16_TRAP  = 3549,
3565
    SUST_B_2D_V4B16_ZERO  = 3550,
3566
    SUST_B_2D_V4B32_CLAMP = 3551,
3567
    SUST_B_2D_V4B32_TRAP  = 3552,
3568
    SUST_B_2D_V4B32_ZERO  = 3553,
3569
    SUST_B_2D_V4B8_CLAMP  = 3554,
3570
    SUST_B_2D_V4B8_TRAP = 3555,
3571
    SUST_B_2D_V4B8_ZERO = 3556,
3572
    SUST_B_3D_B16_CLAMP = 3557,
3573
    SUST_B_3D_B16_TRAP  = 3558,
3574
    SUST_B_3D_B16_ZERO  = 3559,
3575
    SUST_B_3D_B32_CLAMP = 3560,
3576
    SUST_B_3D_B32_TRAP  = 3561,
3577
    SUST_B_3D_B32_ZERO  = 3562,
3578
    SUST_B_3D_B64_CLAMP = 3563,
3579
    SUST_B_3D_B64_TRAP  = 3564,
3580
    SUST_B_3D_B64_ZERO  = 3565,
3581
    SUST_B_3D_B8_CLAMP  = 3566,
3582
    SUST_B_3D_B8_TRAP = 3567,
3583
    SUST_B_3D_B8_ZERO = 3568,
3584
    SUST_B_3D_V2B16_CLAMP = 3569,
3585
    SUST_B_3D_V2B16_TRAP  = 3570,
3586
    SUST_B_3D_V2B16_ZERO  = 3571,
3587
    SUST_B_3D_V2B32_CLAMP = 3572,
3588
    SUST_B_3D_V2B32_TRAP  = 3573,
3589
    SUST_B_3D_V2B32_ZERO  = 3574,
3590
    SUST_B_3D_V2B64_CLAMP = 3575,
3591
    SUST_B_3D_V2B64_TRAP  = 3576,
3592
    SUST_B_3D_V2B64_ZERO  = 3577,
3593
    SUST_B_3D_V2B8_CLAMP  = 3578,
3594
    SUST_B_3D_V2B8_TRAP = 3579,
3595
    SUST_B_3D_V2B8_ZERO = 3580,
3596
    SUST_B_3D_V4B16_CLAMP = 3581,
3597
    SUST_B_3D_V4B16_TRAP  = 3582,
3598
    SUST_B_3D_V4B16_ZERO  = 3583,
3599
    SUST_B_3D_V4B32_CLAMP = 3584,
3600
    SUST_B_3D_V4B32_TRAP  = 3585,
3601
    SUST_B_3D_V4B32_ZERO  = 3586,
3602
    SUST_B_3D_V4B8_CLAMP  = 3587,
3603
    SUST_B_3D_V4B8_TRAP = 3588,
3604
    SUST_B_3D_V4B8_ZERO = 3589,
3605
    SUST_P_1D_ARRAY_B16_TRAP  = 3590,
3606
    SUST_P_1D_ARRAY_B32_TRAP  = 3591,
3607
    SUST_P_1D_ARRAY_B8_TRAP = 3592,
3608
    SUST_P_1D_ARRAY_V2B16_TRAP  = 3593,
3609
    SUST_P_1D_ARRAY_V2B32_TRAP  = 3594,
3610
    SUST_P_1D_ARRAY_V2B8_TRAP = 3595,
3611
    SUST_P_1D_ARRAY_V4B16_TRAP  = 3596,
3612
    SUST_P_1D_ARRAY_V4B32_TRAP  = 3597,
3613
    SUST_P_1D_ARRAY_V4B8_TRAP = 3598,
3614
    SUST_P_1D_B16_TRAP  = 3599,
3615
    SUST_P_1D_B32_TRAP  = 3600,
3616
    SUST_P_1D_B8_TRAP = 3601,
3617
    SUST_P_1D_V2B16_TRAP  = 3602,
3618
    SUST_P_1D_V2B32_TRAP  = 3603,
3619
    SUST_P_1D_V2B8_TRAP = 3604,
3620
    SUST_P_1D_V4B16_TRAP  = 3605,
3621
    SUST_P_1D_V4B32_TRAP  = 3606,
3622
    SUST_P_1D_V4B8_TRAP = 3607,
3623
    SUST_P_2D_ARRAY_B16_TRAP  = 3608,
3624
    SUST_P_2D_ARRAY_B32_TRAP  = 3609,
3625
    SUST_P_2D_ARRAY_B8_TRAP = 3610,
3626
    SUST_P_2D_ARRAY_V2B16_TRAP  = 3611,
3627
    SUST_P_2D_ARRAY_V2B32_TRAP  = 3612,
3628
    SUST_P_2D_ARRAY_V2B8_TRAP = 3613,
3629
    SUST_P_2D_ARRAY_V4B16_TRAP  = 3614,
3630
    SUST_P_2D_ARRAY_V4B32_TRAP  = 3615,
3631
    SUST_P_2D_ARRAY_V4B8_TRAP = 3616,
3632
    SUST_P_2D_B16_TRAP  = 3617,
3633
    SUST_P_2D_B32_TRAP  = 3618,
3634
    SUST_P_2D_B8_TRAP = 3619,
3635
    SUST_P_2D_V2B16_TRAP  = 3620,
3636
    SUST_P_2D_V2B32_TRAP  = 3621,
3637
    SUST_P_2D_V2B8_TRAP = 3622,
3638
    SUST_P_2D_V4B16_TRAP  = 3623,
3639
    SUST_P_2D_V4B32_TRAP  = 3624,
3640
    SUST_P_2D_V4B8_TRAP = 3625,
3641
    SUST_P_3D_B16_TRAP  = 3626,
3642
    SUST_P_3D_B32_TRAP  = 3627,
3643
    SUST_P_3D_B8_TRAP = 3628,
3644
    SUST_P_3D_V2B16_TRAP  = 3629,
3645
    SUST_P_3D_V2B32_TRAP  = 3630,
3646
    SUST_P_3D_V2B8_TRAP = 3631,
3647
    SUST_P_3D_V4B16_TRAP  = 3632,
3648
    SUST_P_3D_V4B32_TRAP  = 3633,
3649
    SUST_P_3D_V4B8_TRAP = 3634,
3650
    SplitF16x2  = 3635,
3651
    SplitI32toF16x2 = 3636,
3652
    StoreParamF16 = 3637,
3653
    StoreParamF16x2 = 3638,
3654
    StoreParamF32 = 3639,
3655
    StoreParamF64 = 3640,
3656
    StoreParamI16 = 3641,
3657
    StoreParamI32 = 3642,
3658
    StoreParamI64 = 3643,
3659
    StoreParamI8  = 3644,
3660
    StoreParamV2F16 = 3645,
3661
    StoreParamV2F16x2 = 3646,
3662
    StoreParamV2F32 = 3647,
3663
    StoreParamV2F64 = 3648,
3664
    StoreParamV2I16 = 3649,
3665
    StoreParamV2I32 = 3650,
3666
    StoreParamV2I64 = 3651,
3667
    StoreParamV2I8  = 3652,
3668
    StoreParamV4F16 = 3653,
3669
    StoreParamV4F16x2 = 3654,
3670
    StoreParamV4F32 = 3655,
3671
    StoreParamV4I16 = 3656,
3672
    StoreParamV4I32 = 3657,
3673
    StoreParamV4I8  = 3658,
3674
    StoreRetvalF16  = 3659,
3675
    StoreRetvalF16x2  = 3660,
3676
    StoreRetvalF32  = 3661,
3677
    StoreRetvalF64  = 3662,
3678
    StoreRetvalI16  = 3663,
3679
    StoreRetvalI32  = 3664,
3680
    StoreRetvalI64  = 3665,
3681
    StoreRetvalI8 = 3666,
3682
    StoreRetvalV2F16  = 3667,
3683
    StoreRetvalV2F16x2  = 3668,
3684
    StoreRetvalV2F32  = 3669,
3685
    StoreRetvalV2F64  = 3670,
3686
    StoreRetvalV2I16  = 3671,
3687
    StoreRetvalV2I32  = 3672,
3688
    StoreRetvalV2I64  = 3673,
3689
    StoreRetvalV2I8 = 3674,
3690
    StoreRetvalV4F16  = 3675,
3691
    StoreRetvalV4F16x2  = 3676,
3692
    StoreRetvalV4F32  = 3677,
3693
    StoreRetvalV4I16  = 3678,
3694
    StoreRetvalV4I32  = 3679,
3695
    StoreRetvalV4I8 = 3680,
3696
    TEX_1D_ARRAY_F32_F32  = 3681,
3697
    TEX_1D_ARRAY_F32_F32_GRAD = 3682,
3698
    TEX_1D_ARRAY_F32_F32_LEVEL  = 3683,
3699
    TEX_1D_ARRAY_F32_S32  = 3684,
3700
    TEX_1D_ARRAY_S32_F32  = 3685,
3701
    TEX_1D_ARRAY_S32_F32_GRAD = 3686,
3702
    TEX_1D_ARRAY_S32_F32_LEVEL  = 3687,
3703
    TEX_1D_ARRAY_S32_S32  = 3688,
3704
    TEX_1D_ARRAY_U32_F32  = 3689,
3705
    TEX_1D_ARRAY_U32_F32_GRAD = 3690,
3706
    TEX_1D_ARRAY_U32_F32_LEVEL  = 3691,
3707
    TEX_1D_ARRAY_U32_S32  = 3692,
3708
    TEX_1D_F32_F32  = 3693,
3709
    TEX_1D_F32_F32_GRAD = 3694,
3710
    TEX_1D_F32_F32_LEVEL  = 3695,
3711
    TEX_1D_F32_S32  = 3696,
3712
    TEX_1D_S32_F32  = 3697,
3713
    TEX_1D_S32_F32_GRAD = 3698,
3714
    TEX_1D_S32_F32_LEVEL  = 3699,
3715
    TEX_1D_S32_S32  = 3700,
3716
    TEX_1D_U32_F32  = 3701,
3717
    TEX_1D_U32_F32_GRAD = 3702,
3718
    TEX_1D_U32_F32_LEVEL  = 3703,
3719
    TEX_1D_U32_S32  = 3704,
3720
    TEX_2D_ARRAY_F32_F32  = 3705,
3721
    TEX_2D_ARRAY_F32_F32_GRAD = 3706,
3722
    TEX_2D_ARRAY_F32_F32_LEVEL  = 3707,
3723
    TEX_2D_ARRAY_F32_S32  = 3708,
3724
    TEX_2D_ARRAY_S32_F32  = 3709,
3725
    TEX_2D_ARRAY_S32_F32_GRAD = 3710,
3726
    TEX_2D_ARRAY_S32_F32_LEVEL  = 3711,
3727
    TEX_2D_ARRAY_S32_S32  = 3712,
3728
    TEX_2D_ARRAY_U32_F32  = 3713,
3729
    TEX_2D_ARRAY_U32_F32_GRAD = 3714,
3730
    TEX_2D_ARRAY_U32_F32_LEVEL  = 3715,
3731
    TEX_2D_ARRAY_U32_S32  = 3716,
3732
    TEX_2D_F32_F32  = 3717,
3733
    TEX_2D_F32_F32_GRAD = 3718,
3734
    TEX_2D_F32_F32_LEVEL  = 3719,
3735
    TEX_2D_F32_S32  = 3720,
3736
    TEX_2D_S32_F32  = 3721,
3737
    TEX_2D_S32_F32_GRAD = 3722,
3738
    TEX_2D_S32_F32_LEVEL  = 3723,
3739
    TEX_2D_S32_S32  = 3724,
3740
    TEX_2D_U32_F32  = 3725,
3741
    TEX_2D_U32_F32_GRAD = 3726,
3742
    TEX_2D_U32_F32_LEVEL  = 3727,
3743
    TEX_2D_U32_S32  = 3728,
3744
    TEX_3D_F32_F32  = 3729,
3745
    TEX_3D_F32_F32_GRAD = 3730,
3746
    TEX_3D_F32_F32_LEVEL  = 3731,
3747
    TEX_3D_F32_S32  = 3732,
3748
    TEX_3D_S32_F32  = 3733,
3749
    TEX_3D_S32_F32_GRAD = 3734,
3750
    TEX_3D_S32_F32_LEVEL  = 3735,
3751
    TEX_3D_S32_S32  = 3736,
3752
    TEX_3D_U32_F32  = 3737,
3753
    TEX_3D_U32_F32_GRAD = 3738,
3754
    TEX_3D_U32_F32_LEVEL  = 3739,
3755
    TEX_3D_U32_S32  = 3740,
3756
    TEX_CUBE_ARRAY_F32_F32  = 3741,
3757
    TEX_CUBE_ARRAY_F32_F32_LEVEL  = 3742,
3758
    TEX_CUBE_ARRAY_S32_F32  = 3743,
3759
    TEX_CUBE_ARRAY_S32_F32_LEVEL  = 3744,
3760
    TEX_CUBE_ARRAY_U32_F32  = 3745,
3761
    TEX_CUBE_ARRAY_U32_F32_LEVEL  = 3746,
3762
    TEX_CUBE_F32_F32  = 3747,
3763
    TEX_CUBE_F32_F32_LEVEL  = 3748,
3764
    TEX_CUBE_S32_F32  = 3749,
3765
    TEX_CUBE_S32_F32_LEVEL  = 3750,
3766
    TEX_CUBE_U32_F32  = 3751,
3767
    TEX_CUBE_U32_F32_LEVEL  = 3752,
3768
    TEX_UNIFIED_1D_ARRAY_F32_F32  = 3753,
3769
    TEX_UNIFIED_1D_ARRAY_F32_F32_GRAD = 3754,
3770
    TEX_UNIFIED_1D_ARRAY_F32_F32_LEVEL  = 3755,
3771
    TEX_UNIFIED_1D_ARRAY_F32_S32  = 3756,
3772
    TEX_UNIFIED_1D_ARRAY_S32_F32  = 3757,
3773
    TEX_UNIFIED_1D_ARRAY_S32_F32_GRAD = 3758,
3774
    TEX_UNIFIED_1D_ARRAY_S32_F32_LEVEL  = 3759,
3775
    TEX_UNIFIED_1D_ARRAY_S32_S32  = 3760,
3776
    TEX_UNIFIED_1D_ARRAY_U32_F32  = 3761,
3777
    TEX_UNIFIED_1D_ARRAY_U32_F32_GRAD = 3762,
3778
    TEX_UNIFIED_1D_ARRAY_U32_F32_LEVEL  = 3763,
3779
    TEX_UNIFIED_1D_ARRAY_U32_S32  = 3764,
3780
    TEX_UNIFIED_1D_F32_F32  = 3765,
3781
    TEX_UNIFIED_1D_F32_F32_GRAD = 3766,
3782
    TEX_UNIFIED_1D_F32_F32_LEVEL  = 3767,
3783
    TEX_UNIFIED_1D_F32_S32  = 3768,
3784
    TEX_UNIFIED_1D_S32_F32  = 3769,
3785
    TEX_UNIFIED_1D_S32_F32_GRAD = 3770,
3786
    TEX_UNIFIED_1D_S32_F32_LEVEL  = 3771,
3787
    TEX_UNIFIED_1D_S32_S32  = 3772,
3788
    TEX_UNIFIED_1D_U32_F32  = 3773,
3789
    TEX_UNIFIED_1D_U32_F32_GRAD = 3774,
3790
    TEX_UNIFIED_1D_U32_F32_LEVEL  = 3775,
3791
    TEX_UNIFIED_1D_U32_S32  = 3776,
3792
    TEX_UNIFIED_2D_ARRAY_F32_F32  = 3777,
3793
    TEX_UNIFIED_2D_ARRAY_F32_F32_GRAD = 3778,
3794
    TEX_UNIFIED_2D_ARRAY_F32_F32_LEVEL  = 3779,
3795
    TEX_UNIFIED_2D_ARRAY_F32_S32  = 3780,
3796
    TEX_UNIFIED_2D_ARRAY_S32_F32  = 3781,
3797
    TEX_UNIFIED_2D_ARRAY_S32_F32_GRAD = 3782,
3798
    TEX_UNIFIED_2D_ARRAY_S32_F32_LEVEL  = 3783,
3799
    TEX_UNIFIED_2D_ARRAY_S32_S32  = 3784,
3800
    TEX_UNIFIED_2D_ARRAY_U32_F32  = 3785,
3801
    TEX_UNIFIED_2D_ARRAY_U32_F32_GRAD = 3786,
3802
    TEX_UNIFIED_2D_ARRAY_U32_F32_LEVEL  = 3787,
3803
    TEX_UNIFIED_2D_ARRAY_U32_S32  = 3788,
3804
    TEX_UNIFIED_2D_F32_F32  = 3789,
3805
    TEX_UNIFIED_2D_F32_F32_GRAD = 3790,
3806
    TEX_UNIFIED_2D_F32_F32_LEVEL  = 3791,
3807
    TEX_UNIFIED_2D_F32_S32  = 3792,
3808
    TEX_UNIFIED_2D_S32_F32  = 3793,
3809
    TEX_UNIFIED_2D_S32_F32_GRAD = 3794,
3810
    TEX_UNIFIED_2D_S32_F32_LEVEL  = 3795,
3811
    TEX_UNIFIED_2D_S32_S32  = 3796,
3812
    TEX_UNIFIED_2D_U32_F32  = 3797,
3813
    TEX_UNIFIED_2D_U32_F32_GRAD = 3798,
3814
    TEX_UNIFIED_2D_U32_F32_LEVEL  = 3799,
3815
    TEX_UNIFIED_2D_U32_S32  = 3800,
3816
    TEX_UNIFIED_3D_F32_F32  = 3801,
3817
    TEX_UNIFIED_3D_F32_F32_GRAD = 3802,
3818
    TEX_UNIFIED_3D_F32_F32_LEVEL  = 3803,
3819
    TEX_UNIFIED_3D_F32_S32  = 3804,
3820
    TEX_UNIFIED_3D_S32_F32  = 3805,
3821
    TEX_UNIFIED_3D_S32_F32_GRAD = 3806,
3822
    TEX_UNIFIED_3D_S32_F32_LEVEL  = 3807,
3823
    TEX_UNIFIED_3D_S32_S32  = 3808,
3824
    TEX_UNIFIED_3D_U32_F32  = 3809,
3825
    TEX_UNIFIED_3D_U32_F32_GRAD = 3810,
3826
    TEX_UNIFIED_3D_U32_F32_LEVEL  = 3811,
3827
    TEX_UNIFIED_3D_U32_S32  = 3812,
3828
    TEX_UNIFIED_CUBE_ARRAY_F32_F32  = 3813,
3829
    TEX_UNIFIED_CUBE_ARRAY_F32_F32_LEVEL  = 3814,
3830
    TEX_UNIFIED_CUBE_ARRAY_S32_F32  = 3815,
3831
    TEX_UNIFIED_CUBE_ARRAY_S32_F32_LEVEL  = 3816,
3832
    TEX_UNIFIED_CUBE_ARRAY_U32_F32  = 3817,
3833
    TEX_UNIFIED_CUBE_ARRAY_U32_F32_LEVEL  = 3818,
3834
    TEX_UNIFIED_CUBE_F32_F32  = 3819,
3835
    TEX_UNIFIED_CUBE_F32_F32_LEVEL  = 3820,
3836
    TEX_UNIFIED_CUBE_S32_F32  = 3821,
3837
    TEX_UNIFIED_CUBE_S32_F32_LEVEL  = 3822,
3838
    TEX_UNIFIED_CUBE_U32_F32  = 3823,
3839
    TEX_UNIFIED_CUBE_U32_F32_LEVEL  = 3824,
3840
    TLD4_A_2D_F32_F32 = 3825,
3841
    TLD4_A_2D_S32_F32 = 3826,
3842
    TLD4_A_2D_U32_F32 = 3827,
3843
    TLD4_B_2D_F32_F32 = 3828,
3844
    TLD4_B_2D_S32_F32 = 3829,
3845
    TLD4_B_2D_U32_F32 = 3830,
3846
    TLD4_G_2D_F32_F32 = 3831,
3847
    TLD4_G_2D_S32_F32 = 3832,
3848
    TLD4_G_2D_U32_F32 = 3833,
3849
    TLD4_R_2D_F32_F32 = 3834,
3850
    TLD4_R_2D_S32_F32 = 3835,
3851
    TLD4_R_2D_U32_F32 = 3836,
3852
    TLD4_UNIFIED_A_2D_F32_F32 = 3837,
3853
    TLD4_UNIFIED_A_2D_S32_F32 = 3838,
3854
    TLD4_UNIFIED_A_2D_U32_F32 = 3839,
3855
    TLD4_UNIFIED_B_2D_F32_F32 = 3840,
3856
    TLD4_UNIFIED_B_2D_S32_F32 = 3841,
3857
    TLD4_UNIFIED_B_2D_U32_F32 = 3842,
3858
    TLD4_UNIFIED_G_2D_F32_F32 = 3843,
3859
    TLD4_UNIFIED_G_2D_S32_F32 = 3844,
3860
    TLD4_UNIFIED_G_2D_U32_F32 = 3845,
3861
    TLD4_UNIFIED_R_2D_F32_F32 = 3846,
3862
    TLD4_UNIFIED_R_2D_S32_F32 = 3847,
3863
    TLD4_UNIFIED_R_2D_U32_F32 = 3848,
3864
    TXQ_ARRAY_SIZE  = 3849,
3865
    TXQ_CHANNEL_DATA_TYPE = 3850,
3866
    TXQ_CHANNEL_ORDER = 3851,
3867
    TXQ_DEPTH = 3852,
3868
    TXQ_HEIGHT  = 3853,
3869
    TXQ_NUM_MIPMAP_LEVELS = 3854,
3870
    TXQ_NUM_SAMPLES = 3855,
3871
    TXQ_WIDTH = 3856,
3872
    UDIVi16ri = 3857,
3873
    UDIVi16rr = 3858,
3874
    UDIVi32ri = 3859,
3875
    UDIVi32rr = 3860,
3876
    UDIVi64ri = 3861,
3877
    UDIVi64rr = 3862,
3878
    UMAXi16ri = 3863,
3879
    UMAXi16rr = 3864,
3880
    UMAXi32ri = 3865,
3881
    UMAXi32rr = 3866,
3882
    UMAXi64ri = 3867,
3883
    UMAXi64rr = 3868,
3884
    UMINi16ri = 3869,
3885
    UMINi16rr = 3870,
3886
    UMINi32ri = 3871,
3887
    UMINi32rr = 3872,
3888
    UMINi64ri = 3873,
3889
    UMINi64rr = 3874,
3890
    UREMi16ri = 3875,
3891
    UREMi16rr = 3876,
3892
    UREMi32ri = 3877,
3893
    UREMi32rr = 3878,
3894
    UREMi64ri = 3879,
3895
    UREMi64rr = 3880,
3896
    V2F32toF64  = 3881,
3897
    V2I16toI32  = 3882,
3898
    V2I32toI64  = 3883,
3899
    V4I16toI64  = 3884,
3900
    VOTE_SYNC_ALLi  = 3885,
3901
    VOTE_SYNC_ALLr  = 3886,
3902
    VOTE_SYNC_ANYi  = 3887,
3903
    VOTE_SYNC_ANYr  = 3888,
3904
    VOTE_SYNC_BALLOTi = 3889,
3905
    VOTE_SYNC_BALLOTr = 3890,
3906
    VOTE_SYNC_UNIi  = 3891,
3907
    VOTE_SYNC_UNIr  = 3892,
3908
    XORb16ri  = 3893,
3909
    XORb16rr  = 3894,
3910
    XORb1ri = 3895,
3911
    XORb1rr = 3896,
3912
    XORb32ri  = 3897,
3913
    XORb32rr  = 3898,
3914
    XORb64ri  = 3899,
3915
    XORb64rr  = 3900,
3916
    anonymous_1963  = 3901,
3917
    anonymous_1964  = 3902,
3918
    anonymous_1965  = 3903,
3919
    anonymous_1966  = 3904,
3920
    anonymous_2084  = 3905,
3921
    anonymous_2085  = 3906,
3922
    anonymous_2086  = 3907,
3923
    anonymous_2087  = 3908,
3924
    anonymous_2088  = 3909,
3925
    anonymous_2089  = 3910,
3926
    anonymous_2090  = 3911,
3927
    anonymous_2091  = 3912,
3928
    anonymous_2092  = 3913,
3929
    anonymous_2093  = 3914,
3930
    anonymous_2094  = 3915,
3931
    anonymous_2095  = 3916,
3932
    anonymous_2098  = 3917,
3933
    anonymous_2099  = 3918,
3934
    anonymous_2100  = 3919,
3935
    anonymous_2101  = 3920,
3936
    anonymous_2102  = 3921,
3937
    anonymous_2103  = 3922,
3938
    anonymous_2104  = 3923,
3939
    anonymous_2105  = 3924,
3940
    anonymous_2106  = 3925,
3941
    anonymous_2107  = 3926,
3942
    anonymous_2108  = 3927,
3943
    anonymous_2109  = 3928,
3944
    anonymous_2110  = 3929,
3945
    anonymous_2111  = 3930,
3946
    anonymous_2112  = 3931,
3947
    anonymous_2113  = 3932,
3948
    anonymous_2114  = 3933,
3949
    anonymous_2115  = 3934,
3950
    anonymous_2116  = 3935,
3951
    anonymous_2117  = 3936,
3952
    anonymous_2118  = 3937,
3953
    anonymous_2119  = 3938,
3954
    anonymous_2120  = 3939,
3955
    anonymous_2121  = 3940,
3956
    anonymous_2122  = 3941,
3957
    anonymous_2123  = 3942,
3958
    anonymous_2124  = 3943,
3959
    anonymous_2125  = 3944,
3960
    anonymous_2126  = 3945,
3961
    anonymous_2127  = 3946,
3962
    anonymous_2128  = 3947,
3963
    anonymous_2129  = 3948,
3964
    anonymous_2130  = 3949,
3965
    anonymous_2131  = 3950,
3966
    anonymous_2132  = 3951,
3967
    anonymous_2133  = 3952,
3968
    anonymous_2134  = 3953,
3969
    anonymous_2135  = 3954,
3970
    anonymous_2136  = 3955,
3971
    anonymous_2137  = 3956,
3972
    anonymous_2138  = 3957,
3973
    anonymous_2139  = 3958,
3974
    anonymous_2140  = 3959,
3975
    anonymous_2141  = 3960,
3976
    anonymous_2142  = 3961,
3977
    anonymous_2143  = 3962,
3978
    anonymous_2144  = 3963,
3979
    anonymous_2145  = 3964,
3980
    anonymous_2146  = 3965,
3981
    anonymous_2147  = 3966,
3982
    anonymous_2148  = 3967,
3983
    anonymous_2149  = 3968,
3984
    anonymous_2150  = 3969,
3985
    anonymous_2151  = 3970,
3986
    anonymous_2152  = 3971,
3987
    anonymous_2153  = 3972,
3988
    anonymous_2154  = 3973,
3989
    anonymous_2155  = 3974,
3990
    anonymous_2156  = 3975,
3991
    anonymous_2157  = 3976,
3992
    anonymous_2158  = 3977,
3993
    anonymous_2159  = 3978,
3994
    anonymous_2160  = 3979,
3995
    anonymous_2161  = 3980,
3996
    anonymous_2162  = 3981,
3997
    anonymous_2163  = 3982,
3998
    anonymous_2164  = 3983,
3999
    anonymous_2165  = 3984,
4000
    anonymous_2166  = 3985,
4001
    anonymous_2167  = 3986,
4002
    anonymous_2168  = 3987,
4003
    anonymous_2169  = 3988,
4004
    anonymous_2170  = 3989,
4005
    anonymous_2171  = 3990,
4006
    anonymous_2172  = 3991,
4007
    anonymous_2173  = 3992,
4008
    anonymous_2174  = 3993,
4009
    anonymous_2175  = 3994,
4010
    anonymous_2176  = 3995,
4011
    anonymous_2177  = 3996,
4012
    anonymous_2178  = 3997,
4013
    anonymous_2179  = 3998,
4014
    anonymous_2180  = 3999,
4015
    anonymous_2181  = 4000,
4016
    anonymous_2182  = 4001,
4017
    anonymous_2183  = 4002,
4018
    anonymous_2184  = 4003,
4019
    anonymous_2185  = 4004,
4020
    anonymous_2186  = 4005,
4021
    anonymous_2187  = 4006,
4022
    anonymous_2188  = 4007,
4023
    anonymous_2189  = 4008,
4024
    anonymous_2190  = 4009,
4025
    anonymous_2191  = 4010,
4026
    anonymous_2192  = 4011,
4027
    anonymous_2193  = 4012,
4028
    anonymous_2194  = 4013,
4029
    anonymous_2195  = 4014,
4030
    anonymous_2196  = 4015,
4031
    anonymous_2197  = 4016,
4032
    anonymous_2198  = 4017,
4033
    anonymous_2199  = 4018,
4034
    anonymous_2200  = 4019,
4035
    anonymous_2201  = 4020,
4036
    anonymous_2202  = 4021,
4037
    anonymous_2203  = 4022,
4038
    anonymous_2204  = 4023,
4039
    anonymous_2205  = 4024,
4040
    anonymous_2206  = 4025,
4041
    anonymous_2207  = 4026,
4042
    anonymous_2208  = 4027,
4043
    anonymous_2209  = 4028,
4044
    anonymous_2210  = 4029,
4045
    anonymous_2211  = 4030,
4046
    anonymous_2212  = 4031,
4047
    anonymous_2213  = 4032,
4048
    anonymous_2214  = 4033,
4049
    anonymous_2215  = 4034,
4050
    anonymous_2216  = 4035,
4051
    anonymous_2217  = 4036,
4052
    anonymous_2218  = 4037,
4053
    anonymous_2219  = 4038,
4054
    anonymous_2220  = 4039,
4055
    anonymous_2221  = 4040,
4056
    anonymous_2222  = 4041,
4057
    anonymous_2223  = 4042,
4058
    anonymous_2224  = 4043,
4059
    anonymous_2225  = 4044,
4060
    anonymous_2226  = 4045,
4061
    anonymous_2227  = 4046,
4062
    anonymous_2228  = 4047,
4063
    anonymous_2229  = 4048,
4064
    anonymous_2230  = 4049,
4065
    anonymous_2231  = 4050,
4066
    anonymous_2232  = 4051,
4067
    anonymous_2233  = 4052,
4068
    anonymous_2234  = 4053,
4069
    anonymous_2235  = 4054,
4070
    anonymous_2236  = 4055,
4071
    anonymous_2237  = 4056,
4072
    anonymous_2238  = 4057,
4073
    anonymous_2239  = 4058,
4074
    anonymous_2240  = 4059,
4075
    anonymous_2241  = 4060,
4076
    anonymous_2242  = 4061,
4077
    anonymous_2243  = 4062,
4078
    anonymous_2244  = 4063,
4079
    anonymous_2245  = 4064,
4080
    anonymous_2246  = 4065,
4081
    anonymous_2247  = 4066,
4082
    anonymous_2248  = 4067,
4083
    anonymous_2249  = 4068,
4084
    anonymous_2250  = 4069,
4085
    anonymous_2251  = 4070,
4086
    anonymous_2252  = 4071,
4087
    anonymous_2253  = 4072,
4088
    anonymous_2254  = 4073,
4089
    anonymous_2255  = 4074,
4090
    anonymous_2256  = 4075,
4091
    anonymous_2257  = 4076,
4092
    anonymous_2258  = 4077,
4093
    anonymous_2259  = 4078,
4094
    anonymous_2260  = 4079,
4095
    anonymous_2261  = 4080,
4096
    anonymous_2262  = 4081,
4097
    anonymous_2263  = 4082,
4098
    anonymous_2264  = 4083,
4099
    anonymous_2265  = 4084,
4100
    anonymous_2266  = 4085,
4101
    anonymous_2267  = 4086,
4102
    anonymous_2268  = 4087,
4103
    anonymous_2269  = 4088,
4104
    anonymous_2270  = 4089,
4105
    anonymous_2271  = 4090,
4106
    anonymous_2272  = 4091,
4107
    anonymous_2273  = 4092,
4108
    anonymous_2274  = 4093,
4109
    anonymous_2275  = 4094,
4110
    anonymous_2276  = 4095,
4111
    anonymous_2277  = 4096,
4112
    anonymous_2278  = 4097,
4113
    anonymous_2279  = 4098,
4114
    anonymous_2280  = 4099,
4115
    anonymous_2281  = 4100,
4116
    anonymous_2282  = 4101,
4117
    anonymous_2283  = 4102,
4118
    anonymous_2284  = 4103,
4119
    anonymous_2285  = 4104,
4120
    anonymous_2286  = 4105,
4121
    anonymous_2287  = 4106,
4122
    anonymous_2288  = 4107,
4123
    anonymous_2289  = 4108,
4124
    anonymous_2290  = 4109,
4125
    anonymous_2291  = 4110,
4126
    anonymous_2292  = 4111,
4127
    anonymous_2293  = 4112,
4128
    anonymous_2294  = 4113,
4129
    anonymous_2295  = 4114,
4130
    anonymous_2296  = 4115,
4131
    anonymous_2297  = 4116,
4132
    anonymous_2298  = 4117,
4133
    anonymous_2299  = 4118,
4134
    anonymous_2300  = 4119,
4135
    anonymous_2301  = 4120,
4136
    anonymous_942 = 4121,
4137
    anonymous_943 = 4122,
4138
    anonymous_944 = 4123,
4139
    cvta_const_yes  = 4124,
4140
    cvta_const_yes_64 = 4125,
4141
    cvta_const_yes_6432 = 4126,
4142
    cvta_global_yes = 4127,
4143
    cvta_global_yes_64  = 4128,
4144
    cvta_global_yes_6432  = 4129,
4145
    cvta_local_yes  = 4130,
4146
    cvta_local_yes_64 = 4131,
4147
    cvta_local_yes_6432 = 4132,
4148
    cvta_shared_yes = 4133,
4149
    cvta_shared_yes_64  = 4134,
4150
    cvta_shared_yes_6432  = 4135,
4151
    cvta_to_const_yes = 4136,
4152
    cvta_to_const_yes_3264  = 4137,
4153
    cvta_to_const_yes_64  = 4138,
4154
    cvta_to_global_yes  = 4139,
4155
    cvta_to_global_yes_3264 = 4140,
4156
    cvta_to_global_yes_64 = 4141,
4157
    cvta_to_local_yes = 4142,
4158
    cvta_to_local_yes_3264  = 4143,
4159
    cvta_to_local_yes_64  = 4144,
4160
    cvta_to_shared_yes  = 4145,
4161
    cvta_to_shared_yes_3264 = 4146,
4162
    cvta_to_shared_yes_64 = 4147,
4163
    nvvm_move_double  = 4148,
4164
    nvvm_move_float = 4149,
4165
    nvvm_move_i16 = 4150,
4166
    nvvm_move_i32 = 4151,
4167
    nvvm_move_i64 = 4152,
4168
    nvvm_move_ptr32 = 4153,
4169
    nvvm_move_ptr64 = 4154,
4170
    nvvm_ptr_gen_to_param = 4155,
4171
    nvvm_ptr_gen_to_param_64  = 4156,
4172
    texsurf_handles = 4157,
4173
    trapinst  = 4158,
4174
    INSTRUCTION_LIST_END = 4159
4175
  };
4176
4177
} // end NVPTX namespace
4178
} // end llvm namespace
4179
#endif // GET_INSTRINFO_ENUM
4180
4181
#ifdef GET_INSTRINFO_SCHED_ENUM
4182
#undef GET_INSTRINFO_SCHED_ENUM
4183
namespace llvm {
4184
4185
namespace NVPTX {
4186
namespace Sched {
4187
  enum {
4188
    NoInstrModel  = 0,
4189
    SCHED_LIST_END = 1
4190
  };
4191
} // end Sched namespace
4192
} // end NVPTX namespace
4193
} // end llvm namespace
4194
#endif // GET_INSTRINFO_SCHED_ENUM
4195
4196
#ifdef GET_INSTRINFO_MC_DESC
4197
#undef GET_INSTRINFO_MC_DESC
4198
namespace llvm {
4199
4200
4201
static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4202
static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4203
static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4204
static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4205
static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4206
static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4207
static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4208
static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4209
static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
4210
static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4211
static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4212
static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
4213
static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
4214
static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4215
static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4216
static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
4217
static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4218
static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
4219
static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
4220
static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
4221
static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
4222
static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
4223
static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
4224
static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
4225
static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
4226
static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4227
static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
4228
static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
4229
static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
4230
static const MCOperandInfo OperandInfo31[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4231
static const MCOperandInfo OperandInfo32[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4232
static const MCOperandInfo OperandInfo33[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4233
static const MCOperandInfo OperandInfo34[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4234
static const MCOperandInfo OperandInfo35[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4235
static const MCOperandInfo OperandInfo36[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4236
static const MCOperandInfo OperandInfo37[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4237
static const MCOperandInfo OperandInfo38[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4238
static const MCOperandInfo OperandInfo39[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4239
static const MCOperandInfo OperandInfo40[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4240
static const MCOperandInfo OperandInfo41[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4241
static const MCOperandInfo OperandInfo42[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4242
static const MCOperandInfo OperandInfo43[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4243
static const MCOperandInfo OperandInfo44[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4244
static const MCOperandInfo OperandInfo45[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4245
static const MCOperandInfo OperandInfo46[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4246
static const MCOperandInfo OperandInfo47[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4247
static const MCOperandInfo OperandInfo48[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4248
static const MCOperandInfo OperandInfo49[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4249
static const MCOperandInfo OperandInfo50[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4250
static const MCOperandInfo OperandInfo51[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4251
static const MCOperandInfo OperandInfo52[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4252
static const MCOperandInfo OperandInfo53[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4253
static const MCOperandInfo OperandInfo54[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4254
static const MCOperandInfo OperandInfo55[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4255
static const MCOperandInfo OperandInfo56[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4256
static const MCOperandInfo OperandInfo57[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4257
static const MCOperandInfo OperandInfo58[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4258
static const MCOperandInfo OperandInfo59[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4259
static const MCOperandInfo OperandInfo60[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4260
static const MCOperandInfo OperandInfo61[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4261
static const MCOperandInfo OperandInfo62[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4262
static const MCOperandInfo OperandInfo63[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4263
static const MCOperandInfo OperandInfo64[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4264
static const MCOperandInfo OperandInfo65[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4265
static const MCOperandInfo OperandInfo66[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4266
static const MCOperandInfo OperandInfo67[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4267
static const MCOperandInfo OperandInfo68[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4268
static const MCOperandInfo OperandInfo69[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4269
static const MCOperandInfo OperandInfo70[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4270
static const MCOperandInfo OperandInfo71[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4271
static const MCOperandInfo OperandInfo72[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4272
static const MCOperandInfo OperandInfo73[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4273
static const MCOperandInfo OperandInfo74[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4274
static const MCOperandInfo OperandInfo75[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4275
static const MCOperandInfo OperandInfo76[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4276
static const MCOperandInfo OperandInfo77[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4277
static const MCOperandInfo OperandInfo78[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4278
static const MCOperandInfo OperandInfo79[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4279
static const MCOperandInfo OperandInfo80[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4280
static const MCOperandInfo OperandInfo81[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4281
static const MCOperandInfo OperandInfo82[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4282
static const MCOperandInfo OperandInfo83[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4283
static const MCOperandInfo OperandInfo84[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4284
static const MCOperandInfo OperandInfo85[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4285
static const MCOperandInfo OperandInfo86[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4286
static const MCOperandInfo OperandInfo87[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4287
static const MCOperandInfo OperandInfo88[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4288
static const MCOperandInfo OperandInfo89[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4289
static const MCOperandInfo OperandInfo90[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4290
static const MCOperandInfo OperandInfo91[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4291
static const MCOperandInfo OperandInfo92[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4292
static const MCOperandInfo OperandInfo93[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4293
static const MCOperandInfo OperandInfo94[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4294
static const MCOperandInfo OperandInfo95[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4295
static const MCOperandInfo OperandInfo96[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4296
static const MCOperandInfo OperandInfo97[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4297
static const MCOperandInfo OperandInfo98[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4298
static const MCOperandInfo OperandInfo99[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4299
static const MCOperandInfo OperandInfo100[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4300
static const MCOperandInfo OperandInfo101[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4301
static const MCOperandInfo OperandInfo102[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4302
static const MCOperandInfo OperandInfo103[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4303
static const MCOperandInfo OperandInfo104[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4304
static const MCOperandInfo OperandInfo105[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4305
static const MCOperandInfo OperandInfo106[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4306
static const MCOperandInfo OperandInfo107[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4307
static const MCOperandInfo OperandInfo108[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4308
static const MCOperandInfo OperandInfo109[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4309
static const MCOperandInfo OperandInfo110[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4310
static const MCOperandInfo OperandInfo111[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4311
static const MCOperandInfo OperandInfo112[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4312
static const MCOperandInfo OperandInfo113[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4313
static const MCOperandInfo OperandInfo114[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4314
static const MCOperandInfo OperandInfo115[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4315
static const MCOperandInfo OperandInfo116[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4316
static const MCOperandInfo OperandInfo117[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4317
static const MCOperandInfo OperandInfo118[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4318
static const MCOperandInfo OperandInfo119[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4319
static const MCOperandInfo OperandInfo120[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4320
static const MCOperandInfo OperandInfo121[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4321
static const MCOperandInfo OperandInfo122[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4322
static const MCOperandInfo OperandInfo123[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4323
static const MCOperandInfo OperandInfo124[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4324
static const MCOperandInfo OperandInfo125[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4325
static const MCOperandInfo OperandInfo126[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4326
static const MCOperandInfo OperandInfo127[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4327
static const MCOperandInfo OperandInfo128[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4328
static const MCOperandInfo OperandInfo129[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4329
static const MCOperandInfo OperandInfo130[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4330
static const MCOperandInfo OperandInfo131[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4331
static const MCOperandInfo OperandInfo132[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4332
static const MCOperandInfo OperandInfo133[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4333
static const MCOperandInfo OperandInfo134[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4334
static const MCOperandInfo OperandInfo135[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4335
static const MCOperandInfo OperandInfo136[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4336
static const MCOperandInfo OperandInfo137[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4337
static const MCOperandInfo OperandInfo138[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4338
static const MCOperandInfo OperandInfo139[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4339
static const MCOperandInfo OperandInfo140[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4340
static const MCOperandInfo OperandInfo141[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4341
static const MCOperandInfo OperandInfo142[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4342
static const MCOperandInfo OperandInfo143[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4343
static const MCOperandInfo OperandInfo144[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4344
static const MCOperandInfo OperandInfo145[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4345
static const MCOperandInfo OperandInfo146[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4346
static const MCOperandInfo OperandInfo147[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4347
static const MCOperandInfo OperandInfo148[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4348
static const MCOperandInfo OperandInfo149[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4349
static const MCOperandInfo OperandInfo150[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4350
static const MCOperandInfo OperandInfo151[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4351
static const MCOperandInfo OperandInfo152[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4352
static const MCOperandInfo OperandInfo153[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4353
static const MCOperandInfo OperandInfo154[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4354
static const MCOperandInfo OperandInfo155[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4355
static const MCOperandInfo OperandInfo156[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4356
static const MCOperandInfo OperandInfo157[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4357
static const MCOperandInfo OperandInfo158[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4358
static const MCOperandInfo OperandInfo159[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4359
static const MCOperandInfo OperandInfo160[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4360
static const MCOperandInfo OperandInfo161[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4361
static const MCOperandInfo OperandInfo162[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4362
static const MCOperandInfo OperandInfo163[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4363
static const MCOperandInfo OperandInfo164[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4364
static const MCOperandInfo OperandInfo165[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4365
static const MCOperandInfo OperandInfo166[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4366
static const MCOperandInfo OperandInfo167[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4367
static const MCOperandInfo OperandInfo168[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4368
static const MCOperandInfo OperandInfo169[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4369
static const MCOperandInfo OperandInfo170[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4370
static const MCOperandInfo OperandInfo171[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4371
static const MCOperandInfo OperandInfo172[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4372
static const MCOperandInfo OperandInfo173[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4373
static const MCOperandInfo OperandInfo174[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4374
static const MCOperandInfo OperandInfo175[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4375
static const MCOperandInfo OperandInfo176[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4376
static const MCOperandInfo OperandInfo177[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4377
static const MCOperandInfo OperandInfo178[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4378
static const MCOperandInfo OperandInfo179[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4379
static const MCOperandInfo OperandInfo180[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4380
static const MCOperandInfo OperandInfo181[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4381
static const MCOperandInfo OperandInfo182[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4382
static const MCOperandInfo OperandInfo183[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4383
static const MCOperandInfo OperandInfo184[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4384
static const MCOperandInfo OperandInfo185[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4385
static const MCOperandInfo OperandInfo186[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4386
static const MCOperandInfo OperandInfo187[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4387
static const MCOperandInfo OperandInfo188[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4388
static const MCOperandInfo OperandInfo189[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4389
static const MCOperandInfo OperandInfo190[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4390
static const MCOperandInfo OperandInfo191[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4391
static const MCOperandInfo OperandInfo192[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4392
static const MCOperandInfo OperandInfo193[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4393
static const MCOperandInfo OperandInfo194[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4394
static const MCOperandInfo OperandInfo195[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4395
static const MCOperandInfo OperandInfo196[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4396
static const MCOperandInfo OperandInfo197[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4397
static const MCOperandInfo OperandInfo198[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4398
static const MCOperandInfo OperandInfo199[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4399
static const MCOperandInfo OperandInfo200[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4400
static const MCOperandInfo OperandInfo201[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4401
static const MCOperandInfo OperandInfo202[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4402
static const MCOperandInfo OperandInfo203[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4403
static const MCOperandInfo OperandInfo204[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4404
static const MCOperandInfo OperandInfo205[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4405
static const MCOperandInfo OperandInfo206[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4406
static const MCOperandInfo OperandInfo207[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4407
static const MCOperandInfo OperandInfo208[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4408
static const MCOperandInfo OperandInfo209[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4409
static const MCOperandInfo OperandInfo210[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4410
static const MCOperandInfo OperandInfo211[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4411
static const MCOperandInfo OperandInfo212[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4412
static const MCOperandInfo OperandInfo213[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4413
static const MCOperandInfo OperandInfo214[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4414
static const MCOperandInfo OperandInfo215[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4415
static const MCOperandInfo OperandInfo216[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4416
static const MCOperandInfo OperandInfo217[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4417
static const MCOperandInfo OperandInfo218[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4418
static const MCOperandInfo OperandInfo219[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4419
static const MCOperandInfo OperandInfo220[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4420
static const MCOperandInfo OperandInfo221[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4421
static const MCOperandInfo OperandInfo222[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4422
static const MCOperandInfo OperandInfo223[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4423
static const MCOperandInfo OperandInfo224[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4424
static const MCOperandInfo OperandInfo225[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4425
static const MCOperandInfo OperandInfo226[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4426
static const MCOperandInfo OperandInfo227[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4427
static const MCOperandInfo OperandInfo228[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4428
static const MCOperandInfo OperandInfo229[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4429
static const MCOperandInfo OperandInfo230[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4430
static const MCOperandInfo OperandInfo231[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4431
static const MCOperandInfo OperandInfo232[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4432
static const MCOperandInfo OperandInfo233[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4433
static const MCOperandInfo OperandInfo234[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4434
static const MCOperandInfo OperandInfo235[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4435
static const MCOperandInfo OperandInfo236[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4436
static const MCOperandInfo OperandInfo237[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4437
static const MCOperandInfo OperandInfo238[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4438
static const MCOperandInfo OperandInfo239[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4439
static const MCOperandInfo OperandInfo240[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4440
static const MCOperandInfo OperandInfo241[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4441
static const MCOperandInfo OperandInfo242[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4442
static const MCOperandInfo OperandInfo243[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4443
static const MCOperandInfo OperandInfo244[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4444
static const MCOperandInfo OperandInfo245[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4445
static const MCOperandInfo OperandInfo246[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4446
static const MCOperandInfo OperandInfo247[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4447
static const MCOperandInfo OperandInfo248[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4448
static const MCOperandInfo OperandInfo249[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4449
static const MCOperandInfo OperandInfo250[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4450
static const MCOperandInfo OperandInfo251[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4451
static const MCOperandInfo OperandInfo252[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4452
static const MCOperandInfo OperandInfo253[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4453
static const MCOperandInfo OperandInfo254[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4454
static const MCOperandInfo OperandInfo255[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4455
static const MCOperandInfo OperandInfo256[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4456
static const MCOperandInfo OperandInfo257[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4457
static const MCOperandInfo OperandInfo258[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4458
static const MCOperandInfo OperandInfo259[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4459
static const MCOperandInfo OperandInfo260[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4460
static const MCOperandInfo OperandInfo261[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4461
static const MCOperandInfo OperandInfo262[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4462
static const MCOperandInfo OperandInfo263[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4463
static const MCOperandInfo OperandInfo264[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4464
static const MCOperandInfo OperandInfo265[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4465
static const MCOperandInfo OperandInfo266[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4466
static const MCOperandInfo OperandInfo267[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4467
static const MCOperandInfo OperandInfo268[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4468
static const MCOperandInfo OperandInfo269[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4469
static const MCOperandInfo OperandInfo270[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4470
static const MCOperandInfo OperandInfo271[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4471
static const MCOperandInfo OperandInfo272[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4472
static const MCOperandInfo OperandInfo273[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4473
static const MCOperandInfo OperandInfo274[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4474
static const MCOperandInfo OperandInfo275[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4475
static const MCOperandInfo OperandInfo276[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4476
static const MCOperandInfo OperandInfo277[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4477
static const MCOperandInfo OperandInfo278[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4478
static const MCOperandInfo OperandInfo279[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4479
static const MCOperandInfo OperandInfo280[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4480
static const MCOperandInfo OperandInfo281[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4481
static const MCOperandInfo OperandInfo282[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4482
static const MCOperandInfo OperandInfo283[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4483
static const MCOperandInfo OperandInfo284[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4484
static const MCOperandInfo OperandInfo285[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4485
static const MCOperandInfo OperandInfo286[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4486
static const MCOperandInfo OperandInfo287[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4487
static const MCOperandInfo OperandInfo288[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4488
static const MCOperandInfo OperandInfo289[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4489
static const MCOperandInfo OperandInfo290[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4490
static const MCOperandInfo OperandInfo291[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4491
static const MCOperandInfo OperandInfo292[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4492
static const MCOperandInfo OperandInfo293[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4493
static const MCOperandInfo OperandInfo294[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4494
static const MCOperandInfo OperandInfo295[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4495
static const MCOperandInfo OperandInfo296[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4496
static const MCOperandInfo OperandInfo297[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4497
static const MCOperandInfo OperandInfo298[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4498
static const MCOperandInfo OperandInfo299[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4499
static const MCOperandInfo OperandInfo300[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4500
static const MCOperandInfo OperandInfo301[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4501
static const MCOperandInfo OperandInfo302[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4502
static const MCOperandInfo OperandInfo303[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4503
static const MCOperandInfo OperandInfo304[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4504
static const MCOperandInfo OperandInfo305[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4505
static const MCOperandInfo OperandInfo306[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4506
static const MCOperandInfo OperandInfo307[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4507
static const MCOperandInfo OperandInfo308[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4508
static const MCOperandInfo OperandInfo309[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4509
static const MCOperandInfo OperandInfo310[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4510
static const MCOperandInfo OperandInfo311[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4511
static const MCOperandInfo OperandInfo312[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4512
static const MCOperandInfo OperandInfo313[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4513
static const MCOperandInfo OperandInfo314[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4514
static const MCOperandInfo OperandInfo315[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4515
static const MCOperandInfo OperandInfo316[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4516
static const MCOperandInfo OperandInfo317[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4517
static const MCOperandInfo OperandInfo318[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4518
static const MCOperandInfo OperandInfo319[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4519
static const MCOperandInfo OperandInfo320[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4520
static const MCOperandInfo OperandInfo321[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4521
static const MCOperandInfo OperandInfo322[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4522
static const MCOperandInfo OperandInfo323[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4523
static const MCOperandInfo OperandInfo324[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4524
static const MCOperandInfo OperandInfo325[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4525
static const MCOperandInfo OperandInfo326[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4526
static const MCOperandInfo OperandInfo327[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4527
static const MCOperandInfo OperandInfo328[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4528
static const MCOperandInfo OperandInfo329[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4529
static const MCOperandInfo OperandInfo330[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4530
static const MCOperandInfo OperandInfo331[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4531
static const MCOperandInfo OperandInfo332[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4532
static const MCOperandInfo OperandInfo333[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4533
static const MCOperandInfo OperandInfo334[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4534
static const MCOperandInfo OperandInfo335[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4535
static const MCOperandInfo OperandInfo336[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4536
static const MCOperandInfo OperandInfo337[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4537
static const MCOperandInfo OperandInfo338[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4538
static const MCOperandInfo OperandInfo339[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4539
static const MCOperandInfo OperandInfo340[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4540
static const MCOperandInfo OperandInfo341[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4541
static const MCOperandInfo OperandInfo342[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4542
static const MCOperandInfo OperandInfo343[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4543
static const MCOperandInfo OperandInfo344[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4544
static const MCOperandInfo OperandInfo345[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4545
static const MCOperandInfo OperandInfo346[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4546
static const MCOperandInfo OperandInfo347[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4547
static const MCOperandInfo OperandInfo348[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4548
static const MCOperandInfo OperandInfo349[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4549
static const MCOperandInfo OperandInfo350[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4550
static const MCOperandInfo OperandInfo351[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4551
static const MCOperandInfo OperandInfo352[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4552
static const MCOperandInfo OperandInfo353[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4553
static const MCOperandInfo OperandInfo354[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4554
static const MCOperandInfo OperandInfo355[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4555
static const MCOperandInfo OperandInfo356[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4556
static const MCOperandInfo OperandInfo357[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4557
static const MCOperandInfo OperandInfo358[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4558
static const MCOperandInfo OperandInfo359[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4559
static const MCOperandInfo OperandInfo360[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4560
static const MCOperandInfo OperandInfo361[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4561
static const MCOperandInfo OperandInfo362[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4562
static const MCOperandInfo OperandInfo363[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4563
static const MCOperandInfo OperandInfo364[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4564
static const MCOperandInfo OperandInfo365[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4565
static const MCOperandInfo OperandInfo366[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4566
static const MCOperandInfo OperandInfo367[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4567
static const MCOperandInfo OperandInfo368[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4568
static const MCOperandInfo OperandInfo369[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4569
static const MCOperandInfo OperandInfo370[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4570
static const MCOperandInfo OperandInfo371[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4571
static const MCOperandInfo OperandInfo372[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4572
static const MCOperandInfo OperandInfo373[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4573
static const MCOperandInfo OperandInfo374[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4574
static const MCOperandInfo OperandInfo375[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4575
static const MCOperandInfo OperandInfo376[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4576
static const MCOperandInfo OperandInfo377[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4577
static const MCOperandInfo OperandInfo378[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4578
static const MCOperandInfo OperandInfo379[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4579
static const MCOperandInfo OperandInfo380[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4580
static const MCOperandInfo OperandInfo381[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4581
static const MCOperandInfo OperandInfo382[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4582
static const MCOperandInfo OperandInfo383[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4583
static const MCOperandInfo OperandInfo384[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4584
static const MCOperandInfo OperandInfo385[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4585
static const MCOperandInfo OperandInfo386[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4586
static const MCOperandInfo OperandInfo387[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4587
static const MCOperandInfo OperandInfo388[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4588
static const MCOperandInfo OperandInfo389[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4589
static const MCOperandInfo OperandInfo390[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4590
static const MCOperandInfo OperandInfo391[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4591
static const MCOperandInfo OperandInfo392[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4592
static const MCOperandInfo OperandInfo393[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4593
static const MCOperandInfo OperandInfo394[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4594
static const MCOperandInfo OperandInfo395[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4595
static const MCOperandInfo OperandInfo396[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4596
static const MCOperandInfo OperandInfo397[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4597
static const MCOperandInfo OperandInfo398[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4598
static const MCOperandInfo OperandInfo399[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4599
static const MCOperandInfo OperandInfo400[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4600
static const MCOperandInfo OperandInfo401[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4601
static const MCOperandInfo OperandInfo402[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4602
static const MCOperandInfo OperandInfo403[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4603
static const MCOperandInfo OperandInfo404[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4604
static const MCOperandInfo OperandInfo405[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4605
static const MCOperandInfo OperandInfo406[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4606
static const MCOperandInfo OperandInfo407[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4607
static const MCOperandInfo OperandInfo408[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4608
static const MCOperandInfo OperandInfo409[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4609
static const MCOperandInfo OperandInfo410[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4610
static const MCOperandInfo OperandInfo411[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4611
static const MCOperandInfo OperandInfo412[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4612
static const MCOperandInfo OperandInfo413[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4613
static const MCOperandInfo OperandInfo414[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4614
static const MCOperandInfo OperandInfo415[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4615
static const MCOperandInfo OperandInfo416[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4616
static const MCOperandInfo OperandInfo417[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4617
static const MCOperandInfo OperandInfo418[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4618
static const MCOperandInfo OperandInfo419[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4619
static const MCOperandInfo OperandInfo420[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4620
static const MCOperandInfo OperandInfo421[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4621
static const MCOperandInfo OperandInfo422[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4622
static const MCOperandInfo OperandInfo423[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4623
static const MCOperandInfo OperandInfo424[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4624
static const MCOperandInfo OperandInfo425[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4625
static const MCOperandInfo OperandInfo426[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4626
static const MCOperandInfo OperandInfo427[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4627
static const MCOperandInfo OperandInfo428[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4628
static const MCOperandInfo OperandInfo429[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4629
static const MCOperandInfo OperandInfo430[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4630
static const MCOperandInfo OperandInfo431[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4631
static const MCOperandInfo OperandInfo432[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4632
static const MCOperandInfo OperandInfo433[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4633
static const MCOperandInfo OperandInfo434[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4634
static const MCOperandInfo OperandInfo435[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4635
static const MCOperandInfo OperandInfo436[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4636
static const MCOperandInfo OperandInfo437[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4637
static const MCOperandInfo OperandInfo438[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4638
static const MCOperandInfo OperandInfo439[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4639
static const MCOperandInfo OperandInfo440[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4640
static const MCOperandInfo OperandInfo441[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4641
static const MCOperandInfo OperandInfo442[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4642
static const MCOperandInfo OperandInfo443[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4643
static const MCOperandInfo OperandInfo444[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4644
static const MCOperandInfo OperandInfo445[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4645
static const MCOperandInfo OperandInfo446[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4646
static const MCOperandInfo OperandInfo447[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4647
static const MCOperandInfo OperandInfo448[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4648
static const MCOperandInfo OperandInfo449[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4649
static const MCOperandInfo OperandInfo450[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4650
static const MCOperandInfo OperandInfo451[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4651
static const MCOperandInfo OperandInfo452[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4652
static const MCOperandInfo OperandInfo453[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4653
static const MCOperandInfo OperandInfo454[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4654
static const MCOperandInfo OperandInfo455[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4655
static const MCOperandInfo OperandInfo456[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4656
static const MCOperandInfo OperandInfo457[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4657
static const MCOperandInfo OperandInfo458[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4658
static const MCOperandInfo OperandInfo459[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4659
static const MCOperandInfo OperandInfo460[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4660
static const MCOperandInfo OperandInfo461[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4661
static const MCOperandInfo OperandInfo462[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::SpecialRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4662
static const MCOperandInfo OperandInfo463[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4663
static const MCOperandInfo OperandInfo464[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
4664
static const MCOperandInfo OperandInfo465[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4665
static const MCOperandInfo OperandInfo466[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4666
static const MCOperandInfo OperandInfo467[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4667
static const MCOperandInfo OperandInfo468[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4668
static const MCOperandInfo OperandInfo469[] = { { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4669
static const MCOperandInfo OperandInfo470[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4670
static const MCOperandInfo OperandInfo471[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4671
static const MCOperandInfo OperandInfo472[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4672
static const MCOperandInfo OperandInfo473[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4673
static const MCOperandInfo OperandInfo474[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4674
static const MCOperandInfo OperandInfo475[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4675
static const MCOperandInfo OperandInfo476[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4676
static const MCOperandInfo OperandInfo477[] = { { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4677
static const MCOperandInfo OperandInfo478[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4678
static const MCOperandInfo OperandInfo479[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4679
static const MCOperandInfo OperandInfo480[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4680
static const MCOperandInfo OperandInfo481[] = { { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4681
static const MCOperandInfo OperandInfo482[] = { { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4682
static const MCOperandInfo OperandInfo483[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4683
static const MCOperandInfo OperandInfo484[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4684
static const MCOperandInfo OperandInfo485[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4685
static const MCOperandInfo OperandInfo486[] = { { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4686
static const MCOperandInfo OperandInfo487[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4687
static const MCOperandInfo OperandInfo488[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4688
static const MCOperandInfo OperandInfo489[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4689
static const MCOperandInfo OperandInfo490[] = { { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
4690
static const MCOperandInfo OperandInfo491[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4691
static const MCOperandInfo OperandInfo492[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4692
static const MCOperandInfo OperandInfo493[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4693
static const MCOperandInfo OperandInfo494[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4694
static const MCOperandInfo OperandInfo495[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4695
static const MCOperandInfo OperandInfo496[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4696
static const MCOperandInfo OperandInfo497[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4697
static const MCOperandInfo OperandInfo498[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4698
static const MCOperandInfo OperandInfo499[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4699
static const MCOperandInfo OperandInfo500[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4700
static const MCOperandInfo OperandInfo501[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float16x2RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4701
static const MCOperandInfo OperandInfo502[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4702
static const MCOperandInfo OperandInfo503[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4703
static const MCOperandInfo OperandInfo504[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4704
static const MCOperandInfo OperandInfo505[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4705
static const MCOperandInfo OperandInfo506[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4706
static const MCOperandInfo OperandInfo507[] = { { NVPTX::Int1RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Float64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4707
static const MCOperandInfo OperandInfo508[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4708
static const MCOperandInfo OperandInfo509[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4709
static const MCOperandInfo OperandInfo510[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4710
static const MCOperandInfo OperandInfo511[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4711
static const MCOperandInfo OperandInfo512[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4712
static const MCOperandInfo OperandInfo513[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4713
static const MCOperandInfo OperandInfo514[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4714
static const MCOperandInfo OperandInfo515[] = { { NVPTX::Int32RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { NVPTX::Int64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
4715