/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc
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1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Target Register Enum Values *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | |
10 | | #ifdef GET_REGINFO_ENUM |
11 | | #undef GET_REGINFO_ENUM |
12 | | |
13 | | namespace llvm { |
14 | | |
15 | | class MCRegisterClass; |
16 | | extern const MCRegisterClass NVPTXMCRegisterClasses[]; |
17 | | |
18 | | namespace NVPTX { |
19 | | enum { |
20 | | NoRegister, |
21 | | VRDepot = 1, |
22 | | VRFrame = 2, |
23 | | VRFrameLocal = 3, |
24 | | ENVREG0 = 4, |
25 | | ENVREG1 = 5, |
26 | | ENVREG2 = 6, |
27 | | ENVREG3 = 7, |
28 | | ENVREG4 = 8, |
29 | | ENVREG5 = 9, |
30 | | ENVREG6 = 10, |
31 | | ENVREG7 = 11, |
32 | | ENVREG8 = 12, |
33 | | ENVREG9 = 13, |
34 | | ENVREG10 = 14, |
35 | | ENVREG11 = 15, |
36 | | ENVREG12 = 16, |
37 | | ENVREG13 = 17, |
38 | | ENVREG14 = 18, |
39 | | ENVREG15 = 19, |
40 | | ENVREG16 = 20, |
41 | | ENVREG17 = 21, |
42 | | ENVREG18 = 22, |
43 | | ENVREG19 = 23, |
44 | | ENVREG20 = 24, |
45 | | ENVREG21 = 25, |
46 | | ENVREG22 = 26, |
47 | | ENVREG23 = 27, |
48 | | ENVREG24 = 28, |
49 | | ENVREG25 = 29, |
50 | | ENVREG26 = 30, |
51 | | ENVREG27 = 31, |
52 | | ENVREG28 = 32, |
53 | | ENVREG29 = 33, |
54 | | ENVREG30 = 34, |
55 | | ENVREG31 = 35, |
56 | | F0 = 36, |
57 | | F1 = 37, |
58 | | F2 = 38, |
59 | | F3 = 39, |
60 | | F4 = 40, |
61 | | FL0 = 41, |
62 | | FL1 = 42, |
63 | | FL2 = 43, |
64 | | FL3 = 44, |
65 | | FL4 = 45, |
66 | | H0 = 46, |
67 | | H1 = 47, |
68 | | H2 = 48, |
69 | | H3 = 49, |
70 | | H4 = 50, |
71 | | HH0 = 51, |
72 | | HH1 = 52, |
73 | | HH2 = 53, |
74 | | HH3 = 54, |
75 | | HH4 = 55, |
76 | | P0 = 56, |
77 | | P1 = 57, |
78 | | P2 = 58, |
79 | | P3 = 59, |
80 | | P4 = 60, |
81 | | R0 = 61, |
82 | | R1 = 62, |
83 | | R2 = 63, |
84 | | R3 = 64, |
85 | | R4 = 65, |
86 | | RL0 = 66, |
87 | | RL1 = 67, |
88 | | RL2 = 68, |
89 | | RL3 = 69, |
90 | | RL4 = 70, |
91 | | RS0 = 71, |
92 | | RS1 = 72, |
93 | | RS2 = 73, |
94 | | RS3 = 74, |
95 | | RS4 = 75, |
96 | | da0 = 76, |
97 | | da1 = 77, |
98 | | da2 = 78, |
99 | | da3 = 79, |
100 | | da4 = 80, |
101 | | fa0 = 81, |
102 | | fa1 = 82, |
103 | | fa2 = 83, |
104 | | fa3 = 84, |
105 | | fa4 = 85, |
106 | | ia0 = 86, |
107 | | ia1 = 87, |
108 | | ia2 = 88, |
109 | | ia3 = 89, |
110 | | ia4 = 90, |
111 | | la0 = 91, |
112 | | la1 = 92, |
113 | | la2 = 93, |
114 | | la3 = 94, |
115 | | la4 = 95, |
116 | | NUM_TARGET_REGS // 96 |
117 | | }; |
118 | | } // end namespace NVPTX |
119 | | |
120 | | // Register classes |
121 | | |
122 | | namespace NVPTX { |
123 | | enum { |
124 | | Int1RegsRegClassID = 0, |
125 | | Float16RegsRegClassID = 1, |
126 | | Int16RegsRegClassID = 2, |
127 | | SpecialRegsRegClassID = 3, |
128 | | Float16x2RegsRegClassID = 4, |
129 | | Float32ArgRegsRegClassID = 5, |
130 | | Float32RegsRegClassID = 6, |
131 | | Int32ArgRegsRegClassID = 7, |
132 | | Int32RegsRegClassID = 8, |
133 | | Float64ArgRegsRegClassID = 9, |
134 | | Float64RegsRegClassID = 10, |
135 | | Int64ArgRegsRegClassID = 11, |
136 | | Int64RegsRegClassID = 12, |
137 | | |
138 | | }; |
139 | | } // end namespace NVPTX |
140 | | |
141 | | } // end namespace llvm |
142 | | |
143 | | #endif // GET_REGINFO_ENUM |
144 | | |
145 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
146 | | |* *| |
147 | | |* MC Register Information *| |
148 | | |* *| |
149 | | |* Automatically generated file, do not edit! *| |
150 | | |* *| |
151 | | \*===----------------------------------------------------------------------===*/ |
152 | | |
153 | | |
154 | | #ifdef GET_REGINFO_MC_DESC |
155 | | #undef GET_REGINFO_MC_DESC |
156 | | |
157 | | namespace llvm { |
158 | | |
159 | | extern const MCPhysReg NVPTXRegDiffLists[] = { |
160 | | /* 0 */ 65535, 0, |
161 | | }; |
162 | | |
163 | | extern const LaneBitmask NVPTXLaneMaskLists[] = { |
164 | | /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(), |
165 | | }; |
166 | | |
167 | | extern const uint16_t NVPTXSubRegIdxLists[] = { |
168 | | /* 0 */ 0, |
169 | | }; |
170 | | |
171 | | extern const MCRegisterInfo::SubRegCoveredBits NVPTXSubRegIdxRanges[] = { |
172 | | { 65535, 65535 }, |
173 | | }; |
174 | | |
175 | | extern const char NVPTXRegStrings[] = { |
176 | | /* 0 */ 'E', 'N', 'V', 'R', 'E', 'G', '1', '0', 0, |
177 | | /* 9 */ 'E', 'N', 'V', 'R', 'E', 'G', '2', '0', 0, |
178 | | /* 18 */ 'E', 'N', 'V', 'R', 'E', 'G', '3', '0', 0, |
179 | | /* 27 */ 'F', '0', 0, |
180 | | /* 30 */ 'E', 'N', 'V', 'R', 'E', 'G', '0', 0, |
181 | | /* 38 */ 'H', 'H', '0', 0, |
182 | | /* 42 */ 'F', 'L', '0', 0, |
183 | | /* 46 */ 'R', 'L', '0', 0, |
184 | | /* 50 */ 'P', '0', 0, |
185 | | /* 53 */ 'R', '0', 0, |
186 | | /* 56 */ 'R', 'S', '0', 0, |
187 | | /* 60 */ 'd', 'a', '0', 0, |
188 | | /* 64 */ 'f', 'a', '0', 0, |
189 | | /* 68 */ 'i', 'a', '0', 0, |
190 | | /* 72 */ 'l', 'a', '0', 0, |
191 | | /* 76 */ 'E', 'N', 'V', 'R', 'E', 'G', '1', '1', 0, |
192 | | /* 85 */ 'E', 'N', 'V', 'R', 'E', 'G', '2', '1', 0, |
193 | | /* 94 */ 'E', 'N', 'V', 'R', 'E', 'G', '3', '1', 0, |
194 | | /* 103 */ 'F', '1', 0, |
195 | | /* 106 */ 'E', 'N', 'V', 'R', 'E', 'G', '1', 0, |
196 | | /* 114 */ 'H', 'H', '1', 0, |
197 | | /* 118 */ 'F', 'L', '1', 0, |
198 | | /* 122 */ 'R', 'L', '1', 0, |
199 | | /* 126 */ 'P', '1', 0, |
200 | | /* 129 */ 'R', '1', 0, |
201 | | /* 132 */ 'R', 'S', '1', 0, |
202 | | /* 136 */ 'd', 'a', '1', 0, |
203 | | /* 140 */ 'f', 'a', '1', 0, |
204 | | /* 144 */ 'i', 'a', '1', 0, |
205 | | /* 148 */ 'l', 'a', '1', 0, |
206 | | /* 152 */ 'E', 'N', 'V', 'R', 'E', 'G', '1', '2', 0, |
207 | | /* 161 */ 'E', 'N', 'V', 'R', 'E', 'G', '2', '2', 0, |
208 | | /* 170 */ 'F', '2', 0, |
209 | | /* 173 */ 'E', 'N', 'V', 'R', 'E', 'G', '2', 0, |
210 | | /* 181 */ 'H', 'H', '2', 0, |
211 | | /* 185 */ 'F', 'L', '2', 0, |
212 | | /* 189 */ 'R', 'L', '2', 0, |
213 | | /* 193 */ 'P', '2', 0, |
214 | | /* 196 */ 'R', '2', 0, |
215 | | /* 199 */ 'R', 'S', '2', 0, |
216 | | /* 203 */ 'd', 'a', '2', 0, |
217 | | /* 207 */ 'f', 'a', '2', 0, |
218 | | /* 211 */ 'i', 'a', '2', 0, |
219 | | /* 215 */ 'l', 'a', '2', 0, |
220 | | /* 219 */ 'E', 'N', 'V', 'R', 'E', 'G', '1', '3', 0, |
221 | | /* 228 */ 'E', 'N', 'V', 'R', 'E', 'G', '2', '3', 0, |
222 | | /* 237 */ 'F', '3', 0, |
223 | | /* 240 */ 'E', 'N', 'V', 'R', 'E', 'G', '3', 0, |
224 | | /* 248 */ 'H', 'H', '3', 0, |
225 | | /* 252 */ 'F', 'L', '3', 0, |
226 | | /* 256 */ 'R', 'L', '3', 0, |
227 | | /* 260 */ 'P', '3', 0, |
228 | | /* 263 */ 'R', '3', 0, |
229 | | /* 266 */ 'R', 'S', '3', 0, |
230 | | /* 270 */ 'd', 'a', '3', 0, |
231 | | /* 274 */ 'f', 'a', '3', 0, |
232 | | /* 278 */ 'i', 'a', '3', 0, |
233 | | /* 282 */ 'l', 'a', '3', 0, |
234 | | /* 286 */ 'E', 'N', 'V', 'R', 'E', 'G', '1', '4', 0, |
235 | | /* 295 */ 'E', 'N', 'V', 'R', 'E', 'G', '2', '4', 0, |
236 | | /* 304 */ 'F', '4', 0, |
237 | | /* 307 */ 'E', 'N', 'V', 'R', 'E', 'G', '4', 0, |
238 | | /* 315 */ 'H', 'H', '4', 0, |
239 | | /* 319 */ 'F', 'L', '4', 0, |
240 | | /* 323 */ 'R', 'L', '4', 0, |
241 | | /* 327 */ 'P', '4', 0, |
242 | | /* 330 */ 'R', '4', 0, |
243 | | /* 333 */ 'R', 'S', '4', 0, |
244 | | /* 337 */ 'd', 'a', '4', 0, |
245 | | /* 341 */ 'f', 'a', '4', 0, |
246 | | /* 345 */ 'i', 'a', '4', 0, |
247 | | /* 349 */ 'l', 'a', '4', 0, |
248 | | /* 353 */ 'E', 'N', 'V', 'R', 'E', 'G', '1', '5', 0, |
249 | | /* 362 */ 'E', 'N', 'V', 'R', 'E', 'G', '2', '5', 0, |
250 | | /* 371 */ 'E', 'N', 'V', 'R', 'E', 'G', '5', 0, |
251 | | /* 379 */ 'E', 'N', 'V', 'R', 'E', 'G', '1', '6', 0, |
252 | | /* 388 */ 'E', 'N', 'V', 'R', 'E', 'G', '2', '6', 0, |
253 | | /* 397 */ 'E', 'N', 'V', 'R', 'E', 'G', '6', 0, |
254 | | /* 405 */ 'E', 'N', 'V', 'R', 'E', 'G', '1', '7', 0, |
255 | | /* 414 */ 'E', 'N', 'V', 'R', 'E', 'G', '2', '7', 0, |
256 | | /* 423 */ 'E', 'N', 'V', 'R', 'E', 'G', '7', 0, |
257 | | /* 431 */ 'E', 'N', 'V', 'R', 'E', 'G', '1', '8', 0, |
258 | | /* 440 */ 'E', 'N', 'V', 'R', 'E', 'G', '2', '8', 0, |
259 | | /* 449 */ 'E', 'N', 'V', 'R', 'E', 'G', '8', 0, |
260 | | /* 457 */ 'E', 'N', 'V', 'R', 'E', 'G', '1', '9', 0, |
261 | | /* 466 */ 'E', 'N', 'V', 'R', 'E', 'G', '2', '9', 0, |
262 | | /* 475 */ 'E', 'N', 'V', 'R', 'E', 'G', '9', 0, |
263 | | /* 483 */ 'V', 'R', 'F', 'r', 'a', 'm', 'e', 0, |
264 | | /* 491 */ 'V', 'R', 'F', 'r', 'a', 'm', 'e', 'L', 'o', 'c', 'a', 'l', 0, |
265 | | /* 504 */ 'V', 'R', 'D', 'e', 'p', 'o', 't', 0, |
266 | | }; |
267 | | |
268 | | extern const MCRegisterDesc NVPTXRegDesc[] = { // Descriptors |
269 | | { 8, 0, 0, 0, 0, 0 }, |
270 | | { 504, 1, 1, 0, 1, 0 }, |
271 | | { 483, 1, 1, 0, 1, 0 }, |
272 | | { 491, 1, 1, 0, 1, 0 }, |
273 | | { 30, 1, 1, 0, 1, 0 }, |
274 | | { 106, 1, 1, 0, 1, 0 }, |
275 | | { 173, 1, 1, 0, 1, 0 }, |
276 | | { 240, 1, 1, 0, 1, 0 }, |
277 | | { 307, 1, 1, 0, 1, 0 }, |
278 | | { 371, 1, 1, 0, 1, 0 }, |
279 | | { 397, 1, 1, 0, 1, 0 }, |
280 | | { 423, 1, 1, 0, 1, 0 }, |
281 | | { 449, 1, 1, 0, 1, 0 }, |
282 | | { 475, 1, 1, 0, 1, 0 }, |
283 | | { 0, 1, 1, 0, 1, 0 }, |
284 | | { 76, 1, 1, 0, 1, 0 }, |
285 | | { 152, 1, 1, 0, 1, 0 }, |
286 | | { 219, 1, 1, 0, 1, 0 }, |
287 | | { 286, 1, 1, 0, 1, 0 }, |
288 | | { 353, 1, 1, 0, 1, 0 }, |
289 | | { 379, 1, 1, 0, 1, 0 }, |
290 | | { 405, 1, 1, 0, 1, 0 }, |
291 | | { 431, 1, 1, 0, 1, 0 }, |
292 | | { 457, 1, 1, 0, 1, 0 }, |
293 | | { 9, 1, 1, 0, 1, 0 }, |
294 | | { 85, 1, 1, 0, 1, 0 }, |
295 | | { 161, 1, 1, 0, 1, 0 }, |
296 | | { 228, 1, 1, 0, 1, 0 }, |
297 | | { 295, 1, 1, 0, 1, 0 }, |
298 | | { 362, 1, 1, 0, 1, 0 }, |
299 | | { 388, 1, 1, 0, 1, 0 }, |
300 | | { 414, 1, 1, 0, 1, 0 }, |
301 | | { 440, 1, 1, 0, 1, 0 }, |
302 | | { 466, 1, 1, 0, 1, 0 }, |
303 | | { 18, 1, 1, 0, 1, 0 }, |
304 | | { 94, 1, 1, 0, 1, 0 }, |
305 | | { 27, 1, 1, 0, 1, 0 }, |
306 | | { 103, 1, 1, 0, 1, 0 }, |
307 | | { 170, 1, 1, 0, 1, 0 }, |
308 | | { 237, 1, 1, 0, 1, 0 }, |
309 | | { 304, 1, 1, 0, 1, 0 }, |
310 | | { 42, 1, 1, 0, 1, 0 }, |
311 | | { 118, 1, 1, 0, 1, 0 }, |
312 | | { 185, 1, 1, 0, 1, 0 }, |
313 | | { 252, 1, 1, 0, 1, 0 }, |
314 | | { 319, 1, 1, 0, 1, 0 }, |
315 | | { 39, 1, 1, 0, 1, 0 }, |
316 | | { 115, 1, 1, 0, 1, 0 }, |
317 | | { 182, 1, 1, 0, 1, 0 }, |
318 | | { 249, 1, 1, 0, 1, 0 }, |
319 | | { 316, 1, 1, 0, 1, 0 }, |
320 | | { 38, 1, 1, 0, 1, 0 }, |
321 | | { 114, 1, 1, 0, 1, 0 }, |
322 | | { 181, 1, 1, 0, 1, 0 }, |
323 | | { 248, 1, 1, 0, 1, 0 }, |
324 | | { 315, 1, 1, 0, 1, 0 }, |
325 | | { 50, 1, 1, 0, 1, 0 }, |
326 | | { 126, 1, 1, 0, 1, 0 }, |
327 | | { 193, 1, 1, 0, 1, 0 }, |
328 | | { 260, 1, 1, 0, 1, 0 }, |
329 | | { 327, 1, 1, 0, 1, 0 }, |
330 | | { 53, 1, 1, 0, 1, 0 }, |
331 | | { 129, 1, 1, 0, 1, 0 }, |
332 | | { 196, 1, 1, 0, 1, 0 }, |
333 | | { 263, 1, 1, 0, 1, 0 }, |
334 | | { 330, 1, 1, 0, 1, 0 }, |
335 | | { 46, 1, 1, 0, 1, 0 }, |
336 | | { 122, 1, 1, 0, 1, 0 }, |
337 | | { 189, 1, 1, 0, 1, 0 }, |
338 | | { 256, 1, 1, 0, 1, 0 }, |
339 | | { 323, 1, 1, 0, 1, 0 }, |
340 | | { 56, 1, 1, 0, 1, 0 }, |
341 | | { 132, 1, 1, 0, 1, 0 }, |
342 | | { 199, 1, 1, 0, 1, 0 }, |
343 | | { 266, 1, 1, 0, 1, 0 }, |
344 | | { 333, 1, 1, 0, 1, 0 }, |
345 | | { 60, 1, 1, 0, 1, 0 }, |
346 | | { 136, 1, 1, 0, 1, 0 }, |
347 | | { 203, 1, 1, 0, 1, 0 }, |
348 | | { 270, 1, 1, 0, 1, 0 }, |
349 | | { 337, 1, 1, 0, 1, 0 }, |
350 | | { 64, 1, 1, 0, 1, 0 }, |
351 | | { 140, 1, 1, 0, 1, 0 }, |
352 | | { 207, 1, 1, 0, 1, 0 }, |
353 | | { 274, 1, 1, 0, 1, 0 }, |
354 | | { 341, 1, 1, 0, 1, 0 }, |
355 | | { 68, 1, 1, 0, 1, 0 }, |
356 | | { 144, 1, 1, 0, 1, 0 }, |
357 | | { 211, 1, 1, 0, 1, 0 }, |
358 | | { 278, 1, 1, 0, 1, 0 }, |
359 | | { 345, 1, 1, 0, 1, 0 }, |
360 | | { 72, 1, 1, 0, 1, 0 }, |
361 | | { 148, 1, 1, 0, 1, 0 }, |
362 | | { 215, 1, 1, 0, 1, 0 }, |
363 | | { 282, 1, 1, 0, 1, 0 }, |
364 | | { 349, 1, 1, 0, 1, 0 }, |
365 | | }; |
366 | | |
367 | | extern const MCPhysReg NVPTXRegUnitRoots[][2] = { |
368 | | { NVPTX::VRDepot }, |
369 | | { NVPTX::VRFrame }, |
370 | | { NVPTX::VRFrameLocal }, |
371 | | { NVPTX::ENVREG0 }, |
372 | | { NVPTX::ENVREG1 }, |
373 | | { NVPTX::ENVREG2 }, |
374 | | { NVPTX::ENVREG3 }, |
375 | | { NVPTX::ENVREG4 }, |
376 | | { NVPTX::ENVREG5 }, |
377 | | { NVPTX::ENVREG6 }, |
378 | | { NVPTX::ENVREG7 }, |
379 | | { NVPTX::ENVREG8 }, |
380 | | { NVPTX::ENVREG9 }, |
381 | | { NVPTX::ENVREG10 }, |
382 | | { NVPTX::ENVREG11 }, |
383 | | { NVPTX::ENVREG12 }, |
384 | | { NVPTX::ENVREG13 }, |
385 | | { NVPTX::ENVREG14 }, |
386 | | { NVPTX::ENVREG15 }, |
387 | | { NVPTX::ENVREG16 }, |
388 | | { NVPTX::ENVREG17 }, |
389 | | { NVPTX::ENVREG18 }, |
390 | | { NVPTX::ENVREG19 }, |
391 | | { NVPTX::ENVREG20 }, |
392 | | { NVPTX::ENVREG21 }, |
393 | | { NVPTX::ENVREG22 }, |
394 | | { NVPTX::ENVREG23 }, |
395 | | { NVPTX::ENVREG24 }, |
396 | | { NVPTX::ENVREG25 }, |
397 | | { NVPTX::ENVREG26 }, |
398 | | { NVPTX::ENVREG27 }, |
399 | | { NVPTX::ENVREG28 }, |
400 | | { NVPTX::ENVREG29 }, |
401 | | { NVPTX::ENVREG30 }, |
402 | | { NVPTX::ENVREG31 }, |
403 | | { NVPTX::F0 }, |
404 | | { NVPTX::F1 }, |
405 | | { NVPTX::F2 }, |
406 | | { NVPTX::F3 }, |
407 | | { NVPTX::F4 }, |
408 | | { NVPTX::FL0 }, |
409 | | { NVPTX::FL1 }, |
410 | | { NVPTX::FL2 }, |
411 | | { NVPTX::FL3 }, |
412 | | { NVPTX::FL4 }, |
413 | | { NVPTX::H0 }, |
414 | | { NVPTX::H1 }, |
415 | | { NVPTX::H2 }, |
416 | | { NVPTX::H3 }, |
417 | | { NVPTX::H4 }, |
418 | | { NVPTX::HH0 }, |
419 | | { NVPTX::HH1 }, |
420 | | { NVPTX::HH2 }, |
421 | | { NVPTX::HH3 }, |
422 | | { NVPTX::HH4 }, |
423 | | { NVPTX::P0 }, |
424 | | { NVPTX::P1 }, |
425 | | { NVPTX::P2 }, |
426 | | { NVPTX::P3 }, |
427 | | { NVPTX::P4 }, |
428 | | { NVPTX::R0 }, |
429 | | { NVPTX::R1 }, |
430 | | { NVPTX::R2 }, |
431 | | { NVPTX::R3 }, |
432 | | { NVPTX::R4 }, |
433 | | { NVPTX::RL0 }, |
434 | | { NVPTX::RL1 }, |
435 | | { NVPTX::RL2 }, |
436 | | { NVPTX::RL3 }, |
437 | | { NVPTX::RL4 }, |
438 | | { NVPTX::RS0 }, |
439 | | { NVPTX::RS1 }, |
440 | | { NVPTX::RS2 }, |
441 | | { NVPTX::RS3 }, |
442 | | { NVPTX::RS4 }, |
443 | | { NVPTX::da0 }, |
444 | | { NVPTX::da1 }, |
445 | | { NVPTX::da2 }, |
446 | | { NVPTX::da3 }, |
447 | | { NVPTX::da4 }, |
448 | | { NVPTX::fa0 }, |
449 | | { NVPTX::fa1 }, |
450 | | { NVPTX::fa2 }, |
451 | | { NVPTX::fa3 }, |
452 | | { NVPTX::fa4 }, |
453 | | { NVPTX::ia0 }, |
454 | | { NVPTX::ia1 }, |
455 | | { NVPTX::ia2 }, |
456 | | { NVPTX::ia3 }, |
457 | | { NVPTX::ia4 }, |
458 | | { NVPTX::la0 }, |
459 | | { NVPTX::la1 }, |
460 | | { NVPTX::la2 }, |
461 | | { NVPTX::la3 }, |
462 | | { NVPTX::la4 }, |
463 | | }; |
464 | | |
465 | | namespace { // Register classes... |
466 | | // Int1Regs Register Class... |
467 | | const MCPhysReg Int1Regs[] = { |
468 | | NVPTX::P0, NVPTX::P1, NVPTX::P2, NVPTX::P3, NVPTX::P4, |
469 | | }; |
470 | | |
471 | | // Int1Regs Bit set. |
472 | | const uint8_t Int1RegsBits[] = { |
473 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, |
474 | | }; |
475 | | |
476 | | // Float16Regs Register Class... |
477 | | const MCPhysReg Float16Regs[] = { |
478 | | NVPTX::H0, NVPTX::H1, NVPTX::H2, NVPTX::H3, NVPTX::H4, |
479 | | }; |
480 | | |
481 | | // Float16Regs Bit set. |
482 | | const uint8_t Float16RegsBits[] = { |
483 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, |
484 | | }; |
485 | | |
486 | | // Int16Regs Register Class... |
487 | | const MCPhysReg Int16Regs[] = { |
488 | | NVPTX::RS0, NVPTX::RS1, NVPTX::RS2, NVPTX::RS3, NVPTX::RS4, |
489 | | }; |
490 | | |
491 | | // Int16Regs Bit set. |
492 | | const uint8_t Int16RegsBits[] = { |
493 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0f, |
494 | | }; |
495 | | |
496 | | // SpecialRegs Register Class... |
497 | | const MCPhysReg SpecialRegs[] = { |
498 | | NVPTX::VRFrame, NVPTX::VRFrameLocal, NVPTX::VRDepot, NVPTX::ENVREG0, NVPTX::ENVREG1, NVPTX::ENVREG2, NVPTX::ENVREG3, NVPTX::ENVREG4, NVPTX::ENVREG5, NVPTX::ENVREG6, NVPTX::ENVREG7, NVPTX::ENVREG8, NVPTX::ENVREG9, NVPTX::ENVREG10, NVPTX::ENVREG11, NVPTX::ENVREG12, NVPTX::ENVREG13, NVPTX::ENVREG14, NVPTX::ENVREG15, NVPTX::ENVREG16, NVPTX::ENVREG17, NVPTX::ENVREG18, NVPTX::ENVREG19, NVPTX::ENVREG20, NVPTX::ENVREG21, NVPTX::ENVREG22, NVPTX::ENVREG23, NVPTX::ENVREG24, NVPTX::ENVREG25, NVPTX::ENVREG26, NVPTX::ENVREG27, NVPTX::ENVREG28, NVPTX::ENVREG29, NVPTX::ENVREG30, NVPTX::ENVREG31, |
499 | | }; |
500 | | |
501 | | // SpecialRegs Bit set. |
502 | | const uint8_t SpecialRegsBits[] = { |
503 | | 0xfe, 0xff, 0xff, 0xff, 0x0f, |
504 | | }; |
505 | | |
506 | | // Float16x2Regs Register Class... |
507 | | const MCPhysReg Float16x2Regs[] = { |
508 | | NVPTX::HH0, NVPTX::HH1, NVPTX::HH2, NVPTX::HH3, NVPTX::HH4, |
509 | | }; |
510 | | |
511 | | // Float16x2Regs Bit set. |
512 | | const uint8_t Float16x2RegsBits[] = { |
513 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, |
514 | | }; |
515 | | |
516 | | // Float32ArgRegs Register Class... |
517 | | const MCPhysReg Float32ArgRegs[] = { |
518 | | NVPTX::fa0, NVPTX::fa1, NVPTX::fa2, NVPTX::fa3, NVPTX::fa4, |
519 | | }; |
520 | | |
521 | | // Float32ArgRegs Bit set. |
522 | | const uint8_t Float32ArgRegsBits[] = { |
523 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3e, |
524 | | }; |
525 | | |
526 | | // Float32Regs Register Class... |
527 | | const MCPhysReg Float32Regs[] = { |
528 | | NVPTX::F0, NVPTX::F1, NVPTX::F2, NVPTX::F3, NVPTX::F4, |
529 | | }; |
530 | | |
531 | | // Float32Regs Bit set. |
532 | | const uint8_t Float32RegsBits[] = { |
533 | | 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01, |
534 | | }; |
535 | | |
536 | | // Int32ArgRegs Register Class... |
537 | | const MCPhysReg Int32ArgRegs[] = { |
538 | | NVPTX::ia0, NVPTX::ia1, NVPTX::ia2, NVPTX::ia3, NVPTX::ia4, |
539 | | }; |
540 | | |
541 | | // Int32ArgRegs Bit set. |
542 | | const uint8_t Int32ArgRegsBits[] = { |
543 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, |
544 | | }; |
545 | | |
546 | | // Int32Regs Register Class... |
547 | | const MCPhysReg Int32Regs[] = { |
548 | | NVPTX::R0, NVPTX::R1, NVPTX::R2, NVPTX::R3, NVPTX::R4, |
549 | | }; |
550 | | |
551 | | // Int32Regs Bit set. |
552 | | const uint8_t Int32RegsBits[] = { |
553 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, |
554 | | }; |
555 | | |
556 | | // Float64ArgRegs Register Class... |
557 | | const MCPhysReg Float64ArgRegs[] = { |
558 | | NVPTX::da0, NVPTX::da1, NVPTX::da2, NVPTX::da3, NVPTX::da4, |
559 | | }; |
560 | | |
561 | | // Float64ArgRegs Bit set. |
562 | | const uint8_t Float64ArgRegsBits[] = { |
563 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01, |
564 | | }; |
565 | | |
566 | | // Float64Regs Register Class... |
567 | | const MCPhysReg Float64Regs[] = { |
568 | | NVPTX::FL0, NVPTX::FL1, NVPTX::FL2, NVPTX::FL3, NVPTX::FL4, |
569 | | }; |
570 | | |
571 | | // Float64Regs Bit set. |
572 | | const uint8_t Float64RegsBits[] = { |
573 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x3e, |
574 | | }; |
575 | | |
576 | | // Int64ArgRegs Register Class... |
577 | | const MCPhysReg Int64ArgRegs[] = { |
578 | | NVPTX::la0, NVPTX::la1, NVPTX::la2, NVPTX::la3, NVPTX::la4, |
579 | | }; |
580 | | |
581 | | // Int64ArgRegs Bit set. |
582 | | const uint8_t Int64ArgRegsBits[] = { |
583 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, |
584 | | }; |
585 | | |
586 | | // Int64Regs Register Class... |
587 | | const MCPhysReg Int64Regs[] = { |
588 | | NVPTX::RL0, NVPTX::RL1, NVPTX::RL2, NVPTX::RL3, NVPTX::RL4, |
589 | | }; |
590 | | |
591 | | // Int64Regs Bit set. |
592 | | const uint8_t Int64RegsBits[] = { |
593 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, |
594 | | }; |
595 | | |
596 | | } // end anonymous namespace |
597 | | |
598 | | extern const char NVPTXRegClassStrings[] = { |
599 | | /* 0 */ 'I', 'n', 't', '1', 'R', 'e', 'g', 's', 0, |
600 | | /* 9 */ 'F', 'l', 'o', 'a', 't', '3', '2', 'R', 'e', 'g', 's', 0, |
601 | | /* 21 */ 'I', 'n', 't', '3', '2', 'R', 'e', 'g', 's', 0, |
602 | | /* 31 */ 'F', 'l', 'o', 'a', 't', '1', '6', 'x', '2', 'R', 'e', 'g', 's', 0, |
603 | | /* 45 */ 'F', 'l', 'o', 'a', 't', '6', '4', 'R', 'e', 'g', 's', 0, |
604 | | /* 57 */ 'I', 'n', 't', '6', '4', 'R', 'e', 'g', 's', 0, |
605 | | /* 67 */ 'F', 'l', 'o', 'a', 't', '1', '6', 'R', 'e', 'g', 's', 0, |
606 | | /* 79 */ 'I', 'n', 't', '1', '6', 'R', 'e', 'g', 's', 0, |
607 | | /* 89 */ 'F', 'l', 'o', 'a', 't', '3', '2', 'A', 'r', 'g', 'R', 'e', 'g', 's', 0, |
608 | | /* 104 */ 'I', 'n', 't', '3', '2', 'A', 'r', 'g', 'R', 'e', 'g', 's', 0, |
609 | | /* 117 */ 'F', 'l', 'o', 'a', 't', '6', '4', 'A', 'r', 'g', 'R', 'e', 'g', 's', 0, |
610 | | /* 132 */ 'I', 'n', 't', '6', '4', 'A', 'r', 'g', 'R', 'e', 'g', 's', 0, |
611 | | /* 145 */ 'S', 'p', 'e', 'c', 'i', 'a', 'l', 'R', 'e', 'g', 's', 0, |
612 | | }; |
613 | | |
614 | | extern const MCRegisterClass NVPTXMCRegisterClasses[] = { |
615 | | { Int1Regs, Int1RegsBits, 0, 5, sizeof(Int1RegsBits), NVPTX::Int1RegsRegClassID, 1, true }, |
616 | | { Float16Regs, Float16RegsBits, 67, 5, sizeof(Float16RegsBits), NVPTX::Float16RegsRegClassID, 1, true }, |
617 | | { Int16Regs, Int16RegsBits, 79, 5, sizeof(Int16RegsBits), NVPTX::Int16RegsRegClassID, 1, true }, |
618 | | { SpecialRegs, SpecialRegsBits, 145, 35, sizeof(SpecialRegsBits), NVPTX::SpecialRegsRegClassID, 1, true }, |
619 | | { Float16x2Regs, Float16x2RegsBits, 31, 5, sizeof(Float16x2RegsBits), NVPTX::Float16x2RegsRegClassID, 1, true }, |
620 | | { Float32ArgRegs, Float32ArgRegsBits, 89, 5, sizeof(Float32ArgRegsBits), NVPTX::Float32ArgRegsRegClassID, 1, true }, |
621 | | { Float32Regs, Float32RegsBits, 9, 5, sizeof(Float32RegsBits), NVPTX::Float32RegsRegClassID, 1, true }, |
622 | | { Int32ArgRegs, Int32ArgRegsBits, 104, 5, sizeof(Int32ArgRegsBits), NVPTX::Int32ArgRegsRegClassID, 1, true }, |
623 | | { Int32Regs, Int32RegsBits, 21, 5, sizeof(Int32RegsBits), NVPTX::Int32RegsRegClassID, 1, true }, |
624 | | { Float64ArgRegs, Float64ArgRegsBits, 117, 5, sizeof(Float64ArgRegsBits), NVPTX::Float64ArgRegsRegClassID, 1, true }, |
625 | | { Float64Regs, Float64RegsBits, 45, 5, sizeof(Float64RegsBits), NVPTX::Float64RegsRegClassID, 1, true }, |
626 | | { Int64ArgRegs, Int64ArgRegsBits, 132, 5, sizeof(Int64ArgRegsBits), NVPTX::Int64ArgRegsRegClassID, 1, true }, |
627 | | { Int64Regs, Int64RegsBits, 57, 5, sizeof(Int64RegsBits), NVPTX::Int64RegsRegClassID, 1, true }, |
628 | | }; |
629 | | |
630 | | extern const uint16_t NVPTXRegEncodingTable[] = { |
631 | | 0, |
632 | | 0, |
633 | | 0, |
634 | | 0, |
635 | | 0, |
636 | | 0, |
637 | | 0, |
638 | | 0, |
639 | | 0, |
640 | | 0, |
641 | | 0, |
642 | | 0, |
643 | | 0, |
644 | | 0, |
645 | | 0, |
646 | | 0, |
647 | | 0, |
648 | | 0, |
649 | | 0, |
650 | | 0, |
651 | | 0, |
652 | | 0, |
653 | | 0, |
654 | | 0, |
655 | | 0, |
656 | | 0, |
657 | | 0, |
658 | | 0, |
659 | | 0, |
660 | | 0, |
661 | | 0, |
662 | | 0, |
663 | | 0, |
664 | | 0, |
665 | | 0, |
666 | | 0, |
667 | | 0, |
668 | | 0, |
669 | | 0, |
670 | | 0, |
671 | | 0, |
672 | | 0, |
673 | | 0, |
674 | | 0, |
675 | | 0, |
676 | | 0, |
677 | | 0, |
678 | | 0, |
679 | | 0, |
680 | | 0, |
681 | | 0, |
682 | | 0, |
683 | | 0, |
684 | | 0, |
685 | | 0, |
686 | | 0, |
687 | | 0, |
688 | | 0, |
689 | | 0, |
690 | | 0, |
691 | | 0, |
692 | | 0, |
693 | | 0, |
694 | | 0, |
695 | | 0, |
696 | | 0, |
697 | | 0, |
698 | | 0, |
699 | | 0, |
700 | | 0, |
701 | | 0, |
702 | | 0, |
703 | | 0, |
704 | | 0, |
705 | | 0, |
706 | | 0, |
707 | | 0, |
708 | | 0, |
709 | | 0, |
710 | | 0, |
711 | | 0, |
712 | | 0, |
713 | | 0, |
714 | | 0, |
715 | | 0, |
716 | | 0, |
717 | | 0, |
718 | | 0, |
719 | | 0, |
720 | | 0, |
721 | | 0, |
722 | | 0, |
723 | | 0, |
724 | | 0, |
725 | | 0, |
726 | | 0, |
727 | | }; |
728 | 455 | static inline void InitNVPTXMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) { |
729 | 455 | RI->InitMCRegisterInfo(NVPTXRegDesc, 96, RA, PC, NVPTXMCRegisterClasses, 13, NVPTXRegUnitRoots, 95, NVPTXRegDiffLists, NVPTXLaneMaskLists, NVPTXRegStrings, NVPTXRegClassStrings, NVPTXSubRegIdxLists, 1, |
730 | 455 | NVPTXSubRegIdxRanges, NVPTXRegEncodingTable); |
731 | 455 | |
732 | 455 | } |
733 | | |
734 | | } // end namespace llvm |
735 | | |
736 | | #endif // GET_REGINFO_MC_DESC |
737 | | |
738 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
739 | | |* *| |
740 | | |* Register Information Header Fragment *| |
741 | | |* *| |
742 | | |* Automatically generated file, do not edit! *| |
743 | | |* *| |
744 | | \*===----------------------------------------------------------------------===*/ |
745 | | |
746 | | |
747 | | #ifdef GET_REGINFO_HEADER |
748 | | #undef GET_REGINFO_HEADER |
749 | | |
750 | | #include "llvm/CodeGen/TargetRegisterInfo.h" |
751 | | |
752 | | namespace llvm { |
753 | | |
754 | | class NVPTXFrameLowering; |
755 | | |
756 | | struct NVPTXGenRegisterInfo : public TargetRegisterInfo { |
757 | | explicit NVPTXGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0, |
758 | | unsigned PC = 0, unsigned HwMode = 0); |
759 | | const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override; |
760 | | unsigned getRegUnitWeight(unsigned RegUnit) const override; |
761 | | unsigned getNumRegPressureSets() const override; |
762 | | const char *getRegPressureSetName(unsigned Idx) const override; |
763 | | unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override; |
764 | | const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override; |
765 | | const int *getRegUnitPressureSets(unsigned RegUnit) const override; |
766 | | ArrayRef<const char *> getRegMaskNames() const override; |
767 | | ArrayRef<const uint32_t *> getRegMasks() const override; |
768 | | /// Devirtualized TargetFrameLowering. |
769 | | static const NVPTXFrameLowering *getFrameLowering( |
770 | | const MachineFunction &MF); |
771 | | }; |
772 | | |
773 | | namespace NVPTX { // Register classes |
774 | | extern const TargetRegisterClass Int1RegsRegClass; |
775 | | extern const TargetRegisterClass Float16RegsRegClass; |
776 | | extern const TargetRegisterClass Int16RegsRegClass; |
777 | | extern const TargetRegisterClass SpecialRegsRegClass; |
778 | | extern const TargetRegisterClass Float16x2RegsRegClass; |
779 | | extern const TargetRegisterClass Float32ArgRegsRegClass; |
780 | | extern const TargetRegisterClass Float32RegsRegClass; |
781 | | extern const TargetRegisterClass Int32ArgRegsRegClass; |
782 | | extern const TargetRegisterClass Int32RegsRegClass; |
783 | | extern const TargetRegisterClass Float64ArgRegsRegClass; |
784 | | extern const TargetRegisterClass Float64RegsRegClass; |
785 | | extern const TargetRegisterClass Int64ArgRegsRegClass; |
786 | | extern const TargetRegisterClass Int64RegsRegClass; |
787 | | } // end namespace NVPTX |
788 | | |
789 | | } // end namespace llvm |
790 | | |
791 | | #endif // GET_REGINFO_HEADER |
792 | | |
793 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
794 | | |* *| |
795 | | |* Target Register and Register Classes Information *| |
796 | | |* *| |
797 | | |* Automatically generated file, do not edit! *| |
798 | | |* *| |
799 | | \*===----------------------------------------------------------------------===*/ |
800 | | |
801 | | |
802 | | #ifdef GET_REGINFO_TARGET_DESC |
803 | | #undef GET_REGINFO_TARGET_DESC |
804 | | |
805 | | namespace llvm { |
806 | | |
807 | | extern const MCRegisterClass NVPTXMCRegisterClasses[]; |
808 | | |
809 | | static const MVT::SimpleValueType VTLists[] = { |
810 | | /* 0 */ MVT::i1, MVT::Other, |
811 | | /* 2 */ MVT::i16, MVT::Other, |
812 | | /* 4 */ MVT::i32, MVT::Other, |
813 | | /* 6 */ MVT::i64, MVT::Other, |
814 | | /* 8 */ MVT::f16, MVT::Other, |
815 | | /* 10 */ MVT::f32, MVT::Other, |
816 | | /* 12 */ MVT::f64, MVT::Other, |
817 | | /* 14 */ MVT::v2f16, MVT::Other, |
818 | | }; |
819 | | |
820 | | static const char *const SubRegIndexNameTable[] = { "" }; |
821 | | |
822 | | |
823 | | static const LaneBitmask SubRegIndexLaneMaskTable[] = { |
824 | | LaneBitmask::getAll(), |
825 | | }; |
826 | | |
827 | | |
828 | | |
829 | | static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = { |
830 | | // Mode = 0 (Default) |
831 | | { 1, 1, 8, VTLists+0 }, // Int1Regs |
832 | | { 16, 16, 16, VTLists+8 }, // Float16Regs |
833 | | { 16, 16, 16, VTLists+2 }, // Int16Regs |
834 | | { 32, 32, 32, VTLists+4 }, // SpecialRegs |
835 | | { 32, 32, 32, VTLists+14 }, // Float16x2Regs |
836 | | { 32, 32, 32, VTLists+10 }, // Float32ArgRegs |
837 | | { 32, 32, 32, VTLists+10 }, // Float32Regs |
838 | | { 32, 32, 32, VTLists+4 }, // Int32ArgRegs |
839 | | { 32, 32, 32, VTLists+4 }, // Int32Regs |
840 | | { 64, 64, 64, VTLists+12 }, // Float64ArgRegs |
841 | | { 64, 64, 64, VTLists+12 }, // Float64Regs |
842 | | { 64, 64, 64, VTLists+6 }, // Int64ArgRegs |
843 | | { 64, 64, 64, VTLists+6 }, // Int64Regs |
844 | | }; |
845 | | |
846 | | static const TargetRegisterClass *const NullRegClasses[] = { nullptr }; |
847 | | |
848 | | static const uint32_t Int1RegsSubClassMask[] = { |
849 | | 0x00000001, |
850 | | }; |
851 | | |
852 | | static const uint32_t Float16RegsSubClassMask[] = { |
853 | | 0x00000002, |
854 | | }; |
855 | | |
856 | | static const uint32_t Int16RegsSubClassMask[] = { |
857 | | 0x00000004, |
858 | | }; |
859 | | |
860 | | static const uint32_t SpecialRegsSubClassMask[] = { |
861 | | 0x00000008, |
862 | | }; |
863 | | |
864 | | static const uint32_t Float16x2RegsSubClassMask[] = { |
865 | | 0x00000010, |
866 | | }; |
867 | | |
868 | | static const uint32_t Float32ArgRegsSubClassMask[] = { |
869 | | 0x00000020, |
870 | | }; |
871 | | |
872 | | static const uint32_t Float32RegsSubClassMask[] = { |
873 | | 0x00000040, |
874 | | }; |
875 | | |
876 | | static const uint32_t Int32ArgRegsSubClassMask[] = { |
877 | | 0x00000080, |
878 | | }; |
879 | | |
880 | | static const uint32_t Int32RegsSubClassMask[] = { |
881 | | 0x00000100, |
882 | | }; |
883 | | |
884 | | static const uint32_t Float64ArgRegsSubClassMask[] = { |
885 | | 0x00000200, |
886 | | }; |
887 | | |
888 | | static const uint32_t Float64RegsSubClassMask[] = { |
889 | | 0x00000400, |
890 | | }; |
891 | | |
892 | | static const uint32_t Int64ArgRegsSubClassMask[] = { |
893 | | 0x00000800, |
894 | | }; |
895 | | |
896 | | static const uint32_t Int64RegsSubClassMask[] = { |
897 | | 0x00001000, |
898 | | }; |
899 | | |
900 | | static const uint16_t SuperRegIdxSeqs[] = { |
901 | | /* 0 */ 0, |
902 | | }; |
903 | | |
904 | | |
905 | | namespace NVPTX { // Register class instances |
906 | | extern const TargetRegisterClass Int1RegsRegClass = { |
907 | | &NVPTXMCRegisterClasses[Int1RegsRegClassID], |
908 | | Int1RegsSubClassMask, |
909 | | SuperRegIdxSeqs + 0, |
910 | | LaneBitmask(0x00000001), |
911 | | 0, |
912 | | false, /* HasDisjunctSubRegs */ |
913 | | false, /* CoveredBySubRegs */ |
914 | | NullRegClasses, |
915 | | nullptr |
916 | | }; |
917 | | |
918 | | extern const TargetRegisterClass Float16RegsRegClass = { |
919 | | &NVPTXMCRegisterClasses[Float16RegsRegClassID], |
920 | | Float16RegsSubClassMask, |
921 | | SuperRegIdxSeqs + 0, |
922 | | LaneBitmask(0x00000001), |
923 | | 0, |
924 | | false, /* HasDisjunctSubRegs */ |
925 | | false, /* CoveredBySubRegs */ |
926 | | NullRegClasses, |
927 | | nullptr |
928 | | }; |
929 | | |
930 | | extern const TargetRegisterClass Int16RegsRegClass = { |
931 | | &NVPTXMCRegisterClasses[Int16RegsRegClassID], |
932 | | Int16RegsSubClassMask, |
933 | | SuperRegIdxSeqs + 0, |
934 | | LaneBitmask(0x00000001), |
935 | | 0, |
936 | | false, /* HasDisjunctSubRegs */ |
937 | | false, /* CoveredBySubRegs */ |
938 | | NullRegClasses, |
939 | | nullptr |
940 | | }; |
941 | | |
942 | | extern const TargetRegisterClass SpecialRegsRegClass = { |
943 | | &NVPTXMCRegisterClasses[SpecialRegsRegClassID], |
944 | | SpecialRegsSubClassMask, |
945 | | SuperRegIdxSeqs + 0, |
946 | | LaneBitmask(0x00000001), |
947 | | 0, |
948 | | false, /* HasDisjunctSubRegs */ |
949 | | false, /* CoveredBySubRegs */ |
950 | | NullRegClasses, |
951 | | nullptr |
952 | | }; |
953 | | |
954 | | extern const TargetRegisterClass Float16x2RegsRegClass = { |
955 | | &NVPTXMCRegisterClasses[Float16x2RegsRegClassID], |
956 | | Float16x2RegsSubClassMask, |
957 | | SuperRegIdxSeqs + 0, |
958 | | LaneBitmask(0x00000001), |
959 | | 0, |
960 | | false, /* HasDisjunctSubRegs */ |
961 | | false, /* CoveredBySubRegs */ |
962 | | NullRegClasses, |
963 | | nullptr |
964 | | }; |
965 | | |
966 | | extern const TargetRegisterClass Float32ArgRegsRegClass = { |
967 | | &NVPTXMCRegisterClasses[Float32ArgRegsRegClassID], |
968 | | Float32ArgRegsSubClassMask, |
969 | | SuperRegIdxSeqs + 0, |
970 | | LaneBitmask(0x00000001), |
971 | | 0, |
972 | | false, /* HasDisjunctSubRegs */ |
973 | | false, /* CoveredBySubRegs */ |
974 | | NullRegClasses, |
975 | | nullptr |
976 | | }; |
977 | | |
978 | | extern const TargetRegisterClass Float32RegsRegClass = { |
979 | | &NVPTXMCRegisterClasses[Float32RegsRegClassID], |
980 | | Float32RegsSubClassMask, |
981 | | SuperRegIdxSeqs + 0, |
982 | | LaneBitmask(0x00000001), |
983 | | 0, |
984 | | false, /* HasDisjunctSubRegs */ |
985 | | false, /* CoveredBySubRegs */ |
986 | | NullRegClasses, |
987 | | nullptr |
988 | | }; |
989 | | |
990 | | extern const TargetRegisterClass Int32ArgRegsRegClass = { |
991 | | &NVPTXMCRegisterClasses[Int32ArgRegsRegClassID], |
992 | | Int32ArgRegsSubClassMask, |
993 | | SuperRegIdxSeqs + 0, |
994 | | LaneBitmask(0x00000001), |
995 | | 0, |
996 | | false, /* HasDisjunctSubRegs */ |
997 | | false, /* CoveredBySubRegs */ |
998 | | NullRegClasses, |
999 | | nullptr |
1000 | | }; |
1001 | | |
1002 | | extern const TargetRegisterClass Int32RegsRegClass = { |
1003 | | &NVPTXMCRegisterClasses[Int32RegsRegClassID], |
1004 | | Int32RegsSubClassMask, |
1005 | | SuperRegIdxSeqs + 0, |
1006 | | LaneBitmask(0x00000001), |
1007 | | 0, |
1008 | | false, /* HasDisjunctSubRegs */ |
1009 | | false, /* CoveredBySubRegs */ |
1010 | | NullRegClasses, |
1011 | | nullptr |
1012 | | }; |
1013 | | |
1014 | | extern const TargetRegisterClass Float64ArgRegsRegClass = { |
1015 | | &NVPTXMCRegisterClasses[Float64ArgRegsRegClassID], |
1016 | | Float64ArgRegsSubClassMask, |
1017 | | SuperRegIdxSeqs + 0, |
1018 | | LaneBitmask(0x00000001), |
1019 | | 0, |
1020 | | false, /* HasDisjunctSubRegs */ |
1021 | | false, /* CoveredBySubRegs */ |
1022 | | NullRegClasses, |
1023 | | nullptr |
1024 | | }; |
1025 | | |
1026 | | extern const TargetRegisterClass Float64RegsRegClass = { |
1027 | | &NVPTXMCRegisterClasses[Float64RegsRegClassID], |
1028 | | Float64RegsSubClassMask, |
1029 | | SuperRegIdxSeqs + 0, |
1030 | | LaneBitmask(0x00000001), |
1031 | | 0, |
1032 | | false, /* HasDisjunctSubRegs */ |
1033 | | false, /* CoveredBySubRegs */ |
1034 | | NullRegClasses, |
1035 | | nullptr |
1036 | | }; |
1037 | | |
1038 | | extern const TargetRegisterClass Int64ArgRegsRegClass = { |
1039 | | &NVPTXMCRegisterClasses[Int64ArgRegsRegClassID], |
1040 | | Int64ArgRegsSubClassMask, |
1041 | | SuperRegIdxSeqs + 0, |
1042 | | LaneBitmask(0x00000001), |
1043 | | 0, |
1044 | | false, /* HasDisjunctSubRegs */ |
1045 | | false, /* CoveredBySubRegs */ |
1046 | | NullRegClasses, |
1047 | | nullptr |
1048 | | }; |
1049 | | |
1050 | | extern const TargetRegisterClass Int64RegsRegClass = { |
1051 | | &NVPTXMCRegisterClasses[Int64RegsRegClassID], |
1052 | | Int64RegsSubClassMask, |
1053 | | SuperRegIdxSeqs + 0, |
1054 | | LaneBitmask(0x00000001), |
1055 | | 0, |
1056 | | false, /* HasDisjunctSubRegs */ |
1057 | | false, /* CoveredBySubRegs */ |
1058 | | NullRegClasses, |
1059 | | nullptr |
1060 | | }; |
1061 | | |
1062 | | } // end namespace NVPTX |
1063 | | |
1064 | | namespace { |
1065 | | const TargetRegisterClass* const RegisterClasses[] = { |
1066 | | &NVPTX::Int1RegsRegClass, |
1067 | | &NVPTX::Float16RegsRegClass, |
1068 | | &NVPTX::Int16RegsRegClass, |
1069 | | &NVPTX::SpecialRegsRegClass, |
1070 | | &NVPTX::Float16x2RegsRegClass, |
1071 | | &NVPTX::Float32ArgRegsRegClass, |
1072 | | &NVPTX::Float32RegsRegClass, |
1073 | | &NVPTX::Int32ArgRegsRegClass, |
1074 | | &NVPTX::Int32RegsRegClass, |
1075 | | &NVPTX::Float64ArgRegsRegClass, |
1076 | | &NVPTX::Float64RegsRegClass, |
1077 | | &NVPTX::Int64ArgRegsRegClass, |
1078 | | &NVPTX::Int64RegsRegClass, |
1079 | | }; |
1080 | | } // end anonymous namespace |
1081 | | |
1082 | | static const TargetRegisterInfoDesc NVPTXRegInfoDesc[] = { // Extra Descriptors |
1083 | | { 0, false }, |
1084 | | { 0, true }, |
1085 | | { 0, true }, |
1086 | | { 0, true }, |
1087 | | { 0, true }, |
1088 | | { 0, true }, |
1089 | | { 0, true }, |
1090 | | { 0, true }, |
1091 | | { 0, true }, |
1092 | | { 0, true }, |
1093 | | { 0, true }, |
1094 | | { 0, true }, |
1095 | | { 0, true }, |
1096 | | { 0, true }, |
1097 | | { 0, true }, |
1098 | | { 0, true }, |
1099 | | { 0, true }, |
1100 | | { 0, true }, |
1101 | | { 0, true }, |
1102 | | { 0, true }, |
1103 | | { 0, true }, |
1104 | | { 0, true }, |
1105 | | { 0, true }, |
1106 | | { 0, true }, |
1107 | | { 0, true }, |
1108 | | { 0, true }, |
1109 | | { 0, true }, |
1110 | | { 0, true }, |
1111 | | { 0, true }, |
1112 | | { 0, true }, |
1113 | | { 0, true }, |
1114 | | { 0, true }, |
1115 | | { 0, true }, |
1116 | | { 0, true }, |
1117 | | { 0, true }, |
1118 | | { 0, true }, |
1119 | | { 0, true }, |
1120 | | { 0, true }, |
1121 | | { 0, true }, |
1122 | | { 0, true }, |
1123 | | { 0, true }, |
1124 | | { 0, true }, |
1125 | | { 0, true }, |
1126 | | { 0, true }, |
1127 | | { 0, true }, |
1128 | | { 0, true }, |
1129 | | { 0, true }, |
1130 | | { 0, true }, |
1131 | | { 0, true }, |
1132 | | { 0, true }, |
1133 | | { 0, true }, |
1134 | | { 0, true }, |
1135 | | { 0, true }, |
1136 | | { 0, true }, |
1137 | | { 0, true }, |
1138 | | { 0, true }, |
1139 | | { 0, true }, |
1140 | | { 0, true }, |
1141 | | { 0, true }, |
1142 | | { 0, true }, |
1143 | | { 0, true }, |
1144 | | { 0, true }, |
1145 | | { 0, true }, |
1146 | | { 0, true }, |
1147 | | { 0, true }, |
1148 | | { 0, true }, |
1149 | | { 0, true }, |
1150 | | { 0, true }, |
1151 | | { 0, true }, |
1152 | | { 0, true }, |
1153 | | { 0, true }, |
1154 | | { 0, true }, |
1155 | | { 0, true }, |
1156 | | { 0, true }, |
1157 | | { 0, true }, |
1158 | | { 0, true }, |
1159 | | { 0, true }, |
1160 | | { 0, true }, |
1161 | | { 0, true }, |
1162 | | { 0, true }, |
1163 | | { 0, true }, |
1164 | | { 0, true }, |
1165 | | { 0, true }, |
1166 | | { 0, true }, |
1167 | | { 0, true }, |
1168 | | { 0, true }, |
1169 | | { 0, true }, |
1170 | | { 0, true }, |
1171 | | { 0, true }, |
1172 | | { 0, true }, |
1173 | | { 0, true }, |
1174 | | { 0, true }, |
1175 | | { 0, true }, |
1176 | | { 0, true }, |
1177 | | { 0, true }, |
1178 | | { 0, true }, |
1179 | | }; |
1180 | | /// Get the weight in units of pressure for this register class. |
1181 | | const RegClassWeight &NVPTXGenRegisterInfo:: |
1182 | 152 | getRegClassWeight(const TargetRegisterClass *RC) const { |
1183 | 152 | static const RegClassWeight RCWeightTable[] = { |
1184 | 152 | {1, 5}, // Int1Regs |
1185 | 152 | {1, 5}, // Float16Regs |
1186 | 152 | {1, 5}, // Int16Regs |
1187 | 152 | {1, 35}, // SpecialRegs |
1188 | 152 | {1, 5}, // Float16x2Regs |
1189 | 152 | {1, 5}, // Float32ArgRegs |
1190 | 152 | {1, 5}, // Float32Regs |
1191 | 152 | {1, 5}, // Int32ArgRegs |
1192 | 152 | {1, 5}, // Int32Regs |
1193 | 152 | {1, 5}, // Float64ArgRegs |
1194 | 152 | {1, 5}, // Float64Regs |
1195 | 152 | {1, 5}, // Int64ArgRegs |
1196 | 152 | {1, 5}, // Int64Regs |
1197 | 152 | }; |
1198 | 152 | return RCWeightTable[RC->getID()]; |
1199 | 152 | } |
1200 | | |
1201 | | /// Get the weight in units of pressure for this register unit. |
1202 | | unsigned NVPTXGenRegisterInfo:: |
1203 | 0 | getRegUnitWeight(unsigned RegUnit) const { |
1204 | 0 | assert(RegUnit < 95 && "invalid register unit"); |
1205 | 0 | // All register units have unit weight. |
1206 | 0 | return 1; |
1207 | 0 | } |
1208 | | |
1209 | | |
1210 | | // Get the number of dimensions of register pressure. |
1211 | 1.26k | unsigned NVPTXGenRegisterInfo::getNumRegPressureSets() const { |
1212 | 1.26k | return 13; |
1213 | 1.26k | } |
1214 | | |
1215 | | // Get the name of this register unit pressure set. |
1216 | | const char *NVPTXGenRegisterInfo:: |
1217 | 0 | getRegPressureSetName(unsigned Idx) const { |
1218 | 0 | static const char *const PressureNameTable[] = { |
1219 | 0 | "Int1Regs", |
1220 | 0 | "Float16Regs", |
1221 | 0 | "Int16Regs", |
1222 | 0 | "Float16x2Regs", |
1223 | 0 | "Float32ArgRegs", |
1224 | 0 | "Float32Regs", |
1225 | 0 | "Int32ArgRegs", |
1226 | 0 | "Int32Regs", |
1227 | 0 | "Float64ArgRegs", |
1228 | 0 | "Float64Regs", |
1229 | 0 | "Int64ArgRegs", |
1230 | 0 | "Int64Regs", |
1231 | 0 | "SpecialRegs", |
1232 | 0 | }; |
1233 | 0 | return PressureNameTable[Idx]; |
1234 | 0 | } |
1235 | | |
1236 | | // Get the register unit pressure limit for this dimension. |
1237 | | // This limit must be adjusted dynamically for reserved registers. |
1238 | | unsigned NVPTXGenRegisterInfo:: |
1239 | 14.0k | getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const { |
1240 | 14.0k | static const uint8_t PressureLimitTable[] = { |
1241 | 14.0k | 5, // 0: Int1Regs |
1242 | 14.0k | 5, // 1: Float16Regs |
1243 | 14.0k | 5, // 2: Int16Regs |
1244 | 14.0k | 5, // 3: Float16x2Regs |
1245 | 14.0k | 5, // 4: Float32ArgRegs |
1246 | 14.0k | 5, // 5: Float32Regs |
1247 | 14.0k | 5, // 6: Int32ArgRegs |
1248 | 14.0k | 5, // 7: Int32Regs |
1249 | 14.0k | 5, // 8: Float64ArgRegs |
1250 | 14.0k | 5, // 9: Float64Regs |
1251 | 14.0k | 5, // 10: Int64ArgRegs |
1252 | 14.0k | 5, // 11: Int64Regs |
1253 | 14.0k | 35, // 12: SpecialRegs |
1254 | 14.0k | }; |
1255 | 14.0k | return PressureLimitTable[Idx]; |
1256 | 14.0k | } |
1257 | | |
1258 | | /// Table of pressure sets per register class or unit. |
1259 | | static const int RCSetsTable[] = { |
1260 | | /* 0 */ 0, -1, |
1261 | | /* 2 */ 1, -1, |
1262 | | /* 4 */ 2, -1, |
1263 | | /* 6 */ 3, -1, |
1264 | | /* 8 */ 4, -1, |
1265 | | /* 10 */ 5, -1, |
1266 | | /* 12 */ 6, -1, |
1267 | | /* 14 */ 7, -1, |
1268 | | /* 16 */ 8, -1, |
1269 | | /* 18 */ 9, -1, |
1270 | | /* 20 */ 10, -1, |
1271 | | /* 22 */ 11, -1, |
1272 | | /* 24 */ 12, -1, |
1273 | | }; |
1274 | | |
1275 | | /// Get the dimensions of register pressure impacted by this register class. |
1276 | | /// Returns a -1 terminated array of pressure set IDs |
1277 | | const int* NVPTXGenRegisterInfo:: |
1278 | 123 | getRegClassPressureSets(const TargetRegisterClass *RC) const { |
1279 | 123 | static const uint8_t RCSetStartTable[] = { |
1280 | 123 | 0,2,4,24,6,8,10,12,14,16,18,20,22,}; |
1281 | 123 | return &RCSetsTable[RCSetStartTable[RC->getID()]]; |
1282 | 123 | } |
1283 | | |
1284 | | /// Get the dimensions of register pressure impacted by this register unit. |
1285 | | /// Returns a -1 terminated array of pressure set IDs |
1286 | | const int* NVPTXGenRegisterInfo:: |
1287 | 0 | getRegUnitPressureSets(unsigned RegUnit) const { |
1288 | 0 | assert(RegUnit < 95 && "invalid register unit"); |
1289 | 0 | static const uint8_t RUSetStartTable[] = { |
1290 | 0 | 24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,10,10,10,10,10,18,18,18,18,18,2,2,2,2,2,6,6,6,6,6,0,0,0,0,0,14,14,14,14,14,22,22,22,22,22,4,4,4,4,4,16,16,16,16,16,8,8,8,8,8,12,12,12,12,12,20,20,20,20,20,}; |
1291 | 0 | return &RCSetsTable[RUSetStartTable[RegUnit]]; |
1292 | 0 | } |
1293 | | |
1294 | | extern const MCRegisterDesc NVPTXRegDesc[]; |
1295 | | extern const MCPhysReg NVPTXRegDiffLists[]; |
1296 | | extern const LaneBitmask NVPTXLaneMaskLists[]; |
1297 | | extern const char NVPTXRegStrings[]; |
1298 | | extern const char NVPTXRegClassStrings[]; |
1299 | | extern const MCPhysReg NVPTXRegUnitRoots[][2]; |
1300 | | extern const uint16_t NVPTXSubRegIdxLists[]; |
1301 | | extern const MCRegisterInfo::SubRegCoveredBits NVPTXSubRegIdxRanges[]; |
1302 | | extern const uint16_t NVPTXRegEncodingTable[]; |
1303 | | NVPTXGenRegisterInfo:: |
1304 | | NVPTXGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, |
1305 | | unsigned PC, unsigned HwMode) |
1306 | | : TargetRegisterInfo(NVPTXRegInfoDesc, RegisterClasses, RegisterClasses+13, |
1307 | | SubRegIndexNameTable, SubRegIndexLaneMaskTable, |
1308 | 455 | LaneBitmask(0xFFFFFFFF), RegClassInfos, HwMode) { |
1309 | 455 | InitMCRegisterInfo(NVPTXRegDesc, 96, RA, PC, |
1310 | 455 | NVPTXMCRegisterClasses, 13, |
1311 | 455 | NVPTXRegUnitRoots, |
1312 | 455 | 95, |
1313 | 455 | NVPTXRegDiffLists, |
1314 | 455 | NVPTXLaneMaskLists, |
1315 | 455 | NVPTXRegStrings, |
1316 | 455 | NVPTXRegClassStrings, |
1317 | 455 | NVPTXSubRegIdxLists, |
1318 | 455 | 1, |
1319 | 455 | NVPTXSubRegIdxRanges, |
1320 | 455 | NVPTXRegEncodingTable); |
1321 | 455 | |
1322 | 455 | } |
1323 | | |
1324 | | |
1325 | | |
1326 | 27 | ArrayRef<const uint32_t *> NVPTXGenRegisterInfo::getRegMasks() const { |
1327 | 27 | return None; |
1328 | 27 | } |
1329 | | |
1330 | 0 | ArrayRef<const char *> NVPTXGenRegisterInfo::getRegMaskNames() const { |
1331 | 0 | return None; |
1332 | 0 | } |
1333 | | |
1334 | | const NVPTXFrameLowering * |
1335 | 0 | NVPTXGenRegisterInfo::getFrameLowering(const MachineFunction &MF) { |
1336 | 0 | return static_cast<const NVPTXFrameLowering *>( |
1337 | 0 | MF.getSubtarget().getFrameLowering()); |
1338 | 0 | } |
1339 | | |
1340 | | } // end namespace llvm |
1341 | | |
1342 | | #endif // GET_REGINFO_TARGET_DESC |
1343 | | |