Coverage Report

Created: 2018-09-19 20:53

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/NVPTX/NVPTXGenSubtargetInfo.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Subtarget Enumeration Source Fragment                                      *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_SUBTARGETINFO_ENUM
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#undef GET_SUBTARGETINFO_ENUM
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namespace llvm {
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namespace NVPTX {
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enum {
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  PTX32 = 0,
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  PTX40 = 1,
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  PTX41 = 2,
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  PTX42 = 3,
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  PTX43 = 4,
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  PTX50 = 5,
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  PTX60 = 6,
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  PTX61 = 7,
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  SM20 = 8,
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  SM21 = 9,
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  SM30 = 10,
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  SM32 = 11,
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  SM35 = 12,
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  SM37 = 13,
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  SM50 = 14,
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  SM52 = 15,
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  SM53 = 16,
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  SM60 = 17,
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  SM61 = 18,
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  SM62 = 19,
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  SM70 = 20,
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  SM72 = 21,
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};
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} // end namespace NVPTX
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} // end namespace llvm
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#endif // GET_SUBTARGETINFO_ENUM
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#ifdef GET_SUBTARGETINFO_MC_DESC
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#undef GET_SUBTARGETINFO_MC_DESC
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namespace llvm {
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// Sorted (by key) array of values for CPU features.
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extern const llvm::SubtargetFeatureKV NVPTXFeatureKV[] = {
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  { "ptx32", "Use PTX version 3.2", { NVPTX::PTX32 }, { } },
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  { "ptx40", "Use PTX version 4.0", { NVPTX::PTX40 }, { } },
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  { "ptx41", "Use PTX version 4.1", { NVPTX::PTX41 }, { } },
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  { "ptx42", "Use PTX version 4.2", { NVPTX::PTX42 }, { } },
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  { "ptx43", "Use PTX version 4.3", { NVPTX::PTX43 }, { } },
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  { "ptx50", "Use PTX version 5.0", { NVPTX::PTX50 }, { } },
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  { "ptx60", "Use PTX version 6.0", { NVPTX::PTX60 }, { } },
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  { "ptx61", "Use PTX version 6.1", { NVPTX::PTX61 }, { } },
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  { "sm_20", "Target SM 2.0", { NVPTX::SM20 }, { } },
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  { "sm_21", "Target SM 2.1", { NVPTX::SM21 }, { } },
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  { "sm_30", "Target SM 3.0", { NVPTX::SM30 }, { } },
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  { "sm_32", "Target SM 3.2", { NVPTX::SM32 }, { } },
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  { "sm_35", "Target SM 3.5", { NVPTX::SM35 }, { } },
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  { "sm_37", "Target SM 3.7", { NVPTX::SM37 }, { } },
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  { "sm_50", "Target SM 5.0", { NVPTX::SM50 }, { } },
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  { "sm_52", "Target SM 5.2", { NVPTX::SM52 }, { } },
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  { "sm_53", "Target SM 5.3", { NVPTX::SM53 }, { } },
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  { "sm_60", "Target SM 6.0", { NVPTX::SM60 }, { } },
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  { "sm_61", "Target SM 6.1", { NVPTX::SM61 }, { } },
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  { "sm_62", "Target SM 6.2", { NVPTX::SM62 }, { } },
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  { "sm_70", "Target SM 7.0", { NVPTX::SM70 }, { } },
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  { "sm_72", "Target SM 7.2", { NVPTX::SM72 }, { } },
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};
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// Sorted (by key) array of values for CPU subtype.
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extern const llvm::SubtargetFeatureKV NVPTXSubTypeKV[] = {
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  { "sm_20", "Select the sm_20 processor", { NVPTX::SM20 }, { } },
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  { "sm_21", "Select the sm_21 processor", { NVPTX::SM21 }, { } },
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  { "sm_30", "Select the sm_30 processor", { NVPTX::SM30 }, { } },
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  { "sm_32", "Select the sm_32 processor", { NVPTX::SM32, NVPTX::PTX40 }, { } },
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  { "sm_35", "Select the sm_35 processor", { NVPTX::SM35 }, { } },
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  { "sm_37", "Select the sm_37 processor", { NVPTX::SM37, NVPTX::PTX41 }, { } },
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  { "sm_50", "Select the sm_50 processor", { NVPTX::SM50, NVPTX::PTX40 }, { } },
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  { "sm_52", "Select the sm_52 processor", { NVPTX::SM52, NVPTX::PTX41 }, { } },
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  { "sm_53", "Select the sm_53 processor", { NVPTX::SM53, NVPTX::PTX42 }, { } },
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  { "sm_60", "Select the sm_60 processor", { NVPTX::SM60, NVPTX::PTX50 }, { } },
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  { "sm_61", "Select the sm_61 processor", { NVPTX::SM61, NVPTX::PTX50 }, { } },
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  { "sm_62", "Select the sm_62 processor", { NVPTX::SM62, NVPTX::PTX50 }, { } },
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  { "sm_70", "Select the sm_70 processor", { NVPTX::SM70, NVPTX::PTX60 }, { } },
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  { "sm_72", "Select the sm_72 processor", { NVPTX::SM72, NVPTX::PTX61 }, { } },
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};
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#ifdef DBGFIELD
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#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
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#endif
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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#define DBGFIELD(x) x,
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#else
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#define DBGFIELD(x)
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#endif
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// ===============================================================
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// Data tables for the new per-operand machine model.
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// {ProcResourceIdx, Cycles}
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extern const llvm::MCWriteProcResEntry NVPTXWriteProcResTable[] = {
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  { 0,  0}, // Invalid
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}; // NVPTXWriteProcResTable
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// {Cycles, WriteResourceID}
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extern const llvm::MCWriteLatencyEntry NVPTXWriteLatencyTable[] = {
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  { 0,  0}, // Invalid
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}; // NVPTXWriteLatencyTable
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// {UseIdx, WriteResourceID, Cycles}
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extern const llvm::MCReadAdvanceEntry NVPTXReadAdvanceTable[] = {
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  {0,  0,  0}, // Invalid
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}; // NVPTXReadAdvanceTable
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static const llvm::MCSchedModel NoSchedModel = {
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  MCSchedModel::DefaultIssueWidth,
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  MCSchedModel::DefaultMicroOpBufferSize,
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  MCSchedModel::DefaultLoopMicroOpBufferSize,
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  MCSchedModel::DefaultLoadLatency,
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  MCSchedModel::DefaultHighLatency,
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  MCSchedModel::DefaultMispredictPenalty,
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  false, // PostRAScheduler
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  false, // CompleteModel
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  0, // Processor ID
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  nullptr, nullptr, 0, 0, // No instruction-level machine model.
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  nullptr, // No Itinerary
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  nullptr // No extra processor descriptor
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};
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// Sorted (by key) array of itineraries for CPU subtype.
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extern const llvm::SubtargetInfoKV NVPTXProcSchedKV[] = {
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  { "sm_20", (const void *)&NoSchedModel },
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  { "sm_21", (const void *)&NoSchedModel },
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  { "sm_30", (const void *)&NoSchedModel },
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  { "sm_32", (const void *)&NoSchedModel },
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  { "sm_35", (const void *)&NoSchedModel },
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  { "sm_37", (const void *)&NoSchedModel },
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  { "sm_50", (const void *)&NoSchedModel },
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  { "sm_52", (const void *)&NoSchedModel },
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  { "sm_53", (const void *)&NoSchedModel },
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  { "sm_60", (const void *)&NoSchedModel },
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  { "sm_61", (const void *)&NoSchedModel },
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  { "sm_62", (const void *)&NoSchedModel },
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  { "sm_70", (const void *)&NoSchedModel },
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  { "sm_72", (const void *)&NoSchedModel },
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};
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#undef DBGFIELD
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namespace NVPTX_MC {
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unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
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0
    const MCInst *MI, unsigned CPUID) {
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  // Don't know how to resolve this scheduling class.
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  return 0;
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}
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} // end of namespace NVPTX_MC
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struct NVPTXGenMCSubtargetInfo : public MCSubtargetInfo {
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  NVPTXGenMCSubtargetInfo(const Triple &TT, 
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    StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
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    ArrayRef<SubtargetFeatureKV> PD,
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    const SubtargetInfoKV *ProcSched,
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    const MCWriteProcResEntry *WPR,
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    const MCWriteLatencyEntry *WL,
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    const MCReadAdvanceEntry *RA, const InstrStage *IS,
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    const unsigned *OC, const unsigned *FP) :
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      MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched,
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                      WPR, WL, RA, IS, OC, FP) { }
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  unsigned resolveVariantSchedClass(unsigned SchedClass,
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      const MCInst *MI, unsigned CPUID) const override {
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    return NVPTX_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID); 
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  }
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};
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static inline MCSubtargetInfo *createNVPTXMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) {
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  return new NVPTXGenMCSubtargetInfo(TT, CPU, FS, NVPTXFeatureKV, NVPTXSubTypeKV, 
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                      NVPTXProcSchedKV, NVPTXWriteProcResTable, NVPTXWriteLatencyTable, NVPTXReadAdvanceTable, 
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                      nullptr, nullptr, nullptr);
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}
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} // end namespace llvm
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#endif // GET_SUBTARGETINFO_MC_DESC
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#ifdef GET_SUBTARGETINFO_TARGET_DESC
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#undef GET_SUBTARGETINFO_TARGET_DESC
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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// ParseSubtargetFeatures - Parses features string setting specified
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// subtarget options.
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void llvm::NVPTXSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {
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  LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
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  LLVM_DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n");
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  InitMCProcessorInfo(CPU, FS);
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  const FeatureBitset& Bits = getFeatureBits();
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  if (Bits[NVPTX::PTX32] && PTXVersion < 32) PTXVersion = 32;
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  if (Bits[NVPTX::PTX40] && PTXVersion < 40) PTXVersion = 40;
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  if (Bits[NVPTX::PTX41] && PTXVersion < 41) PTXVersion = 41;
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  if (Bits[NVPTX::PTX42] && PTXVersion < 42) PTXVersion = 42;
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  if (Bits[NVPTX::PTX43] && PTXVersion < 43) PTXVersion = 43;
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  if (Bits[NVPTX::PTX50] && PTXVersion < 50) PTXVersion = 50;
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  if (Bits[NVPTX::PTX60] && PTXVersion < 60) PTXVersion = 60;
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  if (Bits[NVPTX::PTX61] && PTXVersion < 61) PTXVersion = 61;
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  if (Bits[NVPTX::SM20] && SmVersion < 20) SmVersion = 20;
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  if (Bits[NVPTX::SM21] && SmVersion < 21) SmVersion = 21;
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  if (Bits[NVPTX::SM30] && SmVersion < 30) SmVersion = 30;
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  if (Bits[NVPTX::SM32] && SmVersion < 32) SmVersion = 32;
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  if (Bits[NVPTX::SM35] && SmVersion < 35) SmVersion = 35;
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  if (Bits[NVPTX::SM37] && SmVersion < 37) SmVersion = 37;
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  if (Bits[NVPTX::SM50] && SmVersion < 50) SmVersion = 50;
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  if (Bits[NVPTX::SM52] && SmVersion < 52) SmVersion = 52;
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  if (Bits[NVPTX::SM53] && SmVersion < 53) SmVersion = 53;
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  if (Bits[NVPTX::SM60] && SmVersion < 60) SmVersion = 60;
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  if (Bits[NVPTX::SM61] && SmVersion < 61) SmVersion = 61;
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  if (Bits[NVPTX::SM62] && SmVersion < 62) SmVersion = 62;
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  if (Bits[NVPTX::SM70] && SmVersion < 70) SmVersion = 70;
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  if (Bits[NVPTX::SM72] && SmVersion < 72) SmVersion = 72;
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}
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#endif // GET_SUBTARGETINFO_TARGET_DESC
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#ifdef GET_SUBTARGETINFO_HEADER
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#undef GET_SUBTARGETINFO_HEADER
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namespace llvm {
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class DFAPacketizer;
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namespace NVPTX_MC {
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unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
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}
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struct NVPTXGenSubtargetInfo : public TargetSubtargetInfo {
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  explicit NVPTXGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS);
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public:
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  unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
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  unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
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  DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
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};
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} // end namespace llvm
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#endif // GET_SUBTARGETINFO_HEADER
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#ifdef GET_SUBTARGETINFO_CTOR
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#undef GET_SUBTARGETINFO_CTOR
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#include "llvm/CodeGen/TargetSchedule.h"
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namespace llvm {
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extern const llvm::SubtargetFeatureKV NVPTXFeatureKV[];
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extern const llvm::SubtargetFeatureKV NVPTXSubTypeKV[];
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extern const llvm::SubtargetInfoKV NVPTXProcSchedKV[];
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extern const llvm::MCWriteProcResEntry NVPTXWriteProcResTable[];
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extern const llvm::MCWriteLatencyEntry NVPTXWriteLatencyTable[];
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extern const llvm::MCReadAdvanceEntry NVPTXReadAdvanceTable[];
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NVPTXGenSubtargetInfo::NVPTXGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
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  : TargetSubtargetInfo(TT, CPU, FS, makeArrayRef(NVPTXFeatureKV, 22), makeArrayRef(NVPTXSubTypeKV, 14), 
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                        NVPTXProcSchedKV, NVPTXWriteProcResTable, NVPTXWriteLatencyTable, NVPTXReadAdvanceTable, 
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                        nullptr, nullptr, nullptr) {}
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unsigned NVPTXGenSubtargetInfo
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0
::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
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  report_fatal_error("Expected a variant SchedClass");
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} // NVPTXGenSubtargetInfo::resolveSchedClass
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unsigned NVPTXGenSubtargetInfo
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::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
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  return NVPTX_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
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} // NVPTXGenSubtargetInfo::resolveVariantSchedClass
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} // end namespace llvm
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#endif // GET_SUBTARGETINFO_CTOR
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#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
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#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
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#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
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#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
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#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
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#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
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