Coverage Report

Created: 2018-09-23 22:08

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/PowerPC/PPCGenAsmMatcher.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Assembly Matcher Source Fragment                                           *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
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10
#ifdef GET_ASSEMBLER_HEADER
11
#undef GET_ASSEMBLER_HEADER
12
  // This should be included into the middle of the declaration of
13
  // your subclasses implementation of MCTargetAsmParser.
14
  uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;
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  void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
16
                       const OperandVector &Operands);
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  void convertToMapAndConstraints(unsigned Kind,
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                           const OperandVector &Operands) override;
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  unsigned MatchInstructionImpl(const OperandVector &Operands,
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                                MCInst &Inst,
21
                                uint64_t &ErrorInfo,
22
                                bool matchingInlineAsm,
23
                                unsigned VariantID = 0);
24
#endif // GET_ASSEMBLER_HEADER_INFO
25
26
27
#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
28
#undef GET_OPERAND_DIAGNOSTIC_TYPES
29
30
#endif // GET_OPERAND_DIAGNOSTIC_TYPES
31
32
33
#ifdef GET_REGISTER_MATCHER
34
#undef GET_REGISTER_MATCHER
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36
// Flags for subtarget features that participate in instruction matching.
37
enum SubtargetFeatureFlag : uint8_t {
38
  Feature_None = 0
39
};
40
41
#endif // GET_REGISTER_MATCHER
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43
44
#ifdef GET_SUBTARGET_FEATURE_NAME
45
#undef GET_SUBTARGET_FEATURE_NAME
46
47
// User-level names for subtarget features that participate in
48
// instruction matching.
49
static const char *getSubtargetFeatureName(uint64_t Val) {
50
  return "(unknown)";
51
}
52
53
#endif // GET_SUBTARGET_FEATURE_NAME
54
55
56
#ifdef GET_MATCHER_IMPLEMENTATION
57
#undef GET_MATCHER_IMPLEMENTATION
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59
7.18k
static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features, unsigned VariantID) {
60
7.18k
  switch (VariantID) {
61
7.18k
    case 0:
62
7.18k
      switch (Mnemonic.size()) {
63
7.18k
      
default: break4.67k
;
64
7.18k
      case 5:  // 1 string to match.
65
1.46k
        if (memcmp(Mnemonic.data()+0, "cntlz", 5) != 0)
66
1.45k
          break;
67
4
        Mnemonic = "cntlzw";   // "cntlz"
68
4
        return;
69
1.05k
      case 6:  // 1 string to match.
70
1.05k
        if (memcmp(Mnemonic.data()+0, "cntlz.", 6) != 0)
71
1.05k
          break;
72
0
        Mnemonic = "cntlzw.";  // "cntlz."
73
0
        return;
74
7.18k
      }
75
7.18k
    break;
76
7.18k
  }
77
7.18k
  switch (Mnemonic.size()) {
78
7.18k
  
default: break4.67k
;
79
7.18k
  case 5:  // 1 string to match.
80
1.45k
    if (memcmp(Mnemonic.data()+0, "cntlz", 5) != 0)
81
1.45k
      break;
82
0
    Mnemonic = "cntlzw";   // "cntlz"
83
0
    return;
84
1.05k
  case 6:  // 1 string to match.
85
1.05k
    if (memcmp(Mnemonic.data()+0, "cntlz.", 6) != 0)
86
1.05k
      break;
87
0
    Mnemonic = "cntlzw.";  // "cntlz."
88
0
    return;
89
7.18k
  }
90
7.18k
}
91
92
enum {
93
  Tie0_1_1,
94
};
95
96
static const uint8_t TiedAsmOperandTable[][3] = {
97
  /* Tie0_1_1 */ { 0, 1, 1 },
98
};
99
100
namespace {
101
enum OperatorConversionKind {
102
  CVT_Done,
103
  CVT_Reg,
104
  CVT_Tied,
105
  CVT_95_addRegG8RCOperands,
106
  CVT_95_addTLSRegOperands,
107
  CVT_95_addRegGPRCOperands,
108
  CVT_95_addRegGPRCNoR0Operands,
109
  CVT_95_addS16ImmOperands,
110
  CVT_95_addImmOperands,
111
  CVT_95_addU16ImmOperands,
112
  CVT_95_addBranchTargetOperands,
113
  CVT_95_addRegCRBITRCOperands,
114
  CVT_imm_95_3,
115
  CVT_imm_95_2,
116
  CVT_imm_95_0,
117
  CVT_95_addRegVRRCOperands,
118
  CVT_imm_95_8,
119
  CVT_imm_95_10,
120
  CVT_imm_95_76,
121
  CVT_regCR0,
122
  CVT_95_addRegCRRCOperands,
123
  CVT_imm_95_79,
124
  CVT_imm_95_78,
125
  CVT_imm_95_4,
126
  CVT_imm_95_7,
127
  CVT_imm_95_6,
128
  CVT_imm_95_44,
129
  CVT_imm_95_47,
130
  CVT_imm_95_46,
131
  CVT_imm_95_36,
132
  CVT_imm_95_39,
133
  CVT_imm_95_38,
134
  CVT_imm_95_12,
135
  CVT_imm_95_15,
136
  CVT_imm_95_14,
137
  CVT_imm_95_68,
138
  CVT_imm_95_71,
139
  CVT_imm_95_70,
140
  CVT_imm_95_100,
141
  CVT_imm_95_103,
142
  CVT_imm_95_102,
143
  CVT_imm_95_108,
144
  CVT_imm_95_111,
145
  CVT_imm_95_110,
146
  CVT_imm_95_31,
147
  CVT_95_addRegGxRCNoR0Operands,
148
  CVT_95_addRegGxRCOperands,
149
  CVT_regR0,
150
  CVT_95_addRegSPERCOperands,
151
  CVT_95_addRegSPE4RCOperands,
152
  CVT_95_addRegF4RCOperands,
153
  CVT_95_addRegF8RCOperands,
154
  CVT_imm_95_1,
155
  CVT_95_addRegVFRCOperands,
156
  CVT_95_addRegVSFRCOperands,
157
  CVT_95_addRegVSSRCOperands,
158
  CVT_95_addRegVSRCOperands,
159
  CVT_imm_95_29,
160
  CVT_imm_95_280,
161
  CVT_imm_95_128,
162
  CVT_imm_95_129,
163
  CVT_imm_95_130,
164
  CVT_imm_95_131,
165
  CVT_imm_95_132,
166
  CVT_imm_95_133,
167
  CVT_imm_95_134,
168
  CVT_imm_95_135,
169
  CVT_imm_95_28,
170
  CVT_imm_95_19,
171
  CVT_imm_95_537,
172
  CVT_imm_95_539,
173
  CVT_imm_95_541,
174
  CVT_imm_95_543,
175
  CVT_imm_95_536,
176
  CVT_imm_95_538,
177
  CVT_imm_95_540,
178
  CVT_imm_95_542,
179
  CVT_imm_95_1018,
180
  CVT_imm_95_981,
181
  CVT_imm_95_22,
182
  CVT_imm_95_17,
183
  CVT_imm_95_18,
184
  CVT_imm_95_980,
185
  CVT_imm_95_529,
186
  CVT_imm_95_531,
187
  CVT_imm_95_533,
188
  CVT_imm_95_535,
189
  CVT_imm_95_528,
190
  CVT_imm_95_530,
191
  CVT_imm_95_532,
192
  CVT_imm_95_534,
193
  CVT_imm_95_1019,
194
  CVT_95_addCRBitMaskOperands,
195
  CVT_imm_95_48,
196
  CVT_imm_95_287,
197
  CVT_imm_95_5,
198
  CVT_imm_95_25,
199
  CVT_imm_95_512,
200
  CVT_imm_95_272,
201
  CVT_imm_95_273,
202
  CVT_imm_95_274,
203
  CVT_imm_95_275,
204
  CVT_imm_95_260,
205
  CVT_imm_95_261,
206
  CVT_imm_95_262,
207
  CVT_imm_95_263,
208
  CVT_imm_95_26,
209
  CVT_imm_95_27,
210
  CVT_imm_95_990,
211
  CVT_imm_95_991,
212
  CVT_imm_95_268,
213
  CVT_imm_95_988,
214
  CVT_imm_95_989,
215
  CVT_imm_95_269,
216
  CVT_imm_95_986,
217
  CVT_imm_95_255,
218
  CVT_imm_95_284,
219
  CVT_imm_95_285,
220
  CVT_95_addRegG8RCNoX0Operands,
221
  CVT_95_addRegQFRCOperands,
222
  CVT_95_addRegQSRCOperands,
223
  CVT_95_addRegQBRCOperands,
224
  CVT_imm_95_9,
225
  CVT_imm_95_13,
226
  CVT_imm_95_20,
227
  CVT_imm_95_16,
228
  CVT_imm_95_24,
229
  CVT_NUM_CONVERTERS
230
};
231
232
enum InstructionConversionKind {
233
  Convert__RegG8RC1_0__RegG8RC1_1__TLSReg1_2,
234
  Convert__RegGPRC1_0__RegGPRC1_1__RegGPRC1_2,
235
  Convert__RegGPRC1_1__RegGPRC1_2__RegGPRC1_3,
236
  Convert__RegGPRC1_0__RegGPRCNoR01_1__S16Imm1_2,
237
  Convert__RegGPRC1_0__RegGPRC1_1__S16Imm1_2,
238
  Convert__RegGPRC1_1__RegGPRC1_2__S16Imm1_3,
239
  Convert__RegGPRC1_0__RegGPRCNoR01_1__S17Imm1_2,
240
  Convert__RegGPRC1_0__RegGPRC1_1,
241
  Convert__RegGPRC1_1__RegGPRC1_2,
242
  Convert__RegG8RC1_0__Imm1_1,
243
  Convert__RegGPRC1_1__RegGPRC1_2__U16Imm1_3,
244
  Convert_NoOperands,
245
  Convert__DirectBr1_0,
246
  Convert__U5Imm1_0__RegCRBITRC1_1__CondBr1_2,
247
  Convert__U5Imm1_1__ATBitsAsHint1_0__RegCRBITRC1_2__CondBr1_3,
248
  Convert__U5Imm1_0__imm_95_3__RegCRBITRC1_1__CondBr1_2,
249
  Convert__U5Imm1_0__imm_95_2__RegCRBITRC1_1__CondBr1_2,
250
  Convert__U5Imm1_0__RegCRBITRC1_1__imm_95_0,
251
  Convert__U5Imm1_0__RegCRBITRC1_1__Imm1_2,
252
  Convert__RegVRRC1_1__RegVRRC1_2__U1Imm1_3,
253
  Convert__RegVRRC1_1__RegVRRC1_2__RegVRRC1_3,
254
  Convert__RegVRRC1_1__RegVRRC1_2,
255
  Convert__RegVRRC1_1__RegVRRC1_2__RegVRRC1_3__U1Imm1_4,
256
  Convert__CondBr1_0,
257
  Convert__imm_95_0__RegCRBITRC1_0__CondBr1_1,
258
  Convert__imm_95_0__RegCRBITRC1_0__imm_95_0,
259
  Convert__imm_95_8__RegCRBITRC1_0__CondBr1_1,
260
  Convert__imm_95_8__RegCRBITRC1_0__imm_95_0,
261
  Convert__imm_95_2__RegCRBITRC1_0__CondBr1_1,
262
  Convert__imm_95_2__RegCRBITRC1_0__imm_95_0,
263
  Convert__imm_95_10__RegCRBITRC1_0__CondBr1_1,
264
  Convert__imm_95_10__RegCRBITRC1_0__imm_95_0,
265
  Convert__imm_95_76__regCR0__CondBr1_0,
266
  Convert__imm_95_76__RegCRRC1_0__CondBr1_1,
267
  Convert__imm_95_79__regCR0__CondBr1_0,
268
  Convert__imm_95_79__RegCRRC1_0__CondBr1_1,
269
  Convert__imm_95_78__regCR0__CondBr1_0,
270
  Convert__imm_95_78__RegCRRC1_0__CondBr1_1,
271
  Convert__imm_95_76__regCR0,
272
  Convert__imm_95_76__RegCRRC1_0,
273
  Convert__imm_95_79__regCR0,
274
  Convert__imm_95_79__RegCRRC1_0,
275
  Convert__imm_95_78__regCR0,
276
  Convert__imm_95_78__RegCRRC1_0,
277
  Convert__imm_95_4__RegCRBITRC1_0__CondBr1_1,
278
  Convert__imm_95_7__RegCRBITRC1_0__CondBr1_1,
279
  Convert__imm_95_6__RegCRBITRC1_0__CondBr1_1,
280
  Convert__imm_95_4__RegCRBITRC1_0__imm_95_0,
281
  Convert__imm_95_7__RegCRBITRC1_0__imm_95_0,
282
  Convert__imm_95_6__RegCRBITRC1_0__imm_95_0,
283
  Convert__imm_95_4__regCR0__CondBr1_0,
284
  Convert__imm_95_4__RegCRRC1_0__CondBr1_1,
285
  Convert__imm_95_7__regCR0__CondBr1_0,
286
  Convert__imm_95_7__RegCRRC1_0__CondBr1_1,
287
  Convert__imm_95_6__regCR0__CondBr1_0,
288
  Convert__imm_95_6__RegCRRC1_0__CondBr1_1,
289
  Convert__imm_95_4__regCR0,
290
  Convert__imm_95_4__RegCRRC1_0,
291
  Convert__imm_95_7__regCR0,
292
  Convert__imm_95_7__RegCRRC1_0,
293
  Convert__imm_95_6__regCR0,
294
  Convert__imm_95_6__RegCRRC1_0,
295
  Convert__imm_95_44__regCR0__CondBr1_0,
296
  Convert__imm_95_44__RegCRRC1_0__CondBr1_1,
297
  Convert__imm_95_47__regCR0__CondBr1_0,
298
  Convert__imm_95_47__RegCRRC1_0__CondBr1_1,
299
  Convert__imm_95_46__regCR0__CondBr1_0,
300
  Convert__imm_95_46__RegCRRC1_0__CondBr1_1,
301
  Convert__imm_95_44__regCR0,
302
  Convert__imm_95_44__RegCRRC1_0,
303
  Convert__imm_95_47__regCR0,
304
  Convert__imm_95_47__RegCRRC1_0,
305
  Convert__imm_95_46__regCR0,
306
  Convert__imm_95_46__RegCRRC1_0,
307
  Convert__DirectBr1_0__Imm1_1,
308
  Convert__imm_95_36__regCR0__CondBr1_0,
309
  Convert__imm_95_36__RegCRRC1_0__CondBr1_1,
310
  Convert__imm_95_39__regCR0__CondBr1_0,
311
  Convert__imm_95_39__RegCRRC1_0__CondBr1_1,
312
  Convert__imm_95_38__regCR0__CondBr1_0,
313
  Convert__imm_95_38__RegCRRC1_0__CondBr1_1,
314
  Convert__imm_95_36__regCR0,
315
  Convert__imm_95_36__RegCRRC1_0,
316
  Convert__imm_95_39__regCR0,
317
  Convert__imm_95_39__RegCRRC1_0,
318
  Convert__imm_95_38__regCR0,
319
  Convert__imm_95_38__RegCRRC1_0,
320
  Convert__imm_95_12__regCR0__CondBr1_0,
321
  Convert__imm_95_12__RegCRRC1_0__CondBr1_1,
322
  Convert__imm_95_15__regCR0__CondBr1_0,
323
  Convert__imm_95_15__RegCRRC1_0__CondBr1_1,
324
  Convert__imm_95_14__regCR0__CondBr1_0,
325
  Convert__imm_95_14__RegCRRC1_0__CondBr1_1,
326
  Convert__imm_95_12__regCR0,
327
  Convert__imm_95_12__RegCRRC1_0,
328
  Convert__imm_95_15__regCR0,
329
  Convert__imm_95_15__RegCRRC1_0,
330
  Convert__imm_95_14__regCR0,
331
  Convert__imm_95_14__RegCRRC1_0,
332
  Convert__imm_95_68__regCR0__CondBr1_0,
333
  Convert__imm_95_68__RegCRRC1_0__CondBr1_1,
334
  Convert__imm_95_71__regCR0__CondBr1_0,
335
  Convert__imm_95_71__RegCRRC1_0__CondBr1_1,
336
  Convert__imm_95_70__regCR0__CondBr1_0,
337
  Convert__imm_95_70__RegCRRC1_0__CondBr1_1,
338
  Convert__imm_95_68__regCR0,
339
  Convert__imm_95_68__RegCRRC1_0,
340
  Convert__imm_95_71__regCR0,
341
  Convert__imm_95_71__RegCRRC1_0,
342
  Convert__imm_95_70__regCR0,
343
  Convert__imm_95_70__RegCRRC1_0,
344
  Convert__imm_95_100__regCR0__CondBr1_0,
345
  Convert__imm_95_100__RegCRRC1_0__CondBr1_1,
346
  Convert__imm_95_103__regCR0__CondBr1_0,
347
  Convert__imm_95_103__RegCRRC1_0__CondBr1_1,
348
  Convert__imm_95_102__regCR0__CondBr1_0,
349
  Convert__imm_95_102__RegCRRC1_0__CondBr1_1,
350
  Convert__imm_95_100__regCR0,
351
  Convert__imm_95_100__RegCRRC1_0,
352
  Convert__imm_95_103__regCR0,
353
  Convert__imm_95_103__RegCRRC1_0,
354
  Convert__imm_95_102__regCR0,
355
  Convert__imm_95_102__RegCRRC1_0,
356
  Convert__RegG8RC1_0__RegG8RC1_1__RegG8RC1_2,
357
  Convert__imm_95_108__regCR0__CondBr1_0,
358
  Convert__imm_95_108__RegCRRC1_0__CondBr1_1,
359
  Convert__imm_95_111__regCR0__CondBr1_0,
360
  Convert__imm_95_111__RegCRRC1_0__CondBr1_1,
361
  Convert__imm_95_110__regCR0__CondBr1_0,
362
  Convert__imm_95_110__RegCRRC1_0__CondBr1_1,
363
  Convert__imm_95_108__regCR0,
364
  Convert__imm_95_108__RegCRRC1_0,
365
  Convert__imm_95_111__regCR0,
366
  Convert__imm_95_111__RegCRRC1_0,
367
  Convert__imm_95_110__regCR0,
368
  Convert__imm_95_110__RegCRRC1_0,
369
  Convert__imm_95_12__RegCRBITRC1_0__CondBr1_1,
370
  Convert__imm_95_15__RegCRBITRC1_0__CondBr1_1,
371
  Convert__imm_95_14__RegCRBITRC1_0__CondBr1_1,
372
  Convert__imm_95_12__RegCRBITRC1_0__imm_95_0,
373
  Convert__imm_95_15__RegCRBITRC1_0__imm_95_0,
374
  Convert__imm_95_14__RegCRBITRC1_0__imm_95_0,
375
  Convert__RegG8RC1_0__RegG8RC1_1__imm_95_0__U6Imm1_2,
376
  Convert__RegG8RC1_0__RegGPRC1_1__imm_95_0__U6Imm1_2,
377
  Convert__RegG8RC1_1__RegG8RC1_2__imm_95_0__U6Imm1_3,
378
  Convert__RegG8RC1_0__RegG8RC1_1__U6Imm1_2__U6Imm1_3,
379
  Convert__RegG8RC1_1__RegG8RC1_2__U6Imm1_3__U6Imm1_4,
380
  Convert__RegGPRC1_0__RegGPRC1_1__U5Imm1_2__U5Imm1_3,
381
  Convert__RegGPRC1_1__RegGPRC1_2__U5Imm1_3__U5Imm1_4,
382
  Convert__RegGPRC1_0__RegGPRC1_1__imm_95_0__U5Imm1_2__imm_95_31,
383
  Convert__RegGPRC1_1__RegGPRC1_2__imm_95_0__U5Imm1_3__imm_95_31,
384
  Convert__RegG8RC1_0__RegG8RC1_1__U6Imm1_2,
385
  Convert__RegG8RC1_1__RegG8RC1_2__U6Imm1_3,
386
  Convert__RegGPRC1_0__RegGPRC1_1__U5Imm1_2,
387
  Convert__RegGPRC1_1__RegGPRC1_2__U5Imm1_3,
388
  Convert__RegCRRC1_0__RegGPRC1_2__RegGPRC1_3,
389
  Convert__RegCRRC1_0__RegG8RC1_2__RegG8RC1_3,
390
  Convert__regCR0__RegG8RC1_0__RegG8RC1_1,
391
  Convert__RegCRRC1_0__RegG8RC1_1__RegG8RC1_2,
392
  Convert__regCR0__RegG8RC1_0__S16Imm1_1,
393
  Convert__RegCRRC1_0__RegG8RC1_1__S16Imm1_2,
394
  Convert__RegCRBITRC1_0__RegG8RC1_1__RegG8RC1_2,
395
  Convert__RegCRRC1_0__RegGPRC1_2__S16Imm1_3,
396
  Convert__RegCRRC1_0__RegG8RC1_2__S16Imm1_3,
397
  Convert__regCR0__RegG8RC1_0__U16Imm1_1,
398
  Convert__RegCRRC1_0__RegG8RC1_1__U16Imm1_2,
399
  Convert__RegCRRC1_0__RegGPRC1_2__U16Imm1_3,
400
  Convert__RegCRRC1_0__RegG8RC1_2__U16Imm1_3,
401
  Convert__regCR0__RegGPRC1_0__RegGPRC1_1,
402
  Convert__RegCRRC1_0__RegGPRC1_1__RegGPRC1_2,
403
  Convert__regCR0__RegGPRC1_0__U16Imm1_1,
404
  Convert__RegCRRC1_0__RegGPRC1_1__U16Imm1_2,
405
  Convert__RegCRBITRC1_0__U1Imm1_1__RegG8RC1_2__RegG8RC1_3,
406
  Convert__regCR0__RegGPRC1_0__S16Imm1_1,
407
  Convert__RegCRRC1_0__RegGPRC1_1__S16Imm1_2,
408
  Convert__RegG8RC1_0__RegG8RC1_1,
409
  Convert__RegG8RC1_1__RegG8RC1_2,
410
  Convert__RegGPRC1_0__RegGPRC1_1__U1Imm1_2,
411
  Convert__RegCRBITRC1_0__RegCRBITRC1_1__RegCRBITRC1_2,
412
  Convert__RegCRBITRC1_0__RegCRBITRC1_0__RegCRBITRC1_0,
413
  Convert__RegCRBITRC1_0__RegCRBITRC1_1__RegCRBITRC1_1,
414
  Convert__RegGxRCNoR01_0__RegGxRC1_1,
415
  Convert__U5Imm1_2__RegGxRCNoR01_0__RegGxRC1_1,
416
  Convert__RegGxRCNoR01_0__RegGxRC1_1__U5Imm1_2,
417
  Convert__RegGxRCNoR01_1__RegGxRC1_2__U5Imm1_0,
418
  Convert__regR0__regR0,
419
  Convert__RegG8RC1_1__RegG8RC1_2__RegG8RC1_3,
420
  Convert__U5Imm1_0,
421
  Convert__U5Imm1_2__RegGPRC1_0__RegGPRC1_1,
422
  Convert__RegSPERC1_0__RegSPERC1_1,
423
  Convert__RegSPERC1_0__RegSPERC1_1__RegSPERC1_2,
424
  Convert__RegSPERC1_0__RegSPE4RC1_1,
425
  Convert__RegSPERC1_0__RegGPRC1_1,
426
  Convert__RegCRRC1_0__RegSPERC1_1__RegSPERC1_2,
427
  Convert__RegGPRC1_0__RegSPERC1_1,
428
  Convert__RegSPE4RC1_0__RegSPE4RC1_1,
429
  Convert__RegSPE4RC1_0__RegSPE4RC1_1__RegSPE4RC1_2,
430
  Convert__RegSPE4RC1_0__RegSPERC1_1,
431
  Convert__RegSPE4RC1_0__RegGPRC1_1,
432
  Convert__RegCRRC1_0__RegSPE4RC1_1__RegSPE4RC1_2,
433
  Convert__RegGPRC1_0__RegSPE4RC1_1,
434
  Convert__RegSPERC1_0__RegSPERC1_2__U5Imm1_1,
435
  Convert__RegSPERC1_0__DispSPE81_1__RegGxRCNoR01_2,
436
  Convert__RegSPERC1_0__RegGxRCNoR01_1__RegGxRC1_2,
437
  Convert__RegSPERC1_0__DispSPE21_1__RegGxRCNoR01_2,
438
  Convert__RegSPERC1_0__DispSPE41_1__RegGxRCNoR01_2,
439
  Convert__RegSPERC1_0__RegSPERC1_1__U5Imm1_2,
440
  Convert__RegSPERC1_1__RegSPERC1_2__RegSPERC1_3__imm_95_0,
441
  Convert__RegSPERC1_0__S5Imm1_1,
442
  Convert__RegSPERC1_0__U5Imm1_1__RegSPERC1_2,
443
  Convert__RegG8RC1_0__RegGPRC1_1__U6Imm1_2,
444
  Convert__RegG8RC1_1__RegGPRC1_2__U6Imm1_3,
445
  Convert__RegF4RC1_0__RegF4RC1_1,
446
  Convert__RegF4RC1_1__RegF4RC1_2,
447
  Convert__RegF8RC1_0__RegF8RC1_1__RegF8RC1_2,
448
  Convert__RegF8RC1_1__RegF8RC1_2__RegF8RC1_3,
449
  Convert__RegF4RC1_0__RegF4RC1_1__RegF4RC1_2,
450
  Convert__RegF4RC1_1__RegF4RC1_2__RegF4RC1_3,
451
  Convert__RegF8RC1_0__RegF8RC1_1,
452
  Convert__RegF8RC1_1__RegF8RC1_2,
453
  Convert__RegF4RC1_0__RegF8RC1_1,
454
  Convert__RegF4RC1_1__RegF8RC1_2,
455
  Convert__RegCRRC1_0__RegF4RC1_1__RegF4RC1_2,
456
  Convert__RegF8RC1_0__RegF8RC1_1__RegF8RC1_2__RegF8RC1_3,
457
  Convert__RegF8RC1_1__RegF8RC1_2__RegF8RC1_3__RegF8RC1_4,
458
  Convert__RegF4RC1_0__RegF4RC1_1__RegF4RC1_2__RegF4RC1_3,
459
  Convert__RegF4RC1_1__RegF4RC1_2__RegF4RC1_3__RegF4RC1_4,
460
  Convert__RegF4RC1_0__RegF8RC1_1__RegF4RC1_2__RegF4RC1_3,
461
  Convert__RegF4RC1_1__RegF8RC1_2__RegF4RC1_3__RegF4RC1_4,
462
  Convert__RegCRRC1_0__RegF8RC1_1__RegF8RC1_2,
463
  Convert__RegCRRC1_0__RegF8RC1_1,
464
  Convert__U4Imm1_0__RegGxRCNoR01_1__RegGxRC1_2,
465
  Convert__U4Imm1_1__RegGxRCNoR01_2__RegGxRC1_3,
466
  Convert__RegGPRC1_0__RegGPRCNoR01_1__RegGPRC1_2__RegCRBITRC1_3,
467
  Convert__RegGPRC1_0__DispRI1_1__RegGxRCNoR01_2,
468
  Convert__RegGPRC1_0__RegGxRCNoR01_1__RegGxRC1_2,
469
  Convert__RegGPRC1_0__imm_95_0__DispRI1_1__RegGxRCNoR01_2,
470
  Convert__RegGPRC1_0__imm_95_0__RegGxRCNoR01_1__RegGxRC1_2,
471
  Convert__RegG8RC1_0__RegGxRCNoR01_1__TLSReg1_2,
472
  Convert__RegG8RC1_0__DispRIX1_1__RegGxRCNoR01_2,
473
  Convert__RegG8RC1_0__RegGxRCNoR01_1__RegGxRC1_2,
474
  Convert__RegG8RC1_0__RegG8RC1_1__U5Imm1_2,
475
  Convert__RegG8RC1_0__imm_95_0__DispRIX1_1__RegGxRCNoR01_2,
476
  Convert__RegG8RC1_0__imm_95_0__RegGxRCNoR01_1__RegGxRC1_2,
477
  Convert__RegF8RC1_0__DispRI1_1__RegGxRCNoR01_2,
478
  Convert__RegF8RC1_0__RegGxRCNoR01_1__RegGxRC1_2,
479
  Convert__RegF8RC1_0__imm_95_0__DispRI1_1__RegGxRCNoR01_2,
480
  Convert__RegF8RC1_0__imm_95_0__RegGxRCNoR01_1__RegGxRC1_2,
481
  Convert__RegF4RC1_0__DispRI1_1__RegGxRCNoR01_2,
482
  Convert__RegF4RC1_0__imm_95_0__DispRI1_1__RegGxRCNoR01_2,
483
  Convert__RegF4RC1_0__imm_95_0__RegGxRCNoR01_1__RegGxRC1_2,
484
  Convert__RegF4RC1_0__RegGxRCNoR01_1__RegGxRC1_2,
485
  Convert__RegGPRC1_0__S16Imm1_1,
486
  Convert__RegGPRC1_0__S17Imm1_1,
487
  Convert__RegG8RC1_0__imm_95_0,
488
  Convert__RegVRRC1_0__RegGxRCNoR01_1__RegGxRC1_2,
489
  Convert__imm_95_1,
490
  Convert__RegSPE4RC1_0__DispRI1_1__RegGxRCNoR01_2,
491
  Convert__RegSPE4RC1_0__RegGxRCNoR01_1__RegGxRC1_2,
492
  Convert__RegVFRC1_0__DispRIX1_1__RegGxRCNoR01_2,
493
  Convert__RegVSFRC1_0__RegGxRCNoR01_1__RegGxRC1_2,
494
  Convert__RegVSSRC1_0__RegGxRCNoR01_1__RegGxRC1_2,
495
  Convert__RegVSRC1_0__DispRIX161_1__RegGxRCNoR01_2,
496
  Convert__RegVSRC1_0__RegGxRCNoR01_1__RegGxRC1_2,
497
  Convert__RegVSRC1_0__Imm1_1__RegG8RC1_2,
498
  Convert__RegG8RC1_0__RegG8RC1_1__RegG8RC1_2__RegG8RC1_3,
499
  Convert__imm_95_0,
500
  Convert__RegCRRC1_0__RegCRRC1_1,
501
  Convert__RegCRRC1_0,
502
  Convert__RegGPRC1_0__imm_95_29,
503
  Convert__RegGPRC1_0__imm_95_280,
504
  Convert__RegGPRC1_0__U10Imm1_1__imm_95_0,
505
  Convert__RegGPRC1_0__imm_95_128,
506
  Convert__RegGPRC1_0__imm_95_129,
507
  Convert__RegGPRC1_0__imm_95_130,
508
  Convert__RegGPRC1_0__imm_95_131,
509
  Convert__RegGPRC1_0__imm_95_132,
510
  Convert__RegGPRC1_0__imm_95_133,
511
  Convert__RegGPRC1_0__imm_95_134,
512
  Convert__RegGPRC1_0__imm_95_135,
513
  Convert__RegGPRC1_0__imm_95_28,
514
  Convert__RegGPRC1_0,
515
  Convert__RegGPRC1_0__imm_95_19,
516
  Convert__RegGPRC1_0__imm_95_537,
517
  Convert__RegGPRC1_0__imm_95_539,
518
  Convert__RegGPRC1_0__imm_95_541,
519
  Convert__RegGPRC1_0__imm_95_543,
520
  Convert__RegGPRC1_0__imm_95_536,
521
  Convert__RegGPRC1_0__imm_95_538,
522
  Convert__RegGPRC1_0__imm_95_540,
523
  Convert__RegGPRC1_0__imm_95_542,
524
  Convert__RegGPRC1_0__imm_95_1018,
525
  Convert__RegGPRC1_0__Imm1_1,
526
  Convert__RegGPRC1_0__imm_95_981,
527
  Convert__RegGPRC1_0__imm_95_22,
528
  Convert__RegGPRC1_0__imm_95_17,
529
  Convert__RegGPRC1_0__imm_95_18,
530
  Convert__RegGPRC1_0__imm_95_980,
531
  Convert__RegG8RC1_0__RegF8RC1_1,
532
  Convert__RegF8RC1_0,
533
  Convert__RegF8RC1_1,
534
  Convert__RegF8RC1_0__U3Imm1_1,
535
  Convert__RegF8RC1_0__U2Imm1_1,
536
  Convert__RegGPRC1_0__imm_95_529,
537
  Convert__RegGPRC1_0__imm_95_531,
538
  Convert__RegGPRC1_0__imm_95_533,
539
  Convert__RegGPRC1_0__imm_95_535,
540
  Convert__RegGPRC1_0__imm_95_528,
541
  Convert__RegGPRC1_0__imm_95_530,
542
  Convert__RegGPRC1_0__imm_95_532,
543
  Convert__RegGPRC1_0__imm_95_534,
544
  Convert__RegGPRC1_0__imm_95_1019,
545
  Convert__RegGPRC1_0__CRBitMask1_1,
546
  Convert__RegGPRC1_0__imm_95_48,
547
  Convert__RegGPRC1_0__imm_95_287,
548
  Convert__RegGPRC1_0__imm_95_5,
549
  Convert__RegGPRC1_0__imm_95_4,
550
  Convert__RegGPRC1_0__imm_95_25,
551
  Convert__RegGPRC1_0__imm_95_512,
552
  Convert__RegGPRC1_0__imm_95_272,
553
  Convert__RegGPRC1_0__imm_95_273,
554
  Convert__RegGPRC1_0__imm_95_274,
555
  Convert__RegGPRC1_0__imm_95_275,
556
  Convert__RegGPRC1_0__imm_95_260,
557
  Convert__RegGPRC1_0__imm_95_261,
558
  Convert__RegGPRC1_0__imm_95_262,
559
  Convert__RegGPRC1_0__imm_95_263,
560
  Convert__RegGPRC1_0__U4Imm1_1,
561
  Convert__RegGPRC1_0__imm_95_26,
562
  Convert__RegGPRC1_0__imm_95_27,
563
  Convert__RegGPRC1_0__imm_95_990,
564
  Convert__RegGPRC1_0__imm_95_991,
565
  Convert__RegGPRC1_0__imm_95_268,
566
  Convert__RegGPRC1_0__imm_95_988,
567
  Convert__RegGPRC1_0__imm_95_989,
568
  Convert__RegGPRC1_0__imm_95_269,
569
  Convert__RegGPRC1_0__imm_95_986,
570
  Convert__RegG8RC1_0__RegVRRC1_1,
571
  Convert__RegVRRC1_0,
572
  Convert__RegG8RC1_0__RegVSFRC1_1,
573
  Convert__RegG8RC1_0__RegVSRC1_1,
574
  Convert__RegGPRC1_0__RegVSFRC1_1,
575
  Convert__RegGPRC1_0__imm_95_1,
576
  Convert__RegG8RC1_0__RegG8RC1_1__RegG8RC1_1,
577
  Convert__RegG8RC1_1__RegG8RC1_2__RegG8RC1_2,
578
  Convert__imm_95_29__RegGPRC1_0,
579
  Convert__imm_95_280__RegGPRC1_0,
580
  Convert__imm_95_28__RegGPRC1_0,
581
  Convert__imm_95_255__RegG8RC1_0,
582
  Convert__Imm1_0__RegGPRC1_1,
583
  Convert__imm_95_19__RegGPRC1_0,
584
  Convert__imm_95_537__RegGPRC1_1,
585
  Convert__imm_95_539__RegGPRC1_1,
586
  Convert__imm_95_541__RegGPRC1_1,
587
  Convert__imm_95_543__RegGPRC1_1,
588
  Convert__imm_95_536__RegGPRC1_1,
589
  Convert__imm_95_538__RegGPRC1_1,
590
  Convert__imm_95_540__RegGPRC1_1,
591
  Convert__imm_95_542__RegGPRC1_1,
592
  Convert__imm_95_1018__RegGPRC1_0,
593
  Convert__RegGPRC1_1__Imm1_0,
594
  Convert__imm_95_981__RegGPRC1_0,
595
  Convert__imm_95_22__RegGPRC1_0,
596
  Convert__imm_95_17__RegGPRC1_0,
597
  Convert__imm_95_18__RegGPRC1_0,
598
  Convert__imm_95_980__RegGPRC1_0,
599
  Convert__Imm1_0__RegF8RC1_1__imm_95_0__imm_95_0,
600
  Convert__Imm1_1__RegF8RC1_2__imm_95_0__imm_95_0,
601
  Convert__Imm1_0__RegF8RC1_1__Imm1_2__Imm1_3,
602
  Convert__Imm1_1__RegF8RC1_2__Imm1_3__Imm1_4,
603
  Convert__RegCRRC1_0__Imm1_1__imm_95_0,
604
  Convert__RegCRRC1_1__Imm1_2__imm_95_0,
605
  Convert__RegCRRC1_0__Imm1_1__Imm1_2,
606
  Convert__RegCRRC1_1__Imm1_2__Imm1_3,
607
  Convert__imm_95_529__RegGPRC1_1,
608
  Convert__imm_95_531__RegGPRC1_1,
609
  Convert__imm_95_533__RegGPRC1_1,
610
  Convert__imm_95_535__RegGPRC1_1,
611
  Convert__imm_95_528__RegGPRC1_1,
612
  Convert__imm_95_530__RegGPRC1_1,
613
  Convert__imm_95_532__RegGPRC1_1,
614
  Convert__imm_95_534__RegGPRC1_1,
615
  Convert__imm_95_1019__RegGPRC1_0,
616
  Convert__RegGPRC1_0__imm_95_0,
617
  Convert__CRBitMask1_0__RegGPRC1_1,
618
  Convert__imm_95_48__RegGPRC1_0,
619
  Convert__imm_95_25__RegGPRC1_0,
620
  Convert__imm_95_512__RegGPRC1_0,
621
  Convert__imm_95_272__RegGPRC1_1,
622
  Convert__imm_95_273__RegGPRC1_1,
623
  Convert__imm_95_274__RegGPRC1_1,
624
  Convert__imm_95_275__RegGPRC1_1,
625
  Convert__imm_95_260__RegGPRC1_1,
626
  Convert__imm_95_261__RegGPRC1_1,
627
  Convert__imm_95_262__RegGPRC1_1,
628
  Convert__imm_95_263__RegGPRC1_1,
629
  Convert__imm_95_272__RegGPRC1_0,
630
  Convert__imm_95_273__RegGPRC1_0,
631
  Convert__imm_95_274__RegGPRC1_0,
632
  Convert__imm_95_275__RegGPRC1_0,
633
  Convert__imm_95_260__RegGPRC1_0,
634
  Convert__imm_95_261__RegGPRC1_0,
635
  Convert__imm_95_262__RegGPRC1_0,
636
  Convert__imm_95_263__RegGPRC1_0,
637
  Convert__RegGPRC1_1__U4Imm1_0,
638
  Convert__imm_95_26__RegGPRC1_0,
639
  Convert__imm_95_27__RegGPRC1_0,
640
  Convert__imm_95_990__RegGPRC1_0,
641
  Convert__imm_95_991__RegGPRC1_0,
642
  Convert__imm_95_988__RegGPRC1_0,
643
  Convert__imm_95_284__RegGPRC1_0,
644
  Convert__imm_95_989__RegGPRC1_0,
645
  Convert__imm_95_285__RegGPRC1_0,
646
  Convert__imm_95_986__RegGPRC1_0,
647
  Convert__RegVSFRC1_0__RegG8RC1_1,
648
  Convert__RegVSRC1_0__RegG8RCNoX01_1__RegG8RC1_2,
649
  Convert__RegVSFRC1_0__RegGPRC1_1,
650
  Convert__RegVSRC1_0__RegGPRC1_1,
651
  Convert__imm_95_1__RegGPRC1_0,
652
  Convert__RegGPRC1_0__RegGPRC1_1__U16Imm1_2,
653
  Convert__RegGPRC1_1__RegGPRC1_2__U1Imm1_3,
654
  Convert__imm_95_2,
655
  Convert__RegQFRC1_0__RegQFRC1_1__RegQFRC1_2__U2Imm1_3,
656
  Convert__RegQFRC1_0__RegQFRC1_1__U2Imm1_2,
657
  Convert__RegQFRC1_0__RegQFRC1_1,
658
  Convert__RegQFRC1_0__RegQFRC1_1__RegQFRC1_2,
659
  Convert__RegQSRC1_0__RegQSRC1_1__RegQSRC1_2,
660
  Convert__RegQBRC1_0__RegQBRC1_1__RegQBRC1_2__imm_95_1,
661
  Convert__RegQBRC1_0__RegQBRC1_1__RegQBRC1_2__imm_95_4,
662
  Convert__RegQBRC1_0__RegQBRC1_0__RegQBRC1_0__imm_95_0,
663
  Convert__RegQBRC1_0__RegQFRC1_1__RegQFRC1_2,
664
  Convert__RegQBRC1_0__RegQBRC1_1__RegQBRC1_1__imm_95_5,
665
  Convert__RegQBRC1_0__RegQBRC1_1__RegQBRC1_2__imm_95_9,
666
  Convert__RegQBRC1_0__RegQBRC1_1__RegQBRC1_2__U12Imm1_3,
667
  Convert__RegQFRC1_0__RegQFRC1_1__RegQFRC1_3__RegQFRC1_2,
668
  Convert__RegQSRC1_0__RegQSRC1_1__RegQSRC1_3__RegQSRC1_2,
669
  Convert__RegQBRC1_0__RegQBRC1_1__RegQBRC1_2__imm_95_14,
670
  Convert__RegQBRC1_0__RegQBRC1_1__RegQBRC1_2__imm_95_8,
671
  Convert__RegQBRC1_0__RegQBRC1_1__RegQBRC1_1__imm_95_10,
672
  Convert__RegQBRC1_0__RegQBRC1_1__RegQBRC1_2__imm_95_7,
673
  Convert__RegQBRC1_0__RegQBRC1_1__RegQBRC1_2__imm_95_13,
674
  Convert__RegQFRC1_0__RegQFRC1_1__RegQFRC1_2__RegQFRC1_3,
675
  Convert__RegQSRC1_0__RegQFRC1_1,
676
  Convert__RegQFRC1_0__RegQBRC1_1__RegQFRC1_3__RegQFRC1_2,
677
  Convert__RegQBRC1_0__RegQBRC1_0__RegQBRC1_0__imm_95_15,
678
  Convert__RegQBRC1_0__RegQBRC1_1__RegQBRC1_2__imm_95_6,
679
  Convert__RegQFRC1_0__U12Imm1_1,
680
  Convert__RegQFRC1_0__RegGxRCNoR01_1__RegGxRC1_2,
681
  Convert__RegQFRC1_0__imm_95_0__RegGxRCNoR01_1__RegGxRC1_2,
682
  Convert__RegQSRC1_0__imm_95_0__RegGxRCNoR01_1__RegGxRC1_2,
683
  Convert__imm_95_0__RegQFRC1_0__RegGxRCNoR01_1__RegGxRC1_2,
684
  Convert__imm_95_0__RegQSRC1_0__RegGxRCNoR01_1__RegGxRC1_2,
685
  Convert__U1Imm1_0,
686
  Convert__RegG8RC1_0__RegG8RC1_1__RegGPRC1_2__U6Imm1_3,
687
  Convert__RegG8RC1_1__RegG8RC1_2__RegGPRC1_3__U6Imm1_4,
688
  Convert__RegG8RC1_0__Tie0_1_1__RegG8RC1_1__U6Imm1_2__U6Imm1_3,
689
  Convert__RegG8RC1_1__Tie0_1_1__RegG8RC1_2__U6Imm1_3__U6Imm1_4,
690
  Convert__RegG8RC1_0__RegG8RC1_1__U5Imm1_2__Imm1_3,
691
  Convert__RegG8RC1_1__RegG8RC1_2__U5Imm1_3__Imm1_4,
692
  Convert__RegGPRC1_0__Tie0_1_1__RegGPRC1_1__U5Imm1_2__U5Imm1_3__U5Imm1_4,
693
  Convert__RegGPRC1_1__Tie0_1_1__RegGPRC1_2__U5Imm1_3__U5Imm1_4__U5Imm1_5,
694
  Convert__RegGPRC1_0__RegGPRC1_1__U5Imm1_2__U5Imm1_3__U5Imm1_4,
695
  Convert__RegGPRC1_1__RegGPRC1_2__U5Imm1_3__U5Imm1_4__U5Imm1_5,
696
  Convert__RegGPRC1_0__RegGPRC1_1__RegGPRC1_2__U5Imm1_3__U5Imm1_4,
697
  Convert__RegGPRC1_1__RegGPRC1_2__RegGPRC1_3__U5Imm1_4__U5Imm1_5,
698
  Convert__RegG8RC1_0__RegG8RC1_1__RegGPRC1_2__imm_95_0,
699
  Convert__RegG8RC1_1__RegG8RC1_2__RegGPRC1_3__imm_95_0,
700
  Convert__RegG8RC1_0__RegG8RC1_1__U6Imm1_2__imm_95_0,
701
  Convert__RegG8RC1_1__RegG8RC1_2__U6Imm1_3__imm_95_0,
702
  Convert__RegGPRC1_0__RegGPRC1_1__RegGPRC1_2__imm_95_0__imm_95_31,
703
  Convert__RegGPRC1_1__RegGPRC1_2__RegGPRC1_3__imm_95_0__imm_95_31,
704
  Convert__RegGPRC1_0__RegGPRC1_1__U5Imm1_2__imm_95_0__imm_95_31,
705
  Convert__RegGPRC1_1__RegGPRC1_2__U5Imm1_3__imm_95_0__imm_95_31,
706
  Convert__Imm1_0,
707
  Convert__RegG8RC1_0__RegCRRC1_1,
708
  Convert__RegG8RC1_0__RegG8RC1_1__RegGPRC1_2,
709
  Convert__RegG8RC1_1__RegG8RC1_2__RegGPRC1_3,
710
  Convert__RegGPRC1_1__RegGxRCNoR01_2__RegGxRC1_3,
711
  Convert__imm_95_0__RegGPRC1_0__DispRI1_1__RegGxRCNoR01_2,
712
  Convert__imm_95_0__RegGPRC1_0__RegGxRCNoR01_1__RegGxRC1_2,
713
  Convert__RegG8RC1_1__RegGxRCNoR01_2__RegGxRC1_3,
714
  Convert__imm_95_0__RegG8RC1_0__DispRIX1_1__RegGxRCNoR01_2,
715
  Convert__imm_95_0__RegG8RC1_0__RegGxRCNoR01_1__RegGxRC1_2,
716
  Convert__imm_95_0__RegF8RC1_0__DispRI1_1__RegGxRCNoR01_2,
717
  Convert__imm_95_0__RegF8RC1_0__RegGxRCNoR01_1__RegGxRC1_2,
718
  Convert__imm_95_0__RegF4RC1_0__DispRI1_1__RegGxRCNoR01_2,
719
  Convert__imm_95_0__RegF4RC1_0__RegGxRCNoR01_1__RegGxRC1_2,
720
  Convert__RegG8RC1_0__RegG8RC1_2__RegG8RC1_1,
721
  Convert__RegG8RC1_1__RegG8RC1_3__RegG8RC1_2,
722
  Convert__RegG8RC1_0__S16Imm1_1,
723
  Convert__imm_95_0__RegGPRC1_1,
724
  Convert__imm_95_0__U5Imm1_1__RegGPRC1_2__RegGPRC1_3,
725
  Convert__imm_95_0__U5Imm1_1__RegGPRC1_2__U5Imm1_3,
726
  Convert__imm_95_0__U1Imm1_1,
727
  Convert__U5Imm1_0__RegG8RC1_1__RegG8RC1_2,
728
  Convert__imm_95_4__RegG8RC1_0__RegG8RC1_1,
729
  Convert__imm_95_4__RegG8RC1_0__S16Imm1_1,
730
  Convert__imm_95_12__RegG8RC1_0__RegG8RC1_1,
731
  Convert__imm_95_12__RegG8RC1_0__S16Imm1_1,
732
  Convert__imm_95_8__RegG8RC1_0__RegG8RC1_1,
733
  Convert__imm_95_8__RegG8RC1_0__S16Imm1_1,
734
  Convert__U5Imm1_0__RegG8RC1_1__S16Imm1_2,
735
  Convert__imm_95_20__RegG8RC1_0__RegG8RC1_1,
736
  Convert__imm_95_20__RegG8RC1_0__S16Imm1_1,
737
  Convert__imm_95_5__RegG8RC1_0__RegG8RC1_1,
738
  Convert__imm_95_5__RegG8RC1_0__S16Imm1_1,
739
  Convert__imm_95_1__RegG8RC1_0__RegG8RC1_1,
740
  Convert__imm_95_1__RegG8RC1_0__S16Imm1_1,
741
  Convert__imm_95_6__RegG8RC1_0__RegG8RC1_1,
742
  Convert__imm_95_6__RegG8RC1_0__S16Imm1_1,
743
  Convert__imm_95_2__RegG8RC1_0__RegG8RC1_1,
744
  Convert__imm_95_2__RegG8RC1_0__S16Imm1_1,
745
  Convert__imm_95_16__RegG8RC1_0__RegG8RC1_1,
746
  Convert__imm_95_16__RegG8RC1_0__S16Imm1_1,
747
  Convert__imm_95_24__RegG8RC1_0__RegG8RC1_1,
748
  Convert__imm_95_24__RegG8RC1_0__S16Imm1_1,
749
  Convert__imm_95_31__RegG8RC1_0__RegG8RC1_1,
750
  Convert__imm_95_31__RegG8RC1_0__S16Imm1_1,
751
  Convert__regR0__RegGPRC1_0,
752
  Convert__RegGPRC1_1__RegGPRC1_0,
753
  Convert__RegGPRC1_0__RegGPRC1_1__Imm1_2,
754
  Convert__RegGPRC1_0__RegGPRC1_1__imm_95_0,
755
  Convert__RegGPRC1_0__RegGPRC1_1__imm_95_1,
756
  Convert__U5Imm1_0__RegGPRC1_1__RegGPRC1_2,
757
  Convert__imm_95_4__RegGPRC1_0__RegGPRC1_1,
758
  Convert__imm_95_4__RegGPRC1_0__S16Imm1_1,
759
  Convert__imm_95_12__RegGPRC1_0__RegGPRC1_1,
760
  Convert__imm_95_12__RegGPRC1_0__S16Imm1_1,
761
  Convert__imm_95_8__RegGPRC1_0__RegGPRC1_1,
762
  Convert__imm_95_8__RegGPRC1_0__S16Imm1_1,
763
  Convert__U5Imm1_0__RegGPRC1_1__S16Imm1_2,
764
  Convert__imm_95_20__RegGPRC1_0__RegGPRC1_1,
765
  Convert__imm_95_20__RegGPRC1_0__S16Imm1_1,
766
  Convert__imm_95_5__RegGPRC1_0__RegGPRC1_1,
767
  Convert__imm_95_5__RegGPRC1_0__S16Imm1_1,
768
  Convert__imm_95_1__RegGPRC1_0__RegGPRC1_1,
769
  Convert__imm_95_1__RegGPRC1_0__S16Imm1_1,
770
  Convert__imm_95_6__RegGPRC1_0__RegGPRC1_1,
771
  Convert__imm_95_6__RegGPRC1_0__S16Imm1_1,
772
  Convert__imm_95_2__RegGPRC1_0__RegGPRC1_1,
773
  Convert__imm_95_2__RegGPRC1_0__S16Imm1_1,
774
  Convert__imm_95_16__RegGPRC1_0__RegGPRC1_1,
775
  Convert__imm_95_16__RegGPRC1_0__S16Imm1_1,
776
  Convert__imm_95_24__RegGPRC1_0__RegGPRC1_1,
777
  Convert__imm_95_24__RegGPRC1_0__S16Imm1_1,
778
  Convert__imm_95_31__RegGPRC1_0__RegGPRC1_1,
779
  Convert__imm_95_31__RegGPRC1_0__S16Imm1_1,
780
  Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2,
781
  Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2__RegVRRC1_3,
782
  Convert__RegVRRC1_0__U5Imm1_2__RegVRRC1_1,
783
  Convert__RegVRRC1_0__RegVRRC1_1,
784
  Convert__RegGPRC1_0__RegVRRC1_1,
785
  Convert__RegVRRC1_0__U4Imm1_2__RegVRRC1_1,
786
  Convert__RegG8RC1_0__RegG8RC1_1__RegVRRC1_2,
787
  Convert__RegVRRC1_0__Tie0_1_1__U4Imm1_2__RegVRRC1_1,
788
  Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_1,
789
  Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2__Tie0_1_1,
790
  Convert__RegVRRC1_0__RegVRRC1_1__U1Imm1_2__U4Imm1_3,
791
  Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2__U4Imm1_3,
792
  Convert__RegVRRC1_0__S5Imm1_1,
793
  Convert__regR0__regR0__imm_95_0,
794
  Convert__RegVSFRC1_0__RegVSFRC1_1,
795
  Convert__RegVSFRC1_0__RegVSFRC1_1__RegVSFRC1_2,
796
  Convert__RegVSSRC1_0__RegVSSRC1_1__RegVSSRC1_2,
797
  Convert__RegVSRC1_0__RegVSFRC1_1__RegVSFRC1_2,
798
  Convert__RegCRRC1_0__RegVSFRC1_1__RegVSFRC1_2,
799
  Convert__RegCRRC1_0__RegVRRC1_1__RegVRRC1_2,
800
  Convert__RegVRRC1_0__RegVFRC1_1,
801
  Convert__RegVSRC1_0__RegVSSRC1_1,
802
  Convert__RegVFRC1_0__RegVRRC1_1,
803
  Convert__RegVSSRC1_0__RegVSRC1_1,
804
  Convert__RegVSSRC1_0__RegVSFRC1_1,
805
  Convert__RegVSRC1_0__RegG8RC1_1__RegG8RC1_2,
806
  Convert__RegVRRC1_0__RegVRRC1_1__RegVSFRC1_2,
807
  Convert__RegVSFRC1_0__Tie0_1_1__RegVSFRC1_1__RegVSFRC1_2,
808
  Convert__RegVSSRC1_0__Tie0_1_1__RegVSSRC1_1__RegVSSRC1_2,
809
  Convert__RegVRRC1_0__Tie0_1_1__RegVRRC1_1__RegVRRC1_2,
810
  Convert__RegVSSRC1_0__RegVSSRC1_1,
811
  Convert__RegVRRC1_1__U1Imm1_0__RegVRRC1_2__U2Imm1_3,
812
  Convert__RegCRRC1_0__RegVSFRC1_1,
813
  Convert__RegCRRC1_0__U7Imm1_2__RegVSFRC1_1,
814
  Convert__RegCRRC1_0__U7Imm1_2__RegVRRC1_1,
815
  Convert__RegVSRC1_0__RegVSRC1_1,
816
  Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2,
817
  Convert__RegVSRC1_1__RegVSRC1_2__RegVSRC1_3,
818
  Convert__RegVSRC1_0__Tie0_1_1__RegVSRC1_1__RegVSRC1_2,
819
  Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_1,
820
  Convert__RegCRRC1_0__RegVSRC1_1__RegVSRC1_2,
821
  Convert__RegCRRC1_0__RegVSRC1_1,
822
  Convert__RegVSRC1_0__U7Imm1_2__RegVSRC1_1,
823
  Convert__RegVSFRC1_0__RegVSRC1_1__U4Imm1_2,
824
  Convert__RegVSRC1_0__Tie0_1_1__RegVSRC1_1__U4Imm1_2,
825
  Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2__imm_95_0,
826
  Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2__imm_95_3,
827
  Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2__U2Imm1_3,
828
  Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2__RegVSRC1_3,
829
  Convert__RegVSRC1_0__RegVSFRC1_1__imm_95_0,
830
  Convert__RegVSRC1_0__RegVSFRC1_1__imm_95_3,
831
  Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_1__imm_95_0,
832
  Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_1__imm_95_3,
833
  Convert__RegVSRC1_0__U8Imm1_1,
834
  Convert__RegVSRC1_0__RegVSRC1_1__U2Imm1_2,
835
  Convert__RegVSRC1_0__RegVSFRC1_1__imm_95_2,
836
  Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_1__imm_95_2,
837
  CVT_NUM_SIGNATURES
838
};
839
840
} // end anonymous namespace
841
842
static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][13] = {
843
  // Convert__RegG8RC1_0__RegG8RC1_1__TLSReg1_2
844
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addTLSRegOperands, 3, CVT_Done },
845
  // Convert__RegGPRC1_0__RegGPRC1_1__RegGPRC1_2
846
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_Done },
847
  // Convert__RegGPRC1_1__RegGPRC1_2__RegGPRC1_3
848
  { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addRegGPRCOperands, 4, CVT_Done },
849
  // Convert__RegGPRC1_0__RegGPRCNoR01_1__S16Imm1_2
850
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCNoR0Operands, 2, CVT_95_addS16ImmOperands, 3, CVT_Done },
851
  // Convert__RegGPRC1_0__RegGPRC1_1__S16Imm1_2
852
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addS16ImmOperands, 3, CVT_Done },
853
  // Convert__RegGPRC1_1__RegGPRC1_2__S16Imm1_3
854
  { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addS16ImmOperands, 4, CVT_Done },
855
  // Convert__RegGPRC1_0__RegGPRCNoR01_1__S17Imm1_2
856
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCNoR0Operands, 2, CVT_95_addS16ImmOperands, 3, CVT_Done },
857
  // Convert__RegGPRC1_0__RegGPRC1_1
858
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done },
859
  // Convert__RegGPRC1_1__RegGPRC1_2
860
  { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_Done },
861
  // Convert__RegG8RC1_0__Imm1_1
862
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
863
  // Convert__RegGPRC1_1__RegGPRC1_2__U16Imm1_3
864
  { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addU16ImmOperands, 4, CVT_Done },
865
  // Convert_NoOperands
866
  { CVT_Done },
867
  // Convert__DirectBr1_0
868
  { CVT_95_addBranchTargetOperands, 1, CVT_Done },
869
  // Convert__U5Imm1_0__RegCRBITRC1_1__CondBr1_2
870
  { CVT_95_addImmOperands, 1, CVT_95_addRegCRBITRCOperands, 2, CVT_95_addBranchTargetOperands, 3, CVT_Done },
871
  // Convert__U5Imm1_1__ATBitsAsHint1_0__RegCRBITRC1_2__CondBr1_3
872
  { CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 1, CVT_95_addRegCRBITRCOperands, 3, CVT_95_addBranchTargetOperands, 4, CVT_Done },
873
  // Convert__U5Imm1_0__imm_95_3__RegCRBITRC1_1__CondBr1_2
874
  { CVT_95_addImmOperands, 1, CVT_imm_95_3, 0, CVT_95_addRegCRBITRCOperands, 2, CVT_95_addBranchTargetOperands, 3, CVT_Done },
875
  // Convert__U5Imm1_0__imm_95_2__RegCRBITRC1_1__CondBr1_2
876
  { CVT_95_addImmOperands, 1, CVT_imm_95_2, 0, CVT_95_addRegCRBITRCOperands, 2, CVT_95_addBranchTargetOperands, 3, CVT_Done },
877
  // Convert__U5Imm1_0__RegCRBITRC1_1__imm_95_0
878
  { CVT_95_addImmOperands, 1, CVT_95_addRegCRBITRCOperands, 2, CVT_imm_95_0, 0, CVT_Done },
879
  // Convert__U5Imm1_0__RegCRBITRC1_1__Imm1_2
880
  { CVT_95_addImmOperands, 1, CVT_95_addRegCRBITRCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
881
  // Convert__RegVRRC1_1__RegVRRC1_2__U1Imm1_3
882
  { CVT_95_addRegVRRCOperands, 2, CVT_95_addRegVRRCOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
883
  // Convert__RegVRRC1_1__RegVRRC1_2__RegVRRC1_3
884
  { CVT_95_addRegVRRCOperands, 2, CVT_95_addRegVRRCOperands, 3, CVT_95_addRegVRRCOperands, 4, CVT_Done },
885
  // Convert__RegVRRC1_1__RegVRRC1_2
886
  { CVT_95_addRegVRRCOperands, 2, CVT_95_addRegVRRCOperands, 3, CVT_Done },
887
  // Convert__RegVRRC1_1__RegVRRC1_2__RegVRRC1_3__U1Imm1_4
888
  { CVT_95_addRegVRRCOperands, 2, CVT_95_addRegVRRCOperands, 3, CVT_95_addRegVRRCOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
889
  // Convert__CondBr1_0
890
  { CVT_95_addBranchTargetOperands, 1, CVT_Done },
891
  // Convert__imm_95_0__RegCRBITRC1_0__CondBr1_1
892
  { CVT_imm_95_0, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
893
  // Convert__imm_95_0__RegCRBITRC1_0__imm_95_0
894
  { CVT_imm_95_0, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_imm_95_0, 0, CVT_Done },
895
  // Convert__imm_95_8__RegCRBITRC1_0__CondBr1_1
896
  { CVT_imm_95_8, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
897
  // Convert__imm_95_8__RegCRBITRC1_0__imm_95_0
898
  { CVT_imm_95_8, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_imm_95_0, 0, CVT_Done },
899
  // Convert__imm_95_2__RegCRBITRC1_0__CondBr1_1
900
  { CVT_imm_95_2, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
901
  // Convert__imm_95_2__RegCRBITRC1_0__imm_95_0
902
  { CVT_imm_95_2, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_imm_95_0, 0, CVT_Done },
903
  // Convert__imm_95_10__RegCRBITRC1_0__CondBr1_1
904
  { CVT_imm_95_10, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
905
  // Convert__imm_95_10__RegCRBITRC1_0__imm_95_0
906
  { CVT_imm_95_10, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_imm_95_0, 0, CVT_Done },
907
  // Convert__imm_95_76__regCR0__CondBr1_0
908
  { CVT_imm_95_76, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
909
  // Convert__imm_95_76__RegCRRC1_0__CondBr1_1
910
  { CVT_imm_95_76, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
911
  // Convert__imm_95_79__regCR0__CondBr1_0
912
  { CVT_imm_95_79, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
913
  // Convert__imm_95_79__RegCRRC1_0__CondBr1_1
914
  { CVT_imm_95_79, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
915
  // Convert__imm_95_78__regCR0__CondBr1_0
916
  { CVT_imm_95_78, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
917
  // Convert__imm_95_78__RegCRRC1_0__CondBr1_1
918
  { CVT_imm_95_78, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
919
  // Convert__imm_95_76__regCR0
920
  { CVT_imm_95_76, 0, CVT_regCR0, 0, CVT_Done },
921
  // Convert__imm_95_76__RegCRRC1_0
922
  { CVT_imm_95_76, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done },
923
  // Convert__imm_95_79__regCR0
924
  { CVT_imm_95_79, 0, CVT_regCR0, 0, CVT_Done },
925
  // Convert__imm_95_79__RegCRRC1_0
926
  { CVT_imm_95_79, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done },
927
  // Convert__imm_95_78__regCR0
928
  { CVT_imm_95_78, 0, CVT_regCR0, 0, CVT_Done },
929
  // Convert__imm_95_78__RegCRRC1_0
930
  { CVT_imm_95_78, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done },
931
  // Convert__imm_95_4__RegCRBITRC1_0__CondBr1_1
932
  { CVT_imm_95_4, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
933
  // Convert__imm_95_7__RegCRBITRC1_0__CondBr1_1
934
  { CVT_imm_95_7, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
935
  // Convert__imm_95_6__RegCRBITRC1_0__CondBr1_1
936
  { CVT_imm_95_6, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
937
  // Convert__imm_95_4__RegCRBITRC1_0__imm_95_0
938
  { CVT_imm_95_4, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_imm_95_0, 0, CVT_Done },
939
  // Convert__imm_95_7__RegCRBITRC1_0__imm_95_0
940
  { CVT_imm_95_7, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_imm_95_0, 0, CVT_Done },
941
  // Convert__imm_95_6__RegCRBITRC1_0__imm_95_0
942
  { CVT_imm_95_6, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_imm_95_0, 0, CVT_Done },
943
  // Convert__imm_95_4__regCR0__CondBr1_0
944
  { CVT_imm_95_4, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
945
  // Convert__imm_95_4__RegCRRC1_0__CondBr1_1
946
  { CVT_imm_95_4, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
947
  // Convert__imm_95_7__regCR0__CondBr1_0
948
  { CVT_imm_95_7, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
949
  // Convert__imm_95_7__RegCRRC1_0__CondBr1_1
950
  { CVT_imm_95_7, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
951
  // Convert__imm_95_6__regCR0__CondBr1_0
952
  { CVT_imm_95_6, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
953
  // Convert__imm_95_6__RegCRRC1_0__CondBr1_1
954
  { CVT_imm_95_6, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
955
  // Convert__imm_95_4__regCR0
956
  { CVT_imm_95_4, 0, CVT_regCR0, 0, CVT_Done },
957
  // Convert__imm_95_4__RegCRRC1_0
958
  { CVT_imm_95_4, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done },
959
  // Convert__imm_95_7__regCR0
960
  { CVT_imm_95_7, 0, CVT_regCR0, 0, CVT_Done },
961
  // Convert__imm_95_7__RegCRRC1_0
962
  { CVT_imm_95_7, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done },
963
  // Convert__imm_95_6__regCR0
964
  { CVT_imm_95_6, 0, CVT_regCR0, 0, CVT_Done },
965
  // Convert__imm_95_6__RegCRRC1_0
966
  { CVT_imm_95_6, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done },
967
  // Convert__imm_95_44__regCR0__CondBr1_0
968
  { CVT_imm_95_44, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
969
  // Convert__imm_95_44__RegCRRC1_0__CondBr1_1
970
  { CVT_imm_95_44, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
971
  // Convert__imm_95_47__regCR0__CondBr1_0
972
  { CVT_imm_95_47, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
973
  // Convert__imm_95_47__RegCRRC1_0__CondBr1_1
974
  { CVT_imm_95_47, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
975
  // Convert__imm_95_46__regCR0__CondBr1_0
976
  { CVT_imm_95_46, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
977
  // Convert__imm_95_46__RegCRRC1_0__CondBr1_1
978
  { CVT_imm_95_46, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
979
  // Convert__imm_95_44__regCR0
980
  { CVT_imm_95_44, 0, CVT_regCR0, 0, CVT_Done },
981
  // Convert__imm_95_44__RegCRRC1_0
982
  { CVT_imm_95_44, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done },
983
  // Convert__imm_95_47__regCR0
984
  { CVT_imm_95_47, 0, CVT_regCR0, 0, CVT_Done },
985
  // Convert__imm_95_47__RegCRRC1_0
986
  { CVT_imm_95_47, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done },
987
  // Convert__imm_95_46__regCR0
988
  { CVT_imm_95_46, 0, CVT_regCR0, 0, CVT_Done },
989
  // Convert__imm_95_46__RegCRRC1_0
990
  { CVT_imm_95_46, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done },
991
  // Convert__DirectBr1_0__Imm1_1
992
  { CVT_95_addBranchTargetOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
993
  // Convert__imm_95_36__regCR0__CondBr1_0
994
  { CVT_imm_95_36, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
995
  // Convert__imm_95_36__RegCRRC1_0__CondBr1_1
996
  { CVT_imm_95_36, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
997
  // Convert__imm_95_39__regCR0__CondBr1_0
998
  { CVT_imm_95_39, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
999
  // Convert__imm_95_39__RegCRRC1_0__CondBr1_1
1000
  { CVT_imm_95_39, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
1001
  // Convert__imm_95_38__regCR0__CondBr1_0
1002
  { CVT_imm_95_38, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1003
  // Convert__imm_95_38__RegCRRC1_0__CondBr1_1
1004
  { CVT_imm_95_38, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
1005
  // Convert__imm_95_36__regCR0
1006
  { CVT_imm_95_36, 0, CVT_regCR0, 0, CVT_Done },
1007
  // Convert__imm_95_36__RegCRRC1_0
1008
  { CVT_imm_95_36, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done },
1009
  // Convert__imm_95_39__regCR0
1010
  { CVT_imm_95_39, 0, CVT_regCR0, 0, CVT_Done },
1011
  // Convert__imm_95_39__RegCRRC1_0
1012
  { CVT_imm_95_39, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done },
1013
  // Convert__imm_95_38__regCR0
1014
  { CVT_imm_95_38, 0, CVT_regCR0, 0, CVT_Done },
1015
  // Convert__imm_95_38__RegCRRC1_0
1016
  { CVT_imm_95_38, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done },
1017
  // Convert__imm_95_12__regCR0__CondBr1_0
1018
  { CVT_imm_95_12, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1019
  // Convert__imm_95_12__RegCRRC1_0__CondBr1_1
1020
  { CVT_imm_95_12, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
1021
  // Convert__imm_95_15__regCR0__CondBr1_0
1022
  { CVT_imm_95_15, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1023
  // Convert__imm_95_15__RegCRRC1_0__CondBr1_1
1024
  { CVT_imm_95_15, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
1025
  // Convert__imm_95_14__regCR0__CondBr1_0
1026
  { CVT_imm_95_14, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1027
  // Convert__imm_95_14__RegCRRC1_0__CondBr1_1
1028
  { CVT_imm_95_14, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
1029
  // Convert__imm_95_12__regCR0
1030
  { CVT_imm_95_12, 0, CVT_regCR0, 0, CVT_Done },
1031
  // Convert__imm_95_12__RegCRRC1_0
1032
  { CVT_imm_95_12, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done },
1033
  // Convert__imm_95_15__regCR0
1034
  { CVT_imm_95_15, 0, CVT_regCR0, 0, CVT_Done },
1035
  // Convert__imm_95_15__RegCRRC1_0
1036
  { CVT_imm_95_15, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done },
1037
  // Convert__imm_95_14__regCR0
1038
  { CVT_imm_95_14, 0, CVT_regCR0, 0, CVT_Done },
1039
  // Convert__imm_95_14__RegCRRC1_0
1040
  { CVT_imm_95_14, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done },
1041
  // Convert__imm_95_68__regCR0__CondBr1_0
1042
  { CVT_imm_95_68, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1043
  // Convert__imm_95_68__RegCRRC1_0__CondBr1_1
1044
  { CVT_imm_95_68, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
1045
  // Convert__imm_95_71__regCR0__CondBr1_0
1046
  { CVT_imm_95_71, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1047
  // Convert__imm_95_71__RegCRRC1_0__CondBr1_1
1048
  { CVT_imm_95_71, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
1049
  // Convert__imm_95_70__regCR0__CondBr1_0
1050
  { CVT_imm_95_70, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1051
  // Convert__imm_95_70__RegCRRC1_0__CondBr1_1
1052
  { CVT_imm_95_70, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
1053
  // Convert__imm_95_68__regCR0
1054
  { CVT_imm_95_68, 0, CVT_regCR0, 0, CVT_Done },
1055
  // Convert__imm_95_68__RegCRRC1_0
1056
  { CVT_imm_95_68, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done },
1057
  // Convert__imm_95_71__regCR0
1058
  { CVT_imm_95_71, 0, CVT_regCR0, 0, CVT_Done },
1059
  // Convert__imm_95_71__RegCRRC1_0
1060
  { CVT_imm_95_71, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done },
1061
  // Convert__imm_95_70__regCR0
1062
  { CVT_imm_95_70, 0, CVT_regCR0, 0, CVT_Done },
1063
  // Convert__imm_95_70__RegCRRC1_0
1064
  { CVT_imm_95_70, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done },
1065
  // Convert__imm_95_100__regCR0__CondBr1_0
1066
  { CVT_imm_95_100, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1067
  // Convert__imm_95_100__RegCRRC1_0__CondBr1_1
1068
  { CVT_imm_95_100, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
1069
  // Convert__imm_95_103__regCR0__CondBr1_0
1070
  { CVT_imm_95_103, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1071
  // Convert__imm_95_103__RegCRRC1_0__CondBr1_1
1072
  { CVT_imm_95_103, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
1073
  // Convert__imm_95_102__regCR0__CondBr1_0
1074
  { CVT_imm_95_102, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1075
  // Convert__imm_95_102__RegCRRC1_0__CondBr1_1
1076
  { CVT_imm_95_102, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
1077
  // Convert__imm_95_100__regCR0
1078
  { CVT_imm_95_100, 0, CVT_regCR0, 0, CVT_Done },
1079
  // Convert__imm_95_100__RegCRRC1_0
1080
  { CVT_imm_95_100, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done },
1081
  // Convert__imm_95_103__regCR0
1082
  { CVT_imm_95_103, 0, CVT_regCR0, 0, CVT_Done },
1083
  // Convert__imm_95_103__RegCRRC1_0
1084
  { CVT_imm_95_103, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done },
1085
  // Convert__imm_95_102__regCR0
1086
  { CVT_imm_95_102, 0, CVT_regCR0, 0, CVT_Done },
1087
  // Convert__imm_95_102__RegCRRC1_0
1088
  { CVT_imm_95_102, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done },
1089
  // Convert__RegG8RC1_0__RegG8RC1_1__RegG8RC1_2
1090
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_Done },
1091
  // Convert__imm_95_108__regCR0__CondBr1_0
1092
  { CVT_imm_95_108, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1093
  // Convert__imm_95_108__RegCRRC1_0__CondBr1_1
1094
  { CVT_imm_95_108, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
1095
  // Convert__imm_95_111__regCR0__CondBr1_0
1096
  { CVT_imm_95_111, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1097
  // Convert__imm_95_111__RegCRRC1_0__CondBr1_1
1098
  { CVT_imm_95_111, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
1099
  // Convert__imm_95_110__regCR0__CondBr1_0
1100
  { CVT_imm_95_110, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done },
1101
  // Convert__imm_95_110__RegCRRC1_0__CondBr1_1
1102
  { CVT_imm_95_110, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
1103
  // Convert__imm_95_108__regCR0
1104
  { CVT_imm_95_108, 0, CVT_regCR0, 0, CVT_Done },
1105
  // Convert__imm_95_108__RegCRRC1_0
1106
  { CVT_imm_95_108, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done },
1107
  // Convert__imm_95_111__regCR0
1108
  { CVT_imm_95_111, 0, CVT_regCR0, 0, CVT_Done },
1109
  // Convert__imm_95_111__RegCRRC1_0
1110
  { CVT_imm_95_111, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done },
1111
  // Convert__imm_95_110__regCR0
1112
  { CVT_imm_95_110, 0, CVT_regCR0, 0, CVT_Done },
1113
  // Convert__imm_95_110__RegCRRC1_0
1114
  { CVT_imm_95_110, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done },
1115
  // Convert__imm_95_12__RegCRBITRC1_0__CondBr1_1
1116
  { CVT_imm_95_12, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
1117
  // Convert__imm_95_15__RegCRBITRC1_0__CondBr1_1
1118
  { CVT_imm_95_15, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
1119
  // Convert__imm_95_14__RegCRBITRC1_0__CondBr1_1
1120
  { CVT_imm_95_14, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done },
1121
  // Convert__imm_95_12__RegCRBITRC1_0__imm_95_0
1122
  { CVT_imm_95_12, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1123
  // Convert__imm_95_15__RegCRBITRC1_0__imm_95_0
1124
  { CVT_imm_95_15, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1125
  // Convert__imm_95_14__RegCRBITRC1_0__imm_95_0
1126
  { CVT_imm_95_14, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1127
  // Convert__RegG8RC1_0__RegG8RC1_1__imm_95_0__U6Imm1_2
1128
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_imm_95_0, 0, CVT_95_addImmOperands, 3, CVT_Done },
1129
  // Convert__RegG8RC1_0__RegGPRC1_1__imm_95_0__U6Imm1_2
1130
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_imm_95_0, 0, CVT_95_addImmOperands, 3, CVT_Done },
1131
  // Convert__RegG8RC1_1__RegG8RC1_2__imm_95_0__U6Imm1_3
1132
  { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_imm_95_0, 0, CVT_95_addImmOperands, 4, CVT_Done },
1133
  // Convert__RegG8RC1_0__RegG8RC1_1__U6Imm1_2__U6Imm1_3
1134
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
1135
  // Convert__RegG8RC1_1__RegG8RC1_2__U6Imm1_3__U6Imm1_4
1136
  { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
1137
  // Convert__RegGPRC1_0__RegGPRC1_1__U5Imm1_2__U5Imm1_3
1138
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
1139
  // Convert__RegGPRC1_1__RegGPRC1_2__U5Imm1_3__U5Imm1_4
1140
  { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
1141
  // Convert__RegGPRC1_0__RegGPRC1_1__imm_95_0__U5Imm1_2__imm_95_31
1142
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_imm_95_0, 0, CVT_95_addImmOperands, 3, CVT_imm_95_31, 0, CVT_Done },
1143
  // Convert__RegGPRC1_1__RegGPRC1_2__imm_95_0__U5Imm1_3__imm_95_31
1144
  { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_imm_95_0, 0, CVT_95_addImmOperands, 4, CVT_imm_95_31, 0, CVT_Done },
1145
  // Convert__RegG8RC1_0__RegG8RC1_1__U6Imm1_2
1146
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1147
  // Convert__RegG8RC1_1__RegG8RC1_2__U6Imm1_3
1148
  { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
1149
  // Convert__RegGPRC1_0__RegGPRC1_1__U5Imm1_2
1150
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1151
  // Convert__RegGPRC1_1__RegGPRC1_2__U5Imm1_3
1152
  { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
1153
  // Convert__RegCRRC1_0__RegGPRC1_2__RegGPRC1_3
1154
  { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegGPRCOperands, 3, CVT_95_addRegGPRCOperands, 4, CVT_Done },
1155
  // Convert__RegCRRC1_0__RegG8RC1_2__RegG8RC1_3
1156
  { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegG8RCOperands, 3, CVT_95_addRegG8RCOperands, 4, CVT_Done },
1157
  // Convert__regCR0__RegG8RC1_0__RegG8RC1_1
1158
  { CVT_regCR0, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done },
1159
  // Convert__RegCRRC1_0__RegG8RC1_1__RegG8RC1_2
1160
  { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_Done },
1161
  // Convert__regCR0__RegG8RC1_0__S16Imm1_1
1162
  { CVT_regCR0, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1163
  // Convert__RegCRRC1_0__RegG8RC1_1__S16Imm1_2
1164
  { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addS16ImmOperands, 3, CVT_Done },
1165
  // Convert__RegCRBITRC1_0__RegG8RC1_1__RegG8RC1_2
1166
  { CVT_95_addRegCRBITRCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_Done },
1167
  // Convert__RegCRRC1_0__RegGPRC1_2__S16Imm1_3
1168
  { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegGPRCOperands, 3, CVT_95_addS16ImmOperands, 4, CVT_Done },
1169
  // Convert__RegCRRC1_0__RegG8RC1_2__S16Imm1_3
1170
  { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegG8RCOperands, 3, CVT_95_addS16ImmOperands, 4, CVT_Done },
1171
  // Convert__regCR0__RegG8RC1_0__U16Imm1_1
1172
  { CVT_regCR0, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addU16ImmOperands, 2, CVT_Done },
1173
  // Convert__RegCRRC1_0__RegG8RC1_1__U16Imm1_2
1174
  { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addU16ImmOperands, 3, CVT_Done },
1175
  // Convert__RegCRRC1_0__RegGPRC1_2__U16Imm1_3
1176
  { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegGPRCOperands, 3, CVT_95_addU16ImmOperands, 4, CVT_Done },
1177
  // Convert__RegCRRC1_0__RegG8RC1_2__U16Imm1_3
1178
  { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegG8RCOperands, 3, CVT_95_addU16ImmOperands, 4, CVT_Done },
1179
  // Convert__regCR0__RegGPRC1_0__RegGPRC1_1
1180
  { CVT_regCR0, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1181
  // Convert__RegCRRC1_0__RegGPRC1_1__RegGPRC1_2
1182
  { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_Done },
1183
  // Convert__regCR0__RegGPRC1_0__U16Imm1_1
1184
  { CVT_regCR0, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addU16ImmOperands, 2, CVT_Done },
1185
  // Convert__RegCRRC1_0__RegGPRC1_1__U16Imm1_2
1186
  { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addU16ImmOperands, 3, CVT_Done },
1187
  // Convert__RegCRBITRC1_0__U1Imm1_1__RegG8RC1_2__RegG8RC1_3
1188
  { CVT_95_addRegCRBITRCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_95_addRegG8RCOperands, 4, CVT_Done },
1189
  // Convert__regCR0__RegGPRC1_0__S16Imm1_1
1190
  { CVT_regCR0, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1191
  // Convert__RegCRRC1_0__RegGPRC1_1__S16Imm1_2
1192
  { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addS16ImmOperands, 3, CVT_Done },
1193
  // Convert__RegG8RC1_0__RegG8RC1_1
1194
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done },
1195
  // Convert__RegG8RC1_1__RegG8RC1_2
1196
  { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_Done },
1197
  // Convert__RegGPRC1_0__RegGPRC1_1__U1Imm1_2
1198
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1199
  // Convert__RegCRBITRC1_0__RegCRBITRC1_1__RegCRBITRC1_2
1200
  { CVT_95_addRegCRBITRCOperands, 1, CVT_95_addRegCRBITRCOperands, 2, CVT_95_addRegCRBITRCOperands, 3, CVT_Done },
1201
  // Convert__RegCRBITRC1_0__RegCRBITRC1_0__RegCRBITRC1_0
1202
  { CVT_95_addRegCRBITRCOperands, 1, CVT_95_addRegCRBITRCOperands, 1, CVT_95_addRegCRBITRCOperands, 1, CVT_Done },
1203
  // Convert__RegCRBITRC1_0__RegCRBITRC1_1__RegCRBITRC1_1
1204
  { CVT_95_addRegCRBITRCOperands, 1, CVT_95_addRegCRBITRCOperands, 2, CVT_95_addRegCRBITRCOperands, 2, CVT_Done },
1205
  // Convert__RegGxRCNoR01_0__RegGxRC1_1
1206
  { CVT_95_addRegGxRCNoR0Operands, 1, CVT_95_addRegGxRCOperands, 2, CVT_Done },
1207
  // Convert__U5Imm1_2__RegGxRCNoR01_0__RegGxRC1_1
1208
  { CVT_95_addImmOperands, 3, CVT_95_addRegGxRCNoR0Operands, 1, CVT_95_addRegGxRCOperands, 2, CVT_Done },
1209
  // Convert__RegGxRCNoR01_0__RegGxRC1_1__U5Imm1_2
1210
  { CVT_95_addRegGxRCNoR0Operands, 1, CVT_95_addRegGxRCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1211
  // Convert__RegGxRCNoR01_1__RegGxRC1_2__U5Imm1_0
1212
  { CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
1213
  // Convert__regR0__regR0
1214
  { CVT_regR0, 0, CVT_regR0, 0, CVT_Done },
1215
  // Convert__RegG8RC1_1__RegG8RC1_2__RegG8RC1_3
1216
  { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_95_addRegG8RCOperands, 4, CVT_Done },
1217
  // Convert__U5Imm1_0
1218
  { CVT_95_addImmOperands, 1, CVT_Done },
1219
  // Convert__U5Imm1_2__RegGPRC1_0__RegGPRC1_1
1220
  { CVT_95_addImmOperands, 3, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1221
  // Convert__RegSPERC1_0__RegSPERC1_1
1222
  { CVT_95_addRegSPERCOperands, 1, CVT_95_addRegSPERCOperands, 2, CVT_Done },
1223
  // Convert__RegSPERC1_0__RegSPERC1_1__RegSPERC1_2
1224
  { CVT_95_addRegSPERCOperands, 1, CVT_95_addRegSPERCOperands, 2, CVT_95_addRegSPERCOperands, 3, CVT_Done },
1225
  // Convert__RegSPERC1_0__RegSPE4RC1_1
1226
  { CVT_95_addRegSPERCOperands, 1, CVT_95_addRegSPE4RCOperands, 2, CVT_Done },
1227
  // Convert__RegSPERC1_0__RegGPRC1_1
1228
  { CVT_95_addRegSPERCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1229
  // Convert__RegCRRC1_0__RegSPERC1_1__RegSPERC1_2
1230
  { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegSPERCOperands, 2, CVT_95_addRegSPERCOperands, 3, CVT_Done },
1231
  // Convert__RegGPRC1_0__RegSPERC1_1
1232
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegSPERCOperands, 2, CVT_Done },
1233
  // Convert__RegSPE4RC1_0__RegSPE4RC1_1
1234
  { CVT_95_addRegSPE4RCOperands, 1, CVT_95_addRegSPE4RCOperands, 2, CVT_Done },
1235
  // Convert__RegSPE4RC1_0__RegSPE4RC1_1__RegSPE4RC1_2
1236
  { CVT_95_addRegSPE4RCOperands, 1, CVT_95_addRegSPE4RCOperands, 2, CVT_95_addRegSPE4RCOperands, 3, CVT_Done },
1237
  // Convert__RegSPE4RC1_0__RegSPERC1_1
1238
  { CVT_95_addRegSPE4RCOperands, 1, CVT_95_addRegSPERCOperands, 2, CVT_Done },
1239
  // Convert__RegSPE4RC1_0__RegGPRC1_1
1240
  { CVT_95_addRegSPE4RCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1241
  // Convert__RegCRRC1_0__RegSPE4RC1_1__RegSPE4RC1_2
1242
  { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegSPE4RCOperands, 2, CVT_95_addRegSPE4RCOperands, 3, CVT_Done },
1243
  // Convert__RegGPRC1_0__RegSPE4RC1_1
1244
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegSPE4RCOperands, 2, CVT_Done },
1245
  // Convert__RegSPERC1_0__RegSPERC1_2__U5Imm1_1
1246
  { CVT_95_addRegSPERCOperands, 1, CVT_95_addRegSPERCOperands, 3, CVT_95_addImmOperands, 2, CVT_Done },
1247
  // Convert__RegSPERC1_0__DispSPE81_1__RegGxRCNoR01_2
1248
  { CVT_95_addRegSPERCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done },
1249
  // Convert__RegSPERC1_0__RegGxRCNoR01_1__RegGxRC1_2
1250
  { CVT_95_addRegSPERCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done },
1251
  // Convert__RegSPERC1_0__DispSPE21_1__RegGxRCNoR01_2
1252
  { CVT_95_addRegSPERCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done },
1253
  // Convert__RegSPERC1_0__DispSPE41_1__RegGxRCNoR01_2
1254
  { CVT_95_addRegSPERCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done },
1255
  // Convert__RegSPERC1_0__RegSPERC1_1__U5Imm1_2
1256
  { CVT_95_addRegSPERCOperands, 1, CVT_95_addRegSPERCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1257
  // Convert__RegSPERC1_1__RegSPERC1_2__RegSPERC1_3__imm_95_0
1258
  { CVT_95_addRegSPERCOperands, 2, CVT_95_addRegSPERCOperands, 3, CVT_95_addRegSPERCOperands, 4, CVT_imm_95_0, 0, CVT_Done },
1259
  // Convert__RegSPERC1_0__S5Imm1_1
1260
  { CVT_95_addRegSPERCOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1261
  // Convert__RegSPERC1_0__U5Imm1_1__RegSPERC1_2
1262
  { CVT_95_addRegSPERCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegSPERCOperands, 3, CVT_Done },
1263
  // Convert__RegG8RC1_0__RegGPRC1_1__U6Imm1_2
1264
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1265
  // Convert__RegG8RC1_1__RegGPRC1_2__U6Imm1_3
1266
  { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
1267
  // Convert__RegF4RC1_0__RegF4RC1_1
1268
  { CVT_95_addRegF4RCOperands, 1, CVT_95_addRegF4RCOperands, 2, CVT_Done },
1269
  // Convert__RegF4RC1_1__RegF4RC1_2
1270
  { CVT_95_addRegF4RCOperands, 2, CVT_95_addRegF4RCOperands, 3, CVT_Done },
1271
  // Convert__RegF8RC1_0__RegF8RC1_1__RegF8RC1_2
1272
  { CVT_95_addRegF8RCOperands, 1, CVT_95_addRegF8RCOperands, 2, CVT_95_addRegF8RCOperands, 3, CVT_Done },
1273
  // Convert__RegF8RC1_1__RegF8RC1_2__RegF8RC1_3
1274
  { CVT_95_addRegF8RCOperands, 2, CVT_95_addRegF8RCOperands, 3, CVT_95_addRegF8RCOperands, 4, CVT_Done },
1275
  // Convert__RegF4RC1_0__RegF4RC1_1__RegF4RC1_2
1276
  { CVT_95_addRegF4RCOperands, 1, CVT_95_addRegF4RCOperands, 2, CVT_95_addRegF4RCOperands, 3, CVT_Done },
1277
  // Convert__RegF4RC1_1__RegF4RC1_2__RegF4RC1_3
1278
  { CVT_95_addRegF4RCOperands, 2, CVT_95_addRegF4RCOperands, 3, CVT_95_addRegF4RCOperands, 4, CVT_Done },
1279
  // Convert__RegF8RC1_0__RegF8RC1_1
1280
  { CVT_95_addRegF8RCOperands, 1, CVT_95_addRegF8RCOperands, 2, CVT_Done },
1281
  // Convert__RegF8RC1_1__RegF8RC1_2
1282
  { CVT_95_addRegF8RCOperands, 2, CVT_95_addRegF8RCOperands, 3, CVT_Done },
1283
  // Convert__RegF4RC1_0__RegF8RC1_1
1284
  { CVT_95_addRegF4RCOperands, 1, CVT_95_addRegF8RCOperands, 2, CVT_Done },
1285
  // Convert__RegF4RC1_1__RegF8RC1_2
1286
  { CVT_95_addRegF4RCOperands, 2, CVT_95_addRegF8RCOperands, 3, CVT_Done },
1287
  // Convert__RegCRRC1_0__RegF4RC1_1__RegF4RC1_2
1288
  { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegF4RCOperands, 2, CVT_95_addRegF4RCOperands, 3, CVT_Done },
1289
  // Convert__RegF8RC1_0__RegF8RC1_1__RegF8RC1_2__RegF8RC1_3
1290
  { CVT_95_addRegF8RCOperands, 1, CVT_95_addRegF8RCOperands, 2, CVT_95_addRegF8RCOperands, 3, CVT_95_addRegF8RCOperands, 4, CVT_Done },
1291
  // Convert__RegF8RC1_1__RegF8RC1_2__RegF8RC1_3__RegF8RC1_4
1292
  { CVT_95_addRegF8RCOperands, 2, CVT_95_addRegF8RCOperands, 3, CVT_95_addRegF8RCOperands, 4, CVT_95_addRegF8RCOperands, 5, CVT_Done },
1293
  // Convert__RegF4RC1_0__RegF4RC1_1__RegF4RC1_2__RegF4RC1_3
1294
  { CVT_95_addRegF4RCOperands, 1, CVT_95_addRegF4RCOperands, 2, CVT_95_addRegF4RCOperands, 3, CVT_95_addRegF4RCOperands, 4, CVT_Done },
1295
  // Convert__RegF4RC1_1__RegF4RC1_2__RegF4RC1_3__RegF4RC1_4
1296
  { CVT_95_addRegF4RCOperands, 2, CVT_95_addRegF4RCOperands, 3, CVT_95_addRegF4RCOperands, 4, CVT_95_addRegF4RCOperands, 5, CVT_Done },
1297
  // Convert__RegF4RC1_0__RegF8RC1_1__RegF4RC1_2__RegF4RC1_3
1298
  { CVT_95_addRegF4RCOperands, 1, CVT_95_addRegF8RCOperands, 2, CVT_95_addRegF4RCOperands, 3, CVT_95_addRegF4RCOperands, 4, CVT_Done },
1299
  // Convert__RegF4RC1_1__RegF8RC1_2__RegF4RC1_3__RegF4RC1_4
1300
  { CVT_95_addRegF4RCOperands, 2, CVT_95_addRegF8RCOperands, 3, CVT_95_addRegF4RCOperands, 4, CVT_95_addRegF4RCOperands, 5, CVT_Done },
1301
  // Convert__RegCRRC1_0__RegF8RC1_1__RegF8RC1_2
1302
  { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegF8RCOperands, 2, CVT_95_addRegF8RCOperands, 3, CVT_Done },
1303
  // Convert__RegCRRC1_0__RegF8RC1_1
1304
  { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegF8RCOperands, 2, CVT_Done },
1305
  // Convert__U4Imm1_0__RegGxRCNoR01_1__RegGxRC1_2
1306
  { CVT_95_addImmOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done },
1307
  // Convert__U4Imm1_1__RegGxRCNoR01_2__RegGxRC1_3
1308
  { CVT_95_addImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_95_addRegGxRCOperands, 4, CVT_Done },
1309
  // Convert__RegGPRC1_0__RegGPRCNoR01_1__RegGPRC1_2__RegCRBITRC1_3
1310
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCNoR0Operands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addRegCRBITRCOperands, 4, CVT_Done },
1311
  // Convert__RegGPRC1_0__DispRI1_1__RegGxRCNoR01_2
1312
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done },
1313
  // Convert__RegGPRC1_0__RegGxRCNoR01_1__RegGxRC1_2
1314
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done },
1315
  // Convert__RegGPRC1_0__imm_95_0__DispRI1_1__RegGxRCNoR01_2
1316
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_0, 0, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done },
1317
  // Convert__RegGPRC1_0__imm_95_0__RegGxRCNoR01_1__RegGxRC1_2
1318
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_0, 0, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done },
1319
  // Convert__RegG8RC1_0__RegGxRCNoR01_1__TLSReg1_2
1320
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addTLSRegOperands, 3, CVT_Done },
1321
  // Convert__RegG8RC1_0__DispRIX1_1__RegGxRCNoR01_2
1322
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done },
1323
  // Convert__RegG8RC1_0__RegGxRCNoR01_1__RegGxRC1_2
1324
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done },
1325
  // Convert__RegG8RC1_0__RegG8RC1_1__U5Imm1_2
1326
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1327
  // Convert__RegG8RC1_0__imm_95_0__DispRIX1_1__RegGxRCNoR01_2
1328
  { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_0, 0, CVT_95_addImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done },
1329
  // Convert__RegG8RC1_0__imm_95_0__RegGxRCNoR01_1__RegGxRC1_2
1330
  { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_0, 0, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done },
1331
  // Convert__RegF8RC1_0__DispRI1_1__RegGxRCNoR01_2
1332
  { CVT_95_addRegF8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done },
1333
  // Convert__RegF8RC1_0__RegGxRCNoR01_1__RegGxRC1_2
1334
  { CVT_95_addRegF8RCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done },
1335
  // Convert__RegF8RC1_0__imm_95_0__DispRI1_1__RegGxRCNoR01_2
1336
  { CVT_95_addRegF8RCOperands, 1, CVT_imm_95_0, 0, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done },
1337
  // Convert__RegF8RC1_0__imm_95_0__RegGxRCNoR01_1__RegGxRC1_2
1338
  { CVT_95_addRegF8RCOperands, 1, CVT_imm_95_0, 0, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done },
1339
  // Convert__RegF4RC1_0__DispRI1_1__RegGxRCNoR01_2
1340
  { CVT_95_addRegF4RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done },
1341
  // Convert__RegF4RC1_0__imm_95_0__DispRI1_1__RegGxRCNoR01_2
1342
  { CVT_95_addRegF4RCOperands, 1, CVT_imm_95_0, 0, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done },
1343
  // Convert__RegF4RC1_0__imm_95_0__RegGxRCNoR01_1__RegGxRC1_2
1344
  { CVT_95_addRegF4RCOperands, 1, CVT_imm_95_0, 0, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done },
1345
  // Convert__RegF4RC1_0__RegGxRCNoR01_1__RegGxRC1_2
1346
  { CVT_95_addRegF4RCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done },
1347
  // Convert__RegGPRC1_0__S16Imm1_1
1348
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1349
  // Convert__RegGPRC1_0__S17Imm1_1
1350
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1351
  // Convert__RegG8RC1_0__imm_95_0
1352
  { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1353
  // Convert__RegVRRC1_0__RegGxRCNoR01_1__RegGxRC1_2
1354
  { CVT_95_addRegVRRCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done },
1355
  // Convert__imm_95_1
1356
  { CVT_imm_95_1, 0, CVT_Done },
1357
  // Convert__RegSPE4RC1_0__DispRI1_1__RegGxRCNoR01_2
1358
  { CVT_95_addRegSPE4RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done },
1359
  // Convert__RegSPE4RC1_0__RegGxRCNoR01_1__RegGxRC1_2
1360
  { CVT_95_addRegSPE4RCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done },
1361
  // Convert__RegVFRC1_0__DispRIX1_1__RegGxRCNoR01_2
1362
  { CVT_95_addRegVFRCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done },
1363
  // Convert__RegVSFRC1_0__RegGxRCNoR01_1__RegGxRC1_2
1364
  { CVT_95_addRegVSFRCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done },
1365
  // Convert__RegVSSRC1_0__RegGxRCNoR01_1__RegGxRC1_2
1366
  { CVT_95_addRegVSSRCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done },
1367
  // Convert__RegVSRC1_0__DispRIX161_1__RegGxRCNoR01_2
1368
  { CVT_95_addRegVSRCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done },
1369
  // Convert__RegVSRC1_0__RegGxRCNoR01_1__RegGxRC1_2
1370
  { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done },
1371
  // Convert__RegVSRC1_0__Imm1_1__RegG8RC1_2
1372
  { CVT_95_addRegVSRCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_Done },
1373
  // Convert__RegG8RC1_0__RegG8RC1_1__RegG8RC1_2__RegG8RC1_3
1374
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_95_addRegG8RCOperands, 4, CVT_Done },
1375
  // Convert__imm_95_0
1376
  { CVT_imm_95_0, 0, CVT_Done },
1377
  // Convert__RegCRRC1_0__RegCRRC1_1
1378
  { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegCRRCOperands, 2, CVT_Done },
1379
  // Convert__RegCRRC1_0
1380
  { CVT_95_addRegCRRCOperands, 1, CVT_Done },
1381
  // Convert__RegGPRC1_0__imm_95_29
1382
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_29, 0, CVT_Done },
1383
  // Convert__RegGPRC1_0__imm_95_280
1384
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_280, 0, CVT_Done },
1385
  // Convert__RegGPRC1_0__U10Imm1_1__imm_95_0
1386
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1387
  // Convert__RegGPRC1_0__imm_95_128
1388
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_128, 0, CVT_Done },
1389
  // Convert__RegGPRC1_0__imm_95_129
1390
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_129, 0, CVT_Done },
1391
  // Convert__RegGPRC1_0__imm_95_130
1392
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_130, 0, CVT_Done },
1393
  // Convert__RegGPRC1_0__imm_95_131
1394
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_131, 0, CVT_Done },
1395
  // Convert__RegGPRC1_0__imm_95_132
1396
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_132, 0, CVT_Done },
1397
  // Convert__RegGPRC1_0__imm_95_133
1398
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_133, 0, CVT_Done },
1399
  // Convert__RegGPRC1_0__imm_95_134
1400
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_134, 0, CVT_Done },
1401
  // Convert__RegGPRC1_0__imm_95_135
1402
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_135, 0, CVT_Done },
1403
  // Convert__RegGPRC1_0__imm_95_28
1404
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_28, 0, CVT_Done },
1405
  // Convert__RegGPRC1_0
1406
  { CVT_95_addRegGPRCOperands, 1, CVT_Done },
1407
  // Convert__RegGPRC1_0__imm_95_19
1408
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_19, 0, CVT_Done },
1409
  // Convert__RegGPRC1_0__imm_95_537
1410
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_537, 0, CVT_Done },
1411
  // Convert__RegGPRC1_0__imm_95_539
1412
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_539, 0, CVT_Done },
1413
  // Convert__RegGPRC1_0__imm_95_541
1414
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_541, 0, CVT_Done },
1415
  // Convert__RegGPRC1_0__imm_95_543
1416
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_543, 0, CVT_Done },
1417
  // Convert__RegGPRC1_0__imm_95_536
1418
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_536, 0, CVT_Done },
1419
  // Convert__RegGPRC1_0__imm_95_538
1420
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_538, 0, CVT_Done },
1421
  // Convert__RegGPRC1_0__imm_95_540
1422
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_540, 0, CVT_Done },
1423
  // Convert__RegGPRC1_0__imm_95_542
1424
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_542, 0, CVT_Done },
1425
  // Convert__RegGPRC1_0__imm_95_1018
1426
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_1018, 0, CVT_Done },
1427
  // Convert__RegGPRC1_0__Imm1_1
1428
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1429
  // Convert__RegGPRC1_0__imm_95_981
1430
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_981, 0, CVT_Done },
1431
  // Convert__RegGPRC1_0__imm_95_22
1432
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_22, 0, CVT_Done },
1433
  // Convert__RegGPRC1_0__imm_95_17
1434
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_17, 0, CVT_Done },
1435
  // Convert__RegGPRC1_0__imm_95_18
1436
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_18, 0, CVT_Done },
1437
  // Convert__RegGPRC1_0__imm_95_980
1438
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_980, 0, CVT_Done },
1439
  // Convert__RegG8RC1_0__RegF8RC1_1
1440
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegF8RCOperands, 2, CVT_Done },
1441
  // Convert__RegF8RC1_0
1442
  { CVT_95_addRegF8RCOperands, 1, CVT_Done },
1443
  // Convert__RegF8RC1_1
1444
  { CVT_95_addRegF8RCOperands, 2, CVT_Done },
1445
  // Convert__RegF8RC1_0__U3Imm1_1
1446
  { CVT_95_addRegF8RCOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1447
  // Convert__RegF8RC1_0__U2Imm1_1
1448
  { CVT_95_addRegF8RCOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1449
  // Convert__RegGPRC1_0__imm_95_529
1450
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_529, 0, CVT_Done },
1451
  // Convert__RegGPRC1_0__imm_95_531
1452
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_531, 0, CVT_Done },
1453
  // Convert__RegGPRC1_0__imm_95_533
1454
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_533, 0, CVT_Done },
1455
  // Convert__RegGPRC1_0__imm_95_535
1456
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_535, 0, CVT_Done },
1457
  // Convert__RegGPRC1_0__imm_95_528
1458
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_528, 0, CVT_Done },
1459
  // Convert__RegGPRC1_0__imm_95_530
1460
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_530, 0, CVT_Done },
1461
  // Convert__RegGPRC1_0__imm_95_532
1462
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_532, 0, CVT_Done },
1463
  // Convert__RegGPRC1_0__imm_95_534
1464
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_534, 0, CVT_Done },
1465
  // Convert__RegGPRC1_0__imm_95_1019
1466
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_1019, 0, CVT_Done },
1467
  // Convert__RegGPRC1_0__CRBitMask1_1
1468
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addCRBitMaskOperands, 2, CVT_Done },
1469
  // Convert__RegGPRC1_0__imm_95_48
1470
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_48, 0, CVT_Done },
1471
  // Convert__RegGPRC1_0__imm_95_287
1472
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_287, 0, CVT_Done },
1473
  // Convert__RegGPRC1_0__imm_95_5
1474
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_5, 0, CVT_Done },
1475
  // Convert__RegGPRC1_0__imm_95_4
1476
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_4, 0, CVT_Done },
1477
  // Convert__RegGPRC1_0__imm_95_25
1478
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_25, 0, CVT_Done },
1479
  // Convert__RegGPRC1_0__imm_95_512
1480
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_512, 0, CVT_Done },
1481
  // Convert__RegGPRC1_0__imm_95_272
1482
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_272, 0, CVT_Done },
1483
  // Convert__RegGPRC1_0__imm_95_273
1484
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_273, 0, CVT_Done },
1485
  // Convert__RegGPRC1_0__imm_95_274
1486
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_274, 0, CVT_Done },
1487
  // Convert__RegGPRC1_0__imm_95_275
1488
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_275, 0, CVT_Done },
1489
  // Convert__RegGPRC1_0__imm_95_260
1490
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_260, 0, CVT_Done },
1491
  // Convert__RegGPRC1_0__imm_95_261
1492
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_261, 0, CVT_Done },
1493
  // Convert__RegGPRC1_0__imm_95_262
1494
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_262, 0, CVT_Done },
1495
  // Convert__RegGPRC1_0__imm_95_263
1496
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_263, 0, CVT_Done },
1497
  // Convert__RegGPRC1_0__U4Imm1_1
1498
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1499
  // Convert__RegGPRC1_0__imm_95_26
1500
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_26, 0, CVT_Done },
1501
  // Convert__RegGPRC1_0__imm_95_27
1502
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_27, 0, CVT_Done },
1503
  // Convert__RegGPRC1_0__imm_95_990
1504
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_990, 0, CVT_Done },
1505
  // Convert__RegGPRC1_0__imm_95_991
1506
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_991, 0, CVT_Done },
1507
  // Convert__RegGPRC1_0__imm_95_268
1508
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_268, 0, CVT_Done },
1509
  // Convert__RegGPRC1_0__imm_95_988
1510
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_988, 0, CVT_Done },
1511
  // Convert__RegGPRC1_0__imm_95_989
1512
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_989, 0, CVT_Done },
1513
  // Convert__RegGPRC1_0__imm_95_269
1514
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_269, 0, CVT_Done },
1515
  // Convert__RegGPRC1_0__imm_95_986
1516
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_986, 0, CVT_Done },
1517
  // Convert__RegG8RC1_0__RegVRRC1_1
1518
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_Done },
1519
  // Convert__RegVRRC1_0
1520
  { CVT_95_addRegVRRCOperands, 1, CVT_Done },
1521
  // Convert__RegG8RC1_0__RegVSFRC1_1
1522
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegVSFRCOperands, 2, CVT_Done },
1523
  // Convert__RegG8RC1_0__RegVSRC1_1
1524
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_Done },
1525
  // Convert__RegGPRC1_0__RegVSFRC1_1
1526
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegVSFRCOperands, 2, CVT_Done },
1527
  // Convert__RegGPRC1_0__imm_95_1
1528
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_1, 0, CVT_Done },
1529
  // Convert__RegG8RC1_0__RegG8RC1_1__RegG8RC1_1
1530
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 2, CVT_Done },
1531
  // Convert__RegG8RC1_1__RegG8RC1_2__RegG8RC1_2
1532
  { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_95_addRegG8RCOperands, 3, CVT_Done },
1533
  // Convert__imm_95_29__RegGPRC1_0
1534
  { CVT_imm_95_29, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1535
  // Convert__imm_95_280__RegGPRC1_0
1536
  { CVT_imm_95_280, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1537
  // Convert__imm_95_28__RegGPRC1_0
1538
  { CVT_imm_95_28, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1539
  // Convert__imm_95_255__RegG8RC1_0
1540
  { CVT_imm_95_255, 0, CVT_95_addRegG8RCOperands, 1, CVT_Done },
1541
  // Convert__Imm1_0__RegGPRC1_1
1542
  { CVT_95_addImmOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1543
  // Convert__imm_95_19__RegGPRC1_0
1544
  { CVT_imm_95_19, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1545
  // Convert__imm_95_537__RegGPRC1_1
1546
  { CVT_imm_95_537, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1547
  // Convert__imm_95_539__RegGPRC1_1
1548
  { CVT_imm_95_539, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1549
  // Convert__imm_95_541__RegGPRC1_1
1550
  { CVT_imm_95_541, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1551
  // Convert__imm_95_543__RegGPRC1_1
1552
  { CVT_imm_95_543, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1553
  // Convert__imm_95_536__RegGPRC1_1
1554
  { CVT_imm_95_536, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1555
  // Convert__imm_95_538__RegGPRC1_1
1556
  { CVT_imm_95_538, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1557
  // Convert__imm_95_540__RegGPRC1_1
1558
  { CVT_imm_95_540, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1559
  // Convert__imm_95_542__RegGPRC1_1
1560
  { CVT_imm_95_542, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1561
  // Convert__imm_95_1018__RegGPRC1_0
1562
  { CVT_imm_95_1018, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1563
  // Convert__RegGPRC1_1__Imm1_0
1564
  { CVT_95_addRegGPRCOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
1565
  // Convert__imm_95_981__RegGPRC1_0
1566
  { CVT_imm_95_981, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1567
  // Convert__imm_95_22__RegGPRC1_0
1568
  { CVT_imm_95_22, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1569
  // Convert__imm_95_17__RegGPRC1_0
1570
  { CVT_imm_95_17, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1571
  // Convert__imm_95_18__RegGPRC1_0
1572
  { CVT_imm_95_18, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1573
  // Convert__imm_95_980__RegGPRC1_0
1574
  { CVT_imm_95_980, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1575
  // Convert__Imm1_0__RegF8RC1_1__imm_95_0__imm_95_0
1576
  { CVT_95_addImmOperands, 1, CVT_95_addRegF8RCOperands, 2, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
1577
  // Convert__Imm1_1__RegF8RC1_2__imm_95_0__imm_95_0
1578
  { CVT_95_addImmOperands, 2, CVT_95_addRegF8RCOperands, 3, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
1579
  // Convert__Imm1_0__RegF8RC1_1__Imm1_2__Imm1_3
1580
  { CVT_95_addImmOperands, 1, CVT_95_addRegF8RCOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
1581
  // Convert__Imm1_1__RegF8RC1_2__Imm1_3__Imm1_4
1582
  { CVT_95_addImmOperands, 2, CVT_95_addRegF8RCOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
1583
  // Convert__RegCRRC1_0__Imm1_1__imm_95_0
1584
  { CVT_95_addRegCRRCOperands, 1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1585
  // Convert__RegCRRC1_1__Imm1_2__imm_95_0
1586
  { CVT_95_addRegCRRCOperands, 2, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done },
1587
  // Convert__RegCRRC1_0__Imm1_1__Imm1_2
1588
  { CVT_95_addRegCRRCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1589
  // Convert__RegCRRC1_1__Imm1_2__Imm1_3
1590
  { CVT_95_addRegCRRCOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
1591
  // Convert__imm_95_529__RegGPRC1_1
1592
  { CVT_imm_95_529, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1593
  // Convert__imm_95_531__RegGPRC1_1
1594
  { CVT_imm_95_531, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1595
  // Convert__imm_95_533__RegGPRC1_1
1596
  { CVT_imm_95_533, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1597
  // Convert__imm_95_535__RegGPRC1_1
1598
  { CVT_imm_95_535, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1599
  // Convert__imm_95_528__RegGPRC1_1
1600
  { CVT_imm_95_528, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1601
  // Convert__imm_95_530__RegGPRC1_1
1602
  { CVT_imm_95_530, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1603
  // Convert__imm_95_532__RegGPRC1_1
1604
  { CVT_imm_95_532, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1605
  // Convert__imm_95_534__RegGPRC1_1
1606
  { CVT_imm_95_534, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1607
  // Convert__imm_95_1019__RegGPRC1_0
1608
  { CVT_imm_95_1019, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1609
  // Convert__RegGPRC1_0__imm_95_0
1610
  { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1611
  // Convert__CRBitMask1_0__RegGPRC1_1
1612
  { CVT_95_addCRBitMaskOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1613
  // Convert__imm_95_48__RegGPRC1_0
1614
  { CVT_imm_95_48, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1615
  // Convert__imm_95_25__RegGPRC1_0
1616
  { CVT_imm_95_25, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1617
  // Convert__imm_95_512__RegGPRC1_0
1618
  { CVT_imm_95_512, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1619
  // Convert__imm_95_272__RegGPRC1_1
1620
  { CVT_imm_95_272, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1621
  // Convert__imm_95_273__RegGPRC1_1
1622
  { CVT_imm_95_273, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1623
  // Convert__imm_95_274__RegGPRC1_1
1624
  { CVT_imm_95_274, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1625
  // Convert__imm_95_275__RegGPRC1_1
1626
  { CVT_imm_95_275, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1627
  // Convert__imm_95_260__RegGPRC1_1
1628
  { CVT_imm_95_260, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1629
  // Convert__imm_95_261__RegGPRC1_1
1630
  { CVT_imm_95_261, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1631
  // Convert__imm_95_262__RegGPRC1_1
1632
  { CVT_imm_95_262, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1633
  // Convert__imm_95_263__RegGPRC1_1
1634
  { CVT_imm_95_263, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1635
  // Convert__imm_95_272__RegGPRC1_0
1636
  { CVT_imm_95_272, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1637
  // Convert__imm_95_273__RegGPRC1_0
1638
  { CVT_imm_95_273, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1639
  // Convert__imm_95_274__RegGPRC1_0
1640
  { CVT_imm_95_274, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1641
  // Convert__imm_95_275__RegGPRC1_0
1642
  { CVT_imm_95_275, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1643
  // Convert__imm_95_260__RegGPRC1_0
1644
  { CVT_imm_95_260, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1645
  // Convert__imm_95_261__RegGPRC1_0
1646
  { CVT_imm_95_261, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1647
  // Convert__imm_95_262__RegGPRC1_0
1648
  { CVT_imm_95_262, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1649
  // Convert__imm_95_263__RegGPRC1_0
1650
  { CVT_imm_95_263, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1651
  // Convert__RegGPRC1_1__U4Imm1_0
1652
  { CVT_95_addRegGPRCOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
1653
  // Convert__imm_95_26__RegGPRC1_0
1654
  { CVT_imm_95_26, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1655
  // Convert__imm_95_27__RegGPRC1_0
1656
  { CVT_imm_95_27, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1657
  // Convert__imm_95_990__RegGPRC1_0
1658
  { CVT_imm_95_990, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1659
  // Convert__imm_95_991__RegGPRC1_0
1660
  { CVT_imm_95_991, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1661
  // Convert__imm_95_988__RegGPRC1_0
1662
  { CVT_imm_95_988, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1663
  // Convert__imm_95_284__RegGPRC1_0
1664
  { CVT_imm_95_284, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1665
  // Convert__imm_95_989__RegGPRC1_0
1666
  { CVT_imm_95_989, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1667
  // Convert__imm_95_285__RegGPRC1_0
1668
  { CVT_imm_95_285, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1669
  // Convert__imm_95_986__RegGPRC1_0
1670
  { CVT_imm_95_986, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1671
  // Convert__RegVSFRC1_0__RegG8RC1_1
1672
  { CVT_95_addRegVSFRCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done },
1673
  // Convert__RegVSRC1_0__RegG8RCNoX01_1__RegG8RC1_2
1674
  { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegG8RCNoX0Operands, 2, CVT_95_addRegG8RCOperands, 3, CVT_Done },
1675
  // Convert__RegVSFRC1_0__RegGPRC1_1
1676
  { CVT_95_addRegVSFRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1677
  // Convert__RegVSRC1_0__RegGPRC1_1
1678
  { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1679
  // Convert__imm_95_1__RegGPRC1_0
1680
  { CVT_imm_95_1, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1681
  // Convert__RegGPRC1_0__RegGPRC1_1__U16Imm1_2
1682
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addU16ImmOperands, 3, CVT_Done },
1683
  // Convert__RegGPRC1_1__RegGPRC1_2__U1Imm1_3
1684
  { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
1685
  // Convert__imm_95_2
1686
  { CVT_imm_95_2, 0, CVT_Done },
1687
  // Convert__RegQFRC1_0__RegQFRC1_1__RegQFRC1_2__U2Imm1_3
1688
  { CVT_95_addRegQFRCOperands, 1, CVT_95_addRegQFRCOperands, 2, CVT_95_addRegQFRCOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
1689
  // Convert__RegQFRC1_0__RegQFRC1_1__U2Imm1_2
1690
  { CVT_95_addRegQFRCOperands, 1, CVT_95_addRegQFRCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1691
  // Convert__RegQFRC1_0__RegQFRC1_1
1692
  { CVT_95_addRegQFRCOperands, 1, CVT_95_addRegQFRCOperands, 2, CVT_Done },
1693
  // Convert__RegQFRC1_0__RegQFRC1_1__RegQFRC1_2
1694
  { CVT_95_addRegQFRCOperands, 1, CVT_95_addRegQFRCOperands, 2, CVT_95_addRegQFRCOperands, 3, CVT_Done },
1695
  // Convert__RegQSRC1_0__RegQSRC1_1__RegQSRC1_2
1696
  { CVT_95_addRegQSRCOperands, 1, CVT_95_addRegQSRCOperands, 2, CVT_95_addRegQSRCOperands, 3, CVT_Done },
1697
  // Convert__RegQBRC1_0__RegQBRC1_1__RegQBRC1_2__imm_95_1
1698
  { CVT_95_addRegQBRCOperands, 1, CVT_95_addRegQBRCOperands, 2, CVT_95_addRegQBRCOperands, 3, CVT_imm_95_1, 0, CVT_Done },
1699
  // Convert__RegQBRC1_0__RegQBRC1_1__RegQBRC1_2__imm_95_4
1700
  { CVT_95_addRegQBRCOperands, 1, CVT_95_addRegQBRCOperands, 2, CVT_95_addRegQBRCOperands, 3, CVT_imm_95_4, 0, CVT_Done },
1701
  // Convert__RegQBRC1_0__RegQBRC1_0__RegQBRC1_0__imm_95_0
1702
  { CVT_95_addRegQBRCOperands, 1, CVT_95_addRegQBRCOperands, 1, CVT_95_addRegQBRCOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1703
  // Convert__RegQBRC1_0__RegQFRC1_1__RegQFRC1_2
1704
  { CVT_95_addRegQBRCOperands, 1, CVT_95_addRegQFRCOperands, 2, CVT_95_addRegQFRCOperands, 3, CVT_Done },
1705
  // Convert__RegQBRC1_0__RegQBRC1_1__RegQBRC1_1__imm_95_5
1706
  { CVT_95_addRegQBRCOperands, 1, CVT_95_addRegQBRCOperands, 2, CVT_95_addRegQBRCOperands, 2, CVT_imm_95_5, 0, CVT_Done },
1707
  // Convert__RegQBRC1_0__RegQBRC1_1__RegQBRC1_2__imm_95_9
1708
  { CVT_95_addRegQBRCOperands, 1, CVT_95_addRegQBRCOperands, 2, CVT_95_addRegQBRCOperands, 3, CVT_imm_95_9, 0, CVT_Done },
1709
  // Convert__RegQBRC1_0__RegQBRC1_1__RegQBRC1_2__U12Imm1_3
1710
  { CVT_95_addRegQBRCOperands, 1, CVT_95_addRegQBRCOperands, 2, CVT_95_addRegQBRCOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
1711
  // Convert__RegQFRC1_0__RegQFRC1_1__RegQFRC1_3__RegQFRC1_2
1712
  { CVT_95_addRegQFRCOperands, 1, CVT_95_addRegQFRCOperands, 2, CVT_95_addRegQFRCOperands, 4, CVT_95_addRegQFRCOperands, 3, CVT_Done },
1713
  // Convert__RegQSRC1_0__RegQSRC1_1__RegQSRC1_3__RegQSRC1_2
1714
  { CVT_95_addRegQSRCOperands, 1, CVT_95_addRegQSRCOperands, 2, CVT_95_addRegQSRCOperands, 4, CVT_95_addRegQSRCOperands, 3, CVT_Done },
1715
  // Convert__RegQBRC1_0__RegQBRC1_1__RegQBRC1_2__imm_95_14
1716
  { CVT_95_addRegQBRCOperands, 1, CVT_95_addRegQBRCOperands, 2, CVT_95_addRegQBRCOperands, 3, CVT_imm_95_14, 0, CVT_Done },
1717
  // Convert__RegQBRC1_0__RegQBRC1_1__RegQBRC1_2__imm_95_8
1718
  { CVT_95_addRegQBRCOperands, 1, CVT_95_addRegQBRCOperands, 2, CVT_95_addRegQBRCOperands, 3, CVT_imm_95_8, 0, CVT_Done },
1719
  // Convert__RegQBRC1_0__RegQBRC1_1__RegQBRC1_1__imm_95_10
1720
  { CVT_95_addRegQBRCOperands, 1, CVT_95_addRegQBRCOperands, 2, CVT_95_addRegQBRCOperands, 2, CVT_imm_95_10, 0, CVT_Done },
1721
  // Convert__RegQBRC1_0__RegQBRC1_1__RegQBRC1_2__imm_95_7
1722
  { CVT_95_addRegQBRCOperands, 1, CVT_95_addRegQBRCOperands, 2, CVT_95_addRegQBRCOperands, 3, CVT_imm_95_7, 0, CVT_Done },
1723
  // Convert__RegQBRC1_0__RegQBRC1_1__RegQBRC1_2__imm_95_13
1724
  { CVT_95_addRegQBRCOperands, 1, CVT_95_addRegQBRCOperands, 2, CVT_95_addRegQBRCOperands, 3, CVT_imm_95_13, 0, CVT_Done },
1725
  // Convert__RegQFRC1_0__RegQFRC1_1__RegQFRC1_2__RegQFRC1_3
1726
  { CVT_95_addRegQFRCOperands, 1, CVT_95_addRegQFRCOperands, 2, CVT_95_addRegQFRCOperands, 3, CVT_95_addRegQFRCOperands, 4, CVT_Done },
1727
  // Convert__RegQSRC1_0__RegQFRC1_1
1728
  { CVT_95_addRegQSRCOperands, 1, CVT_95_addRegQFRCOperands, 2, CVT_Done },
1729
  // Convert__RegQFRC1_0__RegQBRC1_1__RegQFRC1_3__RegQFRC1_2
1730
  { CVT_95_addRegQFRCOperands, 1, CVT_95_addRegQBRCOperands, 2, CVT_95_addRegQFRCOperands, 4, CVT_95_addRegQFRCOperands, 3, CVT_Done },
1731
  // Convert__RegQBRC1_0__RegQBRC1_0__RegQBRC1_0__imm_95_15
1732
  { CVT_95_addRegQBRCOperands, 1, CVT_95_addRegQBRCOperands, 1, CVT_95_addRegQBRCOperands, 1, CVT_imm_95_15, 0, CVT_Done },
1733
  // Convert__RegQBRC1_0__RegQBRC1_1__RegQBRC1_2__imm_95_6
1734
  { CVT_95_addRegQBRCOperands, 1, CVT_95_addRegQBRCOperands, 2, CVT_95_addRegQBRCOperands, 3, CVT_imm_95_6, 0, CVT_Done },
1735
  // Convert__RegQFRC1_0__U12Imm1_1
1736
  { CVT_95_addRegQFRCOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1737
  // Convert__RegQFRC1_0__RegGxRCNoR01_1__RegGxRC1_2
1738
  { CVT_95_addRegQFRCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done },
1739
  // Convert__RegQFRC1_0__imm_95_0__RegGxRCNoR01_1__RegGxRC1_2
1740
  { CVT_95_addRegQFRCOperands, 1, CVT_imm_95_0, 0, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done },
1741
  // Convert__RegQSRC1_0__imm_95_0__RegGxRCNoR01_1__RegGxRC1_2
1742
  { CVT_95_addRegQSRCOperands, 1, CVT_imm_95_0, 0, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done },
1743
  // Convert__imm_95_0__RegQFRC1_0__RegGxRCNoR01_1__RegGxRC1_2
1744
  { CVT_imm_95_0, 0, CVT_95_addRegQFRCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done },
1745
  // Convert__imm_95_0__RegQSRC1_0__RegGxRCNoR01_1__RegGxRC1_2
1746
  { CVT_imm_95_0, 0, CVT_95_addRegQSRCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done },
1747
  // Convert__U1Imm1_0
1748
  { CVT_95_addImmOperands, 1, CVT_Done },
1749
  // Convert__RegG8RC1_0__RegG8RC1_1__RegGPRC1_2__U6Imm1_3
1750
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
1751
  // Convert__RegG8RC1_1__RegG8RC1_2__RegGPRC1_3__U6Imm1_4
1752
  { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_95_addRegGPRCOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
1753
  // Convert__RegG8RC1_0__Tie0_1_1__RegG8RC1_1__U6Imm1_2__U6Imm1_3
1754
  { CVT_95_addRegG8RCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegG8RCOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
1755
  // Convert__RegG8RC1_1__Tie0_1_1__RegG8RC1_2__U6Imm1_3__U6Imm1_4
1756
  { CVT_95_addRegG8RCOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addRegG8RCOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
1757
  // Convert__RegG8RC1_0__RegG8RC1_1__U5Imm1_2__Imm1_3
1758
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
1759
  // Convert__RegG8RC1_1__RegG8RC1_2__U5Imm1_3__Imm1_4
1760
  { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
1761
  // Convert__RegGPRC1_0__Tie0_1_1__RegGPRC1_1__U5Imm1_2__U5Imm1_3__U5Imm1_4
1762
  { CVT_95_addRegGPRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegGPRCOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
1763
  // Convert__RegGPRC1_1__Tie0_1_1__RegGPRC1_2__U5Imm1_3__U5Imm1_4__U5Imm1_5
1764
  { CVT_95_addRegGPRCOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addRegGPRCOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
1765
  // Convert__RegGPRC1_0__RegGPRC1_1__U5Imm1_2__U5Imm1_3__U5Imm1_4
1766
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
1767
  // Convert__RegGPRC1_1__RegGPRC1_2__U5Imm1_3__U5Imm1_4__U5Imm1_5
1768
  { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
1769
  // Convert__RegGPRC1_0__RegGPRC1_1__RegGPRC1_2__U5Imm1_3__U5Imm1_4
1770
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
1771
  // Convert__RegGPRC1_1__RegGPRC1_2__RegGPRC1_3__U5Imm1_4__U5Imm1_5
1772
  { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addRegGPRCOperands, 4, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
1773
  // Convert__RegG8RC1_0__RegG8RC1_1__RegGPRC1_2__imm_95_0
1774
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_imm_95_0, 0, CVT_Done },
1775
  // Convert__RegG8RC1_1__RegG8RC1_2__RegGPRC1_3__imm_95_0
1776
  { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_95_addRegGPRCOperands, 4, CVT_imm_95_0, 0, CVT_Done },
1777
  // Convert__RegG8RC1_0__RegG8RC1_1__U6Imm1_2__imm_95_0
1778
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done },
1779
  // Convert__RegG8RC1_1__RegG8RC1_2__U6Imm1_3__imm_95_0
1780
  { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_95_addImmOperands, 4, CVT_imm_95_0, 0, CVT_Done },
1781
  // Convert__RegGPRC1_0__RegGPRC1_1__RegGPRC1_2__imm_95_0__imm_95_31
1782
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_imm_95_0, 0, CVT_imm_95_31, 0, CVT_Done },
1783
  // Convert__RegGPRC1_1__RegGPRC1_2__RegGPRC1_3__imm_95_0__imm_95_31
1784
  { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addRegGPRCOperands, 4, CVT_imm_95_0, 0, CVT_imm_95_31, 0, CVT_Done },
1785
  // Convert__RegGPRC1_0__RegGPRC1_1__U5Imm1_2__imm_95_0__imm_95_31
1786
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_imm_95_31, 0, CVT_Done },
1787
  // Convert__RegGPRC1_1__RegGPRC1_2__U5Imm1_3__imm_95_0__imm_95_31
1788
  { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addImmOperands, 4, CVT_imm_95_0, 0, CVT_imm_95_31, 0, CVT_Done },
1789
  // Convert__Imm1_0
1790
  { CVT_95_addImmOperands, 1, CVT_Done },
1791
  // Convert__RegG8RC1_0__RegCRRC1_1
1792
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegCRRCOperands, 2, CVT_Done },
1793
  // Convert__RegG8RC1_0__RegG8RC1_1__RegGPRC1_2
1794
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_Done },
1795
  // Convert__RegG8RC1_1__RegG8RC1_2__RegGPRC1_3
1796
  { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_95_addRegGPRCOperands, 4, CVT_Done },
1797
  // Convert__RegGPRC1_1__RegGxRCNoR01_2__RegGxRC1_3
1798
  { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_95_addRegGxRCOperands, 4, CVT_Done },
1799
  // Convert__imm_95_0__RegGPRC1_0__DispRI1_1__RegGxRCNoR01_2
1800
  { CVT_imm_95_0, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done },
1801
  // Convert__imm_95_0__RegGPRC1_0__RegGxRCNoR01_1__RegGxRC1_2
1802
  { CVT_imm_95_0, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done },
1803
  // Convert__RegG8RC1_1__RegGxRCNoR01_2__RegGxRC1_3
1804
  { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_95_addRegGxRCOperands, 4, CVT_Done },
1805
  // Convert__imm_95_0__RegG8RC1_0__DispRIX1_1__RegGxRCNoR01_2
1806
  { CVT_imm_95_0, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done },
1807
  // Convert__imm_95_0__RegG8RC1_0__RegGxRCNoR01_1__RegGxRC1_2
1808
  { CVT_imm_95_0, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done },
1809
  // Convert__imm_95_0__RegF8RC1_0__DispRI1_1__RegGxRCNoR01_2
1810
  { CVT_imm_95_0, 0, CVT_95_addRegF8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done },
1811
  // Convert__imm_95_0__RegF8RC1_0__RegGxRCNoR01_1__RegGxRC1_2
1812
  { CVT_imm_95_0, 0, CVT_95_addRegF8RCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done },
1813
  // Convert__imm_95_0__RegF4RC1_0__DispRI1_1__RegGxRCNoR01_2
1814
  { CVT_imm_95_0, 0, CVT_95_addRegF4RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done },
1815
  // Convert__imm_95_0__RegF4RC1_0__RegGxRCNoR01_1__RegGxRC1_2
1816
  { CVT_imm_95_0, 0, CVT_95_addRegF4RCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done },
1817
  // Convert__RegG8RC1_0__RegG8RC1_2__RegG8RC1_1
1818
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 3, CVT_95_addRegG8RCOperands, 2, CVT_Done },
1819
  // Convert__RegG8RC1_1__RegG8RC1_3__RegG8RC1_2
1820
  { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 4, CVT_95_addRegG8RCOperands, 3, CVT_Done },
1821
  // Convert__RegG8RC1_0__S16Imm1_1
1822
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1823
  // Convert__imm_95_0__RegGPRC1_1
1824
  { CVT_imm_95_0, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1825
  // Convert__imm_95_0__U5Imm1_1__RegGPRC1_2__RegGPRC1_3
1826
  { CVT_imm_95_0, 0, CVT_95_addImmOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addRegGPRCOperands, 4, CVT_Done },
1827
  // Convert__imm_95_0__U5Imm1_1__RegGPRC1_2__U5Imm1_3
1828
  { CVT_imm_95_0, 0, CVT_95_addImmOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
1829
  // Convert__imm_95_0__U1Imm1_1
1830
  { CVT_imm_95_0, 0, CVT_95_addImmOperands, 2, CVT_Done },
1831
  // Convert__U5Imm1_0__RegG8RC1_1__RegG8RC1_2
1832
  { CVT_95_addImmOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_Done },
1833
  // Convert__imm_95_4__RegG8RC1_0__RegG8RC1_1
1834
  { CVT_imm_95_4, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done },
1835
  // Convert__imm_95_4__RegG8RC1_0__S16Imm1_1
1836
  { CVT_imm_95_4, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1837
  // Convert__imm_95_12__RegG8RC1_0__RegG8RC1_1
1838
  { CVT_imm_95_12, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done },
1839
  // Convert__imm_95_12__RegG8RC1_0__S16Imm1_1
1840
  { CVT_imm_95_12, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1841
  // Convert__imm_95_8__RegG8RC1_0__RegG8RC1_1
1842
  { CVT_imm_95_8, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done },
1843
  // Convert__imm_95_8__RegG8RC1_0__S16Imm1_1
1844
  { CVT_imm_95_8, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1845
  // Convert__U5Imm1_0__RegG8RC1_1__S16Imm1_2
1846
  { CVT_95_addImmOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addS16ImmOperands, 3, CVT_Done },
1847
  // Convert__imm_95_20__RegG8RC1_0__RegG8RC1_1
1848
  { CVT_imm_95_20, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done },
1849
  // Convert__imm_95_20__RegG8RC1_0__S16Imm1_1
1850
  { CVT_imm_95_20, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1851
  // Convert__imm_95_5__RegG8RC1_0__RegG8RC1_1
1852
  { CVT_imm_95_5, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done },
1853
  // Convert__imm_95_5__RegG8RC1_0__S16Imm1_1
1854
  { CVT_imm_95_5, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1855
  // Convert__imm_95_1__RegG8RC1_0__RegG8RC1_1
1856
  { CVT_imm_95_1, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done },
1857
  // Convert__imm_95_1__RegG8RC1_0__S16Imm1_1
1858
  { CVT_imm_95_1, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1859
  // Convert__imm_95_6__RegG8RC1_0__RegG8RC1_1
1860
  { CVT_imm_95_6, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done },
1861
  // Convert__imm_95_6__RegG8RC1_0__S16Imm1_1
1862
  { CVT_imm_95_6, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1863
  // Convert__imm_95_2__RegG8RC1_0__RegG8RC1_1
1864
  { CVT_imm_95_2, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done },
1865
  // Convert__imm_95_2__RegG8RC1_0__S16Imm1_1
1866
  { CVT_imm_95_2, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1867
  // Convert__imm_95_16__RegG8RC1_0__RegG8RC1_1
1868
  { CVT_imm_95_16, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done },
1869
  // Convert__imm_95_16__RegG8RC1_0__S16Imm1_1
1870
  { CVT_imm_95_16, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1871
  // Convert__imm_95_24__RegG8RC1_0__RegG8RC1_1
1872
  { CVT_imm_95_24, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done },
1873
  // Convert__imm_95_24__RegG8RC1_0__S16Imm1_1
1874
  { CVT_imm_95_24, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1875
  // Convert__imm_95_31__RegG8RC1_0__RegG8RC1_1
1876
  { CVT_imm_95_31, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done },
1877
  // Convert__imm_95_31__RegG8RC1_0__S16Imm1_1
1878
  { CVT_imm_95_31, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1879
  // Convert__regR0__RegGPRC1_0
1880
  { CVT_regR0, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1881
  // Convert__RegGPRC1_1__RegGPRC1_0
1882
  { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 1, CVT_Done },
1883
  // Convert__RegGPRC1_0__RegGPRC1_1__Imm1_2
1884
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1885
  // Convert__RegGPRC1_0__RegGPRC1_1__imm_95_0
1886
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1887
  // Convert__RegGPRC1_0__RegGPRC1_1__imm_95_1
1888
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_imm_95_1, 0, CVT_Done },
1889
  // Convert__U5Imm1_0__RegGPRC1_1__RegGPRC1_2
1890
  { CVT_95_addImmOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_Done },
1891
  // Convert__imm_95_4__RegGPRC1_0__RegGPRC1_1
1892
  { CVT_imm_95_4, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1893
  // Convert__imm_95_4__RegGPRC1_0__S16Imm1_1
1894
  { CVT_imm_95_4, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1895
  // Convert__imm_95_12__RegGPRC1_0__RegGPRC1_1
1896
  { CVT_imm_95_12, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1897
  // Convert__imm_95_12__RegGPRC1_0__S16Imm1_1
1898
  { CVT_imm_95_12, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1899
  // Convert__imm_95_8__RegGPRC1_0__RegGPRC1_1
1900
  { CVT_imm_95_8, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1901
  // Convert__imm_95_8__RegGPRC1_0__S16Imm1_1
1902
  { CVT_imm_95_8, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1903
  // Convert__U5Imm1_0__RegGPRC1_1__S16Imm1_2
1904
  { CVT_95_addImmOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addS16ImmOperands, 3, CVT_Done },
1905
  // Convert__imm_95_20__RegGPRC1_0__RegGPRC1_1
1906
  { CVT_imm_95_20, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1907
  // Convert__imm_95_20__RegGPRC1_0__S16Imm1_1
1908
  { CVT_imm_95_20, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1909
  // Convert__imm_95_5__RegGPRC1_0__RegGPRC1_1
1910
  { CVT_imm_95_5, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1911
  // Convert__imm_95_5__RegGPRC1_0__S16Imm1_1
1912
  { CVT_imm_95_5, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1913
  // Convert__imm_95_1__RegGPRC1_0__RegGPRC1_1
1914
  { CVT_imm_95_1, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1915
  // Convert__imm_95_1__RegGPRC1_0__S16Imm1_1
1916
  { CVT_imm_95_1, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1917
  // Convert__imm_95_6__RegGPRC1_0__RegGPRC1_1
1918
  { CVT_imm_95_6, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1919
  // Convert__imm_95_6__RegGPRC1_0__S16Imm1_1
1920
  { CVT_imm_95_6, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1921
  // Convert__imm_95_2__RegGPRC1_0__RegGPRC1_1
1922
  { CVT_imm_95_2, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1923
  // Convert__imm_95_2__RegGPRC1_0__S16Imm1_1
1924
  { CVT_imm_95_2, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1925
  // Convert__imm_95_16__RegGPRC1_0__RegGPRC1_1
1926
  { CVT_imm_95_16, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1927
  // Convert__imm_95_16__RegGPRC1_0__S16Imm1_1
1928
  { CVT_imm_95_16, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1929
  // Convert__imm_95_24__RegGPRC1_0__RegGPRC1_1
1930
  { CVT_imm_95_24, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1931
  // Convert__imm_95_24__RegGPRC1_0__S16Imm1_1
1932
  { CVT_imm_95_24, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1933
  // Convert__imm_95_31__RegGPRC1_0__RegGPRC1_1
1934
  { CVT_imm_95_31, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done },
1935
  // Convert__imm_95_31__RegGPRC1_0__S16Imm1_1
1936
  { CVT_imm_95_31, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done },
1937
  // Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2
1938
  { CVT_95_addRegVRRCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_95_addRegVRRCOperands, 3, CVT_Done },
1939
  // Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2__RegVRRC1_3
1940
  { CVT_95_addRegVRRCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_95_addRegVRRCOperands, 3, CVT_95_addRegVRRCOperands, 4, CVT_Done },
1941
  // Convert__RegVRRC1_0__U5Imm1_2__RegVRRC1_1
1942
  { CVT_95_addRegVRRCOperands, 1, CVT_95_addImmOperands, 3, CVT_95_addRegVRRCOperands, 2, CVT_Done },
1943
  // Convert__RegVRRC1_0__RegVRRC1_1
1944
  { CVT_95_addRegVRRCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_Done },
1945
  // Convert__RegGPRC1_0__RegVRRC1_1
1946
  { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_Done },
1947
  // Convert__RegVRRC1_0__U4Imm1_2__RegVRRC1_1
1948
  { CVT_95_addRegVRRCOperands, 1, CVT_95_addImmOperands, 3, CVT_95_addRegVRRCOperands, 2, CVT_Done },
1949
  // Convert__RegG8RC1_0__RegG8RC1_1__RegVRRC1_2
1950
  { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addRegVRRCOperands, 3, CVT_Done },
1951
  // Convert__RegVRRC1_0__Tie0_1_1__U4Imm1_2__RegVRRC1_1
1952
  { CVT_95_addRegVRRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_95_addRegVRRCOperands, 2, CVT_Done },
1953
  // Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_1
1954
  { CVT_95_addRegVRRCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_95_addRegVRRCOperands, 2, CVT_Done },
1955
  // Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2__Tie0_1_1
1956
  { CVT_95_addRegVRRCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_95_addRegVRRCOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1957
  // Convert__RegVRRC1_0__RegVRRC1_1__U1Imm1_2__U4Imm1_3
1958
  { CVT_95_addRegVRRCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
1959
  // Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2__U4Imm1_3
1960
  { CVT_95_addRegVRRCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_95_addRegVRRCOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
1961
  // Convert__RegVRRC1_0__S5Imm1_1
1962
  { CVT_95_addRegVRRCOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1963
  // Convert__regR0__regR0__imm_95_0
1964
  { CVT_regR0, 0, CVT_regR0, 0, CVT_imm_95_0, 0, CVT_Done },
1965
  // Convert__RegVSFRC1_0__RegVSFRC1_1
1966
  { CVT_95_addRegVSFRCOperands, 1, CVT_95_addRegVSFRCOperands, 2, CVT_Done },
1967
  // Convert__RegVSFRC1_0__RegVSFRC1_1__RegVSFRC1_2
1968
  { CVT_95_addRegVSFRCOperands, 1, CVT_95_addRegVSFRCOperands, 2, CVT_95_addRegVSFRCOperands, 3, CVT_Done },
1969
  // Convert__RegVSSRC1_0__RegVSSRC1_1__RegVSSRC1_2
1970
  { CVT_95_addRegVSSRCOperands, 1, CVT_95_addRegVSSRCOperands, 2, CVT_95_addRegVSSRCOperands, 3, CVT_Done },
1971
  // Convert__RegVSRC1_0__RegVSFRC1_1__RegVSFRC1_2
1972
  { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSFRCOperands, 2, CVT_95_addRegVSFRCOperands, 3, CVT_Done },
1973
  // Convert__RegCRRC1_0__RegVSFRC1_1__RegVSFRC1_2
1974
  { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegVSFRCOperands, 2, CVT_95_addRegVSFRCOperands, 3, CVT_Done },
1975
  // Convert__RegCRRC1_0__RegVRRC1_1__RegVRRC1_2
1976
  { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_95_addRegVRRCOperands, 3, CVT_Done },
1977
  // Convert__RegVRRC1_0__RegVFRC1_1
1978
  { CVT_95_addRegVRRCOperands, 1, CVT_95_addRegVFRCOperands, 2, CVT_Done },
1979
  // Convert__RegVSRC1_0__RegVSSRC1_1
1980
  { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSSRCOperands, 2, CVT_Done },
1981
  // Convert__RegVFRC1_0__RegVRRC1_1
1982
  { CVT_95_addRegVFRCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_Done },
1983
  // Convert__RegVSSRC1_0__RegVSRC1_1
1984
  { CVT_95_addRegVSSRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_Done },
1985
  // Convert__RegVSSRC1_0__RegVSFRC1_1
1986
  { CVT_95_addRegVSSRCOperands, 1, CVT_95_addRegVSFRCOperands, 2, CVT_Done },
1987
  // Convert__RegVSRC1_0__RegG8RC1_1__RegG8RC1_2
1988
  { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_Done },
1989
  // Convert__RegVRRC1_0__RegVRRC1_1__RegVSFRC1_2
1990
  { CVT_95_addRegVRRCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_95_addRegVSFRCOperands, 3, CVT_Done },
1991
  // Convert__RegVSFRC1_0__Tie0_1_1__RegVSFRC1_1__RegVSFRC1_2
1992
  { CVT_95_addRegVSFRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegVSFRCOperands, 2, CVT_95_addRegVSFRCOperands, 3, CVT_Done },
1993
  // Convert__RegVSSRC1_0__Tie0_1_1__RegVSSRC1_1__RegVSSRC1_2
1994
  { CVT_95_addRegVSSRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegVSSRCOperands, 2, CVT_95_addRegVSSRCOperands, 3, CVT_Done },
1995
  // Convert__RegVRRC1_0__Tie0_1_1__RegVRRC1_1__RegVRRC1_2
1996
  { CVT_95_addRegVRRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegVRRCOperands, 2, CVT_95_addRegVRRCOperands, 3, CVT_Done },
1997
  // Convert__RegVSSRC1_0__RegVSSRC1_1
1998
  { CVT_95_addRegVSSRCOperands, 1, CVT_95_addRegVSSRCOperands, 2, CVT_Done },
1999
  // Convert__RegVRRC1_1__U1Imm1_0__RegVRRC1_2__U2Imm1_3
2000
  { CVT_95_addRegVRRCOperands, 2, CVT_95_addImmOperands, 1, CVT_95_addRegVRRCOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2001
  // Convert__RegCRRC1_0__RegVSFRC1_1
2002
  { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegVSFRCOperands, 2, CVT_Done },
2003
  // Convert__RegCRRC1_0__U7Imm1_2__RegVSFRC1_1
2004
  { CVT_95_addRegCRRCOperands, 1, CVT_95_addImmOperands, 3, CVT_95_addRegVSFRCOperands, 2, CVT_Done },
2005
  // Convert__RegCRRC1_0__U7Imm1_2__RegVRRC1_1
2006
  { CVT_95_addRegCRRCOperands, 1, CVT_95_addImmOperands, 3, CVT_95_addRegVRRCOperands, 2, CVT_Done },
2007
  // Convert__RegVSRC1_0__RegVSRC1_1
2008
  { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_Done },
2009
  // Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2
2010
  { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_Done },
2011
  // Convert__RegVSRC1_1__RegVSRC1_2__RegVSRC1_3
2012
  { CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_95_addRegVSRCOperands, 4, CVT_Done },
2013
  // Convert__RegVSRC1_0__Tie0_1_1__RegVSRC1_1__RegVSRC1_2
2014
  { CVT_95_addRegVSRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_Done },
2015
  // Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_1
2016
  { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 2, CVT_Done },
2017
  // Convert__RegCRRC1_0__RegVSRC1_1__RegVSRC1_2
2018
  { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_Done },
2019
  // Convert__RegCRRC1_0__RegVSRC1_1
2020
  { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_Done },
2021
  // Convert__RegVSRC1_0__U7Imm1_2__RegVSRC1_1
2022
  { CVT_95_addRegVSRCOperands, 1, CVT_95_addImmOperands, 3, CVT_95_addRegVSRCOperands, 2, CVT_Done },
2023
  // Convert__RegVSFRC1_0__RegVSRC1_1__U4Imm1_2
2024
  { CVT_95_addRegVSFRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2025
  // Convert__RegVSRC1_0__Tie0_1_1__RegVSRC1_1__U4Imm1_2
2026
  { CVT_95_addRegVSRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegVSRCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2027
  // Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2__imm_95_0
2028
  { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_imm_95_0, 0, CVT_Done },
2029
  // Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2__imm_95_3
2030
  { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_imm_95_3, 0, CVT_Done },
2031
  // Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2__U2Imm1_3
2032
  { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2033
  // Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2__RegVSRC1_3
2034
  { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_95_addRegVSRCOperands, 4, CVT_Done },
2035
  // Convert__RegVSRC1_0__RegVSFRC1_1__imm_95_0
2036
  { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSFRCOperands, 2, CVT_imm_95_0, 0, CVT_Done },
2037
  // Convert__RegVSRC1_0__RegVSFRC1_1__imm_95_3
2038
  { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSFRCOperands, 2, CVT_imm_95_3, 0, CVT_Done },
2039
  // Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_1__imm_95_0
2040
  { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 2, CVT_imm_95_0, 0, CVT_Done },
2041
  // Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_1__imm_95_3
2042
  { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 2, CVT_imm_95_3, 0, CVT_Done },
2043
  // Convert__RegVSRC1_0__U8Imm1_1
2044
  { CVT_95_addRegVSRCOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2045
  // Convert__RegVSRC1_0__RegVSRC1_1__U2Imm1_2
2046
  { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2047
  // Convert__RegVSRC1_0__RegVSFRC1_1__imm_95_2
2048
  { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSFRCOperands, 2, CVT_imm_95_2, 0, CVT_Done },
2049
  // Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_1__imm_95_2
2050
  { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 2, CVT_imm_95_2, 0, CVT_Done },
2051
};
2052
2053
void PPCAsmParser::
2054
convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
2055
7.15k
                const OperandVector &Operands) {
2056
7.15k
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
2057
7.15k
  const uint8_t *Converter = ConversionTable[Kind];
2058
7.15k
  unsigned OpIdx;
2059
7.15k
  Inst.setOpcode(Opcode);
2060
25.4k
  for (const uint8_t *p = Converter; *p; 
p+= 218.3k
) {
2061
18.3k
    OpIdx = *(p + 1);
2062
18.3k
    switch (*p) {
2063
18.3k
    
default: 0
llvm_unreachable0
("invalid conversion entry!");
2064
18.3k
    case CVT_Reg:
2065
0
      static_cast<PPCOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
2066
0
      break;
2067
18.3k
    case CVT_Tied: {
2068
98
      assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
2069
98
                          std::begin(TiedAsmOperandTable)) &&
2070
98
             "Tied operand not found");
2071
98
      unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];
2072
98
      if (TiedResOpnd != (uint8_t) -1)
2073
98
        Inst.addOperand(Inst.getOperand(TiedResOpnd));
2074
98
      break;
2075
18.3k
    }
2076
18.3k
    case CVT_95_addRegG8RCOperands:
2077
1.22k
      static_cast<PPCOperand&>(*Operands[OpIdx]).addRegG8RCOperands(Inst, 1);
2078
1.22k
      break;
2079
18.3k
    case CVT_95_addTLSRegOperands:
2080
35
      static_cast<PPCOperand&>(*Operands[OpIdx]).addTLSRegOperands(Inst, 1);
2081
35
      break;
2082
18.3k
    case CVT_95_addRegGPRCOperands:
2083
2.88k
      static_cast<PPCOperand&>(*Operands[OpIdx]).addRegGPRCOperands(Inst, 1);
2084
2.88k
      break;
2085
18.3k
    case CVT_95_addRegGPRCNoR0Operands:
2086
654
      static_cast<PPCOperand&>(*Operands[OpIdx]).addRegGPRCNoR0Operands(Inst, 1);
2087
654
      break;
2088
18.3k
    case CVT_95_addS16ImmOperands:
2089
1.07k
      static_cast<PPCOperand&>(*Operands[OpIdx]).addS16ImmOperands(Inst, 1);
2090
1.07k
      break;
2091
18.3k
    case CVT_95_addImmOperands:
2092
1.17k
      static_cast<PPCOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
2093
1.17k
      break;
2094
18.3k
    case CVT_95_addU16ImmOperands:
2095
94
      static_cast<PPCOperand&>(*Operands[OpIdx]).addU16ImmOperands(Inst, 1);
2096
94
      break;
2097
18.3k
    case CVT_95_addBranchTargetOperands:
2098
880
      static_cast<PPCOperand&>(*Operands[OpIdx]).addBranchTargetOperands(Inst, 1);
2099
880
      break;
2100
18.3k
    case CVT_95_addRegCRBITRCOperands:
2101
381
      static_cast<PPCOperand&>(*Operands[OpIdx]).addRegCRBITRCOperands(Inst, 1);
2102
381
      break;
2103
18.3k
    case CVT_imm_95_3:
2104
12
      Inst.addOperand(MCOperand::createImm(3));
2105
12
      break;
2106
18.3k
    case CVT_imm_95_2:
2107
36
      Inst.addOperand(MCOperand::createImm(2));
2108
36
      break;
2109
18.3k
    case CVT_imm_95_0:
2110
391
      Inst.addOperand(MCOperand::createImm(0));
2111
391
      break;
2112
18.3k
    case CVT_95_addRegVRRCOperands:
2113
1.81k
      static_cast<PPCOperand&>(*Operands[OpIdx]).addRegVRRCOperands(Inst, 1);
2114
1.81k
      break;
2115
18.3k
    case CVT_imm_95_8:
2116
21
      Inst.addOperand(MCOperand::createImm(8));
2117
21
      break;
2118
18.3k
    case CVT_imm_95_10:
2119
13
      Inst.addOperand(MCOperand::createImm(10));
2120
13
      break;
2121
18.3k
    case CVT_imm_95_76:
2122
60
      Inst.addOperand(MCOperand::createImm(76));
2123
60
      break;
2124
18.3k
    case CVT_regCR0:
2125
618
      Inst.addOperand(MCOperand::createReg(PPC::CR0));
2126
618
      break;
2127
18.3k
    case CVT_95_addRegCRRCOperands:
2128
736
      static_cast<PPCOperand&>(*Operands[OpIdx]).addRegCRRCOperands(Inst, 1);
2129
736
      break;
2130
18.3k
    case CVT_imm_95_79:
2131
32
      Inst.addOperand(MCOperand::createImm(79));
2132
32
      break;
2133
18.3k
    case CVT_imm_95_78:
2134
32
      Inst.addOperand(MCOperand::createImm(78));
2135
32
      break;
2136
18.3k
    case CVT_imm_95_4:
2137
91
      Inst.addOperand(MCOperand::createImm(4));
2138
91
      break;
2139
18.3k
    case CVT_imm_95_7:
2140
81
      Inst.addOperand(MCOperand::createImm(7));
2141
81
      break;
2142
18.3k
    case CVT_imm_95_6:
2143
97
      Inst.addOperand(MCOperand::createImm(6));
2144
97
      break;
2145
18.3k
    case CVT_imm_95_44:
2146
32
      Inst.addOperand(MCOperand::createImm(44));
2147
32
      break;
2148
18.3k
    case CVT_imm_95_47:
2149
32
      Inst.addOperand(MCOperand::createImm(47));
2150
32
      break;
2151
18.3k
    case CVT_imm_95_46:
2152
32
      Inst.addOperand(MCOperand::createImm(46));
2153
32
      break;
2154
18.3k
    case CVT_imm_95_36:
2155
64
      Inst.addOperand(MCOperand::createImm(36));
2156
64
      break;
2157
18.3k
    case CVT_imm_95_39:
2158
64
      Inst.addOperand(MCOperand::createImm(39));
2159
64
      break;
2160
18.3k
    case CVT_imm_95_38:
2161
64
      Inst.addOperand(MCOperand::createImm(38));
2162
64
      break;
2163
18.3k
    case CVT_imm_95_12:
2164
144
      Inst.addOperand(MCOperand::createImm(12));
2165
144
      break;
2166
18.3k
    case CVT_imm_95_15:
2167
49
      Inst.addOperand(MCOperand::createImm(15));
2168
49
      break;
2169
18.3k
    case CVT_imm_95_14:
2170
49
      Inst.addOperand(MCOperand::createImm(14));
2171
49
      break;
2172
18.3k
    case CVT_imm_95_68:
2173
32
      Inst.addOperand(MCOperand::createImm(68));
2174
32
      break;
2175
18.3k
    case CVT_imm_95_71:
2176
32
      Inst.addOperand(MCOperand::createImm(71));
2177
32
      break;
2178
18.3k
    case CVT_imm_95_70:
2179
40
      Inst.addOperand(MCOperand::createImm(70));
2180
40
      break;
2181
18.3k
    case CVT_imm_95_100:
2182
64
      Inst.addOperand(MCOperand::createImm(100));
2183
64
      break;
2184
18.3k
    case CVT_imm_95_103:
2185
64
      Inst.addOperand(MCOperand::createImm(103));
2186
64
      break;
2187
18.3k
    case CVT_imm_95_102:
2188
64
      Inst.addOperand(MCOperand::createImm(102));
2189
64
      break;
2190
18.3k
    case CVT_imm_95_108:
2191
64
      Inst.addOperand(MCOperand::createImm(108));
2192
64
      break;
2193
18.3k
    case CVT_imm_95_111:
2194
64
      Inst.addOperand(MCOperand::createImm(111));
2195
64
      break;
2196
18.3k
    case CVT_imm_95_110:
2197
64
      Inst.addOperand(MCOperand::createImm(110));
2198
64
      break;
2199
18.3k
    case CVT_imm_95_31:
2200
20
      Inst.addOperand(MCOperand::createImm(31));
2201
20
      break;
2202
18.3k
    case CVT_95_addRegGxRCNoR0Operands:
2203
1.01k
      static_cast<PPCOperand&>(*Operands[OpIdx]).addRegGxRCNoR0Operands(Inst, 1);
2204
1.01k
      break;
2205
18.3k
    case CVT_95_addRegGxRCOperands:
2206
369
      static_cast<PPCOperand&>(*Operands[OpIdx]).addRegGxRCOperands(Inst, 1);
2207
369
      break;
2208
18.3k
    case CVT_regR0:
2209
14
      Inst.addOperand(MCOperand::createReg(PPC::R0));
2210
14
      break;
2211
18.3k
    case CVT_95_addRegSPERCOperands:
2212
989
      static_cast<PPCOperand&>(*Operands[OpIdx]).addRegSPERCOperands(Inst, 1);
2213
989
      break;
2214
18.3k
    case CVT_95_addRegSPE4RCOperands:
2215
85
      static_cast<PPCOperand&>(*Operands[OpIdx]).addRegSPE4RCOperands(Inst, 1);
2216
85
      break;
2217
18.3k
    case CVT_95_addRegF4RCOperands:
2218
259
      static_cast<PPCOperand&>(*Operands[OpIdx]).addRegF4RCOperands(Inst, 1);
2219
259
      break;
2220
18.3k
    case CVT_95_addRegF8RCOperands:
2221
307
      static_cast<PPCOperand&>(*Operands[OpIdx]).addRegF8RCOperands(Inst, 1);
2222
307
      break;
2223
18.3k
    case CVT_imm_95_1:
2224
23
      Inst.addOperand(MCOperand::createImm(1));
2225
23
      break;
2226
18.3k
    case CVT_95_addRegVFRCOperands:
2227
26
      static_cast<PPCOperand&>(*Operands[OpIdx]).addRegVFRCOperands(Inst, 1);
2228
26
      break;
2229
18.3k
    case CVT_95_addRegVSFRCOperands:
2230
274
      static_cast<PPCOperand&>(*Operands[OpIdx]).addRegVSFRCOperands(Inst, 1);
2231
274
      break;
2232
18.3k
    case CVT_95_addRegVSSRCOperands:
2233
96
      static_cast<PPCOperand&>(*Operands[OpIdx]).addRegVSSRCOperands(Inst, 1);
2234
96
      break;
2235
18.3k
    case CVT_95_addRegVSRCOperands:
2236
686
      static_cast<PPCOperand&>(*Operands[OpIdx]).addRegVSRCOperands(Inst, 1);
2237
686
      break;
2238
18.3k
    case CVT_imm_95_29:
2239
4
      Inst.addOperand(MCOperand::createImm(29));
2240
4
      break;
2241
18.3k
    case CVT_imm_95_280:
2242
6
      Inst.addOperand(MCOperand::createImm(280));
2243
6
      break;
2244
18.3k
    case CVT_imm_95_128:
2245
4
      Inst.addOperand(MCOperand::createImm(128));
2246
4
      break;
2247
18.3k
    case CVT_imm_95_129:
2248
4
      Inst.addOperand(MCOperand::createImm(129));
2249
4
      break;
2250
18.3k
    case CVT_imm_95_130:
2251
4
      Inst.addOperand(MCOperand::createImm(130));
2252
4
      break;
2253
18.3k
    case CVT_imm_95_131:
2254
4
      Inst.addOperand(MCOperand::createImm(131));
2255
4
      break;
2256
18.3k
    case CVT_imm_95_132:
2257
4
      Inst.addOperand(MCOperand::createImm(132));
2258
4
      break;
2259
18.3k
    case CVT_imm_95_133:
2260
4
      Inst.addOperand(MCOperand::createImm(133));
2261
4
      break;
2262
18.3k
    case CVT_imm_95_134:
2263
4
      Inst.addOperand(MCOperand::createImm(134));
2264
4
      break;
2265
18.3k
    case CVT_imm_95_135:
2266
4
      Inst.addOperand(MCOperand::createImm(135));
2267
4
      break;
2268
18.3k
    case CVT_imm_95_28:
2269
4
      Inst.addOperand(MCOperand::createImm(28));
2270
4
      break;
2271
18.3k
    case CVT_imm_95_19:
2272
4
      Inst.addOperand(MCOperand::createImm(19));
2273
4
      break;
2274
18.3k
    case CVT_imm_95_537:
2275
4
      Inst.addOperand(MCOperand::createImm(537));
2276
4
      break;
2277
18.3k
    case CVT_imm_95_539:
2278
4
      Inst.addOperand(MCOperand::createImm(539));
2279
4
      break;
2280
18.3k
    case CVT_imm_95_541:
2281
4
      Inst.addOperand(MCOperand::createImm(541));
2282
4
      break;
2283
18.3k
    case CVT_imm_95_543:
2284
4
      Inst.addOperand(MCOperand::createImm(543));
2285
4
      break;
2286
18.3k
    case CVT_imm_95_536:
2287
4
      Inst.addOperand(MCOperand::createImm(536));
2288
4
      break;
2289
18.3k
    case CVT_imm_95_538:
2290
4
      Inst.addOperand(MCOperand::createImm(538));
2291
4
      break;
2292
18.3k
    case CVT_imm_95_540:
2293
4
      Inst.addOperand(MCOperand::createImm(540));
2294
4
      break;
2295
18.3k
    case CVT_imm_95_542:
2296
4
      Inst.addOperand(MCOperand::createImm(542));
2297
4
      break;
2298
18.3k
    case CVT_imm_95_1018:
2299
4
      Inst.addOperand(MCOperand::createImm(1018));
2300
4
      break;
2301
18.3k
    case CVT_imm_95_981:
2302
4
      Inst.addOperand(MCOperand::createImm(981));
2303
4
      break;
2304
18.3k
    case CVT_imm_95_22:
2305
8
      Inst.addOperand(MCOperand::createImm(22));
2306
8
      break;
2307
18.3k
    case CVT_imm_95_17:
2308
4
      Inst.addOperand(MCOperand::createImm(17));
2309
4
      break;
2310
18.3k
    case CVT_imm_95_18:
2311
4
      Inst.addOperand(MCOperand::createImm(18));
2312
4
      break;
2313
18.3k
    case CVT_imm_95_980:
2314
4
      Inst.addOperand(MCOperand::createImm(980));
2315
4
      break;
2316
18.3k
    case CVT_imm_95_529:
2317
4
      Inst.addOperand(MCOperand::createImm(529));
2318
4
      break;
2319
18.3k
    case CVT_imm_95_531:
2320
4
      Inst.addOperand(MCOperand::createImm(531));
2321
4
      break;
2322
18.3k
    case CVT_imm_95_533:
2323
4
      Inst.addOperand(MCOperand::createImm(533));
2324
4
      break;
2325
18.3k
    case CVT_imm_95_535:
2326
4
      Inst.addOperand(MCOperand::createImm(535));
2327
4
      break;
2328
18.3k
    case CVT_imm_95_528:
2329
4
      Inst.addOperand(MCOperand::createImm(528));
2330
4
      break;
2331
18.3k
    case CVT_imm_95_530:
2332
4
      Inst.addOperand(MCOperand::createImm(530));
2333
4
      break;
2334
18.3k
    case CVT_imm_95_532:
2335
4
      Inst.addOperand(MCOperand::createImm(532));
2336
4
      break;
2337
18.3k
    case CVT_imm_95_534:
2338
4
      Inst.addOperand(MCOperand::createImm(534));
2339
4
      break;
2340
18.3k
    case CVT_imm_95_1019:
2341
4
      Inst.addOperand(MCOperand::createImm(1019));
2342
4
      break;
2343
18.3k
    case CVT_95_addCRBitMaskOperands:
2344
4
      static_cast<PPCOperand&>(*Operands[OpIdx]).addCRBitMaskOperands(Inst, 1);
2345
4
      break;
2346
18.3k
    case CVT_imm_95_48:
2347
4
      Inst.addOperand(MCOperand::createImm(48));
2348
4
      break;
2349
18.3k
    case CVT_imm_95_287:
2350
2
      Inst.addOperand(MCOperand::createImm(287));
2351
2
      break;
2352
18.3k
    case CVT_imm_95_5:
2353
19
      Inst.addOperand(MCOperand::createImm(5));
2354
19
      break;
2355
18.3k
    case CVT_imm_95_25:
2356
8
      Inst.addOperand(MCOperand::createImm(25));
2357
8
      break;
2358
18.3k
    case CVT_imm_95_512:
2359
0
      Inst.addOperand(MCOperand::createImm(512));
2360
0
      break;
2361
18.3k
    case CVT_imm_95_272:
2362
8
      Inst.addOperand(MCOperand::createImm(272));
2363
8
      break;
2364
18.3k
    case CVT_imm_95_273:
2365
8
      Inst.addOperand(MCOperand::createImm(273));
2366
8
      break;
2367
18.3k
    case CVT_imm_95_274:
2368
8
      Inst.addOperand(MCOperand::createImm(274));
2369
8
      break;
2370
18.3k
    case CVT_imm_95_275:
2371
8
      Inst.addOperand(MCOperand::createImm(275));
2372
8
      break;
2373
18.3k
    case CVT_imm_95_260:
2374
8
      Inst.addOperand(MCOperand::createImm(260));
2375
8
      break;
2376
18.3k
    case CVT_imm_95_261:
2377
8
      Inst.addOperand(MCOperand::createImm(261));
2378
8
      break;
2379
18.3k
    case CVT_imm_95_262:
2380
8
      Inst.addOperand(MCOperand::createImm(262));
2381
8
      break;
2382
18.3k
    case CVT_imm_95_263:
2383
8
      Inst.addOperand(MCOperand::createImm(263));
2384
8
      break;
2385
18.3k
    case CVT_imm_95_26:
2386
8
      Inst.addOperand(MCOperand::createImm(26));
2387
8
      break;
2388
18.3k
    case CVT_imm_95_27:
2389
8
      Inst.addOperand(MCOperand::createImm(27));
2390
8
      break;
2391
18.3k
    case CVT_imm_95_990:
2392
4
      Inst.addOperand(MCOperand::createImm(990));
2393
4
      break;
2394
18.3k
    case CVT_imm_95_991:
2395
4
      Inst.addOperand(MCOperand::createImm(991));
2396
4
      break;
2397
18.3k
    case CVT_imm_95_268:
2398
14
      Inst.addOperand(MCOperand::createImm(268));
2399
14
      break;
2400
18.3k
    case CVT_imm_95_988:
2401
4
      Inst.addOperand(MCOperand::createImm(988));
2402
4
      break;
2403
18.3k
    case CVT_imm_95_989:
2404
4
      Inst.addOperand(MCOperand::createImm(989));
2405
4
      break;
2406
18.3k
    case CVT_imm_95_269:
2407
9
      Inst.addOperand(MCOperand::createImm(269));
2408
9
      break;
2409
18.3k
    case CVT_imm_95_986:
2410
4
      Inst.addOperand(MCOperand::createImm(986));
2411
4
      break;
2412
18.3k
    case CVT_imm_95_255:
2413
8
      Inst.addOperand(MCOperand::createImm(255));
2414
8
      break;
2415
18.3k
    case CVT_imm_95_284:
2416
2
      Inst.addOperand(MCOperand::createImm(284));
2417
2
      break;
2418
18.3k
    case CVT_imm_95_285:
2419
2
      Inst.addOperand(MCOperand::createImm(285));
2420
2
      break;
2421
18.3k
    case CVT_95_addRegG8RCNoX0Operands:
2422
2
      static_cast<PPCOperand&>(*Operands[OpIdx]).addRegG8RCNoX0Operands(Inst, 1);
2423
2
      break;
2424
18.3k
    case CVT_95_addRegQFRCOperands:
2425
180
      static_cast<PPCOperand&>(*Operands[OpIdx]).addRegQFRCOperands(Inst, 1);
2426
180
      break;
2427
18.3k
    case CVT_95_addRegQSRCOperands:
2428
28
      static_cast<PPCOperand&>(*Operands[OpIdx]).addRegQSRCOperands(Inst, 1);
2429
28
      break;
2430
18.3k
    case CVT_95_addRegQBRCOperands:
2431
40
      static_cast<PPCOperand&>(*Operands[OpIdx]).addRegQBRCOperands(Inst, 1);
2432
40
      break;
2433
18.3k
    case CVT_imm_95_9:
2434
1
      Inst.addOperand(MCOperand::createImm(9));
2435
1
      break;
2436
18.3k
    case CVT_imm_95_13:
2437
1
      Inst.addOperand(MCOperand::createImm(13));
2438
1
      break;
2439
18.3k
    case CVT_imm_95_20:
2440
16
      Inst.addOperand(MCOperand::createImm(20));
2441
16
      break;
2442
18.3k
    case CVT_imm_95_16:
2443
8
      Inst.addOperand(MCOperand::createImm(16));
2444
8
      break;
2445
18.3k
    case CVT_imm_95_24:
2446
8
      Inst.addOperand(MCOperand::createImm(24));
2447
8
      break;
2448
18.3k
    }
2449
18.3k
  }
2450
7.15k
}
2451
2452
void PPCAsmParser::
2453
convertToMapAndConstraints(unsigned Kind,
2454
0
                           const OperandVector &Operands) {
2455
0
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
2456
0
  unsigned NumMCOperands = 0;
2457
0
  const uint8_t *Converter = ConversionTable[Kind];
2458
0
  for (const uint8_t *p = Converter; *p; p+= 2) {
2459
0
    switch (*p) {
2460
0
    default: llvm_unreachable("invalid conversion entry!");
2461
0
    case CVT_Reg:
2462
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2463
0
      Operands[*(p + 1)]->setConstraint("r");
2464
0
      ++NumMCOperands;
2465
0
      break;
2466
0
    case CVT_Tied:
2467
0
      ++NumMCOperands;
2468
0
      break;
2469
0
    case CVT_95_addRegG8RCOperands:
2470
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2471
0
      Operands[*(p + 1)]->setConstraint("m");
2472
0
      NumMCOperands += 1;
2473
0
      break;
2474
0
    case CVT_95_addTLSRegOperands:
2475
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2476
0
      Operands[*(p + 1)]->setConstraint("m");
2477
0
      NumMCOperands += 1;
2478
0
      break;
2479
0
    case CVT_95_addRegGPRCOperands:
2480
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2481
0
      Operands[*(p + 1)]->setConstraint("m");
2482
0
      NumMCOperands += 1;
2483
0
      break;
2484
0
    case CVT_95_addRegGPRCNoR0Operands:
2485
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2486
0
      Operands[*(p + 1)]->setConstraint("m");
2487
0
      NumMCOperands += 1;
2488
0
      break;
2489
0
    case CVT_95_addS16ImmOperands:
2490
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2491
0
      Operands[*(p + 1)]->setConstraint("m");
2492
0
      NumMCOperands += 1;
2493
0
      break;
2494
0
    case CVT_95_addImmOperands:
2495
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2496
0
      Operands[*(p + 1)]->setConstraint("m");
2497
0
      NumMCOperands += 1;
2498
0
      break;
2499
0
    case CVT_95_addU16ImmOperands:
2500
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2501
0
      Operands[*(p + 1)]->setConstraint("m");
2502
0
      NumMCOperands += 1;
2503
0
      break;
2504
0
    case CVT_95_addBranchTargetOperands:
2505
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2506
0
      Operands[*(p + 1)]->setConstraint("m");
2507
0
      NumMCOperands += 1;
2508
0
      break;
2509
0
    case CVT_95_addRegCRBITRCOperands:
2510
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2511
0
      Operands[*(p + 1)]->setConstraint("m");
2512
0
      NumMCOperands += 1;
2513
0
      break;
2514
0
    case CVT_imm_95_3:
2515
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2516
0
      Operands[*(p + 1)]->setConstraint("");
2517
0
      ++NumMCOperands;
2518
0
      break;
2519
0
    case CVT_imm_95_2:
2520
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2521
0
      Operands[*(p + 1)]->setConstraint("");
2522
0
      ++NumMCOperands;
2523
0
      break;
2524
0
    case CVT_imm_95_0:
2525
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2526
0
      Operands[*(p + 1)]->setConstraint("");
2527
0
      ++NumMCOperands;
2528
0
      break;
2529
0
    case CVT_95_addRegVRRCOperands:
2530
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2531
0
      Operands[*(p + 1)]->setConstraint("m");
2532
0
      NumMCOperands += 1;
2533
0
      break;
2534
0
    case CVT_imm_95_8:
2535
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2536
0
      Operands[*(p + 1)]->setConstraint("");
2537
0
      ++NumMCOperands;
2538
0
      break;
2539
0
    case CVT_imm_95_10:
2540
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2541
0
      Operands[*(p + 1)]->setConstraint("");
2542
0
      ++NumMCOperands;
2543
0
      break;
2544
0
    case CVT_imm_95_76:
2545
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2546
0
      Operands[*(p + 1)]->setConstraint("");
2547
0
      ++NumMCOperands;
2548
0
      break;
2549
0
    case CVT_regCR0:
2550
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2551
0
      Operands[*(p + 1)]->setConstraint("m");
2552
0
      ++NumMCOperands;
2553
0
      break;
2554
0
    case CVT_95_addRegCRRCOperands:
2555
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2556
0
      Operands[*(p + 1)]->setConstraint("m");
2557
0
      NumMCOperands += 1;
2558
0
      break;
2559
0
    case CVT_imm_95_79:
2560
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2561
0
      Operands[*(p + 1)]->setConstraint("");
2562
0
      ++NumMCOperands;
2563
0
      break;
2564
0
    case CVT_imm_95_78:
2565
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2566
0
      Operands[*(p + 1)]->setConstraint("");
2567
0
      ++NumMCOperands;
2568
0
      break;
2569
0
    case CVT_imm_95_4:
2570
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2571
0
      Operands[*(p + 1)]->setConstraint("");
2572
0
      ++NumMCOperands;
2573
0
      break;
2574
0
    case CVT_imm_95_7:
2575
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2576
0
      Operands[*(p + 1)]->setConstraint("");
2577
0
      ++NumMCOperands;
2578
0
      break;
2579
0
    case CVT_imm_95_6:
2580
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2581
0
      Operands[*(p + 1)]->setConstraint("");
2582
0
      ++NumMCOperands;
2583
0
      break;
2584
0
    case CVT_imm_95_44:
2585
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2586
0
      Operands[*(p + 1)]->setConstraint("");
2587
0
      ++NumMCOperands;
2588
0
      break;
2589
0
    case CVT_imm_95_47:
2590
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2591
0
      Operands[*(p + 1)]->setConstraint("");
2592
0
      ++NumMCOperands;
2593
0
      break;
2594
0
    case CVT_imm_95_46:
2595
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2596
0
      Operands[*(p + 1)]->setConstraint("");
2597
0
      ++NumMCOperands;
2598
0
      break;
2599
0
    case CVT_imm_95_36:
2600
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2601
0
      Operands[*(p + 1)]->setConstraint("");
2602
0
      ++NumMCOperands;
2603
0
      break;
2604
0
    case CVT_imm_95_39:
2605
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2606
0
      Operands[*(p + 1)]->setConstraint("");
2607
0
      ++NumMCOperands;
2608
0
      break;
2609
0
    case CVT_imm_95_38:
2610
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2611
0
      Operands[*(p + 1)]->setConstraint("");
2612
0
      ++NumMCOperands;
2613
0
      break;
2614
0
    case CVT_imm_95_12:
2615
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2616
0
      Operands[*(p + 1)]->setConstraint("");
2617
0
      ++NumMCOperands;
2618
0
      break;
2619
0
    case CVT_imm_95_15:
2620
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2621
0
      Operands[*(p + 1)]->setConstraint("");
2622
0
      ++NumMCOperands;
2623
0
      break;
2624
0
    case CVT_imm_95_14:
2625
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2626
0
      Operands[*(p + 1)]->setConstraint("");
2627
0
      ++NumMCOperands;
2628
0
      break;
2629
0
    case CVT_imm_95_68:
2630
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2631
0
      Operands[*(p + 1)]->setConstraint("");
2632
0
      ++NumMCOperands;
2633
0
      break;
2634
0
    case CVT_imm_95_71:
2635
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2636
0
      Operands[*(p + 1)]->setConstraint("");
2637
0
      ++NumMCOperands;
2638
0
      break;
2639
0
    case CVT_imm_95_70:
2640
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2641
0
      Operands[*(p + 1)]->setConstraint("");
2642
0
      ++NumMCOperands;
2643
0
      break;
2644
0
    case CVT_imm_95_100:
2645
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2646
0
      Operands[*(p + 1)]->setConstraint("");
2647
0
      ++NumMCOperands;
2648
0
      break;
2649
0
    case CVT_imm_95_103:
2650
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2651
0
      Operands[*(p + 1)]->setConstraint("");
2652
0
      ++NumMCOperands;
2653
0
      break;
2654
0
    case CVT_imm_95_102:
2655
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2656
0
      Operands[*(p + 1)]->setConstraint("");
2657
0
      ++NumMCOperands;
2658
0
      break;
2659
0
    case CVT_imm_95_108:
2660
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2661
0
      Operands[*(p + 1)]->setConstraint("");
2662
0
      ++NumMCOperands;
2663
0
      break;
2664
0
    case CVT_imm_95_111:
2665
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2666
0
      Operands[*(p + 1)]->setConstraint("");
2667
0
      ++NumMCOperands;
2668
0
      break;
2669
0
    case CVT_imm_95_110:
2670
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2671
0
      Operands[*(p + 1)]->setConstraint("");
2672
0
      ++NumMCOperands;
2673
0
      break;
2674
0
    case CVT_imm_95_31:
2675
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2676
0
      Operands[*(p + 1)]->setConstraint("");
2677
0
      ++NumMCOperands;
2678
0
      break;
2679
0
    case CVT_95_addRegGxRCNoR0Operands:
2680
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2681
0
      Operands[*(p + 1)]->setConstraint("m");
2682
0
      NumMCOperands += 1;
2683
0
      break;
2684
0
    case CVT_95_addRegGxRCOperands:
2685
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2686
0
      Operands[*(p + 1)]->setConstraint("m");
2687
0
      NumMCOperands += 1;
2688
0
      break;
2689
0
    case CVT_regR0:
2690
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2691
0
      Operands[*(p + 1)]->setConstraint("m");
2692
0
      ++NumMCOperands;
2693
0
      break;
2694
0
    case CVT_95_addRegSPERCOperands:
2695
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2696
0
      Operands[*(p + 1)]->setConstraint("m");
2697
0
      NumMCOperands += 1;
2698
0
      break;
2699
0
    case CVT_95_addRegSPE4RCOperands:
2700
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2701
0
      Operands[*(p + 1)]->setConstraint("m");
2702
0
      NumMCOperands += 1;
2703
0
      break;
2704
0
    case CVT_95_addRegF4RCOperands:
2705
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2706
0
      Operands[*(p + 1)]->setConstraint("m");
2707
0
      NumMCOperands += 1;
2708
0
      break;
2709
0
    case CVT_95_addRegF8RCOperands:
2710
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2711
0
      Operands[*(p + 1)]->setConstraint("m");
2712
0
      NumMCOperands += 1;
2713
0
      break;
2714
0
    case CVT_imm_95_1:
2715
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2716
0
      Operands[*(p + 1)]->setConstraint("");
2717
0
      ++NumMCOperands;
2718
0
      break;
2719
0
    case CVT_95_addRegVFRCOperands:
2720
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2721
0
      Operands[*(p + 1)]->setConstraint("m");
2722
0
      NumMCOperands += 1;
2723
0
      break;
2724
0
    case CVT_95_addRegVSFRCOperands:
2725
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2726
0
      Operands[*(p + 1)]->setConstraint("m");
2727
0
      NumMCOperands += 1;
2728
0
      break;
2729
0
    case CVT_95_addRegVSSRCOperands:
2730
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2731
0
      Operands[*(p + 1)]->setConstraint("m");
2732
0
      NumMCOperands += 1;
2733
0
      break;
2734
0
    case CVT_95_addRegVSRCOperands:
2735
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2736
0
      Operands[*(p + 1)]->setConstraint("m");
2737
0
      NumMCOperands += 1;
2738
0
      break;
2739
0
    case CVT_imm_95_29:
2740
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2741
0
      Operands[*(p + 1)]->setConstraint("");
2742
0
      ++NumMCOperands;
2743
0
      break;
2744
0
    case CVT_imm_95_280:
2745
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2746
0
      Operands[*(p + 1)]->setConstraint("");
2747
0
      ++NumMCOperands;
2748
0
      break;
2749
0
    case CVT_imm_95_128:
2750
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2751
0
      Operands[*(p + 1)]->setConstraint("");
2752
0
      ++NumMCOperands;
2753
0
      break;
2754
0
    case CVT_imm_95_129:
2755
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2756
0
      Operands[*(p + 1)]->setConstraint("");
2757
0
      ++NumMCOperands;
2758
0
      break;
2759
0
    case CVT_imm_95_130:
2760
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2761
0
      Operands[*(p + 1)]->setConstraint("");
2762
0
      ++NumMCOperands;
2763
0
      break;
2764
0
    case CVT_imm_95_131:
2765
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2766
0
      Operands[*(p + 1)]->setConstraint("");
2767
0
      ++NumMCOperands;
2768
0
      break;
2769
0
    case CVT_imm_95_132:
2770
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2771
0
      Operands[*(p + 1)]->setConstraint("");
2772
0
      ++NumMCOperands;
2773
0
      break;
2774
0
    case CVT_imm_95_133:
2775
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2776
0
      Operands[*(p + 1)]->setConstraint("");
2777
0
      ++NumMCOperands;
2778
0
      break;
2779
0
    case CVT_imm_95_134:
2780
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2781
0
      Operands[*(p + 1)]->setConstraint("");
2782
0
      ++NumMCOperands;
2783
0
      break;
2784
0
    case CVT_imm_95_135:
2785
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2786
0
      Operands[*(p + 1)]->setConstraint("");
2787
0
      ++NumMCOperands;
2788
0
      break;
2789
0
    case CVT_imm_95_28:
2790
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2791
0
      Operands[*(p + 1)]->setConstraint("");
2792
0
      ++NumMCOperands;
2793
0
      break;
2794
0
    case CVT_imm_95_19:
2795
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2796
0
      Operands[*(p + 1)]->setConstraint("");
2797
0
      ++NumMCOperands;
2798
0
      break;
2799
0
    case CVT_imm_95_537:
2800
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2801
0
      Operands[*(p + 1)]->setConstraint("");
2802
0
      ++NumMCOperands;
2803
0
      break;
2804
0
    case CVT_imm_95_539:
2805
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2806
0
      Operands[*(p + 1)]->setConstraint("");
2807
0
      ++NumMCOperands;
2808
0
      break;
2809
0
    case CVT_imm_95_541:
2810
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2811
0
      Operands[*(p + 1)]->setConstraint("");
2812
0
      ++NumMCOperands;
2813
0
      break;
2814
0
    case CVT_imm_95_543:
2815
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2816
0
      Operands[*(p + 1)]->setConstraint("");
2817
0
      ++NumMCOperands;
2818
0
      break;
2819
0
    case CVT_imm_95_536:
2820
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2821
0
      Operands[*(p + 1)]->setConstraint("");
2822
0
      ++NumMCOperands;
2823
0
      break;
2824
0
    case CVT_imm_95_538:
2825
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2826
0
      Operands[*(p + 1)]->setConstraint("");
2827
0
      ++NumMCOperands;
2828
0
      break;
2829
0
    case CVT_imm_95_540:
2830
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2831
0
      Operands[*(p + 1)]->setConstraint("");
2832
0
      ++NumMCOperands;
2833
0
      break;
2834
0
    case CVT_imm_95_542:
2835
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2836
0
      Operands[*(p + 1)]->setConstraint("");
2837
0
      ++NumMCOperands;
2838
0
      break;
2839
0
    case CVT_imm_95_1018:
2840
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2841
0
      Operands[*(p + 1)]->setConstraint("");
2842
0
      ++NumMCOperands;
2843
0
      break;
2844
0
    case CVT_imm_95_981:
2845
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2846
0
      Operands[*(p + 1)]->setConstraint("");
2847
0
      ++NumMCOperands;
2848
0
      break;
2849
0
    case CVT_imm_95_22:
2850
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2851
0
      Operands[*(p + 1)]->setConstraint("");
2852
0
      ++NumMCOperands;
2853
0
      break;
2854
0
    case CVT_imm_95_17:
2855
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2856
0
      Operands[*(p + 1)]->setConstraint("");
2857
0
      ++NumMCOperands;
2858
0
      break;
2859
0
    case CVT_imm_95_18:
2860
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2861
0
      Operands[*(p + 1)]->setConstraint("");
2862
0
      ++NumMCOperands;
2863
0
      break;
2864
0
    case CVT_imm_95_980:
2865
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2866
0
      Operands[*(p + 1)]->setConstraint("");
2867
0
      ++NumMCOperands;
2868
0
      break;
2869
0
    case CVT_imm_95_529:
2870
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2871
0
      Operands[*(p + 1)]->setConstraint("");
2872
0
      ++NumMCOperands;
2873
0
      break;
2874
0
    case CVT_imm_95_531:
2875
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2876
0
      Operands[*(p + 1)]->setConstraint("");
2877
0
      ++NumMCOperands;
2878
0
      break;
2879
0
    case CVT_imm_95_533:
2880
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2881
0
      Operands[*(p + 1)]->setConstraint("");
2882
0
      ++NumMCOperands;
2883
0
      break;
2884
0
    case CVT_imm_95_535:
2885
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2886
0
      Operands[*(p + 1)]->setConstraint("");
2887
0
      ++NumMCOperands;
2888
0
      break;
2889
0
    case CVT_imm_95_528:
2890
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2891
0
      Operands[*(p + 1)]->setConstraint("");
2892
0
      ++NumMCOperands;
2893
0
      break;
2894
0
    case CVT_imm_95_530:
2895
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2896
0
      Operands[*(p + 1)]->setConstraint("");
2897
0
      ++NumMCOperands;
2898
0
      break;
2899
0
    case CVT_imm_95_532:
2900
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2901
0
      Operands[*(p + 1)]->setConstraint("");
2902
0
      ++NumMCOperands;
2903
0
      break;
2904
0
    case CVT_imm_95_534:
2905
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2906
0
      Operands[*(p + 1)]->setConstraint("");
2907
0
      ++NumMCOperands;
2908
0
      break;
2909
0
    case CVT_imm_95_1019:
2910
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2911
0
      Operands[*(p + 1)]->setConstraint("");
2912
0
      ++NumMCOperands;
2913
0
      break;
2914
0
    case CVT_95_addCRBitMaskOperands:
2915
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2916
0
      Operands[*(p + 1)]->setConstraint("m");
2917
0
      NumMCOperands += 1;
2918
0
      break;
2919
0
    case CVT_imm_95_48:
2920
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2921
0
      Operands[*(p + 1)]->setConstraint("");
2922
0
      ++NumMCOperands;
2923
0
      break;
2924
0
    case CVT_imm_95_287:
2925
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2926
0
      Operands[*(p + 1)]->setConstraint("");
2927
0
      ++NumMCOperands;
2928
0
      break;
2929
0
    case CVT_imm_95_5:
2930
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2931
0
      Operands[*(p + 1)]->setConstraint("");
2932
0
      ++NumMCOperands;
2933
0
      break;
2934
0
    case CVT_imm_95_25:
2935
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2936
0
      Operands[*(p + 1)]->setConstraint("");
2937
0
      ++NumMCOperands;
2938
0
      break;
2939
0
    case CVT_imm_95_512:
2940
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2941
0
      Operands[*(p + 1)]->setConstraint("");
2942
0
      ++NumMCOperands;
2943
0
      break;
2944
0
    case CVT_imm_95_272:
2945
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2946
0
      Operands[*(p + 1)]->setConstraint("");
2947
0
      ++NumMCOperands;
2948
0
      break;
2949
0
    case CVT_imm_95_273:
2950
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2951
0
      Operands[*(p + 1)]->setConstraint("");
2952
0
      ++NumMCOperands;
2953
0
      break;
2954
0
    case CVT_imm_95_274:
2955
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2956
0
      Operands[*(p + 1)]->setConstraint("");
2957
0
      ++NumMCOperands;
2958
0
      break;
2959
0
    case CVT_imm_95_275:
2960
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2961
0
      Operands[*(p + 1)]->setConstraint("");
2962
0
      ++NumMCOperands;
2963
0
      break;
2964
0
    case CVT_imm_95_260:
2965
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2966
0
      Operands[*(p + 1)]->setConstraint("");
2967
0
      ++NumMCOperands;
2968
0
      break;
2969
0
    case CVT_imm_95_261:
2970
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2971
0
      Operands[*(p + 1)]->setConstraint("");
2972
0
      ++NumMCOperands;
2973
0
      break;
2974
0
    case CVT_imm_95_262:
2975
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2976
0
      Operands[*(p + 1)]->setConstraint("");
2977
0
      ++NumMCOperands;
2978
0
      break;
2979
0
    case CVT_imm_95_263:
2980
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2981
0
      Operands[*(p + 1)]->setConstraint("");
2982
0
      ++NumMCOperands;
2983
0
      break;
2984
0
    case CVT_imm_95_26:
2985
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2986
0
      Operands[*(p + 1)]->setConstraint("");
2987
0
      ++NumMCOperands;
2988
0
      break;
2989
0
    case CVT_imm_95_27:
2990
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2991
0
      Operands[*(p + 1)]->setConstraint("");
2992
0
      ++NumMCOperands;
2993
0
      break;
2994
0
    case CVT_imm_95_990:
2995
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
2996
0
      Operands[*(p + 1)]->setConstraint("");
2997
0
      ++NumMCOperands;
2998
0
      break;
2999
0
    case CVT_imm_95_991:
3000
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3001
0
      Operands[*(p + 1)]->setConstraint("");
3002
0
      ++NumMCOperands;
3003
0
      break;
3004
0
    case CVT_imm_95_268:
3005
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3006
0
      Operands[*(p + 1)]->setConstraint("");
3007
0
      ++NumMCOperands;
3008
0
      break;
3009
0
    case CVT_imm_95_988:
3010
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3011
0
      Operands[*(p + 1)]->setConstraint("");
3012
0
      ++NumMCOperands;
3013
0
      break;
3014
0
    case CVT_imm_95_989:
3015
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3016
0
      Operands[*(p + 1)]->setConstraint("");
3017
0
      ++NumMCOperands;
3018
0
      break;
3019
0
    case CVT_imm_95_269:
3020
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3021
0
      Operands[*(p + 1)]->setConstraint("");
3022
0
      ++NumMCOperands;
3023
0
      break;
3024
0
    case CVT_imm_95_986:
3025
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3026
0
      Operands[*(p + 1)]->setConstraint("");
3027
0
      ++NumMCOperands;
3028
0
      break;
3029
0
    case CVT_imm_95_255:
3030
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3031
0
      Operands[*(p + 1)]->setConstraint("");
3032
0
      ++NumMCOperands;
3033
0
      break;
3034
0
    case CVT_imm_95_284:
3035
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3036
0
      Operands[*(p + 1)]->setConstraint("");
3037
0
      ++NumMCOperands;
3038
0
      break;
3039
0
    case CVT_imm_95_285:
3040
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3041
0
      Operands[*(p + 1)]->setConstraint("");
3042
0
      ++NumMCOperands;
3043
0
      break;
3044
0
    case CVT_95_addRegG8RCNoX0Operands:
3045
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3046
0
      Operands[*(p + 1)]->setConstraint("m");
3047
0
      NumMCOperands += 1;
3048
0
      break;
3049
0
    case CVT_95_addRegQFRCOperands:
3050
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3051
0
      Operands[*(p + 1)]->setConstraint("m");
3052
0
      NumMCOperands += 1;
3053
0
      break;
3054
0
    case CVT_95_addRegQSRCOperands:
3055
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3056
0
      Operands[*(p + 1)]->setConstraint("m");
3057
0
      NumMCOperands += 1;
3058
0
      break;
3059
0
    case CVT_95_addRegQBRCOperands:
3060
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3061
0
      Operands[*(p + 1)]->setConstraint("m");
3062
0
      NumMCOperands += 1;
3063
0
      break;
3064
0
    case CVT_imm_95_9:
3065
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3066
0
      Operands[*(p + 1)]->setConstraint("");
3067
0
      ++NumMCOperands;
3068
0
      break;
3069
0
    case CVT_imm_95_13:
3070
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3071
0
      Operands[*(p + 1)]->setConstraint("");
3072
0
      ++NumMCOperands;
3073
0
      break;
3074
0
    case CVT_imm_95_20:
3075
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3076
0
      Operands[*(p + 1)]->setConstraint("");
3077
0
      ++NumMCOperands;
3078
0
      break;
3079
0
    case CVT_imm_95_16:
3080
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3081
0
      Operands[*(p + 1)]->setConstraint("");
3082
0
      ++NumMCOperands;
3083
0
      break;
3084
0
    case CVT_imm_95_24:
3085
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3086
0
      Operands[*(p + 1)]->setConstraint("");
3087
0
      ++NumMCOperands;
3088
0
      break;
3089
0
    }
3090
0
  }
3091
0
}
3092
3093
namespace {
3094
3095
/// MatchClassKind - The kinds of classes which participate in
3096
/// instruction matching.
3097
enum MatchClassKind {
3098
  InvalidMatchClass = 0,
3099
  OptionalMatchClass = 1,
3100
  MCK__DOT_, // '.'
3101
  MCK_0, // '0'
3102
  MCK_1, // '1'
3103
  MCK_2, // '2'
3104
  MCK_3, // '3'
3105
  MCK_4, // '4'
3106
  MCK_5, // '5'
3107
  MCK_6, // '6'
3108
  MCK_7, // '7'
3109
  MCK_crD, // 'crD'
3110
  MCK_LAST_TOKEN = MCK_crD,
3111
  MCK_CRRC0, // register class 'CRRC0'
3112
  MCK_CTRRC, // register class 'CTRRC'
3113
  MCK_CTRRC8, // register class 'CTRRC8'
3114
  MCK_VRSAVERC, // register class 'VRSAVERC'
3115
  MCK_CARRYRC, // register class 'CARRYRC'
3116
  MCK_CRRC, // register class 'CRRC'
3117
  MCK_Reg21, // derived register class
3118
  MCK_Reg15, // derived register class
3119
  MCK_Reg9, // derived register class
3120
  MCK_Reg17, // derived register class
3121
  MCK_Reg13, // derived register class
3122
  MCK_Reg8, // derived register class
3123
  MCK_CRBITRC, // register class 'CRBITRC'
3124
  MCK_F4RC, // register class 'F4RC,F8RC'
3125
  MCK_QSRC, // register class 'QSRC,QBRC,QFRC'
3126
  MCK_SPERC, // register class 'SPERC'
3127
  MCK_VFRC, // register class 'VFRC'
3128
  MCK_VRRC, // register class 'VRRC'
3129
  MCK_VSLRC, // register class 'VSLRC'
3130
  MCK_Reg6, // derived register class
3131
  MCK_Reg2, // derived register class
3132
  MCK_Reg20, // derived register class
3133
  MCK_Reg12, // derived register class
3134
  MCK_G8RC, // register class 'G8RC'
3135
  MCK_G8RC_NOX0, // register class 'G8RC_NOX0'
3136
  MCK_GPRC, // register class 'GPRC,SPE4RC'
3137
  MCK_GPRC_NOR0, // register class 'GPRC_NOR0'
3138
  MCK_VSRC, // register class 'VSRC'
3139
  MCK_VSSRC, // register class 'VSSRC,VSFRC'
3140
  MCK_SPILLTOVSRRC, // register class 'SPILLTOVSRRC'
3141
  MCK_LAST_REGISTER = MCK_SPILLTOVSRRC,
3142
  MCK_Imm, // user defined class 'ImmAsmOperand'
3143
  MCK_ATBitsAsHint, // user defined class 'PPCATBitsAsHintAsmOperand'
3144
  MCK_CRBitMask, // user defined class 'PPCCRBitMaskOperand'
3145
  MCK_CondBr, // user defined class 'PPCCondBrAsmOperand'
3146
  MCK_DirectBr, // user defined class 'PPCDirectBrAsmOperand'
3147
  MCK_DispRI, // user defined class 'PPCDispRIOperand'
3148
  MCK_DispRIX16, // user defined class 'PPCDispRIX16Operand'
3149
  MCK_DispRIX, // user defined class 'PPCDispRIXOperand'
3150
  MCK_DispSPE2, // user defined class 'PPCDispSPE2Operand'
3151
  MCK_DispSPE4, // user defined class 'PPCDispSPE4Operand'
3152
  MCK_DispSPE8, // user defined class 'PPCDispSPE8Operand'
3153
  MCK_RegCRBITRC, // user defined class 'PPCRegCRBITRCAsmOperand'
3154
  MCK_RegCRRC, // user defined class 'PPCRegCRRCAsmOperand'
3155
  MCK_RegF4RC, // user defined class 'PPCRegF4RCAsmOperand'
3156
  MCK_RegF8RC, // user defined class 'PPCRegF8RCAsmOperand'
3157
  MCK_RegG8RC, // user defined class 'PPCRegG8RCAsmOperand'
3158
  MCK_RegG8RCNoX0, // user defined class 'PPCRegG8RCNoX0AsmOperand'
3159
  MCK_RegGPRC, // user defined class 'PPCRegGPRCAsmOperand'
3160
  MCK_RegGPRCNoR0, // user defined class 'PPCRegGPRCNoR0AsmOperand'
3161
  MCK_RegGxRCNoR0, // user defined class 'PPCRegGxRCNoR0Operand'
3162
  MCK_RegGxRC, // user defined class 'PPCRegGxRCOperand'
3163
  MCK_RegQBRC, // user defined class 'PPCRegQBRCAsmOperand'
3164
  MCK_RegQFRC, // user defined class 'PPCRegQFRCAsmOperand'
3165
  MCK_RegQSRC, // user defined class 'PPCRegQSRCAsmOperand'
3166
  MCK_RegSPE4RC, // user defined class 'PPCRegSPE4RCAsmOperand'
3167
  MCK_RegSPERC, // user defined class 'PPCRegSPERCAsmOperand'
3168
  MCK_RegSPILLTOVSRRC, // user defined class 'PPCRegSPILLTOVSRRCAsmOperand'
3169
  MCK_RegVFRC, // user defined class 'PPCRegVFRCAsmOperand'
3170
  MCK_RegVRRC, // user defined class 'PPCRegVRRCAsmOperand'
3171
  MCK_RegVSFRC, // user defined class 'PPCRegVSFRCAsmOperand'
3172
  MCK_RegVSRC, // user defined class 'PPCRegVSRCAsmOperand'
3173
  MCK_RegVSSRC, // user defined class 'PPCRegVSSRCAsmOperand'
3174
  MCK_S16Imm, // user defined class 'PPCS16ImmAsmOperand'
3175
  MCK_S17Imm, // user defined class 'PPCS17ImmAsmOperand'
3176
  MCK_S5Imm, // user defined class 'PPCS5ImmAsmOperand'
3177
  MCK_TLSReg, // user defined class 'PPCTLSRegOperand'
3178
  MCK_U10Imm, // user defined class 'PPCU10ImmAsmOperand'
3179
  MCK_U12Imm, // user defined class 'PPCU12ImmAsmOperand'
3180
  MCK_U16Imm, // user defined class 'PPCU16ImmAsmOperand'
3181
  MCK_U1Imm, // user defined class 'PPCU1ImmAsmOperand'
3182
  MCK_U2Imm, // user defined class 'PPCU2ImmAsmOperand'
3183
  MCK_U3Imm, // user defined class 'PPCU3ImmAsmOperand'
3184
  MCK_U4Imm, // user defined class 'PPCU4ImmAsmOperand'
3185
  MCK_U5Imm, // user defined class 'PPCU5ImmAsmOperand'
3186
  MCK_U6Imm, // user defined class 'PPCU6ImmAsmOperand'
3187
  MCK_U7Imm, // user defined class 'PPCU7ImmAsmOperand'
3188
  MCK_U8Imm, // user defined class 'PPCU8ImmAsmOperand'
3189
  NumMatchClassKinds
3190
};
3191
3192
}
3193
3194
0
static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
3195
0
  return MCTargetAsmParser::Match_InvalidOperand;
3196
0
}
3197
3198
425
static MatchClassKind matchTokenString(StringRef Name) {
3199
425
  switch (Name.size()) {
3200
425
  
default: break0
;
3201
425
  case 1:  // 9 strings to match.
3202
425
    switch (Name[0]) {
3203
425
    
default: break0
;
3204
425
    case '.':  // 1 string to match.
3205
425
      return MCK__DOT_;  // "."
3206
425
    case '0':  // 1 string to match.
3207
0
      return MCK_0;  // "0"
3208
425
    case '1':  // 1 string to match.
3209
0
      return MCK_1;  // "1"
3210
425
    case '2':  // 1 string to match.
3211
0
      return MCK_2;  // "2"
3212
425
    case '3':  // 1 string to match.
3213
0
      return MCK_3;  // "3"
3214
425
    case '4':  // 1 string to match.
3215
0
      return MCK_4;  // "4"
3216
425
    case '5':  // 1 string to match.
3217
0
      return MCK_5;  // "5"
3218
425
    case '6':  // 1 string to match.
3219
0
      return MCK_6;  // "6"
3220
425
    case '7':  // 1 string to match.
3221
0
      return MCK_7;  // "7"
3222
0
    }
3223
0
    break;
3224
0
  case 3:  // 1 string to match.
3225
0
    if (memcmp(Name.data()+0, "crD", 3) != 0)
3226
0
      break;
3227
0
    return MCK_crD;  // "crD"
3228
0
  }
3229
0
  return InvalidMatchClass;
3230
0
}
3231
3232
/// isSubclass - Compute whether \p A is a subclass of \p B.
3233
1.90k
static bool isSubclass(MatchClassKind A, MatchClassKind B) {
3234
1.90k
  if (A == B)
3235
425
    return true;
3236
1.47k
3237
1.47k
  switch (A) {
3238
1.47k
  default:
3239
1.47k
    return false;
3240
1.47k
3241
1.47k
  case MCK_CRRC0:
3242
0
    return B == MCK_CRRC;
3243
1.47k
3244
1.47k
  case MCK_Reg21:
3245
0
    switch (B) {
3246
0
    default: return false;
3247
0
    case MCK_VSLRC: return true;
3248
0
    case MCK_Reg20: return true;
3249
0
    case MCK_VSRC: return true;
3250
0
    }
3251
0
3252
0
  case MCK_Reg15:
3253
0
    return B == MCK_QSRC;
3254
0
3255
0
  case MCK_Reg9:
3256
0
    switch (B) {
3257
0
    default: return false;
3258
0
    case MCK_F4RC: return true;
3259
0
    case MCK_Reg12: return true;
3260
0
    case MCK_VSSRC: return true;
3261
0
    case MCK_SPILLTOVSRRC: return true;
3262
0
    }
3263
0
3264
0
  case MCK_Reg17:
3265
0
    switch (B) {
3266
0
    default: return false;
3267
0
    case MCK_VRRC: return true;
3268
0
    case MCK_Reg20: return true;
3269
0
    case MCK_VSRC: return true;
3270
0
    }
3271
0
3272
0
  case MCK_Reg13:
3273
0
    switch (B) {
3274
0
    default: return false;
3275
0
    case MCK_VFRC: return true;
3276
0
    case MCK_Reg12: return true;
3277
0
    case MCK_VSSRC: return true;
3278
0
    case MCK_SPILLTOVSRRC: return true;
3279
0
    }
3280
0
3281
0
  case MCK_Reg8:
3282
0
    return B == MCK_SPERC;
3283
0
3284
0
  case MCK_F4RC:
3285
0
    return B == MCK_VSSRC;
3286
0
3287
0
  case MCK_VFRC:
3288
0
    return B == MCK_VSSRC;
3289
0
3290
0
  case MCK_VRRC:
3291
0
    return B == MCK_VSRC;
3292
0
3293
0
  case MCK_VSLRC:
3294
0
    return B == MCK_VSRC;
3295
0
3296
0
  case MCK_Reg6:
3297
0
    switch (B) {
3298
0
    default: return false;
3299
0
    case MCK_G8RC: return true;
3300
0
    case MCK_G8RC_NOX0: return true;
3301
0
    case MCK_SPILLTOVSRRC: return true;
3302
0
    }
3303
0
3304
0
  case MCK_Reg2:
3305
0
    switch (B) {
3306
0
    default: return false;
3307
0
    case MCK_GPRC: return true;
3308
0
    case MCK_GPRC_NOR0: return true;
3309
0
    }
3310
0
3311
0
  case MCK_Reg20:
3312
0
    return B == MCK_VSRC;
3313
0
3314
0
  case MCK_Reg12:
3315
0
    switch (B) {
3316
0
    default: return false;
3317
0
    case MCK_VSSRC: return true;
3318
0
    case MCK_SPILLTOVSRRC: return true;
3319
0
    }
3320
0
3321
0
  case MCK_G8RC:
3322
0
    return B == MCK_SPILLTOVSRRC;
3323
1.47k
  }
3324
1.47k
}
3325
3326
17.8k
static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
3327
17.8k
  PPCOperand &Operand = (PPCOperand&)GOp;
3328
17.8k
  if (Kind == InvalidMatchClass)
3329
484
    return MCTargetAsmParser::Match_InvalidOperand;
3330
17.3k
3331
17.3k
  if (Operand.isToken() && 
Kind <= MCK_LAST_TOKEN789
)
3332
425
    return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
3333
425
             MCTargetAsmParser::Match_Success :
3334
425
             
MCTargetAsmParser::Match_InvalidOperand0
;
3335
16.9k
3336
16.9k
  switch (Kind) {
3337
16.9k
  
default: break360
;
3338
16.9k
  // 'Imm' class
3339
16.9k
  case MCK_Imm: {
3340
194
    DiagnosticPredicate DP(Operand.isImm());
3341
194
    if (DP.isMatch())
3342
188
      return MCTargetAsmParser::Match_Success;
3343
6
    break;
3344
6
    }
3345
6
  // 'ATBitsAsHint' class
3346
6
  case MCK_ATBitsAsHint: {
3347
0
    DiagnosticPredicate DP(Operand.isATBitsAsHint());
3348
0
    if (DP.isMatch())
3349
0
      return MCTargetAsmParser::Match_Success;
3350
0
    break;
3351
0
    }
3352
0
  // 'CRBitMask' class
3353
4
  case MCK_CRBitMask: {
3354
4
    DiagnosticPredicate DP(Operand.isCRBitMask());
3355
4
    if (DP.isMatch())
3356
4
      return MCTargetAsmParser::Match_Success;
3357
0
    break;
3358
0
    }
3359
0
  // 'CondBr' class
3360
1.04k
  case MCK_CondBr: {
3361
1.04k
    DiagnosticPredicate DP(Operand.isCondBr());
3362
1.04k
    if (DP.isMatch())
3363
753
      return MCTargetAsmParser::Match_Success;
3364
288
    break;
3365
288
    }
3366
288
  // 'DirectBr' class
3367
288
  case MCK_DirectBr: {
3368
169
    DiagnosticPredicate DP(Operand.isDirectBr());
3369
169
    if (DP.isMatch())
3370
169
      return MCTargetAsmParser::Match_Success;
3371
0
    break;
3372
0
    }
3373
0
  // 'DispRI' class
3374
143
  case MCK_DispRI: {
3375
143
    DiagnosticPredicate DP(Operand.isS16Imm());
3376
143
    if (DP.isMatch())
3377
135
      return MCTargetAsmParser::Match_Success;
3378
8
    break;
3379
8
    }
3380
8
  // 'DispRIX16' class
3381
18
  case MCK_DispRIX16: {
3382
18
    DiagnosticPredicate DP(Operand.isS16ImmX16());
3383
18
    if (DP.isMatch())
3384
18
      return MCTargetAsmParser::Match_Success;
3385
0
    break;
3386
0
    }
3387
0
  // 'DispRIX' class
3388
375
  case MCK_DispRIX: {
3389
375
    DiagnosticPredicate DP(Operand.isS16ImmX4());
3390
375
    if (DP.isMatch())
3391
365
      return MCTargetAsmParser::Match_Success;
3392
10
    break;
3393
10
    }
3394
10
  // 'DispSPE2' class
3395
14
  case MCK_DispSPE2: {
3396
14
    DiagnosticPredicate DP(Operand.isU6ImmX2());
3397
14
    if (DP.isMatch())
3398
14
      return MCTargetAsmParser::Match_Success;
3399
0
    break;
3400
0
    }
3401
0
  // 'DispSPE4' class
3402
54
  case MCK_DispSPE4: {
3403
54
    DiagnosticPredicate DP(Operand.isU7ImmX4());
3404
54
    if (DP.isMatch())
3405
54
      return MCTargetAsmParser::Match_Success;
3406
0
    break;
3407
0
    }
3408
0
  // 'DispSPE8' class
3409
36
  case MCK_DispSPE8: {
3410
36
    DiagnosticPredicate DP(Operand.isU8ImmX8());
3411
36
    if (DP.isMatch())
3412
36
      return MCTargetAsmParser::Match_Success;
3413
0
    break;
3414
0
    }
3415
0
  // 'RegCRBITRC' class
3416
377
  case MCK_RegCRBITRC: {
3417
377
    DiagnosticPredicate DP(Operand.isCRBitNumber());
3418
377
    if (DP.isMatch())
3419
377
      return MCTargetAsmParser::Match_Success;
3420
0
    break;
3421
0
    }
3422
0
  // 'RegCRRC' class
3423
754
  case MCK_RegCRRC: {
3424
754
    DiagnosticPredicate DP(Operand.isCCRegNumber());
3425
754
    if (DP.isMatch())
3426
748
      return MCTargetAsmParser::Match_Success;
3427
6
    break;
3428
6
    }
3429
6
  // 'RegF4RC' class
3430
307
  case MCK_RegF4RC: {
3431
307
    DiagnosticPredicate DP(Operand.isRegNumber());
3432
307
    if (DP.isMatch())
3433
259
      return MCTargetAsmParser::Match_Success;
3434
48
    break;
3435
48
    }
3436
48
  // 'RegF8RC' class
3437
355
  case MCK_RegF8RC: {
3438
355
    DiagnosticPredicate DP(Operand.isRegNumber());
3439
355
    if (DP.isMatch())
3440
311
      return MCTargetAsmParser::Match_Success;
3441
44
    break;
3442
44
    }
3443
44
  // 'RegG8RC' class
3444
1.44k
  case MCK_RegG8RC: {
3445
1.44k
    DiagnosticPredicate DP(Operand.isRegNumber());
3446
1.44k
    if (DP.isMatch())
3447
1.35k
      return MCTargetAsmParser::Match_Success;
3448
98
    break;
3449
98
    }
3450
98
  // 'RegG8RCNoX0' class
3451
98
  case MCK_RegG8RCNoX0: {
3452
2
    DiagnosticPredicate DP(Operand.isRegNumber());
3453
2
    if (DP.isMatch())
3454
2
      return MCTargetAsmParser::Match_Success;
3455
0
    break;
3456
0
    }
3457
0
  // 'RegGPRC' class
3458
3.20k
  case MCK_RegGPRC: {
3459
3.20k
    DiagnosticPredicate DP(Operand.isRegNumber());
3460
3.20k
    if (DP.isMatch())
3461
3.08k
      return MCTargetAsmParser::Match_Success;
3462
116
    break;
3463
116
    }
3464
116
  // 'RegGPRCNoR0' class
3465
662
  case MCK_RegGPRCNoR0: {
3466
662
    DiagnosticPredicate DP(Operand.isRegNumber());
3467
662
    if (DP.isMatch())
3468
662
      return MCTargetAsmParser::Match_Success;
3469
0
    break;
3470
0
    }
3471
0
  // 'RegGxRCNoR0' class
3472
1.07k
  case MCK_RegGxRCNoR0: {
3473
1.07k
    DiagnosticPredicate DP(Operand.isRegNumber());
3474
1.07k
    if (DP.isMatch())
3475
1.07k
      return MCTargetAsmParser::Match_Success;
3476
0
    break;
3477
0
    }
3478
0
  // 'RegGxRC' class
3479
409
  case MCK_RegGxRC: {
3480
409
    DiagnosticPredicate DP(Operand.isRegNumber());
3481
409
    if (DP.isMatch())
3482
401
      return MCTargetAsmParser::Match_Success;
3483
8
    break;
3484
8
    }
3485
8
  // 'RegQBRC' class
3486
34
  case MCK_RegQBRC: {
3487
34
    DiagnosticPredicate DP(Operand.isRegNumber());
3488
34
    if (DP.isMatch())
3489
34
      return MCTargetAsmParser::Match_Success;
3490
0
    break;
3491
0
    }
3492
0
  // 'RegQFRC' class
3493
180
  case MCK_RegQFRC: {
3494
180
    DiagnosticPredicate DP(Operand.isRegNumber());
3495
180
    if (DP.isMatch())
3496
180
      return MCTargetAsmParser::Match_Success;
3497
0
    break;
3498
0
    }
3499
0
  // 'RegQSRC' class
3500
28
  case MCK_RegQSRC: {
3501
28
    DiagnosticPredicate DP(Operand.isRegNumber());
3502
28
    if (DP.isMatch())
3503
28
      return MCTargetAsmParser::Match_Success;
3504
0
    break;
3505
0
    }
3506
0
  // 'RegSPE4RC' class
3507
89
  case MCK_RegSPE4RC: {
3508
89
    DiagnosticPredicate DP(Operand.isRegNumber());
3509
89
    if (DP.isMatch())
3510
89
      return MCTargetAsmParser::Match_Success;
3511
0
    break;
3512
0
    }
3513
0
  // 'RegSPERC' class
3514
989
  case MCK_RegSPERC: {
3515
989
    DiagnosticPredicate DP(Operand.isRegNumber());
3516
989
    if (DP.isMatch())
3517
989
      return MCTargetAsmParser::Match_Success;
3518
0
    break;
3519
0
    }
3520
0
  // 'RegSPILLTOVSRRC' class
3521
0
  case MCK_RegSPILLTOVSRRC: {
3522
0
    DiagnosticPredicate DP(Operand.isVSRegNumber());
3523
0
    if (DP.isMatch())
3524
0
      return MCTargetAsmParser::Match_Success;
3525
0
    break;
3526
0
    }
3527
0
  // 'RegVFRC' class
3528
26
  case MCK_RegVFRC: {
3529
26
    DiagnosticPredicate DP(Operand.isRegNumber());
3530
26
    if (DP.isMatch())
3531
26
      return MCTargetAsmParser::Match_Success;
3532
0
    break;
3533
0
    }
3534
0
  // 'RegVRRC' class
3535
1.85k
  case MCK_RegVRRC: {
3536
1.85k
    DiagnosticPredicate DP(Operand.isRegNumber());
3537
1.85k
    if (DP.isMatch())
3538
1.80k
      return MCTargetAsmParser::Match_Success;
3539
44
    break;
3540
44
    }
3541
44
  // 'RegVSFRC' class
3542
276
  case MCK_RegVSFRC: {
3543
276
    DiagnosticPredicate DP(Operand.isVSRegNumber());
3544
276
    if (DP.isMatch())
3545
276
      return MCTargetAsmParser::Match_Success;
3546
0
    break;
3547
0
    }
3548
0
  // 'RegVSRC' class
3549
696
  case MCK_RegVSRC: {
3550
696
    DiagnosticPredicate DP(Operand.isVSRegNumber());
3551
696
    if (DP.isMatch())
3552
684
      return MCTargetAsmParser::Match_Success;
3553
12
    break;
3554
12
    }
3555
12
  // 'RegVSSRC' class
3556
96
  case MCK_RegVSSRC: {
3557
96
    DiagnosticPredicate DP(Operand.isVSRegNumber());
3558
96
    if (DP.isMatch())
3559
96
      return MCTargetAsmParser::Match_Success;
3560
0
    break;
3561
0
    }
3562
0
  // 'S16Imm' class
3563
560
  case MCK_S16Imm: {
3564
560
    DiagnosticPredicate DP(Operand.isS16Imm());
3565
560
    if (DP.isMatch())
3566
556
      return MCTargetAsmParser::Match_Success;
3567
4
    break;
3568
4
    }
3569
4
  // 'S17Imm' class
3570
393
  case MCK_S17Imm: {
3571
393
    DiagnosticPredicate DP(Operand.isS17Imm());
3572
393
    if (DP.isMatch())
3573
389
      return MCTargetAsmParser::Match_Success;
3574
4
    break;
3575
4
    }
3576
4
  // 'S5Imm' class
3577
10
  case MCK_S5Imm: {
3578
10
    DiagnosticPredicate DP(Operand.isS5Imm());
3579
10
    if (DP.isMatch())
3580
10
      return MCTargetAsmParser::Match_Success;
3581
0
    break;
3582
0
    }
3583
0
  // 'TLSReg' class
3584
93
  case MCK_TLSReg: {
3585
93
    DiagnosticPredicate DP(Operand.isTLSReg());
3586
93
    if (DP.isMatch())
3587
35
      return MCTargetAsmParser::Match_Success;
3588
58
    break;
3589
58
    }
3590
58
  // 'U10Imm' class
3591
58
  case MCK_U10Imm: {
3592
2
    DiagnosticPredicate DP(Operand.isU10Imm());
3593
2
    if (DP.isMatch())
3594
2
      return MCTargetAsmParser::Match_Success;
3595
0
    break;
3596
0
    }
3597
0
  // 'U12Imm' class
3598
1
  case MCK_U12Imm: {
3599
1
    DiagnosticPredicate DP(Operand.isU12Imm());
3600
1
    if (DP.isMatch())
3601
1
      return MCTargetAsmParser::Match_Success;
3602
0
    break;
3603
0
    }
3604
0
  // 'U16Imm' class
3605
102
  case MCK_U16Imm: {
3606
102
    DiagnosticPredicate DP(Operand.isU16Imm());
3607
102
    if (DP.isMatch())
3608
98
      return MCTargetAsmParser::Match_Success;
3609
4
    break;
3610
4
    }
3611
4
  // 'U1Imm' class
3612
46
  case MCK_U1Imm: {
3613
46
    DiagnosticPredicate DP(Operand.isU1Imm());
3614
46
    if (DP.isMatch())
3615
46
      return MCTargetAsmParser::Match_Success;
3616
0
    break;
3617
0
    }
3618
0
  // 'U2Imm' class
3619
14
  case MCK_U2Imm: {
3620
14
    DiagnosticPredicate DP(Operand.isU2Imm());
3621
14
    if (DP.isMatch())
3622
14
      return MCTargetAsmParser::Match_Success;
3623
0
    break;
3624
0
    }
3625
0
  // 'U3Imm' class
3626
2
  case MCK_U3Imm: {
3627
2
    DiagnosticPredicate DP(Operand.isU3Imm());
3628
2
    if (DP.isMatch())
3629
2
      return MCTargetAsmParser::Match_Success;
3630
0
    break;
3631
0
    }
3632
0
  // 'U4Imm' class
3633
36
  case MCK_U4Imm: {
3634
36
    DiagnosticPredicate DP(Operand.isU4Imm());
3635
36
    if (DP.isMatch())
3636
36
      return MCTargetAsmParser::Match_Success;
3637
0
    break;
3638
0
    }
3639
0
  // 'U5Imm' class
3640
297
  case MCK_U5Imm: {
3641
297
    DiagnosticPredicate DP(Operand.isU5Imm());
3642
297
    if (DP.isMatch())
3643
297
      return MCTargetAsmParser::Match_Success;
3644
0
    break;
3645
0
    }
3646
0
  // 'U6Imm' class
3647
122
  case MCK_U6Imm: {
3648
122
    DiagnosticPredicate DP(Operand.isU6Imm());
3649
122
    if (DP.isMatch())
3650
122
      return MCTargetAsmParser::Match_Success;
3651
0
    break;
3652
0
    }
3653
0
  // 'U7Imm' class
3654
12
  case MCK_U7Imm: {
3655
12
    DiagnosticPredicate DP(Operand.isU7Imm());
3656
12
    if (DP.isMatch())
3657
12
      return MCTargetAsmParser::Match_Success;
3658
0
    break;
3659
0
    }
3660
0
  // 'U8Imm' class
3661
2
  case MCK_U8Imm: {
3662
2
    DiagnosticPredicate DP(Operand.isU8Imm());
3663
2
    if (DP.isMatch())
3664
2
      return MCTargetAsmParser::Match_Success;
3665
0
    break;
3666
0
    }
3667
1.11k
  } // end switch (Kind)
3668
1.11k
3669
1.11k
  if (Operand.isReg()) {
3670
0
    MatchClassKind OpKind;
3671
0
    switch (Operand.getReg()) {
3672
0
    default: OpKind = InvalidMatchClass; break;
3673
0
    case PPC::R0: OpKind = MCK_GPRC; break;
3674
0
    case PPC::R1: OpKind = MCK_Reg2; break;
3675
0
    case PPC::R2: OpKind = MCK_Reg2; break;
3676
0
    case PPC::R3: OpKind = MCK_Reg2; break;
3677
0
    case PPC::R4: OpKind = MCK_Reg2; break;
3678
0
    case PPC::R5: OpKind = MCK_Reg2; break;
3679
0
    case PPC::R6: OpKind = MCK_Reg2; break;
3680
0
    case PPC::R7: OpKind = MCK_Reg2; break;
3681
0
    case PPC::R8: OpKind = MCK_Reg2; break;
3682
0
    case PPC::R9: OpKind = MCK_Reg2; break;
3683
0
    case PPC::R10: OpKind = MCK_Reg2; break;
3684
0
    case PPC::R11: OpKind = MCK_Reg2; break;
3685
0
    case PPC::R12: OpKind = MCK_Reg2; break;
3686
0
    case PPC::R13: OpKind = MCK_Reg2; break;
3687
0
    case PPC::R14: OpKind = MCK_Reg2; break;
3688
0
    case PPC::R15: OpKind = MCK_Reg2; break;
3689
0
    case PPC::R16: OpKind = MCK_Reg2; break;
3690
0
    case PPC::R17: OpKind = MCK_Reg2; break;
3691
0
    case PPC::R18: OpKind = MCK_Reg2; break;
3692
0
    case PPC::R19: OpKind = MCK_Reg2; break;
3693
0
    case PPC::R20: OpKind = MCK_Reg2; break;
3694
0
    case PPC::R21: OpKind = MCK_Reg2; break;
3695
0
    case PPC::R22: OpKind = MCK_Reg2; break;
3696
0
    case PPC::R23: OpKind = MCK_Reg2; break;
3697
0
    case PPC::R24: OpKind = MCK_Reg2; break;
3698
0
    case PPC::R25: OpKind = MCK_Reg2; break;
3699
0
    case PPC::R26: OpKind = MCK_Reg2; break;
3700
0
    case PPC::R27: OpKind = MCK_Reg2; break;
3701
0
    case PPC::R28: OpKind = MCK_Reg2; break;
3702
0
    case PPC::R29: OpKind = MCK_Reg2; break;
3703
0
    case PPC::R30: OpKind = MCK_Reg2; break;
3704
0
    case PPC::R31: OpKind = MCK_Reg2; break;
3705
0
    case PPC::X0: OpKind = MCK_G8RC; break;
3706
0
    case PPC::X1: OpKind = MCK_Reg6; break;
3707
0
    case PPC::X2: OpKind = MCK_Reg6; break;
3708
0
    case PPC::X3: OpKind = MCK_Reg6; break;
3709
0
    case PPC::X4: OpKind = MCK_Reg6; break;
3710
0
    case PPC::X5: OpKind = MCK_Reg6; break;
3711
0
    case PPC::X6: OpKind = MCK_Reg6; break;
3712
0
    case PPC::X7: OpKind = MCK_Reg6; break;
3713
0
    case PPC::X8: OpKind = MCK_Reg6; break;
3714
0
    case PPC::X9: OpKind = MCK_Reg6; break;
3715
0
    case PPC::X10: OpKind = MCK_Reg6; break;
3716
0
    case PPC::X11: OpKind = MCK_Reg6; break;
3717
0
    case PPC::X12: OpKind = MCK_Reg6; break;
3718
0
    case PPC::X13: OpKind = MCK_Reg6; break;
3719
0
    case PPC::X14: OpKind = MCK_Reg6; break;
3720
0
    case PPC::X15: OpKind = MCK_Reg6; break;
3721
0
    case PPC::X16: OpKind = MCK_Reg6; break;
3722
0
    case PPC::X17: OpKind = MCK_Reg6; break;
3723
0
    case PPC::X18: OpKind = MCK_Reg6; break;
3724
0
    case PPC::X19: OpKind = MCK_Reg6; break;
3725
0
    case PPC::X20: OpKind = MCK_Reg6; break;
3726
0
    case PPC::X21: OpKind = MCK_Reg6; break;
3727
0
    case PPC::X22: OpKind = MCK_Reg6; break;
3728
0
    case PPC::X23: OpKind = MCK_Reg6; break;
3729
0
    case PPC::X24: OpKind = MCK_Reg6; break;
3730
0
    case PPC::X25: OpKind = MCK_Reg6; break;
3731
0
    case PPC::X26: OpKind = MCK_Reg6; break;
3732
0
    case PPC::X27: OpKind = MCK_Reg6; break;
3733
0
    case PPC::X28: OpKind = MCK_Reg6; break;
3734
0
    case PPC::X29: OpKind = MCK_Reg6; break;
3735
0
    case PPC::X30: OpKind = MCK_Reg6; break;
3736
0
    case PPC::X31: OpKind = MCK_Reg6; break;
3737
0
    case PPC::S0: OpKind = MCK_SPERC; break;
3738
0
    case PPC::S1: OpKind = MCK_Reg8; break;
3739
0
    case PPC::S2: OpKind = MCK_Reg8; break;
3740
0
    case PPC::S3: OpKind = MCK_Reg8; break;
3741
0
    case PPC::S4: OpKind = MCK_Reg8; break;
3742
0
    case PPC::S5: OpKind = MCK_Reg8; break;
3743
0
    case PPC::S6: OpKind = MCK_Reg8; break;
3744
0
    case PPC::S7: OpKind = MCK_Reg8; break;
3745
0
    case PPC::S8: OpKind = MCK_Reg8; break;
3746
0
    case PPC::S9: OpKind = MCK_Reg8; break;
3747
0
    case PPC::S10: OpKind = MCK_Reg8; break;
3748
0
    case PPC::S11: OpKind = MCK_Reg8; break;
3749
0
    case PPC::S12: OpKind = MCK_Reg8; break;
3750
0
    case PPC::S13: OpKind = MCK_Reg8; break;
3751
0
    case PPC::S14: OpKind = MCK_Reg8; break;
3752
0
    case PPC::S15: OpKind = MCK_Reg8; break;
3753
0
    case PPC::S16: OpKind = MCK_Reg8; break;
3754
0
    case PPC::S17: OpKind = MCK_Reg8; break;
3755
0
    case PPC::S18: OpKind = MCK_Reg8; break;
3756
0
    case PPC::S19: OpKind = MCK_Reg8; break;
3757
0
    case PPC::S20: OpKind = MCK_Reg8; break;
3758
0
    case PPC::S21: OpKind = MCK_Reg8; break;
3759
0
    case PPC::S22: OpKind = MCK_Reg8; break;
3760
0
    case PPC::S23: OpKind = MCK_Reg8; break;
3761
0
    case PPC::S24: OpKind = MCK_Reg8; break;
3762
0
    case PPC::S25: OpKind = MCK_Reg8; break;
3763
0
    case PPC::S26: OpKind = MCK_Reg8; break;
3764
0
    case PPC::S27: OpKind = MCK_Reg8; break;
3765
0
    case PPC::S28: OpKind = MCK_Reg8; break;
3766
0
    case PPC::S29: OpKind = MCK_Reg8; break;
3767
0
    case PPC::S30: OpKind = MCK_Reg8; break;
3768
0
    case PPC::S31: OpKind = MCK_Reg8; break;
3769
0
    case PPC::F0: OpKind = MCK_Reg9; break;
3770
0
    case PPC::F1: OpKind = MCK_Reg9; break;
3771
0
    case PPC::F2: OpKind = MCK_Reg9; break;
3772
0
    case PPC::F3: OpKind = MCK_Reg9; break;
3773
0
    case PPC::F4: OpKind = MCK_Reg9; break;
3774
0
    case PPC::F5: OpKind = MCK_Reg9; break;
3775
0
    case PPC::F6: OpKind = MCK_Reg9; break;
3776
0
    case PPC::F7: OpKind = MCK_Reg9; break;
3777
0
    case PPC::F8: OpKind = MCK_Reg9; break;
3778
0
    case PPC::F9: OpKind = MCK_Reg9; break;
3779
0
    case PPC::F10: OpKind = MCK_Reg9; break;
3780
0
    case PPC::F11: OpKind = MCK_Reg9; break;
3781
0
    case PPC::F12: OpKind = MCK_Reg9; break;
3782
0
    case PPC::F13: OpKind = MCK_Reg9; break;
3783
0
    case PPC::F14: OpKind = MCK_F4RC; break;
3784
0
    case PPC::F15: OpKind = MCK_F4RC; break;
3785
0
    case PPC::F16: OpKind = MCK_F4RC; break;
3786
0
    case PPC::F17: OpKind = MCK_F4RC; break;
3787
0
    case PPC::F18: OpKind = MCK_F4RC; break;
3788
0
    case PPC::F19: OpKind = MCK_F4RC; break;
3789
0
    case PPC::F20: OpKind = MCK_F4RC; break;
3790
0
    case PPC::F21: OpKind = MCK_F4RC; break;
3791
0
    case PPC::F22: OpKind = MCK_F4RC; break;
3792
0
    case PPC::F23: OpKind = MCK_F4RC; break;
3793
0
    case PPC::F24: OpKind = MCK_F4RC; break;
3794
0
    case PPC::F25: OpKind = MCK_F4RC; break;
3795
0
    case PPC::F26: OpKind = MCK_F4RC; break;
3796
0
    case PPC::F27: OpKind = MCK_F4RC; break;
3797
0
    case PPC::F28: OpKind = MCK_F4RC; break;
3798
0
    case PPC::F29: OpKind = MCK_F4RC; break;
3799
0
    case PPC::F30: OpKind = MCK_F4RC; break;
3800
0
    case PPC::F31: OpKind = MCK_F4RC; break;
3801
0
    case PPC::VF0: OpKind = MCK_Reg13; break;
3802
0
    case PPC::VF1: OpKind = MCK_Reg13; break;
3803
0
    case PPC::VF2: OpKind = MCK_Reg13; break;
3804
0
    case PPC::VF3: OpKind = MCK_Reg13; break;
3805
0
    case PPC::VF4: OpKind = MCK_Reg13; break;
3806
0
    case PPC::VF5: OpKind = MCK_Reg13; break;
3807
0
    case PPC::VF6: OpKind = MCK_Reg13; break;
3808
0
    case PPC::VF7: OpKind = MCK_Reg13; break;
3809
0
    case PPC::VF8: OpKind = MCK_Reg13; break;
3810
0
    case PPC::VF9: OpKind = MCK_Reg13; break;
3811
0
    case PPC::VF10: OpKind = MCK_Reg13; break;
3812
0
    case PPC::VF11: OpKind = MCK_Reg13; break;
3813
0
    case PPC::VF12: OpKind = MCK_Reg13; break;
3814
0
    case PPC::VF13: OpKind = MCK_Reg13; break;
3815
0
    case PPC::VF14: OpKind = MCK_Reg13; break;
3816
0
    case PPC::VF15: OpKind = MCK_Reg13; break;
3817
0
    case PPC::VF16: OpKind = MCK_Reg13; break;
3818
0
    case PPC::VF17: OpKind = MCK_Reg13; break;
3819
0
    case PPC::VF18: OpKind = MCK_Reg13; break;
3820
0
    case PPC::VF19: OpKind = MCK_Reg13; break;
3821
0
    case PPC::VF20: OpKind = MCK_VFRC; break;
3822
0
    case PPC::VF21: OpKind = MCK_VFRC; break;
3823
0
    case PPC::VF22: OpKind = MCK_VFRC; break;
3824
0
    case PPC::VF23: OpKind = MCK_VFRC; break;
3825
0
    case PPC::VF24: OpKind = MCK_VFRC; break;
3826
0
    case PPC::VF25: OpKind = MCK_VFRC; break;
3827
0
    case PPC::VF26: OpKind = MCK_VFRC; break;
3828
0
    case PPC::VF27: OpKind = MCK_VFRC; break;
3829
0
    case PPC::VF28: OpKind = MCK_VFRC; break;
3830
0
    case PPC::VF29: OpKind = MCK_VFRC; break;
3831
0
    case PPC::VF30: OpKind = MCK_VFRC; break;
3832
0
    case PPC::VF31: OpKind = MCK_VFRC; break;
3833
0
    case PPC::QF0: OpKind = MCK_Reg15; break;
3834
0
    case PPC::QF1: OpKind = MCK_Reg15; break;
3835
0
    case PPC::QF2: OpKind = MCK_Reg15; break;
3836
0
    case PPC::QF3: OpKind = MCK_Reg15; break;
3837
0
    case PPC::QF4: OpKind = MCK_Reg15; break;
3838
0
    case PPC::QF5: OpKind = MCK_Reg15; break;
3839
0
    case PPC::QF6: OpKind = MCK_Reg15; break;
3840
0
    case PPC::QF7: OpKind = MCK_Reg15; break;
3841
0
    case PPC::QF8: OpKind = MCK_Reg15; break;
3842
0
    case PPC::QF9: OpKind = MCK_Reg15; break;
3843
0
    case PPC::QF10: OpKind = MCK_Reg15; break;
3844
0
    case PPC::QF11: OpKind = MCK_Reg15; break;
3845
0
    case PPC::QF12: OpKind = MCK_Reg15; break;
3846
0
    case PPC::QF13: OpKind = MCK_Reg15; break;
3847
0
    case PPC::QF14: OpKind = MCK_QSRC; break;
3848
0
    case PPC::QF15: OpKind = MCK_QSRC; break;
3849
0
    case PPC::QF16: OpKind = MCK_QSRC; break;
3850
0
    case PPC::QF17: OpKind = MCK_QSRC; break;
3851
0
    case PPC::QF18: OpKind = MCK_QSRC; break;
3852
0
    case PPC::QF19: OpKind = MCK_QSRC; break;
3853
0
    case PPC::QF20: OpKind = MCK_QSRC; break;
3854
0
    case PPC::QF21: OpKind = MCK_QSRC; break;
3855
0
    case PPC::QF22: OpKind = MCK_QSRC; break;
3856
0
    case PPC::QF23: OpKind = MCK_QSRC; break;
3857
0
    case PPC::QF24: OpKind = MCK_QSRC; break;
3858
0
    case PPC::QF25: OpKind = MCK_QSRC; break;
3859
0
    case PPC::QF26: OpKind = MCK_QSRC; break;
3860
0
    case PPC::QF27: OpKind = MCK_QSRC; break;
3861
0
    case PPC::QF28: OpKind = MCK_QSRC; break;
3862
0
    case PPC::QF29: OpKind = MCK_QSRC; break;
3863
0
    case PPC::QF30: OpKind = MCK_QSRC; break;
3864
0
    case PPC::QF31: OpKind = MCK_QSRC; break;
3865
0
    case PPC::V0: OpKind = MCK_Reg17; break;
3866
0
    case PPC::V1: OpKind = MCK_Reg17; break;
3867
0
    case PPC::V2: OpKind = MCK_Reg17; break;
3868
0
    case PPC::V3: OpKind = MCK_Reg17; break;
3869
0
    case PPC::V4: OpKind = MCK_Reg17; break;
3870
0
    case PPC::V5: OpKind = MCK_Reg17; break;
3871
0
    case PPC::V6: OpKind = MCK_Reg17; break;
3872
0
    case PPC::V7: OpKind = MCK_Reg17; break;
3873
0
    case PPC::V8: OpKind = MCK_Reg17; break;
3874
0
    case PPC::V9: OpKind = MCK_Reg17; break;
3875
0
    case PPC::V10: OpKind = MCK_Reg17; break;
3876
0
    case PPC::V11: OpKind = MCK_Reg17; break;
3877
0
    case PPC::V12: OpKind = MCK_Reg17; break;
3878
0
    case PPC::V13: OpKind = MCK_Reg17; break;
3879
0
    case PPC::V14: OpKind = MCK_Reg17; break;
3880
0
    case PPC::V15: OpKind = MCK_Reg17; break;
3881
0
    case PPC::V16: OpKind = MCK_Reg17; break;
3882
0
    case PPC::V17: OpKind = MCK_Reg17; break;
3883
0
    case PPC::V18: OpKind = MCK_Reg17; break;
3884
0
    case PPC::V19: OpKind = MCK_Reg17; break;
3885
0
    case PPC::V20: OpKind = MCK_VRRC; break;
3886
0
    case PPC::V21: OpKind = MCK_VRRC; break;
3887
0
    case PPC::V22: OpKind = MCK_VRRC; break;
3888
0
    case PPC::V23: OpKind = MCK_VRRC; break;
3889
0
    case PPC::V24: OpKind = MCK_VRRC; break;
3890
0
    case PPC::V25: OpKind = MCK_VRRC; break;
3891
0
    case PPC::V26: OpKind = MCK_VRRC; break;
3892
0
    case PPC::V27: OpKind = MCK_VRRC; break;
3893
0
    case PPC::V28: OpKind = MCK_VRRC; break;
3894
0
    case PPC::V29: OpKind = MCK_VRRC; break;
3895
0
    case PPC::V30: OpKind = MCK_VRRC; break;
3896
0
    case PPC::V31: OpKind = MCK_VRRC; break;
3897
0
    case PPC::VSL0: OpKind = MCK_Reg21; break;
3898
0
    case PPC::VSL1: OpKind = MCK_Reg21; break;
3899
0
    case PPC::VSL2: OpKind = MCK_Reg21; break;
3900
0
    case PPC::VSL3: OpKind = MCK_Reg21; break;
3901
0
    case PPC::VSL4: OpKind = MCK_Reg21; break;
3902
0
    case PPC::VSL5: OpKind = MCK_Reg21; break;
3903
0
    case PPC::VSL6: OpKind = MCK_Reg21; break;
3904
0
    case PPC::VSL7: OpKind = MCK_Reg21; break;
3905
0
    case PPC::VSL8: OpKind = MCK_Reg21; break;
3906
0
    case PPC::VSL9: OpKind = MCK_Reg21; break;
3907
0
    case PPC::VSL10: OpKind = MCK_Reg21; break;
3908
0
    case PPC::VSL11: OpKind = MCK_Reg21; break;
3909
0
    case PPC::VSL12: OpKind = MCK_Reg21; break;
3910
0
    case PPC::VSL13: OpKind = MCK_Reg21; break;
3911
0
    case PPC::VSL14: OpKind = MCK_VSLRC; break;
3912
0
    case PPC::VSL15: OpKind = MCK_VSLRC; break;
3913
0
    case PPC::VSL16: OpKind = MCK_VSLRC; break;
3914
0
    case PPC::VSL17: OpKind = MCK_VSLRC; break;
3915
0
    case PPC::VSL18: OpKind = MCK_VSLRC; break;
3916
0
    case PPC::VSL19: OpKind = MCK_VSLRC; break;
3917
0
    case PPC::VSL20: OpKind = MCK_VSLRC; break;
3918
0
    case PPC::VSL21: OpKind = MCK_VSLRC; break;
3919
0
    case PPC::VSL22: OpKind = MCK_VSLRC; break;
3920
0
    case PPC::VSL23: OpKind = MCK_VSLRC; break;
3921
0
    case PPC::VSL24: OpKind = MCK_VSLRC; break;
3922
0
    case PPC::VSL25: OpKind = MCK_VSLRC; break;
3923
0
    case PPC::VSL26: OpKind = MCK_VSLRC; break;
3924
0
    case PPC::VSL27: OpKind = MCK_VSLRC; break;
3925
0
    case PPC::VSL28: OpKind = MCK_VSLRC; break;
3926
0
    case PPC::VSL29: OpKind = MCK_VSLRC; break;
3927
0
    case PPC::VSL30: OpKind = MCK_VSLRC; break;
3928
0
    case PPC::VSL31: OpKind = MCK_VSLRC; break;
3929
0
    case PPC::ZERO: OpKind = MCK_GPRC_NOR0; break;
3930
0
    case PPC::ZERO8: OpKind = MCK_G8RC_NOX0; break;
3931
0
    case PPC::FP: OpKind = MCK_Reg2; break;
3932
0
    case PPC::FP8: OpKind = MCK_Reg6; break;
3933
0
    case PPC::BP: OpKind = MCK_Reg2; break;
3934
0
    case PPC::BP8: OpKind = MCK_Reg6; break;
3935
0
    case PPC::CR0LT: OpKind = MCK_CRBITRC; break;
3936
0
    case PPC::CR0GT: OpKind = MCK_CRBITRC; break;
3937
0
    case PPC::CR0EQ: OpKind = MCK_CRBITRC; break;
3938
0
    case PPC::CR0UN: OpKind = MCK_CRBITRC; break;
3939
0
    case PPC::CR1LT: OpKind = MCK_CRBITRC; break;
3940
0
    case PPC::CR1GT: OpKind = MCK_CRBITRC; break;
3941
0
    case PPC::CR1EQ: OpKind = MCK_CRBITRC; break;
3942
0
    case PPC::CR1UN: OpKind = MCK_CRBITRC; break;
3943
0
    case PPC::CR2LT: OpKind = MCK_CRBITRC; break;
3944
0
    case PPC::CR2GT: OpKind = MCK_CRBITRC; break;
3945
0
    case PPC::CR2EQ: OpKind = MCK_CRBITRC; break;
3946
0
    case PPC::CR2UN: OpKind = MCK_CRBITRC; break;
3947
0
    case PPC::CR3LT: OpKind = MCK_CRBITRC; break;
3948
0
    case PPC::CR3GT: OpKind = MCK_CRBITRC; break;
3949
0
    case PPC::CR3EQ: OpKind = MCK_CRBITRC; break;
3950
0
    case PPC::CR3UN: OpKind = MCK_CRBITRC; break;
3951
0
    case PPC::CR4LT: OpKind = MCK_CRBITRC; break;
3952
0
    case PPC::CR4GT: OpKind = MCK_CRBITRC; break;
3953
0
    case PPC::CR4EQ: OpKind = MCK_CRBITRC; break;
3954
0
    case PPC::CR4UN: OpKind = MCK_CRBITRC; break;
3955
0
    case PPC::CR5LT: OpKind = MCK_CRBITRC; break;
3956
0
    case PPC::CR5GT: OpKind = MCK_CRBITRC; break;
3957
0
    case PPC::CR5EQ: OpKind = MCK_CRBITRC; break;
3958
0
    case PPC::CR5UN: OpKind = MCK_CRBITRC; break;
3959
0
    case PPC::CR6LT: OpKind = MCK_CRBITRC; break;
3960
0
    case PPC::CR6GT: OpKind = MCK_CRBITRC; break;
3961
0
    case PPC::CR6EQ: OpKind = MCK_CRBITRC; break;
3962
0
    case PPC::CR6UN: OpKind = MCK_CRBITRC; break;
3963
0
    case PPC::CR7LT: OpKind = MCK_CRBITRC; break;
3964
0
    case PPC::CR7GT: OpKind = MCK_CRBITRC; break;
3965
0
    case PPC::CR7EQ: OpKind = MCK_CRBITRC; break;
3966
0
    case PPC::CR7UN: OpKind = MCK_CRBITRC; break;
3967
0
    case PPC::CR0: OpKind = MCK_CRRC0; break;
3968
0
    case PPC::CR1: OpKind = MCK_CRRC; break;
3969
0
    case PPC::CR2: OpKind = MCK_CRRC; break;
3970
0
    case PPC::CR3: OpKind = MCK_CRRC; break;
3971
0
    case PPC::CR4: OpKind = MCK_CRRC; break;
3972
0
    case PPC::CR5: OpKind = MCK_CRRC; break;
3973
0
    case PPC::CR6: OpKind = MCK_CRRC; break;
3974
0
    case PPC::CR7: OpKind = MCK_CRRC; break;
3975
0
    case PPC::CTR: OpKind = MCK_CTRRC; break;
3976
0
    case PPC::CTR8: OpKind = MCK_CTRRC8; break;
3977
0
    case PPC::VRSAVE: OpKind = MCK_VRSAVERC; break;
3978
0
    case PPC::XER: OpKind = MCK_CARRYRC; break;
3979
0
    case PPC::CARRY: OpKind = MCK_CARRYRC; break;
3980
0
    }
3981
0
    return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
3982
0
                                      getDiagKindFromRegisterClass(Kind);
3983
0
  }
3984
1.11k
3985
1.11k
  if (Kind > MCK_LAST_TOKEN && 
Kind <= MCK_LAST_REGISTER758
)
3986
0
    return getDiagKindFromRegisterClass(Kind);
3987
1.11k
3988
1.11k
  return MCTargetAsmParser::Match_InvalidOperand;
3989
1.11k
}
3990
3991
#ifndef NDEBUG
3992
const char *getMatchClassName(MatchClassKind Kind) {
3993
  switch (Kind) {
3994
  case InvalidMatchClass: return "InvalidMatchClass";
3995
  case OptionalMatchClass: return "OptionalMatchClass";
3996
  case MCK__DOT_: return "MCK__DOT_";
3997
  case MCK_0: return "MCK_0";
3998
  case MCK_1: return "MCK_1";
3999
  case MCK_2: return "MCK_2";
4000
  case MCK_3: return "MCK_3";
4001
  case MCK_4: return "MCK_4";
4002
  case MCK_5: return "MCK_5";
4003
  case MCK_6: return "MCK_6";
4004
  case MCK_7: return "MCK_7";
4005
  case MCK_crD: return "MCK_crD";
4006
  case MCK_CRRC0: return "MCK_CRRC0";
4007
  case MCK_CTRRC: return "MCK_CTRRC";
4008
  case MCK_CTRRC8: return "MCK_CTRRC8";
4009
  case MCK_VRSAVERC: return "MCK_VRSAVERC";
4010
  case MCK_CARRYRC: return "MCK_CARRYRC";
4011
  case MCK_CRRC: return "MCK_CRRC";
4012
  case MCK_Reg21: return "MCK_Reg21";
4013
  case MCK_Reg15: return "MCK_Reg15";
4014
  case MCK_Reg9: return "MCK_Reg9";
4015
  case MCK_Reg17: return "MCK_Reg17";
4016
  case MCK_Reg13: return "MCK_Reg13";
4017
  case MCK_Reg8: return "MCK_Reg8";
4018
  case MCK_CRBITRC: return "MCK_CRBITRC";
4019
  case MCK_F4RC: return "MCK_F4RC";
4020
  case MCK_QSRC: return "MCK_QSRC";
4021
  case MCK_SPERC: return "MCK_SPERC";
4022
  case MCK_VFRC: return "MCK_VFRC";
4023
  case MCK_VRRC: return "MCK_VRRC";
4024
  case MCK_VSLRC: return "MCK_VSLRC";
4025
  case MCK_Reg6: return "MCK_Reg6";
4026
  case MCK_Reg2: return "MCK_Reg2";
4027
  case MCK_Reg20: return "MCK_Reg20";
4028
  case MCK_Reg12: return "MCK_Reg12";
4029
  case MCK_G8RC: return "MCK_G8RC";
4030
  case MCK_G8RC_NOX0: return "MCK_G8RC_NOX0";
4031
  case MCK_GPRC: return "MCK_GPRC";
4032
  case MCK_GPRC_NOR0: return "MCK_GPRC_NOR0";
4033
  case MCK_VSRC: return "MCK_VSRC";
4034
  case MCK_VSSRC: return "MCK_VSSRC";
4035
  case MCK_SPILLTOVSRRC: return "MCK_SPILLTOVSRRC";
4036
  case MCK_Imm: return "MCK_Imm";
4037
  case MCK_ATBitsAsHint: return "MCK_ATBitsAsHint";
4038
  case MCK_CRBitMask: return "MCK_CRBitMask";
4039
  case MCK_CondBr: return "MCK_CondBr";
4040
  case MCK_DirectBr: return "MCK_DirectBr";
4041
  case MCK_DispRI: return "MCK_DispRI";
4042
  case MCK_DispRIX16: return "MCK_DispRIX16";
4043
  case MCK_DispRIX: return "MCK_DispRIX";
4044
  case MCK_DispSPE2: return "MCK_DispSPE2";
4045
  case MCK_DispSPE4: return "MCK_DispSPE4";
4046
  case MCK_DispSPE8: return "MCK_DispSPE8";
4047
  case MCK_RegCRBITRC: return "MCK_RegCRBITRC";
4048
  case MCK_RegCRRC: return "MCK_RegCRRC";
4049
  case MCK_RegF4RC: return "MCK_RegF4RC";
4050
  case MCK_RegF8RC: return "MCK_RegF8RC";
4051
  case MCK_RegG8RC: return "MCK_RegG8RC";
4052
  case MCK_RegG8RCNoX0: return "MCK_RegG8RCNoX0";
4053
  case MCK_RegGPRC: return "MCK_RegGPRC";
4054
  case MCK_RegGPRCNoR0: return "MCK_RegGPRCNoR0";
4055
  case MCK_RegGxRCNoR0: return "MCK_RegGxRCNoR0";
4056
  case MCK_RegGxRC: return "MCK_RegGxRC";
4057
  case MCK_RegQBRC: return "MCK_RegQBRC";
4058
  case MCK_RegQFRC: return "MCK_RegQFRC";
4059
  case MCK_RegQSRC: return "MCK_RegQSRC";
4060
  case MCK_RegSPE4RC: return "MCK_RegSPE4RC";
4061
  case MCK_RegSPERC: return "MCK_RegSPERC";
4062
  case MCK_RegSPILLTOVSRRC: return "MCK_RegSPILLTOVSRRC";
4063
  case MCK_RegVFRC: return "MCK_RegVFRC";
4064
  case MCK_RegVRRC: return "MCK_RegVRRC";
4065
  case MCK_RegVSFRC: return "MCK_RegVSFRC";
4066
  case MCK_RegVSRC: return "MCK_RegVSRC";
4067
  case MCK_RegVSSRC: return "MCK_RegVSSRC";
4068
  case MCK_S16Imm: return "MCK_S16Imm";
4069
  case MCK_S17Imm: return "MCK_S17Imm";
4070
  case MCK_S5Imm: return "MCK_S5Imm";
4071
  case MCK_TLSReg: return "MCK_TLSReg";
4072
  case MCK_U10Imm: return "MCK_U10Imm";
4073
  case MCK_U12Imm: return "MCK_U12Imm";
4074
  case MCK_U16Imm: return "MCK_U16Imm";
4075
  case MCK_U1Imm: return "MCK_U1Imm";
4076
  case MCK_U2Imm: return "MCK_U2Imm";
4077
  case MCK_U3Imm: return "MCK_U3Imm";
4078
  case MCK_U4Imm: return "MCK_U4Imm";
4079
  case MCK_U5Imm: return "MCK_U5Imm";
4080
  case MCK_U6Imm: return "MCK_U6Imm";
4081
  case MCK_U7Imm: return "MCK_U7Imm";
4082
  case MCK_U8Imm: return "MCK_U8Imm";
4083
  case NumMatchClassKinds: return "NumMatchClassKinds";
4084
  }
4085
  llvm_unreachable("unhandled MatchClassKind!");
4086
}
4087
4088
#endif // NDEBUG
4089
uint64_t PPCAsmParser::
4090
396
ComputeAvailableFeatures(const FeatureBitset& FB) const {
4091
396
  uint64_t Features = 0;
4092
396
  return Features;
4093
396
}
4094
4095
static bool checkAsmTiedOperandConstraints(const PPCAsmParser&AsmParser,
4096
                               unsigned Kind,
4097
                               const OperandVector &Operands,
4098
7.15k
                               uint64_t &ErrorInfo) {
4099
7.15k
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
4100
7.15k
  const uint8_t *Converter = ConversionTable[Kind];
4101
25.4k
  for (const uint8_t *p = Converter; *p; 
p+= 218.3k
) {
4102
18.3k
    switch (*p) {
4103
18.3k
    case CVT_Tied: {
4104
98
      unsigned OpIdx = *(p+1);
4105
98
      assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
4106
98
                              std::begin(TiedAsmOperandTable)) &&
4107
98
             "Tied operand not found");
4108
98
      unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];
4109
98
      unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];
4110
98
      if (OpndNum1 != OpndNum2) {
4111
0
        auto &SrcOp1 = Operands[OpndNum1];
4112
0
        auto &SrcOp2 = Operands[OpndNum2];
4113
0
        if (SrcOp1->isReg() && SrcOp2->isReg()) {
4114
0
          if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) {
4115
0
            ErrorInfo = OpndNum2;
4116
0
            return false;
4117
0
          }
4118
98
        }
4119
0
      }
4120
98
      break;
4121
98
    }
4122
18.2k
    default:
4123
18.2k
      break;
4124
18.3k
    }
4125
18.3k
  }
4126
7.15k
  return true;
4127
7.15k
}
4128
4129
static const char *const MnemonicTable =
4130
    "\003add\004addc\004adde\004addi\005addic\005addis\005addme\007addpcis\005"
4131
    "addze\003and\004andc\004andi\005andis\004attn\001b\002ba\002bc\003bc+\003"
4132
    "bc-\003bca\004bca+\004bca-\005bcctr\006bcctrl\006bcdcfn\007bcdcfsq\006b"
4133
    "cdcfz\010bcdcpsgn\006bcdctn\007bcdctsq\006bcdctz\004bcds\tbcdsetsgn\005"
4134
    "bcdsr\010bcdtrunc\005bcdus\tbcdutrunc\003bcl\004bcl+\004bcl-\004bcla\005"
4135
    "bcla+\005bcla-\004bclr\005bclrl\004bctr\005bctrl\004bdnz\005bdnz+\005bd"
4136
    "nz-\005bdnza\006bdnza+\006bdnza-\005bdnzf\006bdnzfa\006bdnzfl\007bdnzfl"
4137
    "a\007bdnzflr\010bdnzflrl\005bdnzl\006bdnzl+\006bdnzl-\006bdnzla\007bdnz"
4138
    "la+\007bdnzla-\006bdnzlr\007bdnzlr+\007bdnzlr-\007bdnzlrl\010bdnzlrl+\010"
4139
    "bdnzlrl-\005bdnzt\006bdnzta\006bdnztl\007bdnztla\007bdnztlr\010bdnztlrl"
4140
    "\003bdz\004bdz+\004bdz-\004bdza\005bdza+\005bdza-\004bdzf\005bdzfa\005b"
4141
    "dzfl\006bdzfla\006bdzflr\007bdzflrl\004bdzl\005bdzl+\005bdzl-\005bdzla\006"
4142
    "bdzla+\006bdzla-\005bdzlr\006bdzlr+\006bdzlr-\006bdzlrl\007bdzlrl+\007b"
4143
    "dzlrl-\004bdzt\005bdzta\005bdztl\006bdztla\006bdztlr\007bdztlrl\003beq\004"
4144
    "beq+\004beq-\004beqa\005beqa+\005beqa-\006beqctr\007beqctr+\007beqctr-\007"
4145
    "beqctrl\010beqctrl+\010beqctrl-\004beql\005beql+\005beql-\005beqla\006b"
4146
    "eqla+\006beqla-\005beqlr\006beqlr+\006beqlr-\006beqlrl\007beqlrl+\007be"
4147
    "qlrl-\002bf\003bf+\003bf-\003bfa\004bfa+\004bfa-\005bfctr\006bfctr+\006"
4148
    "bfctr-\006bfctrl\007bfctrl+\007bfctrl-\003bfl\004bfl+\004bfl-\004bfla\005"
4149
    "bfla+\005bfla-\004bflr\005bflr+\005bflr-\005bflrl\006bflrl+\006bflrl-\003"
4150
    "bge\004bge+\004bge-\004bgea\005bgea+\005bgea-\006bgectr\007bgectr+\007b"
4151
    "gectr-\007bgectrl\010bgectrl+\010bgectrl-\004bgel\005bgel+\005bgel-\005"
4152
    "bgela\006bgela+\006bgela-\005bgelr\006bgelr+\006bgelr-\006bgelrl\007bge"
4153
    "lrl+\007bgelrl-\003bgt\004bgt+\004bgt-\004bgta\005bgta+\005bgta-\006bgt"
4154
    "ctr\007bgtctr+\007bgtctr-\007bgtctrl\010bgtctrl+\010bgtctrl-\004bgtl\005"
4155
    "bgtl+\005bgtl-\005bgtla\006bgtla+\006bgtla-\005bgtlr\006bgtlr+\006bgtlr"
4156
    "-\006bgtlrl\007bgtlrl+\007bgtlrl-\002bl\003bla\003ble\004ble+\004ble-\004"
4157
    "blea\005blea+\005blea-\006blectr\007blectr+\007blectr-\007blectrl\010bl"
4158
    "ectrl+\010blectrl-\004blel\005blel+\005blel-\005blela\006blela+\006blel"
4159
    "a-\005blelr\006blelr+\006blelr-\006blelrl\007blelrl+\007blelrl-\003blr\004"
4160
    "blrl\003blt\004blt+\004blt-\004blta\005blta+\005blta-\006bltctr\007bltc"
4161
    "tr+\007bltctr-\007bltctrl\010bltctrl+\010bltctrl-\004bltl\005bltl+\005b"
4162
    "ltl-\005bltla\006bltla+\006bltla-\005bltlr\006bltlr+\006bltlr-\006bltlr"
4163
    "l\007bltlrl+\007bltlrl-\003bne\004bne+\004bne-\004bnea\005bnea+\005bnea"
4164
    "-\006bnectr\007bnectr+\007bnectr-\007bnectrl\010bnectrl+\010bnectrl-\004"
4165
    "bnel\005bnel+\005bnel-\005bnela\006bnela+\006bnela-\005bnelr\006bnelr+\006"
4166
    "bnelr-\006bnelrl\007bnelrl+\007bnelrl-\003bng\004bng+\004bng-\004bnga\005"
4167
    "bnga+\005bnga-\006bngctr\007bngctr+\007bngctr-\007bngctrl\010bngctrl+\010"
4168
    "bngctrl-\004bngl\005bngl+\005bngl-\005bngla\006bngla+\006bngla-\005bngl"
4169
    "r\006bnglr+\006bnglr-\006bnglrl\007bnglrl+\007bnglrl-\003bnl\004bnl+\004"
4170
    "bnl-\004bnla\005bnla+\005bnla-\006bnlctr\007bnlctr+\007bnlctr-\007bnlct"
4171
    "rl\010bnlctrl+\010bnlctrl-\004bnll\005bnll+\005bnll-\005bnlla\006bnlla+"
4172
    "\006bnlla-\005bnllr\006bnllr+\006bnllr-\006bnllrl\007bnllrl+\007bnllrl-"
4173
    "\003bns\004bns+\004bns-\004bnsa\005bnsa+\005bnsa-\006bnsctr\007bnsctr+\007"
4174
    "bnsctr-\007bnsctrl\010bnsctrl+\010bnsctrl-\004bnsl\005bnsl+\005bnsl-\005"
4175
    "bnsla\006bnsla+\006bnsla-\005bnslr\006bnslr+\006bnslr-\006bnslrl\007bns"
4176
    "lrl+\007bnslrl-\003bnu\004bnu+\004bnu-\004bnua\005bnua+\005bnua-\006bnu"
4177
    "ctr\007bnuctr+\007bnuctr-\007bnuctrl\010bnuctrl+\010bnuctrl-\004bnul\005"
4178
    "bnul+\005bnul-\005bnula\006bnula+\006bnula-\005bnulr\006bnulr+\006bnulr"
4179
    "-\006bnulrl\007bnulrl+\007bnulrl-\006bpermd\005brinc\003bso\004bso+\004"
4180
    "bso-\004bsoa\005bsoa+\005bsoa-\006bsoctr\007bsoctr+\007bsoctr-\007bsoct"
4181
    "rl\010bsoctrl+\010bsoctrl-\004bsol\005bsol+\005bsol-\005bsola\006bsola+"
4182
    "\006bsola-\005bsolr\006bsolr+\006bsolr-\006bsolrl\007bsolrl+\007bsolrl-"
4183
    "\002bt\003bt+\003bt-\003bta\004bta+\004bta-\005btctr\006btctr+\006btctr"
4184
    "-\006btctrl\007btctrl+\007btctrl-\003btl\004btl+\004btl-\004btla\005btl"
4185
    "a+\005btla-\004btlr\005btlr+\005btlr-\005btlrl\006btlrl+\006btlrl-\003b"
4186
    "un\004bun+\004bun-\004buna\005buna+\005buna-\006bunctr\007bunctr+\007bu"
4187
    "nctr-\007bunctrl\010bunctrl+\010bunctrl-\004bunl\005bunl+\005bunl-\005b"
4188
    "unla\006bunla+\006bunla-\005bunlr\006bunlr+\006bunlr-\006bunlrl\007bunl"
4189
    "rl+\007bunlrl-\007clrbhrb\006clrldi\010clrlsldi\010clrlslwi\006clrlwi\006"
4190
    "clrrdi\006clrrwi\003cmp\004cmpb\004cmpd\005cmpdi\006cmpeqb\004cmpi\004c"
4191
    "mpl\005cmpld\006cmpldi\005cmpli\005cmplw\006cmplwi\005cmprb\004cmpw\005"
4192
    "cmpwi\006cntlzd\006cntlzw\006cnttzd\006cnttzw\004copy\ncopy_first\010cp"
4193
    "_abort\005crand\006crandc\005crclr\005creqv\006crmove\006crnand\005crno"
4194
    "r\005crnot\004cror\005crorc\005crset\005crxor\004darn\004dcba\004dcbf\006"
4195
    "dcbfep\005dcbfl\006dcbflp\004dcbi\005dcbst\007dcbstep\004dcbt\006dcbtct"
4196
    "\006dcbtds\006dcbtep\006dcbtst\010dcbtstct\010dcbtstds\010dcbtstep\007d"
4197
    "cbtstt\005dcbtt\004dcbz\006dcbzep\005dcbzl\007dcbzlep\005dccci\003dci\004"
4198
    "divd\005divde\006divdeu\005divdu\004divw\005divwe\006divweu\005divwu\003"
4199
    "dss\006dssall\003dst\005dstst\006dststt\004dstt\006efdabs\006efdadd\006"
4200
    "efdcfs\007efdcfsf\007efdcfsi\010efdcfsid\007efdcfuf\007efdcfui\010efdcf"
4201
    "uid\010efdcmpeq\010efdcmpgt\010efdcmplt\007efdctsf\007efdctsi\tefdctsid"
4202
    "z\010efdctsiz\007efdctuf\007efdctui\tefdctuidz\010efdctuiz\006efddiv\006"
4203
    "efdmul\007efdnabs\006efdneg\006efdsub\010efdtsteq\010efdtstgt\010efdtst"
4204
    "lt\006efsabs\006efsadd\006efscfd\007efscfsf\007efscfsi\007efscfuf\007ef"
4205
    "scfui\010efscmpeq\010efscmpgt\010efscmplt\007efsctsf\007efsctsi\010efsc"
4206
    "tsiz\007efsctuf\007efsctui\010efsctuiz\006efsdiv\006efsmul\007efsnabs\006"
4207
    "efsneg\006efssub\010efststeq\010efststgt\010efststlt\005eieio\003eqv\005"
4208
    "evabs\007evaddiw\013evaddsmiaaw\013evaddssiaaw\013evaddumiaaw\013evaddu"
4209
    "siaaw\006evaddw\005evand\006evandc\007evcmpeq\010evcmpgts\010evcmpgtu\010"
4210
    "evcmplts\010evcmpltu\010evcntlsw\010evcntlzw\007evdivws\007evdivwu\005e"
4211
    "veqv\007evextsb\007evextsh\007evfsabs\007evfsadd\010evfscfsf\010evfscfs"
4212
    "i\010evfscfuf\010evfscfui\tevfscmpeq\tevfscmpgt\tevfscmplt\010evfsctsf\010"
4213
    "evfsctsi\tevfsctsiz\010evfsctui\007evfsdiv\007evfsmul\010evfsnabs\007ev"
4214
    "fsneg\007evfssub\tevfststeq\tevfststgt\tevfststlt\005evldd\006evlddx\005"
4215
    "evldh\006evldhx\005evldw\006evldwx\013evlhhesplat\014evlhhesplatx\014ev"
4216
    "lhhossplat\015evlhhossplatx\014evlhhousplat\015evlhhousplatx\006evlwhe\007"
4217
    "evlwhex\007evlwhos\010evlwhosx\007evlwhou\010evlwhoux\nevlwhsplat\013ev"
4218
    "lwhsplatx\nevlwwsplat\013evlwwsplatx\tevmergehi\013evmergehilo\tevmerge"
4219
    "lo\013evmergelohi\013evmhegsmfaa\013evmhegsmfan\013evmhegsmiaa\013evmhe"
4220
    "gsmian\013evmhegumiaa\013evmhegumian\010evmhesmf\tevmhesmfa\013evmhesmf"
4221
    "aaw\013evmhesmfanw\010evmhesmi\tevmhesmia\013evmhesmiaaw\013evmhesmianw"
4222
    "\010evmhessf\tevmhessfa\013evmhessfaaw\013evmhessfanw\013evmhessiaaw\013"
4223
    "evmhessianw\010evmheumi\tevmheumia\013evmheumiaaw\013evmheumianw\013evm"
4224
    "heusiaaw\013evmheusianw\013evmhogsmfaa\013evmhogsmfan\013evmhogsmiaa\013"
4225
    "evmhogsmian\013evmhogumiaa\013evmhogumian\010evmhosmf\tevmhosmfa\013evm"
4226
    "hosmfaaw\013evmhosmfanw\010evmhosmi\tevmhosmia\013evmhosmiaaw\013evmhos"
4227
    "mianw\010evmhossf\tevmhossfa\013evmhossfaaw\013evmhossfanw\013evmhossia"
4228
    "aw\013evmhossianw\010evmhoumi\tevmhoumia\013evmhoumiaaw\013evmhoumianw\013"
4229
    "evmhousiaaw\013evmhousianw\005evmra\010evmwhsmf\tevmwhsmfa\010evmwhsmi\t"
4230
    "evmwhsmia\010evmwhssf\tevmwhssfa\010evmwhumi\tevmwhumia\013evmwlsmiaaw\013"
4231
    "evmwlsmianw\013evmwlssiaaw\013evmwlssianw\010evmwlumi\tevmwlumia\013evm"
4232
    "wlumiaaw\013evmwlumianw\013evmwlusiaaw\013evmwlusianw\007evmwsmf\010evm"
4233
    "wsmfa\tevmwsmfaa\tevmwsmfan\007evmwsmi\010evmwsmia\tevmwsmiaa\tevmwsmia"
4234
    "n\007evmwssf\010evmwssfa\tevmwssfaa\tevmwssfan\007evmwumi\010evmwumia\t"
4235
    "evmwumiaa\tevmwumian\006evnand\005evneg\005evnor\004evor\005evorc\005ev"
4236
    "rlw\006evrlwi\006evrndw\005evsel\005evslw\006evslwi\tevsplatfi\010evspl"
4237
    "ati\007evsrwis\007evsrwiu\006evsrws\006evsrwu\006evstdd\007evstddx\006e"
4238
    "vstdh\007evstdhx\006evstdw\007evstdwx\007evstwhe\010evstwhex\007evstwho"
4239
    "\010evstwhox\007evstwwe\010evstwwex\007evstwwo\010evstwwox\014evsubfsmi"
4240
    "aaw\014evsubfssiaaw\014evsubfumiaaw\014evsubfusiaaw\007evsubfw\010evsub"
4241
    "ifw\005evxor\006extldi\006extlwi\006extrdi\006extrwi\005extsb\005extsh\005"
4242
    "extsw\010extswsli\004fabs\004fadd\005fadds\005fcfid\006fcfids\006fcfidu"
4243
    "\007fcfidus\005fcmpu\006fcpsgn\005fctid\006fctidu\007fctiduz\006fctidz\005"
4244
    "fctiw\006fctiwu\007fctiwuz\006fctiwz\004fdiv\005fdivs\005fmadd\006fmadd"
4245
    "s\003fmr\005fmsub\006fmsubs\004fmul\005fmuls\005fnabs\004fneg\006fnmadd"
4246
    "\007fnmadds\006fnmsub\007fnmsubs\003fre\004fres\004frim\004frin\004frip"
4247
    "\004friz\004frsp\007frsqrte\010frsqrtes\004fsel\005fsqrt\006fsqrts\004f"
4248
    "sub\005fsubs\005ftdiv\006ftsqrt\005hrfid\004icbi\006icbiep\005icblc\005"
4249
    "icblq\004icbt\006icbtls\005iccci\003ici\006inslwi\006insrdi\006insrwi\004"
4250
    "isel\005isync\002la\005lbarx\005lbepx\003lbz\006lbzcix\004lbzu\005lbzux"
4251
    "\004lbzx\002ld\005ldarx\004ldat\005ldbrx\005ldcix\004ldmx\003ldu\004ldu"
4252
    "x\003ldx\003lfd\006lfdepx\004lfdu\005lfdux\004lfdx\006lfiwax\006lfiwzx\003"
4253
    "lfs\004lfsu\005lfsux\004lfsx\003lha\005lharx\004lhau\005lhaux\004lhax\005"
4254
    "lhbrx\005lhepx\003lhz\006lhzcix\004lhzu\005lhzux\004lhzx\002li\003lis\003"
4255
    "lmw\004lnia\004lswi\005lvebx\005lvehx\005lvewx\004lvsl\004lvsr\003lvx\004"
4256
    "lvxl\003lwa\005lwarx\004lwat\005lwaux\004lwax\005lwbrx\005lwepx\006lwsy"
4257
    "nc\003lwz\006lwzcix\004lwzu\005lwzux\004lwzx\004lxsd\005lxsdx\007lxsibz"
4258
    "x\007lxsihzx\007lxsiwax\007lxsiwzx\005lxssp\006lxsspx\003lxv\007lxvb16x"
4259
    "\006lxvd2x\006lxvdsx\006lxvh8x\004lxvl\005lxvll\006lxvw4x\006lxvwsx\004"
4260
    "lxvx\006maddhd\007maddhdu\006maddld\004mbar\004mcrf\005mcrfs\006mcrxrx\005"
4261
    "mfamr\005mfasr\007mfbhrbe\005mfbr0\005mfbr1\005mfbr2\005mfbr3\005mfbr4\005"
4262
    "mfbr5\005mfbr6\005mfbr7\006mfcfar\004mfcr\005mfctr\005mfdar\007mfdbatl\007"
4263
    "mfdbatu\006mfdccr\005mfdcr\006mfdear\005mfdec\006mfdscr\007mfdsisr\005m"
4264
    "fesr\006mffprd\004mffs\010mffscdrn\tmffscdrni\006mffsce\007mffscrn\010m"
4265
    "ffscrni\005mffsl\007mfibatl\007mfibatu\006mficcr\004mflr\005mfmsr\006mf"
4266
    "ocrf\005mfpid\005mfpmr\005mfpvr\006mfrtcl\006mfrtcu\006mfsdr1\tmfspefsc"
4267
    "r\005mfspr\006mfsprg\007mfsprg0\007mfsprg1\007mfsprg2\007mfsprg3\007mfs"
4268
    "prg4\007mfsprg5\007mfsprg6\007mfsprg7\004mfsr\006mfsrin\006mfsrr0\006mf"
4269
    "srr1\006mfsrr2\006mfsrr3\004mftb\006mftbhi\005mftbl\006mftblo\005mftbu\005"
4270
    "mftcr\005mfvrd\010mfvrsave\006mfvscr\006mfvsrd\007mfvsrld\007mfvsrwz\005"
4271
    "mfxer\005modsd\005modsw\005modud\005moduw\002mr\007msgsync\005msync\005"
4272
    "mtamr\005mtasr\005mtbr0\005mtbr1\005mtbr2\005mtbr3\005mtbr4\005mtbr5\005"
4273
    "mtbr6\005mtbr7\006mtcfar\004mtcr\005mtcrf\005mtctr\005mtdar\007mtdbatl\007"
4274
    "mtdbatu\006mtdccr\005mtdcr\006mtdear\005mtdec\006mtdscr\007mtdsisr\005m"
4275
    "tesr\006mtfsb0\006mtfsb1\005mtfsf\006mtfsfi\007mtibatl\007mtibatu\006mt"
4276
    "iccr\004mtlr\005mtmsr\006mtmsrd\006mtocrf\005mtpid\005mtpmr\006mtsdr1\t"
4277
    "mtspefscr\005mtspr\006mtsprg\007mtsprg0\007mtsprg1\007mtsprg2\007mtsprg"
4278
    "3\007mtsprg4\007mtsprg5\007mtsprg6\007mtsprg7\004mtsr\006mtsrin\006mtsr"
4279
    "r0\006mtsrr1\006mtsrr2\006mtsrr3\006mttbhi\005mttbl\006mttblo\005mttbu\005"
4280
    "mttcr\010mtvrsave\006mtvscr\006mtvsrd\007mtvsrdd\007mtvsrwa\007mtvsrws\007"
4281
    "mtvsrwz\005mtxer\005mulhd\006mulhdu\005mulhw\006mulhwu\005mulld\005mull"
4282
    "i\005mullw\004nand\003nap\003neg\003nop\003nor\003not\002or\003orc\003o"
4283
    "ri\004oris\005paste\npaste_last\007popcntb\007popcntd\007popcntw\007pte"
4284
    "sync\010qvaligni\tqvesplati\006qvfabs\006qvfadd\007qvfadds\006qvfand\007"
4285
    "qvfandc\007qvfcfid\010qvfcfids\010qvfcfidu\tqvfcfidus\006qvfclr\010qvfc"
4286
    "mpeq\010qvfcmpgt\010qvfcmplt\010qvfcpsgn\007qvfctfb\007qvfctid\010qvfct"
4287
    "idu\tqvfctiduz\010qvfctidz\007qvfctiw\010qvfctiwu\tqvfctiwuz\010qvfctiw"
4288
    "z\006qvfequ\nqvflogical\007qvfmadd\010qvfmadds\005qvfmr\007qvfmsub\010q"
4289
    "vfmsubs\006qvfmul\007qvfmuls\007qvfnabs\007qvfnand\006qvfneg\010qvfnmad"
4290
    "d\tqvfnmadds\010qvfnmsub\tqvfnmsubs\006qvfnor\006qvfnot\005qvfor\006qvf"
4291
    "orc\007qvfperm\005qvfre\006qvfres\006qvfrim\006qvfrin\006qvfrip\006qvfr"
4292
    "iz\006qvfrsp\tqvfrsqrte\nqvfrsqrtes\006qvfsel\006qvfset\006qvfsub\007qv"
4293
    "fsubs\tqvftstnan\010qvfxmadd\tqvfxmadds\007qvfxmul\010qvfxmuls\006qvfxo"
4294
    "r\014qvfxxcpnmadd\015qvfxxcpnmadds\tqvfxxmadd\nqvfxxmadds\013qvfxxnpmad"
4295
    "d\014qvfxxnpmadds\006qvgpci\010qvlfcdux\tqvlfcduxa\007qvlfcdx\010qvlfcd"
4296
    "xa\010qvlfcsux\tqvlfcsuxa\007qvlfcsx\010qvlfcsxa\007qvlfdux\010qvlfduxa"
4297
    "\006qvlfdx\007qvlfdxa\010qvlfiwax\tqvlfiwaxa\010qvlfiwzx\tqvlfiwzxa\007"
4298
    "qvlfsux\010qvlfsuxa\006qvlfsx\007qvlfsxa\010qvlpcldx\010qvlpclsx\010qvl"
4299
    "pcrdx\010qvlpcrsx\tqvstfcdux\nqvstfcduxa\nqvstfcduxi\013qvstfcduxia\010"
4300
    "qvstfcdx\tqvstfcdxa\tqvstfcdxi\nqvstfcdxia\tqvstfcsux\nqvstfcsuxa\nqvst"
4301
    "fcsuxi\013qvstfcsuxia\010qvstfcsx\tqvstfcsxa\tqvstfcsxi\nqvstfcsxia\010"
4302
    "qvstfdux\tqvstfduxa\tqvstfduxi\nqvstfduxia\007qvstfdx\010qvstfdxa\010qv"
4303
    "stfdxi\tqvstfdxia\010qvstfiwx\tqvstfiwxa\010qvstfsux\tqvstfsuxa\tqvstfs"
4304
    "uxi\nqvstfsuxia\007qvstfsx\010qvstfsxa\010qvstfsxi\tqvstfsxia\004rfci\004"
4305
    "rfdi\005rfebb\003rfi\004rfid\005rfmci\005rldcl\005rldcr\005rldic\006rld"
4306
    "icl\006rldicr\006rldimi\006rlwimi\006rlwinm\005rlwnm\005rotld\006rotldi"
4307
    "\005rotlw\006rotlwi\006rotrdi\006rotrwi\002sc\004setb\005slbia\005slbie"
4308
    "\006slbieg\007slbmfee\007slbmfev\006slbmte\007slbsync\003sld\004sldi\003"
4309
    "slw\004slwi\004srad\005sradi\004sraw\005srawi\003srd\004srdi\003srw\004"
4310
    "srwi\003stb\006stbcix\005stbcx\006stbepx\004stbu\005stbux\004stbx\003st"
4311
    "d\005stdat\006stdbrx\006stdcix\005stdcx\004stdu\005stdux\004stdx\004stf"
4312
    "d\007stfdepx\005stfdu\006stfdux\005stfdx\006stfiwx\004stfs\005stfsu\006"
4313
    "stfsux\005stfsx\003sth\006sthbrx\006sthcix\005sthcx\006sthepx\004sthu\005"
4314
    "sthux\004sthx\004stmw\004stop\005stswi\006stvebx\006stvehx\006stvewx\004"
4315
    "stvx\005stvxl\003stw\005stwat\006stwbrx\006stwcix\005stwcx\006stwepx\004"
4316
    "stwu\005stwux\004stwx\005stxsd\006stxsdx\007stxsibx\007stxsihx\007stxsi"
4317
    "wx\006stxssp\007stxsspx\004stxv\010stxvb16x\007stxvd2x\007stxvh8x\005st"
4318
    "xvl\006stxvll\007stxvw4x\005stxvx\003sub\004subc\004subf\005subfc\005su"
4319
    "bfe\006subfic\006subfme\006subfze\004subi\005subic\005subis\007subpcis\004"
4320
    "sync\006tabort\010tabortdc\ttabortdci\010tabortwc\ttabortwci\006tbegin\006"
4321
    "tcheck\002td\004tdeq\005tdeqi\004tdge\005tdgei\004tdgt\005tdgti\003tdi\004"
4322
    "tdle\005tdlei\005tdlge\006tdlgei\005tdlgt\006tdlgti\005tdlle\006tdllei\005"
4323
    "tdllt\006tdllti\005tdlng\006tdlngi\005tdlnl\006tdlnli\004tdlt\005tdlti\004"
4324
    "tdne\005tdnei\004tdng\005tdngi\004tdnl\005tdnli\003tdu\004tdui\004tend\005"
4325
    "tlbia\005tlbie\006tlbiel\007tlbivax\005tlbld\005tlbli\005tlbre\007tlbre"
4326
    "hi\007tlbrelo\005tlbsx\007tlbsync\005tlbwe\007tlbwehi\007tlbwelo\004tra"
4327
    "p\010trechkpt\010treclaim\003tsr\002tw\004tweq\005tweqi\004twge\005twge"
4328
    "i\004twgt\005twgti\003twi\004twle\005twlei\005twlge\006twlgei\005twlgt\006"
4329
    "twlgti\005twlle\006twllei\005twllt\006twllti\005twlng\006twlngi\005twln"
4330
    "l\006twlnli\004twlt\005twlti\004twne\005twnei\004twng\005twngi\004twnl\005"
4331
    "twnli\003twu\004twui\007vabsdub\007vabsduh\007vabsduw\007vaddcuq\007vad"
4332
    "dcuw\010vaddecuq\010vaddeuqm\006vaddfp\007vaddsbs\007vaddshs\007vaddsws"
4333
    "\007vaddubm\007vaddubs\007vaddudm\007vadduhm\007vadduhs\007vadduqm\007v"
4334
    "adduwm\007vadduws\004vand\005vandc\006vavgsb\006vavgsh\006vavgsw\006vav"
4335
    "gub\006vavguh\006vavguw\007vbpermd\007vbpermq\005vcfsx\005vcfux\007vcip"
4336
    "her\013vcipherlast\005vclzb\005vclzd\005vclzh\010vclzlsbb\005vclzw\007v"
4337
    "cmpbfp\010vcmpeqfp\010vcmpequb\010vcmpequd\010vcmpequh\010vcmpequw\010v"
4338
    "cmpgefp\010vcmpgtfp\010vcmpgtsb\010vcmpgtsd\010vcmpgtsh\010vcmpgtsw\010"
4339
    "vcmpgtub\010vcmpgtud\010vcmpgtuh\010vcmpgtuw\007vcmpneb\007vcmpneh\007v"
4340
    "cmpnew\010vcmpnezb\010vcmpnezh\010vcmpnezw\006vctsxs\006vctuxs\005vctzb"
4341
    "\005vctzd\005vctzh\010vctzlsbb\005vctzw\004veqv\010vexptefp\tvextractd\n"
4342
    "vextractub\nvextractuh\nvextractuw\010vextsb2d\010vextsb2w\010vextsh2d\010"
4343
    "vextsh2w\010vextsw2d\010vextublx\010vextubrx\010vextuhlx\010vextuhrx\010"
4344
    "vextuwlx\010vextuwrx\005vgbbd\010vinsertb\010vinsertd\010vinserth\010vi"
4345
    "nsertw\007vlogefp\007vmaddfp\006vmaxfp\006vmaxsb\006vmaxsd\006vmaxsh\006"
4346
    "vmaxsw\006vmaxub\006vmaxud\006vmaxuh\006vmaxuw\tvmhaddshs\nvmhraddshs\006"
4347
    "vminfp\006vminsb\006vminsd\006vminsh\006vminsw\006vminub\006vminud\006v"
4348
    "minuh\006vminuw\tvmladduhm\003vmr\006vmrgew\006vmrghb\006vmrghh\006vmrg"
4349
    "hw\006vmrglb\006vmrglh\006vmrglw\006vmrgow\010vmsummbm\010vmsumshm\010v"
4350
    "msumshs\010vmsumubm\010vmsumuhm\010vmsumuhs\tvmul10cuq\nvmul10ecuq\tvmu"
4351
    "l10euq\010vmul10uq\007vmulesb\007vmulesh\007vmulesw\007vmuleub\007vmule"
4352
    "uh\007vmuleuw\007vmulosb\007vmulosh\007vmulosw\007vmuloub\007vmulouh\007"
4353
    "vmulouw\007vmuluwm\005vnand\010vncipher\014vncipherlast\005vnegd\005vne"
4354
    "gw\010vnmsubfp\004vnor\004vnot\003vor\004vorc\005vperm\006vpermr\010vpe"
4355
    "rmxor\005vpkpx\007vpksdss\007vpksdus\007vpkshss\007vpkshus\007vpkswss\007"
4356
    "vpkswus\007vpkudum\007vpkudus\007vpkuhum\007vpkuhus\007vpkuwum\007vpkuw"
4357
    "us\007vpmsumb\007vpmsumd\007vpmsumh\007vpmsumw\010vpopcntb\010vpopcntd\010"
4358
    "vpopcnth\010vpopcntw\007vprtybd\007vprtybq\007vprtybw\005vrefp\005vrfim"
4359
    "\005vrfin\005vrfip\005vrfiz\004vrlb\004vrld\006vrldmi\006vrldnm\004vrlh"
4360
    "\004vrlw\006vrlwmi\006vrlwnm\tvrsqrtefp\005vsbox\004vsel\nvshasigmad\nv"
4361
    "shasigmaw\003vsl\004vslb\004vsld\006vsldoi\004vslh\004vslo\004vslv\004v"
4362
    "slw\006vspltb\006vsplth\010vspltisb\010vspltish\010vspltisw\006vspltw\003"
4363
    "vsr\005vsrab\005vsrad\005vsrah\005vsraw\004vsrb\004vsrd\004vsrh\004vsro"
4364
    "\004vsrv\004vsrw\007vsubcuq\007vsubcuw\010vsubecuq\010vsubeuqm\006vsubf"
4365
    "p\007vsubsbs\007vsubshs\007vsubsws\007vsububm\007vsububs\007vsubudm\007"
4366
    "vsubuhm\007vsubuhs\007vsubuqm\007vsubuwm\007vsubuws\010vsum2sws\010vsum"
4367
    "4sbs\010vsum4shs\010vsum4ubs\007vsumsws\007vupkhpx\007vupkhsb\007vupkhs"
4368
    "h\007vupkhsw\007vupklpx\007vupklsb\007vupklsh\007vupklsw\004vxor\004wai"
4369
    "t\010waitimpl\007waitrsv\005wrtee\006wrteei\004xnop\003xor\004xori\005x"
4370
    "oris\007xsabsdp\007xsabsqp\007xsadddp\007xsaddqp\010xsaddqpo\007xsaddsp"
4371
    "\txscmpeqdp\nxscmpexpdp\nxscmpexpqp\txscmpgedp\txscmpgtdp\010xscmpodp\010"
4372
    "xscmpoqp\010xscmpudp\010xscmpuqp\txscpsgndp\txscpsgnqp\010xscvdphp\010x"
4373
    "scvdpqp\010xscvdpsp\txscvdpspn\nxscvdpsxds\nxscvdpsxws\nxscvdpuxds\nxsc"
4374
    "vdpuxws\010xscvhpdp\010xscvqpdp\txscvqpdpo\txscvqpsdz\txscvqpswz\txscvq"
4375
    "pudz\txscvqpuwz\010xscvsdqp\010xscvspdp\txscvspdpn\txscvsxddp\txscvsxds"
4376
    "p\010xscvudqp\txscvuxddp\txscvuxdsp\007xsdivdp\007xsdivqp\010xsdivqpo\007"
4377
    "xsdivsp\010xsiexpdp\010xsiexpqp\txsmaddadp\txsmaddasp\txsmaddmdp\txsmad"
4378
    "dmsp\010xsmaddqp\txsmaddqpo\010xsmaxcdp\007xsmaxdp\010xsmaxjdp\010xsmin"
4379
    "cdp\007xsmindp\010xsminjdp\txsmsubadp\txsmsubasp\txsmsubmdp\txsmsubmsp\010"
4380
    "xsmsubqp\txsmsubqpo\007xsmuldp\007xsmulqp\010xsmulqpo\007xsmulsp\010xsn"
4381
    "absdp\010xsnabsqp\007xsnegdp\007xsnegqp\nxsnmaddadp\nxsnmaddasp\nxsnmad"
4382
    "dmdp\nxsnmaddmsp\txsnmaddqp\nxsnmaddqpo\nxsnmsubadp\nxsnmsubasp\nxsnmsu"
4383
    "bmdp\nxsnmsubmsp\txsnmsubqp\nxsnmsubqpo\006xsrdpi\007xsrdpic\007xsrdpim"
4384
    "\007xsrdpip\007xsrdpiz\006xsredp\006xsresp\006xsrqpi\007xsrqpix\007xsrq"
4385
    "pxp\005xsrsp\nxsrsqrtedp\nxsrsqrtesp\010xssqrtdp\010xssqrtqp\txssqrtqpo"
4386
    "\010xssqrtsp\007xssubdp\007xssubqp\010xssubqpo\007xssubsp\010xstdivdp\t"
4387
    "xstsqrtdp\txststdcdp\txststdcqp\txststdcsp\010xsxexpdp\010xsxexpqp\010x"
4388
    "sxsigdp\010xsxsigqp\007xvabsdp\007xvabssp\007xvadddp\007xvaddsp\txvcmpe"
4389
    "qdp\txvcmpeqsp\txvcmpgedp\txvcmpgesp\txvcmpgtdp\txvcmpgtsp\txvcpsgndp\t"
4390
    "xvcpsgnsp\010xvcvdpsp\nxvcvdpsxds\nxvcvdpsxws\nxvcvdpuxds\nxvcvdpuxws\010"
4391
    "xvcvhpsp\010xvcvspdp\010xvcvsphp\nxvcvspsxds\nxvcvspsxws\nxvcvspuxds\nx"
4392
    "vcvspuxws\txvcvsxddp\txvcvsxdsp\txvcvsxwdp\txvcvsxwsp\txvcvuxddp\txvcvu"
4393
    "xdsp\txvcvuxwdp\txvcvuxwsp\007xvdivdp\007xvdivsp\010xviexpdp\010xviexps"
4394
    "p\txvmaddadp\txvmaddasp\txvmaddmdp\txvmaddmsp\007xvmaxdp\007xvmaxsp\007"
4395
    "xvmindp\007xvminsp\007xvmovdp\007xvmovsp\txvmsubadp\txvmsubasp\txvmsubm"
4396
    "dp\txvmsubmsp\007xvmuldp\007xvmulsp\010xvnabsdp\010xvnabssp\007xvnegdp\007"
4397
    "xvnegsp\nxvnmaddadp\nxvnmaddasp\nxvnmaddmdp\nxvnmaddmsp\nxvnmsubadp\nxv"
4398
    "nmsubasp\nxvnmsubmdp\nxvnmsubmsp\006xvrdpi\007xvrdpic\007xvrdpim\007xvr"
4399
    "dpip\007xvrdpiz\006xvredp\006xvresp\006xvrspi\007xvrspic\007xvrspim\007"
4400
    "xvrspip\007xvrspiz\nxvrsqrtedp\nxvrsqrtesp\010xvsqrtdp\010xvsqrtsp\007x"
4401
    "vsubdp\007xvsubsp\010xvtdivdp\010xvtdivsp\txvtsqrtdp\txvtsqrtsp\txvtstd"
4402
    "cdp\txvtstdcsp\010xvxexpdp\010xvxexpsp\010xvxsigdp\010xvxsigsp\005xxbrd"
4403
    "\005xxbrh\005xxbrq\005xxbrw\013xxextractuw\txxinsertw\006xxland\007xxla"
4404
    "ndc\006xxleqv\007xxlnand\006xxlnor\005xxlor\006xxlorc\006xxlxor\007xxmr"
4405
    "ghd\007xxmrghw\007xxmrgld\007xxmrglw\006xxperm\010xxpermdi\007xxpermr\005"
4406
    "xxsel\007xxsldwi\007xxspltd\010xxspltib\007xxspltw\007xxswapd";
4407
4408
namespace {
4409
  struct MatchEntry {
4410
    uint16_t Mnemonic;
4411
    uint16_t Opcode;
4412
    uint16_t ConvertFn;
4413
    uint8_t RequiredFeatures;
4414
    uint8_t Classes[6];
4415
146k
    StringRef getMnemonic() const {
4416
146k
      return StringRef(MnemonicTable + Mnemonic + 1,
4417
146k
                       MnemonicTable[Mnemonic]);
4418
146k
    }
4419
  };
4420
4421
  // Predicate for searching for an opcode.
4422
  struct LessOpcode {
4423
82.1k
    bool operator()(const MatchEntry &LHS, StringRef RHS) {
4424
82.1k
      return LHS.getMnemonic() < RHS;
4425
82.1k
    }
4426
54.6k
    bool operator()(StringRef LHS, const MatchEntry &RHS) {
4427
54.6k
      return LHS < RHS.getMnemonic();
4428
54.6k
    }
4429
0
    bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
4430
0
      return LHS.getMnemonic() < RHS.getMnemonic();
4431
0
    }
4432
  };
4433
} // end anonymous namespace.
4434
4435
static const MatchEntry MatchTable0[] = {
4436
  { 0 /* add */, PPC::ADD8TLS_, Convert__RegG8RC1_0__RegG8RC1_1__TLSReg1_2, 0, { MCK_RegG8RC, MCK_RegG8RC, MCK_TLSReg }, },
4437
  { 0 /* add */, PPC::ADD4, Convert__RegGPRC1_0__RegGPRC1_1__RegGPRC1_2, 0, { MCK_RegGPRC, MCK_RegGPRC, MCK_RegGPRC }, },
4438
  { 0 /* add */, PPC::ADD4o, Convert__RegGPRC1_1__RegGPRC1_2__RegGPRC1_3, 0, { MCK__DOT_, MCK_RegGPRC, MCK_RegGPRC, MCK_RegGPRC }, },
4439
  { 4 /* addc */, PPC::ADDC, Convert__RegGPRC1_0__RegGPRC1_1__RegGPRC1_2, 0, { MCK_RegGPRC, MCK_RegGPRC, MCK_RegGPRC }, },
4440
  { 4 /* addc */, PPC::ADDCo, Convert__RegGPRC1_1__RegGPRC1_2__RegGPRC1_3, 0, { MCK__DOT_, MCK_RegGPRC, MCK_RegGPRC, MCK_RegGPRC }, },
4441
  { 9 /* adde */, PPC::ADDE, Convert__RegGPRC1_0__RegGPRC1_1__RegGPRC1_2, 0, { MCK_RegGPRC, MCK_RegGPRC, MCK_RegGPRC }, },
4442
  { 9 /* adde */, PPC::ADDEo, Convert__RegGPRC1_1__RegGPRC1_2__RegGPRC1_3, 0, { MCK__DOT_, MCK_RegGPRC, MCK_RegGPRC, MCK_RegGPRC }, },
4443
  { 14 /* addi */, PPC::ADDI, Convert__RegGPRC1_0__RegGPRCNoR01_1__S16Imm1_2, 0, { MCK_RegGPRC, MCK_RegGPRCNoR0, MCK_S16Imm }, },
4444
  { 19 /* addic */, PPC::ADDIC, Convert__RegGPRC1_0__RegGPRC1_1__S16Imm1_2, 0, { MCK_RegGPRC, MCK_RegGPRC, MCK_S16Imm }, },
4445
  { 19 /* addic */, PPC::ADDICo, Convert__RegGPRC1_1__RegGPRC1_2__S16Imm1_3, 0, { MCK__DOT_, MCK_RegGPRC, MCK_RegGPRC, MCK_S16Imm }, },
4446
  { 25 /* addis */, PPC::ADDIS, Convert__RegGPRC1_0__RegGPRCNoR01_1__S17Imm1_2, 0, { MCK_RegGPRC, MCK_RegGPRCNoR0, MCK_S17Imm }, },
4447
  { 31 /* addme */, PPC::ADDME, Convert__RegGPRC1_0__RegGPRC1_1, 0, { MCK_RegGPRC, MCK_RegGPRC }, },
4448
  { 31 /* addme */, PPC::ADDMEo, Convert__RegGPRC1_1__RegGPRC1_2, 0, { MCK__DOT_, MCK_RegGPRC, MCK_RegGPRC }, },
4449
  { 37 /* addpcis */, PPC::ADDPCIS, Convert__RegG8RC1_0__Imm1_1, 0, { MCK_RegG8RC, MCK_Imm }, },
4450
  { 45 /* addze */, PPC::ADDZE, Convert__RegGPRC1_0__RegGPRC1_1, 0, { MCK_RegGPRC, MCK_RegGPRC }, },
4451
  { 45 /* addze */, PPC::ADDZEo, Convert__RegGPRC1_1__RegGPRC1_2, 0, { MCK__DOT_, MCK_RegGPRC, MCK_RegGPRC }, },
4452
  { 51 /* and */, PPC::AND, Convert__RegGPRC1_0__RegGPRC1_1__RegGPRC1_2, 0, { MCK_RegGPRC, MCK_RegGPRC, MCK_RegGPRC }, },
4453
  { 51 /* and */, PPC::ANDo, Convert__RegGPRC1_1__RegGPRC1_2__RegGPRC1_3, 0, { MCK__DOT_, MCK_RegGPRC, MCK_RegGPRC, MCK_RegGPRC }, },
4454
  { 55 /* andc */, PPC::ANDC, Convert__RegGPRC1_0__RegGPRC1_1__RegGPRC1_2, 0, { MCK_RegGPRC, MCK_RegGPRC, MCK_RegGPRC }, },
4455
  { 55 /* andc */, PPC::ANDCo, Convert__RegGPRC1_1__RegGPRC1_2__RegGPRC1_3, 0, { MCK__DOT_, MCK_RegGPRC, MCK_RegGPRC, MCK_RegGPRC }, },
4456
  { 60 /* andi */, PPC::ANDIo, Convert__RegGPRC1_1__RegGPRC1_2__U16Imm1_3, 0, { MCK__DOT_, MCK_RegGPRC, MCK_RegGPRC, MCK_U16Imm }, },
4457
  { 65 /* andis */, PPC::ANDISo, Convert__RegGPRC1_1__RegGPRC1_2__U16Imm1_3, 0, { MCK__DOT_, MCK_RegGPRC, MCK_RegGPRC, MCK_U16Imm }, },
4458
  { 71 /* attn */, PPC::ATTN, Convert_NoOperands, 0, {  }, },
4459
  { 76 /* b */, PPC::B, Convert__DirectBr1_0, 0, { MCK_DirectBr }, },
4460
  { 78 /* ba */, PPC::BA, Convert__DirectBr1_0, 0, { MCK_DirectBr }, },
4461
  { 81 /* bc */, PPC::gBC, Convert__U5Imm1_0__RegCRBITRC1_1__CondBr1_2, 0, { MCK_U5Imm, MCK_RegCRBITRC, MCK_CondBr }, },
4462
  { 81 /* bc */, PPC::gBCat, Convert__U5Imm1_1__ATBitsAsHint1_0__RegCRBITRC1_2__CondBr1_3, 0, { MCK_ATBitsAsHint, MCK_U5Imm, MCK_RegCRBITRC, MCK_CondBr }, },
4463
  { 84 /* bc+ */, PPC::gBCat, Convert__U5Imm1_0__imm_95_3__RegCRBITRC1_1__CondBr1_2, 0, { MCK_U5Imm, MCK_RegCRBITRC, MCK_CondBr }, },
4464
  { 88 /* bc- */, PPC::gBCat, Convert__U5Imm1_0__imm_95_2__RegCRBITRC1_1__CondBr1_2, 0, { MCK_U5Imm, MCK_RegCRBITRC, MCK_CondBr }, },
4465
  { 92 /* bca */, PPC::gBCA, Convert__U5Imm1_0__RegCRBITRC1_1__CondBr1_2, 0, { MCK_U5Imm, MCK_RegCRBITRC, MCK_CondBr }, },
4466
  { 92 /* bca */, PPC::gBCAat, Convert__U5Imm1_1__ATBitsAsHint1_0__RegCRBITRC1_2__CondBr1_3, 0, { MCK_ATBitsAsHint, MCK_U5Imm, MCK_RegCRBITRC, MCK_CondBr }, },
4467
  { 96 /* bca+ */, PPC::gBCAat, Convert__U5Imm1_0__imm_95_3__RegCRBITRC1_1__CondBr1_2, 0, { MCK_U5Imm, MCK_RegCRBITRC, MCK_CondBr }, },
4468
  { 101 /* bca- */, PPC::gBCAat, Convert__U5Imm1_0__imm_95_2__RegCRBITRC1_1__CondBr1_2, 0, { MCK_U5Imm, MCK_RegCRBITRC, MCK_CondBr }, },
4469
  { 106 /* bcctr */, PPC::gBCCTR, Convert__U5Imm1_0__RegCRBITRC1_1__imm_95_0, 0, { MCK_U5Imm, MCK_RegCRBITRC }, },
4470
  { 106 /* bcctr */, PPC::gBCCTR, Convert__U5Imm1_0__RegCRBITRC1_1__Imm1_2, 0, { MCK_U5Imm, MCK_RegCRBITRC, MCK_Imm }, },
4471
  { 112 /* bcctrl */, PPC::gBCCTRL, Convert__U5Imm1_0__RegCRBITRC1_1__imm_95_0, 0, { MCK_U5Imm, MCK_RegCRBITRC }, },
4472
  { 112 /* bcctrl */, PPC::gBCCTRL, Convert__U5Imm1_0__RegCRBITRC1_1__Imm1_2, 0, { MCK_U5Imm, MCK_RegCRBITRC, MCK_Imm }, },
4473
  { 119 /* bcdcfn */, PPC::BCDCFNo, Convert__RegVRRC1_1__RegVRRC1_2__U1Imm1_3, 0, { MCK__DOT_, MCK_RegVRRC, MCK_RegVRRC, MCK_U1Imm }, },
4474
  { 126 /* bcdcfsq */, PPC::BCDCFSQo, Convert__RegVRRC1_1__RegVRRC1_2__U1Imm1_3, 0, { MCK__DOT_, MCK_RegVRRC, MCK_RegVRRC, MCK_U1Imm }, },
4475
  { 134 /* bcdcfz */, PPC::BCDCFZo, Convert__RegVRRC1_1__RegVRRC1_2__U1Imm1_3, 0, { MCK__DOT_, MCK_RegVRRC, MCK_RegVRRC, MCK_U1Imm }, },
4476
  { 141 /* bcdcpsgn */, PPC::BCDCPSGNo, Convert__RegVRRC1_1__RegVRRC1_2__RegVRRC1_3, 0, { MCK__DOT_, MCK_RegVRRC, MCK_RegVRRC, MCK_RegVRRC }, },
4477
  { 150 /* bcdctn */, PPC::BCDCTNo, Convert__RegVRRC1_1__RegVRRC1_2, 0, { MCK__DOT_, MCK_RegVRRC, MCK_RegVRRC }, },
4478
  { 157 /* bcdctsq */, PPC::BCDCTSQo, Convert__RegVRRC1_1__RegVRRC1_2, 0, { MCK__DOT_, MCK_RegVRRC, MCK_RegVRRC }, },
4479
  { 165 /* bcdctz */, PPC::BCDCTZo, Convert__RegVRRC1_1__RegVRRC1_2__U1Imm1_3, 0, { MCK__DOT_, MCK_RegVRRC, MCK_RegVRRC, MCK_U1Imm }, },
4480
  { 172 /* bcds */, PPC::BCDSo, Convert__RegVRRC1_1__RegVRRC1_2__RegVRRC1_3__U1Imm1_4, 0, { MCK__DOT_, MCK_RegVRRC, MCK_RegVRRC, MCK_RegVRRC, MCK_U1Imm }, },
4481
  { 177 /* bcdsetsgn */, PPC::BCDSETSGNo, Convert__RegVRRC1_1__RegVRRC1_2__U1Imm1_3, 0, { MCK__DOT_, MCK_RegVRRC, MCK_RegVRRC, MCK_U1Imm }, },
4482
  { 187 /* bcdsr */, PPC::BCDSRo, Convert__RegVRRC1_1__RegVRRC1_2__RegVRRC1_3__U1Imm1_4, 0, { MCK__DOT_, MCK_RegVRRC, MCK_RegVRRC, MCK_RegVRRC, MCK_U1Imm }, },
4483
  { 193 /* bcdtrunc */, PPC::BCDTRUNCo, Convert__RegVRRC1_1__RegVRRC1_2__RegVRRC1_3__U1Imm1_4, 0, { MCK__DOT_, MCK_RegVRRC, MCK_RegVRRC, MCK_RegVRRC, MCK_U1Imm }, },
4484
  { 202 /* bcdus */, PPC::BCDUSo, Convert__RegVRRC1_1__RegVRRC1_2__RegVRRC1_3, 0, { MCK__DOT_, MCK_RegVRRC, MCK_RegVRRC, MCK_RegVRRC }, },
4485
  { 208 /* bcdutrunc */, PPC::BCDUTRUNCo, Convert__RegVRRC1_1__RegVRRC1_2__RegVRRC1_3, 0, { MCK__DOT_, MCK_RegVRRC, MCK_RegVRRC, MCK_RegVRRC }, },
4486
  { 218 /* bcl */, PPC::gBCL, Convert__U5Imm1_0__RegCRBITRC1_1__CondBr1_2, 0, { MCK_U5Imm, MCK_RegCRBITRC, MCK_CondBr }, },
4487
  { 218 /* bcl */, PPC::gBCLat, Convert__U5Imm1_1__ATBitsAsHint1_0__RegCRBITRC1_2__CondBr1_3, 0, { MCK_ATBitsAsHint, MCK_U5Imm, MCK_RegCRBITRC, MCK_CondBr }, },
4488
  { 222 /* bcl+ */, PPC::gBCLat, Convert__U5Imm1_0__imm_95_3__RegCRBITRC1_1__CondBr1_2, 0, { MCK_U5Imm, MCK_RegCRBITRC, MCK_CondBr }, },
4489
  { 227 /* bcl- */, PPC::gBCLat, Convert__U5Imm1_0__imm_95_2__RegCRBITRC1_1__CondBr1_2, 0, { MCK_U5Imm, MCK_RegCRBITRC, MCK_CondBr }, },
4490
  { 232 /* bcla */, PPC::gBCLA, Convert__U5Imm1_0__RegCRBITRC1_1__CondBr1_2, 0, { MCK_U5Imm, MCK_RegCRBITRC, MCK_CondBr }, },
4491
  { 232 /* bcla */, PPC::gBCLAat, Convert__U5Imm1_1__ATBitsAsHint1_0__RegCRBITRC1_2__CondBr1_3, 0, { MCK_ATBitsAsHint, MCK_U5Imm, MCK_RegCRBITRC, MCK_CondBr }, },
4492
  { 237 /* bcla+ */, PPC::gBCLAat, Convert__U5Imm1_0__imm_95_3__RegCRBITRC1_1__CondBr1_2, 0, { MCK_U5Imm, MCK_RegCRBITRC, MCK_CondBr }, },
4493
  { 243 /* bcla- */, PPC::gBCLAat, Convert__U5Imm1_0__imm_95_2__RegCRBITRC1_1__CondBr1_2, 0, { MCK_U5Imm, MCK_RegCRBITRC, MCK_CondBr }, },
4494
  { 249 /* bclr */, PPC::gBCLR, Convert__U5Imm1_0__RegCRBITRC1_1__imm_95_0, 0, { MCK_U5Imm, MCK_RegCRBITRC }, },
4495
  { 249 /* bclr */, PPC::gBCLR, Convert__U5Imm1_0__RegCRBITRC1_1__Imm1_2, 0, { MCK_U5Imm, MCK_RegCRBITRC, MCK_Imm }, },
4496
  { 254 /* bclrl */, PPC::gBCLRL, Convert__U5Imm1_0__RegCRBITRC1_1__imm_95_0, 0, { MCK_U5Imm, MCK_RegCRBITRC }, },
4497
  { 254 /* bclrl */, PPC::gBCLRL, Convert__U5Imm1_0__RegCRBITRC1_1__Imm1_2, 0, { MCK_U5Imm, MCK_RegCRBITRC, MCK_Imm }, },
4498
  { 260 /* bctr */, PPC::BCTR, Convert_NoOperands, 0, {  }, },
4499
  { 265 /* bctrl */, PPC::BCTRL, Convert_NoOperands, 0, {  }, },
4500
  { 271 /* bdnz */, PPC::BDNZ, Convert__CondBr1_0, 0, { MCK_CondBr }, },
4501
  { 276 /* bdnz+ */, PPC::BDNZp, Convert__CondBr1_0, 0, { MCK_CondBr }, },
4502
  { 282 /* bdnz- */, PPC::BDNZm, Convert__CondBr1_0, 0, { MCK_CondBr }, },
4503
  { 288 /* bdnza */, PPC::BDNZA, Convert__CondBr1_0, 0, { MCK_CondBr }, },
4504
  { 294 /* bdnza+ */, PPC::BDNZAp, Convert__CondBr1_0, 0, { MCK_CondBr }, },
4505
  { 301 /* bdnza- */, PPC::BDNZAm, Convert__CondBr1_0, 0, { MCK_CondBr }, },
4506
  { 308 /* bdnzf */, PPC::gBC, Convert__imm_95_0__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4507
  { 314 /* bdnzfa */, PPC::gBCA, Convert__imm_95_0__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4508
  { 321 /* bdnzfl */, PPC::gBCL, Convert__imm_95_0__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4509
  { 328 /* bdnzfla */, PPC::gBCLA, Convert__imm_95_0__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4510
  { 336 /* bdnzflr */, PPC::gBCLR, Convert__imm_95_0__RegCRBITRC1_0__imm_95_0, 0, { MCK_RegCRBITRC }, },
4511
  { 344 /* bdnzflrl */, PPC::gBCLRL, Convert__imm_95_0__RegCRBITRC1_0__imm_95_0, 0, { MCK_RegCRBITRC }, },
4512
  { 353 /* bdnzl */, PPC::BDNZL, Convert__CondBr1_0, 0, { MCK_CondBr }, },
4513
  { 359 /* bdnzl+ */, PPC::BDNZLp, Convert__CondBr1_0, 0, { MCK_CondBr }, },
4514
  { 366 /* bdnzl- */, PPC::BDNZLm, Convert__CondBr1_0, 0, { MCK_CondBr }, },
4515
  { 373 /* bdnzla */, PPC::BDNZLA, Convert__CondBr1_0, 0, { MCK_CondBr }, },
4516
  { 380 /* bdnzla+ */, PPC::BDNZLAp, Convert__CondBr1_0, 0, { MCK_CondBr }, },
4517
  { 388 /* bdnzla- */, PPC::BDNZLAm, Convert__CondBr1_0, 0, { MCK_CondBr }, },
4518
  { 396 /* bdnzlr */, PPC::BDNZLR, Convert_NoOperands, 0, {  }, },
4519
  { 403 /* bdnzlr+ */, PPC::BDNZLRp, Convert_NoOperands, 0, {  }, },
4520
  { 411 /* bdnzlr- */, PPC::BDNZLRm, Convert_NoOperands, 0, {  }, },
4521
  { 419 /* bdnzlrl */, PPC::BDNZLRL, Convert_NoOperands, 0, {  }, },
4522
  { 427 /* bdnzlrl+ */, PPC::BDNZLRLp, Convert_NoOperands, 0, {  }, },
4523
  { 436 /* bdnzlrl- */, PPC::BDNZLRLm, Convert_NoOperands, 0, {  }, },
4524
  { 445 /* bdnzt */, PPC::gBC, Convert__imm_95_8__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4525
  { 451 /* bdnzta */, PPC::gBCA, Convert__imm_95_8__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4526
  { 458 /* bdnztl */, PPC::gBCL, Convert__imm_95_8__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4527
  { 465 /* bdnztla */, PPC::gBCLA, Convert__imm_95_8__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4528
  { 473 /* bdnztlr */, PPC::gBCLR, Convert__imm_95_8__RegCRBITRC1_0__imm_95_0, 0, { MCK_RegCRBITRC }, },
4529
  { 481 /* bdnztlrl */, PPC::gBCLRL, Convert__imm_95_8__RegCRBITRC1_0__imm_95_0, 0, { MCK_RegCRBITRC }, },
4530
  { 490 /* bdz */, PPC::BDZ, Convert__CondBr1_0, 0, { MCK_CondBr }, },
4531
  { 494 /* bdz+ */, PPC::BDZp, Convert__CondBr1_0, 0, { MCK_CondBr }, },
4532
  { 499 /* bdz- */, PPC::BDZm, Convert__CondBr1_0, 0, { MCK_CondBr }, },
4533
  { 504 /* bdza */, PPC::BDZA, Convert__CondBr1_0, 0, { MCK_CondBr }, },
4534
  { 509 /* bdza+ */, PPC::BDZAp, Convert__CondBr1_0, 0, { MCK_CondBr }, },
4535
  { 515 /* bdza- */, PPC::BDZAm, Convert__CondBr1_0, 0, { MCK_CondBr }, },
4536
  { 521 /* bdzf */, PPC::gBC, Convert__imm_95_2__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4537
  { 526 /* bdzfa */, PPC::gBCA, Convert__imm_95_2__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4538
  { 532 /* bdzfl */, PPC::gBCL, Convert__imm_95_2__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4539
  { 538 /* bdzfla */, PPC::gBCLA, Convert__imm_95_2__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4540
  { 545 /* bdzflr */, PPC::gBCLR, Convert__imm_95_2__RegCRBITRC1_0__imm_95_0, 0, { MCK_RegCRBITRC }, },
4541
  { 552 /* bdzflrl */, PPC::gBCLRL, Convert__imm_95_2__RegCRBITRC1_0__imm_95_0, 0, { MCK_RegCRBITRC }, },
4542
  { 560 /* bdzl */, PPC::BDZL, Convert__CondBr1_0, 0, { MCK_CondBr }, },
4543
  { 565 /* bdzl+ */, PPC::BDZLp, Convert__CondBr1_0, 0, { MCK_CondBr }, },
4544
  { 571 /* bdzl- */, PPC::BDZLm, Convert__CondBr1_0, 0, { MCK_CondBr }, },
4545
  { 577 /* bdzla */, PPC::BDZLA, Convert__CondBr1_0, 0, { MCK_CondBr }, },
4546
  { 583 /* bdzla+ */, PPC::BDZLAp, Convert__CondBr1_0, 0, { MCK_CondBr }, },
4547
  { 590 /* bdzla- */, PPC::BDZLAm, Convert__CondBr1_0, 0, { MCK_CondBr }, },
4548
  { 597 /* bdzlr */, PPC::BDZLR, Convert_NoOperands, 0, {  }, },
4549
  { 603 /* bdzlr+ */, PPC::BDZLRp, Convert_NoOperands, 0, {  }, },
4550
  { 610 /* bdzlr- */, PPC::BDZLRm, Convert_NoOperands, 0, {  }, },
4551
  { 617 /* bdzlrl */, PPC::BDZLRL, Convert_NoOperands, 0, {  }, },
4552
  { 624 /* bdzlrl+ */, PPC::BDZLRLp, Convert_NoOperands, 0, {  }, },
4553
  { 632 /* bdzlrl- */, PPC::BDZLRLm, Convert_NoOperands, 0, {  }, },
4554
  { 640 /* bdzt */, PPC::gBC, Convert__imm_95_10__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4555
  { 645 /* bdzta */, PPC::gBCA, Convert__imm_95_10__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4556
  { 651 /* bdztl */, PPC::gBCL, Convert__imm_95_10__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4557
  { 657 /* bdztla */, PPC::gBCLA, Convert__imm_95_10__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4558
  { 664 /* bdztlr */, PPC::gBCLR, Convert__imm_95_10__RegCRBITRC1_0__imm_95_0, 0, { MCK_RegCRBITRC }, },
4559
  { 671 /* bdztlrl */, PPC::gBCLRL, Convert__imm_95_10__RegCRBITRC1_0__imm_95_0, 0, { MCK_RegCRBITRC }, },
4560
  { 679 /* beq */, PPC::BCC, Convert__imm_95_76__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4561
  { 679 /* beq */, PPC::BCC, Convert__imm_95_76__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4562
  { 683 /* beq+ */, PPC::BCC, Convert__imm_95_79__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4563
  { 683 /* beq+ */, PPC::BCC, Convert__imm_95_79__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4564
  { 688 /* beq- */, PPC::BCC, Convert__imm_95_78__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4565
  { 688 /* beq- */, PPC::BCC, Convert__imm_95_78__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4566
  { 693 /* beqa */, PPC::BCCA, Convert__imm_95_76__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4567
  { 693 /* beqa */, PPC::BCCA, Convert__imm_95_76__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4568
  { 698 /* beqa+ */, PPC::BCCA, Convert__imm_95_79__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4569
  { 698 /* beqa+ */, PPC::BCCA, Convert__imm_95_79__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4570
  { 704 /* beqa- */, PPC::BCCA, Convert__imm_95_78__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4571
  { 704 /* beqa- */, PPC::BCCA, Convert__imm_95_78__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4572
  { 710 /* beqctr */, PPC::BCCCTR, Convert__imm_95_76__regCR0, 0, {  }, },
4573
  { 710 /* beqctr */, PPC::BCCCTR, Convert__imm_95_76__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4574
  { 717 /* beqctr+ */, PPC::BCCCTR, Convert__imm_95_79__regCR0, 0, {  }, },
4575
  { 717 /* beqctr+ */, PPC::BCCCTR, Convert__imm_95_79__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4576
  { 725 /* beqctr- */, PPC::BCCCTR, Convert__imm_95_78__regCR0, 0, {  }, },
4577
  { 725 /* beqctr- */, PPC::BCCCTR, Convert__imm_95_78__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4578
  { 733 /* beqctrl */, PPC::BCCCTRL, Convert__imm_95_76__regCR0, 0, {  }, },
4579
  { 733 /* beqctrl */, PPC::BCCCTRL, Convert__imm_95_76__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4580
  { 741 /* beqctrl+ */, PPC::BCCCTRL, Convert__imm_95_79__regCR0, 0, {  }, },
4581
  { 741 /* beqctrl+ */, PPC::BCCCTRL, Convert__imm_95_79__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4582
  { 750 /* beqctrl- */, PPC::BCCCTRL, Convert__imm_95_78__regCR0, 0, {  }, },
4583
  { 750 /* beqctrl- */, PPC::BCCCTRL, Convert__imm_95_78__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4584
  { 759 /* beql */, PPC::BCCL, Convert__imm_95_76__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4585
  { 759 /* beql */, PPC::BCCL, Convert__imm_95_76__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4586
  { 764 /* beql+ */, PPC::BCCL, Convert__imm_95_79__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4587
  { 764 /* beql+ */, PPC::BCCL, Convert__imm_95_79__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4588
  { 770 /* beql- */, PPC::BCCL, Convert__imm_95_78__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4589
  { 770 /* beql- */, PPC::BCCL, Convert__imm_95_78__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4590
  { 776 /* beqla */, PPC::BCCLA, Convert__imm_95_76__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4591
  { 776 /* beqla */, PPC::BCCLA, Convert__imm_95_76__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4592
  { 782 /* beqla+ */, PPC::BCCLA, Convert__imm_95_79__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4593
  { 782 /* beqla+ */, PPC::BCCLA, Convert__imm_95_79__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4594
  { 789 /* beqla- */, PPC::BCCLA, Convert__imm_95_78__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4595
  { 789 /* beqla- */, PPC::BCCLA, Convert__imm_95_78__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4596
  { 796 /* beqlr */, PPC::BCCLR, Convert__imm_95_76__regCR0, 0, {  }, },
4597
  { 796 /* beqlr */, PPC::BCCLR, Convert__imm_95_76__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4598
  { 802 /* beqlr+ */, PPC::BCCLR, Convert__imm_95_79__regCR0, 0, {  }, },
4599
  { 802 /* beqlr+ */, PPC::BCCLR, Convert__imm_95_79__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4600
  { 809 /* beqlr- */, PPC::BCCLR, Convert__imm_95_78__regCR0, 0, {  }, },
4601
  { 809 /* beqlr- */, PPC::BCCLR, Convert__imm_95_78__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4602
  { 816 /* beqlrl */, PPC::BCCLRL, Convert__imm_95_76__regCR0, 0, {  }, },
4603
  { 816 /* beqlrl */, PPC::BCCLRL, Convert__imm_95_76__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4604
  { 823 /* beqlrl+ */, PPC::BCCLRL, Convert__imm_95_79__regCR0, 0, {  }, },
4605
  { 823 /* beqlrl+ */, PPC::BCCLRL, Convert__imm_95_79__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4606
  { 831 /* beqlrl- */, PPC::BCCLRL, Convert__imm_95_78__regCR0, 0, {  }, },
4607
  { 831 /* beqlrl- */, PPC::BCCLRL, Convert__imm_95_78__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4608
  { 839 /* bf */, PPC::gBC, Convert__imm_95_4__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4609
  { 842 /* bf+ */, PPC::gBC, Convert__imm_95_7__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4610
  { 846 /* bf- */, PPC::gBC, Convert__imm_95_6__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4611
  { 850 /* bfa */, PPC::gBCA, Convert__imm_95_4__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4612
  { 854 /* bfa+ */, PPC::gBCA, Convert__imm_95_7__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4613
  { 859 /* bfa- */, PPC::gBCA, Convert__imm_95_6__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4614
  { 864 /* bfctr */, PPC::gBCCTR, Convert__imm_95_4__RegCRBITRC1_0__imm_95_0, 0, { MCK_RegCRBITRC }, },
4615
  { 870 /* bfctr+ */, PPC::gBCCTR, Convert__imm_95_7__RegCRBITRC1_0__imm_95_0, 0, { MCK_RegCRBITRC }, },
4616
  { 877 /* bfctr- */, PPC::gBCCTR, Convert__imm_95_6__RegCRBITRC1_0__imm_95_0, 0, { MCK_RegCRBITRC }, },
4617
  { 884 /* bfctrl */, PPC::gBCCTRL, Convert__imm_95_4__RegCRBITRC1_0__imm_95_0, 0, { MCK_RegCRBITRC }, },
4618
  { 891 /* bfctrl+ */, PPC::gBCCTRL, Convert__imm_95_7__RegCRBITRC1_0__imm_95_0, 0, { MCK_RegCRBITRC }, },
4619
  { 899 /* bfctrl- */, PPC::gBCCTRL, Convert__imm_95_6__RegCRBITRC1_0__imm_95_0, 0, { MCK_RegCRBITRC }, },
4620
  { 907 /* bfl */, PPC::gBCL, Convert__imm_95_4__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4621
  { 911 /* bfl+ */, PPC::gBCL, Convert__imm_95_7__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4622
  { 916 /* bfl- */, PPC::gBCL, Convert__imm_95_6__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4623
  { 921 /* bfla */, PPC::gBCLA, Convert__imm_95_4__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4624
  { 926 /* bfla+ */, PPC::gBCLA, Convert__imm_95_7__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4625
  { 932 /* bfla- */, PPC::gBCLA, Convert__imm_95_6__RegCRBITRC1_0__CondBr1_1, 0, { MCK_RegCRBITRC, MCK_CondBr }, },
4626
  { 938 /* bflr */, PPC::gBCLR, Convert__imm_95_4__RegCRBITRC1_0__imm_95_0, 0, { MCK_RegCRBITRC }, },
4627
  { 943 /* bflr+ */, PPC::gBCLR, Convert__imm_95_7__RegCRBITRC1_0__imm_95_0, 0, { MCK_RegCRBITRC }, },
4628
  { 949 /* bflr- */, PPC::gBCLR, Convert__imm_95_6__RegCRBITRC1_0__imm_95_0, 0, { MCK_RegCRBITRC }, },
4629
  { 955 /* bflrl */, PPC::gBCLRL, Convert__imm_95_4__RegCRBITRC1_0__imm_95_0, 0, { MCK_RegCRBITRC }, },
4630
  { 961 /* bflrl+ */, PPC::gBCLRL, Convert__imm_95_7__RegCRBITRC1_0__imm_95_0, 0, { MCK_RegCRBITRC }, },
4631
  { 968 /* bflrl- */, PPC::gBCLRL, Convert__imm_95_6__RegCRBITRC1_0__imm_95_0, 0, { MCK_RegCRBITRC }, },
4632
  { 975 /* bge */, PPC::BCC, Convert__imm_95_4__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4633
  { 975 /* bge */, PPC::BCC, Convert__imm_95_4__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4634
  { 979 /* bge+ */, PPC::BCC, Convert__imm_95_7__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4635
  { 979 /* bge+ */, PPC::BCC, Convert__imm_95_7__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4636
  { 984 /* bge- */, PPC::BCC, Convert__imm_95_6__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4637
  { 984 /* bge- */, PPC::BCC, Convert__imm_95_6__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4638
  { 989 /* bgea */, PPC::BCCA, Convert__imm_95_4__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4639
  { 989 /* bgea */, PPC::BCCA, Convert__imm_95_4__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4640
  { 994 /* bgea+ */, PPC::BCCA, Convert__imm_95_7__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4641
  { 994 /* bgea+ */, PPC::BCCA, Convert__imm_95_7__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4642
  { 1000 /* bgea- */, PPC::BCCA, Convert__imm_95_6__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4643
  { 1000 /* bgea- */, PPC::BCCA, Convert__imm_95_6__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4644
  { 1006 /* bgectr */, PPC::BCCCTR, Convert__imm_95_4__regCR0, 0, {  }, },
4645
  { 1006 /* bgectr */, PPC::BCCCTR, Convert__imm_95_4__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4646
  { 1013 /* bgectr+ */, PPC::BCCCTR, Convert__imm_95_7__regCR0, 0, {  }, },
4647
  { 1013 /* bgectr+ */, PPC::BCCCTR, Convert__imm_95_7__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4648
  { 1021 /* bgectr- */, PPC::BCCCTR, Convert__imm_95_6__regCR0, 0, {  }, },
4649
  { 1021 /* bgectr- */, PPC::BCCCTR, Convert__imm_95_6__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4650
  { 1029 /* bgectrl */, PPC::BCCCTRL, Convert__imm_95_4__regCR0, 0, {  }, },
4651
  { 1029 /* bgectrl */, PPC::BCCCTRL, Convert__imm_95_4__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4652
  { 1037 /* bgectrl+ */, PPC::BCCCTRL, Convert__imm_95_7__regCR0, 0, {  }, },
4653
  { 1037 /* bgectrl+ */, PPC::BCCCTRL, Convert__imm_95_7__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4654
  { 1046 /* bgectrl- */, PPC::BCCCTRL, Convert__imm_95_6__regCR0, 0, {  }, },
4655
  { 1046 /* bgectrl- */, PPC::BCCCTRL, Convert__imm_95_6__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4656
  { 1055 /* bgel */, PPC::BCCL, Convert__imm_95_4__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4657
  { 1055 /* bgel */, PPC::BCCL, Convert__imm_95_4__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4658
  { 1060 /* bgel+ */, PPC::BCCL, Convert__imm_95_7__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4659
  { 1060 /* bgel+ */, PPC::BCCL, Convert__imm_95_7__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4660
  { 1066 /* bgel- */, PPC::BCCL, Convert__imm_95_6__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4661
  { 1066 /* bgel- */, PPC::BCCL, Convert__imm_95_6__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4662
  { 1072 /* bgela */, PPC::BCCLA, Convert__imm_95_4__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4663
  { 1072 /* bgela */, PPC::BCCLA, Convert__imm_95_4__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4664
  { 1078 /* bgela+ */, PPC::BCCLA, Convert__imm_95_7__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4665
  { 1078 /* bgela+ */, PPC::BCCLA, Convert__imm_95_7__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4666
  { 1085 /* bgela- */, PPC::BCCLA, Convert__imm_95_6__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4667
  { 1085 /* bgela- */, PPC::BCCLA, Convert__imm_95_6__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4668
  { 1092 /* bgelr */, PPC::BCCLR, Convert__imm_95_4__regCR0, 0, {  }, },
4669
  { 1092 /* bgelr */, PPC::BCCLR, Convert__imm_95_4__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4670
  { 1098 /* bgelr+ */, PPC::BCCLR, Convert__imm_95_7__regCR0, 0, {  }, },
4671
  { 1098 /* bgelr+ */, PPC::BCCLR, Convert__imm_95_7__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4672
  { 1105 /* bgelr- */, PPC::BCCLR, Convert__imm_95_6__regCR0, 0, {  }, },
4673
  { 1105 /* bgelr- */, PPC::BCCLR, Convert__imm_95_6__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4674
  { 1112 /* bgelrl */, PPC::BCCLRL, Convert__imm_95_4__regCR0, 0, {  }, },
4675
  { 1112 /* bgelrl */, PPC::BCCLRL, Convert__imm_95_4__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4676
  { 1119 /* bgelrl+ */, PPC::BCCLRL, Convert__imm_95_7__regCR0, 0, {  }, },
4677
  { 1119 /* bgelrl+ */, PPC::BCCLRL, Convert__imm_95_7__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4678
  { 1127 /* bgelrl- */, PPC::BCCLRL, Convert__imm_95_6__regCR0, 0, {  }, },
4679
  { 1127 /* bgelrl- */, PPC::BCCLRL, Convert__imm_95_6__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4680
  { 1135 /* bgt */, PPC::BCC, Convert__imm_95_44__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4681
  { 1135 /* bgt */, PPC::BCC, Convert__imm_95_44__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4682
  { 1139 /* bgt+ */, PPC::BCC, Convert__imm_95_47__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4683
  { 1139 /* bgt+ */, PPC::BCC, Convert__imm_95_47__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4684
  { 1144 /* bgt- */, PPC::BCC, Convert__imm_95_46__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4685
  { 1144 /* bgt- */, PPC::BCC, Convert__imm_95_46__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4686
  { 1149 /* bgta */, PPC::BCCA, Convert__imm_95_44__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4687
  { 1149 /* bgta */, PPC::BCCA, Convert__imm_95_44__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4688
  { 1154 /* bgta+ */, PPC::BCCA, Convert__imm_95_47__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4689
  { 1154 /* bgta+ */, PPC::BCCA, Convert__imm_95_47__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4690
  { 1160 /* bgta- */, PPC::BCCA, Convert__imm_95_46__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4691
  { 1160 /* bgta- */, PPC::BCCA, Convert__imm_95_46__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4692
  { 1166 /* bgtctr */, PPC::BCCCTR, Convert__imm_95_44__regCR0, 0, {  }, },
4693
  { 1166 /* bgtctr */, PPC::BCCCTR, Convert__imm_95_44__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4694
  { 1173 /* bgtctr+ */, PPC::BCCCTR, Convert__imm_95_47__regCR0, 0, {  }, },
4695
  { 1173 /* bgtctr+ */, PPC::BCCCTR, Convert__imm_95_47__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4696
  { 1181 /* bgtctr- */, PPC::BCCCTR, Convert__imm_95_46__regCR0, 0, {  }, },
4697
  { 1181 /* bgtctr- */, PPC::BCCCTR, Convert__imm_95_46__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4698
  { 1189 /* bgtctrl */, PPC::BCCCTRL, Convert__imm_95_44__regCR0, 0, {  }, },
4699
  { 1189 /* bgtctrl */, PPC::BCCCTRL, Convert__imm_95_44__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4700
  { 1197 /* bgtctrl+ */, PPC::BCCCTRL, Convert__imm_95_47__regCR0, 0, {  }, },
4701
  { 1197 /* bgtctrl+ */, PPC::BCCCTRL, Convert__imm_95_47__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4702
  { 1206 /* bgtctrl- */, PPC::BCCCTRL, Convert__imm_95_46__regCR0, 0, {  }, },
4703
  { 1206 /* bgtctrl- */, PPC::BCCCTRL, Convert__imm_95_46__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4704
  { 1215 /* bgtl */, PPC::BCCL, Convert__imm_95_44__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4705
  { 1215 /* bgtl */, PPC::BCCL, Convert__imm_95_44__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4706
  { 1220 /* bgtl+ */, PPC::BCCL, Convert__imm_95_47__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4707
  { 1220 /* bgtl+ */, PPC::BCCL, Convert__imm_95_47__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4708
  { 1226 /* bgtl- */, PPC::BCCL, Convert__imm_95_46__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4709
  { 1226 /* bgtl- */, PPC::BCCL, Convert__imm_95_46__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4710
  { 1232 /* bgtla */, PPC::BCCLA, Convert__imm_95_44__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4711
  { 1232 /* bgtla */, PPC::BCCLA, Convert__imm_95_44__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4712
  { 1238 /* bgtla+ */, PPC::BCCLA, Convert__imm_95_47__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4713
  { 1238 /* bgtla+ */, PPC::BCCLA, Convert__imm_95_47__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4714
  { 1245 /* bgtla- */, PPC::BCCLA, Convert__imm_95_46__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4715
  { 1245 /* bgtla- */, PPC::BCCLA, Convert__imm_95_46__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4716
  { 1252 /* bgtlr */, PPC::BCCLR, Convert__imm_95_44__regCR0, 0, {  }, },
4717
  { 1252 /* bgtlr */, PPC::BCCLR, Convert__imm_95_44__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4718
  { 1258 /* bgtlr+ */, PPC::BCCLR, Convert__imm_95_47__regCR0, 0, {  }, },
4719
  { 1258 /* bgtlr+ */, PPC::BCCLR, Convert__imm_95_47__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4720
  { 1265 /* bgtlr- */, PPC::BCCLR, Convert__imm_95_46__regCR0, 0, {  }, },
4721
  { 1265 /* bgtlr- */, PPC::BCCLR, Convert__imm_95_46__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4722
  { 1272 /* bgtlrl */, PPC::BCCLRL, Convert__imm_95_44__regCR0, 0, {  }, },
4723
  { 1272 /* bgtlrl */, PPC::BCCLRL, Convert__imm_95_44__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4724
  { 1279 /* bgtlrl+ */, PPC::BCCLRL, Convert__imm_95_47__regCR0, 0, {  }, },
4725
  { 1279 /* bgtlrl+ */, PPC::BCCLRL, Convert__imm_95_47__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4726
  { 1287 /* bgtlrl- */, PPC::BCCLRL, Convert__imm_95_46__regCR0, 0, {  }, },
4727
  { 1287 /* bgtlrl- */, PPC::BCCLRL, Convert__imm_95_46__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4728
  { 1295 /* bl */, PPC::BL, Convert__DirectBr1_0, 0, { MCK_DirectBr }, },
4729
  { 1295 /* bl */, PPC::BL8_TLS_, Convert__DirectBr1_0__Imm1_1, 0, { MCK_DirectBr, MCK_Imm }, },
4730
  { 1298 /* bla */, PPC::BLA, Convert__DirectBr1_0, 0, { MCK_DirectBr }, },
4731
  { 1302 /* ble */, PPC::BCC, Convert__imm_95_36__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4732
  { 1302 /* ble */, PPC::BCC, Convert__imm_95_36__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4733
  { 1306 /* ble+ */, PPC::BCC, Convert__imm_95_39__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4734
  { 1306 /* ble+ */, PPC::BCC, Convert__imm_95_39__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4735
  { 1311 /* ble- */, PPC::BCC, Convert__imm_95_38__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4736
  { 1311 /* ble- */, PPC::BCC, Convert__imm_95_38__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4737
  { 1316 /* blea */, PPC::BCCA, Convert__imm_95_36__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4738
  { 1316 /* blea */, PPC::BCCA, Convert__imm_95_36__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4739
  { 1321 /* blea+ */, PPC::BCCA, Convert__imm_95_39__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4740
  { 1321 /* blea+ */, PPC::BCCA, Convert__imm_95_39__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4741
  { 1327 /* blea- */, PPC::BCCA, Convert__imm_95_38__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4742
  { 1327 /* blea- */, PPC::BCCA, Convert__imm_95_38__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4743
  { 1333 /* blectr */, PPC::BCCCTR, Convert__imm_95_36__regCR0, 0, {  }, },
4744
  { 1333 /* blectr */, PPC::BCCCTR, Convert__imm_95_36__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4745
  { 1340 /* blectr+ */, PPC::BCCCTR, Convert__imm_95_39__regCR0, 0, {  }, },
4746
  { 1340 /* blectr+ */, PPC::BCCCTR, Convert__imm_95_39__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4747
  { 1348 /* blectr- */, PPC::BCCCTR, Convert__imm_95_38__regCR0, 0, {  }, },
4748
  { 1348 /* blectr- */, PPC::BCCCTR, Convert__imm_95_38__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4749
  { 1356 /* blectrl */, PPC::BCCCTRL, Convert__imm_95_36__regCR0, 0, {  }, },
4750
  { 1356 /* blectrl */, PPC::BCCCTRL, Convert__imm_95_36__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4751
  { 1364 /* blectrl+ */, PPC::BCCCTRL, Convert__imm_95_39__regCR0, 0, {  }, },
4752
  { 1364 /* blectrl+ */, PPC::BCCCTRL, Convert__imm_95_39__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4753
  { 1373 /* blectrl- */, PPC::BCCCTRL, Convert__imm_95_38__regCR0, 0, {  }, },
4754
  { 1373 /* blectrl- */, PPC::BCCCTRL, Convert__imm_95_38__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4755
  { 1382 /* blel */, PPC::BCCL, Convert__imm_95_36__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4756
  { 1382 /* blel */, PPC::BCCL, Convert__imm_95_36__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4757
  { 1387 /* blel+ */, PPC::BCCL, Convert__imm_95_39__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4758
  { 1387 /* blel+ */, PPC::BCCL, Convert__imm_95_39__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4759
  { 1393 /* blel- */, PPC::BCCL, Convert__imm_95_38__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4760
  { 1393 /* blel- */, PPC::BCCL, Convert__imm_95_38__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4761
  { 1399 /* blela */, PPC::BCCLA, Convert__imm_95_36__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4762
  { 1399 /* blela */, PPC::BCCLA, Convert__imm_95_36__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4763
  { 1405 /* blela+ */, PPC::BCCLA, Convert__imm_95_39__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4764
  { 1405 /* blela+ */, PPC::BCCLA, Convert__imm_95_39__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4765
  { 1412 /* blela- */, PPC::BCCLA, Convert__imm_95_38__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4766
  { 1412 /* blela- */, PPC::BCCLA, Convert__imm_95_38__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4767
  { 1419 /* blelr */, PPC::BCCLR, Convert__imm_95_36__regCR0, 0, {  }, },
4768
  { 1419 /* blelr */, PPC::BCCLR, Convert__imm_95_36__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4769
  { 1425 /* blelr+ */, PPC::BCCLR, Convert__imm_95_39__regCR0, 0, {  }, },
4770
  { 1425 /* blelr+ */, PPC::BCCLR, Convert__imm_95_39__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4771
  { 1432 /* blelr- */, PPC::BCCLR, Convert__imm_95_38__regCR0, 0, {  }, },
4772
  { 1432 /* blelr- */, PPC::BCCLR, Convert__imm_95_38__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4773
  { 1439 /* blelrl */, PPC::BCCLRL, Convert__imm_95_36__regCR0, 0, {  }, },
4774
  { 1439 /* blelrl */, PPC::BCCLRL, Convert__imm_95_36__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4775
  { 1446 /* blelrl+ */, PPC::BCCLRL, Convert__imm_95_39__regCR0, 0, {  }, },
4776
  { 1446 /* blelrl+ */, PPC::BCCLRL, Convert__imm_95_39__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4777
  { 1454 /* blelrl- */, PPC::BCCLRL, Convert__imm_95_38__regCR0, 0, {  }, },
4778
  { 1454 /* blelrl- */, PPC::BCCLRL, Convert__imm_95_38__RegCRRC1_0, 0, { MCK_RegCRRC }, },
4779
  { 1462 /* blr */, PPC::BLR, Convert_NoOperands, 0, {  }, },
4780
  { 1466 /* blrl */, PPC::BLRL, Convert_NoOperands, 0, {  }, },
4781
  { 1471 /* blt */, PPC::BCC, Convert__imm_95_12__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4782
  { 1471 /* blt */, PPC::BCC, Convert__imm_95_12__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4783
  { 1475 /* blt+ */, PPC::BCC, Convert__imm_95_15__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4784
  { 1475 /* blt+ */, PPC::BCC, Convert__imm_95_15__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4785
  { 1480 /* blt- */, PPC::BCC, Convert__imm_95_14__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4786
  { 1480 /* blt- */, PPC::BCC, Convert__imm_95_14__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4787
  { 1485 /* blta */, PPC::BCCA, Convert__imm_95_12__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4788
  { 1485 /* blta */, PPC::BCCA, Convert__imm_95_12__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4789
  { 1490 /* blta+ */, PPC::BCCA, Convert__imm_95_15__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4790
  { 1490 /* blta+ */, PPC::BCCA, Convert__imm_95_15__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4791
  { 1496 /* blta- */, PPC::BCCA, Convert__imm_95_14__regCR0__CondBr1_0, 0, { MCK_CondBr }, },
4792
  { 1496 /* blta- */, PPC::BCCA, Convert__imm_95_14__RegCRRC1_0__CondBr1_1, 0, { MCK_RegCRRC, MCK_CondBr }, },
4793
  { 1502 /* b