Coverage Report

Created: 2018-12-14 11:24

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/PowerPC/PPCGenFastISel.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* "Fast" Instruction Selector for the PPC target                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
// FastEmit Immediate Predicate functions.
11
23
static bool Predicate_imm32SExt16(int64_t Imm) {
12
23
13
23
  // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
14
23
  // sign extended field.  Used by instructions like 'addi'.
15
23
  return (int32_t)Imm == (short)Imm;
16
23
17
23
}
18
19
static bool Predicate_imm64SExt16(int64_t Imm) {
19
19
20
19
  // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
21
19
  // sign extended field.  Used by instructions like 'addi'.
22
19
  return (int64_t)Imm == (short)Imm;
23
19
24
19
}
25
0
static bool Predicate_immSExt5NonZero(int64_t Imm) {
26
0
 return Imm && isInt<5>(Imm); 
27
0
}
28
29
30
// FastEmit functions for ISD::READCYCLECOUNTER.
31
32
0
unsigned fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(MVT RetVT) {
33
0
  if (RetVT.SimpleTy != MVT::i64)
34
0
    return 0;
35
0
  return fastEmitInst_(PPC::MFTB8, &PPC::G8RCRegClass);
36
0
}
37
38
unsigned fastEmit_ISD_READCYCLECOUNTER_(MVT VT, MVT RetVT) {
39
  switch (VT.SimpleTy) {
40
  case MVT::i64: return fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(RetVT);
41
  default: return 0;
42
  }
43
}
44
45
// FastEmit functions for PPCISD::MFFS.
46
47
0
unsigned fastEmit_PPCISD_MFFS_MVT_f64_(MVT RetVT) {
48
0
  if (RetVT.SimpleTy != MVT::f64)
49
0
    return 0;
50
0
  if ((PPCSubTarget->hasFPU())) {
51
0
    return fastEmitInst_(PPC::MFFS, &PPC::F8RCRegClass);
52
0
  }
53
0
  return 0;
54
0
}
55
56
unsigned fastEmit_PPCISD_MFFS_(MVT VT, MVT RetVT) {
57
  switch (VT.SimpleTy) {
58
  case MVT::f64: return fastEmit_PPCISD_MFFS_MVT_f64_(RetVT);
59
  default: return 0;
60
  }
61
}
62
63
// FastEmit functions for PPCISD::PPC32_GOT.
64
65
0
unsigned fastEmit_PPCISD_PPC32_GOT_MVT_i32_(MVT RetVT) {
66
0
  if (RetVT.SimpleTy != MVT::i32)
67
0
    return 0;
68
0
  return fastEmitInst_(PPC::PPC32GOT, &PPC::GPRCRegClass);
69
0
}
70
71
unsigned fastEmit_PPCISD_PPC32_GOT_(MVT VT, MVT RetVT) {
72
  switch (VT.SimpleTy) {
73
  case MVT::i32: return fastEmit_PPCISD_PPC32_GOT_MVT_i32_(RetVT);
74
  default: return 0;
75
  }
76
}
77
78
// Top-level FastEmit function.
79
80
unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode) override {
81
  switch (Opcode) {
82
  case ISD::READCYCLECOUNTER: return fastEmit_ISD_READCYCLECOUNTER_(VT, RetVT);
83
  case PPCISD::MFFS: return fastEmit_PPCISD_MFFS_(VT, RetVT);
84
  case PPCISD::PPC32_GOT: return fastEmit_PPCISD_PPC32_GOT_(VT, RetVT);
85
  default: return 0;
86
  }
87
}
88
89
// FastEmit functions for ISD::BITCAST.
90
91
0
unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
92
0
  if (RetVT.SimpleTy != MVT::f64)
93
0
    return 0;
94
0
  if ((PPCSubTarget->hasDirectMove()) && (PPCSubTarget->hasVSX())) {
95
0
    return fastEmitInst_r(PPC::MTVSRD, &PPC::VSFRCRegClass, Op0, Op0IsKill);
96
0
  }
97
0
  return 0;
98
0
}
99
100
0
unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
101
0
  if (RetVT.SimpleTy != MVT::i64)
102
0
    return 0;
103
0
  if ((PPCSubTarget->hasDirectMove()) && (PPCSubTarget->hasVSX())) {
104
0
    return fastEmitInst_r(PPC::MFVSRD, &PPC::G8RCRegClass, Op0, Op0IsKill);
105
0
  }
106
0
  return 0;
107
0
}
108
109
1
unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
110
1
  switch (VT.SimpleTy) {
111
1
  
case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0, Op0IsKill)0
;
112
1
  
case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill)0
;
113
1
  default: return 0;
114
1
  }
115
1
}
116
117
// FastEmit functions for ISD::CTLZ.
118
119
0
unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
120
0
  if (RetVT.SimpleTy != MVT::i32)
121
0
    return 0;
122
0
  return fastEmitInst_r(PPC::CNTLZW, &PPC::GPRCRegClass, Op0, Op0IsKill);
123
0
}
124
125
0
unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
126
0
  if (RetVT.SimpleTy != MVT::i64)
127
0
    return 0;
128
0
  return fastEmitInst_r(PPC::CNTLZD, &PPC::G8RCRegClass, Op0, Op0IsKill);
129
0
}
130
131
0
unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
132
0
  if (RetVT.SimpleTy != MVT::v16i8)
133
0
    return 0;
134
0
  if ((PPCSubTarget->hasP8Altivec())) {
135
0
    return fastEmitInst_r(PPC::VCLZB, &PPC::VRRCRegClass, Op0, Op0IsKill);
136
0
  }
137
0
  return 0;
138
0
}
139
140
0
unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
141
0
  if (RetVT.SimpleTy != MVT::v8i16)
142
0
    return 0;
143
0
  if ((PPCSubTarget->hasP8Altivec())) {
144
0
    return fastEmitInst_r(PPC::VCLZH, &PPC::VRRCRegClass, Op0, Op0IsKill);
145
0
  }
146
0
  return 0;
147
0
}
148
149
0
unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
150
0
  if (RetVT.SimpleTy != MVT::v4i32)
151
0
    return 0;
152
0
  if ((PPCSubTarget->hasP8Altivec())) {
153
0
    return fastEmitInst_r(PPC::VCLZW, &PPC::VRRCRegClass, Op0, Op0IsKill);
154
0
  }
155
0
  return 0;
156
0
}
157
158
0
unsigned fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
159
0
  if (RetVT.SimpleTy != MVT::v2i64)
160
0
    return 0;
161
0
  if ((PPCSubTarget->hasP8Altivec())) {
162
0
    return fastEmitInst_r(PPC::VCLZD, &PPC::VRRCRegClass, Op0, Op0IsKill);
163
0
  }
164
0
  return 0;
165
0
}
166
167
unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
168
  switch (VT.SimpleTy) {
169
  case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
170
  case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0, Op0IsKill);
171
  case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
172
  case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
173
  case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
174
  case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
175
  default: return 0;
176
  }
177
}
178
179
// FastEmit functions for ISD::CTPOP.
180
181
0
unsigned fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
182
0
  if (RetVT.SimpleTy != MVT::i32)
183
0
    return 0;
184
0
  return fastEmitInst_r(PPC::POPCNTW, &PPC::GPRCRegClass, Op0, Op0IsKill);
185
0
}
186
187
0
unsigned fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
188
0
  if (RetVT.SimpleTy != MVT::i64)
189
0
    return 0;
190
0
  return fastEmitInst_r(PPC::POPCNTD, &PPC::G8RCRegClass, Op0, Op0IsKill);
191
0
}
192
193
0
unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
194
0
  if (RetVT.SimpleTy != MVT::v16i8)
195
0
    return 0;
196
0
  if ((PPCSubTarget->hasP8Altivec())) {
197
0
    return fastEmitInst_r(PPC::VPOPCNTB, &PPC::VRRCRegClass, Op0, Op0IsKill);
198
0
  }
199
0
  return 0;
200
0
}
201
202
0
unsigned fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
203
0
  if (RetVT.SimpleTy != MVT::v8i16)
204
0
    return 0;
205
0
  if ((PPCSubTarget->hasP8Altivec())) {
206
0
    return fastEmitInst_r(PPC::VPOPCNTH, &PPC::VRRCRegClass, Op0, Op0IsKill);
207
0
  }
208
0
  return 0;
209
0
}
210
211
0
unsigned fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
212
0
  if (RetVT.SimpleTy != MVT::v4i32)
213
0
    return 0;
214
0
  if ((PPCSubTarget->hasP8Altivec())) {
215
0
    return fastEmitInst_r(PPC::VPOPCNTW, &PPC::VRRCRegClass, Op0, Op0IsKill);
216
0
  }
217
0
  return 0;
218
0
}
219
220
0
unsigned fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
221
0
  if (RetVT.SimpleTy != MVT::v2i64)
222
0
    return 0;
223
0
  if ((PPCSubTarget->hasP8Altivec())) {
224
0
    return fastEmitInst_r(PPC::VPOPCNTD, &PPC::VRRCRegClass, Op0, Op0IsKill);
225
0
  }
226
0
  return 0;
227
0
}
228
229
unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
230
  switch (VT.SimpleTy) {
231
  case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0, Op0IsKill);
232
  case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0, Op0IsKill);
233
  case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
234
  case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
235
  case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
236
  case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
237
  default: return 0;
238
  }
239
}
240
241
// FastEmit functions for ISD::CTTZ.
242
243
0
unsigned fastEmit_ISD_CTTZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
244
0
  if (RetVT.SimpleTy != MVT::i32)
245
0
    return 0;
246
0
  if ((PPCSubTarget->isISA3_0())) {
247
0
    return fastEmitInst_r(PPC::CNTTZW, &PPC::GPRCRegClass, Op0, Op0IsKill);
248
0
  }
249
0
  return 0;
250
0
}
251
252
0
unsigned fastEmit_ISD_CTTZ_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
253
0
  if (RetVT.SimpleTy != MVT::i64)
254
0
    return 0;
255
0
  if ((PPCSubTarget->isISA3_0())) {
256
0
    return fastEmitInst_r(PPC::CNTTZD, &PPC::G8RCRegClass, Op0, Op0IsKill);
257
0
  }
258
0
  return 0;
259
0
}
260
261
0
unsigned fastEmit_ISD_CTTZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
262
0
  if (RetVT.SimpleTy != MVT::v16i8)
263
0
    return 0;
264
0
  if ((PPCSubTarget->hasP9Altivec())) {
265
0
    return fastEmitInst_r(PPC::VCTZB, &PPC::VRRCRegClass, Op0, Op0IsKill);
266
0
  }
267
0
  return 0;
268
0
}
269
270
0
unsigned fastEmit_ISD_CTTZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
271
0
  if (RetVT.SimpleTy != MVT::v8i16)
272
0
    return 0;
273
0
  if ((PPCSubTarget->hasP9Altivec())) {
274
0
    return fastEmitInst_r(PPC::VCTZH, &PPC::VRRCRegClass, Op0, Op0IsKill);
275
0
  }
276
0
  return 0;
277
0
}
278
279
0
unsigned fastEmit_ISD_CTTZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
280
0
  if (RetVT.SimpleTy != MVT::v4i32)
281
0
    return 0;
282
0
  if ((PPCSubTarget->hasP9Altivec())) {
283
0
    return fastEmitInst_r(PPC::VCTZW, &PPC::VRRCRegClass, Op0, Op0IsKill);
284
0
  }
285
0
  return 0;
286
0
}
287
288
0
unsigned fastEmit_ISD_CTTZ_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
289
0
  if (RetVT.SimpleTy != MVT::v2i64)
290
0
    return 0;
291
0
  if ((PPCSubTarget->hasP9Altivec())) {
292
0
    return fastEmitInst_r(PPC::VCTZD, &PPC::VRRCRegClass, Op0, Op0IsKill);
293
0
  }
294
0
  return 0;
295
0
}
296
297
unsigned fastEmit_ISD_CTTZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
298
  switch (VT.SimpleTy) {
299
  case MVT::i32: return fastEmit_ISD_CTTZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
300
  case MVT::i64: return fastEmit_ISD_CTTZ_MVT_i64_r(RetVT, Op0, Op0IsKill);
301
  case MVT::v16i8: return fastEmit_ISD_CTTZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
302
  case MVT::v8i16: return fastEmit_ISD_CTTZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
303
  case MVT::v4i32: return fastEmit_ISD_CTTZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
304
  case MVT::v2i64: return fastEmit_ISD_CTTZ_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
305
  default: return 0;
306
  }
307
}
308
309
// FastEmit functions for ISD::FABS.
310
311
0
unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
312
0
  if (RetVT.SimpleTy != MVT::f32)
313
0
    return 0;
314
0
  if ((PPCSubTarget->hasSPE())) {
315
0
    return fastEmitInst_r(PPC::EFSABS, &PPC::SPE4RCRegClass, Op0, Op0IsKill);
316
0
  }
317
0
  if ((PPCSubTarget->hasFPU())) {
318
0
    return fastEmitInst_r(PPC::FABSS, &PPC::F4RCRegClass, Op0, Op0IsKill);
319
0
  }
320
0
  return 0;
321
0
}
322
323
0
unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
324
0
  if (RetVT.SimpleTy != MVT::f64)
325
0
    return 0;
326
0
  if ((PPCSubTarget->hasVSX())) {
327
0
    return fastEmitInst_r(PPC::XSABSDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
328
0
  }
329
0
  if ((PPCSubTarget->hasSPE())) {
330
0
    return fastEmitInst_r(PPC::EFDABS, &PPC::SPERCRegClass, Op0, Op0IsKill);
331
0
  }
332
0
  if ((PPCSubTarget->hasFPU())) {
333
0
    return fastEmitInst_r(PPC::FABSD, &PPC::F8RCRegClass, Op0, Op0IsKill);
334
0
  }
335
0
  return 0;
336
0
}
337
338
0
unsigned fastEmit_ISD_FABS_MVT_f128_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
339
0
  if (RetVT.SimpleTy != MVT::f128)
340
0
    return 0;
341
0
  if ((PPCSubTarget->hasP9Vector())) {
342
0
    return fastEmitInst_r(PPC::XSABSQP, &PPC::VRRCRegClass, Op0, Op0IsKill);
343
0
  }
344
0
  return 0;
345
0
}
346
347
0
unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
348
0
  if (RetVT.SimpleTy != MVT::v4f32)
349
0
    return 0;
350
0
  if ((PPCSubTarget->hasVSX())) {
351
0
    return fastEmitInst_r(PPC::XVABSSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
352
0
  }
353
0
  if ((PPCSubTarget->hasQPX())) {
354
0
    return fastEmitInst_r(PPC::QVFABSs, &PPC::QSRCRegClass, Op0, Op0IsKill);
355
0
  }
356
0
  return 0;
357
0
}
358
359
0
unsigned fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
360
0
  if (RetVT.SimpleTy != MVT::v2f64)
361
0
    return 0;
362
0
  if ((PPCSubTarget->hasVSX())) {
363
0
    return fastEmitInst_r(PPC::XVABSDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
364
0
  }
365
0
  return 0;
366
0
}
367
368
0
unsigned fastEmit_ISD_FABS_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
369
0
  if (RetVT.SimpleTy != MVT::v4f64)
370
0
    return 0;
371
0
  if ((PPCSubTarget->hasQPX())) {
372
0
    return fastEmitInst_r(PPC::QVFABS, &PPC::QFRCRegClass, Op0, Op0IsKill);
373
0
  }
374
0
  return 0;
375
0
}
376
377
unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
378
  switch (VT.SimpleTy) {
379
  case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill);
380
  case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0, Op0IsKill);
381
  case MVT::f128: return fastEmit_ISD_FABS_MVT_f128_r(RetVT, Op0, Op0IsKill);
382
  case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
383
  case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
384
  case MVT::v4f64: return fastEmit_ISD_FABS_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
385
  default: return 0;
386
  }
387
}
388
389
// FastEmit functions for ISD::FCEIL.
390
391
0
unsigned fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
392
0
  if (RetVT.SimpleTy != MVT::f32)
393
0
    return 0;
394
0
  if ((PPCSubTarget->hasFPU())) {
395
0
    return fastEmitInst_r(PPC::FRIPS, &PPC::F4RCRegClass, Op0, Op0IsKill);
396
0
  }
397
0
  return 0;
398
0
}
399
400
0
unsigned fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
401
0
  if (RetVT.SimpleTy != MVT::f64)
402
0
    return 0;
403
0
  if ((PPCSubTarget->hasVSX())) {
404
0
    return fastEmitInst_r(PPC::XSRDPIP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
405
0
  }
406
0
  if ((PPCSubTarget->hasFPU())) {
407
0
    return fastEmitInst_r(PPC::FRIPD, &PPC::F8RCRegClass, Op0, Op0IsKill);
408
0
  }
409
0
  return 0;
410
0
}
411
412
0
unsigned fastEmit_ISD_FCEIL_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
413
0
  if (RetVT.SimpleTy != MVT::v4f32)
414
0
    return 0;
415
0
  if ((PPCSubTarget->hasVSX())) {
416
0
    return fastEmitInst_r(PPC::XVRSPIP, &PPC::VSRCRegClass, Op0, Op0IsKill);
417
0
  }
418
0
  if ((PPCSubTarget->hasAltivec())) {
419
0
    return fastEmitInst_r(PPC::VRFIP, &PPC::VRRCRegClass, Op0, Op0IsKill);
420
0
  }
421
0
  if ((PPCSubTarget->hasQPX())) {
422
0
    return fastEmitInst_r(PPC::QVFRIPs, &PPC::QSRCRegClass, Op0, Op0IsKill);
423
0
  }
424
0
  return 0;
425
0
}
426
427
0
unsigned fastEmit_ISD_FCEIL_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
428
0
  if (RetVT.SimpleTy != MVT::v2f64)
429
0
    return 0;
430
0
  if ((PPCSubTarget->hasVSX())) {
431
0
    return fastEmitInst_r(PPC::XVRDPIP, &PPC::VSRCRegClass, Op0, Op0IsKill);
432
0
  }
433
0
  return 0;
434
0
}
435
436
0
unsigned fastEmit_ISD_FCEIL_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
437
0
  if (RetVT.SimpleTy != MVT::v4f64)
438
0
    return 0;
439
0
  if ((PPCSubTarget->hasQPX())) {
440
0
    return fastEmitInst_r(PPC::QVFRIP, &PPC::QFRCRegClass, Op0, Op0IsKill);
441
0
  }
442
0
  return 0;
443
0
}
444
445
unsigned fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
446
  switch (VT.SimpleTy) {
447
  case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0, Op0IsKill);
448
  case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0, Op0IsKill);
449
  case MVT::v4f32: return fastEmit_ISD_FCEIL_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
450
  case MVT::v2f64: return fastEmit_ISD_FCEIL_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
451
  case MVT::v4f64: return fastEmit_ISD_FCEIL_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
452
  default: return 0;
453
  }
454
}
455
456
// FastEmit functions for ISD::FFLOOR.
457
458
0
unsigned fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
459
0
  if (RetVT.SimpleTy != MVT::f32)
460
0
    return 0;
461
0
  if ((PPCSubTarget->hasFPU())) {
462
0
    return fastEmitInst_r(PPC::FRIMS, &PPC::F4RCRegClass, Op0, Op0IsKill);
463
0
  }
464
0
  return 0;
465
0
}
466
467
0
unsigned fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
468
0
  if (RetVT.SimpleTy != MVT::f64)
469
0
    return 0;
470
0
  if ((PPCSubTarget->hasVSX())) {
471
0
    return fastEmitInst_r(PPC::XSRDPIM, &PPC::VSFRCRegClass, Op0, Op0IsKill);
472
0
  }
473
0
  if ((PPCSubTarget->hasFPU())) {
474
0
    return fastEmitInst_r(PPC::FRIMD, &PPC::F8RCRegClass, Op0, Op0IsKill);
475
0
  }
476
0
  return 0;
477
0
}
478
479
0
unsigned fastEmit_ISD_FFLOOR_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
480
0
  if (RetVT.SimpleTy != MVT::v4f32)
481
0
    return 0;
482
0
  if ((PPCSubTarget->hasVSX())) {
483
0
    return fastEmitInst_r(PPC::XVRSPIM, &PPC::VSRCRegClass, Op0, Op0IsKill);
484
0
  }
485
0
  if ((PPCSubTarget->hasAltivec())) {
486
0
    return fastEmitInst_r(PPC::VRFIM, &PPC::VRRCRegClass, Op0, Op0IsKill);
487
0
  }
488
0
  if ((PPCSubTarget->hasQPX())) {
489
0
    return fastEmitInst_r(PPC::QVFRIMs, &PPC::QSRCRegClass, Op0, Op0IsKill);
490
0
  }
491
0
  return 0;
492
0
}
493
494
0
unsigned fastEmit_ISD_FFLOOR_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
495
0
  if (RetVT.SimpleTy != MVT::v2f64)
496
0
    return 0;
497
0
  if ((PPCSubTarget->hasVSX())) {
498
0
    return fastEmitInst_r(PPC::XVRDPIM, &PPC::VSRCRegClass, Op0, Op0IsKill);
499
0
  }
500
0
  return 0;
501
0
}
502
503
0
unsigned fastEmit_ISD_FFLOOR_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
504
0
  if (RetVT.SimpleTy != MVT::v4f64)
505
0
    return 0;
506
0
  if ((PPCSubTarget->hasQPX())) {
507
0
    return fastEmitInst_r(PPC::QVFRIM, &PPC::QFRCRegClass, Op0, Op0IsKill);
508
0
  }
509
0
  return 0;
510
0
}
511
512
unsigned fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
513
  switch (VT.SimpleTy) {
514
  case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0, Op0IsKill);
515
  case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0, Op0IsKill);
516
  case MVT::v4f32: return fastEmit_ISD_FFLOOR_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
517
  case MVT::v2f64: return fastEmit_ISD_FFLOOR_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
518
  case MVT::v4f64: return fastEmit_ISD_FFLOOR_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
519
  default: return 0;
520
  }
521
}
522
523
// FastEmit functions for ISD::FNEARBYINT.
524
525
0
unsigned fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
526
0
  if (RetVT.SimpleTy != MVT::f64)
527
0
    return 0;
528
0
  if ((PPCSubTarget->hasVSX())) {
529
0
    return fastEmitInst_r(PPC::XSRDPIC, &PPC::VSFRCRegClass, Op0, Op0IsKill);
530
0
  }
531
0
  return 0;
532
0
}
533
534
0
unsigned fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
535
0
  if (RetVT.SimpleTy != MVT::v4f32)
536
0
    return 0;
537
0
  if ((PPCSubTarget->hasVSX())) {
538
0
    return fastEmitInst_r(PPC::XVRSPIC, &PPC::VSRCRegClass, Op0, Op0IsKill);
539
0
  }
540
0
  if ((PPCSubTarget->hasAltivec())) {
541
0
    return fastEmitInst_r(PPC::VRFIN, &PPC::VRRCRegClass, Op0, Op0IsKill);
542
0
  }
543
0
  return 0;
544
0
}
545
546
0
unsigned fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
547
0
  if (RetVT.SimpleTy != MVT::v2f64)
548
0
    return 0;
549
0
  if ((PPCSubTarget->hasVSX())) {
550
0
    return fastEmitInst_r(PPC::XVRDPIC, &PPC::VSRCRegClass, Op0, Op0IsKill);
551
0
  }
552
0
  return 0;
553
0
}
554
555
unsigned fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
556
  switch (VT.SimpleTy) {
557
  case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0, Op0IsKill);
558
  case MVT::v4f32: return fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
559
  case MVT::v2f64: return fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
560
  default: return 0;
561
  }
562
}
563
564
// FastEmit functions for ISD::FNEG.
565
566
0
unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
567
0
  if (RetVT.SimpleTy != MVT::f32)
568
0
    return 0;
569
0
  if ((PPCSubTarget->hasSPE())) {
570
0
    return fastEmitInst_r(PPC::EFSNEG, &PPC::SPE4RCRegClass, Op0, Op0IsKill);
571
0
  }
572
0
  if ((PPCSubTarget->hasFPU())) {
573
0
    return fastEmitInst_r(PPC::FNEGS, &PPC::F4RCRegClass, Op0, Op0IsKill);
574
0
  }
575
0
  return 0;
576
0
}
577
578
0
unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
579
0
  if (RetVT.SimpleTy != MVT::f64)
580
0
    return 0;
581
0
  if ((PPCSubTarget->hasVSX())) {
582
0
    return fastEmitInst_r(PPC::XSNEGDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
583
0
  }
584
0
  if ((PPCSubTarget->hasSPE())) {
585
0
    return fastEmitInst_r(PPC::EFDNEG, &PPC::SPERCRegClass, Op0, Op0IsKill);
586
0
  }
587
0
  if ((PPCSubTarget->hasFPU())) {
588
0
    return fastEmitInst_r(PPC::FNEGD, &PPC::F8RCRegClass, Op0, Op0IsKill);
589
0
  }
590
0
  return 0;
591
0
}
592
593
0
unsigned fastEmit_ISD_FNEG_MVT_f128_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
594
0
  if (RetVT.SimpleTy != MVT::f128)
595
0
    return 0;
596
0
  if ((PPCSubTarget->hasP9Vector())) {
597
0
    return fastEmitInst_r(PPC::XSNEGQP, &PPC::VRRCRegClass, Op0, Op0IsKill);
598
0
  }
599
0
  return 0;
600
0
}
601
602
0
unsigned fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
603
0
  if (RetVT.SimpleTy != MVT::v4f32)
604
0
    return 0;
605
0
  if ((PPCSubTarget->hasVSX())) {
606
0
    return fastEmitInst_r(PPC::XVNEGSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
607
0
  }
608
0
  if ((PPCSubTarget->hasQPX())) {
609
0
    return fastEmitInst_r(PPC::QVFNEGs, &PPC::QSRCRegClass, Op0, Op0IsKill);
610
0
  }
611
0
  return 0;
612
0
}
613
614
0
unsigned fastEmit_ISD_FNEG_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
615
0
  if (RetVT.SimpleTy != MVT::v2f64)
616
0
    return 0;
617
0
  if ((PPCSubTarget->hasVSX())) {
618
0
    return fastEmitInst_r(PPC::XVNEGDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
619
0
  }
620
0
  return 0;
621
0
}
622
623
0
unsigned fastEmit_ISD_FNEG_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
624
0
  if (RetVT.SimpleTy != MVT::v4f64)
625
0
    return 0;
626
0
  if ((PPCSubTarget->hasQPX())) {
627
0
    return fastEmitInst_r(PPC::QVFNEG, &PPC::QFRCRegClass, Op0, Op0IsKill);
628
0
  }
629
0
  return 0;
630
0
}
631
632
unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
633
  switch (VT.SimpleTy) {
634
  case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill);
635
  case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0, Op0IsKill);
636
  case MVT::f128: return fastEmit_ISD_FNEG_MVT_f128_r(RetVT, Op0, Op0IsKill);
637
  case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
638
  case MVT::v2f64: return fastEmit_ISD_FNEG_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
639
  case MVT::v4f64: return fastEmit_ISD_FNEG_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
640
  default: return 0;
641
  }
642
}
643
644
// FastEmit functions for ISD::FP_EXTEND.
645
646
0
unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
647
0
  if (RetVT.SimpleTy != MVT::f64)
648
0
    return 0;
649
0
  if ((PPCSubTarget->hasSPE())) {
650
0
    return fastEmitInst_r(PPC::EFDCFS, &PPC::SPERCRegClass, Op0, Op0IsKill);
651
0
  }
652
0
  return 0;
653
0
}
654
655
0
unsigned fastEmit_ISD_FP_EXTEND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
656
0
  if (RetVT.SimpleTy != MVT::f128)
657
0
    return 0;
658
0
  if ((PPCSubTarget->hasP9Vector())) {
659
0
    return fastEmitInst_r(PPC::XSCVDPQP, &PPC::VRRCRegClass, Op0, Op0IsKill);
660
0
  }
661
0
  return 0;
662
0
}
663
664
unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
665
  switch (VT.SimpleTy) {
666
  case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill);
667
  case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f64_r(RetVT, Op0, Op0IsKill);
668
  default: return 0;
669
  }
670
}
671
672
// FastEmit functions for ISD::FP_ROUND.
673
674
0
unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
675
0
  if (RetVT.SimpleTy != MVT::f32)
676
0
    return 0;
677
0
  if ((PPCSubTarget->hasSPE())) {
678
0
    return fastEmitInst_r(PPC::EFSCFD, &PPC::SPE4RCRegClass, Op0, Op0IsKill);
679
0
  }
680
0
  if ((PPCSubTarget->hasFPU())) {
681
0
    return fastEmitInst_r(PPC::FRSP, &PPC::F4RCRegClass, Op0, Op0IsKill);
682
0
  }
683
0
  return 0;
684
0
}
685
686
0
unsigned fastEmit_ISD_FP_ROUND_MVT_f128_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
687
0
  if (RetVT.SimpleTy != MVT::f64)
688
0
    return 0;
689
0
  if ((PPCSubTarget->hasP9Vector())) {
690
0
    return fastEmitInst_r(PPC::XSCVQPDP, &PPC::VFRCRegClass, Op0, Op0IsKill);
691
0
  }
692
0
  return 0;
693
0
}
694
695
unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
696
  switch (VT.SimpleTy) {
697
  case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
698
  case MVT::f128: return fastEmit_ISD_FP_ROUND_MVT_f128_r(RetVT, Op0, Op0IsKill);
699
  default: return 0;
700
  }
701
}
702
703
// FastEmit functions for ISD::FP_TO_SINT.
704
705
10
unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
706
10
  if (RetVT.SimpleTy != MVT::i32)
707
4
    return 0;
708
6
  if ((PPCSubTarget->hasSPE())) {
709
0
    return fastEmitInst_r(PPC::EFSCTSIZ, &PPC::GPRCRegClass, Op0, Op0IsKill);
710
0
  }
711
6
  return 0;
712
6
}
713
714
8
unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
715
8
  if (RetVT.SimpleTy != MVT::i32)
716
4
    return 0;
717
4
  if ((PPCSubTarget->hasSPE())) {
718
0
    return fastEmitInst_r(PPC::EFDCTSIZ, &PPC::GPRCRegClass, Op0, Op0IsKill);
719
0
  }
720
4
  return 0;
721
4
}
722
723
0
unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
724
0
  if (RetVT.SimpleTy != MVT::v4i32)
725
0
    return 0;
726
0
  if ((PPCSubTarget->hasVSX())) {
727
0
    return fastEmitInst_r(PPC::XVCVSPSXWS, &PPC::VSRCRegClass, Op0, Op0IsKill);
728
0
  }
729
0
  if ((PPCSubTarget->hasAltivec())) {
730
0
    return fastEmitInst_r(PPC::VCTSXS_0, &PPC::VRRCRegClass, Op0, Op0IsKill);
731
0
  }
732
0
  return 0;
733
0
}
734
735
1
unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
736
1
  if (RetVT.SimpleTy != MVT::v2i64)
737
0
    return 0;
738
1
  if ((PPCSubTarget->hasVSX())) {
739
1
    return fastEmitInst_r(PPC::XVCVDPSXDS, &PPC::VSRCRegClass, Op0, Op0IsKill);
740
1
  }
741
0
  return 0;
742
0
}
743
744
19
unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
745
19
  switch (VT.SimpleTy) {
746
19
  
case MVT::f32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_r(RetVT, Op0, Op0IsKill)10
;
747
19
  
case MVT::f64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_r(RetVT, Op0, Op0IsKill)8
;
748
19
  
case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill)0
;
749
19
  
case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill)1
;
750
19
  
default: return 00
;
751
19
  }
752
19
}
753
754
// FastEmit functions for ISD::FP_TO_UINT.
755
756
0
unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
757
0
  if (RetVT.SimpleTy != MVT::i32)
758
0
    return 0;
759
0
  if ((PPCSubTarget->hasSPE())) {
760
0
    return fastEmitInst_r(PPC::EFSCTUIZ, &PPC::GPRCRegClass, Op0, Op0IsKill);
761
0
  }
762
0
  return 0;
763
0
}
764
765
0
unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
766
0
  if (RetVT.SimpleTy != MVT::i32)
767
0
    return 0;
768
0
  if ((PPCSubTarget->hasSPE())) {
769
0
    return fastEmitInst_r(PPC::EFDCTUIZ, &PPC::GPRCRegClass, Op0, Op0IsKill);
770
0
  }
771
0
  return 0;
772
0
}
773
774
0
unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
775
0
  if (RetVT.SimpleTy != MVT::v4i32)
776
0
    return 0;
777
0
  if ((PPCSubTarget->hasVSX())) {
778
0
    return fastEmitInst_r(PPC::XVCVSPUXWS, &PPC::VSRCRegClass, Op0, Op0IsKill);
779
0
  }
780
0
  if ((PPCSubTarget->hasAltivec())) {
781
0
    return fastEmitInst_r(PPC::VCTUXS_0, &PPC::VRRCRegClass, Op0, Op0IsKill);
782
0
  }
783
0
  return 0;
784
0
}
785
786
0
unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
787
0
  if (RetVT.SimpleTy != MVT::v2i64)
788
0
    return 0;
789
0
  if ((PPCSubTarget->hasVSX())) {
790
0
    return fastEmitInst_r(PPC::XVCVDPUXDS, &PPC::VSRCRegClass, Op0, Op0IsKill);
791
0
  }
792
0
  return 0;
793
0
}
794
795
unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
796
  switch (VT.SimpleTy) {
797
  case MVT::f32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
798
  case MVT::f64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_r(RetVT, Op0, Op0IsKill);
799
  case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
800
  case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
801
  default: return 0;
802
  }
803
}
804
805
// FastEmit functions for ISD::FROUND.
806
807
0
unsigned fastEmit_ISD_FROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
808
0
  if (RetVT.SimpleTy != MVT::f32)
809
0
    return 0;
810
0
  if ((PPCSubTarget->hasFPU())) {
811
0
    return fastEmitInst_r(PPC::FRINS, &PPC::F4RCRegClass, Op0, Op0IsKill);
812
0
  }
813
0
  return 0;
814
0
}
815
816
0
unsigned fastEmit_ISD_FROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
817
0
  if (RetVT.SimpleTy != MVT::f64)
818
0
    return 0;
819
0
  if ((PPCSubTarget->hasVSX())) {
820
0
    return fastEmitInst_r(PPC::XSRDPI, &PPC::VSFRCRegClass, Op0, Op0IsKill);
821
0
  }
822
0
  if ((PPCSubTarget->hasFPU())) {
823
0
    return fastEmitInst_r(PPC::FRIND, &PPC::F8RCRegClass, Op0, Op0IsKill);
824
0
  }
825
0
  return 0;
826
0
}
827
828
0
unsigned fastEmit_ISD_FROUND_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
829
0
  if (RetVT.SimpleTy != MVT::v4f32)
830
0
    return 0;
831
0
  if ((PPCSubTarget->hasVSX())) {
832
0
    return fastEmitInst_r(PPC::XVRSPI, &PPC::VSRCRegClass, Op0, Op0IsKill);
833
0
  }
834
0
  if ((PPCSubTarget->hasQPX())) {
835
0
    return fastEmitInst_r(PPC::QVFRINs, &PPC::QSRCRegClass, Op0, Op0IsKill);
836
0
  }
837
0
  return 0;
838
0
}
839
840
0
unsigned fastEmit_ISD_FROUND_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
841
0
  if (RetVT.SimpleTy != MVT::v2f64)
842
0
    return 0;
843
0
  if ((PPCSubTarget->hasVSX())) {
844
0
    return fastEmitInst_r(PPC::XVRDPI, &PPC::VSRCRegClass, Op0, Op0IsKill);
845
0
  }
846
0
  return 0;
847
0
}
848
849
0
unsigned fastEmit_ISD_FROUND_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
850
0
  if (RetVT.SimpleTy != MVT::v4f64)
851
0
    return 0;
852
0
  if ((PPCSubTarget->hasQPX())) {
853
0
    return fastEmitInst_r(PPC::QVFRIN, &PPC::QFRCRegClass, Op0, Op0IsKill);
854
0
  }
855
0
  return 0;
856
0
}
857
858
unsigned fastEmit_ISD_FROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
859
  switch (VT.SimpleTy) {
860
  case MVT::f32: return fastEmit_ISD_FROUND_MVT_f32_r(RetVT, Op0, Op0IsKill);
861
  case MVT::f64: return fastEmit_ISD_FROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
862
  case MVT::v4f32: return fastEmit_ISD_FROUND_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
863
  case MVT::v2f64: return fastEmit_ISD_FROUND_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
864
  case MVT::v4f64: return fastEmit_ISD_FROUND_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
865
  default: return 0;
866
  }
867
}
868
869
// FastEmit functions for ISD::FSQRT.
870
871
0
unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
872
0
  if (RetVT.SimpleTy != MVT::f32)
873
0
    return 0;
874
0
  if ((PPCSubTarget->hasP8Vector())) {
875
0
    return fastEmitInst_r(PPC::XSSQRTSP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
876
0
  }
877
0
  if ((PPCSubTarget->hasFPU())) {
878
0
    return fastEmitInst_r(PPC::FSQRTS, &PPC::F4RCRegClass, Op0, Op0IsKill);
879
0
  }
880
0
  return 0;
881
0
}
882
883
0
unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
884
0
  if (RetVT.SimpleTy != MVT::f64)
885
0
    return 0;
886
0
  if ((PPCSubTarget->hasVSX())) {
887
0
    return fastEmitInst_r(PPC::XSSQRTDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
888
0
  }
889
0
  if ((PPCSubTarget->hasFPU())) {
890
0
    return fastEmitInst_r(PPC::FSQRT, &PPC::F8RCRegClass, Op0, Op0IsKill);
891
0
  }
892
0
  return 0;
893
0
}
894
895
0
unsigned fastEmit_ISD_FSQRT_MVT_f128_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
896
0
  if (RetVT.SimpleTy != MVT::f128)
897
0
    return 0;
898
0
  if ((PPCSubTarget->hasP9Vector())) {
899
0
    return fastEmitInst_r(PPC::XSSQRTQP, &PPC::VRRCRegClass, Op0, Op0IsKill);
900
0
  }
901
0
  return 0;
902
0
}
903
904
0
unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
905
0
  if (RetVT.SimpleTy != MVT::v4f32)
906
0
    return 0;
907
0
  if ((PPCSubTarget->hasVSX())) {
908
0
    return fastEmitInst_r(PPC::XVSQRTSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
909
0
  }
910
0
  return 0;
911
0
}
912
913
0
unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
914
0
  if (RetVT.SimpleTy != MVT::v2f64)
915
0
    return 0;
916
0
  if ((PPCSubTarget->hasVSX())) {
917
0
    return fastEmitInst_r(PPC::XVSQRTDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
918
0
  }
919
0
  return 0;
920
0
}
921
922
unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
923
  switch (VT.SimpleTy) {
924
  case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill);
925
  case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0, Op0IsKill);
926
  case MVT::f128: return fastEmit_ISD_FSQRT_MVT_f128_r(RetVT, Op0, Op0IsKill);
927
  case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
928
  case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
929
  default: return 0;
930
  }
931
}
932
933
// FastEmit functions for ISD::FTRUNC.
934
935
0
unsigned fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
936
0
  if (RetVT.SimpleTy != MVT::f32)
937
0
    return 0;
938
0
  if ((PPCSubTarget->hasFPU())) {
939
0
    return fastEmitInst_r(PPC::FRIZS, &PPC::F4RCRegClass, Op0, Op0IsKill);
940
0
  }
941
0
  return 0;
942
0
}
943
944
0
unsigned fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
945
0
  if (RetVT.SimpleTy != MVT::f64)
946
0
    return 0;
947
0
  if ((PPCSubTarget->hasVSX())) {
948
0
    return fastEmitInst_r(PPC::XSRDPIZ, &PPC::VSFRCRegClass, Op0, Op0IsKill);
949
0
  }
950
0
  if ((PPCSubTarget->hasFPU())) {
951
0
    return fastEmitInst_r(PPC::FRIZD, &PPC::F8RCRegClass, Op0, Op0IsKill);
952
0
  }
953
0
  return 0;
954
0
}
955
956
0
unsigned fastEmit_ISD_FTRUNC_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
957
0
  if (RetVT.SimpleTy != MVT::v4f32)
958
0
    return 0;
959
0
  if ((PPCSubTarget->hasVSX())) {
960
0
    return fastEmitInst_r(PPC::XVRSPIZ, &PPC::VSRCRegClass, Op0, Op0IsKill);
961
0
  }
962
0
  if ((PPCSubTarget->hasAltivec())) {
963
0
    return fastEmitInst_r(PPC::VRFIZ, &PPC::VRRCRegClass, Op0, Op0IsKill);
964
0
  }
965
0
  if ((PPCSubTarget->hasQPX())) {
966
0
    return fastEmitInst_r(PPC::QVFRIZs, &PPC::QSRCRegClass, Op0, Op0IsKill);
967
0
  }
968
0
  return 0;
969
0
}
970
971
0
unsigned fastEmit_ISD_FTRUNC_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
972
0
  if (RetVT.SimpleTy != MVT::v2f64)
973
0
    return 0;
974
0
  if ((PPCSubTarget->hasVSX())) {
975
0
    return fastEmitInst_r(PPC::XVRDPIZ, &PPC::VSRCRegClass, Op0, Op0IsKill);
976
0
  }
977
0
  return 0;
978
0
}
979
980
0
unsigned fastEmit_ISD_FTRUNC_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
981
0
  if (RetVT.SimpleTy != MVT::v4f64)
982
0
    return 0;
983
0
  if ((PPCSubTarget->hasQPX())) {
984
0
    return fastEmitInst_r(PPC::QVFRIZ, &PPC::QFRCRegClass, Op0, Op0IsKill);
985
0
  }
986
0
  return 0;
987
0
}
988
989
unsigned fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
990
  switch (VT.SimpleTy) {
991
  case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0, Op0IsKill);
992
  case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0, Op0IsKill);
993
  case MVT::v4f32: return fastEmit_ISD_FTRUNC_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
994
  case MVT::v2f64: return fastEmit_ISD_FTRUNC_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
995
  case MVT::v4f64: return fastEmit_ISD_FTRUNC_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
996
  default: return 0;
997
  }
998
}
999
1000
// FastEmit functions for ISD::SCALAR_TO_VECTOR.
1001
1002
0
unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1003
0
  if (RetVT.SimpleTy != MVT::v4i32)
1004
0
    return 0;
1005
0
  if ((PPCSubTarget->hasP9Vector())) {
1006
0
    return fastEmitInst_r(PPC::MTVSRWS, &PPC::VSRCRegClass, Op0, Op0IsKill);
1007
0
  }
1008
0
  return 0;
1009
0
}
1010
1011
0
unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1012
0
  if (RetVT.SimpleTy != MVT::v4f32)
1013
0
    return 0;
1014
0
  if ((PPCSubTarget->hasP8Vector()) && (!PPCSubTarget->isLittleEndian())) {
1015
0
    return fastEmitInst_r(PPC::XSCVDPSPN, &PPC::VSRCRegClass, Op0, Op0IsKill);
1016
0
  }
1017
0
  return 0;
1018
0
}
1019
1020
unsigned fastEmit_ISD_SCALAR_TO_VECTOR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1021
  switch (VT.SimpleTy) {
1022
  case MVT::i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(RetVT, Op0, Op0IsKill);
1023
  case MVT::f32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(RetVT, Op0, Op0IsKill);
1024
  default: return 0;
1025
  }
1026
}
1027
1028
// FastEmit functions for ISD::SIGN_EXTEND.
1029
1030
4
unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1031
4
  if (RetVT.SimpleTy != MVT::i64)
1032
0
    return 0;
1033
4
  return fastEmitInst_r(PPC::EXTSW_32_64, &PPC::G8RCRegClass, Op0, Op0IsKill);
1034
4
}
1035
1036
5
unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1037
5
  switch (VT.SimpleTy) {
1038
5
  
case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0, Op0IsKill)4
;
1039
5
  
default: return 01
;
1040
5
  }
1041
5
}
1042
1043
// FastEmit functions for ISD::SINT_TO_FP.
1044
1045
3
unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
1046
3
  if ((PPCSubTarget->hasSPE())) {
1047
0
    return fastEmitInst_r(PPC::EFSCFSI, &PPC::SPE4RCRegClass, Op0, Op0IsKill);
1048
0
  }
1049
3
  return 0;
1050
3
}
1051
1052
4
unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
1053
4
  if ((PPCSubTarget->hasSPE())) {
1054
0
    return fastEmitInst_r(PPC::EFDCFSI, &PPC::SPERCRegClass, Op0, Op0IsKill);
1055
0
  }
1056
4
  return 0;
1057
4
}
1058
1059
7
unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1060
7
switch (RetVT.SimpleTy) {
1061
7
  
case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill)3
;
1062
7
  
case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0, Op0IsKill)4
;
1063
7
  
default: return 00
;
1064
7
}
1065
7
}
1066
1067
0
unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1068
0
  if (RetVT.SimpleTy != MVT::v4f32)
1069
0
    return 0;
1070
0
  if ((PPCSubTarget->hasVSX())) {
1071
0
    return fastEmitInst_r(PPC::XVCVSXWSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
1072
0
  }
1073
0
  if ((PPCSubTarget->hasAltivec())) {
1074
0
    return fastEmitInst_r(PPC::VCFSX_0, &PPC::VRRCRegClass, Op0, Op0IsKill);
1075
0
  }
1076
0
  return 0;
1077
0
}
1078
1079
1
unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1080
1
  if (RetVT.SimpleTy != MVT::v2f64)
1081
0
    return 0;
1082
1
  if ((PPCSubTarget->hasVSX())) {
1083
1
    return fastEmitInst_r(PPC::XVCVSXDDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
1084
1
  }
1085
0
  return 0;
1086
0
}
1087
1088
15
unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1089
15
  switch (VT.SimpleTy) {
1090
15
  
case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0, Op0IsKill)7
;
1091
15
  
case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill)0
;
1092
15
  
case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill)1
;
1093
15
  
default: return 07
;
1094
15
  }
1095
15
}
1096
1097
// FastEmit functions for ISD::TRUNCATE.
1098
1099
0
unsigned fastEmit_ISD_TRUNCATE_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1100
0
  if (RetVT.SimpleTy != MVT::i1)
1101
0
    return 0;
1102
0
  return fastEmitInst_r(PPC::ANDIo_1_GT_BIT, &PPC::CRBITRCRegClass, Op0, Op0IsKill);
1103
0
}
1104
1105
0
unsigned fastEmit_ISD_TRUNCATE_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1106
0
  if (RetVT.SimpleTy != MVT::i1)
1107
0
    return 0;
1108
0
  return fastEmitInst_r(PPC::ANDIo_1_GT_BIT8, &PPC::CRBITRCRegClass, Op0, Op0IsKill);
1109
0
}
1110
1111
unsigned fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1112
  switch (VT.SimpleTy) {
1113
  case MVT::i32: return fastEmit_ISD_TRUNCATE_MVT_i32_r(RetVT, Op0, Op0IsKill);
1114
  case MVT::i64: return fastEmit_ISD_TRUNCATE_MVT_i64_r(RetVT, Op0, Op0IsKill);
1115
  default: return 0;
1116
  }
1117
}
1118
1119
// FastEmit functions for ISD::UINT_TO_FP.
1120
1121
0
unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
1122
0
  if ((PPCSubTarget->hasSPE())) {
1123
0
    return fastEmitInst_r(PPC::EFSCFUI, &PPC::SPE4RCRegClass, Op0, Op0IsKill);
1124
0
  }
1125
0
  return 0;
1126
0
}
1127
1128
0
unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
1129
0
  if ((PPCSubTarget->hasSPE())) {
1130
0
    return fastEmitInst_r(PPC::EFDCFUI, &PPC::SPERCRegClass, Op0, Op0IsKill);
1131
0
  }
1132
0
  return 0;
1133
0
}
1134
1135
unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1136
switch (RetVT.SimpleTy) {
1137
  case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill);
1138
  case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0, Op0IsKill);
1139
  default: return 0;
1140
}
1141
}
1142
1143
0
unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1144
0
  if (RetVT.SimpleTy != MVT::v4f32)
1145
0
    return 0;
1146
0
  if ((PPCSubTarget->hasVSX())) {
1147
0
    return fastEmitInst_r(PPC::XVCVUXWSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
1148
0
  }
1149
0
  if ((PPCSubTarget->hasAltivec())) {
1150
0
    return fastEmitInst_r(PPC::VCFUX_0, &PPC::VRRCRegClass, Op0, Op0IsKill);
1151
0
  }
1152
0
  return 0;
1153
0
}
1154
1155
0
unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1156
0
  if (RetVT.SimpleTy != MVT::v2f64)
1157
0
    return 0;
1158
0
  if ((PPCSubTarget->hasVSX())) {
1159
0
    return fastEmitInst_r(PPC::XVCVUXDDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
1160
0
  }
1161
0
  return 0;
1162
0
}
1163
1164
unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1165
  switch (VT.SimpleTy) {
1166
  case MVT::i32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_r(RetVT, Op0, Op0IsKill);
1167
  case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
1168
  case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
1169
  default: return 0;
1170
  }
1171
}
1172
1173
// FastEmit functions for PPCISD::FCFID.
1174
1175
0
unsigned fastEmit_PPCISD_FCFID_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1176
0
  if (RetVT.SimpleTy != MVT::f64)
1177
0
    return 0;
1178
0
  if ((PPCSubTarget->hasVSX())) {
1179
0
    return fastEmitInst_r(PPC::XSCVSXDDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
1180
0
  }
1181
0
  return fastEmitInst_r(PPC::FCFID, &PPC::F8RCRegClass, Op0, Op0IsKill);
1182
0
}
1183
1184
unsigned fastEmit_PPCISD_FCFID_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1185
  switch (VT.SimpleTy) {
1186
  case MVT::f64: return fastEmit_PPCISD_FCFID_MVT_f64_r(RetVT, Op0, Op0IsKill);
1187
  default: return 0;
1188
  }
1189
}
1190
1191
// FastEmit functions for PPCISD::FCFIDS.
1192
1193
0
unsigned fastEmit_PPCISD_FCFIDS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1194
0
  if (RetVT.SimpleTy != MVT::f32)
1195
0
    return 0;
1196
0
  if ((PPCSubTarget->hasP8Vector())) {
1197
0
    return fastEmitInst_r(PPC::XSCVSXDSP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
1198
0
  }
1199
0
  return fastEmitInst_r(PPC::FCFIDS, &PPC::F4RCRegClass, Op0, Op0IsKill);
1200
0
}
1201
1202
unsigned fastEmit_PPCISD_FCFIDS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1203
  switch (VT.SimpleTy) {
1204
  case MVT::f64: return fastEmit_PPCISD_FCFIDS_MVT_f64_r(RetVT, Op0, Op0IsKill);
1205
  default: return 0;
1206
  }
1207
}
1208
1209
// FastEmit functions for PPCISD::FCFIDU.
1210
1211
0
unsigned fastEmit_PPCISD_FCFIDU_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1212
0
  if (RetVT.SimpleTy != MVT::f64)
1213
0
    return 0;
1214
0
  if ((PPCSubTarget->hasVSX())) {
1215
0
    return fastEmitInst_r(PPC::XSCVUXDDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
1216
0
  }
1217
0
  return fastEmitInst_r(PPC::FCFIDU, &PPC::F8RCRegClass, Op0, Op0IsKill);
1218
0
}
1219
1220
unsigned fastEmit_PPCISD_FCFIDU_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1221
  switch (VT.SimpleTy) {
1222
  case MVT::f64: return fastEmit_PPCISD_FCFIDU_MVT_f64_r(RetVT, Op0, Op0IsKill);
1223
  default: return 0;
1224
  }
1225
}
1226
1227
// FastEmit functions for PPCISD::FCFIDUS.
1228
1229
0
unsigned fastEmit_PPCISD_FCFIDUS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1230
0
  if (RetVT.SimpleTy != MVT::f32)
1231
0
    return 0;
1232
0
  if ((PPCSubTarget->hasP8Vector())) {
1233
0
    return fastEmitInst_r(PPC::XSCVUXDSP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
1234
0
  }
1235
0
  return fastEmitInst_r(PPC::FCFIDUS, &PPC::F4RCRegClass, Op0, Op0IsKill);
1236
0
}
1237
1238
unsigned fastEmit_PPCISD_FCFIDUS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1239
  switch (VT.SimpleTy) {
1240
  case MVT::f64: return fastEmit_PPCISD_FCFIDUS_MVT_f64_r(RetVT, Op0, Op0IsKill);
1241
  default: return 0;
1242
  }
1243
}
1244
1245
// FastEmit functions for PPCISD::FCTIDUZ.
1246
1247
0
unsigned fastEmit_PPCISD_FCTIDUZ_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1248
0
  if (RetVT.SimpleTy != MVT::f32)
1249
0
    return 0;
1250
0
  if ((PPCSubTarget->hasVSX())) {
1251
0
    return fastEmitInst_r(PPC::XSCVDPUXDSs, &PPC::VSSRCRegClass, Op0, Op0IsKill);
1252
0
  }
1253
0
  return 0;
1254
0
}
1255
1256
0
unsigned fastEmit_PPCISD_FCTIDUZ_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1257
0
  if (RetVT.SimpleTy != MVT::f64)
1258
0
    return 0;
1259
0
  if ((PPCSubTarget->hasVSX())) {
1260
0
    return fastEmitInst_r(PPC::XSCVDPUXDS, &PPC::VSFRCRegClass, Op0, Op0IsKill);
1261
0
  }
1262
0
  return fastEmitInst_r(PPC::FCTIDUZ, &PPC::F8RCRegClass, Op0, Op0IsKill);
1263
0
}
1264
1265
unsigned fastEmit_PPCISD_FCTIDUZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1266
  switch (VT.SimpleTy) {
1267
  case MVT::f32: return fastEmit_PPCISD_FCTIDUZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
1268
  case MVT::f64: return fastEmit_PPCISD_FCTIDUZ_MVT_f64_r(RetVT, Op0, Op0IsKill);
1269
  default: return 0;
1270
  }
1271
}
1272
1273
// FastEmit functions for PPCISD::FCTIDZ.
1274
1275
0
unsigned fastEmit_PPCISD_FCTIDZ_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1276
0
  if (RetVT.SimpleTy != MVT::f32)
1277
0
    return 0;
1278
0
  if ((PPCSubTarget->hasVSX())) {
1279
0
    return fastEmitInst_r(PPC::XSCVDPSXDSs, &PPC::VSSRCRegClass, Op0, Op0IsKill);
1280
0
  }
1281
0
  return 0;
1282
0
}
1283
1284
0
unsigned fastEmit_PPCISD_FCTIDZ_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1285
0
  if (RetVT.SimpleTy != MVT::f64)
1286
0
    return 0;
1287
0
  if ((PPCSubTarget->hasVSX())) {
1288
0
    return fastEmitInst_r(PPC::XSCVDPSXDS, &PPC::VSFRCRegClass, Op0, Op0IsKill);
1289
0
  }
1290
0
  return fastEmitInst_r(PPC::FCTIDZ, &PPC::F8RCRegClass, Op0, Op0IsKill);
1291
0
}
1292
1293
unsigned fastEmit_PPCISD_FCTIDZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1294
  switch (VT.SimpleTy) {
1295
  case MVT::f32: return fastEmit_PPCISD_FCTIDZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
1296
  case MVT::f64: return fastEmit_PPCISD_FCTIDZ_MVT_f64_r(RetVT, Op0, Op0IsKill);
1297
  default: return 0;
1298
  }
1299
}
1300
1301
// FastEmit functions for PPCISD::FCTIWUZ.
1302
1303
0
unsigned fastEmit_PPCISD_FCTIWUZ_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1304
0
  if (RetVT.SimpleTy != MVT::f32)
1305
0
    return 0;
1306
0
  if ((PPCSubTarget->hasVSX())) {
1307
0
    return fastEmitInst_r(PPC::XSCVDPUXWSs, &PPC::VSSRCRegClass, Op0, Op0IsKill);
1308
0
  }
1309
0
  return 0;
1310
0
}
1311
1312
0
unsigned fastEmit_PPCISD_FCTIWUZ_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1313
0
  if (RetVT.SimpleTy != MVT::f64)
1314
0
    return 0;
1315
0
  if ((PPCSubTarget->hasVSX())) {
1316
0
    return fastEmitInst_r(PPC::XSCVDPUXWS, &PPC::VSFRCRegClass, Op0, Op0IsKill);
1317
0
  }
1318
0
  return fastEmitInst_r(PPC::FCTIWUZ, &PPC::F8RCRegClass, Op0, Op0IsKill);
1319
0
}
1320
1321
unsigned fastEmit_PPCISD_FCTIWUZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1322
  switch (VT.SimpleTy) {
1323
  case MVT::f32: return fastEmit_PPCISD_FCTIWUZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
1324
  case MVT::f64: return fastEmit_PPCISD_FCTIWUZ_MVT_f64_r(RetVT, Op0, Op0IsKill);
1325
  default: return 0;
1326
  }
1327
}
1328
1329
// FastEmit functions for PPCISD::FCTIWZ.
1330
1331
0
unsigned fastEmit_PPCISD_FCTIWZ_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1332
0
  if (RetVT.SimpleTy != MVT::f32)
1333
0
    return 0;
1334
0
  if ((PPCSubTarget->hasVSX())) {
1335
0
    return fastEmitInst_r(PPC::XSCVDPSXWSs, &PPC::VSSRCRegClass, Op0, Op0IsKill);
1336
0
  }
1337
0
  return 0;
1338
0
}
1339
1340
0
unsigned fastEmit_PPCISD_FCTIWZ_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1341
0
  if (RetVT.SimpleTy != MVT::f64)
1342
0
    return 0;
1343
0
  if ((PPCSubTarget->hasVSX())) {
1344
0
    return fastEmitInst_r(PPC::XSCVDPSXWS, &PPC::VSFRCRegClass, Op0, Op0IsKill);
1345
0
  }
1346
0
  if ((PPCSubTarget->hasFPU())) {
1347
0
    return fastEmitInst_r(PPC::FCTIWZ, &PPC::F8RCRegClass, Op0, Op0IsKill);
1348
0
  }
1349
0
  return 0;
1350
0
}
1351
1352
unsigned fastEmit_PPCISD_FCTIWZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1353
  switch (VT.SimpleTy) {
1354
  case MVT::f32: return fastEmit_PPCISD_FCTIWZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
1355
  case MVT::f64: return fastEmit_PPCISD_FCTIWZ_MVT_f64_r(RetVT, Op0, Op0IsKill);
1356
  default: return 0;
1357
  }
1358
}
1359
1360
// FastEmit functions for PPCISD::FRE.
1361
1362
0
unsigned fastEmit_PPCISD_FRE_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1363
0
  if (RetVT.SimpleTy != MVT::f32)
1364
0
    return 0;
1365
0
  if ((PPCSubTarget->hasP8Vector())) {
1366
0
    return fastEmitInst_r(PPC::XSRESP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
1367
0
  }
1368
0
  if ((PPCSubTarget->hasFPU())) {
1369
0
    return fastEmitInst_r(PPC::FRES, &PPC::F4RCRegClass, Op0, Op0IsKill);
1370
0
  }
1371
0
  return 0;
1372
0
}
1373
1374
0
unsigned fastEmit_PPCISD_FRE_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1375
0
  if (RetVT.SimpleTy != MVT::f64)
1376
0
    return 0;
1377
0
  if ((PPCSubTarget->hasVSX())) {
1378
0
    return fastEmitInst_r(PPC::XSREDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
1379
0
  }
1380
0
  if ((PPCSubTarget->hasFPU())) {
1381
0
    return fastEmitInst_r(PPC::FRE, &PPC::F8RCRegClass, Op0, Op0IsKill);
1382
0
  }
1383
0
  return 0;
1384
0
}
1385
1386
0
unsigned fastEmit_PPCISD_FRE_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1387
0
  if (RetVT.SimpleTy != MVT::v4f32)
1388
0
    return 0;
1389
0
  if ((PPCSubTarget->hasVSX())) {
1390
0
    return fastEmitInst_r(PPC::XVRESP, &PPC::VSRCRegClass, Op0, Op0IsKill);
1391
0
  }
1392
0
  if ((PPCSubTarget->hasAltivec())) {
1393
0
    return fastEmitInst_r(PPC::VREFP, &PPC::VRRCRegClass, Op0, Op0IsKill);
1394
0
  }
1395
0
  if ((PPCSubTarget->hasQPX())) {
1396
0
    return fastEmitInst_r(PPC::QVFRESs, &PPC::QSRCRegClass, Op0, Op0IsKill);
1397
0
  }
1398
0
  return 0;
1399
0
}
1400
1401
0
unsigned fastEmit_PPCISD_FRE_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1402
0
  if (RetVT.SimpleTy != MVT::v2f64)
1403
0
    return 0;
1404
0
  if ((PPCSubTarget->hasVSX())) {
1405
0
    return fastEmitInst_r(PPC::XVREDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
1406
0
  }
1407
0
  return 0;
1408
0
}
1409
1410
0
unsigned fastEmit_PPCISD_FRE_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1411
0
  if (RetVT.SimpleTy != MVT::v4f64)
1412
0
    return 0;
1413
0
  if ((PPCSubTarget->hasQPX())) {
1414
0
    return fastEmitInst_r(PPC::QVFRE, &PPC::QFRCRegClass, Op0, Op0IsKill);
1415
0
  }
1416
0
  return 0;
1417
0
}
1418
1419
unsigned fastEmit_PPCISD_FRE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1420
  switch (VT.SimpleTy) {
1421
  case MVT::f32: return fastEmit_PPCISD_FRE_MVT_f32_r(RetVT, Op0, Op0IsKill);
1422
  case MVT::f64: return fastEmit_PPCISD_FRE_MVT_f64_r(RetVT, Op0, Op0IsKill);
1423
  case MVT::v4f32: return fastEmit_PPCISD_FRE_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
1424
  case MVT::v2f64: return fastEmit_PPCISD_FRE_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
1425
  case MVT::v4f64: return fastEmit_PPCISD_FRE_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
1426
  default: return 0;
1427
  }
1428
}
1429
1430
// FastEmit functions for PPCISD::FRSQRTE.
1431
1432
0
unsigned fastEmit_PPCISD_FRSQRTE_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1433
0
  if (RetVT.SimpleTy != MVT::f32)
1434
0
    return 0;
1435
0
  if ((PPCSubTarget->hasP8Vector())) {
1436
0
    return fastEmitInst_r(PPC::XSRSQRTESP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
1437
0
  }
1438
0
  if ((PPCSubTarget->hasFPU())) {
1439
0
    return fastEmitInst_r(PPC::FRSQRTES, &PPC::F4RCRegClass, Op0, Op0IsKill);
1440
0
  }
1441
0
  return 0;
1442
0
}
1443
1444
0
unsigned fastEmit_PPCISD_FRSQRTE_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1445
0
  if (RetVT.SimpleTy != MVT::f64)
1446
0
    return 0;
1447
0
  if ((PPCSubTarget->hasVSX())) {
1448
0
    return fastEmitInst_r(PPC::XSRSQRTEDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
1449
0
  }
1450
0
  if ((PPCSubTarget->hasFPU())) {
1451
0
    return fastEmitInst_r(PPC::FRSQRTE, &PPC::F8RCRegClass, Op0, Op0IsKill);
1452
0
  }
1453
0
  return 0;
1454
0
}
1455
1456
0
unsigned fastEmit_PPCISD_FRSQRTE_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1457
0
  if (RetVT.SimpleTy != MVT::v4f32)
1458
0
    return 0;
1459
0
  if ((PPCSubTarget->hasVSX())) {
1460
0
    return fastEmitInst_r(PPC::XVRSQRTESP, &PPC::VSRCRegClass, Op0, Op0IsKill);
1461
0
  }
1462
0
  if ((PPCSubTarget->hasAltivec())) {
1463
0
    return fastEmitInst_r(PPC::VRSQRTEFP, &PPC::VRRCRegClass, Op0, Op0IsKill);
1464
0
  }
1465
0
  if ((PPCSubTarget->hasQPX())) {
1466
0
    return fastEmitInst_r(PPC::QVFRSQRTESs, &PPC::QSRCRegClass, Op0, Op0IsKill);
1467
0
  }
1468
0
  return 0;
1469
0
}
1470
1471
0
unsigned fastEmit_PPCISD_FRSQRTE_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1472
0
  if (RetVT.SimpleTy != MVT::v2f64)
1473
0
    return 0;
1474
0
  if ((PPCSubTarget->hasVSX())) {
1475
0
    return fastEmitInst_r(PPC::XVRSQRTEDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
1476
0
  }
1477
0
  return 0;
1478
0
}
1479
1480
0
unsigned fastEmit_PPCISD_FRSQRTE_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1481
0
  if (RetVT.SimpleTy != MVT::v4f64)
1482
0
    return 0;
1483
0
  if ((PPCSubTarget->hasQPX())) {
1484
0
    return fastEmitInst_r(PPC::QVFRSQRTE, &PPC::QFRCRegClass, Op0, Op0IsKill);
1485
0
  }
1486
0
  return 0;
1487
0
}
1488
1489
unsigned fastEmit_PPCISD_FRSQRTE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1490
  switch (VT.SimpleTy) {
1491
  case MVT::f32: return fastEmit_PPCISD_FRSQRTE_MVT_f32_r(RetVT, Op0, Op0IsKill);
1492
  case MVT::f64: return fastEmit_PPCISD_FRSQRTE_MVT_f64_r(RetVT, Op0, Op0IsKill);
1493
  case MVT::v4f32: return fastEmit_PPCISD_FRSQRTE_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
1494
  case MVT::v2f64: return fastEmit_PPCISD_FRSQRTE_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
1495
  case MVT::v4f64: return fastEmit_PPCISD_FRSQRTE_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
1496
  default: return 0;
1497
  }
1498
}
1499
1500
// FastEmit functions for PPCISD::MFVSR.
1501
1502
0
unsigned fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i32_r(unsigned Op0, bool Op0IsKill) {
1503
0
  if ((PPCSubTarget->hasDirectMove())) {
1504
0
    return fastEmitInst_r(PPC::MFVSRWZ, &PPC::GPRCRegClass, Op0, Op0IsKill);
1505
0
  }
1506
0
  return 0;
1507
0
}
1508
1509
0
unsigned fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i64_r(unsigned Op0, bool Op0IsKill) {
1510
0
  if ((PPCSubTarget->hasDirectMove())) {
1511
0
    return fastEmitInst_r(PPC::MFVSRD, &PPC::G8RCRegClass, Op0, Op0IsKill);
1512
0
  }
1513
0
  return 0;
1514
0
}
1515
1516
unsigned fastEmit_PPCISD_MFVSR_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1517
switch (RetVT.SimpleTy) {
1518
  case MVT::i32: return fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i32_r(Op0, Op0IsKill);
1519
  case MVT::i64: return fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i64_r(Op0, Op0IsKill);
1520
  default: return 0;
1521
}
1522
}
1523
1524
unsigned fastEmit_PPCISD_MFVSR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1525
  switch (VT.SimpleTy) {
1526
  case MVT::f64: return fastEmit_PPCISD_MFVSR_MVT_f64_r(RetVT, Op0, Op0IsKill);
1527
  default: return 0;
1528
  }
1529
}
1530
1531
// FastEmit functions for PPCISD::MTCTR.
1532
1533
0
unsigned fastEmit_PPCISD_MTCTR_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1534
0
  if (RetVT.SimpleTy != MVT::isVoid)
1535
0
    return 0;
1536
0
  return fastEmitInst_r(PPC::MTCTR, &PPC::GPRCRegClass, Op0, Op0IsKill);
1537
0
}
1538
1539
0
unsigned fastEmit_PPCISD_MTCTR_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1540
0
  if (RetVT.SimpleTy != MVT::isVoid)
1541
0
    return 0;
1542
0
  return fastEmitInst_r(PPC::MTCTR8, &PPC::G8RCRegClass, Op0, Op0IsKill);
1543
0
}
1544
1545
unsigned fastEmit_PPCISD_MTCTR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1546
  switch (VT.SimpleTy) {
1547
  case MVT::i32: return fastEmit_PPCISD_MTCTR_MVT_i32_r(RetVT, Op0, Op0IsKill);
1548
  case MVT::i64: return fastEmit_PPCISD_MTCTR_MVT_i64_r(RetVT, Op0, Op0IsKill);
1549
  default: return 0;
1550
  }
1551
}
1552
1553
// FastEmit functions for PPCISD::MTVSRA.
1554
1555
0
unsigned fastEmit_PPCISD_MTVSRA_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1556
0
  if (RetVT.SimpleTy != MVT::f64)
1557
0
    return 0;
1558
0
  if ((PPCSubTarget->hasDirectMove())) {
1559
0
    return fastEmitInst_r(PPC::MTVSRWA, &PPC::VSFRCRegClass, Op0, Op0IsKill);
1560
0
  }
1561
0
  return 0;
1562
0
}
1563
1564
0
unsigned fastEmit_PPCISD_MTVSRA_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1565
0
  if (RetVT.SimpleTy != MVT::f64)
1566
0
    return 0;
1567
0
  if ((PPCSubTarget->hasDirectMove())) {
1568
0
    return fastEmitInst_r(PPC::MTVSRD, &PPC::VSFRCRegClass, Op0, Op0IsKill);
1569
0
  }
1570
0
  return 0;
1571
0
}
1572
1573
unsigned fastEmit_PPCISD_MTVSRA_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1574
  switch (VT.SimpleTy) {
1575
  case MVT::i32: return fastEmit_PPCISD_MTVSRA_MVT_i32_r(RetVT, Op0, Op0IsKill);
1576
  case MVT::i64: return fastEmit_PPCISD_MTVSRA_MVT_i64_r(RetVT, Op0, Op0IsKill);
1577
  default: return 0;
1578
  }
1579
}
1580
1581
// FastEmit functions for PPCISD::MTVSRZ.
1582
1583
0
unsigned fastEmit_PPCISD_MTVSRZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1584
0
  if (RetVT.SimpleTy != MVT::f64)
1585
0
    return 0;
1586
0
  if ((PPCSubTarget->hasDirectMove())) {
1587
0
    return fastEmitInst_r(PPC::MTVSRWZ, &PPC::VSFRCRegClass, Op0, Op0IsKill);
1588
0
  }
1589
0
  return 0;
1590
0
}
1591
1592
unsigned fastEmit_PPCISD_MTVSRZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1593
  switch (VT.SimpleTy) {
1594
  case MVT::i32: return fastEmit_PPCISD_MTVSRZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
1595
  default: return 0;
1596
  }
1597
}
1598
1599
// FastEmit functions for PPCISD::SExtVElems.
1600
1601
0
unsigned fastEmit_PPCISD_SExtVElems_MVT_v16i8_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
1602
0
  if ((PPCSubTarget->hasP9Altivec())) {
1603
0
    return fastEmitInst_r(PPC::VEXTSB2W, &PPC::VRRCRegClass, Op0, Op0IsKill);
1604
0
  }
1605
0
  return 0;
1606
0
}
1607
1608
0
unsigned fastEmit_PPCISD_SExtVElems_MVT_v16i8_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
1609
0
  if ((PPCSubTarget->hasP9Altivec())) {
1610
0
    return fastEmitInst_r(PPC::VEXTSB2D, &PPC::VRRCRegClass, Op0, Op0IsKill);
1611
0
  }
1612
0
  return 0;
1613
0
}
1614
1615
unsigned fastEmit_PPCISD_SExtVElems_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1616
switch (RetVT.SimpleTy) {
1617
  case MVT::v4i32: return fastEmit_PPCISD_SExtVElems_MVT_v16i8_MVT_v4i32_r(Op0, Op0IsKill);
1618
  case MVT::v2i64: return fastEmit_PPCISD_SExtVElems_MVT_v16i8_MVT_v2i64_r(Op0, Op0IsKill);
1619
  default: return 0;
1620
}
1621
}
1622
1623
0
unsigned fastEmit_PPCISD_SExtVElems_MVT_v8i16_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
1624
0
  if ((PPCSubTarget->hasP9Altivec())) {
1625
0
    return fastEmitInst_r(PPC::VEXTSH2W, &PPC::VRRCRegClass, Op0, Op0IsKill);
1626
0
  }
1627
0
  return 0;
1628
0
}
1629
1630
0
unsigned fastEmit_PPCISD_SExtVElems_MVT_v8i16_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
1631
0
  if ((PPCSubTarget->hasP9Altivec())) {
1632
0
    return fastEmitInst_r(PPC::VEXTSH2D, &PPC::VRRCRegClass, Op0, Op0IsKill);
1633
0
  }
1634
0
  return 0;
1635
0
}
1636
1637
unsigned fastEmit_PPCISD_SExtVElems_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1638
switch (RetVT.SimpleTy) {
1639
  case MVT::v4i32: return fastEmit_PPCISD_SExtVElems_MVT_v8i16_MVT_v4i32_r(Op0, Op0IsKill);
1640
  case MVT::v2i64: return fastEmit_PPCISD_SExtVElems_MVT_v8i16_MVT_v2i64_r(Op0, Op0IsKill);
1641
  default: return 0;
1642
}
1643
}
1644
1645
0
unsigned fastEmit_PPCISD_SExtVElems_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1646
0
  if (RetVT.SimpleTy != MVT::v2i64)
1647
0
    return 0;
1648
0
  if ((PPCSubTarget->hasP9Altivec())) {
1649
0
    return fastEmitInst_r(PPC::VEXTSW2D, &PPC::VRRCRegClass, Op0, Op0IsKill);
1650
0
  }
1651
0
  return 0;
1652
0
}
1653
1654
unsigned fastEmit_PPCISD_SExtVElems_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1655
  switch (VT.SimpleTy) {
1656
  case MVT::v16i8: return fastEmit_PPCISD_SExtVElems_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
1657
  case MVT::v8i16: return fastEmit_PPCISD_SExtVElems_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
1658
  case MVT::v4i32: return fastEmit_PPCISD_SExtVElems_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
1659
  default: return 0;
1660
  }
1661
}
1662
1663
// FastEmit functions for PPCISD::XXREVERSE.
1664
1665
0
unsigned fastEmit_PPCISD_XXREVERSE_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1666
0
  if (RetVT.SimpleTy != MVT::v4i32)
1667
0
    return 0;
1668
0
  if ((PPCSubTarget->hasP9Vector())) {
1669
0
    return fastEmitInst_r(PPC::XXBRW, &PPC::VSRCRegClass, Op0, Op0IsKill);
1670
0
  }
1671
0
  return 0;
1672
0
}
1673
1674
0
unsigned fastEmit_PPCISD_XXREVERSE_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1675
0
  if (RetVT.SimpleTy != MVT::v2i64)
1676
0
    return 0;
1677
0
  if ((PPCSubTarget->hasP9Vector())) {
1678
0
    return fastEmitInst_r(PPC::XXBRD, &PPC::VSRCRegClass, Op0, Op0IsKill);
1679
0
  }
1680
0
  return 0;
1681
0
}
1682
1683
unsigned fastEmit_PPCISD_XXREVERSE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1684
  switch (VT.SimpleTy) {
1685
  case MVT::v4i32: return fastEmit_PPCISD_XXREVERSE_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
1686
  case MVT::v2i64: return fastEmit_PPCISD_XXREVERSE_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
1687
  default: return 0;
1688
  }
1689
}
1690
1691
// Top-level FastEmit function.
1692
1693
42
unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill) override {
1694
42
  switch (Opcode) {
1695
42
  
case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0, Op0IsKill)1
;
1696
42
  
case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill)0
;
1697
42
  
case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill)0
;
1698
42
  
case ISD::CTTZ: return fastEmit_ISD_CTTZ_r(VT, RetVT, Op0, Op0IsKill)0
;
1699
42
  
case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill)0
;
1700
42
  
case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0, Op0IsKill)0
;
1701
42
  
case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0, Op0IsKill)0
;
1702
42
  
case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0, Op0IsKill)0
;
1703
42
  
case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill)0
;
1704
42
  
case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill)0
;
1705
42
  
case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill)0
;
1706
42
  
case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill)19
;
1707
42
  
case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill)0
;
1708
42
  
case ISD::FROUND: return fastEmit_ISD_FROUND_r(VT, RetVT, Op0, Op0IsKill)0
;
1709
42
  
case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill)0
;
1710
42
  
case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0, Op0IsKill)0
;
1711
42
  
case ISD::SCALAR_TO_VECTOR: return fastEmit_ISD_SCALAR_TO_VECTOR_r(VT, RetVT, Op0, Op0IsKill)0
;
1712
42
  
case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill)5
;
1713
42
  
case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill)15
;
1714
42
  
case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0, Op0IsKill)0
;
1715
42
  
case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill)0
;
1716
42
  
case PPCISD::FCFID: return fastEmit_PPCISD_FCFID_r(VT, RetVT, Op0, Op0IsKill)0
;
1717
42
  
case PPCISD::FCFIDS: return fastEmit_PPCISD_FCFIDS_r(VT, RetVT, Op0, Op0IsKill)0
;
1718
42
  
case PPCISD::FCFIDU: return fastEmit_PPCISD_FCFIDU_r(VT, RetVT, Op0, Op0IsKill)0
;
1719
42
  
case PPCISD::FCFIDUS: return fastEmit_PPCISD_FCFIDUS_r(VT, RetVT, Op0, Op0IsKill)0
;
1720
42
  
case PPCISD::FCTIDUZ: return fastEmit_PPCISD_FCTIDUZ_r(VT, RetVT, Op0, Op0IsKill)0
;
1721
42
  
case PPCISD::FCTIDZ: return fastEmit_PPCISD_FCTIDZ_r(VT, RetVT, Op0, Op0IsKill)0
;
1722
42
  
case PPCISD::FCTIWUZ: return fastEmit_PPCISD_FCTIWUZ_r(VT, RetVT, Op0, Op0IsKill)0
;
1723
42
  
case PPCISD::FCTIWZ: return fastEmit_PPCISD_FCTIWZ_r(VT, RetVT, Op0, Op0IsKill)0
;
1724
42
  
case PPCISD::FRE: return fastEmit_PPCISD_FRE_r(VT, RetVT, Op0, Op0IsKill)0
;
1725
42
  
case PPCISD::FRSQRTE: return fastEmit_PPCISD_FRSQRTE_r(VT, RetVT, Op0, Op0IsKill)0
;
1726
42
  
case PPCISD::MFVSR: return fastEmit_PPCISD_MFVSR_r(VT, RetVT, Op0, Op0IsKill)0
;
1727
42
  
case PPCISD::MTCTR: return fastEmit_PPCISD_MTCTR_r(VT, RetVT, Op0, Op0IsKill)0
;
1728
42
  
case PPCISD::MTVSRA: return fastEmit_PPCISD_MTVSRA_r(VT, RetVT, Op0, Op0IsKill)0
;
1729
42
  
case PPCISD::MTVSRZ: return fastEmit_PPCISD_MTVSRZ_r(VT, RetVT, Op0, Op0IsKill)0
;
1730
42
  
case PPCISD::SExtVElems: return fastEmit_PPCISD_SExtVElems_r(VT, RetVT, Op0, Op0IsKill)0
;
1731
42
  
case PPCISD::XXREVERSE: return fastEmit_PPCISD_XXREVERSE_r(VT, RetVT, Op0, Op0IsKill)0
;
1732
42
  
default: return 02
;
1733
42
  }
1734
42
}
1735
1736
// FastEmit functions for ISD::ADD.
1737
1738
0
unsigned fastEmit_ISD_ADD_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1739
0
  if (RetVT.SimpleTy != MVT::i1)
1740
0
    return 0;
1741
0
  return fastEmitInst_rr(PPC::CRXOR, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1742
0
}
1743
1744
0
unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1745
0
  if (RetVT.SimpleTy != MVT::i32)
1746
0
    return 0;
1747
0
  return fastEmitInst_rr(PPC::ADD4, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1748
0
}
1749
1750
0
unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1751
0
  if (RetVT.SimpleTy != MVT::i64)
1752
0
    return 0;
1753
0
  return fastEmitInst_rr(PPC::ADD8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1754
0
}
1755
1756
0
unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1757
0
  if (RetVT.SimpleTy != MVT::v16i8)
1758
0
    return 0;
1759
0
  if ((PPCSubTarget->hasAltivec())) {
1760
0
    return fastEmitInst_rr(PPC::VADDUBM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1761
0
  }
1762
0
  return 0;
1763
0
}
1764
1765
0
unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1766
0
  if (RetVT.SimpleTy != MVT::v8i16)
1767
0
    return 0;
1768
0
  if ((PPCSubTarget->hasAltivec())) {
1769
0
    return fastEmitInst_rr(PPC::VADDUHM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1770
0
  }
1771
0
  return 0;
1772
0
}
1773
1774
0
unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1775
0
  if (RetVT.SimpleTy != MVT::v4i32)
1776
0
    return 0;
1777
0
  if ((PPCSubTarget->hasAltivec())) {
1778
0
    return fastEmitInst_rr(PPC::VADDUWM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1779
0
  }
1780
0
  return 0;
1781
0
}
1782
1783
1
unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1784
1
  if (RetVT.SimpleTy != MVT::v2i64)
1785
0
    return 0;
1786
1
  if ((PPCSubTarget->hasP8Altivec())) {
1787
0
    return fastEmitInst_rr(PPC::VADDUDM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1788
0
  }
1789
1
  return 0;
1790
1
}
1791
1792
0
unsigned fastEmit_ISD_ADD_MVT_v1i128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1793
0
  if (RetVT.SimpleTy != MVT::v1i128)
1794
0
    return 0;
1795
0
  if ((PPCSubTarget->hasP8Altivec())) {
1796
0
    return fastEmitInst_rr(PPC::VADDUQM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1797
0
  }
1798
0
  return 0;
1799
0
}
1800
1801
1
unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1802
1
  switch (VT.SimpleTy) {
1803
1
  
case MVT::i1: return fastEmit_ISD_ADD_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1804
1
  
case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1805
1
  
case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1806
1
  
case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1807
1
  
case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1808
1
  
case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1809
1
  case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1810
1
  
case MVT::v1i128: return fastEmit_ISD_ADD_MVT_v1i128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1811
1
  
default: return 00
;
1812
1
  }
1813
1
}
1814
1815
// FastEmit functions for ISD::ADDC.
1816
1817
0
unsigned fastEmit_ISD_ADDC_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1818
0
  if (RetVT.SimpleTy != MVT::i32)
1819
0
    return 0;
1820
0
  return fastEmitInst_rr(PPC::ADDC, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1821
0
}
1822
1823
0
unsigned fastEmit_ISD_ADDC_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1824
0
  if (RetVT.SimpleTy != MVT::i64)
1825
0
    return 0;
1826
0
  return fastEmitInst_rr(PPC::ADDC8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1827
0
}
1828
1829
unsigned fastEmit_ISD_ADDC_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1830
  switch (VT.SimpleTy) {
1831
  case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1832
  case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1833
  default: return 0;
1834
  }
1835
}
1836
1837
// FastEmit functions for ISD::ADDE.
1838
1839
0
unsigned fastEmit_ISD_ADDE_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1840
0
  if (RetVT.SimpleTy != MVT::i32)
1841
0
    return 0;
1842
0
  return fastEmitInst_rr(PPC::ADDE, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1843
0
}
1844
1845
0
unsigned fastEmit_ISD_ADDE_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1846
0
  if (RetVT.SimpleTy != MVT::i64)
1847
0
    return 0;
1848
0
  return fastEmitInst_rr(PPC::ADDE8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1849
0
}
1850
1851
unsigned fastEmit_ISD_ADDE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1852
  switch (VT.SimpleTy) {
1853
  case MVT::i32: return fastEmit_ISD_ADDE_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1854
  case MVT::i64: return fastEmit_ISD_ADDE_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1855
  default: return 0;
1856
  }
1857
}
1858
1859
// FastEmit functions for ISD::AND.
1860
1861
0
unsigned fastEmit_ISD_AND_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1862
0
  if (RetVT.SimpleTy != MVT::i1)
1863
0
    return 0;
1864
0
  return fastEmitInst_rr(PPC::CRAND, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1865
0
}
1866
1867
0
unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1868
0
  if (RetVT.SimpleTy != MVT::i32)
1869
0
    return 0;
1870
0
  return fastEmitInst_rr(PPC::AND, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1871
0
}
1872
1873
1
unsigned fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1874
1
  if (RetVT.SimpleTy != MVT::i64)
1875
0
    return 0;
1876
1
  return fastEmitInst_rr(PPC::AND8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1877
1
}
1878
1879
2
unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1880
2
  if (RetVT.SimpleTy != MVT::v4i32)
1881
0
    return 0;
1882
2
  if ((PPCSubTarget->hasVSX())) {
1883
2
    return fastEmitInst_rr(PPC::XXLAND, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1884
2
  }
1885
0
  if ((PPCSubTarget->hasAltivec())) {
1886
0
    return fastEmitInst_rr(PPC::VAND, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1887
0
  }
1888
0
  return 0;
1889
0
}
1890
1891
8
unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1892
8
  switch (VT.SimpleTy) {
1893
8
  
case MVT::i1: return fastEmit_ISD_AND_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1894
8
  
case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1895
8
  
case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)1
;
1896
8
  
case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)2
;
1897
8
  
default: return 05
;
1898
8
  }
1899
8
}
1900
1901
// FastEmit functions for ISD::BUILD_VECTOR.
1902
1903
0
unsigned fastEmit_ISD_BUILD_VECTOR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1904
0
  if (RetVT.SimpleTy != MVT::v2i64)
1905
0
    return 0;
1906
0
  if ((PPCSubTarget->hasDirectMove()) && (!PPCSubTarget->isLittleEndian()) && (PPCSubTarget->isISA3_0())) {
1907
0
    return fastEmitInst_rr(PPC::MTVSRDD, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1908
0
  }
1909
0
  return 0;
1910
0
}
1911
1912
unsigned fastEmit_ISD_BUILD_VECTOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1913
  switch (VT.SimpleTy) {
1914
  case MVT::i64: return fastEmit_ISD_BUILD_VECTOR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1915
  default: return 0;
1916
  }
1917
}
1918
1919
// FastEmit functions for ISD::FADD.
1920
1921
2
unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1922
2
  if (RetVT.SimpleTy != MVT::f32)
1923
0
    return 0;
1924
2
  if ((PPCSubTarget->hasP8Vector())) {
1925
0
    return fastEmitInst_rr(PPC::XSADDSP, &PPC::VSSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1926
0
  }
1927
2
  if ((PPCSubTarget->hasSPE())) {
1928
0
    return fastEmitInst_rr(PPC::EFSADD, &PPC::SPE4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1929
0
  }
1930
2
  if ((PPCSubTarget->hasFPU())) {
1931
2
    return fastEmitInst_rr(PPC::FADDS, &PPC::F4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1932
2
  }
1933
0
  return 0;
1934
0
}
1935
1936
9
unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1937
9
  if (RetVT.SimpleTy != MVT::f64)
1938
0
    return 0;
1939
9
  if ((PPCSubTarget->hasVSX())) {
1940
7
    return fastEmitInst_rr(PPC::XSADDDP, &PPC::VSFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1941
7
  }
1942
2
  if ((PPCSubTarget->hasSPE())) {
1943
0
    return fastEmitInst_rr(PPC::EFDADD, &PPC::SPERCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1944
0
  }
1945
2
  if ((PPCSubTarget->hasFPU())) {
1946
2
    return fastEmitInst_rr(PPC::FADD, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1947
2
  }
1948
0
  return 0;
1949
0
}
1950
1951
0
unsigned fastEmit_ISD_FADD_MVT_f128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1952
0
  if (RetVT.SimpleTy != MVT::f128)
1953
0
    return 0;
1954
0
  if ((PPCSubTarget->hasP9Vector())) {
1955
0
    return fastEmitInst_rr(PPC::XSADDQP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1956
0
  }
1957
0
  return 0;
1958
0
}
1959
1960
0
unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1961
0
  if (RetVT.SimpleTy != MVT::v4f32)
1962
0
    return 0;
1963
0
  if ((PPCSubTarget->hasVSX())) {
1964
0
    return fastEmitInst_rr(PPC::XVADDSP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1965
0
  }
1966
0
  if ((PPCSubTarget->hasQPX())) {
1967
0
    return fastEmitInst_rr(PPC::QVFADDSs, &PPC::QSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1968
0
  }
1969
0
  if ((PPCSubTarget->hasAltivec())) {
1970
0
    return fastEmitInst_rr(PPC::VADDFP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1971
0
  }
1972
0
  return 0;
1973
0
}
1974
1975
1
unsigned fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1976
1
  if (RetVT.SimpleTy != MVT::v2f64)
1977
0
    return 0;
1978
1
  if ((PPCSubTarget->hasVSX())) {
1979
1
    return fastEmitInst_rr(PPC::XVADDDP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1980
1
  }
1981
0
  return 0;
1982
0
}
1983
1984
0
unsigned fastEmit_ISD_FADD_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1985
0
  if (RetVT.SimpleTy != MVT::v4f64)
1986
0
    return 0;
1987
0
  if ((PPCSubTarget->hasQPX())) {
1988
0
    return fastEmitInst_rr(PPC::QVFADD, &PPC::QFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1989
0
  }
1990
0
  return 0;
1991
0
}
1992
1993
12
unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1994
12
  switch (VT.SimpleTy) {
1995
12
  
case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)2
;
1996
12
  
case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)9
;
1997
12
  
case MVT::f128: return fastEmit_ISD_FADD_MVT_f128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1998
12
  
case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1999
12
  
case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)1
;
2000
12
  
case MVT::v4f64: return fastEmit_ISD_FADD_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2001
12
  
default: return 00
;
2002
12
  }
2003
12
}
2004
2005
// FastEmit functions for ISD::FDIV.
2006
2007
0
unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2008
0
  if (RetVT.SimpleTy != MVT::f32)
2009
0
    return 0;
2010
0
  if ((PPCSubTarget->hasP8Vector())) {
2011
0
    return fastEmitInst_rr(PPC::XSDIVSP, &PPC::VSSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2012
0
  }
2013
0
  if ((PPCSubTarget->hasSPE())) {
2014
0
    return fastEmitInst_rr(PPC::EFSDIV, &PPC::SPE4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2015
0
  }
2016
0
  if ((PPCSubTarget->hasFPU())) {
2017
0
    return fastEmitInst_rr(PPC::FDIVS, &PPC::F4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2018
0
  }
2019
0
  return 0;
2020
0
}
2021
2022
1
unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2023
1
  if (RetVT.SimpleTy != MVT::f64)
2024
0
    return 0;
2025
1
  if ((PPCSubTarget->hasVSX())) {
2026
1
    return fastEmitInst_rr(PPC::XSDIVDP, &PPC::VSFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2027
1
  }
2028
0
  if ((PPCSubTarget->hasSPE())) {
2029
0
    return fastEmitInst_rr(PPC::EFDDIV, &PPC::SPERCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2030
0
  }
2031
0
  if ((PPCSubTarget->hasFPU())) {
2032
0
    return fastEmitInst_rr(PPC::FDIV, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2033
0
  }
2034
0
  return 0;
2035
0
}
2036
2037
0
unsigned fastEmit_ISD_FDIV_MVT_f128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2038
0
  if (RetVT.SimpleTy != MVT::f128)
2039
0
    return 0;
2040
0
  if ((PPCSubTarget->hasP9Vector())) {
2041
0
    return fastEmitInst_rr(PPC::XSDIVQP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2042
0
  }
2043
0
  return 0;
2044
0
}
2045
2046
0
unsigned fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2047
0
  if (RetVT.SimpleTy != MVT::v4f32)
2048
0
    return 0;
2049
0
  if ((PPCSubTarget->hasVSX())) {
2050
0
    return fastEmitInst_rr(PPC::XVDIVSP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2051
0
  }
2052
0
  return 0;
2053
0
}
2054
2055
0
unsigned fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2056
0
  if (RetVT.SimpleTy != MVT::v2f64)
2057
0
    return 0;
2058
0
  if ((PPCSubTarget->hasVSX())) {
2059
0
    return fastEmitInst_rr(PPC::XVDIVDP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2060
0
  }
2061
0
  return 0;
2062
0
}
2063
2064
1
unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2065
1
  switch (VT.SimpleTy) {
2066
1
  
case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2067
1
  case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2068
1
  
case MVT::f128: return fastEmit_ISD_FDIV_MVT_f128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2069
1
  
case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2070
1
  
case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2071
1
  
default: return 00
;
2072
1
  }
2073
1
}
2074
2075
// FastEmit functions for ISD::FMUL.
2076
2077
0
unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2078
0
  if (RetVT.SimpleTy != MVT::f32)
2079
0
    return 0;
2080
0
  if ((PPCSubTarget->hasP8Vector())) {
2081
0
    return fastEmitInst_rr(PPC::XSMULSP, &PPC::VSSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2082
0
  }
2083
0
  if ((PPCSubTarget->hasSPE())) {
2084
0
    return fastEmitInst_rr(PPC::EFSMUL, &PPC::SPE4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2085
0
  }
2086
0
  if ((PPCSubTarget->hasFPU())) {
2087
0
    return fastEmitInst_rr(PPC::FMULS, &PPC::F4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2088
0
  }
2089
0
  return 0;
2090
0
}
2091
2092
1
unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2093
1
  if (RetVT.SimpleTy != MVT::f64)
2094
0
    return 0;
2095
1
  if ((PPCSubTarget->hasVSX())) {
2096
1
    return fastEmitInst_rr(PPC::XSMULDP, &PPC::VSFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2097
1
  }
2098
0
  if ((PPCSubTarget->hasSPE())) {
2099
0
    return fastEmitInst_rr(PPC::EFDMUL, &PPC::SPERCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2100
0
  }
2101
0
  if ((PPCSubTarget->hasFPU())) {
2102
0
    return fastEmitInst_rr(PPC::FMUL, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2103
0
  }
2104
0
  return 0;
2105
0
}
2106
2107
0
unsigned fastEmit_ISD_FMUL_MVT_f128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2108
0
  if (RetVT.SimpleTy != MVT::f128)
2109
0
    return 0;
2110
0
  if ((PPCSubTarget->hasP9Vector())) {
2111
0
    return fastEmitInst_rr(PPC::XSMULQP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2112
0
  }
2113
0
  return 0;
2114
0
}
2115
2116
0
unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2117
0
  if (RetVT.SimpleTy != MVT::v4f32)
2118
0
    return 0;
2119
0
  if ((PPCSubTarget->hasVSX())) {
2120
0
    return fastEmitInst_rr(PPC::XVMULSP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2121
0
  }
2122
0
  if ((PPCSubTarget->hasQPX())) {
2123
0
    return fastEmitInst_rr(PPC::QVFMULSs, &PPC::QSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2124
0
  }
2125
0
  return 0;
2126
0
}
2127
2128
0
unsigned fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2129
0
  if (RetVT.SimpleTy != MVT::v2f64)
2130
0
    return 0;
2131
0
  if ((PPCSubTarget->hasVSX())) {
2132
0
    return fastEmitInst_rr(PPC::XVMULDP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2133
0
  }
2134
0
  return 0;
2135
0
}
2136
2137
0
unsigned fastEmit_ISD_FMUL_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2138
0
  if (RetVT.SimpleTy != MVT::v4f64)
2139
0
    return 0;
2140
0
  if ((PPCSubTarget->hasQPX())) {
2141
0
    return fastEmitInst_rr(PPC::QVFMUL, &PPC::QFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2142
0
  }
2143
0
  return 0;
2144
0
}
2145
2146
1
unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2147
1
  switch (VT.SimpleTy) {
2148
1
  
case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2149
1
  case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2150
1
  
case MVT::f128: return fastEmit_ISD_FMUL_MVT_f128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2151
1
  
case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2152
1
  
case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2153
1
  
case MVT::v4f64: return fastEmit_ISD_FMUL_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2154
1
  
default: return 00
;
2155
1
  }
2156
1
}
2157
2158
// FastEmit functions for ISD::FSUB.
2159
2160
0
unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2161
0
  if (RetVT.SimpleTy != MVT::f32)
2162
0
    return 0;
2163
0
  if ((PPCSubTarget->hasP8Vector())) {
2164
0
    return fastEmitInst_rr(PPC::XSSUBSP, &PPC::VSSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2165
0
  }
2166
0
  if ((PPCSubTarget->hasSPE())) {
2167
0
    return fastEmitInst_rr(PPC::EFSSUB, &PPC::SPE4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2168
0
  }
2169
0
  if ((PPCSubTarget->hasFPU())) {
2170
0
    return fastEmitInst_rr(PPC::FSUBS, &PPC::F4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2171
0
  }
2172
0
  return 0;
2173
0
}
2174
2175
0
unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2176
0
  if (RetVT.SimpleTy != MVT::f64)
2177
0
    return 0;
2178
0
  if ((PPCSubTarget->hasVSX())) {
2179
0
    return fastEmitInst_rr(PPC::XSSUBDP, &PPC::VSFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2180
0
  }
2181
0
  if ((PPCSubTarget->hasSPE())) {
2182
0
    return fastEmitInst_rr(PPC::EFDSUB, &PPC::SPERCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2183
0
  }
2184
0
  if ((PPCSubTarget->hasFPU())) {
2185
0
    return fastEmitInst_rr(PPC::FSUB, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2186
0
  }
2187
0
  return 0;
2188
0
}
2189
2190
0
unsigned fastEmit_ISD_FSUB_MVT_f128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2191
0
  if (RetVT.SimpleTy != MVT::f128)
2192
0
    return 0;
2193
0
  if ((PPCSubTarget->hasP9Vector())) {
2194
0
    return fastEmitInst_rr(PPC::XSSUBQP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2195
0
  }
2196
0
  return 0;
2197
0
}
2198
2199
0
unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2200
0
  if (RetVT.SimpleTy != MVT::v4f32)
2201
0
    return 0;
2202
0
  if ((PPCSubTarget->hasVSX())) {
2203
0
    return fastEmitInst_rr(PPC::XVSUBSP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2204
0
  }
2205
0
  if ((PPCSubTarget->hasQPX())) {
2206
0
    return fastEmitInst_rr(PPC::QVFSUBSs, &PPC::QSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2207
0
  }
2208
0
  if ((PPCSubTarget->hasAltivec())) {
2209
0
    return fastEmitInst_rr(PPC::VSUBFP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2210
0
  }
2211
0
  return 0;
2212
0
}
2213
2214
0
unsigned fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2215
0
  if (RetVT.SimpleTy != MVT::v2f64)
2216
0
    return 0;
2217
0
  if ((PPCSubTarget->hasVSX())) {
2218
0
    return fastEmitInst_rr(PPC::XVSUBDP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2219
0
  }
2220
0
  return 0;
2221
0
}
2222
2223
0
unsigned fastEmit_ISD_FSUB_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2224
0
  if (RetVT.SimpleTy != MVT::v4f64)
2225
0
    return 0;
2226
0
  if ((PPCSubTarget->hasQPX())) {
2227
0
    return fastEmitInst_rr(PPC::QVFSUB, &PPC::QFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2228
0
  }
2229
0
  return 0;
2230
0
}
2231
2232
unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2233
  switch (VT.SimpleTy) {
2234
  case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2235
  case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2236
  case MVT::f128: return fastEmit_ISD_FSUB_MVT_f128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2237
  case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2238
  case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2239
  case MVT::v4f64: return fastEmit_ISD_FSUB_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2240
  default: return 0;
2241
  }
2242
}
2243
2244
// FastEmit functions for ISD::MUL.
2245
2246
0
unsigned fastEmit_ISD_MUL_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2247
0
  if (RetVT.SimpleTy != MVT::i1)
2248
0
    return 0;
2249
0
  return fastEmitInst_rr(PPC::CRAND, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2250
0
}
2251
2252
0
unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2253
0
  if (RetVT.SimpleTy != MVT::i32)
2254
0
    return 0;
2255
0
  return fastEmitInst_rr(PPC::MULLW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2256
0
}
2257
2258
0
unsigned fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2259
0
  if (RetVT.SimpleTy != MVT::i64)
2260
0
    return 0;
2261
0
  return fastEmitInst_rr(PPC::MULLD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2262
0
}
2263
2264
0
unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2265
0
  if (RetVT.SimpleTy != MVT::v4i32)
2266
0
    return 0;
2267
0
  if ((PPCSubTarget->hasP8Altivec())) {
2268
0
    return fastEmitInst_rr(PPC::VMULUWM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2269
0
  }
2270
0
  return 0;
2271
0
}
2272
2273
unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2274
  switch (VT.SimpleTy) {
2275
  case MVT::i1: return fastEmit_ISD_MUL_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2276
  case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2277
  case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2278
  case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2279
  default: return 0;
2280
  }
2281
}
2282
2283
// FastEmit functions for ISD::MULHS.
2284
2285
0
unsigned fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2286
0
  if (RetVT.SimpleTy != MVT::i32)
2287
0
    return 0;
2288
0
  return fastEmitInst_rr(PPC::MULHW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2289
0
}
2290
2291
0
unsigned fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2292
0
  if (RetVT.SimpleTy != MVT::i64)
2293
0
    return 0;
2294
0
  return fastEmitInst_rr(PPC::MULHD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2295
0
}
2296
2297
unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2298
  switch (VT.SimpleTy) {
2299
  case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2300
  case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2301
  default: return 0;
2302
  }
2303
}
2304
2305
// FastEmit functions for ISD::MULHU.
2306
2307
0
unsigned fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2308
0
  if (RetVT.SimpleTy != MVT::i32)
2309
0
    return 0;
2310
0
  return fastEmitInst_rr(PPC::MULHWU, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2311
0
}
2312
2313
0
unsigned fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2314
0
  if (RetVT.SimpleTy != MVT::i64)
2315
0
    return 0;
2316
0
  return fastEmitInst_rr(PPC::MULHDU, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2317
0
}
2318
2319
unsigned fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2320
  switch (VT.SimpleTy) {
2321
  case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2322
  case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2323
  default: return 0;
2324
  }
2325
}
2326
2327
// FastEmit functions for ISD::OR.
2328
2329
0
unsigned fastEmit_ISD_OR_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2330
0
  if (RetVT.SimpleTy != MVT::i1)
2331
0
    return 0;
2332
0
  return fastEmitInst_rr(PPC::CROR, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2333
0
}
2334
2335
0
unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2336
0
  if (RetVT.SimpleTy != MVT::i32)
2337
0
    return 0;
2338
0
  return fastEmitInst_rr(PPC::OR, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2339
0
}
2340
2341
0
unsigned fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2342
0
  if (RetVT.SimpleTy != MVT::i64)
2343
0
    return 0;
2344
0
  return fastEmitInst_rr(PPC::OR8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2345
0
}
2346
2347
1
unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2348
1
  if (RetVT.SimpleTy != MVT::v4i32)
2349
0
    return 0;
2350
1
  if ((PPCSubTarget->hasVSX())) {
2351
1
    return fastEmitInst_rr(PPC::XXLOR, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2352
1
  }
2353
0
  if ((PPCSubTarget->hasAltivec())) {
2354
0
    return fastEmitInst_rr(PPC::VOR, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2355
0
  }
2356
0
  return 0;
2357
0
}
2358
2359
3
unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2360
3
  switch (VT.SimpleTy) {
2361
3
  
case MVT::i1: return fastEmit_ISD_OR_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2362
3
  
case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2363
3
  
case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2364
3
  
case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)1
;
2365
3
  
default: return 02
;
2366
3
  }
2367
3
}
2368
2369
// FastEmit functions for ISD::SDIV.
2370
2371
0
unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2372
0
  if (RetVT.SimpleTy != MVT::i32)
2373
0
    return 0;
2374
0
  return fastEmitInst_rr(PPC::DIVW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2375
0
}
2376
2377
0
unsigned fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2378
0
  if (RetVT.SimpleTy != MVT::i64)
2379
0
    return 0;
2380
0
  return fastEmitInst_rr(PPC::DIVD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2381
0
}
2382
2383
unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2384
  switch (VT.SimpleTy) {
2385
  case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2386
  case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2387
  default: return 0;
2388
  }
2389
}
2390
2391
// FastEmit functions for ISD::SHL.
2392
2393
2
unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2394
2
  if (RetVT.SimpleTy != MVT::i32)
2395
0
    return 0;
2396
2
  return fastEmitInst_rr(PPC::SLW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2397
2
}
2398
2399
0
unsigned fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2400
0
  if (RetVT.SimpleTy != MVT::v16i8)
2401
0
    return 0;
2402
0
  if ((PPCSubTarget->hasAltivec())) {
2403
0
    return fastEmitInst_rr(PPC::VSLB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2404
0
  }
2405
0
  return 0;
2406
0
}
2407
2408
0
unsigned fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2409
0
  if (RetVT.SimpleTy != MVT::v8i16)
2410
0
    return 0;
2411
0
  if ((PPCSubTarget->hasAltivec())) {
2412
0
    return fastEmitInst_rr(PPC::VSLH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2413
0
  }
2414
0
  return 0;
2415
0
}
2416
2417
0
unsigned fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2418
0
  if (RetVT.SimpleTy != MVT::v4i32)
2419
0
    return 0;
2420
0
  if ((PPCSubTarget->hasAltivec())) {
2421
0
    return fastEmitInst_rr(PPC::VSLW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2422
0
  }
2423
0
  return 0;
2424
0
}
2425
2426
1
unsigned fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2427
1
  if (RetVT.SimpleTy != MVT::v2i64)
2428
0
    return 0;
2429
1
  if ((PPCSubTarget->hasP8Altivec())) {
2430
0
    return fastEmitInst_rr(PPC::VSLD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2431
0
  }
2432
1
  return 0;
2433
1
}
2434
2435
4
unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2436
4
  switch (VT.SimpleTy) {
2437
4
  
case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)2
;
2438
4
  
case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2439
4
  
case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2440
4
  
case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2441
4
  
case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)1
;
2442
4
  
default: return 01
;
2443
4
  }
2444
4
}
2445
2446
// FastEmit functions for ISD::SRA.
2447
2448
1
unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2449
1
  if (RetVT.SimpleTy != MVT::i32)
2450
0
    return 0;
2451
1
  return fastEmitInst_rr(PPC::SRAW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2452
1
}
2453
2454
0
unsigned fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2455
0
  if (RetVT.SimpleTy != MVT::v16i8)
2456
0
    return 0;
2457
0
  if ((PPCSubTarget->hasAltivec())) {
2458
0
    return fastEmitInst_rr(PPC::VSRAB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2459
0
  }
2460
0
  return 0;
2461
0
}
2462
2463
0
unsigned fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2464
0
  if (RetVT.SimpleTy != MVT::v8i16)
2465
0
    return 0;
2466
0
  if ((PPCSubTarget->hasAltivec())) {
2467
0
    return fastEmitInst_rr(PPC::VSRAH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2468
0
  }
2469
0
  return 0;
2470
0
}
2471
2472
0
unsigned fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2473
0
  if (RetVT.SimpleTy != MVT::v4i32)
2474
0
    return 0;
2475
0
  if ((PPCSubTarget->hasAltivec())) {
2476
0
    return fastEmitInst_rr(PPC::VSRAW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2477
0
  }
2478
0
  return 0;
2479
0
}
2480
2481
1
unsigned fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2482
1
  if (RetVT.SimpleTy != MVT::v2i64)
2483
0
    return 0;
2484
1
  if ((PPCSubTarget->hasP8Altivec())) {
2485
0
    return fastEmitInst_rr(PPC::VSRAD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2486
0
  }
2487
1
  return 0;
2488
1
}
2489
2490
2
unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2491
2
  switch (VT.SimpleTy) {
2492
2
  
case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)1
;
2493
2
  
case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2494
2
  
case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2495
2
  
case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2496
2
  
case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)1
;
2497
2
  
default: return 00
;
2498
2
  }
2499
2
}
2500
2501
// FastEmit functions for ISD::SREM.
2502
2503
0
unsigned fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2504
0
  if (RetVT.SimpleTy != MVT::i32)
2505
0
    return 0;
2506
0
  if ((PPCSubTarget->isISA3_0())) {
2507
0
    return fastEmitInst_rr(PPC::MODSW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2508
0
  }
2509
0
  return 0;
2510
0
}
2511
2512
0
unsigned fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2513
0
  if (RetVT.SimpleTy != MVT::i64)
2514
0
    return 0;
2515
0
  if ((PPCSubTarget->isISA3_0())) {
2516
0
    return fastEmitInst_rr(PPC::MODSD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2517
0
  }
2518
0
  return 0;
2519
0
}
2520
2521
unsigned fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2522
  switch (VT.SimpleTy) {
2523
  case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2524
  case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2525
  default: return 0;
2526
  }
2527
}
2528
2529
// FastEmit functions for ISD::SRL.
2530
2531
2
unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2532
2
  if (RetVT.SimpleTy != MVT::i32)
2533
0
    return 0;
2534
2
  return fastEmitInst_rr(PPC::SRW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2535
2
}
2536
2537
0
unsigned fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2538
0
  if (RetVT.SimpleTy != MVT::v16i8)
2539
0
    return 0;
2540
0
  if ((PPCSubTarget->hasAltivec())) {
2541
0
    return fastEmitInst_rr(PPC::VSRB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2542
0
  }
2543
0
  return 0;
2544
0
}
2545
2546
0
unsigned fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2547
0
  if (RetVT.SimpleTy != MVT::v8i16)
2548
0
    return 0;
2549
0
  if ((PPCSubTarget->hasAltivec())) {
2550
0
    return fastEmitInst_rr(PPC::VSRH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2551
0
  }
2552
0
  return 0;
2553
0
}
2554
2555
0
unsigned fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2556
0
  if (RetVT.SimpleTy != MVT::v4i32)
2557
0
    return 0;
2558
0
  if ((PPCSubTarget->hasAltivec())) {
2559
0
    return fastEmitInst_rr(PPC::VSRW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2560
0
  }
2561
0
  return 0;
2562
0
}
2563
2564
1
unsigned fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2565
1
  if (RetVT.SimpleTy != MVT::v2i64)
2566
0
    return 0;
2567
1
  if ((PPCSubTarget->hasP8Altivec())) {
2568
0
    return fastEmitInst_rr(PPC::VSRD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2569
0
  }
2570
1
  return 0;
2571
1
}
2572
2573
3
unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2574
3
  switch (VT.SimpleTy) {
2575
3
  
case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)2
;
2576
3
  
case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2577
3
  
case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2578
3
  
case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2579
3
  
case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)1
;
2580
3
  
default: return 00
;
2581
3
  }
2582
3
}
2583
2584
// FastEmit functions for ISD::SUB.
2585
2586
0
unsigned fastEmit_ISD_SUB_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2587
0
  if (RetVT.SimpleTy != MVT::i1)
2588
0
    return 0;
2589
0
  return fastEmitInst_rr(PPC::CRXOR, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2590
0
}
2591
2592
0
unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2593
0
  if (RetVT.SimpleTy != MVT::v16i8)
2594
0
    return 0;
2595
0
  if ((PPCSubTarget->hasAltivec())) {
2596
0
    return fastEmitInst_rr(PPC::VSUBUBM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2597
0
  }
2598
0
  return 0;
2599
0
}
2600
2601
0
unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2602
0
  if (RetVT.SimpleTy != MVT::v8i16)
2603
0
    return 0;
2604
0
  if ((PPCSubTarget->hasAltivec())) {
2605
0
    return fastEmitInst_rr(PPC::VSUBUHM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2606
0
  }
2607
0
  return 0;
2608
0
}
2609
2610
0
unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2611
0
  if (RetVT.SimpleTy != MVT::v4i32)
2612
0
    return 0;
2613
0
  if ((PPCSubTarget->hasAltivec())) {
2614
0
    return fastEmitInst_rr(PPC::VSUBUWM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2615
0
  }
2616
0
  return 0;
2617
0
}
2618
2619
0
unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2620
0
  if (RetVT.SimpleTy != MVT::v2i64)
2621
0
    return 0;
2622
0
  if ((PPCSubTarget->hasP8Altivec())) {
2623
0
    return fastEmitInst_rr(PPC::VSUBUDM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2624
0
  }
2625
0
  return 0;
2626
0
}
2627
2628
0
unsigned fastEmit_ISD_SUB_MVT_v1i128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2629
0
  if (RetVT.SimpleTy != MVT::v1i128)
2630
0
    return 0;
2631
0
  if ((PPCSubTarget->hasP8Altivec())) {
2632
0
    return fastEmitInst_rr(PPC::VSUBUQM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2633
0
  }
2634
0
  return 0;
2635
0
}
2636
2637
1
unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2638
1
  switch (VT.SimpleTy) {
2639
1
  
case MVT::i1: return fastEmit_ISD_SUB_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2640
1
  
case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2641
1
  
case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2642
1
  
case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2643
1
  
case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2644
1
  
case MVT::v1i128: return fastEmit_ISD_SUB_MVT_v1i128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2645
1
  default: return 0;
2646
1
  }
2647
1
}
2648
2649
// FastEmit functions for ISD::UDIV.
2650
2651
0
unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2652
0
  if (RetVT.SimpleTy != MVT::i32)
2653
0
    return 0;
2654
0
  return fastEmitInst_rr(PPC::DIVWU, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2655
0
}
2656
2657
0
unsigned fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2658
0
  if (RetVT.SimpleTy != MVT::i64)
2659
0
    return 0;
2660
0
  return fastEmitInst_rr(PPC::DIVDU, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2661
0
}
2662
2663
unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2664
  switch (VT.SimpleTy) {
2665
  case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2666
  case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2667
  default: return 0;
2668
  }
2669
}
2670
2671
// FastEmit functions for ISD::UREM.
2672
2673
0
unsigned fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2674
0
  if (RetVT.SimpleTy != MVT::i32)
2675
0
    return 0;
2676
0
  if ((PPCSubTarget->isISA3_0())) {
2677
0
    return fastEmitInst_rr(PPC::MODUW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2678
0
  }
2679
0
  return 0;
2680
0
}
2681
2682
0
unsigned fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2683
0
  if (RetVT.SimpleTy != MVT::i64)
2684
0
    return 0;
2685
0
  if ((PPCSubTarget->isISA3_0())) {
2686
0
    return fastEmitInst_rr(PPC::MODUD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2687
0
  }
2688
0
  return 0;
2689
0
}
2690
2691
unsigned fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2692
  switch (VT.SimpleTy) {
2693
  case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2694
  case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2695
  default: return 0;
2696
  }
2697
}
2698
2699
// FastEmit functions for ISD::XOR.
2700
2701
0
unsigned fastEmit_ISD_XOR_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2702
0
  if (RetVT.SimpleTy != MVT::i1)
2703
0
    return 0;
2704
0
  return fastEmitInst_rr(PPC::CRXOR, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2705
0
}
2706
2707
0
unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2708
0
  if (RetVT.SimpleTy != MVT::i32)
2709
0
    return 0;
2710
0
  return fastEmitInst_rr(PPC::XOR, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2711
0
}
2712
2713
0
unsigned fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2714
0
  if (RetVT.SimpleTy != MVT::i64)
2715
0
    return 0;
2716
0
  return fastEmitInst_rr(PPC::XOR8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2717
0
}
2718
2719
1
unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2720
1
  if (RetVT.SimpleTy != MVT::v4i32)
2721
0
    return 0;
2722
1
  if ((PPCSubTarget->hasVSX())) {
2723
1
    return fastEmitInst_rr(PPC::XXLXOR, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2724
1
  }
2725
0
  if ((PPCSubTarget->hasAltivec())) {
2726
0
    return fastEmitInst_rr(PPC::VXOR, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2727
0
  }
2728
0
  return 0;
2729
0
}
2730
2731
3
unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2732
3
  switch (VT.SimpleTy) {
2733
3
  
case MVT::i1: return fastEmit_ISD_XOR_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2734
3
  
case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2735
3
  
case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2736
3
  
case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)1
;
2737
3
  
default: return 02
;
2738
3
  }
2739
3
}
2740
2741
// FastEmit functions for PPCISD::CMPB.
2742
2743
0
unsigned fastEmit_PPCISD_CMPB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2744
0
  if (RetVT.SimpleTy != MVT::i32)
2745
0
    return 0;
2746
0
  return fastEmitInst_rr(PPC::CMPB, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2747
0
}
2748
2749
0
unsigned fastEmit_PPCISD_CMPB_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2750
0
  if (RetVT.SimpleTy != MVT::i64)
2751
0
    return 0;
2752
0
  return fastEmitInst_rr(PPC::CMPB8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2753
0
}
2754
2755
unsigned fastEmit_PPCISD_CMPB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2756
  switch (VT.SimpleTy) {
2757
  case MVT::i32: return fastEmit_PPCISD_CMPB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2758
  case MVT::i64: return fastEmit_PPCISD_CMPB_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2759
  default: return 0;
2760
  }
2761
}
2762
2763
// FastEmit functions for PPCISD::FADDRTZ.
2764
2765
0
unsigned fastEmit_PPCISD_FADDRTZ_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2766
0
  if (RetVT.SimpleTy != MVT::f64)
2767
0
    return 0;
2768
0
  if ((PPCSubTarget->hasFPU())) {
2769
0
    return fastEmitInst_rr(PPC::FADDrtz, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2770
0
  }
2771
0
  return 0;
2772
0
}
2773
2774
unsigned fastEmit_PPCISD_FADDRTZ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2775
  switch (VT.SimpleTy) {
2776
  case MVT::f64: return fastEmit_PPCISD_FADDRTZ_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2777
  default: return 0;
2778
  }
2779
}
2780
2781
// FastEmit functions for PPCISD::SHL.
2782
2783
0
unsigned fastEmit_PPCISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2784
0
  if (RetVT.SimpleTy != MVT::i32)
2785
0
    return 0;
2786
0
  return fastEmitInst_rr(PPC::SLW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2787
0
}
2788
2789
0
unsigned fastEmit_PPCISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2790
0
  if (RetVT.SimpleTy != MVT::v16i8)
2791
0
    return 0;
2792
0
  if ((PPCSubTarget->hasAltivec())) {
2793
0
    return fastEmitInst_rr(PPC::VSLB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2794
0
  }
2795
0
  return 0;
2796
0
}
2797
2798
0
unsigned fastEmit_PPCISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2799
0
  if (RetVT.SimpleTy != MVT::v8i16)
2800
0
    return 0;
2801
0
  if ((PPCSubTarget->hasAltivec())) {
2802
0
    return fastEmitInst_rr(PPC::VSLH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2803
0
  }
2804
0
  return 0;
2805
0
}
2806
2807
0
unsigned fastEmit_PPCISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2808
0
  if (RetVT.SimpleTy != MVT::v4i32)
2809
0
    return 0;
2810
0
  if ((PPCSubTarget->hasAltivec())) {
2811
0
    return fastEmitInst_rr(PPC::VSLW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2812
0
  }
2813
0
  return 0;
2814
0
}
2815
2816
0
unsigned fastEmit_PPCISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2817
0
  if (RetVT.SimpleTy != MVT::v2i64)
2818
0
    return 0;
2819
0
  if ((PPCSubTarget->hasP8Altivec())) {
2820
0
    return fastEmitInst_rr(PPC::VSLD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2821
0
  }
2822
0
  return 0;
2823
0
}
2824
2825
unsigned fastEmit_PPCISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2826
  switch (VT.SimpleTy) {
2827
  case MVT::i32: return fastEmit_PPCISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2828
  case MVT::v16i8: return fastEmit_PPCISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2829
  case MVT::v8i16: return fastEmit_PPCISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2830
  case MVT::v4i32: return fastEmit_PPCISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2831
  case MVT::v2i64: return fastEmit_PPCISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2832
  default: return 0;
2833
  }
2834
}
2835
2836
// FastEmit functions for PPCISD::SRA.
2837
2838
0
unsigned fastEmit_PPCISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2839
0
  if (RetVT.SimpleTy != MVT::i32)
2840
0
    return 0;
2841
0
  return fastEmitInst_rr(PPC::SRAW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2842
0
}
2843
2844
0
unsigned fastEmit_PPCISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2845
0
  if (RetVT.SimpleTy != MVT::v16i8)
2846
0
    return 0;
2847
0
  if ((PPCSubTarget->hasAltivec())) {
2848
0
    return fastEmitInst_rr(PPC::VSRAB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2849
0
  }
2850
0
  return 0;
2851
0
}
2852
2853
0
unsigned fastEmit_PPCISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2854
0
  if (RetVT.SimpleTy != MVT::v8i16)
2855
0
    return 0;
2856
0
  if ((PPCSubTarget->hasAltivec())) {
2857
0
    return fastEmitInst_rr(PPC::VSRAH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2858
0
  }
2859
0
  return 0;
2860
0
}
2861
2862
0
unsigned fastEmit_PPCISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2863
0
  if (RetVT.SimpleTy != MVT::v4i32)
2864
0
    return 0;
2865
0
  if ((PPCSubTarget->hasAltivec())) {
2866
0
    return fastEmitInst_rr(PPC::VSRAW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2867
0
  }
2868
0
  return 0;
2869
0
}
2870
2871
0
unsigned fastEmit_PPCISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2872
0
  if (RetVT.SimpleTy != MVT::v2i64)
2873
0
    return 0;
2874
0
  if ((PPCSubTarget->hasP8Altivec())) {
2875
0
    return fastEmitInst_rr(PPC::VSRAD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2876
0
  }
2877
0
  return 0;
2878
0
}
2879
2880
unsigned fastEmit_PPCISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2881
  switch (VT.SimpleTy) {
2882
  case MVT::i32: return fastEmit_PPCISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2883
  case MVT::v16i8: return fastEmit_PPCISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2884
  case MVT::v8i16: return fastEmit_PPCISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2885
  case MVT::v4i32: return fastEmit_PPCISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2886
  case MVT::v2i64: return fastEmit_PPCISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2887
  default: return 0;
2888
  }
2889
}
2890
2891
// FastEmit functions for PPCISD::SRL.
2892
2893
0
unsigned fastEmit_PPCISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2894
0
  if (RetVT.SimpleTy != MVT::i32)
2895
0
    return 0;
2896
0
  return fastEmitInst_rr(PPC::SRW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2897
0
}
2898
2899
0
unsigned fastEmit_PPCISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2900
0
  if (RetVT.SimpleTy != MVT::v16i8)
2901
0
    return 0;
2902
0
  if ((PPCSubTarget->hasAltivec())) {
2903
0
    return fastEmitInst_rr(PPC::VSRB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2904
0
  }
2905
0
  return 0;
2906
0
}
2907
2908
0
unsigned fastEmit_PPCISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2909
0
  if (RetVT.SimpleTy != MVT::v8i16)
2910
0
    return 0;
2911
0
  if ((PPCSubTarget->hasAltivec())) {
2912
0
    return fastEmitInst_rr(PPC::VSRH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2913
0
  }
2914
0
  return 0;
2915
0
}
2916
2917
0
unsigned fastEmit_PPCISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2918
0
  if (RetVT.SimpleTy != MVT::v4i32)
2919
0
    return 0;
2920
0
  if ((PPCSubTarget->hasAltivec())) {
2921
0
    return fastEmitInst_rr(PPC::VSRW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2922
0
  }
2923
0
  return 0;
2924
0
}
2925
2926
0
unsigned fastEmit_PPCISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2927
0
  if (RetVT.SimpleTy != MVT::v2i64)
2928
0
    return 0;
2929
0
  if ((PPCSubTarget->hasP8Altivec())) {
2930
0
    return fastEmitInst_rr(PPC::VSRD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2931
0
  }
2932
0
  return 0;
2933
0
}
2934
2935
unsigned fastEmit_PPCISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2936
  switch (VT.SimpleTy) {
2937
  case MVT::i32: return fastEmit_PPCISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2938
  case MVT::v16i8: return fastEmit_PPCISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2939
  case MVT::v8i16: return fastEmit_PPCISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2940
  case MVT::v4i32: return fastEmit_PPCISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2941
  case MVT::v2i64: return fastEmit_PPCISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2942
  default: return 0;
2943
  }
2944
}
2945
2946
// Top-level FastEmit function.
2947
2948
39
unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) override {
2949
39
  switch (Opcode) {
2950
39
  
case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)1
;
2951
39
  
case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2952
39
  
case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2953
39
  
case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)8
;
2954
39
  
case ISD::BUILD_VECTOR: return fastEmit_ISD_BUILD_VECTOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2955
39
  
case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)12
;
2956
39
  
case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)1
;
2957
39
  
case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)1
;
2958
39
  
case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2959
39
  
case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2960
39
  
case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2961
39
  
case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2962
39
  
case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)3
;
2963
39
  
case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2964
39
  
case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)4
;
2965
39
  
case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)2
;
2966
39
  
case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2967
39
  
case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)3
;
2968
39
  
case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)1
;
2969
39
  
case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2970
39
  
case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2971
39
  
case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)3
;
2972
39
  
case PPCISD::CMPB: return fastEmit_PPCISD_CMPB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2973
39
  
case PPCISD::FADDRTZ: return fastEmit_PPCISD_FADDRTZ_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2974
39
  
case PPCISD::SHL: return fastEmit_PPCISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2975
39
  
case PPCISD::SRA: return fastEmit_PPCISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2976
39
  
case PPCISD::SRL: return fastEmit_PPCISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2977
39
  
default: return 00
;
2978
39
  }
2979
39
}
2980
2981
// FastEmit functions for ISD::SRA.
2982
2983
1
unsigned fastEmit_ISD_SRA_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2984
1
  if (RetVT.SimpleTy != MVT::i32)
2985
0
    return 0;
2986
1
  return fastEmitInst_ri(PPC::SRAWI, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
2987
1
}
2988
2989
0
unsigned fastEmit_ISD_SRA_MVT_i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2990
0
  if (RetVT.SimpleTy != MVT::i64)
2991
0
    return 0;
2992
0
  return fastEmitInst_ri(PPC::SRADI, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
2993
0
}
2994
2995
1
unsigned fastEmit_ISD_SRA_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2996
1
  switch (VT.SimpleTy) {
2997
1
  case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
2998
1
  
case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri(RetVT, Op0, Op0IsKill, imm1)0
;
2999
1
  
default: return 00
;
3000
1
  }
3001
1
}
3002
3003
// FastEmit functions for PPCISD::EXTSWSLI.
3004
3005
0
unsigned fastEmit_PPCISD_EXTSWSLI_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3006
0
  if (RetVT.SimpleTy != MVT::i64)
3007
0
    return 0;
3008
0
  if ((PPCSubTarget->isISA3_0())) {
3009
0
    return fastEmitInst_ri(PPC::EXTSWSLI, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
3010
0
  }
3011
0
  return 0;
3012
0
}
3013
3014
unsigned fastEmit_PPCISD_EXTSWSLI_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3015
  switch (VT.SimpleTy) {
3016
  case MVT::i32: return fastEmit_PPCISD_EXTSWSLI_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
3017
  default: return 0;
3018
  }
3019
}
3020
3021
// FastEmit functions for PPCISD::QVESPLATI.
3022
3023
0
unsigned fastEmit_PPCISD_QVESPLATI_MVT_v4i1_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3024
0
  if (RetVT.SimpleTy != MVT::v4i1)
3025
0
    return 0;
3026
0
  if ((PPCSubTarget->hasQPX())) {
3027
0
    return fastEmitInst_ri(PPC::QVESPLATIb, &PPC::QBRCRegClass, Op0, Op0IsKill, imm1);
3028
0
  }
3029
0
  return 0;
3030
0
}
3031
3032
0
unsigned fastEmit_PPCISD_QVESPLATI_MVT_v4f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3033
0
  if (RetVT.SimpleTy != MVT::v4f32)
3034
0
    return 0;
3035
0
  if ((PPCSubTarget->hasQPX())) {
3036
0
    return fastEmitInst_ri(PPC::QVESPLATIs, &PPC::QSRCRegClass, Op0, Op0IsKill, imm1);
3037
0
  }
3038
0
  return 0;
3039
0
}
3040
3041
0
unsigned fastEmit_PPCISD_QVESPLATI_MVT_v4f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3042
0
  if (RetVT.SimpleTy != MVT::v4f64)
3043
0
    return 0;
3044
0
  if ((PPCSubTarget->hasQPX())) {
3045
0
    return fastEmitInst_ri(PPC::QVESPLATI, &PPC::QFRCRegClass, Op0, Op0IsKill, imm1);
3046
0
  }
3047
0
  return 0;
3048
0
}
3049
3050
unsigned fastEmit_PPCISD_QVESPLATI_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3051
  switch (VT.SimpleTy) {
3052
  case MVT::v4i1: return fastEmit_PPCISD_QVESPLATI_MVT_v4i1_ri(RetVT, Op0, Op0IsKill, imm1);
3053
  case MVT::v4f32: return fastEmit_PPCISD_QVESPLATI_MVT_v4f32_ri(RetVT, Op0, Op0IsKill, imm1);
3054
  case MVT::v4f64: return fastEmit_PPCISD_QVESPLATI_MVT_v4f64_ri(RetVT, Op0, Op0IsKill, imm1);
3055
  default: return 0;
3056
  }
3057
}
3058
3059
// FastEmit functions for PPCISD::TC_RETURN.
3060
3061
0
unsigned fastEmit_PPCISD_TC_RETURN_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3062
0
  if (RetVT.SimpleTy != MVT::isVoid)
3063
0
    return 0;
3064
0
  return fastEmitInst_ri(PPC::TCRETURNri, &PPC::CTRRCRegClass, Op0, Op0IsKill, imm1);
3065
0
}
3066
3067
0
unsigned fastEmit_PPCISD_TC_RETURN_MVT_i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3068
0
  if (RetVT.SimpleTy != MVT::isVoid)
3069
0
    return 0;
3070
0
  return fastEmitInst_ri(PPC::TCRETURNri8, &PPC::CTRRC8RegClass, Op0, Op0IsKill, imm1);
3071
0
}
3072
3073
unsigned fastEmit_PPCISD_TC_RETURN_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3074
  switch (VT.SimpleTy) {
3075
  case MVT::i32: return fastEmit_PPCISD_TC_RETURN_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
3076
  case MVT::i64: return fastEmit_PPCISD_TC_RETURN_MVT_i64_ri(RetVT, Op0, Op0IsKill, imm1);
3077
  default: return 0;
3078
  }
3079
}
3080
3081
// Top-level FastEmit function.
3082
3083
42
unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) override {
3084
42
  if (VT == MVT::i32 && 
Predicate_imm32SExt16(imm1)23
)
3085
23
    if (unsigned Reg = fastEmit_ri_Predicate_imm32SExt16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
3086
20
      return Reg;
3087
22
3088
22
  if (VT == MVT::i64 && 
Predicate_imm64SExt16(imm1)19
)
3089
19
    if (unsigned Reg = fastEmit_ri_Predicate_imm64SExt16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
3090
17
      return Reg;
3091
5
3092
5
  switch (Opcode) {
3093
5
  
case ISD::SRA: return fastEmit_ISD_SRA_ri(VT, RetVT, Op0, Op0IsKill, imm1)1
;
3094
5
  
case PPCISD::EXTSWSLI: return fastEmit_PPCISD_EXTSWSLI_ri(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3095
5
  
case PPCISD::QVESPLATI: return fastEmit_PPCISD_QVESPLATI_ri(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3096
5
  
case PPCISD::TC_RETURN: return fastEmit_PPCISD_TC_RETURN_ri(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3097
5
  
default: return 04
;
3098
5
  }
3099
5
}
3100
3101
// FastEmit functions for ISD::ADD.
3102
3103
20
unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3104
20
  if (RetVT.SimpleTy != MVT::i32)
3105
0
    return 0;
3106
20
  return fastEmitInst_ri(PPC::ADDI, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
3107
20
}
3108
3109
20
unsigned fastEmit_ISD_ADD_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3110
20
  switch (VT.SimpleTy) {
3111
20
  case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, Op0IsKill, imm1);
3112
20
  
default: return 00
;
3113
20
  }
3114
20
}
3115
3116
// FastEmit functions for ISD::ADDC.
3117
3118
0
unsigned fastEmit_ISD_ADDC_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3119
0
  if (RetVT.SimpleTy != MVT::i32)
3120
0
    return 0;
3121
0
  return fastEmitInst_ri(PPC::ADDIC, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
3122
0
}
3123
3124
unsigned fastEmit_ISD_ADDC_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3125
  switch (VT.SimpleTy) {
3126
  case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, Op0IsKill, imm1);
3127
  default: return 0;
3128
  }
3129
}
3130
3131
// FastEmit functions for ISD::MUL.
3132
3133
0
unsigned fastEmit_ISD_MUL_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3134
0
  if (RetVT.SimpleTy != MVT::i32)
3135
0
    return 0;
3136
0
  return fastEmitInst_ri(PPC::MULLI, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
3137
0
}
3138
3139
unsigned fastEmit_ISD_MUL_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3140
  switch (VT.SimpleTy) {
3141
  case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, Op0IsKill, imm1);
3142
  default: return 0;
3143
  }
3144
}
3145
3146
// FastEmit functions for PPCISD::XXSPLT.
3147
3148
0
unsigned fastEmit_PPCISD_XXSPLT_MVT_v4i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3149
0
  if (RetVT.SimpleTy != MVT::v4i32)
3150
0
    return 0;
3151
0
  if ((PPCSubTarget->hasVSX())) {
3152
0
    return fastEmitInst_ri(PPC::XXSPLTW, &PPC::VSRCRegClass, Op0, Op0IsKill, imm1);
3153
0
  }
3154
0
  return 0;
3155
0
}
3156
3157
unsigned fastEmit_PPCISD_XXSPLT_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3158
  switch (VT.SimpleTy) {
3159
  case MVT::v4i32: return fastEmit_PPCISD_XXSPLT_MVT_v4i32_ri_Predicate_imm32SExt16(RetVT, Op0, Op0IsKill, imm1);
3160
  default: return 0;
3161
  }
3162
}
3163
3164
// Top-level FastEmit function.
3165
3166
23
unsigned fastEmit_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3167
23
  switch (Opcode) {
3168
23
  
case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm32SExt16(VT, RetVT, Op0, Op0IsKill, imm1)20
;
3169
23
  
case ISD::ADDC: return fastEmit_ISD_ADDC_ri_Predicate_imm32SExt16(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3170
23
  
case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_imm32SExt16(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3171
23
  
case PPCISD::XXSPLT: return fastEmit_PPCISD_XXSPLT_ri_Predicate_imm32SExt16(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3172
23
  
default: return 03
;
3173
23
  }
3174
23
}
3175
3176
// FastEmit functions for ISD::ADD.
3177
3178
17
unsigned fastEmit_ISD_ADD_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3179
17
  if (RetVT.SimpleTy != MVT::i64)
3180
0
    return 0;
3181
17
  return fastEmitInst_ri(PPC::ADDI8, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
3182
17
}
3183
3184
17
unsigned fastEmit_ISD_ADD_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3185
17
  switch (VT.SimpleTy) {
3186
17
  case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, Op0IsKill, imm1);
3187
17
  
default: return 00
;
3188
17
  }
3189
17
}
3190
3191
// FastEmit functions for ISD::ADDC.
3192
3193
0
unsigned fastEmit_ISD_ADDC_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3194
0
  if (RetVT.SimpleTy != MVT::i64)
3195
0
    return 0;
3196
0
  return fastEmitInst_ri(PPC::ADDIC8, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
3197
0
}
3198
3199
unsigned fastEmit_ISD_ADDC_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3200
  switch (VT.SimpleTy) {
3201
  case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, Op0IsKill, imm1);
3202
  default: return 0;
3203
  }
3204
}
3205
3206
// FastEmit functions for ISD::MUL.
3207
3208
0
unsigned fastEmit_ISD_MUL_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3209
0
  if (RetVT.SimpleTy != MVT::i64)
3210
0
    return 0;
3211
0
  return fastEmitInst_ri(PPC::MULLI8, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
3212
0
}
3213
3214
unsigned fastEmit_ISD_MUL_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3215
  switch (VT.SimpleTy) {
3216
  case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, Op0IsKill, imm1);
3217
  default: return 0;
3218
  }
3219
}
3220
3221
// Top-level FastEmit function.
3222
3223
19
unsigned fastEmit_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
3224
19
  switch (Opcode) {
3225
19
  
case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm64SExt16(VT, RetVT, Op0, Op0IsKill, imm1)17
;
3226
19
  
case ISD::ADDC: return fastEmit_ISD_ADDC_ri_Predicate_imm64SExt16(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3227
19
  
case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_imm64SExt16(VT, RetVT, Op0, Op0IsKill, imm1)0
;
3228
19
  
default: return 02
;
3229
19
  }
3230
19
}
3231