Coverage Report

Created: 2018-07-12 09:57

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/PowerPC/PPCGenFastISel.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* "Fast" Instruction Selector for the PPC target                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
// FastEmit Immediate Predicate functions.
11
23
static bool Predicate_imm32SExt16(int64_t Imm) {
12
23
13
23
  // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
14
23
  // sign extended field.  Used by instructions like 'addi'.
15
23
  return (int32_t)Imm == (short)Imm;
16
23
17
23
}
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19
static bool Predicate_imm64SExt16(int64_t Imm) {
19
19
20
19
  // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
21
19
  // sign extended field.  Used by instructions like 'addi'.
22
19
  return (int64_t)Imm == (short)Imm;
23
19
24
19
}
25
0
static bool Predicate_immSExt5NonZero(int64_t Imm) {
26
0
 return Imm && isInt<5>(Imm); 
27
0
}
28
29
30
// FastEmit functions for ISD::READCYCLECOUNTER.
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32
0
unsigned fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(MVT RetVT) {
33
0
  if (RetVT.SimpleTy != MVT::i64)
34
0
    return 0;
35
0
  return fastEmitInst_(PPC::MFTB8, &PPC::G8RCRegClass);
36
0
}
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38
unsigned fastEmit_ISD_READCYCLECOUNTER_(MVT VT, MVT RetVT) {
39
  switch (VT.SimpleTy) {
40
  case MVT::i64: return fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(RetVT);
41
  default: return 0;
42
  }
43
}
44
45
// FastEmit functions for PPCISD::MFFS.
46
47
0
unsigned fastEmit_PPCISD_MFFS_MVT_f64_(MVT RetVT) {
48
0
  if (RetVT.SimpleTy != MVT::f64)
49
0
    return 0;
50
0
  return fastEmitInst_(PPC::MFFS, &PPC::F8RCRegClass);
51
0
}
52
53
unsigned fastEmit_PPCISD_MFFS_(MVT VT, MVT RetVT) {
54
  switch (VT.SimpleTy) {
55
  case MVT::f64: return fastEmit_PPCISD_MFFS_MVT_f64_(RetVT);
56
  default: return 0;
57
  }
58
}
59
60
// FastEmit functions for PPCISD::PPC32_GOT.
61
62
0
unsigned fastEmit_PPCISD_PPC32_GOT_MVT_i32_(MVT RetVT) {
63
0
  if (RetVT.SimpleTy != MVT::i32)
64
0
    return 0;
65
0
  return fastEmitInst_(PPC::PPC32GOT, &PPC::GPRCRegClass);
66
0
}
67
68
unsigned fastEmit_PPCISD_PPC32_GOT_(MVT VT, MVT RetVT) {
69
  switch (VT.SimpleTy) {
70
  case MVT::i32: return fastEmit_PPCISD_PPC32_GOT_MVT_i32_(RetVT);
71
  default: return 0;
72
  }
73
}
74
75
// Top-level FastEmit function.
76
77
unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode) override {
78
  switch (Opcode) {
79
  case ISD::READCYCLECOUNTER: return fastEmit_ISD_READCYCLECOUNTER_(VT, RetVT);
80
  case PPCISD::MFFS: return fastEmit_PPCISD_MFFS_(VT, RetVT);
81
  case PPCISD::PPC32_GOT: return fastEmit_PPCISD_PPC32_GOT_(VT, RetVT);
82
  default: return 0;
83
  }
84
}
85
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// FastEmit functions for ISD::BITCAST.
87
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0
unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
89
0
  if (RetVT.SimpleTy != MVT::f64)
90
0
    return 0;
91
0
  if ((PPCSubTarget->hasDirectMove()) && (PPCSubTarget->hasVSX())) {
92
0
    return fastEmitInst_r(PPC::MTVSRD, &PPC::VSFRCRegClass, Op0, Op0IsKill);
93
0
  }
94
0
  return 0;
95
0
}
96
97
0
unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
98
0
  if (RetVT.SimpleTy != MVT::i64)
99
0
    return 0;
100
0
  if ((PPCSubTarget->hasDirectMove()) && (PPCSubTarget->hasVSX())) {
101
0
    return fastEmitInst_r(PPC::MFVSRD, &PPC::G8RCRegClass, Op0, Op0IsKill);
102
0
  }
103
0
  return 0;
104
0
}
105
106
2
unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
107
2
  switch (VT.SimpleTy) {
108
2
  
case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0, Op0IsKill)0
;
109
2
  
case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill)0
;
110
2
  default: return 0;
111
2
  }
112
2
}
113
114
// FastEmit functions for ISD::CTLZ.
115
116
0
unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
117
0
  if (RetVT.SimpleTy != MVT::i32)
118
0
    return 0;
119
0
  return fastEmitInst_r(PPC::CNTLZW, &PPC::GPRCRegClass, Op0, Op0IsKill);
120
0
}
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0
unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
123
0
  if (RetVT.SimpleTy != MVT::i64)
124
0
    return 0;
125
0
  return fastEmitInst_r(PPC::CNTLZD, &PPC::G8RCRegClass, Op0, Op0IsKill);
126
0
}
127
128
0
unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
129
0
  if (RetVT.SimpleTy != MVT::v16i8)
130
0
    return 0;
131
0
  if ((PPCSubTarget->hasP8Altivec())) {
132
0
    return fastEmitInst_r(PPC::VCLZB, &PPC::VRRCRegClass, Op0, Op0IsKill);
133
0
  }
134
0
  return 0;
135
0
}
136
137
0
unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
138
0
  if (RetVT.SimpleTy != MVT::v8i16)
139
0
    return 0;
140
0
  if ((PPCSubTarget->hasP8Altivec())) {
141
0
    return fastEmitInst_r(PPC::VCLZH, &PPC::VRRCRegClass, Op0, Op0IsKill);
142
0
  }
143
0
  return 0;
144
0
}
145
146
0
unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
147
0
  if (RetVT.SimpleTy != MVT::v4i32)
148
0
    return 0;
149
0
  if ((PPCSubTarget->hasP8Altivec())) {
150
0
    return fastEmitInst_r(PPC::VCLZW, &PPC::VRRCRegClass, Op0, Op0IsKill);
151
0
  }
152
0
  return 0;
153
0
}
154
155
0
unsigned fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
156
0
  if (RetVT.SimpleTy != MVT::v2i64)
157
0
    return 0;
158
0
  if ((PPCSubTarget->hasP8Altivec())) {
159
0
    return fastEmitInst_r(PPC::VCLZD, &PPC::VRRCRegClass, Op0, Op0IsKill);
160
0
  }
161
0
  return 0;
162
0
}
163
164
unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
165
  switch (VT.SimpleTy) {
166
  case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
167
  case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0, Op0IsKill);
168
  case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
169
  case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
170
  case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
171
  case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
172
  default: return 0;
173
  }
174
}
175
176
// FastEmit functions for ISD::CTPOP.
177
178
0
unsigned fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
179
0
  if (RetVT.SimpleTy != MVT::i32)
180
0
    return 0;
181
0
  return fastEmitInst_r(PPC::POPCNTW, &PPC::GPRCRegClass, Op0, Op0IsKill);
182
0
}
183
184
0
unsigned fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
185
0
  if (RetVT.SimpleTy != MVT::i64)
186
0
    return 0;
187
0
  return fastEmitInst_r(PPC::POPCNTD, &PPC::G8RCRegClass, Op0, Op0IsKill);
188
0
}
189
190
0
unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
191
0
  if (RetVT.SimpleTy != MVT::v16i8)
192
0
    return 0;
193
0
  if ((PPCSubTarget->hasP8Altivec())) {
194
0
    return fastEmitInst_r(PPC::VPOPCNTB, &PPC::VRRCRegClass, Op0, Op0IsKill);
195
0
  }
196
0
  return 0;
197
0
}
198
199
0
unsigned fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
200
0
  if (RetVT.SimpleTy != MVT::v8i16)
201
0
    return 0;
202
0
  if ((PPCSubTarget->hasP8Altivec())) {
203
0
    return fastEmitInst_r(PPC::VPOPCNTH, &PPC::VRRCRegClass, Op0, Op0IsKill);
204
0
  }
205
0
  return 0;
206
0
}
207
208
0
unsigned fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
209
0
  if (RetVT.SimpleTy != MVT::v4i32)
210
0
    return 0;
211
0
  if ((PPCSubTarget->hasP8Altivec())) {
212
0
    return fastEmitInst_r(PPC::VPOPCNTW, &PPC::VRRCRegClass, Op0, Op0IsKill);
213
0
  }
214
0
  return 0;
215
0
}
216
217
0
unsigned fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
218
0
  if (RetVT.SimpleTy != MVT::v2i64)
219
0
    return 0;
220
0
  if ((PPCSubTarget->hasP8Altivec())) {
221
0
    return fastEmitInst_r(PPC::VPOPCNTD, &PPC::VRRCRegClass, Op0, Op0IsKill);
222
0
  }
223
0
  return 0;
224
0
}
225
226
unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
227
  switch (VT.SimpleTy) {
228
  case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0, Op0IsKill);
229
  case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0, Op0IsKill);
230
  case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
231
  case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
232
  case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
233
  case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
234
  default: return 0;
235
  }
236
}
237
238
// FastEmit functions for ISD::CTTZ.
239
240
0
unsigned fastEmit_ISD_CTTZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
241
0
  if (RetVT.SimpleTy != MVT::i32)
242
0
    return 0;
243
0
  if ((PPCSubTarget->isISA3_0())) {
244
0
    return fastEmitInst_r(PPC::CNTTZW, &PPC::GPRCRegClass, Op0, Op0IsKill);
245
0
  }
246
0
  return 0;
247
0
}
248
249
0
unsigned fastEmit_ISD_CTTZ_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
250
0
  if (RetVT.SimpleTy != MVT::i64)
251
0
    return 0;
252
0
  if ((PPCSubTarget->isISA3_0())) {
253
0
    return fastEmitInst_r(PPC::CNTTZD, &PPC::G8RCRegClass, Op0, Op0IsKill);
254
0
  }
255
0
  return 0;
256
0
}
257
258
0
unsigned fastEmit_ISD_CTTZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
259
0
  if (RetVT.SimpleTy != MVT::v16i8)
260
0
    return 0;
261
0
  if ((PPCSubTarget->hasP9Altivec())) {
262
0
    return fastEmitInst_r(PPC::VCTZB, &PPC::VRRCRegClass, Op0, Op0IsKill);
263
0
  }
264
0
  return 0;
265
0
}
266
267
0
unsigned fastEmit_ISD_CTTZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
268
0
  if (RetVT.SimpleTy != MVT::v8i16)
269
0
    return 0;
270
0
  if ((PPCSubTarget->hasP9Altivec())) {
271
0
    return fastEmitInst_r(PPC::VCTZH, &PPC::VRRCRegClass, Op0, Op0IsKill);
272
0
  }
273
0
  return 0;
274
0
}
275
276
0
unsigned fastEmit_ISD_CTTZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
277
0
  if (RetVT.SimpleTy != MVT::v4i32)
278
0
    return 0;
279
0
  if ((PPCSubTarget->hasP9Altivec())) {
280
0
    return fastEmitInst_r(PPC::VCTZW, &PPC::VRRCRegClass, Op0, Op0IsKill);
281
0
  }
282
0
  return 0;
283
0
}
284
285
0
unsigned fastEmit_ISD_CTTZ_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
286
0
  if (RetVT.SimpleTy != MVT::v2i64)
287
0
    return 0;
288
0
  if ((PPCSubTarget->hasP9Altivec())) {
289
0
    return fastEmitInst_r(PPC::VCTZD, &PPC::VRRCRegClass, Op0, Op0IsKill);
290
0
  }
291
0
  return 0;
292
0
}
293
294
unsigned fastEmit_ISD_CTTZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
295
  switch (VT.SimpleTy) {
296
  case MVT::i32: return fastEmit_ISD_CTTZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
297
  case MVT::i64: return fastEmit_ISD_CTTZ_MVT_i64_r(RetVT, Op0, Op0IsKill);
298
  case MVT::v16i8: return fastEmit_ISD_CTTZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
299
  case MVT::v8i16: return fastEmit_ISD_CTTZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
300
  case MVT::v4i32: return fastEmit_ISD_CTTZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
301
  case MVT::v2i64: return fastEmit_ISD_CTTZ_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
302
  default: return 0;
303
  }
304
}
305
306
// FastEmit functions for ISD::FABS.
307
308
0
unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
309
0
  if (RetVT.SimpleTy != MVT::f32)
310
0
    return 0;
311
0
  return fastEmitInst_r(PPC::FABSS, &PPC::F4RCRegClass, Op0, Op0IsKill);
312
0
}
313
314
0
unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
315
0
  if (RetVT.SimpleTy != MVT::f64)
316
0
    return 0;
317
0
  if ((PPCSubTarget->hasVSX())) {
318
0
    return fastEmitInst_r(PPC::XSABSDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
319
0
  }
320
0
  return fastEmitInst_r(PPC::FABSD, &PPC::F8RCRegClass, Op0, Op0IsKill);
321
0
}
322
323
0
unsigned fastEmit_ISD_FABS_MVT_f128_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
324
0
  if (RetVT.SimpleTy != MVT::f128)
325
0
    return 0;
326
0
  if ((PPCSubTarget->hasP9Vector())) {
327
0
    return fastEmitInst_r(PPC::XSABSQP, &PPC::VRRCRegClass, Op0, Op0IsKill);
328
0
  }
329
0
  return 0;
330
0
}
331
332
0
unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
333
0
  if (RetVT.SimpleTy != MVT::v4f32)
334
0
    return 0;
335
0
  if ((PPCSubTarget->hasVSX())) {
336
0
    return fastEmitInst_r(PPC::XVABSSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
337
0
  }
338
0
  if ((PPCSubTarget->hasQPX())) {
339
0
    return fastEmitInst_r(PPC::QVFABSs, &PPC::QSRCRegClass, Op0, Op0IsKill);
340
0
  }
341
0
  return 0;
342
0
}
343
344
0
unsigned fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
345
0
  if (RetVT.SimpleTy != MVT::v2f64)
346
0
    return 0;
347
0
  if ((PPCSubTarget->hasVSX())) {
348
0
    return fastEmitInst_r(PPC::XVABSDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
349
0
  }
350
0
  return 0;
351
0
}
352
353
0
unsigned fastEmit_ISD_FABS_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
354
0
  if (RetVT.SimpleTy != MVT::v4f64)
355
0
    return 0;
356
0
  if ((PPCSubTarget->hasQPX())) {
357
0
    return fastEmitInst_r(PPC::QVFABS, &PPC::QFRCRegClass, Op0, Op0IsKill);
358
0
  }
359
0
  return 0;
360
0
}
361
362
unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
363
  switch (VT.SimpleTy) {
364
  case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill);
365
  case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0, Op0IsKill);
366
  case MVT::f128: return fastEmit_ISD_FABS_MVT_f128_r(RetVT, Op0, Op0IsKill);
367
  case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
368
  case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
369
  case MVT::v4f64: return fastEmit_ISD_FABS_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
370
  default: return 0;
371
  }
372
}
373
374
// FastEmit functions for ISD::FCEIL.
375
376
0
unsigned fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
377
0
  if (RetVT.SimpleTy != MVT::f32)
378
0
    return 0;
379
0
  return fastEmitInst_r(PPC::FRIPS, &PPC::F4RCRegClass, Op0, Op0IsKill);
380
0
}
381
382
0
unsigned fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
383
0
  if (RetVT.SimpleTy != MVT::f64)
384
0
    return 0;
385
0
  if ((PPCSubTarget->hasVSX())) {
386
0
    return fastEmitInst_r(PPC::XSRDPIP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
387
0
  }
388
0
  return fastEmitInst_r(PPC::FRIPD, &PPC::F8RCRegClass, Op0, Op0IsKill);
389
0
}
390
391
0
unsigned fastEmit_ISD_FCEIL_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
392
0
  if (RetVT.SimpleTy != MVT::v4f32)
393
0
    return 0;
394
0
  if ((PPCSubTarget->hasVSX())) {
395
0
    return fastEmitInst_r(PPC::XVRSPIP, &PPC::VSRCRegClass, Op0, Op0IsKill);
396
0
  }
397
0
  if ((PPCSubTarget->hasAltivec())) {
398
0
    return fastEmitInst_r(PPC::VRFIP, &PPC::VRRCRegClass, Op0, Op0IsKill);
399
0
  }
400
0
  if ((PPCSubTarget->hasQPX())) {
401
0
    return fastEmitInst_r(PPC::QVFRIPs, &PPC::QSRCRegClass, Op0, Op0IsKill);
402
0
  }
403
0
  return 0;
404
0
}
405
406
0
unsigned fastEmit_ISD_FCEIL_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
407
0
  if (RetVT.SimpleTy != MVT::v2f64)
408
0
    return 0;
409
0
  if ((PPCSubTarget->hasVSX())) {
410
0
    return fastEmitInst_r(PPC::XVRDPIP, &PPC::VSRCRegClass, Op0, Op0IsKill);
411
0
  }
412
0
  return 0;
413
0
}
414
415
0
unsigned fastEmit_ISD_FCEIL_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
416
0
  if (RetVT.SimpleTy != MVT::v4f64)
417
0
    return 0;
418
0
  if ((PPCSubTarget->hasQPX())) {
419
0
    return fastEmitInst_r(PPC::QVFRIP, &PPC::QFRCRegClass, Op0, Op0IsKill);
420
0
  }
421
0
  return 0;
422
0
}
423
424
unsigned fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
425
  switch (VT.SimpleTy) {
426
  case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0, Op0IsKill);
427
  case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0, Op0IsKill);
428
  case MVT::v4f32: return fastEmit_ISD_FCEIL_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
429
  case MVT::v2f64: return fastEmit_ISD_FCEIL_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
430
  case MVT::v4f64: return fastEmit_ISD_FCEIL_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
431
  default: return 0;
432
  }
433
}
434
435
// FastEmit functions for ISD::FFLOOR.
436
437
0
unsigned fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
438
0
  if (RetVT.SimpleTy != MVT::f32)
439
0
    return 0;
440
0
  return fastEmitInst_r(PPC::FRIMS, &PPC::F4RCRegClass, Op0, Op0IsKill);
441
0
}
442
443
0
unsigned fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
444
0
  if (RetVT.SimpleTy != MVT::f64)
445
0
    return 0;
446
0
  if ((PPCSubTarget->hasVSX())) {
447
0
    return fastEmitInst_r(PPC::XSRDPIM, &PPC::VSFRCRegClass, Op0, Op0IsKill);
448
0
  }
449
0
  return fastEmitInst_r(PPC::FRIMD, &PPC::F8RCRegClass, Op0, Op0IsKill);
450
0
}
451
452
0
unsigned fastEmit_ISD_FFLOOR_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
453
0
  if (RetVT.SimpleTy != MVT::v4f32)
454
0
    return 0;
455
0
  if ((PPCSubTarget->hasVSX())) {
456
0
    return fastEmitInst_r(PPC::XVRSPIM, &PPC::VSRCRegClass, Op0, Op0IsKill);
457
0
  }
458
0
  if ((PPCSubTarget->hasAltivec())) {
459
0
    return fastEmitInst_r(PPC::VRFIM, &PPC::VRRCRegClass, Op0, Op0IsKill);
460
0
  }
461
0
  if ((PPCSubTarget->hasQPX())) {
462
0
    return fastEmitInst_r(PPC::QVFRIMs, &PPC::QSRCRegClass, Op0, Op0IsKill);
463
0
  }
464
0
  return 0;
465
0
}
466
467
0
unsigned fastEmit_ISD_FFLOOR_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
468
0
  if (RetVT.SimpleTy != MVT::v2f64)
469
0
    return 0;
470
0
  if ((PPCSubTarget->hasVSX())) {
471
0
    return fastEmitInst_r(PPC::XVRDPIM, &PPC::VSRCRegClass, Op0, Op0IsKill);
472
0
  }
473
0
  return 0;
474
0
}
475
476
0
unsigned fastEmit_ISD_FFLOOR_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
477
0
  if (RetVT.SimpleTy != MVT::v4f64)
478
0
    return 0;
479
0
  if ((PPCSubTarget->hasQPX())) {
480
0
    return fastEmitInst_r(PPC::QVFRIM, &PPC::QFRCRegClass, Op0, Op0IsKill);
481
0
  }
482
0
  return 0;
483
0
}
484
485
unsigned fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
486
  switch (VT.SimpleTy) {
487
  case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0, Op0IsKill);
488
  case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0, Op0IsKill);
489
  case MVT::v4f32: return fastEmit_ISD_FFLOOR_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
490
  case MVT::v2f64: return fastEmit_ISD_FFLOOR_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
491
  case MVT::v4f64: return fastEmit_ISD_FFLOOR_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
492
  default: return 0;
493
  }
494
}
495
496
// FastEmit functions for ISD::FNEARBYINT.
497
498
0
unsigned fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
499
0
  if (RetVT.SimpleTy != MVT::f64)
500
0
    return 0;
501
0
  if ((PPCSubTarget->hasVSX())) {
502
0
    return fastEmitInst_r(PPC::XSRDPIC, &PPC::VSFRCRegClass, Op0, Op0IsKill);
503
0
  }
504
0
  return 0;
505
0
}
506
507
0
unsigned fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
508
0
  if (RetVT.SimpleTy != MVT::v4f32)
509
0
    return 0;
510
0
  if ((PPCSubTarget->hasVSX())) {
511
0
    return fastEmitInst_r(PPC::XVRSPIC, &PPC::VSRCRegClass, Op0, Op0IsKill);
512
0
  }
513
0
  if ((PPCSubTarget->hasAltivec())) {
514
0
    return fastEmitInst_r(PPC::VRFIN, &PPC::VRRCRegClass, Op0, Op0IsKill);
515
0
  }
516
0
  return 0;
517
0
}
518
519
0
unsigned fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
520
0
  if (RetVT.SimpleTy != MVT::v2f64)
521
0
    return 0;
522
0
  if ((PPCSubTarget->hasVSX())) {
523
0
    return fastEmitInst_r(PPC::XVRDPIC, &PPC::VSRCRegClass, Op0, Op0IsKill);
524
0
  }
525
0
  return 0;
526
0
}
527
528
unsigned fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
529
  switch (VT.SimpleTy) {
530
  case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0, Op0IsKill);
531
  case MVT::v4f32: return fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
532
  case MVT::v2f64: return fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
533
  default: return 0;
534
  }
535
}
536
537
// FastEmit functions for ISD::FNEG.
538
539
0
unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
540
0
  if (RetVT.SimpleTy != MVT::f32)
541
0
    return 0;
542
0
  return fastEmitInst_r(PPC::FNEGS, &PPC::F4RCRegClass, Op0, Op0IsKill);
543
0
}
544
545
0
unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
546
0
  if (RetVT.SimpleTy != MVT::f64)
547
0
    return 0;
548
0
  if ((PPCSubTarget->hasVSX())) {
549
0
    return fastEmitInst_r(PPC::XSNEGDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
550
0
  }
551
0
  return fastEmitInst_r(PPC::FNEGD, &PPC::F8RCRegClass, Op0, Op0IsKill);
552
0
}
553
554
0
unsigned fastEmit_ISD_FNEG_MVT_f128_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
555
0
  if (RetVT.SimpleTy != MVT::f128)
556
0
    return 0;
557
0
  if ((PPCSubTarget->hasP9Vector())) {
558
0
    return fastEmitInst_r(PPC::XSNEGQP, &PPC::VRRCRegClass, Op0, Op0IsKill);
559
0
  }
560
0
  return 0;
561
0
}
562
563
0
unsigned fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
564
0
  if (RetVT.SimpleTy != MVT::v4f32)
565
0
    return 0;
566
0
  if ((PPCSubTarget->hasVSX())) {
567
0
    return fastEmitInst_r(PPC::XVNEGSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
568
0
  }
569
0
  if ((PPCSubTarget->hasQPX())) {
570
0
    return fastEmitInst_r(PPC::QVFNEGs, &PPC::QSRCRegClass, Op0, Op0IsKill);
571
0
  }
572
0
  return 0;
573
0
}
574
575
0
unsigned fastEmit_ISD_FNEG_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
576
0
  if (RetVT.SimpleTy != MVT::v2f64)
577
0
    return 0;
578
0
  if ((PPCSubTarget->hasVSX())) {
579
0
    return fastEmitInst_r(PPC::XVNEGDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
580
0
  }
581
0
  return 0;
582
0
}
583
584
0
unsigned fastEmit_ISD_FNEG_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
585
0
  if (RetVT.SimpleTy != MVT::v4f64)
586
0
    return 0;
587
0
  if ((PPCSubTarget->hasQPX())) {
588
0
    return fastEmitInst_r(PPC::QVFNEG, &PPC::QFRCRegClass, Op0, Op0IsKill);
589
0
  }
590
0
  return 0;
591
0
}
592
593
unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
594
  switch (VT.SimpleTy) {
595
  case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill);
596
  case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0, Op0IsKill);
597
  case MVT::f128: return fastEmit_ISD_FNEG_MVT_f128_r(RetVT, Op0, Op0IsKill);
598
  case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
599
  case MVT::v2f64: return fastEmit_ISD_FNEG_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
600
  case MVT::v4f64: return fastEmit_ISD_FNEG_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
601
  default: return 0;
602
  }
603
}
604
605
// FastEmit functions for ISD::FP_EXTEND.
606
607
0
unsigned fastEmit_ISD_FP_EXTEND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
608
0
  if (RetVT.SimpleTy != MVT::f128)
609
0
    return 0;
610
0
  if ((PPCSubTarget->hasP9Vector())) {
611
0
    return fastEmitInst_r(PPC::XSCVDPQP, &PPC::VRRCRegClass, Op0, Op0IsKill);
612
0
  }
613
0
  return 0;
614
0
}
615
616
unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
617
  switch (VT.SimpleTy) {
618
  case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f64_r(RetVT, Op0, Op0IsKill);
619
  default: return 0;
620
  }
621
}
622
623
// FastEmit functions for ISD::FP_ROUND.
624
625
0
unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
626
0
  if (RetVT.SimpleTy != MVT::f32)
627
0
    return 0;
628
0
  return fastEmitInst_r(PPC::FRSP, &PPC::F4RCRegClass, Op0, Op0IsKill);
629
0
}
630
631
0
unsigned fastEmit_ISD_FP_ROUND_MVT_f128_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
632
0
  if (RetVT.SimpleTy != MVT::f64)
633
0
    return 0;
634
0
  if ((PPCSubTarget->hasP9Vector())) {
635
0
    return fastEmitInst_r(PPC::XSCVQPDP, &PPC::VFRCRegClass, Op0, Op0IsKill);
636
0
  }
637
0
  return 0;
638
0
}
639
640
unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
641
  switch (VT.SimpleTy) {
642
  case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
643
  case MVT::f128: return fastEmit_ISD_FP_ROUND_MVT_f128_r(RetVT, Op0, Op0IsKill);
644
  default: return 0;
645
  }
646
}
647
648
// FastEmit functions for ISD::FP_TO_SINT.
649
650
0
unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
651
0
  if (RetVT.SimpleTy != MVT::v4i32)
652
0
    return 0;
653
0
  if ((PPCSubTarget->hasVSX())) {
654
0
    return fastEmitInst_r(PPC::XVCVSPSXWS, &PPC::VSRCRegClass, Op0, Op0IsKill);
655
0
  }
656
0
  if ((PPCSubTarget->hasAltivec())) {
657
0
    return fastEmitInst_r(PPC::VCTSXS_0, &PPC::VRRCRegClass, Op0, Op0IsKill);
658
0
  }
659
0
  return 0;
660
0
}
661
662
2
unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
663
2
  if (RetVT.SimpleTy != MVT::v2i64)
664
0
    return 0;
665
2
  if ((PPCSubTarget->hasVSX())) {
666
2
    return fastEmitInst_r(PPC::XVCVDPSXDS, &PPC::VSRCRegClass, Op0, Op0IsKill);
667
2
  }
668
0
  return 0;
669
0
}
670
671
20
unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
672
20
  switch (VT.SimpleTy) {
673
20
  
case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill)0
;
674
20
  
case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill)2
;
675
20
  
default: return 018
;
676
20
  }
677
20
}
678
679
// FastEmit functions for ISD::FP_TO_UINT.
680
681
0
unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
682
0
  if (RetVT.SimpleTy != MVT::v4i32)
683
0
    return 0;
684
0
  if ((PPCSubTarget->hasVSX())) {
685
0
    return fastEmitInst_r(PPC::XVCVSPUXWS, &PPC::VSRCRegClass, Op0, Op0IsKill);
686
0
  }
687
0
  if ((PPCSubTarget->hasAltivec())) {
688
0
    return fastEmitInst_r(PPC::VCTUXS_0, &PPC::VRRCRegClass, Op0, Op0IsKill);
689
0
  }
690
0
  return 0;
691
0
}
692
693
0
unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
694
0
  if (RetVT.SimpleTy != MVT::v2i64)
695
0
    return 0;
696
0
  if ((PPCSubTarget->hasVSX())) {
697
0
    return fastEmitInst_r(PPC::XVCVDPUXDS, &PPC::VSRCRegClass, Op0, Op0IsKill);
698
0
  }
699
0
  return 0;
700
0
}
701
702
unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
703
  switch (VT.SimpleTy) {
704
  case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
705
  case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
706
  default: return 0;
707
  }
708
}
709
710
// FastEmit functions for ISD::FROUND.
711
712
0
unsigned fastEmit_ISD_FROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
713
0
  if (RetVT.SimpleTy != MVT::f32)
714
0
    return 0;
715
0
  return fastEmitInst_r(PPC::FRINS, &PPC::F4RCRegClass, Op0, Op0IsKill);
716
0
}
717
718
0
unsigned fastEmit_ISD_FROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
719
0
  if (RetVT.SimpleTy != MVT::f64)
720
0
    return 0;
721
0
  if ((PPCSubTarget->hasVSX())) {
722
0
    return fastEmitInst_r(PPC::XSRDPI, &PPC::VSFRCRegClass, Op0, Op0IsKill);
723
0
  }
724
0
  return fastEmitInst_r(PPC::FRIND, &PPC::F8RCRegClass, Op0, Op0IsKill);
725
0
}
726
727
0
unsigned fastEmit_ISD_FROUND_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
728
0
  if (RetVT.SimpleTy != MVT::v4f32)
729
0
    return 0;
730
0
  if ((PPCSubTarget->hasVSX())) {
731
0
    return fastEmitInst_r(PPC::XVRSPI, &PPC::VSRCRegClass, Op0, Op0IsKill);
732
0
  }
733
0
  if ((PPCSubTarget->hasQPX())) {
734
0
    return fastEmitInst_r(PPC::QVFRINs, &PPC::QSRCRegClass, Op0, Op0IsKill);
735
0
  }
736
0
  return 0;
737
0
}
738
739
0
unsigned fastEmit_ISD_FROUND_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
740
0
  if (RetVT.SimpleTy != MVT::v2f64)
741
0
    return 0;
742
0
  if ((PPCSubTarget->hasVSX())) {
743
0
    return fastEmitInst_r(PPC::XVRDPI, &PPC::VSRCRegClass, Op0, Op0IsKill);
744
0
  }
745
0
  return 0;
746
0
}
747
748
0
unsigned fastEmit_ISD_FROUND_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
749
0
  if (RetVT.SimpleTy != MVT::v4f64)
750
0
    return 0;
751
0
  if ((PPCSubTarget->hasQPX())) {
752
0
    return fastEmitInst_r(PPC::QVFRIN, &PPC::QFRCRegClass, Op0, Op0IsKill);
753
0
  }
754
0
  return 0;
755
0
}
756
757
unsigned fastEmit_ISD_FROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
758
  switch (VT.SimpleTy) {
759
  case MVT::f32: return fastEmit_ISD_FROUND_MVT_f32_r(RetVT, Op0, Op0IsKill);
760
  case MVT::f64: return fastEmit_ISD_FROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
761
  case MVT::v4f32: return fastEmit_ISD_FROUND_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
762
  case MVT::v2f64: return fastEmit_ISD_FROUND_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
763
  case MVT::v4f64: return fastEmit_ISD_FROUND_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
764
  default: return 0;
765
  }
766
}
767
768
// FastEmit functions for ISD::FSQRT.
769
770
0
unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
771
0
  if (RetVT.SimpleTy != MVT::f32)
772
0
    return 0;
773
0
  if ((PPCSubTarget->hasP8Vector())) {
774
0
    return fastEmitInst_r(PPC::XSSQRTSP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
775
0
  }
776
0
  return fastEmitInst_r(PPC::FSQRTS, &PPC::F4RCRegClass, Op0, Op0IsKill);
777
0
}
778
779
0
unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
780
0
  if (RetVT.SimpleTy != MVT::f64)
781
0
    return 0;
782
0
  if ((PPCSubTarget->hasVSX())) {
783
0
    return fastEmitInst_r(PPC::XSSQRTDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
784
0
  }
785
0
  return fastEmitInst_r(PPC::FSQRT, &PPC::F8RCRegClass, Op0, Op0IsKill);
786
0
}
787
788
0
unsigned fastEmit_ISD_FSQRT_MVT_f128_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
789
0
  if (RetVT.SimpleTy != MVT::f128)
790
0
    return 0;
791
0
  if ((PPCSubTarget->hasP9Vector())) {
792
0
    return fastEmitInst_r(PPC::XSSQRTQP, &PPC::VRRCRegClass, Op0, Op0IsKill);
793
0
  }
794
0
  return 0;
795
0
}
796
797
0
unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
798
0
  if (RetVT.SimpleTy != MVT::v4f32)
799
0
    return 0;
800
0
  if ((PPCSubTarget->hasVSX())) {
801
0
    return fastEmitInst_r(PPC::XVSQRTSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
802
0
  }
803
0
  return 0;
804
0
}
805
806
0
unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
807
0
  if (RetVT.SimpleTy != MVT::v2f64)
808
0
    return 0;
809
0
  if ((PPCSubTarget->hasVSX())) {
810
0
    return fastEmitInst_r(PPC::XVSQRTDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
811
0
  }
812
0
  return 0;
813
0
}
814
815
unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
816
  switch (VT.SimpleTy) {
817
  case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill);
818
  case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0, Op0IsKill);
819
  case MVT::f128: return fastEmit_ISD_FSQRT_MVT_f128_r(RetVT, Op0, Op0IsKill);
820
  case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
821
  case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
822
  default: return 0;
823
  }
824
}
825
826
// FastEmit functions for ISD::FTRUNC.
827
828
0
unsigned fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
829
0
  if (RetVT.SimpleTy != MVT::f32)
830
0
    return 0;
831
0
  return fastEmitInst_r(PPC::FRIZS, &PPC::F4RCRegClass, Op0, Op0IsKill);
832
0
}
833
834
0
unsigned fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
835
0
  if (RetVT.SimpleTy != MVT::f64)
836
0
    return 0;
837
0
  if ((PPCSubTarget->hasVSX())) {
838
0
    return fastEmitInst_r(PPC::XSRDPIZ, &PPC::VSFRCRegClass, Op0, Op0IsKill);
839
0
  }
840
0
  return fastEmitInst_r(PPC::FRIZD, &PPC::F8RCRegClass, Op0, Op0IsKill);
841
0
}
842
843
0
unsigned fastEmit_ISD_FTRUNC_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
844
0
  if (RetVT.SimpleTy != MVT::v4f32)
845
0
    return 0;
846
0
  if ((PPCSubTarget->hasVSX())) {
847
0
    return fastEmitInst_r(PPC::XVRSPIZ, &PPC::VSRCRegClass, Op0, Op0IsKill);
848
0
  }
849
0
  if ((PPCSubTarget->hasAltivec())) {
850
0
    return fastEmitInst_r(PPC::VRFIZ, &PPC::VRRCRegClass, Op0, Op0IsKill);
851
0
  }
852
0
  if ((PPCSubTarget->hasQPX())) {
853
0
    return fastEmitInst_r(PPC::QVFRIZs, &PPC::QSRCRegClass, Op0, Op0IsKill);
854
0
  }
855
0
  return 0;
856
0
}
857
858
0
unsigned fastEmit_ISD_FTRUNC_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
859
0
  if (RetVT.SimpleTy != MVT::v2f64)
860
0
    return 0;
861
0
  if ((PPCSubTarget->hasVSX())) {
862
0
    return fastEmitInst_r(PPC::XVRDPIZ, &PPC::VSRCRegClass, Op0, Op0IsKill);
863
0
  }
864
0
  return 0;
865
0
}
866
867
0
unsigned fastEmit_ISD_FTRUNC_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
868
0
  if (RetVT.SimpleTy != MVT::v4f64)
869
0
    return 0;
870
0
  if ((PPCSubTarget->hasQPX())) {
871
0
    return fastEmitInst_r(PPC::QVFRIZ, &PPC::QFRCRegClass, Op0, Op0IsKill);
872
0
  }
873
0
  return 0;
874
0
}
875
876
unsigned fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
877
  switch (VT.SimpleTy) {
878
  case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0, Op0IsKill);
879
  case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0, Op0IsKill);
880
  case MVT::v4f32: return fastEmit_ISD_FTRUNC_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
881
  case MVT::v2f64: return fastEmit_ISD_FTRUNC_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
882
  case MVT::v4f64: return fastEmit_ISD_FTRUNC_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
883
  default: return 0;
884
  }
885
}
886
887
// FastEmit functions for ISD::SCALAR_TO_VECTOR.
888
889
0
unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
890
0
  if (RetVT.SimpleTy != MVT::v4i32)
891
0
    return 0;
892
0
  if ((PPCSubTarget->hasP9Vector())) {
893
0
    return fastEmitInst_r(PPC::MTVSRWS, &PPC::VSRCRegClass, Op0, Op0IsKill);
894
0
  }
895
0
  return 0;
896
0
}
897
898
0
unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
899
0
  if (RetVT.SimpleTy != MVT::v4f32)
900
0
    return 0;
901
0
  if ((PPCSubTarget->hasP8Vector()) && (!PPCSubTarget->isLittleEndian())) {
902
0
    return fastEmitInst_r(PPC::XSCVDPSPN, &PPC::VSRCRegClass, Op0, Op0IsKill);
903
0
  }
904
0
  return 0;
905
0
}
906
907
unsigned fastEmit_ISD_SCALAR_TO_VECTOR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
908
  switch (VT.SimpleTy) {
909
  case MVT::i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(RetVT, Op0, Op0IsKill);
910
  case MVT::f32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(RetVT, Op0, Op0IsKill);
911
  default: return 0;
912
  }
913
}
914
915
// FastEmit functions for ISD::SIGN_EXTEND.
916
917
4
unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
918
4
  if (RetVT.SimpleTy != MVT::i64)
919
0
    return 0;
920
4
  return fastEmitInst_r(PPC::EXTSW_32_64, &PPC::G8RCRegClass, Op0, Op0IsKill);
921
4
}
922
923
5
unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
924
5
  switch (VT.SimpleTy) {
925
5
  
case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0, Op0IsKill)4
;
926
5
  
default: return 01
;
927
5
  }
928
5
}
929
930
// FastEmit functions for ISD::SINT_TO_FP.
931
932
0
unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
933
0
  if (RetVT.SimpleTy != MVT::v4f32)
934
0
    return 0;
935
0
  if ((PPCSubTarget->hasVSX())) {
936
0
    return fastEmitInst_r(PPC::XVCVSXWSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
937
0
  }
938
0
  if ((PPCSubTarget->hasAltivec())) {
939
0
    return fastEmitInst_r(PPC::VCFSX_0, &PPC::VRRCRegClass, Op0, Op0IsKill);
940
0
  }
941
0
  return 0;
942
0
}
943
944
2
unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
945
2
  if (RetVT.SimpleTy != MVT::v2f64)
946
0
    return 0;
947
2
  if ((PPCSubTarget->hasVSX())) {
948
2
    return fastEmitInst_r(PPC::XVCVSXDDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
949
2
  }
950
0
  return 0;
951
0
}
952
953
16
unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
954
16
  switch (VT.SimpleTy) {
955
16
  
case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill)0
;
956
16
  
case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill)2
;
957
16
  
default: return 014
;
958
16
  }
959
16
}
960
961
// FastEmit functions for ISD::TRUNCATE.
962
963
0
unsigned fastEmit_ISD_TRUNCATE_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
964
0
  if (RetVT.SimpleTy != MVT::i1)
965
0
    return 0;
966
0
  return fastEmitInst_r(PPC::ANDIo_1_GT_BIT, &PPC::CRBITRCRegClass, Op0, Op0IsKill);
967
0
}
968
969
0
unsigned fastEmit_ISD_TRUNCATE_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
970
0
  if (RetVT.SimpleTy != MVT::i1)
971
0
    return 0;
972
0
  return fastEmitInst_r(PPC::ANDIo_1_GT_BIT8, &PPC::CRBITRCRegClass, Op0, Op0IsKill);
973
0
}
974
975
unsigned fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
976
  switch (VT.SimpleTy) {
977
  case MVT::i32: return fastEmit_ISD_TRUNCATE_MVT_i32_r(RetVT, Op0, Op0IsKill);
978
  case MVT::i64: return fastEmit_ISD_TRUNCATE_MVT_i64_r(RetVT, Op0, Op0IsKill);
979
  default: return 0;
980
  }
981
}
982
983
// FastEmit functions for ISD::UINT_TO_FP.
984
985
0
unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
986
0
  if (RetVT.SimpleTy != MVT::v4f32)
987
0
    return 0;
988
0
  if ((PPCSubTarget->hasVSX())) {
989
0
    return fastEmitInst_r(PPC::XVCVUXWSP, &PPC::VSRCRegClass, Op0, Op0IsKill);
990
0
  }
991
0
  if ((PPCSubTarget->hasAltivec())) {
992
0
    return fastEmitInst_r(PPC::VCFUX_0, &PPC::VRRCRegClass, Op0, Op0IsKill);
993
0
  }
994
0
  return 0;
995
0
}
996
997
0
unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
998
0
  if (RetVT.SimpleTy != MVT::v2f64)
999
0
    return 0;
1000
0
  if ((PPCSubTarget->hasVSX())) {
1001
0
    return fastEmitInst_r(PPC::XVCVUXDDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
1002
0
  }
1003
0
  return 0;
1004
0
}
1005
1006
unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1007
  switch (VT.SimpleTy) {
1008
  case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
1009
  case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
1010
  default: return 0;
1011
  }
1012
}
1013
1014
// FastEmit functions for PPCISD::FCFID.
1015
1016
0
unsigned fastEmit_PPCISD_FCFID_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1017
0
  if (RetVT.SimpleTy != MVT::f64)
1018
0
    return 0;
1019
0
  if ((PPCSubTarget->hasVSX())) {
1020
0
    return fastEmitInst_r(PPC::XSCVSXDDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
1021
0
  }
1022
0
  return fastEmitInst_r(PPC::FCFID, &PPC::F8RCRegClass, Op0, Op0IsKill);
1023
0
}
1024
1025
unsigned fastEmit_PPCISD_FCFID_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1026
  switch (VT.SimpleTy) {
1027
  case MVT::f64: return fastEmit_PPCISD_FCFID_MVT_f64_r(RetVT, Op0, Op0IsKill);
1028
  default: return 0;
1029
  }
1030
}
1031
1032
// FastEmit functions for PPCISD::FCFIDS.
1033
1034
0
unsigned fastEmit_PPCISD_FCFIDS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1035
0
  if (RetVT.SimpleTy != MVT::f32)
1036
0
    return 0;
1037
0
  if ((PPCSubTarget->hasP8Vector())) {
1038
0
    return fastEmitInst_r(PPC::XSCVSXDSP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
1039
0
  }
1040
0
  return fastEmitInst_r(PPC::FCFIDS, &PPC::F4RCRegClass, Op0, Op0IsKill);
1041
0
}
1042
1043
unsigned fastEmit_PPCISD_FCFIDS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1044
  switch (VT.SimpleTy) {
1045
  case MVT::f64: return fastEmit_PPCISD_FCFIDS_MVT_f64_r(RetVT, Op0, Op0IsKill);
1046
  default: return 0;
1047
  }
1048
}
1049
1050
// FastEmit functions for PPCISD::FCFIDU.
1051
1052
0
unsigned fastEmit_PPCISD_FCFIDU_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1053
0
  if (RetVT.SimpleTy != MVT::f64)
1054
0
    return 0;
1055
0
  if ((PPCSubTarget->hasVSX())) {
1056
0
    return fastEmitInst_r(PPC::XSCVUXDDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
1057
0
  }
1058
0
  return fastEmitInst_r(PPC::FCFIDU, &PPC::F8RCRegClass, Op0, Op0IsKill);
1059
0
}
1060
1061
unsigned fastEmit_PPCISD_FCFIDU_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1062
  switch (VT.SimpleTy) {
1063
  case MVT::f64: return fastEmit_PPCISD_FCFIDU_MVT_f64_r(RetVT, Op0, Op0IsKill);
1064
  default: return 0;
1065
  }
1066
}
1067
1068
// FastEmit functions for PPCISD::FCFIDUS.
1069
1070
0
unsigned fastEmit_PPCISD_FCFIDUS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1071
0
  if (RetVT.SimpleTy != MVT::f32)
1072
0
    return 0;
1073
0
  if ((PPCSubTarget->hasP8Vector())) {
1074
0
    return fastEmitInst_r(PPC::XSCVUXDSP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
1075
0
  }
1076
0
  return fastEmitInst_r(PPC::FCFIDUS, &PPC::F4RCRegClass, Op0, Op0IsKill);
1077
0
}
1078
1079
unsigned fastEmit_PPCISD_FCFIDUS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1080
  switch (VT.SimpleTy) {
1081
  case MVT::f64: return fastEmit_PPCISD_FCFIDUS_MVT_f64_r(RetVT, Op0, Op0IsKill);
1082
  default: return 0;
1083
  }
1084
}
1085
1086
// FastEmit functions for PPCISD::FCTIDUZ.
1087
1088
0
unsigned fastEmit_PPCISD_FCTIDUZ_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1089
0
  if (RetVT.SimpleTy != MVT::f32)
1090
0
    return 0;
1091
0
  if ((PPCSubTarget->hasVSX())) {
1092
0
    return fastEmitInst_r(PPC::XSCVDPUXDSs, &PPC::VSSRCRegClass, Op0, Op0IsKill);
1093
0
  }
1094
0
  return 0;
1095
0
}
1096
1097
0
unsigned fastEmit_PPCISD_FCTIDUZ_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1098
0
  if (RetVT.SimpleTy != MVT::f64)
1099
0
    return 0;
1100
0
  if ((PPCSubTarget->hasVSX())) {
1101
0
    return fastEmitInst_r(PPC::XSCVDPUXDS, &PPC::VSFRCRegClass, Op0, Op0IsKill);
1102
0
  }
1103
0
  return fastEmitInst_r(PPC::FCTIDUZ, &PPC::F8RCRegClass, Op0, Op0IsKill);
1104
0
}
1105
1106
unsigned fastEmit_PPCISD_FCTIDUZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1107
  switch (VT.SimpleTy) {
1108
  case MVT::f32: return fastEmit_PPCISD_FCTIDUZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
1109
  case MVT::f64: return fastEmit_PPCISD_FCTIDUZ_MVT_f64_r(RetVT, Op0, Op0IsKill);
1110
  default: return 0;
1111
  }
1112
}
1113
1114
// FastEmit functions for PPCISD::FCTIDZ.
1115
1116
0
unsigned fastEmit_PPCISD_FCTIDZ_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1117
0
  if (RetVT.SimpleTy != MVT::f32)
1118
0
    return 0;
1119
0
  if ((PPCSubTarget->hasVSX())) {
1120
0
    return fastEmitInst_r(PPC::XSCVDPSXDSs, &PPC::VSSRCRegClass, Op0, Op0IsKill);
1121
0
  }
1122
0
  return 0;
1123
0
}
1124
1125
0
unsigned fastEmit_PPCISD_FCTIDZ_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1126
0
  if (RetVT.SimpleTy != MVT::f64)
1127
0
    return 0;
1128
0
  if ((PPCSubTarget->hasVSX())) {
1129
0
    return fastEmitInst_r(PPC::XSCVDPSXDS, &PPC::VSFRCRegClass, Op0, Op0IsKill);
1130
0
  }
1131
0
  return fastEmitInst_r(PPC::FCTIDZ, &PPC::F8RCRegClass, Op0, Op0IsKill);
1132
0
}
1133
1134
unsigned fastEmit_PPCISD_FCTIDZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1135
  switch (VT.SimpleTy) {
1136
  case MVT::f32: return fastEmit_PPCISD_FCTIDZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
1137
  case MVT::f64: return fastEmit_PPCISD_FCTIDZ_MVT_f64_r(RetVT, Op0, Op0IsKill);
1138
  default: return 0;
1139
  }
1140
}
1141
1142
// FastEmit functions for PPCISD::FCTIWUZ.
1143
1144
0
unsigned fastEmit_PPCISD_FCTIWUZ_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1145
0
  if (RetVT.SimpleTy != MVT::f32)
1146
0
    return 0;
1147
0
  if ((PPCSubTarget->hasVSX())) {
1148
0
    return fastEmitInst_r(PPC::XSCVDPUXWSs, &PPC::VSSRCRegClass, Op0, Op0IsKill);
1149
0
  }
1150
0
  return 0;
1151
0
}
1152
1153
0
unsigned fastEmit_PPCISD_FCTIWUZ_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1154
0
  if (RetVT.SimpleTy != MVT::f64)
1155
0
    return 0;
1156
0
  if ((PPCSubTarget->hasVSX())) {
1157
0
    return fastEmitInst_r(PPC::XSCVDPUXWS, &PPC::VSFRCRegClass, Op0, Op0IsKill);
1158
0
  }
1159
0
  return fastEmitInst_r(PPC::FCTIWUZ, &PPC::F8RCRegClass, Op0, Op0IsKill);
1160
0
}
1161
1162
unsigned fastEmit_PPCISD_FCTIWUZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1163
  switch (VT.SimpleTy) {
1164
  case MVT::f32: return fastEmit_PPCISD_FCTIWUZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
1165
  case MVT::f64: return fastEmit_PPCISD_FCTIWUZ_MVT_f64_r(RetVT, Op0, Op0IsKill);
1166
  default: return 0;
1167
  }
1168
}
1169
1170
// FastEmit functions for PPCISD::FCTIWZ.
1171
1172
0
unsigned fastEmit_PPCISD_FCTIWZ_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1173
0
  if (RetVT.SimpleTy != MVT::f32)
1174
0
    return 0;
1175
0
  if ((PPCSubTarget->hasVSX())) {
1176
0
    return fastEmitInst_r(PPC::XSCVDPSXWSs, &PPC::VSSRCRegClass, Op0, Op0IsKill);
1177
0
  }
1178
0
  return 0;
1179
0
}
1180
1181
0
unsigned fastEmit_PPCISD_FCTIWZ_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1182
0
  if (RetVT.SimpleTy != MVT::f64)
1183
0
    return 0;
1184
0
  if ((PPCSubTarget->hasVSX())) {
1185
0
    return fastEmitInst_r(PPC::XSCVDPSXWS, &PPC::VSFRCRegClass, Op0, Op0IsKill);
1186
0
  }
1187
0
  return fastEmitInst_r(PPC::FCTIWZ, &PPC::F8RCRegClass, Op0, Op0IsKill);
1188
0
}
1189
1190
unsigned fastEmit_PPCISD_FCTIWZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1191
  switch (VT.SimpleTy) {
1192
  case MVT::f32: return fastEmit_PPCISD_FCTIWZ_MVT_f32_r(RetVT, Op0, Op0IsKill);
1193
  case MVT::f64: return fastEmit_PPCISD_FCTIWZ_MVT_f64_r(RetVT, Op0, Op0IsKill);
1194
  default: return 0;
1195
  }
1196
}
1197
1198
// FastEmit functions for PPCISD::FRE.
1199
1200
0
unsigned fastEmit_PPCISD_FRE_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1201
0
  if (RetVT.SimpleTy != MVT::f32)
1202
0
    return 0;
1203
0
  if ((PPCSubTarget->hasP8Vector())) {
1204
0
    return fastEmitInst_r(PPC::XSRESP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
1205
0
  }
1206
0
  return fastEmitInst_r(PPC::FRES, &PPC::F4RCRegClass, Op0, Op0IsKill);
1207
0
}
1208
1209
0
unsigned fastEmit_PPCISD_FRE_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1210
0
  if (RetVT.SimpleTy != MVT::f64)
1211
0
    return 0;
1212
0
  if ((PPCSubTarget->hasVSX())) {
1213
0
    return fastEmitInst_r(PPC::XSREDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
1214
0
  }
1215
0
  return fastEmitInst_r(PPC::FRE, &PPC::F8RCRegClass, Op0, Op0IsKill);
1216
0
}
1217
1218
0
unsigned fastEmit_PPCISD_FRE_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1219
0
  if (RetVT.SimpleTy != MVT::v4f32)
1220
0
    return 0;
1221
0
  if ((PPCSubTarget->hasVSX())) {
1222
0
    return fastEmitInst_r(PPC::XVRESP, &PPC::VSRCRegClass, Op0, Op0IsKill);
1223
0
  }
1224
0
  if ((PPCSubTarget->hasAltivec())) {
1225
0
    return fastEmitInst_r(PPC::VREFP, &PPC::VRRCRegClass, Op0, Op0IsKill);
1226
0
  }
1227
0
  if ((PPCSubTarget->hasQPX())) {
1228
0
    return fastEmitInst_r(PPC::QVFRESs, &PPC::QSRCRegClass, Op0, Op0IsKill);
1229
0
  }
1230
0
  return 0;
1231
0
}
1232
1233
0
unsigned fastEmit_PPCISD_FRE_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1234
0
  if (RetVT.SimpleTy != MVT::v2f64)
1235
0
    return 0;
1236
0
  if ((PPCSubTarget->hasVSX())) {
1237
0
    return fastEmitInst_r(PPC::XVREDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
1238
0
  }
1239
0
  return 0;
1240
0
}
1241
1242
0
unsigned fastEmit_PPCISD_FRE_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1243
0
  if (RetVT.SimpleTy != MVT::v4f64)
1244
0
    return 0;
1245
0
  if ((PPCSubTarget->hasQPX())) {
1246
0
    return fastEmitInst_r(PPC::QVFRE, &PPC::QFRCRegClass, Op0, Op0IsKill);
1247
0
  }
1248
0
  return 0;
1249
0
}
1250
1251
unsigned fastEmit_PPCISD_FRE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1252
  switch (VT.SimpleTy) {
1253
  case MVT::f32: return fastEmit_PPCISD_FRE_MVT_f32_r(RetVT, Op0, Op0IsKill);
1254
  case MVT::f64: return fastEmit_PPCISD_FRE_MVT_f64_r(RetVT, Op0, Op0IsKill);
1255
  case MVT::v4f32: return fastEmit_PPCISD_FRE_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
1256
  case MVT::v2f64: return fastEmit_PPCISD_FRE_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
1257
  case MVT::v4f64: return fastEmit_PPCISD_FRE_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
1258
  default: return 0;
1259
  }
1260
}
1261
1262
// FastEmit functions for PPCISD::FRSQRTE.
1263
1264
0
unsigned fastEmit_PPCISD_FRSQRTE_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1265
0
  if (RetVT.SimpleTy != MVT::f32)
1266
0
    return 0;
1267
0
  if ((PPCSubTarget->hasP8Vector())) {
1268
0
    return fastEmitInst_r(PPC::XSRSQRTESP, &PPC::VSSRCRegClass, Op0, Op0IsKill);
1269
0
  }
1270
0
  return fastEmitInst_r(PPC::FRSQRTES, &PPC::F4RCRegClass, Op0, Op0IsKill);
1271
0
}
1272
1273
0
unsigned fastEmit_PPCISD_FRSQRTE_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1274
0
  if (RetVT.SimpleTy != MVT::f64)
1275
0
    return 0;
1276
0
  if ((PPCSubTarget->hasVSX())) {
1277
0
    return fastEmitInst_r(PPC::XSRSQRTEDP, &PPC::VSFRCRegClass, Op0, Op0IsKill);
1278
0
  }
1279
0
  return fastEmitInst_r(PPC::FRSQRTE, &PPC::F8RCRegClass, Op0, Op0IsKill);
1280
0
}
1281
1282
0
unsigned fastEmit_PPCISD_FRSQRTE_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1283
0
  if (RetVT.SimpleTy != MVT::v4f32)
1284
0
    return 0;
1285
0
  if ((PPCSubTarget->hasVSX())) {
1286
0
    return fastEmitInst_r(PPC::XVRSQRTESP, &PPC::VSRCRegClass, Op0, Op0IsKill);
1287
0
  }
1288
0
  if ((PPCSubTarget->hasAltivec())) {
1289
0
    return fastEmitInst_r(PPC::VRSQRTEFP, &PPC::VRRCRegClass, Op0, Op0IsKill);
1290
0
  }
1291
0
  if ((PPCSubTarget->hasQPX())) {
1292
0
    return fastEmitInst_r(PPC::QVFRSQRTESs, &PPC::QSRCRegClass, Op0, Op0IsKill);
1293
0
  }
1294
0
  return 0;
1295
0
}
1296
1297
0
unsigned fastEmit_PPCISD_FRSQRTE_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1298
0
  if (RetVT.SimpleTy != MVT::v2f64)
1299
0
    return 0;
1300
0
  if ((PPCSubTarget->hasVSX())) {
1301
0
    return fastEmitInst_r(PPC::XVRSQRTEDP, &PPC::VSRCRegClass, Op0, Op0IsKill);
1302
0
  }
1303
0
  return 0;
1304
0
}
1305
1306
0
unsigned fastEmit_PPCISD_FRSQRTE_MVT_v4f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1307
0
  if (RetVT.SimpleTy != MVT::v4f64)
1308
0
    return 0;
1309
0
  if ((PPCSubTarget->hasQPX())) {
1310
0
    return fastEmitInst_r(PPC::QVFRSQRTE, &PPC::QFRCRegClass, Op0, Op0IsKill);
1311
0
  }
1312
0
  return 0;
1313
0
}
1314
1315
unsigned fastEmit_PPCISD_FRSQRTE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1316
  switch (VT.SimpleTy) {
1317
  case MVT::f32: return fastEmit_PPCISD_FRSQRTE_MVT_f32_r(RetVT, Op0, Op0IsKill);
1318
  case MVT::f64: return fastEmit_PPCISD_FRSQRTE_MVT_f64_r(RetVT, Op0, Op0IsKill);
1319
  case MVT::v4f32: return fastEmit_PPCISD_FRSQRTE_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
1320
  case MVT::v2f64: return fastEmit_PPCISD_FRSQRTE_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
1321
  case MVT::v4f64: return fastEmit_PPCISD_FRSQRTE_MVT_v4f64_r(RetVT, Op0, Op0IsKill);
1322
  default: return 0;
1323
  }
1324
}
1325
1326
// FastEmit functions for PPCISD::MFVSR.
1327
1328
0
unsigned fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i32_r(unsigned Op0, bool Op0IsKill) {
1329
0
  if ((PPCSubTarget->hasDirectMove())) {
1330
0
    return fastEmitInst_r(PPC::MFVSRWZ, &PPC::GPRCRegClass, Op0, Op0IsKill);
1331
0
  }
1332
0
  return 0;
1333
0
}
1334
1335
0
unsigned fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i64_r(unsigned Op0, bool Op0IsKill) {
1336
0
  if ((PPCSubTarget->hasDirectMove())) {
1337
0
    return fastEmitInst_r(PPC::MFVSRD, &PPC::G8RCRegClass, Op0, Op0IsKill);
1338
0
  }
1339
0
  return 0;
1340
0
}
1341
1342
unsigned fastEmit_PPCISD_MFVSR_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1343
switch (RetVT.SimpleTy) {
1344
  case MVT::i32: return fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i32_r(Op0, Op0IsKill);
1345
  case MVT::i64: return fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i64_r(Op0, Op0IsKill);
1346
  default: return 0;
1347
}
1348
}
1349
1350
unsigned fastEmit_PPCISD_MFVSR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1351
  switch (VT.SimpleTy) {
1352
  case MVT::f64: return fastEmit_PPCISD_MFVSR_MVT_f64_r(RetVT, Op0, Op0IsKill);
1353
  default: return 0;
1354
  }
1355
}
1356
1357
// FastEmit functions for PPCISD::MTCTR.
1358
1359
0
unsigned fastEmit_PPCISD_MTCTR_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1360
0
  if (RetVT.SimpleTy != MVT::isVoid)
1361
0
    return 0;
1362
0
  return fastEmitInst_r(PPC::MTCTR, &PPC::GPRCRegClass, Op0, Op0IsKill);
1363
0
}
1364
1365
0
unsigned fastEmit_PPCISD_MTCTR_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1366
0
  if (RetVT.SimpleTy != MVT::isVoid)
1367
0
    return 0;
1368
0
  return fastEmitInst_r(PPC::MTCTR8, &PPC::G8RCRegClass, Op0, Op0IsKill);
1369
0
}
1370
1371
unsigned fastEmit_PPCISD_MTCTR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1372
  switch (VT.SimpleTy) {
1373
  case MVT::i32: return fastEmit_PPCISD_MTCTR_MVT_i32_r(RetVT, Op0, Op0IsKill);
1374
  case MVT::i64: return fastEmit_PPCISD_MTCTR_MVT_i64_r(RetVT, Op0, Op0IsKill);
1375
  default: return 0;
1376
  }
1377
}
1378
1379
// FastEmit functions for PPCISD::MTVSRA.
1380
1381
0
unsigned fastEmit_PPCISD_MTVSRA_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1382
0
  if (RetVT.SimpleTy != MVT::f64)
1383
0
    return 0;
1384
0
  if ((PPCSubTarget->hasDirectMove())) {
1385
0
    return fastEmitInst_r(PPC::MTVSRWA, &PPC::VSFRCRegClass, Op0, Op0IsKill);
1386
0
  }
1387
0
  return 0;
1388
0
}
1389
1390
0
unsigned fastEmit_PPCISD_MTVSRA_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1391
0
  if (RetVT.SimpleTy != MVT::f64)
1392
0
    return 0;
1393
0
  if ((PPCSubTarget->hasDirectMove())) {
1394
0
    return fastEmitInst_r(PPC::MTVSRD, &PPC::VSFRCRegClass, Op0, Op0IsKill);
1395
0
  }
1396
0
  return 0;
1397
0
}
1398
1399
unsigned fastEmit_PPCISD_MTVSRA_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1400
  switch (VT.SimpleTy) {
1401
  case MVT::i32: return fastEmit_PPCISD_MTVSRA_MVT_i32_r(RetVT, Op0, Op0IsKill);
1402
  case MVT::i64: return fastEmit_PPCISD_MTVSRA_MVT_i64_r(RetVT, Op0, Op0IsKill);
1403
  default: return 0;
1404
  }
1405
}
1406
1407
// FastEmit functions for PPCISD::MTVSRZ.
1408
1409
0
unsigned fastEmit_PPCISD_MTVSRZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1410
0
  if (RetVT.SimpleTy != MVT::f64)
1411
0
    return 0;
1412
0
  if ((PPCSubTarget->hasDirectMove())) {
1413
0
    return fastEmitInst_r(PPC::MTVSRWZ, &PPC::VSFRCRegClass, Op0, Op0IsKill);
1414
0
  }
1415
0
  return 0;
1416
0
}
1417
1418
unsigned fastEmit_PPCISD_MTVSRZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1419
  switch (VT.SimpleTy) {
1420
  case MVT::i32: return fastEmit_PPCISD_MTVSRZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
1421
  default: return 0;
1422
  }
1423
}
1424
1425
// FastEmit functions for PPCISD::SExtVElems.
1426
1427
0
unsigned fastEmit_PPCISD_SExtVElems_MVT_v16i8_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
1428
0
  if ((PPCSubTarget->hasP9Altivec())) {
1429
0
    return fastEmitInst_r(PPC::VEXTSB2W, &PPC::VRRCRegClass, Op0, Op0IsKill);
1430
0
  }
1431
0
  return 0;
1432
0
}
1433
1434
0
unsigned fastEmit_PPCISD_SExtVElems_MVT_v16i8_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
1435
0
  if ((PPCSubTarget->hasP9Altivec())) {
1436
0
    return fastEmitInst_r(PPC::VEXTSB2D, &PPC::VRRCRegClass, Op0, Op0IsKill);
1437
0
  }
1438
0
  return 0;
1439
0
}
1440
1441
unsigned fastEmit_PPCISD_SExtVElems_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1442
switch (RetVT.SimpleTy) {
1443
  case MVT::v4i32: return fastEmit_PPCISD_SExtVElems_MVT_v16i8_MVT_v4i32_r(Op0, Op0IsKill);
1444
  case MVT::v2i64: return fastEmit_PPCISD_SExtVElems_MVT_v16i8_MVT_v2i64_r(Op0, Op0IsKill);
1445
  default: return 0;
1446
}
1447
}
1448
1449
0
unsigned fastEmit_PPCISD_SExtVElems_MVT_v8i16_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
1450
0
  if ((PPCSubTarget->hasP9Altivec())) {
1451
0
    return fastEmitInst_r(PPC::VEXTSH2W, &PPC::VRRCRegClass, Op0, Op0IsKill);
1452
0
  }
1453
0
  return 0;
1454
0
}
1455
1456
0
unsigned fastEmit_PPCISD_SExtVElems_MVT_v8i16_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
1457
0
  if ((PPCSubTarget->hasP9Altivec())) {
1458
0
    return fastEmitInst_r(PPC::VEXTSH2D, &PPC::VRRCRegClass, Op0, Op0IsKill);
1459
0
  }
1460
0
  return 0;
1461
0
}
1462
1463
unsigned fastEmit_PPCISD_SExtVElems_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1464
switch (RetVT.SimpleTy) {
1465
  case MVT::v4i32: return fastEmit_PPCISD_SExtVElems_MVT_v8i16_MVT_v4i32_r(Op0, Op0IsKill);
1466
  case MVT::v2i64: return fastEmit_PPCISD_SExtVElems_MVT_v8i16_MVT_v2i64_r(Op0, Op0IsKill);
1467
  default: return 0;
1468
}
1469
}
1470
1471
0
unsigned fastEmit_PPCISD_SExtVElems_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1472
0
  if (RetVT.SimpleTy != MVT::v2i64)
1473
0
    return 0;
1474
0
  if ((PPCSubTarget->hasP9Altivec())) {
1475
0
    return fastEmitInst_r(PPC::VEXTSW2D, &PPC::VRRCRegClass, Op0, Op0IsKill);
1476
0
  }
1477
0
  return 0;
1478
0
}
1479
1480
unsigned fastEmit_PPCISD_SExtVElems_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1481
  switch (VT.SimpleTy) {
1482
  case MVT::v16i8: return fastEmit_PPCISD_SExtVElems_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
1483
  case MVT::v8i16: return fastEmit_PPCISD_SExtVElems_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
1484
  case MVT::v4i32: return fastEmit_PPCISD_SExtVElems_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
1485
  default: return 0;
1486
  }
1487
}
1488
1489
// FastEmit functions for PPCISD::XXREVERSE.
1490
1491
0
unsigned fastEmit_PPCISD_XXREVERSE_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1492
0
  if (RetVT.SimpleTy != MVT::v4i32)
1493
0
    return 0;
1494
0
  if ((PPCSubTarget->hasP9Vector())) {
1495
0
    return fastEmitInst_r(PPC::XXBRW, &PPC::VSRCRegClass, Op0, Op0IsKill);
1496
0
  }
1497
0
  return 0;
1498
0
}
1499
1500
0
unsigned fastEmit_PPCISD_XXREVERSE_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1501
0
  if (RetVT.SimpleTy != MVT::v2i64)
1502
0
    return 0;
1503
0
  if ((PPCSubTarget->hasP9Vector())) {
1504
0
    return fastEmitInst_r(PPC::XXBRD, &PPC::VSRCRegClass, Op0, Op0IsKill);
1505
0
  }
1506
0
  return 0;
1507
0
}
1508
1509
unsigned fastEmit_PPCISD_XXREVERSE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1510
  switch (VT.SimpleTy) {
1511
  case MVT::v4i32: return fastEmit_PPCISD_XXREVERSE_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
1512
  case MVT::v2i64: return fastEmit_PPCISD_XXREVERSE_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
1513
  default: return 0;
1514
  }
1515
}
1516
1517
// Top-level FastEmit function.
1518
1519
45
unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill) override {
1520
45
  switch (Opcode) {
1521
45
  
case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0, Op0IsKill)2
;
1522
45
  
case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill)0
;
1523
45
  
case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill)0
;
1524
45
  
case ISD::CTTZ: return fastEmit_ISD_CTTZ_r(VT, RetVT, Op0, Op0IsKill)0
;
1525
45
  
case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill)0
;
1526
45
  
case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0, Op0IsKill)0
;
1527
45
  
case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0, Op0IsKill)0
;
1528
45
  
case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0, Op0IsKill)0
;
1529
45
  
case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill)0
;
1530
45
  
case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill)0
;
1531
45
  
case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill)0
;
1532
45
  
case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill)20
;
1533
45
  
case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill)0
;
1534
45
  
case ISD::FROUND: return fastEmit_ISD_FROUND_r(VT, RetVT, Op0, Op0IsKill)0
;
1535
45
  
case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill)0
;
1536
45
  
case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0, Op0IsKill)0
;
1537
45
  
case ISD::SCALAR_TO_VECTOR: return fastEmit_ISD_SCALAR_TO_VECTOR_r(VT, RetVT, Op0, Op0IsKill)0
;
1538
45
  
case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill)5
;
1539
45
  
case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill)16
;
1540
45
  
case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0, Op0IsKill)0
;
1541
45
  
case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill)0
;
1542
45
  
case PPCISD::FCFID: return fastEmit_PPCISD_FCFID_r(VT, RetVT, Op0, Op0IsKill)0
;
1543
45
  
case PPCISD::FCFIDS: return fastEmit_PPCISD_FCFIDS_r(VT, RetVT, Op0, Op0IsKill)0
;
1544
45
  
case PPCISD::FCFIDU: return fastEmit_PPCISD_FCFIDU_r(VT, RetVT, Op0, Op0IsKill)0
;
1545
45
  
case PPCISD::FCFIDUS: return fastEmit_PPCISD_FCFIDUS_r(VT, RetVT, Op0, Op0IsKill)0
;
1546
45
  
case PPCISD::FCTIDUZ: return fastEmit_PPCISD_FCTIDUZ_r(VT, RetVT, Op0, Op0IsKill)0
;
1547
45
  
case PPCISD::FCTIDZ: return fastEmit_PPCISD_FCTIDZ_r(VT, RetVT, Op0, Op0IsKill)0
;
1548
45
  
case PPCISD::FCTIWUZ: return fastEmit_PPCISD_FCTIWUZ_r(VT, RetVT, Op0, Op0IsKill)0
;
1549
45
  
case PPCISD::FCTIWZ: return fastEmit_PPCISD_FCTIWZ_r(VT, RetVT, Op0, Op0IsKill)0
;
1550
45
  
case PPCISD::FRE: return fastEmit_PPCISD_FRE_r(VT, RetVT, Op0, Op0IsKill)0
;
1551
45
  
case PPCISD::FRSQRTE: return fastEmit_PPCISD_FRSQRTE_r(VT, RetVT, Op0, Op0IsKill)0
;
1552
45
  
case PPCISD::MFVSR: return fastEmit_PPCISD_MFVSR_r(VT, RetVT, Op0, Op0IsKill)0
;
1553
45
  
case PPCISD::MTCTR: return fastEmit_PPCISD_MTCTR_r(VT, RetVT, Op0, Op0IsKill)0
;
1554
45
  
case PPCISD::MTVSRA: return fastEmit_PPCISD_MTVSRA_r(VT, RetVT, Op0, Op0IsKill)0
;
1555
45
  
case PPCISD::MTVSRZ: return fastEmit_PPCISD_MTVSRZ_r(VT, RetVT, Op0, Op0IsKill)0
;
1556
45
  
case PPCISD::SExtVElems: return fastEmit_PPCISD_SExtVElems_r(VT, RetVT, Op0, Op0IsKill)0
;
1557
45
  
case PPCISD::XXREVERSE: return fastEmit_PPCISD_XXREVERSE_r(VT, RetVT, Op0, Op0IsKill)0
;
1558
45
  
default: return 02
;
1559
45
  }
1560
45
}
1561
1562
// FastEmit functions for ISD::ADD.
1563
1564
0
unsigned fastEmit_ISD_ADD_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1565
0
  if (RetVT.SimpleTy != MVT::i1)
1566
0
    return 0;
1567
0
  return fastEmitInst_rr(PPC::CRXOR, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1568
0
}
1569
1570
0
unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1571
0
  if (RetVT.SimpleTy != MVT::i32)
1572
0
    return 0;
1573
0
  return fastEmitInst_rr(PPC::ADD4, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1574
0
}
1575
1576
0
unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1577
0
  if (RetVT.SimpleTy != MVT::i64)
1578
0
    return 0;
1579
0
  return fastEmitInst_rr(PPC::ADD8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1580
0
}
1581
1582
0
unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1583
0
  if (RetVT.SimpleTy != MVT::v16i8)
1584
0
    return 0;
1585
0
  if ((PPCSubTarget->hasAltivec())) {
1586
0
    return fastEmitInst_rr(PPC::VADDUBM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1587
0
  }
1588
0
  return 0;
1589
0
}
1590
1591
0
unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1592
0
  if (RetVT.SimpleTy != MVT::v8i16)
1593
0
    return 0;
1594
0
  if ((PPCSubTarget->hasAltivec())) {
1595
0
    return fastEmitInst_rr(PPC::VADDUHM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1596
0
  }
1597
0
  return 0;
1598
0
}
1599
1600
0
unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1601
0
  if (RetVT.SimpleTy != MVT::v4i32)
1602
0
    return 0;
1603
0
  if ((PPCSubTarget->hasAltivec())) {
1604
0
    return fastEmitInst_rr(PPC::VADDUWM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1605
0
  }
1606
0
  return 0;
1607
0
}
1608
1609
2
unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1610
2
  if (RetVT.SimpleTy != MVT::v2i64)
1611
0
    return 0;
1612
2
  if ((PPCSubTarget->hasP8Altivec())) {
1613
0
    return fastEmitInst_rr(PPC::VADDUDM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1614
0
  }
1615
2
  return 0;
1616
2
}
1617
1618
0
unsigned fastEmit_ISD_ADD_MVT_v1i128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1619
0
  if (RetVT.SimpleTy != MVT::v1i128)
1620
0
    return 0;
1621
0
  if ((PPCSubTarget->hasP8Altivec())) {
1622
0
    return fastEmitInst_rr(PPC::VADDUQM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1623
0
  }
1624
0
  return 0;
1625
0
}
1626
1627
2
unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1628
2
  switch (VT.SimpleTy) {
1629
2
  
case MVT::i1: return fastEmit_ISD_ADD_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1630
2
  
case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1631
2
  
case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1632
2
  
case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1633
2
  
case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1634
2
  
case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1635
2
  case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1636
2
  
case MVT::v1i128: return fastEmit_ISD_ADD_MVT_v1i128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1637
2
  
default: return 00
;
1638
2
  }
1639
2
}
1640
1641
// FastEmit functions for ISD::ADDC.
1642
1643
0
unsigned fastEmit_ISD_ADDC_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1644
0
  if (RetVT.SimpleTy != MVT::i32)
1645
0
    return 0;
1646
0
  return fastEmitInst_rr(PPC::ADDC, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1647
0
}
1648
1649
0
unsigned fastEmit_ISD_ADDC_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1650
0
  if (RetVT.SimpleTy != MVT::i64)
1651
0
    return 0;
1652
0
  return fastEmitInst_rr(PPC::ADDC8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1653
0
}
1654
1655
unsigned fastEmit_ISD_ADDC_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1656
  switch (VT.SimpleTy) {
1657
  case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1658
  case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1659
  default: return 0;
1660
  }
1661
}
1662
1663
// FastEmit functions for ISD::ADDE.
1664
1665
0
unsigned fastEmit_ISD_ADDE_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1666
0
  if (RetVT.SimpleTy != MVT::i32)
1667
0
    return 0;
1668
0
  return fastEmitInst_rr(PPC::ADDE, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1669
0
}
1670
1671
0
unsigned fastEmit_ISD_ADDE_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1672
0
  if (RetVT.SimpleTy != MVT::i64)
1673
0
    return 0;
1674
0
  return fastEmitInst_rr(PPC::ADDE8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1675
0
}
1676
1677
unsigned fastEmit_ISD_ADDE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1678
  switch (VT.SimpleTy) {
1679
  case MVT::i32: return fastEmit_ISD_ADDE_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1680
  case MVT::i64: return fastEmit_ISD_ADDE_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1681
  default: return 0;
1682
  }
1683
}
1684
1685
// FastEmit functions for ISD::AND.
1686
1687
0
unsigned fastEmit_ISD_AND_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1688
0
  if (RetVT.SimpleTy != MVT::i1)
1689
0
    return 0;
1690
0
  return fastEmitInst_rr(PPC::CRAND, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1691
0
}
1692
1693
0
unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1694
0
  if (RetVT.SimpleTy != MVT::i32)
1695
0
    return 0;
1696
0
  return fastEmitInst_rr(PPC::AND, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1697
0
}
1698
1699
1
unsigned fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1700
1
  if (RetVT.SimpleTy != MVT::i64)
1701
0
    return 0;
1702
1
  return fastEmitInst_rr(PPC::AND8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1703
1
}
1704
1705
4
unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1706
4
  if (RetVT.SimpleTy != MVT::v4i32)
1707
0
    return 0;
1708
4
  if ((PPCSubTarget->hasVSX())) {
1709
4
    return fastEmitInst_rr(PPC::XXLAND, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1710
4
  }
1711
0
  if ((PPCSubTarget->hasAltivec())) {
1712
0
    return fastEmitInst_rr(PPC::VAND, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1713
0
  }
1714
0
  return 0;
1715
0
}
1716
1717
15
unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1718
15
  switch (VT.SimpleTy) {
1719
15
  
case MVT::i1: return fastEmit_ISD_AND_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1720
15
  
case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1721
15
  
case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)1
;
1722
15
  
case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)4
;
1723
15
  
default: return 010
;
1724
15
  }
1725
15
}
1726
1727
// FastEmit functions for ISD::BUILD_VECTOR.
1728
1729
0
unsigned fastEmit_ISD_BUILD_VECTOR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1730
0
  if (RetVT.SimpleTy != MVT::v2i64)
1731
0
    return 0;
1732
0
  if ((PPCSubTarget->hasDirectMove()) && (!PPCSubTarget->isLittleEndian()) && (PPCSubTarget->isISA3_0())) {
1733
0
    return fastEmitInst_rr(PPC::MTVSRDD, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1734
0
  }
1735
0
  return 0;
1736
0
}
1737
1738
unsigned fastEmit_ISD_BUILD_VECTOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1739
  switch (VT.SimpleTy) {
1740
  case MVT::i64: return fastEmit_ISD_BUILD_VECTOR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1741
  default: return 0;
1742
  }
1743
}
1744
1745
// FastEmit functions for ISD::FADD.
1746
1747
2
unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1748
2
  if (RetVT.SimpleTy != MVT::f32)
1749
0
    return 0;
1750
2
  if ((PPCSubTarget->hasP8Vector())) {
1751
0
    return fastEmitInst_rr(PPC::XSADDSP, &PPC::VSSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1752
0
  }
1753
2
  return fastEmitInst_rr(PPC::FADDS, &PPC::F4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1754
2
}
1755
1756
10
unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1757
10
  if (RetVT.SimpleTy != MVT::f64)
1758
0
    return 0;
1759
10
  if ((PPCSubTarget->hasVSX())) {
1760
8
    return fastEmitInst_rr(PPC::XSADDDP, &PPC::VSFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1761
8
  }
1762
2
  return fastEmitInst_rr(PPC::FADD, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1763
2
}
1764
1765
0
unsigned fastEmit_ISD_FADD_MVT_f128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1766
0
  if (RetVT.SimpleTy != MVT::f128)
1767
0
    return 0;
1768
0
  if ((PPCSubTarget->hasP9Vector())) {
1769
0
    return fastEmitInst_rr(PPC::XSADDQP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1770
0
  }
1771
0
  return 0;
1772
0
}
1773
1774
0
unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1775
0
  if (RetVT.SimpleTy != MVT::v4f32)
1776
0
    return 0;
1777
0
  if ((PPCSubTarget->hasVSX())) {
1778
0
    return fastEmitInst_rr(PPC::XVADDSP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1779
0
  }
1780
0
  if ((PPCSubTarget->hasQPX())) {
1781
0
    return fastEmitInst_rr(PPC::QVFADDSs, &PPC::QSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1782
0
  }
1783
0
  if ((PPCSubTarget->hasAltivec())) {
1784
0
    return fastEmitInst_rr(PPC::VADDFP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1785
0
  }
1786
0
  return 0;
1787
0
}
1788
1789
2
unsigned fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1790
2
  if (RetVT.SimpleTy != MVT::v2f64)
1791
0
    return 0;
1792
2
  if ((PPCSubTarget->hasVSX())) {
1793
2
    return fastEmitInst_rr(PPC::XVADDDP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1794
2
  }
1795
0
  return 0;
1796
0
}
1797
1798
0
unsigned fastEmit_ISD_FADD_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1799
0
  if (RetVT.SimpleTy != MVT::v4f64)
1800
0
    return 0;
1801
0
  if ((PPCSubTarget->hasQPX())) {
1802
0
    return fastEmitInst_rr(PPC::QVFADD, &PPC::QFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1803
0
  }
1804
0
  return 0;
1805
0
}
1806
1807
14
unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1808
14
  switch (VT.SimpleTy) {
1809
14
  
case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)2
;
1810
14
  
case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)10
;
1811
14
  
case MVT::f128: return fastEmit_ISD_FADD_MVT_f128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1812
14
  
case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1813
14
  
case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)2
;
1814
14
  
case MVT::v4f64: return fastEmit_ISD_FADD_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1815
14
  
default: return 00
;
1816
14
  }
1817
14
}
1818
1819
// FastEmit functions for ISD::FDIV.
1820
1821
0
unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1822
0
  if (RetVT.SimpleTy != MVT::f32)
1823
0
    return 0;
1824
0
  if ((PPCSubTarget->hasP8Vector())) {
1825
0
    return fastEmitInst_rr(PPC::XSDIVSP, &PPC::VSSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1826
0
  }
1827
0
  return fastEmitInst_rr(PPC::FDIVS, &PPC::F4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1828
0
}
1829
1830
2
unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1831
2
  if (RetVT.SimpleTy != MVT::f64)
1832
0
    return 0;
1833
2
  if ((PPCSubTarget->hasVSX())) {
1834
2
    return fastEmitInst_rr(PPC::XSDIVDP, &PPC::VSFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1835
2
  }
1836
0
  return fastEmitInst_rr(PPC::FDIV, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1837
0
}
1838
1839
0
unsigned fastEmit_ISD_FDIV_MVT_f128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1840
0
  if (RetVT.SimpleTy != MVT::f128)
1841
0
    return 0;
1842
0
  if ((PPCSubTarget->hasP9Vector())) {
1843
0
    return fastEmitInst_rr(PPC::XSDIVQP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1844
0
  }
1845
0
  return 0;
1846
0
}
1847
1848
0
unsigned fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1849
0
  if (RetVT.SimpleTy != MVT::v4f32)
1850
0
    return 0;
1851
0
  if ((PPCSubTarget->hasVSX())) {
1852
0
    return fastEmitInst_rr(PPC::XVDIVSP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1853
0
  }
1854
0
  return 0;
1855
0
}
1856
1857
0
unsigned fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1858
0
  if (RetVT.SimpleTy != MVT::v2f64)
1859
0
    return 0;
1860
0
  if ((PPCSubTarget->hasVSX())) {
1861
0
    return fastEmitInst_rr(PPC::XVDIVDP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1862
0
  }
1863
0
  return 0;
1864
0
}
1865
1866
2
unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1867
2
  switch (VT.SimpleTy) {
1868
2
  
case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1869
2
  case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1870
2
  
case MVT::f128: return fastEmit_ISD_FDIV_MVT_f128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1871
2
  
case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1872
2
  
case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1873
2
  
default: return 00
;
1874
2
  }
1875
2
}
1876
1877
// FastEmit functions for ISD::FMUL.
1878
1879
0
unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1880
0
  if (RetVT.SimpleTy != MVT::f32)
1881
0
    return 0;
1882
0
  if ((PPCSubTarget->hasP8Vector())) {
1883
0
    return fastEmitInst_rr(PPC::XSMULSP, &PPC::VSSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1884
0
  }
1885
0
  return fastEmitInst_rr(PPC::FMULS, &PPC::F4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1886
0
}
1887
1888
2
unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1889
2
  if (RetVT.SimpleTy != MVT::f64)
1890
0
    return 0;
1891
2
  if ((PPCSubTarget->hasVSX())) {
1892
2
    return fastEmitInst_rr(PPC::XSMULDP, &PPC::VSFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1893
2
  }
1894
0
  return fastEmitInst_rr(PPC::FMUL, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1895
0
}
1896
1897
0
unsigned fastEmit_ISD_FMUL_MVT_f128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1898
0
  if (RetVT.SimpleTy != MVT::f128)
1899
0
    return 0;
1900
0
  if ((PPCSubTarget->hasP9Vector())) {
1901
0
    return fastEmitInst_rr(PPC::XSMULQP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1902
0
  }
1903
0
  return 0;
1904
0
}
1905
1906
0
unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1907
0
  if (RetVT.SimpleTy != MVT::v4f32)
1908
0
    return 0;
1909
0
  if ((PPCSubTarget->hasVSX())) {
1910
0
    return fastEmitInst_rr(PPC::XVMULSP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1911
0
  }
1912
0
  if ((PPCSubTarget->hasQPX())) {
1913
0
    return fastEmitInst_rr(PPC::QVFMULSs, &PPC::QSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1914
0
  }
1915
0
  return 0;
1916
0
}
1917
1918
0
unsigned fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1919
0
  if (RetVT.SimpleTy != MVT::v2f64)
1920
0
    return 0;
1921
0
  if ((PPCSubTarget->hasVSX())) {
1922
0
    return fastEmitInst_rr(PPC::XVMULDP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1923
0
  }
1924
0
  return 0;
1925
0
}
1926
1927
0
unsigned fastEmit_ISD_FMUL_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1928
0
  if (RetVT.SimpleTy != MVT::v4f64)
1929
0
    return 0;
1930
0
  if ((PPCSubTarget->hasQPX())) {
1931
0
    return fastEmitInst_rr(PPC::QVFMUL, &PPC::QFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1932
0
  }
1933
0
  return 0;
1934
0
}
1935
1936
2
unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1937
2
  switch (VT.SimpleTy) {
1938
2
  
case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1939
2
  case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
1940
2
  
case MVT::f128: return fastEmit_ISD_FMUL_MVT_f128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1941
2
  
case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1942
2
  
case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1943
2
  
case MVT::v4f64: return fastEmit_ISD_FMUL_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
1944
2
  
default: return 00
;
1945
2
  }
1946
2
}
1947
1948
// FastEmit functions for ISD::FSUB.
1949
1950
0
unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1951
0
  if (RetVT.SimpleTy != MVT::f32)
1952
0
    return 0;
1953
0
  if ((PPCSubTarget->hasP8Vector())) {
1954
0
    return fastEmitInst_rr(PPC::XSSUBSP, &PPC::VSSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1955
0
  }
1956
0
  return fastEmitInst_rr(PPC::FSUBS, &PPC::F4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1957
0
}
1958
1959
0
unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1960
0
  if (RetVT.SimpleTy != MVT::f64)
1961
0
    return 0;
1962
0
  if ((PPCSubTarget->hasVSX())) {
1963
0
    return fastEmitInst_rr(PPC::XSSUBDP, &PPC::VSFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1964
0
  }
1965
0
  return fastEmitInst_rr(PPC::FSUB, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1966
0
}
1967
1968
0
unsigned fastEmit_ISD_FSUB_MVT_f128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1969
0
  if (RetVT.SimpleTy != MVT::f128)
1970
0
    return 0;
1971
0
  if ((PPCSubTarget->hasP9Vector())) {
1972
0
    return fastEmitInst_rr(PPC::XSSUBQP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1973
0
  }
1974
0
  return 0;
1975
0
}
1976
1977
0
unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1978
0
  if (RetVT.SimpleTy != MVT::v4f32)
1979
0
    return 0;
1980
0
  if ((PPCSubTarget->hasVSX())) {
1981
0
    return fastEmitInst_rr(PPC::XVSUBSP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1982
0
  }
1983
0
  if ((PPCSubTarget->hasQPX())) {
1984
0
    return fastEmitInst_rr(PPC::QVFSUBSs, &PPC::QSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1985
0
  }
1986
0
  if ((PPCSubTarget->hasAltivec())) {
1987
0
    return fastEmitInst_rr(PPC::VSUBFP, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1988
0
  }
1989
0
  return 0;
1990
0
}
1991
1992
0
unsigned fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
1993
0
  if (RetVT.SimpleTy != MVT::v2f64)
1994
0
    return 0;
1995
0
  if ((PPCSubTarget->hasVSX())) {
1996
0
    return fastEmitInst_rr(PPC::XVSUBDP, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1997
0
  }
1998
0
  return 0;
1999
0
}
2000
2001
0
unsigned fastEmit_ISD_FSUB_MVT_v4f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2002
0
  if (RetVT.SimpleTy != MVT::v4f64)
2003
0
    return 0;
2004
0
  if ((PPCSubTarget->hasQPX())) {
2005
0
    return fastEmitInst_rr(PPC::QVFSUB, &PPC::QFRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2006
0
  }
2007
0
  return 0;
2008
0
}
2009
2010
unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2011
  switch (VT.SimpleTy) {
2012
  case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2013
  case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2014
  case MVT::f128: return fastEmit_ISD_FSUB_MVT_f128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2015
  case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2016
  case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2017
  case MVT::v4f64: return fastEmit_ISD_FSUB_MVT_v4f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2018
  default: return 0;
2019
  }
2020
}
2021
2022
// FastEmit functions for ISD::MUL.
2023
2024
0
unsigned fastEmit_ISD_MUL_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2025
0
  if (RetVT.SimpleTy != MVT::i1)
2026
0
    return 0;
2027
0
  return fastEmitInst_rr(PPC::CRAND, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2028
0
}
2029
2030
0
unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2031
0
  if (RetVT.SimpleTy != MVT::i32)
2032
0
    return 0;
2033
0
  return fastEmitInst_rr(PPC::MULLW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2034
0
}
2035
2036
0
unsigned fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2037
0
  if (RetVT.SimpleTy != MVT::i64)
2038
0
    return 0;
2039
0
  return fastEmitInst_rr(PPC::MULLD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2040
0
}
2041
2042
0
unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2043
0
  if (RetVT.SimpleTy != MVT::v4i32)
2044
0
    return 0;
2045
0
  if ((PPCSubTarget->hasP8Altivec())) {
2046
0
    return fastEmitInst_rr(PPC::VMULUWM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2047
0
  }
2048
0
  return 0;
2049
0
}
2050
2051
unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2052
  switch (VT.SimpleTy) {
2053
  case MVT::i1: return fastEmit_ISD_MUL_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2054
  case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2055
  case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2056
  case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2057
  default: return 0;
2058
  }
2059
}
2060
2061
// FastEmit functions for ISD::MULHS.
2062
2063
0
unsigned fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2064
0
  if (RetVT.SimpleTy != MVT::i32)
2065
0
    return 0;
2066
0
  return fastEmitInst_rr(PPC::MULHW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2067
0
}
2068
2069
0
unsigned fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2070
0
  if (RetVT.SimpleTy != MVT::i64)
2071
0
    return 0;
2072
0
  return fastEmitInst_rr(PPC::MULHD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2073
0
}
2074
2075
unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2076
  switch (VT.SimpleTy) {
2077
  case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2078
  case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2079
  default: return 0;
2080
  }
2081
}
2082
2083
// FastEmit functions for ISD::MULHU.
2084
2085
0
unsigned fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2086
0
  if (RetVT.SimpleTy != MVT::i32)
2087
0
    return 0;
2088
0
  return fastEmitInst_rr(PPC::MULHWU, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2089
0
}
2090
2091
0
unsigned fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2092
0
  if (RetVT.SimpleTy != MVT::i64)
2093
0
    return 0;
2094
0
  return fastEmitInst_rr(PPC::MULHDU, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2095
0
}
2096
2097
unsigned fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2098
  switch (VT.SimpleTy) {
2099
  case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2100
  case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2101
  default: return 0;
2102
  }
2103
}
2104
2105
// FastEmit functions for ISD::OR.
2106
2107
0
unsigned fastEmit_ISD_OR_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2108
0
  if (RetVT.SimpleTy != MVT::i1)
2109
0
    return 0;
2110
0
  return fastEmitInst_rr(PPC::CROR, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2111
0
}
2112
2113
0
unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2114
0
  if (RetVT.SimpleTy != MVT::i32)
2115
0
    return 0;
2116
0
  return fastEmitInst_rr(PPC::OR, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2117
0
}
2118
2119
0
unsigned fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2120
0
  if (RetVT.SimpleTy != MVT::i64)
2121
0
    return 0;
2122
0
  return fastEmitInst_rr(PPC::OR8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2123
0
}
2124
2125
2
unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2126
2
  if (RetVT.SimpleTy != MVT::v4i32)
2127
0
    return 0;
2128
2
  if ((PPCSubTarget->hasVSX())) {
2129
2
    return fastEmitInst_rr(PPC::XXLOR, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2130
2
  }
2131
0
  if ((PPCSubTarget->hasAltivec())) {
2132
0
    return fastEmitInst_rr(PPC::VOR, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2133
0
  }
2134
0
  return 0;
2135
0
}
2136
2137
6
unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2138
6
  switch (VT.SimpleTy) {
2139
6
  
case MVT::i1: return fastEmit_ISD_OR_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2140
6
  
case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2141
6
  
case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2142
6
  
case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)2
;
2143
6
  
default: return 04
;
2144
6
  }
2145
6
}
2146
2147
// FastEmit functions for ISD::SDIV.
2148
2149
0
unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2150
0
  if (RetVT.SimpleTy != MVT::i32)
2151
0
    return 0;
2152
0
  return fastEmitInst_rr(PPC::DIVW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2153
0
}
2154
2155
0
unsigned fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2156
0
  if (RetVT.SimpleTy != MVT::i64)
2157
0
    return 0;
2158
0
  return fastEmitInst_rr(PPC::DIVD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2159
0
}
2160
2161
unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2162
  switch (VT.SimpleTy) {
2163
  case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2164
  case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2165
  default: return 0;
2166
  }
2167
}
2168
2169
// FastEmit functions for ISD::SHL.
2170
2171
2
unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2172
2
  if (RetVT.SimpleTy != MVT::i32)
2173
0
    return 0;
2174
2
  return fastEmitInst_rr(PPC::SLW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2175
2
}
2176
2177
0
unsigned fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2178
0
  if (RetVT.SimpleTy != MVT::v16i8)
2179
0
    return 0;
2180
0
  if ((PPCSubTarget->hasAltivec())) {
2181
0
    return fastEmitInst_rr(PPC::VSLB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2182
0
  }
2183
0
  return 0;
2184
0
}
2185
2186
0
unsigned fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2187
0
  if (RetVT.SimpleTy != MVT::v8i16)
2188
0
    return 0;
2189
0
  if ((PPCSubTarget->hasAltivec())) {
2190
0
    return fastEmitInst_rr(PPC::VSLH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2191
0
  }
2192
0
  return 0;
2193
0
}
2194
2195
0
unsigned fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2196
0
  if (RetVT.SimpleTy != MVT::v4i32)
2197
0
    return 0;
2198
0
  if ((PPCSubTarget->hasAltivec())) {
2199
0
    return fastEmitInst_rr(PPC::VSLW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2200
0
  }
2201
0
  return 0;
2202
0
}
2203
2204
2
unsigned fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2205
2
  if (RetVT.SimpleTy != MVT::v2i64)
2206
0
    return 0;
2207
2
  if ((PPCSubTarget->hasP8Altivec())) {
2208
0
    return fastEmitInst_rr(PPC::VSLD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2209
0
  }
2210
2
  return 0;
2211
2
}
2212
2213
5
unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2214
5
  switch (VT.SimpleTy) {
2215
5
  
case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)2
;
2216
5
  
case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2217
5
  
case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2218
5
  
case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2219
5
  
case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)2
;
2220
5
  
default: return 01
;
2221
5
  }
2222
5
}
2223
2224
// FastEmit functions for ISD::SRA.
2225
2226
1
unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2227
1
  if (RetVT.SimpleTy != MVT::i32)
2228
0
    return 0;
2229
1
  return fastEmitInst_rr(PPC::SRAW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2230
1
}
2231
2232
0
unsigned fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2233
0
  if (RetVT.SimpleTy != MVT::v16i8)
2234
0
    return 0;
2235
0
  if ((PPCSubTarget->hasAltivec())) {
2236
0
    return fastEmitInst_rr(PPC::VSRAB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2237
0
  }
2238
0
  return 0;
2239
0
}
2240
2241
0
unsigned fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2242
0
  if (RetVT.SimpleTy != MVT::v8i16)
2243
0
    return 0;
2244
0
  if ((PPCSubTarget->hasAltivec())) {
2245
0
    return fastEmitInst_rr(PPC::VSRAH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2246
0
  }
2247
0
  return 0;
2248
0
}
2249
2250
0
unsigned fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2251
0
  if (RetVT.SimpleTy != MVT::v4i32)
2252
0
    return 0;
2253
0
  if ((PPCSubTarget->hasAltivec())) {
2254
0
    return fastEmitInst_rr(PPC::VSRAW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2255
0
  }
2256
0
  return 0;
2257
0
}
2258
2259
2
unsigned fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2260
2
  if (RetVT.SimpleTy != MVT::v2i64)
2261
0
    return 0;
2262
2
  if ((PPCSubTarget->hasP8Altivec())) {
2263
0
    return fastEmitInst_rr(PPC::VSRAD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2264
0
  }
2265
2
  return 0;
2266
2
}
2267
2268
3
unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2269
3
  switch (VT.SimpleTy) {
2270
3
  
case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)1
;
2271
3
  
case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2272
3
  
case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2273
3
  
case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2274
3
  
case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)2
;
2275
3
  
default: return 00
;
2276
3
  }
2277
3
}
2278
2279
// FastEmit functions for ISD::SREM.
2280
2281
0
unsigned fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2282
0
  if (RetVT.SimpleTy != MVT::i32)
2283
0
    return 0;
2284
0
  if ((PPCSubTarget->isISA3_0())) {
2285
0
    return fastEmitInst_rr(PPC::MODSW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2286
0
  }
2287
0
  return 0;
2288
0
}
2289
2290
0
unsigned fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2291
0
  if (RetVT.SimpleTy != MVT::i64)
2292
0
    return 0;
2293
0
  if ((PPCSubTarget->isISA3_0())) {
2294
0
    return fastEmitInst_rr(PPC::MODSD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2295
0
  }
2296
0
  return 0;
2297
0
}
2298
2299
unsigned fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2300
  switch (VT.SimpleTy) {
2301
  case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2302
  case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2303
  default: return 0;
2304
  }
2305
}
2306
2307
// FastEmit functions for ISD::SRL.
2308
2309
2
unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2310
2
  if (RetVT.SimpleTy != MVT::i32)
2311
0
    return 0;
2312
2
  return fastEmitInst_rr(PPC::SRW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2313
2
}
2314
2315
0
unsigned fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2316
0
  if (RetVT.SimpleTy != MVT::v16i8)
2317
0
    return 0;
2318
0
  if ((PPCSubTarget->hasAltivec())) {
2319
0
    return fastEmitInst_rr(PPC::VSRB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2320
0
  }
2321
0
  return 0;
2322
0
}
2323
2324
0
unsigned fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2325
0
  if (RetVT.SimpleTy != MVT::v8i16)
2326
0
    return 0;
2327
0
  if ((PPCSubTarget->hasAltivec())) {
2328
0
    return fastEmitInst_rr(PPC::VSRH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2329
0
  }
2330
0
  return 0;
2331
0
}
2332
2333
0
unsigned fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2334
0
  if (RetVT.SimpleTy != MVT::v4i32)
2335
0
    return 0;
2336
0
  if ((PPCSubTarget->hasAltivec())) {
2337
0
    return fastEmitInst_rr(PPC::VSRW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2338
0
  }
2339
0
  return 0;
2340
0
}
2341
2342
2
unsigned fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2343
2
  if (RetVT.SimpleTy != MVT::v2i64)
2344
0
    return 0;
2345
2
  if ((PPCSubTarget->hasP8Altivec())) {
2346
0
    return fastEmitInst_rr(PPC::VSRD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2347
0
  }
2348
2
  return 0;
2349
2
}
2350
2351
4
unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2352
4
  switch (VT.SimpleTy) {
2353
4
  
case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)2
;
2354
4
  
case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2355
4
  
case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2356
4
  
case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2357
4
  
case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)2
;
2358
4
  
default: return 00
;
2359
4
  }
2360
4
}
2361
2362
// FastEmit functions for ISD::SUB.
2363
2364
0
unsigned fastEmit_ISD_SUB_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2365
0
  if (RetVT.SimpleTy != MVT::i1)
2366
0
    return 0;
2367
0
  return fastEmitInst_rr(PPC::CRXOR, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2368
0
}
2369
2370
0
unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2371
0
  if (RetVT.SimpleTy != MVT::v16i8)
2372
0
    return 0;
2373
0
  if ((PPCSubTarget->hasAltivec())) {
2374
0
    return fastEmitInst_rr(PPC::VSUBUBM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2375
0
  }
2376
0
  return 0;
2377
0
}
2378
2379
0
unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2380
0
  if (RetVT.SimpleTy != MVT::v8i16)
2381
0
    return 0;
2382
0
  if ((PPCSubTarget->hasAltivec())) {
2383
0
    return fastEmitInst_rr(PPC::VSUBUHM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2384
0
  }
2385
0
  return 0;
2386
0
}
2387
2388
0
unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2389
0
  if (RetVT.SimpleTy != MVT::v4i32)
2390
0
    return 0;
2391
0
  if ((PPCSubTarget->hasAltivec())) {
2392
0
    return fastEmitInst_rr(PPC::VSUBUWM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2393
0
  }
2394
0
  return 0;
2395
0
}
2396
2397
0
unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2398
0
  if (RetVT.SimpleTy != MVT::v2i64)
2399
0
    return 0;
2400
0
  if ((PPCSubTarget->hasP8Altivec())) {
2401
0
    return fastEmitInst_rr(PPC::VSUBUDM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2402
0
  }
2403
0
  return 0;
2404
0
}
2405
2406
0
unsigned fastEmit_ISD_SUB_MVT_v1i128_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2407
0
  if (RetVT.SimpleTy != MVT::v1i128)
2408
0
    return 0;
2409
0
  if ((PPCSubTarget->hasP8Altivec())) {
2410
0
    return fastEmitInst_rr(PPC::VSUBUQM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2411
0
  }
2412
0
  return 0;
2413
0
}
2414
2415
1
unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2416
1
  switch (VT.SimpleTy) {
2417
1
  
case MVT::i1: return fastEmit_ISD_SUB_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2418
1
  
case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2419
1
  
case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2420
1
  
case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2421
1
  
case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2422
1
  
case MVT::v1i128: return fastEmit_ISD_SUB_MVT_v1i128_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2423
1
  default: return 0;
2424
1
  }
2425
1
}
2426
2427
// FastEmit functions for ISD::UDIV.
2428
2429
0
unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2430
0
  if (RetVT.SimpleTy != MVT::i32)
2431
0
    return 0;
2432
0
  return fastEmitInst_rr(PPC::DIVWU, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2433
0
}
2434
2435
0
unsigned fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2436
0
  if (RetVT.SimpleTy != MVT::i64)
2437
0
    return 0;
2438
0
  return fastEmitInst_rr(PPC::DIVDU, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2439
0
}
2440
2441
unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2442
  switch (VT.SimpleTy) {
2443
  case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2444
  case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2445
  default: return 0;
2446
  }
2447
}
2448
2449
// FastEmit functions for ISD::UREM.
2450
2451
0
unsigned fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2452
0
  if (RetVT.SimpleTy != MVT::i32)
2453
0
    return 0;
2454
0
  if ((PPCSubTarget->isISA3_0())) {
2455
0
    return fastEmitInst_rr(PPC::MODUW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2456
0
  }
2457
0
  return 0;
2458
0
}
2459
2460
0
unsigned fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2461
0
  if (RetVT.SimpleTy != MVT::i64)
2462
0
    return 0;
2463
0
  if ((PPCSubTarget->isISA3_0())) {
2464
0
    return fastEmitInst_rr(PPC::MODUD, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2465
0
  }
2466
0
  return 0;
2467
0
}
2468
2469
unsigned fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2470
  switch (VT.SimpleTy) {
2471
  case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2472
  case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2473
  default: return 0;
2474
  }
2475
}
2476
2477
// FastEmit functions for ISD::XOR.
2478
2479
0
unsigned fastEmit_ISD_XOR_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2480
0
  if (RetVT.SimpleTy != MVT::i1)
2481
0
    return 0;
2482
0
  return fastEmitInst_rr(PPC::CRXOR, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2483
0
}
2484
2485
0
unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2486
0
  if (RetVT.SimpleTy != MVT::i32)
2487
0
    return 0;
2488
0
  return fastEmitInst_rr(PPC::XOR, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2489
0
}
2490
2491
0
unsigned fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2492
0
  if (RetVT.SimpleTy != MVT::i64)
2493
0
    return 0;
2494
0
  return fastEmitInst_rr(PPC::XOR8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2495
0
}
2496
2497
2
unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2498
2
  if (RetVT.SimpleTy != MVT::v4i32)
2499
0
    return 0;
2500
2
  if ((PPCSubTarget->hasVSX())) {
2501
2
    return fastEmitInst_rr(PPC::XXLXOR, &PPC::VSRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2502
2
  }
2503
0
  if ((PPCSubTarget->hasAltivec())) {
2504
0
    return fastEmitInst_rr(PPC::VXOR, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2505
0
  }
2506
0
  return 0;
2507
0
}
2508
2509
6
unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2510
6
  switch (VT.SimpleTy) {
2511
6
  
case MVT::i1: return fastEmit_ISD_XOR_MVT_i1_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2512
6
  
case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2513
6
  
case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2514
6
  
case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill)2
;
2515
6
  
default: return 04
;
2516
6
  }
2517
6
}
2518
2519
// FastEmit functions for PPCISD::CMPB.
2520
2521
0
unsigned fastEmit_PPCISD_CMPB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2522
0
  if (RetVT.SimpleTy != MVT::i32)
2523
0
    return 0;
2524
0
  return fastEmitInst_rr(PPC::CMPB, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2525
0
}
2526
2527
0
unsigned fastEmit_PPCISD_CMPB_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2528
0
  if (RetVT.SimpleTy != MVT::i64)
2529
0
    return 0;
2530
0
  return fastEmitInst_rr(PPC::CMPB8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2531
0
}
2532
2533
unsigned fastEmit_PPCISD_CMPB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2534
  switch (VT.SimpleTy) {
2535
  case MVT::i32: return fastEmit_PPCISD_CMPB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2536
  case MVT::i64: return fastEmit_PPCISD_CMPB_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2537
  default: return 0;
2538
  }
2539
}
2540
2541
// FastEmit functions for PPCISD::FADDRTZ.
2542
2543
0
unsigned fastEmit_PPCISD_FADDRTZ_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2544
0
  if (RetVT.SimpleTy != MVT::f64)
2545
0
    return 0;
2546
0
  return fastEmitInst_rr(PPC::FADDrtz, &PPC::F8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2547
0
}
2548
2549
unsigned fastEmit_PPCISD_FADDRTZ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2550
  switch (VT.SimpleTy) {
2551
  case MVT::f64: return fastEmit_PPCISD_FADDRTZ_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2552
  default: return 0;
2553
  }
2554
}
2555
2556
// FastEmit functions for PPCISD::SHL.
2557
2558
0
unsigned fastEmit_PPCISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2559
0
  if (RetVT.SimpleTy != MVT::i32)
2560
0
    return 0;
2561
0
  return fastEmitInst_rr(PPC::SLW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2562
0
}
2563
2564
0
unsigned fastEmit_PPCISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2565
0
  if (RetVT.SimpleTy != MVT::v16i8)
2566
0
    return 0;
2567
0
  if ((PPCSubTarget->hasAltivec())) {
2568
0
    return fastEmitInst_rr(PPC::VSLB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2569
0
  }
2570
0
  return 0;
2571
0
}
2572
2573
0
unsigned fastEmit_PPCISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2574
0
  if (RetVT.SimpleTy != MVT::v8i16)
2575
0
    return 0;
2576
0
  if ((PPCSubTarget->hasAltivec())) {
2577
0
    return fastEmitInst_rr(PPC::VSLH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2578
0
  }
2579
0
  return 0;
2580
0
}
2581
2582
0
unsigned fastEmit_PPCISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2583
0
  if (RetVT.SimpleTy != MVT::v4i32)
2584
0
    return 0;
2585
0
  if ((PPCSubTarget->hasAltivec())) {
2586
0
    return fastEmitInst_rr(PPC::VSLW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2587
0
  }
2588
0
  return 0;
2589
0
}
2590
2591
0
unsigned fastEmit_PPCISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2592
0
  if (RetVT.SimpleTy != MVT::v2i64)
2593
0
    return 0;
2594
0
  if ((PPCSubTarget->hasP8Altivec())) {
2595
0
    return fastEmitInst_rr(PPC::VSLD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2596
0
  }
2597
0
  return 0;
2598
0
}
2599
2600
unsigned fastEmit_PPCISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2601
  switch (VT.SimpleTy) {
2602
  case MVT::i32: return fastEmit_PPCISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2603
  case MVT::v16i8: return fastEmit_PPCISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2604
  case MVT::v8i16: return fastEmit_PPCISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2605
  case MVT::v4i32: return fastEmit_PPCISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2606
  case MVT::v2i64: return fastEmit_PPCISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2607
  default: return 0;
2608
  }
2609
}
2610
2611
// FastEmit functions for PPCISD::SRA.
2612
2613
0
unsigned fastEmit_PPCISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2614
0
  if (RetVT.SimpleTy != MVT::i32)
2615
0
    return 0;
2616
0
  return fastEmitInst_rr(PPC::SRAW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2617
0
}
2618
2619
0
unsigned fastEmit_PPCISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2620
0
  if (RetVT.SimpleTy != MVT::v16i8)
2621
0
    return 0;
2622
0
  if ((PPCSubTarget->hasAltivec())) {
2623
0
    return fastEmitInst_rr(PPC::VSRAB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2624
0
  }
2625
0
  return 0;
2626
0
}
2627
2628
0
unsigned fastEmit_PPCISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2629
0
  if (RetVT.SimpleTy != MVT::v8i16)
2630
0
    return 0;
2631
0
  if ((PPCSubTarget->hasAltivec())) {
2632
0
    return fastEmitInst_rr(PPC::VSRAH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2633
0
  }
2634
0
  return 0;
2635
0
}
2636
2637
0
unsigned fastEmit_PPCISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2638
0
  if (RetVT.SimpleTy != MVT::v4i32)
2639
0
    return 0;
2640
0
  if ((PPCSubTarget->hasAltivec())) {
2641
0
    return fastEmitInst_rr(PPC::VSRAW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2642
0
  }
2643
0
  return 0;
2644
0
}
2645
2646
0
unsigned fastEmit_PPCISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2647
0
  if (RetVT.SimpleTy != MVT::v2i64)
2648
0
    return 0;
2649
0
  if ((PPCSubTarget->hasP8Altivec())) {
2650
0
    return fastEmitInst_rr(PPC::VSRAD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2651
0
  }
2652
0
  return 0;
2653
0
}
2654
2655
unsigned fastEmit_PPCISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2656
  switch (VT.SimpleTy) {
2657
  case MVT::i32: return fastEmit_PPCISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2658
  case MVT::v16i8: return fastEmit_PPCISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2659
  case MVT::v8i16: return fastEmit_PPCISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2660
  case MVT::v4i32: return fastEmit_PPCISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2661
  case MVT::v2i64: return fastEmit_PPCISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2662
  default: return 0;
2663
  }
2664
}
2665
2666
// FastEmit functions for PPCISD::SRL.
2667
2668
0
unsigned fastEmit_PPCISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2669
0
  if (RetVT.SimpleTy != MVT::i32)
2670
0
    return 0;
2671
0
  return fastEmitInst_rr(PPC::SRW, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2672
0
}
2673
2674
0
unsigned fastEmit_PPCISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2675
0
  if (RetVT.SimpleTy != MVT::v16i8)
2676
0
    return 0;
2677
0
  if ((PPCSubTarget->hasAltivec())) {
2678
0
    return fastEmitInst_rr(PPC::VSRB, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2679
0
  }
2680
0
  return 0;
2681
0
}
2682
2683
0
unsigned fastEmit_PPCISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2684
0
  if (RetVT.SimpleTy != MVT::v8i16)
2685
0
    return 0;
2686
0
  if ((PPCSubTarget->hasAltivec())) {
2687
0
    return fastEmitInst_rr(PPC::VSRH, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2688
0
  }
2689
0
  return 0;
2690
0
}
2691
2692
0
unsigned fastEmit_PPCISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2693
0
  if (RetVT.SimpleTy != MVT::v4i32)
2694
0
    return 0;
2695
0
  if ((PPCSubTarget->hasAltivec())) {
2696
0
    return fastEmitInst_rr(PPC::VSRW, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2697
0
  }
2698
0
  return 0;
2699
0
}
2700
2701
0
unsigned fastEmit_PPCISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2702
0
  if (RetVT.SimpleTy != MVT::v2i64)
2703
0
    return 0;
2704
0
  if ((PPCSubTarget->hasP8Altivec())) {
2705
0
    return fastEmitInst_rr(PPC::VSRD, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2706
0
  }
2707
0
  return 0;
2708
0
}
2709
2710
unsigned fastEmit_PPCISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2711
  switch (VT.SimpleTy) {
2712
  case MVT::i32: return fastEmit_PPCISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2713
  case MVT::v16i8: return fastEmit_PPCISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2714
  case MVT::v8i16: return fastEmit_PPCISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2715
  case MVT::v4i32: return fastEmit_PPCISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2716
  case MVT::v2i64: return fastEmit_PPCISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2717
  default: return 0;
2718
  }
2719
}
2720
2721
// Top-level FastEmit function.
2722
2723
60
unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) override {
2724
60
  switch (Opcode) {
2725
60
  
case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)2
;
2726
60
  
case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2727
60
  
case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2728
60
  
case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)15
;
2729
60
  
case ISD::BUILD_VECTOR: return fastEmit_ISD_BUILD_VECTOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2730
60
  
case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)14
;
2731
60
  
case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)2
;
2732
60
  
case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)2
;
2733
60
  
case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2734
60
  
case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2735
60
  
case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2736
60
  
case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2737
60
  
case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)6
;
2738
60
  
case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2739
60
  
case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)5
;
2740
60
  
case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)3
;
2741
60
  
case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2742
60
  
case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)4
;
2743
60
  
case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)1
;
2744
60
  
case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2745
60
  
case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2746
60
  
case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)6
;
2747
60
  
case PPCISD::CMPB: return fastEmit_PPCISD_CMPB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2748
60
  
case PPCISD::FADDRTZ: return fastEmit_PPCISD_FADDRTZ_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2749
60
  
case PPCISD::SHL: return fastEmit_PPCISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2750
60
  
case PPCISD::SRA: return fastEmit_PPCISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2751
60
  
case PPCISD::SRL: return fastEmit_PPCISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill)0
;
2752
60
  
default: return 00
;
2753
60
  }
2754
60
}
2755
2756
// FastEmit functions for ISD::SRA.
2757
2758
1
unsigned fastEmit_ISD_SRA_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2759
1
  if (RetVT.SimpleTy != MVT::i32)
2760
0
    return 0;
2761
1
  return fastEmitInst_ri(PPC::SRAWI, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
2762
1
}
2763
2764
0
unsigned fastEmit_ISD_SRA_MVT_i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2765
0
  if (RetVT.SimpleTy != MVT::i64)
2766
0
    return 0;
2767
0
  return fastEmitInst_ri(PPC::SRADI, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
2768
0
}
2769
2770
1
unsigned fastEmit_ISD_SRA_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2771
1
  switch (VT.SimpleTy) {
2772
1
  case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
2773
1
  
case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri(RetVT, Op0, Op0IsKill, imm1)0
;
2774
1
  
default: return 00
;
2775
1
  }
2776
1
}
2777
2778
// FastEmit functions for PPCISD::QVESPLATI.
2779
2780
0
unsigned fastEmit_PPCISD_QVESPLATI_MVT_v4i1_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2781
0
  if (RetVT.SimpleTy != MVT::v4i1)
2782
0
    return 0;
2783
0
  if ((PPCSubTarget->hasQPX())) {
2784
0
    return fastEmitInst_ri(PPC::QVESPLATIb, &PPC::QBRCRegClass, Op0, Op0IsKill, imm1);
2785
0
  }
2786
0
  return 0;
2787
0
}
2788
2789
0
unsigned fastEmit_PPCISD_QVESPLATI_MVT_v4f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2790
0
  if (RetVT.SimpleTy != MVT::v4f32)
2791
0
    return 0;
2792
0
  if ((PPCSubTarget->hasQPX())) {
2793
0
    return fastEmitInst_ri(PPC::QVESPLATIs, &PPC::QSRCRegClass, Op0, Op0IsKill, imm1);
2794
0
  }
2795
0
  return 0;
2796
0
}
2797
2798
0
unsigned fastEmit_PPCISD_QVESPLATI_MVT_v4f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2799
0
  if (RetVT.SimpleTy != MVT::v4f64)
2800
0
    return 0;
2801
0
  if ((PPCSubTarget->hasQPX())) {
2802
0
    return fastEmitInst_ri(PPC::QVESPLATI, &PPC::QFRCRegClass, Op0, Op0IsKill, imm1);
2803
0
  }
2804
0
  return 0;
2805
0
}
2806
2807
unsigned fastEmit_PPCISD_QVESPLATI_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2808
  switch (VT.SimpleTy) {
2809
  case MVT::v4i1: return fastEmit_PPCISD_QVESPLATI_MVT_v4i1_ri(RetVT, Op0, Op0IsKill, imm1);
2810
  case MVT::v4f32: return fastEmit_PPCISD_QVESPLATI_MVT_v4f32_ri(RetVT, Op0, Op0IsKill, imm1);
2811
  case MVT::v4f64: return fastEmit_PPCISD_QVESPLATI_MVT_v4f64_ri(RetVT, Op0, Op0IsKill, imm1);
2812
  default: return 0;
2813
  }
2814
}
2815
2816
// FastEmit functions for PPCISD::TC_RETURN.
2817
2818
0
unsigned fastEmit_PPCISD_TC_RETURN_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2819
0
  if (RetVT.SimpleTy != MVT::isVoid)
2820
0
    return 0;
2821
0
  return fastEmitInst_ri(PPC::TCRETURNri, &PPC::CTRRCRegClass, Op0, Op0IsKill, imm1);
2822
0
}
2823
2824
0
unsigned fastEmit_PPCISD_TC_RETURN_MVT_i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2825
0
  if (RetVT.SimpleTy != MVT::isVoid)
2826
0
    return 0;
2827
0
  return fastEmitInst_ri(PPC::TCRETURNri8, &PPC::CTRRC8RegClass, Op0, Op0IsKill, imm1);
2828
0
}
2829
2830
unsigned fastEmit_PPCISD_TC_RETURN_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2831
  switch (VT.SimpleTy) {
2832
  case MVT::i32: return fastEmit_PPCISD_TC_RETURN_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
2833
  case MVT::i64: return fastEmit_PPCISD_TC_RETURN_MVT_i64_ri(RetVT, Op0, Op0IsKill, imm1);
2834
  default: return 0;
2835
  }
2836
}
2837
2838
// Top-level FastEmit function.
2839
2840
42
unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) override {
2841
42
  if (VT == MVT::i32 && 
Predicate_imm32SExt16(imm1)23
)
2842
23
    if (unsigned Reg = fastEmit_ri_Predicate_imm32SExt16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
2843
20
      return Reg;
2844
22
2845
22
  if (VT == MVT::i64 && 
Predicate_imm64SExt16(imm1)19
)
2846
19
    if (unsigned Reg = fastEmit_ri_Predicate_imm64SExt16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
2847
17
      return Reg;
2848
5
2849
5
  switch (Opcode) {
2850
5
  
case ISD::SRA: return fastEmit_ISD_SRA_ri(VT, RetVT, Op0, Op0IsKill, imm1)1
;
2851
5
  
case PPCISD::QVESPLATI: return fastEmit_PPCISD_QVESPLATI_ri(VT, RetVT, Op0, Op0IsKill, imm1)0
;
2852
5
  
case PPCISD::TC_RETURN: return fastEmit_PPCISD_TC_RETURN_ri(VT, RetVT, Op0, Op0IsKill, imm1)0
;
2853
5
  
default: return 04
;
2854
5
  }
2855
5
}
2856
2857
// FastEmit functions for ISD::ADD.
2858
2859
20
unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2860
20
  if (RetVT.SimpleTy != MVT::i32)
2861
0
    return 0;
2862
20
  return fastEmitInst_ri(PPC::ADDI, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
2863
20
}
2864
2865
20
unsigned fastEmit_ISD_ADD_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2866
20
  switch (VT.SimpleTy) {
2867
20
  case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, Op0IsKill, imm1);
2868
20
  
default: return 00
;
2869
20
  }
2870
20
}
2871
2872
// FastEmit functions for ISD::ADDC.
2873
2874
0
unsigned fastEmit_ISD_ADDC_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2875
0
  if (RetVT.SimpleTy != MVT::i32)
2876
0
    return 0;
2877
0
  return fastEmitInst_ri(PPC::ADDIC, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
2878
0
}
2879
2880
unsigned fastEmit_ISD_ADDC_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2881
  switch (VT.SimpleTy) {
2882
  case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, Op0IsKill, imm1);
2883
  default: return 0;
2884
  }
2885
}
2886
2887
// FastEmit functions for ISD::MUL.
2888
2889
0
unsigned fastEmit_ISD_MUL_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2890
0
  if (RetVT.SimpleTy != MVT::i32)
2891
0
    return 0;
2892
0
  return fastEmitInst_ri(PPC::MULLI, &PPC::GPRCRegClass, Op0, Op0IsKill, imm1);
2893
0
}
2894
2895
unsigned fastEmit_ISD_MUL_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2896
  switch (VT.SimpleTy) {
2897
  case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, Op0IsKill, imm1);
2898
  default: return 0;
2899
  }
2900
}
2901
2902
// FastEmit functions for PPCISD::XXSPLT.
2903
2904
0
unsigned fastEmit_PPCISD_XXSPLT_MVT_v4i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2905
0
  if (RetVT.SimpleTy != MVT::v4i32)
2906
0
    return 0;
2907
0
  if ((PPCSubTarget->hasVSX())) {
2908
0
    return fastEmitInst_ri(PPC::XXSPLTW, &PPC::VSRCRegClass, Op0, Op0IsKill, imm1);
2909
0
  }
2910
0
  return 0;
2911
0
}
2912
2913
unsigned fastEmit_PPCISD_XXSPLT_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2914
  switch (VT.SimpleTy) {
2915
  case MVT::v4i32: return fastEmit_PPCISD_XXSPLT_MVT_v4i32_ri_Predicate_imm32SExt16(RetVT, Op0, Op0IsKill, imm1);
2916
  default: return 0;
2917
  }
2918
}
2919
2920
// Top-level FastEmit function.
2921
2922
23
unsigned fastEmit_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2923
23
  switch (Opcode) {
2924
23
  
case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm32SExt16(VT, RetVT, Op0, Op0IsKill, imm1)20
;
2925
23
  
case ISD::ADDC: return fastEmit_ISD_ADDC_ri_Predicate_imm32SExt16(VT, RetVT, Op0, Op0IsKill, imm1)0
;
2926
23
  
case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_imm32SExt16(VT, RetVT, Op0, Op0IsKill, imm1)0
;
2927
23
  
case PPCISD::XXSPLT: return fastEmit_PPCISD_XXSPLT_ri_Predicate_imm32SExt16(VT, RetVT, Op0, Op0IsKill, imm1)0
;
2928
23
  
default: return 03
;
2929
23
  }
2930
23
}
2931
2932
// FastEmit functions for ISD::ADD.
2933
2934
17
unsigned fastEmit_ISD_ADD_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2935
17
  if (RetVT.SimpleTy != MVT::i64)
2936
0
    return 0;
2937
17
  return fastEmitInst_ri(PPC::ADDI8, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
2938
17
}
2939
2940
17
unsigned fastEmit_ISD_ADD_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2941
17
  switch (VT.SimpleTy) {
2942
17
  case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, Op0IsKill, imm1);
2943
17
  
default: return 00
;
2944
17
  }
2945
17
}
2946
2947
// FastEmit functions for ISD::ADDC.
2948
2949
0
unsigned fastEmit_ISD_ADDC_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2950
0
  if (RetVT.SimpleTy != MVT::i64)
2951
0
    return 0;
2952
0
  return fastEmitInst_ri(PPC::ADDIC8, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
2953
0
}
2954
2955
unsigned fastEmit_ISD_ADDC_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2956
  switch (VT.SimpleTy) {
2957
  case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, Op0IsKill, imm1);
2958
  default: return 0;
2959
  }
2960
}
2961
2962
// FastEmit functions for ISD::MUL.
2963
2964
0
unsigned fastEmit_ISD_MUL_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2965
0
  if (RetVT.SimpleTy != MVT::i64)
2966
0
    return 0;
2967
0
  return fastEmitInst_ri(PPC::MULLI8, &PPC::G8RCRegClass, Op0, Op0IsKill, imm1);
2968
0
}
2969
2970
unsigned fastEmit_ISD_MUL_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2971
  switch (VT.SimpleTy) {
2972
  case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, Op0IsKill, imm1);
2973
  default: return 0;
2974
  }
2975
}
2976
2977
// Top-level FastEmit function.
2978
2979
19
unsigned fastEmit_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
2980
19
  switch (Opcode) {
2981
19
  
case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm64SExt16(VT, RetVT, Op0, Op0IsKill, imm1)17
;
2982
19
  
case ISD::ADDC: return fastEmit_ISD_ADDC_ri_Predicate_imm64SExt16(VT, RetVT, Op0, Op0IsKill, imm1)0
;
2983
19
  
case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_imm64SExt16(VT, RetVT, Op0, Op0IsKill, imm1)0
;
2984
19
  
default: return 02
;
2985
19
  }
2986
19
}
2987