Coverage Report

Created: 2018-07-12 09:57

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Sparc/SparcGenCallingConv.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Calling Convention Implementation Fragment                                 *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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static bool CC_Sparc32(unsigned ValNo, MVT ValVT,
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                       MVT LocVT, CCValAssign::LocInfo LocInfo,
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                       ISD::ArgFlagsTy ArgFlags, CCState &State);
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static bool CC_Sparc64(unsigned ValNo, MVT ValVT,
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                       MVT LocVT, CCValAssign::LocInfo LocInfo,
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                       ISD::ArgFlagsTy ArgFlags, CCState &State);
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static bool RetCC_Sparc32(unsigned ValNo, MVT ValVT,
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                          MVT LocVT, CCValAssign::LocInfo LocInfo,
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                          ISD::ArgFlagsTy ArgFlags, CCState &State);
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static bool RetCC_Sparc64(unsigned ValNo, MVT ValVT,
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                          MVT LocVT, CCValAssign::LocInfo LocInfo,
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                          ISD::ArgFlagsTy ArgFlags, CCState &State);
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static bool CC_Sparc32(unsigned ValNo, MVT ValVT,
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                       MVT LocVT, CCValAssign::LocInfo LocInfo,
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1.35k
                       ISD::ArgFlagsTy ArgFlags, CCState &State) {
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1.35k
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  if (ArgFlags.isSRet()) {
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    if (CC_Sparc_Assign_SRet(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
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        return false;
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1.29k
  }
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1.29k
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  if (LocVT == MVT::i32 ||
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1.29k
      
LocVT == MVT::f32121
) {
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1.23k
    static const MCPhysReg RegList1[] = {
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1.23k
      SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
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1.23k
    };
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    if (unsigned Reg = State.AllocateReg(RegList1)) {
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1.12k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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1.12k
      return false;
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    }
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  }
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  if (LocVT == MVT::f64) {
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    if (CC_Sparc_Assign_Split_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
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        return false;
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  }
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  if (LocVT == MVT::v2i32) {
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0
    if (CC_Sparc_Assign_Split_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
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        return false;
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  }
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  unsigned Offset2 = State.AllocateStack(4, 4);
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  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
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  return false;
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return true0
; // CC didn't match.
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}
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static bool CC_Sparc64(unsigned ValNo, MVT ValVT,
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                       MVT LocVT, CCValAssign::LocInfo LocInfo,
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                       ISD::ArgFlagsTy ArgFlags, CCState &State) {
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  if (ArgFlags.isInReg()) {
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    if (LocVT == MVT::i32 ||
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LocVT == MVT::f328
) {
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      if (CC_Sparc64_Half(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
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            return false;
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    }
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  }
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  if (LocVT == MVT::i32) {
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    LocVT = MVT::i64;
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    if (ArgFlags.isSExt())
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        LocInfo = CCValAssign::SExt;
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    else if (ArgFlags.isZExt())
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        LocInfo = CCValAssign::ZExt;
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    else
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        LocInfo = CCValAssign::AExt;
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  }
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  if (CC_Sparc64_Full(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
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    return false;
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  return true;  // CC didn't match.
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0
}
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static bool RetCC_Sparc32(unsigned ValNo, MVT ValVT,
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                          MVT LocVT, CCValAssign::LocInfo LocInfo,
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                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
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  if (LocVT == MVT::i32) {
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    static const MCPhysReg RegList1[] = {
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      SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
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    };
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    if (unsigned Reg = State.AllocateReg(RegList1)) {
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      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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      return false;
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    }
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  }
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  if (LocVT == MVT::f32) {
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    static const MCPhysReg RegList2[] = {
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      SP::F0, SP::F1, SP::F2, SP::F3
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    };
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    if (unsigned Reg = State.AllocateReg(RegList2)) {
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      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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      return false;
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    }
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  }
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  if (LocVT == MVT::f64) {
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    static const MCPhysReg RegList3[] = {
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      SP::D0, SP::D1
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    };
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    if (unsigned Reg = State.AllocateReg(RegList3)) {
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      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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      return false;
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    }
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  }
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  if (LocVT == MVT::v2i32) {
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    if (CC_Sparc_Assign_Ret_Split_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
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        return false;
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  }
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  return true;  // CC didn't match.
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}
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static bool RetCC_Sparc64(unsigned ValNo, MVT ValVT,
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                          MVT LocVT, CCValAssign::LocInfo LocInfo,
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                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
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  if (LocVT == MVT::f32) {
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    if (CC_Sparc64_Half(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
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        return false;
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  }
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  if (!CC_Sparc64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
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    return false;
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  return true;  // CC didn't match.
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}