Coverage Report

Created: 2018-07-12 09:57

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Sparc/SparcGenRegisterInfo.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Register Enum Values                                                *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
#ifdef GET_REGINFO_ENUM
11
#undef GET_REGINFO_ENUM
12
13
namespace llvm {
14
15
class MCRegisterClass;
16
extern const MCRegisterClass SparcMCRegisterClasses[];
17
18
namespace SP {
19
enum {
20
  NoRegister,
21
  CANRESTORE = 1,
22
  CANSAVE = 2,
23
  CLEANWIN = 3,
24
  CPQ = 4,
25
  CPSR = 5,
26
  CWP = 6,
27
  FQ = 7,
28
  FSR = 8,
29
  ICC = 9,
30
  OTHERWIN = 10,
31
  PIL = 11,
32
  PSR = 12,
33
  PSTATE = 13,
34
  TBA = 14,
35
  TBR = 15,
36
  TICK = 16,
37
  TL = 17,
38
  TNPC = 18,
39
  TPC = 19,
40
  TSTATE = 20,
41
  TT = 21,
42
  WIM = 22,
43
  WSTATE = 23,
44
  Y = 24,
45
  ASR1 = 25,
46
  ASR2 = 26,
47
  ASR3 = 27,
48
  ASR4 = 28,
49
  ASR5 = 29,
50
  ASR6 = 30,
51
  ASR7 = 31,
52
  ASR8 = 32,
53
  ASR9 = 33,
54
  ASR10 = 34,
55
  ASR11 = 35,
56
  ASR12 = 36,
57
  ASR13 = 37,
58
  ASR14 = 38,
59
  ASR15 = 39,
60
  ASR16 = 40,
61
  ASR17 = 41,
62
  ASR18 = 42,
63
  ASR19 = 43,
64
  ASR20 = 44,
65
  ASR21 = 45,
66
  ASR22 = 46,
67
  ASR23 = 47,
68
  ASR24 = 48,
69
  ASR25 = 49,
70
  ASR26 = 50,
71
  ASR27 = 51,
72
  ASR28 = 52,
73
  ASR29 = 53,
74
  ASR30 = 54,
75
  ASR31 = 55,
76
  C0 = 56,
77
  C1 = 57,
78
  C2 = 58,
79
  C3 = 59,
80
  C4 = 60,
81
  C5 = 61,
82
  C6 = 62,
83
  C7 = 63,
84
  C8 = 64,
85
  C9 = 65,
86
  C10 = 66,
87
  C11 = 67,
88
  C12 = 68,
89
  C13 = 69,
90
  C14 = 70,
91
  C15 = 71,
92
  C16 = 72,
93
  C17 = 73,
94
  C18 = 74,
95
  C19 = 75,
96
  C20 = 76,
97
  C21 = 77,
98
  C22 = 78,
99
  C23 = 79,
100
  C24 = 80,
101
  C25 = 81,
102
  C26 = 82,
103
  C27 = 83,
104
  C28 = 84,
105
  C29 = 85,
106
  C30 = 86,
107
  C31 = 87,
108
  D0 = 88,
109
  D1 = 89,
110
  D2 = 90,
111
  D3 = 91,
112
  D4 = 92,
113
  D5 = 93,
114
  D6 = 94,
115
  D7 = 95,
116
  D8 = 96,
117
  D9 = 97,
118
  D10 = 98,
119
  D11 = 99,
120
  D12 = 100,
121
  D13 = 101,
122
  D14 = 102,
123
  D15 = 103,
124
  D16 = 104,
125
  D17 = 105,
126
  D18 = 106,
127
  D19 = 107,
128
  D20 = 108,
129
  D21 = 109,
130
  D22 = 110,
131
  D23 = 111,
132
  D24 = 112,
133
  D25 = 113,
134
  D26 = 114,
135
  D27 = 115,
136
  D28 = 116,
137
  D29 = 117,
138
  D30 = 118,
139
  D31 = 119,
140
  F0 = 120,
141
  F1 = 121,
142
  F2 = 122,
143
  F3 = 123,
144
  F4 = 124,
145
  F5 = 125,
146
  F6 = 126,
147
  F7 = 127,
148
  F8 = 128,
149
  F9 = 129,
150
  F10 = 130,
151
  F11 = 131,
152
  F12 = 132,
153
  F13 = 133,
154
  F14 = 134,
155
  F15 = 135,
156
  F16 = 136,
157
  F17 = 137,
158
  F18 = 138,
159
  F19 = 139,
160
  F20 = 140,
161
  F21 = 141,
162
  F22 = 142,
163
  F23 = 143,
164
  F24 = 144,
165
  F25 = 145,
166
  F26 = 146,
167
  F27 = 147,
168
  F28 = 148,
169
  F29 = 149,
170
  F30 = 150,
171
  F31 = 151,
172
  FCC0 = 152,
173
  FCC1 = 153,
174
  FCC2 = 154,
175
  FCC3 = 155,
176
  G0 = 156,
177
  G1 = 157,
178
  G2 = 158,
179
  G3 = 159,
180
  G4 = 160,
181
  G5 = 161,
182
  G6 = 162,
183
  G7 = 163,
184
  I0 = 164,
185
  I1 = 165,
186
  I2 = 166,
187
  I3 = 167,
188
  I4 = 168,
189
  I5 = 169,
190
  I6 = 170,
191
  I7 = 171,
192
  L0 = 172,
193
  L1 = 173,
194
  L2 = 174,
195
  L3 = 175,
196
  L4 = 176,
197
  L5 = 177,
198
  L6 = 178,
199
  L7 = 179,
200
  O0 = 180,
201
  O1 = 181,
202
  O2 = 182,
203
  O3 = 183,
204
  O4 = 184,
205
  O5 = 185,
206
  O6 = 186,
207
  O7 = 187,
208
  Q0 = 188,
209
  Q1 = 189,
210
  Q2 = 190,
211
  Q3 = 191,
212
  Q4 = 192,
213
  Q5 = 193,
214
  Q6 = 194,
215
  Q7 = 195,
216
  Q8 = 196,
217
  Q9 = 197,
218
  Q10 = 198,
219
  Q11 = 199,
220
  Q12 = 200,
221
  Q13 = 201,
222
  Q14 = 202,
223
  Q15 = 203,
224
  C0_C1 = 204,
225
  C2_C3 = 205,
226
  C4_C5 = 206,
227
  C6_C7 = 207,
228
  C8_C9 = 208,
229
  C10_C11 = 209,
230
  C12_C13 = 210,
231
  C14_C15 = 211,
232
  C16_C17 = 212,
233
  C18_C19 = 213,
234
  C20_C21 = 214,
235
  C22_C23 = 215,
236
  C24_C25 = 216,
237
  C26_C27 = 217,
238
  C28_C29 = 218,
239
  C30_C31 = 219,
240
  G0_G1 = 220,
241
  G2_G3 = 221,
242
  G4_G5 = 222,
243
  G6_G7 = 223,
244
  I0_I1 = 224,
245
  I2_I3 = 225,
246
  I4_I5 = 226,
247
  I6_I7 = 227,
248
  L0_L1 = 228,
249
  L2_L3 = 229,
250
  L4_L5 = 230,
251
  L6_L7 = 231,
252
  O0_O1 = 232,
253
  O2_O3 = 233,
254
  O4_O5 = 234,
255
  O6_O7 = 235,
256
  NUM_TARGET_REGS   // 236
257
};
258
} // end namespace SP
259
260
// Register classes
261
262
namespace SP {
263
enum {
264
  FCCRegsRegClassID = 0,
265
  ASRRegsRegClassID = 1,
266
  CoprocRegsRegClassID = 2,
267
  FPRegsRegClassID = 3,
268
  IntRegsRegClassID = 4,
269
  DFPRegsRegClassID = 5,
270
  I64RegsRegClassID = 6,
271
  CoprocPairRegClassID = 7,
272
  IntPairRegClassID = 8,
273
  LowDFPRegsRegClassID = 9,
274
  PRRegsRegClassID = 10,
275
  QFPRegsRegClassID = 11,
276
  LowQFPRegsRegClassID = 12,
277
278
  };
279
} // end namespace SP
280
281
282
// Subregister indices
283
284
namespace SP {
285
enum {
286
  NoSubRegister,
287
  sub_even, // 1
288
  sub_even64, // 2
289
  sub_odd,  // 3
290
  sub_odd64,  // 4
291
  sub_odd64_then_sub_even,  // 5
292
  sub_odd64_then_sub_odd, // 6
293
  NUM_TARGET_SUBREGS
294
};
295
} // end namespace SP
296
297
} // end namespace llvm
298
299
#endif // GET_REGINFO_ENUM
300
301
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
302
|*                                                                            *|
303
|* MC Register Information                                                    *|
304
|*                                                                            *|
305
|* Automatically generated file, do not edit!                                 *|
306
|*                                                                            *|
307
\*===----------------------------------------------------------------------===*/
308
309
310
#ifdef GET_REGINFO_MC_DESC
311
#undef GET_REGINFO_MC_DESC
312
313
namespace llvm {
314
315
extern const MCPhysReg SparcRegDiffLists[] = {
316
  /* 0 */ 64871, 1, 1, 1, 0,
317
  /* 5 */ 32, 1, 0,
318
  /* 8 */ 65436, 32, 1, 65504, 33, 1, 0,
319
  /* 15 */ 34, 1, 0,
320
  /* 18 */ 65437, 34, 1, 65502, 35, 1, 0,
321
  /* 25 */ 36, 1, 0,
322
  /* 28 */ 65438, 36, 1, 65500, 37, 1, 0,
323
  /* 35 */ 38, 1, 0,
324
  /* 38 */ 65439, 38, 1, 65498, 39, 1, 0,
325
  /* 45 */ 40, 1, 0,
326
  /* 48 */ 65440, 40, 1, 65496, 41, 1, 0,
327
  /* 55 */ 42, 1, 0,
328
  /* 58 */ 65441, 42, 1, 65494, 43, 1, 0,
329
  /* 65 */ 44, 1, 0,
330
  /* 68 */ 65442, 44, 1, 65492, 45, 1, 0,
331
  /* 75 */ 46, 1, 0,
332
  /* 78 */ 65443, 46, 1, 65490, 47, 1, 0,
333
  /* 85 */ 65183, 1, 0,
334
  /* 88 */ 65235, 1, 0,
335
  /* 91 */ 65263, 1, 0,
336
  /* 94 */ 65388, 1, 0,
337
  /* 97 */ 65389, 1, 0,
338
  /* 100 */ 65390, 1, 0,
339
  /* 103 */ 65391, 1, 0,
340
  /* 106 */ 65392, 1, 0,
341
  /* 109 */ 65393, 1, 0,
342
  /* 112 */ 65394, 1, 0,
343
  /* 115 */ 65395, 1, 0,
344
  /* 118 */ 65396, 1, 0,
345
  /* 121 */ 65397, 1, 0,
346
  /* 124 */ 65398, 1, 0,
347
  /* 127 */ 65399, 1, 0,
348
  /* 130 */ 65400, 1, 0,
349
  /* 133 */ 65401, 1, 0,
350
  /* 136 */ 65402, 1, 0,
351
  /* 139 */ 65403, 1, 0,
352
  /* 142 */ 65444, 1, 0,
353
  /* 145 */ 65445, 1, 0,
354
  /* 148 */ 65446, 1, 0,
355
  /* 151 */ 65447, 1, 0,
356
  /* 154 */ 65448, 1, 0,
357
  /* 157 */ 65449, 1, 0,
358
  /* 160 */ 65450, 1, 0,
359
  /* 163 */ 65451, 1, 0,
360
  /* 166 */ 65472, 1, 0,
361
  /* 169 */ 65473, 1, 0,
362
  /* 172 */ 65474, 1, 0,
363
  /* 175 */ 65475, 1, 0,
364
  /* 178 */ 65476, 1, 0,
365
  /* 181 */ 65477, 1, 0,
366
  /* 184 */ 65478, 1, 0,
367
  /* 187 */ 65479, 1, 0,
368
  /* 190 */ 65480, 1, 0,
369
  /* 193 */ 65481, 1, 0,
370
  /* 196 */ 65482, 1, 0,
371
  /* 199 */ 65483, 1, 0,
372
  /* 202 */ 65484, 1, 0,
373
  /* 205 */ 65485, 1, 0,
374
  /* 208 */ 65486, 1, 0,
375
  /* 211 */ 65487, 1, 0,
376
  /* 214 */ 15, 0,
377
  /* 216 */ 48, 0,
378
  /* 218 */ 49, 0,
379
  /* 220 */ 50, 0,
380
  /* 222 */ 51, 0,
381
  /* 224 */ 52, 0,
382
  /* 226 */ 53, 0,
383
  /* 228 */ 54, 0,
384
  /* 230 */ 55, 0,
385
  /* 232 */ 56, 0,
386
  /* 234 */ 57, 0,
387
  /* 236 */ 58, 0,
388
  /* 238 */ 59, 0,
389
  /* 240 */ 60, 0,
390
  /* 242 */ 61, 0,
391
  /* 244 */ 62, 0,
392
  /* 246 */ 63, 0,
393
  /* 248 */ 64, 0,
394
  /* 250 */ 84, 0,
395
  /* 252 */ 85, 0,
396
  /* 254 */ 86, 0,
397
  /* 256 */ 87, 0,
398
  /* 258 */ 88, 0,
399
  /* 260 */ 89, 0,
400
  /* 262 */ 90, 0,
401
  /* 264 */ 91, 0,
402
  /* 266 */ 65488, 92, 0,
403
  /* 269 */ 65489, 92, 0,
404
  /* 272 */ 65489, 93, 0,
405
  /* 275 */ 65490, 93, 0,
406
  /* 278 */ 65491, 93, 0,
407
  /* 281 */ 65491, 94, 0,
408
  /* 284 */ 65492, 94, 0,
409
  /* 287 */ 65493, 94, 0,
410
  /* 290 */ 65493, 95, 0,
411
  /* 293 */ 65494, 95, 0,
412
  /* 296 */ 65495, 95, 0,
413
  /* 299 */ 65495, 96, 0,
414
  /* 302 */ 65496, 96, 0,
415
  /* 305 */ 65497, 96, 0,
416
  /* 308 */ 65497, 97, 0,
417
  /* 311 */ 65498, 97, 0,
418
  /* 314 */ 65499, 97, 0,
419
  /* 317 */ 65499, 98, 0,
420
  /* 320 */ 65500, 98, 0,
421
  /* 323 */ 65501, 98, 0,
422
  /* 326 */ 65501, 99, 0,
423
  /* 329 */ 65502, 99, 0,
424
  /* 332 */ 65503, 99, 0,
425
  /* 335 */ 65503, 100, 0,
426
  /* 338 */ 65504, 100, 0,
427
  /* 341 */ 132, 0,
428
  /* 343 */ 133, 0,
429
  /* 345 */ 134, 0,
430
  /* 347 */ 135, 0,
431
  /* 349 */ 136, 0,
432
  /* 351 */ 137, 0,
433
  /* 353 */ 138, 0,
434
  /* 355 */ 139, 0,
435
  /* 357 */ 140, 0,
436
  /* 359 */ 141, 0,
437
  /* 361 */ 142, 0,
438
  /* 363 */ 143, 0,
439
  /* 365 */ 144, 0,
440
  /* 367 */ 145, 0,
441
  /* 369 */ 146, 0,
442
  /* 371 */ 147, 0,
443
  /* 373 */ 148, 0,
444
  /* 375 */ 65503, 0,
445
  /* 377 */ 65519, 0,
446
  /* 379 */ 65535, 0,
447
};
448
449
extern const LaneBitmask SparcLaneMaskLists[] = {
450
  /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
451
  /* 2 */ LaneBitmask(0x00000001), LaneBitmask(0x00000002), LaneBitmask::getAll(),
452
  /* 5 */ LaneBitmask(0x00000001), LaneBitmask(0x00000002), LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask::getAll(),
453
  /* 10 */ LaneBitmask(0x00000003), LaneBitmask(0x0000000C), LaneBitmask::getAll(),
454
};
455
456
extern const uint16_t SparcSubRegIdxLists[] = {
457
  /* 0 */ 1, 3, 0,
458
  /* 3 */ 2, 4, 0,
459
  /* 6 */ 2, 1, 3, 4, 5, 6, 0,
460
};
461
462
extern const MCRegisterInfo::SubRegCoveredBits SparcSubRegIdxRanges[] = {
463
  { 65535, 65535 },
464
  { 0, 32 },  // sub_even
465
  { 0, 64 },  // sub_even64
466
  { 32, 32 }, // sub_odd
467
  { 64, 64 }, // sub_odd64
468
  { 64, 32 }, // sub_odd64_then_sub_even
469
  { 96, 32 }, // sub_odd64_then_sub_odd
470
};
471
472
extern const char SparcRegStrings[] = {
473
  /* 0 */ 'C', '1', '0', 0,
474
  /* 4 */ 'D', '1', '0', 0,
475
  /* 8 */ 'F', '1', '0', 0,
476
  /* 12 */ 'Q', '1', '0', 0,
477
  /* 16 */ 'A', 'S', 'R', '1', '0', 0,
478
  /* 22 */ 'C', '2', '0', 0,
479
  /* 26 */ 'D', '2', '0', 0,
480
  /* 30 */ 'F', '2', '0', 0,
481
  /* 34 */ 'A', 'S', 'R', '2', '0', 0,
482
  /* 40 */ 'C', '3', '0', 0,
483
  /* 44 */ 'D', '3', '0', 0,
484
  /* 48 */ 'F', '3', '0', 0,
485
  /* 52 */ 'A', 'S', 'R', '3', '0', 0,
486
  /* 58 */ 'F', 'C', 'C', '0', 0,
487
  /* 63 */ 'D', '0', 0,
488
  /* 66 */ 'F', '0', 0,
489
  /* 69 */ 'G', '0', 0,
490
  /* 72 */ 'I', '0', 0,
491
  /* 75 */ 'L', '0', 0,
492
  /* 78 */ 'O', '0', 0,
493
  /* 81 */ 'Q', '0', 0,
494
  /* 84 */ 'C', '1', '0', '_', 'C', '1', '1', 0,
495
  /* 92 */ 'D', '1', '1', 0,
496
  /* 96 */ 'F', '1', '1', 0,
497
  /* 100 */ 'Q', '1', '1', 0,
498
  /* 104 */ 'A', 'S', 'R', '1', '1', 0,
499
  /* 110 */ 'C', '2', '0', '_', 'C', '2', '1', 0,
500
  /* 118 */ 'D', '2', '1', 0,
501
  /* 122 */ 'F', '2', '1', 0,
502
  /* 126 */ 'A', 'S', 'R', '2', '1', 0,
503
  /* 132 */ 'C', '3', '0', '_', 'C', '3', '1', 0,
504
  /* 140 */ 'D', '3', '1', 0,
505
  /* 144 */ 'F', '3', '1', 0,
506
  /* 148 */ 'A', 'S', 'R', '3', '1', 0,
507
  /* 154 */ 'F', 'C', 'C', '1', 0,
508
  /* 159 */ 'C', '0', '_', 'C', '1', 0,
509
  /* 165 */ 'D', '1', 0,
510
  /* 168 */ 'F', '1', 0,
511
  /* 171 */ 'G', '0', '_', 'G', '1', 0,
512
  /* 177 */ 'I', '0', '_', 'I', '1', 0,
513
  /* 183 */ 'L', '0', '_', 'L', '1', 0,
514
  /* 189 */ 'O', '0', '_', 'O', '1', 0,
515
  /* 195 */ 'Q', '1', 0,
516
  /* 198 */ 'A', 'S', 'R', '1', 0,
517
  /* 203 */ 'C', '1', '2', 0,
518
  /* 207 */ 'D', '1', '2', 0,
519
  /* 211 */ 'F', '1', '2', 0,
520
  /* 215 */ 'Q', '1', '2', 0,
521
  /* 219 */ 'A', 'S', 'R', '1', '2', 0,
522
  /* 225 */ 'C', '2', '2', 0,
523
  /* 229 */ 'D', '2', '2', 0,
524
  /* 233 */ 'F', '2', '2', 0,
525
  /* 237 */ 'A', 'S', 'R', '2', '2', 0,
526
  /* 243 */ 'F', 'C', 'C', '2', 0,
527
  /* 248 */ 'D', '2', 0,
528
  /* 251 */ 'F', '2', 0,
529
  /* 254 */ 'G', '2', 0,
530
  /* 257 */ 'I', '2', 0,
531
  /* 260 */ 'L', '2', 0,
532
  /* 263 */ 'O', '2', 0,
533
  /* 266 */ 'Q', '2', 0,
534
  /* 269 */ 'A', 'S', 'R', '2', 0,
535
  /* 274 */ 'C', '1', '2', '_', 'C', '1', '3', 0,
536
  /* 282 */ 'D', '1', '3', 0,
537
  /* 286 */ 'F', '1', '3', 0,
538
  /* 290 */ 'Q', '1', '3', 0,
539
  /* 294 */ 'A', 'S', 'R', '1', '3', 0,
540
  /* 300 */ 'C', '2', '2', '_', 'C', '2', '3', 0,
541
  /* 308 */ 'D', '2', '3', 0,
542
  /* 312 */ 'F', '2', '3', 0,
543
  /* 316 */ 'A', 'S', 'R', '2', '3', 0,
544
  /* 322 */ 'F', 'C', 'C', '3', 0,
545
  /* 327 */ 'C', '2', '_', 'C', '3', 0,
546
  /* 333 */ 'D', '3', 0,
547
  /* 336 */ 'F', '3', 0,
548
  /* 339 */ 'G', '2', '_', 'G', '3', 0,
549
  /* 345 */ 'I', '2', '_', 'I', '3', 0,
550
  /* 351 */ 'L', '2', '_', 'L', '3', 0,
551
  /* 357 */ 'O', '2', '_', 'O', '3', 0,
552
  /* 363 */ 'Q', '3', 0,
553
  /* 366 */ 'A', 'S', 'R', '3', 0,
554
  /* 371 */ 'C', '1', '4', 0,
555
  /* 375 */ 'D', '1', '4', 0,
556
  /* 379 */ 'F', '1', '4', 0,
557
  /* 383 */ 'Q', '1', '4', 0,
558
  /* 387 */ 'A', 'S', 'R', '1', '4', 0,
559
  /* 393 */ 'C', '2', '4', 0,
560
  /* 397 */ 'D', '2', '4', 0,
561
  /* 401 */ 'F', '2', '4', 0,
562
  /* 405 */ 'A', 'S', 'R', '2', '4', 0,
563
  /* 411 */ 'C', '4', 0,
564
  /* 414 */ 'D', '4', 0,
565
  /* 417 */ 'F', '4', 0,
566
  /* 420 */ 'G', '4', 0,
567
  /* 423 */ 'I', '4', 0,
568
  /* 426 */ 'L', '4', 0,
569
  /* 429 */ 'O', '4', 0,
570
  /* 432 */ 'Q', '4', 0,
571
  /* 435 */ 'A', 'S', 'R', '4', 0,
572
  /* 440 */ 'C', '1', '4', '_', 'C', '1', '5', 0,
573
  /* 448 */ 'D', '1', '5', 0,
574
  /* 452 */ 'F', '1', '5', 0,
575
  /* 456 */ 'Q', '1', '5', 0,
576
  /* 460 */ 'A', 'S', 'R', '1', '5', 0,
577
  /* 466 */ 'C', '2', '4', '_', 'C', '2', '5', 0,
578
  /* 474 */ 'D', '2', '5', 0,
579
  /* 478 */ 'F', '2', '5', 0,
580
  /* 482 */ 'A', 'S', 'R', '2', '5', 0,
581
  /* 488 */ 'C', '4', '_', 'C', '5', 0,
582
  /* 494 */ 'D', '5', 0,
583
  /* 497 */ 'F', '5', 0,
584
  /* 500 */ 'G', '4', '_', 'G', '5', 0,
585
  /* 506 */ 'I', '4', '_', 'I', '5', 0,
586
  /* 512 */ 'L', '4', '_', 'L', '5', 0,
587
  /* 518 */ 'O', '4', '_', 'O', '5', 0,
588
  /* 524 */ 'Q', '5', 0,
589
  /* 527 */ 'A', 'S', 'R', '5', 0,
590
  /* 532 */ 'C', '1', '6', 0,
591
  /* 536 */ 'D', '1', '6', 0,
592
  /* 540 */ 'F', '1', '6', 0,
593
  /* 544 */ 'A', 'S', 'R', '1', '6', 0,
594
  /* 550 */ 'C', '2', '6', 0,
595
  /* 554 */ 'D', '2', '6', 0,
596
  /* 558 */ 'F', '2', '6', 0,
597
  /* 562 */ 'A', 'S', 'R', '2', '6', 0,
598
  /* 568 */ 'C', '6', 0,
599
  /* 571 */ 'D', '6', 0,
600
  /* 574 */ 'F', '6', 0,
601
  /* 577 */ 'G', '6', 0,
602
  /* 580 */ 'I', '6', 0,
603
  /* 583 */ 'L', '6', 0,
604
  /* 586 */ 'O', '6', 0,
605
  /* 589 */ 'Q', '6', 0,
606
  /* 592 */ 'A', 'S', 'R', '6', 0,
607
  /* 597 */ 'C', '1', '6', '_', 'C', '1', '7', 0,
608
  /* 605 */ 'D', '1', '7', 0,
609
  /* 609 */ 'F', '1', '7', 0,
610
  /* 613 */ 'A', 'S', 'R', '1', '7', 0,
611
  /* 619 */ 'C', '2', '6', '_', 'C', '2', '7', 0,
612
  /* 627 */ 'D', '2', '7', 0,
613
  /* 631 */ 'F', '2', '7', 0,
614
  /* 635 */ 'A', 'S', 'R', '2', '7', 0,
615
  /* 641 */ 'C', '6', '_', 'C', '7', 0,
616
  /* 647 */ 'D', '7', 0,
617
  /* 650 */ 'F', '7', 0,
618
  /* 653 */ 'G', '6', '_', 'G', '7', 0,
619
  /* 659 */ 'I', '6', '_', 'I', '7', 0,
620
  /* 665 */ 'L', '6', '_', 'L', '7', 0,
621
  /* 671 */ 'O', '6', '_', 'O', '7', 0,
622
  /* 677 */ 'Q', '7', 0,
623
  /* 680 */ 'A', 'S', 'R', '7', 0,
624
  /* 685 */ 'C', '1', '8', 0,
625
  /* 689 */ 'D', '1', '8', 0,
626
  /* 693 */ 'F', '1', '8', 0,
627
  /* 697 */ 'A', 'S', 'R', '1', '8', 0,
628
  /* 703 */ 'C', '2', '8', 0,
629
  /* 707 */ 'D', '2', '8', 0,
630
  /* 711 */ 'F', '2', '8', 0,
631
  /* 715 */ 'A', 'S', 'R', '2', '8', 0,
632
  /* 721 */ 'C', '8', 0,
633
  /* 724 */ 'D', '8', 0,
634
  /* 727 */ 'F', '8', 0,
635
  /* 730 */ 'Q', '8', 0,
636
  /* 733 */ 'A', 'S', 'R', '8', 0,
637
  /* 738 */ 'C', '1', '8', '_', 'C', '1', '9', 0,
638
  /* 746 */ 'D', '1', '9', 0,
639
  /* 750 */ 'F', '1', '9', 0,
640
  /* 754 */ 'A', 'S', 'R', '1', '9', 0,
641
  /* 760 */ 'C', '2', '8', '_', 'C', '2', '9', 0,
642
  /* 768 */ 'D', '2', '9', 0,
643
  /* 772 */ 'F', '2', '9', 0,
644
  /* 776 */ 'A', 'S', 'R', '2', '9', 0,
645
  /* 782 */ 'C', '8', '_', 'C', '9', 0,
646
  /* 788 */ 'D', '9', 0,
647
  /* 791 */ 'F', '9', 0,
648
  /* 794 */ 'Q', '9', 0,
649
  /* 797 */ 'A', 'S', 'R', '9', 0,
650
  /* 802 */ 'T', 'B', 'A', 0,
651
  /* 806 */ 'I', 'C', 'C', 0,
652
  /* 810 */ 'T', 'N', 'P', 'C', 0,
653
  /* 815 */ 'T', 'P', 'C', 0,
654
  /* 819 */ 'C', 'A', 'N', 'R', 'E', 'S', 'T', 'O', 'R', 'E', 0,
655
  /* 830 */ 'P', 'S', 'T', 'A', 'T', 'E', 0,
656
  /* 837 */ 'T', 'S', 'T', 'A', 'T', 'E', 0,
657
  /* 844 */ 'W', 'S', 'T', 'A', 'T', 'E', 0,
658
  /* 851 */ 'C', 'A', 'N', 'S', 'A', 'V', 'E', 0,
659
  /* 859 */ 'T', 'I', 'C', 'K', 0,
660
  /* 864 */ 'P', 'I', 'L', 0,
661
  /* 868 */ 'T', 'L', 0,
662
  /* 871 */ 'W', 'I', 'M', 0,
663
  /* 875 */ 'C', 'L', 'E', 'A', 'N', 'W', 'I', 'N', 0,
664
  /* 884 */ 'O', 'T', 'H', 'E', 'R', 'W', 'I', 'N', 0,
665
  /* 893 */ 'C', 'W', 'P', 0,
666
  /* 897 */ 'F', 'Q', 0,
667
  /* 900 */ 'C', 'P', 'Q', 0,
668
  /* 904 */ 'T', 'B', 'R', 0,
669
  /* 908 */ 'F', 'S', 'R', 0,
670
  /* 912 */ 'C', 'P', 'S', 'R', 0,
671
  /* 917 */ 'T', 'T', 0,
672
  /* 920 */ 'Y', 0,
673
};
674
675
extern const MCRegisterDesc SparcRegDesc[] = { // Descriptors
676
  { 3, 0, 0, 0, 0, 0 },
677
  { 819, 4, 4, 2, 6065, 0 },
678
  { 851, 4, 4, 2, 6065, 0 },
679
  { 875, 4, 4, 2, 6065, 0 },
680
  { 900, 4, 4, 2, 6065, 0 },
681
  { 912, 4, 4, 2, 6065, 0 },
682
  { 893, 4, 4, 2, 6065, 0 },
683
  { 897, 4, 4, 2, 6065, 0 },
684
  { 908, 4, 4, 2, 6065, 0 },
685
  { 806, 4, 4, 2, 6065, 0 },
686
  { 884, 4, 4, 2, 6065, 0 },
687
  { 864, 4, 4, 2, 6065, 0 },
688
  { 913, 4, 4, 2, 6065, 0 },
689
  { 830, 4, 4, 2, 6065, 0 },
690
  { 802, 4, 4, 2, 6065, 0 },
691
  { 904, 4, 4, 2, 6065, 0 },
692
  { 859, 4, 4, 2, 6065, 0 },
693
  { 868, 4, 4, 2, 6065, 0 },
694
  { 810, 4, 4, 2, 6065, 0 },
695
  { 815, 4, 4, 2, 6065, 0 },
696
  { 837, 4, 4, 2, 6065, 0 },
697
  { 917, 4, 4, 2, 6065, 0 },
698
  { 871, 4, 4, 2, 6065, 0 },
699
  { 844, 4, 4, 2, 6065, 0 },
700
  { 920, 4, 4, 2, 6065, 0 },
701
  { 198, 4, 4, 2, 6065, 0 },
702
  { 269, 4, 4, 2, 6065, 0 },
703
  { 366, 4, 4, 2, 6065, 0 },
704
  { 435, 4, 4, 2, 6065, 0 },
705
  { 527, 4, 4, 2, 6065, 0 },
706
  { 592, 4, 4, 2, 6065, 0 },
707
  { 680, 4, 4, 2, 6065, 0 },
708
  { 733, 4, 4, 2, 6065, 0 },
709
  { 797, 4, 4, 2, 6065, 0 },
710
  { 16, 4, 4, 2, 6065, 0 },
711
  { 104, 4, 4, 2, 6065, 0 },
712
  { 219, 4, 4, 2, 6065, 0 },
713
  { 294, 4, 4, 2, 6065, 0 },
714
  { 387, 4, 4, 2, 6065, 0 },
715
  { 460, 4, 4, 2, 6065, 0 },
716
  { 544, 4, 4, 2, 6065, 0 },
717
  { 613, 4, 4, 2, 6065, 0 },
718
  { 697, 4, 4, 2, 6065, 0 },
719
  { 754, 4, 4, 2, 6065, 0 },
720
  { 34, 4, 4, 2, 6065, 0 },
721
  { 126, 4, 4, 2, 6065, 0 },
722
  { 237, 4, 4, 2, 6065, 0 },
723
  { 316, 4, 4, 2, 6065, 0 },
724
  { 405, 4, 4, 2, 6065, 0 },
725
  { 482, 4, 4, 2, 6065, 0 },
726
  { 562, 4, 4, 2, 6065, 0 },
727
  { 635, 4, 4, 2, 6065, 0 },
728
  { 715, 4, 4, 2, 6065, 0 },
729
  { 776, 4, 4, 2, 6065, 0 },
730
  { 52, 4, 4, 2, 6065, 0 },
731
  { 148, 4, 4, 2, 6065, 0 },
732
  { 60, 4, 373, 2, 6065, 0 },
733
  { 156, 4, 371, 2, 6065, 0 },
734
  { 245, 4, 371, 2, 6065, 0 },
735
  { 324, 4, 369, 2, 6065, 0 },
736
  { 411, 4, 369, 2, 6065, 0 },
737
  { 491, 4, 367, 2, 6065, 0 },
738
  { 568, 4, 367, 2, 6065, 0 },
739
  { 644, 4, 365, 2, 6065, 0 },
740
  { 721, 4, 365, 2, 6065, 0 },
741
  { 785, 4, 363, 2, 6065, 0 },
742
  { 0, 4, 363, 2, 6065, 0 },
743
  { 88, 4, 361, 2, 6065, 0 },
744
  { 203, 4, 361, 2, 6065, 0 },
745
  { 278, 4, 359, 2, 6065, 0 },
746
  { 371, 4, 359, 2, 6065, 0 },
747
  { 444, 4, 357, 2, 6065, 0 },
748
  { 532, 4, 357, 2, 6065, 0 },
749
  { 601, 4, 355, 2, 6065, 0 },
750
  { 685, 4, 355, 2, 6065, 0 },
751
  { 742, 4, 353, 2, 6065, 0 },
752
  { 22, 4, 353, 2, 6065, 0 },
753
  { 114, 4, 351, 2, 6065, 0 },
754
  { 225, 4, 351, 2, 6065, 0 },
755
  { 304, 4, 349, 2, 6065, 0 },
756
  { 393, 4, 349, 2, 6065, 0 },
757
  { 470, 4, 347, 2, 6065, 0 },
758
  { 550, 4, 347, 2, 6065, 0 },
759
  { 623, 4, 345, 2, 6065, 0 },
760
  { 703, 4, 345, 2, 6065, 0 },
761
  { 764, 4, 343, 2, 6065, 0 },
762
  { 40, 4, 343, 2, 6065, 0 },
763
  { 136, 4, 341, 2, 6065, 0 },
764
  { 63, 5, 336, 0, 2418, 2 },
765
  { 165, 12, 327, 0, 2418, 2 },
766
  { 248, 15, 327, 0, 2418, 2 },
767
  { 333, 22, 318, 0, 2418, 2 },
768
  { 414, 25, 318, 0, 2418, 2 },
769
  { 494, 32, 309, 0, 2418, 2 },
770
  { 571, 35, 309, 0, 2418, 2 },
771
  { 647, 42, 300, 0, 2418, 2 },
772
  { 724, 45, 300, 0, 2418, 2 },
773
  { 788, 52, 291, 0, 2418, 2 },
774
  { 4, 55, 291, 0, 2418, 2 },
775
  { 92, 62, 282, 0, 2418, 2 },
776
  { 207, 65, 282, 0, 2418, 2 },
777
  { 282, 72, 273, 0, 2418, 2 },
778
  { 375, 75, 273, 0, 2418, 2 },
779
  { 448, 82, 267, 0, 2418, 2 },
780
  { 536, 4, 267, 2, 3425, 0 },
781
  { 605, 4, 264, 2, 3425, 0 },
782
  { 689, 4, 264, 2, 3425, 0 },
783
  { 746, 4, 262, 2, 3425, 0 },
784
  { 26, 4, 262, 2, 3425, 0 },
785
  { 118, 4, 260, 2, 3425, 0 },
786
  { 229, 4, 260, 2, 3425, 0 },
787
  { 308, 4, 258, 2, 3425, 0 },
788
  { 397, 4, 258, 2, 3425, 0 },
789
  { 474, 4, 256, 2, 3425, 0 },
790
  { 554, 4, 256, 2, 3425, 0 },
791
  { 627, 4, 254, 2, 3425, 0 },
792
  { 707, 4, 254, 2, 3425, 0 },
793
  { 768, 4, 252, 2, 3425, 0 },
794
  { 44, 4, 252, 2, 3425, 0 },
795
  { 140, 4, 250, 2, 3425, 0 },
796
  { 66, 4, 338, 2, 6001, 0 },
797
  { 168, 4, 335, 2, 6001, 0 },
798
  { 251, 4, 332, 2, 6001, 0 },
799
  { 336, 4, 329, 2, 6001, 0 },
800
  { 417, 4, 329, 2, 6001, 0 },
801
  { 497, 4, 326, 2, 6001, 0 },
802
  { 574, 4, 323, 2, 6001, 0 },
803
  { 650, 4, 320, 2, 6001, 0 },
804
  { 727, 4, 320, 2, 6001, 0 },
805
  { 791, 4, 317, 2, 6001, 0 },
806
  { 8, 4, 314, 2, 6001, 0 },
807
  { 96, 4, 311, 2, 6001, 0 },
808
  { 211, 4, 311, 2, 6001, 0 },
809
  { 286, 4, 308, 2, 6001, 0 },
810
  { 379, 4, 305, 2, 6001, 0 },
811
  { 452, 4, 302, 2, 6001, 0 },
812
  { 540, 4, 302, 2, 6001, 0 },
813
  { 609, 4, 299, 2, 6001, 0 },
814
  { 693, 4, 296, 2, 6001, 0 },
815
  { 750, 4, 293, 2, 6001, 0 },
816
  { 30, 4, 293, 2, 6001, 0 },
817
  { 122, 4, 290, 2, 6001, 0 },
818
  { 233, 4, 287, 2, 6001, 0 },
819
  { 312, 4, 284, 2, 6001, 0 },
820
  { 401, 4, 284, 2, 6001, 0 },
821
  { 478, 4, 281, 2, 6001, 0 },
822
  { 558, 4, 278, 2, 6001, 0 },
823
  { 631, 4, 275, 2, 6001, 0 },
824
  { 711, 4, 275, 2, 6001, 0 },
825
  { 772, 4, 272, 2, 6001, 0 },
826
  { 48, 4, 269, 2, 6001, 0 },
827
  { 144, 4, 266, 2, 6001, 0 },
828
  { 58, 4, 4, 2, 6033, 0 },
829
  { 154, 4, 4, 2, 6033, 0 },
830
  { 243, 4, 4, 2, 6033, 0 },
831
  { 322, 4, 4, 2, 6033, 0 },
832
  { 69, 4, 248, 2, 6033, 0 },
833
  { 174, 4, 246, 2, 6033, 0 },
834
  { 254, 4, 246, 2, 6033, 0 },
835
  { 342, 4, 244, 2, 6033, 0 },
836
  { 420, 4, 244, 2, 6033, 0 },
837
  { 503, 4, 242, 2, 6033, 0 },
838
  { 577, 4, 242, 2, 6033, 0 },
839
  { 656, 4, 240, 2, 6033, 0 },
840
  { 72, 4, 240, 2, 6033, 0 },
841
  { 180, 4, 238, 2, 6033, 0 },
842
  { 257, 4, 238, 2, 6033, 0 },
843
  { 348, 4, 236, 2, 6033, 0 },
844
  { 423, 4, 236, 2, 6033, 0 },
845
  { 509, 4, 234, 2, 6033, 0 },
846
  { 580, 4, 234, 2, 6033, 0 },
847
  { 662, 4, 232, 2, 6033, 0 },
848
  { 75, 4, 232, 2, 6033, 0 },
849
  { 186, 4, 230, 2, 6033, 0 },
850
  { 260, 4, 230, 2, 6033, 0 },
851
  { 354, 4, 228, 2, 6033, 0 },
852
  { 426, 4, 228, 2, 6033, 0 },
853
  { 515, 4, 226, 2, 6033, 0 },
854
  { 583, 4, 226, 2, 6033, 0 },
855
  { 668, 4, 224, 2, 6033, 0 },
856
  { 78, 4, 224, 2, 6033, 0 },
857
  { 192, 4, 222, 2, 6033, 0 },
858
  { 263, 4, 222, 2, 6033, 0 },
859
  { 360, 4, 220, 2, 6033, 0 },
860
  { 429, 4, 220, 2, 6033, 0 },
861
  { 521, 4, 218, 2, 6033, 0 },
862
  { 586, 4, 218, 2, 6033, 0 },
863
  { 674, 4, 216, 2, 6033, 0 },
864
  { 81, 8, 4, 6, 4, 5 },
865
  { 195, 18, 4, 6, 4, 5 },
866
  { 266, 28, 4, 6, 4, 5 },
867
  { 363, 38, 4, 6, 4, 5 },
868
  { 432, 48, 4, 6, 4, 5 },
869
  { 524, 58, 4, 6, 4, 5 },
870
  { 589, 68, 4, 6, 4, 5 },
871
  { 677, 78, 4, 6, 4, 5 },
872
  { 730, 142, 4, 3, 1458, 10 },
873
  { 794, 145, 4, 3, 1458, 10 },
874
  { 12, 148, 4, 3, 1458, 10 },
875
  { 100, 151, 4, 3, 1458, 10 },
876
  { 215, 154, 4, 3, 1458, 10 },
877
  { 290, 157, 4, 3, 1458, 10 },
878
  { 383, 160, 4, 3, 1458, 10 },
879
  { 456, 163, 4, 3, 1458, 10 },
880
  { 159, 94, 4, 0, 1362, 2 },
881
  { 327, 97, 4, 0, 1362, 2 },
882
  { 488, 100, 4, 0, 1362, 2 },
883
  { 641, 103, 4, 0, 1362, 2 },
884
  { 782, 106, 4, 0, 1362, 2 },
885
  { 84, 109, 4, 0, 1362, 2 },
886
  { 274, 112, 4, 0, 1362, 2 },
887
  { 440, 115, 4, 0, 1362, 2 },
888
  { 597, 118, 4, 0, 1362, 2 },
889
  { 738, 121, 4, 0, 1362, 2 },
890
  { 110, 124, 4, 0, 1362, 2 },
891
  { 300, 127, 4, 0, 1362, 2 },
892
  { 466, 130, 4, 0, 1362, 2 },
893
  { 619, 133, 4, 0, 1362, 2 },
894
  { 760, 136, 4, 0, 1362, 2 },
895
  { 132, 139, 4, 0, 1362, 2 },
896
  { 171, 166, 4, 0, 1410, 2 },
897
  { 339, 169, 4, 0, 1410, 2 },
898
  { 500, 172, 4, 0, 1410, 2 },
899
  { 653, 175, 4, 0, 1410, 2 },
900
  { 177, 178, 4, 0, 1410, 2 },
901
  { 345, 181, 4, 0, 1410, 2 },
902
  { 506, 184, 4, 0, 1410, 2 },
903
  { 659, 187, 4, 0, 1410, 2 },
904
  { 183, 190, 4, 0, 1410, 2 },
905
  { 351, 193, 4, 0, 1410, 2 },
906
  { 512, 196, 4, 0, 1410, 2 },
907
  { 665, 199, 4, 0, 1410, 2 },
908
  { 189, 202, 4, 0, 1410, 2 },
909
  { 357, 205, 4, 0, 1410, 2 },
910
  { 518, 208, 4, 0, 1410, 2 },
911
  { 671, 211, 4, 0, 1410, 2 },
912
};
913
914
extern const MCPhysReg SparcRegUnitRoots[][2] = {
915
  { SP::CANRESTORE },
916
  { SP::CANSAVE },
917
  { SP::CLEANWIN },
918
  { SP::CPQ },
919
  { SP::CPSR },
920
  { SP::CWP },
921
  { SP::FQ },
922
  { SP::FSR },
923
  { SP::ICC },
924
  { SP::OTHERWIN },
925
  { SP::PIL },
926
  { SP::PSR },
927
  { SP::PSTATE },
928
  { SP::TBA },
929
  { SP::TBR },
930
  { SP::TICK },
931
  { SP::TL },
932
  { SP::TNPC },
933
  { SP::TPC },
934
  { SP::TSTATE },
935
  { SP::TT },
936
  { SP::WIM },
937
  { SP::WSTATE },
938
  { SP::Y },
939
  { SP::ASR1 },
940
  { SP::ASR2 },
941
  { SP::ASR3 },
942
  { SP::ASR4 },
943
  { SP::ASR5 },
944
  { SP::ASR6 },
945
  { SP::ASR7 },
946
  { SP::ASR8 },
947
  { SP::ASR9 },
948
  { SP::ASR10 },
949
  { SP::ASR11 },
950
  { SP::ASR12 },
951
  { SP::ASR13 },
952
  { SP::ASR14 },
953
  { SP::ASR15 },
954
  { SP::ASR16 },
955
  { SP::ASR17 },
956
  { SP::ASR18 },
957
  { SP::ASR19 },
958
  { SP::ASR20 },
959
  { SP::ASR21 },
960
  { SP::ASR22 },
961
  { SP::ASR23 },
962
  { SP::ASR24 },
963
  { SP::ASR25 },
964
  { SP::ASR26 },
965
  { SP::ASR27 },
966
  { SP::ASR28 },
967
  { SP::ASR29 },
968
  { SP::ASR30 },
969
  { SP::ASR31 },
970
  { SP::C0 },
971
  { SP::C1 },
972
  { SP::C2 },
973
  { SP::C3 },
974
  { SP::C4 },
975
  { SP::C5 },
976
  { SP::C6 },
977
  { SP::C7 },
978
  { SP::C8 },
979
  { SP::C9 },
980
  { SP::C10 },
981
  { SP::C11 },
982
  { SP::C12 },
983
  { SP::C13 },
984
  { SP::C14 },
985
  { SP::C15 },
986
  { SP::C16 },
987
  { SP::C17 },
988
  { SP::C18 },
989
  { SP::C19 },
990
  { SP::C20 },
991
  { SP::C21 },
992
  { SP::C22 },
993
  { SP::C23 },
994
  { SP::C24 },
995
  { SP::C25 },
996
  { SP::C26 },
997
  { SP::C27 },
998
  { SP::C28 },
999
  { SP::C29 },
1000
  { SP::C30 },
1001
  { SP::C31 },
1002
  { SP::F0 },
1003
  { SP::F1 },
1004
  { SP::F2 },
1005
  { SP::F3 },
1006
  { SP::F4 },
1007
  { SP::F5 },
1008
  { SP::F6 },
1009
  { SP::F7 },
1010
  { SP::F8 },
1011
  { SP::F9 },
1012
  { SP::F10 },
1013
  { SP::F11 },
1014
  { SP::F12 },
1015
  { SP::F13 },
1016
  { SP::F14 },
1017
  { SP::F15 },
1018
  { SP::F16 },
1019
  { SP::F17 },
1020
  { SP::F18 },
1021
  { SP::F19 },
1022
  { SP::F20 },
1023
  { SP::F21 },
1024
  { SP::F22 },
1025
  { SP::F23 },
1026
  { SP::F24 },
1027
  { SP::F25 },
1028
  { SP::F26 },
1029
  { SP::F27 },
1030
  { SP::F28 },
1031
  { SP::F29 },
1032
  { SP::F30 },
1033
  { SP::F31 },
1034
  { SP::D16 },
1035
  { SP::D17 },
1036
  { SP::D18 },
1037
  { SP::D19 },
1038
  { SP::D20 },
1039
  { SP::D21 },
1040
  { SP::D22 },
1041
  { SP::D23 },
1042
  { SP::D24 },
1043
  { SP::D25 },
1044
  { SP::D26 },
1045
  { SP::D27 },
1046
  { SP::D28 },
1047
  { SP::D29 },
1048
  { SP::D30 },
1049
  { SP::D31 },
1050
  { SP::FCC0 },
1051
  { SP::FCC1 },
1052
  { SP::FCC2 },
1053
  { SP::FCC3 },
1054
  { SP::G0 },
1055
  { SP::G1 },
1056
  { SP::G2 },
1057
  { SP::G3 },
1058
  { SP::G4 },
1059
  { SP::G5 },
1060
  { SP::G6 },
1061
  { SP::G7 },
1062
  { SP::I0 },
1063
  { SP::I1 },
1064
  { SP::I2 },
1065
  { SP::I3 },
1066
  { SP::I4 },
1067
  { SP::I5 },
1068
  { SP::I6 },
1069
  { SP::I7 },
1070
  { SP::L0 },
1071
  { SP::L1 },
1072
  { SP::L2 },
1073
  { SP::L3 },
1074
  { SP::L4 },
1075
  { SP::L5 },
1076
  { SP::L6 },
1077
  { SP::L7 },
1078
  { SP::O0 },
1079
  { SP::O1 },
1080
  { SP::O2 },
1081
  { SP::O3 },
1082
  { SP::O4 },
1083
  { SP::O5 },
1084
  { SP::O6 },
1085
  { SP::O7 },
1086
};
1087
1088
namespace {     // Register classes...
1089
  // FCCRegs Register Class...
1090
  const MCPhysReg FCCRegs[] = {
1091
    SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3, 
1092
  };
1093
1094
  // FCCRegs Bit set.
1095
  const uint8_t FCCRegsBits[] = {
1096
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 
1097
  };
1098
1099
  // ASRRegs Register Class...
1100
  const MCPhysReg ASRRegs[] = {
1101
    SP::Y, SP::ASR1, SP::ASR2, SP::ASR3, SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7, SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11, SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15, SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19, SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23, SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27, SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31, 
1102
  };
1103
1104
  // ASRRegs Bit set.
1105
  const uint8_t ASRRegsBits[] = {
1106
    0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 
1107
  };
1108
1109
  // CoprocRegs Register Class...
1110
  const MCPhysReg CoprocRegs[] = {
1111
    SP::C0, SP::C1, SP::C2, SP::C3, SP::C4, SP::C5, SP::C6, SP::C7, SP::C8, SP::C9, SP::C10, SP::C11, SP::C12, SP::C13, SP::C14, SP::C15, SP::C16, SP::C17, SP::C18, SP::C19, SP::C20, SP::C21, SP::C22, SP::C23, SP::C24, SP::C25, SP::C26, SP::C27, SP::C28, SP::C29, SP::C30, SP::C31, 
1112
  };
1113
1114
  // CoprocRegs Bit set.
1115
  const uint8_t CoprocRegsBits[] = {
1116
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 
1117
  };
1118
1119
  // FPRegs Register Class...
1120
  const MCPhysReg FPRegs[] = {
1121
    SP::F0, SP::F1, SP::F2, SP::F3, SP::F4, SP::F5, SP::F6, SP::F7, SP::F8, SP::F9, SP::F10, SP::F11, SP::F12, SP::F13, SP::F14, SP::F15, SP::F16, SP::F17, SP::F18, SP::F19, SP::F20, SP::F21, SP::F22, SP::F23, SP::F24, SP::F25, SP::F26, SP::F27, SP::F28, SP::F29, SP::F30, SP::F31, 
1122
  };
1123
1124
  // FPRegs Bit set.
1125
  const uint8_t FPRegsBits[] = {
1126
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 
1127
  };
1128
1129
  // IntRegs Register Class...
1130
  const MCPhysReg IntRegs[] = {
1131
    SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5, SP::I6, SP::I7, SP::G0, SP::G1, SP::G2, SP::G3, SP::G4, SP::G5, SP::G6, SP::G7, SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::O6, SP::O7, 
1132
  };
1133
1134
  // IntRegs Bit set.
1135
  const uint8_t IntRegsBits[] = {
1136
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
1137
  };
1138
1139
  // DFPRegs Register Class...
1140
  const MCPhysReg DFPRegs[] = {
1141
    SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15, SP::D16, SP::D17, SP::D18, SP::D19, SP::D20, SP::D21, SP::D22, SP::D23, SP::D24, SP::D25, SP::D26, SP::D27, SP::D28, SP::D29, SP::D30, SP::D31, 
1142
  };
1143
1144
  // DFPRegs Bit set.
1145
  const uint8_t DFPRegsBits[] = {
1146
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 
1147
  };
1148
1149
  // I64Regs Register Class...
1150
  const MCPhysReg I64Regs[] = {
1151
    SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5, SP::I6, SP::I7, SP::G0, SP::G1, SP::G2, SP::G3, SP::G4, SP::G5, SP::G6, SP::G7, SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::O6, SP::O7, 
1152
  };
1153
1154
  // I64Regs Bit set.
1155
  const uint8_t I64RegsBits[] = {
1156
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
1157
  };
1158
1159
  // CoprocPair Register Class...
1160
  const MCPhysReg CoprocPair[] = {
1161
    SP::C0_C1, SP::C2_C3, SP::C4_C5, SP::C6_C7, SP::C8_C9, SP::C10_C11, SP::C12_C13, SP::C14_C15, SP::C16_C17, SP::C18_C19, SP::C20_C21, SP::C22_C23, SP::C24_C25, SP::C26_C27, SP::C28_C29, SP::C30_C31, 
1162
  };
1163
1164
  // CoprocPair Bit set.
1165
  const uint8_t CoprocPairBits[] = {
1166
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, 
1167
  };
1168
1169
  // IntPair Register Class...
1170
  const MCPhysReg IntPair[] = {
1171
    SP::I0_I1, SP::I2_I3, SP::I4_I5, SP::I6_I7, SP::G0_G1, SP::G2_G3, SP::G4_G5, SP::G6_G7, SP::L0_L1, SP::L2_L3, SP::L4_L5, SP::L6_L7, SP::O0_O1, SP::O2_O3, SP::O4_O5, SP::O6_O7, 
1172
  };
1173
1174
  // IntPair Bit set.
1175
  const uint8_t IntPairBits[] = {
1176
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, 
1177
  };
1178
1179
  // LowDFPRegs Register Class...
1180
  const MCPhysReg LowDFPRegs[] = {
1181
    SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15, 
1182
  };
1183
1184
  // LowDFPRegs Bit set.
1185
  const uint8_t LowDFPRegsBits[] = {
1186
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 
1187
  };
1188
1189
  // PRRegs Register Class...
1190
  const MCPhysReg PRRegs[] = {
1191
    SP::TPC, SP::TNPC, SP::TSTATE, SP::TT, SP::TICK, SP::TBA, SP::PSTATE, SP::TL, SP::PIL, SP::CWP, SP::CANSAVE, SP::CANRESTORE, SP::CLEANWIN, SP::OTHERWIN, SP::WSTATE, 
1192
  };
1193
1194
  // PRRegs Bit set.
1195
  const uint8_t PRRegsBits[] = {
1196
    0x4e, 0x6c, 0xbf, 
1197
  };
1198
1199
  // QFPRegs Register Class...
1200
  const MCPhysReg QFPRegs[] = {
1201
    SP::Q0, SP::Q1, SP::Q2, SP::Q3, SP::Q4, SP::Q5, SP::Q6, SP::Q7, SP::Q8, SP::Q9, SP::Q10, SP::Q11, SP::Q12, SP::Q13, SP::Q14, SP::Q15, 
1202
  };
1203
1204
  // QFPRegs Bit set.
1205
  const uint8_t QFPRegsBits[] = {
1206
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, 
1207
  };
1208
1209
  // LowQFPRegs Register Class...
1210
  const MCPhysReg LowQFPRegs[] = {
1211
    SP::Q0, SP::Q1, SP::Q2, SP::Q3, SP::Q4, SP::Q5, SP::Q6, SP::Q7, 
1212
  };
1213
1214
  // LowQFPRegs Bit set.
1215
  const uint8_t LowQFPRegsBits[] = {
1216
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, 
1217
  };
1218
1219
} // end anonymous namespace
1220
1221
extern const char SparcRegClassStrings[] = {
1222
  /* 0 */ 'C', 'o', 'p', 'r', 'o', 'c', 'P', 'a', 'i', 'r', 0,
1223
  /* 11 */ 'I', 'n', 't', 'P', 'a', 'i', 'r', 0,
1224
  /* 19 */ 'I', '6', '4', 'R', 'e', 'g', 's', 0,
1225
  /* 27 */ 'F', 'C', 'C', 'R', 'e', 'g', 's', 0,
1226
  /* 35 */ 'L', 'o', 'w', 'D', 'F', 'P', 'R', 'e', 'g', 's', 0,
1227
  /* 46 */ 'L', 'o', 'w', 'Q', 'F', 'P', 'R', 'e', 'g', 's', 0,
1228
  /* 57 */ 'P', 'R', 'R', 'e', 'g', 's', 0,
1229
  /* 64 */ 'A', 'S', 'R', 'R', 'e', 'g', 's', 0,
1230
  /* 72 */ 'C', 'o', 'p', 'r', 'o', 'c', 'R', 'e', 'g', 's', 0,
1231
  /* 83 */ 'I', 'n', 't', 'R', 'e', 'g', 's', 0,
1232
};
1233
1234
extern const MCRegisterClass SparcMCRegisterClasses[] = {
1235
  { FCCRegs, FCCRegsBits, 27, 4, sizeof(FCCRegsBits), SP::FCCRegsRegClassID, 0, 1, true },
1236
  { ASRRegs, ASRRegsBits, 64, 32, sizeof(ASRRegsBits), SP::ASRRegsRegClassID, 4, 1, false },
1237
  { CoprocRegs, CoprocRegsBits, 72, 32, sizeof(CoprocRegsBits), SP::CoprocRegsRegClassID, 4, 1, false },
1238
  { FPRegs, FPRegsBits, 39, 32, sizeof(FPRegsBits), SP::FPRegsRegClassID, 4, 1, true },
1239
  { IntRegs, IntRegsBits, 83, 32, sizeof(IntRegsBits), SP::IntRegsRegClassID, 4, 1, true },
1240
  { DFPRegs, DFPRegsBits, 38, 32, sizeof(DFPRegsBits), SP::DFPRegsRegClassID, 8, 1, true },
1241
  { I64Regs, I64RegsBits, 19, 32, sizeof(I64RegsBits), SP::I64RegsRegClassID, 8, 1, true },
1242
  { CoprocPair, CoprocPairBits, 0, 16, sizeof(CoprocPairBits), SP::CoprocPairRegClassID, 8, 1, false },
1243
  { IntPair, IntPairBits, 11, 16, sizeof(IntPairBits), SP::IntPairRegClassID, 8, 1, true },
1244
  { LowDFPRegs, LowDFPRegsBits, 35, 16, sizeof(LowDFPRegsBits), SP::LowDFPRegsRegClassID, 8, 1, true },
1245
  { PRRegs, PRRegsBits, 57, 15, sizeof(PRRegsBits), SP::PRRegsRegClassID, 8, 1, true },
1246
  { QFPRegs, QFPRegsBits, 49, 16, sizeof(QFPRegsBits), SP::QFPRegsRegClassID, 16, 1, true },
1247
  { LowQFPRegs, LowQFPRegsBits, 46, 8, sizeof(LowQFPRegsBits), SP::LowQFPRegsRegClassID, 16, 1, true },
1248
};
1249
1250
// SP Dwarf<->LLVM register mappings.
1251
extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0Dwarf2L[] = {
1252
  { 0U, SP::G0 },
1253
  { 1U, SP::G1 },
1254
  { 2U, SP::G2 },
1255
  { 3U, SP::G3 },
1256
  { 4U, SP::G4 },
1257
  { 5U, SP::G5 },
1258
  { 6U, SP::G6 },
1259
  { 7U, SP::G7 },
1260
  { 8U, SP::O0 },
1261
  { 9U, SP::O1 },
1262
  { 10U, SP::O2 },
1263
  { 11U, SP::O3 },
1264
  { 12U, SP::O4 },
1265
  { 13U, SP::O5 },
1266
  { 14U, SP::O6 },
1267
  { 15U, SP::O7 },
1268
  { 16U, SP::L0 },
1269
  { 17U, SP::L1 },
1270
  { 18U, SP::L2 },
1271
  { 19U, SP::L3 },
1272
  { 20U, SP::L4 },
1273
  { 21U, SP::L5 },
1274
  { 22U, SP::L6 },
1275
  { 23U, SP::L7 },
1276
  { 24U, SP::I0 },
1277
  { 25U, SP::I1 },
1278
  { 26U, SP::I2 },
1279
  { 27U, SP::I3 },
1280
  { 28U, SP::I4 },
1281
  { 29U, SP::I5 },
1282
  { 30U, SP::I6 },
1283
  { 31U, SP::I7 },
1284
  { 32U, SP::F0 },
1285
  { 33U, SP::F1 },
1286
  { 34U, SP::F2 },
1287
  { 35U, SP::F3 },
1288
  { 36U, SP::F4 },
1289
  { 37U, SP::F5 },
1290
  { 38U, SP::F6 },
1291
  { 39U, SP::F7 },
1292
  { 40U, SP::F8 },
1293
  { 41U, SP::F9 },
1294
  { 42U, SP::F10 },
1295
  { 43U, SP::F11 },
1296
  { 44U, SP::F12 },
1297
  { 45U, SP::F13 },
1298
  { 46U, SP::F14 },
1299
  { 47U, SP::F15 },
1300
  { 48U, SP::F16 },
1301
  { 49U, SP::F17 },
1302
  { 50U, SP::F18 },
1303
  { 51U, SP::F19 },
1304
  { 52U, SP::F20 },
1305
  { 53U, SP::F21 },
1306
  { 54U, SP::F22 },
1307
  { 55U, SP::F23 },
1308
  { 56U, SP::F24 },
1309
  { 57U, SP::F25 },
1310
  { 58U, SP::F26 },
1311
  { 59U, SP::F27 },
1312
  { 60U, SP::F28 },
1313
  { 61U, SP::F29 },
1314
  { 62U, SP::F30 },
1315
  { 63U, SP::F31 },
1316
  { 64U, SP::Y },
1317
  { 72U, SP::D0 },
1318
  { 73U, SP::D1 },
1319
  { 74U, SP::D2 },
1320
  { 75U, SP::D3 },
1321
  { 76U, SP::D4 },
1322
  { 77U, SP::D5 },
1323
  { 78U, SP::D6 },
1324
  { 79U, SP::D7 },
1325
  { 80U, SP::D8 },
1326
  { 81U, SP::D9 },
1327
  { 82U, SP::D10 },
1328
  { 83U, SP::D11 },
1329
  { 84U, SP::D12 },
1330
  { 85U, SP::D13 },
1331
  { 86U, SP::D14 },
1332
  { 87U, SP::D15 },
1333
};
1334
extern const unsigned SPDwarfFlavour0Dwarf2LSize = array_lengthof(SPDwarfFlavour0Dwarf2L);
1335
1336
extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0Dwarf2L[] = {
1337
  { 0U, SP::G0 },
1338
  { 1U, SP::G1 },
1339
  { 2U, SP::G2 },
1340
  { 3U, SP::G3 },
1341
  { 4U, SP::G4 },
1342
  { 5U, SP::G5 },
1343
  { 6U, SP::G6 },
1344
  { 7U, SP::G7 },
1345
  { 8U, SP::O0 },
1346
  { 9U, SP::O1 },
1347
  { 10U, SP::O2 },
1348
  { 11U, SP::O3 },
1349
  { 12U, SP::O4 },
1350
  { 13U, SP::O5 },
1351
  { 14U, SP::O6 },
1352
  { 15U, SP::O7 },
1353
  { 16U, SP::L0 },
1354
  { 17U, SP::L1 },
1355
  { 18U, SP::L2 },
1356
  { 19U, SP::L3 },
1357
  { 20U, SP::L4 },
1358
  { 21U, SP::L5 },
1359
  { 22U, SP::L6 },
1360
  { 23U, SP::L7 },
1361
  { 24U, SP::I0 },
1362
  { 25U, SP::I1 },
1363
  { 26U, SP::I2 },
1364
  { 27U, SP::I3 },
1365
  { 28U, SP::I4 },
1366
  { 29U, SP::I5 },
1367
  { 30U, SP::I6 },
1368
  { 31U, SP::I7 },
1369
  { 32U, SP::F0 },
1370
  { 33U, SP::F1 },
1371
  { 34U, SP::F2 },
1372
  { 35U, SP::F3 },
1373
  { 36U, SP::F4 },
1374
  { 37U, SP::F5 },
1375
  { 38U, SP::F6 },
1376
  { 39U, SP::F7 },
1377
  { 40U, SP::F8 },
1378
  { 41U, SP::F9 },
1379
  { 42U, SP::F10 },
1380
  { 43U, SP::F11 },
1381
  { 44U, SP::F12 },
1382
  { 45U, SP::F13 },
1383
  { 46U, SP::F14 },
1384
  { 47U, SP::F15 },
1385
  { 48U, SP::F16 },
1386
  { 49U, SP::F17 },
1387
  { 50U, SP::F18 },
1388
  { 51U, SP::F19 },
1389
  { 52U, SP::F20 },
1390
  { 53U, SP::F21 },
1391
  { 54U, SP::F22 },
1392
  { 55U, SP::F23 },
1393
  { 56U, SP::F24 },
1394
  { 57U, SP::F25 },
1395
  { 58U, SP::F26 },
1396
  { 59U, SP::F27 },
1397
  { 60U, SP::F28 },
1398
  { 61U, SP::F29 },
1399
  { 62U, SP::F30 },
1400
  { 63U, SP::F31 },
1401
  { 64U, SP::Y },
1402
  { 72U, SP::D0 },
1403
  { 73U, SP::D1 },
1404
  { 74U, SP::D2 },
1405
  { 75U, SP::D3 },
1406
  { 76U, SP::D4 },
1407
  { 77U, SP::D5 },
1408
  { 78U, SP::D6 },
1409
  { 79U, SP::D7 },
1410
  { 80U, SP::D8 },
1411
  { 81U, SP::D9 },
1412
  { 82U, SP::D10 },
1413
  { 83U, SP::D11 },
1414
  { 84U, SP::D12 },
1415
  { 85U, SP::D13 },
1416
  { 86U, SP::D14 },
1417
  { 87U, SP::D15 },
1418
};
1419
extern const unsigned SPEHFlavour0Dwarf2LSize = array_lengthof(SPEHFlavour0Dwarf2L);
1420
1421
extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0L2Dwarf[] = {
1422
  { SP::Y, 64U },
1423
  { SP::D0, 72U },
1424
  { SP::D1, 73U },
1425
  { SP::D2, 74U },
1426
  { SP::D3, 75U },
1427
  { SP::D4, 76U },
1428
  { SP::D5, 77U },
1429
  { SP::D6, 78U },
1430
  { SP::D7, 79U },
1431
  { SP::D8, 80U },
1432
  { SP::D9, 81U },
1433
  { SP::D10, 82U },
1434
  { SP::D11, 83U },
1435
  { SP::D12, 84U },
1436
  { SP::D13, 85U },
1437
  { SP::D14, 86U },
1438
  { SP::D15, 87U },
1439
  { SP::F0, 32U },
1440
  { SP::F1, 33U },
1441
  { SP::F2, 34U },
1442
  { SP::F3, 35U },
1443
  { SP::F4, 36U },
1444
  { SP::F5, 37U },
1445
  { SP::F6, 38U },
1446
  { SP::F7, 39U },
1447
  { SP::F8, 40U },
1448
  { SP::F9, 41U },
1449
  { SP::F10, 42U },
1450
  { SP::F11, 43U },
1451
  { SP::F12, 44U },
1452
  { SP::F13, 45U },
1453
  { SP::F14, 46U },
1454
  { SP::F15, 47U },
1455
  { SP::F16, 48U },
1456
  { SP::F17, 49U },
1457
  { SP::F18, 50U },
1458
  { SP::F19, 51U },
1459
  { SP::F20, 52U },
1460
  { SP::F21, 53U },
1461
  { SP::F22, 54U },
1462
  { SP::F23, 55U },
1463
  { SP::F24, 56U },
1464
  { SP::F25, 57U },
1465
  { SP::F26, 58U },
1466
  { SP::F27, 59U },
1467
  { SP::F28, 60U },
1468
  { SP::F29, 61U },
1469
  { SP::F30, 62U },
1470
  { SP::F31, 63U },
1471
  { SP::G0, 0U },
1472
  { SP::G1, 1U },
1473
  { SP::G2, 2U },
1474
  { SP::G3, 3U },
1475
  { SP::G4, 4U },
1476
  { SP::G5, 5U },
1477
  { SP::G6, 6U },
1478
  { SP::G7, 7U },
1479
  { SP::I0, 24U },
1480
  { SP::I1, 25U },
1481
  { SP::I2, 26U },
1482
  { SP::I3, 27U },
1483
  { SP::I4, 28U },
1484
  { SP::I5, 29U },
1485
  { SP::I6, 30U },
1486
  { SP::I7, 31U },
1487
  { SP::L0, 16U },
1488
  { SP::L1, 17U },
1489
  { SP::L2, 18U },
1490
  { SP::L3, 19U },
1491
  { SP::L4, 20U },
1492
  { SP::L5, 21U },
1493
  { SP::L6, 22U },
1494
  { SP::L7, 23U },
1495
  { SP::O0, 8U },
1496
  { SP::O1, 9U },
1497
  { SP::O2, 10U },
1498
  { SP::O3, 11U },
1499
  { SP::O4, 12U },
1500
  { SP::O5, 13U },
1501
  { SP::O6, 14U },
1502
  { SP::O7, 15U },
1503
};
1504
extern const unsigned SPDwarfFlavour0L2DwarfSize = array_lengthof(SPDwarfFlavour0L2Dwarf);
1505
1506
extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0L2Dwarf[] = {
1507
  { SP::Y, 64U },
1508
  { SP::D0, 72U },
1509
  { SP::D1, 73U },
1510
  { SP::D2, 74U },
1511
  { SP::D3, 75U },
1512
  { SP::D4, 76U },
1513
  { SP::D5, 77U },
1514
  { SP::D6, 78U },
1515
  { SP::D7, 79U },
1516
  { SP::D8, 80U },
1517
  { SP::D9, 81U },
1518
  { SP::D10, 82U },
1519
  { SP::D11, 83U },
1520
  { SP::D12, 84U },
1521
  { SP::D13, 85U },
1522
  { SP::D14, 86U },
1523
  { SP::D15, 87U },
1524
  { SP::F0, 32U },
1525
  { SP::F1, 33U },
1526
  { SP::F2, 34U },
1527
  { SP::F3, 35U },
1528
  { SP::F4, 36U },
1529
  { SP::F5, 37U },
1530
  { SP::F6, 38U },
1531
  { SP::F7, 39U },
1532
  { SP::F8, 40U },
1533
  { SP::F9, 41U },
1534
  { SP::F10, 42U },
1535
  { SP::F11, 43U },
1536
  { SP::F12, 44U },
1537
  { SP::F13, 45U },
1538
  { SP::F14, 46U },
1539
  { SP::F15, 47U },
1540
  { SP::F16, 48U },
1541
  { SP::F17, 49U },
1542
  { SP::F18, 50U },
1543
  { SP::F19, 51U },
1544
  { SP::F20, 52U },
1545
  { SP::F21, 53U },
1546
  { SP::F22, 54U },
1547
  { SP::F23, 55U },
1548
  { SP::F24, 56U },
1549
  { SP::F25, 57U },
1550
  { SP::F26, 58U },
1551
  { SP::F27, 59U },
1552
  { SP::F28, 60U },
1553
  { SP::F29, 61U },
1554
  { SP::F30, 62U },
1555
  { SP::F31, 63U },
1556
  { SP::G0, 0U },
1557
  { SP::G1, 1U },
1558
  { SP::G2, 2U },
1559
  { SP::G3, 3U },
1560
  { SP::G4, 4U },
1561
  { SP::G5, 5U },
1562
  { SP::G6, 6U },
1563
  { SP::G7, 7U },
1564
  { SP::I0, 24U },
1565
  { SP::I1, 25U },
1566
  { SP::I2, 26U },
1567
  { SP::I3, 27U },
1568
  { SP::I4, 28U },
1569
  { SP::I5, 29U },
1570
  { SP::I6, 30U },
1571
  { SP::I7, 31U },
1572
  { SP::L0, 16U },
1573
  { SP::L1, 17U },
1574
  { SP::L2, 18U },
1575
  { SP::L3, 19U },
1576
  { SP::L4, 20U },
1577
  { SP::L5, 21U },
1578
  { SP::L6, 22U },
1579
  { SP::L7, 23U },
1580
  { SP::O0, 8U },
1581
  { SP::O1, 9U },
1582
  { SP::O2, 10U },
1583
  { SP::O3, 11U },
1584
  { SP::O4, 12U },
1585
  { SP::O5, 13U },
1586
  { SP::O6, 14U },
1587
  { SP::O7, 15U },
1588
};
1589
extern const unsigned SPEHFlavour0L2DwarfSize = array_lengthof(SPEHFlavour0L2Dwarf);
1590
1591
extern const uint16_t SparcRegEncodingTable[] = {
1592
  0,
1593
  11,
1594
  10,
1595
  12,
1596
  0,
1597
  0,
1598
  9,
1599
  0,
1600
  0,
1601
  0,
1602
  13,
1603
  8,
1604
  0,
1605
  6,
1606
  5,
1607
  0,
1608
  4,
1609
  7,
1610
  1,
1611
  0,
1612
  2,
1613
  3,
1614
  0,
1615
  14,
1616
  0,
1617
  1,
1618
  2,
1619
  3,
1620
  4,
1621
  5,
1622
  6,
1623
  7,
1624
  8,
1625
  9,
1626
  10,
1627
  11,
1628
  12,
1629
  13,
1630
  14,
1631
  15,
1632
  16,
1633
  17,
1634
  18,
1635
  19,
1636
  20,
1637
  21,
1638
  22,
1639
  23,
1640
  24,
1641
  25,
1642
  26,
1643
  27,
1644
  28,
1645
  29,
1646
  30,
1647
  31,
1648
  0,
1649
  1,
1650
  2,
1651
  3,
1652
  4,
1653
  5,
1654
  6,
1655
  7,
1656
  8,
1657
  9,
1658
  10,
1659
  11,
1660
  12,
1661
  13,
1662
  14,
1663
  15,
1664
  16,
1665
  17,
1666
  18,
1667
  19,
1668
  20,
1669
  21,
1670
  22,
1671
  23,
1672
  24,
1673
  25,
1674
  26,
1675
  27,
1676
  28,
1677
  29,
1678
  30,
1679
  31,
1680
  0,
1681
  2,
1682
  4,
1683
  6,
1684
  8,
1685
  10,
1686
  12,
1687
  14,
1688
  16,
1689
  18,
1690
  20,
1691
  22,
1692
  24,
1693
  26,
1694
  28,
1695
  30,
1696
  1,
1697
  3,
1698
  5,
1699
  7,
1700
  9,
1701
  11,
1702
  13,
1703
  15,
1704
  17,
1705
  19,
1706
  21,
1707
  23,
1708
  25,
1709
  27,
1710
  29,
1711
  31,
1712
  0,
1713
  1,
1714
  2,
1715
  3,
1716
  4,
1717
  5,
1718
  6,
1719
  7,
1720
  8,
1721
  9,
1722
  10,
1723
  11,
1724
  12,
1725
  13,
1726
  14,
1727
  15,
1728
  16,
1729
  17,
1730
  18,
1731
  19,
1732
  20,
1733
  21,
1734
  22,
1735
  23,
1736
  24,
1737
  25,
1738
  26,
1739
  27,
1740
  28,
1741
  29,
1742
  30,
1743
  31,
1744
  0,
1745
  1,
1746
  2,
1747
  3,
1748
  0,
1749
  1,
1750
  2,
1751
  3,
1752
  4,
1753
  5,
1754
  6,
1755
  7,
1756
  24,
1757
  25,
1758
  26,
1759
  27,
1760
  28,
1761
  29,
1762
  30,
1763
  31,
1764
  16,
1765
  17,
1766
  18,
1767
  19,
1768
  20,
1769
  21,
1770
  22,
1771
  23,
1772
  8,
1773
  9,
1774
  10,
1775
  11,
1776
  12,
1777
  13,
1778
  14,
1779
  15,
1780
  0,
1781
  4,
1782
  8,
1783
  12,
1784
  16,
1785
  20,
1786
  24,
1787
  28,
1788
  1,
1789
  5,
1790
  9,
1791
  13,
1792
  17,
1793
  21,
1794
  25,
1795
  29,
1796
  0,
1797
  2,
1798
  4,
1799
  6,
1800
  8,
1801
  10,
1802
  12,
1803
  14,
1804
  16,
1805
  18,
1806
  20,
1807
  22,
1808
  24,
1809
  26,
1810
  28,
1811
  30,
1812
  0,
1813
  2,
1814
  4,
1815
  6,
1816
  24,
1817
  26,
1818
  28,
1819
  30,
1820
  16,
1821
  18,
1822
  20,
1823
  22,
1824
  8,
1825
  10,
1826
  12,
1827
  14,
1828
};
1829
294
static inline void InitSparcMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
1830
294
  RI->InitMCRegisterInfo(SparcRegDesc, 236, RA, PC, SparcMCRegisterClasses, 13, SparcRegUnitRoots, 171, SparcRegDiffLists, SparcLaneMaskLists, SparcRegStrings, SparcRegClassStrings, SparcSubRegIdxLists, 7,
1831
294
SparcSubRegIdxRanges, SparcRegEncodingTable);
1832
294
1833
294
  switch (DwarfFlavour) {
1834
294
  default:
1835
0
    llvm_unreachable("Unknown DWARF flavour");
1836
294
  case 0:
1837
294
    RI->mapDwarfRegsToLLVMRegs(SPDwarfFlavour0Dwarf2L, SPDwarfFlavour0Dwarf2LSize, false);
1838
294
    break;
1839
294
  }
1840
294
  switch (EHFlavour) {
1841
294
  default:
1842
0
    llvm_unreachable("Unknown DWARF flavour");
1843
294
  case 0:
1844
294
    RI->mapDwarfRegsToLLVMRegs(SPEHFlavour0Dwarf2L, SPEHFlavour0Dwarf2LSize, true);
1845
294
    break;
1846
294
  }
1847
294
  switch (DwarfFlavour) {
1848
294
  default:
1849
0
    llvm_unreachable("Unknown DWARF flavour");
1850
294
  case 0:
1851
294
    RI->mapLLVMRegsToDwarfRegs(SPDwarfFlavour0L2Dwarf, SPDwarfFlavour0L2DwarfSize, false);
1852
294
    break;
1853
294
  }
1854
294
  switch (EHFlavour) {
1855
294
  default:
1856
0
    llvm_unreachable("Unknown DWARF flavour");
1857
294
  case 0:
1858
294
    RI->mapLLVMRegsToDwarfRegs(SPEHFlavour0L2Dwarf, SPEHFlavour0L2DwarfSize, true);
1859
294
    break;
1860
294
  }
1861
294
}
1862
1863
} // end namespace llvm
1864
1865
#endif // GET_REGINFO_MC_DESC
1866
1867
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
1868
|*                                                                            *|
1869
|* Register Information Header Fragment                                       *|
1870
|*                                                                            *|
1871
|* Automatically generated file, do not edit!                                 *|
1872
|*                                                                            *|
1873
\*===----------------------------------------------------------------------===*/
1874
1875
1876
#ifdef GET_REGINFO_HEADER
1877
#undef GET_REGINFO_HEADER
1878
1879
#include "llvm/CodeGen/TargetRegisterInfo.h"
1880
1881
namespace llvm {
1882
1883
class SparcFrameLowering;
1884
1885
struct SparcGenRegisterInfo : public TargetRegisterInfo {
1886
  explicit SparcGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
1887
      unsigned PC = 0, unsigned HwMode = 0);
1888
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
1889
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
1890
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
1891
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
1892
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
1893
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
1894
  unsigned getNumRegPressureSets() const override;
1895
  const char *getRegPressureSetName(unsigned Idx) const override;
1896
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
1897
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
1898
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
1899
  ArrayRef<const char *> getRegMaskNames() const override;
1900
  ArrayRef<const uint32_t *> getRegMasks() const override;
1901
  /// Devirtualized TargetFrameLowering.
1902
  static const SparcFrameLowering *getFrameLowering(
1903
      const MachineFunction &MF);
1904
};
1905
1906
namespace SP { // Register classes
1907
  extern const TargetRegisterClass FCCRegsRegClass;
1908
  extern const TargetRegisterClass ASRRegsRegClass;
1909
  extern const TargetRegisterClass CoprocRegsRegClass;
1910
  extern const TargetRegisterClass FPRegsRegClass;
1911
  extern const TargetRegisterClass IntRegsRegClass;
1912
  extern const TargetRegisterClass DFPRegsRegClass;
1913
  extern const TargetRegisterClass I64RegsRegClass;
1914
  extern const TargetRegisterClass CoprocPairRegClass;
1915
  extern const TargetRegisterClass IntPairRegClass;
1916
  extern const TargetRegisterClass LowDFPRegsRegClass;
1917
  extern const TargetRegisterClass PRRegsRegClass;
1918
  extern const TargetRegisterClass QFPRegsRegClass;
1919
  extern const TargetRegisterClass LowQFPRegsRegClass;
1920
} // end namespace SP
1921
1922
} // end namespace llvm
1923
1924
#endif // GET_REGINFO_HEADER
1925
1926
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
1927
|*                                                                            *|
1928
|* Target Register and Register Classes Information                           *|
1929
|*                                                                            *|
1930
|* Automatically generated file, do not edit!                                 *|
1931
|*                                                                            *|
1932
\*===----------------------------------------------------------------------===*/
1933
1934
1935
#ifdef GET_REGINFO_TARGET_DESC
1936
#undef GET_REGINFO_TARGET_DESC
1937
1938
namespace llvm {
1939
1940
extern const MCRegisterClass SparcMCRegisterClasses[];
1941
1942
static const MVT::SimpleValueType VTLists[] = {
1943
  /* 0 */ MVT::i1, MVT::Other,
1944
  /* 2 */ MVT::i32, MVT::Other,
1945
  /* 4 */ MVT::i32, MVT::i64, MVT::Other,
1946
  /* 7 */ MVT::f32, MVT::Other,
1947
  /* 9 */ MVT::f64, MVT::Other,
1948
  /* 11 */ MVT::f128, MVT::Other,
1949
  /* 13 */ MVT::v2i32, MVT::Other,
1950
};
1951
1952
static const char *const SubRegIndexNameTable[] = { "sub_even", "sub_even64", "sub_odd", "sub_odd64", "sub_odd64_then_sub_even", "sub_odd64_then_sub_odd", "" };
1953
1954
1955
static const LaneBitmask SubRegIndexLaneMaskTable[] = {
1956
  LaneBitmask::getAll(),
1957
  LaneBitmask(0x00000001), // sub_even
1958
  LaneBitmask(0x00000003), // sub_even64
1959
  LaneBitmask(0x00000002), // sub_odd
1960
  LaneBitmask(0x0000000C), // sub_odd64
1961
  LaneBitmask(0x00000004), // sub_odd64_then_sub_even
1962
  LaneBitmask(0x00000008), // sub_odd64_then_sub_odd
1963
 };
1964
1965
1966
1967
static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
1968
  // Mode = 0 (Default)
1969
  { 1, 1, 1, VTLists+0 },    // FCCRegs
1970
  { 32, 32, 32, VTLists+2 },    // ASRRegs
1971
  { 32, 32, 32, VTLists+2 },    // CoprocRegs
1972
  { 32, 32, 32, VTLists+7 },    // FPRegs
1973
  { 32, 32, 32, VTLists+4 },    // IntRegs
1974
  { 64, 64, 64, VTLists+9 },    // DFPRegs
1975
  { 64, 64, 64, VTLists+5 },    // I64Regs
1976
  { 64, 64, 64, VTLists+13 },    // CoprocPair
1977
  { 64, 64, 64, VTLists+13 },    // IntPair
1978
  { 64, 64, 64, VTLists+9 },    // LowDFPRegs
1979
  { 64, 64, 64, VTLists+5 },    // PRRegs
1980
  { 128, 128, 128, VTLists+11 },    // QFPRegs
1981
  { 128, 128, 128, VTLists+11 },    // LowQFPRegs
1982
};
1983
1984
static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
1985
1986
static const uint32_t FCCRegsSubClassMask[] = {
1987
  0x00000001, 
1988
};
1989
1990
static const uint32_t ASRRegsSubClassMask[] = {
1991
  0x00000002, 
1992
};
1993
1994
static const uint32_t CoprocRegsSubClassMask[] = {
1995
  0x00000004, 
1996
  0x00000080, // sub_even
1997
  0x00000080, // sub_odd
1998
};
1999
2000
static const uint32_t FPRegsSubClassMask[] = {
2001
  0x00000008, 
2002
  0x00001200, // sub_even
2003
  0x00001200, // sub_odd
2004
  0x00001000, // sub_odd64_then_sub_even
2005
  0x00001000, // sub_odd64_then_sub_odd
2006
};
2007
2008
static const uint32_t IntRegsSubClassMask[] = {
2009
  0x00000050, 
2010
  0x00000100, // sub_even
2011
  0x00000100, // sub_odd
2012
};
2013
2014
static const uint32_t DFPRegsSubClassMask[] = {
2015
  0x00000220, 
2016
  0x00001800, // sub_even64
2017
  0x00001800, // sub_odd64
2018
};
2019
2020
static const uint32_t I64RegsSubClassMask[] = {
2021
  0x00000040, 
2022
  0x00000100, // sub_even
2023
  0x00000100, // sub_odd
2024
};
2025
2026
static const uint32_t CoprocPairSubClassMask[] = {
2027
  0x00000080, 
2028
};
2029
2030
static const uint32_t IntPairSubClassMask[] = {
2031
  0x00000100, 
2032
};
2033
2034
static const uint32_t LowDFPRegsSubClassMask[] = {
2035
  0x00000200, 
2036
  0x00001000, // sub_even64
2037
  0x00001000, // sub_odd64
2038
};
2039
2040
static const uint32_t PRRegsSubClassMask[] = {
2041
  0x00000400, 
2042
};
2043
2044
static const uint32_t QFPRegsSubClassMask[] = {
2045
  0x00001800, 
2046
};
2047
2048
static const uint32_t LowQFPRegsSubClassMask[] = {
2049
  0x00001000, 
2050
};
2051
2052
static const uint16_t SuperRegIdxSeqs[] = {
2053
  /* 0 */ 1, 3, 0,
2054
  /* 3 */ 2, 4, 0,
2055
  /* 6 */ 1, 3, 5, 6, 0,
2056
};
2057
2058
static const TargetRegisterClass *const I64RegsSuperclasses[] = {
2059
  &SP::IntRegsRegClass,
2060
  nullptr
2061
};
2062
2063
static const TargetRegisterClass *const LowDFPRegsSuperclasses[] = {
2064
  &SP::DFPRegsRegClass,
2065
  nullptr
2066
};
2067
2068
static const TargetRegisterClass *const LowQFPRegsSuperclasses[] = {
2069
  &SP::QFPRegsRegClass,
2070
  nullptr
2071
};
2072
2073
2074
namespace SP {   // Register class instances
2075
  extern const TargetRegisterClass FCCRegsRegClass = {
2076
    &SparcMCRegisterClasses[FCCRegsRegClassID],
2077
    FCCRegsSubClassMask,
2078
    SuperRegIdxSeqs + 2,
2079
    LaneBitmask(0x00000001),
2080
    0,
2081
    false, /* HasDisjunctSubRegs */
2082
    false, /* CoveredBySubRegs */
2083
    NullRegClasses,
2084
    nullptr
2085
  };
2086
2087
  extern const TargetRegisterClass ASRRegsRegClass = {
2088
    &SparcMCRegisterClasses[ASRRegsRegClassID],
2089
    ASRRegsSubClassMask,
2090
    SuperRegIdxSeqs + 2,
2091
    LaneBitmask(0x00000001),
2092
    0,
2093
    false, /* HasDisjunctSubRegs */
2094
    false, /* CoveredBySubRegs */
2095
    NullRegClasses,
2096
    nullptr
2097
  };
2098
2099
  extern const TargetRegisterClass CoprocRegsRegClass = {
2100
    &SparcMCRegisterClasses[CoprocRegsRegClassID],
2101
    CoprocRegsSubClassMask,
2102
    SuperRegIdxSeqs + 0,
2103
    LaneBitmask(0x00000001),
2104
    0,
2105
    false, /* HasDisjunctSubRegs */
2106
    false, /* CoveredBySubRegs */
2107
    NullRegClasses,
2108
    nullptr
2109
  };
2110
2111
  extern const TargetRegisterClass FPRegsRegClass = {
2112
    &SparcMCRegisterClasses[FPRegsRegClassID],
2113
    FPRegsSubClassMask,
2114
    SuperRegIdxSeqs + 6,
2115
    LaneBitmask(0x00000001),
2116
    0,
2117
    false, /* HasDisjunctSubRegs */
2118
    false, /* CoveredBySubRegs */
2119
    NullRegClasses,
2120
    nullptr
2121
  };
2122
2123
  extern const TargetRegisterClass IntRegsRegClass = {
2124
    &SparcMCRegisterClasses[IntRegsRegClassID],
2125
    IntRegsSubClassMask,
2126
    SuperRegIdxSeqs + 0,
2127
    LaneBitmask(0x00000001),
2128
    0,
2129
    false, /* HasDisjunctSubRegs */
2130
    false, /* CoveredBySubRegs */
2131
    NullRegClasses,
2132
    nullptr
2133
  };
2134
2135
  extern const TargetRegisterClass DFPRegsRegClass = {
2136
    &SparcMCRegisterClasses[DFPRegsRegClassID],
2137
    DFPRegsSubClassMask,
2138
    SuperRegIdxSeqs + 3,
2139
    LaneBitmask(0x00000003),
2140
    0,
2141
    true, /* HasDisjunctSubRegs */
2142
    false, /* CoveredBySubRegs */
2143
    NullRegClasses,
2144
    nullptr
2145
  };
2146
2147
  extern const TargetRegisterClass I64RegsRegClass = {
2148
    &SparcMCRegisterClasses[I64RegsRegClassID],
2149
    I64RegsSubClassMask,
2150
    SuperRegIdxSeqs + 0,
2151
    LaneBitmask(0x00000001),
2152
    0,
2153
    false, /* HasDisjunctSubRegs */
2154
    false, /* CoveredBySubRegs */
2155
    I64RegsSuperclasses,
2156
    nullptr
2157
  };
2158
2159
  extern const TargetRegisterClass CoprocPairRegClass = {
2160
    &SparcMCRegisterClasses[CoprocPairRegClassID],
2161
    CoprocPairSubClassMask,
2162
    SuperRegIdxSeqs + 2,
2163
    LaneBitmask(0x00000003),
2164
    0,
2165
    true, /* HasDisjunctSubRegs */
2166
    true, /* CoveredBySubRegs */
2167
    NullRegClasses,
2168
    nullptr
2169
  };
2170
2171
  extern const TargetRegisterClass IntPairRegClass = {
2172
    &SparcMCRegisterClasses[IntPairRegClassID],
2173
    IntPairSubClassMask,
2174
    SuperRegIdxSeqs + 2,
2175
    LaneBitmask(0x00000003),
2176
    0,
2177
    true, /* HasDisjunctSubRegs */
2178
    true, /* CoveredBySubRegs */
2179
    NullRegClasses,
2180
    nullptr
2181
  };
2182
2183
  extern const TargetRegisterClass LowDFPRegsRegClass = {
2184
    &SparcMCRegisterClasses[LowDFPRegsRegClassID],
2185
    LowDFPRegsSubClassMask,
2186
    SuperRegIdxSeqs + 3,
2187
    LaneBitmask(0x00000003),
2188
    0,
2189
    true, /* HasDisjunctSubRegs */
2190
    true, /* CoveredBySubRegs */
2191
    LowDFPRegsSuperclasses,
2192
    nullptr
2193
  };
2194
2195
  extern const TargetRegisterClass PRRegsRegClass = {
2196
    &SparcMCRegisterClasses[PRRegsRegClassID],
2197
    PRRegsSubClassMask,
2198
    SuperRegIdxSeqs + 2,
2199
    LaneBitmask(0x00000001),
2200
    0,
2201
    false, /* HasDisjunctSubRegs */
2202
    false, /* CoveredBySubRegs */
2203
    NullRegClasses,
2204
    nullptr
2205
  };
2206
2207
  extern const TargetRegisterClass QFPRegsRegClass = {
2208
    &SparcMCRegisterClasses[QFPRegsRegClassID],
2209
    QFPRegsSubClassMask,
2210
    SuperRegIdxSeqs + 2,
2211
    LaneBitmask(0x0000000F),
2212
    0,
2213
    true, /* HasDisjunctSubRegs */
2214
    true, /* CoveredBySubRegs */
2215
    NullRegClasses,
2216
    nullptr
2217
  };
2218
2219
  extern const TargetRegisterClass LowQFPRegsRegClass = {
2220
    &SparcMCRegisterClasses[LowQFPRegsRegClassID],
2221
    LowQFPRegsSubClassMask,
2222
    SuperRegIdxSeqs + 2,
2223
    LaneBitmask(0x0000000F),
2224
    0,
2225
    true, /* HasDisjunctSubRegs */
2226
    true, /* CoveredBySubRegs */
2227
    LowQFPRegsSuperclasses,
2228
    nullptr
2229
  };
2230
2231
} // end namespace SP
2232
2233
namespace {
2234
  const TargetRegisterClass* const RegisterClasses[] = {
2235
    &SP::FCCRegsRegClass,
2236
    &SP::ASRRegsRegClass,
2237
    &SP::CoprocRegsRegClass,
2238
    &SP::FPRegsRegClass,
2239
    &SP::IntRegsRegClass,
2240
    &SP::DFPRegsRegClass,
2241
    &SP::I64RegsRegClass,
2242
    &SP::CoprocPairRegClass,
2243
    &SP::IntPairRegClass,
2244
    &SP::LowDFPRegsRegClass,
2245
    &SP::PRRegsRegClass,
2246
    &SP::QFPRegsRegClass,
2247
    &SP::LowQFPRegsRegClass,
2248
  };
2249
} // end anonymous namespace
2250
2251
static const TargetRegisterInfoDesc SparcRegInfoDesc[] = { // Extra Descriptors
2252
  { 0, false },
2253
  { 0, true },
2254
  { 0, true },
2255
  { 0, true },
2256
  { 0, false },
2257
  { 0, false },
2258
  { 0, true },
2259
  { 0, false },
2260
  { 0, false },
2261
  { 0, false },
2262
  { 0, true },
2263
  { 0, true },
2264
  { 0, false },
2265
  { 0, true },
2266
  { 0, true },
2267
  { 0, false },
2268
  { 0, true },
2269
  { 0, true },
2270
  { 0, true },
2271
  { 0, true },
2272
  { 0, true },
2273
  { 0, true },
2274
  { 0, false },
2275
  { 0, true },
2276
  { 0, false },
2277
  { 0, false },
2278
  { 0, false },
2279
  { 0, false },
2280
  { 0, false },
2281
  { 0, false },
2282
  { 0, false },
2283
  { 0, false },
2284
  { 0, false },
2285
  { 0, false },
2286
  { 0, false },
2287
  { 0, false },
2288
  { 0, false },
2289
  { 0, false },
2290
  { 0, false },
2291
  { 0, false },
2292
  { 0, false },
2293
  { 0, false },
2294
  { 0, false },
2295
  { 0, false },
2296
  { 0, false },
2297
  { 0, false },
2298
  { 0, false },
2299
  { 0, false },
2300
  { 0, false },
2301
  { 0, false },
2302
  { 0, false },
2303
  { 0, false },
2304
  { 0, false },
2305
  { 0, false },
2306
  { 0, false },
2307
  { 0, false },
2308
  { 0, false },
2309
  { 0, false },
2310
  { 0, false },
2311
  { 0, false },
2312
  { 0, false },
2313
  { 0, false },
2314
  { 0, false },
2315
  { 0, false },
2316
  { 0, false },
2317
  { 0, false },
2318
  { 0, false },
2319
  { 0, false },
2320
  { 0, false },
2321
  { 0, false },
2322
  { 0, false },
2323
  { 0, false },
2324
  { 0, false },
2325
  { 0, false },
2326
  { 0, false },
2327
  { 0, false },
2328
  { 0, false },
2329
  { 0, false },
2330
  { 0, false },
2331
  { 0, false },
2332
  { 0, false },
2333
  { 0, false },
2334
  { 0, false },
2335
  { 0, false },
2336
  { 0, false },
2337
  { 0, false },
2338
  { 0, false },
2339
  { 0, false },
2340
  { 0, true },
2341
  { 0, true },
2342
  { 0, true },
2343
  { 0, true },
2344
  { 0, true },
2345
  { 0, true },
2346
  { 0, true },
2347
  { 0, true },
2348
  { 0, true },
2349
  { 0, true },
2350
  { 0, true },
2351
  { 0, true },
2352
  { 0, true },
2353
  { 0, true },
2354
  { 0, true },
2355
  { 0, true },
2356
  { 0, true },
2357
  { 0, true },
2358
  { 0, true },
2359
  { 0, true },
2360
  { 0, true },
2361
  { 0, true },
2362
  { 0, true },
2363
  { 0, true },
2364
  { 0, true },
2365
  { 0, true },
2366
  { 0, true },
2367
  { 0, true },
2368
  { 0, true },
2369
  { 0, true },
2370
  { 0, true },
2371
  { 0, true },
2372
  { 0, true },
2373
  { 0, true },
2374
  { 0, true },
2375
  { 0, true },
2376
  { 0, true },
2377
  { 0, true },
2378
  { 0, true },
2379
  { 0, true },
2380
  { 0, true },
2381
  { 0, true },
2382
  { 0, true },
2383
  { 0, true },
2384
  { 0, true },
2385
  { 0, true },
2386
  { 0, true },
2387
  { 0, true },
2388
  { 0, true },
2389
  { 0, true },
2390
  { 0, true },
2391
  { 0, true },
2392
  { 0, true },
2393
  { 0, true },
2394
  { 0, true },
2395
  { 0, true },
2396
  { 0, true },
2397
  { 0, true },
2398
  { 0, true },
2399
  { 0, true },
2400
  { 0, true },
2401
  { 0, true },
2402
  { 0, true },
2403
  { 0, true },
2404
  { 0, true },
2405
  { 0, true },
2406
  { 0, true },
2407
  { 0, true },
2408
  { 0, true },
2409
  { 0, true },
2410
  { 0, true },
2411
  { 0, true },
2412
  { 0, true },
2413
  { 0, true },
2414
  { 0, true },
2415
  { 0, true },
2416
  { 0, true },
2417
  { 0, true },
2418
  { 0, true },
2419
  { 0, true },
2420
  { 0, true },
2421
  { 0, true },
2422
  { 0, true },
2423
  { 0, true },
2424
  { 0, true },
2425
  { 0, true },
2426
  { 0, true },
2427
  { 0, true },
2428
  { 0, true },
2429
  { 0, true },
2430
  { 0, true },
2431
  { 0, true },
2432
  { 0, true },
2433
  { 0, true },
2434
  { 0, true },
2435
  { 0, true },
2436
  { 0, true },
2437
  { 0, true },
2438
  { 0, true },
2439
  { 0, true },
2440
  { 0, true },
2441
  { 0, true },
2442
  { 0, true },
2443
  { 0, true },
2444
  { 0, true },
2445
  { 0, true },
2446
  { 0, true },
2447
  { 0, true },
2448
  { 0, true },
2449
  { 0, true },
2450
  { 0, true },
2451
  { 0, true },
2452
  { 0, true },
2453
  { 0, true },
2454
  { 0, true },
2455
  { 0, true },
2456
  { 0, false },
2457
  { 0, false },
2458
  { 0, false },
2459
  { 0, false },
2460
  { 0, false },
2461
  { 0, false },
2462
  { 0, false },
2463
  { 0, false },
2464
  { 0, false },
2465
  { 0, false },
2466
  { 0, false },
2467
  { 0, false },
2468
  { 0, false },
2469
  { 0, false },
2470
  { 0, false },
2471
  { 0, false },
2472
  { 0, true },
2473
  { 0, true },
2474
  { 0, true },
2475
  { 0, true },
2476
  { 0, true },
2477
  { 0, true },
2478
  { 0, true },
2479
  { 0, true },
2480
  { 0, true },
2481
  { 0, true },
2482
  { 0, true },
2483
  { 0, true },
2484
  { 0, true },
2485
  { 0, true },
2486
  { 0, true },
2487
  { 0, true },
2488
};
2489
60
unsigned SparcGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
2490
60
  static const uint8_t RowMap[6] = {
2491
60
    0, 0, 0, 1, 0, 0, 
2492
60
  };
2493
60
  static const uint8_t Rows[2][6] = {
2494
60
    { 1, 0, 3, 0, 0, 0, },
2495
60
    { 5, 0, 6, 0, 0, 0, },
2496
60
  };
2497
60
2498
60
  --IdxA; assert(IdxA < 6);
2499
60
  --IdxB; assert(IdxB < 6);
2500
60
  return Rows[RowMap[IdxA]][IdxB];
2501
60
}
2502
2503
  struct MaskRolOp {
2504
    LaneBitmask Mask;
2505
    uint8_t  RotateLeft;
2506
  };
2507
  static const MaskRolOp LaneMaskComposeSequences[] = {
2508
    { LaneBitmask(0xFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
2509
    { LaneBitmask(0xFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 2
2510
    { LaneBitmask(0xFFFFFFFF),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 4
2511
    { LaneBitmask(0xFFFFFFFF),  3 }, { LaneBitmask::getNone(), 0 }  // Sequence 6
2512
  };
2513
  static const MaskRolOp *const CompositeSequences[] = {
2514
    &LaneMaskComposeSequences[0], // to sub_even
2515
    &LaneMaskComposeSequences[0], // to sub_even64
2516
    &LaneMaskComposeSequences[2], // to sub_odd
2517
    &LaneMaskComposeSequences[4], // to sub_odd64
2518
    &LaneMaskComposeSequences[4], // to sub_odd64_then_sub_even
2519
    &LaneMaskComposeSequences[6] // to sub_odd64_then_sub_odd
2520
  };
2521
2522
0
LaneBitmask SparcGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
2523
0
  --IdxA; assert(IdxA < 6 && "Subregister index out of bounds");
2524
0
  LaneBitmask Result;
2525
0
  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
2526
0
    LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
2527
0
    if (unsigned S = Ops->RotateLeft)
2528
0
      Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
2529
0
    else
2530
0
      Result |= LaneBitmask(M);
2531
0
  }
2532
0
  return Result;
2533
0
}
2534
2535
0
LaneBitmask SparcGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
2536
0
  LaneMask &= getSubRegIndexLaneMask(IdxA);
2537
0
  --IdxA; assert(IdxA < 6 && "Subregister index out of bounds");
2538
0
  LaneBitmask Result;
2539
0
  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
2540
0
    LaneBitmask::Type M = LaneMask.getAsInteger();
2541
0
    if (unsigned S = Ops->RotateLeft)
2542
0
      Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
2543
0
    else
2544
0
      Result |= LaneBitmask(M);
2545
0
  }
2546
0
  return Result;
2547
0
}
2548
2549
708
const TargetRegisterClass *SparcGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
2550
708
  static const uint8_t Table[13][6] = {
2551
708
    { // FCCRegs
2552
708
      0,  // sub_even
2553
708
      0,  // sub_even64
2554
708
      0,  // sub_odd
2555
708
      0,  // sub_odd64
2556
708
      0,  // sub_odd64_then_sub_even
2557
708
      0,  // sub_odd64_then_sub_odd
2558
708
    },
2559
708
    { // ASRRegs
2560
708
      0,  // sub_even
2561
708
      0,  // sub_even64
2562
708
      0,  // sub_odd
2563
708
      0,  // sub_odd64
2564
708
      0,  // sub_odd64_then_sub_even
2565
708
      0,  // sub_odd64_then_sub_odd
2566
708
    },
2567
708
    { // CoprocRegs
2568
708
      0,  // sub_even
2569
708
      0,  // sub_even64
2570
708
      0,  // sub_odd
2571
708
      0,  // sub_odd64
2572
708
      0,  // sub_odd64_then_sub_even
2573
708
      0,  // sub_odd64_then_sub_odd
2574
708
    },
2575
708
    { // FPRegs
2576
708
      0,  // sub_even
2577
708
      0,  // sub_even64
2578
708
      0,  // sub_odd
2579
708
      0,  // sub_odd64
2580
708
      0,  // sub_odd64_then_sub_even
2581
708
      0,  // sub_odd64_then_sub_odd
2582
708
    },
2583
708
    { // IntRegs
2584
708
      0,  // sub_even
2585
708
      0,  // sub_even64
2586
708
      0,  // sub_odd
2587
708
      0,  // sub_odd64
2588
708
      0,  // sub_odd64_then_sub_even
2589
708
      0,  // sub_odd64_then_sub_odd
2590
708
    },
2591
708
    { // DFPRegs
2592
708
      10, // sub_even -> LowDFPRegs
2593
708
      0,  // sub_even64
2594
708
      10, // sub_odd -> LowDFPRegs
2595
708
      0,  // sub_odd64
2596
708
      0,  // sub_odd64_then_sub_even
2597
708
      0,  // sub_odd64_then_sub_odd
2598
708
    },
2599
708
    { // I64Regs
2600
708
      0,  // sub_even
2601
708
      0,  // sub_even64
2602
708
      0,  // sub_odd
2603
708
      0,  // sub_odd64
2604
708
      0,  // sub_odd64_then_sub_even
2605
708
      0,  // sub_odd64_then_sub_odd
2606
708
    },
2607
708
    { // CoprocPair
2608
708
      8,  // sub_even -> CoprocPair
2609
708
      0,  // sub_even64
2610
708
      8,  // sub_odd -> CoprocPair
2611
708
      0,  // sub_odd64
2612
708
      0,  // sub_odd64_then_sub_even
2613
708
      0,  // sub_odd64_then_sub_odd
2614
708
    },
2615
708
    { // IntPair
2616
708
      9,  // sub_even -> IntPair
2617
708
      0,  // sub_even64
2618
708
      9,  // sub_odd -> IntPair
2619
708
      0,  // sub_odd64
2620
708
      0,  // sub_odd64_then_sub_even
2621
708
      0,  // sub_odd64_then_sub_odd
2622
708
    },
2623
708
    { // LowDFPRegs
2624
708
      10, // sub_even -> LowDFPRegs
2625
708
      0,  // sub_even64
2626
708
      10, // sub_odd -> LowDFPRegs
2627
708
      0,  // sub_odd64
2628
708
      0,  // sub_odd64_then_sub_even
2629
708
      0,  // sub_odd64_then_sub_odd
2630
708
    },
2631
708
    { // PRRegs
2632
708
      0,  // sub_even
2633
708
      0,  // sub_even64
2634
708
      0,  // sub_odd
2635
708
      0,  // sub_odd64
2636
708
      0,  // sub_odd64_then_sub_even
2637
708
      0,  // sub_odd64_then_sub_odd
2638
708
    },
2639
708
    { // QFPRegs
2640
708
      13, // sub_even -> LowQFPRegs
2641
708
      12, // sub_even64 -> QFPRegs
2642
708
      13, // sub_odd -> LowQFPRegs
2643
708
      12, // sub_odd64 -> QFPRegs
2644
708
      13, // sub_odd64_then_sub_even -> LowQFPRegs
2645
708
      13, // sub_odd64_then_sub_odd -> LowQFPRegs
2646
708
    },
2647
708
    { // LowQFPRegs
2648
708
      13, // sub_even -> LowQFPRegs
2649
708
      13, // sub_even64 -> LowQFPRegs
2650
708
      13, // sub_odd -> LowQFPRegs
2651
708
      13, // sub_odd64 -> LowQFPRegs
2652
708
      13, // sub_odd64_then_sub_even -> LowQFPRegs
2653
708
      13, // sub_odd64_then_sub_odd -> LowQFPRegs
2654
708
    },
2655
708
  };
2656
708
  assert(RC && "Missing regclass");
2657
708
  if (!Idx) 
return RC0
;
2658
708
  --Idx;
2659
708
  assert(Idx < 6 && "Bad subreg");
2660
708
  unsigned TV = Table[RC->getID()][Idx];
2661
708
  return TV ? getRegClass(TV - 1) : 
nullptr0
;
2662
708
}
2663
2664
/// Get the weight in units of pressure for this register class.
2665
const RegClassWeight &SparcGenRegisterInfo::
2666
14.3k
getRegClassWeight(const TargetRegisterClass *RC) const {
2667
14.3k
  static const RegClassWeight RCWeightTable[] = {
2668
14.3k
    {1, 4},   // FCCRegs
2669
14.3k
    {0, 0},   // ASRRegs
2670
14.3k
    {0, 0},   // CoprocRegs
2671
14.3k
    {1, 32},    // FPRegs
2672
14.3k
    {1, 32},    // IntRegs
2673
14.3k
    {2, 64},    // DFPRegs
2674
14.3k
    {1, 32},    // I64Regs
2675
14.3k
    {0, 0},   // CoprocPair
2676
14.3k
    {2, 32},    // IntPair
2677
14.3k
    {2, 32},    // LowDFPRegs
2678
14.3k
    {1, 15},    // PRRegs
2679
14.3k
    {4, 64},    // QFPRegs
2680
14.3k
    {4, 32},    // LowQFPRegs
2681
14.3k
  };
2682
14.3k
  return RCWeightTable[RC->getID()];
2683
14.3k
}
2684
2685
/// Get the weight in units of pressure for this register unit.
2686
unsigned SparcGenRegisterInfo::
2687
1.55k
getRegUnitWeight(unsigned RegUnit) const {
2688
1.55k
  assert(RegUnit < 171 && "invalid register unit");
2689
1.55k
  static const uint8_t RUWeightTable[] = {
2690
1.55k
    1, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
2691
1.55k
  return RUWeightTable[RegUnit];
2692
1.55k
}
2693
2694
2695
// Get the number of dimensions of register pressure.
2696
1.65k
unsigned SparcGenRegisterInfo::getNumRegPressureSets() const {
2697
1.65k
  return 5;
2698
1.65k
}
2699
2700
// Get the name of this register unit pressure set.
2701
const char *SparcGenRegisterInfo::
2702
0
getRegPressureSetName(unsigned Idx) const {
2703
0
  static const char *const PressureNameTable[] = {
2704
0
    "FCCRegs",
2705
0
    "PRRegs",
2706
0
    "FPRegs",
2707
0
    "IntRegs",
2708
0
    "DFPRegs",
2709
0
  };
2710
0
  return PressureNameTable[Idx];
2711
0
}
2712
2713
// Get the register unit pressure limit for this dimension.
2714
// This limit must be adjusted dynamically for reserved registers.
2715
unsigned SparcGenRegisterInfo::
2716
2.95k
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
2717
2.95k
  static const uint8_t PressureLimitTable[] = {
2718
2.95k
    4,    // 0: FCCRegs
2719
2.95k
    15,   // 1: PRRegs
2720
2.95k
    32,   // 2: FPRegs
2721
2.95k
    32,   // 3: IntRegs
2722
2.95k
    64,   // 4: DFPRegs
2723
2.95k
  };
2724
2.95k
  return PressureLimitTable[Idx];
2725
2.95k
}
2726
2727
/// Table of pressure sets per register class or unit.
2728
static const int RCSetsTable[] = {
2729
  /* 0 */ 0, -1,
2730
  /* 2 */ 1, -1,
2731
  /* 4 */ 3, -1,
2732
  /* 6 */ 2, 4, -1,
2733
};
2734
2735
/// Get the dimensions of register pressure impacted by this register class.
2736
/// Returns a -1 terminated array of pressure set IDs
2737
const int* SparcGenRegisterInfo::
2738
15.7k
getRegClassPressureSets(const TargetRegisterClass *RC) const {
2739
15.7k
  static const uint8_t RCSetStartTable[] = {
2740
15.7k
    0,1,1,6,4,7,4,1,4,6,2,7,6,};
2741
15.7k
  return &RCSetsTable[RCSetStartTable[RC->getID()]];
2742
15.7k
}
2743
2744
/// Get the dimensions of register pressure impacted by this register unit.
2745
/// Returns a -1 terminated array of pressure set IDs
2746
const int* SparcGenRegisterInfo::
2747
1.55k
getRegUnitPressureSets(unsigned RegUnit) const {
2748
1.55k
  assert(RegUnit < 171 && "invalid register unit");
2749
1.55k
  static const uint8_t RUSetStartTable[] = {
2750
1.55k
    2,2,2,1,1,2,1,1,1,2,2,1,2,2,1,2,2,2,2,2,2,1,2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,0,0,0,0,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,};
2751
1.55k
  return &RCSetsTable[RUSetStartTable[RegUnit]];
2752
1.55k
}
2753
2754
extern const MCRegisterDesc SparcRegDesc[];
2755
extern const MCPhysReg SparcRegDiffLists[];
2756
extern const LaneBitmask SparcLaneMaskLists[];
2757
extern const char SparcRegStrings[];
2758
extern const char SparcRegClassStrings[];
2759
extern const MCPhysReg SparcRegUnitRoots[][2];
2760
extern const uint16_t SparcSubRegIdxLists[];
2761
extern const MCRegisterInfo::SubRegCoveredBits SparcSubRegIdxRanges[];
2762
extern const uint16_t SparcRegEncodingTable[];
2763
// SP Dwarf<->LLVM register mappings.
2764
extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0Dwarf2L[];
2765
extern const unsigned SPDwarfFlavour0Dwarf2LSize;
2766
2767
extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0Dwarf2L[];
2768
extern const unsigned SPEHFlavour0Dwarf2LSize;
2769
2770
extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0L2Dwarf[];
2771
extern const unsigned SPDwarfFlavour0L2DwarfSize;
2772
2773
extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0L2Dwarf[];
2774
extern const unsigned SPEHFlavour0L2DwarfSize;
2775
2776
SparcGenRegisterInfo::
2777
SparcGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
2778
      unsigned PC, unsigned HwMode)
2779
  : TargetRegisterInfo(SparcRegInfoDesc, RegisterClasses, RegisterClasses+13,
2780
             SubRegIndexNameTable, SubRegIndexLaneMaskTable,
2781
413
             LaneBitmask(0xFFFFFFFF), RegClassInfos, HwMode) {
2782
413
  InitMCRegisterInfo(SparcRegDesc, 236, RA, PC,
2783
413
                     SparcMCRegisterClasses, 13,
2784
413
                     SparcRegUnitRoots,
2785
413
                     171,
2786
413
                     SparcRegDiffLists,
2787
413
                     SparcLaneMaskLists,
2788
413
                     SparcRegStrings,
2789
413
                     SparcRegClassStrings,
2790
413
                     SparcSubRegIdxLists,
2791
413
                     7,
2792
413
                     SparcSubRegIdxRanges,
2793
413
                     SparcRegEncodingTable);
2794
413
2795
413
  switch (DwarfFlavour) {
2796
413
  default:
2797
0
    llvm_unreachable("Unknown DWARF flavour");
2798
413
  case 0:
2799
413
    mapDwarfRegsToLLVMRegs(SPDwarfFlavour0Dwarf2L, SPDwarfFlavour0Dwarf2LSize, false);
2800
413
    break;
2801
413
  }
2802
413
  switch (EHFlavour) {
2803
413
  default:
2804
0
    llvm_unreachable("Unknown DWARF flavour");
2805
413
  case 0:
2806
413
    mapDwarfRegsToLLVMRegs(SPEHFlavour0Dwarf2L, SPEHFlavour0Dwarf2LSize, true);
2807
413
    break;
2808
413
  }
2809
413
  switch (DwarfFlavour) {
2810
413
  default:
2811
0
    llvm_unreachable("Unknown DWARF flavour");
2812
413
  case 0:
2813
413
    mapLLVMRegsToDwarfRegs(SPDwarfFlavour0L2Dwarf, SPDwarfFlavour0L2DwarfSize, false);
2814
413
    break;
2815
413
  }
2816
413
  switch (EHFlavour) {
2817
413
  default:
2818
0
    llvm_unreachable("Unknown DWARF flavour");
2819
413
  case 0:
2820
413
    mapLLVMRegsToDwarfRegs(SPEHFlavour0L2Dwarf, SPEHFlavour0L2DwarfSize, true);
2821
413
    break;
2822
413
  }
2823
413
}
2824
2825
static const MCPhysReg CSR_SaveList[] = { 0 };
2826
static const uint32_t CSR_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000ffff0, 0x00000000, 0x000000ff, };
2827
static const MCPhysReg RTCSR_SaveList[] = { 0 };
2828
static const uint32_t RTCSR_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000c00, 0x00000000, 0x00000008, };
2829
2830
2831
0
ArrayRef<const uint32_t *> SparcGenRegisterInfo::getRegMasks() const {
2832
0
  static const uint32_t *const Masks[] = {
2833
0
    CSR_RegMask,
2834
0
    RTCSR_RegMask,
2835
0
  };
2836
0
  return makeArrayRef(Masks);
2837
0
}
2838
2839
0
ArrayRef<const char *> SparcGenRegisterInfo::getRegMaskNames() const {
2840
0
  static const char *const Names[] = {
2841
0
    "CSR",
2842
0
    "RTCSR",
2843
0
  };
2844
0
  return makeArrayRef(Names);
2845
0
}
2846
2847
const SparcFrameLowering *
2848
1.65k
SparcGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
2849
1.65k
  return static_cast<const SparcFrameLowering *>(
2850
1.65k
      MF.getSubtarget().getFrameLowering());
2851
1.65k
}
2852
2853
} // end namespace llvm
2854
2855
#endif // GET_REGINFO_TARGET_DESC
2856