Coverage Report

Created: 2019-03-22 08:08

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Sparc/SparcGenSubtargetInfo.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Subtarget Enumeration Source Fragment                                      *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_SUBTARGETINFO_ENUM
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#undef GET_SUBTARGETINFO_ENUM
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namespace llvm {
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namespace Sparc {
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enum {
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  DetectRoundChange = 0,
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  FeatureHardQuad = 1,
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  FeatureLeon = 2,
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  FeatureNoFMULS = 3,
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  FeatureNoFSMULD = 4,
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  FeaturePWRPSR = 5,
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  FeatureSoftFloat = 6,
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  FeatureSoftMulDiv = 7,
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  FeatureV8Deprecated = 8,
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  FeatureV9 = 9,
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  FeatureVIS = 10,
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  FeatureVIS2 = 11,
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  FeatureVIS3 = 12,
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  FixAllFDIVSQRT = 13,
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  InsertNOPLoad = 14,
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  LeonCASA = 15,
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  LeonCycleCounter = 16,
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  UMACSMACSupport = 17,
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  UsePopc = 18,
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};
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} // end namespace Sparc
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} // end namespace llvm
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#endif // GET_SUBTARGETINFO_ENUM
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#ifdef GET_SUBTARGETINFO_MC_DESC
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#undef GET_SUBTARGETINFO_MC_DESC
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namespace llvm {
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// Sorted (by key) array of values for CPU features.
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extern const llvm::SubtargetFeatureKV SparcFeatureKV[] = {
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  { "deprecated-v8", "Enable deprecated V8 instructions in V9 mode", Sparc::FeatureV8Deprecated, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
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  { "detectroundchange", "LEON3 erratum detection: Detects any rounding mode change request: use only the round-to-nearest rounding mode", Sparc::DetectRoundChange, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
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  { "fixallfdivsqrt", "LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store", Sparc::FixAllFDIVSQRT, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
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  { "hard-quad-float", "Enable quad-word floating point instructions", Sparc::FeatureHardQuad, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
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  { "hasleoncasa", "Enable CASA instruction for LEON3 and LEON4 processors", Sparc::LeonCASA, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
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  { "hasumacsmac", "Enable UMAC and SMAC for LEON3 and LEON4 processors", Sparc::UMACSMACSupport, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
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  { "insertnopload", "LEON3 erratum fix: Insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction", Sparc::InsertNOPLoad, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
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  { "leon", "Enable LEON extensions", Sparc::FeatureLeon, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
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  { "leoncyclecounter", "Use the Leon cycle counter register", Sparc::LeonCycleCounter, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
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  { "leonpwrpsr", "Enable the PWRPSR instruction", Sparc::FeaturePWRPSR, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
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  { "no-fmuls", "Disable the fmuls instruction.", Sparc::FeatureNoFMULS, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
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  { "no-fsmuld", "Disable the fsmuld instruction.", Sparc::FeatureNoFSMULD, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
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  { "popc", "Use the popc (population count) instruction", Sparc::UsePopc, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
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  { "soft-float", "Use software emulation for floating point", Sparc::FeatureSoftFloat, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
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  { "soft-mul-div", "Use software emulation for integer multiply and divide", Sparc::FeatureSoftMulDiv, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
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  { "v9", "Enable SPARC-V9 instructions", Sparc::FeatureV9, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
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  { "vis", "Enable UltraSPARC Visual Instruction Set extensions", Sparc::FeatureVIS, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
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  { "vis2", "Enable Visual Instruction Set extensions II", Sparc::FeatureVIS2, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
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  { "vis3", "Enable Visual Instruction Set extensions III", Sparc::FeatureVIS3, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
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};
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#ifdef DBGFIELD
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#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
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#endif
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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#define DBGFIELD(x) x,
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#else
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#define DBGFIELD(x)
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#endif
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// Functional units for "LEON2Itineraries"
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namespace LEON2ItinerariesFU {
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  const unsigned LEONIU = 1 << 0;
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  const unsigned LEONFPU = 1 << 1;
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} // end namespace LEON2ItinerariesFU
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// Functional units for "LEON3Itineraries"
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namespace LEON3ItinerariesFU {
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  const unsigned LEONIU = 1 << 0;
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  const unsigned LEONFPU = 1 << 1;
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} // end namespace LEON3ItinerariesFU
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// Functional units for "LEON4Itineraries"
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namespace LEON4ItinerariesFU {
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  const unsigned LEONIU = 1 << 0;
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  const unsigned LEONFPU = 1 << 1;
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} // end namespace LEON4ItinerariesFU
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extern const llvm::InstrStage SparcStages[] = {
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  { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
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  { 1, LEON2ItinerariesFU::LEONIU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
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  { 1, LEON2ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
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  { 1, LEON2ItinerariesFU::LEONIU | LEON2ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
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  { 1, LEON3ItinerariesFU::LEONIU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 4
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  { 1, LEON3ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 5
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  { 1, LEON3ItinerariesFU::LEONIU | LEON3ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 6
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  { 1, LEON4ItinerariesFU::LEONIU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 7
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  { 1, LEON4ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 8
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  { 1, LEON4ItinerariesFU::LEONIU | LEON4ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 9
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  { 0, 0, 0, llvm::InstrStage::Required } // End stages
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};
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extern const unsigned SparcOperandCycles[] = {
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  0, // No itinerary
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  1,   1, // 1-2
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  7,   1, // 3-4
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  2,   1, // 5-6
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  2,   1, // 7-8
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  7,   1, // 9-10
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  36,   1, // 11-12
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  20,   1, // 13-14
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  21,   1, // 15-16
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  16,   1, // 17-18
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  2,   1, // 19-20
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  65,   1, // 21-22
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  37,   1, // 23-24
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  2,   1, // 25-26
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  2,   1, // 27-28
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  1,   1, // 29-30
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  35,   1, // 31-32
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  5,   1, // 33-34
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  2,   1, // 35-36
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  3,   1, // 37-38
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  5,   1, // 39-40
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  1,   1, // 41-42
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  7,   1, // 43-44
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  3,   1, // 45-46
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  2,   1, // 47-48
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  4,   1, // 49-50
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  17,   1, // 51-52
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  16,   1, // 53-54
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  4,   1, // 55-56
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  4,   1, // 57-58
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  2,   1, // 59-60
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  25,   1, // 61-62
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  24,   1, // 63-64
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  4,   1, // 65-66
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  2,   1, // 67-68
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  1,   1, // 69-70
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  35,   1, // 71-72
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  2,   1, // 73-74
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  1,   1, // 75-76
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  4,   1, // 77-78
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  5,   1, // 79-80
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  4,   1, // 81-82
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  1,   1, // 83-84
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  7,   1, // 85-86
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  3,   1, // 87-88
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  2,   1, // 89-90
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  4,   1, // 91-92
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  17,   1, // 93-94
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  16,   1, // 95-96
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  4,   1, // 97-98
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  4,   1, // 99-100
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  2,   1, // 101-102
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  25,   1, // 103-104
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  24,   1, // 105-106
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  4,   1, // 107-108
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  1,   1, // 109-110
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  1,   1, // 111-112
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  35,   1, // 113-114
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  2,   1, // 115-116
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  1,   1, // 117-118
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  1,   1, // 119-120
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  1,   1, // 121-122
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  4,   1, // 123-124
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  0 // End operand cycles
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};
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extern const unsigned SparcForwardingPaths[] = {
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 0, // No itinerary
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 0,  0, // 1-2
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 0,  0, // 3-4
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 0,  0, // 5-6
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 0,  0, // 7-8
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 0,  0, // 9-10
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 0,  0, // 11-12
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 0,  0, // 13-14
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 0,  0, // 15-16
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 0,  0, // 17-18
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 0,  0, // 19-20
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 0,  0, // 21-22
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 0,  0, // 23-24
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 0,  0, // 25-26
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 0,  0, // 27-28
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 0,  0, // 29-30
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 0,  0, // 31-32
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 0,  0, // 33-34
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 0,  0, // 35-36
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 0,  0, // 37-38
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 0,  0, // 39-40
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 0,  0, // 41-42
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 0,  0, // 43-44
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 0,  0, // 45-46
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 0,  0, // 47-48
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 0,  0, // 49-50
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 0,  0, // 51-52
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 0,  0, // 53-54
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 0,  0, // 55-56
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 0,  0, // 57-58
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 0,  0, // 59-60
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 0,  0, // 61-62
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 0,  0, // 63-64
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 0,  0, // 65-66
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 0,  0, // 67-68
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 0,  0, // 69-70
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 0,  0, // 71-72
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 0,  0, // 73-74
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 0,  0, // 75-76
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 0,  0, // 77-78
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 0,  0, // 79-80
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 0,  0, // 81-82
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 0,  0, // 83-84
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 0,  0, // 85-86
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 0,  0, // 87-88
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 0,  0, // 89-90
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 0,  0, // 91-92
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 0,  0, // 93-94
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 0,  0, // 95-96
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 0,  0, // 97-98
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 0,  0, // 99-100
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 0,  0, // 101-102
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 0,  0, // 103-104
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 0,  0, // 105-106
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 0,  0, // 107-108
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 0,  0, // 109-110
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 0,  0, // 111-112
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 0,  0, // 113-114
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 0,  0, // 115-116
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 0,  0, // 117-118
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 0,  0, // 119-120
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 0,  0, // 121-122
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 0,  0, // 123-124
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 0 // End bypass tables
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};
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static const llvm::InstrItinerary LEON2Itineraries[] = {
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  { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
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  { 1, 1, 2, 1, 3 }, // 1 IIC_iu_instr
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  { 1, 2, 3, 3, 5 }, // 2 IIC_fpu_normal_instr
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  { 1, 3, 4, 5, 7 }, // 3 IIC_jmp_or_call
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  { 1, 2, 3, 7, 9 }, // 4 IIC_fpu_abs
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  { 1, 2, 3, 9, 11 }, // 5 IIC_fpu_fast_instr
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  { 1, 2, 3, 11, 13 }, // 6 IIC_fpu_divd
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  { 1, 2, 3, 13, 15 }, // 7 IIC_fpu_divs
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  { 1, 2, 3, 15, 17 }, // 8 IIC_fpu_muld
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  { 1, 2, 3, 17, 19 }, // 9 IIC_fpu_muls
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  { 1, 2, 3, 19, 21 }, // 10 IIC_fpu_negs
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  { 1, 2, 3, 21, 23 }, // 11 IIC_fpu_sqrtd
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  { 1, 2, 3, 23, 25 }, // 12 IIC_fpu_sqrts
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  { 1, 2, 3, 25, 27 }, // 13 IIC_fpu_stod
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  { 1, 3, 4, 27, 29 }, // 14 IIC_ldd
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  { 1, 3, 4, 29, 31 }, // 15 IIC_iu_or_fpu_instr
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  { 1, 1, 2, 31, 33 }, // 16 IIC_iu_div
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  { 0, 0, 0, 0, 0 }, // 17 IIC_smac_umac
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  { 1, 1, 2, 33, 35 }, // 18 IIC_iu_smul
262
  { 1, 3, 4, 35, 37 }, // 19 IIC_st
263
  { 1, 3, 4, 37, 39 }, // 20 IIC_std
264
  { 1, 1, 2, 39, 41 }, // 21 IIC_iu_umul
265
  { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
266
};
267
268
static const llvm::InstrItinerary LEON3Itineraries[] = {
269
  { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
270
  { 1, 4, 5, 41, 43 }, // 1 IIC_iu_instr
271
  { 1, 5, 6, 43, 45 }, // 2 IIC_fpu_normal_instr
272
  { 1, 6, 7, 45, 47 }, // 3 IIC_jmp_or_call
273
  { 1, 5, 6, 47, 49 }, // 4 IIC_fpu_abs
274
  { 1, 5, 6, 49, 51 }, // 5 IIC_fpu_fast_instr
275
  { 1, 5, 6, 51, 53 }, // 6 IIC_fpu_divd
276
  { 1, 5, 6, 53, 55 }, // 7 IIC_fpu_divs
277
  { 1, 5, 6, 55, 57 }, // 8 IIC_fpu_muld
278
  { 1, 5, 6, 57, 59 }, // 9 IIC_fpu_muls
279
  { 1, 5, 6, 59, 61 }, // 10 IIC_fpu_negs
280
  { 1, 5, 6, 61, 63 }, // 11 IIC_fpu_sqrtd
281
  { 1, 5, 6, 63, 65 }, // 12 IIC_fpu_sqrts
282
  { 1, 5, 6, 65, 67 }, // 13 IIC_fpu_stod
283
  { 1, 6, 7, 67, 69 }, // 14 IIC_ldd
284
  { 1, 6, 7, 69, 71 }, // 15 IIC_iu_or_fpu_instr
285
  { 1, 4, 5, 71, 73 }, // 16 IIC_iu_div
286
  { 1, 4, 5, 73, 75 }, // 17 IIC_smac_umac
287
  { 1, 4, 5, 75, 77 }, // 18 IIC_iu_smul
288
  { 1, 6, 7, 77, 79 }, // 19 IIC_st
289
  { 1, 6, 7, 79, 81 }, // 20 IIC_std
290
  { 1, 4, 5, 81, 83 }, // 21 IIC_iu_umul
291
  { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
292
};
293
294
static const llvm::InstrItinerary LEON4Itineraries[] = {
295
  { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
296
  { 1, 7, 8, 83, 85 }, // 1 IIC_iu_instr
297
  { 1, 8, 9, 85, 87 }, // 2 IIC_fpu_normal_instr
298
  { 1, 9, 10, 87, 89 }, // 3 IIC_jmp_or_call
299
  { 1, 8, 9, 89, 91 }, // 4 IIC_fpu_abs
300
  { 1, 8, 9, 91, 93 }, // 5 IIC_fpu_fast_instr
301
  { 1, 8, 9, 93, 95 }, // 6 IIC_fpu_divd
302
  { 1, 8, 9, 95, 97 }, // 7 IIC_fpu_divs
303
  { 1, 8, 9, 97, 99 }, // 8 IIC_fpu_muld
304
  { 1, 8, 9, 99, 101 }, // 9 IIC_fpu_muls
305
  { 1, 8, 9, 101, 103 }, // 10 IIC_fpu_negs
306
  { 1, 8, 9, 103, 105 }, // 11 IIC_fpu_sqrtd
307
  { 1, 8, 9, 105, 107 }, // 12 IIC_fpu_sqrts
308
  { 1, 8, 9, 107, 109 }, // 13 IIC_fpu_stod
309
  { 1, 9, 10, 109, 111 }, // 14 IIC_ldd
310
  { 1, 9, 10, 111, 113 }, // 15 IIC_iu_or_fpu_instr
311
  { 1, 7, 8, 113, 115 }, // 16 IIC_iu_div
312
  { 1, 7, 8, 115, 117 }, // 17 IIC_smac_umac
313
  { 1, 7, 8, 117, 119 }, // 18 IIC_iu_smul
314
  { 1, 9, 10, 119, 121 }, // 19 IIC_st
315
  { 1, 9, 10, 121, 123 }, // 20 IIC_std
316
  { 1, 7, 8, 123, 125 }, // 21 IIC_iu_umul
317
  { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
318
};
319
320
// ===============================================================
321
// Data tables for the new per-operand machine model.
322
323
// {ProcResourceIdx, Cycles}
324
extern const llvm::MCWriteProcResEntry SparcWriteProcResTable[] = {
325
  { 0,  0}, // Invalid
326
}; // SparcWriteProcResTable
327
328
// {Cycles, WriteResourceID}
329
extern const llvm::MCWriteLatencyEntry SparcWriteLatencyTable[] = {
330
  { 0,  0}, // Invalid
331
}; // SparcWriteLatencyTable
332
333
// {UseIdx, WriteResourceID, Cycles}
334
extern const llvm::MCReadAdvanceEntry SparcReadAdvanceTable[] = {
335
  {0,  0,  0}, // Invalid
336
}; // SparcReadAdvanceTable
337
338
#undef DBGFIELD
339
340
static const llvm::MCSchedModel NoSchedModel = {
341
  MCSchedModel::DefaultIssueWidth,
342
  MCSchedModel::DefaultMicroOpBufferSize,
343
  MCSchedModel::DefaultLoopMicroOpBufferSize,
344
  MCSchedModel::DefaultLoadLatency,
345
  MCSchedModel::DefaultHighLatency,
346
  MCSchedModel::DefaultMispredictPenalty,
347
  false, // PostRAScheduler
348
  false, // CompleteModel
349
  0, // Processor ID
350
  nullptr, nullptr, 0, 0, // No instruction-level machine model.
351
  nullptr, // No Itinerary
352
  nullptr // No extra processor descriptor
353
};
354
355
static const llvm::MCSchedModel LEON2ItinerariesModel = {
356
  MCSchedModel::DefaultIssueWidth,
357
  MCSchedModel::DefaultMicroOpBufferSize,
358
  MCSchedModel::DefaultLoopMicroOpBufferSize,
359
  MCSchedModel::DefaultLoadLatency,
360
  MCSchedModel::DefaultHighLatency,
361
  MCSchedModel::DefaultMispredictPenalty,
362
  false, // PostRAScheduler
363
  false, // CompleteModel
364
  1, // Processor ID
365
  nullptr, nullptr, 0, 0, // No instruction-level machine model.
366
  LEON2Itineraries,
367
  nullptr // No extra processor descriptor
368
};
369
370
static const llvm::MCSchedModel LEON3ItinerariesModel = {
371
  MCSchedModel::DefaultIssueWidth,
372
  MCSchedModel::DefaultMicroOpBufferSize,
373
  MCSchedModel::DefaultLoopMicroOpBufferSize,
374
  MCSchedModel::DefaultLoadLatency,
375
  MCSchedModel::DefaultHighLatency,
376
  MCSchedModel::DefaultMispredictPenalty,
377
  false, // PostRAScheduler
378
  false, // CompleteModel
379
  2, // Processor ID
380
  nullptr, nullptr, 0, 0, // No instruction-level machine model.
381
  LEON3Itineraries,
382
  nullptr // No extra processor descriptor
383
};
384
385
static const llvm::MCSchedModel LEON4ItinerariesModel = {
386
  MCSchedModel::DefaultIssueWidth,
387
  MCSchedModel::DefaultMicroOpBufferSize,
388
  MCSchedModel::DefaultLoopMicroOpBufferSize,
389
  MCSchedModel::DefaultLoadLatency,
390
  MCSchedModel::DefaultHighLatency,
391
  MCSchedModel::DefaultMispredictPenalty,
392
  false, // PostRAScheduler
393
  false, // CompleteModel
394
  3, // Processor ID
395
  nullptr, nullptr, 0, 0, // No instruction-level machine model.
396
  LEON4Itineraries,
397
  nullptr // No extra processor descriptor
398
};
399
400
// Sorted (by key) array of values for CPU subtype.
401
extern const llvm::SubtargetSubTypeKV SparcSubTypeKV[] = {
402
 { "at697e", { { { 0x4004ULL, 0x0ULL, 0x0ULL, } } }, &LEON2ItinerariesModel },
403
 { "at697f", { { { 0x4004ULL, 0x0ULL, 0x0ULL, } } }, &LEON2ItinerariesModel },
404
 { "f934", { { { 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
405
 { "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
406
 { "gr712rc", { { { 0x8004ULL, 0x0ULL, 0x0ULL, } } }, &LEON3ItinerariesModel },
407
 { "gr740", { { { 0x38024ULL, 0x0ULL, 0x0ULL, } } }, &LEON4ItinerariesModel },
408
 { "hypersparc", { { { 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
409
 { "leon2", { { { 0x4ULL, 0x0ULL, 0x0ULL, } } }, &LEON2ItinerariesModel },
410
 { "leon3", { { { 0x20004ULL, 0x0ULL, 0x0ULL, } } }, &LEON3ItinerariesModel },
411
 { "leon4", { { { 0x28004ULL, 0x0ULL, 0x0ULL, } } }, &LEON4ItinerariesModel },
412
 { "ma2080", { { { 0x8004ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
413
 { "ma2085", { { { 0x8004ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
414
 { "ma2100", { { { 0x8004ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
415
 { "ma2150", { { { 0x8004ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
416
 { "ma2155", { { { 0x8004ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
417
 { "ma2450", { { { 0x8004ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
418
 { "ma2455", { { { 0x8004ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
419
 { "ma2480", { { { 0x8004ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
420
 { "ma2485", { { { 0x8004ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
421
 { "ma2x5x", { { { 0x8004ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
422
 { "ma2x8x", { { { 0x8004ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
423
 { "myriad2", { { { 0x8004ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
424
 { "myriad2.1", { { { 0x8004ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
425
 { "myriad2.2", { { { 0x8004ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
426
 { "myriad2.3", { { { 0x8004ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
427
 { "niagara", { { { 0xf00ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
428
 { "niagara2", { { { 0x40f00ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
429
 { "niagara3", { { { 0x40f00ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
430
 { "niagara4", { { { 0x41f00ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
431
 { "sparclet", { { { 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
432
 { "sparclite", { { { 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
433
 { "sparclite86x", { { { 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
434
 { "supersparc", { { { 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
435
 { "tsc701", { { { 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
436
 { "ultrasparc", { { { 0x700ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
437
 { "ultrasparc3", { { { 0xf00ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
438
 { "ut699", { { { 0x601cULL, 0x0ULL, 0x0ULL, } } }, &LEON3ItinerariesModel },
439
 { "v7", { { { 0x90ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
440
 { "v8", { { { 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
441
 { "v9", { { { 0x200ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
442
};
443
444
namespace Sparc_MC {
445
unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
446
0
    const MCInst *MI, unsigned CPUID) {
447
0
  // Don't know how to resolve this scheduling class.
448
0
  return 0;
449
0
}
450
} // end of namespace Sparc_MC
451
452
struct SparcGenMCSubtargetInfo : public MCSubtargetInfo {
453
  SparcGenMCSubtargetInfo(const Triple &TT, 
454
    StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
455
    ArrayRef<SubtargetSubTypeKV> PD,
456
    const MCWriteProcResEntry *WPR,
457
    const MCWriteLatencyEntry *WL,
458
    const MCReadAdvanceEntry *RA, const InstrStage *IS,
459
    const unsigned *OC, const unsigned *FP) :
460
      MCSubtargetInfo(TT, CPU, FS, PF, PD,
461
293
                      WPR, WL, RA, IS, OC, FP) { }
462
463
  unsigned resolveVariantSchedClass(unsigned SchedClass,
464
0
      const MCInst *MI, unsigned CPUID) const override {
465
0
    return Sparc_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID); 
466
0
  }
467
};
468
469
293
static inline MCSubtargetInfo *createSparcMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) {
470
293
  return new SparcGenMCSubtargetInfo(TT, CPU, FS, SparcFeatureKV, SparcSubTypeKV, 
471
293
                      SparcWriteProcResTable, SparcWriteLatencyTable, SparcReadAdvanceTable, 
472
293
                      SparcStages, SparcOperandCycles, SparcForwardingPaths);
473
293
}
474
475
} // end namespace llvm
476
477
#endif // GET_SUBTARGETINFO_MC_DESC
478
479
480
#ifdef GET_SUBTARGETINFO_TARGET_DESC
481
#undef GET_SUBTARGETINFO_TARGET_DESC
482
483
#include "llvm/Support/Debug.h"
484
#include "llvm/Support/raw_ostream.h"
485
486
// ParseSubtargetFeatures - Parses features string setting specified
487
// subtarget options.
488
419
void llvm::SparcSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {
489
419
  LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
490
419
  LLVM_DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n");
491
419
  InitMCProcessorInfo(CPU, FS);
492
419
  const FeatureBitset& Bits = getFeatureBits();
493
419
  if (Bits[Sparc::DetectRoundChange]) 
DetectRoundChange = true2
;
494
419
  if (Bits[Sparc::FeatureHardQuad]) 
HasHardQuad = true4
;
495
419
  if (Bits[Sparc::FeatureLeon]) 
IsLeon = true62
;
496
419
  if (Bits[Sparc::FeatureNoFMULS]) 
HasNoFMULS = true8
;
497
419
  if (Bits[Sparc::FeatureNoFSMULD]) 
HasNoFSMULD = true10
;
498
419
  if (Bits[Sparc::FeaturePWRPSR]) 
HasPWRPSR = true4
;
499
419
  if (Bits[Sparc::FeatureSoftFloat]) 
UseSoftFloat = true7
;
500
419
  if (Bits[Sparc::FeatureSoftMulDiv]) 
UseSoftMulDiv = true2
;
501
419
  if (Bits[Sparc::FeatureV8Deprecated]) 
V8DeprecatedInsts = true12
;
502
419
  if (Bits[Sparc::FeatureV9]) 
IsV9 = true151
;
503
419
  if (Bits[Sparc::FeatureVIS]) 
IsVIS = true12
;
504
419
  if (Bits[Sparc::FeatureVIS2]) 
IsVIS2 = true10
;
505
419
  if (Bits[Sparc::FeatureVIS3]) 
IsVIS3 = true2
;
506
419
  if (Bits[Sparc::FixAllFDIVSQRT]) 
FixAllFDIVSQRT = true6
;
507
419
  if (Bits[Sparc::InsertNOPLoad]) 
InsertNOPLoad = true6
;
508
419
  if (Bits[Sparc::LeonCASA]) 
HasLeonCasa = true44
;
509
419
  if (Bits[Sparc::LeonCycleCounter]) 
HasLeonCycleCounter = true4
;
510
419
  if (Bits[Sparc::UMACSMACSupport]) 
HasUmacSmac = true22
;
511
419
  if (Bits[Sparc::UsePopc]) 
UsePopc = true14
;
512
419
}
513
#endif // GET_SUBTARGETINFO_TARGET_DESC
514
515
516
#ifdef GET_SUBTARGETINFO_HEADER
517
#undef GET_SUBTARGETINFO_HEADER
518
519
namespace llvm {
520
class DFAPacketizer;
521
namespace Sparc_MC {
522
unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
523
}
524
525
struct SparcGenSubtargetInfo : public TargetSubtargetInfo {
526
  explicit SparcGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS);
527
public:
528
  unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
529
  unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
530
  DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
531
};
532
} // end namespace llvm
533
534
#endif // GET_SUBTARGETINFO_HEADER
535
536
537
#ifdef GET_SUBTARGETINFO_CTOR
538
#undef GET_SUBTARGETINFO_CTOR
539
540
#include "llvm/CodeGen/TargetSchedule.h"
541
542
namespace llvm {
543
extern const llvm::SubtargetFeatureKV SparcFeatureKV[];
544
extern const llvm::SubtargetSubTypeKV SparcSubTypeKV[];
545
extern const llvm::MCWriteProcResEntry SparcWriteProcResTable[];
546
extern const llvm::MCWriteLatencyEntry SparcWriteLatencyTable[];
547
extern const llvm::MCReadAdvanceEntry SparcReadAdvanceTable[];
548
extern const llvm::InstrStage SparcStages[];
549
extern const unsigned SparcOperandCycles[];
550
extern const unsigned SparcForwardingPaths[];
551
SparcGenSubtargetInfo::SparcGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
552
  : TargetSubtargetInfo(TT, CPU, FS, makeArrayRef(SparcFeatureKV, 19), makeArrayRef(SparcSubTypeKV, 40), 
553
                        SparcWriteProcResTable, SparcWriteLatencyTable, SparcReadAdvanceTable, 
554
419
                        SparcStages, SparcOperandCycles, SparcForwardingPaths) {}
555
556
unsigned SparcGenSubtargetInfo
557
0
::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
558
0
  report_fatal_error("Expected a variant SchedClass");
559
0
} // SparcGenSubtargetInfo::resolveSchedClass
560
561
unsigned SparcGenSubtargetInfo
562
0
::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
563
0
  return Sparc_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
564
0
} // SparcGenSubtargetInfo::resolveVariantSchedClass
565
566
} // end namespace llvm
567
568
#endif // GET_SUBTARGETINFO_CTOR
569
570
571
#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
572
#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
573
574
#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
575
576
577
#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
578
#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
579
580
#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
581