Coverage Report

Created: 2018-07-12 09:57

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/Sparc/SparcGenSubtargetInfo.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Subtarget Enumeration Source Fragment                                      *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_SUBTARGETINFO_ENUM
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#undef GET_SUBTARGETINFO_ENUM
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namespace llvm {
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namespace Sparc {
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enum {
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  DetectRoundChange = 0,
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  FeatureHardQuad = 1,
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  FeatureLeon = 2,
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  FeatureNoFMULS = 3,
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  FeatureNoFSMULD = 4,
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  FeatureSoftFloat = 5,
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  FeatureSoftMulDiv = 6,
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  FeatureV8Deprecated = 7,
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  FeatureV9 = 8,
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  FeatureVIS = 9,
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  FeatureVIS2 = 10,
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  FeatureVIS3 = 11,
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  FixAllFDIVSQRT = 12,
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  InsertNOPLoad = 13,
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  LeonCASA = 14,
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  UMACSMACSupport = 15,
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  UsePopc = 16,
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};
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} // end namespace Sparc
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} // end namespace llvm
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#endif // GET_SUBTARGETINFO_ENUM
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#ifdef GET_SUBTARGETINFO_MC_DESC
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#undef GET_SUBTARGETINFO_MC_DESC
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namespace llvm {
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// Sorted (by key) array of values for CPU features.
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extern const llvm::SubtargetFeatureKV SparcFeatureKV[] = {
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  { "deprecated-v8", "Enable deprecated V8 instructions in V9 mode", { Sparc::FeatureV8Deprecated }, { } },
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  { "detectroundchange", "LEON3 erratum detection: Detects any rounding mode change request: use only the round-to-nearest rounding mode", { Sparc::DetectRoundChange }, { } },
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  { "fixallfdivsqrt", "LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store", { Sparc::FixAllFDIVSQRT }, { } },
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  { "hard-quad-float", "Enable quad-word floating point instructions", { Sparc::FeatureHardQuad }, { } },
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  { "hasleoncasa", "Enable CASA instruction for LEON3 and LEON4 processors", { Sparc::LeonCASA }, { } },
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  { "hasumacsmac", "Enable UMAC and SMAC for LEON3 and LEON4 processors", { Sparc::UMACSMACSupport }, { } },
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  { "insertnopload", "LEON3 erratum fix: Insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction", { Sparc::InsertNOPLoad }, { } },
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  { "leon", "Enable LEON extensions", { Sparc::FeatureLeon }, { } },
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  { "no-fmuls", "Disable the fmuls instruction.", { Sparc::FeatureNoFMULS }, { } },
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  { "no-fsmuld", "Disable the fsmuld instruction.", { Sparc::FeatureNoFSMULD }, { } },
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  { "popc", "Use the popc (population count) instruction", { Sparc::UsePopc }, { } },
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  { "soft-float", "Use software emulation for floating point", { Sparc::FeatureSoftFloat }, { } },
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  { "soft-mul-div", "Use software emulation for integer multiply and divide", { Sparc::FeatureSoftMulDiv }, { } },
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  { "v9", "Enable SPARC-V9 instructions", { Sparc::FeatureV9 }, { } },
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  { "vis", "Enable UltraSPARC Visual Instruction Set extensions", { Sparc::FeatureVIS }, { } },
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  { "vis2", "Enable Visual Instruction Set extensions II", { Sparc::FeatureVIS2 }, { } },
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  { "vis3", "Enable Visual Instruction Set extensions III", { Sparc::FeatureVIS3 }, { } },
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};
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// Sorted (by key) array of values for CPU subtype.
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extern const llvm::SubtargetFeatureKV SparcSubTypeKV[] = {
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  { "at697e", "Select the at697e processor", { Sparc::FeatureLeon, Sparc::InsertNOPLoad }, { } },
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  { "at697f", "Select the at697f processor", { Sparc::FeatureLeon, Sparc::InsertNOPLoad }, { } },
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  { "f934", "Select the f934 processor", { }, { } },
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  { "generic", "Select the generic processor", { }, { } },
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  { "gr712rc", "Select the gr712rc processor", { Sparc::FeatureLeon, Sparc::LeonCASA }, { } },
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  { "gr740", "Select the gr740 processor", { Sparc::FeatureLeon, Sparc::UMACSMACSupport, Sparc::LeonCASA }, { } },
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  { "hypersparc", "Select the hypersparc processor", { }, { } },
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  { "leon2", "Select the leon2 processor", { Sparc::FeatureLeon }, { } },
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  { "leon3", "Select the leon3 processor", { Sparc::FeatureLeon, Sparc::UMACSMACSupport }, { } },
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  { "leon4", "Select the leon4 processor", { Sparc::FeatureLeon, Sparc::UMACSMACSupport, Sparc::LeonCASA }, { } },
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  { "ma2080", "Select the ma2080 processor", { Sparc::FeatureLeon, Sparc::LeonCASA }, { } },
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  { "ma2085", "Select the ma2085 processor", { Sparc::FeatureLeon, Sparc::LeonCASA }, { } },
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  { "ma2100", "Select the ma2100 processor", { Sparc::FeatureLeon, Sparc::LeonCASA }, { } },
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  { "ma2150", "Select the ma2150 processor", { Sparc::FeatureLeon, Sparc::LeonCASA }, { } },
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  { "ma2155", "Select the ma2155 processor", { Sparc::FeatureLeon, Sparc::LeonCASA }, { } },
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  { "ma2450", "Select the ma2450 processor", { Sparc::FeatureLeon, Sparc::LeonCASA }, { } },
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  { "ma2455", "Select the ma2455 processor", { Sparc::FeatureLeon, Sparc::LeonCASA }, { } },
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  { "ma2480", "Select the ma2480 processor", { Sparc::FeatureLeon, Sparc::LeonCASA }, { } },
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  { "ma2485", "Select the ma2485 processor", { Sparc::FeatureLeon, Sparc::LeonCASA }, { } },
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  { "ma2x5x", "Select the ma2x5x processor", { Sparc::FeatureLeon, Sparc::LeonCASA }, { } },
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  { "ma2x8x", "Select the ma2x8x processor", { Sparc::FeatureLeon, Sparc::LeonCASA }, { } },
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  { "myriad2", "Select the myriad2 processor", { Sparc::FeatureLeon, Sparc::LeonCASA }, { } },
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  { "myriad2.1", "Select the myriad2.1 processor", { Sparc::FeatureLeon, Sparc::LeonCASA }, { } },
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  { "myriad2.2", "Select the myriad2.2 processor", { Sparc::FeatureLeon, Sparc::LeonCASA }, { } },
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  { "myriad2.3", "Select the myriad2.3 processor", { Sparc::FeatureLeon, Sparc::LeonCASA }, { } },
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  { "niagara", "Select the niagara processor", { Sparc::FeatureV9, Sparc::FeatureV8Deprecated, Sparc::FeatureVIS, Sparc::FeatureVIS2 }, { } },
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  { "niagara2", "Select the niagara2 processor", { Sparc::FeatureV9, Sparc::FeatureV8Deprecated, Sparc::UsePopc, Sparc::FeatureVIS, Sparc::FeatureVIS2 }, { } },
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  { "niagara3", "Select the niagara3 processor", { Sparc::FeatureV9, Sparc::FeatureV8Deprecated, Sparc::UsePopc, Sparc::FeatureVIS, Sparc::FeatureVIS2 }, { } },
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  { "niagara4", "Select the niagara4 processor", { Sparc::FeatureV9, Sparc::FeatureV8Deprecated, Sparc::UsePopc, Sparc::FeatureVIS, Sparc::FeatureVIS2, Sparc::FeatureVIS3 }, { } },
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  { "sparclet", "Select the sparclet processor", { }, { } },
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  { "sparclite", "Select the sparclite processor", { }, { } },
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  { "sparclite86x", "Select the sparclite86x processor", { }, { } },
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  { "supersparc", "Select the supersparc processor", { }, { } },
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  { "tsc701", "Select the tsc701 processor", { }, { } },
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  { "ultrasparc", "Select the ultrasparc processor", { Sparc::FeatureV9, Sparc::FeatureV8Deprecated, Sparc::FeatureVIS }, { } },
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  { "ultrasparc3", "Select the ultrasparc3 processor", { Sparc::FeatureV9, Sparc::FeatureV8Deprecated, Sparc::FeatureVIS, Sparc::FeatureVIS2 }, { } },
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  { "ut699", "Select the ut699 processor", { Sparc::FeatureLeon, Sparc::InsertNOPLoad, Sparc::FeatureNoFSMULD, Sparc::FeatureNoFMULS, Sparc::FixAllFDIVSQRT }, { } },
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  { "v7", "Select the v7 processor", { Sparc::FeatureSoftMulDiv, Sparc::FeatureNoFSMULD }, { } },
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  { "v8", "Select the v8 processor", { }, { } },
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  { "v9", "Select the v9 processor", { Sparc::FeatureV9 }, { } },
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};
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#ifdef DBGFIELD
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#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
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#endif
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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#define DBGFIELD(x) x,
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#else
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#define DBGFIELD(x)
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#endif
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// Functional units for "LEON2Itineraries"
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namespace LEON2ItinerariesFU {
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  const unsigned LEONIU = 1 << 0;
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  const unsigned LEONFPU = 1 << 1;
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} // end namespace LEON2ItinerariesFU
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// Functional units for "LEON3Itineraries"
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namespace LEON3ItinerariesFU {
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  const unsigned LEONIU = 1 << 0;
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  const unsigned LEONFPU = 1 << 1;
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} // end namespace LEON3ItinerariesFU
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// Functional units for "LEON4Itineraries"
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namespace LEON4ItinerariesFU {
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  const unsigned LEONIU = 1 << 0;
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  const unsigned LEONFPU = 1 << 1;
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} // end namespace LEON4ItinerariesFU
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extern const llvm::InstrStage SparcStages[] = {
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  { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
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  { 1, LEON2ItinerariesFU::LEONIU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
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  { 1, LEON2ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
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  { 1, LEON2ItinerariesFU::LEONIU | LEON2ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
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  { 1, LEON3ItinerariesFU::LEONIU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 4
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  { 1, LEON3ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 5
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  { 1, LEON3ItinerariesFU::LEONIU | LEON3ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 6
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  { 1, LEON4ItinerariesFU::LEONIU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 7
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  { 1, LEON4ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 8
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  { 1, LEON4ItinerariesFU::LEONIU | LEON4ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 9
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  { 0, 0, 0, llvm::InstrStage::Required } // End stages
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};
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extern const unsigned SparcOperandCycles[] = {
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  0, // No itinerary
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  1,   1, // 1-2
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  7,   1, // 3-4
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  2,   1, // 5-6
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  2,   1, // 7-8
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  7,   1, // 9-10
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  36,   1, // 11-12
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  20,   1, // 13-14
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  21,   1, // 15-16
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  16,   1, // 17-18
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  2,   1, // 19-20
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  65,   1, // 21-22
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  37,   1, // 23-24
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  2,   1, // 25-26
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  2,   1, // 27-28
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  1,   1, // 29-30
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  35,   1, // 31-32
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  5,   1, // 33-34
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  2,   1, // 35-36
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  3,   1, // 37-38
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  5,   1, // 39-40
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  1,   1, // 41-42
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  7,   1, // 43-44
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  3,   1, // 45-46
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  2,   1, // 47-48
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  4,   1, // 49-50
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  17,   1, // 51-52
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  16,   1, // 53-54
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  4,   1, // 55-56
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  4,   1, // 57-58
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  2,   1, // 59-60
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  25,   1, // 61-62
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  24,   1, // 63-64
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  4,   1, // 65-66
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  2,   1, // 67-68
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  1,   1, // 69-70
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  35,   1, // 71-72
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  2,   1, // 73-74
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  1,   1, // 75-76
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  4,   1, // 77-78
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  5,   1, // 79-80
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  4,   1, // 81-82
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  1,   1, // 83-84
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  7,   1, // 85-86
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  3,   1, // 87-88
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  2,   1, // 89-90
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  4,   1, // 91-92
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  17,   1, // 93-94
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  16,   1, // 95-96
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  4,   1, // 97-98
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  4,   1, // 99-100
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  2,   1, // 101-102
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  25,   1, // 103-104
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  24,   1, // 105-106
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  4,   1, // 107-108
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  1,   1, // 109-110
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  1,   1, // 111-112
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  35,   1, // 113-114
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  2,   1, // 115-116
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  1,   1, // 117-118
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  1,   1, // 119-120
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  1,   1, // 121-122
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  4,   1, // 123-124
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  0 // End operand cycles
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};
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extern const unsigned SparcForwardingPaths[] = {
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 0, // No itinerary
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 0,  0, // 1-2
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 0,  0, // 3-4
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 0,  0, // 5-6
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 0,  0, // 7-8
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 0,  0, // 9-10
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 0,  0, // 11-12
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 0,  0, // 13-14
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 0,  0, // 15-16
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 0,  0, // 17-18
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 0,  0, // 19-20
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 0,  0, // 21-22
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 0,  0, // 23-24
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 0,  0, // 25-26
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 0,  0, // 27-28
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 0,  0, // 29-30
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 0,  0, // 31-32
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 0,  0, // 33-34
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 0,  0, // 35-36
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 0,  0, // 37-38
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 0,  0, // 39-40
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 0,  0, // 41-42
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 0,  0, // 43-44
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 0,  0, // 45-46
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 0,  0, // 47-48
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 0,  0, // 49-50
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 0,  0, // 51-52
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 0,  0, // 53-54
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 0,  0, // 55-56
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 0,  0, // 57-58
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 0,  0, // 59-60
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 0,  0, // 61-62
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 0,  0, // 63-64
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 0,  0, // 65-66
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 0,  0, // 67-68
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 0,  0, // 69-70
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 0,  0, // 71-72
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 0,  0, // 73-74
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 0,  0, // 75-76
255
 0,  0, // 77-78
256
 0,  0, // 79-80
257
 0,  0, // 81-82
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 0,  0, // 83-84
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 0,  0, // 85-86
260
 0,  0, // 87-88
261
 0,  0, // 89-90
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 0,  0, // 91-92
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 0,  0, // 93-94
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 0,  0, // 95-96
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 0,  0, // 97-98
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 0,  0, // 99-100
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 0,  0, // 101-102
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 0,  0, // 103-104
269
 0,  0, // 105-106
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 0,  0, // 107-108
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 0,  0, // 109-110
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 0,  0, // 111-112
273
 0,  0, // 113-114
274
 0,  0, // 115-116
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 0,  0, // 117-118
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 0,  0, // 119-120
277
 0,  0, // 121-122
278
 0,  0, // 123-124
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 0 // End bypass tables
280
};
281
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static const llvm::InstrItinerary LEON2Itineraries[] = {
283
  { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
284
  { 1, 1, 2, 1, 3 }, // 1 IIC_iu_instr
285
  { 1, 2, 3, 3, 5 }, // 2 IIC_fpu_normal_instr
286
  { 1, 3, 4, 5, 7 }, // 3 IIC_jmp_or_call
287
  { 1, 2, 3, 7, 9 }, // 4 IIC_fpu_abs
288
  { 1, 2, 3, 9, 11 }, // 5 IIC_fpu_fast_instr
289
  { 1, 2, 3, 11, 13 }, // 6 IIC_fpu_divd
290
  { 1, 2, 3, 13, 15 }, // 7 IIC_fpu_divs
291
  { 1, 2, 3, 15, 17 }, // 8 IIC_fpu_muld
292
  { 1, 2, 3, 17, 19 }, // 9 IIC_fpu_muls
293
  { 1, 2, 3, 19, 21 }, // 10 IIC_fpu_negs
294
  { 1, 2, 3, 21, 23 }, // 11 IIC_fpu_sqrtd
295
  { 1, 2, 3, 23, 25 }, // 12 IIC_fpu_sqrts
296
  { 1, 2, 3, 25, 27 }, // 13 IIC_fpu_stod
297
  { 1, 3, 4, 27, 29 }, // 14 IIC_ldd
298
  { 1, 3, 4, 29, 31 }, // 15 IIC_iu_or_fpu_instr
299
  { 1, 1, 2, 31, 33 }, // 16 IIC_iu_div
300
  { 0, 0, 0, 0, 0 }, // 17 IIC_smac_umac
301
  { 1, 1, 2, 33, 35 }, // 18 IIC_iu_smul
302
  { 1, 3, 4, 35, 37 }, // 19 IIC_st
303
  { 1, 3, 4, 37, 39 }, // 20 IIC_std
304
  { 1, 1, 2, 39, 41 }, // 21 IIC_iu_umul
305
  { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
306
};
307
308
static const llvm::InstrItinerary LEON3Itineraries[] = {
309
  { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
310
  { 1, 4, 5, 41, 43 }, // 1 IIC_iu_instr
311
  { 1, 5, 6, 43, 45 }, // 2 IIC_fpu_normal_instr
312
  { 1, 6, 7, 45, 47 }, // 3 IIC_jmp_or_call
313
  { 1, 5, 6, 47, 49 }, // 4 IIC_fpu_abs
314
  { 1, 5, 6, 49, 51 }, // 5 IIC_fpu_fast_instr
315
  { 1, 5, 6, 51, 53 }, // 6 IIC_fpu_divd
316
  { 1, 5, 6, 53, 55 }, // 7 IIC_fpu_divs
317
  { 1, 5, 6, 55, 57 }, // 8 IIC_fpu_muld
318
  { 1, 5, 6, 57, 59 }, // 9 IIC_fpu_muls
319
  { 1, 5, 6, 59, 61 }, // 10 IIC_fpu_negs
320
  { 1, 5, 6, 61, 63 }, // 11 IIC_fpu_sqrtd
321
  { 1, 5, 6, 63, 65 }, // 12 IIC_fpu_sqrts
322
  { 1, 5, 6, 65, 67 }, // 13 IIC_fpu_stod
323
  { 1, 6, 7, 67, 69 }, // 14 IIC_ldd
324
  { 1, 6, 7, 69, 71 }, // 15 IIC_iu_or_fpu_instr
325
  { 1, 4, 5, 71, 73 }, // 16 IIC_iu_div
326
  { 1, 4, 5, 73, 75 }, // 17 IIC_smac_umac
327
  { 1, 4, 5, 75, 77 }, // 18 IIC_iu_smul
328
  { 1, 6, 7, 77, 79 }, // 19 IIC_st
329
  { 1, 6, 7, 79, 81 }, // 20 IIC_std
330
  { 1, 4, 5, 81, 83 }, // 21 IIC_iu_umul
331
  { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
332
};
333
334
static const llvm::InstrItinerary LEON4Itineraries[] = {
335
  { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
336
  { 1, 7, 8, 83, 85 }, // 1 IIC_iu_instr
337
  { 1, 8, 9, 85, 87 }, // 2 IIC_fpu_normal_instr
338
  { 1, 9, 10, 87, 89 }, // 3 IIC_jmp_or_call
339
  { 1, 8, 9, 89, 91 }, // 4 IIC_fpu_abs
340
  { 1, 8, 9, 91, 93 }, // 5 IIC_fpu_fast_instr
341
  { 1, 8, 9, 93, 95 }, // 6 IIC_fpu_divd
342
  { 1, 8, 9, 95, 97 }, // 7 IIC_fpu_divs
343
  { 1, 8, 9, 97, 99 }, // 8 IIC_fpu_muld
344
  { 1, 8, 9, 99, 101 }, // 9 IIC_fpu_muls
345
  { 1, 8, 9, 101, 103 }, // 10 IIC_fpu_negs
346
  { 1, 8, 9, 103, 105 }, // 11 IIC_fpu_sqrtd
347
  { 1, 8, 9, 105, 107 }, // 12 IIC_fpu_sqrts
348
  { 1, 8, 9, 107, 109 }, // 13 IIC_fpu_stod
349
  { 1, 9, 10, 109, 111 }, // 14 IIC_ldd
350
  { 1, 9, 10, 111, 113 }, // 15 IIC_iu_or_fpu_instr
351
  { 1, 7, 8, 113, 115 }, // 16 IIC_iu_div
352
  { 1, 7, 8, 115, 117 }, // 17 IIC_smac_umac
353
  { 1, 7, 8, 117, 119 }, // 18 IIC_iu_smul
354
  { 1, 9, 10, 119, 121 }, // 19 IIC_st
355
  { 1, 9, 10, 121, 123 }, // 20 IIC_std
356
  { 1, 7, 8, 123, 125 }, // 21 IIC_iu_umul
357
  { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
358
};
359
360
// ===============================================================
361
// Data tables for the new per-operand machine model.
362
363
// {ProcResourceIdx, Cycles}
364
extern const llvm::MCWriteProcResEntry SparcWriteProcResTable[] = {
365
  { 0,  0}, // Invalid
366
}; // SparcWriteProcResTable
367
368
// {Cycles, WriteResourceID}
369
extern const llvm::MCWriteLatencyEntry SparcWriteLatencyTable[] = {
370
  { 0,  0}, // Invalid
371
}; // SparcWriteLatencyTable
372
373
// {UseIdx, WriteResourceID, Cycles}
374
extern const llvm::MCReadAdvanceEntry SparcReadAdvanceTable[] = {
375
  {0,  0,  0}, // Invalid
376
}; // SparcReadAdvanceTable
377
378
static const llvm::MCSchedModel NoSchedModel = {
379
  MCSchedModel::DefaultIssueWidth,
380
  MCSchedModel::DefaultMicroOpBufferSize,
381
  MCSchedModel::DefaultLoopMicroOpBufferSize,
382
  MCSchedModel::DefaultLoadLatency,
383
  MCSchedModel::DefaultHighLatency,
384
  MCSchedModel::DefaultMispredictPenalty,
385
  false, // PostRAScheduler
386
  false, // CompleteModel
387
  0, // Processor ID
388
  nullptr, nullptr, 0, 0, // No instruction-level machine model.
389
  nullptr, // No Itinerary
390
  nullptr // No extra processor descriptor
391
};
392
393
static const llvm::MCSchedModel LEON2ItinerariesModel = {
394
  MCSchedModel::DefaultIssueWidth,
395
  MCSchedModel::DefaultMicroOpBufferSize,
396
  MCSchedModel::DefaultLoopMicroOpBufferSize,
397
  MCSchedModel::DefaultLoadLatency,
398
  MCSchedModel::DefaultHighLatency,
399
  MCSchedModel::DefaultMispredictPenalty,
400
  false, // PostRAScheduler
401
  false, // CompleteModel
402
  1, // Processor ID
403
  nullptr, nullptr, 0, 0, // No instruction-level machine model.
404
  LEON2Itineraries,
405
  nullptr // No extra processor descriptor
406
};
407
408
static const llvm::MCSchedModel LEON3ItinerariesModel = {
409
  MCSchedModel::DefaultIssueWidth,
410
  MCSchedModel::DefaultMicroOpBufferSize,
411
  MCSchedModel::DefaultLoopMicroOpBufferSize,
412
  MCSchedModel::DefaultLoadLatency,
413
  MCSchedModel::DefaultHighLatency,
414
  MCSchedModel::DefaultMispredictPenalty,
415
  false, // PostRAScheduler
416
  false, // CompleteModel
417
  2, // Processor ID
418
  nullptr, nullptr, 0, 0, // No instruction-level machine model.
419
  LEON3Itineraries,
420
  nullptr // No extra processor descriptor
421
};
422
423
static const llvm::MCSchedModel LEON4ItinerariesModel = {
424
  MCSchedModel::DefaultIssueWidth,
425
  MCSchedModel::DefaultMicroOpBufferSize,
426
  MCSchedModel::DefaultLoopMicroOpBufferSize,
427
  MCSchedModel::DefaultLoadLatency,
428
  MCSchedModel::DefaultHighLatency,
429
  MCSchedModel::DefaultMispredictPenalty,
430
  false, // PostRAScheduler
431
  false, // CompleteModel
432
  3, // Processor ID
433
  nullptr, nullptr, 0, 0, // No instruction-level machine model.
434
  LEON4Itineraries,
435
  nullptr // No extra processor descriptor
436
};
437
438
// Sorted (by key) array of itineraries for CPU subtype.
439
extern const llvm::SubtargetInfoKV SparcProcSchedKV[] = {
440
  { "at697e", (const void *)&LEON2ItinerariesModel },
441
  { "at697f", (const void *)&LEON2ItinerariesModel },
442
  { "f934", (const void *)&NoSchedModel },
443
  { "generic", (const void *)&NoSchedModel },
444
  { "gr712rc", (const void *)&LEON3ItinerariesModel },
445
  { "gr740", (const void *)&LEON4ItinerariesModel },
446
  { "hypersparc", (const void *)&NoSchedModel },
447
  { "leon2", (const void *)&LEON2ItinerariesModel },
448
  { "leon3", (const void *)&LEON3ItinerariesModel },
449
  { "leon4", (const void *)&LEON4ItinerariesModel },
450
  { "ma2080", (const void *)&NoSchedModel },
451
  { "ma2085", (const void *)&NoSchedModel },
452
  { "ma2100", (const void *)&NoSchedModel },
453
  { "ma2150", (const void *)&NoSchedModel },
454
  { "ma2155", (const void *)&NoSchedModel },
455
  { "ma2450", (const void *)&NoSchedModel },
456
  { "ma2455", (const void *)&NoSchedModel },
457
  { "ma2480", (const void *)&NoSchedModel },
458
  { "ma2485", (const void *)&NoSchedModel },
459
  { "ma2x5x", (const void *)&NoSchedModel },
460
  { "ma2x8x", (const void *)&NoSchedModel },
461
  { "myriad2", (const void *)&NoSchedModel },
462
  { "myriad2.1", (const void *)&NoSchedModel },
463
  { "myriad2.2", (const void *)&NoSchedModel },
464
  { "myriad2.3", (const void *)&NoSchedModel },
465
  { "niagara", (const void *)&NoSchedModel },
466
  { "niagara2", (const void *)&NoSchedModel },
467
  { "niagara3", (const void *)&NoSchedModel },
468
  { "niagara4", (const void *)&NoSchedModel },
469
  { "sparclet", (const void *)&NoSchedModel },
470
  { "sparclite", (const void *)&NoSchedModel },
471
  { "sparclite86x", (const void *)&NoSchedModel },
472
  { "supersparc", (const void *)&NoSchedModel },
473
  { "tsc701", (const void *)&NoSchedModel },
474
  { "ultrasparc", (const void *)&NoSchedModel },
475
  { "ultrasparc3", (const void *)&NoSchedModel },
476
  { "ut699", (const void *)&LEON3ItinerariesModel },
477
  { "v7", (const void *)&NoSchedModel },
478
  { "v8", (const void *)&NoSchedModel },
479
  { "v9", (const void *)&NoSchedModel },
480
};
481
482
#undef DBGFIELD
483
namespace Sparc_MC {
484
unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
485
0
    const MCInst *MI, unsigned CPUID) {
486
0
  // Don't know how to resolve this scheduling class.
487
0
  return 0;
488
0
}
489
} // end of namespace Sparc_MC
490
491
struct SparcGenMCSubtargetInfo : public MCSubtargetInfo {
492
  SparcGenMCSubtargetInfo(const Triple &TT, 
493
    StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
494
    ArrayRef<SubtargetFeatureKV> PD,
495
    const SubtargetInfoKV *ProcSched,
496
    const MCWriteProcResEntry *WPR,
497
    const MCWriteLatencyEntry *WL,
498
    const MCReadAdvanceEntry *RA, const InstrStage *IS,
499
    const unsigned *OC, const unsigned *FP) :
500
      MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched,
501
287
                      WPR, WL, RA, IS, OC, FP) { }
502
503
  unsigned resolveVariantSchedClass(unsigned SchedClass,
504
0
      const MCInst *MI, unsigned CPUID) const override {
505
0
    return Sparc_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID); 
506
0
  }
507
};
508
509
287
static inline MCSubtargetInfo *createSparcMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) {
510
287
  return new SparcGenMCSubtargetInfo(TT, CPU, FS, SparcFeatureKV, SparcSubTypeKV, 
511
287
                      SparcProcSchedKV, SparcWriteProcResTable, SparcWriteLatencyTable, SparcReadAdvanceTable, 
512
287
                      SparcStages, SparcOperandCycles, SparcForwardingPaths);
513
287
}
514
515
} // end namespace llvm
516
517
#endif // GET_SUBTARGETINFO_MC_DESC
518
519
520
#ifdef GET_SUBTARGETINFO_TARGET_DESC
521
#undef GET_SUBTARGETINFO_TARGET_DESC
522
523
#include "llvm/Support/Debug.h"
524
#include "llvm/Support/raw_ostream.h"
525
526
// ParseSubtargetFeatures - Parses features string setting specified
527
// subtarget options.
528
413
void llvm::SparcSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {
529
413
  LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
530
413
  LLVM_DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n");
531
413
  InitMCProcessorInfo(CPU, FS);
532
413
  const FeatureBitset& Bits = getFeatureBits();
533
413
  if (Bits[Sparc::DetectRoundChange]) 
DetectRoundChange = true2
;
534
413
  if (Bits[Sparc::FeatureHardQuad]) 
HasHardQuad = true4
;
535
413
  if (Bits[Sparc::FeatureLeon]) 
IsLeon = true66
;
536
413
  if (Bits[Sparc::FeatureNoFMULS]) 
HasNoFMULS = true8
;
537
413
  if (Bits[Sparc::FeatureNoFSMULD]) 
HasNoFSMULD = true10
;
538
413
  if (Bits[Sparc::FeatureSoftFloat]) 
UseSoftFloat = true7
;
539
413
  if (Bits[Sparc::FeatureSoftMulDiv]) 
UseSoftMulDiv = true2
;
540
413
  if (Bits[Sparc::FeatureV8Deprecated]) 
V8DeprecatedInsts = true12
;
541
413
  if (Bits[Sparc::FeatureV9]) 
IsV9 = true149
;
542
413
  if (Bits[Sparc::FeatureVIS]) 
IsVIS = true12
;
543
413
  if (Bits[Sparc::FeatureVIS2]) 
IsVIS2 = true10
;
544
413
  if (Bits[Sparc::FeatureVIS3]) 
IsVIS3 = true2
;
545
413
  if (Bits[Sparc::FixAllFDIVSQRT]) 
FixAllFDIVSQRT = true6
;
546
413
  if (Bits[Sparc::InsertNOPLoad]) 
InsertNOPLoad = true6
;
547
413
  if (Bits[Sparc::LeonCASA]) 
HasLeonCasa = true44
;
548
413
  if (Bits[Sparc::UMACSMACSupport]) 
HasUmacSmac = true24
;
549
413
  if (Bits[Sparc::UsePopc]) 
UsePopc = true14
;
550
413
}
551
#endif // GET_SUBTARGETINFO_TARGET_DESC
552
553
554
#ifdef GET_SUBTARGETINFO_HEADER
555
#undef GET_SUBTARGETINFO_HEADER
556
557
namespace llvm {
558
class DFAPacketizer;
559
namespace Sparc_MC {
560
unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
561
}
562
563
struct SparcGenSubtargetInfo : public TargetSubtargetInfo {
564
  explicit SparcGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS);
565
public:
566
  unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
567
  unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
568
  DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
569
};
570
} // end namespace llvm
571
572
#endif // GET_SUBTARGETINFO_HEADER
573
574
575
#ifdef GET_SUBTARGETINFO_CTOR
576
#undef GET_SUBTARGETINFO_CTOR
577
578
#include "llvm/CodeGen/TargetSchedule.h"
579
580
namespace llvm {
581
extern const llvm::SubtargetFeatureKV SparcFeatureKV[];
582
extern const llvm::SubtargetFeatureKV SparcSubTypeKV[];
583
extern const llvm::SubtargetInfoKV SparcProcSchedKV[];
584
extern const llvm::MCWriteProcResEntry SparcWriteProcResTable[];
585
extern const llvm::MCWriteLatencyEntry SparcWriteLatencyTable[];
586
extern const llvm::MCReadAdvanceEntry SparcReadAdvanceTable[];
587
extern const llvm::InstrStage SparcStages[];
588
extern const unsigned SparcOperandCycles[];
589
extern const unsigned SparcForwardingPaths[];
590
SparcGenSubtargetInfo::SparcGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
591
  : TargetSubtargetInfo(TT, CPU, FS, makeArrayRef(SparcFeatureKV, 17), makeArrayRef(SparcSubTypeKV, 40), 
592
                        SparcProcSchedKV, SparcWriteProcResTable, SparcWriteLatencyTable, SparcReadAdvanceTable, 
593
413
                        SparcStages, SparcOperandCycles, SparcForwardingPaths) {}
594
595
unsigned SparcGenSubtargetInfo
596
0
::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
597
0
  report_fatal_error("Expected a variant SchedClass");
598
0
} // SparcGenSubtargetInfo::resolveSchedClass
599
600
unsigned SparcGenSubtargetInfo
601
0
::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
602
0
  return Sparc_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
603
0
} // SparcGenSubtargetInfo::resolveVariantSchedClass
604
} // end namespace llvm
605
606
#endif // GET_SUBTARGETINFO_CTOR
607