/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/SystemZ/SystemZGenInstrInfo.inc
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1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Target Instruction Enum Values and Descriptors *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | #ifdef GET_INSTRINFO_ENUM |
10 | | #undef GET_INSTRINFO_ENUM |
11 | | namespace llvm { |
12 | | |
13 | | namespace SystemZ { |
14 | | enum { |
15 | | PHI = 0, |
16 | | INLINEASM = 1, |
17 | | INLINEASM_BR = 2, |
18 | | CFI_INSTRUCTION = 3, |
19 | | EH_LABEL = 4, |
20 | | GC_LABEL = 5, |
21 | | ANNOTATION_LABEL = 6, |
22 | | KILL = 7, |
23 | | EXTRACT_SUBREG = 8, |
24 | | INSERT_SUBREG = 9, |
25 | | IMPLICIT_DEF = 10, |
26 | | SUBREG_TO_REG = 11, |
27 | | COPY_TO_REGCLASS = 12, |
28 | | DBG_VALUE = 13, |
29 | | DBG_LABEL = 14, |
30 | | REG_SEQUENCE = 15, |
31 | | COPY = 16, |
32 | | BUNDLE = 17, |
33 | | LIFETIME_START = 18, |
34 | | LIFETIME_END = 19, |
35 | | STACKMAP = 20, |
36 | | FENTRY_CALL = 21, |
37 | | PATCHPOINT = 22, |
38 | | LOAD_STACK_GUARD = 23, |
39 | | STATEPOINT = 24, |
40 | | LOCAL_ESCAPE = 25, |
41 | | FAULTING_OP = 26, |
42 | | PATCHABLE_OP = 27, |
43 | | PATCHABLE_FUNCTION_ENTER = 28, |
44 | | PATCHABLE_RET = 29, |
45 | | PATCHABLE_FUNCTION_EXIT = 30, |
46 | | PATCHABLE_TAIL_CALL = 31, |
47 | | PATCHABLE_EVENT_CALL = 32, |
48 | | PATCHABLE_TYPED_EVENT_CALL = 33, |
49 | | ICALL_BRANCH_FUNNEL = 34, |
50 | | G_ADD = 35, |
51 | | G_SUB = 36, |
52 | | G_MUL = 37, |
53 | | G_SDIV = 38, |
54 | | G_UDIV = 39, |
55 | | G_SREM = 40, |
56 | | G_UREM = 41, |
57 | | G_AND = 42, |
58 | | G_OR = 43, |
59 | | G_XOR = 44, |
60 | | G_IMPLICIT_DEF = 45, |
61 | | G_PHI = 46, |
62 | | G_FRAME_INDEX = 47, |
63 | | G_GLOBAL_VALUE = 48, |
64 | | G_EXTRACT = 49, |
65 | | G_UNMERGE_VALUES = 50, |
66 | | G_INSERT = 51, |
67 | | G_MERGE_VALUES = 52, |
68 | | G_BUILD_VECTOR = 53, |
69 | | G_BUILD_VECTOR_TRUNC = 54, |
70 | | G_CONCAT_VECTORS = 55, |
71 | | G_PTRTOINT = 56, |
72 | | G_INTTOPTR = 57, |
73 | | G_BITCAST = 58, |
74 | | G_INTRINSIC_TRUNC = 59, |
75 | | G_INTRINSIC_ROUND = 60, |
76 | | G_LOAD = 61, |
77 | | G_SEXTLOAD = 62, |
78 | | G_ZEXTLOAD = 63, |
79 | | G_STORE = 64, |
80 | | G_ATOMIC_CMPXCHG_WITH_SUCCESS = 65, |
81 | | G_ATOMIC_CMPXCHG = 66, |
82 | | G_ATOMICRMW_XCHG = 67, |
83 | | G_ATOMICRMW_ADD = 68, |
84 | | G_ATOMICRMW_SUB = 69, |
85 | | G_ATOMICRMW_AND = 70, |
86 | | G_ATOMICRMW_NAND = 71, |
87 | | G_ATOMICRMW_OR = 72, |
88 | | G_ATOMICRMW_XOR = 73, |
89 | | G_ATOMICRMW_MAX = 74, |
90 | | G_ATOMICRMW_MIN = 75, |
91 | | G_ATOMICRMW_UMAX = 76, |
92 | | G_ATOMICRMW_UMIN = 77, |
93 | | G_BRCOND = 78, |
94 | | G_BRINDIRECT = 79, |
95 | | G_INTRINSIC = 80, |
96 | | G_INTRINSIC_W_SIDE_EFFECTS = 81, |
97 | | G_ANYEXT = 82, |
98 | | G_TRUNC = 83, |
99 | | G_CONSTANT = 84, |
100 | | G_FCONSTANT = 85, |
101 | | G_VASTART = 86, |
102 | | G_VAARG = 87, |
103 | | G_SEXT = 88, |
104 | | G_ZEXT = 89, |
105 | | G_SHL = 90, |
106 | | G_LSHR = 91, |
107 | | G_ASHR = 92, |
108 | | G_ICMP = 93, |
109 | | G_FCMP = 94, |
110 | | G_SELECT = 95, |
111 | | G_UADDO = 96, |
112 | | G_UADDE = 97, |
113 | | G_USUBO = 98, |
114 | | G_USUBE = 99, |
115 | | G_SADDO = 100, |
116 | | G_SADDE = 101, |
117 | | G_SSUBO = 102, |
118 | | G_SSUBE = 103, |
119 | | G_UMULO = 104, |
120 | | G_SMULO = 105, |
121 | | G_UMULH = 106, |
122 | | G_SMULH = 107, |
123 | | G_FADD = 108, |
124 | | G_FSUB = 109, |
125 | | G_FMUL = 110, |
126 | | G_FMA = 111, |
127 | | G_FDIV = 112, |
128 | | G_FREM = 113, |
129 | | G_FPOW = 114, |
130 | | G_FEXP = 115, |
131 | | G_FEXP2 = 116, |
132 | | G_FLOG = 117, |
133 | | G_FLOG2 = 118, |
134 | | G_FLOG10 = 119, |
135 | | G_FNEG = 120, |
136 | | G_FPEXT = 121, |
137 | | G_FPTRUNC = 122, |
138 | | G_FPTOSI = 123, |
139 | | G_FPTOUI = 124, |
140 | | G_SITOFP = 125, |
141 | | G_UITOFP = 126, |
142 | | G_FABS = 127, |
143 | | G_FCANONICALIZE = 128, |
144 | | G_GEP = 129, |
145 | | G_PTR_MASK = 130, |
146 | | G_BR = 131, |
147 | | G_INSERT_VECTOR_ELT = 132, |
148 | | G_EXTRACT_VECTOR_ELT = 133, |
149 | | G_SHUFFLE_VECTOR = 134, |
150 | | G_CTTZ = 135, |
151 | | G_CTTZ_ZERO_UNDEF = 136, |
152 | | G_CTLZ = 137, |
153 | | G_CTLZ_ZERO_UNDEF = 138, |
154 | | G_CTPOP = 139, |
155 | | G_BSWAP = 140, |
156 | | G_FCEIL = 141, |
157 | | G_FCOS = 142, |
158 | | G_FSIN = 143, |
159 | | G_FSQRT = 144, |
160 | | G_FFLOOR = 145, |
161 | | G_ADDRSPACE_CAST = 146, |
162 | | G_BLOCK_ADDR = 147, |
163 | | ADJCALLSTACKDOWN = 148, |
164 | | ADJCALLSTACKUP = 149, |
165 | | ADJDYNALLOC = 150, |
166 | | AEXT128 = 151, |
167 | | AFIMux = 152, |
168 | | AHIMux = 153, |
169 | | AHIMuxK = 154, |
170 | | ATOMIC_CMP_SWAPW = 155, |
171 | | ATOMIC_LOADW_AFI = 156, |
172 | | ATOMIC_LOADW_AR = 157, |
173 | | ATOMIC_LOADW_MAX = 158, |
174 | | ATOMIC_LOADW_MIN = 159, |
175 | | ATOMIC_LOADW_NILH = 160, |
176 | | ATOMIC_LOADW_NILHi = 161, |
177 | | ATOMIC_LOADW_NR = 162, |
178 | | ATOMIC_LOADW_NRi = 163, |
179 | | ATOMIC_LOADW_OILH = 164, |
180 | | ATOMIC_LOADW_OR = 165, |
181 | | ATOMIC_LOADW_SR = 166, |
182 | | ATOMIC_LOADW_UMAX = 167, |
183 | | ATOMIC_LOADW_UMIN = 168, |
184 | | ATOMIC_LOADW_XILF = 169, |
185 | | ATOMIC_LOADW_XR = 170, |
186 | | ATOMIC_LOAD_AFI = 171, |
187 | | ATOMIC_LOAD_AGFI = 172, |
188 | | ATOMIC_LOAD_AGHI = 173, |
189 | | ATOMIC_LOAD_AGR = 174, |
190 | | ATOMIC_LOAD_AHI = 175, |
191 | | ATOMIC_LOAD_AR = 176, |
192 | | ATOMIC_LOAD_MAX_32 = 177, |
193 | | ATOMIC_LOAD_MAX_64 = 178, |
194 | | ATOMIC_LOAD_MIN_32 = 179, |
195 | | ATOMIC_LOAD_MIN_64 = 180, |
196 | | ATOMIC_LOAD_NGR = 181, |
197 | | ATOMIC_LOAD_NGRi = 182, |
198 | | ATOMIC_LOAD_NIHF64 = 183, |
199 | | ATOMIC_LOAD_NIHF64i = 184, |
200 | | ATOMIC_LOAD_NIHH64 = 185, |
201 | | ATOMIC_LOAD_NIHH64i = 186, |
202 | | ATOMIC_LOAD_NIHL64 = 187, |
203 | | ATOMIC_LOAD_NIHL64i = 188, |
204 | | ATOMIC_LOAD_NILF = 189, |
205 | | ATOMIC_LOAD_NILF64 = 190, |
206 | | ATOMIC_LOAD_NILF64i = 191, |
207 | | ATOMIC_LOAD_NILFi = 192, |
208 | | ATOMIC_LOAD_NILH = 193, |
209 | | ATOMIC_LOAD_NILH64 = 194, |
210 | | ATOMIC_LOAD_NILH64i = 195, |
211 | | ATOMIC_LOAD_NILHi = 196, |
212 | | ATOMIC_LOAD_NILL = 197, |
213 | | ATOMIC_LOAD_NILL64 = 198, |
214 | | ATOMIC_LOAD_NILL64i = 199, |
215 | | ATOMIC_LOAD_NILLi = 200, |
216 | | ATOMIC_LOAD_NR = 201, |
217 | | ATOMIC_LOAD_NRi = 202, |
218 | | ATOMIC_LOAD_OGR = 203, |
219 | | ATOMIC_LOAD_OIHF64 = 204, |
220 | | ATOMIC_LOAD_OIHH64 = 205, |
221 | | ATOMIC_LOAD_OIHL64 = 206, |
222 | | ATOMIC_LOAD_OILF = 207, |
223 | | ATOMIC_LOAD_OILF64 = 208, |
224 | | ATOMIC_LOAD_OILH = 209, |
225 | | ATOMIC_LOAD_OILH64 = 210, |
226 | | ATOMIC_LOAD_OILL = 211, |
227 | | ATOMIC_LOAD_OILL64 = 212, |
228 | | ATOMIC_LOAD_OR = 213, |
229 | | ATOMIC_LOAD_SGR = 214, |
230 | | ATOMIC_LOAD_SR = 215, |
231 | | ATOMIC_LOAD_UMAX_32 = 216, |
232 | | ATOMIC_LOAD_UMAX_64 = 217, |
233 | | ATOMIC_LOAD_UMIN_32 = 218, |
234 | | ATOMIC_LOAD_UMIN_64 = 219, |
235 | | ATOMIC_LOAD_XGR = 220, |
236 | | ATOMIC_LOAD_XIHF64 = 221, |
237 | | ATOMIC_LOAD_XILF = 222, |
238 | | ATOMIC_LOAD_XILF64 = 223, |
239 | | ATOMIC_LOAD_XR = 224, |
240 | | ATOMIC_SWAPW = 225, |
241 | | ATOMIC_SWAP_32 = 226, |
242 | | ATOMIC_SWAP_64 = 227, |
243 | | CFIMux = 228, |
244 | | CGIBCall = 229, |
245 | | CGIBReturn = 230, |
246 | | CGRBCall = 231, |
247 | | CGRBReturn = 232, |
248 | | CHIMux = 233, |
249 | | CIBCall = 234, |
250 | | CIBReturn = 235, |
251 | | CLCLoop = 236, |
252 | | CLCSequence = 237, |
253 | | CLFIMux = 238, |
254 | | CLGIBCall = 239, |
255 | | CLGIBReturn = 240, |
256 | | CLGRBCall = 241, |
257 | | CLGRBReturn = 242, |
258 | | CLIBCall = 243, |
259 | | CLIBReturn = 244, |
260 | | CLMux = 245, |
261 | | CLRBCall = 246, |
262 | | CLRBReturn = 247, |
263 | | CLSTLoop = 248, |
264 | | CMux = 249, |
265 | | CRBCall = 250, |
266 | | CRBReturn = 251, |
267 | | CallBASR = 252, |
268 | | CallBCR = 253, |
269 | | CallBR = 254, |
270 | | CallBRASL = 255, |
271 | | CallBRCL = 256, |
272 | | CallJG = 257, |
273 | | CondReturn = 258, |
274 | | CondStore16 = 259, |
275 | | CondStore16Inv = 260, |
276 | | CondStore16Mux = 261, |
277 | | CondStore16MuxInv = 262, |
278 | | CondStore32 = 263, |
279 | | CondStore32Inv = 264, |
280 | | CondStore32Mux = 265, |
281 | | CondStore32MuxInv = 266, |
282 | | CondStore64 = 267, |
283 | | CondStore64Inv = 268, |
284 | | CondStore8 = 269, |
285 | | CondStore8Inv = 270, |
286 | | CondStore8Mux = 271, |
287 | | CondStore8MuxInv = 272, |
288 | | CondStoreF32 = 273, |
289 | | CondStoreF32Inv = 274, |
290 | | CondStoreF64 = 275, |
291 | | CondStoreF64Inv = 276, |
292 | | CondTrap = 277, |
293 | | GOT = 278, |
294 | | IIFMux = 279, |
295 | | IIHF64 = 280, |
296 | | IIHH64 = 281, |
297 | | IIHL64 = 282, |
298 | | IIHMux = 283, |
299 | | IILF64 = 284, |
300 | | IILH64 = 285, |
301 | | IILL64 = 286, |
302 | | IILMux = 287, |
303 | | L128 = 288, |
304 | | LBMux = 289, |
305 | | LEFR = 290, |
306 | | LFER = 291, |
307 | | LHIMux = 292, |
308 | | LHMux = 293, |
309 | | LLCMux = 294, |
310 | | LLCRMux = 295, |
311 | | LLHMux = 296, |
312 | | LLHRMux = 297, |
313 | | LMux = 298, |
314 | | LOCHIMux = 299, |
315 | | LOCMux = 300, |
316 | | LOCRMux = 301, |
317 | | LRMux = 302, |
318 | | LTDBRCompare_VecPseudo = 303, |
319 | | LTEBRCompare_VecPseudo = 304, |
320 | | LTXBRCompare_VecPseudo = 305, |
321 | | LX = 306, |
322 | | MVCLoop = 307, |
323 | | MVCSequence = 308, |
324 | | MVSTLoop = 309, |
325 | | MemBarrier = 310, |
326 | | NCLoop = 311, |
327 | | NCSequence = 312, |
328 | | NIFMux = 313, |
329 | | NIHF64 = 314, |
330 | | NIHH64 = 315, |
331 | | NIHL64 = 316, |
332 | | NIHMux = 317, |
333 | | NILF64 = 318, |
334 | | NILH64 = 319, |
335 | | NILL64 = 320, |
336 | | NILMux = 321, |
337 | | OCLoop = 322, |
338 | | OCSequence = 323, |
339 | | OIFMux = 324, |
340 | | OIHF64 = 325, |
341 | | OIHH64 = 326, |
342 | | OIHL64 = 327, |
343 | | OIHMux = 328, |
344 | | OILF64 = 329, |
345 | | OILH64 = 330, |
346 | | OILL64 = 331, |
347 | | OILMux = 332, |
348 | | PAIR128 = 333, |
349 | | RISBHH = 334, |
350 | | RISBHL = 335, |
351 | | RISBLH = 336, |
352 | | RISBLL = 337, |
353 | | RISBMux = 338, |
354 | | Return = 339, |
355 | | SRSTLoop = 340, |
356 | | ST128 = 341, |
357 | | STCMux = 342, |
358 | | STHMux = 343, |
359 | | STMux = 344, |
360 | | STOCMux = 345, |
361 | | STX = 346, |
362 | | Select32 = 347, |
363 | | Select64 = 348, |
364 | | SelectF128 = 349, |
365 | | SelectF32 = 350, |
366 | | SelectF64 = 351, |
367 | | SelectVR128 = 352, |
368 | | SelectVR32 = 353, |
369 | | SelectVR64 = 354, |
370 | | Serialize = 355, |
371 | | TBEGIN_nofloat = 356, |
372 | | TLS_GDCALL = 357, |
373 | | TLS_LDCALL = 358, |
374 | | TMHH64 = 359, |
375 | | TMHL64 = 360, |
376 | | TMHMux = 361, |
377 | | TMLH64 = 362, |
378 | | TMLL64 = 363, |
379 | | TMLMux = 364, |
380 | | Trap = 365, |
381 | | VL32 = 366, |
382 | | VL64 = 367, |
383 | | VLR32 = 368, |
384 | | VLR64 = 369, |
385 | | VLVGP32 = 370, |
386 | | VST32 = 371, |
387 | | VST64 = 372, |
388 | | XCLoop = 373, |
389 | | XCSequence = 374, |
390 | | XIFMux = 375, |
391 | | XIHF64 = 376, |
392 | | XILF64 = 377, |
393 | | ZEXT128 = 378, |
394 | | A = 379, |
395 | | AD = 380, |
396 | | ADB = 381, |
397 | | ADBR = 382, |
398 | | ADR = 383, |
399 | | ADTR = 384, |
400 | | ADTRA = 385, |
401 | | AE = 386, |
402 | | AEB = 387, |
403 | | AEBR = 388, |
404 | | AER = 389, |
405 | | AFI = 390, |
406 | | AG = 391, |
407 | | AGF = 392, |
408 | | AGFI = 393, |
409 | | AGFR = 394, |
410 | | AGH = 395, |
411 | | AGHI = 396, |
412 | | AGHIK = 397, |
413 | | AGR = 398, |
414 | | AGRK = 399, |
415 | | AGSI = 400, |
416 | | AH = 401, |
417 | | AHHHR = 402, |
418 | | AHHLR = 403, |
419 | | AHI = 404, |
420 | | AHIK = 405, |
421 | | AHY = 406, |
422 | | AIH = 407, |
423 | | AL = 408, |
424 | | ALC = 409, |
425 | | ALCG = 410, |
426 | | ALCGR = 411, |
427 | | ALCR = 412, |
428 | | ALFI = 413, |
429 | | ALG = 414, |
430 | | ALGF = 415, |
431 | | ALGFI = 416, |
432 | | ALGFR = 417, |
433 | | ALGHSIK = 418, |
434 | | ALGR = 419, |
435 | | ALGRK = 420, |
436 | | ALGSI = 421, |
437 | | ALHHHR = 422, |
438 | | ALHHLR = 423, |
439 | | ALHSIK = 424, |
440 | | ALR = 425, |
441 | | ALRK = 426, |
442 | | ALSI = 427, |
443 | | ALSIH = 428, |
444 | | ALSIHN = 429, |
445 | | ALY = 430, |
446 | | AP = 431, |
447 | | AR = 432, |
448 | | ARK = 433, |
449 | | ASI = 434, |
450 | | AU = 435, |
451 | | AUR = 436, |
452 | | AW = 437, |
453 | | AWR = 438, |
454 | | AXBR = 439, |
455 | | AXR = 440, |
456 | | AXTR = 441, |
457 | | AXTRA = 442, |
458 | | AY = 443, |
459 | | B = 444, |
460 | | BAKR = 445, |
461 | | BAL = 446, |
462 | | BALR = 447, |
463 | | BAS = 448, |
464 | | BASR = 449, |
465 | | BASSM = 450, |
466 | | BAsmE = 451, |
467 | | BAsmH = 452, |
468 | | BAsmHE = 453, |
469 | | BAsmL = 454, |
470 | | BAsmLE = 455, |
471 | | BAsmLH = 456, |
472 | | BAsmM = 457, |
473 | | BAsmNE = 458, |
474 | | BAsmNH = 459, |
475 | | BAsmNHE = 460, |
476 | | BAsmNL = 461, |
477 | | BAsmNLE = 462, |
478 | | BAsmNLH = 463, |
479 | | BAsmNM = 464, |
480 | | BAsmNO = 465, |
481 | | BAsmNP = 466, |
482 | | BAsmNZ = 467, |
483 | | BAsmO = 468, |
484 | | BAsmP = 469, |
485 | | BAsmZ = 470, |
486 | | BC = 471, |
487 | | BCAsm = 472, |
488 | | BCR = 473, |
489 | | BCRAsm = 474, |
490 | | BCT = 475, |
491 | | BCTG = 476, |
492 | | BCTGR = 477, |
493 | | BCTR = 478, |
494 | | BI = 479, |
495 | | BIAsmE = 480, |
496 | | BIAsmH = 481, |
497 | | BIAsmHE = 482, |
498 | | BIAsmL = 483, |
499 | | BIAsmLE = 484, |
500 | | BIAsmLH = 485, |
501 | | BIAsmM = 486, |
502 | | BIAsmNE = 487, |
503 | | BIAsmNH = 488, |
504 | | BIAsmNHE = 489, |
505 | | BIAsmNL = 490, |
506 | | BIAsmNLE = 491, |
507 | | BIAsmNLH = 492, |
508 | | BIAsmNM = 493, |
509 | | BIAsmNO = 494, |
510 | | BIAsmNP = 495, |
511 | | BIAsmNZ = 496, |
512 | | BIAsmO = 497, |
513 | | BIAsmP = 498, |
514 | | BIAsmZ = 499, |
515 | | BIC = 500, |
516 | | BICAsm = 501, |
517 | | BPP = 502, |
518 | | BPRP = 503, |
519 | | BR = 504, |
520 | | BRAS = 505, |
521 | | BRASL = 506, |
522 | | BRAsmE = 507, |
523 | | BRAsmH = 508, |
524 | | BRAsmHE = 509, |
525 | | BRAsmL = 510, |
526 | | BRAsmLE = 511, |
527 | | BRAsmLH = 512, |
528 | | BRAsmM = 513, |
529 | | BRAsmNE = 514, |
530 | | BRAsmNH = 515, |
531 | | BRAsmNHE = 516, |
532 | | BRAsmNL = 517, |
533 | | BRAsmNLE = 518, |
534 | | BRAsmNLH = 519, |
535 | | BRAsmNM = 520, |
536 | | BRAsmNO = 521, |
537 | | BRAsmNP = 522, |
538 | | BRAsmNZ = 523, |
539 | | BRAsmO = 524, |
540 | | BRAsmP = 525, |
541 | | BRAsmZ = 526, |
542 | | BRC = 527, |
543 | | BRCAsm = 528, |
544 | | BRCL = 529, |
545 | | BRCLAsm = 530, |
546 | | BRCT = 531, |
547 | | BRCTG = 532, |
548 | | BRCTH = 533, |
549 | | BRXH = 534, |
550 | | BRXHG = 535, |
551 | | BRXLE = 536, |
552 | | BRXLG = 537, |
553 | | BSA = 538, |
554 | | BSG = 539, |
555 | | BSM = 540, |
556 | | BXH = 541, |
557 | | BXHG = 542, |
558 | | BXLE = 543, |
559 | | BXLEG = 544, |
560 | | C = 545, |
561 | | CD = 546, |
562 | | CDB = 547, |
563 | | CDBR = 548, |
564 | | CDFBR = 549, |
565 | | CDFBRA = 550, |
566 | | CDFR = 551, |
567 | | CDFTR = 552, |
568 | | CDGBR = 553, |
569 | | CDGBRA = 554, |
570 | | CDGR = 555, |
571 | | CDGTR = 556, |
572 | | CDGTRA = 557, |
573 | | CDLFBR = 558, |
574 | | CDLFTR = 559, |
575 | | CDLGBR = 560, |
576 | | CDLGTR = 561, |
577 | | CDPT = 562, |
578 | | CDR = 563, |
579 | | CDS = 564, |
580 | | CDSG = 565, |
581 | | CDSTR = 566, |
582 | | CDSY = 567, |
583 | | CDTR = 568, |
584 | | CDUTR = 569, |
585 | | CDZT = 570, |
586 | | CE = 571, |
587 | | CEB = 572, |
588 | | CEBR = 573, |
589 | | CEDTR = 574, |
590 | | CEFBR = 575, |
591 | | CEFBRA = 576, |
592 | | CEFR = 577, |
593 | | CEGBR = 578, |
594 | | CEGBRA = 579, |
595 | | CEGR = 580, |
596 | | CELFBR = 581, |
597 | | CELGBR = 582, |
598 | | CER = 583, |
599 | | CEXTR = 584, |
600 | | CFC = 585, |
601 | | CFDBR = 586, |
602 | | CFDBRA = 587, |
603 | | CFDR = 588, |
604 | | CFDTR = 589, |
605 | | CFEBR = 590, |
606 | | CFEBRA = 591, |
607 | | CFER = 592, |
608 | | CFI = 593, |
609 | | CFXBR = 594, |
610 | | CFXBRA = 595, |
611 | | CFXR = 596, |
612 | | CFXTR = 597, |
613 | | CG = 598, |
614 | | CGDBR = 599, |
615 | | CGDBRA = 600, |
616 | | CGDR = 601, |
617 | | CGDTR = 602, |
618 | | CGDTRA = 603, |
619 | | CGEBR = 604, |
620 | | CGEBRA = 605, |
621 | | CGER = 606, |
622 | | CGF = 607, |
623 | | CGFI = 608, |
624 | | CGFR = 609, |
625 | | CGFRL = 610, |
626 | | CGH = 611, |
627 | | CGHI = 612, |
628 | | CGHRL = 613, |
629 | | CGHSI = 614, |
630 | | CGIB = 615, |
631 | | CGIBAsm = 616, |
632 | | CGIBAsmE = 617, |
633 | | CGIBAsmH = 618, |
634 | | CGIBAsmHE = 619, |
635 | | CGIBAsmL = 620, |
636 | | CGIBAsmLE = 621, |
637 | | CGIBAsmLH = 622, |
638 | | CGIBAsmNE = 623, |
639 | | CGIBAsmNH = 624, |
640 | | CGIBAsmNHE = 625, |
641 | | CGIBAsmNL = 626, |
642 | | CGIBAsmNLE = 627, |
643 | | CGIBAsmNLH = 628, |
644 | | CGIJ = 629, |
645 | | CGIJAsm = 630, |
646 | | CGIJAsmE = 631, |
647 | | CGIJAsmH = 632, |
648 | | CGIJAsmHE = 633, |
649 | | CGIJAsmL = 634, |
650 | | CGIJAsmLE = 635, |
651 | | CGIJAsmLH = 636, |
652 | | CGIJAsmNE = 637, |
653 | | CGIJAsmNH = 638, |
654 | | CGIJAsmNHE = 639, |
655 | | CGIJAsmNL = 640, |
656 | | CGIJAsmNLE = 641, |
657 | | CGIJAsmNLH = 642, |
658 | | CGIT = 643, |
659 | | CGITAsm = 644, |
660 | | CGITAsmE = 645, |
661 | | CGITAsmH = 646, |
662 | | CGITAsmHE = 647, |
663 | | CGITAsmL = 648, |
664 | | CGITAsmLE = 649, |
665 | | CGITAsmLH = 650, |
666 | | CGITAsmNE = 651, |
667 | | CGITAsmNH = 652, |
668 | | CGITAsmNHE = 653, |
669 | | CGITAsmNL = 654, |
670 | | CGITAsmNLE = 655, |
671 | | CGITAsmNLH = 656, |
672 | | CGR = 657, |
673 | | CGRB = 658, |
674 | | CGRBAsm = 659, |
675 | | CGRBAsmE = 660, |
676 | | CGRBAsmH = 661, |
677 | | CGRBAsmHE = 662, |
678 | | CGRBAsmL = 663, |
679 | | CGRBAsmLE = 664, |
680 | | CGRBAsmLH = 665, |
681 | | CGRBAsmNE = 666, |
682 | | CGRBAsmNH = 667, |
683 | | CGRBAsmNHE = 668, |
684 | | CGRBAsmNL = 669, |
685 | | CGRBAsmNLE = 670, |
686 | | CGRBAsmNLH = 671, |
687 | | CGRJ = 672, |
688 | | CGRJAsm = 673, |
689 | | CGRJAsmE = 674, |
690 | | CGRJAsmH = 675, |
691 | | CGRJAsmHE = 676, |
692 | | CGRJAsmL = 677, |
693 | | CGRJAsmLE = 678, |
694 | | CGRJAsmLH = 679, |
695 | | CGRJAsmNE = 680, |
696 | | CGRJAsmNH = 681, |
697 | | CGRJAsmNHE = 682, |
698 | | CGRJAsmNL = 683, |
699 | | CGRJAsmNLE = 684, |
700 | | CGRJAsmNLH = 685, |
701 | | CGRL = 686, |
702 | | CGRT = 687, |
703 | | CGRTAsm = 688, |
704 | | CGRTAsmE = 689, |
705 | | CGRTAsmH = 690, |
706 | | CGRTAsmHE = 691, |
707 | | CGRTAsmL = 692, |
708 | | CGRTAsmLE = 693, |
709 | | CGRTAsmLH = 694, |
710 | | CGRTAsmNE = 695, |
711 | | CGRTAsmNH = 696, |
712 | | CGRTAsmNHE = 697, |
713 | | CGRTAsmNL = 698, |
714 | | CGRTAsmNLE = 699, |
715 | | CGRTAsmNLH = 700, |
716 | | CGXBR = 701, |
717 | | CGXBRA = 702, |
718 | | CGXR = 703, |
719 | | CGXTR = 704, |
720 | | CGXTRA = 705, |
721 | | CH = 706, |
722 | | CHF = 707, |
723 | | CHHR = 708, |
724 | | CHHSI = 709, |
725 | | CHI = 710, |
726 | | CHLR = 711, |
727 | | CHRL = 712, |
728 | | CHSI = 713, |
729 | | CHY = 714, |
730 | | CIB = 715, |
731 | | CIBAsm = 716, |
732 | | CIBAsmE = 717, |
733 | | CIBAsmH = 718, |
734 | | CIBAsmHE = 719, |
735 | | CIBAsmL = 720, |
736 | | CIBAsmLE = 721, |
737 | | CIBAsmLH = 722, |
738 | | CIBAsmNE = 723, |
739 | | CIBAsmNH = 724, |
740 | | CIBAsmNHE = 725, |
741 | | CIBAsmNL = 726, |
742 | | CIBAsmNLE = 727, |
743 | | CIBAsmNLH = 728, |
744 | | CIH = 729, |
745 | | CIJ = 730, |
746 | | CIJAsm = 731, |
747 | | CIJAsmE = 732, |
748 | | CIJAsmH = 733, |
749 | | CIJAsmHE = 734, |
750 | | CIJAsmL = 735, |
751 | | CIJAsmLE = 736, |
752 | | CIJAsmLH = 737, |
753 | | CIJAsmNE = 738, |
754 | | CIJAsmNH = 739, |
755 | | CIJAsmNHE = 740, |
756 | | CIJAsmNL = 741, |
757 | | CIJAsmNLE = 742, |
758 | | CIJAsmNLH = 743, |
759 | | CIT = 744, |
760 | | CITAsm = 745, |
761 | | CITAsmE = 746, |
762 | | CITAsmH = 747, |
763 | | CITAsmHE = 748, |
764 | | CITAsmL = 749, |
765 | | CITAsmLE = 750, |
766 | | CITAsmLH = 751, |
767 | | CITAsmNE = 752, |
768 | | CITAsmNH = 753, |
769 | | CITAsmNHE = 754, |
770 | | CITAsmNL = 755, |
771 | | CITAsmNLE = 756, |
772 | | CITAsmNLH = 757, |
773 | | CKSM = 758, |
774 | | CL = 759, |
775 | | CLC = 760, |
776 | | CLCL = 761, |
777 | | CLCLE = 762, |
778 | | CLCLU = 763, |
779 | | CLFDBR = 764, |
780 | | CLFDTR = 765, |
781 | | CLFEBR = 766, |
782 | | CLFHSI = 767, |
783 | | CLFI = 768, |
784 | | CLFIT = 769, |
785 | | CLFITAsm = 770, |
786 | | CLFITAsmE = 771, |
787 | | CLFITAsmH = 772, |
788 | | CLFITAsmHE = 773, |
789 | | CLFITAsmL = 774, |
790 | | CLFITAsmLE = 775, |
791 | | CLFITAsmLH = 776, |
792 | | CLFITAsmNE = 777, |
793 | | CLFITAsmNH = 778, |
794 | | CLFITAsmNHE = 779, |
795 | | CLFITAsmNL = 780, |
796 | | CLFITAsmNLE = 781, |
797 | | CLFITAsmNLH = 782, |
798 | | CLFXBR = 783, |
799 | | CLFXTR = 784, |
800 | | CLG = 785, |
801 | | CLGDBR = 786, |
802 | | CLGDTR = 787, |
803 | | CLGEBR = 788, |
804 | | CLGF = 789, |
805 | | CLGFI = 790, |
806 | | CLGFR = 791, |
807 | | CLGFRL = 792, |
808 | | CLGHRL = 793, |
809 | | CLGHSI = 794, |
810 | | CLGIB = 795, |
811 | | CLGIBAsm = 796, |
812 | | CLGIBAsmE = 797, |
813 | | CLGIBAsmH = 798, |
814 | | CLGIBAsmHE = 799, |
815 | | CLGIBAsmL = 800, |
816 | | CLGIBAsmLE = 801, |
817 | | CLGIBAsmLH = 802, |
818 | | CLGIBAsmNE = 803, |
819 | | CLGIBAsmNH = 804, |
820 | | CLGIBAsmNHE = 805, |
821 | | CLGIBAsmNL = 806, |
822 | | CLGIBAsmNLE = 807, |
823 | | CLGIBAsmNLH = 808, |
824 | | CLGIJ = 809, |
825 | | CLGIJAsm = 810, |
826 | | CLGIJAsmE = 811, |
827 | | CLGIJAsmH = 812, |
828 | | CLGIJAsmHE = 813, |
829 | | CLGIJAsmL = 814, |
830 | | CLGIJAsmLE = 815, |
831 | | CLGIJAsmLH = 816, |
832 | | CLGIJAsmNE = 817, |
833 | | CLGIJAsmNH = 818, |
834 | | CLGIJAsmNHE = 819, |
835 | | CLGIJAsmNL = 820, |
836 | | CLGIJAsmNLE = 821, |
837 | | CLGIJAsmNLH = 822, |
838 | | CLGIT = 823, |
839 | | CLGITAsm = 824, |
840 | | CLGITAsmE = 825, |
841 | | CLGITAsmH = 826, |
842 | | CLGITAsmHE = 827, |
843 | | CLGITAsmL = 828, |
844 | | CLGITAsmLE = 829, |
845 | | CLGITAsmLH = 830, |
846 | | CLGITAsmNE = 831, |
847 | | CLGITAsmNH = 832, |
848 | | CLGITAsmNHE = 833, |
849 | | CLGITAsmNL = 834, |
850 | | CLGITAsmNLE = 835, |
851 | | CLGITAsmNLH = 836, |
852 | | CLGR = 837, |
853 | | CLGRB = 838, |
854 | | CLGRBAsm = 839, |
855 | | CLGRBAsmE = 840, |
856 | | CLGRBAsmH = 841, |
857 | | CLGRBAsmHE = 842, |
858 | | CLGRBAsmL = 843, |
859 | | CLGRBAsmLE = 844, |
860 | | CLGRBAsmLH = 845, |
861 | | CLGRBAsmNE = 846, |
862 | | CLGRBAsmNH = 847, |
863 | | CLGRBAsmNHE = 848, |
864 | | CLGRBAsmNL = 849, |
865 | | CLGRBAsmNLE = 850, |
866 | | CLGRBAsmNLH = 851, |
867 | | CLGRJ = 852, |
868 | | CLGRJAsm = 853, |
869 | | CLGRJAsmE = 854, |
870 | | CLGRJAsmH = 855, |
871 | | CLGRJAsmHE = 856, |
872 | | CLGRJAsmL = 857, |
873 | | CLGRJAsmLE = 858, |
874 | | CLGRJAsmLH = 859, |
875 | | CLGRJAsmNE = 860, |
876 | | CLGRJAsmNH = 861, |
877 | | CLGRJAsmNHE = 862, |
878 | | CLGRJAsmNL = 863, |
879 | | CLGRJAsmNLE = 864, |
880 | | CLGRJAsmNLH = 865, |
881 | | CLGRL = 866, |
882 | | CLGRT = 867, |
883 | | CLGRTAsm = 868, |
884 | | CLGRTAsmE = 869, |
885 | | CLGRTAsmH = 870, |
886 | | CLGRTAsmHE = 871, |
887 | | CLGRTAsmL = 872, |
888 | | CLGRTAsmLE = 873, |
889 | | CLGRTAsmLH = 874, |
890 | | CLGRTAsmNE = 875, |
891 | | CLGRTAsmNH = 876, |
892 | | CLGRTAsmNHE = 877, |
893 | | CLGRTAsmNL = 878, |
894 | | CLGRTAsmNLE = 879, |
895 | | CLGRTAsmNLH = 880, |
896 | | CLGT = 881, |
897 | | CLGTAsm = 882, |
898 | | CLGTAsmE = 883, |
899 | | CLGTAsmH = 884, |
900 | | CLGTAsmHE = 885, |
901 | | CLGTAsmL = 886, |
902 | | CLGTAsmLE = 887, |
903 | | CLGTAsmLH = 888, |
904 | | CLGTAsmNE = 889, |
905 | | CLGTAsmNH = 890, |
906 | | CLGTAsmNHE = 891, |
907 | | CLGTAsmNL = 892, |
908 | | CLGTAsmNLE = 893, |
909 | | CLGTAsmNLH = 894, |
910 | | CLGXBR = 895, |
911 | | CLGXTR = 896, |
912 | | CLHF = 897, |
913 | | CLHHR = 898, |
914 | | CLHHSI = 899, |
915 | | CLHLR = 900, |
916 | | CLHRL = 901, |
917 | | CLI = 902, |
918 | | CLIB = 903, |
919 | | CLIBAsm = 904, |
920 | | CLIBAsmE = 905, |
921 | | CLIBAsmH = 906, |
922 | | CLIBAsmHE = 907, |
923 | | CLIBAsmL = 908, |
924 | | CLIBAsmLE = 909, |
925 | | CLIBAsmLH = 910, |
926 | | CLIBAsmNE = 911, |
927 | | CLIBAsmNH = 912, |
928 | | CLIBAsmNHE = 913, |
929 | | CLIBAsmNL = 914, |
930 | | CLIBAsmNLE = 915, |
931 | | CLIBAsmNLH = 916, |
932 | | CLIH = 917, |
933 | | CLIJ = 918, |
934 | | CLIJAsm = 919, |
935 | | CLIJAsmE = 920, |
936 | | CLIJAsmH = 921, |
937 | | CLIJAsmHE = 922, |
938 | | CLIJAsmL = 923, |
939 | | CLIJAsmLE = 924, |
940 | | CLIJAsmLH = 925, |
941 | | CLIJAsmNE = 926, |
942 | | CLIJAsmNH = 927, |
943 | | CLIJAsmNHE = 928, |
944 | | CLIJAsmNL = 929, |
945 | | CLIJAsmNLE = 930, |
946 | | CLIJAsmNLH = 931, |
947 | | CLIY = 932, |
948 | | CLM = 933, |
949 | | CLMH = 934, |
950 | | CLMY = 935, |
951 | | CLR = 936, |
952 | | CLRB = 937, |
953 | | CLRBAsm = 938, |
954 | | CLRBAsmE = 939, |
955 | | CLRBAsmH = 940, |
956 | | CLRBAsmHE = 941, |
957 | | CLRBAsmL = 942, |
958 | | CLRBAsmLE = 943, |
959 | | CLRBAsmLH = 944, |
960 | | CLRBAsmNE = 945, |
961 | | CLRBAsmNH = 946, |
962 | | CLRBAsmNHE = 947, |
963 | | CLRBAsmNL = 948, |
964 | | CLRBAsmNLE = 949, |
965 | | CLRBAsmNLH = 950, |
966 | | CLRJ = 951, |
967 | | CLRJAsm = 952, |
968 | | CLRJAsmE = 953, |
969 | | CLRJAsmH = 954, |
970 | | CLRJAsmHE = 955, |
971 | | CLRJAsmL = 956, |
972 | | CLRJAsmLE = 957, |
973 | | CLRJAsmLH = 958, |
974 | | CLRJAsmNE = 959, |
975 | | CLRJAsmNH = 960, |
976 | | CLRJAsmNHE = 961, |
977 | | CLRJAsmNL = 962, |
978 | | CLRJAsmNLE = 963, |
979 | | CLRJAsmNLH = 964, |
980 | | CLRL = 965, |
981 | | CLRT = 966, |
982 | | CLRTAsm = 967, |
983 | | CLRTAsmE = 968, |
984 | | CLRTAsmH = 969, |
985 | | CLRTAsmHE = 970, |
986 | | CLRTAsmL = 971, |
987 | | CLRTAsmLE = 972, |
988 | | CLRTAsmLH = 973, |
989 | | CLRTAsmNE = 974, |
990 | | CLRTAsmNH = 975, |
991 | | CLRTAsmNHE = 976, |
992 | | CLRTAsmNL = 977, |
993 | | CLRTAsmNLE = 978, |
994 | | CLRTAsmNLH = 979, |
995 | | CLST = 980, |
996 | | CLT = 981, |
997 | | CLTAsm = 982, |
998 | | CLTAsmE = 983, |
999 | | CLTAsmH = 984, |
1000 | | CLTAsmHE = 985, |
1001 | | CLTAsmL = 986, |
1002 | | CLTAsmLE = 987, |
1003 | | CLTAsmLH = 988, |
1004 | | CLTAsmNE = 989, |
1005 | | CLTAsmNH = 990, |
1006 | | CLTAsmNHE = 991, |
1007 | | CLTAsmNL = 992, |
1008 | | CLTAsmNLE = 993, |
1009 | | CLTAsmNLH = 994, |
1010 | | CLY = 995, |
1011 | | CMPSC = 996, |
1012 | | CP = 997, |
1013 | | CPDT = 998, |
1014 | | CPSDRdd = 999, |
1015 | | CPSDRds = 1000, |
1016 | | CPSDRsd = 1001, |
1017 | | CPSDRss = 1002, |
1018 | | CPXT = 1003, |
1019 | | CPYA = 1004, |
1020 | | CR = 1005, |
1021 | | CRB = 1006, |
1022 | | CRBAsm = 1007, |
1023 | | CRBAsmE = 1008, |
1024 | | CRBAsmH = 1009, |
1025 | | CRBAsmHE = 1010, |
1026 | | CRBAsmL = 1011, |
1027 | | CRBAsmLE = 1012, |
1028 | | CRBAsmLH = 1013, |
1029 | | CRBAsmNE = 1014, |
1030 | | CRBAsmNH = 1015, |
1031 | | CRBAsmNHE = 1016, |
1032 | | CRBAsmNL = 1017, |
1033 | | CRBAsmNLE = 1018, |
1034 | | CRBAsmNLH = 1019, |
1035 | | CRDTE = 1020, |
1036 | | CRDTEOpt = 1021, |
1037 | | CRJ = 1022, |
1038 | | CRJAsm = 1023, |
1039 | | CRJAsmE = 1024, |
1040 | | CRJAsmH = 1025, |
1041 | | CRJAsmHE = 1026, |
1042 | | CRJAsmL = 1027, |
1043 | | CRJAsmLE = 1028, |
1044 | | CRJAsmLH = 1029, |
1045 | | CRJAsmNE = 1030, |
1046 | | CRJAsmNH = 1031, |
1047 | | CRJAsmNHE = 1032, |
1048 | | CRJAsmNL = 1033, |
1049 | | CRJAsmNLE = 1034, |
1050 | | CRJAsmNLH = 1035, |
1051 | | CRL = 1036, |
1052 | | CRT = 1037, |
1053 | | CRTAsm = 1038, |
1054 | | CRTAsmE = 1039, |
1055 | | CRTAsmH = 1040, |
1056 | | CRTAsmHE = 1041, |
1057 | | CRTAsmL = 1042, |
1058 | | CRTAsmLE = 1043, |
1059 | | CRTAsmLH = 1044, |
1060 | | CRTAsmNE = 1045, |
1061 | | CRTAsmNH = 1046, |
1062 | | CRTAsmNHE = 1047, |
1063 | | CRTAsmNL = 1048, |
1064 | | CRTAsmNLE = 1049, |
1065 | | CRTAsmNLH = 1050, |
1066 | | CS = 1051, |
1067 | | CSCH = 1052, |
1068 | | CSDTR = 1053, |
1069 | | CSG = 1054, |
1070 | | CSP = 1055, |
1071 | | CSPG = 1056, |
1072 | | CSST = 1057, |
1073 | | CSXTR = 1058, |
1074 | | CSY = 1059, |
1075 | | CU12 = 1060, |
1076 | | CU12Opt = 1061, |
1077 | | CU14 = 1062, |
1078 | | CU14Opt = 1063, |
1079 | | CU21 = 1064, |
1080 | | CU21Opt = 1065, |
1081 | | CU24 = 1066, |
1082 | | CU24Opt = 1067, |
1083 | | CU41 = 1068, |
1084 | | CU42 = 1069, |
1085 | | CUDTR = 1070, |
1086 | | CUSE = 1071, |
1087 | | CUTFU = 1072, |
1088 | | CUTFUOpt = 1073, |
1089 | | CUUTF = 1074, |
1090 | | CUUTFOpt = 1075, |
1091 | | CUXTR = 1076, |
1092 | | CVB = 1077, |
1093 | | CVBG = 1078, |
1094 | | CVBY = 1079, |
1095 | | CVD = 1080, |
1096 | | CVDG = 1081, |
1097 | | CVDY = 1082, |
1098 | | CXBR = 1083, |
1099 | | CXFBR = 1084, |
1100 | | CXFBRA = 1085, |
1101 | | CXFR = 1086, |
1102 | | CXFTR = 1087, |
1103 | | CXGBR = 1088, |
1104 | | CXGBRA = 1089, |
1105 | | CXGR = 1090, |
1106 | | CXGTR = 1091, |
1107 | | CXGTRA = 1092, |
1108 | | CXLFBR = 1093, |
1109 | | CXLFTR = 1094, |
1110 | | CXLGBR = 1095, |
1111 | | CXLGTR = 1096, |
1112 | | CXPT = 1097, |
1113 | | CXR = 1098, |
1114 | | CXSTR = 1099, |
1115 | | CXTR = 1100, |
1116 | | CXUTR = 1101, |
1117 | | CXZT = 1102, |
1118 | | CY = 1103, |
1119 | | CZDT = 1104, |
1120 | | CZXT = 1105, |
1121 | | D = 1106, |
1122 | | DD = 1107, |
1123 | | DDB = 1108, |
1124 | | DDBR = 1109, |
1125 | | DDR = 1110, |
1126 | | DDTR = 1111, |
1127 | | DDTRA = 1112, |
1128 | | DE = 1113, |
1129 | | DEB = 1114, |
1130 | | DEBR = 1115, |
1131 | | DER = 1116, |
1132 | | DIAG = 1117, |
1133 | | DIDBR = 1118, |
1134 | | DIEBR = 1119, |
1135 | | DL = 1120, |
1136 | | DLG = 1121, |
1137 | | DLGR = 1122, |
1138 | | DLR = 1123, |
1139 | | DP = 1124, |
1140 | | DR = 1125, |
1141 | | DSG = 1126, |
1142 | | DSGF = 1127, |
1143 | | DSGFR = 1128, |
1144 | | DSGR = 1129, |
1145 | | DXBR = 1130, |
1146 | | DXR = 1131, |
1147 | | DXTR = 1132, |
1148 | | DXTRA = 1133, |
1149 | | EAR = 1134, |
1150 | | ECAG = 1135, |
1151 | | ECCTR = 1136, |
1152 | | ECPGA = 1137, |
1153 | | ECTG = 1138, |
1154 | | ED = 1139, |
1155 | | EDMK = 1140, |
1156 | | EEDTR = 1141, |
1157 | | EEXTR = 1142, |
1158 | | EFPC = 1143, |
1159 | | EPAIR = 1144, |
1160 | | EPAR = 1145, |
1161 | | EPCTR = 1146, |
1162 | | EPSW = 1147, |
1163 | | EREG = 1148, |
1164 | | EREGG = 1149, |
1165 | | ESAIR = 1150, |
1166 | | ESAR = 1151, |
1167 | | ESDTR = 1152, |
1168 | | ESEA = 1153, |
1169 | | ESTA = 1154, |
1170 | | ESXTR = 1155, |
1171 | | ETND = 1156, |
1172 | | EX = 1157, |
1173 | | EXRL = 1158, |
1174 | | FIDBR = 1159, |
1175 | | FIDBRA = 1160, |
1176 | | FIDR = 1161, |
1177 | | FIDTR = 1162, |
1178 | | FIEBR = 1163, |
1179 | | FIEBRA = 1164, |
1180 | | FIER = 1165, |
1181 | | FIXBR = 1166, |
1182 | | FIXBRA = 1167, |
1183 | | FIXR = 1168, |
1184 | | FIXTR = 1169, |
1185 | | FLOGR = 1170, |
1186 | | HDR = 1171, |
1187 | | HER = 1172, |
1188 | | HSCH = 1173, |
1189 | | IAC = 1174, |
1190 | | IC = 1175, |
1191 | | IC32 = 1176, |
1192 | | IC32Y = 1177, |
1193 | | ICM = 1178, |
1194 | | ICMH = 1179, |
1195 | | ICMY = 1180, |
1196 | | ICY = 1181, |
1197 | | IDTE = 1182, |
1198 | | IDTEOpt = 1183, |
1199 | | IEDTR = 1184, |
1200 | | IEXTR = 1185, |
1201 | | IIHF = 1186, |
1202 | | IIHH = 1187, |
1203 | | IIHL = 1188, |
1204 | | IILF = 1189, |
1205 | | IILH = 1190, |
1206 | | IILL = 1191, |
1207 | | IPK = 1192, |
1208 | | IPM = 1193, |
1209 | | IPTE = 1194, |
1210 | | IPTEOpt = 1195, |
1211 | | IPTEOptOpt = 1196, |
1212 | | IRBM = 1197, |
1213 | | ISKE = 1198, |
1214 | | IVSK = 1199, |
1215 | | InsnE = 1200, |
1216 | | InsnRI = 1201, |
1217 | | InsnRIE = 1202, |
1218 | | InsnRIL = 1203, |
1219 | | InsnRILU = 1204, |
1220 | | InsnRIS = 1205, |
1221 | | InsnRR = 1206, |
1222 | | InsnRRE = 1207, |
1223 | | InsnRRF = 1208, |
1224 | | InsnRRS = 1209, |
1225 | | InsnRS = 1210, |
1226 | | InsnRSE = 1211, |
1227 | | InsnRSI = 1212, |
1228 | | InsnRSY = 1213, |
1229 | | InsnRX = 1214, |
1230 | | InsnRXE = 1215, |
1231 | | InsnRXF = 1216, |
1232 | | InsnRXY = 1217, |
1233 | | InsnS = 1218, |
1234 | | InsnSI = 1219, |
1235 | | InsnSIL = 1220, |
1236 | | InsnSIY = 1221, |
1237 | | InsnSS = 1222, |
1238 | | InsnSSE = 1223, |
1239 | | InsnSSF = 1224, |
1240 | | J = 1225, |
1241 | | JAsmE = 1226, |
1242 | | JAsmH = 1227, |
1243 | | JAsmHE = 1228, |
1244 | | JAsmL = 1229, |
1245 | | JAsmLE = 1230, |
1246 | | JAsmLH = 1231, |
1247 | | JAsmM = 1232, |
1248 | | JAsmNE = 1233, |
1249 | | JAsmNH = 1234, |
1250 | | JAsmNHE = 1235, |
1251 | | JAsmNL = 1236, |
1252 | | JAsmNLE = 1237, |
1253 | | JAsmNLH = 1238, |
1254 | | JAsmNM = 1239, |
1255 | | JAsmNO = 1240, |
1256 | | JAsmNP = 1241, |
1257 | | JAsmNZ = 1242, |
1258 | | JAsmO = 1243, |
1259 | | JAsmP = 1244, |
1260 | | JAsmZ = 1245, |
1261 | | JG = 1246, |
1262 | | JGAsmE = 1247, |
1263 | | JGAsmH = 1248, |
1264 | | JGAsmHE = 1249, |
1265 | | JGAsmL = 1250, |
1266 | | JGAsmLE = 1251, |
1267 | | JGAsmLH = 1252, |
1268 | | JGAsmM = 1253, |
1269 | | JGAsmNE = 1254, |
1270 | | JGAsmNH = 1255, |
1271 | | JGAsmNHE = 1256, |
1272 | | JGAsmNL = 1257, |
1273 | | JGAsmNLE = 1258, |
1274 | | JGAsmNLH = 1259, |
1275 | | JGAsmNM = 1260, |
1276 | | JGAsmNO = 1261, |
1277 | | JGAsmNP = 1262, |
1278 | | JGAsmNZ = 1263, |
1279 | | JGAsmO = 1264, |
1280 | | JGAsmP = 1265, |
1281 | | JGAsmZ = 1266, |
1282 | | KDB = 1267, |
1283 | | KDBR = 1268, |
1284 | | KDTR = 1269, |
1285 | | KEB = 1270, |
1286 | | KEBR = 1271, |
1287 | | KIMD = 1272, |
1288 | | KLMD = 1273, |
1289 | | KM = 1274, |
1290 | | KMA = 1275, |
1291 | | KMAC = 1276, |
1292 | | KMC = 1277, |
1293 | | KMCTR = 1278, |
1294 | | KMF = 1279, |
1295 | | KMO = 1280, |
1296 | | KXBR = 1281, |
1297 | | KXTR = 1282, |
1298 | | L = 1283, |
1299 | | LA = 1284, |
1300 | | LAA = 1285, |
1301 | | LAAG = 1286, |
1302 | | LAAL = 1287, |
1303 | | LAALG = 1288, |
1304 | | LAE = 1289, |
1305 | | LAEY = 1290, |
1306 | | LAM = 1291, |
1307 | | LAMY = 1292, |
1308 | | LAN = 1293, |
1309 | | LANG = 1294, |
1310 | | LAO = 1295, |
1311 | | LAOG = 1296, |
1312 | | LARL = 1297, |
1313 | | LASP = 1298, |
1314 | | LAT = 1299, |
1315 | | LAX = 1300, |
1316 | | LAXG = 1301, |
1317 | | LAY = 1302, |
1318 | | LB = 1303, |
1319 | | LBH = 1304, |
1320 | | LBR = 1305, |
1321 | | LCBB = 1306, |
1322 | | LCCTL = 1307, |
1323 | | LCDBR = 1308, |
1324 | | LCDFR = 1309, |
1325 | | LCDFR_32 = 1310, |
1326 | | LCDR = 1311, |
1327 | | LCEBR = 1312, |
1328 | | LCER = 1313, |
1329 | | LCGFR = 1314, |
1330 | | LCGR = 1315, |
1331 | | LCR = 1316, |
1332 | | LCTL = 1317, |
1333 | | LCTLG = 1318, |
1334 | | LCXBR = 1319, |
1335 | | LCXR = 1320, |
1336 | | LD = 1321, |
1337 | | LDE = 1322, |
1338 | | LDE32 = 1323, |
1339 | | LDEB = 1324, |
1340 | | LDEBR = 1325, |
1341 | | LDER = 1326, |
1342 | | LDETR = 1327, |
1343 | | LDGR = 1328, |
1344 | | LDR = 1329, |
1345 | | LDR32 = 1330, |
1346 | | LDXBR = 1331, |
1347 | | LDXBRA = 1332, |
1348 | | LDXR = 1333, |
1349 | | LDXTR = 1334, |
1350 | | LDY = 1335, |
1351 | | LE = 1336, |
1352 | | LEDBR = 1337, |
1353 | | LEDBRA = 1338, |
1354 | | LEDR = 1339, |
1355 | | LEDTR = 1340, |
1356 | | LER = 1341, |
1357 | | LEXBR = 1342, |
1358 | | LEXBRA = 1343, |
1359 | | LEXR = 1344, |
1360 | | LEY = 1345, |
1361 | | LFAS = 1346, |
1362 | | LFH = 1347, |
1363 | | LFHAT = 1348, |
1364 | | LFPC = 1349, |
1365 | | LG = 1350, |
1366 | | LGAT = 1351, |
1367 | | LGB = 1352, |
1368 | | LGBR = 1353, |
1369 | | LGDR = 1354, |
1370 | | LGF = 1355, |
1371 | | LGFI = 1356, |
1372 | | LGFR = 1357, |
1373 | | LGFRL = 1358, |
1374 | | LGG = 1359, |
1375 | | LGH = 1360, |
1376 | | LGHI = 1361, |
1377 | | LGHR = 1362, |
1378 | | LGHRL = 1363, |
1379 | | LGR = 1364, |
1380 | | LGRL = 1365, |
1381 | | LGSC = 1366, |
1382 | | LH = 1367, |
1383 | | LHH = 1368, |
1384 | | LHI = 1369, |
1385 | | LHR = 1370, |
1386 | | LHRL = 1371, |
1387 | | LHY = 1372, |
1388 | | LLC = 1373, |
1389 | | LLCH = 1374, |
1390 | | LLCR = 1375, |
1391 | | LLGC = 1376, |
1392 | | LLGCR = 1377, |
1393 | | LLGF = 1378, |
1394 | | LLGFAT = 1379, |
1395 | | LLGFR = 1380, |
1396 | | LLGFRL = 1381, |
1397 | | LLGFSG = 1382, |
1398 | | LLGH = 1383, |
1399 | | LLGHR = 1384, |
1400 | | LLGHRL = 1385, |
1401 | | LLGT = 1386, |
1402 | | LLGTAT = 1387, |
1403 | | LLGTR = 1388, |
1404 | | LLH = 1389, |
1405 | | LLHH = 1390, |
1406 | | LLHR = 1391, |
1407 | | LLHRL = 1392, |
1408 | | LLIHF = 1393, |
1409 | | LLIHH = 1394, |
1410 | | LLIHL = 1395, |
1411 | | LLILF = 1396, |
1412 | | LLILH = 1397, |
1413 | | LLILL = 1398, |
1414 | | LLZRGF = 1399, |
1415 | | LM = 1400, |
1416 | | LMD = 1401, |
1417 | | LMG = 1402, |
1418 | | LMH = 1403, |
1419 | | LMY = 1404, |
1420 | | LNDBR = 1405, |
1421 | | LNDFR = 1406, |
1422 | | LNDFR_32 = 1407, |
1423 | | LNDR = 1408, |
1424 | | LNEBR = 1409, |
1425 | | LNER = 1410, |
1426 | | LNGFR = 1411, |
1427 | | LNGR = 1412, |
1428 | | LNR = 1413, |
1429 | | LNXBR = 1414, |
1430 | | LNXR = 1415, |
1431 | | LOC = 1416, |
1432 | | LOCAsm = 1417, |
1433 | | LOCAsmE = 1418, |
1434 | | LOCAsmH = 1419, |
1435 | | LOCAsmHE = 1420, |
1436 | | LOCAsmL = 1421, |
1437 | | LOCAsmLE = 1422, |
1438 | | LOCAsmLH = 1423, |
1439 | | LOCAsmM = 1424, |
1440 | | LOCAsmNE = 1425, |
1441 | | LOCAsmNH = 1426, |
1442 | | LOCAsmNHE = 1427, |
1443 | | LOCAsmNL = 1428, |
1444 | | LOCAsmNLE = 1429, |
1445 | | LOCAsmNLH = 1430, |
1446 | | LOCAsmNM = 1431, |
1447 | | LOCAsmNO = 1432, |
1448 | | LOCAsmNP = 1433, |
1449 | | LOCAsmNZ = 1434, |
1450 | | LOCAsmO = 1435, |
1451 | | LOCAsmP = 1436, |
1452 | | LOCAsmZ = 1437, |
1453 | | LOCFH = 1438, |
1454 | | LOCFHAsm = 1439, |
1455 | | LOCFHAsmE = 1440, |
1456 | | LOCFHAsmH = 1441, |
1457 | | LOCFHAsmHE = 1442, |
1458 | | LOCFHAsmL = 1443, |
1459 | | LOCFHAsmLE = 1444, |
1460 | | LOCFHAsmLH = 1445, |
1461 | | LOCFHAsmM = 1446, |
1462 | | LOCFHAsmNE = 1447, |
1463 | | LOCFHAsmNH = 1448, |
1464 | | LOCFHAsmNHE = 1449, |
1465 | | LOCFHAsmNL = 1450, |
1466 | | LOCFHAsmNLE = 1451, |
1467 | | LOCFHAsmNLH = 1452, |
1468 | | LOCFHAsmNM = 1453, |
1469 | | LOCFHAsmNO = 1454, |
1470 | | LOCFHAsmNP = 1455, |
1471 | | LOCFHAsmNZ = 1456, |
1472 | | LOCFHAsmO = 1457, |
1473 | | LOCFHAsmP = 1458, |
1474 | | LOCFHAsmZ = 1459, |
1475 | | LOCFHR = 1460, |
1476 | | LOCFHRAsm = 1461, |
1477 | | LOCFHRAsmE = 1462, |
1478 | | LOCFHRAsmH = 1463, |
1479 | | LOCFHRAsmHE = 1464, |
1480 | | LOCFHRAsmL = 1465, |
1481 | | LOCFHRAsmLE = 1466, |
1482 | | LOCFHRAsmLH = 1467, |
1483 | | LOCFHRAsmM = 1468, |
1484 | | LOCFHRAsmNE = 1469, |
1485 | | LOCFHRAsmNH = 1470, |
1486 | | LOCFHRAsmNHE = 1471, |
1487 | | LOCFHRAsmNL = 1472, |
1488 | | LOCFHRAsmNLE = 1473, |
1489 | | LOCFHRAsmNLH = 1474, |
1490 | | LOCFHRAsmNM = 1475, |
1491 | | LOCFHRAsmNO = 1476, |
1492 | | LOCFHRAsmNP = 1477, |
1493 | | LOCFHRAsmNZ = 1478, |
1494 | | LOCFHRAsmO = 1479, |
1495 | | LOCFHRAsmP = 1480, |
1496 | | LOCFHRAsmZ = 1481, |
1497 | | LOCG = 1482, |
1498 | | LOCGAsm = 1483, |
1499 | | LOCGAsmE = 1484, |
1500 | | LOCGAsmH = 1485, |
1501 | | LOCGAsmHE = 1486, |
1502 | | LOCGAsmL = 1487, |
1503 | | LOCGAsmLE = 1488, |
1504 | | LOCGAsmLH = 1489, |
1505 | | LOCGAsmM = 1490, |
1506 | | LOCGAsmNE = 1491, |
1507 | | LOCGAsmNH = 1492, |
1508 | | LOCGAsmNHE = 1493, |
1509 | | LOCGAsmNL = 1494, |
1510 | | LOCGAsmNLE = 1495, |
1511 | | LOCGAsmNLH = 1496, |
1512 | | LOCGAsmNM = 1497, |
1513 | | LOCGAsmNO = 1498, |
1514 | | LOCGAsmNP = 1499, |
1515 | | LOCGAsmNZ = 1500, |
1516 | | LOCGAsmO = 1501, |
1517 | | LOCGAsmP = 1502, |
1518 | | LOCGAsmZ = 1503, |
1519 | | LOCGHI = 1504, |
1520 | | LOCGHIAsm = 1505, |
1521 | | LOCGHIAsmE = 1506, |
1522 | | LOCGHIAsmH = 1507, |
1523 | | LOCGHIAsmHE = 1508, |
1524 | | LOCGHIAsmL = 1509, |
1525 | | LOCGHIAsmLE = 1510, |
1526 | | LOCGHIAsmLH = 1511, |
1527 | | LOCGHIAsmM = 1512, |
1528 | | LOCGHIAsmNE = 1513, |
1529 | | LOCGHIAsmNH = 1514, |
1530 | | LOCGHIAsmNHE = 1515, |
1531 | | LOCGHIAsmNL = 1516, |
1532 | | LOCGHIAsmNLE = 1517, |
1533 | | LOCGHIAsmNLH = 1518, |
1534 | | LOCGHIAsmNM = 1519, |
1535 | | LOCGHIAsmNO = 1520, |
1536 | | LOCGHIAsmNP = 1521, |
1537 | | LOCGHIAsmNZ = 1522, |
1538 | | LOCGHIAsmO = 1523, |
1539 | | LOCGHIAsmP = 1524, |
1540 | | LOCGHIAsmZ = 1525, |
1541 | | LOCGR = 1526, |
1542 | | LOCGRAsm = 1527, |
1543 | | LOCGRAsmE = 1528, |
1544 | | LOCGRAsmH = 1529, |
1545 | | LOCGRAsmHE = 1530, |
1546 | | LOCGRAsmL = 1531, |
1547 | | LOCGRAsmLE = 1532, |
1548 | | LOCGRAsmLH = 1533, |
1549 | | LOCGRAsmM = 1534, |
1550 | | LOCGRAsmNE = 1535, |
1551 | | LOCGRAsmNH = 1536, |
1552 | | LOCGRAsmNHE = 1537, |
1553 | | LOCGRAsmNL = 1538, |
1554 | | LOCGRAsmNLE = 1539, |
1555 | | LOCGRAsmNLH = 1540, |
1556 | | LOCGRAsmNM = 1541, |
1557 | | LOCGRAsmNO = 1542, |
1558 | | LOCGRAsmNP = 1543, |
1559 | | LOCGRAsmNZ = 1544, |
1560 | | LOCGRAsmO = 1545, |
1561 | | LOCGRAsmP = 1546, |
1562 | | LOCGRAsmZ = 1547, |
1563 | | LOCHHI = 1548, |
1564 | | LOCHHIAsm = 1549, |
1565 | | LOCHHIAsmE = 1550, |
1566 | | LOCHHIAsmH = 1551, |
1567 | | LOCHHIAsmHE = 1552, |
1568 | | LOCHHIAsmL = 1553, |
1569 | | LOCHHIAsmLE = 1554, |
1570 | | LOCHHIAsmLH = 1555, |
1571 | | LOCHHIAsmM = 1556, |
1572 | | LOCHHIAsmNE = 1557, |
1573 | | LOCHHIAsmNH = 1558, |
1574 | | LOCHHIAsmNHE = 1559, |
1575 | | LOCHHIAsmNL = 1560, |
1576 | | LOCHHIAsmNLE = 1561, |
1577 | | LOCHHIAsmNLH = 1562, |
1578 | | LOCHHIAsmNM = 1563, |
1579 | | LOCHHIAsmNO = 1564, |
1580 | | LOCHHIAsmNP = 1565, |
1581 | | LOCHHIAsmNZ = 1566, |
1582 | | LOCHHIAsmO = 1567, |
1583 | | LOCHHIAsmP = 1568, |
1584 | | LOCHHIAsmZ = 1569, |
1585 | | LOCHI = 1570, |
1586 | | LOCHIAsm = 1571, |
1587 | | LOCHIAsmE = 1572, |
1588 | | LOCHIAsmH = 1573, |
1589 | | LOCHIAsmHE = 1574, |
1590 | | LOCHIAsmL = 1575, |
1591 | | LOCHIAsmLE = 1576, |
1592 | | LOCHIAsmLH = 1577, |
1593 | | LOCHIAsmM = 1578, |
1594 | | LOCHIAsmNE = 1579, |
1595 | | LOCHIAsmNH = 1580, |
1596 | | LOCHIAsmNHE = 1581, |
1597 | | LOCHIAsmNL = 1582, |
1598 | | LOCHIAsmNLE = 1583, |
1599 | | LOCHIAsmNLH = 1584, |
1600 | | LOCHIAsmNM = 1585, |
1601 | | LOCHIAsmNO = 1586, |
1602 | | LOCHIAsmNP = 1587, |
1603 | | LOCHIAsmNZ = 1588, |
1604 | | LOCHIAsmO = 1589, |
1605 | | LOCHIAsmP = 1590, |
1606 | | LOCHIAsmZ = 1591, |
1607 | | LOCR = 1592, |
1608 | | LOCRAsm = 1593, |
1609 | | LOCRAsmE = 1594, |
1610 | | LOCRAsmH = 1595, |
1611 | | LOCRAsmHE = 1596, |
1612 | | LOCRAsmL = 1597, |
1613 | | LOCRAsmLE = 1598, |
1614 | | LOCRAsmLH = 1599, |
1615 | | LOCRAsmM = 1600, |
1616 | | LOCRAsmNE = 1601, |
1617 | | LOCRAsmNH = 1602, |
1618 | | LOCRAsmNHE = 1603, |
1619 | | LOCRAsmNL = 1604, |
1620 | | LOCRAsmNLE = 1605, |
1621 | | LOCRAsmNLH = 1606, |
1622 | | LOCRAsmNM = 1607, |
1623 | | LOCRAsmNO = 1608, |
1624 | | LOCRAsmNP = 1609, |
1625 | | LOCRAsmNZ = 1610, |
1626 | | LOCRAsmO = 1611, |
1627 | | LOCRAsmP = 1612, |
1628 | | LOCRAsmZ = 1613, |
1629 | | LPCTL = 1614, |
1630 | | LPD = 1615, |
1631 | | LPDBR = 1616, |
1632 | | LPDFR = 1617, |
1633 | | LPDFR_32 = 1618, |
1634 | | LPDG = 1619, |
1635 | | LPDR = 1620, |
1636 | | LPEBR = 1621, |
1637 | | LPER = 1622, |
1638 | | LPGFR = 1623, |
1639 | | LPGR = 1624, |
1640 | | LPP = 1625, |
1641 | | LPQ = 1626, |
1642 | | LPR = 1627, |
1643 | | LPSW = 1628, |
1644 | | LPSWE = 1629, |
1645 | | LPTEA = 1630, |
1646 | | LPXBR = 1631, |
1647 | | LPXR = 1632, |
1648 | | LR = 1633, |
1649 | | LRA = 1634, |
1650 | | LRAG = 1635, |
1651 | | LRAY = 1636, |
1652 | | LRDR = 1637, |
1653 | | LRER = 1638, |
1654 | | LRL = 1639, |
1655 | | LRV = 1640, |
1656 | | LRVG = 1641, |
1657 | | LRVGR = 1642, |
1658 | | LRVH = 1643, |
1659 | | LRVR = 1644, |
1660 | | LSCTL = 1645, |
1661 | | LT = 1646, |
1662 | | LTDBR = 1647, |
1663 | | LTDBRCompare = 1648, |
1664 | | LTDR = 1649, |
1665 | | LTDTR = 1650, |
1666 | | LTEBR = 1651, |
1667 | | LTEBRCompare = 1652, |
1668 | | LTER = 1653, |
1669 | | LTG = 1654, |
1670 | | LTGF = 1655, |
1671 | | LTGFR = 1656, |
1672 | | LTGR = 1657, |
1673 | | LTR = 1658, |
1674 | | LTXBR = 1659, |
1675 | | LTXBRCompare = 1660, |
1676 | | LTXR = 1661, |
1677 | | LTXTR = 1662, |
1678 | | LURA = 1663, |
1679 | | LURAG = 1664, |
1680 | | LXD = 1665, |
1681 | | LXDB = 1666, |
1682 | | LXDBR = 1667, |
1683 | | LXDR = 1668, |
1684 | | LXDTR = 1669, |
1685 | | LXE = 1670, |
1686 | | LXEB = 1671, |
1687 | | LXEBR = 1672, |
1688 | | LXER = 1673, |
1689 | | LXR = 1674, |
1690 | | LY = 1675, |
1691 | | LZDR = 1676, |
1692 | | LZER = 1677, |
1693 | | LZRF = 1678, |
1694 | | LZRG = 1679, |
1695 | | LZXR = 1680, |
1696 | | M = 1681, |
1697 | | MAD = 1682, |
1698 | | MADB = 1683, |
1699 | | MADBR = 1684, |
1700 | | MADR = 1685, |
1701 | | MAE = 1686, |
1702 | | MAEB = 1687, |
1703 | | MAEBR = 1688, |
1704 | | MAER = 1689, |
1705 | | MAY = 1690, |
1706 | | MAYH = 1691, |
1707 | | MAYHR = 1692, |
1708 | | MAYL = 1693, |
1709 | | MAYLR = 1694, |
1710 | | MAYR = 1695, |
1711 | | MC = 1696, |
1712 | | MD = 1697, |
1713 | | MDB = 1698, |
1714 | | MDBR = 1699, |
1715 | | MDE = 1700, |
1716 | | MDEB = 1701, |
1717 | | MDEBR = 1702, |
1718 | | MDER = 1703, |
1719 | | MDR = 1704, |
1720 | | MDTR = 1705, |
1721 | | MDTRA = 1706, |
1722 | | ME = 1707, |
1723 | | MEE = 1708, |
1724 | | MEEB = 1709, |
1725 | | MEEBR = 1710, |
1726 | | MEER = 1711, |
1727 | | MER = 1712, |
1728 | | MFY = 1713, |
1729 | | MG = 1714, |
1730 | | MGH = 1715, |
1731 | | MGHI = 1716, |
1732 | | MGRK = 1717, |
1733 | | MH = 1718, |
1734 | | MHI = 1719, |
1735 | | MHY = 1720, |
1736 | | ML = 1721, |
1737 | | MLG = 1722, |
1738 | | MLGR = 1723, |
1739 | | MLR = 1724, |
1740 | | MP = 1725, |
1741 | | MR = 1726, |
1742 | | MS = 1727, |
1743 | | MSC = 1728, |
1744 | | MSCH = 1729, |
1745 | | MSD = 1730, |
1746 | | MSDB = 1731, |
1747 | | MSDBR = 1732, |
1748 | | MSDR = 1733, |
1749 | | MSE = 1734, |
1750 | | MSEB = 1735, |
1751 | | MSEBR = 1736, |
1752 | | MSER = 1737, |
1753 | | MSFI = 1738, |
1754 | | MSG = 1739, |
1755 | | MSGC = 1740, |
1756 | | MSGF = 1741, |
1757 | | MSGFI = 1742, |
1758 | | MSGFR = 1743, |
1759 | | MSGR = 1744, |
1760 | | MSGRKC = 1745, |
1761 | | MSR = 1746, |
1762 | | MSRKC = 1747, |
1763 | | MSTA = 1748, |
1764 | | MSY = 1749, |
1765 | | MVC = 1750, |
1766 | | MVCDK = 1751, |
1767 | | MVCIN = 1752, |
1768 | | MVCK = 1753, |
1769 | | MVCL = 1754, |
1770 | | MVCLE = 1755, |
1771 | | MVCLU = 1756, |
1772 | | MVCOS = 1757, |
1773 | | MVCP = 1758, |
1774 | | MVCS = 1759, |
1775 | | MVCSK = 1760, |
1776 | | MVGHI = 1761, |
1777 | | MVHHI = 1762, |
1778 | | MVHI = 1763, |
1779 | | MVI = 1764, |
1780 | | MVIY = 1765, |
1781 | | MVN = 1766, |
1782 | | MVO = 1767, |
1783 | | MVPG = 1768, |
1784 | | MVST = 1769, |
1785 | | MVZ = 1770, |
1786 | | MXBR = 1771, |
1787 | | MXD = 1772, |
1788 | | MXDB = 1773, |
1789 | | MXDBR = 1774, |
1790 | | MXDR = 1775, |
1791 | | MXR = 1776, |
1792 | | MXTR = 1777, |
1793 | | MXTRA = 1778, |
1794 | | MY = 1779, |
1795 | | MYH = 1780, |
1796 | | MYHR = 1781, |
1797 | | MYL = 1782, |
1798 | | MYLR = 1783, |
1799 | | MYR = 1784, |
1800 | | N = 1785, |
1801 | | NC = 1786, |
1802 | | NG = 1787, |
1803 | | NGR = 1788, |
1804 | | NGRK = 1789, |
1805 | | NI = 1790, |
1806 | | NIAI = 1791, |
1807 | | NIHF = 1792, |
1808 | | NIHH = 1793, |
1809 | | NIHL = 1794, |
1810 | | NILF = 1795, |
1811 | | NILH = 1796, |
1812 | | NILL = 1797, |
1813 | | NIY = 1798, |
1814 | | NR = 1799, |
1815 | | NRK = 1800, |
1816 | | NTSTG = 1801, |
1817 | | NY = 1802, |
1818 | | O = 1803, |
1819 | | OC = 1804, |
1820 | | OG = 1805, |
1821 | | OGR = 1806, |
1822 | | OGRK = 1807, |
1823 | | OI = 1808, |
1824 | | OIHF = 1809, |
1825 | | OIHH = 1810, |
1826 | | OIHL = 1811, |
1827 | | OILF = 1812, |
1828 | | OILH = 1813, |
1829 | | OILL = 1814, |
1830 | | OIY = 1815, |
1831 | | OR = 1816, |
1832 | | ORK = 1817, |
1833 | | OY = 1818, |
1834 | | PACK = 1819, |
1835 | | PALB = 1820, |
1836 | | PC = 1821, |
1837 | | PCC = 1822, |
1838 | | PCKMO = 1823, |
1839 | | PFD = 1824, |
1840 | | PFDRL = 1825, |
1841 | | PFMF = 1826, |
1842 | | PFPO = 1827, |
1843 | | PGIN = 1828, |
1844 | | PGOUT = 1829, |
1845 | | PKA = 1830, |
1846 | | PKU = 1831, |
1847 | | PLO = 1832, |
1848 | | POPCNT = 1833, |
1849 | | PPA = 1834, |
1850 | | PPNO = 1835, |
1851 | | PR = 1836, |
1852 | | PRNO = 1837, |
1853 | | PT = 1838, |
1854 | | PTF = 1839, |
1855 | | PTFF = 1840, |
1856 | | PTI = 1841, |
1857 | | PTLB = 1842, |
1858 | | QADTR = 1843, |
1859 | | QAXTR = 1844, |
1860 | | QCTRI = 1845, |
1861 | | QSI = 1846, |
1862 | | RCHP = 1847, |
1863 | | RISBG = 1848, |
1864 | | RISBG32 = 1849, |
1865 | | RISBGN = 1850, |
1866 | | RISBHG = 1851, |
1867 | | RISBLG = 1852, |
1868 | | RLL = 1853, |
1869 | | RLLG = 1854, |
1870 | | RNSBG = 1855, |
1871 | | ROSBG = 1856, |
1872 | | RP = 1857, |
1873 | | RRBE = 1858, |
1874 | | RRBM = 1859, |
1875 | | RRDTR = 1860, |
1876 | | RRXTR = 1861, |
1877 | | RSCH = 1862, |
1878 | | RXSBG = 1863, |
1879 | | S = 1864, |
1880 | | SAC = 1865, |
1881 | | SACF = 1866, |
1882 | | SAL = 1867, |
1883 | | SAM24 = 1868, |
1884 | | SAM31 = 1869, |
1885 | | SAM64 = 1870, |
1886 | | SAR = 1871, |
1887 | | SCCTR = 1872, |
1888 | | SCHM = 1873, |
1889 | | SCK = 1874, |
1890 | | SCKC = 1875, |
1891 | | SCKPF = 1876, |
1892 | | SD = 1877, |
1893 | | SDB = 1878, |
1894 | | SDBR = 1879, |
1895 | | SDR = 1880, |
1896 | | SDTR = 1881, |
1897 | | SDTRA = 1882, |
1898 | | SE = 1883, |
1899 | | SEB = 1884, |
1900 | | SEBR = 1885, |
1901 | | SER = 1886, |
1902 | | SFASR = 1887, |
1903 | | SFPC = 1888, |
1904 | | SG = 1889, |
1905 | | SGF = 1890, |
1906 | | SGFR = 1891, |
1907 | | SGH = 1892, |
1908 | | SGR = 1893, |
1909 | | SGRK = 1894, |
1910 | | SH = 1895, |
1911 | | SHHHR = 1896, |
1912 | | SHHLR = 1897, |
1913 | | SHY = 1898, |
1914 | | SIE = 1899, |
1915 | | SIGA = 1900, |
1916 | | SIGP = 1901, |
1917 | | SL = 1902, |
1918 | | SLA = 1903, |
1919 | | SLAG = 1904, |
1920 | | SLAK = 1905, |
1921 | | SLB = 1906, |
1922 | | SLBG = 1907, |
1923 | | SLBGR = 1908, |
1924 | | SLBR = 1909, |
1925 | | SLDA = 1910, |
1926 | | SLDL = 1911, |
1927 | | SLDT = 1912, |
1928 | | SLFI = 1913, |
1929 | | SLG = 1914, |
1930 | | SLGF = 1915, |
1931 | | SLGFI = 1916, |
1932 | | SLGFR = 1917, |
1933 | | SLGR = 1918, |
1934 | | SLGRK = 1919, |
1935 | | SLHHHR = 1920, |
1936 | | SLHHLR = 1921, |
1937 | | SLL = 1922, |
1938 | | SLLG = 1923, |
1939 | | SLLK = 1924, |
1940 | | SLR = 1925, |
1941 | | SLRK = 1926, |
1942 | | SLXT = 1927, |
1943 | | SLY = 1928, |
1944 | | SP = 1929, |
1945 | | SPCTR = 1930, |
1946 | | SPKA = 1931, |
1947 | | SPM = 1932, |
1948 | | SPT = 1933, |
1949 | | SPX = 1934, |
1950 | | SQD = 1935, |
1951 | | SQDB = 1936, |
1952 | | SQDBR = 1937, |
1953 | | SQDR = 1938, |
1954 | | SQE = 1939, |
1955 | | SQEB = 1940, |
1956 | | SQEBR = 1941, |
1957 | | SQER = 1942, |
1958 | | SQXBR = 1943, |
1959 | | SQXR = 1944, |
1960 | | SR = 1945, |
1961 | | SRA = 1946, |
1962 | | SRAG = 1947, |
1963 | | SRAK = 1948, |
1964 | | SRDA = 1949, |
1965 | | SRDL = 1950, |
1966 | | SRDT = 1951, |
1967 | | SRK = 1952, |
1968 | | SRL = 1953, |
1969 | | SRLG = 1954, |
1970 | | SRLK = 1955, |
1971 | | SRNM = 1956, |
1972 | | SRNMB = 1957, |
1973 | | SRNMT = 1958, |
1974 | | SRP = 1959, |
1975 | | SRST = 1960, |
1976 | | SRSTU = 1961, |
1977 | | SRXT = 1962, |
1978 | | SSAIR = 1963, |
1979 | | SSAR = 1964, |
1980 | | SSCH = 1965, |
1981 | | SSKE = 1966, |
1982 | | SSKEOpt = 1967, |
1983 | | SSM = 1968, |
1984 | | ST = 1969, |
1985 | | STAM = 1970, |
1986 | | STAMY = 1971, |
1987 | | STAP = 1972, |
1988 | | STC = 1973, |
1989 | | STCH = 1974, |
1990 | | STCK = 1975, |
1991 | | STCKC = 1976, |
1992 | | STCKE = 1977, |
1993 | | STCKF = 1978, |
1994 | | STCM = 1979, |
1995 | | STCMH = 1980, |
1996 | | STCMY = 1981, |
1997 | | STCPS = 1982, |
1998 | | STCRW = 1983, |
1999 | | STCTG = 1984, |
2000 | | STCTL = 1985, |
2001 | | STCY = 1986, |
2002 | | STD = 1987, |
2003 | | STDY = 1988, |
2004 | | STE = 1989, |
2005 | | STEY = 1990, |
2006 | | STFH = 1991, |
2007 | | STFL = 1992, |
2008 | | STFLE = 1993, |
2009 | | STFPC = 1994, |
2010 | | STG = 1995, |
2011 | | STGRL = 1996, |
2012 | | STGSC = 1997, |
2013 | | STH = 1998, |
2014 | | STHH = 1999, |
2015 | | STHRL = 2000, |
2016 | | STHY = 2001, |
2017 | | STIDP = 2002, |
2018 | | STM = 2003, |
2019 | | STMG = 2004, |
2020 | | STMH = 2005, |
2021 | | STMY = 2006, |
2022 | | STNSM = 2007, |
2023 | | STOC = 2008, |
2024 | | STOCAsm = 2009, |
2025 | | STOCAsmE = 2010, |
2026 | | STOCAsmH = 2011, |
2027 | | STOCAsmHE = 2012, |
2028 | | STOCAsmL = 2013, |
2029 | | STOCAsmLE = 2014, |
2030 | | STOCAsmLH = 2015, |
2031 | | STOCAsmM = 2016, |
2032 | | STOCAsmNE = 2017, |
2033 | | STOCAsmNH = 2018, |
2034 | | STOCAsmNHE = 2019, |
2035 | | STOCAsmNL = 2020, |
2036 | | STOCAsmNLE = 2021, |
2037 | | STOCAsmNLH = 2022, |
2038 | | STOCAsmNM = 2023, |
2039 | | STOCAsmNO = 2024, |
2040 | | STOCAsmNP = 2025, |
2041 | | STOCAsmNZ = 2026, |
2042 | | STOCAsmO = 2027, |
2043 | | STOCAsmP = 2028, |
2044 | | STOCAsmZ = 2029, |
2045 | | STOCFH = 2030, |
2046 | | STOCFHAsm = 2031, |
2047 | | STOCFHAsmE = 2032, |
2048 | | STOCFHAsmH = 2033, |
2049 | | STOCFHAsmHE = 2034, |
2050 | | STOCFHAsmL = 2035, |
2051 | | STOCFHAsmLE = 2036, |
2052 | | STOCFHAsmLH = 2037, |
2053 | | STOCFHAsmM = 2038, |
2054 | | STOCFHAsmNE = 2039, |
2055 | | STOCFHAsmNH = 2040, |
2056 | | STOCFHAsmNHE = 2041, |
2057 | | STOCFHAsmNL = 2042, |
2058 | | STOCFHAsmNLE = 2043, |
2059 | | STOCFHAsmNLH = 2044, |
2060 | | STOCFHAsmNM = 2045, |
2061 | | STOCFHAsmNO = 2046, |
2062 | | STOCFHAsmNP = 2047, |
2063 | | STOCFHAsmNZ = 2048, |
2064 | | STOCFHAsmO = 2049, |
2065 | | STOCFHAsmP = 2050, |
2066 | | STOCFHAsmZ = 2051, |
2067 | | STOCG = 2052, |
2068 | | STOCGAsm = 2053, |
2069 | | STOCGAsmE = 2054, |
2070 | | STOCGAsmH = 2055, |
2071 | | STOCGAsmHE = 2056, |
2072 | | STOCGAsmL = 2057, |
2073 | | STOCGAsmLE = 2058, |
2074 | | STOCGAsmLH = 2059, |
2075 | | STOCGAsmM = 2060, |
2076 | | STOCGAsmNE = 2061, |
2077 | | STOCGAsmNH = 2062, |
2078 | | STOCGAsmNHE = 2063, |
2079 | | STOCGAsmNL = 2064, |
2080 | | STOCGAsmNLE = 2065, |
2081 | | STOCGAsmNLH = 2066, |
2082 | | STOCGAsmNM = 2067, |
2083 | | STOCGAsmNO = 2068, |
2084 | | STOCGAsmNP = 2069, |
2085 | | STOCGAsmNZ = 2070, |
2086 | | STOCGAsmO = 2071, |
2087 | | STOCGAsmP = 2072, |
2088 | | STOCGAsmZ = 2073, |
2089 | | STOSM = 2074, |
2090 | | STPQ = 2075, |
2091 | | STPT = 2076, |
2092 | | STPX = 2077, |
2093 | | STRAG = 2078, |
2094 | | STRL = 2079, |
2095 | | STRV = 2080, |
2096 | | STRVG = 2081, |
2097 | | STRVH = 2082, |
2098 | | STSCH = 2083, |
2099 | | STSI = 2084, |
2100 | | STURA = 2085, |
2101 | | STURG = 2086, |
2102 | | STY = 2087, |
2103 | | SU = 2088, |
2104 | | SUR = 2089, |
2105 | | SVC = 2090, |
2106 | | SW = 2091, |
2107 | | SWR = 2092, |
2108 | | SXBR = 2093, |
2109 | | SXR = 2094, |
2110 | | SXTR = 2095, |
2111 | | SXTRA = 2096, |
2112 | | SY = 2097, |
2113 | | TABORT = 2098, |
2114 | | TAM = 2099, |
2115 | | TAR = 2100, |
2116 | | TB = 2101, |
2117 | | TBDR = 2102, |
2118 | | TBEDR = 2103, |
2119 | | TBEGIN = 2104, |
2120 | | TBEGINC = 2105, |
2121 | | TCDB = 2106, |
2122 | | TCEB = 2107, |
2123 | | TCXB = 2108, |
2124 | | TDCDT = 2109, |
2125 | | TDCET = 2110, |
2126 | | TDCXT = 2111, |
2127 | | TDGDT = 2112, |
2128 | | TDGET = 2113, |
2129 | | TDGXT = 2114, |
2130 | | TEND = 2115, |
2131 | | THDER = 2116, |
2132 | | THDR = 2117, |
2133 | | TM = 2118, |
2134 | | TMHH = 2119, |
2135 | | TMHL = 2120, |
2136 | | TMLH = 2121, |
2137 | | TMLL = 2122, |
2138 | | TMY = 2123, |
2139 | | TP = 2124, |
2140 | | TPI = 2125, |
2141 | | TPROT = 2126, |
2142 | | TR = 2127, |
2143 | | TRACE = 2128, |
2144 | | TRACG = 2129, |
2145 | | TRAP2 = 2130, |
2146 | | TRAP4 = 2131, |
2147 | | TRE = 2132, |
2148 | | TROO = 2133, |
2149 | | TROOOpt = 2134, |
2150 | | TROT = 2135, |
2151 | | TROTOpt = 2136, |
2152 | | TRT = 2137, |
2153 | | TRTE = 2138, |
2154 | | TRTEOpt = 2139, |
2155 | | TRTO = 2140, |
2156 | | TRTOOpt = 2141, |
2157 | | TRTR = 2142, |
2158 | | TRTRE = 2143, |
2159 | | TRTREOpt = 2144, |
2160 | | TRTT = 2145, |
2161 | | TRTTOpt = 2146, |
2162 | | TS = 2147, |
2163 | | TSCH = 2148, |
2164 | | UNPK = 2149, |
2165 | | UNPKA = 2150, |
2166 | | UNPKU = 2151, |
2167 | | UPT = 2152, |
2168 | | VA = 2153, |
2169 | | VAB = 2154, |
2170 | | VAC = 2155, |
2171 | | VACC = 2156, |
2172 | | VACCB = 2157, |
2173 | | VACCC = 2158, |
2174 | | VACCCQ = 2159, |
2175 | | VACCF = 2160, |
2176 | | VACCG = 2161, |
2177 | | VACCH = 2162, |
2178 | | VACCQ = 2163, |
2179 | | VACQ = 2164, |
2180 | | VAF = 2165, |
2181 | | VAG = 2166, |
2182 | | VAH = 2167, |
2183 | | VAP = 2168, |
2184 | | VAQ = 2169, |
2185 | | VAVG = 2170, |
2186 | | VAVGB = 2171, |
2187 | | VAVGF = 2172, |
2188 | | VAVGG = 2173, |
2189 | | VAVGH = 2174, |
2190 | | VAVGL = 2175, |
2191 | | VAVGLB = 2176, |
2192 | | VAVGLF = 2177, |
2193 | | VAVGLG = 2178, |
2194 | | VAVGLH = 2179, |
2195 | | VBPERM = 2180, |
2196 | | VCDG = 2181, |
2197 | | VCDGB = 2182, |
2198 | | VCDLG = 2183, |
2199 | | VCDLGB = 2184, |
2200 | | VCEQ = 2185, |
2201 | | VCEQB = 2186, |
2202 | | VCEQBS = 2187, |
2203 | | VCEQF = 2188, |
2204 | | VCEQFS = 2189, |
2205 | | VCEQG = 2190, |
2206 | | VCEQGS = 2191, |
2207 | | VCEQH = 2192, |
2208 | | VCEQHS = 2193, |
2209 | | VCGD = 2194, |
2210 | | VCGDB = 2195, |
2211 | | VCH = 2196, |
2212 | | VCHB = 2197, |
2213 | | VCHBS = 2198, |
2214 | | VCHF = 2199, |
2215 | | VCHFS = 2200, |
2216 | | VCHG = 2201, |
2217 | | VCHGS = 2202, |
2218 | | VCHH = 2203, |
2219 | | VCHHS = 2204, |
2220 | | VCHL = 2205, |
2221 | | VCHLB = 2206, |
2222 | | VCHLBS = 2207, |
2223 | | VCHLF = 2208, |
2224 | | VCHLFS = 2209, |
2225 | | VCHLG = 2210, |
2226 | | VCHLGS = 2211, |
2227 | | VCHLH = 2212, |
2228 | | VCHLHS = 2213, |
2229 | | VCKSM = 2214, |
2230 | | VCLGD = 2215, |
2231 | | VCLGDB = 2216, |
2232 | | VCLZ = 2217, |
2233 | | VCLZB = 2218, |
2234 | | VCLZF = 2219, |
2235 | | VCLZG = 2220, |
2236 | | VCLZH = 2221, |
2237 | | VCP = 2222, |
2238 | | VCTZ = 2223, |
2239 | | VCTZB = 2224, |
2240 | | VCTZF = 2225, |
2241 | | VCTZG = 2226, |
2242 | | VCTZH = 2227, |
2243 | | VCVB = 2228, |
2244 | | VCVBG = 2229, |
2245 | | VCVD = 2230, |
2246 | | VCVDG = 2231, |
2247 | | VDP = 2232, |
2248 | | VEC = 2233, |
2249 | | VECB = 2234, |
2250 | | VECF = 2235, |
2251 | | VECG = 2236, |
2252 | | VECH = 2237, |
2253 | | VECL = 2238, |
2254 | | VECLB = 2239, |
2255 | | VECLF = 2240, |
2256 | | VECLG = 2241, |
2257 | | VECLH = 2242, |
2258 | | VERIM = 2243, |
2259 | | VERIMB = 2244, |
2260 | | VERIMF = 2245, |
2261 | | VERIMG = 2246, |
2262 | | VERIMH = 2247, |
2263 | | VERLL = 2248, |
2264 | | VERLLB = 2249, |
2265 | | VERLLF = 2250, |
2266 | | VERLLG = 2251, |
2267 | | VERLLH = 2252, |
2268 | | VERLLV = 2253, |
2269 | | VERLLVB = 2254, |
2270 | | VERLLVF = 2255, |
2271 | | VERLLVG = 2256, |
2272 | | VERLLVH = 2257, |
2273 | | VESL = 2258, |
2274 | | VESLB = 2259, |
2275 | | VESLF = 2260, |
2276 | | VESLG = 2261, |
2277 | | VESLH = 2262, |
2278 | | VESLV = 2263, |
2279 | | VESLVB = 2264, |
2280 | | VESLVF = 2265, |
2281 | | VESLVG = 2266, |
2282 | | VESLVH = 2267, |
2283 | | VESRA = 2268, |
2284 | | VESRAB = 2269, |
2285 | | VESRAF = 2270, |
2286 | | VESRAG = 2271, |
2287 | | VESRAH = 2272, |
2288 | | VESRAV = 2273, |
2289 | | VESRAVB = 2274, |
2290 | | VESRAVF = 2275, |
2291 | | VESRAVG = 2276, |
2292 | | VESRAVH = 2277, |
2293 | | VESRL = 2278, |
2294 | | VESRLB = 2279, |
2295 | | VESRLF = 2280, |
2296 | | VESRLG = 2281, |
2297 | | VESRLH = 2282, |
2298 | | VESRLV = 2283, |
2299 | | VESRLVB = 2284, |
2300 | | VESRLVF = 2285, |
2301 | | VESRLVG = 2286, |
2302 | | VESRLVH = 2287, |
2303 | | VFA = 2288, |
2304 | | VFADB = 2289, |
2305 | | VFAE = 2290, |
2306 | | VFAEB = 2291, |
2307 | | VFAEBS = 2292, |
2308 | | VFAEF = 2293, |
2309 | | VFAEFS = 2294, |
2310 | | VFAEH = 2295, |
2311 | | VFAEHS = 2296, |
2312 | | VFAEZB = 2297, |
2313 | | VFAEZBS = 2298, |
2314 | | VFAEZF = 2299, |
2315 | | VFAEZFS = 2300, |
2316 | | VFAEZH = 2301, |
2317 | | VFAEZHS = 2302, |
2318 | | VFASB = 2303, |
2319 | | VFCE = 2304, |
2320 | | VFCEDB = 2305, |
2321 | | VFCEDBS = 2306, |
2322 | | VFCESB = 2307, |
2323 | | VFCESBS = 2308, |
2324 | | VFCH = 2309, |
2325 | | VFCHDB = 2310, |
2326 | | VFCHDBS = 2311, |
2327 | | VFCHE = 2312, |
2328 | | VFCHEDB = 2313, |
2329 | | VFCHEDBS = 2314, |
2330 | | VFCHESB = 2315, |
2331 | | VFCHESBS = 2316, |
2332 | | VFCHSB = 2317, |
2333 | | VFCHSBS = 2318, |
2334 | | VFD = 2319, |
2335 | | VFDDB = 2320, |
2336 | | VFDSB = 2321, |
2337 | | VFEE = 2322, |
2338 | | VFEEB = 2323, |
2339 | | VFEEBS = 2324, |
2340 | | VFEEF = 2325, |
2341 | | VFEEFS = 2326, |
2342 | | VFEEH = 2327, |
2343 | | VFEEHS = 2328, |
2344 | | VFEEZB = 2329, |
2345 | | VFEEZBS = 2330, |
2346 | | VFEEZF = 2331, |
2347 | | VFEEZFS = 2332, |
2348 | | VFEEZH = 2333, |
2349 | | VFEEZHS = 2334, |
2350 | | VFENE = 2335, |
2351 | | VFENEB = 2336, |
2352 | | VFENEBS = 2337, |
2353 | | VFENEF = 2338, |
2354 | | VFENEFS = 2339, |
2355 | | VFENEH = 2340, |
2356 | | VFENEHS = 2341, |
2357 | | VFENEZB = 2342, |
2358 | | VFENEZBS = 2343, |
2359 | | VFENEZF = 2344, |
2360 | | VFENEZFS = 2345, |
2361 | | VFENEZH = 2346, |
2362 | | VFENEZHS = 2347, |
2363 | | VFI = 2348, |
2364 | | VFIDB = 2349, |
2365 | | VFISB = 2350, |
2366 | | VFKEDB = 2351, |
2367 | | VFKEDBS = 2352, |
2368 | | VFKESB = 2353, |
2369 | | VFKESBS = 2354, |
2370 | | VFKHDB = 2355, |
2371 | | VFKHDBS = 2356, |
2372 | | VFKHEDB = 2357, |
2373 | | VFKHEDBS = 2358, |
2374 | | VFKHESB = 2359, |
2375 | | VFKHESBS = 2360, |
2376 | | VFKHSB = 2361, |
2377 | | VFKHSBS = 2362, |
2378 | | VFLCDB = 2363, |
2379 | | VFLCSB = 2364, |
2380 | | VFLL = 2365, |
2381 | | VFLLS = 2366, |
2382 | | VFLNDB = 2367, |
2383 | | VFLNSB = 2368, |
2384 | | VFLPDB = 2369, |
2385 | | VFLPSB = 2370, |
2386 | | VFLR = 2371, |
2387 | | VFLRD = 2372, |
2388 | | VFM = 2373, |
2389 | | VFMA = 2374, |
2390 | | VFMADB = 2375, |
2391 | | VFMASB = 2376, |
2392 | | VFMAX = 2377, |
2393 | | VFMAXDB = 2378, |
2394 | | VFMAXSB = 2379, |
2395 | | VFMDB = 2380, |
2396 | | VFMIN = 2381, |
2397 | | VFMINDB = 2382, |
2398 | | VFMINSB = 2383, |
2399 | | VFMS = 2384, |
2400 | | VFMSB = 2385, |
2401 | | VFMSDB = 2386, |
2402 | | VFMSSB = 2387, |
2403 | | VFNMA = 2388, |
2404 | | VFNMADB = 2389, |
2405 | | VFNMASB = 2390, |
2406 | | VFNMS = 2391, |
2407 | | VFNMSDB = 2392, |
2408 | | VFNMSSB = 2393, |
2409 | | VFPSO = 2394, |
2410 | | VFPSODB = 2395, |
2411 | | VFPSOSB = 2396, |
2412 | | VFS = 2397, |
2413 | | VFSDB = 2398, |
2414 | | VFSQ = 2399, |
2415 | | VFSQDB = 2400, |
2416 | | VFSQSB = 2401, |
2417 | | VFSSB = 2402, |
2418 | | VFTCI = 2403, |
2419 | | VFTCIDB = 2404, |
2420 | | VFTCISB = 2405, |
2421 | | VGBM = 2406, |
2422 | | VGEF = 2407, |
2423 | | VGEG = 2408, |
2424 | | VGFM = 2409, |
2425 | | VGFMA = 2410, |
2426 | | VGFMAB = 2411, |
2427 | | VGFMAF = 2412, |
2428 | | VGFMAG = 2413, |
2429 | | VGFMAH = 2414, |
2430 | | VGFMB = 2415, |
2431 | | VGFMF = 2416, |
2432 | | VGFMG = 2417, |
2433 | | VGFMH = 2418, |
2434 | | VGM = 2419, |
2435 | | VGMB = 2420, |
2436 | | VGMF = 2421, |
2437 | | VGMG = 2422, |
2438 | | VGMH = 2423, |
2439 | | VISTR = 2424, |
2440 | | VISTRB = 2425, |
2441 | | VISTRBS = 2426, |
2442 | | VISTRF = 2427, |
2443 | | VISTRFS = 2428, |
2444 | | VISTRH = 2429, |
2445 | | VISTRHS = 2430, |
2446 | | VL = 2431, |
2447 | | VLBB = 2432, |
2448 | | VLC = 2433, |
2449 | | VLCB = 2434, |
2450 | | VLCF = 2435, |
2451 | | VLCG = 2436, |
2452 | | VLCH = 2437, |
2453 | | VLDE = 2438, |
2454 | | VLDEB = 2439, |
2455 | | VLEB = 2440, |
2456 | | VLED = 2441, |
2457 | | VLEDB = 2442, |
2458 | | VLEF = 2443, |
2459 | | VLEG = 2444, |
2460 | | VLEH = 2445, |
2461 | | VLEIB = 2446, |
2462 | | VLEIF = 2447, |
2463 | | VLEIG = 2448, |
2464 | | VLEIH = 2449, |
2465 | | VLGV = 2450, |
2466 | | VLGVB = 2451, |
2467 | | VLGVF = 2452, |
2468 | | VLGVG = 2453, |
2469 | | VLGVH = 2454, |
2470 | | VLIP = 2455, |
2471 | | VLL = 2456, |
2472 | | VLLEZ = 2457, |
2473 | | VLLEZB = 2458, |
2474 | | VLLEZF = 2459, |
2475 | | VLLEZG = 2460, |
2476 | | VLLEZH = 2461, |
2477 | | VLLEZLF = 2462, |
2478 | | VLM = 2463, |
2479 | | VLP = 2464, |
2480 | | VLPB = 2465, |
2481 | | VLPF = 2466, |
2482 | | VLPG = 2467, |
2483 | | VLPH = 2468, |
2484 | | VLR = 2469, |
2485 | | VLREP = 2470, |
2486 | | VLREPB = 2471, |
2487 | | VLREPF = 2472, |
2488 | | VLREPG = 2473, |
2489 | | VLREPH = 2474, |
2490 | | VLRL = 2475, |
2491 | | VLRLR = 2476, |
2492 | | VLVG = 2477, |
2493 | | VLVGB = 2478, |
2494 | | VLVGF = 2479, |
2495 | | VLVGG = 2480, |
2496 | | VLVGH = 2481, |
2497 | | VLVGP = 2482, |
2498 | | VMAE = 2483, |
2499 | | VMAEB = 2484, |
2500 | | VMAEF = 2485, |
2501 | | VMAEH = 2486, |
2502 | | VMAH = 2487, |
2503 | | VMAHB = 2488, |
2504 | | VMAHF = 2489, |
2505 | | VMAHH = 2490, |
2506 | | VMAL = 2491, |
2507 | | VMALB = 2492, |
2508 | | VMALE = 2493, |
2509 | | VMALEB = 2494, |
2510 | | VMALEF = 2495, |
2511 | | VMALEH = 2496, |
2512 | | VMALF = 2497, |
2513 | | VMALH = 2498, |
2514 | | VMALHB = 2499, |
2515 | | VMALHF = 2500, |
2516 | | VMALHH = 2501, |
2517 | | VMALHW = 2502, |
2518 | | VMALO = 2503, |
2519 | | VMALOB = 2504, |
2520 | | VMALOF = 2505, |
2521 | | VMALOH = 2506, |
2522 | | VMAO = 2507, |
2523 | | VMAOB = 2508, |
2524 | | VMAOF = 2509, |
2525 | | VMAOH = 2510, |
2526 | | VME = 2511, |
2527 | | VMEB = 2512, |
2528 | | VMEF = 2513, |
2529 | | VMEH = 2514, |
2530 | | VMH = 2515, |
2531 | | VMHB = 2516, |
2532 | | VMHF = 2517, |
2533 | | VMHH = 2518, |
2534 | | VML = 2519, |
2535 | | VMLB = 2520, |
2536 | | VMLE = 2521, |
2537 | | VMLEB = 2522, |
2538 | | VMLEF = 2523, |
2539 | | VMLEH = 2524, |
2540 | | VMLF = 2525, |
2541 | | VMLH = 2526, |
2542 | | VMLHB = 2527, |
2543 | | VMLHF = 2528, |
2544 | | VMLHH = 2529, |
2545 | | VMLHW = 2530, |
2546 | | VMLO = 2531, |
2547 | | VMLOB = 2532, |
2548 | | VMLOF = 2533, |
2549 | | VMLOH = 2534, |
2550 | | VMN = 2535, |
2551 | | VMNB = 2536, |
2552 | | VMNF = 2537, |
2553 | | VMNG = 2538, |
2554 | | VMNH = 2539, |
2555 | | VMNL = 2540, |
2556 | | VMNLB = 2541, |
2557 | | VMNLF = 2542, |
2558 | | VMNLG = 2543, |
2559 | | VMNLH = 2544, |
2560 | | VMO = 2545, |
2561 | | VMOB = 2546, |
2562 | | VMOF = 2547, |
2563 | | VMOH = 2548, |
2564 | | VMP = 2549, |
2565 | | VMRH = 2550, |
2566 | | VMRHB = 2551, |
2567 | | VMRHF = 2552, |
2568 | | VMRHG = 2553, |
2569 | | VMRHH = 2554, |
2570 | | VMRL = 2555, |
2571 | | VMRLB = 2556, |
2572 | | VMRLF = 2557, |
2573 | | VMRLG = 2558, |
2574 | | VMRLH = 2559, |
2575 | | VMSL = 2560, |
2576 | | VMSLG = 2561, |
2577 | | VMSP = 2562, |
2578 | | VMX = 2563, |
2579 | | VMXB = 2564, |
2580 | | VMXF = 2565, |
2581 | | VMXG = 2566, |
2582 | | VMXH = 2567, |
2583 | | VMXL = 2568, |
2584 | | VMXLB = 2569, |
2585 | | VMXLF = 2570, |
2586 | | VMXLG = 2571, |
2587 | | VMXLH = 2572, |
2588 | | VN = 2573, |
2589 | | VNC = 2574, |
2590 | | VNN = 2575, |
2591 | | VNO = 2576, |
2592 | | VNX = 2577, |
2593 | | VO = 2578, |
2594 | | VOC = 2579, |
2595 | | VONE = 2580, |
2596 | | VPDI = 2581, |
2597 | | VPERM = 2582, |
2598 | | VPK = 2583, |
2599 | | VPKF = 2584, |
2600 | | VPKG = 2585, |
2601 | | VPKH = 2586, |
2602 | | VPKLS = 2587, |
2603 | | VPKLSF = 2588, |
2604 | | VPKLSFS = 2589, |
2605 | | VPKLSG = 2590, |
2606 | | VPKLSGS = 2591, |
2607 | | VPKLSH = 2592, |
2608 | | VPKLSHS = 2593, |
2609 | | VPKS = 2594, |
2610 | | VPKSF = 2595, |
2611 | | VPKSFS = 2596, |
2612 | | VPKSG = 2597, |
2613 | | VPKSGS = 2598, |
2614 | | VPKSH = 2599, |
2615 | | VPKSHS = 2600, |
2616 | | VPKZ = 2601, |
2617 | | VPOPCT = 2602, |
2618 | | VPOPCTB = 2603, |
2619 | | VPOPCTF = 2604, |
2620 | | VPOPCTG = 2605, |
2621 | | VPOPCTH = 2606, |
2622 | | VPSOP = 2607, |
2623 | | VREP = 2608, |
2624 | | VREPB = 2609, |
2625 | | VREPF = 2610, |
2626 | | VREPG = 2611, |
2627 | | VREPH = 2612, |
2628 | | VREPI = 2613, |
2629 | | VREPIB = 2614, |
2630 | | VREPIF = 2615, |
2631 | | VREPIG = 2616, |
2632 | | VREPIH = 2617, |
2633 | | VRP = 2618, |
2634 | | VS = 2619, |
2635 | | VSB = 2620, |
2636 | | VSBCBI = 2621, |
2637 | | VSBCBIQ = 2622, |
2638 | | VSBI = 2623, |
2639 | | VSBIQ = 2624, |
2640 | | VSCBI = 2625, |
2641 | | VSCBIB = 2626, |
2642 | | VSCBIF = 2627, |
2643 | | VSCBIG = 2628, |
2644 | | VSCBIH = 2629, |
2645 | | VSCBIQ = 2630, |
2646 | | VSCEF = 2631, |
2647 | | VSCEG = 2632, |
2648 | | VSDP = 2633, |
2649 | | VSEG = 2634, |
2650 | | VSEGB = 2635, |
2651 | | VSEGF = 2636, |
2652 | | VSEGH = 2637, |
2653 | | VSEL = 2638, |
2654 | | VSF = 2639, |
2655 | | VSG = 2640, |
2656 | | VSH = 2641, |
2657 | | VSL = 2642, |
2658 | | VSLB = 2643, |
2659 | | VSLDB = 2644, |
2660 | | VSP = 2645, |
2661 | | VSQ = 2646, |
2662 | | VSRA = 2647, |
2663 | | VSRAB = 2648, |
2664 | | VSRL = 2649, |
2665 | | VSRLB = 2650, |
2666 | | VSRP = 2651, |
2667 | | VST = 2652, |
2668 | | VSTEB = 2653, |
2669 | | VSTEF = 2654, |
2670 | | VSTEG = 2655, |
2671 | | VSTEH = 2656, |
2672 | | VSTL = 2657, |
2673 | | VSTM = 2658, |
2674 | | VSTRC = 2659, |
2675 | | VSTRCB = 2660, |
2676 | | VSTRCBS = 2661, |
2677 | | VSTRCF = 2662, |
2678 | | VSTRCFS = 2663, |
2679 | | VSTRCH = 2664, |
2680 | | VSTRCHS = 2665, |
2681 | | VSTRCZB = 2666, |
2682 | | VSTRCZBS = 2667, |
2683 | | VSTRCZF = 2668, |
2684 | | VSTRCZFS = 2669, |
2685 | | VSTRCZH = 2670, |
2686 | | VSTRCZHS = 2671, |
2687 | | VSTRL = 2672, |
2688 | | VSTRLR = 2673, |
2689 | | VSUM = 2674, |
2690 | | VSUMB = 2675, |
2691 | | VSUMG = 2676, |
2692 | | VSUMGF = 2677, |
2693 | | VSUMGH = 2678, |
2694 | | VSUMH = 2679, |
2695 | | VSUMQ = 2680, |
2696 | | VSUMQF = 2681, |
2697 | | VSUMQG = 2682, |
2698 | | VTM = 2683, |
2699 | | VTP = 2684, |
2700 | | VUPH = 2685, |
2701 | | VUPHB = 2686, |
2702 | | VUPHF = 2687, |
2703 | | VUPHH = 2688, |
2704 | | VUPKZ = 2689, |
2705 | | VUPL = 2690, |
2706 | | VUPLB = 2691, |
2707 | | VUPLF = 2692, |
2708 | | VUPLH = 2693, |
2709 | | VUPLHB = 2694, |
2710 | | VUPLHF = 2695, |
2711 | | VUPLHH = 2696, |
2712 | | VUPLHW = 2697, |
2713 | | VUPLL = 2698, |
2714 | | VUPLLB = 2699, |
2715 | | VUPLLF = 2700, |
2716 | | VUPLLH = 2701, |
2717 | | VX = 2702, |
2718 | | VZERO = 2703, |
2719 | | WCDGB = 2704, |
2720 | | WCDLGB = 2705, |
2721 | | WCGDB = 2706, |
2722 | | WCLGDB = 2707, |
2723 | | WFADB = 2708, |
2724 | | WFASB = 2709, |
2725 | | WFAXB = 2710, |
2726 | | WFC = 2711, |
2727 | | WFCDB = 2712, |
2728 | | WFCEDB = 2713, |
2729 | | WFCEDBS = 2714, |
2730 | | WFCESB = 2715, |
2731 | | WFCESBS = 2716, |
2732 | | WFCEXB = 2717, |
2733 | | WFCEXBS = 2718, |
2734 | | WFCHDB = 2719, |
2735 | | WFCHDBS = 2720, |
2736 | | WFCHEDB = 2721, |
2737 | | WFCHEDBS = 2722, |
2738 | | WFCHESB = 2723, |
2739 | | WFCHESBS = 2724, |
2740 | | WFCHEXB = 2725, |
2741 | | WFCHEXBS = 2726, |
2742 | | WFCHSB = 2727, |
2743 | | WFCHSBS = 2728, |
2744 | | WFCHXB = 2729, |
2745 | | WFCHXBS = 2730, |
2746 | | WFCSB = 2731, |
2747 | | WFCXB = 2732, |
2748 | | WFDDB = 2733, |
2749 | | WFDSB = 2734, |
2750 | | WFDXB = 2735, |
2751 | | WFIDB = 2736, |
2752 | | WFISB = 2737, |
2753 | | WFIXB = 2738, |
2754 | | WFK = 2739, |
2755 | | WFKDB = 2740, |
2756 | | WFKEDB = 2741, |
2757 | | WFKEDBS = 2742, |
2758 | | WFKESB = 2743, |
2759 | | WFKESBS = 2744, |
2760 | | WFKEXB = 2745, |
2761 | | WFKEXBS = 2746, |
2762 | | WFKHDB = 2747, |
2763 | | WFKHDBS = 2748, |
2764 | | WFKHEDB = 2749, |
2765 | | WFKHEDBS = 2750, |
2766 | | WFKHESB = 2751, |
2767 | | WFKHESBS = 2752, |
2768 | | WFKHEXB = 2753, |
2769 | | WFKHEXBS = 2754, |
2770 | | WFKHSB = 2755, |
2771 | | WFKHSBS = 2756, |
2772 | | WFKHXB = 2757, |
2773 | | WFKHXBS = 2758, |
2774 | | WFKSB = 2759, |
2775 | | WFKXB = 2760, |
2776 | | WFLCDB = 2761, |
2777 | | WFLCSB = 2762, |
2778 | | WFLCXB = 2763, |
2779 | | WFLLD = 2764, |
2780 | | WFLLS = 2765, |
2781 | | WFLNDB = 2766, |
2782 | | WFLNSB = 2767, |
2783 | | WFLNXB = 2768, |
2784 | | WFLPDB = 2769, |
2785 | | WFLPSB = 2770, |
2786 | | WFLPXB = 2771, |
2787 | | WFLRD = 2772, |
2788 | | WFLRX = 2773, |
2789 | | WFMADB = 2774, |
2790 | | WFMASB = 2775, |
2791 | | WFMAXB = 2776, |
2792 | | WFMAXDB = 2777, |
2793 | | WFMAXSB = 2778, |
2794 | | WFMAXXB = 2779, |
2795 | | WFMDB = 2780, |
2796 | | WFMINDB = 2781, |
2797 | | WFMINSB = 2782, |
2798 | | WFMINXB = 2783, |
2799 | | WFMSB = 2784, |
2800 | | WFMSDB = 2785, |
2801 | | WFMSSB = 2786, |
2802 | | WFMSXB = 2787, |
2803 | | WFMXB = 2788, |
2804 | | WFNMADB = 2789, |
2805 | | WFNMASB = 2790, |
2806 | | WFNMAXB = 2791, |
2807 | | WFNMSDB = 2792, |
2808 | | WFNMSSB = 2793, |
2809 | | WFNMSXB = 2794, |
2810 | | WFPSODB = 2795, |
2811 | | WFPSOSB = 2796, |
2812 | | WFPSOXB = 2797, |
2813 | | WFSDB = 2798, |
2814 | | WFSQDB = 2799, |
2815 | | WFSQSB = 2800, |
2816 | | WFSQXB = 2801, |
2817 | | WFSSB = 2802, |
2818 | | WFSXB = 2803, |
2819 | | WFTCIDB = 2804, |
2820 | | WFTCISB = 2805, |
2821 | | WFTCIXB = 2806, |
2822 | | WLDEB = 2807, |
2823 | | WLEDB = 2808, |
2824 | | X = 2809, |
2825 | | XC = 2810, |
2826 | | XG = 2811, |
2827 | | XGR = 2812, |
2828 | | XGRK = 2813, |
2829 | | XI = 2814, |
2830 | | XIHF = 2815, |
2831 | | XILF = 2816, |
2832 | | XIY = 2817, |
2833 | | XR = 2818, |
2834 | | XRK = 2819, |
2835 | | XSCH = 2820, |
2836 | | XY = 2821, |
2837 | | ZAP = 2822, |
2838 | | INSTRUCTION_LIST_END = 2823 |
2839 | | }; |
2840 | | |
2841 | | } // end SystemZ namespace |
2842 | | } // end llvm namespace |
2843 | | #endif // GET_INSTRINFO_ENUM |
2844 | | |
2845 | | #ifdef GET_INSTRINFO_SCHED_ENUM |
2846 | | #undef GET_INSTRINFO_SCHED_ENUM |
2847 | | namespace llvm { |
2848 | | |
2849 | | namespace SystemZ { |
2850 | | namespace Sched { |
2851 | | enum { |
2852 | | NoInstrModel = 0, |
2853 | | ADJDYNALLOC = 1, |
2854 | | CallBRCL_BRC_BRCAsm_BRCL_BRCLAsm = 2, |
2855 | | CallJG_J_JAsmE_JAsmH_JAsmHE_JAsmL_JAsmLE_JAsmLH_JAsmM_JAsmNE_JAsmNH_JAsmNHE_JAsmNL_JAsmNLE_JAsmNLH_JAsmNM_JAsmNO_JAsmNP_JAsmNZ_JAsmO_JAsmP_JAsmZ_JG_JGAsmE_JGAsmH_JGAsmHE_JGAsmL_JGAsmLE_JGAsmLH_JGAsmM_JGAsmNE_JGAsmNH_JGAsmNHE_JGAsmNL_JGAsmNLE_JGAsmNLH_JGAsmNM_JGAsmNO_JGAsmNP_JGAsmNZ_JGAsmO_JGAsmP_JGAsmZ = 3, |
2856 | | CallBCR_BC_BCAsm_BCR_BCRAsm = 4, |
2857 | | CallBR_B_BAsmE_BAsmH_BAsmHE_BAsmL_BAsmLE_BAsmLH_BAsmM_BAsmNE_BAsmNH_BAsmNHE_BAsmNL_BAsmNLE_BAsmNLH_BAsmNM_BAsmNO_BAsmNP_BAsmNZ_BAsmO_BAsmP_BAsmZ_BR_BRAsmE_BRAsmH_BRAsmHE_BRAsmL_BRAsmLE_BRAsmLH_BRAsmM_BRAsmNE_BRAsmNH_BRAsmNHE_BRAsmNL_BRAsmNLE_BRAsmNLH_BRAsmNM_BRAsmNO_BRAsmNP_BRAsmNZ_BRAsmO_BRAsmP_BRAsmZ = 5, |
2858 | | BI_BIAsmE_BIAsmH_BIAsmHE_BIAsmL_BIAsmLE_BIAsmLH_BIAsmM_BIAsmNE_BIAsmNH_BIAsmNHE_BIAsmNL_BIAsmNLE_BIAsmNLH_BIAsmNM_BIAsmNO_BIAsmNP_BIAsmNZ_BIAsmO_BIAsmP_BIAsmZ_BIC_BICAsm = 6, |
2859 | | BRCT_BRCTG = 7, |
2860 | | BRCTH = 8, |
2861 | | BCT_BCTG_BCTGR_BCTR = 9, |
2862 | | BRXH_BRXHG_BRXLE_BRXLG_BXH_BXHG_BXLE_BXLEG = 10, |
2863 | | CGIJ_CGIJAsm_CGIJAsmE_CGIJAsmH_CGIJAsmHE_CGIJAsmL_CGIJAsmLE_CGIJAsmLH_CGIJAsmNE_CGIJAsmNH_CGIJAsmNHE_CGIJAsmNL_CGIJAsmNLE_CGIJAsmNLH_CGRJ_CGRJAsm_CGRJAsmE_CGRJAsmH_CGRJAsmHE_CGRJAsmL_CGRJAsmLE_CGRJAsmLH_CGRJAsmNE_CGRJAsmNH_CGRJAsmNHE_CGRJAsmNL_CGRJAsmNLE_CGRJAsmNLH_CIJ_CIJAsm_CIJAsmE_CIJAsmH_CIJAsmHE_CIJAsmL_CIJAsmLE_CIJAsmLH_CIJAsmNE_CIJAsmNH_CIJAsmNHE_CIJAsmNL_CIJAsmNLE_CIJAsmNLH_CLGIJ_CLGIJAsm_CLGIJAsmE_CLGIJAsmH_CLGIJAsmHE_CLGIJAsmL_CLGIJAsmLE_CLGIJAsmLH_CLGIJAsmNE_CLGIJAsmNH_CLGIJAsmNHE_CLGIJAsmNL_CLGIJAsmNLE_CLGIJAsmNLH_CLGRJ_CLGRJAsm_CLGRJAsmE_CLGRJAsmH_CLGRJAsmHE_CLGRJAsmL_CLGRJAsmLE_CLGRJAsmLH_CLGRJAsmNE_CLGRJAsmNH_CLGRJAsmNHE_CLGRJAsmNL_CLGRJAsmNLE_CLGRJAsmNLH_CLIJ_CLIJAsm_CLIJAsmE_CLIJAsmH_CLIJAsmHE_CLIJAsmL_CLIJAsmLE_CLIJAsmLH_CLIJAsmNE_CLIJAsmNH_CLIJAsmNHE_CLIJAsmNL_CLIJAsmNLE_CLIJAsmNLH_CLRJ_CLRJAsm_CLRJAsmE_CLRJAsmH_CLRJAsmHE_CLRJAsmL_CLRJAsmLE_CLRJAsmLH_CLRJAsmNE_CLRJAsmNH_CLRJAsmNHE_CLRJAsmNL_CLRJAsmNLE_CLRJAsmNLH_CRJ_CRJAsm_CRJAsmE_CRJAsmH_CRJAsmHE_CRJAsmL_CRJAsmLE_CRJAsmLH_CRJAsmNE_CRJAsmNH_CRJAsmNHE_CRJAsmNL_CRJAsmNLE_CRJAsmNLH = 11, |
2864 | | CGIBCall_CGIBReturn_CGRBCall_CGRBReturn_CIBCall_CIBReturn_CLGIBCall_CLGIBReturn_CLGRBCall_CLGRBReturn_CLIBCall_CLIBReturn_CLRBCall_CLRBReturn_CRBCall_CRBReturn_CGIB_CGIBAsm_CGIBAsmE_CGIBAsmH_CGIBAsmHE_CGIBAsmL_CGIBAsmLE_CGIBAsmLH_CGIBAsmNE_CGIBAsmNH_CGIBAsmNHE_CGIBAsmNL_CGIBAsmNLE_CGIBAsmNLH_CGRB_CGRBAsm_CGRBAsmE_CGRBAsmH_CGRBAsmHE_CGRBAsmL_CGRBAsmLE_CGRBAsmLH_CGRBAsmNE_CGRBAsmNH_CGRBAsmNHE_CGRBAsmNL_CGRBAsmNLE_CGRBAsmNLH_CIB_CIBAsm_CIBAsmE_CIBAsmH_CIBAsmHE_CIBAsmL_CIBAsmLE_CIBAsmLH_CIBAsmNE_CIBAsmNH_CIBAsmNHE_CIBAsmNL_CIBAsmNLE_CIBAsmNLH_CLGIB_CLGIBAsm_CLGIBAsmE_CLGIBAsmH_CLGIBAsmHE_CLGIBAsmL_CLGIBAsmLE_CLGIBAsmLH_CLGIBAsmNE_CLGIBAsmNH_CLGIBAsmNHE_CLGIBAsmNL_CLGIBAsmNLE_CLGIBAsmNLH_CLGRB_CLGRBAsm_CLGRBAsmE_CLGRBAsmH_CLGRBAsmHE_CLGRBAsmL_CLGRBAsmLE_CLGRBAsmLH_CLGRBAsmNE_CLGRBAsmNH_CLGRBAsmNHE_CLGRBAsmNL_CLGRBAsmNLE_CLGRBAsmNLH_CLIB_CLIBAsm_CLIBAsmE_CLIBAsmH_CLIBAsmHE_CLIBAsmL_CLIBAsmLE_CLIBAsmLH_CLIBAsmNE_CLIBAsmNH_CLIBAsmNHE_CLIBAsmNL_CLIBAsmNLE_CLIBAsmNLH_CLRB_CLRBAsm_CLRBAsmE_CLRBAsmH_CLRBAsmHE_CLRBAsmL_CLRBAsmLE_CLRBAsmLH_CLRBAsmNE_CLRBAsmNH_CLRBAsmNHE_CLRBAsmNL_CLRBAsmNLE_CLRBAsmNLH_CRB_CRBAsm_CRBAsmE_CRBAsmH_CRBAsmHE_CRBAsmL_CRBAsmLE_CRBAsmLH_CRBAsmNE_CRBAsmNH_CRBAsmNHE_CRBAsmNL_CRBAsmNLE_CRBAsmNLH = 12, |
2865 | | CondTrap_Trap = 13, |
2866 | | CGIT_CGITAsm_CGITAsmE_CGITAsmH_CGITAsmHE_CGITAsmL_CGITAsmLE_CGITAsmLH_CGITAsmNE_CGITAsmNH_CGITAsmNHE_CGITAsmNL_CGITAsmNLE_CGITAsmNLH_CGRT_CGRTAsm_CGRTAsmE_CGRTAsmH_CGRTAsmHE_CGRTAsmL_CGRTAsmLE_CGRTAsmLH_CGRTAsmNE_CGRTAsmNH_CGRTAsmNHE_CGRTAsmNL_CGRTAsmNLE_CGRTAsmNLH_CIT_CITAsm_CITAsmE_CITAsmH_CITAsmHE_CITAsmL_CITAsmLE_CITAsmLH_CITAsmNE_CITAsmNH_CITAsmNHE_CITAsmNL_CITAsmNLE_CITAsmNLH_CRT_CRTAsm_CRTAsmE_CRTAsmH_CRTAsmHE_CRTAsmL_CRTAsmLE_CRTAsmLH_CRTAsmNE_CRTAsmNH_CRTAsmNHE_CRTAsmNL_CRTAsmNLE_CRTAsmNLH = 14, |
2867 | | CLGRT_CLGRTAsm_CLGRTAsmE_CLGRTAsmH_CLGRTAsmHE_CLGRTAsmL_CLGRTAsmLE_CLGRTAsmLH_CLGRTAsmNE_CLGRTAsmNH_CLGRTAsmNHE_CLGRTAsmNL_CLGRTAsmNLE_CLGRTAsmNLH_CLRT_CLRTAsm_CLRTAsmE_CLRTAsmH_CLRTAsmHE_CLRTAsmL_CLRTAsmLE_CLRTAsmLH_CLRTAsmNE_CLRTAsmNH_CLRTAsmNHE_CLRTAsmNL_CLRTAsmNLE_CLRTAsmNLH = 15, |
2868 | | CLFIT_CLFITAsm_CLFITAsmE_CLFITAsmH_CLFITAsmHE_CLFITAsmL_CLFITAsmLE_CLFITAsmLH_CLFITAsmNE_CLFITAsmNH_CLFITAsmNHE_CLFITAsmNL_CLFITAsmNLE_CLFITAsmNLH_CLGIT_CLGITAsm_CLGITAsmE_CLGITAsmH_CLGITAsmHE_CLGITAsmL_CLGITAsmLE_CLGITAsmLH_CLGITAsmNE_CLGITAsmNH_CLGITAsmNHE_CLGITAsmNL_CLGITAsmNLE_CLGITAsmNLH = 16, |
2869 | | CLGT_CLGTAsm_CLGTAsmE_CLGTAsmH_CLGTAsmHE_CLGTAsmL_CLGTAsmLE_CLGTAsmLH_CLGTAsmNE_CLGTAsmNH_CLGTAsmNHE_CLGTAsmNL_CLGTAsmNLE_CLGTAsmNLH_CLT_CLTAsm_CLTAsmE_CLTAsmH_CLTAsmHE_CLTAsmL_CLTAsmLE_CLTAsmLH_CLTAsmNE_CLTAsmNH_CLTAsmNHE_CLTAsmNL_CLTAsmNLE_CLTAsmNLH = 17, |
2870 | | BRAS = 18, |
2871 | | CallBRASL_BRASL = 19, |
2872 | | CallBASR_BAS_BASR = 20, |
2873 | | TLS_GDCALL_TLS_LDCALL = 21, |
2874 | | Return = 22, |
2875 | | CondReturn = 23, |
2876 | | MVGHI_MVHHI_MVHI = 24, |
2877 | | MVI_MVIY = 25, |
2878 | | MVC = 26, |
2879 | | MVCL_MVCLE_MVCLU = 27, |
2880 | | COPY_TO_REGCLASS_COPY = 28, |
2881 | | EXTRACT_SUBREG = 29, |
2882 | | INSERT_SUBREG = 30, |
2883 | | REG_SEQUENCE = 31, |
2884 | | LMux_L_LFH_LRL_LY = 32, |
2885 | | LCBB = 33, |
2886 | | LG_LGRL = 34, |
2887 | | L128 = 35, |
2888 | | LLIHF_LLIHH_LLIHL = 36, |
2889 | | LLILF_LLILH_LLILL = 37, |
2890 | | LGFI_LGHI = 38, |
2891 | | LHIMux_LHI = 39, |
2892 | | LRMux_LR = 40, |
2893 | | LZRF_LZRG = 41, |
2894 | | LAT_LFHAT_LGAT = 42, |
2895 | | LT_LTG = 43, |
2896 | | LTGR_LTR = 44, |
2897 | | STG_STGRL = 45, |
2898 | | ST128 = 46, |
2899 | | STMux_ST_STFH_STRL_STY = 47, |
2900 | | MVST = 48, |
2901 | | LOCRMux = 49, |
2902 | | LOCFHR_LOCFHRAsm_LOCFHRAsmE_LOCFHRAsmH_LOCFHRAsmHE_LOCFHRAsmL_LOCFHRAsmLE_LOCFHRAsmLH_LOCFHRAsmM_LOCFHRAsmNE_LOCFHRAsmNH_LOCFHRAsmNHE_LOCFHRAsmNL_LOCFHRAsmNLE_LOCFHRAsmNLH_LOCFHRAsmNM_LOCFHRAsmNO_LOCFHRAsmNP_LOCFHRAsmNZ_LOCFHRAsmO_LOCFHRAsmP_LOCFHRAsmZ_LOCGR_LOCGRAsm_LOCGRAsmE_LOCGRAsmH_LOCGRAsmHE_LOCGRAsmL_LOCGRAsmLE_LOCGRAsmLH_LOCGRAsmM_LOCGRAsmNE_LOCGRAsmNH_LOCGRAsmNHE_LOCGRAsmNL_LOCGRAsmNLE_LOCGRAsmNLH_LOCGRAsmNM_LOCGRAsmNO_LOCGRAsmNP_LOCGRAsmNZ_LOCGRAsmO_LOCGRAsmP_LOCGRAsmZ_LOCR_LOCRAsm_LOCRAsmE_LOCRAsmH_LOCRAsmHE_LOCRAsmL_LOCRAsmLE_LOCRAsmLH_LOCRAsmM_LOCRAsmNE_LOCRAsmNH_LOCRAsmNHE_LOCRAsmNL_LOCRAsmNLE_LOCRAsmNLH_LOCRAsmNM_LOCRAsmNO_LOCRAsmNP_LOCRAsmNZ_LOCRAsmO_LOCRAsmP_LOCRAsmZ = 50, |
2903 | | LOCHIMux_LOCGHI_LOCGHIAsm_LOCGHIAsmE_LOCGHIAsmH_LOCGHIAsmHE_LOCGHIAsmL_LOCGHIAsmLE_LOCGHIAsmLH_LOCGHIAsmM_LOCGHIAsmNE_LOCGHIAsmNH_LOCGHIAsmNHE_LOCGHIAsmNL_LOCGHIAsmNLE_LOCGHIAsmNLH_LOCGHIAsmNM_LOCGHIAsmNO_LOCGHIAsmNP_LOCGHIAsmNZ_LOCGHIAsmO_LOCGHIAsmP_LOCGHIAsmZ_LOCHHI_LOCHHIAsm_LOCHHIAsmE_LOCHHIAsmH_LOCHHIAsmHE_LOCHHIAsmL_LOCHHIAsmLE_LOCHHIAsmLH_LOCHHIAsmM_LOCHHIAsmNE_LOCHHIAsmNH_LOCHHIAsmNHE_LOCHHIAsmNL_LOCHHIAsmNLE_LOCHHIAsmNLH_LOCHHIAsmNM_LOCHHIAsmNO_LOCHHIAsmNP_LOCHHIAsmNZ_LOCHHIAsmO_LOCHHIAsmP_LOCHHIAsmZ_LOCHI_LOCHIAsm_LOCHIAsmE_LOCHIAsmH_LOCHIAsmHE_LOCHIAsmL_LOCHIAsmLE_LOCHIAsmLH_LOCHIAsmM_LOCHIAsmNE_LOCHIAsmNH_LOCHIAsmNHE_LOCHIAsmNL_LOCHIAsmNLE_LOCHIAsmNLH_LOCHIAsmNM_LOCHIAsmNO_LOCHIAsmNP_LOCHIAsmNZ_LOCHIAsmO_LOCHIAsmP_LOCHIAsmZ = 51, |
2904 | | LOCMux_LOC_LOCAsm_LOCAsmE_LOCAsmH_LOCAsmHE_LOCAsmL_LOCAsmLE_LOCAsmLH_LOCAsmM_LOCAsmNE_LOCAsmNH_LOCAsmNHE_LOCAsmNL_LOCAsmNLE_LOCAsmNLH_LOCAsmNM_LOCAsmNO_LOCAsmNP_LOCAsmNZ_LOCAsmO_LOCAsmP_LOCAsmZ_LOCFH_LOCFHAsm_LOCFHAsmE_LOCFHAsmH_LOCFHAsmHE_LOCFHAsmL_LOCFHAsmLE_LOCFHAsmLH_LOCFHAsmM_LOCFHAsmNE_LOCFHAsmNH_LOCFHAsmNHE_LOCFHAsmNL_LOCFHAsmNLE_LOCFHAsmNLH_LOCFHAsmNM_LOCFHAsmNO_LOCFHAsmNP_LOCFHAsmNZ_LOCFHAsmO_LOCFHAsmP_LOCFHAsmZ_LOCG_LOCGAsm_LOCGAsmE_LOCGAsmH_LOCGAsmHE_LOCGAsmL_LOCGAsmLE_LOCGAsmLH_LOCGAsmM_LOCGAsmNE_LOCGAsmNH_LOCGAsmNHE_LOCGAsmNL_LOCGAsmNLE_LOCGAsmNLH_LOCGAsmNM_LOCGAsmNO_LOCGAsmNP_LOCGAsmNZ_LOCGAsmO_LOCGAsmP_LOCGAsmZ = 52, |
2905 | | STOCMux_STOC_STOCAsm_STOCAsmE_STOCAsmH_STOCAsmHE_STOCAsmL_STOCAsmLE_STOCAsmLH_STOCAsmM_STOCAsmNE_STOCAsmNH_STOCAsmNHE_STOCAsmNL_STOCAsmNLE_STOCAsmNLH_STOCAsmNM_STOCAsmNO_STOCAsmNP_STOCAsmNZ_STOCAsmO_STOCAsmP_STOCAsmZ_STOCFH_STOCFHAsm_STOCFHAsmE_STOCFHAsmH_STOCFHAsmHE_STOCFHAsmL_STOCFHAsmLE_STOCFHAsmLH_STOCFHAsmM_STOCFHAsmNE_STOCFHAsmNH_STOCFHAsmNHE_STOCFHAsmNL_STOCFHAsmNLE_STOCFHAsmNLH_STOCFHAsmNM_STOCFHAsmNO_STOCFHAsmNP_STOCFHAsmNZ_STOCFHAsmO_STOCFHAsmP_STOCFHAsmZ_STOCG_STOCGAsm_STOCGAsmE_STOCGAsmH_STOCGAsmHE_STOCGAsmL_STOCGAsmLE_STOCGAsmLH_STOCGAsmM_STOCGAsmNE_STOCGAsmNH_STOCGAsmNHE_STOCGAsmNL_STOCGAsmNLE_STOCGAsmNLH_STOCGAsmNM_STOCGAsmNO_STOCGAsmNP_STOCGAsmNZ_STOCGAsmO_STOCGAsmP_STOCGAsmZ = 53, |
2906 | | LBR_LGR_LHR = 54, |
2907 | | LGBR_LGFR_LGHR = 55, |
2908 | | LTGF = 56, |
2909 | | LTGFR = 57, |
2910 | | LBMux_LB_LBH = 58, |
2911 | | LH_LHY = 59, |
2912 | | LHMux_LHH_LHRL = 60, |
2913 | | LGB_LGF_LGH = 61, |
2914 | | LGFRL_LGHRL = 62, |
2915 | | LLCRMux_LLCR = 63, |
2916 | | LLHRMux_LLHR = 64, |
2917 | | LLGCR_LLGFR_LLGHR_LLGTR = 65, |
2918 | | LLCMux_LLC = 66, |
2919 | | LLHMux_LLH = 67, |
2920 | | LLCH_LLHH = 68, |
2921 | | LLHRL = 69, |
2922 | | LLGC_LLGF_LLGFRL_LLGH_LLGHRL_LLGT = 70, |
2923 | | LLZRGF = 71, |
2924 | | LLGFAT_LLGTAT = 72, |
2925 | | STCMux_STC_STCH_STCY = 73, |
2926 | | STHMux_STH_STHH_STHRL_STHY = 74, |
2927 | | STCM_STCMH_STCMY = 75, |
2928 | | LM_LMG_LMH_LMY = 76, |
2929 | | LMD = 77, |
2930 | | STM_STMG_STMH_STMY = 78, |
2931 | | LRVGR_LRVR = 79, |
2932 | | LRV_LRVG_LRVH = 80, |
2933 | | STRV_STRVG_STRVH = 81, |
2934 | | MVCIN = 82, |
2935 | | LA_LARL_LAY = 83, |
2936 | | GOT = 84, |
2937 | | LPGR_LPR = 85, |
2938 | | LNGFR_LPGFR = 86, |
2939 | | LNGR_LNR = 87, |
2940 | | LCGR_LCR = 88, |
2941 | | LCGFR = 89, |
2942 | | IC_ICY = 90, |
2943 | | IC32_IC32Y = 91, |
2944 | | ICM_ICMH_ICMY = 92, |
2945 | | IIFMux_IIHMux_IILMux = 93, |
2946 | | IIHF64_IIHF = 94, |
2947 | | IIHH64_IIHH = 95, |
2948 | | IIHL64_IIHL = 96, |
2949 | | IILF64_IILF = 97, |
2950 | | IILH64_IILH = 98, |
2951 | | IILL64_IILL = 99, |
2952 | | A_AY = 100, |
2953 | | AH_AHY = 101, |
2954 | | AIH = 102, |
2955 | | AFIMux_AFI = 103, |
2956 | | AG = 104, |
2957 | | AGFI = 105, |
2958 | | AGHI_AGHIK = 106, |
2959 | | AGR_AGRK = 107, |
2960 | | AHI_AHIK = 108, |
2961 | | AHIMux_AHIMuxK = 109, |
2962 | | AL_ALY = 110, |
2963 | | ALFI_ALHSIK = 111, |
2964 | | ALG_ALGF = 112, |
2965 | | ALGHSIK = 113, |
2966 | | ALGFI_ALGFR = 114, |
2967 | | ALGR_ALGRK = 115, |
2968 | | ALR_ALRK = 116, |
2969 | | AR_ARK = 117, |
2970 | | AHHHR_ALHHHR = 118, |
2971 | | AHHLR_ALHHLR = 119, |
2972 | | ALSIH_ALSIHN = 120, |
2973 | | AGSI_ALGSI_ALSI_ASI = 121, |
2974 | | ALC_ALCG = 122, |
2975 | | ALCGR_ALCR = 123, |
2976 | | AGF_AGH = 124, |
2977 | | AGFR = 125, |
2978 | | S_SG_SY = 126, |
2979 | | SH_SHY = 127, |
2980 | | SGR_SGRK = 128, |
2981 | | SLFI = 129, |
2982 | | SL_SLG_SLGF_SLY = 130, |
2983 | | SLGFI_SLGFR = 131, |
2984 | | SLGR_SLGRK = 132, |
2985 | | SLR_SLRK = 133, |
2986 | | SR_SRK = 134, |
2987 | | SHHHR_SLHHHR = 135, |
2988 | | SHHLR_SLHHLR = 136, |
2989 | | SLB_SLBG = 137, |
2990 | | SLBGR_SLBR = 138, |
2991 | | SGF_SGH = 139, |
2992 | | SGFR = 140, |
2993 | | N_NG_NY = 141, |
2994 | | NGR_NGRK = 142, |
2995 | | NIFMux_NIHMux_NILMux = 143, |
2996 | | NI_NIY = 144, |
2997 | | NIHF64_NIHF = 145, |
2998 | | NIHH64_NIHH = 146, |
2999 | | NIHL64_NIHL = 147, |
3000 | | NILF64_NILF = 148, |
3001 | | NILH64_NILH = 149, |
3002 | | NILL64_NILL = 150, |
3003 | | NR_NRK = 151, |
3004 | | NC = 152, |
3005 | | O_OG_OY = 153, |
3006 | | OGR_OGRK = 154, |
3007 | | OI_OIY = 155, |
3008 | | OIFMux_OIHMux_OILMux = 156, |
3009 | | OIHF64_OIHF = 157, |
3010 | | OIHH64_OIHH = 158, |
3011 | | OIHL64_OIHL = 159, |
3012 | | OILF64_OILF = 160, |
3013 | | OILH64_OILH = 161, |
3014 | | OILL64_OILL = 162, |
3015 | | OR_ORK = 163, |
3016 | | OC = 164, |
3017 | | X_XG_XY = 165, |
3018 | | XI_XIY = 166, |
3019 | | XIFMux = 167, |
3020 | | XGR_XGRK = 168, |
3021 | | XIHF64_XIHF = 169, |
3022 | | XILF64_XILF = 170, |
3023 | | XR_XRK = 171, |
3024 | | XC = 172, |
3025 | | MS_MSGF_MSY = 173, |
3026 | | MSFI_MSR = 174, |
3027 | | MSG = 175, |
3028 | | MSGR = 176, |
3029 | | MSGFI_MSGFR = 177, |
3030 | | MLG = 178, |
3031 | | MLGR = 179, |
3032 | | MGHI = 180, |
3033 | | MHI = 181, |
3034 | | MH_MHY = 182, |
3035 | | MLR_MR = 183, |
3036 | | M_MFY_ML = 184, |
3037 | | MGH = 185, |
3038 | | MG = 186, |
3039 | | MGRK = 187, |
3040 | | MSC = 188, |
3041 | | MSGC = 189, |
3042 | | MSRKC = 190, |
3043 | | MSGRKC = 191, |
3044 | | DR = 192, |
3045 | | D = 193, |
3046 | | DSGFR_DSGR = 194, |
3047 | | DSG_DSGF = 195, |
3048 | | DLR = 196, |
3049 | | DLGR = 197, |
3050 | | DL_DLG = 198, |
3051 | | SLL_SLLG_SLLK = 199, |
3052 | | SRL_SRLG_SRLK = 200, |
3053 | | SRA_SRAG_SRAK = 201, |
3054 | | SLA_SLAG_SLAK = 202, |
3055 | | SLDA_SLDL_SRDA_SRDL = 203, |
3056 | | RLL_RLLG = 204, |
3057 | | RISBG_RISBG32_RISBGN = 205, |
3058 | | RISBHH_RISBHL_RISBHG = 206, |
3059 | | RISBLH_RISBLL_RISBLG = 207, |
3060 | | RISBMux = 208, |
3061 | | RNSBG_ROSBG_RXSBG = 209, |
3062 | | CMux_C_CG_CY = 210, |
3063 | | CRL = 211, |
3064 | | CFIMux_CHIMux_CFI_CHI = 212, |
3065 | | CGFI_CGHI = 213, |
3066 | | CGHSI_CGRL = 214, |
3067 | | CGR_CR = 215, |
3068 | | CIH = 216, |
3069 | | CHF = 217, |
3070 | | CHSI = 218, |
3071 | | CLMux_CL_CLY = 219, |
3072 | | CLFHSI = 220, |
3073 | | CLFIMux_CLFI = 221, |
3074 | | CLG = 222, |
3075 | | CLGHRL_CLGHSI = 223, |
3076 | | CLGF = 224, |
3077 | | CLGFRL = 225, |
3078 | | CLGFI_CLGFR = 226, |
3079 | | CLGR = 227, |
3080 | | CLGRL = 228, |
3081 | | CLHF = 229, |
3082 | | CLHHSI_CLHRL = 230, |
3083 | | CLIH = 231, |
3084 | | CLI_CLIY = 232, |
3085 | | CLR = 233, |
3086 | | CLRL = 234, |
3087 | | CHHR_CLHHR = 235, |
3088 | | CHLR_CLHLR = 236, |
3089 | | CH_CHY = 237, |
3090 | | CHRL = 238, |
3091 | | CGH = 239, |
3092 | | CGHRL = 240, |
3093 | | CHHSI = 241, |
3094 | | CGF = 242, |
3095 | | CGFRL = 243, |
3096 | | CGFR = 244, |
3097 | | CLC = 245, |
3098 | | CLCL_CLCLE_CLCLU = 246, |
3099 | | CLST = 247, |
3100 | | TM_TMY = 248, |
3101 | | TMHMux_TMLMux = 249, |
3102 | | TMHH64_TMHH = 250, |
3103 | | TMHL64_TMHL = 251, |
3104 | | TMLH64_TMLH = 252, |
3105 | | TMLL64_TMLL = 253, |
3106 | | CLM_CLMH_CLMY = 254, |
3107 | | PFD_PFDRL = 255, |
3108 | | BPP = 256, |
3109 | | BPRP = 257, |
3110 | | NIAI = 258, |
3111 | | Serialize = 259, |
3112 | | LAA_LAAG = 260, |
3113 | | LAAL_LAALG = 261, |
3114 | | LAN_LANG = 262, |
3115 | | LAO_LAOG = 263, |
3116 | | LAX_LAXG = 264, |
3117 | | TS = 265, |
3118 | | CS_CSG_CSY = 266, |
3119 | | CDS_CDSY = 267, |
3120 | | CDSG = 268, |
3121 | | CSST = 269, |
3122 | | PLO = 270, |
3123 | | LPQ = 271, |
3124 | | STPQ = 272, |
3125 | | LPD_LPDG = 273, |
3126 | | TR = 274, |
3127 | | TRT = 275, |
3128 | | TRTR = 276, |
3129 | | TRE = 277, |
3130 | | TRTE_TRTEOpt_TRTRE_TRTREOpt = 278, |
3131 | | TROO_TROOOpt_TROT_TROTOpt_TRTO_TRTOOpt_TRTT_TRTTOpt = 279, |
3132 | | CU12_CU12Opt_CU14_CU14Opt_CU21_CU21Opt_CU24_CU24Opt_CU41_CU42 = 280, |
3133 | | CUTFU_CUTFUOpt_CUUTF_CUUTFOpt = 281, |
3134 | | KM_KMA_KMC_KMCTR_KMF_KMO = 282, |
3135 | | KIMD_KLMD_KMAC = 283, |
3136 | | PCC_PPNO_PRNO = 284, |
3137 | | LGG = 285, |
3138 | | LLGFSG = 286, |
3139 | | LGSC_STGSC = 287, |
3140 | | CVBG = 288, |
3141 | | CVB_CVBY = 289, |
3142 | | CVDG = 290, |
3143 | | CVD_CVDY = 291, |
3144 | | MVN_MVO_MVZ = 292, |
3145 | | PACK_PKA_PKU = 293, |
3146 | | UNPKA_UNPKU = 294, |
3147 | | UNPK = 295, |
3148 | | AP_SP_ZAP = 296, |
3149 | | DP_MP = 297, |
3150 | | SRP = 298, |
3151 | | CP = 299, |
3152 | | TP = 300, |
3153 | | ED_EDMK = 301, |
3154 | | CPYA_EAR_SAR = 302, |
3155 | | LAE_LAEY = 303, |
3156 | | LAM_LAMY = 304, |
3157 | | STAM_STAMY = 305, |
3158 | | IPM = 306, |
3159 | | SPM = 307, |
3160 | | BAL_BALR = 308, |
3161 | | TAM = 309, |
3162 | | SAM24_SAM31_SAM64 = 310, |
3163 | | BSM = 311, |
3164 | | BASSM = 312, |
3165 | | TBEGIN_TBEGINC = 313, |
3166 | | TEND = 314, |
3167 | | TABORT = 315, |
3168 | | ETND = 316, |
3169 | | NTSTG = 317, |
3170 | | PPA = 318, |
3171 | | FLOGR = 319, |
3172 | | POPCNT = 320, |
3173 | | SRST_SRSTU = 321, |
3174 | | CUSE = 322, |
3175 | | CFC = 323, |
3176 | | UPT = 324, |
3177 | | CKSM = 325, |
3178 | | CMPSC = 326, |
3179 | | EX_EXRL = 327, |
3180 | | InsnE_InsnRI_InsnRIE_InsnRIL_InsnRILU_InsnRIS_InsnRR_InsnRRE_InsnRRF_InsnRRS_InsnRS_InsnRSE_InsnRSI_InsnRSY_InsnRX_InsnRXE_InsnRXF_InsnRXY_InsnS_InsnSI_InsnSIL_InsnSIY_InsnSS_InsnSSE_InsnSSF = 328, |
3181 | | LZDR_LZER = 329, |
3182 | | LZXR = 330, |
3183 | | LER = 331, |
3184 | | LDGR_LDR_LDR32 = 332, |
3185 | | LGDR = 333, |
3186 | | LXR = 334, |
3187 | | LTDBR_LTEBR = 335, |
3188 | | LTDBRCompare_LTEBRCompare = 336, |
3189 | | LTXBR_LTXBRCompare = 337, |
3190 | | CPSDRdd_CPSDRds_CPSDRsd_CPSDRss = 338, |
3191 | | LE_LEY = 339, |
3192 | | LD_LDE32_LDY = 340, |
3193 | | LX = 341, |
3194 | | STD_STDY_STE_STEY = 342, |
3195 | | STX = 343, |
3196 | | LEDBR_LEDBRA = 344, |
3197 | | LDXBR_LDXBRA_LEXBR_LEXBRA = 345, |
3198 | | LDEB = 346, |
3199 | | LDEBR = 347, |
3200 | | LXDB_LXEB = 348, |
3201 | | LXDBR_LXEBR = 349, |
3202 | | CDFBR_CDFBRA_CDGBR_CDGBRA_CEFBR_CEFBRA_CEGBR_CEGBRA = 350, |
3203 | | CXFBR_CXFBRA_CXGBR_CXGBRA = 351, |
3204 | | CDLFBR_CDLGBR_CELFBR_CELGBR = 352, |
3205 | | CXLFBR_CXLGBR = 353, |
3206 | | CFDBR_CFDBRA_CFEBR_CFEBRA_CGDBR_CGDBRA_CGEBR_CGEBRA = 354, |
3207 | | CFXBR_CFXBRA_CGXBR_CGXBRA = 355, |
3208 | | CLFEBR = 356, |
3209 | | CLFDBR = 357, |
3210 | | CLGDBR_CLGEBR = 358, |
3211 | | CLFXBR_CLGXBR = 359, |
3212 | | LCDBR_LCEBR_LNDBR_LNEBR_LPDBR_LPEBR = 360, |
3213 | | LCDFR_LCDFR_32_LNDFR_LNDFR_32_LPDFR_LPDFR_32 = 361, |
3214 | | LCXBR_LNXBR_LPXBR = 362, |
3215 | | SQDB_SQEB = 363, |
3216 | | SQDBR_SQEBR = 364, |
3217 | | SQXBR = 365, |
3218 | | FIDBR_FIDBRA_FIEBR_FIEBRA = 366, |
3219 | | FIXBR_FIXBRA = 367, |
3220 | | ADB_AEB = 368, |
3221 | | ADBR_AEBR = 369, |
3222 | | AXBR = 370, |
3223 | | SDB_SEB = 371, |
3224 | | SDBR_SEBR = 372, |
3225 | | SXBR = 373, |
3226 | | MDB_MDEB_MEEB = 374, |
3227 | | MDBR_MDEBR_MEEBR = 375, |
3228 | | MXDB = 376, |
3229 | | MXDBR = 377, |
3230 | | MXBR = 378, |
3231 | | MAEB_MSEB = 379, |
3232 | | MAEBR_MSEBR = 380, |
3233 | | MADB_MSDB = 381, |
3234 | | MADBR_MSDBR = 382, |
3235 | | DDB_DEB = 383, |
3236 | | DDBR_DEBR = 384, |
3237 | | DXBR = 385, |
3238 | | DIDBR_DIEBR = 386, |
3239 | | CDB_CEB_KDB_KEB = 387, |
3240 | | CDBR_CEBR_KDBR_KEBR = 388, |
3241 | | CXBR_KXBR = 389, |
3242 | | TCDB_TCEB = 390, |
3243 | | TCXB = 391, |
3244 | | EFPC = 392, |
3245 | | STFPC = 393, |
3246 | | SFPC = 394, |
3247 | | LFPC = 395, |
3248 | | SFASR = 396, |
3249 | | LFAS = 397, |
3250 | | SRNM_SRNMB_SRNMT = 398, |
3251 | | LTDR_LTER = 399, |
3252 | | LTXR = 400, |
3253 | | LEDR_LRER = 401, |
3254 | | LEXR = 402, |
3255 | | LDXR_LRDR = 403, |
3256 | | LDE = 404, |
3257 | | LDER = 405, |
3258 | | LXD_LXE = 406, |
3259 | | LXDR_LXER = 407, |
3260 | | CDFR_CDGR_CEFR_CEGR = 408, |
3261 | | CXFR_CXGR = 409, |
3262 | | CFDR_CFER_CGDR_CGER = 410, |
3263 | | CFXR_CGXR = 411, |
3264 | | THDER_THDR = 412, |
3265 | | TBDR_TBEDR = 413, |
3266 | | LCDR_LCER_LNDR_LNER_LPDR_LPER = 414, |
3267 | | LCXR_LNXR_LPXR = 415, |
3268 | | HDR_HER = 416, |
3269 | | SQD_SQE = 417, |
3270 | | SQDR_SQER = 418, |
3271 | | SQXR = 419, |
3272 | | FIDR_FIER = 420, |
3273 | | FIXR = 421, |
3274 | | AD_AE_AU_AW = 422, |
3275 | | ADR_AER_AUR_AWR = 423, |
3276 | | AXR = 424, |
3277 | | SD_SE_SU_SW = 425, |
3278 | | SDR_SER_SUR_SWR = 426, |
3279 | | SXR = 427, |
3280 | | MD_MDE_ME_MEE = 428, |
3281 | | MDER_MDR_MEER_MER = 429, |
3282 | | MXD = 430, |
3283 | | MXDR = 431, |
3284 | | MXR = 432, |
3285 | | MY = 433, |
3286 | | MYH_MYL = 434, |
3287 | | MYR = 435, |
3288 | | MYHR_MYLR = 436, |
3289 | | MAD_MAE_MSD_MSE = 437, |
3290 | | MADR_MAER_MSDR_MSER = 438, |
3291 | | MAY = 439, |
3292 | | MAYH_MAYL = 440, |
3293 | | MAYR = 441, |
3294 | | MAYHR_MAYLR = 442, |
3295 | | DD_DE = 443, |
3296 | | DDR_DER = 444, |
3297 | | DXR = 445, |
3298 | | CD_CE = 446, |
3299 | | CDR_CER = 447, |
3300 | | CXR = 448, |
3301 | | LTDTR = 449, |
3302 | | LTXTR = 450, |
3303 | | LEDTR = 451, |
3304 | | LDXTR = 452, |
3305 | | LDETR = 453, |
3306 | | LXDTR = 454, |
3307 | | CDFTR_CDGTR_CDGTRA = 455, |
3308 | | CXFTR_CXGTR_CXGTRA = 456, |
3309 | | CDLFTR_CDLGTR = 457, |
3310 | | CXLFTR_CXLGTR = 458, |
3311 | | CFDTR_CGDTR_CGDTRA = 459, |
3312 | | CFXTR_CGXTR_CGXTRA = 460, |
3313 | | CLFDTR_CLGDTR = 461, |
3314 | | CLFXTR_CLGXTR = 462, |
3315 | | CDSTR_CDUTR = 463, |
3316 | | CXSTR_CXUTR = 464, |
3317 | | CSDTR_CUDTR = 465, |
3318 | | CSXTR_CUXTR = 466, |
3319 | | CDZT = 467, |
3320 | | CXZT = 468, |
3321 | | CZDT = 469, |
3322 | | CZXT = 470, |
3323 | | CDPT = 471, |
3324 | | CXPT = 472, |
3325 | | CPDT = 473, |
3326 | | CPXT = 474, |
3327 | | PFPO = 475, |
3328 | | FIDTR = 476, |
3329 | | FIXTR = 477, |
3330 | | EEDTR = 478, |
3331 | | EEXTR = 479, |
3332 | | ESDTR = 480, |
3333 | | ESXTR = 481, |
3334 | | ADTR_ADTRA = 482, |
3335 | | AXTR_AXTRA = 483, |
3336 | | SDTR_SDTRA = 484, |
3337 | | SXTR_SXTRA = 485, |
3338 | | MDTR_MDTRA = 486, |
3339 | | MXTR_MXTRA = 487, |
3340 | | DDTR_DDTRA = 488, |
3341 | | DXTR_DXTRA = 489, |
3342 | | QADTR = 490, |
3343 | | QAXTR = 491, |
3344 | | RRDTR = 492, |
3345 | | RRXTR = 493, |
3346 | | SLDT_SRDT = 494, |
3347 | | SLXT_SRXT = 495, |
3348 | | IEDTR = 496, |
3349 | | IEXTR = 497, |
3350 | | CDTR_KDTR = 498, |
3351 | | CXTR_KXTR = 499, |
3352 | | CEDTR = 500, |
3353 | | CEXTR = 501, |
3354 | | TDCDT_TDCET_TDGDT_TDGET = 502, |
3355 | | TDCXT_TDGXT = 503, |
3356 | | VLR32_VLR64_VLR = 504, |
3357 | | VLGV_VLGVB_VLGVF_VLGVG_VLGVH = 505, |
3358 | | VLVG_VLVGB_VLVGF_VLVGG_VLVGH = 506, |
3359 | | VLVGP32_VLVGP = 507, |
3360 | | VZERO = 508, |
3361 | | VONE = 509, |
3362 | | VGBM = 510, |
3363 | | VGM_VGMB_VGMF_VGMG_VGMH = 511, |
3364 | | VREPI_VREPIB_VREPIF_VREPIG_VREPIH = 512, |
3365 | | VLEIB_VLEIF_VLEIG_VLEIH = 513, |
3366 | | VL_VLBB = 514, |
3367 | | VLL = 515, |
3368 | | VL32_VL64 = 516, |
3369 | | VLLEZ_VLLEZB_VLLEZF_VLLEZG_VLLEZH_VLLEZLF = 517, |
3370 | | VLREP_VLREPB_VLREPF_VLREPG_VLREPH = 518, |
3371 | | VLEB_VLEF_VLEG_VLEH = 519, |
3372 | | VGEF_VGEG = 520, |
3373 | | VLM = 521, |
3374 | | VLRL_VLRLR = 522, |
3375 | | VST32_VST64_VST_VSTL = 523, |
3376 | | VSTEF_VSTEG = 524, |
3377 | | VSTEB_VSTEH = 525, |
3378 | | VSTM = 526, |
3379 | | VSCEF_VSCEG = 527, |
3380 | | VSTRL_VSTRLR = 528, |
3381 | | VMRH_VMRHB_VMRHF_VMRHG_VMRHH = 529, |
3382 | | VMRL_VMRLB_VMRLF_VMRLG_VMRLH = 530, |
3383 | | VPERM = 531, |
3384 | | VPDI = 532, |
3385 | | VBPERM = 533, |
3386 | | VREP_VREPB_VREPF_VREPG_VREPH = 534, |
3387 | | VSEL = 535, |
3388 | | VPK_VPKF_VPKG_VPKH = 536, |
3389 | | VPKS_VPKSF_VPKSG_VPKSH = 537, |
3390 | | VPKSFS_VPKSGS_VPKSHS = 538, |
3391 | | VPKLS_VPKLSF_VPKLSG_VPKLSH = 539, |
3392 | | VPKLSFS_VPKLSGS_VPKLSHS = 540, |
3393 | | VSEG_VSEGB_VSEGF_VSEGH = 541, |
3394 | | VUPH_VUPHB_VUPHF_VUPHH = 542, |
3395 | | VUPL_VUPLB_VUPLF = 543, |
3396 | | VUPLH_VUPLHB_VUPLHF_VUPLHH_VUPLHW = 544, |
3397 | | VUPLL_VUPLLB_VUPLLF_VUPLLH = 545, |
3398 | | VA_VAB_VAC_VACQ_VAF_VAG_VAH_VAQ = 546, |
3399 | | VACC_VACCB_VACCC_VACCCQ_VACCF_VACCG_VACCH_VACCQ = 547, |
3400 | | VAVG_VAVGB_VAVGF_VAVGG_VAVGH = 548, |
3401 | | VAVGL_VAVGLB_VAVGLF_VAVGLG_VAVGLH = 549, |
3402 | | VN_VNC_VNN_VNO_VNX = 550, |
3403 | | VO_VOC = 551, |
3404 | | VCKSM = 552, |
3405 | | VCLZ_VCLZB_VCLZF_VCLZG_VCLZH = 553, |
3406 | | VCTZ_VCTZB_VCTZF_VCTZG_VCTZH = 554, |
3407 | | VX = 555, |
3408 | | VGFM = 556, |
3409 | | VGFMA_VGFMAB_VGFMAF_VGFMAG_VGFMAH = 557, |
3410 | | VGFMB_VGFMF_VGFMG_VGFMH = 558, |
3411 | | VLC_VLCB_VLCF_VLCG_VLCH = 559, |
3412 | | VLP_VLPB_VLPF_VLPG_VLPH = 560, |
3413 | | VMX_VMXB_VMXF_VMXG_VMXH = 561, |
3414 | | VMXL_VMXLB_VMXLF_VMXLG_VMXLH = 562, |
3415 | | VMN_VMNB_VMNF_VMNG_VMNH = 563, |
3416 | | VMNL_VMNLB_VMNLF_VMNLG_VMNLH = 564, |
3417 | | VMAL_VMALB_VMALF = 565, |
3418 | | VMALE_VMALEB_VMALEF_VMALEH = 566, |
3419 | | VMALH_VMALHB_VMALHF_VMALHH_VMALHW = 567, |
3420 | | VMALO_VMALOB_VMALOF_VMALOH = 568, |
3421 | | VMAO_VMAOB_VMAOF_VMAOH = 569, |
3422 | | VMAE_VMAEB_VMAEF_VMAEH = 570, |
3423 | | VMAH_VMAHB_VMAHF_VMAHH = 571, |
3424 | | VME_VMEB_VMEF_VMEH = 572, |
3425 | | VMH_VMHB_VMHF_VMHH = 573, |
3426 | | VML_VMLB_VMLF = 574, |
3427 | | VMLE_VMLEB_VMLEF_VMLEH = 575, |
3428 | | VMLH_VMLHB_VMLHF_VMLHH_VMLHW = 576, |
3429 | | VMLO_VMLOB_VMLOF_VMLOH = 577, |
3430 | | VMO_VMOB_VMOF_VMOH = 578, |
3431 | | VMSL_VMSLG = 579, |
3432 | | VPOPCT_VPOPCTB_VPOPCTF_VPOPCTG_VPOPCTH = 580, |
3433 | | VERLL_VERLLB_VERLLF_VERLLG_VERLLH = 581, |
3434 | | VERLLV_VERLLVB_VERLLVF_VERLLVG_VERLLVH = 582, |
3435 | | VERIM_VERIMB_VERIMF_VERIMG_VERIMH = 583, |
3436 | | VESL_VESLB_VESLF_VESLG_VESLH = 584, |
3437 | | VESLV_VESLVB_VESLVF_VESLVG_VESLVH = 585, |
3438 | | VESRA_VESRAB_VESRAF_VESRAG_VESRAH = 586, |
3439 | | VESRAV_VESRAVB_VESRAVF_VESRAVG_VESRAVH = 587, |
3440 | | VESRL_VESRLB_VESRLF_VESRLG_VESRLH = 588, |
3441 | | VESRLV_VESRLVB_VESRLVF_VESRLVG_VESRLVH = 589, |
3442 | | VSL_VSLDB = 590, |
3443 | | VSLB = 591, |
3444 | | VSRA_VSRL = 592, |
3445 | | VSRAB_VSRLB = 593, |
3446 | | VSB_VSBCBI_VSBCBIQ_VSBI_VSBIQ = 594, |
3447 | | VSCBI_VSCBIB_VSCBIF_VSCBIG_VSCBIH_VSCBIQ = 595, |
3448 | | VS_VSF_VSG_VSH_VSQ = 596, |
3449 | | VSUM_VSUMB_VSUMH = 597, |
3450 | | VSUMG_VSUMGF_VSUMGH = 598, |
3451 | | VSUMQ_VSUMQF_VSUMQG = 599, |
3452 | | VEC_VECB_VECF_VECG_VECH = 600, |
3453 | | VECL_VECLB_VECLF_VECLG_VECLH = 601, |
3454 | | VCEQ_VCEQB_VCEQF_VCEQG_VCEQH = 602, |
3455 | | VCEQBS_VCEQFS_VCEQGS_VCEQHS = 603, |
3456 | | VCH_VCHB_VCHF_VCHG_VCHH = 604, |
3457 | | VCHBS_VCHFS_VCHGS_VCHHS = 605, |
3458 | | VCHL_VCHLB_VCHLF_VCHLG_VCHLH = 606, |
3459 | | VCHLBS_VCHLFS_VCHLGS_VCHLHS = 607, |
3460 | | VTM = 608, |
3461 | | VCDG_VCDLG = 609, |
3462 | | VCDGB_VCDLGB = 610, |
3463 | | WCDGB_WCDLGB = 611, |
3464 | | VCGD_VCLGD = 612, |
3465 | | VCGDB_VCLGDB = 613, |
3466 | | WCGDB_WCLGDB = 614, |
3467 | | VLDE_VLED = 615, |
3468 | | VLDEB_VLEDB = 616, |
3469 | | WLDEB_WLEDB = 617, |
3470 | | VFLL_VFLR = 618, |
3471 | | VFLLS_VFLRD = 619, |
3472 | | WFLLS_WFLRD = 620, |
3473 | | WFLLD = 621, |
3474 | | WFLRX = 622, |
3475 | | VFI = 623, |
3476 | | VFIDB = 624, |
3477 | | WFIDB = 625, |
3478 | | VFISB = 626, |
3479 | | WFISB = 627, |
3480 | | WFIXB = 628, |
3481 | | VFPSO = 629, |
3482 | | VFPSODB_WFPSODB = 630, |
3483 | | VFPSOSB_WFPSOSB = 631, |
3484 | | WFPSOXB = 632, |
3485 | | VFLCDB_VFLNDB_VFLPDB_WFLCDB_WFLNDB_WFLPDB = 633, |
3486 | | VFLCSB_VFLNSB_VFLPSB_WFLCSB_WFLNSB_WFLPSB = 634, |
3487 | | WFLCXB_WFLNXB_WFLPXB = 635, |
3488 | | VFMAX_VFMIN = 636, |
3489 | | VFMAXDB_VFMINDB = 637, |
3490 | | WFMAXDB_WFMINDB = 638, |
3491 | | VFMAXSB_VFMINSB = 639, |
3492 | | WFMAXSB_WFMINSB = 640, |
3493 | | WFMAXXB_WFMINXB = 641, |
3494 | | VFTCI = 642, |
3495 | | VFTCIDB_WFTCIDB = 643, |
3496 | | VFTCISB_WFTCISB = 644, |
3497 | | WFTCIXB = 645, |
3498 | | VFA_VFS = 646, |
3499 | | VFADB_VFSDB = 647, |
3500 | | WFADB_WFSDB = 648, |
3501 | | VFASB_VFSSB = 649, |
3502 | | WFASB_WFSSB = 650, |
3503 | | WFAXB_WFSXB = 651, |
3504 | | VFM = 652, |
3505 | | VFMDB = 653, |
3506 | | WFMDB_WFMSB = 654, |
3507 | | VFMSB = 655, |
3508 | | WFMXB = 656, |
3509 | | VFMA_VFMS_VFNMA_VFNMS = 657, |
3510 | | VFMADB_VFMSDB_VFNMADB_VFNMSDB = 658, |
3511 | | WFMADB_WFMSDB_WFNMADB_WFNMSDB = 659, |
3512 | | VFMASB_VFMSSB_VFNMASB_VFNMSSB = 660, |
3513 | | WFMASB_WFMSSB_WFNMASB_WFNMSSB = 661, |
3514 | | WFMAXB_WFMSXB_WFNMAXB_WFNMSXB = 662, |
3515 | | VFD = 663, |
3516 | | VFDDB_WFDDB = 664, |
3517 | | VFDSB_WFDSB = 665, |
3518 | | WFDXB = 666, |
3519 | | VFSQ = 667, |
3520 | | VFSQDB_WFSQDB = 668, |
3521 | | VFSQSB_WFSQSB = 669, |
3522 | | WFSQXB = 670, |
3523 | | VFCE_VFCH_VFCHE = 671, |
3524 | | VFCEDB_VFCHDB_VFCHEDB_VFKEDB_VFKHDB_VFKHEDB = 672, |
3525 | | WFCEDB_WFCHDB_WFCHEDB = 673, |
3526 | | WFKEDB_WFKHDB_WFKHEDB = 674, |
3527 | | VFCESB_VFCHESB_VFCHSB_VFKESB_VFKHESB_VFKHSB = 675, |
3528 | | WFCESB_WFCHESB_WFCHSB = 676, |
3529 | | WFKESB_WFKHESB_WFKHSB = 677, |
3530 | | WFCEXB_WFCHEXB_WFCHXB = 678, |
3531 | | WFKEXB_WFKHEXB_WFKHXB = 679, |
3532 | | VFCEDBS_VFCHDBS_VFCHEDBS = 680, |
3533 | | VFKEDBS_VFKHDBS_VFKHEDBS = 681, |
3534 | | WFCEDBS_WFCHDBS_WFCHEDBS_WFKEDBS_WFKHDBS_WFKHEDBS = 682, |
3535 | | VFCESBS_VFCHESBS_VFCHSBS_VFKESBS_VFKHESBS_VFKHSBS = 683, |
3536 | | WFCESBS_WFCHESBS_WFCHSBS = 684, |
3537 | | WFKESBS_WFKHESBS_WFKHSBS = 685, |
3538 | | WFCEXBS_WFCHEXBS_WFCHXBS = 686, |
3539 | | WFKEXBS_WFKHEXBS_WFKHXBS = 687, |
3540 | | WFC_WFK = 688, |
3541 | | WFCDB_WFKDB = 689, |
3542 | | WFCSB_WFKSB = 690, |
3543 | | WFCXB_WFKXB = 691, |
3544 | | LEFR = 692, |
3545 | | LFER = 693, |
3546 | | VFAE_VFAEB = 694, |
3547 | | VFAEF_VFAEH = 695, |
3548 | | VFAEBS_VFAEFS_VFAEHS = 696, |
3549 | | VFAEZB_VFAEZF_VFAEZH = 697, |
3550 | | VFAEZBS_VFAEZFS_VFAEZHS = 698, |
3551 | | VFEE_VFEEB_VFEEF_VFEEH_VFEEZB_VFEEZF_VFEEZH = 699, |
3552 | | VFEEBS_VFEEFS_VFEEHS_VFEEZBS_VFEEZFS_VFEEZHS = 700, |
3553 | | VFENE_VFENEB_VFENEF_VFENEH_VFENEZB_VFENEZF_VFENEZH = 701, |
3554 | | VFENEBS_VFENEFS_VFENEHS_VFENEZBS_VFENEZFS_VFENEZHS = 702, |
3555 | | VISTR_VISTRB_VISTRF_VISTRH = 703, |
3556 | | VISTRBS_VISTRFS_VISTRHS = 704, |
3557 | | VSTRC_VSTRCB_VSTRCF_VSTRCH = 705, |
3558 | | VSTRCBS_VSTRCFS_VSTRCHS = 706, |
3559 | | VSTRCZB_VSTRCZF_VSTRCZH = 707, |
3560 | | VSTRCZBS_VSTRCZFS_VSTRCZHS = 708, |
3561 | | VLIP = 709, |
3562 | | VPKZ = 710, |
3563 | | VUPKZ = 711, |
3564 | | VCVB_VCVBG = 712, |
3565 | | VCVD_VCVDG = 713, |
3566 | | VAP_VSP = 714, |
3567 | | VMP_VMSP = 715, |
3568 | | VDP_VRP = 716, |
3569 | | VSDP = 717, |
3570 | | VSRP = 718, |
3571 | | VPSOP = 719, |
3572 | | VCP_VTP = 720, |
3573 | | EPSW = 721, |
3574 | | LPSW_LPSWE = 722, |
3575 | | IPK = 723, |
3576 | | SPKA = 724, |
3577 | | SSM = 725, |
3578 | | STNSM_STOSM = 726, |
3579 | | IAC = 727, |
3580 | | SAC_SACF = 728, |
3581 | | LCTL_LCTLG = 729, |
3582 | | STCTG_STCTL = 730, |
3583 | | EPAIR_EPAR_ESAIR_ESAR = 731, |
3584 | | SSAIR_SSAR = 732, |
3585 | | ESEA = 733, |
3586 | | SPX_STPX = 734, |
3587 | | ISKE = 735, |
3588 | | IVSK = 736, |
3589 | | SSKE_SSKEOpt = 737, |
3590 | | RRBE_RRBM = 738, |
3591 | | IRBM = 739, |
3592 | | PFMF = 740, |
3593 | | TB = 741, |
3594 | | PGIN = 742, |
3595 | | PGOUT = 743, |
3596 | | IPTE_IPTEOpt_IPTEOptOpt = 744, |
3597 | | IDTE_IDTEOpt = 745, |
3598 | | CRDTE_CRDTEOpt = 746, |
3599 | | PTLB = 747, |
3600 | | CSP_CSPG = 748, |
3601 | | LPTEA = 749, |
3602 | | LRA_LRAG_LRAY = 750, |
3603 | | STRAG = 751, |
3604 | | LURA_LURAG = 752, |
3605 | | STURA_STURG = 753, |
3606 | | TPROT = 754, |
3607 | | MVCK_MVCP_MVCS = 755, |
3608 | | MVCDK_MVCSK = 756, |
3609 | | MVCOS = 757, |
3610 | | MVPG = 758, |
3611 | | LASP = 759, |
3612 | | PALB = 760, |
3613 | | PC = 761, |
3614 | | PR = 762, |
3615 | | PT_PTI = 763, |
3616 | | RP = 764, |
3617 | | BSA_BSG = 765, |
3618 | | TAR = 766, |
3619 | | BAKR = 767, |
3620 | | EREG_EREGG = 768, |
3621 | | ESTA_MSTA = 769, |
3622 | | PTFF = 770, |
3623 | | SCK_SCKC_SCKPF = 771, |
3624 | | SPT = 772, |
3625 | | STCK_STCKF = 773, |
3626 | | STCKE = 774, |
3627 | | STCKC = 775, |
3628 | | STPT = 776, |
3629 | | STAP = 777, |
3630 | | STIDP = 778, |
3631 | | STSI = 779, |
3632 | | STFL_STFLE = 780, |
3633 | | ECAG = 781, |
3634 | | ECTG = 782, |
3635 | | PTF = 783, |
3636 | | PCKMO = 784, |
3637 | | SVC = 785, |
3638 | | MC = 786, |
3639 | | DIAG = 787, |
3640 | | TRACE_TRACG = 788, |
3641 | | TRAP2_TRAP4 = 789, |
3642 | | SIGA_SIGP = 790, |
3643 | | SIE = 791, |
3644 | | LPP = 792, |
3645 | | ECPGA = 793, |
3646 | | ECCTR_EPCTR = 794, |
3647 | | LCCTL = 795, |
3648 | | LPCTL_LSCTL = 796, |
3649 | | QCTRI_QSI = 797, |
3650 | | SCCTR_SPCTR = 798, |
3651 | | CSCH_HSCH_RSCH_XSCH = 799, |
3652 | | MSCH_SSCH_STSCH_TSCH = 800, |
3653 | | RCHP = 801, |
3654 | | SCHM = 802, |
3655 | | STCPS_STCRW = 803, |
3656 | | TPI = 804, |
3657 | | SAL = 805, |
3658 | | AGF = 806, |
3659 | | SGF = 807, |
3660 | | KM_KMC_KMCTR_KMF_KMO = 808, |
3661 | | PCC_PPNO = 809, |
3662 | | VLLEZ_VLLEZB_VLLEZF_VLLEZG_VLLEZH = 810, |
3663 | | VN_VNC_VNO = 811, |
3664 | | VO = 812, |
3665 | | VPOPCT = 813, |
3666 | | WFMDB = 814, |
3667 | | VFMA_VFMS = 815, |
3668 | | VFMADB_VFMSDB = 816, |
3669 | | WFMADB_WFMSDB = 817, |
3670 | | VFCEDB_VFCHDB_VFCHEDB = 818, |
3671 | | WFCEDBS_WFCHDBS_WFCHEDBS = 819, |
3672 | | LOCGR_LOCGRAsm_LOCGRAsmE_LOCGRAsmH_LOCGRAsmHE_LOCGRAsmL_LOCGRAsmLE_LOCGRAsmLH_LOCGRAsmM_LOCGRAsmNE_LOCGRAsmNH_LOCGRAsmNHE_LOCGRAsmNL_LOCGRAsmNLE_LOCGRAsmNLH_LOCGRAsmNM_LOCGRAsmNO_LOCGRAsmNP_LOCGRAsmNZ_LOCGRAsmO_LOCGRAsmP_LOCGRAsmZ_LOCR_LOCRAsm_LOCRAsmE_LOCRAsmH_LOCRAsmHE_LOCRAsmL_LOCRAsmLE_LOCRAsmLH_LOCRAsmM_LOCRAsmNE_LOCRAsmNH_LOCRAsmNHE_LOCRAsmNL_LOCRAsmNLE_LOCRAsmNLH_LOCRAsmNM_LOCRAsmNO_LOCRAsmNP_LOCRAsmNZ_LOCRAsmO_LOCRAsmP_LOCRAsmZ = 820, |
3673 | | LOC_LOCAsm_LOCAsmE_LOCAsmH_LOCAsmHE_LOCAsmL_LOCAsmLE_LOCAsmLH_LOCAsmM_LOCAsmNE_LOCAsmNH_LOCAsmNHE_LOCAsmNL_LOCAsmNLE_LOCAsmNLH_LOCAsmNM_LOCAsmNO_LOCAsmNP_LOCAsmNZ_LOCAsmO_LOCAsmP_LOCAsmZ_LOCG_LOCGAsm_LOCGAsmE_LOCGAsmH_LOCGAsmHE_LOCGAsmL_LOCGAsmLE_LOCGAsmLH_LOCGAsmM_LOCGAsmNE_LOCGAsmNH_LOCGAsmNHE_LOCGAsmNL_LOCGAsmNLE_LOCGAsmNLH_LOCGAsmNM_LOCGAsmNO_LOCGAsmNP_LOCGAsmNZ_LOCGAsmO_LOCGAsmP_LOCGAsmZ = 821, |
3674 | | STOC_STOCAsm_STOCAsmE_STOCAsmH_STOCAsmHE_STOCAsmL_STOCAsmLE_STOCAsmLH_STOCAsmM_STOCAsmNE_STOCAsmNH_STOCAsmNHE_STOCAsmNL_STOCAsmNLE_STOCAsmNLH_STOCAsmNM_STOCAsmNO_STOCAsmNP_STOCAsmNZ_STOCAsmO_STOCAsmP_STOCAsmZ_STOCG_STOCGAsm_STOCGAsmE_STOCGAsmH_STOCGAsmHE_STOCGAsmL_STOCGAsmLE_STOCGAsmLH_STOCGAsmM_STOCGAsmNE_STOCGAsmNH_STOCGAsmNHE_STOCGAsmNL_STOCGAsmNLE_STOCGAsmNLH_STOCGAsmNM_STOCGAsmNO_STOCGAsmNP_STOCGAsmNZ_STOCGAsmO_STOCGAsmP_STOCGAsmZ = 822, |
3675 | | ALSI_ASI = 823, |
3676 | | ALGF = 824, |
3677 | | PCC = 825, |
3678 | | CELFBR_CELGBR = 826, |
3679 | | MD_MEE = 827, |
3680 | | MDR_MEER = 828, |
3681 | | CDFTR = 829, |
3682 | | CXFTR = 830, |
3683 | | CXLFTR = 831, |
3684 | | CFDTR = 832, |
3685 | | CFXTR = 833, |
3686 | | TDCDT_TDGDT = 834, |
3687 | | SCK = 835, |
3688 | | SCKPF = 836, |
3689 | | RISBG_RISBG32 = 837, |
3690 | | SCHED_LIST_END = 838 |
3691 | | }; |
3692 | | } // end Sched namespace |
3693 | | } // end SystemZ namespace |
3694 | | } // end llvm namespace |
3695 | | #endif // GET_INSTRINFO_SCHED_ENUM |
3696 | | |
3697 | | #ifdef GET_INSTRINFO_MC_DESC |
3698 | | #undef GET_INSTRINFO_MC_DESC |
3699 | | namespace llvm { |
3700 | | |
3701 | | static const MCPhysReg ImplicitList1[] = { SystemZ::CC, 0 }; |
3702 | | static const MCPhysReg ImplicitList2[] = { SystemZ::R1D, 0 }; |
3703 | | static const MCPhysReg ImplicitList3[] = { SystemZ::R14D, SystemZ::CC, 0 }; |
3704 | | static const MCPhysReg ImplicitList4[] = { SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, 0 }; |
3705 | | static const MCPhysReg ImplicitList5[] = { SystemZ::CC, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, 0 }; |
3706 | | static const MCPhysReg ImplicitList6[] = { SystemZ::R0L, 0 }; |
3707 | | static const MCPhysReg ImplicitList7[] = { SystemZ::R0L, SystemZ::R1D, 0 }; |
3708 | | static const MCPhysReg ImplicitList8[] = { SystemZ::CC, SystemZ::R1D, 0 }; |
3709 | | static const MCPhysReg ImplicitList9[] = { SystemZ::R1L, 0 }; |
3710 | | static const MCPhysReg ImplicitList10[] = { SystemZ::R0L, SystemZ::R1L, 0 }; |
3711 | | static const MCPhysReg ImplicitList11[] = { SystemZ::R0D, SystemZ::R1D, 0 }; |
3712 | | static const MCPhysReg ImplicitList12[] = { SystemZ::R2L, 0 }; |
3713 | | static const MCPhysReg ImplicitList13[] = { SystemZ::R0L, SystemZ::F4Q, 0 }; |
3714 | | static const MCPhysReg ImplicitList14[] = { SystemZ::CC, SystemZ::R1L, SystemZ::F0Q, 0 }; |
3715 | | static const MCPhysReg ImplicitList15[] = { SystemZ::R1L, SystemZ::R2D, 0 }; |
3716 | | static const MCPhysReg ImplicitList16[] = { SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, 0 }; |
3717 | | static const MCPhysReg ImplicitList17[] = { SystemZ::R0D, 0 }; |
3718 | | static const MCPhysReg ImplicitList18[] = { SystemZ::R0D, SystemZ::CC, 0 }; |
3719 | | static const MCPhysReg ImplicitList19[] = { SystemZ::R0L, SystemZ::CC, 0 }; |
3720 | | static const MCPhysReg ImplicitList20[] = { SystemZ::CC, SystemZ::R0L, SystemZ::R1D, 0 }; |
3721 | | static const MCPhysReg ImplicitList21[] = { SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, 0 }; |
3722 | | static const MCPhysReg ImplicitList22[] = { SystemZ::CC, SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R5D, 0 }; |
3723 | | |
3724 | | static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3725 | | static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
3726 | | static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
3727 | | static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
3728 | | static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
3729 | | static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3730 | | static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
3731 | | static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
3732 | | static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; |
3733 | | static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
3734 | | static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
3735 | | static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
3736 | | static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
3737 | | static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3738 | | static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3739 | | static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
3740 | | static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3741 | | static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
3742 | | static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
3743 | | static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
3744 | | static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
3745 | | static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
3746 | | static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
3747 | | static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
3748 | | static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
3749 | | static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3750 | | static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, }; |
3751 | | static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, }; |
3752 | | static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, }; |
3753 | | static const MCOperandInfo OperandInfo31[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3754 | | static const MCOperandInfo OperandInfo32[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3755 | | static const MCOperandInfo OperandInfo33[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3756 | | static const MCOperandInfo OperandInfo34[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3757 | | static const MCOperandInfo OperandInfo35[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3758 | | static const MCOperandInfo OperandInfo36[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3759 | | static const MCOperandInfo OperandInfo37[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3760 | | static const MCOperandInfo OperandInfo38[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3761 | | static const MCOperandInfo OperandInfo39[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3762 | | static const MCOperandInfo OperandInfo40[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3763 | | static const MCOperandInfo OperandInfo41[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3764 | | static const MCOperandInfo OperandInfo42[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3765 | | static const MCOperandInfo OperandInfo43[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3766 | | static const MCOperandInfo OperandInfo44[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3767 | | static const MCOperandInfo OperandInfo45[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3768 | | static const MCOperandInfo OperandInfo46[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3769 | | static const MCOperandInfo OperandInfo47[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3770 | | static const MCOperandInfo OperandInfo48[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3771 | | static const MCOperandInfo OperandInfo49[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3772 | | static const MCOperandInfo OperandInfo50[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3773 | | static const MCOperandInfo OperandInfo51[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3774 | | static const MCOperandInfo OperandInfo52[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3775 | | static const MCOperandInfo OperandInfo53[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3776 | | static const MCOperandInfo OperandInfo54[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3777 | | static const MCOperandInfo OperandInfo55[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3778 | | static const MCOperandInfo OperandInfo56[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3779 | | static const MCOperandInfo OperandInfo57[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3780 | | static const MCOperandInfo OperandInfo58[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3781 | | static const MCOperandInfo OperandInfo59[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3782 | | static const MCOperandInfo OperandInfo60[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3783 | | static const MCOperandInfo OperandInfo61[] = { { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3784 | | static const MCOperandInfo OperandInfo62[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3785 | | static const MCOperandInfo OperandInfo63[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3786 | | static const MCOperandInfo OperandInfo64[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3787 | | static const MCOperandInfo OperandInfo65[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3788 | | static const MCOperandInfo OperandInfo66[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3789 | | static const MCOperandInfo OperandInfo67[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3790 | | static const MCOperandInfo OperandInfo68[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3791 | | static const MCOperandInfo OperandInfo69[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3792 | | static const MCOperandInfo OperandInfo70[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3793 | | static const MCOperandInfo OperandInfo71[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3794 | | static const MCOperandInfo OperandInfo72[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3795 | | static const MCOperandInfo OperandInfo73[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3796 | | static const MCOperandInfo OperandInfo74[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3797 | | static const MCOperandInfo OperandInfo75[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3798 | | static const MCOperandInfo OperandInfo76[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3799 | | static const MCOperandInfo OperandInfo77[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3800 | | static const MCOperandInfo OperandInfo78[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3801 | | static const MCOperandInfo OperandInfo79[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3802 | | static const MCOperandInfo OperandInfo80[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3803 | | static const MCOperandInfo OperandInfo81[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3804 | | static const MCOperandInfo OperandInfo82[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3805 | | static const MCOperandInfo OperandInfo83[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3806 | | static const MCOperandInfo OperandInfo84[] = { { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3807 | | static const MCOperandInfo OperandInfo85[] = { { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3808 | | static const MCOperandInfo OperandInfo86[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3809 | | static const MCOperandInfo OperandInfo87[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3810 | | static const MCOperandInfo OperandInfo88[] = { { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3811 | | static const MCOperandInfo OperandInfo89[] = { { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3812 | | static const MCOperandInfo OperandInfo90[] = { { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3813 | | static const MCOperandInfo OperandInfo91[] = { { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3814 | | static const MCOperandInfo OperandInfo92[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3815 | | static const MCOperandInfo OperandInfo93[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3816 | | static const MCOperandInfo OperandInfo94[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3817 | | static const MCOperandInfo OperandInfo95[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3818 | | static const MCOperandInfo OperandInfo96[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3819 | | static const MCOperandInfo OperandInfo97[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3820 | | static const MCOperandInfo OperandInfo98[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3821 | | static const MCOperandInfo OperandInfo99[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3822 | | static const MCOperandInfo OperandInfo100[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3823 | | static const MCOperandInfo OperandInfo101[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3824 | | static const MCOperandInfo OperandInfo102[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3825 | | static const MCOperandInfo OperandInfo103[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3826 | | static const MCOperandInfo OperandInfo104[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3827 | | static const MCOperandInfo OperandInfo105[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3828 | | static const MCOperandInfo OperandInfo106[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3829 | | static const MCOperandInfo OperandInfo107[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3830 | | static const MCOperandInfo OperandInfo108[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3831 | | static const MCOperandInfo OperandInfo109[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3832 | | static const MCOperandInfo OperandInfo110[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3833 | | static const MCOperandInfo OperandInfo111[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3834 | | static const MCOperandInfo OperandInfo112[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3835 | | static const MCOperandInfo OperandInfo113[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3836 | | static const MCOperandInfo OperandInfo114[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3837 | | static const MCOperandInfo OperandInfo115[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3838 | | static const MCOperandInfo OperandInfo116[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3839 | | static const MCOperandInfo OperandInfo117[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3840 | | static const MCOperandInfo OperandInfo118[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3841 | | static const MCOperandInfo OperandInfo119[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3842 | | static const MCOperandInfo OperandInfo120[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3843 | | static const MCOperandInfo OperandInfo121[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3844 | | static const MCOperandInfo OperandInfo122[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3845 | | static const MCOperandInfo OperandInfo123[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3846 | | static const MCOperandInfo OperandInfo124[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3847 | | static const MCOperandInfo OperandInfo125[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3848 | | static const MCOperandInfo OperandInfo126[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3849 | | static const MCOperandInfo OperandInfo127[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3850 | | static const MCOperandInfo OperandInfo128[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3851 | | static const MCOperandInfo OperandInfo129[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3852 | | static const MCOperandInfo OperandInfo130[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3853 | | static const MCOperandInfo OperandInfo131[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3854 | | static const MCOperandInfo OperandInfo132[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3855 | | static const MCOperandInfo OperandInfo133[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3856 | | static const MCOperandInfo OperandInfo134[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3857 | | static const MCOperandInfo OperandInfo135[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3858 | | static const MCOperandInfo OperandInfo136[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3859 | | static const MCOperandInfo OperandInfo137[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3860 | | static const MCOperandInfo OperandInfo138[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3861 | | static const MCOperandInfo OperandInfo139[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3862 | | static const MCOperandInfo OperandInfo140[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3863 | | static const MCOperandInfo OperandInfo141[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3864 | | static const MCOperandInfo OperandInfo142[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3865 | | static const MCOperandInfo OperandInfo143[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3866 | | static const MCOperandInfo OperandInfo144[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3867 | | static const MCOperandInfo OperandInfo145[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3868 | | static const MCOperandInfo OperandInfo146[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3869 | | static const MCOperandInfo OperandInfo147[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3870 | | static const MCOperandInfo OperandInfo148[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3871 | | static const MCOperandInfo OperandInfo149[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3872 | | static const MCOperandInfo OperandInfo150[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3873 | | static const MCOperandInfo OperandInfo151[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3874 | | static const MCOperandInfo OperandInfo152[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3875 | | static const MCOperandInfo OperandInfo153[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3876 | | static const MCOperandInfo OperandInfo154[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3877 | | static const MCOperandInfo OperandInfo155[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3878 | | static const MCOperandInfo OperandInfo156[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3879 | | static const MCOperandInfo OperandInfo157[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3880 | | static const MCOperandInfo OperandInfo158[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3881 | | static const MCOperandInfo OperandInfo159[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3882 | | static const MCOperandInfo OperandInfo160[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3883 | | static const MCOperandInfo OperandInfo161[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3884 | | static const MCOperandInfo OperandInfo162[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3885 | | static const MCOperandInfo OperandInfo163[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3886 | | static const MCOperandInfo OperandInfo164[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3887 | | static const MCOperandInfo OperandInfo165[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3888 | | static const MCOperandInfo OperandInfo166[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3889 | | static const MCOperandInfo OperandInfo167[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, }; |
3890 | | static const MCOperandInfo OperandInfo168[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3891 | | static const MCOperandInfo OperandInfo169[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, }; |
3892 | | static const MCOperandInfo OperandInfo170[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3893 | | static const MCOperandInfo OperandInfo171[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3894 | | static const MCOperandInfo OperandInfo172[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3895 | | static const MCOperandInfo OperandInfo173[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3896 | | static const MCOperandInfo OperandInfo174[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3897 | | static const MCOperandInfo OperandInfo175[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3898 | | static const MCOperandInfo OperandInfo176[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3899 | | static const MCOperandInfo OperandInfo177[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, }; |
3900 | | static const MCOperandInfo OperandInfo178[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3901 | | static const MCOperandInfo OperandInfo179[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3902 | | static const MCOperandInfo OperandInfo180[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3903 | | static const MCOperandInfo OperandInfo181[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3904 | | static const MCOperandInfo OperandInfo182[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3905 | | static const MCOperandInfo OperandInfo183[] = { { SystemZ::AR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::AR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3906 | | static const MCOperandInfo OperandInfo184[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3907 | | static const MCOperandInfo OperandInfo185[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3908 | | static const MCOperandInfo OperandInfo186[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3909 | | static const MCOperandInfo OperandInfo187[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3910 | | static const MCOperandInfo OperandInfo188[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3911 | | static const MCOperandInfo OperandInfo189[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3912 | | static const MCOperandInfo OperandInfo190[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3913 | | static const MCOperandInfo OperandInfo191[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3914 | | static const MCOperandInfo OperandInfo192[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3915 | | static const MCOperandInfo OperandInfo193[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3916 | | static const MCOperandInfo OperandInfo194[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3917 | | static const MCOperandInfo OperandInfo195[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3918 | | static const MCOperandInfo OperandInfo196[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3919 | | static const MCOperandInfo OperandInfo197[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3920 | | static const MCOperandInfo OperandInfo198[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3921 | | static const MCOperandInfo OperandInfo199[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3922 | | static const MCOperandInfo OperandInfo200[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3923 | | static const MCOperandInfo OperandInfo201[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3924 | | static const MCOperandInfo OperandInfo202[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::AR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3925 | | static const MCOperandInfo OperandInfo203[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3926 | | static const MCOperandInfo OperandInfo204[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3927 | | static const MCOperandInfo OperandInfo205[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3928 | | static const MCOperandInfo OperandInfo206[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
3929 | | static const MCOperandInfo OperandInfo207[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3930 | | static const MCOperandInfo OperandInfo208[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3931 | | static const MCOperandInfo OperandInfo209[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3932 | | static const MCOperandInfo OperandInfo210[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3933 | | static const MCOperandInfo OperandInfo211[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3934 | | static const MCOperandInfo OperandInfo212[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3935 | | static const MCOperandInfo OperandInfo213[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3936 | | static const MCOperandInfo OperandInfo214[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3937 | | static const MCOperandInfo OperandInfo215[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3938 | | static const MCOperandInfo OperandInfo216[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3939 | | static const MCOperandInfo OperandInfo217[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3940 | | static const MCOperandInfo OperandInfo218[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3941 | | static const MCOperandInfo OperandInfo219[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3942 | | static const MCOperandInfo OperandInfo220[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3943 | | static const MCOperandInfo OperandInfo221[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3944 | | static const MCOperandInfo OperandInfo222[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3945 | | static const MCOperandInfo OperandInfo223[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3946 | | static const MCOperandInfo OperandInfo224[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3947 | | static const MCOperandInfo OperandInfo225[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3948 | | static const MCOperandInfo OperandInfo226[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3949 | | static const MCOperandInfo OperandInfo227[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3950 | | static const MCOperandInfo OperandInfo228[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3951 | | static const MCOperandInfo OperandInfo229[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3952 | | static const MCOperandInfo OperandInfo230[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3953 | | static const MCOperandInfo OperandInfo231[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3954 | | static const MCOperandInfo OperandInfo232[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3955 | | static const MCOperandInfo OperandInfo233[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
3956 | | static const MCOperandInfo OperandInfo234[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((2 << 16) | (1 << MCOI::TIED_TO)) }, }; |
3957 | | static const MCOperandInfo OperandInfo235[] = { { SystemZ::AR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::AR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3958 | | static const MCOperandInfo OperandInfo236[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3959 | | static const MCOperandInfo OperandInfo237[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3960 | | static const MCOperandInfo OperandInfo238[] = { { SystemZ::CR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::CR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3961 | | static const MCOperandInfo OperandInfo239[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3962 | | static const MCOperandInfo OperandInfo240[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3963 | | static const MCOperandInfo OperandInfo241[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3964 | | static const MCOperandInfo OperandInfo242[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3965 | | static const MCOperandInfo OperandInfo243[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3966 | | static const MCOperandInfo OperandInfo244[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3967 | | static const MCOperandInfo OperandInfo245[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3968 | | static const MCOperandInfo OperandInfo246[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3969 | | static const MCOperandInfo OperandInfo247[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3970 | | static const MCOperandInfo OperandInfo248[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3971 | | static const MCOperandInfo OperandInfo249[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3972 | | static const MCOperandInfo OperandInfo250[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3973 | | static const MCOperandInfo OperandInfo251[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3974 | | static const MCOperandInfo OperandInfo252[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3975 | | static const MCOperandInfo OperandInfo253[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3976 | | static const MCOperandInfo OperandInfo254[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3977 | | static const MCOperandInfo OperandInfo255[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3978 | | static const MCOperandInfo OperandInfo256[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3979 | | static const MCOperandInfo OperandInfo257[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3980 | | static const MCOperandInfo OperandInfo258[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3981 | | static const MCOperandInfo OperandInfo259[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3982 | | static const MCOperandInfo OperandInfo260[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3983 | | static const MCOperandInfo OperandInfo261[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3984 | | static const MCOperandInfo OperandInfo262[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3985 | | static const MCOperandInfo OperandInfo263[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3986 | | static const MCOperandInfo OperandInfo264[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3987 | | static const MCOperandInfo OperandInfo265[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3988 | | static const MCOperandInfo OperandInfo266[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3989 | | static const MCOperandInfo OperandInfo267[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3990 | | static const MCOperandInfo OperandInfo268[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3991 | | static const MCOperandInfo OperandInfo269[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3992 | | static const MCOperandInfo OperandInfo270[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3993 | | static const MCOperandInfo OperandInfo271[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3994 | | static const MCOperandInfo OperandInfo272[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3995 | | static const MCOperandInfo OperandInfo273[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3996 | | static const MCOperandInfo OperandInfo274[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3997 | | static const MCOperandInfo OperandInfo275[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
3998 | | static const MCOperandInfo OperandInfo276[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
3999 | | static const MCOperandInfo OperandInfo277[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4000 | | static const MCOperandInfo OperandInfo278[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
4001 | | static const MCOperandInfo OperandInfo279[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4002 | | static const MCOperandInfo OperandInfo280[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
4003 | | static const MCOperandInfo OperandInfo281[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
4004 | | static const MCOperandInfo OperandInfo282[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
4005 | | static const MCOperandInfo OperandInfo283[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
4006 | | static const MCOperandInfo OperandInfo284[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4007 | | static const MCOperandInfo OperandInfo285[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
4008 | | static const MCOperandInfo OperandInfo286[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4009 | | static const MCOperandInfo OperandInfo287[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4010 | | static const MCOperandInfo OperandInfo288[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
4011 | | static const MCOperandInfo OperandInfo289[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
4012 | | static const MCOperandInfo OperandInfo290[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4013 | | static const MCOperandInfo OperandInfo291[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
4014 | | static const MCOperandInfo OperandInfo292[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4015 | | static const MCOperandInfo OperandInfo293[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4016 | | static const MCOperandInfo OperandInfo294[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4017 | | static const MCOperandInfo OperandInfo295[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4018 | | static const MCOperandInfo OperandInfo296[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4019 | | static const MCOperandInfo OperandInfo297[] = { { SystemZ::AR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
4020 | | static const MCOperandInfo OperandInfo298[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4021 | | static const MCOperandInfo OperandInfo299[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4022 | | static const MCOperandInfo OperandInfo300[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4023 | | static const MCOperandInfo OperandInfo301[] = { { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4024 | | static const MCOperandInfo OperandInfo302[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4025 | | static const MCOperandInfo OperandInfo303[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4026 | | static const MCOperandInfo OperandInfo304[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4027 | | static const MCOperandInfo OperandInfo305[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4028 | | static const MCOperandInfo OperandInfo306[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4029 | | static const MCOperandInfo OperandInfo307[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4030 | | static const MCOperandInfo OperandInfo308[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4031 | | static const MCOperandInfo OperandInfo309[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
4032 | | static const MCOperandInfo OperandInfo310[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, }; |
4033 | | static const MCOperandInfo OperandInfo311[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4034 | | static const MCOperandInfo OperandInfo312[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4035 | | static const MCOperandInfo OperandInfo313[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, }; |
4036 | | static const MCOperandInfo OperandInfo314[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4037 | | static const MCOperandInfo OperandInfo315[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
4038 | | static const MCOperandInfo OperandInfo316[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4039 | | static const MCOperandInfo OperandInfo317[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
4040 | | static const MCOperandInfo OperandInfo318[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4041 | | static const MCOperandInfo OperandInfo319[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4042 | | static const MCOperandInfo OperandInfo320[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4043 | | static const MCOperandInfo OperandInfo321[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
4044 | | static const MCOperandInfo OperandInfo322[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4045 | | static const MCOperandInfo OperandInfo323[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4046 | | static const MCOperandInfo OperandInfo324[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4047 | | static const MCOperandInfo OperandInfo325[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4048 | | static const MCOperandInfo OperandInfo326[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4049 | | static const MCOperandInfo OperandInfo327[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4050 | | static const MCOperandInfo OperandInfo328[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4051 | | static const MCOperandInfo OperandInfo329[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4052 | | static const MCOperandInfo OperandInfo330[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4053 | | static const MCOperandInfo OperandInfo331[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4054 | | static const MCOperandInfo OperandInfo332[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4055 | | static const MCOperandInfo OperandInfo333[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4056 | | static const MCOperandInfo OperandInfo334[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4057 | | static const MCOperandInfo OperandInfo335[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4058 | | static const MCOperandInfo OperandInfo336[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4059 | | static const MCOperandInfo OperandInfo337[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4060 | | static const MCOperandInfo OperandInfo338[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4061 | | static const MCOperandInfo OperandInfo339[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4062 | | static const MCOperandInfo OperandInfo340[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4063 | | static const MCOperandInfo OperandInfo341[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4064 | | static const MCOperandInfo OperandInfo342[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4065 | | static const MCOperandInfo OperandInfo343[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4066 | | static const MCOperandInfo OperandInfo344[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4067 | | static const MCOperandInfo OperandInfo345[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4068 | | static const MCOperandInfo OperandInfo346[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4069 | | static const MCOperandInfo OperandInfo347[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4070 | | static const MCOperandInfo OperandInfo348[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
4071 | | static const MCOperandInfo OperandInfo349[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
4072 | | static const MCOperandInfo OperandInfo350[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4073 | | static const MCOperandInfo OperandInfo351[] = { { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4074 | | static const MCOperandInfo OperandInfo352[] = { { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
4075 | | static const MCOperandInfo OperandInfo353[] = { { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
4076 | | static const MCOperandInfo OperandInfo354[] = { { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4077 | | static const MCOperandInfo OperandInfo355[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
4078 | | static const MCOperandInfo OperandInfo356[] = { { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
4079 | | static const MCOperandInfo OperandInfo357[] = { { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4080 | | static const MCOperandInfo OperandInfo358[] = { { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4081 | | static const MCOperandInfo OperandInfo359[] = { { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
4082 | | static const MCOperandInfo OperandInfo360[] = { { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
4083 | | static const MCOperandInfo OperandInfo361[] = { { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4084 | | static const MCOperandInfo OperandInfo362[] = { { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4085 | | static const MCOperandInfo OperandInfo363[] = { { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4086 | | static const MCOperandInfo OperandInfo364[] = { { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
4087 | | |
4088 | | extern const MCInstrDesc SystemZInsts[] = { |
4089 | | { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI |
4090 | | { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM |
4091 | | { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR |
4092 | | { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = CFI_INSTRUCTION |
4093 | | { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = EH_LABEL |
4094 | | { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = GC_LABEL |
4095 | | { 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = ANNOTATION_LABEL |
4096 | | { 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #7 = KILL |
4097 | | { 8, 3, 1, 0, 29, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #8 = EXTRACT_SUBREG |
4098 | | { 9, 4, 1, 0, 30, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #9 = INSERT_SUBREG |
4099 | | { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF |
4100 | | { 11, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #11 = SUBREG_TO_REG |
4101 | | { 12, 3, 1, 0, 28, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #12 = COPY_TO_REGCLASS |
4102 | | { 13, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #13 = DBG_VALUE |
4103 | | { 14, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #14 = DBG_LABEL |
4104 | | { 15, 2, 1, 0, 31, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = REG_SEQUENCE |
4105 | | { 16, 2, 1, 0, 28, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #16 = COPY |
4106 | | { 17, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #17 = BUNDLE |
4107 | | { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_START |
4108 | | { 19, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #19 = LIFETIME_END |
4109 | | { 20, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #20 = STACKMAP |
4110 | | { 21, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #21 = FENTRY_CALL |
4111 | | { 22, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #22 = PATCHPOINT |
4112 | | { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD |
4113 | | { 24, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #24 = STATEPOINT |
4114 | | { 25, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #25 = LOCAL_ESCAPE |
4115 | | { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP |
4116 | | { 27, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #27 = PATCHABLE_OP |
4117 | | { 28, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #28 = PATCHABLE_FUNCTION_ENTER |
4118 | | { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET |
4119 | | { 30, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #30 = PATCHABLE_FUNCTION_EXIT |
4120 | | { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL |
4121 | | { 32, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #32 = PATCHABLE_EVENT_CALL |
4122 | | { 33, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #33 = PATCHABLE_TYPED_EVENT_CALL |
4123 | | { 34, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #34 = ICALL_BRANCH_FUNNEL |
4124 | | { 35, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #35 = G_ADD |
4125 | | { 36, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #36 = G_SUB |
4126 | | { 37, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #37 = G_MUL |
4127 | | { 38, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #38 = G_SDIV |
4128 | | { 39, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #39 = G_UDIV |
4129 | | { 40, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #40 = G_SREM |
4130 | | { 41, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #41 = G_UREM |
4131 | | { 42, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #42 = G_AND |
4132 | | { 43, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #43 = G_OR |
4133 | | { 44, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #44 = G_XOR |
4134 | | { 45, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #45 = G_IMPLICIT_DEF |
4135 | | { 46, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #46 = G_PHI |
4136 | | { 47, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #47 = G_FRAME_INDEX |
4137 | | { 48, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #48 = G_GLOBAL_VALUE |
4138 | | { 49, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #49 = G_EXTRACT |
4139 | | { 50, 2, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #50 = G_UNMERGE_VALUES |
4140 | | { 51, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #51 = G_INSERT |
4141 | | { 52, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #52 = G_MERGE_VALUES |
4142 | | { 53, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #53 = G_BUILD_VECTOR |
4143 | | { 54, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #54 = G_BUILD_VECTOR_TRUNC |
4144 | | { 55, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #55 = G_CONCAT_VECTORS |
4145 | | { 56, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #56 = G_PTRTOINT |
4146 | | { 57, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #57 = G_INTTOPTR |
4147 | | { 58, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #58 = G_BITCAST |
4148 | | { 59, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #59 = G_INTRINSIC_TRUNC |
4149 | | { 60, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #60 = G_INTRINSIC_ROUND |
4150 | | { 61, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #61 = G_LOAD |
4151 | | { 62, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #62 = G_SEXTLOAD |
4152 | | { 63, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #63 = G_ZEXTLOAD |
4153 | | { 64, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #64 = G_STORE |
4154 | | { 65, 5, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #65 = G_ATOMIC_CMPXCHG_WITH_SUCCESS |
4155 | | { 66, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #66 = G_ATOMIC_CMPXCHG |
4156 | | { 67, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #67 = G_ATOMICRMW_XCHG |
4157 | | { 68, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #68 = G_ATOMICRMW_ADD |
4158 | | { 69, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #69 = G_ATOMICRMW_SUB |
4159 | | { 70, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #70 = G_ATOMICRMW_AND |
4160 | | { 71, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #71 = G_ATOMICRMW_NAND |
4161 | | { 72, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #72 = G_ATOMICRMW_OR |
4162 | | { 73, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #73 = G_ATOMICRMW_XOR |
4163 | | { 74, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #74 = G_ATOMICRMW_MAX |
4164 | | { 75, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #75 = G_ATOMICRMW_MIN |
4165 | | { 76, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #76 = G_ATOMICRMW_UMAX |
4166 | | { 77, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #77 = G_ATOMICRMW_UMIN |
4167 | | { 78, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #78 = G_BRCOND |
4168 | | { 79, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #79 = G_BRINDIRECT |
4169 | | { 80, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #80 = G_INTRINSIC |
4170 | | { 81, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #81 = G_INTRINSIC_W_SIDE_EFFECTS |
4171 | | { 82, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #82 = G_ANYEXT |
4172 | | { 83, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #83 = G_TRUNC |
4173 | | { 84, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #84 = G_CONSTANT |
4174 | | { 85, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #85 = G_FCONSTANT |
4175 | | { 86, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #86 = G_VASTART |
4176 | | { 87, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #87 = G_VAARG |
4177 | | { 88, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #88 = G_SEXT |
4178 | | { 89, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #89 = G_ZEXT |
4179 | | { 90, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #90 = G_SHL |
4180 | | { 91, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #91 = G_LSHR |
4181 | | { 92, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #92 = G_ASHR |
4182 | | { 93, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #93 = G_ICMP |
4183 | | { 94, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #94 = G_FCMP |
4184 | | { 95, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #95 = G_SELECT |
4185 | | { 96, 4, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #96 = G_UADDO |
4186 | | { 97, 5, 2, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #97 = G_UADDE |
4187 | | { 98, 4, 2, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #98 = G_USUBO |
4188 | | { 99, 5, 2, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #99 = G_USUBE |
4189 | | { 100, 4, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #100 = G_SADDO |
4190 | | { 101, 5, 2, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #101 = G_SADDE |
4191 | | { 102, 4, 2, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #102 = G_SSUBO |
4192 | | { 103, 5, 2, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #103 = G_SSUBE |
4193 | | { 104, 4, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #104 = G_UMULO |
4194 | | { 105, 4, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #105 = G_SMULO |
4195 | | { 106, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #106 = G_UMULH |
4196 | | { 107, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #107 = G_SMULH |
4197 | | { 108, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #108 = G_FADD |
4198 | | { 109, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #109 = G_FSUB |
4199 | | { 110, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #110 = G_FMUL |
4200 | | { 111, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #111 = G_FMA |
4201 | | { 112, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #112 = G_FDIV |
4202 | | { 113, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #113 = G_FREM |
4203 | | { 114, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #114 = G_FPOW |
4204 | | { 115, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #115 = G_FEXP |
4205 | | { 116, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #116 = G_FEXP2 |
4206 | | { 117, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #117 = G_FLOG |
4207 | | { 118, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #118 = G_FLOG2 |
4208 | | { 119, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #119 = G_FLOG10 |
4209 | | { 120, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #120 = G_FNEG |
4210 | | { 121, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #121 = G_FPEXT |
4211 | | { 122, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #122 = G_FPTRUNC |
4212 | | { 123, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #123 = G_FPTOSI |
4213 | | { 124, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #124 = G_FPTOUI |
4214 | | { 125, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #125 = G_SITOFP |
4215 | | { 126, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #126 = G_UITOFP |
4216 | | { 127, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #127 = G_FABS |
4217 | | { 128, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #128 = G_FCANONICALIZE |
4218 | | { 129, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #129 = G_GEP |
4219 | | { 130, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #130 = G_PTR_MASK |
4220 | | { 131, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #131 = G_BR |
4221 | | { 132, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #132 = G_INSERT_VECTOR_ELT |
4222 | | { 133, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #133 = G_EXTRACT_VECTOR_ELT |
4223 | | { 134, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #134 = G_SHUFFLE_VECTOR |
4224 | | { 135, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #135 = G_CTTZ |
4225 | | { 136, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #136 = G_CTTZ_ZERO_UNDEF |
4226 | | { 137, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #137 = G_CTLZ |
4227 | | { 138, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #138 = G_CTLZ_ZERO_UNDEF |
4228 | | { 139, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #139 = G_CTPOP |
4229 | | { 140, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #140 = G_BSWAP |
4230 | | { 141, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #141 = G_FCEIL |
4231 | | { 142, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #142 = G_FCOS |
4232 | | { 143, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #143 = G_FSIN |
4233 | | { 144, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #144 = G_FSQRT |
4234 | | { 145, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #145 = G_FFLOOR |
4235 | | { 146, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #146 = G_ADDRSPACE_CAST |
4236 | | { 147, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #147 = G_BLOCK_ADDR |
4237 | | { 148, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #148 = ADJCALLSTACKDOWN |
4238 | | { 149, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #149 = ADJCALLSTACKUP |
4239 | | { 150, 4, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #150 = ADJDYNALLOC |
4240 | | { 151, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #151 = AEXT128 |
4241 | | { 152, 3, 1, 0, 103, 0|(1ULL<<MCID::Pseudo), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr }, // Inst #152 = AFIMux |
4242 | | { 153, 3, 1, 0, 109, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr }, // Inst #153 = AHIMux |
4243 | | { 154, 3, 1, 0, 109, 0|(1ULL<<MCID::Pseudo), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr }, // Inst #154 = AHIMuxK |
4244 | | { 155, 8, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr }, // Inst #155 = ATOMIC_CMP_SWAPW |
4245 | | { 156, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #156 = ATOMIC_LOADW_AFI |
4246 | | { 157, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #157 = ATOMIC_LOADW_AR |
4247 | | { 158, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #158 = ATOMIC_LOADW_MAX |
4248 | | { 159, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #159 = ATOMIC_LOADW_MIN |
4249 | | { 160, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #160 = ATOMIC_LOADW_NILH |
4250 | | { 161, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #161 = ATOMIC_LOADW_NILHi |
4251 | | { 162, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #162 = ATOMIC_LOADW_NR |
4252 | | { 163, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #163 = ATOMIC_LOADW_NRi |
4253 | | { 164, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #164 = ATOMIC_LOADW_OILH |
4254 | | { 165, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #165 = ATOMIC_LOADW_OR |
4255 | | { 166, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #166 = ATOMIC_LOADW_SR |
4256 | | { 167, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #167 = ATOMIC_LOADW_UMAX |
4257 | | { 168, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #168 = ATOMIC_LOADW_UMIN |
4258 | | { 169, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #169 = ATOMIC_LOADW_XILF |
4259 | | { 170, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #170 = ATOMIC_LOADW_XR |
4260 | | { 171, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #171 = ATOMIC_LOAD_AFI |
4261 | | { 172, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #172 = ATOMIC_LOAD_AGFI |
4262 | | { 173, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #173 = ATOMIC_LOAD_AGHI |
4263 | | { 174, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #174 = ATOMIC_LOAD_AGR |
4264 | | { 175, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #175 = ATOMIC_LOAD_AHI |
4265 | | { 176, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #176 = ATOMIC_LOAD_AR |
4266 | | { 177, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #177 = ATOMIC_LOAD_MAX_32 |
4267 | | { 178, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #178 = ATOMIC_LOAD_MAX_64 |
4268 | | { 179, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #179 = ATOMIC_LOAD_MIN_32 |
4269 | | { 180, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #180 = ATOMIC_LOAD_MIN_64 |
4270 | | { 181, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #181 = ATOMIC_LOAD_NGR |
4271 | | { 182, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #182 = ATOMIC_LOAD_NGRi |
4272 | | { 183, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #183 = ATOMIC_LOAD_NIHF64 |
4273 | | { 184, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #184 = ATOMIC_LOAD_NIHF64i |
4274 | | { 185, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #185 = ATOMIC_LOAD_NIHH64 |
4275 | | { 186, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #186 = ATOMIC_LOAD_NIHH64i |
4276 | | { 187, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #187 = ATOMIC_LOAD_NIHL64 |
4277 | | { 188, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #188 = ATOMIC_LOAD_NIHL64i |
4278 | | { 189, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #189 = ATOMIC_LOAD_NILF |
4279 | | { 190, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #190 = ATOMIC_LOAD_NILF64 |
4280 | | { 191, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #191 = ATOMIC_LOAD_NILF64i |
4281 | | { 192, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #192 = ATOMIC_LOAD_NILFi |
4282 | | { 193, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #193 = ATOMIC_LOAD_NILH |
4283 | | { 194, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #194 = ATOMIC_LOAD_NILH64 |
4284 | | { 195, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #195 = ATOMIC_LOAD_NILH64i |
4285 | | { 196, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #196 = ATOMIC_LOAD_NILHi |
4286 | | { 197, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #197 = ATOMIC_LOAD_NILL |
4287 | | { 198, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #198 = ATOMIC_LOAD_NILL64 |
4288 | | { 199, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #199 = ATOMIC_LOAD_NILL64i |
4289 | | { 200, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #200 = ATOMIC_LOAD_NILLi |
4290 | | { 201, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #201 = ATOMIC_LOAD_NR |
4291 | | { 202, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #202 = ATOMIC_LOAD_NRi |
4292 | | { 203, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #203 = ATOMIC_LOAD_OGR |
4293 | | { 204, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #204 = ATOMIC_LOAD_OIHF64 |
4294 | | { 205, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #205 = ATOMIC_LOAD_OIHH64 |
4295 | | { 206, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #206 = ATOMIC_LOAD_OIHL64 |
4296 | | { 207, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #207 = ATOMIC_LOAD_OILF |
4297 | | { 208, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #208 = ATOMIC_LOAD_OILF64 |
4298 | | { 209, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #209 = ATOMIC_LOAD_OILH |
4299 | | { 210, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #210 = ATOMIC_LOAD_OILH64 |
4300 | | { 211, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #211 = ATOMIC_LOAD_OILL |
4301 | | { 212, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #212 = ATOMIC_LOAD_OILL64 |
4302 | | { 213, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #213 = ATOMIC_LOAD_OR |
4303 | | { 214, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #214 = ATOMIC_LOAD_SGR |
4304 | | { 215, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #215 = ATOMIC_LOAD_SR |
4305 | | { 216, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #216 = ATOMIC_LOAD_UMAX_32 |
4306 | | { 217, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #217 = ATOMIC_LOAD_UMAX_64 |
4307 | | { 218, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #218 = ATOMIC_LOAD_UMIN_32 |
4308 | | { 219, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #219 = ATOMIC_LOAD_UMIN_64 |
4309 | | { 220, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #220 = ATOMIC_LOAD_XGR |
4310 | | { 221, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #221 = ATOMIC_LOAD_XIHF64 |
4311 | | { 222, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #222 = ATOMIC_LOAD_XILF |
4312 | | { 223, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #223 = ATOMIC_LOAD_XILF64 |
4313 | | { 224, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #224 = ATOMIC_LOAD_XR |
4314 | | { 225, 7, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #225 = ATOMIC_SWAPW |
4315 | | { 226, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #226 = ATOMIC_SWAP_32 |
4316 | | { 227, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #227 = ATOMIC_SWAP_64 |
4317 | | { 228, 2, 0, 0, 212, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #228 = CFIMux |
4318 | | { 229, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #229 = CGIBCall |
4319 | | { 230, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #230 = CGIBReturn |
4320 | | { 231, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #231 = CGRBCall |
4321 | | { 232, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #232 = CGRBReturn |
4322 | | { 233, 2, 0, 0, 212, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #233 = CHIMux |
4323 | | { 234, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #234 = CIBCall |
4324 | | { 235, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #235 = CIBReturn |
4325 | | { 236, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #236 = CLCLoop |
4326 | | { 237, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr }, // Inst #237 = CLCSequence |
4327 | | { 238, 2, 0, 0, 221, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x103800ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #238 = CLFIMux |
4328 | | { 239, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #239 = CLGIBCall |
4329 | | { 240, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #240 = CLGIBReturn |
4330 | | { 241, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #241 = CLGRBCall |
4331 | | { 242, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #242 = CLGRBReturn |
4332 | | { 243, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #243 = CLIBCall |
4333 | | { 244, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #244 = CLIBReturn |
4334 | | { 245, 4, 0, 0, 219, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x10388cULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr }, // Inst #245 = CLMux |
4335 | | { 246, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #246 = CLRBCall |
4336 | | { 247, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #247 = CLRBReturn |
4337 | | { 248, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr }, // Inst #248 = CLSTLoop |
4338 | | { 249, 4, 0, 0, 210, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x388cULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr }, // Inst #249 = CMux |
4339 | | { 250, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #250 = CRBCall |
4340 | | { 251, 3, 0, 6, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #251 = CRBReturn |
4341 | | { 252, 1, 0, 2, 20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, ImplicitList3, OperandInfo51, -1 ,nullptr }, // Inst #252 = CallBASR |
4342 | | { 253, 2, 0, 2, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x40000ULL, ImplicitList2, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #253 = CallBCR |
4343 | | { 254, 0, 0, 2, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, nullptr, -1 ,nullptr }, // Inst #254 = CallBR |
4344 | | { 255, 1, 0, 6, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #255 = CallBRASL |
4345 | | { 256, 3, 0, 6, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x40000ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #256 = CallBRCL |
4346 | | { 257, 1, 0, 6, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #257 = CallJG |
4347 | | { 258, 2, 0, 2, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x40000ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #258 = CondReturn |
4348 | | { 259, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #259 = CondStore16 |
4349 | | { 260, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #260 = CondStore16Inv |
4350 | | { 261, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #261 = CondStore16Mux |
4351 | | { 262, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #262 = CondStore16MuxInv |
4352 | | { 263, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #263 = CondStore32 |
4353 | | { 264, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #264 = CondStore32Inv |
4354 | | { 265, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #265 = CondStore32Mux |
4355 | | { 266, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #266 = CondStore32MuxInv |
4356 | | { 267, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #267 = CondStore64 |
4357 | | { 268, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #268 = CondStore64Inv |
4358 | | { 269, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #269 = CondStore8 |
4359 | | { 270, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #270 = CondStore8Inv |
4360 | | { 271, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #271 = CondStore8Mux |
4361 | | { 272, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #272 = CondStore8MuxInv |
4362 | | { 273, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #273 = CondStoreF32 |
4363 | | { 274, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #274 = CondStoreF32Inv |
4364 | | { 275, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #275 = CondStoreF64 |
4365 | | { 276, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #276 = CondStoreF64Inv |
4366 | | { 277, 2, 0, 4, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #277 = CondTrap |
4367 | | { 278, 1, 1, 6, 84, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #278 = GOT |
4368 | | { 279, 2, 1, 0, 93, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #279 = IIFMux |
4369 | | { 280, 3, 1, 6, 94, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #280 = IIHF64 |
4370 | | { 281, 3, 1, 4, 95, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #281 = IIHH64 |
4371 | | { 282, 3, 1, 4, 96, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #282 = IIHL64 |
4372 | | { 283, 3, 1, 0, 93, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #283 = IIHMux |
4373 | | { 284, 3, 1, 6, 97, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #284 = IILF64 |
4374 | | { 285, 3, 1, 4, 98, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #285 = IILH64 |
4375 | | { 286, 3, 1, 4, 99, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #286 = IILL64 |
4376 | | { 287, 3, 1, 0, 93, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #287 = IILMux |
4377 | | { 288, 4, 1, 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x1dULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #288 = L128 |
4378 | | { 289, 4, 1, 0, 58, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x2cULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #289 = LBMux |
4379 | | { 290, 2, 1, 6, 692, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #290 = LEFR |
4380 | | { 291, 2, 1, 6, 693, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #291 = LFER |
4381 | | { 292, 2, 1, 0, 39, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #292 = LHIMux |
4382 | | { 293, 4, 1, 0, 60, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4cULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #293 = LHMux |
4383 | | { 294, 4, 1, 0, 66, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x2cULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #294 = LLCMux |
4384 | | { 295, 2, 1, 0, 63, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #295 = LLCRMux |
4385 | | { 296, 4, 1, 0, 67, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4cULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #296 = LLHMux |
4386 | | { 297, 2, 1, 0, 64, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #297 = LLHRMux |
4387 | | { 298, 4, 1, 0, 32, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x8dULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #298 = LMux |
4388 | | { 299, 5, 1, 0, 51, 0|(1ULL<<MCID::Pseudo), 0x80000ULL, ImplicitList1, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #299 = LOCHIMux |
4389 | | { 300, 6, 1, 0, 52, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80080ULL, ImplicitList1, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #300 = LOCMux |
4390 | | { 301, 5, 1, 0, 49, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x80000ULL, ImplicitList1, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #301 = LOCRMux |
4391 | | { 302, 2, 1, 0, 40, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #302 = LRMux |
4392 | | { 303, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr }, // Inst #303 = LTDBRCompare_VecPseudo |
4393 | | { 304, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo68, -1 ,nullptr }, // Inst #304 = LTEBRCompare_VecPseudo |
4394 | | { 305, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo69, -1 ,nullptr }, // Inst #305 = LTXBRCompare_VecPseudo |
4395 | | { 306, 4, 1, 0, 341, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x1dULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #306 = LX |
4396 | | { 307, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #307 = MVCLoop |
4397 | | { 308, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr }, // Inst #308 = MVCSequence |
4398 | | { 309, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr }, // Inst #309 = MVSTLoop |
4399 | | { 310, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #310 = MemBarrier |
4400 | | { 311, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #311 = NCLoop |
4401 | | { 312, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr }, // Inst #312 = NCSequence |
4402 | | { 313, 3, 1, 0, 143, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x23000ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr }, // Inst #313 = NIFMux |
4403 | | { 314, 3, 1, 6, 145, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr }, // Inst #314 = NIHF64 |
4404 | | { 315, 3, 1, 4, 146, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr }, // Inst #315 = NIHH64 |
4405 | | { 316, 3, 1, 4, 147, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr }, // Inst #316 = NIHL64 |
4406 | | { 317, 3, 1, 0, 143, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr }, // Inst #317 = NIHMux |
4407 | | { 318, 3, 1, 6, 148, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr }, // Inst #318 = NILF64 |
4408 | | { 319, 3, 1, 4, 149, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr }, // Inst #319 = NILH64 |
4409 | | { 320, 3, 1, 4, 150, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr }, // Inst #320 = NILL64 |
4410 | | { 321, 3, 1, 0, 143, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr }, // Inst #321 = NILMux |
4411 | | { 322, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #322 = OCLoop |
4412 | | { 323, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr }, // Inst #323 = OCSequence |
4413 | | { 324, 3, 1, 0, 156, 0|(1ULL<<MCID::Pseudo), 0x23000ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr }, // Inst #324 = OIFMux |
4414 | | { 325, 3, 1, 6, 157, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr }, // Inst #325 = OIHF64 |
4415 | | { 326, 3, 1, 4, 158, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr }, // Inst #326 = OIHH64 |
4416 | | { 327, 3, 1, 4, 159, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr }, // Inst #327 = OIHL64 |
4417 | | { 328, 3, 1, 0, 156, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr }, // Inst #328 = OIHMux |
4418 | | { 329, 3, 1, 6, 160, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr }, // Inst #329 = OILF64 |
4419 | | { 330, 3, 1, 4, 161, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr }, // Inst #330 = OILH64 |
4420 | | { 331, 3, 1, 4, 162, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr }, // Inst #331 = OILL64 |
4421 | | { 332, 3, 1, 0, 156, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr }, // Inst #332 = OILMux |
4422 | | { 333, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #333 = PAIR128 |
4423 | | { 334, 6, 1, 6, 206, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #334 = RISBHH |
4424 | | { 335, 6, 1, 6, 206, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #335 = RISBHL |
4425 | | { 336, 6, 1, 6, 207, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #336 = RISBLH |
4426 | | { 337, 6, 1, 6, 207, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #337 = RISBLL |
4427 | | { 338, 6, 1, 0, 208, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #338 = RISBMux |
4428 | | { 339, 0, 0, 2, 22, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #339 = Return |
4429 | | { 340, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr }, // Inst #340 = SRSTLoop |
4430 | | { 341, 4, 0, 0, 46, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1eULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #341 = ST128 |
4431 | | { 342, 4, 0, 0, 73, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x2cULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #342 = STCMux |
4432 | | { 343, 4, 0, 0, 74, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x2cULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #343 = STHMux |
4433 | | { 344, 4, 0, 0, 47, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8eULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #344 = STMux |
4434 | | { 345, 5, 0, 0, 53, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80080ULL, ImplicitList1, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #345 = STOCMux |
4435 | | { 346, 4, 0, 0, 343, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1eULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #346 = STX |
4436 | | { 347, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #347 = Select32 |
4437 | | { 348, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #348 = Select64 |
4438 | | { 349, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #349 = SelectF128 |
4439 | | { 350, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #350 = SelectF32 |
4440 | | { 351, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #351 = SelectF64 |
4441 | | { 352, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #352 = SelectVR128 |
4442 | | { 353, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #353 = SelectVR32 |
4443 | | { 354, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #354 = SelectVR64 |
4444 | | { 355, 0, 0, 2, 259, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #355 = Serialize |
4445 | | { 356, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo86, -1 ,nullptr }, // Inst #356 = TBEGIN_nofloat |
4446 | | { 357, 1, 0, 6, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #357 = TLS_GDCALL |
4447 | | { 358, 1, 0, 6, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #358 = TLS_LDCALL |
4448 | | { 359, 2, 0, 4, 250, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr }, // Inst #359 = TMHH64 |
4449 | | { 360, 2, 0, 4, 251, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr }, // Inst #360 = TMHL64 |
4450 | | { 361, 2, 0, 0, 249, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #361 = TMHMux |
4451 | | { 362, 2, 0, 4, 252, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr }, // Inst #362 = TMLH64 |
4452 | | { 363, 2, 0, 4, 253, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr }, // Inst #363 = TMLL64 |
4453 | | { 364, 2, 0, 0, 249, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #364 = TMLMux |
4454 | | { 365, 0, 0, 4, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #365 = Trap |
4455 | | { 366, 4, 1, 6, 516, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #366 = VL32 |
4456 | | { 367, 4, 1, 6, 516, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #367 = VL64 |
4457 | | { 368, 2, 1, 6, 504, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #368 = VLR32 |
4458 | | { 369, 2, 1, 6, 504, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #369 = VLR64 |
4459 | | { 370, 3, 1, 6, 507, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #370 = VLVGP32 |
4460 | | { 371, 4, 0, 6, 523, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #371 = VST32 |
4461 | | { 372, 4, 0, 6, 523, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #372 = VST64 |
4462 | | { 373, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #373 = XCLoop |
4463 | | { 374, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr }, // Inst #374 = XCSequence |
4464 | | { 375, 3, 1, 0, 167, 0|(1ULL<<MCID::Pseudo), 0x23000ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr }, // Inst #375 = XIFMux |
4465 | | { 376, 3, 1, 6, 169, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr }, // Inst #376 = XIHF64 |
4466 | | { 377, 3, 1, 6, 170, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr }, // Inst #377 = XILF64 |
4467 | | { 378, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #378 = ZEXT128 |
4468 | | { 379, 5, 1, 4, 100, 0|(1ULL<<MCID::MayLoad), 0x23c88ULL, nullptr, ImplicitList1, OperandInfo93, -1 ,nullptr }, // Inst #379 = A |
4469 | | { 380, 5, 1, 4, 422, 0|(1ULL<<MCID::MayLoad), 0x108ULL, nullptr, ImplicitList1, OperandInfo94, -1 ,nullptr }, // Inst #380 = AD |
4470 | | { 381, 5, 1, 6, 368, 0|(1ULL<<MCID::MayLoad), 0x3fd08ULL, nullptr, ImplicitList1, OperandInfo94, -1 ,nullptr }, // Inst #381 = ADB |
4471 | | { 382, 3, 1, 4, 369, 0|(1ULL<<MCID::Commutable), 0x3fc00ULL, nullptr, ImplicitList1, OperandInfo95, -1 ,nullptr }, // Inst #382 = ADBR |
4472 | | { 383, 3, 1, 2, 423, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo95, -1 ,nullptr }, // Inst #383 = ADR |
4473 | | { 384, 3, 1, 4, 482, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo96, -1 ,nullptr }, // Inst #384 = ADTR |
4474 | | { 385, 4, 1, 4, 482, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo97, -1 ,nullptr }, // Inst #385 = ADTRA |
4475 | | { 386, 5, 1, 4, 422, 0|(1ULL<<MCID::MayLoad), 0x88ULL, nullptr, ImplicitList1, OperandInfo98, -1 ,nullptr }, // Inst #386 = AE |
4476 | | { 387, 5, 1, 6, 368, 0|(1ULL<<MCID::MayLoad), 0x3fc88ULL, nullptr, ImplicitList1, OperandInfo98, -1 ,nullptr }, // Inst #387 = AEB |
4477 | | { 388, 3, 1, 4, 369, 0|(1ULL<<MCID::Commutable), 0x3fc00ULL, nullptr, ImplicitList1, OperandInfo99, -1 ,nullptr }, // Inst #388 = AEBR |
4478 | | { 389, 3, 1, 2, 423, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo99, -1 ,nullptr }, // Inst #389 = AER |
4479 | | { 390, 3, 1, 6, 103, 0, 0x23c00ULL, nullptr, ImplicitList1, OperandInfo100, -1 ,nullptr }, // Inst #390 = AFI |
4480 | | { 391, 5, 1, 6, 104, 0|(1ULL<<MCID::MayLoad), 0x23d0cULL, nullptr, ImplicitList1, OperandInfo101, -1 ,nullptr }, // Inst #391 = AG |
4481 | | { 392, 5, 1, 6, 806, 0|(1ULL<<MCID::MayLoad), 0x23c8cULL, nullptr, ImplicitList1, OperandInfo101, -1 ,nullptr }, // Inst #392 = AGF |
4482 | | { 393, 3, 1, 6, 105, 0, 0x23c00ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr }, // Inst #393 = AGFI |
4483 | | { 394, 3, 1, 4, 125, 0, 0x23c00ULL, nullptr, ImplicitList1, OperandInfo102, -1 ,nullptr }, // Inst #394 = AGFR |
4484 | | { 395, 5, 1, 6, 124, 0|(1ULL<<MCID::MayLoad), 0x23c4cULL, nullptr, ImplicitList1, OperandInfo101, -1 ,nullptr }, // Inst #395 = AGH |
4485 | | { 396, 3, 1, 4, 106, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr }, // Inst #396 = AGHI |
4486 | | { 397, 3, 1, 6, 106, 0, 0x23c00ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #397 = AGHIK |
4487 | | { 398, 3, 1, 4, 107, 0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo103, -1 ,nullptr }, // Inst #398 = AGR |
4488 | | { 399, 3, 1, 4, 107, 0|(1ULL<<MCID::Commutable), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo104, -1 ,nullptr }, // Inst #399 = AGRK |
4489 | | { 400, 3, 0, 6, 121, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x23c04ULL, nullptr, ImplicitList1, OperandInfo86, -1 ,nullptr }, // Inst #400 = AGSI |
4490 | | { 401, 5, 1, 4, 101, 0|(1ULL<<MCID::MayLoad), 0x23c48ULL, nullptr, ImplicitList1, OperandInfo93, -1 ,nullptr }, // Inst #401 = AH |
4491 | | { 402, 3, 1, 4, 118, 0, 0x23c00ULL, nullptr, ImplicitList1, OperandInfo105, -1 ,nullptr }, // Inst #402 = AHHHR |
4492 | | { 403, 3, 1, 4, 119, 0, 0x23c00ULL, nullptr, ImplicitList1, OperandInfo106, -1 ,nullptr }, // Inst #403 = AHHLR |
4493 | | { 404, 3, 1, 4, 108, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo100, -1 ,nullptr }, // Inst #404 = AHI |
4494 | | { 405, 3, 1, 6, 108, 0, 0x23c00ULL, nullptr, ImplicitList1, OperandInfo49, -1 ,nullptr }, // Inst #405 = AHIK |
4495 | | { 406, 5, 1, 6, 101, 0|(1ULL<<MCID::MayLoad), 0x23c4cULL, nullptr, ImplicitList1, OperandInfo93, -1 ,nullptr }, // Inst #406 = AHY |
4496 | | { 407, 3, 1, 6, 102, 0, 0x23c00ULL, nullptr, ImplicitList1, OperandInfo107, -1 ,nullptr }, // Inst #407 = AIH |
4497 | | { 408, 5, 1, 4, 110, 0|(1ULL<<MCID::MayLoad), 0x88ULL, nullptr, ImplicitList1, OperandInfo93, -1 ,nullptr }, // Inst #408 = AL |
4498 | | { 409, 5, 1, 6, 122, 0|(1ULL<<MCID::MayLoad), 0x8cULL, ImplicitList1, ImplicitList1, OperandInfo93, -1 ,nullptr }, // Inst #409 = ALC |
4499 | | { 410, 5, 1, 6, 122, 0|(1ULL<<MCID::MayLoad), 0x10cULL, ImplicitList1, ImplicitList1, OperandInfo101, -1 ,nullptr }, // Inst #410 = ALCG |
4500 | | { 411, 3, 1, 4, 123, 0, 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo103, -1 ,nullptr }, // Inst #411 = ALCGR |
4501 | | { 412, 3, 1, 4, 123, 0, 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo108, -1 ,nullptr }, // Inst #412 = ALCR |
4502 | | { 413, 3, 1, 6, 111, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo100, -1 ,nullptr }, // Inst #413 = ALFI |
4503 | | { 414, 5, 1, 6, 112, 0|(1ULL<<MCID::MayLoad), 0x10cULL, nullptr, ImplicitList1, OperandInfo101, -1 ,nullptr }, // Inst #414 = ALG |
4504 | | { 415, 5, 1, 6, 824, 0|(1ULL<<MCID::MayLoad), 0x8cULL, nullptr, ImplicitList1, OperandInfo101, -1 ,nullptr }, // Inst #415 = ALGF |
4505 | | { 416, 3, 1, 6, 114, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr }, // Inst #416 = ALGFI |
4506 | | { 417, 3, 1, 4, 114, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo102, -1 ,nullptr }, // Inst #417 = ALGFR |
4507 | | { 418, 3, 1, 6, 113, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #418 = ALGHSIK |
4508 | | { 419, 3, 1, 4, 115, 0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo103, -1 ,nullptr }, // Inst #419 = ALGR |
4509 | | { 420, 3, 1, 4, 115, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo104, -1 ,nullptr }, // Inst #420 = ALGRK |
4510 | | { 421, 3, 0, 6, 121, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, ImplicitList1, OperandInfo86, -1 ,nullptr }, // Inst #421 = ALGSI |
4511 | | { 422, 3, 1, 4, 118, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo105, -1 ,nullptr }, // Inst #422 = ALHHHR |
4512 | | { 423, 3, 1, 4, 119, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo106, -1 ,nullptr }, // Inst #423 = ALHHLR |
4513 | | { 424, 3, 1, 6, 111, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo49, -1 ,nullptr }, // Inst #424 = ALHSIK |
4514 | | { 425, 3, 1, 2, 116, 0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo108, -1 ,nullptr }, // Inst #425 = ALR |
4515 | | { 426, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo109, -1 ,nullptr }, // Inst #426 = ALRK |
4516 | | { 427, 3, 0, 6, 823, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, ImplicitList1, OperandInfo86, -1 ,nullptr }, // Inst #427 = ALSI |
4517 | | { 428, 3, 1, 6, 120, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo107, -1 ,nullptr }, // Inst #428 = ALSIH |
4518 | | { 429, 3, 1, 6, 120, 0, 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #429 = ALSIHN |
4519 | | { 430, 5, 1, 6, 110, 0|(1ULL<<MCID::MayLoad), 0x8cULL, nullptr, ImplicitList1, OperandInfo93, -1 ,nullptr }, // Inst #430 = ALY |
4520 | | { 431, 6, 0, 6, 296, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, ImplicitList1, OperandInfo110, -1 ,nullptr }, // Inst #431 = AP |
4521 | | { 432, 3, 1, 2, 117, 0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo108, -1 ,nullptr }, // Inst #432 = AR |
4522 | | { 433, 3, 1, 4, 117, 0|(1ULL<<MCID::Commutable), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo109, -1 ,nullptr }, // Inst #433 = ARK |
4523 | | { 434, 3, 0, 6, 823, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x23c04ULL, nullptr, ImplicitList1, OperandInfo86, -1 ,nullptr }, // Inst #434 = ASI |
4524 | | { 435, 5, 1, 4, 422, 0|(1ULL<<MCID::MayLoad), 0x88ULL, nullptr, ImplicitList1, OperandInfo98, -1 ,nullptr }, // Inst #435 = AU |
4525 | | { 436, 3, 1, 2, 423, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo99, -1 ,nullptr }, // Inst #436 = AUR |
4526 | | { 437, 5, 1, 4, 422, 0|(1ULL<<MCID::MayLoad), 0x108ULL, nullptr, ImplicitList1, OperandInfo94, -1 ,nullptr }, // Inst #437 = AW |
4527 | | { 438, 3, 1, 2, 423, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo95, -1 ,nullptr }, // Inst #438 = AWR |
4528 | | { 439, 3, 1, 4, 370, 0|(1ULL<<MCID::Commutable), 0x3fc00ULL, nullptr, ImplicitList1, OperandInfo111, -1 ,nullptr }, // Inst #439 = AXBR |
4529 | | { 440, 3, 1, 2, 424, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo111, -1 ,nullptr }, // Inst #440 = AXR |
4530 | | { 441, 3, 1, 4, 483, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo112, -1 ,nullptr }, // Inst #441 = AXTR |
4531 | | { 442, 4, 1, 4, 483, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo113, -1 ,nullptr }, // Inst #442 = AXTRA |
4532 | | { 443, 5, 1, 6, 100, 0|(1ULL<<MCID::MayLoad), 0x23c8cULL, nullptr, ImplicitList1, OperandInfo93, -1 ,nullptr }, // Inst #443 = AY |
4533 | | { 444, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x8ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #444 = B |
4534 | | { 445, 2, 0, 4, 767, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #445 = BAKR |
4535 | | { 446, 4, 0, 4, 308, 0|(1ULL<<MCID::Call), 0x8ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr }, // Inst #446 = BAL |
4536 | | { 447, 2, 0, 2, 308, 0|(1ULL<<MCID::Call), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #447 = BALR |
4537 | | { 448, 4, 0, 4, 20, 0|(1ULL<<MCID::Call), 0x8ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr }, // Inst #448 = BAS |
4538 | | { 449, 2, 0, 2, 20, 0|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #449 = BASR |
4539 | | { 450, 2, 0, 2, 312, 0|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #450 = BASSM |
4540 | | { 451, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #451 = BAsmE |
4541 | | { 452, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #452 = BAsmH |
4542 | | { 453, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #453 = BAsmHE |
4543 | | { 454, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #454 = BAsmL |
4544 | | { 455, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #455 = BAsmLE |
4545 | | { 456, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #456 = BAsmLH |
4546 | | { 457, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #457 = BAsmM |
4547 | | { 458, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #458 = BAsmNE |
4548 | | { 459, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #459 = BAsmNH |
4549 | | { 460, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #460 = BAsmNHE |
4550 | | { 461, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #461 = BAsmNL |
4551 | | { 462, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #462 = BAsmNLE |
4552 | | { 463, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #463 = BAsmNLH |
4553 | | { 464, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #464 = BAsmNM |
4554 | | { 465, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #465 = BAsmNO |
4555 | | { 466, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #466 = BAsmNP |
4556 | | { 467, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #467 = BAsmNZ |
4557 | | { 468, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #468 = BAsmO |
4558 | | { 469, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #469 = BAsmP |
4559 | | { 470, 3, 0, 4, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #470 = BAsmZ |
4560 | | { 471, 5, 0, 4, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x40008ULL, ImplicitList1, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #471 = BC |
4561 | | { 472, 4, 0, 4, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #472 = BCAsm |
4562 | | { 473, 3, 0, 2, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x40000ULL, ImplicitList1, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #473 = BCR |
4563 | | { 474, 2, 0, 2, 4, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #474 = BCRAsm |
4564 | | { 475, 5, 1, 4, 9, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x8ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #475 = BCT |
4565 | | { 476, 5, 1, 6, 9, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0xcULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #476 = BCTG |
4566 | | { 477, 3, 1, 4, 9, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #477 = BCTGR |
4567 | | { 478, 3, 1, 2, 9, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #478 = BCTR |
4568 | | { 479, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #479 = BI |
4569 | | { 480, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #480 = BIAsmE |
4570 | | { 481, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #481 = BIAsmH |
4571 | | { 482, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #482 = BIAsmHE |
4572 | | { 483, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #483 = BIAsmL |
4573 | | { 484, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #484 = BIAsmLE |
4574 | | { 485, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #485 = BIAsmLH |
4575 | | { 486, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #486 = BIAsmM |
4576 | | { 487, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #487 = BIAsmNE |
4577 | | { 488, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #488 = BIAsmNH |
4578 | | { 489, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #489 = BIAsmNHE |
4579 | | { 490, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #490 = BIAsmNL |
4580 | | { 491, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #491 = BIAsmNLE |
4581 | | { 492, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #492 = BIAsmNLH |
4582 | | { 493, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #493 = BIAsmNM |
4583 | | { 494, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #494 = BIAsmNO |
4584 | | { 495, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #495 = BIAsmNP |
4585 | | { 496, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #496 = BIAsmNZ |
4586 | | { 497, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #497 = BIAsmO |
4587 | | { 498, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #498 = BIAsmP |
4588 | | { 499, 3, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #499 = BIAsmZ |
4589 | | { 500, 5, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x4000cULL, ImplicitList1, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #500 = BIC |
4590 | | { 501, 4, 0, 6, 6, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #501 = BICAsm |
4591 | | { 502, 5, 0, 6, 256, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #502 = BPP |
4592 | | { 503, 3, 0, 6, 257, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #503 = BPRP |
4593 | | { 504, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #504 = BR |
4594 | | { 505, 3, 0, 4, 18, 0|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #505 = BRAS |
4595 | | { 506, 3, 0, 6, 19, 0|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #506 = BRASL |
4596 | | { 507, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #507 = BRAsmE |
4597 | | { 508, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #508 = BRAsmH |
4598 | | { 509, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #509 = BRAsmHE |
4599 | | { 510, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #510 = BRAsmL |
4600 | | { 511, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #511 = BRAsmLE |
4601 | | { 512, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #512 = BRAsmLH |
4602 | | { 513, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #513 = BRAsmM |
4603 | | { 514, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #514 = BRAsmNE |
4604 | | { 515, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #515 = BRAsmNH |
4605 | | { 516, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #516 = BRAsmNHE |
4606 | | { 517, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #517 = BRAsmNL |
4607 | | { 518, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #518 = BRAsmNLE |
4608 | | { 519, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #519 = BRAsmNLH |
4609 | | { 520, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #520 = BRAsmNM |
4610 | | { 521, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #521 = BRAsmNO |
4611 | | { 522, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #522 = BRAsmNP |
4612 | | { 523, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #523 = BRAsmNZ |
4613 | | { 524, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #524 = BRAsmO |
4614 | | { 525, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #525 = BRAsmP |
4615 | | { 526, 1, 0, 2, 5, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #526 = BRAsmZ |
4616 | | { 527, 3, 0, 4, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x40000ULL, ImplicitList1, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #527 = BRC |
4617 | | { 528, 2, 0, 4, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #528 = BRCAsm |
4618 | | { 529, 3, 0, 6, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x40000ULL, ImplicitList1, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #529 = BRCL |
4619 | | { 530, 2, 0, 6, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #530 = BRCLAsm |
4620 | | { 531, 3, 1, 4, 7, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo100, -1 ,nullptr }, // Inst #531 = BRCT |
4621 | | { 532, 3, 1, 4, 7, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr }, // Inst #532 = BRCTG |
4622 | | { 533, 3, 1, 6, 8, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #533 = BRCTH |
4623 | | { 534, 4, 1, 4, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo122, -1 ,nullptr }, // Inst #534 = BRXH |
4624 | | { 535, 4, 1, 6, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo123, -1 ,nullptr }, // Inst #535 = BRXHG |
4625 | | { 536, 4, 1, 4, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo122, -1 ,nullptr }, // Inst #536 = BRXLE |
4626 | | { 537, 4, 1, 6, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo123, -1 ,nullptr }, // Inst #537 = BRXLG |
4627 | | { 538, 2, 1, 4, 765, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #538 = BSA |
4628 | | { 539, 2, 1, 4, 765, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #539 = BSG |
4629 | | { 540, 2, 0, 2, 311, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #540 = BSM |
4630 | | { 541, 5, 1, 4, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #541 = BXH |
4631 | | { 542, 5, 1, 6, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x4ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #542 = BXHG |
4632 | | { 543, 5, 1, 4, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #543 = BXLE |
4633 | | { 544, 5, 1, 6, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x4ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #544 = BXLEG |
4634 | | { 545, 4, 0, 4, 210, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3888ULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr }, // Inst #545 = C |
4635 | | { 546, 4, 0, 4, 446, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x108ULL, nullptr, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #546 = CD |
4636 | | { 547, 4, 0, 6, 387, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3d08ULL, nullptr, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #547 = CDB |
4637 | | { 548, 2, 0, 4, 388, 0|(1ULL<<MCID::Compare), 0x3c00ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr }, // Inst #548 = CDBR |
4638 | | { 549, 2, 1, 4, 350, 0, 0x0ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #549 = CDFBR |
4639 | | { 550, 4, 1, 4, 350, 0, 0x0ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #550 = CDFBRA |
4640 | | { 551, 2, 1, 4, 408, 0, 0x0ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #551 = CDFR |
4641 | | { 552, 4, 1, 4, 829, 0, 0x0ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #552 = CDFTR |
4642 | | { 553, 2, 1, 4, 350, 0, 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #553 = CDGBR |
4643 | | { 554, 4, 1, 4, 350, 0, 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #554 = CDGBRA |
4644 | | { 555, 2, 1, 4, 408, 0, 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #555 = CDGR |
4645 | | { 556, 2, 1, 4, 455, 0, 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #556 = CDGTR |
4646 | | { 557, 4, 1, 4, 455, 0, 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #557 = CDGTRA |
4647 | | { 558, 4, 1, 4, 352, 0, 0x0ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #558 = CDLFBR |
4648 | | { 559, 4, 1, 4, 457, 0, 0x0ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #559 = CDLFTR |
4649 | | { 560, 4, 1, 4, 352, 0, 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #560 = CDLGBR |
4650 | | { 561, 4, 1, 4, 457, 0, 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #561 = CDLGTR |
4651 | | { 562, 5, 1, 6, 471, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #562 = CDPT |
4652 | | { 563, 2, 0, 2, 447, 0|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr }, // Inst #563 = CDR |
4653 | | { 564, 5, 1, 4, 267, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, ImplicitList1, OperandInfo133, -1 ,nullptr }, // Inst #564 = CDS |
4654 | | { 565, 5, 1, 6, 268, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, ImplicitList1, OperandInfo133, -1 ,nullptr }, // Inst #565 = CDSG |
4655 | | { 566, 2, 1, 4, 463, 0, 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #566 = CDSTR |
4656 | | { 567, 5, 1, 6, 267, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, ImplicitList1, OperandInfo133, -1 ,nullptr }, // Inst #567 = CDSY |
4657 | | { 568, 2, 0, 4, 498, 0|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr }, // Inst #568 = CDTR |
4658 | | { 569, 2, 1, 4, 463, 0, 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #569 = CDUTR |
4659 | | { 570, 5, 1, 6, 467, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #570 = CDZT |
4660 | | { 571, 4, 0, 4, 446, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x88ULL, nullptr, ImplicitList1, OperandInfo134, -1 ,nullptr }, // Inst #571 = CE |
4661 | | { 572, 4, 0, 6, 387, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3c88ULL, nullptr, ImplicitList1, OperandInfo134, -1 ,nullptr }, // Inst #572 = CEB |
4662 | | { 573, 2, 0, 4, 388, 0|(1ULL<<MCID::Compare), 0x3c00ULL, nullptr, ImplicitList1, OperandInfo68, -1 ,nullptr }, // Inst #573 = CEBR |
4663 | | { 574, 2, 0, 4, 500, 0|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr }, // Inst #574 = CEDTR |
4664 | | { 575, 2, 1, 4, 350, 0, 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #575 = CEFBR |
4665 | | { 576, 4, 1, 4, 350, 0, 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #576 = CEFBRA |
4666 | | { 577, 2, 1, 4, 408, 0, 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #577 = CEFR |
4667 | | { 578, 2, 1, 4, 350, 0, 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #578 = CEGBR |
4668 | | { 579, 4, 1, 4, 350, 0, 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #579 = CEGBRA |
4669 | | { 580, 2, 1, 4, 408, 0, 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #580 = CEGR |
4670 | | { 581, 4, 1, 4, 826, 0, 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #581 = CELFBR |
4671 | | { 582, 4, 1, 4, 826, 0, 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #582 = CELGBR |
4672 | | { 583, 2, 0, 2, 447, 0|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo68, -1 ,nullptr }, // Inst #583 = CER |
4673 | | { 584, 2, 0, 4, 501, 0|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo69, -1 ,nullptr }, // Inst #584 = CEXTR |
4674 | | { 585, 2, 0, 4, 323, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList4, ImplicitList5, OperandInfo139, -1 ,nullptr }, // Inst #585 = CFC |
4675 | | { 586, 3, 1, 4, 354, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo140, -1 ,nullptr }, // Inst #586 = CFDBR |
4676 | | { 587, 4, 1, 4, 354, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo141, -1 ,nullptr }, // Inst #587 = CFDBRA |
4677 | | { 588, 3, 1, 4, 410, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo140, -1 ,nullptr }, // Inst #588 = CFDR |
4678 | | { 589, 4, 1, 4, 832, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo141, -1 ,nullptr }, // Inst #589 = CFDTR |
4679 | | { 590, 3, 1, 4, 354, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo142, -1 ,nullptr }, // Inst #590 = CFEBR |
4680 | | { 591, 4, 1, 4, 354, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo143, -1 ,nullptr }, // Inst #591 = CFEBRA |
4681 | | { 592, 3, 1, 4, 410, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo142, -1 ,nullptr }, // Inst #592 = CFER |
4682 | | { 593, 2, 0, 6, 212, 0|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo144, -1 ,nullptr }, // Inst #593 = CFI |
4683 | | { 594, 3, 1, 4, 355, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo145, -1 ,nullptr }, // Inst #594 = CFXBR |
4684 | | { 595, 4, 1, 4, 355, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo146, -1 ,nullptr }, // Inst #595 = CFXBRA |
4685 | | { 596, 3, 1, 4, 411, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo145, -1 ,nullptr }, // Inst #596 = CFXR |
4686 | | { 597, 4, 1, 4, 833, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo146, -1 ,nullptr }, // Inst #597 = CFXTR |
4687 | | { 598, 4, 0, 6, 210, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x390cULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr }, // Inst #598 = CG |
4688 | | { 599, 3, 1, 4, 354, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo147, -1 ,nullptr }, // Inst #599 = CGDBR |
4689 | | { 600, 4, 1, 4, 354, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo148, -1 ,nullptr }, // Inst #600 = CGDBRA |
4690 | | { 601, 3, 1, 4, 410, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo147, -1 ,nullptr }, // Inst #601 = CGDR |
4691 | | { 602, 3, 1, 4, 459, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo147, -1 ,nullptr }, // Inst #602 = CGDTR |
4692 | | { 603, 4, 1, 4, 459, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo148, -1 ,nullptr }, // Inst #603 = CGDTRA |
4693 | | { 604, 3, 1, 4, 354, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo149, -1 ,nullptr }, // Inst #604 = CGEBR |
4694 | | { 605, 4, 1, 4, 354, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo150, -1 ,nullptr }, // Inst #605 = CGEBRA |
4695 | | { 606, 3, 1, 4, 410, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo149, -1 ,nullptr }, // Inst #606 = CGER |
4696 | | { 607, 4, 0, 6, 242, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x388cULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr }, // Inst #607 = CGF |
4697 | | { 608, 2, 0, 6, 213, 0|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr }, // Inst #608 = CGFI |
4698 | | { 609, 2, 0, 4, 244, 0|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo151, -1 ,nullptr }, // Inst #609 = CGFR |
4699 | | { 610, 2, 0, 6, 243, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr }, // Inst #610 = CGFRL |
4700 | | { 611, 4, 0, 6, 239, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x384cULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr }, // Inst #611 = CGH |
4701 | | { 612, 2, 0, 4, 213, 0|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr }, // Inst #612 = CGHI |
4702 | | { 613, 2, 0, 6, 240, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr }, // Inst #613 = CGHRL |
4703 | | { 614, 3, 0, 6, 214, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL, nullptr, ImplicitList1, OperandInfo86, -1 ,nullptr }, // Inst #614 = CGHSI |
4704 | | { 615, 5, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #615 = CGIB |
4705 | | { 616, 5, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #616 = CGIBAsm |
4706 | | { 617, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #617 = CGIBAsmE |
4707 | | { 618, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #618 = CGIBAsmH |
4708 | | { 619, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #619 = CGIBAsmHE |
4709 | | { 620, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #620 = CGIBAsmL |
4710 | | { 621, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #621 = CGIBAsmLE |
4711 | | { 622, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #622 = CGIBAsmLH |
4712 | | { 623, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #623 = CGIBAsmNE |
4713 | | { 624, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #624 = CGIBAsmNH |
4714 | | { 625, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #625 = CGIBAsmNHE |
4715 | | { 626, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #626 = CGIBAsmNL |
4716 | | { 627, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #627 = CGIBAsmNLE |
4717 | | { 628, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #628 = CGIBAsmNLH |
4718 | | { 629, 4, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo154, -1 ,nullptr }, // Inst #629 = CGIJ |
4719 | | { 630, 4, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo154, -1 ,nullptr }, // Inst #630 = CGIJAsm |
4720 | | { 631, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #631 = CGIJAsmE |
4721 | | { 632, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #632 = CGIJAsmH |
4722 | | { 633, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #633 = CGIJAsmHE |
4723 | | { 634, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #634 = CGIJAsmL |
4724 | | { 635, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #635 = CGIJAsmLE |
4725 | | { 636, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #636 = CGIJAsmLH |
4726 | | { 637, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #637 = CGIJAsmNE |
4727 | | { 638, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #638 = CGIJAsmNH |
4728 | | { 639, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #639 = CGIJAsmNHE |
4729 | | { 640, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #640 = CGIJAsmNL |
4730 | | { 641, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #641 = CGIJAsmNLE |
4731 | | { 642, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #642 = CGIJAsmNLH |
4732 | | { 643, 3, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #643 = CGIT |
4733 | | { 644, 3, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #644 = CGITAsm |
4734 | | { 645, 2, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #645 = CGITAsmE |
4735 | | { 646, 2, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #646 = CGITAsmH |
4736 | | { 647, 2, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #647 = CGITAsmHE |
4737 | | { 648, 2, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #648 = CGITAsmL |
4738 | | { 649, 2, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #649 = CGITAsmLE |
4739 | | { 650, 2, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #650 = CGITAsmLH |
4740 | | { 651, 2, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #651 = CGITAsmNE |
4741 | | { 652, 2, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #652 = CGITAsmNH |
4742 | | { 653, 2, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #653 = CGITAsmNHE |
4743 | | { 654, 2, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #654 = CGITAsmNL |
4744 | | { 655, 2, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #655 = CGITAsmNLE |
4745 | | { 656, 2, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #656 = CGITAsmNLH |
4746 | | { 657, 2, 0, 4, 215, 0|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #657 = CGR |
4747 | | { 658, 5, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #658 = CGRB |
4748 | | { 659, 5, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #659 = CGRBAsm |
4749 | | { 660, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #660 = CGRBAsmE |
4750 | | { 661, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #661 = CGRBAsmH |
4751 | | { 662, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #662 = CGRBAsmHE |
4752 | | { 663, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #663 = CGRBAsmL |
4753 | | { 664, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #664 = CGRBAsmLE |
4754 | | { 665, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #665 = CGRBAsmLH |
4755 | | { 666, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #666 = CGRBAsmNE |
4756 | | { 667, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #667 = CGRBAsmNH |
4757 | | { 668, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #668 = CGRBAsmNHE |
4758 | | { 669, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #669 = CGRBAsmNL |
4759 | | { 670, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #670 = CGRBAsmNLE |
4760 | | { 671, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #671 = CGRBAsmNLH |
4761 | | { 672, 4, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo157, -1 ,nullptr }, // Inst #672 = CGRJ |
4762 | | { 673, 4, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo157, -1 ,nullptr }, // Inst #673 = CGRJAsm |
4763 | | { 674, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #674 = CGRJAsmE |
4764 | | { 675, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #675 = CGRJAsmH |
4765 | | { 676, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #676 = CGRJAsmHE |
4766 | | { 677, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #677 = CGRJAsmL |
4767 | | { 678, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #678 = CGRJAsmLE |
4768 | | { 679, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #679 = CGRJAsmLH |
4769 | | { 680, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #680 = CGRJAsmNE |
4770 | | { 681, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #681 = CGRJAsmNH |
4771 | | { 682, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #682 = CGRJAsmNHE |
4772 | | { 683, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #683 = CGRJAsmNL |
4773 | | { 684, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #684 = CGRJAsmNLE |
4774 | | { 685, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #685 = CGRJAsmNLH |
4775 | | { 686, 2, 0, 6, 214, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr }, // Inst #686 = CGRL |
4776 | | { 687, 3, 0, 4, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #687 = CGRT |
4777 | | { 688, 3, 0, 4, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #688 = CGRTAsm |
4778 | | { 689, 2, 0, 4, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #689 = CGRTAsmE |
4779 | | { 690, 2, 0, 4, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #690 = CGRTAsmH |
4780 | | { 691, 2, 0, 4, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #691 = CGRTAsmHE |
4781 | | { 692, 2, 0, 4, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #692 = CGRTAsmL |
4782 | | { 693, 2, 0, 4, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #693 = CGRTAsmLE |
4783 | | { 694, 2, 0, 4, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #694 = CGRTAsmLH |
4784 | | { 695, 2, 0, 4, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #695 = CGRTAsmNE |
4785 | | { 696, 2, 0, 4, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #696 = CGRTAsmNH |
4786 | | { 697, 2, 0, 4, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #697 = CGRTAsmNHE |
4787 | | { 698, 2, 0, 4, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #698 = CGRTAsmNL |
4788 | | { 699, 2, 0, 4, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #699 = CGRTAsmNLE |
4789 | | { 700, 2, 0, 4, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #700 = CGRTAsmNLH |
4790 | | { 701, 3, 1, 4, 355, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo158, -1 ,nullptr }, // Inst #701 = CGXBR |
4791 | | { 702, 4, 1, 4, 355, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo159, -1 ,nullptr }, // Inst #702 = CGXBRA |
4792 | | { 703, 3, 1, 4, 411, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo158, -1 ,nullptr }, // Inst #703 = CGXR |
4793 | | { 704, 3, 1, 4, 460, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo158, -1 ,nullptr }, // Inst #704 = CGXTR |
4794 | | { 705, 4, 1, 4, 460, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo159, -1 ,nullptr }, // Inst #705 = CGXTRA |
4795 | | { 706, 4, 0, 4, 237, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3848ULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr }, // Inst #706 = CH |
4796 | | { 707, 4, 0, 6, 217, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x388cULL, nullptr, ImplicitList1, OperandInfo160, -1 ,nullptr }, // Inst #707 = CHF |
4797 | | { 708, 2, 0, 4, 235, 0|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo161, -1 ,nullptr }, // Inst #708 = CHHR |
4798 | | { 709, 3, 0, 6, 241, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL, nullptr, ImplicitList1, OperandInfo86, -1 ,nullptr }, // Inst #709 = CHHSI |
4799 | | { 710, 2, 0, 4, 212, 0|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo144, -1 ,nullptr }, // Inst #710 = CHI |
4800 | | { 711, 2, 0, 4, 236, 0|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo162, -1 ,nullptr }, // Inst #711 = CHLR |
4801 | | { 712, 2, 0, 6, 238, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL, nullptr, ImplicitList1, OperandInfo144, -1 ,nullptr }, // Inst #712 = CHRL |
4802 | | { 713, 3, 0, 6, 218, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL, nullptr, ImplicitList1, OperandInfo86, -1 ,nullptr }, // Inst #713 = CHSI |
4803 | | { 714, 4, 0, 6, 237, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x384cULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr }, // Inst #714 = CHY |
4804 | | { 715, 5, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #715 = CIB |
4805 | | { 716, 5, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #716 = CIBAsm |
4806 | | { 717, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #717 = CIBAsmE |
4807 | | { 718, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #718 = CIBAsmH |
4808 | | { 719, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #719 = CIBAsmHE |
4809 | | { 720, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #720 = CIBAsmL |
4810 | | { 721, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #721 = CIBAsmLE |
4811 | | { 722, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #722 = CIBAsmLH |
4812 | | { 723, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #723 = CIBAsmNE |
4813 | | { 724, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #724 = CIBAsmNH |
4814 | | { 725, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #725 = CIBAsmNHE |
4815 | | { 726, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #726 = CIBAsmNL |
4816 | | { 727, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #727 = CIBAsmNLE |
4817 | | { 728, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #728 = CIBAsmNLH |
4818 | | { 729, 2, 0, 6, 216, 0|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo165, -1 ,nullptr }, // Inst #729 = CIH |
4819 | | { 730, 4, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo166, -1 ,nullptr }, // Inst #730 = CIJ |
4820 | | { 731, 4, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo166, -1 ,nullptr }, // Inst #731 = CIJAsm |
4821 | | { 732, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #732 = CIJAsmE |
4822 | | { 733, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #733 = CIJAsmH |
4823 | | { 734, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #734 = CIJAsmHE |
4824 | | { 735, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #735 = CIJAsmL |
4825 | | { 736, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #736 = CIJAsmLE |
4826 | | { 737, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #737 = CIJAsmLH |
4827 | | { 738, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #738 = CIJAsmNE |
4828 | | { 739, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #739 = CIJAsmNH |
4829 | | { 740, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #740 = CIJAsmNHE |
4830 | | { 741, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #741 = CIJAsmNL |
4831 | | { 742, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #742 = CIJAsmNLE |
4832 | | { 743, 3, 0, 6, 11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #743 = CIJAsmNLH |
4833 | | { 744, 3, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #744 = CIT |
4834 | | { 745, 3, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #745 = CITAsm |
4835 | | { 746, 2, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #746 = CITAsmE |
4836 | | { 747, 2, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #747 = CITAsmH |
4837 | | { 748, 2, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #748 = CITAsmHE |
4838 | | { 749, 2, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #749 = CITAsmL |
4839 | | { 750, 2, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #750 = CITAsmLE |
4840 | | { 751, 2, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #751 = CITAsmLH |
4841 | | { 752, 2, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #752 = CITAsmNE |
4842 | | { 753, 2, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #753 = CITAsmNH |
4843 | | { 754, 2, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #754 = CITAsmNHE |
4844 | | { 755, 2, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #755 = CITAsmNL |
4845 | | { 756, 2, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #756 = CITAsmNLE |
4846 | | { 757, 2, 0, 6, 14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #757 = CITAsmNLH |
4847 | | { 758, 4, 2, 4, 325, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, ImplicitList1, OperandInfo167, -1 ,nullptr }, // Inst #758 = CKSM |
4848 | | { 759, 4, 0, 4, 219, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoa
|