/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/SystemZ/SystemZGenInstrInfo.inc

Source
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Instruction Enum Values and Descriptors                             *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM
namespace llvm {

namespace SystemZ {
  enum {
    PHI = 0,
    INLINEASM = 1,
    CFI_INSTRUCTION = 2,
    EH_LABEL  = 3,
    GC_LABEL  = 4,
    ANNOTATION_LABEL  = 5,
    KILL  = 6,
    EXTRACT_SUBREG  = 7,
    INSERT_SUBREG = 8,
    IMPLICIT_DEF  = 9,
    SUBREG_TO_REG = 10,
    COPY_TO_REGCLASS  = 11,
    DBG_VALUE = 12,
    DBG_LABEL = 13,
    REG_SEQUENCE  = 14,
    COPY  = 15,
    BUNDLE  = 16,
    LIFETIME_START  = 17,
    LIFETIME_END  = 18,
    STACKMAP  = 19,
    FENTRY_CALL = 20,
    PATCHPOINT  = 21,
    LOAD_STACK_GUARD  = 22,
    STATEPOINT  = 23,
    LOCAL_ESCAPE  = 24,
    FAULTING_OP = 25,
    PATCHABLE_OP  = 26,
    PATCHABLE_FUNCTION_ENTER  = 27,
    PATCHABLE_RET = 28,
    PATCHABLE_FUNCTION_EXIT = 29,
    PATCHABLE_TAIL_CALL = 30,
    PATCHABLE_EVENT_CALL  = 31,
    PATCHABLE_TYPED_EVENT_CALL  = 32,
    ICALL_BRANCH_FUNNEL = 33,
    G_ADD = 34,
    G_SUB = 35,
    G_MUL = 36,
    G_SDIV  = 37,
    G_UDIV  = 38,
    G_SREM  = 39,
    G_UREM  = 40,
    G_AND = 41,
    G_OR  = 42,
    G_XOR = 43,
    G_IMPLICIT_DEF  = 44,
    G_PHI = 45,
    G_FRAME_INDEX = 46,
    G_GLOBAL_VALUE  = 47,
    G_EXTRACT = 48,
    G_UNMERGE_VALUES  = 49,
    G_INSERT  = 50,
    G_MERGE_VALUES  = 51,
    G_PTRTOINT  = 52,
    G_INTTOPTR  = 53,
    G_BITCAST = 54,
    G_INTRINSIC_TRUNC = 55,
    G_INTRINSIC_ROUND = 56,
    G_LOAD  = 57,
    G_SEXTLOAD  = 58,
    G_ZEXTLOAD  = 59,
    G_STORE = 60,
    G_ATOMIC_CMPXCHG_WITH_SUCCESS = 61,
    G_ATOMIC_CMPXCHG  = 62,
    G_ATOMICRMW_XCHG  = 63,
    G_ATOMICRMW_ADD = 64,
    G_ATOMICRMW_SUB = 65,
    G_ATOMICRMW_AND = 66,
    G_ATOMICRMW_NAND  = 67,
    G_ATOMICRMW_OR  = 68,
    G_ATOMICRMW_XOR = 69,
    G_ATOMICRMW_MAX = 70,
    G_ATOMICRMW_MIN = 71,
    G_ATOMICRMW_UMAX  = 72,
    G_ATOMICRMW_UMIN  = 73,
    G_BRCOND  = 74,
    G_BRINDIRECT  = 75,
    G_INTRINSIC = 76,
    G_INTRINSIC_W_SIDE_EFFECTS  = 77,
    G_ANYEXT  = 78,
    G_TRUNC = 79,
    G_CONSTANT  = 80,
    G_FCONSTANT = 81,
    G_VASTART = 82,
    G_VAARG = 83,
    G_SEXT  = 84,
    G_ZEXT  = 85,
    G_SHL = 86,
    G_LSHR  = 87,
    G_ASHR  = 88,
    G_ICMP  = 89,
    G_FCMP  = 90,
    G_SELECT  = 91,
    G_UADDO = 92,
    G_UADDE = 93,
    G_USUBO = 94,
    G_USUBE = 95,
    G_SADDO = 96,
    G_SADDE = 97,
    G_SSUBO = 98,
    G_SSUBE = 99,
    G_UMULO = 100,
    G_SMULO = 101,
    G_UMULH = 102,
    G_SMULH = 103,
    G_FADD  = 104,
    G_FSUB  = 105,
    G_FMUL  = 106,
    G_FMA = 107,
    G_FDIV  = 108,
    G_FREM  = 109,
    G_FPOW  = 110,
    G_FEXP  = 111,
    G_FEXP2 = 112,
    G_FLOG  = 113,
    G_FLOG2 = 114,
    G_FNEG  = 115,
    G_FPEXT = 116,
    G_FPTRUNC = 117,
    G_FPTOSI  = 118,
    G_FPTOUI  = 119,
    G_SITOFP  = 120,
    G_UITOFP  = 121,
    G_FABS  = 122,
    G_GEP = 123,
    G_PTR_MASK  = 124,
    G_BR  = 125,
    G_INSERT_VECTOR_ELT = 126,
    G_EXTRACT_VECTOR_ELT  = 127,
    G_SHUFFLE_VECTOR  = 128,
    G_CTTZ  = 129,
    G_CTTZ_ZERO_UNDEF = 130,
    G_CTLZ  = 131,
    G_CTLZ_ZERO_UNDEF = 132,
    G_CTPOP = 133,
    G_BSWAP = 134,
    G_ADDRSPACE_CAST  = 135,
    G_BLOCK_ADDR  = 136,
    ADJCALLSTACKDOWN  = 137,
    ADJCALLSTACKUP  = 138,
    ADJDYNALLOC = 139,
    AEXT128 = 140,
    AFIMux  = 141,
    AHIMux  = 142,
    AHIMuxK = 143,
    ATOMIC_CMP_SWAPW  = 144,
    ATOMIC_LOADW_AFI  = 145,
    ATOMIC_LOADW_AR = 146,
    ATOMIC_LOADW_MAX  = 147,
    ATOMIC_LOADW_MIN  = 148,
    ATOMIC_LOADW_NILH = 149,
    ATOMIC_LOADW_NILHi  = 150,
    ATOMIC_LOADW_NR = 151,
    ATOMIC_LOADW_NRi  = 152,
    ATOMIC_LOADW_OILH = 153,
    ATOMIC_LOADW_OR = 154,
    ATOMIC_LOADW_SR = 155,
    ATOMIC_LOADW_UMAX = 156,
    ATOMIC_LOADW_UMIN = 157,
    ATOMIC_LOADW_XILF = 158,
    ATOMIC_LOADW_XR = 159,
    ATOMIC_LOAD_AFI = 160,
    ATOMIC_LOAD_AGFI  = 161,
    ATOMIC_LOAD_AGHI  = 162,
    ATOMIC_LOAD_AGR = 163,
    ATOMIC_LOAD_AHI = 164,
    ATOMIC_LOAD_AR  = 165,
    ATOMIC_LOAD_MAX_32  = 166,
    ATOMIC_LOAD_MAX_64  = 167,
    ATOMIC_LOAD_MIN_32  = 168,
    ATOMIC_LOAD_MIN_64  = 169,
    ATOMIC_LOAD_NGR = 170,
    ATOMIC_LOAD_NGRi  = 171,
    ATOMIC_LOAD_NIHF64  = 172,
    ATOMIC_LOAD_NIHF64i = 173,
    ATOMIC_LOAD_NIHH64  = 174,
    ATOMIC_LOAD_NIHH64i = 175,
    ATOMIC_LOAD_NIHL64  = 176,
    ATOMIC_LOAD_NIHL64i = 177,
    ATOMIC_LOAD_NILF  = 178,
    ATOMIC_LOAD_NILF64  = 179,
    ATOMIC_LOAD_NILF64i = 180,
    ATOMIC_LOAD_NILFi = 181,
    ATOMIC_LOAD_NILH  = 182,
    ATOMIC_LOAD_NILH64  = 183,
    ATOMIC_LOAD_NILH64i = 184,
    ATOMIC_LOAD_NILHi = 185,
    ATOMIC_LOAD_NILL  = 186,
    ATOMIC_LOAD_NILL64  = 187,
    ATOMIC_LOAD_NILL64i = 188,
    ATOMIC_LOAD_NILLi = 189,
    ATOMIC_LOAD_NR  = 190,
    ATOMIC_LOAD_NRi = 191,
    ATOMIC_LOAD_OGR = 192,
    ATOMIC_LOAD_OIHF64  = 193,
    ATOMIC_LOAD_OIHH64  = 194,
    ATOMIC_LOAD_OIHL64  = 195,
    ATOMIC_LOAD_OILF  = 196,
    ATOMIC_LOAD_OILF64  = 197,
    ATOMIC_LOAD_OILH  = 198,
    ATOMIC_LOAD_OILH64  = 199,
    ATOMIC_LOAD_OILL  = 200,
    ATOMIC_LOAD_OILL64  = 201,
    ATOMIC_LOAD_OR  = 202,
    ATOMIC_LOAD_SGR = 203,
    ATOMIC_LOAD_SR  = 204,
    ATOMIC_LOAD_UMAX_32 = 205,
    ATOMIC_LOAD_UMAX_64 = 206,
    ATOMIC_LOAD_UMIN_32 = 207,
    ATOMIC_LOAD_UMIN_64 = 208,
    ATOMIC_LOAD_XGR = 209,
    ATOMIC_LOAD_XIHF64  = 210,
    ATOMIC_LOAD_XILF  = 211,
    ATOMIC_LOAD_XILF64  = 212,
    ATOMIC_LOAD_XR  = 213,
    ATOMIC_SWAPW  = 214,
    ATOMIC_SWAP_32  = 215,
    ATOMIC_SWAP_64  = 216,
    CFIMux  = 217,
    CGIBCall  = 218,
    CGIBReturn  = 219,
    CGRBCall  = 220,
    CGRBReturn  = 221,
    CHIMux  = 222,
    CIBCall = 223,
    CIBReturn = 224,
    CLCLoop = 225,
    CLCSequence = 226,
    CLFIMux = 227,
    CLGIBCall = 228,
    CLGIBReturn = 229,
    CLGRBCall = 230,
    CLGRBReturn = 231,
    CLIBCall  = 232,
    CLIBReturn  = 233,
    CLMux = 234,
    CLRBCall  = 235,
    CLRBReturn  = 236,
    CLSTLoop  = 237,
    CMux  = 238,
    CRBCall = 239,
    CRBReturn = 240,
    CallBASR  = 241,
    CallBCR = 242,
    CallBR  = 243,
    CallBRASL = 244,
    CallBRCL  = 245,
    CallJG  = 246,
    CondReturn  = 247,
    CondStore16 = 248,
    CondStore16Inv  = 249,
    CondStore16Mux  = 250,
    CondStore16MuxInv = 251,
    CondStore32 = 252,
    CondStore32Inv  = 253,
    CondStore32Mux  = 254,
    CondStore32MuxInv = 255,
    CondStore64 = 256,
    CondStore64Inv  = 257,
    CondStore8  = 258,
    CondStore8Inv = 259,
    CondStore8Mux = 260,
    CondStore8MuxInv  = 261,
    CondStoreF32  = 262,
    CondStoreF32Inv = 263,
    CondStoreF64  = 264,
    CondStoreF64Inv = 265,
    CondTrap  = 266,
    GOT = 267,
    IIFMux  = 268,
    IIHF64  = 269,
    IIHH64  = 270,
    IIHL64  = 271,
    IIHMux  = 272,
    IILF64  = 273,
    IILH64  = 274,
    IILL64  = 275,
    IILMux  = 276,
    L128  = 277,
    LBMux = 278,
    LEFR  = 279,
    LFER  = 280,
    LHIMux  = 281,
    LHMux = 282,
    LLCMux  = 283,
    LLCRMux = 284,
    LLHMux  = 285,
    LLHRMux = 286,
    LMux  = 287,
    LOCHIMux  = 288,
    LOCMux  = 289,
    LOCRMux = 290,
    LRMux = 291,
    LTDBRCompare_VecPseudo  = 292,
    LTEBRCompare_VecPseudo  = 293,
    LTXBRCompare_VecPseudo  = 294,
    LX  = 295,
    MVCLoop = 296,
    MVCSequence = 297,
    MVSTLoop  = 298,
    MemBarrier  = 299,
    NCLoop  = 300,
    NCSequence  = 301,
    NIFMux  = 302,
    NIHF64  = 303,
    NIHH64  = 304,
    NIHL64  = 305,
    NIHMux  = 306,
    NILF64  = 307,
    NILH64  = 308,
    NILL64  = 309,
    NILMux  = 310,
    OCLoop  = 311,
    OCSequence  = 312,
    OIFMux  = 313,
    OIHF64  = 314,
    OIHH64  = 315,
    OIHL64  = 316,
    OIHMux  = 317,
    OILF64  = 318,
    OILH64  = 319,
    OILL64  = 320,
    OILMux  = 321,
    PAIR128 = 322,
    RISBHH  = 323,
    RISBHL  = 324,
    RISBLH  = 325,
    RISBLL  = 326,
    RISBMux = 327,
    Return  = 328,
    SRSTLoop  = 329,
    ST128 = 330,
    STCMux  = 331,
    STHMux  = 332,
    STMux = 333,
    STOCMux = 334,
    STX = 335,
    Select32  = 336,
    Select64  = 337,
    SelectF128  = 338,
    SelectF32 = 339,
    SelectF64 = 340,
    SelectVR128 = 341,
    SelectVR32  = 342,
    SelectVR64  = 343,
    Serialize = 344,
    TBEGIN_nofloat  = 345,
    TLS_GDCALL  = 346,
    TLS_LDCALL  = 347,
    TMHH64  = 348,
    TMHL64  = 349,
    TMHMux  = 350,
    TMLH64  = 351,
    TMLL64  = 352,
    TMLMux  = 353,
    Trap  = 354,
    VL32  = 355,
    VL64  = 356,
    VLR32 = 357,
    VLR64 = 358,
    VLVGP32 = 359,
    VST32 = 360,
    VST64 = 361,
    XCLoop  = 362,
    XCSequence  = 363,
    XIFMux  = 364,
    XIHF64  = 365,
    XILF64  = 366,
    ZEXT128 = 367,
    A = 368,
    AD  = 369,
    ADB = 370,
    ADBR  = 371,
    ADR = 372,
    ADTR  = 373,
    ADTRA = 374,
    AE  = 375,
    AEB = 376,
    AEBR  = 377,
    AER = 378,
    AFI = 379,
    AG  = 380,
    AGF = 381,
    AGFI  = 382,
    AGFR  = 383,
    AGH = 384,
    AGHI  = 385,
    AGHIK = 386,
    AGR = 387,
    AGRK  = 388,
    AGSI  = 389,
    AH  = 390,
    AHHHR = 391,
    AHHLR = 392,
    AHI = 393,
    AHIK  = 394,
    AHY = 395,
    AIH = 396,
    AL  = 397,
    ALC = 398,
    ALCG  = 399,
    ALCGR = 400,
    ALCR  = 401,
    ALFI  = 402,
    ALG = 403,
    ALGF  = 404,
    ALGFI = 405,
    ALGFR = 406,
    ALGHSIK = 407,
    ALGR  = 408,
    ALGRK = 409,
    ALGSI = 410,
    ALHHHR  = 411,
    ALHHLR  = 412,
    ALHSIK  = 413,
    ALR = 414,
    ALRK  = 415,
    ALSI  = 416,
    ALSIH = 417,
    ALSIHN  = 418,
    ALY = 419,
    AP  = 420,
    AR  = 421,
    ARK = 422,
    ASI = 423,
    AU  = 424,
    AUR = 425,
    AW  = 426,
    AWR = 427,
    AXBR  = 428,
    AXR = 429,
    AXTR  = 430,
    AXTRA = 431,
    AY  = 432,
    B = 433,
    BAKR  = 434,
    BAL = 435,
    BALR  = 436,
    BAS = 437,
    BASR  = 438,
    BASSM = 439,
    BAsmE = 440,
    BAsmH = 441,
    BAsmHE  = 442,
    BAsmL = 443,
    BAsmLE  = 444,
    BAsmLH  = 445,
    BAsmM = 446,
    BAsmNE  = 447,
    BAsmNH  = 448,
    BAsmNHE = 449,
    BAsmNL  = 450,
    BAsmNLE = 451,
    BAsmNLH = 452,
    BAsmNM  = 453,
    BAsmNO  = 454,
    BAsmNP  = 455,
    BAsmNZ  = 456,
    BAsmO = 457,
    BAsmP = 458,
    BAsmZ = 459,
    BC  = 460,
    BCAsm = 461,
    BCR = 462,
    BCRAsm  = 463,
    BCT = 464,
    BCTG  = 465,
    BCTGR = 466,
    BCTR  = 467,
    BI  = 468,
    BIAsmE  = 469,
    BIAsmH  = 470,
    BIAsmHE = 471,
    BIAsmL  = 472,
    BIAsmLE = 473,
    BIAsmLH = 474,
    BIAsmM  = 475,
    BIAsmNE = 476,
    BIAsmNH = 477,
    BIAsmNHE  = 478,
    BIAsmNL = 479,
    BIAsmNLE  = 480,
    BIAsmNLH  = 481,
    BIAsmNM = 482,
    BIAsmNO = 483,
    BIAsmNP = 484,
    BIAsmNZ = 485,
    BIAsmO  = 486,
    BIAsmP  = 487,
    BIAsmZ  = 488,
    BIC = 489,
    BICAsm  = 490,
    BPP = 491,
    BPRP  = 492,
    BR  = 493,
    BRAS  = 494,
    BRASL = 495,
    BRAsmE  = 496,
    BRAsmH  = 497,
    BRAsmHE = 498,
    BRAsmL  = 499,
    BRAsmLE = 500,
    BRAsmLH = 501,
    BRAsmM  = 502,
    BRAsmNE = 503,
    BRAsmNH = 504,
    BRAsmNHE  = 505,
    BRAsmNL = 506,
    BRAsmNLE  = 507,
    BRAsmNLH  = 508,
    BRAsmNM = 509,
    BRAsmNO = 510,
    BRAsmNP = 511,
    BRAsmNZ = 512,
    BRAsmO  = 513,
    BRAsmP  = 514,
    BRAsmZ  = 515,
    BRC = 516,
    BRCAsm  = 517,
    BRCL  = 518,
    BRCLAsm = 519,
    BRCT  = 520,
    BRCTG = 521,
    BRCTH = 522,
    BRXH  = 523,
    BRXHG = 524,
    BRXLE = 525,
    BRXLG = 526,
    BSA = 527,
    BSG = 528,
    BSM = 529,
    BXH = 530,
    BXHG  = 531,
    BXLE  = 532,
    BXLEG = 533,
    C = 534,
    CD  = 535,
    CDB = 536,
    CDBR  = 537,
    CDFBR = 538,
    CDFBRA  = 539,
    CDFR  = 540,
    CDFTR = 541,
    CDGBR = 542,
    CDGBRA  = 543,
    CDGR  = 544,
    CDGTR = 545,
    CDGTRA  = 546,
    CDLFBR  = 547,
    CDLFTR  = 548,
    CDLGBR  = 549,
    CDLGTR  = 550,
    CDPT  = 551,
    CDR = 552,
    CDS = 553,
    CDSG  = 554,
    CDSTR = 555,
    CDSY  = 556,
    CDTR  = 557,
    CDUTR = 558,
    CDZT  = 559,
    CE  = 560,
    CEB = 561,
    CEBR  = 562,
    CEDTR = 563,
    CEFBR = 564,
    CEFBRA  = 565,
    CEFR  = 566,
    CEGBR = 567,
    CEGBRA  = 568,
    CEGR  = 569,
    CELFBR  = 570,
    CELGBR  = 571,
    CER = 572,
    CEXTR = 573,
    CFC = 574,
    CFDBR = 575,
    CFDBRA  = 576,
    CFDR  = 577,
    CFDTR = 578,
    CFEBR = 579,
    CFEBRA  = 580,
    CFER  = 581,
    CFI = 582,
    CFXBR = 583,
    CFXBRA  = 584,
    CFXR  = 585,
    CFXTR = 586,
    CG  = 587,
    CGDBR = 588,
    CGDBRA  = 589,
    CGDR  = 590,
    CGDTR = 591,
    CGDTRA  = 592,
    CGEBR = 593,
    CGEBRA  = 594,
    CGER  = 595,
    CGF = 596,
    CGFI  = 597,
    CGFR  = 598,
    CGFRL = 599,
    CGH = 600,
    CGHI  = 601,
    CGHRL = 602,
    CGHSI = 603,
    CGIB  = 604,
    CGIBAsm = 605,
    CGIBAsmE  = 606,
    CGIBAsmH  = 607,
    CGIBAsmHE = 608,
    CGIBAsmL  = 609,
    CGIBAsmLE = 610,
    CGIBAsmLH = 611,
    CGIBAsmNE = 612,
    CGIBAsmNH = 613,
    CGIBAsmNHE  = 614,
    CGIBAsmNL = 615,
    CGIBAsmNLE  = 616,
    CGIBAsmNLH  = 617,
    CGIJ  = 618,
    CGIJAsm = 619,
    CGIJAsmE  = 620,
    CGIJAsmH  = 621,
    CGIJAsmHE = 622,
    CGIJAsmL  = 623,
    CGIJAsmLE = 624,
    CGIJAsmLH = 625,
    CGIJAsmNE = 626,
    CGIJAsmNH = 627,
    CGIJAsmNHE  = 628,
    CGIJAsmNL = 629,
    CGIJAsmNLE  = 630,
    CGIJAsmNLH  = 631,
    CGIT  = 632,
    CGITAsm = 633,
    CGITAsmE  = 634,
    CGITAsmH  = 635,
    CGITAsmHE = 636,
    CGITAsmL  = 637,
    CGITAsmLE = 638,
    CGITAsmLH = 639,
    CGITAsmNE = 640,
    CGITAsmNH = 641,
    CGITAsmNHE  = 642,
    CGITAsmNL = 643,
    CGITAsmNLE  = 644,
    CGITAsmNLH  = 645,
    CGR = 646,
    CGRB  = 647,
    CGRBAsm = 648,
    CGRBAsmE  = 649,
    CGRBAsmH  = 650,
    CGRBAsmHE = 651,
    CGRBAsmL  = 652,
    CGRBAsmLE = 653,
    CGRBAsmLH = 654,
    CGRBAsmNE = 655,
    CGRBAsmNH = 656,
    CGRBAsmNHE  = 657,
    CGRBAsmNL = 658,
    CGRBAsmNLE  = 659,
    CGRBAsmNLH  = 660,
    CGRJ  = 661,
    CGRJAsm = 662,
    CGRJAsmE  = 663,
    CGRJAsmH  = 664,
    CGRJAsmHE = 665,
    CGRJAsmL  = 666,
    CGRJAsmLE = 667,
    CGRJAsmLH = 668,
    CGRJAsmNE = 669,
    CGRJAsmNH = 670,
    CGRJAsmNHE  = 671,
    CGRJAsmNL = 672,
    CGRJAsmNLE  = 673,
    CGRJAsmNLH  = 674,
    CGRL  = 675,
    CGRT  = 676,
    CGRTAsm = 677,
    CGRTAsmE  = 678,
    CGRTAsmH  = 679,
    CGRTAsmHE = 680,
    CGRTAsmL  = 681,
    CGRTAsmLE = 682,
    CGRTAsmLH = 683,
    CGRTAsmNE = 684,
    CGRTAsmNH = 685,
    CGRTAsmNHE  = 686,
    CGRTAsmNL = 687,
    CGRTAsmNLE  = 688,
    CGRTAsmNLH  = 689,
    CGXBR = 690,
    CGXBRA  = 691,
    CGXR  = 692,
    CGXTR = 693,
    CGXTRA  = 694,
    CH  = 695,
    CHF = 696,
    CHHR  = 697,
    CHHSI = 698,
    CHI = 699,
    CHLR  = 700,
    CHRL  = 701,
    CHSI  = 702,
    CHY = 703,
    CIB = 704,
    CIBAsm  = 705,
    CIBAsmE = 706,
    CIBAsmH = 707,
    CIBAsmHE  = 708,
    CIBAsmL = 709,
    CIBAsmLE  = 710,
    CIBAsmLH  = 711,
    CIBAsmNE  = 712,
    CIBAsmNH  = 713,
    CIBAsmNHE = 714,
    CIBAsmNL  = 715,
    CIBAsmNLE = 716,
    CIBAsmNLH = 717,
    CIH = 718,
    CIJ = 719,
    CIJAsm  = 720,
    CIJAsmE = 721,
    CIJAsmH = 722,
    CIJAsmHE  = 723,
    CIJAsmL = 724,
    CIJAsmLE  = 725,
    CIJAsmLH  = 726,
    CIJAsmNE  = 727,
    CIJAsmNH  = 728,
    CIJAsmNHE = 729,
    CIJAsmNL  = 730,
    CIJAsmNLE = 731,
    CIJAsmNLH = 732,
    CIT = 733,
    CITAsm  = 734,
    CITAsmE = 735,
    CITAsmH = 736,
    CITAsmHE  = 737,
    CITAsmL = 738,
    CITAsmLE  = 739,
    CITAsmLH  = 740,
    CITAsmNE  = 741,
    CITAsmNH  = 742,
    CITAsmNHE = 743,
    CITAsmNL  = 744,
    CITAsmNLE = 745,
    CITAsmNLH = 746,
    CKSM  = 747,
    CL  = 748,
    CLC = 749,
    CLCL  = 750,
    CLCLE = 751,
    CLCLU = 752,
    CLFDBR  = 753,
    CLFDTR  = 754,
    CLFEBR  = 755,
    CLFHSI  = 756,
    CLFI  = 757,
    CLFIT = 758,
    CLFITAsm  = 759,
    CLFITAsmE = 760,
    CLFITAsmH = 761,
    CLFITAsmHE  = 762,
    CLFITAsmL = 763,
    CLFITAsmLE  = 764,
    CLFITAsmLH  = 765,
    CLFITAsmNE  = 766,
    CLFITAsmNH  = 767,
    CLFITAsmNHE = 768,
    CLFITAsmNL  = 769,
    CLFITAsmNLE = 770,
    CLFITAsmNLH = 771,
    CLFXBR  = 772,
    CLFXTR  = 773,
    CLG = 774,
    CLGDBR  = 775,
    CLGDTR  = 776,
    CLGEBR  = 777,
    CLGF  = 778,
    CLGFI = 779,
    CLGFR = 780,
    CLGFRL  = 781,
    CLGHRL  = 782,
    CLGHSI  = 783,
    CLGIB = 784,
    CLGIBAsm  = 785,
    CLGIBAsmE = 786,
    CLGIBAsmH = 787,
    CLGIBAsmHE  = 788,
    CLGIBAsmL = 789,
    CLGIBAsmLE  = 790,
    CLGIBAsmLH  = 791,
    CLGIBAsmNE  = 792,
    CLGIBAsmNH  = 793,
    CLGIBAsmNHE = 794,
    CLGIBAsmNL  = 795,
    CLGIBAsmNLE = 796,
    CLGIBAsmNLH = 797,
    CLGIJ = 798,
    CLGIJAsm  = 799,
    CLGIJAsmE = 800,
    CLGIJAsmH = 801,
    CLGIJAsmHE  = 802,
    CLGIJAsmL = 803,
    CLGIJAsmLE  = 804,
    CLGIJAsmLH  = 805,
    CLGIJAsmNE  = 806,
    CLGIJAsmNH  = 807,
    CLGIJAsmNHE = 808,
    CLGIJAsmNL  = 809,
    CLGIJAsmNLE = 810,
    CLGIJAsmNLH = 811,
    CLGIT = 812,
    CLGITAsm  = 813,
    CLGITAsmE = 814,
    CLGITAsmH = 815,
    CLGITAsmHE  = 816,
    CLGITAsmL = 817,
    CLGITAsmLE  = 818,
    CLGITAsmLH  = 819,
    CLGITAsmNE  = 820,
    CLGITAsmNH  = 821,
    CLGITAsmNHE = 822,
    CLGITAsmNL  = 823,
    CLGITAsmNLE = 824,
    CLGITAsmNLH = 825,
    CLGR  = 826,
    CLGRB = 827,
    CLGRBAsm  = 828,
    CLGRBAsmE = 829,
    CLGRBAsmH = 830,
    CLGRBAsmHE  = 831,
    CLGRBAsmL = 832,
    CLGRBAsmLE  = 833,
    CLGRBAsmLH  = 834,
    CLGRBAsmNE  = 835,
    CLGRBAsmNH  = 836,
    CLGRBAsmNHE = 837,
    CLGRBAsmNL  = 838,
    CLGRBAsmNLE = 839,
    CLGRBAsmNLH = 840,
    CLGRJ = 841,
    CLGRJAsm  = 842,
    CLGRJAsmE = 843,
    CLGRJAsmH = 844,
    CLGRJAsmHE  = 845,
    CLGRJAsmL = 846,
    CLGRJAsmLE  = 847,
    CLGRJAsmLH  = 848,
    CLGRJAsmNE  = 849,
    CLGRJAsmNH  = 850,
    CLGRJAsmNHE = 851,
    CLGRJAsmNL  = 852,
    CLGRJAsmNLE = 853,
    CLGRJAsmNLH = 854,
    CLGRL = 855,
    CLGRT = 856,
    CLGRTAsm  = 857,
    CLGRTAsmE = 858,
    CLGRTAsmH = 859,
    CLGRTAsmHE  = 860,
    CLGRTAsmL = 861,
    CLGRTAsmLE  = 862,
    CLGRTAsmLH  = 863,
    CLGRTAsmNE  = 864,
    CLGRTAsmNH  = 865,
    CLGRTAsmNHE = 866,
    CLGRTAsmNL  = 867,
    CLGRTAsmNLE = 868,
    CLGRTAsmNLH = 869,
    CLGT  = 870,
    CLGTAsm = 871,
    CLGTAsmE  = 872,
    CLGTAsmH  = 873,
    CLGTAsmHE = 874,
    CLGTAsmL  = 875,
    CLGTAsmLE = 876,
    CLGTAsmLH = 877,
    CLGTAsmNE = 878,
    CLGTAsmNH = 879,
    CLGTAsmNHE  = 880,
    CLGTAsmNL = 881,
    CLGTAsmNLE  = 882,
    CLGTAsmNLH  = 883,
    CLGXBR  = 884,
    CLGXTR  = 885,
    CLHF  = 886,
    CLHHR = 887,
    CLHHSI  = 888,
    CLHLR = 889,
    CLHRL = 890,
    CLI = 891,
    CLIB  = 892,
    CLIBAsm = 893,
    CLIBAsmE  = 894,
    CLIBAsmH  = 895,
    CLIBAsmHE = 896,
    CLIBAsmL  = 897,
    CLIBAsmLE = 898,
    CLIBAsmLH = 899,
    CLIBAsmNE = 900,
    CLIBAsmNH = 901,
    CLIBAsmNHE  = 902,
    CLIBAsmNL = 903,
    CLIBAsmNLE  = 904,
    CLIBAsmNLH  = 905,
    CLIH  = 906,
    CLIJ  = 907,
    CLIJAsm = 908,
    CLIJAsmE  = 909,
    CLIJAsmH  = 910,
    CLIJAsmHE = 911,
    CLIJAsmL  = 912,
    CLIJAsmLE = 913,
    CLIJAsmLH = 914,
    CLIJAsmNE = 915,
    CLIJAsmNH = 916,
    CLIJAsmNHE  = 917,
    CLIJAsmNL = 918,
    CLIJAsmNLE  = 919,
    CLIJAsmNLH  = 920,
    CLIY  = 921,
    CLM = 922,
    CLMH  = 923,
    CLMY  = 924,
    CLR = 925,
    CLRB  = 926,
    CLRBAsm = 927,
    CLRBAsmE  = 928,
    CLRBAsmH  = 929,
    CLRBAsmHE = 930,
    CLRBAsmL  = 931,
    CLRBAsmLE = 932,
    CLRBAsmLH = 933,
    CLRBAsmNE = 934,
    CLRBAsmNH = 935,
    CLRBAsmNHE  = 936,
    CLRBAsmNL = 937,
    CLRBAsmNLE  = 938,
    CLRBAsmNLH  = 939,
    CLRJ  = 940,
    CLRJAsm = 941,
    CLRJAsmE  = 942,
    CLRJAsmH  = 943,
    CLRJAsmHE = 944,
    CLRJAsmL  = 945,
    CLRJAsmLE = 946,
    CLRJAsmLH = 947,
    CLRJAsmNE = 948,
    CLRJAsmNH = 949,
    CLRJAsmNHE  = 950,
    CLRJAsmNL = 951,
    CLRJAsmNLE  = 952,
    CLRJAsmNLH  = 953,
    CLRL  = 954,
    CLRT  = 955,
    CLRTAsm = 956,
    CLRTAsmE  = 957,
    CLRTAsmH  = 958,
    CLRTAsmHE = 959,
    CLRTAsmL  = 960,
    CLRTAsmLE = 961,
    CLRTAsmLH = 962,
    CLRTAsmNE = 963,
    CLRTAsmNH = 964,
    CLRTAsmNHE  = 965,
    CLRTAsmNL = 966,
    CLRTAsmNLE  = 967,
    CLRTAsmNLH  = 968,
    CLST  = 969,
    CLT = 970,
    CLTAsm  = 971,
    CLTAsmE = 972,
    CLTAsmH = 973,
    CLTAsmHE  = 974,
    CLTAsmL = 975,
    CLTAsmLE  = 976,
    CLTAsmLH  = 977,
    CLTAsmNE  = 978,
    CLTAsmNH  = 979,
    CLTAsmNHE = 980,
    CLTAsmNL  = 981,
    CLTAsmNLE = 982,
    CLTAsmNLH = 983,
    CLY = 984,
    CMPSC = 985,
    CP  = 986,
    CPDT  = 987,
    CPSDRdd = 988,
    CPSDRds = 989,
    CPSDRsd = 990,
    CPSDRss = 991,
    CPXT  = 992,
    CPYA  = 993,
    CR  = 994,
    CRB = 995,
    CRBAsm  = 996,
    CRBAsmE = 997,
    CRBAsmH = 998,
    CRBAsmHE  = 999,
    CRBAsmL = 1000,
    CRBAsmLE  = 1001,
    CRBAsmLH  = 1002,
    CRBAsmNE  = 1003,
    CRBAsmNH  = 1004,
    CRBAsmNHE = 1005,
    CRBAsmNL  = 1006,
    CRBAsmNLE = 1007,
    CRBAsmNLH = 1008,
    CRDTE = 1009,
    CRDTEOpt  = 1010,
    CRJ = 1011,
    CRJAsm  = 1012,
    CRJAsmE = 1013,
    CRJAsmH = 1014,
    CRJAsmHE  = 1015,
    CRJAsmL = 1016,
    CRJAsmLE  = 1017,
    CRJAsmLH  = 1018,
    CRJAsmNE  = 1019,
    CRJAsmNH  = 1020,
    CRJAsmNHE = 1021,
    CRJAsmNL  = 1022,
    CRJAsmNLE = 1023,
    CRJAsmNLH = 1024,
    CRL = 1025,
    CRT = 1026,
    CRTAsm  = 1027,
    CRTAsmE = 1028,
    CRTAsmH = 1029,
    CRTAsmHE  = 1030,
    CRTAsmL = 1031,
    CRTAsmLE  = 1032,
    CRTAsmLH  = 1033,
    CRTAsmNE  = 1034,
    CRTAsmNH  = 1035,
    CRTAsmNHE = 1036,
    CRTAsmNL  = 1037,
    CRTAsmNLE = 1038,
    CRTAsmNLH = 1039,
    CS  = 1040,
    CSCH  = 1041,
    CSDTR = 1042,
    CSG = 1043,
    CSP = 1044,
    CSPG  = 1045,
    CSST  = 1046,
    CSXTR = 1047,
    CSY = 1048,
    CU12  = 1049,
    CU12Opt = 1050,
    CU14  = 1051,
    CU14Opt = 1052,
    CU21  = 1053,
    CU21Opt = 1054,
    CU24  = 1055,
    CU24Opt = 1056,
    CU41  = 1057,
    CU42  = 1058,
    CUDTR = 1059,
    CUSE  = 1060,
    CUTFU = 1061,
    CUTFUOpt  = 1062,
    CUUTF = 1063,
    CUUTFOpt  = 1064,
    CUXTR = 1065,
    CVB = 1066,
    CVBG  = 1067,
    CVBY  = 1068,
    CVD = 1069,
    CVDG  = 1070,
    CVDY  = 1071,
    CXBR  = 1072,
    CXFBR = 1073,
    CXFBRA  = 1074,
    CXFR  = 1075,
    CXFTR = 1076,
    CXGBR = 1077,
    CXGBRA  = 1078,
    CXGR  = 1079,
    CXGTR = 1080,
    CXGTRA  = 1081,
    CXLFBR  = 1082,
    CXLFTR  = 1083,
    CXLGBR  = 1084,
    CXLGTR  = 1085,
    CXPT  = 1086,
    CXR = 1087,
    CXSTR = 1088,
    CXTR  = 1089,
    CXUTR = 1090,
    CXZT  = 1091,
    CY  = 1092,
    CZDT  = 1093,
    CZXT  = 1094,
    D = 1095,
    DD  = 1096,
    DDB = 1097,
    DDBR  = 1098,
    DDR = 1099,
    DDTR  = 1100,
    DDTRA = 1101,
    DE  = 1102,
    DEB = 1103,
    DEBR  = 1104,
    DER = 1105,
    DIAG  = 1106,
    DIDBR = 1107,
    DIEBR = 1108,
    DL  = 1109,
    DLG = 1110,
    DLGR  = 1111,
    DLR = 1112,
    DP  = 1113,
    DR  = 1114,
    DSG = 1115,
    DSGF  = 1116,
    DSGFR = 1117,
    DSGR  = 1118,
    DXBR  = 1119,
    DXR = 1120,
    DXTR  = 1121,
    DXTRA = 1122,
    EAR = 1123,
    ECAG  = 1124,
    ECCTR = 1125,
    ECPGA = 1126,
    ECTG  = 1127,
    ED  = 1128,
    EDMK  = 1129,
    EEDTR = 1130,
    EEXTR = 1131,
    EFPC  = 1132,
    EPAIR = 1133,
    EPAR  = 1134,
    EPCTR = 1135,
    EPSW  = 1136,
    EREG  = 1137,
    EREGG = 1138,
    ESAIR = 1139,
    ESAR  = 1140,
    ESDTR = 1141,
    ESEA  = 1142,
    ESTA  = 1143,
    ESXTR = 1144,
    ETND  = 1145,
    EX  = 1146,
    EXRL  = 1147,
    FIDBR = 1148,
    FIDBRA  = 1149,
    FIDR  = 1150,
    FIDTR = 1151,
    FIEBR = 1152,
    FIEBRA  = 1153,
    FIER  = 1154,
    FIXBR = 1155,
    FIXBRA  = 1156,
    FIXR  = 1157,
    FIXTR = 1158,
    FLOGR = 1159,
    HDR = 1160,
    HER = 1161,
    HSCH  = 1162,
    IAC = 1163,
    IC  = 1164,
    IC32  = 1165,
    IC32Y = 1166,
    ICM = 1167,
    ICMH  = 1168,
    ICMY  = 1169,
    ICY = 1170,
    IDTE  = 1171,
    IDTEOpt = 1172,
    IEDTR = 1173,
    IEXTR = 1174,
    IIHF  = 1175,
    IIHH  = 1176,
    IIHL  = 1177,
    IILF  = 1178,
    IILH  = 1179,
    IILL  = 1180,
    IPK = 1181,
    IPM = 1182,
    IPTE  = 1183,
    IPTEOpt = 1184,
    IPTEOptOpt  = 1185,
    IRBM  = 1186,
    ISKE  = 1187,
    IVSK  = 1188,
    InsnE = 1189,
    InsnRI  = 1190,
    InsnRIE = 1191,
    InsnRIL = 1192,
    InsnRILU  = 1193,
    InsnRIS = 1194,
    InsnRR  = 1195,
    InsnRRE = 1196,
    InsnRRF = 1197,
    InsnRRS = 1198,
    InsnRS  = 1199,
    InsnRSE = 1200,
    InsnRSI = 1201,
    InsnRSY = 1202,
    InsnRX  = 1203,
    InsnRXE = 1204,
    InsnRXF = 1205,
    InsnRXY = 1206,
    InsnS = 1207,
    InsnSI  = 1208,
    InsnSIL = 1209,
    InsnSIY = 1210,
    InsnSS  = 1211,
    InsnSSE = 1212,
    InsnSSF = 1213,
    J = 1214,
    JAsmE = 1215,
    JAsmH = 1216,
    JAsmHE  = 1217,
    JAsmL = 1218,
    JAsmLE  = 1219,
    JAsmLH  = 1220,
    JAsmM = 1221,
    JAsmNE  = 1222,
    JAsmNH  = 1223,
    JAsmNHE = 1224,
    JAsmNL  = 1225,
    JAsmNLE = 1226,
    JAsmNLH = 1227,
    JAsmNM  = 1228,
    JAsmNO  = 1229,
    JAsmNP  = 1230,
    JAsmNZ  = 1231,
    JAsmO = 1232,
    JAsmP = 1233,
    JAsmZ = 1234,
    JG  = 1235,
    JGAsmE  = 1236,
    JGAsmH  = 1237,
    JGAsmHE = 1238,
    JGAsmL  = 1239,
    JGAsmLE = 1240,
    JGAsmLH = 1241,
    JGAsmM  = 1242,
    JGAsmNE = 1243,
    JGAsmNH = 1244,
    JGAsmNHE  = 1245,
    JGAsmNL = 1246,
    JGAsmNLE  = 1247,
    JGAsmNLH  = 1248,
    JGAsmNM = 1249,
    JGAsmNO = 1250,
    JGAsmNP = 1251,
    JGAsmNZ = 1252,
    JGAsmO  = 1253,
    JGAsmP  = 1254,
    JGAsmZ  = 1255,
    KDB = 1256,
    KDBR  = 1257,
    KDTR  = 1258,
    KEB = 1259,
    KEBR  = 1260,
    KIMD  = 1261,
    KLMD  = 1262,
    KM  = 1263,
    KMA = 1264,
    KMAC  = 1265,
    KMC = 1266,
    KMCTR = 1267,
    KMF = 1268,
    KMO = 1269,
    KXBR  = 1270,
    KXTR  = 1271,
    L = 1272,
    LA  = 1273,
    LAA = 1274,
    LAAG  = 1275,
    LAAL  = 1276,
    LAALG = 1277,
    LAE = 1278,
    LAEY  = 1279,
    LAM = 1280,
    LAMY  = 1281,
    LAN = 1282,
    LANG  = 1283,
    LAO = 1284,
    LAOG  = 1285,
    LARL  = 1286,
    LASP  = 1287,
    LAT = 1288,
    LAX = 1289,
    LAXG  = 1290,
    LAY = 1291,
    LB  = 1292,
    LBH = 1293,
    LBR = 1294,
    LCBB  = 1295,
    LCCTL = 1296,
    LCDBR = 1297,
    LCDFR = 1298,
    LCDFR_32  = 1299,
    LCDR  = 1300,
    LCEBR = 1301,
    LCER  = 1302,
    LCGFR = 1303,
    LCGR  = 1304,
    LCR = 1305,
    LCTL  = 1306,
    LCTLG = 1307,
    LCXBR = 1308,
    LCXR  = 1309,
    LD  = 1310,
    LDE = 1311,
    LDE32 = 1312,
    LDEB  = 1313,
    LDEBR = 1314,
    LDER  = 1315,
    LDETR = 1316,
    LDGR  = 1317,
    LDR = 1318,
    LDR32 = 1319,
    LDXBR = 1320,
    LDXBRA  = 1321,
    LDXR  = 1322,
    LDXTR = 1323,
    LDY = 1324,
    LE  = 1325,
    LEDBR = 1326,
    LEDBRA  = 1327,
    LEDR  = 1328,
    LEDTR = 1329,
    LER = 1330,
    LEXBR = 1331,
    LEXBRA  = 1332,
    LEXR  = 1333,
    LEY = 1334,
    LFAS  = 1335,
    LFH = 1336,
    LFHAT = 1337,
    LFPC  = 1338,
    LG  = 1339,
    LGAT  = 1340,
    LGB = 1341,
    LGBR  = 1342,
    LGDR  = 1343,
    LGF = 1344,
    LGFI  = 1345,
    LGFR  = 1346,
    LGFRL = 1347,
    LGG = 1348,
    LGH = 1349,
    LGHI  = 1350,
    LGHR  = 1351,
    LGHRL = 1352,
    LGR = 1353,
    LGRL  = 1354,
    LGSC  = 1355,
    LH  = 1356,
    LHH = 1357,
    LHI = 1358,
    LHR = 1359,
    LHRL  = 1360,
    LHY = 1361,
    LLC = 1362,
    LLCH  = 1363,
    LLCR  = 1364,
    LLGC  = 1365,
    LLGCR = 1366,
    LLGF  = 1367,
    LLGFAT  = 1368,
    LLGFR = 1369,
    LLGFRL  = 1370,
    LLGFSG  = 1371,
    LLGH  = 1372,
    LLGHR = 1373,
    LLGHRL  = 1374,
    LLGT  = 1375,
    LLGTAT  = 1376,
    LLGTR = 1377,
    LLH = 1378,
    LLHH  = 1379,
    LLHR  = 1380,
    LLHRL = 1381,
    LLIHF = 1382,
    LLIHH = 1383,
    LLIHL = 1384,
    LLILF = 1385,
    LLILH = 1386,
    LLILL = 1387,
    LLZRGF  = 1388,
    LM  = 1389,
    LMD = 1390,
    LMG = 1391,
    LMH = 1392,
    LMY = 1393,
    LNDBR = 1394,
    LNDFR = 1395,
    LNDFR_32  = 1396,
    LNDR  = 1397,
    LNEBR = 1398,
    LNER  = 1399,
    LNGFR = 1400,
    LNGR  = 1401,
    LNR = 1402,
    LNXBR = 1403,
    LNXR  = 1404,
    LOC = 1405,
    LOCAsm  = 1406,
    LOCAsmE = 1407,
    LOCAsmH = 1408,
    LOCAsmHE  = 1409,
    LOCAsmL = 1410,
    LOCAsmLE  = 1411,
    LOCAsmLH  = 1412,
    LOCAsmM = 1413,
    LOCAsmNE  = 1414,
    LOCAsmNH  = 1415,
    LOCAsmNHE = 1416,
    LOCAsmNL  = 1417,
    LOCAsmNLE = 1418,
    LOCAsmNLH = 1419,
    LOCAsmNM  = 1420,
    LOCAsmNO  = 1421,
    LOCAsmNP  = 1422,
    LOCAsmNZ  = 1423,
    LOCAsmO = 1424,
    LOCAsmP = 1425,
    LOCAsmZ = 1426,
    LOCFH = 1427,
    LOCFHAsm  = 1428,
    LOCFHAsmE = 1429,
    LOCFHAsmH = 1430,
    LOCFHAsmHE  = 1431,
    LOCFHAsmL = 1432,
    LOCFHAsmLE  = 1433,
    LOCFHAsmLH  = 1434,
    LOCFHAsmM = 1435,
    LOCFHAsmNE  = 1436,
    LOCFHAsmNH  = 1437,
    LOCFHAsmNHE = 1438,
    LOCFHAsmNL  = 1439,
    LOCFHAsmNLE = 1440,
    LOCFHAsmNLH = 1441,
    LOCFHAsmNM  = 1442,
    LOCFHAsmNO  = 1443,
    LOCFHAsmNP  = 1444,
    LOCFHAsmNZ  = 1445,
    LOCFHAsmO = 1446,
    LOCFHAsmP = 1447,
    LOCFHAsmZ = 1448,
    LOCFHR  = 1449,
    LOCFHRAsm = 1450,
    LOCFHRAsmE  = 1451,
    LOCFHRAsmH  = 1452,
    LOCFHRAsmHE = 1453,
    LOCFHRAsmL  = 1454,
    LOCFHRAsmLE = 1455,
    LOCFHRAsmLH = 1456,
    LOCFHRAsmM  = 1457,
    LOCFHRAsmNE = 1458,
    LOCFHRAsmNH = 1459,
    LOCFHRAsmNHE  = 1460,
    LOCFHRAsmNL = 1461,
    LOCFHRAsmNLE  = 1462,
    LOCFHRAsmNLH  = 1463,
    LOCFHRAsmNM = 1464,
    LOCFHRAsmNO = 1465,
    LOCFHRAsmNP = 1466,
    LOCFHRAsmNZ = 1467,
    LOCFHRAsmO  = 1468,
    LOCFHRAsmP  = 1469,
    LOCFHRAsmZ  = 1470,
    LOCG  = 1471,
    LOCGAsm = 1472,
    LOCGAsmE  = 1473,
    LOCGAsmH  = 1474,
    LOCGAsmHE = 1475,
    LOCGAsmL  = 1476,
    LOCGAsmLE = 1477,
    LOCGAsmLH = 1478,
    LOCGAsmM  = 1479,
    LOCGAsmNE = 1480,
    LOCGAsmNH = 1481,
    LOCGAsmNHE  = 1482,
    LOCGAsmNL = 1483,
    LOCGAsmNLE  = 1484,
    LOCGAsmNLH  = 1485,
    LOCGAsmNM = 1486,
    LOCGAsmNO = 1487,
    LOCGAsmNP = 1488,
    LOCGAsmNZ = 1489,
    LOCGAsmO  = 1490,
    LOCGAsmP  = 1491,
    LOCGAsmZ  = 1492,
    LOCGHI  = 1493,
    LOCGHIAsm = 1494,
    LOCGHIAsmE  = 1495,
    LOCGHIAsmH  = 1496,
    LOCGHIAsmHE = 1497,
    LOCGHIAsmL  = 1498,
    LOCGHIAsmLE = 1499,
    LOCGHIAsmLH = 1500,
    LOCGHIAsmM  = 1501,
    LOCGHIAsmNE = 1502,
    LOCGHIAsmNH = 1503,
    LOCGHIAsmNHE  = 1504,
    LOCGHIAsmNL = 1505,
    LOCGHIAsmNLE  = 1506,
    LOCGHIAsmNLH  = 1507,
    LOCGHIAsmNM = 1508,
    LOCGHIAsmNO = 1509,
    LOCGHIAsmNP = 1510,
    LOCGHIAsmNZ = 1511,
    LOCGHIAsmO  = 1512,
    LOCGHIAsmP  = 1513,
    LOCGHIAsmZ  = 1514,
    LOCGR = 1515,
    LOCGRAsm  = 1516,
    LOCGRAsmE = 1517,
    LOCGRAsmH = 1518,
    LOCGRAsmHE  = 1519,
    LOCGRAsmL = 1520,
    LOCGRAsmLE  = 1521,
    LOCGRAsmLH  = 1522,
    LOCGRAsmM = 1523,
    LOCGRAsmNE  = 1524,
    LOCGRAsmNH  = 1525,
    LOCGRAsmNHE = 1526,
    LOCGRAsmNL  = 1527,
    LOCGRAsmNLE = 1528,
    LOCGRAsmNLH = 1529,
    LOCGRAsmNM  = 1530,
    LOCGRAsmNO  = 1531,
    LOCGRAsmNP  = 1532,
    LOCGRAsmNZ  = 1533,
    LOCGRAsmO = 1534,
    LOCGRAsmP = 1535,
    LOCGRAsmZ = 1536,
    LOCHHI  = 1537,
    LOCHHIAsm = 1538,
    LOCHHIAsmE  = 1539,
    LOCHHIAsmH  = 1540,
    LOCHHIAsmHE = 1541,
    LOCHHIAsmL  = 1542,
    LOCHHIAsmLE = 1543,
    LOCHHIAsmLH = 1544,
    LOCHHIAsmM  = 1545,
    LOCHHIAsmNE = 1546,
    LOCHHIAsmNH = 1547,
    LOCHHIAsmNHE  = 1548,
    LOCHHIAsmNL = 1549,
    LOCHHIAsmNLE  = 1550,
    LOCHHIAsmNLH  = 1551,
    LOCHHIAsmNM = 1552,
    LOCHHIAsmNO = 1553,
    LOCHHIAsmNP = 1554,
    LOCHHIAsmNZ = 1555,
    LOCHHIAsmO  = 1556,
    LOCHHIAsmP  = 1557,
    LOCHHIAsmZ  = 1558,
    LOCHI = 1559,
    LOCHIAsm  = 1560,
    LOCHIAsmE = 1561,
    LOCHIAsmH = 1562,
    LOCHIAsmHE  = 1563,
    LOCHIAsmL = 1564,
    LOCHIAsmLE  = 1565,
    LOCHIAsmLH  = 1566,
    LOCHIAsmM = 1567,
    LOCHIAsmNE  = 1568,
    LOCHIAsmNH  = 1569,
    LOCHIAsmNHE = 1570,
    LOCHIAsmNL  = 1571,
    LOCHIAsmNLE = 1572,
    LOCHIAsmNLH = 1573,
    LOCHIAsmNM  = 1574,
    LOCHIAsmNO  = 1575,
    LOCHIAsmNP  = 1576,
    LOCHIAsmNZ  = 1577,
    LOCHIAsmO = 1578,
    LOCHIAsmP = 1579,
    LOCHIAsmZ = 1580,
    LOCR  = 1581,
    LOCRAsm = 1582,
    LOCRAsmE  = 1583,
    LOCRAsmH  = 1584,
    LOCRAsmHE = 1585,
    LOCRAsmL  = 1586,
    LOCRAsmLE = 1587,
    LOCRAsmLH = 1588,
    LOCRAsmM  = 1589,
    LOCRAsmNE = 1590,
    LOCRAsmNH = 1591,
    LOCRAsmNHE  = 1592,
    LOCRAsmNL = 1593,
    LOCRAsmNLE  = 1594,
    LOCRAsmNLH  = 1595,
    LOCRAsmNM = 1596,
    LOCRAsmNO = 1597,
    LOCRAsmNP = 1598,
    LOCRAsmNZ = 1599,
    LOCRAsmO  = 1600,
    LOCRAsmP  = 1601,
    LOCRAsmZ  = 1602,
    LPCTL = 1603,
    LPD = 1604,
    LPDBR = 1605,
    LPDFR = 1606,
    LPDFR_32  = 1607,
    LPDG  = 1608,
    LPDR  = 1609,
    LPEBR = 1610,
    LPER  = 1611,
    LPGFR = 1612,
    LPGR  = 1613,
    LPP = 1614,
    LPQ = 1615,
    LPR = 1616,
    LPSW  = 1617,
    LPSWE = 1618,
    LPTEA = 1619,
    LPXBR = 1620,
    LPXR  = 1621,
    LR  = 1622,
    LRA = 1623,
    LRAG  = 1624,
    LRAY  = 1625,
    LRDR  = 1626,
    LRER  = 1627,
    LRL = 1628,
    LRV = 1629,
    LRVG  = 1630,
    LRVGR = 1631,
    LRVH  = 1632,
    LRVR  = 1633,
    LSCTL = 1634,
    LT  = 1635,
    LTDBR = 1636,
    LTDBRCompare  = 1637,
    LTDR  = 1638,
    LTDTR = 1639,
    LTEBR = 1640,
    LTEBRCompare  = 1641,
    LTER  = 1642,
    LTG = 1643,
    LTGF  = 1644,
    LTGFR = 1645,
    LTGR  = 1646,
    LTR = 1647,
    LTXBR = 1648,
    LTXBRCompare  = 1649,
    LTXR  = 1650,
    LTXTR = 1651,
    LURA  = 1652,
    LURAG = 1653,
    LXD = 1654,
    LXDB  = 1655,
    LXDBR = 1656,
    LXDR  = 1657,
    LXDTR = 1658,
    LXE = 1659,
    LXEB  = 1660,
    LXEBR = 1661,
    LXER  = 1662,
    LXR = 1663,
    LY  = 1664,
    LZDR  = 1665,
    LZER  = 1666,
    LZRF  = 1667,
    LZRG  = 1668,
    LZXR  = 1669,
    M = 1670,
    MAD = 1671,
    MADB  = 1672,
    MADBR = 1673,
    MADR  = 1674,
    MAE = 1675,
    MAEB  = 1676,
    MAEBR = 1677,
    MAER  = 1678,
    MAY = 1679,
    MAYH  = 1680,
    MAYHR = 1681,
    MAYL  = 1682,
    MAYLR = 1683,
    MAYR  = 1684,
    MC  = 1685,
    MD  = 1686,
    MDB = 1687,
    MDBR  = 1688,
    MDE = 1689,
    MDEB  = 1690,
    MDEBR = 1691,
    MDER  = 1692,
    MDR = 1693,
    MDTR  = 1694,
    MDTRA = 1695,
    ME  = 1696,
    MEE = 1697,
    MEEB  = 1698,
    MEEBR = 1699,
    MEER  = 1700,
    MER = 1701,
    MFY = 1702,
    MG  = 1703,
    MGH = 1704,
    MGHI  = 1705,
    MGRK  = 1706,
    MH  = 1707,
    MHI = 1708,
    MHY = 1709,
    ML  = 1710,
    MLG = 1711,
    MLGR  = 1712,
    MLR = 1713,
    MP  = 1714,
    MR  = 1715,
    MS  = 1716,
    MSC = 1717,
    MSCH  = 1718,
    MSD = 1719,
    MSDB  = 1720,
    MSDBR = 1721,
    MSDR  = 1722,
    MSE = 1723,
    MSEB  = 1724,
    MSEBR = 1725,
    MSER  = 1726,
    MSFI  = 1727,
    MSG = 1728,
    MSGC  = 1729,
    MSGF  = 1730,
    MSGFI = 1731,
    MSGFR = 1732,
    MSGR  = 1733,
    MSGRKC  = 1734,
    MSR = 1735,
    MSRKC = 1736,
    MSTA  = 1737,
    MSY = 1738,
    MVC = 1739,
    MVCDK = 1740,
    MVCIN = 1741,
    MVCK  = 1742,
    MVCL  = 1743,
    MVCLE = 1744,
    MVCLU = 1745,
    MVCOS = 1746,
    MVCP  = 1747,
    MVCS  = 1748,
    MVCSK = 1749,
    MVGHI = 1750,
    MVHHI = 1751,
    MVHI  = 1752,
    MVI = 1753,
    MVIY  = 1754,
    MVN = 1755,
    MVO = 1756,
    MVPG  = 1757,
    MVST  = 1758,
    MVZ = 1759,
    MXBR  = 1760,
    MXD = 1761,
    MXDB  = 1762,
    MXDBR = 1763,
    MXDR  = 1764,
    MXR = 1765,
    MXTR  = 1766,
    MXTRA = 1767,
    MY  = 1768,
    MYH = 1769,
    MYHR  = 1770,
    MYL = 1771,
    MYLR  = 1772,
    MYR = 1773,
    N = 1774,
    NC  = 1775,
    NG  = 1776,
    NGR = 1777,
    NGRK  = 1778,
    NI  = 1779,
    NIAI  = 1780,
    NIHF  = 1781,
    NIHH  = 1782,
    NIHL  = 1783,
    NILF  = 1784,
    NILH  = 1785,
    NILL  = 1786,
    NIY = 1787,
    NR  = 1788,
    NRK = 1789,
    NTSTG = 1790,
    NY  = 1791,
    O = 1792,
    OC  = 1793,
    OG  = 1794,
    OGR = 1795,
    OGRK  = 1796,
    OI  = 1797,
    OIHF  = 1798,
    OIHH  = 1799,
    OIHL  = 1800,
    OILF  = 1801,
    OILH  = 1802,
    OILL  = 1803,
    OIY = 1804,
    OR  = 1805,
    ORK = 1806,
    OY  = 1807,
    PACK  = 1808,
    PALB  = 1809,
    PC  = 1810,
    PCC = 1811,
    PCKMO = 1812,
    PFD = 1813,
    PFDRL = 1814,
    PFMF  = 1815,
    PFPO  = 1816,
    PGIN  = 1817,
    PGOUT = 1818,
    PKA = 1819,
    PKU = 1820,
    PLO = 1821,
    POPCNT  = 1822,
    PPA = 1823,
    PPNO  = 1824,
    PR  = 1825,
    PRNO  = 1826,
    PT  = 1827,
    PTF = 1828,
    PTFF  = 1829,
    PTI = 1830,
    PTLB  = 1831,
    QADTR = 1832,
    QAXTR = 1833,
    QCTRI = 1834,
    QSI = 1835,
    RCHP  = 1836,
    RISBG = 1837,
    RISBG32 = 1838,
    RISBGN  = 1839,
    RISBHG  = 1840,
    RISBLG  = 1841,
    RLL = 1842,
    RLLG  = 1843,
    RNSBG = 1844,
    ROSBG = 1845,
    RP  = 1846,
    RRBE  = 1847,
    RRBM  = 1848,
    RRDTR = 1849,
    RRXTR = 1850,
    RSCH  = 1851,
    RXSBG = 1852,
    S = 1853,
    SAC = 1854,
    SACF  = 1855,
    SAL = 1856,
    SAM24 = 1857,
    SAM31 = 1858,
    SAM64 = 1859,
    SAR = 1860,
    SCCTR = 1861,
    SCHM  = 1862,
    SCK = 1863,
    SCKC  = 1864,
    SCKPF = 1865,
    SD  = 1866,
    SDB = 1867,
    SDBR  = 1868,
    SDR = 1869,
    SDTR  = 1870,
    SDTRA = 1871,
    SE  = 1872,
    SEB = 1873,
    SEBR  = 1874,
    SER = 1875,
    SFASR = 1876,
    SFPC  = 1877,
    SG  = 1878,
    SGF = 1879,
    SGFR  = 1880,
    SGH = 1881,
    SGR = 1882,
    SGRK  = 1883,
    SH  = 1884,
    SHHHR = 1885,
    SHHLR = 1886,
    SHY = 1887,
    SIE = 1888,
    SIGA  = 1889,
    SIGP  = 1890,
    SL  = 1891,
    SLA = 1892,
    SLAG  = 1893,
    SLAK  = 1894,
    SLB = 1895,
    SLBG  = 1896,
    SLBGR = 1897,
    SLBR  = 1898,
    SLDA  = 1899,
    SLDL  = 1900,
    SLDT  = 1901,
    SLFI  = 1902,
    SLG = 1903,
    SLGF  = 1904,
    SLGFI = 1905,
    SLGFR = 1906,
    SLGR  = 1907,
    SLGRK = 1908,
    SLHHHR  = 1909,
    SLHHLR  = 1910,
    SLL = 1911,
    SLLG  = 1912,
    SLLK  = 1913,
    SLR = 1914,
    SLRK  = 1915,
    SLXT  = 1916,
    SLY = 1917,
    SP  = 1918,
    SPCTR = 1919,
    SPKA  = 1920,
    SPM = 1921,
    SPT = 1922,
    SPX = 1923,
    SQD = 1924,
    SQDB  = 1925,
    SQDBR = 1926,
    SQDR  = 1927,
    SQE = 1928,
    SQEB  = 1929,
    SQEBR = 1930,
    SQER  = 1931,
    SQXBR = 1932,
    SQXR  = 1933,
    SR  = 1934,
    SRA = 1935,
    SRAG  = 1936,
    SRAK  = 1937,
    SRDA  = 1938,
    SRDL  = 1939,
    SRDT  = 1940,
    SRK = 1941,
    SRL = 1942,
    SRLG  = 1943,
    SRLK  = 1944,
    SRNM  = 1945,
    SRNMB = 1946,
    SRNMT = 1947,
    SRP = 1948,
    SRST  = 1949,
    SRSTU = 1950,
    SRXT  = 1951,
    SSAIR = 1952,
    SSAR  = 1953,
    SSCH  = 1954,
    SSKE  = 1955,
    SSKEOpt = 1956,
    SSM = 1957,
    ST  = 1958,
    STAM  = 1959,
    STAMY = 1960,
    STAP  = 1961,
    STC = 1962,
    STCH  = 1963,
    STCK  = 1964,
    STCKC = 1965,
    STCKE = 1966,
    STCKF = 1967,
    STCM  = 1968,
    STCMH = 1969,
    STCMY = 1970,
    STCPS = 1971,
    STCRW = 1972,
    STCTG = 1973,
    STCTL = 1974,
    STCY  = 1975,
    STD = 1976,
    STDY  = 1977,
    STE = 1978,
    STEY  = 1979,
    STFH  = 1980,
    STFL  = 1981,
    STFLE = 1982,
    STFPC = 1983,
    STG = 1984,
    STGRL = 1985,
    STGSC = 1986,
    STH = 1987,
    STHH  = 1988,
    STHRL = 1989,
    STHY  = 1990,
    STIDP = 1991,
    STM = 1992,
    STMG  = 1993,
    STMH  = 1994,
    STMY  = 1995,
    STNSM = 1996,
    STOC  = 1997,
    STOCAsm = 1998,
    STOCAsmE  = 1999,
    STOCAsmH  = 2000,
    STOCAsmHE = 2001,
    STOCAsmL  = 2002,
    STOCAsmLE = 2003,
    STOCAsmLH = 2004,
    STOCAsmM  = 2005,
    STOCAsmNE = 2006,
    STOCAsmNH = 2007,
    STOCAsmNHE  = 2008,
    STOCAsmNL = 2009,
    STOCAsmNLE  = 2010,
    STOCAsmNLH  = 2011,
    STOCAsmNM = 2012,
    STOCAsmNO = 2013,
    STOCAsmNP = 2014,
    STOCAsmNZ = 2015,
    STOCAsmO  = 2016,
    STOCAsmP  = 2017,
    STOCAsmZ  = 2018,
    STOCFH  = 2019,
    STOCFHAsm = 2020,
    STOCFHAsmE  = 2021,
    STOCFHAsmH  = 2022,
    STOCFHAsmHE = 2023,
    STOCFHAsmL  = 2024,
    STOCFHAsmLE = 2025,
    STOCFHAsmLH = 2026,
    STOCFHAsmM  = 2027,
    STOCFHAsmNE = 2028,
    STOCFHAsmNH = 2029,
    STOCFHAsmNHE  = 2030,
    STOCFHAsmNL = 2031,
    STOCFHAsmNLE  = 2032,
    STOCFHAsmNLH  = 2033,
    STOCFHAsmNM = 2034,
    STOCFHAsmNO = 2035,
    STOCFHAsmNP = 2036,
    STOCFHAsmNZ = 2037,
    STOCFHAsmO  = 2038,
    STOCFHAsmP  = 2039,
    STOCFHAsmZ  = 2040,
    STOCG = 2041,
    STOCGAsm  = 2042,
    STOCGAsmE = 2043,
    STOCGAsmH = 2044,
    STOCGAsmHE  = 2045,
    STOCGAsmL = 2046,
    STOCGAsmLE  = 2047,
    STOCGAsmLH  = 2048,
    STOCGAsmM = 2049,
    STOCGAsmNE  = 2050,
    STOCGAsmNH  = 2051,
    STOCGAsmNHE = 2052,
    STOCGAsmNL  = 2053,
    STOCGAsmNLE = 2054,
    STOCGAsmNLH = 2055,
    STOCGAsmNM  = 2056,
    STOCGAsmNO  = 2057,
    STOCGAsmNP  = 2058,
    STOCGAsmNZ  = 2059,
    STOCGAsmO = 2060,
    STOCGAsmP = 2061,
    STOCGAsmZ = 2062,
    STOSM = 2063,
    STPQ  = 2064,
    STPT  = 2065,
    STPX  = 2066,
    STRAG = 2067,
    STRL  = 2068,
    STRV  = 2069,
    STRVG = 2070,
    STRVH = 2071,
    STSCH = 2072,
    STSI  = 2073,
    STURA = 2074,
    STURG = 2075,
    STY = 2076,
    SU  = 2077,
    SUR = 2078,
    SVC = 2079,
    SW  = 2080,
    SWR = 2081,
    SXBR  = 2082,
    SXR = 2083,
    SXTR  = 2084,
    SXTRA = 2085,
    SY  = 2086,
    TABORT  = 2087,
    TAM = 2088,
    TAR = 2089,
    TB  = 2090,
    TBDR  = 2091,
    TBEDR = 2092,
    TBEGIN  = 2093,
    TBEGINC = 2094,
    TCDB  = 2095,
    TCEB  = 2096,
    TCXB  = 2097,
    TDCDT = 2098,
    TDCET = 2099,
    TDCXT = 2100,
    TDGDT = 2101,
    TDGET = 2102,
    TDGXT = 2103,
    TEND  = 2104,
    THDER = 2105,
    THDR  = 2106,
    TM  = 2107,
    TMHH  = 2108,
    TMHL  = 2109,
    TMLH  = 2110,
    TMLL  = 2111,
    TMY = 2112,
    TP  = 2113,
    TPI = 2114,
    TPROT = 2115,
    TR  = 2116,
    TRACE = 2117,
    TRACG = 2118,
    TRAP2 = 2119,
    TRAP4 = 2120,
    TRE = 2121,
    TROO  = 2122,
    TROOOpt = 2123,
    TROT  = 2124,
    TROTOpt = 2125,
    TRT = 2126,
    TRTE  = 2127,
    TRTEOpt = 2128,
    TRTO  = 2129,
    TRTOOpt = 2130,
    TRTR  = 2131,
    TRTRE = 2132,
    TRTREOpt  = 2133,
    TRTT  = 2134,
    TRTTOpt = 2135,
    TS  = 2136,
    TSCH  = 2137,
    UNPK  = 2138,
    UNPKA = 2139,
    UNPKU = 2140,
    UPT = 2141,
    VA  = 2142,
    VAB = 2143,
    VAC = 2144,
    VACC  = 2145,
    VACCB = 2146,
    VACCC = 2147,
    VACCCQ  = 2148,
    VACCF = 2149,
    VACCG = 2150,
    VACCH = 2151,
    VACCQ = 2152,
    VACQ  = 2153,
    VAF = 2154,
    VAG = 2155,
    VAH = 2156,
    VAP = 2157,
    VAQ = 2158,
    VAVG  = 2159,
    VAVGB = 2160,
    VAVGF = 2161,
    VAVGG = 2162,
    VAVGH = 2163,
    VAVGL = 2164,
    VAVGLB  = 2165,
    VAVGLF  = 2166,
    VAVGLG  = 2167,
    VAVGLH  = 2168,
    VBPERM  = 2169,
    VCDG  = 2170,
    VCDGB = 2171,
    VCDLG = 2172,
    VCDLGB  = 2173,
    VCEQ  = 2174,
    VCEQB = 2175,
    VCEQBS  = 2176,
    VCEQF = 2177,
    VCEQFS  = 2178,
    VCEQG = 2179,
    VCEQGS  = 2180,
    VCEQH = 2181,
    VCEQHS  = 2182,
    VCGD  = 2183,
    VCGDB = 2184,
    VCH = 2185,
    VCHB  = 2186,
    VCHBS = 2187,
    VCHF  = 2188,
    VCHFS = 2189,
    VCHG  = 2190,
    VCHGS = 2191,
    VCHH  = 2192,
    VCHHS = 2193,
    VCHL  = 2194,
    VCHLB = 2195,
    VCHLBS  = 2196,
    VCHLF = 2197,
    VCHLFS  = 2198,
    VCHLG = 2199,
    VCHLGS  = 2200,
    VCHLH = 2201,
    VCHLHS  = 2202,
    VCKSM = 2203,
    VCLGD = 2204,
    VCLGDB  = 2205,
    VCLZ  = 2206,
    VCLZB = 2207,
    VCLZF = 2208,
    VCLZG = 2209,
    VCLZH = 2210,
    VCP = 2211,
    VCTZ  = 2212,
    VCTZB = 2213,
    VCTZF = 2214,
    VCTZG = 2215,
    VCTZH = 2216,
    VCVB  = 2217,
    VCVBG = 2218,
    VCVD  = 2219,
    VCVDG = 2220,
    VDP = 2221,
    VEC = 2222,
    VECB  = 2223,
    VECF  = 2224,
    VECG  = 2225,
    VECH  = 2226,
    VECL  = 2227,
    VECLB = 2228,
    VECLF = 2229,
    VECLG = 2230,
    VECLH = 2231,
    VERIM = 2232,
    VERIMB  = 2233,
    VERIMF  = 2234,
    VERIMG  = 2235,
    VERIMH  = 2236,
    VERLL = 2237,
    VERLLB  = 2238,
    VERLLF  = 2239,
    VERLLG  = 2240,
    VERLLH  = 2241,
    VERLLV  = 2242,
    VERLLVB = 2243,
    VERLLVF = 2244,
    VERLLVG = 2245,
    VERLLVH = 2246,
    VESL  = 2247,
    VESLB = 2248,
    VESLF = 2249,
    VESLG = 2250,
    VESLH = 2251,
    VESLV = 2252,
    VESLVB  = 2253,
    VESLVF  = 2254,
    VESLVG  = 2255,
    VESLVH  = 2256,
    VESRA = 2257,
    VESRAB  = 2258,
    VESRAF  = 2259,
    VESRAG  = 2260,
    VESRAH  = 2261,
    VESRAV  = 2262,
    VESRAVB = 2263,
    VESRAVF = 2264,
    VESRAVG = 2265,
    VESRAVH = 2266,
    VESRL = 2267,
    VESRLB  = 2268,
    VESRLF  = 2269,
    VESRLG  = 2270,
    VESRLH  = 2271,
    VESRLV  = 2272,
    VESRLVB = 2273,
    VESRLVF = 2274,
    VESRLVG = 2275,
    VESRLVH = 2276,
    VFA = 2277,
    VFADB = 2278,
    VFAE  = 2279,
    VFAEB = 2280,
    VFAEBS  = 2281,
    VFAEF = 2282,
    VFAEFS  = 2283,
    VFAEH = 2284,
    VFAEHS  = 2285,
    VFAEZB  = 2286,
    VFAEZBS = 2287,
    VFAEZF  = 2288,
    VFAEZFS = 2289,
    VFAEZH  = 2290,
    VFAEZHS = 2291,
    VFASB = 2292,
    VFCE  = 2293,
    VFCEDB  = 2294,
    VFCEDBS = 2295,
    VFCESB  = 2296,
    VFCESBS = 2297,
    VFCH  = 2298,
    VFCHDB  = 2299,
    VFCHDBS = 2300,
    VFCHE = 2301,
    VFCHEDB = 2302,
    VFCHEDBS  = 2303,
    VFCHESB = 2304,
    VFCHESBS  = 2305,
    VFCHSB  = 2306,
    VFCHSBS = 2307,
    VFD = 2308,
    VFDDB = 2309,
    VFDSB = 2310,
    VFEE  = 2311,
    VFEEB = 2312,
    VFEEBS  = 2313,
    VFEEF = 2314,
    VFEEFS  = 2315,
    VFEEH = 2316,
    VFEEHS  = 2317,
    VFEEZB  = 2318,
    VFEEZBS = 2319,
    VFEEZF  = 2320,
    VFEEZFS = 2321,
    VFEEZH  = 2322,
    VFEEZHS = 2323,
    VFENE = 2324,
    VFENEB  = 2325,
    VFENEBS = 2326,
    VFENEF  = 2327,
    VFENEFS = 2328,
    VFENEH  = 2329,
    VFENEHS = 2330,
    VFENEZB = 2331,
    VFENEZBS  = 2332,
    VFENEZF = 2333,
    VFENEZFS  = 2334,
    VFENEZH = 2335,
    VFENEZHS  = 2336,
    VFI = 2337,
    VFIDB = 2338,
    VFISB = 2339,
    VFKEDB  = 2340,
    VFKEDBS = 2341,
    VFKESB  = 2342,
    VFKESBS = 2343,
    VFKHDB  = 2344,
    VFKHDBS = 2345,
    VFKHEDB = 2346,
    VFKHEDBS  = 2347,
    VFKHESB = 2348,
    VFKHESBS  = 2349,
    VFKHSB  = 2350,
    VFKHSBS = 2351,
    VFLCDB  = 2352,
    VFLCSB  = 2353,
    VFLL  = 2354,
    VFLLS = 2355,
    VFLNDB  = 2356,
    VFLNSB  = 2357,
    VFLPDB  = 2358,
    VFLPSB  = 2359,
    VFLR  = 2360,
    VFLRD = 2361,
    VFM = 2362,
    VFMA  = 2363,
    VFMADB  = 2364,
    VFMASB  = 2365,
    VFMAX = 2366,
    VFMAXDB = 2367,
    VFMAXSB = 2368,
    VFMDB = 2369,
    VFMIN = 2370,
    VFMINDB = 2371,
    VFMINSB = 2372,
    VFMS  = 2373,
    VFMSB = 2374,
    VFMSDB  = 2375,
    VFMSSB  = 2376,
    VFNMA = 2377,
    VFNMADB = 2378,
    VFNMASB = 2379,
    VFNMS = 2380,
    VFNMSDB = 2381,
    VFNMSSB = 2382,
    VFPSO = 2383,
    VFPSODB = 2384,
    VFPSOSB = 2385,
    VFS = 2386,
    VFSDB = 2387,
    VFSQ  = 2388,
    VFSQDB  = 2389,
    VFSQSB  = 2390,
    VFSSB = 2391,
    VFTCI = 2392,
    VFTCIDB = 2393,
    VFTCISB = 2394,
    VGBM  = 2395,
    VGEF  = 2396,
    VGEG  = 2397,
    VGFM  = 2398,
    VGFMA = 2399,
    VGFMAB  = 2400,
    VGFMAF  = 2401,
    VGFMAG  = 2402,
    VGFMAH  = 2403,
    VGFMB = 2404,
    VGFMF = 2405,
    VGFMG = 2406,
    VGFMH = 2407,
    VGM = 2408,
    VGMB  = 2409,
    VGMF  = 2410,
    VGMG  = 2411,
    VGMH  = 2412,
    VISTR = 2413,
    VISTRB  = 2414,
    VISTRBS = 2415,
    VISTRF  = 2416,
    VISTRFS = 2417,
    VISTRH  = 2418,
    VISTRHS = 2419,
    VL  = 2420,
    VLBB  = 2421,
    VLC = 2422,
    VLCB  = 2423,
    VLCF  = 2424,
    VLCG  = 2425,
    VLCH  = 2426,
    VLDE  = 2427,
    VLDEB = 2428,
    VLEB  = 2429,
    VLED  = 2430,
    VLEDB = 2431,
    VLEF  = 2432,
    VLEG  = 2433,
    VLEH  = 2434,
    VLEIB = 2435,
    VLEIF = 2436,
    VLEIG = 2437,
    VLEIH = 2438,
    VLGV  = 2439,
    VLGVB = 2440,
    VLGVF = 2441,
    VLGVG = 2442,
    VLGVH = 2443,
    VLIP  = 2444,
    VLL = 2445,
    VLLEZ = 2446,
    VLLEZB  = 2447,
    VLLEZF  = 2448,
    VLLEZG  = 2449,
    VLLEZH  = 2450,
    VLLEZLF = 2451,
    VLM = 2452,
    VLP = 2453,
    VLPB  = 2454,
    VLPF  = 2455,
    VLPG  = 2456,
    VLPH  = 2457,
    VLR = 2458,
    VLREP = 2459,
    VLREPB  = 2460,
    VLREPF  = 2461,
    VLREPG  = 2462,
    VLREPH  = 2463,
    VLRL  = 2464,
    VLRLR = 2465,
    VLVG  = 2466,
    VLVGB = 2467,
    VLVGF = 2468,
    VLVGG = 2469,
    VLVGH = 2470,
    VLVGP = 2471,
    VMAE  = 2472,
    VMAEB = 2473,
    VMAEF = 2474,
    VMAEH = 2475,
    VMAH  = 2476,
    VMAHB = 2477,
    VMAHF = 2478,
    VMAHH = 2479,
    VMAL  = 2480,
    VMALB = 2481,
    VMALE = 2482,
    VMALEB  = 2483,
    VMALEF  = 2484,
    VMALEH  = 2485,
    VMALF = 2486,
    VMALH = 2487,
    VMALHB  = 2488,
    VMALHF  = 2489,
    VMALHH  = 2490,
    VMALHW  = 2491,
    VMALO = 2492,
    VMALOB  = 2493,
    VMALOF  = 2494,
    VMALOH  = 2495,
    VMAO  = 2496,
    VMAOB = 2497,
    VMAOF = 2498,
    VMAOH = 2499,
    VME = 2500,
    VMEB  = 2501,
    VMEF  = 2502,
    VMEH  = 2503,
    VMH = 2504,
    VMHB  = 2505,
    VMHF  = 2506,
    VMHH  = 2507,
    VML = 2508,
    VMLB  = 2509,
    VMLE  = 2510,
    VMLEB = 2511,
    VMLEF = 2512,
    VMLEH = 2513,
    VMLF  = 2514,
    VMLH  = 2515,
    VMLHB = 2516,
    VMLHF = 2517,
    VMLHH = 2518,
    VMLHW = 2519,
    VMLO  = 2520,
    VMLOB = 2521,
    VMLOF = 2522,
    VMLOH = 2523,
    VMN = 2524,
    VMNB  = 2525,
    VMNF  = 2526,
    VMNG  = 2527,
    VMNH  = 2528,
    VMNL  = 2529,
    VMNLB = 2530,
    VMNLF = 2531,
    VMNLG = 2532,
    VMNLH = 2533,
    VMO = 2534,
    VMOB  = 2535,
    VMOF  = 2536,
    VMOH  = 2537,
    VMP = 2538,
    VMRH  = 2539,
    VMRHB = 2540,
    VMRHF = 2541,
    VMRHG = 2542,
    VMRHH = 2543,
    VMRL  = 2544,
    VMRLB = 2545,
    VMRLF = 2546,
    VMRLG = 2547,
    VMRLH = 2548,
    VMSL  = 2549,
    VMSLG = 2550,
    VMSP  = 2551,
    VMX = 2552,
    VMXB  = 2553,
    VMXF  = 2554,
    VMXG  = 2555,
    VMXH  = 2556,
    VMXL  = 2557,
    VMXLB = 2558,
    VMXLF = 2559,
    VMXLG = 2560,
    VMXLH = 2561,
    VN  = 2562,
    VNC = 2563,
    VNN = 2564,
    VNO = 2565,
    VNX = 2566,
    VO  = 2567,
    VOC = 2568,
    VONE  = 2569,
    VPDI  = 2570,
    VPERM = 2571,
    VPK = 2572,
    VPKF  = 2573,
    VPKG  = 2574,
    VPKH  = 2575,
    VPKLS = 2576,
    VPKLSF  = 2577,
    VPKLSFS = 2578,
    VPKLSG  = 2579,
    VPKLSGS = 2580,
    VPKLSH  = 2581,
    VPKLSHS = 2582,
    VPKS  = 2583,
    VPKSF = 2584,
    VPKSFS  = 2585,
    VPKSG = 2586,
    VPKSGS  = 2587,
    VPKSH = 2588,
    VPKSHS  = 2589,
    VPKZ  = 2590,
    VPOPCT  = 2591,
    VPOPCTB = 2592,
    VPOPCTF = 2593,
    VPOPCTG = 2594,
    VPOPCTH = 2595,
    VPSOP = 2596,
    VREP  = 2597,
    VREPB = 2598,
    VREPF = 2599,
    VREPG = 2600,
    VREPH = 2601,
    VREPI = 2602,
    VREPIB  = 2603,
    VREPIF  = 2604,
    VREPIG  = 2605,
    VREPIH  = 2606,
    VRP = 2607,
    VS  = 2608,
    VSB = 2609,
    VSBCBI  = 2610,
    VSBCBIQ = 2611,
    VSBI  = 2612,
    VSBIQ = 2613,
    VSCBI = 2614,
    VSCBIB  = 2615,
    VSCBIF  = 2616,
    VSCBIG  = 2617,
    VSCBIH  = 2618,
    VSCBIQ  = 2619,
    VSCEF = 2620,
    VSCEG = 2621,
    VSDP  = 2622,
    VSEG  = 2623,
    VSEGB = 2624,
    VSEGF = 2625,
    VSEGH = 2626,
    VSEL  = 2627,
    VSF = 2628,
    VSG = 2629,
    VSH = 2630,
    VSL = 2631,
    VSLB  = 2632,
    VSLDB = 2633,
    VSP = 2634,
    VSQ = 2635,
    VSRA  = 2636,
    VSRAB = 2637,
    VSRL  = 2638,
    VSRLB = 2639,
    VSRP  = 2640,
    VST = 2641,
    VSTEB = 2642,
    VSTEF = 2643,
    VSTEG = 2644,
    VSTEH = 2645,
    VSTL  = 2646,
    VSTM  = 2647,
    VSTRC = 2648,
    VSTRCB  = 2649,
    VSTRCBS = 2650,
    VSTRCF  = 2651,
    VSTRCFS = 2652,
    VSTRCH  = 2653,
    VSTRCHS = 2654,
    VSTRCZB = 2655,
    VSTRCZBS  = 2656,
    VSTRCZF = 2657,
    VSTRCZFS  = 2658,
    VSTRCZH = 2659,
    VSTRCZHS  = 2660,
    VSTRL = 2661,
    VSTRLR  = 2662,
    VSUM  = 2663,
    VSUMB = 2664,
    VSUMG = 2665,
    VSUMGF  = 2666,
    VSUMGH  = 2667,
    VSUMH = 2668,
    VSUMQ = 2669,
    VSUMQF  = 2670,
    VSUMQG  = 2671,
    VTM = 2672,
    VTP = 2673,
    VUPH  = 2674,
    VUPHB = 2675,
    VUPHF = 2676,
    VUPHH = 2677,
    VUPKZ = 2678,
    VUPL  = 2679,
    VUPLB = 2680,
    VUPLF = 2681,
    VUPLH = 2682,
    VUPLHB  = 2683,
    VUPLHF  = 2684,
    VUPLHH  = 2685,
    VUPLHW  = 2686,
    VUPLL = 2687,
    VUPLLB  = 2688,
    VUPLLF  = 2689,
    VUPLLH  = 2690,
    VX  = 2691,
    VZERO = 2692,
    WCDGB = 2693,
    WCDLGB  = 2694,
    WCGDB = 2695,
    WCLGDB  = 2696,
    WFADB = 2697,
    WFASB = 2698,
    WFAXB = 2699,
    WFC = 2700,
    WFCDB = 2701,
    WFCEDB  = 2702,
    WFCEDBS = 2703,
    WFCESB  = 2704,
    WFCESBS = 2705,
    WFCEXB  = 2706,
    WFCEXBS = 2707,
    WFCHDB  = 2708,
    WFCHDBS = 2709,
    WFCHEDB = 2710,
    WFCHEDBS  = 2711,
    WFCHESB = 2712,
    WFCHESBS  = 2713,
    WFCHEXB = 2714,
    WFCHEXBS  = 2715,
    WFCHSB  = 2716,
    WFCHSBS = 2717,
    WFCHXB  = 2718,
    WFCHXBS = 2719,
    WFCSB = 2720,
    WFCXB = 2721,
    WFDDB = 2722,
    WFDSB = 2723,
    WFDXB = 2724,
    WFIDB = 2725,
    WFISB = 2726,
    WFIXB = 2727,
    WFK = 2728,
    WFKDB = 2729,
    WFKEDB  = 2730,
    WFKEDBS = 2731,
    WFKESB  = 2732,
    WFKESBS = 2733,
    WFKEXB  = 2734,
    WFKEXBS = 2735,
    WFKHDB  = 2736,
    WFKHDBS = 2737,
    WFKHEDB = 2738,
    WFKHEDBS  = 2739,
    WFKHESB = 2740,
    WFKHESBS  = 2741,
    WFKHEXB = 2742,
    WFKHEXBS  = 2743,
    WFKHSB  = 2744,
    WFKHSBS = 2745,
    WFKHXB  = 2746,
    WFKHXBS = 2747,
    WFKSB = 2748,
    WFKXB = 2749,
    WFLCDB  = 2750,
    WFLCSB  = 2751,
    WFLCXB  = 2752,
    WFLLD = 2753,
    WFLLS = 2754,
    WFLNDB  = 2755,
    WFLNSB  = 2756,
    WFLNXB  = 2757,
    WFLPDB  = 2758,
    WFLPSB  = 2759,
    WFLPXB  = 2760,
    WFLRD = 2761,
    WFLRX = 2762,
    WFMADB  = 2763,
    WFMASB  = 2764,
    WFMAXB  = 2765,
    WFMAXDB = 2766,
    WFMAXSB = 2767,
    WFMAXXB = 2768,
    WFMDB = 2769,
    WFMINDB = 2770,
    WFMINSB = 2771,
    WFMINXB = 2772,
    WFMSB = 2773,
    WFMSDB  = 2774,
    WFMSSB  = 2775,
    WFMSXB  = 2776,
    WFMXB = 2777,
    WFNMADB = 2778,
    WFNMASB = 2779,
    WFNMAXB = 2780,
    WFNMSDB = 2781,
    WFNMSSB = 2782,
    WFNMSXB = 2783,
    WFPSODB = 2784,
    WFPSOSB = 2785,
    WFPSOXB = 2786,
    WFSDB = 2787,
    WFSQDB  = 2788,
    WFSQSB  = 2789,
    WFSQXB  = 2790,
    WFSSB = 2791,
    WFSXB = 2792,
    WFTCIDB = 2793,
    WFTCISB = 2794,
    WFTCIXB = 2795,
    WLDEB = 2796,
    WLEDB = 2797,
    X = 2798,
    XC  = 2799,
    XG  = 2800,
    XGR = 2801,
    XGRK  = 2802,
    XI  = 2803,
    XIHF  = 2804,
    XILF  = 2805,
    XIY = 2806,
    XR  = 2807,
    XRK = 2808,
    XSCH  = 2809,
    XY  = 2810,
    ZAP = 2811,
    INSTRUCTION_LIST_END = 2812
  };

} // end SystemZ namespace
} // end llvm namespace
#endif // GET_INSTRINFO_ENUM

#ifdef GET_INSTRINFO_SCHED_ENUM
#undef GET_INSTRINFO_SCHED_ENUM
namespace llvm {

namespace SystemZ {
namespace Sched {
  enum {
    NoInstrModel  = 0,
    ADJDYNALLOC = 1,
    CallBRCL_BRC_BRCAsm_BRCL_BRCLAsm  = 2,
    CallJG_J_JAsmE_JAsmH_JAsmHE_JAsmL_JAsmLE_JAsmLH_JAsmM_JAsmNE_JAsmNH_JAsmNHE_JAsmNL_JAsmNLE_JAsmNLH_JAsmNM_JAsmNO_JAsmNP_JAsmNZ_JAsmO_JAsmP_JAsmZ_JG_JGAsmE_JGAsmH_JGAsmHE_JGAsmL_JGAsmLE_JGAsmLH_JGAsmM_JGAsmNE_JGAsmNH_JGAsmNHE_JGAsmNL_JGAsmNLE_JGAsmNLH_JGAsmNM_JGAsmNO_JGAsmNP_JGAsmNZ_JGAsmO_JGAsmP_JGAsmZ = 3,
    CallBCR_BC_BCAsm_BCR_BCRAsm = 4,
    CallBR_B_BAsmE_BAsmH_BAsmHE_BAsmL_BAsmLE_BAsmLH_BAsmM_BAsmNE_BAsmNH_BAsmNHE_BAsmNL_BAsmNLE_BAsmNLH_BAsmNM_BAsmNO_BAsmNP_BAsmNZ_BAsmO_BAsmP_BAsmZ_BR_BRAsmE_BRAsmH_BRAsmHE_BRAsmL_BRAsmLE_BRAsmLH_BRAsmM_BRAsmNE_BRAsmNH_BRAsmNHE_BRAsmNL_BRAsmNLE_BRAsmNLH_BRAsmNM_BRAsmNO_BRAsmNP_BRAsmNZ_BRAsmO_BRAsmP_BRAsmZ = 5,
    BI_BIAsmE_BIAsmH_BIAsmHE_BIAsmL_BIAsmLE_BIAsmLH_BIAsmM_BIAsmNE_BIAsmNH_BIAsmNHE_BIAsmNL_BIAsmNLE_BIAsmNLH_BIAsmNM_BIAsmNO_BIAsmNP_BIAsmNZ_BIAsmO_BIAsmP_BIAsmZ_BIC_BICAsm = 6,
    BRCT_BRCTG  = 7,
    BRCTH = 8,
    BCT_BCTG_BCTGR_BCTR = 9,
    BRXH_BRXHG_BRXLE_BRXLG_BXH_BXHG_BXLE_BXLEG  = 10,
    CGIJ_CGIJAsm_CGIJAsmE_CGIJAsmH_CGIJAsmHE_CGIJAsmL_CGIJAsmLE_CGIJAsmLH_CGIJAsmNE_CGIJAsmNH_CGIJAsmNHE_CGIJAsmNL_CGIJAsmNLE_CGIJAsmNLH_CGRJ_CGRJAsm_CGRJAsmE_CGRJAsmH_CGRJAsmHE_CGRJAsmL_CGRJAsmLE_CGRJAsmLH_CGRJAsmNE_CGRJAsmNH_CGRJAsmNHE_CGRJAsmNL_CGRJAsmNLE_CGRJAsmNLH_CIJ_CIJAsm_CIJAsmE_CIJAsmH_CIJAsmHE_CIJAsmL_CIJAsmLE_CIJAsmLH_CIJAsmNE_CIJAsmNH_CIJAsmNHE_CIJAsmNL_CIJAsmNLE_CIJAsmNLH_CLGIJ_CLGIJAsm_CLGIJAsmE_CLGIJAsmH_CLGIJAsmHE_CLGIJAsmL_CLGIJAsmLE_CLGIJAsmLH_CLGIJAsmNE_CLGIJAsmNH_CLGIJAsmNHE_CLGIJAsmNL_CLGIJAsmNLE_CLGIJAsmNLH_CLGRJ_CLGRJAsm_CLGRJAsmE_CLGRJAsmH_CLGRJAsmHE_CLGRJAsmL_CLGRJAsmLE_CLGRJAsmLH_CLGRJAsmNE_CLGRJAsmNH_CLGRJAsmNHE_CLGRJAsmNL_CLGRJAsmNLE_CLGRJAsmNLH_CLIJ_CLIJAsm_CLIJAsmE_CLIJAsmH_CLIJAsmHE_CLIJAsmL_CLIJAsmLE_CLIJAsmLH_CLIJAsmNE_CLIJAsmNH_CLIJAsmNHE_CLIJAsmNL_CLIJAsmNLE_CLIJAsmNLH_CLRJ_CLRJAsm_CLRJAsmE_CLRJAsmH_CLRJAsmHE_CLRJAsmL_CLRJAsmLE_CLRJAsmLH_CLRJAsmNE_CLRJAsmNH_CLRJAsmNHE_CLRJAsmNL_CLRJAsmNLE_CLRJAsmNLH_CRJ_CRJAsm_CRJAsmE_CRJAsmH_CRJAsmHE_CRJAsmL_CRJAsmLE_CRJAsmLH_CRJAsmNE_CRJAsmNH_CRJAsmNHE_CRJAsmNL_CRJAsmNLE_CRJAsmNLH = 11,
    CGIBCall_CGIBReturn_CGRBCall_CGRBReturn_CIBCall_CIBReturn_CLGIBCall_CLGIBReturn_CLGRBCall_CLGRBReturn_CLIBCall_CLIBReturn_CLRBCall_CLRBReturn_CRBCall_CRBReturn_CGIB_CGIBAsm_CGIBAsmE_CGIBAsmH_CGIBAsmHE_CGIBAsmL_CGIBAsmLE_CGIBAsmLH_CGIBAsmNE_CGIBAsmNH_CGIBAsmNHE_CGIBAsmNL_CGIBAsmNLE_CGIBAsmNLH_CGRB_CGRBAsm_CGRBAsmE_CGRBAsmH_CGRBAsmHE_CGRBAsmL_CGRBAsmLE_CGRBAsmLH_CGRBAsmNE_CGRBAsmNH_CGRBAsmNHE_CGRBAsmNL_CGRBAsmNLE_CGRBAsmNLH_CIB_CIBAsm_CIBAsmE_CIBAsmH_CIBAsmHE_CIBAsmL_CIBAsmLE_CIBAsmLH_CIBAsmNE_CIBAsmNH_CIBAsmNHE_CIBAsmNL_CIBAsmNLE_CIBAsmNLH_CLGIB_CLGIBAsm_CLGIBAsmE_CLGIBAsmH_CLGIBAsmHE_CLGIBAsmL_CLGIBAsmLE_CLGIBAsmLH_CLGIBAsmNE_CLGIBAsmNH_CLGIBAsmNHE_CLGIBAsmNL_CLGIBAsmNLE_CLGIBAsmNLH_CLGRB_CLGRBAsm_CLGRBAsmE_CLGRBAsmH_CLGRBAsmHE_CLGRBAsmL_CLGRBAsmLE_CLGRBAsmLH_CLGRBAsmNE_CLGRBAsmNH_CLGRBAsmNHE_CLGRBAsmNL_CLGRBAsmNLE_CLGRBAsmNLH_CLIB_CLIBAsm_CLIBAsmE_CLIBAsmH_CLIBAsmHE_CLIBAsmL_CLIBAsmLE_CLIBAsmLH_CLIBAsmNE_CLIBAsmNH_CLIBAsmNHE_CLIBAsmNL_CLIBAsmNLE_CLIBAsmNLH_CLRB_CLRBAsm_CLRBAsmE_CLRBAsmH_CLRBAsmHE_CLRBAsmL_CLRBAsmLE_CLRBAsmLH_CLRBAsmNE_CLRBAsmNH_CLRBAsmNHE_CLRBAsmNL_CLRBAsmNLE_CLRBAsmNLH_CRB_CRBAsm_CRBAsmE_CRBAsmH_CRBAsmHE_CRBAsmL_CRBAsmLE_CRBAsmLH_CRBAsmNE_CRBAsmNH_CRBAsmNHE_CRBAsmNL_CRBAsmNLE_CRBAsmNLH = 12,
    CondTrap_Trap = 13,
    CGIT_CGITAsm_CGITAsmE_CGITAsmH_CGITAsmHE_CGITAsmL_CGITAsmLE_CGITAsmLH_CGITAsmNE_CGITAsmNH_CGITAsmNHE_CGITAsmNL_CGITAsmNLE_CGITAsmNLH_CGRT_CGRTAsm_CGRTAsmE_CGRTAsmH_CGRTAsmHE_CGRTAsmL_CGRTAsmLE_CGRTAsmLH_CGRTAsmNE_CGRTAsmNH_CGRTAsmNHE_CGRTAsmNL_CGRTAsmNLE_CGRTAsmNLH_CIT_CITAsm_CITAsmE_CITAsmH_CITAsmHE_CITAsmL_CITAsmLE_CITAsmLH_CITAsmNE_CITAsmNH_CITAsmNHE_CITAsmNL_CITAsmNLE_CITAsmNLH_CRT_CRTAsm_CRTAsmE_CRTAsmH_CRTAsmHE_CRTAsmL_CRTAsmLE_CRTAsmLH_CRTAsmNE_CRTAsmNH_CRTAsmNHE_CRTAsmNL_CRTAsmNLE_CRTAsmNLH = 14,
    CLGRT_CLGRTAsm_CLGRTAsmE_CLGRTAsmH_CLGRTAsmHE_CLGRTAsmL_CLGRTAsmLE_CLGRTAsmLH_CLGRTAsmNE_CLGRTAsmNH_CLGRTAsmNHE_CLGRTAsmNL_CLGRTAsmNLE_CLGRTAsmNLH_CLRT_CLRTAsm_CLRTAsmE_CLRTAsmH_CLRTAsmHE_CLRTAsmL_CLRTAsmLE_CLRTAsmLH_CLRTAsmNE_CLRTAsmNH_CLRTAsmNHE_CLRTAsmNL_CLRTAsmNLE_CLRTAsmNLH = 15,
    CLFIT_CLFITAsm_CLFITAsmE_CLFITAsmH_CLFITAsmHE_CLFITAsmL_CLFITAsmLE_CLFITAsmLH_CLFITAsmNE_CLFITAsmNH_CLFITAsmNHE_CLFITAsmNL_CLFITAsmNLE_CLFITAsmNLH_CLGIT_CLGITAsm_CLGITAsmE_CLGITAsmH_CLGITAsmHE_CLGITAsmL_CLGITAsmLE_CLGITAsmLH_CLGITAsmNE_CLGITAsmNH_CLGITAsmNHE_CLGITAsmNL_CLGITAsmNLE_CLGITAsmNLH = 16,
    CLGT_CLGTAsm_CLGTAsmE_CLGTAsmH_CLGTAsmHE_CLGTAsmL_CLGTAsmLE_CLGTAsmLH_CLGTAsmNE_CLGTAsmNH_CLGTAsmNHE_CLGTAsmNL_CLGTAsmNLE_CLGTAsmNLH_CLT_CLTAsm_CLTAsmE_CLTAsmH_CLTAsmHE_CLTAsmL_CLTAsmLE_CLTAsmLH_CLTAsmNE_CLTAsmNH_CLTAsmNHE_CLTAsmNL_CLTAsmNLE_CLTAsmNLH = 17,
    BRAS  = 18,
    CallBRASL_BRASL = 19,
    CallBASR_BAS_BASR = 20,
    TLS_GDCALL_TLS_LDCALL = 21,
    Return  = 22,
    CondReturn  = 23,
    MVGHI_MVHHI_MVHI  = 24,
    MVI_MVIY  = 25,
    MVC = 26,
    MVCL_MVCLE_MVCLU  = 27,
    COPY_TO_REGCLASS_COPY = 28,
    EXTRACT_SUBREG  = 29,
    INSERT_SUBREG = 30,
    REG_SEQUENCE  = 31,
    LMux_L_LFH_LRL_LY = 32,
    LCBB  = 33,
    LG_LGRL = 34,
    L128  = 35,
    LLIHF_LLIHH_LLIHL = 36,
    LLILF_LLILH_LLILL = 37,
    LGFI_LGHI = 38,
    LHIMux_LHI  = 39,
    LRMux_LR  = 40,
    LZRF_LZRG = 41,
    LAT_LFHAT_LGAT  = 42,
    LT_LTG  = 43,
    LTGR_LTR  = 44,
    STG_STGRL = 45,
    ST128 = 46,
    STMux_ST_STFH_STRL_STY  = 47,
    MVST  = 48,
    LOCRMux = 49,
    LOCFHR_LOCFHRAsm_LOCFHRAsmE_LOCFHRAsmH_LOCFHRAsmHE_LOCFHRAsmL_LOCFHRAsmLE_LOCFHRAsmLH_LOCFHRAsmM_LOCFHRAsmNE_LOCFHRAsmNH_LOCFHRAsmNHE_LOCFHRAsmNL_LOCFHRAsmNLE_LOCFHRAsmNLH_LOCFHRAsmNM_LOCFHRAsmNO_LOCFHRAsmNP_LOCFHRAsmNZ_LOCFHRAsmO_LOCFHRAsmP_LOCFHRAsmZ_LOCGR_LOCGRAsm_LOCGRAsmE_LOCGRAsmH_LOCGRAsmHE_LOCGRAsmL_LOCGRAsmLE_LOCGRAsmLH_LOCGRAsmM_LOCGRAsmNE_LOCGRAsmNH_LOCGRAsmNHE_LOCGRAsmNL_LOCGRAsmNLE_LOCGRAsmNLH_LOCGRAsmNM_LOCGRAsmNO_LOCGRAsmNP_LOCGRAsmNZ_LOCGRAsmO_LOCGRAsmP_LOCGRAsmZ_LOCR_LOCRAsm_LOCRAsmE_LOCRAsmH_LOCRAsmHE_LOCRAsmL_LOCRAsmLE_LOCRAsmLH_LOCRAsmM_LOCRAsmNE_LOCRAsmNH_LOCRAsmNHE_LOCRAsmNL_LOCRAsmNLE_LOCRAsmNLH_LOCRAsmNM_LOCRAsmNO_LOCRAsmNP_LOCRAsmNZ_LOCRAsmO_LOCRAsmP_LOCRAsmZ  = 50,
    LOCHIMux_LOCGHI_LOCGHIAsm_LOCGHIAsmE_LOCGHIAsmH_LOCGHIAsmHE_LOCGHIAsmL_LOCGHIAsmLE_LOCGHIAsmLH_LOCGHIAsmM_LOCGHIAsmNE_LOCGHIAsmNH_LOCGHIAsmNHE_LOCGHIAsmNL_LOCGHIAsmNLE_LOCGHIAsmNLH_LOCGHIAsmNM_LOCGHIAsmNO_LOCGHIAsmNP_LOCGHIAsmNZ_LOCGHIAsmO_LOCGHIAsmP_LOCGHIAsmZ_LOCHHI_LOCHHIAsm_LOCHHIAsmE_LOCHHIAsmH_LOCHHIAsmHE_LOCHHIAsmL_LOCHHIAsmLE_LOCHHIAsmLH_LOCHHIAsmM_LOCHHIAsmNE_LOCHHIAsmNH_LOCHHIAsmNHE_LOCHHIAsmNL_LOCHHIAsmNLE_LOCHHIAsmNLH_LOCHHIAsmNM_LOCHHIAsmNO_LOCHHIAsmNP_LOCHHIAsmNZ_LOCHHIAsmO_LOCHHIAsmP_LOCHHIAsmZ_LOCHI_LOCHIAsm_LOCHIAsmE_LOCHIAsmH_LOCHIAsmHE_LOCHIAsmL_LOCHIAsmLE_LOCHIAsmLH_LOCHIAsmM_LOCHIAsmNE_LOCHIAsmNH_LOCHIAsmNHE_LOCHIAsmNL_LOCHIAsmNLE_LOCHIAsmNLH_LOCHIAsmNM_LOCHIAsmNO_LOCHIAsmNP_LOCHIAsmNZ_LOCHIAsmO_LOCHIAsmP_LOCHIAsmZ = 51,
    LOCMux_LOC_LOCAsm_LOCAsmE_LOCAsmH_LOCAsmHE_LOCAsmL_LOCAsmLE_LOCAsmLH_LOCAsmM_LOCAsmNE_LOCAsmNH_LOCAsmNHE_LOCAsmNL_LOCAsmNLE_LOCAsmNLH_LOCAsmNM_LOCAsmNO_LOCAsmNP_LOCAsmNZ_LOCAsmO_LOCAsmP_LOCAsmZ_LOCFH_LOCFHAsm_LOCFHAsmE_LOCFHAsmH_LOCFHAsmHE_LOCFHAsmL_LOCFHAsmLE_LOCFHAsmLH_LOCFHAsmM_LOCFHAsmNE_LOCFHAsmNH_LOCFHAsmNHE_LOCFHAsmNL_LOCFHAsmNLE_LOCFHAsmNLH_LOCFHAsmNM_LOCFHAsmNO_LOCFHAsmNP_LOCFHAsmNZ_LOCFHAsmO_LOCFHAsmP_LOCFHAsmZ_LOCG_LOCGAsm_LOCGAsmE_LOCGAsmH_LOCGAsmHE_LOCGAsmL_LOCGAsmLE_LOCGAsmLH_LOCGAsmM_LOCGAsmNE_LOCGAsmNH_LOCGAsmNHE_LOCGAsmNL_LOCGAsmNLE_LOCGAsmNLH_LOCGAsmNM_LOCGAsmNO_LOCGAsmNP_LOCGAsmNZ_LOCGAsmO_LOCGAsmP_LOCGAsmZ = 52,
    STOCMux_STOC_STOCAsm_STOCAsmE_STOCAsmH_STOCAsmHE_STOCAsmL_STOCAsmLE_STOCAsmLH_STOCAsmM_STOCAsmNE_STOCAsmNH_STOCAsmNHE_STOCAsmNL_STOCAsmNLE_STOCAsmNLH_STOCAsmNM_STOCAsmNO_STOCAsmNP_STOCAsmNZ_STOCAsmO_STOCAsmP_STOCAsmZ_STOCFH_STOCFHAsm_STOCFHAsmE_STOCFHAsmH_STOCFHAsmHE_STOCFHAsmL_STOCFHAsmLE_STOCFHAsmLH_STOCFHAsmM_STOCFHAsmNE_STOCFHAsmNH_STOCFHAsmNHE_STOCFHAsmNL_STOCFHAsmNLE_STOCFHAsmNLH_STOCFHAsmNM_STOCFHAsmNO_STOCFHAsmNP_STOCFHAsmNZ_STOCFHAsmO_STOCFHAsmP_STOCFHAsmZ_STOCG_STOCGAsm_STOCGAsmE_STOCGAsmH_STOCGAsmHE_STOCGAsmL_STOCGAsmLE_STOCGAsmLH_STOCGAsmM_STOCGAsmNE_STOCGAsmNH_STOCGAsmNHE_STOCGAsmNL_STOCGAsmNLE_STOCGAsmNLH_STOCGAsmNM_STOCGAsmNO_STOCGAsmNP_STOCGAsmNZ_STOCGAsmO_STOCGAsmP_STOCGAsmZ  = 53,
    LBR_LGR_LHR = 54,
    LGBR_LGFR_LGHR  = 55,
    LTGF  = 56,
    LTGFR = 57,
    LBMux_LB_LBH  = 58,
    LH_LHY  = 59,
    LHMux_LHH_LHRL  = 60,
    LGB_LGF_LGH = 61,
    LGFRL_LGHRL = 62,
    LLCRMux_LLCR  = 63,
    LLHRMux_LLHR  = 64,
    LLGCR_LLGFR_LLGHR_LLGTR = 65,
    LLCMux_LLC  = 66,
    LLHMux_LLH  = 67,
    LLCH_LLHH = 68,
    LLHRL = 69,
    LLGC_LLGF_LLGFRL_LLGH_LLGHRL_LLGT = 70,
    LLZRGF  = 71,
    LLGFAT_LLGTAT = 72,
    STCMux_STC_STCH_STCY  = 73,
    STHMux_STH_STHH_STHRL_STHY  = 74,
    STCM_STCMH_STCMY  = 75,
    LM_LMG_LMH_LMY  = 76,
    LMD = 77,
    STM_STMG_STMH_STMY  = 78,
    LRVGR_LRVR  = 79,
    LRV_LRVG_LRVH = 80,
    STRV_STRVG_STRVH  = 81,
    MVCIN = 82,
    LA_LARL_LAY = 83,
    GOT = 84,
    LPGR_LPR  = 85,
    LNGFR_LPGFR = 86,
    LNGR_LNR  = 87,
    LCGR_LCR  = 88,
    LCGFR = 89,
    IC_ICY  = 90,
    IC32_IC32Y  = 91,
    ICM_ICMH_ICMY = 92,
    IIFMux_IIHMux_IILMux  = 93,
    IIHF64_IIHF = 94,
    IIHH64_IIHH = 95,
    IIHL64_IIHL = 96,
    IILF64_IILF = 97,
    IILH64_IILH = 98,
    IILL64_IILL = 99,
    A_AY  = 100,
    AH_AHY  = 101,
    AIH = 102,
    AFIMux_AFI  = 103,
    AG  = 104,
    AGFI  = 105,
    AGHI_AGHIK  = 106,
    AGR_AGRK  = 107,
    AHI_AHIK  = 108,
    AHIMux_AHIMuxK  = 109,
    AL_ALY  = 110,
    ALFI_ALHSIK = 111,
    ALG_ALGF  = 112,
    ALGHSIK = 113,
    ALGFI_ALGFR = 114,
    ALGR_ALGRK  = 115,
    ALR_ALRK  = 116,
    AR_ARK  = 117,
    AHHHR_ALHHHR  = 118,
    AHHLR_ALHHLR  = 119,
    ALSIH_ALSIHN  = 120,
    AGSI_ALGSI_ALSI_ASI = 121,
    ALC_ALCG  = 122,
    ALCGR_ALCR  = 123,
    AGF_AGH = 124,
    AGFR  = 125,
    S_SG_SY = 126,
    SH_SHY  = 127,
    SGR_SGRK  = 128,
    SLFI  = 129,
    SL_SLG_SLGF_SLY = 130,
    SLGFI_SLGFR = 131,
    SLGR_SLGRK  = 132,
    SLR_SLRK  = 133,
    SR_SRK  = 134,
    SHHHR_SLHHHR  = 135,
    SHHLR_SLHHLR  = 136,
    SLB_SLBG  = 137,
    SLBGR_SLBR  = 138,
    SGF_SGH = 139,
    SGFR  = 140,
    N_NG_NY = 141,
    NGR_NGRK  = 142,
    NIFMux_NIHMux_NILMux  = 143,
    NI_NIY  = 144,
    NIHF64_NIHF = 145,
    NIHH64_NIHH = 146,
    NIHL64_NIHL = 147,
    NILF64_NILF = 148,
    NILH64_NILH = 149,
    NILL64_NILL = 150,
    NR_NRK  = 151,
    NC  = 152,
    O_OG_OY = 153,
    OGR_OGRK  = 154,
    OI_OIY  = 155,
    OIFMux_OIHMux_OILMux  = 156,
    OIHF64_OIHF = 157,
    OIHH64_OIHH = 158,
    OIHL64_OIHL = 159,
    OILF64_OILF = 160,
    OILH64_OILH = 161,
    OILL64_OILL = 162,
    OR_ORK  = 163,
    OC  = 164,
    X_XG_XY = 165,
    XI_XIY  = 166,
    XIFMux  = 167,
    XGR_XGRK  = 168,
    XIHF64_XIHF = 169,
    XILF64_XILF = 170,
    XR_XRK  = 171,
    XC  = 172,
    MS_MSGF_MSY = 173,
    MSFI_MSR  = 174,
    MSG = 175,
    MSGR  = 176,
    MSGFI_MSGFR = 177,
    MLG = 178,
    MLGR  = 179,
    MGHI  = 180,
    MHI = 181,
    MH_MHY  = 182,
    MLR_MR  = 183,
    M_MFY_ML  = 184,
    MGH = 185,
    MG  = 186,
    MGRK  = 187,
    MSC = 188,
    MSGC  = 189,
    MSRKC = 190,
    MSGRKC  = 191,
    DR  = 192,
    D = 193,
    DSGFR_DSGR  = 194,
    DSG_DSGF  = 195,
    DLR = 196,
    DLGR  = 197,
    DL_DLG  = 198,
    SLL_SLLG_SLLK = 199,
    SRL_SRLG_SRLK = 200,
    SRA_SRAG_SRAK = 201,
    SLA_SLAG_SLAK = 202,
    SLDA_SLDL_SRDA_SRDL = 203,
    RLL_RLLG  = 204,
    RISBG_RISBG32_RISBGN  = 205,
    RISBHH_RISBHL_RISBHG  = 206,
    RISBLH_RISBLL_RISBLG  = 207,
    RISBMux = 208,
    RNSBG_ROSBG_RXSBG = 209,
    CMux_C_CG_CY  = 210,
    CRL = 211,
    CFIMux_CHIMux_CFI_CHI = 212,
    CGFI_CGHI = 213,
    CGHSI_CGRL  = 214,
    CGR_CR  = 215,
    CIH = 216,
    CHF = 217,
    CHSI  = 218,
    CLMux_CL_CLY  = 219,
    CLFHSI  = 220,
    CLFIMux_CLFI  = 221,
    CLG = 222,
    CLGHRL_CLGHSI = 223,
    CLGF  = 224,
    CLGFRL  = 225,
    CLGFI_CLGFR = 226,
    CLGR  = 227,
    CLGRL = 228,
    CLHF  = 229,
    CLHHSI_CLHRL  = 230,
    CLIH  = 231,
    CLI_CLIY  = 232,
    CLR = 233,
    CLRL  = 234,
    CHHR_CLHHR  = 235,
    CHLR_CLHLR  = 236,
    CH_CHY  = 237,
    CHRL  = 238,
    CGH = 239,
    CGHRL = 240,
    CHHSI = 241,
    CGF = 242,
    CGFRL = 243,
    CGFR  = 244,
    CLC = 245,
    CLCL_CLCLE_CLCLU  = 246,
    CLST  = 247,
    TM_TMY  = 248,
    TMHMux_TMLMux = 249,
    TMHH64_TMHH = 250,
    TMHL64_TMHL = 251,
    TMLH64_TMLH = 252,
    TMLL64_TMLL = 253,
    CLM_CLMH_CLMY = 254,
    PFD_PFDRL = 255,
    BPP = 256,
    BPRP  = 257,
    NIAI  = 258,
    Serialize = 259,
    LAA_LAAG  = 260,
    LAAL_LAALG  = 261,
    LAN_LANG  = 262,
    LAO_LAOG  = 263,
    LAX_LAXG  = 264,
    TS  = 265,
    CS_CSG_CSY  = 266,
    CDS_CDSY  = 267,
    CDSG  = 268,
    CSST  = 269,
    PLO = 270,
    LPQ = 271,
    STPQ  = 272,
    LPD_LPDG  = 273,
    TR  = 274,
    TRT = 275,
    TRTR  = 276,
    TRE = 277,
    TRTE_TRTEOpt_TRTRE_TRTREOpt = 278,
    TROO_TROOOpt_TROT_TROTOpt_TRTO_TRTOOpt_TRTT_TRTTOpt = 279,
    CU12_CU12Opt_CU14_CU14Opt_CU21_CU21Opt_CU24_CU24Opt_CU41_CU42 = 280,
    CUTFU_CUTFUOpt_CUUTF_CUUTFOpt = 281,
    KM_KMA_KMC_KMCTR_KMF_KMO  = 282,
    KIMD_KLMD_KMAC  = 283,
    PCC_PPNO_PRNO = 284,
    LGG = 285,
    LLGFSG  = 286,
    LGSC_STGSC  = 287,
    CVBG  = 288,
    CVB_CVBY  = 289,
    CVDG  = 290,
    CVD_CVDY  = 291,
    MVN_MVO_MVZ = 292,
    PACK_PKA_PKU  = 293,
    UNPKA_UNPKU = 294,
    UNPK  = 295,
    AP_SP_ZAP = 296,
    DP_MP = 297,
    SRP = 298,
    CP  = 299,
    TP  = 300,
    ED_EDMK = 301,
    CPYA_EAR_SAR  = 302,
    LAE_LAEY  = 303,
    LAM_LAMY  = 304,
    STAM_STAMY  = 305,
    IPM = 306,
    SPM = 307,
    BAL_BALR  = 308,
    TAM = 309,
    SAM24_SAM31_SAM64 = 310,
    BSM = 311,
    BASSM = 312,
    TBEGIN_TBEGINC  = 313,
    TEND  = 314,
    TABORT  = 315,
    ETND  = 316,
    NTSTG = 317,
    PPA = 318,
    FLOGR = 319,
    POPCNT  = 320,
    SRST_SRSTU  = 321,
    CUSE  = 322,
    CFC = 323,
    UPT = 324,
    CKSM  = 325,
    CMPSC = 326,
    EX_EXRL = 327,
    InsnE_InsnRI_InsnRIE_InsnRIL_InsnRILU_InsnRIS_InsnRR_InsnRRE_InsnRRF_InsnRRS_InsnRS_InsnRSE_InsnRSI_InsnRSY_InsnRX_InsnRXE_InsnRXF_InsnRXY_InsnS_InsnSI_InsnSIL_InsnSIY_InsnSS_InsnSSE_InsnSSF  = 328,
    LZDR_LZER = 329,
    LZXR  = 330,
    LER = 331,
    LDGR_LDR_LDR32  = 332,
    LGDR  = 333,
    LXR = 334,
    LTDBR_LTEBR = 335,
    LTDBRCompare_LTEBRCompare = 336,
    LTXBR_LTXBRCompare  = 337,
    CPSDRdd_CPSDRds_CPSDRsd_CPSDRss = 338,
    LE_LEY  = 339,
    LD_LDE32_LDY  = 340,
    LX  = 341,
    STD_STDY_STE_STEY = 342,
    STX = 343,
    LEDBR_LEDBRA  = 344,
    LDXBR_LDXBRA_LEXBR_LEXBRA = 345,
    LDEB  = 346,
    LDEBR = 347,
    LXDB_LXEB = 348,
    LXDBR_LXEBR = 349,
    CDFBR_CDFBRA_CDGBR_CDGBRA_CEFBR_CEFBRA_CEGBR_CEGBRA = 350,
    CXFBR_CXFBRA_CXGBR_CXGBRA = 351,
    CDLFBR_CDLGBR_CELFBR_CELGBR = 352,
    CXLFBR_CXLGBR = 353,
    CFDBR_CFDBRA_CFEBR_CFEBRA_CGDBR_CGDBRA_CGEBR_CGEBRA = 354,
    CFXBR_CFXBRA_CGXBR_CGXBRA = 355,
    CLFEBR  = 356,
    CLFDBR  = 357,
    CLGDBR_CLGEBR = 358,
    CLFXBR_CLGXBR = 359,
    LCDBR_LCEBR_LNDBR_LNEBR_LPDBR_LPEBR = 360,
    LCDFR_LCDFR_32_LNDFR_LNDFR_32_LPDFR_LPDFR_32  = 361,
    LCXBR_LNXBR_LPXBR = 362,
    SQDB_SQEB = 363,
    SQDBR_SQEBR = 364,
    SQXBR = 365,
    FIDBR_FIDBRA_FIEBR_FIEBRA = 366,
    FIXBR_FIXBRA  = 367,
    ADB_AEB = 368,
    ADBR_AEBR = 369,
    AXBR  = 370,
    SDB_SEB = 371,
    SDBR_SEBR = 372,
    SXBR  = 373,
    MDB_MDEB_MEEB = 374,
    MDBR_MDEBR_MEEBR  = 375,
    MXDB  = 376,
    MXDBR = 377,
    MXBR  = 378,
    MAEB_MSEB = 379,
    MAEBR_MSEBR = 380,
    MADB_MSDB = 381,
    MADBR_MSDBR = 382,
    DDB_DEB = 383,
    DDBR_DEBR = 384,
    DXBR  = 385,
    DIDBR_DIEBR = 386,
    CDB_CEB_KDB_KEB = 387,
    CDBR_CEBR_KDBR_KEBR = 388,
    CXBR_KXBR = 389,
    TCDB_TCEB = 390,
    TCXB  = 391,
    EFPC  = 392,
    STFPC = 393,
    SFPC  = 394,
    LFPC  = 395,
    SFASR = 396,
    LFAS  = 397,
    SRNM_SRNMB_SRNMT  = 398,
    LTDR_LTER = 399,
    LTXR  = 400,
    LEDR_LRER = 401,
    LEXR  = 402,
    LDXR_LRDR = 403,
    LDE = 404,
    LDER  = 405,
    LXD_LXE = 406,
    LXDR_LXER = 407,
    CDFR_CDGR_CEFR_CEGR = 408,
    CXFR_CXGR = 409,
    CFDR_CFER_CGDR_CGER = 410,
    CFXR_CGXR = 411,
    THDER_THDR  = 412,
    TBDR_TBEDR  = 413,
    LCDR_LCER_LNDR_LNER_LPDR_LPER = 414,
    LCXR_LNXR_LPXR  = 415,
    HDR_HER = 416,
    SQD_SQE = 417,
    SQDR_SQER = 418,
    SQXR  = 419,
    FIDR_FIER = 420,
    FIXR  = 421,
    AD_AE_AU_AW = 422,
    ADR_AER_AUR_AWR = 423,
    AXR = 424,
    SD_SE_SU_SW = 425,
    SDR_SER_SUR_SWR = 426,
    SXR = 427,
    MD_MDE_ME_MEE = 428,
    MDER_MDR_MEER_MER = 429,
    MXD = 430,
    MXDR  = 431,
    MXR = 432,
    MY  = 433,
    MYH_MYL = 434,
    MYR = 435,
    MYHR_MYLR = 436,
    MAD_MAE_MSD_MSE = 437,
    MADR_MAER_MSDR_MSER = 438,
    MAY = 439,
    MAYH_MAYL = 440,
    MAYR  = 441,
    MAYHR_MAYLR = 442,
    DD_DE = 443,
    DDR_DER = 444,
    DXR = 445,
    CD_CE = 446,
    CDR_CER = 447,
    CXR = 448,
    LTDTR = 449,
    LTXTR = 450,
    LEDTR = 451,
    LDXTR = 452,
    LDETR = 453,
    LXDTR = 454,
    CDFTR_CDGTR_CDGTRA  = 455,
    CXFTR_CXGTR_CXGTRA  = 456,
    CDLFTR_CDLGTR = 457,
    CXLFTR_CXLGTR = 458,
    CFDTR_CGDTR_CGDTRA  = 459,
    CFXTR_CGXTR_CGXTRA  = 460,
    CLFDTR_CLGDTR = 461,
    CLFXTR_CLGXTR = 462,
    CDSTR_CDUTR = 463,
    CXSTR_CXUTR = 464,
    CSDTR_CUDTR = 465,
    CSXTR_CUXTR = 466,
    CDZT  = 467,
    CXZT  = 468,
    CZDT  = 469,
    CZXT  = 470,
    CDPT  = 471,
    CXPT  = 472,
    CPDT  = 473,
    CPXT  = 474,
    PFPO  = 475,
    FIDTR = 476,
    FIXTR = 477,
    EEDTR = 478,
    EEXTR = 479,
    ESDTR = 480,
    ESXTR = 481,
    ADTR_ADTRA  = 482,
    AXTR_AXTRA  = 483,
    SDTR_SDTRA  = 484,
    SXTR_SXTRA  = 485,
    MDTR_MDTRA  = 486,
    MXTR_MXTRA  = 487,
    DDTR_DDTRA  = 488,
    DXTR_DXTRA  = 489,
    QADTR = 490,
    QAXTR = 491,
    RRDTR = 492,
    RRXTR = 493,
    SLDT_SRDT = 494,
    SLXT_SRXT = 495,
    IEDTR = 496,
    IEXTR = 497,
    CDTR_KDTR = 498,
    CXTR_KXTR = 499,
    CEDTR = 500,
    CEXTR = 501,
    TDCDT_TDCET_TDGDT_TDGET = 502,
    TDCXT_TDGXT = 503,
    VLR32_VLR64_VLR = 504,
    VLGV_VLGVB_VLGVF_VLGVG_VLGVH  = 505,
    VLVG_VLVGB_VLVGF_VLVGG_VLVGH  = 506,
    VLVGP32_VLVGP = 507,
    VZERO = 508,
    VONE  = 509,
    VGBM  = 510,
    VGM_VGMB_VGMF_VGMG_VGMH = 511,
    VREPI_VREPIB_VREPIF_VREPIG_VREPIH = 512,
    VLEIB_VLEIF_VLEIG_VLEIH = 513,
    VL_VLBB = 514,
    VLL = 515,
    VL32_VL64 = 516,
    VLLEZ_VLLEZB_VLLEZF_VLLEZG_VLLEZH_VLLEZLF = 517,
    VLREP_VLREPB_VLREPF_VLREPG_VLREPH = 518,
    VLEB_VLEF_VLEG_VLEH = 519,
    VGEF_VGEG = 520,
    VLM = 521,
    VLRL_VLRLR  = 522,
    VST32_VST64_VST_VSTL  = 523,
    VSTEF_VSTEG = 524,
    VSTEB_VSTEH = 525,
    VSTM  = 526,
    VSCEF_VSCEG = 527,
    VSTRL_VSTRLR  = 528,
    VMRH_VMRHB_VMRHF_VMRHG_VMRHH  = 529,
    VMRL_VMRLB_VMRLF_VMRLG_VMRLH  = 530,
    VPERM = 531,
    VPDI  = 532,
    VBPERM  = 533,
    VREP_VREPB_VREPF_VREPG_VREPH  = 534,
    VSEL  = 535,
    VPK_VPKF_VPKG_VPKH  = 536,
    VPKS_VPKSF_VPKSG_VPKSH  = 537,
    VPKSFS_VPKSGS_VPKSHS  = 538,
    VPKLS_VPKLSF_VPKLSG_VPKLSH  = 539,
    VPKLSFS_VPKLSGS_VPKLSHS = 540,
    VSEG_VSEGB_VSEGF_VSEGH  = 541,
    VUPH_VUPHB_VUPHF_VUPHH  = 542,
    VUPL_VUPLB_VUPLF  = 543,
    VUPLH_VUPLHB_VUPLHF_VUPLHH_VUPLHW = 544,
    VUPLL_VUPLLB_VUPLLF_VUPLLH  = 545,
    VA_VAB_VAC_VACQ_VAF_VAG_VAH_VAQ = 546,
    VACC_VACCB_VACCC_VACCCQ_VACCF_VACCG_VACCH_VACCQ = 547,
    VAVG_VAVGB_VAVGF_VAVGG_VAVGH  = 548,
    VAVGL_VAVGLB_VAVGLF_VAVGLG_VAVGLH = 549,
    VN_VNC_VNN_VNO_VNX  = 550,
    VO_VOC  = 551,
    VCKSM = 552,
    VCLZ_VCLZB_VCLZF_VCLZG_VCLZH  = 553,
    VCTZ_VCTZB_VCTZF_VCTZG_VCTZH  = 554,
    VX  = 555,
    VGFM  = 556,
    VGFMA_VGFMAB_VGFMAF_VGFMAG_VGFMAH = 557,
    VGFMB_VGFMF_VGFMG_VGFMH = 558,
    VLC_VLCB_VLCF_VLCG_VLCH = 559,
    VLP_VLPB_VLPF_VLPG_VLPH = 560,
    VMX_VMXB_VMXF_VMXG_VMXH = 561,
    VMXL_VMXLB_VMXLF_VMXLG_VMXLH  = 562,
    VMN_VMNB_VMNF_VMNG_VMNH = 563,
    VMNL_VMNLB_VMNLF_VMNLG_VMNLH  = 564,
    VMAL_VMALB_VMALF  = 565,
    VMALE_VMALEB_VMALEF_VMALEH  = 566,
    VMALH_VMALHB_VMALHF_VMALHH_VMALHW = 567,
    VMALO_VMALOB_VMALOF_VMALOH  = 568,
    VMAO_VMAOB_VMAOF_VMAOH  = 569,
    VMAE_VMAEB_VMAEF_VMAEH  = 570,
    VMAH_VMAHB_VMAHF_VMAHH  = 571,
    VME_VMEB_VMEF_VMEH  = 572,
    VMH_VMHB_VMHF_VMHH  = 573,
    VML_VMLB_VMLF = 574,
    VMLE_VMLEB_VMLEF_VMLEH  = 575,
    VMLH_VMLHB_VMLHF_VMLHH_VMLHW  = 576,
    VMLO_VMLOB_VMLOF_VMLOH  = 577,
    VMO_VMOB_VMOF_VMOH  = 578,
    VMSL_VMSLG  = 579,
    VPOPCT_VPOPCTB_VPOPCTF_VPOPCTG_VPOPCTH  = 580,
    VERLL_VERLLB_VERLLF_VERLLG_VERLLH = 581,
    VERLLV_VERLLVB_VERLLVF_VERLLVG_VERLLVH  = 582,
    VERIM_VERIMB_VERIMF_VERIMG_VERIMH = 583,
    VESL_VESLB_VESLF_VESLG_VESLH  = 584,
    VESLV_VESLVB_VESLVF_VESLVG_VESLVH = 585,
    VESRA_VESRAB_VESRAF_VESRAG_VESRAH = 586,
    VESRAV_VESRAVB_VESRAVF_VESRAVG_VESRAVH  = 587,
    VESRL_VESRLB_VESRLF_VESRLG_VESRLH = 588,
    VESRLV_VESRLVB_VESRLVF_VESRLVG_VESRLVH  = 589,
    VSL_VSLDB = 590,
    VSLB  = 591,
    VSRA_VSRL = 592,
    VSRAB_VSRLB = 593,
    VSB_VSBCBI_VSBCBIQ_VSBI_VSBIQ = 594,
    VSCBI_VSCBIB_VSCBIF_VSCBIG_VSCBIH_VSCBIQ  = 595,
    VS_VSF_VSG_VSH_VSQ  = 596,
    VSUM_VSUMB_VSUMH  = 597,
    VSUMG_VSUMGF_VSUMGH = 598,
    VSUMQ_VSUMQF_VSUMQG = 599,
    VEC_VECB_VECF_VECG_VECH = 600,
    VECL_VECLB_VECLF_VECLG_VECLH  = 601,
    VCEQ_VCEQB_VCEQF_VCEQG_VCEQH  = 602,
    VCEQBS_VCEQFS_VCEQGS_VCEQHS = 603,
    VCH_VCHB_VCHF_VCHG_VCHH = 604,
    VCHBS_VCHFS_VCHGS_VCHHS = 605,
    VCHL_VCHLB_VCHLF_VCHLG_VCHLH  = 606,
    VCHLBS_VCHLFS_VCHLGS_VCHLHS = 607,
    VTM = 608,
    VCDG_VCDLG  = 609,
    VCDGB_VCDLGB  = 610,
    WCDGB_WCDLGB  = 611,
    VCGD_VCLGD  = 612,
    VCGDB_VCLGDB  = 613,
    WCGDB_WCLGDB  = 614,
    VLDE_VLED = 615,
    VLDEB_VLEDB = 616,
    WLDEB_WLEDB = 617,
    VFLL_VFLR = 618,
    VFLLS_VFLRD = 619,
    WFLLS_WFLRD = 620,
    WFLLD = 621,
    WFLRX = 622,
    VFI = 623,
    VFIDB = 624,
    WFIDB = 625,
    VFISB = 626,
    WFISB = 627,
    WFIXB = 628,
    VFPSO = 629,
    VFPSODB_WFPSODB = 630,
    VFPSOSB_WFPSOSB = 631,
    WFPSOXB = 632,
    VFLCDB_VFLNDB_VFLPDB_WFLCDB_WFLNDB_WFLPDB = 633,
    VFLCSB_VFLNSB_VFLPSB_WFLCSB_WFLNSB_WFLPSB = 634,
    WFLCXB_WFLNXB_WFLPXB  = 635,
    VFMAX_VFMIN = 636,
    VFMAXDB_VFMINDB = 637,
    WFMAXDB_WFMINDB = 638,
    VFMAXSB_VFMINSB = 639,
    WFMAXSB_WFMINSB = 640,
    WFMAXXB_WFMINXB = 641,
    VFTCI = 642,
    VFTCIDB_WFTCIDB = 643,
    VFTCISB_WFTCISB = 644,
    WFTCIXB = 645,
    VFA_VFS = 646,
    VFADB_VFSDB = 647,
    WFADB_WFSDB = 648,
    VFASB_VFSSB = 649,
    WFASB_WFSSB = 650,
    WFAXB_WFSXB = 651,
    VFM = 652,
    VFMDB = 653,
    WFMDB_WFMSB = 654,
    VFMSB = 655,
    WFMXB = 656,
    VFMA_VFMS_VFNMA_VFNMS = 657,
    VFMADB_VFMSDB_VFNMADB_VFNMSDB = 658,
    WFMADB_WFMSDB_WFNMADB_WFNMSDB = 659,
    VFMASB_VFMSSB_VFNMASB_VFNMSSB = 660,
    WFMASB_WFMSSB_WFNMASB_WFNMSSB = 661,
    WFMAXB_WFMSXB_WFNMAXB_WFNMSXB = 662,
    VFD = 663,
    VFDDB_WFDDB = 664,
    VFDSB_WFDSB = 665,
    WFDXB = 666,
    VFSQ  = 667,
    VFSQDB_WFSQDB = 668,
    VFSQSB_WFSQSB = 669,
    WFSQXB  = 670,
    VFCE_VFCH_VFCHE = 671,
    VFCEDB_VFCHDB_VFCHEDB_VFKEDB_VFKHDB_VFKHEDB = 672,
    WFCEDB_WFCHDB_WFCHEDB = 673,
    WFKEDB_WFKHDB_WFKHEDB = 674,
    VFCESB_VFCHESB_VFCHSB_VFKESB_VFKHESB_VFKHSB = 675,
    WFCESB_WFCHESB_WFCHSB = 676,
    WFKESB_WFKHESB_WFKHSB = 677,
    WFCEXB_WFCHEXB_WFCHXB = 678,
    WFKEXB_WFKHEXB_WFKHXB = 679,
    VFCEDBS_VFCHDBS_VFCHEDBS  = 680,
    VFKEDBS_VFKHDBS_VFKHEDBS  = 681,
    WFCEDBS_WFCHDBS_WFCHEDBS_WFKEDBS_WFKHDBS_WFKHEDBS = 682,
    VFCESBS_VFCHESBS_VFCHSBS_VFKESBS_VFKHESBS_VFKHSBS = 683,
    WFCESBS_WFCHESBS_WFCHSBS  = 684,
    WFKESBS_WFKHESBS_WFKHSBS  = 685,
    WFCEXBS_WFCHEXBS_WFCHXBS  = 686,
    WFKEXBS_WFKHEXBS_WFKHXBS  = 687,
    WFC_WFK = 688,
    WFCDB_WFKDB = 689,
    WFCSB_WFKSB = 690,
    WFCXB_WFKXB = 691,
    LEFR  = 692,
    LFER  = 693,
    VFAE_VFAEB  = 694,
    VFAEF_VFAEH = 695,
    VFAEBS_VFAEFS_VFAEHS  = 696,
    VFAEZB_VFAEZF_VFAEZH  = 697,
    VFAEZBS_VFAEZFS_VFAEZHS = 698,
    VFEE_VFEEB_VFEEF_VFEEH_VFEEZB_VFEEZF_VFEEZH = 699,
    VFEEBS_VFEEFS_VFEEHS_VFEEZBS_VFEEZFS_VFEEZHS  = 700,
    VFENE_VFENEB_VFENEF_VFENEH_VFENEZB_VFENEZF_VFENEZH  = 701,
    VFENEBS_VFENEFS_VFENEHS_VFENEZBS_VFENEZFS_VFENEZHS  = 702,
    VISTR_VISTRB_VISTRF_VISTRH  = 703,
    VISTRBS_VISTRFS_VISTRHS = 704,
    VSTRC_VSTRCB_VSTRCF_VSTRCH  = 705,
    VSTRCBS_VSTRCFS_VSTRCHS = 706,
    VSTRCZB_VSTRCZF_VSTRCZH = 707,
    VSTRCZBS_VSTRCZFS_VSTRCZHS  = 708,
    VLIP  = 709,
    VPKZ  = 710,
    VUPKZ = 711,
    VCVB_VCVBG  = 712,
    VCVD_VCVDG  = 713,
    VAP_VSP = 714,
    VMP_VMSP  = 715,
    VDP_VRP = 716,
    VSDP  = 717,
    VSRP  = 718,
    VPSOP = 719,
    VCP_VTP = 720,
    EPSW  = 721,
    LPSW_LPSWE  = 722,
    IPK = 723,
    SPKA  = 724,
    SSM = 725,
    STNSM_STOSM = 726,
    IAC = 727,
    SAC_SACF  = 728,
    LCTL_LCTLG  = 729,
    STCTG_STCTL = 730,
    EPAIR_EPAR_ESAIR_ESAR = 731,
    SSAIR_SSAR  = 732,
    ESEA  = 733,
    SPX_STPX  = 734,
    ISKE  = 735,
    IVSK  = 736,
    SSKE_SSKEOpt  = 737,
    RRBE_RRBM = 738,
    IRBM  = 739,
    PFMF  = 740,
    TB  = 741,
    PGIN  = 742,
    PGOUT = 743,
    IPTE_IPTEOpt_IPTEOptOpt = 744,
    IDTE_IDTEOpt  = 745,
    CRDTE_CRDTEOpt  = 746,
    PTLB  = 747,
    CSP_CSPG  = 748,
    LPTEA = 749,
    LRA_LRAG_LRAY = 750,
    STRAG = 751,
    LURA_LURAG  = 752,
    STURA_STURG = 753,
    TPROT = 754,
    MVCK_MVCP_MVCS  = 755,
    MVCDK_MVCSK = 756,
    MVCOS = 757,
    MVPG  = 758,
    LASP  = 759,
    PALB  = 760,
    PC  = 761,
    PR  = 762,
    PT_PTI  = 763,
    RP  = 764,
    BSA_BSG = 765,
    TAR = 766,
    BAKR  = 767,
    EREG_EREGG  = 768,
    ESTA_MSTA = 769,
    PTFF  = 770,
    SCK_SCKC_SCKPF  = 771,
    SPT = 772,
    STCK_STCKF  = 773,
    STCKE = 774,
    STCKC = 775,
    STPT  = 776,
    STAP  = 777,
    STIDP = 778,
    STSI  = 779,
    STFL_STFLE  = 780,
    ECAG  = 781,
    ECTG  = 782,
    PTF = 783,
    PCKMO = 784,
    SVC = 785,
    MC  = 786,
    DIAG  = 787,
    TRACE_TRACG = 788,
    TRAP2_TRAP4 = 789,
    SIGA_SIGP = 790,
    SIE = 791,
    LPP = 792,
    ECPGA = 793,
    ECCTR_EPCTR = 794,
    LCCTL = 795,
    LPCTL_LSCTL = 796,
    QCTRI_QSI = 797,
    SCCTR_SPCTR = 798,
    CSCH_HSCH_RSCH_XSCH = 799,
    MSCH_SSCH_STSCH_TSCH  = 800,
    RCHP  = 801,
    SCHM  = 802,
    STCPS_STCRW = 803,
    TPI = 804,
    SAL = 805,
    AGF = 806,
    SGF = 807,
    KM_KMC_KMCTR_KMF_KMO  = 808,
    PCC_PPNO  = 809,
    VLLEZ_VLLEZB_VLLEZF_VLLEZG_VLLEZH = 810,
    VN_VNC_VNO  = 811,
    VO  = 812,
    VPOPCT  = 813,
    WFMDB = 814,
    VFMA_VFMS = 815,
    VFMADB_VFMSDB = 816,
    WFMADB_WFMSDB = 817,
    VFCEDB_VFCHDB_VFCHEDB = 818,
    WFCEDBS_WFCHDBS_WFCHEDBS  = 819,
    LOCGR_LOCGRAsm_LOCGRAsmE_LOCGRAsmH_LOCGRAsmHE_LOCGRAsmL_LOCGRAsmLE_LOCGRAsmLH_LOCGRAsmM_LOCGRAsmNE_LOCGRAsmNH_LOCGRAsmNHE_LOCGRAsmNL_LOCGRAsmNLE_LOCGRAsmNLH_LOCGRAsmNM_LOCGRAsmNO_LOCGRAsmNP_LOCGRAsmNZ_LOCGRAsmO_LOCGRAsmP_LOCGRAsmZ_LOCR_LOCRAsm_LOCRAsmE_LOCRAsmH_LOCRAsmHE_LOCRAsmL_LOCRAsmLE_LOCRAsmLH_LOCRAsmM_LOCRAsmNE_LOCRAsmNH_LOCRAsmNHE_LOCRAsmNL_LOCRAsmNLE_LOCRAsmNLH_LOCRAsmNM_LOCRAsmNO_LOCRAsmNP_LOCRAsmNZ_LOCRAsmO_LOCRAsmP_LOCRAsmZ = 820,
    LOC_LOCAsm_LOCAsmE_LOCAsmH_LOCAsmHE_LOCAsmL_LOCAsmLE_LOCAsmLH_LOCAsmM_LOCAsmNE_LOCAsmNH_LOCAsmNHE_LOCAsmNL_LOCAsmNLE_LOCAsmNLH_LOCAsmNM_LOCAsmNO_LOCAsmNP_LOCAsmNZ_LOCAsmO_LOCAsmP_LOCAsmZ_LOCG_LOCGAsm_LOCGAsmE_LOCGAsmH_LOCGAsmHE_LOCGAsmL_LOCGAsmLE_LOCGAsmLH_LOCGAsmM_LOCGAsmNE_LOCGAsmNH_LOCGAsmNHE_LOCGAsmNL_LOCGAsmNLE_LOCGAsmNLH_LOCGAsmNM_LOCGAsmNO_LOCGAsmNP_LOCGAsmNZ_LOCGAsmO_LOCGAsmP_LOCGAsmZ = 821,
    STOC_STOCAsm_STOCAsmE_STOCAsmH_STOCAsmHE_STOCAsmL_STOCAsmLE_STOCAsmLH_STOCAsmM_STOCAsmNE_STOCAsmNH_STOCAsmNHE_STOCAsmNL_STOCAsmNLE_STOCAsmNLH_STOCAsmNM_STOCAsmNO_STOCAsmNP_STOCAsmNZ_STOCAsmO_STOCAsmP_STOCAsmZ_STOCG_STOCGAsm_STOCGAsmE_STOCGAsmH_STOCGAsmHE_STOCGAsmL_STOCGAsmLE_STOCGAsmLH_STOCGAsmM_STOCGAsmNE_STOCGAsmNH_STOCGAsmNHE_STOCGAsmNL_STOCGAsmNLE_STOCGAsmNLH_STOCGAsmNM_STOCGAsmNO_STOCGAsmNP_STOCGAsmNZ_STOCGAsmO_STOCGAsmP_STOCGAsmZ = 822,
    ALSI_ASI  = 823,
    ALGF  = 824,
    PCC = 825,
    CELFBR_CELGBR = 826,
    MD_MEE  = 827,
    MDR_MEER  = 828,
    CDFTR = 829,
    CXFTR = 830,
    CXLFTR  = 831,
    CFDTR = 832,
    CFXTR = 833,
    TDCDT_TDGDT = 834,
    SCK = 835,
    SCKPF = 836,
    RISBG_RISBG32 = 837,
    SCHED_LIST_END = 838
  };
} // end Sched namespace
} // end SystemZ namespace
} // end llvm namespace
#endif // GET_INSTRINFO_SCHED_ENUM

#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC
namespace llvm {

static const MCPhysReg ImplicitList1[] = { SystemZ::CC, 0 };
static const MCPhysReg ImplicitList2[] = { SystemZ::R1D, 0 };
static const MCPhysReg ImplicitList3[] = { SystemZ::R14D, SystemZ::CC, 0 };
static const MCPhysReg ImplicitList4[] = { SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, 0 };
static const MCPhysReg ImplicitList5[] = { SystemZ::CC, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, 0 };
static const MCPhysReg ImplicitList6[] = { SystemZ::R0L, 0 };
static const MCPhysReg ImplicitList7[] = { SystemZ::R0L, SystemZ::R1D, 0 };
static const MCPhysReg ImplicitList8[] = { SystemZ::CC, SystemZ::R1D, 0 };
static const MCPhysReg ImplicitList9[] = { SystemZ::R1L, 0 };
static const MCPhysReg ImplicitList10[] = { SystemZ::R0L, SystemZ::R1L, 0 };
static const MCPhysReg ImplicitList11[] = { SystemZ::R0D, SystemZ::R1D, 0 };
static const MCPhysReg ImplicitList12[] = { SystemZ::R2L, 0 };
static const MCPhysReg ImplicitList13[] = { SystemZ::R0L, SystemZ::F4Q, 0 };
static const MCPhysReg ImplicitList14[] = { SystemZ::CC, SystemZ::R1L, SystemZ::F0Q, 0 };
static const MCPhysReg ImplicitList15[] = { SystemZ::R1L, SystemZ::R2D, 0 };
static const MCPhysReg ImplicitList16[] = { SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, 0 };
static const MCPhysReg ImplicitList17[] = { SystemZ::R0D, 0 };
static const MCPhysReg ImplicitList18[] = { SystemZ::R0D, SystemZ::CC, 0 };
static const MCPhysReg ImplicitList19[] = { SystemZ::R0L, SystemZ::CC, 0 };
static const MCPhysReg ImplicitList20[] = { SystemZ::CC, SystemZ::R0L, SystemZ::R1D, 0 };
static const MCPhysReg ImplicitList21[] = { SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, 0 };
static const MCPhysReg ImplicitList22[] = { SystemZ::CC, SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R5D, 0 };

static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
static const MCOperandInfo OperandInfo31[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo32[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo33[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo34[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo35[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo36[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo37[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo38[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo39[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo40[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo41[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo42[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo43[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo44[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo45[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo46[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo47[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo48[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo49[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo50[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo51[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo52[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo53[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo54[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo55[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo56[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo57[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo58[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo59[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo60[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo61[] = { { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo62[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo63[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo64[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo65[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo66[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo67[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo68[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo69[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo70[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo71[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo72[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo73[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo74[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo75[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo76[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo77[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo78[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo79[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo80[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo81[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo82[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo83[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo84[] = { { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo85[] = { { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo86[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo87[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo88[] = { { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo89[] = { { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo90[] = { { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo91[] = { { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo92[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo93[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo94[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo95[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo96[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo97[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo98[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo99[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo100[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo101[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo102[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo103[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo104[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo105[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo106[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo107[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo108[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo109[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo110[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo111[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo112[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo113[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo114[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo115[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo116[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo117[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo118[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo119[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo120[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo121[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo122[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo123[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo124[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo125[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo126[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo127[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo128[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo129[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo130[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo131[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo132[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo133[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo134[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo135[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo136[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo137[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo138[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo139[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo140[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo141[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo142[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo143[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo144[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo145[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo146[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo147[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo148[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo149[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo150[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo151[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo152[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo153[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo154[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo155[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo156[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo157[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo158[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo159[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo160[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo161[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo162[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo163[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo164[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo165[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo166[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo167[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
static const MCOperandInfo OperandInfo168[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo169[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
static const MCOperandInfo OperandInfo170[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo171[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo172[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo173[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo174[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo175[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo176[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo177[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
static const MCOperandInfo OperandInfo178[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo179[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo180[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo181[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo182[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo183[] = { { SystemZ::AR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::AR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo184[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo185[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo186[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo187[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo188[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo189[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo190[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo191[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo192[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo193[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo194[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo195[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo196[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo197[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo198[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo199[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo200[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo201[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo202[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::AR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo203[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo204[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo205[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo206[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
static const MCOperandInfo OperandInfo207[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo208[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo209[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo210[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo211[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo212[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo213[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo214[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo215[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo216[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo217[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo218[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo219[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo220[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo221[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo222[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo223[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo224[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo225[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo226[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo227[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo228[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo229[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo230[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo231[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo232[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::AnyRegBitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo233[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
static const MCOperandInfo OperandInfo234[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((2 << 16) | (1 << MCOI::TIED_TO)) }, };
static const MCOperandInfo OperandInfo235[] = { { SystemZ::AR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::AR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo236[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo237[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo238[] = { { SystemZ::CR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::CR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo239[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo240[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo241[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo242[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo243[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo244[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo245[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo246[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo247[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo248[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo249[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo250[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo251[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo252[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo253[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo254[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo255[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo256[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo257[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo258[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo259[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo260[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo261[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo262[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo263[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo264[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo265[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo266[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo267[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo268[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo269[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo270[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo271[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo272[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo273[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo274[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo275[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo276[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo277[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo278[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo279[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo280[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo281[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo282[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo283[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo284[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo285[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo286[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo287[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo288[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo289[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
static const MCOperandInfo OperandInfo290[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo291[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
static const MCOperandInfo OperandInfo292[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo293[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo294[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo295[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo296[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo297[] = { { SystemZ::AR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo298[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo299[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo300[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo301[] = { { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo302[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo303[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo304[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo305[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo306[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo307[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo308[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo309[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo310[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
static const MCOperandInfo OperandInfo311[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo312[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo313[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
static const MCOperandInfo OperandInfo314[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo315[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo316[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo317[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo318[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo319[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo320[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo321[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo322[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo323[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo324[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo325[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo326[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo327[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo328[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo329[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo330[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo331[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo332[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo333[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo334[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo335[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo336[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo337[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo338[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo339[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo340[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo341[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo342[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo343[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo344[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo345[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo346[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo347[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo348[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo349[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo350[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo351[] = { { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo352[] = { { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo353[] = { { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo354[] = { { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo355[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo356[] = { { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo357[] = { { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo358[] = { { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo359[] = { { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo360[] = { { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo361[] = { { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo362[] = { { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo363[] = { { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo364[] = { { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };

extern const MCInstrDesc SystemZInsts[] = {
  { 0,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
  { 1,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
  { 2,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #2 = CFI_INSTRUCTION
  { 3,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = EH_LABEL
  { 4,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = GC_LABEL
  { 5,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = ANNOTATION_LABEL
  { 6,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #6 = KILL
  { 7,  3,  1,  0,  29, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #7 = EXTRACT_SUBREG
  { 8,  4,  1,  0,  30, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #8 = INSERT_SUBREG
  { 9,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #9 = IMPLICIT_DEF
  { 10, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #10 = SUBREG_TO_REG
  { 11, 3,  1,  0,  28, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #11 = COPY_TO_REGCLASS
  { 12, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #12 = DBG_VALUE
  { 13, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #13 = DBG_LABEL
  { 14, 2,  1,  0,  31, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #14 = REG_SEQUENCE
  { 15, 2,  1,  0,  28, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #15 = COPY
  { 16, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #16 = BUNDLE
  { 17, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #17 = LIFETIME_START
  { 18, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #18 = LIFETIME_END
  { 19, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #19 = STACKMAP
  { 20, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #20 = FENTRY_CALL
  { 21, 6,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #21 = PATCHPOINT
  { 22, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #22 = LOAD_STACK_GUARD
  { 23, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #23 = STATEPOINT
  { 24, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #24 = LOCAL_ESCAPE
  { 25, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #25 = FAULTING_OP
  { 26, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #26 = PATCHABLE_OP
  { 27, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #27 = PATCHABLE_FUNCTION_ENTER
  { 28, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #28 = PATCHABLE_RET
  { 29, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #29 = PATCHABLE_FUNCTION_EXIT
  { 30, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #30 = PATCHABLE_TAIL_CALL
  { 31, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #31 = PATCHABLE_EVENT_CALL
  { 32, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #32 = PATCHABLE_TYPED_EVENT_CALL
  { 33, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #33 = ICALL_BRANCH_FUNNEL
  { 34, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #34 = G_ADD
  { 35, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #35 = G_SUB
  { 36, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #36 = G_MUL
  { 37, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #37 = G_SDIV
  { 38, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #38 = G_UDIV
  { 39, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #39 = G_SREM
  { 40, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #40 = G_UREM
  { 41, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_AND
  { 42, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_OR
  { 43, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #43 = G_XOR
  { 44, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #44 = G_IMPLICIT_DEF
  { 45, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #45 = G_PHI
  { 46, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #46 = G_FRAME_INDEX
  { 47, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #47 = G_GLOBAL_VALUE
  { 48, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #48 = G_EXTRACT
  { 49, 2,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #49 = G_UNMERGE_VALUES
  { 50, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #50 = G_INSERT
  { 51, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #51 = G_MERGE_VALUES
  { 52, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #52 = G_PTRTOINT
  { 53, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = G_INTTOPTR
  { 54, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #54 = G_BITCAST
  { 55, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #55 = G_INTRINSIC_TRUNC
  { 56, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #56 = G_INTRINSIC_ROUND
  { 57, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #57 = G_LOAD
  { 58, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #58 = G_SEXTLOAD
  { 59, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #59 = G_ZEXTLOAD
  { 60, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #60 = G_STORE
  { 61, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #61 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
  { 62, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #62 = G_ATOMIC_CMPXCHG
  { 63, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #63 = G_ATOMICRMW_XCHG
  { 64, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #64 = G_ATOMICRMW_ADD
  { 65, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #65 = G_ATOMICRMW_SUB
  { 66, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #66 = G_ATOMICRMW_AND
  { 67, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #67 = G_ATOMICRMW_NAND
  { 68, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #68 = G_ATOMICRMW_OR
  { 69, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #69 = G_ATOMICRMW_XOR
  { 70, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #70 = G_ATOMICRMW_MAX
  { 71, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #71 = G_ATOMICRMW_MIN
  { 72, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #72 = G_ATOMICRMW_UMAX
  { 73, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #73 = G_ATOMICRMW_UMIN
  { 74, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #74 = G_BRCOND
  { 75, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #75 = G_BRINDIRECT
  { 76, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #76 = G_INTRINSIC
  { 77, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #77 = G_INTRINSIC_W_SIDE_EFFECTS
  { 78, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #78 = G_ANYEXT
  { 79, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #79 = G_TRUNC
  { 80, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #80 = G_CONSTANT
  { 81, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #81 = G_FCONSTANT
  { 82, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #82 = G_VASTART
  { 83, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #83 = G_VAARG
  { 84, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #84 = G_SEXT
  { 85, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #85 = G_ZEXT
  { 86, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #86 = G_SHL
  { 87, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #87 = G_LSHR
  { 88, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #88 = G_ASHR
  { 89, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #89 = G_ICMP
  { 90, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #90 = G_FCMP
  { 91, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #91 = G_SELECT
  { 92, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #92 = G_UADDO
  { 93, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #93 = G_UADDE
  { 94, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #94 = G_USUBO
  { 95, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #95 = G_USUBE
  { 96, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #96 = G_SADDO
  { 97, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #97 = G_SADDE
  { 98, 4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #98 = G_SSUBO
  { 99, 5,  2,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #99 = G_SSUBE
  { 100,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #100 = G_UMULO
  { 101,  4,  2,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #101 = G_SMULO
  { 102,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #102 = G_UMULH
  { 103,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #103 = G_SMULH
  { 104,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #104 = G_FADD
  { 105,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #105 = G_FSUB
  { 106,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #106 = G_FMUL
  { 107,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #107 = G_FMA
  { 108,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #108 = G_FDIV
  { 109,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #109 = G_FREM
  { 110,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #110 = G_FPOW
  { 111,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #111 = G_FEXP
  { 112,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #112 = G_FEXP2
  { 113,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #113 = G_FLOG
  { 114,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #114 = G_FLOG2
  { 115,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #115 = G_FNEG
  { 116,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #116 = G_FPEXT
  { 117,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #117 = G_FPTRUNC
  { 118,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #118 = G_FPTOSI
  { 119,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #119 = G_FPTOUI
  { 120,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #120 = G_SITOFP
  { 121,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #121 = G_UITOFP
  { 122,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #122 = G_FABS
  { 123,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #123 = G_GEP
  { 124,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #124 = G_PTR_MASK
  { 125,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #125 = G_BR
  { 126,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #126 = G_INSERT_VECTOR_ELT
  { 127,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #127 = G_EXTRACT_VECTOR_ELT
  { 128,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #128 = G_SHUFFLE_VECTOR
  { 129,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #129 = G_CTTZ
  { 130,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #130 = G_CTTZ_ZERO_UNDEF
  { 131,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #131 = G_CTLZ
  { 132,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #132 = G_CTLZ_ZERO_UNDEF
  { 133,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #133 = G_CTPOP
  { 134,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #134 = G_BSWAP
  { 135,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #135 = G_ADDRSPACE_CAST
  { 136,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #136 = G_BLOCK_ADDR
  { 137,  2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #137 = ADJCALLSTACKDOWN
  { 138,  2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #138 = ADJCALLSTACKUP
  { 139,  4,  1,  0,  1,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #139 = ADJDYNALLOC
  { 140,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #140 = AEXT128
  { 141,  3,  1,  0,  103,  0|(1ULL<<MCID::Pseudo), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #141 = AFIMux
  { 142,  3,  1,  0,  109,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #142 = AHIMux
  { 143,  3,  1,  0,  109,  0|(1ULL<<MCID::Pseudo), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #143 = AHIMuxK
  { 144,  8,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #144 = ATOMIC_CMP_SWAPW
  { 145,  7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #145 = ATOMIC_LOADW_AFI
  { 146,  7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #146 = ATOMIC_LOADW_AR
  { 147,  7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #147 = ATOMIC_LOADW_MAX
  { 148,  7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #148 = ATOMIC_LOADW_MIN
  { 149,  7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #149 = ATOMIC_LOADW_NILH
  { 150,  7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #150 = ATOMIC_LOADW_NILHi
  { 151,  7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #151 = ATOMIC_LOADW_NR
  { 152,  7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #152 = ATOMIC_LOADW_NRi
  { 153,  7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #153 = ATOMIC_LOADW_OILH
  { 154,  7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #154 = ATOMIC_LOADW_OR
  { 155,  7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #155 = ATOMIC_LOADW_SR
  { 156,  7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #156 = ATOMIC_LOADW_UMAX
  { 157,  7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #157 = ATOMIC_LOADW_UMIN
  { 158,  7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #158 = ATOMIC_LOADW_XILF
  { 159,  7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #159 = ATOMIC_LOADW_XR
  { 160,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #160 = ATOMIC_LOAD_AFI
  { 161,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #161 = ATOMIC_LOAD_AGFI
  { 162,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #162 = ATOMIC_LOAD_AGHI
  { 163,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #163 = ATOMIC_LOAD_AGR
  { 164,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #164 = ATOMIC_LOAD_AHI
  { 165,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #165 = ATOMIC_LOAD_AR
  { 166,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #166 = ATOMIC_LOAD_MAX_32
  { 167,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #167 = ATOMIC_LOAD_MAX_64
  { 168,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #168 = ATOMIC_LOAD_MIN_32
  { 169,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #169 = ATOMIC_LOAD_MIN_64
  { 170,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #170 = ATOMIC_LOAD_NGR
  { 171,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #171 = ATOMIC_LOAD_NGRi
  { 172,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #172 = ATOMIC_LOAD_NIHF64
  { 173,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #173 = ATOMIC_LOAD_NIHF64i
  { 174,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #174 = ATOMIC_LOAD_NIHH64
  { 175,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #175 = ATOMIC_LOAD_NIHH64i
  { 176,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #176 = ATOMIC_LOAD_NIHL64
  { 177,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #177 = ATOMIC_LOAD_NIHL64i
  { 178,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #178 = ATOMIC_LOAD_NILF
  { 179,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #179 = ATOMIC_LOAD_NILF64
  { 180,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #180 = ATOMIC_LOAD_NILF64i
  { 181,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #181 = ATOMIC_LOAD_NILFi
  { 182,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #182 = ATOMIC_LOAD_NILH
  { 183,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #183 = ATOMIC_LOAD_NILH64
  { 184,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #184 = ATOMIC_LOAD_NILH64i
  { 185,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #185 = ATOMIC_LOAD_NILHi
  { 186,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #186 = ATOMIC_LOAD_NILL
  { 187,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #187 = ATOMIC_LOAD_NILL64
  { 188,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #188 = ATOMIC_LOAD_NILL64i
  { 189,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #189 = ATOMIC_LOAD_NILLi
  { 190,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #190 = ATOMIC_LOAD_NR
  { 191,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #191 = ATOMIC_LOAD_NRi
  { 192,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #192 = ATOMIC_LOAD_OGR
  { 193,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #193 = ATOMIC_LOAD_OIHF64
  { 194,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #194 = ATOMIC_LOAD_OIHH64
  { 195,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #195 = ATOMIC_LOAD_OIHL64
  { 196,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #196 = ATOMIC_LOAD_OILF
  { 197,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #197 = ATOMIC_LOAD_OILF64
  { 198,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #198 = ATOMIC_LOAD_OILH
  { 199,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #199 = ATOMIC_LOAD_OILH64
  { 200,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #200 = ATOMIC_LOAD_OILL
  { 201,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #201 = ATOMIC_LOAD_OILL64
  { 202,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #202 = ATOMIC_LOAD_OR
  { 203,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #203 = ATOMIC_LOAD_SGR
  { 204,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #204 = ATOMIC_LOAD_SR
  { 205,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #205 = ATOMIC_LOAD_UMAX_32
  { 206,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #206 = ATOMIC_LOAD_UMAX_64
  { 207,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #207 = ATOMIC_LOAD_UMIN_32
  { 208,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #208 = ATOMIC_LOAD_UMIN_64
  { 209,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #209 = ATOMIC_LOAD_XGR
  { 210,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #210 = ATOMIC_LOAD_XIHF64
  { 211,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #211 = ATOMIC_LOAD_XILF
  { 212,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #212 = ATOMIC_LOAD_XILF64
  { 213,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #213 = ATOMIC_LOAD_XR
  { 214,  7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #214 = ATOMIC_SWAPW
  { 215,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #215 = ATOMIC_SWAP_32
  { 216,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #216 = ATOMIC_SWAP_64
  { 217,  2,  0,  0,  212,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #217 = CFIMux
  { 218,  3,  0,  6,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #218 = CGIBCall
  { 219,  3,  0,  6,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #219 = CGIBReturn
  { 220,  3,  0,  6,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #220 = CGRBCall
  { 221,  3,  0,  6,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #221 = CGRBReturn
  { 222,  2,  0,  0,  212,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #222 = CHIMux
  { 223,  3,  0,  6,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #223 = CIBCall
  { 224,  3,  0,  6,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #224 = CIBReturn
  { 225,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #225 = CLCLoop
  { 226,  5,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #226 = CLCSequence
  { 227,  2,  0,  0,  221,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x103800ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #227 = CLFIMux
  { 228,  3,  0,  6,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #228 = CLGIBCall
  { 229,  3,  0,  6,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #229 = CLGIBReturn
  { 230,  3,  0,  6,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #230 = CLGRBCall
  { 231,  3,  0,  6,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #231 = CLGRBReturn
  { 232,  3,  0,  6,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #232 = CLIBCall
  { 233,  3,  0,  6,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #233 = CLIBReturn
  { 234,  4,  0,  0,  219,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x10388cULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #234 = CLMux
  { 235,  3,  0,  6,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #235 = CLRBCall
  { 236,  3,  0,  6,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #236 = CLRBReturn
  { 237,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr },  // Inst #237 = CLSTLoop
  { 238,  4,  0,  0,  210,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x388cULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #238 = CMux
  { 239,  3,  0,  6,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #239 = CRBCall
  { 240,  3,  0,  6,  12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #240 = CRBReturn
  { 241,  1,  0,  2,  20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, ImplicitList3, OperandInfo51, -1 ,nullptr },  // Inst #241 = CallBASR
  { 242,  2,  0,  2,  4,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x40000ULL, ImplicitList2, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #242 = CallBCR
  { 243,  0,  0,  2,  5,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, nullptr, -1 ,nullptr },  // Inst #243 = CallBR
  { 244,  1,  0,  6,  19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr },  // Inst #244 = CallBRASL
  { 245,  3,  0,  6,  2,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x40000ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #245 = CallBRCL
  { 246,  1,  0,  6,  3,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #246 = CallJG
  { 247,  2,  0,  2,  23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator), 0x40000ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #247 = CondReturn
  { 248,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #248 = CondStore16
  { 249,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #249 = CondStore16Inv
  { 250,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #250 = CondStore16Mux
  { 251,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #251 = CondStore16MuxInv
  { 252,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #252 = CondStore32
  { 253,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #253 = CondStore32Inv
  { 254,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #254 = CondStore32Mux
  { 255,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #255 = CondStore32MuxInv
  { 256,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #256 = CondStore64
  { 257,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #257 = CondStore64Inv
  { 258,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #258 = CondStore8
  { 259,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #259 = CondStore8Inv
  { 260,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #260 = CondStore8Mux
  { 261,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #261 = CondStore8MuxInv
  { 262,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #262 = CondStoreF32
  { 263,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #263 = CondStoreF32Inv
  { 264,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #264 = CondStoreF64
  { 265,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #265 = CondStoreF64Inv
  { 266,  2,  0,  4,  13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #266 = CondTrap
  { 267,  1,  1,  6,  84, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #267 = GOT
  { 268,  2,  1,  0,  93, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #268 = IIFMux
  { 269,  3,  1,  6,  94, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #269 = IIHF64
  { 270,  3,  1,  4,  95, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #270 = IIHH64
  { 271,  3,  1,  4,  96, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #271 = IIHL64
  { 272,  3,  1,  0,  93, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #272 = IIHMux
  { 273,  3,  1,  6,  97, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #273 = IILF64
  { 274,  3,  1,  4,  98, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #274 = IILH64
  { 275,  3,  1,  4,  99, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #275 = IILL64
  { 276,  3,  1,  0,  93, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #276 = IILMux
  { 277,  4,  1,  0,  35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x1dULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #277 = L128
  { 278,  4,  1,  0,  58, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x2cULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #278 = LBMux
  { 279,  2,  1,  6,  692,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #279 = LEFR
  { 280,  2,  1,  6,  693,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #280 = LFER
  { 281,  2,  1,  0,  39, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #281 = LHIMux
  { 282,  4,  1,  0,  60, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4cULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #282 = LHMux
  { 283,  4,  1,  0,  66, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x2cULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #283 = LLCMux
  { 284,  2,  1,  0,  63, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #284 = LLCRMux
  { 285,  4,  1,  0,  67, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4cULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #285 = LLHMux
  { 286,  2,  1,  0,  64, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #286 = LLHRMux
  { 287,  4,  1,  0,  32, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x8dULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #287 = LMux
  { 288,  5,  1,  0,  51, 0|(1ULL<<MCID::Pseudo), 0x80000ULL, ImplicitList1, nullptr, OperandInfo64, -1 ,nullptr },  // Inst #288 = LOCHIMux
  { 289,  6,  1,  0,  52, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80080ULL, ImplicitList1, nullptr, OperandInfo65, -1 ,nullptr },  // Inst #289 = LOCMux
  { 290,  5,  1,  0,  49, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x80000ULL, ImplicitList1, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #290 = LOCRMux
  { 291,  2,  1,  0,  40, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #291 = LRMux
  { 292,  2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #292 = LTDBRCompare_VecPseudo
  { 293,  2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo68, -1 ,nullptr },  // Inst #293 = LTEBRCompare_VecPseudo
  { 294,  2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo69, -1 ,nullptr },  // Inst #294 = LTXBRCompare_VecPseudo
  { 295,  4,  1,  0,  341,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x1dULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #295 = LX
  { 296,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #296 = MVCLoop
  { 297,  5,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #297 = MVCSequence
  { 298,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr },  // Inst #298 = MVSTLoop
  { 299,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #299 = MemBarrier
  { 300,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #300 = NCLoop
  { 301,  5,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #301 = NCSequence
  { 302,  3,  1,  0,  143,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x23000ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #302 = NIFMux
  { 303,  3,  1,  6,  145,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #303 = NIHF64
  { 304,  3,  1,  4,  146,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #304 = NIHH64
  { 305,  3,  1,  4,  147,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #305 = NIHL64
  { 306,  3,  1,  0,  143,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #306 = NIHMux
  { 307,  3,  1,  6,  148,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #307 = NILF64
  { 308,  3,  1,  4,  149,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #308 = NILH64
  { 309,  3,  1,  4,  150,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #309 = NILL64
  { 310,  3,  1,  0,  143,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #310 = NILMux
  { 311,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #311 = OCLoop
  { 312,  5,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #312 = OCSequence
  { 313,  3,  1,  0,  156,  0|(1ULL<<MCID::Pseudo), 0x23000ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #313 = OIFMux
  { 314,  3,  1,  6,  157,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #314 = OIHF64
  { 315,  3,  1,  4,  158,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #315 = OIHH64
  { 316,  3,  1,  4,  159,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #316 = OIHL64
  { 317,  3,  1,  0,  156,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #317 = OIHMux
  { 318,  3,  1,  6,  160,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #318 = OILF64
  { 319,  3,  1,  4,  161,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #319 = OILH64
  { 320,  3,  1,  4,  162,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #320 = OILL64
  { 321,  3,  1,  0,  156,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #321 = OILMux
  { 322,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #322 = PAIR128
  { 323,  6,  1,  6,  206,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #323 = RISBHH
  { 324,  6,  1,  6,  206,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr },  // Inst #324 = RISBHL
  { 325,  6,  1,  6,  207,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr },  // Inst #325 = RISBLH
  { 326,  6,  1,  6,  207,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr },  // Inst #326 = RISBLL
  { 327,  6,  1,  0,  208,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr },  // Inst #327 = RISBMux
  { 328,  0,  0,  2,  22, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #328 = Return
  { 329,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr },  // Inst #329 = SRSTLoop
  { 330,  4,  0,  0,  46, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1eULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #330 = ST128
  { 331,  4,  0,  0,  73, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x2cULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #331 = STCMux
  { 332,  4,  0,  0,  74, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x2cULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #332 = STHMux
  { 333,  4,  0,  0,  47, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8eULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #333 = STMux
  { 334,  5,  0,  0,  53, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80080ULL, ImplicitList1, nullptr, OperandInfo77, -1 ,nullptr },  // Inst #334 = STOCMux
  { 335,  4,  0,  0,  343,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1eULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #335 = STX
  { 336,  5,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo78, -1 ,nullptr },  // Inst #336 = Select32
  { 337,  5,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #337 = Select64
  { 338,  5,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #338 = SelectF128
  { 339,  5,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #339 = SelectF32
  { 340,  5,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #340 = SelectF64
  { 341,  5,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #341 = SelectVR128
  { 342,  5,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo84, -1 ,nullptr },  // Inst #342 = SelectVR32
  { 343,  5,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo85, -1 ,nullptr },  // Inst #343 = SelectVR64
  { 344,  0,  0,  2,  259,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #344 = Serialize
  { 345,  3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo86, -1 ,nullptr },  // Inst #345 = TBEGIN_nofloat
  { 346,  1,  0,  6,  21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr },  // Inst #346 = TLS_GDCALL
  { 347,  1,  0,  6,  21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr },  // Inst #347 = TLS_LDCALL
  { 348,  2,  0,  4,  250,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr },  // Inst #348 = TMHH64
  { 349,  2,  0,  4,  251,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr },  // Inst #349 = TMHL64
  { 350,  2,  0,  0,  249,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #350 = TMHMux
  { 351,  2,  0,  4,  252,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr },  // Inst #351 = TMLH64
  { 352,  2,  0,  4,  253,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr },  // Inst #352 = TMLL64
  { 353,  2,  0,  0,  249,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #353 = TMLMux
  { 354,  0,  0,  4,  13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #354 = Trap
  { 355,  4,  1,  6,  516,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #355 = VL32
  { 356,  4,  1,  6,  516,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #356 = VL64
  { 357,  2,  1,  6,  504,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #357 = VLR32
  { 358,  2,  1,  6,  504,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #358 = VLR64
  { 359,  3,  1,  6,  507,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #359 = VLVGP32
  { 360,  4,  0,  6,  523,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #360 = VST32
  { 361,  4,  0,  6,  523,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #361 = VST64
  { 362,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #362 = XCLoop
  { 363,  5,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #363 = XCSequence
  { 364,  3,  1,  0,  167,  0|(1ULL<<MCID::Pseudo), 0x23000ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #364 = XIFMux
  { 365,  3,  1,  6,  169,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #365 = XIHF64
  { 366,  3,  1,  6,  170,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #366 = XILF64
  { 367,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #367 = ZEXT128
  { 368,  5,  1,  4,  100,  0|(1ULL<<MCID::MayLoad), 0x23c88ULL, nullptr, ImplicitList1, OperandInfo93, -1 ,nullptr },  // Inst #368 = A
  { 369,  5,  1,  4,  422,  0|(1ULL<<MCID::MayLoad), 0x108ULL, nullptr, ImplicitList1, OperandInfo94, -1 ,nullptr },  // Inst #369 = AD
  { 370,  5,  1,  6,  368,  0|(1ULL<<MCID::MayLoad), 0x3fd08ULL, nullptr, ImplicitList1, OperandInfo94, -1 ,nullptr },  // Inst #370 = ADB
  { 371,  3,  1,  4,  369,  0|(1ULL<<MCID::Commutable), 0x3fc00ULL, nullptr, ImplicitList1, OperandInfo95, -1 ,nullptr },  // Inst #371 = ADBR
  { 372,  3,  1,  2,  423,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo95, -1 ,nullptr },  // Inst #372 = ADR
  { 373,  3,  1,  4,  482,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo96, -1 ,nullptr },  // Inst #373 = ADTR
  { 374,  4,  1,  4,  482,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo97, -1 ,nullptr },  // Inst #374 = ADTRA
  { 375,  5,  1,  4,  422,  0|(1ULL<<MCID::MayLoad), 0x88ULL, nullptr, ImplicitList1, OperandInfo98, -1 ,nullptr },  // Inst #375 = AE
  { 376,  5,  1,  6,  368,  0|(1ULL<<MCID::MayLoad), 0x3fc88ULL, nullptr, ImplicitList1, OperandInfo98, -1 ,nullptr },  // Inst #376 = AEB
  { 377,  3,  1,  4,  369,  0|(1ULL<<MCID::Commutable), 0x3fc00ULL, nullptr, ImplicitList1, OperandInfo99, -1 ,nullptr },  // Inst #377 = AEBR
  { 378,  3,  1,  2,  423,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo99, -1 ,nullptr },  // Inst #378 = AER
  { 379,  3,  1,  6,  103,  0, 0x23c00ULL, nullptr, ImplicitList1, OperandInfo100, -1 ,nullptr },  // Inst #379 = AFI
  { 380,  5,  1,  6,  104,  0|(1ULL<<MCID::MayLoad), 0x23d0cULL, nullptr, ImplicitList1, OperandInfo101, -1 ,nullptr },  // Inst #380 = AG
  { 381,  5,  1,  6,  806,  0|(1ULL<<MCID::MayLoad), 0x23c8cULL, nullptr, ImplicitList1, OperandInfo101, -1 ,nullptr },  // Inst #381 = AGF
  { 382,  3,  1,  6,  105,  0, 0x23c00ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #382 = AGFI
  { 383,  3,  1,  4,  125,  0, 0x23c00ULL, nullptr, ImplicitList1, OperandInfo102, -1 ,nullptr },  // Inst #383 = AGFR
  { 384,  5,  1,  6,  124,  0|(1ULL<<MCID::MayLoad), 0x23c4cULL, nullptr, ImplicitList1, OperandInfo101, -1 ,nullptr },  // Inst #384 = AGH
  { 385,  3,  1,  4,  106,  0|(1ULL<<MCID::ConvertibleTo3Addr), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #385 = AGHI
  { 386,  3,  1,  6,  106,  0, 0x23c00ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #386 = AGHIK
  { 387,  3,  1,  4,  107,  0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo103, -1 ,nullptr },  // Inst #387 = AGR
  { 388,  3,  1,  4,  107,  0|(1ULL<<MCID::Commutable), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo104, -1 ,nullptr },  // Inst #388 = AGRK
  { 389,  3,  0,  6,  121,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x23c04ULL, nullptr, ImplicitList1, OperandInfo86, -1 ,nullptr },  // Inst #389 = AGSI
  { 390,  5,  1,  4,  101,  0|(1ULL<<MCID::MayLoad), 0x23c48ULL, nullptr, ImplicitList1, OperandInfo93, -1 ,nullptr },  // Inst #390 = AH
  { 391,  3,  1,  4,  118,  0, 0x23c00ULL, nullptr, ImplicitList1, OperandInfo105, -1 ,nullptr },  // Inst #391 = AHHHR
  { 392,  3,  1,  4,  119,  0, 0x23c00ULL, nullptr, ImplicitList1, OperandInfo106, -1 ,nullptr },  // Inst #392 = AHHLR
  { 393,  3,  1,  4,  108,  0|(1ULL<<MCID::ConvertibleTo3Addr), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo100, -1 ,nullptr },  // Inst #393 = AHI
  { 394,  3,  1,  6,  108,  0, 0x23c00ULL, nullptr, ImplicitList1, OperandInfo49, -1 ,nullptr },  // Inst #394 = AHIK
  { 395,  5,  1,  6,  101,  0|(1ULL<<MCID::MayLoad), 0x23c4cULL, nullptr, ImplicitList1, OperandInfo93, -1 ,nullptr },  // Inst #395 = AHY
  { 396,  3,  1,  6,  102,  0, 0x23c00ULL, nullptr, ImplicitList1, OperandInfo107, -1 ,nullptr },  // Inst #396 = AIH
  { 397,  5,  1,  4,  110,  0|(1ULL<<MCID::MayLoad), 0x88ULL, nullptr, ImplicitList1, OperandInfo93, -1 ,nullptr },  // Inst #397 = AL
  { 398,  5,  1,  6,  122,  0|(1ULL<<MCID::MayLoad), 0x8cULL, ImplicitList1, ImplicitList1, OperandInfo93, -1 ,nullptr },  // Inst #398 = ALC
  { 399,  5,  1,  6,  122,  0|(1ULL<<MCID::MayLoad), 0x10cULL, ImplicitList1, ImplicitList1, OperandInfo101, -1 ,nullptr },  // Inst #399 = ALCG
  { 400,  3,  1,  4,  123,  0, 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo103, -1 ,nullptr },  // Inst #400 = ALCGR
  { 401,  3,  1,  4,  123,  0, 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo108, -1 ,nullptr },  // Inst #401 = ALCR
  { 402,  3,  1,  6,  111,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo100, -1 ,nullptr },  // Inst #402 = ALFI
  { 403,  5,  1,  6,  112,  0|(1ULL<<MCID::MayLoad), 0x10cULL, nullptr, ImplicitList1, OperandInfo101, -1 ,nullptr },  // Inst #403 = ALG
  { 404,  5,  1,  6,  824,  0|(1ULL<<MCID::MayLoad), 0x8cULL, nullptr, ImplicitList1, OperandInfo101, -1 ,nullptr },  // Inst #404 = ALGF
  { 405,  3,  1,  6,  114,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #405 = ALGFI
  { 406,  3,  1,  4,  114,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo102, -1 ,nullptr },  // Inst #406 = ALGFR
  { 407,  3,  1,  6,  113,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #407 = ALGHSIK
  { 408,  3,  1,  4,  115,  0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo103, -1 ,nullptr },  // Inst #408 = ALGR
  { 409,  3,  1,  4,  115,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo104, -1 ,nullptr },  // Inst #409 = ALGRK
  { 410,  3,  0,  6,  121,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, ImplicitList1, OperandInfo86, -1 ,nullptr },  // Inst #410 = ALGSI
  { 411,  3,  1,  4,  118,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo105, -1 ,nullptr },  // Inst #411 = ALHHHR
  { 412,  3,  1,  4,  119,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo106, -1 ,nullptr },  // Inst #412 = ALHHLR
  { 413,  3,  1,  6,  111,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo49, -1 ,nullptr },  // Inst #413 = ALHSIK
  { 414,  3,  1,  2,  116,  0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo108, -1 ,nullptr },  // Inst #414 = ALR
  { 415,  3,  1,  4,  116,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo109, -1 ,nullptr },  // Inst #415 = ALRK
  { 416,  3,  0,  6,  823,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, ImplicitList1, OperandInfo86, -1 ,nullptr },  // Inst #416 = ALSI
  { 417,  3,  1,  6,  120,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo107, -1 ,nullptr },  // Inst #417 = ALSIH
  { 418,  3,  1,  6,  120,  0, 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #418 = ALSIHN
  { 419,  5,  1,  6,  110,  0|(1ULL<<MCID::MayLoad), 0x8cULL, nullptr, ImplicitList1, OperandInfo93, -1 ,nullptr },  // Inst #419 = ALY
  { 420,  6,  0,  6,  296,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, ImplicitList1, OperandInfo110, -1 ,nullptr },  // Inst #420 = AP
  { 421,  3,  1,  2,  117,  0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo108, -1 ,nullptr },  // Inst #421 = AR
  { 422,  3,  1,  4,  117,  0|(1ULL<<MCID::Commutable), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo109, -1 ,nullptr },  // Inst #422 = ARK
  { 423,  3,  0,  6,  823,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x23c04ULL, nullptr, ImplicitList1, OperandInfo86, -1 ,nullptr },  // Inst #423 = ASI
  { 424,  5,  1,  4,  422,  0|(1ULL<<MCID::MayLoad), 0x88ULL, nullptr, ImplicitList1, OperandInfo98, -1 ,nullptr },  // Inst #424 = AU
  { 425,  3,  1,  2,  423,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo99, -1 ,nullptr },  // Inst #425 = AUR
  { 426,  5,  1,  4,  422,  0|(1ULL<<MCID::MayLoad), 0x108ULL, nullptr, ImplicitList1, OperandInfo94, -1 ,nullptr },  // Inst #426 = AW
  { 427,  3,  1,  2,  423,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo95, -1 ,nullptr },  // Inst #427 = AWR
  { 428,  3,  1,  4,  370,  0|(1ULL<<MCID::Commutable), 0x3fc00ULL, nullptr, ImplicitList1, OperandInfo111, -1 ,nullptr },  // Inst #428 = AXBR
  { 429,  3,  1,  2,  424,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo111, -1 ,nullptr },  // Inst #429 = AXR
  { 430,  3,  1,  4,  483,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo112, -1 ,nullptr },  // Inst #430 = AXTR
  { 431,  4,  1,  4,  483,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo113, -1 ,nullptr },  // Inst #431 = AXTRA
  { 432,  5,  1,  6,  100,  0|(1ULL<<MCID::MayLoad), 0x23c8cULL, nullptr, ImplicitList1, OperandInfo93, -1 ,nullptr },  // Inst #432 = AY
  { 433,  3,  0,  4,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x8ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #433 = B
  { 434,  2,  0,  4,  767,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #434 = BAKR
  { 435,  4,  0,  4,  308,  0|(1ULL<<MCID::Call), 0x8ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #435 = BAL
  { 436,  2,  0,  2,  308,  0|(1ULL<<MCID::Call), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo116, -1 ,nullptr },  // Inst #436 = BALR
  { 437,  4,  0,  4,  20, 0|(1ULL<<MCID::Call), 0x8ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #437 = BAS
  { 438,  2,  0,  2,  20, 0|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr },  // Inst #438 = BASR
  { 439,  2,  0,  2,  312,  0|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr },  // Inst #439 = BASSM
  { 440,  3,  0,  4,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #440 = BAsmE
  { 441,  3,  0,  4,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #441 = BAsmH
  { 442,  3,  0,  4,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #442 = BAsmHE
  { 443,  3,  0,  4,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #443 = BAsmL
  { 444,  3,  0,  4,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #444 = BAsmLE
  { 445,  3,  0,  4,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #445 = BAsmLH
  { 446,  3,  0,  4,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #446 = BAsmM
  { 447,  3,  0,  4,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #447 = BAsmNE
  { 448,  3,  0,  4,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #448 = BAsmNH
  { 449,  3,  0,  4,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #449 = BAsmNHE
  { 450,  3,  0,  4,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #450 = BAsmNL
  { 451,  3,  0,  4,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #451 = BAsmNLE
  { 452,  3,  0,  4,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #452 = BAsmNLH
  { 453,  3,  0,  4,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #453 = BAsmNM
  { 454,  3,  0,  4,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #454 = BAsmNO
  { 455,  3,  0,  4,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #455 = BAsmNP
  { 456,  3,  0,  4,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #456 = BAsmNZ
  { 457,  3,  0,  4,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #457 = BAsmO
  { 458,  3,  0,  4,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #458 = BAsmP
  { 459,  3,  0,  4,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #459 = BAsmZ
  { 460,  5,  0,  4,  4,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x40008ULL, ImplicitList1, nullptr, OperandInfo117, -1 ,nullptr },  // Inst #460 = BC
  { 461,  4,  0,  4,  4,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #461 = BCAsm
  { 462,  3,  0,  2,  4,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x40000ULL, ImplicitList1, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #462 = BCR
  { 463,  2,  0,  2,  4,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #463 = BCRAsm
  { 464,  5,  1,  4,  9,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x8ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #464 = BCT
  { 465,  5,  1,  6,  9,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0xcULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #465 = BCTG
  { 466,  3,  1,  4,  9,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr },  // Inst #466 = BCTGR
  { 467,  3,  1,  2,  9,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #467 = BCTR
  { 468,  3,  0,  6,  6,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #468 = BI
  { 469,  3,  0,  6,  6,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #469 = BIAsmE
  { 470,  3,  0,  6,  6,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #470 = BIAsmH
  { 471,  3,  0,  6,  6,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #471 = BIAsmHE
  { 472,  3,  0,  6,  6,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #472 = BIAsmL
  { 473,  3,  0,  6,  6,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #473 = BIAsmLE
  { 474,  3,  0,  6,  6,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #474 = BIAsmLH
  { 475,  3,  0,  6,  6,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #475 = BIAsmM
  { 476,  3,  0,  6,  6,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #476 = BIAsmNE
  { 477,  3,  0,  6,  6,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #477 = BIAsmNH
  { 478,  3,  0,  6,  6,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #478 = BIAsmNHE
  { 479,  3,  0,  6,  6,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #479 = BIAsmNL
  { 480,  3,  0,  6,  6,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #480 = BIAsmNLE
  { 481,  3,  0,  6,  6,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #481 = BIAsmNLH
  { 482,  3,  0,  6,  6,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #482 = BIAsmNM
  { 483,  3,  0,  6,  6,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #483 = BIAsmNO
  { 484,  3,  0,  6,  6,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #484 = BIAsmNP
  { 485,  3,  0,  6,  6,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #485 = BIAsmNZ
  { 486,  3,  0,  6,  6,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #486 = BIAsmO
  { 487,  3,  0,  6,  6,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #487 = BIAsmP
  { 488,  3,  0,  6,  6,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #488 = BIAsmZ
  { 489,  5,  0,  6,  6,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x4000cULL, ImplicitList1, nullptr, OperandInfo117, -1 ,nullptr },  // Inst #489 = BIC
  { 490,  4,  0,  6,  6,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #490 = BICAsm
  { 491,  5,  0,  6,  256,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr },  // Inst #491 = BPP
  { 492,  3,  0,  6,  257,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #492 = BPRP
  { 493,  1,  0,  2,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #493 = BR
  { 494,  3,  0,  4,  18, 0|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #494 = BRAS
  { 495,  3,  0,  6,  19, 0|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #495 = BRASL
  { 496,  1,  0,  2,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #496 = BRAsmE
  { 497,  1,  0,  2,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #497 = BRAsmH
  { 498,  1,  0,  2,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #498 = BRAsmHE
  { 499,  1,  0,  2,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #499 = BRAsmL
  { 500,  1,  0,  2,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #500 = BRAsmLE
  { 501,  1,  0,  2,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #501 = BRAsmLH
  { 502,  1,  0,  2,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #502 = BRAsmM
  { 503,  1,  0,  2,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #503 = BRAsmNE
  { 504,  1,  0,  2,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #504 = BRAsmNH
  { 505,  1,  0,  2,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #505 = BRAsmNHE
  { 506,  1,  0,  2,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #506 = BRAsmNL
  { 507,  1,  0,  2,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #507 = BRAsmNLE
  { 508,  1,  0,  2,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #508 = BRAsmNLH
  { 509,  1,  0,  2,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #509 = BRAsmNM
  { 510,  1,  0,  2,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #510 = BRAsmNO
  { 511,  1,  0,  2,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #511 = BRAsmNP
  { 512,  1,  0,  2,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #512 = BRAsmNZ
  { 513,  1,  0,  2,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #513 = BRAsmO
  { 514,  1,  0,  2,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #514 = BRAsmP
  { 515,  1,  0,  2,  5,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #515 = BRAsmZ
  { 516,  3,  0,  4,  2,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x40000ULL, ImplicitList1, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #516 = BRC
  { 517,  2,  0,  4,  2,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #517 = BRCAsm
  { 518,  3,  0,  6,  2,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x40000ULL, ImplicitList1, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #518 = BRCL
  { 519,  2,  0,  6,  2,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #519 = BRCLAsm
  { 520,  3,  1,  4,  7,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo100, -1 ,nullptr },  // Inst #520 = BRCT
  { 521,  3,  1,  4,  7,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #521 = BRCTG
  { 522,  3,  1,  6,  8,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #522 = BRCTH
  { 523,  4,  1,  4,  10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo122, -1 ,nullptr },  // Inst #523 = BRXH
  { 524,  4,  1,  6,  10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo123, -1 ,nullptr },  // Inst #524 = BRXHG
  { 525,  4,  1,  4,  10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo122, -1 ,nullptr },  // Inst #525 = BRXLE
  { 526,  4,  1,  6,  10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo123, -1 ,nullptr },  // Inst #526 = BRXLG
  { 527,  2,  1,  4,  765,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #527 = BSA
  { 528,  2,  1,  4,  765,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #528 = BSG
  { 529,  2,  0,  2,  311,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #529 = BSM
  { 530,  5,  1,  4,  10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr },  // Inst #530 = BXH
  { 531,  5,  1,  6,  10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x4ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #531 = BXHG
  { 532,  5,  1,  4,  10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr },  // Inst #532 = BXLE
  { 533,  5,  1,  6,  10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x4ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #533 = BXLEG
  { 534,  4,  0,  4,  210,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3888ULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr },  // Inst #534 = C
  { 535,  4,  0,  4,  446,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x108ULL, nullptr, ImplicitList1, OperandInfo127, -1 ,nullptr },  // Inst #535 = CD
  { 536,  4,  0,  6,  387,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3d08ULL, nullptr, ImplicitList1, OperandInfo127, -1 ,nullptr },  // Inst #536 = CDB
  { 537,  2,  0,  4,  388,  0|(1ULL<<MCID::Compare), 0x3c00ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #537 = CDBR
  { 538,  2,  1,  4,  350,  0, 0x0ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr },  // Inst #538 = CDFBR
  { 539,  4,  1,  4,  350,  0, 0x0ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #539 = CDFBRA
  { 540,  2,  1,  4,  408,  0, 0x0ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr },  // Inst #540 = CDFR
  { 541,  4,  1,  4,  829,  0, 0x0ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #541 = CDFTR
  { 542,  2,  1,  4,  350,  0, 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr },  // Inst #542 = CDGBR
  { 543,  4,  1,  4,  350,  0, 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #543 = CDGBRA
  { 544,  2,  1,  4,  408,  0, 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr },  // Inst #544 = CDGR
  { 545,  2,  1,  4,  455,  0, 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr },  // Inst #545 = CDGTR
  { 546,  4,  1,  4,  455,  0, 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #546 = CDGTRA
  { 547,  4,  1,  4,  352,  0, 0x0ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #547 = CDLFBR
  { 548,  4,  1,  4,  457,  0, 0x0ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #548 = CDLFTR
  { 549,  4,  1,  4,  352,  0, 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #549 = CDLGBR
  { 550,  4,  1,  4,  457,  0, 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #550 = CDLGTR
  { 551,  5,  1,  6,  471,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr },  // Inst #551 = CDPT
  { 552,  2,  0,  2,  447,  0|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #552 = CDR
  { 553,  5,  1,  4,  267,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, ImplicitList1, OperandInfo133, -1 ,nullptr },  // Inst #553 = CDS
  { 554,  5,  1,  6,  268,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, ImplicitList1, OperandInfo133, -1 ,nullptr },  // Inst #554 = CDSG
  { 555,  2,  1,  4,  463,  0, 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr },  // Inst #555 = CDSTR
  { 556,  5,  1,  6,  267,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, ImplicitList1, OperandInfo133, -1 ,nullptr },  // Inst #556 = CDSY
  { 557,  2,  0,  4,  498,  0|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #557 = CDTR
  { 558,  2,  1,  4,  463,  0, 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr },  // Inst #558 = CDUTR
  { 559,  5,  1,  6,  467,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr },  // Inst #559 = CDZT
  { 560,  4,  0,  4,  446,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x88ULL, nullptr, ImplicitList1, OperandInfo134, -1 ,nullptr },  // Inst #560 = CE
  { 561,  4,  0,  6,  387,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3c88ULL, nullptr, ImplicitList1, OperandInfo134, -1 ,nullptr },  // Inst #561 = CEB
  { 562,  2,  0,  4,  388,  0|(1ULL<<MCID::Compare), 0x3c00ULL, nullptr, ImplicitList1, OperandInfo68, -1 ,nullptr },  // Inst #562 = CEBR
  { 563,  2,  0,  4,  500,  0|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #563 = CEDTR
  { 564,  2,  1,  4,  350,  0, 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #564 = CEFBR
  { 565,  4,  1,  4,  350,  0, 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #565 = CEFBRA
  { 566,  2,  1,  4,  408,  0, 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #566 = CEFR
  { 567,  2,  1,  4,  350,  0, 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #567 = CEGBR
  { 568,  4,  1,  4,  350,  0, 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr },  // Inst #568 = CEGBRA
  { 569,  2,  1,  4,  408,  0, 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #569 = CEGR
  { 570,  4,  1,  4,  826,  0, 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #570 = CELFBR
  { 571,  4,  1,  4,  826,  0, 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr },  // Inst #571 = CELGBR
  { 572,  2,  0,  2,  447,  0|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo68, -1 ,nullptr },  // Inst #572 = CER
  { 573,  2,  0,  4,  501,  0|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo69, -1 ,nullptr },  // Inst #573 = CEXTR
  { 574,  2,  0,  4,  323,  0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList4, ImplicitList5, OperandInfo139, -1 ,nullptr },  // Inst #574 = CFC
  { 575,  3,  1,  4,  354,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo140, -1 ,nullptr },  // Inst #575 = CFDBR
  { 576,  4,  1,  4,  354,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo141, -1 ,nullptr },  // Inst #576 = CFDBRA
  { 577,  3,  1,  4,  410,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo140, -1 ,nullptr },  // Inst #577 = CFDR
  { 578,  4,  1,  4,  832,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo141, -1 ,nullptr },  // Inst #578 = CFDTR
  { 579,  3,  1,  4,  354,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo142, -1 ,nullptr },  // Inst #579 = CFEBR
  { 580,  4,  1,  4,  354,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo143, -1 ,nullptr },  // Inst #580 = CFEBRA
  { 581,  3,  1,  4,  410,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo142, -1 ,nullptr },  // Inst #581 = CFER
  { 582,  2,  0,  6,  212,  0|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo144, -1 ,nullptr },  // Inst #582 = CFI
  { 583,  3,  1,  4,  355,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo145, -1 ,nullptr },  // Inst #583 = CFXBR
  { 584,  4,  1,  4,  355,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo146, -1 ,nullptr },  // Inst #584 = CFXBRA
  { 585,  3,  1,  4,  411,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo145, -1 ,nullptr },  // Inst #585 = CFXR
  { 586,  4,  1,  4,  833,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo146, -1 ,nullptr },  // Inst #586 = CFXTR
  { 587,  4,  0,  6,  210,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x390cULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #587 = CG
  { 588,  3,  1,  4,  354,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo147, -1 ,nullptr },  // Inst #588 = CGDBR
  { 589,  4,  1,  4,  354,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo148, -1 ,nullptr },  // Inst #589 = CGDBRA
  { 590,  3,  1,  4,  410,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo147, -1 ,nullptr },  // Inst #590 = CGDR
  { 591,  3,  1,  4,  459,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo147, -1 ,nullptr },  // Inst #591 = CGDTR
  { 592,  4,  1,  4,  459,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo148, -1 ,nullptr },  // Inst #592 = CGDTRA
  { 593,  3,  1,  4,  354,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo149, -1 ,nullptr },  // Inst #593 = CGEBR
  { 594,  4,  1,  4,  354,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo150, -1 ,nullptr },  // Inst #594 = CGEBRA
  { 595,  3,  1,  4,  410,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo149, -1 ,nullptr },  // Inst #595 = CGER
  { 596,  4,  0,  6,  242,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x388cULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #596 = CGF
  { 597,  2,  0,  6,  213,  0|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr },  // Inst #597 = CGFI
  { 598,  2,  0,  4,  244,  0|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo151, -1 ,nullptr },  // Inst #598 = CGFR
  { 599,  2,  0,  6,  243,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr },  // Inst #599 = CGFRL
  { 600,  4,  0,  6,  239,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x384cULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #600 = CGH
  { 601,  2,  0,  4,  213,  0|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr },  // Inst #601 = CGHI
  { 602,  2,  0,  6,  240,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr },  // Inst #602 = CGHRL
  { 603,  3,  0,  6,  214,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL, nullptr, ImplicitList1, OperandInfo86, -1 ,nullptr },  // Inst #603 = CGHSI
  { 604,  5,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #604 = CGIB
  { 605,  5,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #605 = CGIBAsm
  { 606,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #606 = CGIBAsmE
  { 607,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #607 = CGIBAsmH
  { 608,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #608 = CGIBAsmHE
  { 609,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #609 = CGIBAsmL
  { 610,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #610 = CGIBAsmLE
  { 611,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #611 = CGIBAsmLH
  { 612,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #612 = CGIBAsmNE
  { 613,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #613 = CGIBAsmNH
  { 614,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #614 = CGIBAsmNHE
  { 615,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #615 = CGIBAsmNL
  { 616,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #616 = CGIBAsmNLE
  { 617,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #617 = CGIBAsmNLH
  { 618,  4,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo154, -1 ,nullptr },  // Inst #618 = CGIJ
  { 619,  4,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo154, -1 ,nullptr },  // Inst #619 = CGIJAsm
  { 620,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #620 = CGIJAsmE
  { 621,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #621 = CGIJAsmH
  { 622,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #622 = CGIJAsmHE
  { 623,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #623 = CGIJAsmL
  { 624,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #624 = CGIJAsmLE
  { 625,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #625 = CGIJAsmLH
  { 626,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #626 = CGIJAsmNE
  { 627,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #627 = CGIJAsmNH
  { 628,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #628 = CGIJAsmNHE
  { 629,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #629 = CGIJAsmNL
  { 630,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #630 = CGIJAsmNLE
  { 631,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #631 = CGIJAsmNLH
  { 632,  3,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #632 = CGIT
  { 633,  3,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #633 = CGITAsm
  { 634,  2,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #634 = CGITAsmE
  { 635,  2,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #635 = CGITAsmH
  { 636,  2,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #636 = CGITAsmHE
  { 637,  2,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #637 = CGITAsmL
  { 638,  2,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #638 = CGITAsmLE
  { 639,  2,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #639 = CGITAsmLH
  { 640,  2,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #640 = CGITAsmNE
  { 641,  2,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #641 = CGITAsmNH
  { 642,  2,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #642 = CGITAsmNHE
  { 643,  2,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #643 = CGITAsmNL
  { 644,  2,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #644 = CGITAsmNLE
  { 645,  2,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #645 = CGITAsmNLH
  { 646,  2,  0,  4,  215,  0|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr },  // Inst #646 = CGR
  { 647,  5,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr },  // Inst #647 = CGRB
  { 648,  5,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr },  // Inst #648 = CGRBAsm
  { 649,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #649 = CGRBAsmE
  { 650,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #650 = CGRBAsmH
  { 651,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #651 = CGRBAsmHE
  { 652,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #652 = CGRBAsmL
  { 653,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #653 = CGRBAsmLE
  { 654,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #654 = CGRBAsmLH
  { 655,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #655 = CGRBAsmNE
  { 656,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #656 = CGRBAsmNH
  { 657,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #657 = CGRBAsmNHE
  { 658,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #658 = CGRBAsmNL
  { 659,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #659 = CGRBAsmNLE
  { 660,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #660 = CGRBAsmNLH
  { 661,  4,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo157, -1 ,nullptr },  // Inst #661 = CGRJ
  { 662,  4,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo157, -1 ,nullptr },  // Inst #662 = CGRJAsm
  { 663,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #663 = CGRJAsmE
  { 664,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #664 = CGRJAsmH
  { 665,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #665 = CGRJAsmHE
  { 666,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #666 = CGRJAsmL
  { 667,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #667 = CGRJAsmLE
  { 668,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #668 = CGRJAsmLH
  { 669,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #669 = CGRJAsmNE
  { 670,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #670 = CGRJAsmNH
  { 671,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #671 = CGRJAsmNHE
  { 672,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #672 = CGRJAsmNL
  { 673,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #673 = CGRJAsmNLE
  { 674,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #674 = CGRJAsmNLH
  { 675,  2,  0,  6,  214,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr },  // Inst #675 = CGRL
  { 676,  3,  0,  4,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #676 = CGRT
  { 677,  3,  0,  4,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #677 = CGRTAsm
  { 678,  2,  0,  4,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #678 = CGRTAsmE
  { 679,  2,  0,  4,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #679 = CGRTAsmH
  { 680,  2,  0,  4,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #680 = CGRTAsmHE
  { 681,  2,  0,  4,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #681 = CGRTAsmL
  { 682,  2,  0,  4,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #682 = CGRTAsmLE
  { 683,  2,  0,  4,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #683 = CGRTAsmLH
  { 684,  2,  0,  4,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #684 = CGRTAsmNE
  { 685,  2,  0,  4,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #685 = CGRTAsmNH
  { 686,  2,  0,  4,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #686 = CGRTAsmNHE
  { 687,  2,  0,  4,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #687 = CGRTAsmNL
  { 688,  2,  0,  4,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #688 = CGRTAsmNLE
  { 689,  2,  0,  4,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #689 = CGRTAsmNLH
  { 690,  3,  1,  4,  355,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo158, -1 ,nullptr },  // Inst #690 = CGXBR
  { 691,  4,  1,  4,  355,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo159, -1 ,nullptr },  // Inst #691 = CGXBRA
  { 692,  3,  1,  4,  411,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo158, -1 ,nullptr },  // Inst #692 = CGXR
  { 693,  3,  1,  4,  460,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo158, -1 ,nullptr },  // Inst #693 = CGXTR
  { 694,  4,  1,  4,  460,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo159, -1 ,nullptr },  // Inst #694 = CGXTRA
  { 695,  4,  0,  4,  237,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3848ULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr },  // Inst #695 = CH
  { 696,  4,  0,  6,  217,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x388cULL, nullptr, ImplicitList1, OperandInfo160, -1 ,nullptr },  // Inst #696 = CHF
  { 697,  2,  0,  4,  235,  0|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo161, -1 ,nullptr },  // Inst #697 = CHHR
  { 698,  3,  0,  6,  241,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL, nullptr, ImplicitList1, OperandInfo86, -1 ,nullptr },  // Inst #698 = CHHSI
  { 699,  2,  0,  4,  212,  0|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo144, -1 ,nullptr },  // Inst #699 = CHI
  { 700,  2,  0,  4,  236,  0|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo162, -1 ,nullptr },  // Inst #700 = CHLR
  { 701,  2,  0,  6,  238,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL, nullptr, ImplicitList1, OperandInfo144, -1 ,nullptr },  // Inst #701 = CHRL
  { 702,  3,  0,  6,  218,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL, nullptr, ImplicitList1, OperandInfo86, -1 ,nullptr },  // Inst #702 = CHSI
  { 703,  4,  0,  6,  237,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x384cULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr },  // Inst #703 = CHY
  { 704,  5,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr },  // Inst #704 = CIB
  { 705,  5,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr },  // Inst #705 = CIBAsm
  { 706,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #706 = CIBAsmE
  { 707,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #707 = CIBAsmH
  { 708,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #708 = CIBAsmHE
  { 709,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #709 = CIBAsmL
  { 710,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #710 = CIBAsmLE
  { 711,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #711 = CIBAsmLH
  { 712,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #712 = CIBAsmNE
  { 713,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #713 = CIBAsmNH
  { 714,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #714 = CIBAsmNHE
  { 715,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #715 = CIBAsmNL
  { 716,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #716 = CIBAsmNLE
  { 717,  4,  0,  6,  12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #717 = CIBAsmNLH
  { 718,  2,  0,  6,  216,  0|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo165, -1 ,nullptr },  // Inst #718 = CIH
  { 719,  4,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo166, -1 ,nullptr },  // Inst #719 = CIJ
  { 720,  4,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo166, -1 ,nullptr },  // Inst #720 = CIJAsm
  { 721,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #721 = CIJAsmE
  { 722,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #722 = CIJAsmH
  { 723,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #723 = CIJAsmHE
  { 724,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #724 = CIJAsmL
  { 725,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #725 = CIJAsmLE
  { 726,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #726 = CIJAsmLH
  { 727,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #727 = CIJAsmNE
  { 728,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #728 = CIJAsmNH
  { 729,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #729 = CIJAsmNHE
  { 730,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #730 = CIJAsmNL
  { 731,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #731 = CIJAsmNLE
  { 732,  3,  0,  6,  11, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #732 = CIJAsmNLH
  { 733,  3,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #733 = CIT
  { 734,  3,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #734 = CITAsm
  { 735,  2,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #735 = CITAsmE
  { 736,  2,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #736 = CITAsmH
  { 737,  2,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #737 = CITAsmHE
  { 738,  2,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #738 = CITAsmL
  { 739,  2,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #739 = CITAsmLE
  { 740,  2,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #740 = CITAsmLH
  { 741,  2,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #741 = CITAsmNE
  { 742,  2,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #742 = CITAsmNH
  { 743,  2,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #743 = CITAsmNHE
  { 744,  2,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #744 = CITAsmNL
  { 745,  2,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #745 = CITAsmNLE
  { 746,  2,  0,  6,  14, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #746 = CITAsmNLH
  { 747,  4,  2,  4,  325,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, ImplicitList1, OperandInfo167, -1 ,nullptr },  // Inst #747 = CKSM
  { 748,  4,  0,  4,  219,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x103888ULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr },  // Inst #748 = CL
  { 749,  5,  0,  6,  245,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, ImplicitList1, OperandInfo168, -1 ,nullptr },  // Inst #749 = CLC
  { 750,  4,  2,  2,  246,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, ImplicitList1, OperandInfo169, -1 ,nullptr },  // Inst #750 = CLCL
  { 751,  6,  2,  4,  246,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, ImplicitList1, OperandInfo170, -1 ,nullptr },  // Inst #751 = CLCLE
  { 752,  6,  2,  6,  246,  0|(1ULL<<MCID::MayLoad), 0x4ULL, nullptr, ImplicitList1, OperandInfo170, -1 ,nullptr },  // Inst #752 = CLCLU
  { 753,  4,  1,  4,  357,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo141, -1 ,nullptr },  // Inst #753 = CLFDBR
  { 754,  4,  1,  4,  461,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo141, -1 ,nullptr },  // Inst #754 = CLFDTR
  { 755,  4,  1,  4,  356,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo143, -1 ,nullptr },  // Inst #755 = CLFEBR
  { 756,  3,  0,  6,  220,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x103800ULL, nullptr, ImplicitList1, OperandInfo86, -1 ,nullptr },  // Inst #756 = CLFHSI
  { 757,  2,  0,  6,  221,  0|(1ULL<<MCID::Compare), 0x103800ULL, nullptr, ImplicitList1, OperandInfo144, -1 ,nullptr },  // Inst #757 = CLFI
  { 758,  3,  0,  6,  16, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #758 = CLFIT
  { 759,  3,  0,  6,  16, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #759 = CLFITAsm
  { 760,  2,  0,  6,  16, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #760 = CLFITAsmE
  { 761,  2,  0,  6,  16, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #761 = CLFITAsmH
  { 762,  2,  0,  6,  16, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #762 = CLFITAsmHE
  { 763,  2,  0,  6,  16, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #763 = CLFITAsmL
  { 764,  2,  0,  6,  16, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #764 = CLFITAsmLE
  { 765,  2,  0,  6,  16, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #765 = CLFITAsmLH
  { 766,  2,  0,  6,  16, 0|(1ULL<<MCID::Unmodele

Coverage Report

Created: 2018-11-13 17:19