Coverage Report

Created: 2018-11-16 02:38

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/SystemZ/SystemZGenRegisterInfo.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Register Enum Values                                                *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
#ifdef GET_REGINFO_ENUM
11
#undef GET_REGINFO_ENUM
12
13
namespace llvm {
14
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class MCRegisterClass;
16
extern const MCRegisterClass SystemZMCRegisterClasses[];
17
18
namespace SystemZ {
19
enum {
20
  NoRegister,
21
  CC = 1,
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  A0 = 2,
23
  A1 = 3,
24
  A2 = 4,
25
  A3 = 5,
26
  A4 = 6,
27
  A5 = 7,
28
  A6 = 8,
29
  A7 = 9,
30
  A8 = 10,
31
  A9 = 11,
32
  A10 = 12,
33
  A11 = 13,
34
  A12 = 14,
35
  A13 = 15,
36
  A14 = 16,
37
  A15 = 17,
38
  C0 = 18,
39
  C1 = 19,
40
  C2 = 20,
41
  C3 = 21,
42
  C4 = 22,
43
  C5 = 23,
44
  C6 = 24,
45
  C7 = 25,
46
  C8 = 26,
47
  C9 = 27,
48
  C10 = 28,
49
  C11 = 29,
50
  C12 = 30,
51
  C13 = 31,
52
  C14 = 32,
53
  C15 = 33,
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  V0 = 34,
55
  V1 = 35,
56
  V2 = 36,
57
  V3 = 37,
58
  V4 = 38,
59
  V5 = 39,
60
  V6 = 40,
61
  V7 = 41,
62
  V8 = 42,
63
  V9 = 43,
64
  V10 = 44,
65
  V11 = 45,
66
  V12 = 46,
67
  V13 = 47,
68
  V14 = 48,
69
  V15 = 49,
70
  V16 = 50,
71
  V17 = 51,
72
  V18 = 52,
73
  V19 = 53,
74
  V20 = 54,
75
  V21 = 55,
76
  V22 = 56,
77
  V23 = 57,
78
  V24 = 58,
79
  V25 = 59,
80
  V26 = 60,
81
  V27 = 61,
82
  V28 = 62,
83
  V29 = 63,
84
  V30 = 64,
85
  V31 = 65,
86
  F0D = 66,
87
  F1D = 67,
88
  F2D = 68,
89
  F3D = 69,
90
  F4D = 70,
91
  F5D = 71,
92
  F6D = 72,
93
  F7D = 73,
94
  F8D = 74,
95
  F9D = 75,
96
  F10D = 76,
97
  F11D = 77,
98
  F12D = 78,
99
  F13D = 79,
100
  F14D = 80,
101
  F15D = 81,
102
  F16D = 82,
103
  F17D = 83,
104
  F18D = 84,
105
  F19D = 85,
106
  F20D = 86,
107
  F21D = 87,
108
  F22D = 88,
109
  F23D = 89,
110
  F24D = 90,
111
  F25D = 91,
112
  F26D = 92,
113
  F27D = 93,
114
  F28D = 94,
115
  F29D = 95,
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  F30D = 96,
117
  F31D = 97,
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  F0Q = 98,
119
  F1Q = 99,
120
  F4Q = 100,
121
  F5Q = 101,
122
  F8Q = 102,
123
  F9Q = 103,
124
  F12Q = 104,
125
  F13Q = 105,
126
  F0S = 106,
127
  F1S = 107,
128
  F2S = 108,
129
  F3S = 109,
130
  F4S = 110,
131
  F5S = 111,
132
  F6S = 112,
133
  F7S = 113,
134
  F8S = 114,
135
  F9S = 115,
136
  F10S = 116,
137
  F11S = 117,
138
  F12S = 118,
139
  F13S = 119,
140
  F14S = 120,
141
  F15S = 121,
142
  F16S = 122,
143
  F17S = 123,
144
  F18S = 124,
145
  F19S = 125,
146
  F20S = 126,
147
  F21S = 127,
148
  F22S = 128,
149
  F23S = 129,
150
  F24S = 130,
151
  F25S = 131,
152
  F26S = 132,
153
  F27S = 133,
154
  F28S = 134,
155
  F29S = 135,
156
  F30S = 136,
157
  F31S = 137,
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  R0D = 138,
159
  R1D = 139,
160
  R2D = 140,
161
  R3D = 141,
162
  R4D = 142,
163
  R5D = 143,
164
  R6D = 144,
165
  R7D = 145,
166
  R8D = 146,
167
  R9D = 147,
168
  R10D = 148,
169
  R11D = 149,
170
  R12D = 150,
171
  R13D = 151,
172
  R14D = 152,
173
  R15D = 153,
174
  R0H = 154,
175
  R1H = 155,
176
  R2H = 156,
177
  R3H = 157,
178
  R4H = 158,
179
  R5H = 159,
180
  R6H = 160,
181
  R7H = 161,
182
  R8H = 162,
183
  R9H = 163,
184
  R10H = 164,
185
  R11H = 165,
186
  R12H = 166,
187
  R13H = 167,
188
  R14H = 168,
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  R15H = 169,
190
  R0L = 170,
191
  R1L = 171,
192
  R2L = 172,
193
  R3L = 173,
194
  R4L = 174,
195
  R5L = 175,
196
  R6L = 176,
197
  R7L = 177,
198
  R8L = 178,
199
  R9L = 179,
200
  R10L = 180,
201
  R11L = 181,
202
  R12L = 182,
203
  R13L = 183,
204
  R14L = 184,
205
  R15L = 185,
206
  R0Q = 186,
207
  R2Q = 187,
208
  R4Q = 188,
209
  R6Q = 189,
210
  R8Q = 190,
211
  R10Q = 191,
212
  R12Q = 192,
213
  R14Q = 193,
214
  NUM_TARGET_REGS   // 194
215
};
216
} // end namespace SystemZ
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// Register classes
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namespace SystemZ {
221
enum {
222
  GRX32BitRegClassID = 0,
223
  VR32BitRegClassID = 1,
224
  AR32BitRegClassID = 2,
225
  FP32BitRegClassID = 3,
226
  GR32BitRegClassID = 4,
227
  GRH32BitRegClassID = 5,
228
  ADDR32BitRegClassID = 6,
229
  CCRRegClassID = 7,
230
  AnyRegBitRegClassID = 8,
231
  AnyRegBit_with_subreg_h32_in_FP32BitRegClassID = 9,
232
  VR64BitRegClassID = 10,
233
  AnyRegBit_with_subreg_h64RegClassID = 11,
234
  CR64BitRegClassID = 12,
235
  FP64BitRegClassID = 13,
236
  GR64BitRegClassID = 14,
237
  ADDR64BitRegClassID = 15,
238
  VR128BitRegClassID = 16,
239
  VF128BitRegClassID = 17,
240
  FP128BitRegClassID = 18,
241
  GR128BitRegClassID = 19,
242
  ADDR128BitRegClassID = 20,
243
244
  };
245
} // end namespace SystemZ
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// Subregister indices
249
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namespace SystemZ {
251
enum {
252
  NoSubRegister,
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  subreg_h32, // 1
254
  subreg_h64, // 2
255
  subreg_hh32,  // 3
256
  subreg_hl32,  // 4
257
  subreg_l32, // 5
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  subreg_l64, // 6
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  NUM_TARGET_SUBREGS
260
};
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} // end namespace SystemZ
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} // end namespace llvm
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#endif // GET_REGINFO_ENUM
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
268
|*                                                                            *|
269
|* MC Register Information                                                    *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
273
\*===----------------------------------------------------------------------===*/
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#ifdef GET_REGINFO_MC_DESC
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#undef GET_REGINFO_MC_DESC
278
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namespace llvm {
280
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extern const MCPhysReg SystemZRegDiffLists[] = {
282
  /* 0 */ 64857, 1, 1, 1, 0,
283
  /* 5 */ 65325, 1, 0,
284
  /* 8 */ 65471, 2, 0,
285
  /* 11 */ 65473, 2, 0,
286
  /* 14 */ 65475, 2, 0,
287
  /* 17 */ 65477, 2, 0,
288
  /* 20 */ 32, 40, 0,
289
  /* 23 */ 65506, 40, 65494, 40, 0,
290
  /* 28 */ 65508, 40, 65494, 40, 0,
291
  /* 33 */ 65510, 40, 65494, 40, 0,
292
  /* 38 */ 65512, 40, 65494, 40, 0,
293
  /* 43 */ 65504, 40, 0,
294
  /* 46 */ 65520, 40, 0,
295
  /* 49 */ 65504, 41, 0,
296
  /* 52 */ 65520, 41, 0,
297
  /* 55 */ 65504, 42, 0,
298
  /* 58 */ 65520, 42, 0,
299
  /* 61 */ 65504, 43, 0,
300
  /* 64 */ 65520, 43, 0,
301
  /* 67 */ 65504, 44, 0,
302
  /* 70 */ 65520, 44, 0,
303
  /* 73 */ 65504, 45, 0,
304
  /* 76 */ 65520, 45, 0,
305
  /* 79 */ 65504, 46, 0,
306
  /* 82 */ 65520, 46, 0,
307
  /* 85 */ 65504, 47, 0,
308
  /* 88 */ 65520, 47, 0,
309
  /* 91 */ 65504, 48, 0,
310
  /* 94 */ 65520, 48, 0,
311
  /* 97 */ 65496, 65504, 56, 0,
312
  /* 101 */ 65496, 65504, 58, 0,
313
  /* 105 */ 65496, 65504, 60, 0,
314
  /* 109 */ 65496, 65504, 62, 0,
315
  /* 113 */ 65496, 65504, 64, 0,
316
  /* 117 */ 65261, 0,
317
  /* 119 */ 65294, 0,
318
  /* 121 */ 65463, 0,
319
  /* 123 */ 65503, 0,
320
  /* 125 */ 65496, 65504, 0,
321
  /* 128 */ 65489, 32, 65520, 65519, 32, 65520, 0,
322
  /* 135 */ 65490, 32, 65520, 65519, 32, 65520, 0,
323
  /* 142 */ 65491, 32, 65520, 65519, 32, 65520, 0,
324
  /* 149 */ 65492, 32, 65520, 65519, 32, 65520, 0,
325
  /* 156 */ 65493, 32, 65520, 65519, 32, 65520, 0,
326
  /* 163 */ 65494, 32, 65520, 65519, 32, 65520, 0,
327
  /* 170 */ 65495, 32, 65520, 65519, 32, 65520, 0,
328
  /* 177 */ 65496, 32, 65520, 65519, 32, 65520, 0,
329
  /* 184 */ 65535, 0,
330
};
331
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extern const LaneBitmask SystemZLaneMaskLists[] = {
333
  /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
334
  /* 2 */ LaneBitmask(0x00000002), LaneBitmask(0x00000001), LaneBitmask::getAll(),
335
  /* 5 */ LaneBitmask(0x00000004), LaneBitmask(0x00000002), LaneBitmask(0x00000008), LaneBitmask(0x00000001), LaneBitmask::getAll(),
336
};
337
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extern const uint16_t SystemZSubRegIdxLists[] = {
339
  /* 0 */ 2, 1, 0,
340
  /* 3 */ 5, 1, 0,
341
  /* 6 */ 6, 1, 2, 3, 0,
342
  /* 11 */ 6, 5, 1, 2, 4, 3, 0,
343
};
344
345
extern const MCRegisterInfo::SubRegCoveredBits SystemZSubRegIdxRanges[] = {
346
  { 65535, 65535 },
347
  { 32, 32 }, // subreg_h32
348
  { 64, 64 }, // subreg_h64
349
  { 96, 32 }, // subreg_hh32
350
  { 64, 32 }, // subreg_hl32
351
  { 0, 32 },  // subreg_l32
352
  { 0, 64 },  // subreg_l64
353
};
354
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extern const char SystemZRegStrings[] = {
356
  /* 0 */ 'A', '1', '0', 0,
357
  /* 4 */ 'C', '1', '0', 0,
358
  /* 8 */ 'V', '1', '0', 0,
359
  /* 12 */ 'V', '2', '0', 0,
360
  /* 16 */ 'V', '3', '0', 0,
361
  /* 20 */ 'A', '0', 0,
362
  /* 23 */ 'C', '0', 0,
363
  /* 26 */ 'V', '0', 0,
364
  /* 29 */ 'A', '1', '1', 0,
365
  /* 33 */ 'C', '1', '1', 0,
366
  /* 37 */ 'V', '1', '1', 0,
367
  /* 41 */ 'V', '2', '1', 0,
368
  /* 45 */ 'V', '3', '1', 0,
369
  /* 49 */ 'A', '1', 0,
370
  /* 52 */ 'C', '1', 0,
371
  /* 55 */ 'V', '1', 0,
372
  /* 58 */ 'A', '1', '2', 0,
373
  /* 62 */ 'C', '1', '2', 0,
374
  /* 66 */ 'V', '1', '2', 0,
375
  /* 70 */ 'V', '2', '2', 0,
376
  /* 74 */ 'A', '2', 0,
377
  /* 77 */ 'C', '2', 0,
378
  /* 80 */ 'V', '2', 0,
379
  /* 83 */ 'A', '1', '3', 0,
380
  /* 87 */ 'C', '1', '3', 0,
381
  /* 91 */ 'V', '1', '3', 0,
382
  /* 95 */ 'V', '2', '3', 0,
383
  /* 99 */ 'A', '3', 0,
384
  /* 102 */ 'C', '3', 0,
385
  /* 105 */ 'V', '3', 0,
386
  /* 108 */ 'A', '1', '4', 0,
387
  /* 112 */ 'C', '1', '4', 0,
388
  /* 116 */ 'V', '1', '4', 0,
389
  /* 120 */ 'V', '2', '4', 0,
390
  /* 124 */ 'A', '4', 0,
391
  /* 127 */ 'C', '4', 0,
392
  /* 130 */ 'V', '4', 0,
393
  /* 133 */ 'A', '1', '5', 0,
394
  /* 137 */ 'C', '1', '5', 0,
395
  /* 141 */ 'V', '1', '5', 0,
396
  /* 145 */ 'V', '2', '5', 0,
397
  /* 149 */ 'A', '5', 0,
398
  /* 152 */ 'C', '5', 0,
399
  /* 155 */ 'V', '5', 0,
400
  /* 158 */ 'V', '1', '6', 0,
401
  /* 162 */ 'V', '2', '6', 0,
402
  /* 166 */ 'A', '6', 0,
403
  /* 169 */ 'C', '6', 0,
404
  /* 172 */ 'V', '6', 0,
405
  /* 175 */ 'V', '1', '7', 0,
406
  /* 179 */ 'V', '2', '7', 0,
407
  /* 183 */ 'A', '7', 0,
408
  /* 186 */ 'C', '7', 0,
409
  /* 189 */ 'V', '7', 0,
410
  /* 192 */ 'V', '1', '8', 0,
411
  /* 196 */ 'V', '2', '8', 0,
412
  /* 200 */ 'A', '8', 0,
413
  /* 203 */ 'C', '8', 0,
414
  /* 206 */ 'V', '8', 0,
415
  /* 209 */ 'V', '1', '9', 0,
416
  /* 213 */ 'V', '2', '9', 0,
417
  /* 217 */ 'A', '9', 0,
418
  /* 220 */ 'C', '9', 0,
419
  /* 223 */ 'V', '9', 0,
420
  /* 226 */ 'C', 'C', 0,
421
  /* 229 */ 'F', '1', '0', 'D', 0,
422
  /* 234 */ 'R', '1', '0', 'D', 0,
423
  /* 239 */ 'F', '2', '0', 'D', 0,
424
  /* 244 */ 'F', '3', '0', 'D', 0,
425
  /* 249 */ 'F', '0', 'D', 0,
426
  /* 253 */ 'R', '0', 'D', 0,
427
  /* 257 */ 'F', '1', '1', 'D', 0,
428
  /* 262 */ 'R', '1', '1', 'D', 0,
429
  /* 267 */ 'F', '2', '1', 'D', 0,
430
  /* 272 */ 'F', '3', '1', 'D', 0,
431
  /* 277 */ 'F', '1', 'D', 0,
432
  /* 281 */ 'R', '1', 'D', 0,
433
  /* 285 */ 'F', '1', '2', 'D', 0,
434
  /* 290 */ 'R', '1', '2', 'D', 0,
435
  /* 295 */ 'F', '2', '2', 'D', 0,
436
  /* 300 */ 'F', '2', 'D', 0,
437
  /* 304 */ 'R', '2', 'D', 0,
438
  /* 308 */ 'F', '1', '3', 'D', 0,
439
  /* 313 */ 'R', '1', '3', 'D', 0,
440
  /* 318 */ 'F', '2', '3', 'D', 0,
441
  /* 323 */ 'F', '3', 'D', 0,
442
  /* 327 */ 'R', '3', 'D', 0,
443
  /* 331 */ 'F', '1', '4', 'D', 0,
444
  /* 336 */ 'R', '1', '4', 'D', 0,
445
  /* 341 */ 'F', '2', '4', 'D', 0,
446
  /* 346 */ 'F', '4', 'D', 0,
447
  /* 350 */ 'R', '4', 'D', 0,
448
  /* 354 */ 'F', '1', '5', 'D', 0,
449
  /* 359 */ 'R', '1', '5', 'D', 0,
450
  /* 364 */ 'F', '2', '5', 'D', 0,
451
  /* 369 */ 'F', '5', 'D', 0,
452
  /* 373 */ 'R', '5', 'D', 0,
453
  /* 377 */ 'F', '1', '6', 'D', 0,
454
  /* 382 */ 'F', '2', '6', 'D', 0,
455
  /* 387 */ 'F', '6', 'D', 0,
456
  /* 391 */ 'R', '6', 'D', 0,
457
  /* 395 */ 'F', '1', '7', 'D', 0,
458
  /* 400 */ 'F', '2', '7', 'D', 0,
459
  /* 405 */ 'F', '7', 'D', 0,
460
  /* 409 */ 'R', '7', 'D', 0,
461
  /* 413 */ 'F', '1', '8', 'D', 0,
462
  /* 418 */ 'F', '2', '8', 'D', 0,
463
  /* 423 */ 'F', '8', 'D', 0,
464
  /* 427 */ 'R', '8', 'D', 0,
465
  /* 431 */ 'F', '1', '9', 'D', 0,
466
  /* 436 */ 'F', '2', '9', 'D', 0,
467
  /* 441 */ 'F', '9', 'D', 0,
468
  /* 445 */ 'R', '9', 'D', 0,
469
  /* 449 */ 'R', '1', '0', 'H', 0,
470
  /* 454 */ 'R', '0', 'H', 0,
471
  /* 458 */ 'R', '1', '1', 'H', 0,
472
  /* 463 */ 'R', '1', 'H', 0,
473
  /* 467 */ 'R', '1', '2', 'H', 0,
474
  /* 472 */ 'R', '2', 'H', 0,
475
  /* 476 */ 'R', '1', '3', 'H', 0,
476
  /* 481 */ 'R', '3', 'H', 0,
477
  /* 485 */ 'R', '1', '4', 'H', 0,
478
  /* 490 */ 'R', '4', 'H', 0,
479
  /* 494 */ 'R', '1', '5', 'H', 0,
480
  /* 499 */ 'R', '5', 'H', 0,
481
  /* 503 */ 'R', '6', 'H', 0,
482
  /* 507 */ 'R', '7', 'H', 0,
483
  /* 511 */ 'R', '8', 'H', 0,
484
  /* 515 */ 'R', '9', 'H', 0,
485
  /* 519 */ 'R', '1', '0', 'L', 0,
486
  /* 524 */ 'R', '0', 'L', 0,
487
  /* 528 */ 'R', '1', '1', 'L', 0,
488
  /* 533 */ 'R', '1', 'L', 0,
489
  /* 537 */ 'R', '1', '2', 'L', 0,
490
  /* 542 */ 'R', '2', 'L', 0,
491
  /* 546 */ 'R', '1', '3', 'L', 0,
492
  /* 551 */ 'R', '3', 'L', 0,
493
  /* 555 */ 'R', '1', '4', 'L', 0,
494
  /* 560 */ 'R', '4', 'L', 0,
495
  /* 564 */ 'R', '1', '5', 'L', 0,
496
  /* 569 */ 'R', '5', 'L', 0,
497
  /* 573 */ 'R', '6', 'L', 0,
498
  /* 577 */ 'R', '7', 'L', 0,
499
  /* 581 */ 'R', '8', 'L', 0,
500
  /* 585 */ 'R', '9', 'L', 0,
501
  /* 589 */ 'R', '1', '0', 'Q', 0,
502
  /* 594 */ 'F', '0', 'Q', 0,
503
  /* 598 */ 'R', '0', 'Q', 0,
504
  /* 602 */ 'F', '1', 'Q', 0,
505
  /* 606 */ 'F', '1', '2', 'Q', 0,
506
  /* 611 */ 'R', '1', '2', 'Q', 0,
507
  /* 616 */ 'R', '2', 'Q', 0,
508
  /* 620 */ 'F', '1', '3', 'Q', 0,
509
  /* 625 */ 'R', '1', '4', 'Q', 0,
510
  /* 630 */ 'F', '4', 'Q', 0,
511
  /* 634 */ 'R', '4', 'Q', 0,
512
  /* 638 */ 'F', '5', 'Q', 0,
513
  /* 642 */ 'R', '6', 'Q', 0,
514
  /* 646 */ 'F', '8', 'Q', 0,
515
  /* 650 */ 'R', '8', 'Q', 0,
516
  /* 654 */ 'F', '9', 'Q', 0,
517
  /* 658 */ 'F', '1', '0', 'S', 0,
518
  /* 663 */ 'F', '2', '0', 'S', 0,
519
  /* 668 */ 'F', '3', '0', 'S', 0,
520
  /* 673 */ 'F', '0', 'S', 0,
521
  /* 677 */ 'F', '1', '1', 'S', 0,
522
  /* 682 */ 'F', '2', '1', 'S', 0,
523
  /* 687 */ 'F', '3', '1', 'S', 0,
524
  /* 692 */ 'F', '1', 'S', 0,
525
  /* 696 */ 'F', '1', '2', 'S', 0,
526
  /* 701 */ 'F', '2', '2', 'S', 0,
527
  /* 706 */ 'F', '2', 'S', 0,
528
  /* 710 */ 'F', '1', '3', 'S', 0,
529
  /* 715 */ 'F', '2', '3', 'S', 0,
530
  /* 720 */ 'F', '3', 'S', 0,
531
  /* 724 */ 'F', '1', '4', 'S', 0,
532
  /* 729 */ 'F', '2', '4', 'S', 0,
533
  /* 734 */ 'F', '4', 'S', 0,
534
  /* 738 */ 'F', '1', '5', 'S', 0,
535
  /* 743 */ 'F', '2', '5', 'S', 0,
536
  /* 748 */ 'F', '5', 'S', 0,
537
  /* 752 */ 'F', '1', '6', 'S', 0,
538
  /* 757 */ 'F', '2', '6', 'S', 0,
539
  /* 762 */ 'F', '6', 'S', 0,
540
  /* 766 */ 'F', '1', '7', 'S', 0,
541
  /* 771 */ 'F', '2', '7', 'S', 0,
542
  /* 776 */ 'F', '7', 'S', 0,
543
  /* 780 */ 'F', '1', '8', 'S', 0,
544
  /* 785 */ 'F', '2', '8', 'S', 0,
545
  /* 790 */ 'F', '8', 'S', 0,
546
  /* 794 */ 'F', '1', '9', 'S', 0,
547
  /* 799 */ 'F', '2', '9', 'S', 0,
548
  /* 804 */ 'F', '9', 'S', 0,
549
};
550
551
extern const MCRegisterDesc SystemZRegDesc[] = { // Descriptors
552
  { 3, 0, 0, 0, 0, 0 },
553
  { 226, 4, 4, 2, 2945, 0 },
554
  { 20, 4, 4, 2, 2945, 0 },
555
  { 49, 4, 4, 2, 2945, 0 },
556
  { 74, 4, 4, 2, 2945, 0 },
557
  { 99, 4, 4, 2, 2945, 0 },
558
  { 124, 4, 4, 2, 2945, 0 },
559
  { 149, 4, 4, 2, 2945, 0 },
560
  { 166, 4, 4, 2, 2945, 0 },
561
  { 183, 4, 4, 2, 2945, 0 },
562
  { 200, 4, 4, 2, 2945, 0 },
563
  { 217, 4, 4, 2, 2945, 0 },
564
  { 0, 4, 4, 2, 2945, 0 },
565
  { 29, 4, 4, 2, 2945, 0 },
566
  { 58, 4, 4, 2, 2945, 0 },
567
  { 83, 4, 4, 2, 2945, 0 },
568
  { 108, 4, 4, 2, 2945, 0 },
569
  { 133, 4, 4, 2, 2945, 0 },
570
  { 23, 4, 4, 2, 2945, 0 },
571
  { 52, 4, 4, 2, 2945, 0 },
572
  { 77, 4, 4, 2, 2945, 0 },
573
  { 102, 4, 4, 2, 2945, 0 },
574
  { 127, 4, 4, 2, 2945, 0 },
575
  { 152, 4, 4, 2, 2945, 0 },
576
  { 169, 4, 4, 2, 2945, 0 },
577
  { 186, 4, 4, 2, 2945, 0 },
578
  { 203, 4, 4, 2, 2945, 0 },
579
  { 220, 4, 4, 2, 2945, 0 },
580
  { 4, 4, 4, 2, 2945, 0 },
581
  { 33, 4, 4, 2, 2945, 0 },
582
  { 62, 4, 4, 2, 2945, 0 },
583
  { 87, 4, 4, 2, 2945, 0 },
584
  { 112, 4, 4, 2, 2945, 0 },
585
  { 137, 4, 4, 2, 2945, 0 },
586
  { 26, 20, 4, 0, 2945, 3 },
587
  { 55, 20, 4, 0, 2945, 3 },
588
  { 80, 20, 4, 0, 2945, 3 },
589
  { 105, 20, 4, 0, 2945, 3 },
590
  { 130, 20, 4, 0, 2945, 3 },
591
  { 155, 20, 4, 0, 2945, 3 },
592
  { 172, 20, 4, 0, 2945, 3 },
593
  { 189, 20, 4, 0, 2945, 3 },
594
  { 206, 20, 4, 0, 2945, 3 },
595
  { 223, 20, 4, 0, 2945, 3 },
596
  { 8, 20, 4, 0, 2945, 3 },
597
  { 37, 20, 4, 0, 2945, 3 },
598
  { 66, 20, 4, 0, 2945, 3 },
599
  { 91, 20, 4, 0, 2945, 3 },
600
  { 116, 20, 4, 0, 2945, 3 },
601
  { 141, 20, 4, 0, 2945, 3 },
602
  { 158, 20, 4, 0, 2945, 3 },
603
  { 175, 20, 4, 0, 2945, 3 },
604
  { 192, 20, 4, 0, 2945, 3 },
605
  { 209, 20, 4, 0, 2945, 3 },
606
  { 12, 20, 4, 0, 2945, 3 },
607
  { 41, 20, 4, 0, 2945, 3 },
608
  { 70, 20, 4, 0, 2945, 3 },
609
  { 95, 20, 4, 0, 2945, 3 },
610
  { 120, 20, 4, 0, 2945, 3 },
611
  { 145, 20, 4, 0, 2945, 3 },
612
  { 162, 20, 4, 0, 2945, 3 },
613
  { 179, 20, 4, 0, 2945, 3 },
614
  { 196, 20, 4, 0, 2945, 3 },
615
  { 213, 20, 4, 0, 2945, 3 },
616
  { 16, 20, 4, 0, 2945, 3 },
617
  { 45, 20, 4, 0, 2945, 3 },
618
  { 249, 21, 114, 1, 1969, 3 },
619
  { 277, 21, 114, 1, 1969, 3 },
620
  { 300, 21, 110, 1, 1969, 3 },
621
  { 323, 21, 110, 1, 1969, 3 },
622
  { 346, 21, 110, 1, 1969, 3 },
623
  { 369, 21, 110, 1, 1969, 3 },
624
  { 387, 21, 106, 1, 1969, 3 },
625
  { 405, 21, 106, 1, 1969, 3 },
626
  { 423, 21, 106, 1, 1969, 3 },
627
  { 441, 21, 106, 1, 1969, 3 },
628
  { 229, 21, 102, 1, 1969, 3 },
629
  { 257, 21, 102, 1, 1969, 3 },
630
  { 285, 21, 102, 1, 1969, 3 },
631
  { 308, 21, 102, 1, 1969, 3 },
632
  { 331, 21, 98, 1, 1969, 3 },
633
  { 354, 21, 98, 1, 1969, 3 },
634
  { 377, 21, 126, 1, 1969, 3 },
635
  { 395, 21, 126, 1, 1969, 3 },
636
  { 413, 21, 126, 1, 1969, 3 },
637
  { 431, 21, 126, 1, 1969, 3 },
638
  { 239, 21, 126, 1, 1969, 3 },
639
  { 267, 21, 126, 1, 1969, 3 },
640
  { 295, 21, 126, 1, 1969, 3 },
641
  { 318, 21, 126, 1, 1969, 3 },
642
  { 341, 21, 126, 1, 1969, 3 },
643
  { 364, 21, 126, 1, 1969, 3 },
644
  { 382, 21, 126, 1, 1969, 3 },
645
  { 400, 21, 126, 1, 1969, 3 },
646
  { 418, 21, 126, 1, 1969, 3 },
647
  { 436, 21, 126, 1, 1969, 3 },
648
  { 244, 21, 126, 1, 1969, 3 },
649
  { 272, 21, 126, 1, 1969, 3 },
650
  { 594, 23, 4, 6, 129, 2 },
651
  { 602, 23, 4, 6, 129, 2 },
652
  { 630, 28, 4, 6, 177, 2 },
653
  { 638, 28, 4, 6, 177, 2 },
654
  { 646, 33, 4, 6, 225, 2 },
655
  { 654, 33, 4, 6, 225, 2 },
656
  { 606, 38, 4, 6, 273, 2 },
657
  { 620, 38, 4, 6, 273, 2 },
658
  { 673, 4, 113, 2, 1937, 0 },
659
  { 692, 4, 113, 2, 1937, 0 },
660
  { 706, 4, 109, 2, 1937, 0 },
661
  { 720, 4, 109, 2, 1937, 0 },
662
  { 734, 4, 109, 2, 1937, 0 },
663
  { 748, 4, 109, 2, 1937, 0 },
664
  { 762, 4, 105, 2, 1937, 0 },
665
  { 776, 4, 105, 2, 1937, 0 },
666
  { 790, 4, 105, 2, 1937, 0 },
667
  { 804, 4, 105, 2, 1937, 0 },
668
  { 658, 4, 101, 2, 1937, 0 },
669
  { 677, 4, 101, 2, 1937, 0 },
670
  { 696, 4, 101, 2, 1937, 0 },
671
  { 710, 4, 101, 2, 1937, 0 },
672
  { 724, 4, 97, 2, 1937, 0 },
673
  { 738, 4, 97, 2, 1937, 0 },
674
  { 752, 4, 125, 2, 1937, 0 },
675
  { 766, 4, 125, 2, 1937, 0 },
676
  { 780, 4, 125, 2, 1937, 0 },
677
  { 794, 4, 125, 2, 1937, 0 },
678
  { 663, 4, 125, 2, 1937, 0 },
679
  { 682, 4, 125, 2, 1937, 0 },
680
  { 701, 4, 125, 2, 1937, 0 },
681
  { 715, 4, 125, 2, 1937, 0 },
682
  { 729, 4, 125, 2, 1937, 0 },
683
  { 743, 4, 125, 2, 1937, 0 },
684
  { 757, 4, 125, 2, 1937, 0 },
685
  { 771, 4, 125, 2, 1937, 0 },
686
  { 785, 4, 125, 2, 1937, 0 },
687
  { 799, 4, 125, 2, 1937, 0 },
688
  { 668, 4, 125, 2, 1937, 0 },
689
  { 687, 4, 125, 2, 1937, 0 },
690
  { 253, 132, 92, 3, 82, 7 },
691
  { 281, 132, 86, 3, 82, 7 },
692
  { 304, 132, 86, 3, 82, 7 },
693
  { 327, 132, 80, 3, 82, 7 },
694
  { 350, 132, 80, 3, 82, 7 },
695
  { 373, 132, 74, 3, 82, 7 },
696
  { 391, 132, 74, 3, 82, 7 },
697
  { 409, 132, 68, 3, 82, 7 },
698
  { 427, 132, 68, 3, 82, 7 },
699
  { 445, 132, 62, 3, 82, 7 },
700
  { 234, 132, 62, 3, 82, 7 },
701
  { 262, 132, 56, 3, 82, 7 },
702
  { 290, 132, 56, 3, 82, 7 },
703
  { 313, 132, 50, 3, 82, 7 },
704
  { 336, 132, 50, 3, 82, 7 },
705
  { 359, 132, 21, 3, 82, 7 },
706
  { 454, 4, 94, 2, 1906, 0 },
707
  { 463, 4, 88, 2, 1906, 0 },
708
  { 472, 4, 88, 2, 1906, 0 },
709
  { 481, 4, 82, 2, 1906, 0 },
710
  { 490, 4, 82, 2, 1906, 0 },
711
  { 499, 4, 76, 2, 1906, 0 },
712
  { 503, 4, 76, 2, 1906, 0 },
713
  { 507, 4, 70, 2, 1906, 0 },
714
  { 511, 4, 70, 2, 1906, 0 },
715
  { 515, 4, 64, 2, 1906, 0 },
716
  { 449, 4, 64, 2, 1906, 0 },
717
  { 458, 4, 58, 2, 1906, 0 },
718
  { 467, 4, 58, 2, 1906, 0 },
719
  { 476, 4, 52, 2, 1906, 0 },
720
  { 485, 4, 52, 2, 1906, 0 },
721
  { 494, 4, 46, 2, 1906, 0 },
722
  { 524, 4, 91, 2, 1874, 0 },
723
  { 533, 4, 85, 2, 1874, 0 },
724
  { 542, 4, 85, 2, 1874, 0 },
725
  { 551, 4, 79, 2, 1874, 0 },
726
  { 560, 4, 79, 2, 1874, 0 },
727
  { 569, 4, 73, 2, 1874, 0 },
728
  { 573, 4, 73, 2, 1874, 0 },
729
  { 577, 4, 67, 2, 1874, 0 },
730
  { 581, 4, 67, 2, 1874, 0 },
731
  { 585, 4, 61, 2, 1874, 0 },
732
  { 519, 4, 61, 2, 1874, 0 },
733
  { 528, 4, 55, 2, 1874, 0 },
734
  { 537, 4, 55, 2, 1874, 0 },
735
  { 546, 4, 49, 2, 1874, 0 },
736
  { 555, 4, 49, 2, 1874, 0 },
737
  { 564, 4, 43, 2, 1874, 0 },
738
  { 598, 128, 4, 11, 4, 5 },
739
  { 616, 135, 4, 11, 4, 5 },
740
  { 634, 142, 4, 11, 4, 5 },
741
  { 642, 149, 4, 11, 4, 5 },
742
  { 650, 156, 4, 11, 4, 5 },
743
  { 589, 163, 4, 11, 4, 5 },
744
  { 611, 170, 4, 11, 4, 5 },
745
  { 625, 177, 4, 11, 4, 5 },
746
};
747
748
extern const MCPhysReg SystemZRegUnitRoots[][2] = {
749
  { SystemZ::CC },
750
  { SystemZ::A0 },
751
  { SystemZ::A1 },
752
  { SystemZ::A2 },
753
  { SystemZ::A3 },
754
  { SystemZ::A4 },
755
  { SystemZ::A5 },
756
  { SystemZ::A6 },
757
  { SystemZ::A7 },
758
  { SystemZ::A8 },
759
  { SystemZ::A9 },
760
  { SystemZ::A10 },
761
  { SystemZ::A11 },
762
  { SystemZ::A12 },
763
  { SystemZ::A13 },
764
  { SystemZ::A14 },
765
  { SystemZ::A15 },
766
  { SystemZ::C0 },
767
  { SystemZ::C1 },
768
  { SystemZ::C2 },
769
  { SystemZ::C3 },
770
  { SystemZ::C4 },
771
  { SystemZ::C5 },
772
  { SystemZ::C6 },
773
  { SystemZ::C7 },
774
  { SystemZ::C8 },
775
  { SystemZ::C9 },
776
  { SystemZ::C10 },
777
  { SystemZ::C11 },
778
  { SystemZ::C12 },
779
  { SystemZ::C13 },
780
  { SystemZ::C14 },
781
  { SystemZ::C15 },
782
  { SystemZ::F0S },
783
  { SystemZ::F1S },
784
  { SystemZ::F2S },
785
  { SystemZ::F3S },
786
  { SystemZ::F4S },
787
  { SystemZ::F5S },
788
  { SystemZ::F6S },
789
  { SystemZ::F7S },
790
  { SystemZ::F8S },
791
  { SystemZ::F9S },
792
  { SystemZ::F10S },
793
  { SystemZ::F11S },
794
  { SystemZ::F12S },
795
  { SystemZ::F13S },
796
  { SystemZ::F14S },
797
  { SystemZ::F15S },
798
  { SystemZ::F16S },
799
  { SystemZ::F17S },
800
  { SystemZ::F18S },
801
  { SystemZ::F19S },
802
  { SystemZ::F20S },
803
  { SystemZ::F21S },
804
  { SystemZ::F22S },
805
  { SystemZ::F23S },
806
  { SystemZ::F24S },
807
  { SystemZ::F25S },
808
  { SystemZ::F26S },
809
  { SystemZ::F27S },
810
  { SystemZ::F28S },
811
  { SystemZ::F29S },
812
  { SystemZ::F30S },
813
  { SystemZ::F31S },
814
  { SystemZ::R0L },
815
  { SystemZ::R0H },
816
  { SystemZ::R1L },
817
  { SystemZ::R1H },
818
  { SystemZ::R2L },
819
  { SystemZ::R2H },
820
  { SystemZ::R3L },
821
  { SystemZ::R3H },
822
  { SystemZ::R4L },
823
  { SystemZ::R4H },
824
  { SystemZ::R5L },
825
  { SystemZ::R5H },
826
  { SystemZ::R6L },
827
  { SystemZ::R6H },
828
  { SystemZ::R7L },
829
  { SystemZ::R7H },
830
  { SystemZ::R8L },
831
  { SystemZ::R8H },
832
  { SystemZ::R9L },
833
  { SystemZ::R9H },
834
  { SystemZ::R10L },
835
  { SystemZ::R10H },
836
  { SystemZ::R11L },
837
  { SystemZ::R11H },
838
  { SystemZ::R12L },
839
  { SystemZ::R12H },
840
  { SystemZ::R13L },
841
  { SystemZ::R13H },
842
  { SystemZ::R14L },
843
  { SystemZ::R14H },
844
  { SystemZ::R15L },
845
  { SystemZ::R15H },
846
};
847
848
namespace {     // Register classes...
849
  // GRX32Bit Register Class...
850
  const MCPhysReg GRX32Bit[] = {
851
    SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4H, SystemZ::R5H, SystemZ::R15L, SystemZ::R15H, SystemZ::R14L, SystemZ::R14H, SystemZ::R13L, SystemZ::R13H, SystemZ::R12L, SystemZ::R12H, SystemZ::R11L, SystemZ::R11H, SystemZ::R10L, SystemZ::R10H, SystemZ::R9L, SystemZ::R9H, SystemZ::R8L, SystemZ::R8H, SystemZ::R7L, SystemZ::R7H, SystemZ::R6L, SystemZ::R6H, 
852
  };
853
854
  // GRX32Bit Bit set.
855
  const uint8_t GRX32BitBits[] = {
856
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, 
857
  };
858
859
  // VR32Bit Register Class...
860
  const MCPhysReg VR32Bit[] = {
861
    SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S, SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S, SystemZ::F24S, SystemZ::F25S, SystemZ::F26S, SystemZ::F27S, SystemZ::F28S, SystemZ::F29S, SystemZ::F30S, SystemZ::F31S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S, 
862
  };
863
864
  // VR32Bit Bit set.
865
  const uint8_t VR32BitBits[] = {
866
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, 
867
  };
868
869
  // AR32Bit Register Class...
870
  const MCPhysReg AR32Bit[] = {
871
    SystemZ::A0, SystemZ::A1, SystemZ::A2, SystemZ::A3, SystemZ::A4, SystemZ::A5, SystemZ::A6, SystemZ::A7, SystemZ::A8, SystemZ::A9, SystemZ::A10, SystemZ::A11, SystemZ::A12, SystemZ::A13, SystemZ::A14, SystemZ::A15, 
872
  };
873
874
  // AR32Bit Bit set.
875
  const uint8_t AR32BitBits[] = {
876
    0xfc, 0xff, 0x03, 
877
  };
878
879
  // FP32Bit Register Class...
880
  const MCPhysReg FP32Bit[] = {
881
    SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S, 
882
  };
883
884
  // FP32Bit Bit set.
885
  const uint8_t FP32BitBits[] = {
886
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 
887
  };
888
889
  // GR32Bit Register Class...
890
  const MCPhysReg GR32Bit[] = {
891
    SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R15L, SystemZ::R14L, SystemZ::R13L, SystemZ::R12L, SystemZ::R11L, SystemZ::R10L, SystemZ::R9L, SystemZ::R8L, SystemZ::R7L, SystemZ::R6L, 
892
  };
893
894
  // GR32Bit Bit set.
895
  const uint8_t GR32BitBits[] = {
896
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 
897
  };
898
899
  // GRH32Bit Register Class...
900
  const MCPhysReg GRH32Bit[] = {
901
    SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4H, SystemZ::R5H, SystemZ::R15H, SystemZ::R14H, SystemZ::R13H, SystemZ::R12H, SystemZ::R11H, SystemZ::R10H, SystemZ::R9H, SystemZ::R8H, SystemZ::R7H, SystemZ::R6H, 
902
  };
903
904
  // GRH32Bit Bit set.
905
  const uint8_t GRH32BitBits[] = {
906
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 
907
  };
908
909
  // ADDR32Bit Register Class...
910
  const MCPhysReg ADDR32Bit[] = {
911
    SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R15L, SystemZ::R14L, SystemZ::R13L, SystemZ::R12L, SystemZ::R11L, SystemZ::R10L, SystemZ::R9L, SystemZ::R8L, SystemZ::R7L, SystemZ::R6L, 
912
  };
913
914
  // ADDR32Bit Bit set.
915
  const uint8_t ADDR32BitBits[] = {
916
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, 
917
  };
918
919
  // CCR Register Class...
920
  const MCPhysReg CCR[] = {
921
    SystemZ::CC, 
922
  };
923
924
  // CCR Bit set.
925
  const uint8_t CCRBits[] = {
926
    0x02, 
927
  };
928
929
  // AnyRegBit Register Class...
930
  const MCPhysReg AnyRegBit[] = {
931
    SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15, 
932
  };
933
934
  // AnyRegBit Bit set.
935
  const uint8_t AnyRegBitBits[] = {
936
    0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0xfc, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 
937
  };
938
939
  // AnyRegBit_with_subreg_h32_in_FP32Bit Register Class...
940
  const MCPhysReg AnyRegBit_with_subreg_h32_in_FP32Bit[] = {
941
    SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15, 
942
  };
943
944
  // AnyRegBit_with_subreg_h32_in_FP32Bit Bit set.
945
  const uint8_t AnyRegBit_with_subreg_h32_in_FP32BitBits[] = {
946
    0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0xfc, 0xff, 0x03, 
947
  };
948
949
  // VR64Bit Register Class...
950
  const MCPhysReg VR64Bit[] = {
951
    SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D, SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D, SystemZ::F24D, SystemZ::F25D, SystemZ::F26D, SystemZ::F27D, SystemZ::F28D, SystemZ::F29D, SystemZ::F30D, SystemZ::F31D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 
952
  };
953
954
  // VR64Bit Bit set.
955
  const uint8_t VR64BitBits[] = {
956
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, 
957
  };
958
959
  // AnyRegBit_with_subreg_h64 Register Class...
960
  const MCPhysReg AnyRegBit_with_subreg_h64[] = {
961
    SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15, 
962
  };
963
964
  // AnyRegBit_with_subreg_h64 Bit set.
965
  const uint8_t AnyRegBit_with_subreg_h64Bits[] = {
966
    0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 
967
  };
968
969
  // CR64Bit Register Class...
970
  const MCPhysReg CR64Bit[] = {
971
    SystemZ::C0, SystemZ::C1, SystemZ::C2, SystemZ::C3, SystemZ::C4, SystemZ::C5, SystemZ::C6, SystemZ::C7, SystemZ::C8, SystemZ::C9, SystemZ::C10, SystemZ::C11, SystemZ::C12, SystemZ::C13, SystemZ::C14, SystemZ::C15, 
972
  };
973
974
  // CR64Bit Bit set.
975
  const uint8_t CR64BitBits[] = {
976
    0x00, 0x00, 0xfc, 0xff, 0x03, 
977
  };
978
979
  // FP64Bit Register Class...
980
  const MCPhysReg FP64Bit[] = {
981
    SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 
982
  };
983
984
  // FP64Bit Bit set.
985
  const uint8_t FP64BitBits[] = {
986
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 
987
  };
988
989
  // GR64Bit Register Class...
990
  const MCPhysReg GR64Bit[] = {
991
    SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R15D, SystemZ::R14D, SystemZ::R13D, SystemZ::R12D, SystemZ::R11D, SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, SystemZ::R6D, 
992
  };
993
994
  // GR64Bit Bit set.
995
  const uint8_t GR64BitBits[] = {
996
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 
997
  };
998
999
  // ADDR64Bit Register Class...
1000
  const MCPhysReg ADDR64Bit[] = {
1001
    SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R15D, SystemZ::R14D, SystemZ::R13D, SystemZ::R12D, SystemZ::R11D, SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, SystemZ::R6D, 
1002
  };
1003
1004
  // ADDR64Bit Bit set.
1005
  const uint8_t ADDR64BitBits[] = {
1006
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, 
1007
  };
1008
1009
  // VR128Bit Register Class...
1010
  const MCPhysReg VR128Bit[] = {
1011
    SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15, 
1012
  };
1013
1014
  // VR128Bit Bit set.
1015
  const uint8_t VR128BitBits[] = {
1016
    0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, 
1017
  };
1018
1019
  // VF128Bit Register Class...
1020
  const MCPhysReg VF128Bit[] = {
1021
    SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15, 
1022
  };
1023
1024
  // VF128Bit Bit set.
1025
  const uint8_t VF128BitBits[] = {
1026
    0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 
1027
  };
1028
1029
  // FP128Bit Register Class...
1030
  const MCPhysReg FP128Bit[] = {
1031
    SystemZ::F0Q, SystemZ::F1Q, SystemZ::F4Q, SystemZ::F5Q, SystemZ::F8Q, SystemZ::F9Q, SystemZ::F12Q, SystemZ::F13Q, 
1032
  };
1033
1034
  // FP128Bit Bit set.
1035
  const uint8_t FP128BitBits[] = {
1036
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 
1037
  };
1038
1039
  // GR128Bit Register Class...
1040
  const MCPhysReg GR128Bit[] = {
1041
    SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, SystemZ::R12Q, SystemZ::R10Q, SystemZ::R8Q, SystemZ::R6Q, SystemZ::R14Q, 
1042
  };
1043
1044
  // GR128Bit Bit set.
1045
  const uint8_t GR128BitBits[] = {
1046
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 
1047
  };
1048
1049
  // ADDR128Bit Register Class...
1050
  const MCPhysReg ADDR128Bit[] = {
1051
    SystemZ::R2Q, SystemZ::R4Q, SystemZ::R12Q, SystemZ::R10Q, SystemZ::R8Q, SystemZ::R6Q, SystemZ::R14Q, 
1052
  };
1053
1054
  // ADDR128Bit Bit set.
1055
  const uint8_t ADDR128BitBits[] = {
1056
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 
1057
  };
1058
1059
} // end anonymous namespace
1060
1061
extern const char SystemZRegClassStrings[] = {
1062
  /* 0 */ 'A', 'n', 'y', 'R', 'e', 'g', 'B', 'i', 't', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'r', 'e', 'g', '_', 'h', '6', '4', 0,
1063
  /* 26 */ 'C', 'C', 'R', 0,
1064
  /* 30 */ 'G', 'R', 'H', '3', '2', 'B', 'i', 't', 0,
1065
  /* 39 */ 'A', 'n', 'y', 'R', 'e', 'g', 'B', 'i', 't', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'r', 'e', 'g', '_', 'h', '3', '2', '_', 'i', 'n', '_', 'F', 'P', '3', '2', 'B', 'i', 't', 0,
1066
  /* 76 */ 'A', 'R', '3', '2', 'B', 'i', 't', 0,
1067
  /* 84 */ 'A', 'D', 'D', 'R', '3', '2', 'B', 'i', 't', 0,
1068
  /* 94 */ 'G', 'R', '3', '2', 'B', 'i', 't', 0,
1069
  /* 102 */ 'V', 'R', '3', '2', 'B', 'i', 't', 0,
1070
  /* 110 */ 'G', 'R', 'X', '3', '2', 'B', 'i', 't', 0,
1071
  /* 119 */ 'F', 'P', '6', '4', 'B', 'i', 't', 0,
1072
  /* 127 */ 'C', 'R', '6', '4', 'B', 'i', 't', 0,
1073
  /* 135 */ 'A', 'D', 'D', 'R', '6', '4', 'B', 'i', 't', 0,
1074
  /* 145 */ 'G', 'R', '6', '4', 'B', 'i', 't', 0,
1075
  /* 153 */ 'V', 'R', '6', '4', 'B', 'i', 't', 0,
1076
  /* 161 */ 'V', 'F', '1', '2', '8', 'B', 'i', 't', 0,
1077
  /* 170 */ 'F', 'P', '1', '2', '8', 'B', 'i', 't', 0,
1078
  /* 179 */ 'A', 'D', 'D', 'R', '1', '2', '8', 'B', 'i', 't', 0,
1079
  /* 190 */ 'G', 'R', '1', '2', '8', 'B', 'i', 't', 0,
1080
  /* 199 */ 'V', 'R', '1', '2', '8', 'B', 'i', 't', 0,
1081
  /* 208 */ 'A', 'n', 'y', 'R', 'e', 'g', 'B', 'i', 't', 0,
1082
};
1083
1084
extern const MCRegisterClass SystemZMCRegisterClasses[] = {
1085
  { GRX32Bit, GRX32BitBits, 110, 32, sizeof(GRX32BitBits), SystemZ::GRX32BitRegClassID, 1, true },
1086
  { VR32Bit, VR32BitBits, 102, 32, sizeof(VR32BitBits), SystemZ::VR32BitRegClassID, 1, true },
1087
  { AR32Bit, AR32BitBits, 76, 16, sizeof(AR32BitBits), SystemZ::AR32BitRegClassID, 1, false },
1088
  { FP32Bit, FP32BitBits, 68, 16, sizeof(FP32BitBits), SystemZ::FP32BitRegClassID, 1, true },
1089
  { GR32Bit, GR32BitBits, 94, 16, sizeof(GR32BitBits), SystemZ::GR32BitRegClassID, 1, true },
1090
  { GRH32Bit, GRH32BitBits, 30, 16, sizeof(GRH32BitBits), SystemZ::GRH32BitRegClassID, 1, true },
1091
  { ADDR32Bit, ADDR32BitBits, 84, 15, sizeof(ADDR32BitBits), SystemZ::ADDR32BitRegClassID, 1, true },
1092
  { CCR, CCRBits, 26, 1, sizeof(CCRBits), SystemZ::CCRRegClassID, -1, false },
1093
  { AnyRegBit, AnyRegBitBits, 208, 48, sizeof(AnyRegBitBits), SystemZ::AnyRegBitRegClassID, 1, false },
1094
  { AnyRegBit_with_subreg_h32_in_FP32Bit, AnyRegBit_with_subreg_h32_in_FP32BitBits, 39, 32, sizeof(AnyRegBit_with_subreg_h32_in_FP32BitBits), SystemZ::AnyRegBit_with_subreg_h32_in_FP32BitRegClassID, 1, false },
1095
  { VR64Bit, VR64BitBits, 153, 32, sizeof(VR64BitBits), SystemZ::VR64BitRegClassID, 1, true },
1096
  { AnyRegBit_with_subreg_h64, AnyRegBit_with_subreg_h64Bits, 0, 16, sizeof(AnyRegBit_with_subreg_h64Bits), SystemZ::AnyRegBit_with_subreg_h64RegClassID, 1, false },
1097
  { CR64Bit, CR64BitBits, 127, 16, sizeof(CR64BitBits), SystemZ::CR64BitRegClassID, 1, false },
1098
  { FP64Bit, FP64BitBits, 119, 16, sizeof(FP64BitBits), SystemZ::FP64BitRegClassID, 1, true },
1099
  { GR64Bit, GR64BitBits, 145, 16, sizeof(GR64BitBits), SystemZ::GR64BitRegClassID, 1, true },
1100
  { ADDR64Bit, ADDR64BitBits, 135, 15, sizeof(ADDR64BitBits), SystemZ::ADDR64BitRegClassID, 1, true },
1101
  { VR128Bit, VR128BitBits, 199, 32, sizeof(VR128BitBits), SystemZ::VR128BitRegClassID, 1, true },
1102
  { VF128Bit, VF128BitBits, 161, 16, sizeof(VF128BitBits), SystemZ::VF128BitRegClassID, 1, true },
1103
  { FP128Bit, FP128BitBits, 170, 8, sizeof(FP128BitBits), SystemZ::FP128BitRegClassID, 1, true },
1104
  { GR128Bit, GR128BitBits, 190, 8, sizeof(GR128BitBits), SystemZ::GR128BitRegClassID, 1, true },
1105
  { ADDR128Bit, ADDR128BitBits, 179, 7, sizeof(ADDR128BitBits), SystemZ::ADDR128BitRegClassID, 1, true },
1106
};
1107
1108
// SystemZ Dwarf<->LLVM register mappings.
1109
extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0Dwarf2L[] = {
1110
  { 0U, SystemZ::R0D },
1111
  { 1U, SystemZ::R1D },
1112
  { 2U, SystemZ::R2D },
1113
  { 3U, SystemZ::R3D },
1114
  { 4U, SystemZ::R4D },
1115
  { 5U, SystemZ::R5D },
1116
  { 6U, SystemZ::R6D },
1117
  { 7U, SystemZ::R7D },
1118
  { 8U, SystemZ::R8D },
1119
  { 9U, SystemZ::R9D },
1120
  { 10U, SystemZ::R10D },
1121
  { 11U, SystemZ::R11D },
1122
  { 12U, SystemZ::R12D },
1123
  { 13U, SystemZ::R13D },
1124
  { 14U, SystemZ::R14D },
1125
  { 15U, SystemZ::R15D },
1126
  { 16U, SystemZ::F0D },
1127
  { 17U, SystemZ::F2D },
1128
  { 18U, SystemZ::F4D },
1129
  { 19U, SystemZ::F6D },
1130
  { 20U, SystemZ::F1D },
1131
  { 21U, SystemZ::F3D },
1132
  { 22U, SystemZ::F5D },
1133
  { 23U, SystemZ::F7D },
1134
  { 24U, SystemZ::F8D },
1135
  { 25U, SystemZ::F10D },
1136
  { 26U, SystemZ::F12D },
1137
  { 27U, SystemZ::F14D },
1138
  { 28U, SystemZ::F9D },
1139
  { 29U, SystemZ::F11D },
1140
  { 30U, SystemZ::F13D },
1141
  { 31U, SystemZ::F15D },
1142
  { 32U, SystemZ::C0 },
1143
  { 33U, SystemZ::C1 },
1144
  { 34U, SystemZ::C2 },
1145
  { 35U, SystemZ::C3 },
1146
  { 36U, SystemZ::C4 },
1147
  { 37U, SystemZ::C5 },
1148
  { 38U, SystemZ::C6 },
1149
  { 39U, SystemZ::C7 },
1150
  { 40U, SystemZ::C8 },
1151
  { 41U, SystemZ::C9 },
1152
  { 42U, SystemZ::C10 },
1153
  { 43U, SystemZ::C11 },
1154
  { 44U, SystemZ::C12 },
1155
  { 45U, SystemZ::C13 },
1156
  { 46U, SystemZ::C14 },
1157
  { 47U, SystemZ::C15 },
1158
  { 48U, SystemZ::A0 },
1159
  { 49U, SystemZ::A1 },
1160
  { 50U, SystemZ::A2 },
1161
  { 51U, SystemZ::A3 },
1162
  { 52U, SystemZ::A4 },
1163
  { 53U, SystemZ::A5 },
1164
  { 54U, SystemZ::A6 },
1165
  { 55U, SystemZ::A7 },
1166
  { 56U, SystemZ::A8 },
1167
  { 57U, SystemZ::A9 },
1168
  { 58U, SystemZ::A10 },
1169
  { 59U, SystemZ::A11 },
1170
  { 60U, SystemZ::A12 },
1171
  { 61U, SystemZ::A13 },
1172
  { 62U, SystemZ::A14 },
1173
  { 63U, SystemZ::A15 },
1174
  { 68U, SystemZ::F16D },
1175
  { 69U, SystemZ::F18D },
1176
  { 70U, SystemZ::F20D },
1177
  { 71U, SystemZ::F22D },
1178
  { 72U, SystemZ::F17D },
1179
  { 73U, SystemZ::F19D },
1180
  { 74U, SystemZ::F21D },
1181
  { 75U, SystemZ::F23D },
1182
  { 76U, SystemZ::F24D },
1183
  { 77U, SystemZ::F26D },
1184
  { 78U, SystemZ::F28D },
1185
  { 79U, SystemZ::F30D },
1186
  { 80U, SystemZ::F25D },
1187
  { 81U, SystemZ::F27D },
1188
  { 82U, SystemZ::F29D },
1189
  { 83U, SystemZ::F31D },
1190
};
1191
extern const unsigned SystemZDwarfFlavour0Dwarf2LSize = array_lengthof(SystemZDwarfFlavour0Dwarf2L);
1192
1193
extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0Dwarf2L[] = {
1194
  { 0U, SystemZ::R0D },
1195
  { 1U, SystemZ::R1D },
1196
  { 2U, SystemZ::R2D },
1197
  { 3U, SystemZ::R3D },
1198
  { 4U, SystemZ::R4D },
1199
  { 5U, SystemZ::R5D },
1200
  { 6U, SystemZ::R6D },
1201
  { 7U, SystemZ::R7D },
1202
  { 8U, SystemZ::R8D },
1203
  { 9U, SystemZ::R9D },
1204
  { 10U, SystemZ::R10D },
1205
  { 11U, SystemZ::R11D },
1206
  { 12U, SystemZ::R12D },
1207
  { 13U, SystemZ::R13D },
1208
  { 14U, SystemZ::R14D },
1209
  { 15U, SystemZ::R15D },
1210
  { 16U, SystemZ::F0D },
1211
  { 17U, SystemZ::F2D },
1212
  { 18U, SystemZ::F4D },
1213
  { 19U, SystemZ::F6D },
1214
  { 20U, SystemZ::F1D },
1215
  { 21U, SystemZ::F3D },
1216
  { 22U, SystemZ::F5D },
1217
  { 23U, SystemZ::F7D },
1218
  { 24U, SystemZ::F8D },
1219
  { 25U, SystemZ::F10D },
1220
  { 26U, SystemZ::F12D },
1221
  { 27U, SystemZ::F14D },
1222
  { 28U, SystemZ::F9D },
1223
  { 29U, SystemZ::F11D },
1224
  { 30U, SystemZ::F13D },
1225
  { 31U, SystemZ::F15D },
1226
  { 32U, SystemZ::C0 },
1227
  { 33U, SystemZ::C1 },
1228
  { 34U, SystemZ::C2 },
1229
  { 35U, SystemZ::C3 },
1230
  { 36U, SystemZ::C4 },
1231
  { 37U, SystemZ::C5 },
1232
  { 38U, SystemZ::C6 },
1233
  { 39U, SystemZ::C7 },
1234
  { 40U, SystemZ::C8 },
1235
  { 41U, SystemZ::C9 },
1236
  { 42U, SystemZ::C10 },
1237
  { 43U, SystemZ::C11 },
1238
  { 44U, SystemZ::C12 },
1239
  { 45U, SystemZ::C13 },
1240
  { 46U, SystemZ::C14 },
1241
  { 47U, SystemZ::C15 },
1242
  { 48U, SystemZ::A0 },
1243
  { 49U, SystemZ::A1 },
1244
  { 50U, SystemZ::A2 },
1245
  { 51U, SystemZ::A3 },
1246
  { 52U, SystemZ::A4 },
1247
  { 53U, SystemZ::A5 },
1248
  { 54U, SystemZ::A6 },
1249
  { 55U, SystemZ::A7 },
1250
  { 56U, SystemZ::A8 },
1251
  { 57U, SystemZ::A9 },
1252
  { 58U, SystemZ::A10 },
1253
  { 59U, SystemZ::A11 },
1254
  { 60U, SystemZ::A12 },
1255
  { 61U, SystemZ::A13 },
1256
  { 62U, SystemZ::A14 },
1257
  { 63U, SystemZ::A15 },
1258
  { 68U, SystemZ::F16D },
1259
  { 69U, SystemZ::F18D },
1260
  { 70U, SystemZ::F20D },
1261
  { 71U, SystemZ::F22D },
1262
  { 72U, SystemZ::F17D },
1263
  { 73U, SystemZ::F19D },
1264
  { 74U, SystemZ::F21D },
1265
  { 75U, SystemZ::F23D },
1266
  { 76U, SystemZ::F24D },
1267
  { 77U, SystemZ::F26D },
1268
  { 78U, SystemZ::F28D },
1269
  { 79U, SystemZ::F30D },
1270
  { 80U, SystemZ::F25D },
1271
  { 81U, SystemZ::F27D },
1272
  { 82U, SystemZ::F29D },
1273
  { 83U, SystemZ::F31D },
1274
};
1275
extern const unsigned SystemZEHFlavour0Dwarf2LSize = array_lengthof(SystemZEHFlavour0Dwarf2L);
1276
1277
extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0L2Dwarf[] = {
1278
  { SystemZ::A0, 48U },
1279
  { SystemZ::A1, 49U },
1280
  { SystemZ::A2, 50U },
1281
  { SystemZ::A3, 51U },
1282
  { SystemZ::A4, 52U },
1283
  { SystemZ::A5, 53U },
1284
  { SystemZ::A6, 54U },
1285
  { SystemZ::A7, 55U },
1286
  { SystemZ::A8, 56U },
1287
  { SystemZ::A9, 57U },
1288
  { SystemZ::A10, 58U },
1289
  { SystemZ::A11, 59U },
1290
  { SystemZ::A12, 60U },
1291
  { SystemZ::A13, 61U },
1292
  { SystemZ::A14, 62U },
1293
  { SystemZ::A15, 63U },
1294
  { SystemZ::C0, 32U },
1295
  { SystemZ::C1, 33U },
1296
  { SystemZ::C2, 34U },
1297
  { SystemZ::C3, 35U },
1298
  { SystemZ::C4, 36U },
1299
  { SystemZ::C5, 37U },
1300
  { SystemZ::C6, 38U },
1301
  { SystemZ::C7, 39U },
1302
  { SystemZ::C8, 40U },
1303
  { SystemZ::C9, 41U },
1304
  { SystemZ::C10, 42U },
1305
  { SystemZ::C11, 43U },
1306
  { SystemZ::C12, 44U },
1307
  { SystemZ::C13, 45U },
1308
  { SystemZ::C14, 46U },
1309
  { SystemZ::C15, 47U },
1310
  { SystemZ::V0, 16U },
1311
  { SystemZ::V1, 20U },
1312
  { SystemZ::V2, 17U },
1313
  { SystemZ::V3, 21U },
1314
  { SystemZ::V4, 18U },
1315
  { SystemZ::V5, 22U },
1316
  { SystemZ::V6, 19U },
1317
  { SystemZ::V7, 23U },
1318
  { SystemZ::V8, 24U },
1319
  { SystemZ::V9, 28U },
1320
  { SystemZ::V10, 25U },
1321
  { SystemZ::V11, 29U },
1322
  { SystemZ::V12, 26U },
1323
  { SystemZ::V13, 30U },
1324
  { SystemZ::V14, 27U },
1325
  { SystemZ::V15, 31U },
1326
  { SystemZ::V16, 68U },
1327
  { SystemZ::V17, 72U },
1328
  { SystemZ::V18, 69U },
1329
  { SystemZ::V19, 73U },
1330
  { SystemZ::V20, 70U },
1331
  { SystemZ::V21, 74U },
1332
  { SystemZ::V22, 71U },
1333
  { SystemZ::V23, 75U },
1334
  { SystemZ::V24, 76U },
1335
  { SystemZ::V25, 80U },
1336
  { SystemZ::V26, 77U },
1337
  { SystemZ::V27, 81U },
1338
  { SystemZ::V28, 78U },
1339
  { SystemZ::V29, 82U },
1340
  { SystemZ::V30, 79U },
1341
  { SystemZ::V31, 83U },
1342
  { SystemZ::F0D, 16U },
1343
  { SystemZ::F1D, 20U },
1344
  { SystemZ::F2D, 17U },
1345
  { SystemZ::F3D, 21U },
1346
  { SystemZ::F4D, 18U },
1347
  { SystemZ::F5D, 22U },
1348
  { SystemZ::F6D, 19U },
1349
  { SystemZ::F7D, 23U },
1350
  { SystemZ::F8D, 24U },
1351
  { SystemZ::F9D, 28U },
1352
  { SystemZ::F10D, 25U },
1353
  { SystemZ::F11D, 29U },
1354
  { SystemZ::F12D, 26U },
1355
  { SystemZ::F13D, 30U },
1356
  { SystemZ::F14D, 27U },
1357
  { SystemZ::F15D, 31U },
1358
  { SystemZ::F16D, 68U },
1359
  { SystemZ::F17D, 72U },
1360
  { SystemZ::F18D, 69U },
1361
  { SystemZ::F19D, 73U },
1362
  { SystemZ::F20D, 70U },
1363
  { SystemZ::F21D, 74U },
1364
  { SystemZ::F22D, 71U },
1365
  { SystemZ::F23D, 75U },
1366
  { SystemZ::F24D, 76U },
1367
  { SystemZ::F25D, 80U },
1368
  { SystemZ::F26D, 77U },
1369
  { SystemZ::F27D, 81U },
1370
  { SystemZ::F28D, 78U },
1371
  { SystemZ::F29D, 82U },
1372
  { SystemZ::F30D, 79U },
1373
  { SystemZ::F31D, 83U },
1374
  { SystemZ::R0D, 0U },
1375
  { SystemZ::R1D, 1U },
1376
  { SystemZ::R2D, 2U },
1377
  { SystemZ::R3D, 3U },
1378
  { SystemZ::R4D, 4U },
1379
  { SystemZ::R5D, 5U },
1380
  { SystemZ::R6D, 6U },
1381
  { SystemZ::R7D, 7U },
1382
  { SystemZ::R8D, 8U },
1383
  { SystemZ::R9D, 9U },
1384
  { SystemZ::R10D, 10U },
1385
  { SystemZ::R11D, 11U },
1386
  { SystemZ::R12D, 12U },
1387
  { SystemZ::R13D, 13U },
1388
  { SystemZ::R14D, 14U },
1389
  { SystemZ::R15D, 15U },
1390
};
1391
extern const unsigned SystemZDwarfFlavour0L2DwarfSize = array_lengthof(SystemZDwarfFlavour0L2Dwarf);
1392
1393
extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0L2Dwarf[] = {
1394
  { SystemZ::A0, 48U },
1395
  { SystemZ::A1, 49U },
1396
  { SystemZ::A2, 50U },
1397
  { SystemZ::A3, 51U },
1398
  { SystemZ::A4, 52U },
1399
  { SystemZ::A5, 53U },
1400
  { SystemZ::A6, 54U },
1401
  { SystemZ::A7, 55U },
1402
  { SystemZ::A8, 56U },
1403
  { SystemZ::A9, 57U },
1404
  { SystemZ::A10, 58U },
1405
  { SystemZ::A11, 59U },
1406
  { SystemZ::A12, 60U },
1407
  { SystemZ::A13, 61U },
1408
  { SystemZ::A14, 62U },
1409
  { SystemZ::A15, 63U },
1410
  { SystemZ::C0, 32U },
1411
  { SystemZ::C1, 33U },
1412
  { SystemZ::C2, 34U },
1413
  { SystemZ::C3, 35U },
1414
  { SystemZ::C4, 36U },
1415
  { SystemZ::C5, 37U },
1416
  { SystemZ::C6, 38U },
1417
  { SystemZ::C7, 39U },
1418
  { SystemZ::C8, 40U },
1419
  { SystemZ::C9, 41U },
1420
  { SystemZ::C10, 42U },
1421
  { SystemZ::C11, 43U },
1422
  { SystemZ::C12, 44U },
1423
  { SystemZ::C13, 45U },
1424
  { SystemZ::C14, 46U },
1425
  { SystemZ::C15, 47U },
1426
  { SystemZ::V0, 16U },
1427
  { SystemZ::V1, 20U },
1428
  { SystemZ::V2, 17U },
1429
  { SystemZ::V3, 21U },
1430
  { SystemZ::V4, 18U },
1431
  { SystemZ::V5, 22U },
1432
  { SystemZ::V6, 19U },
1433
  { SystemZ::V7, 23U },
1434
  { SystemZ::V8, 24U },
1435
  { SystemZ::V9, 28U },
1436
  { SystemZ::V10, 25U },
1437
  { SystemZ::V11, 29U },
1438
  { SystemZ::V12, 26U },
1439
  { SystemZ::V13, 30U },
1440
  { SystemZ::V14, 27U },
1441
  { SystemZ::V15, 31U },
1442
  { SystemZ::V16, 68U },
1443
  { SystemZ::V17, 72U },
1444
  { SystemZ::V18, 69U },
1445
  { SystemZ::V19, 73U },
1446
  { SystemZ::V20, 70U },
1447
  { SystemZ::V21, 74U },
1448
  { SystemZ::V22, 71U },
1449
  { SystemZ::V23, 75U },
1450
  { SystemZ::V24, 76U },
1451
  { SystemZ::V25, 80U },
1452
  { SystemZ::V26, 77U },
1453
  { SystemZ::V27, 81U },
1454
  { SystemZ::V28, 78U },
1455
  { SystemZ::V29, 82U },
1456
  { SystemZ::V30, 79U },
1457
  { SystemZ::V31, 83U },
1458
  { SystemZ::F0D, 16U },
1459
  { SystemZ::F1D, 20U },
1460
  { SystemZ::F2D, 17U },
1461
  { SystemZ::F3D, 21U },
1462
  { SystemZ::F4D, 18U },
1463
  { SystemZ::F5D, 22U },
1464
  { SystemZ::F6D, 19U },
1465
  { SystemZ::F7D, 23U },
1466
  { SystemZ::F8D, 24U },
1467
  { SystemZ::F9D, 28U },
1468
  { SystemZ::F10D, 25U },
1469
  { SystemZ::F11D, 29U },
1470
  { SystemZ::F12D, 26U },
1471
  { SystemZ::F13D, 30U },
1472
  { SystemZ::F14D, 27U },
1473
  { SystemZ::F15D, 31U },
1474
  { SystemZ::F16D, 68U },
1475
  { SystemZ::F17D, 72U },
1476
  { SystemZ::F18D, 69U },
1477
  { SystemZ::F19D, 73U },
1478
  { SystemZ::F20D, 70U },
1479
  { SystemZ::F21D, 74U },
1480
  { SystemZ::F22D, 71U },
1481
  { SystemZ::F23D, 75U },
1482
  { SystemZ::F24D, 76U },
1483
  { SystemZ::F25D, 80U },
1484
  { SystemZ::F26D, 77U },
1485
  { SystemZ::F27D, 81U },
1486
  { SystemZ::F28D, 78U },
1487
  { SystemZ::F29D, 82U },
1488
  { SystemZ::F30D, 79U },
1489
  { SystemZ::F31D, 83U },
1490
  { SystemZ::R0D, 0U },
1491
  { SystemZ::R1D, 1U },
1492
  { SystemZ::R2D, 2U },
1493
  { SystemZ::R3D, 3U },
1494
  { SystemZ::R4D, 4U },
1495
  { SystemZ::R5D, 5U },
1496
  { SystemZ::R6D, 6U },
1497
  { SystemZ::R7D, 7U },
1498
  { SystemZ::R8D, 8U },
1499
  { SystemZ::R9D, 9U },
1500
  { SystemZ::R10D, 10U },
1501
  { SystemZ::R11D, 11U },
1502
  { SystemZ::R12D, 12U },
1503
  { SystemZ::R13D, 13U },
1504
  { SystemZ::R14D, 14U },
1505
  { SystemZ::R15D, 15U },
1506
};
1507
extern const unsigned SystemZEHFlavour0L2DwarfSize = array_lengthof(SystemZEHFlavour0L2Dwarf);
1508
1509
extern const uint16_t SystemZRegEncodingTable[] = {
1510
  0,
1511
  0,
1512
  0,
1513
  1,
1514
  2,
1515
  3,
1516
  4,
1517
  5,
1518
  6,
1519
  7,
1520
  8,
1521
  9,
1522
  10,
1523
  11,
1524
  12,
1525
  13,
1526
  14,
1527
  15,
1528
  0,
1529
  1,
1530
  2,
1531
  3,
1532
  4,
1533
  5,
1534
  6,
1535
  7,
1536
  8,
1537
  9,
1538
  10,
1539
  11,
1540
  12,
1541
  13,
1542
  14,
1543
  15,
1544
  0,
1545
  1,
1546
  2,
1547
  3,
1548
  4,
1549
  5,
1550
  6,
1551
  7,
1552
  8,
1553
  9,
1554
  10,
1555
  11,
1556
  12,
1557
  13,
1558
  14,
1559
  15,
1560
  16,
1561
  17,
1562
  18,
1563
  19,
1564
  20,
1565
  21,
1566
  22,
1567
  23,
1568
  24,
1569
  25,
1570
  26,
1571
  27,
1572
  28,
1573
  29,
1574
  30,
1575
  31,
1576
  0,
1577
  1,
1578
  2,
1579
  3,
1580
  4,
1581
  5,
1582
  6,
1583
  7,
1584
  8,
1585
  9,
1586
  10,
1587
  11,
1588
  12,
1589
  13,
1590
  14,
1591
  15,
1592
  16,
1593
  17,
1594
  18,
1595
  19,
1596
  20,
1597
  21,
1598
  22,
1599
  23,
1600
  24,
1601
  25,
1602
  26,
1603
  27,
1604
  28,
1605
  29,
1606
  30,
1607
  31,
1608
  0,
1609
  1,
1610
  4,
1611
  5,
1612
  8,
1613
  9,
1614
  12,
1615
  13,
1616
  0,
1617
  1,
1618
  2,
1619
  3,
1620
  4,
1621
  5,
1622
  6,
1623
  7,
1624
  8,
1625
  9,
1626
  10,
1627
  11,
1628
  12,
1629
  13,
1630
  14,
1631
  15,
1632
  16,
1633
  17,
1634
  18,
1635
  19,
1636
  20,
1637
  21,
1638
  22,
1639
  23,
1640
  24,
1641
  25,
1642
  26,
1643
  27,
1644
  28,
1645
  29,
1646
  30,
1647
  31,
1648
  0,
1649
  1,
1650
  2,
1651
  3,
1652
  4,
1653
  5,
1654
  6,
1655
  7,
1656
  8,
1657
  9,
1658
  10,
1659
  11,
1660
  12,
1661
  13,
1662
  14,
1663
  15,
1664
  0,
1665
  1,
1666
  2,
1667
  3,
1668
  4,
1669
  5,
1670
  6,
1671
  7,
1672
  8,
1673
  9,
1674
  10,
1675
  11,
1676
  12,
1677
  13,
1678
  14,
1679
  15,
1680
  0,
1681
  1,
1682
  2,
1683
  3,
1684
  4,
1685
  5,
1686
  6,
1687
  7,
1688
  8,
1689
  9,
1690
  10,
1691
  11,
1692
  12,
1693
  13,
1694
  14,
1695
  15,
1696
  0,
1697
  2,
1698
  4,
1699
  6,
1700
  8,
1701
  10,
1702
  12,
1703
  14,
1704
};
1705
1.03k
static inline void InitSystemZMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
1706
1.03k
  RI->InitMCRegisterInfo(SystemZRegDesc, 194, RA, PC, SystemZMCRegisterClasses, 21, SystemZRegUnitRoots, 97, SystemZRegDiffLists, SystemZLaneMaskLists, SystemZRegStrings, SystemZRegClassStrings, SystemZSubRegIdxLists, 7,
1707
1.03k
SystemZSubRegIdxRanges, SystemZRegEncodingTable);
1708
1.03k
1709
1.03k
  switch (DwarfFlavour) {
1710
1.03k
  default:
1711
0
    llvm_unreachable("Unknown DWARF flavour");
1712
1.03k
  case 0:
1713
1.03k
    RI->mapDwarfRegsToLLVMRegs(SystemZDwarfFlavour0Dwarf2L, SystemZDwarfFlavour0Dwarf2LSize, false);
1714
1.03k
    break;
1715
1.03k
  }
1716
1.03k
  switch (EHFlavour) {
1717
1.03k
  default:
1718
0
    llvm_unreachable("Unknown DWARF flavour");
1719
1.03k
  case 0:
1720
1.03k
    RI->mapDwarfRegsToLLVMRegs(SystemZEHFlavour0Dwarf2L, SystemZEHFlavour0Dwarf2LSize, true);
1721
1.03k
    break;
1722
1.03k
  }
1723
1.03k
  switch (DwarfFlavour) {
1724
1.03k
  default:
1725
0
    llvm_unreachable("Unknown DWARF flavour");
1726
1.03k
  case 0:
1727
1.03k
    RI->mapLLVMRegsToDwarfRegs(SystemZDwarfFlavour0L2Dwarf, SystemZDwarfFlavour0L2DwarfSize, false);
1728
1.03k
    break;
1729
1.03k
  }
1730
1.03k
  switch (EHFlavour) {
1731
1.03k
  default:
1732
0
    llvm_unreachable("Unknown DWARF flavour");
1733
1.03k
  case 0:
1734
1.03k
    RI->mapLLVMRegsToDwarfRegs(SystemZEHFlavour0L2Dwarf, SystemZEHFlavour0L2DwarfSize, true);
1735
1.03k
    break;
1736
1.03k
  }
1737
1.03k
}
1738
1739
} // end namespace llvm
1740
1741
#endif // GET_REGINFO_MC_DESC
1742
1743
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
1744
|*                                                                            *|
1745
|* Register Information Header Fragment                                       *|
1746
|*                                                                            *|
1747
|* Automatically generated file, do not edit!                                 *|
1748
|*                                                                            *|
1749
\*===----------------------------------------------------------------------===*/
1750
1751
1752
#ifdef GET_REGINFO_HEADER
1753
#undef GET_REGINFO_HEADER
1754
1755
#include "llvm/CodeGen/TargetRegisterInfo.h"
1756
1757
namespace llvm {
1758
1759
class SystemZFrameLowering;
1760
1761
struct SystemZGenRegisterInfo : public TargetRegisterInfo {
1762
  explicit SystemZGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
1763
      unsigned PC = 0, unsigned HwMode = 0);
1764
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
1765
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
1766
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
1767
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
1768
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
1769
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
1770
  unsigned getNumRegPressureSets() const override;
1771
  const char *getRegPressureSetName(unsigned Idx) const override;
1772
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
1773
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
1774
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
1775
  ArrayRef<const char *> getRegMaskNames() const override;
1776
  ArrayRef<const uint32_t *> getRegMasks() const override;
1777
  /// Devirtualized TargetFrameLowering.
1778
  static const SystemZFrameLowering *getFrameLowering(
1779
      const MachineFunction &MF);
1780
};
1781
1782
namespace SystemZ { // Register classes
1783
  extern const TargetRegisterClass GRX32BitRegClass;
1784
  extern const TargetRegisterClass VR32BitRegClass;
1785
  extern const TargetRegisterClass AR32BitRegClass;
1786
  extern const TargetRegisterClass FP32BitRegClass;
1787
  extern const TargetRegisterClass GR32BitRegClass;
1788
  extern const TargetRegisterClass GRH32BitRegClass;
1789
  extern const TargetRegisterClass ADDR32BitRegClass;
1790
  extern const TargetRegisterClass CCRRegClass;
1791
  extern const TargetRegisterClass AnyRegBitRegClass;
1792
  extern const TargetRegisterClass AnyRegBit_with_subreg_h32_in_FP32BitRegClass;
1793
  extern const TargetRegisterClass VR64BitRegClass;
1794
  extern const TargetRegisterClass AnyRegBit_with_subreg_h64RegClass;
1795
  extern const TargetRegisterClass CR64BitRegClass;
1796
  extern const TargetRegisterClass FP64BitRegClass;
1797
  extern const TargetRegisterClass GR64BitRegClass;
1798
  extern const TargetRegisterClass ADDR64BitRegClass;
1799
  extern const TargetRegisterClass VR128BitRegClass;
1800
  extern const TargetRegisterClass VF128BitRegClass;
1801
  extern const TargetRegisterClass FP128BitRegClass;
1802
  extern const TargetRegisterClass GR128BitRegClass;
1803
  extern const TargetRegisterClass ADDR128BitRegClass;
1804
} // end namespace SystemZ
1805
1806
} // end namespace llvm
1807
1808
#endif // GET_REGINFO_HEADER
1809
1810
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
1811
|*                                                                            *|
1812
|* Target Register and Register Classes Information                           *|
1813
|*                                                                            *|
1814
|* Automatically generated file, do not edit!                                 *|
1815
|*                                                                            *|
1816
\*===----------------------------------------------------------------------===*/
1817
1818
1819
#ifdef GET_REGINFO_TARGET_DESC
1820
#undef GET_REGINFO_TARGET_DESC
1821
1822
namespace llvm {
1823
1824
extern const MCRegisterClass SystemZMCRegisterClasses[];
1825
1826
static const MVT::SimpleValueType VTLists[] = {
1827
  /* 0 */ MVT::i32, MVT::Other,
1828
  /* 2 */ MVT::i64, MVT::Other,
1829
  /* 4 */ MVT::f32, MVT::Other,
1830
  /* 6 */ MVT::f64, MVT::Other,
1831
  /* 8 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::f128, MVT::Other,
1832
  /* 16 */ MVT::f32, MVT::v4i8, MVT::v2i16, MVT::Other,
1833
  /* 20 */ MVT::i64, MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v2f32, MVT::Other,
1834
  /* 27 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::Other,
1835
  /* 34 */ MVT::Untyped, MVT::Other,
1836
};
1837
1838
static const char *const SubRegIndexNameTable[] = { "subreg_h32", "subreg_h64", "subreg_hh32", "subreg_hl32", "subreg_l32", "subreg_l64", "" };
1839
1840
1841
static const LaneBitmask SubRegIndexLaneMaskTable[] = {
1842
  LaneBitmask::getAll(),
1843
  LaneBitmask(0x00000001), // subreg_h32
1844
  LaneBitmask(0x00000006), // subreg_h64
1845
  LaneBitmask(0x00000002), // subreg_hh32
1846
  LaneBitmask(0x00000004), // subreg_hl32
1847
  LaneBitmask(0x00000008), // subreg_l32
1848
  LaneBitmask(0x00000009), // subreg_l64
1849
 };
1850
1851
1852
1853
static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
1854
  // Mode = 0 (Default)
1855
  { 32, 32, 32, VTLists+0 },    // GRX32Bit
1856
  { 32, 32, 32, VTLists+16 },    // VR32Bit
1857
  { 32, 32, 32, VTLists+0 },    // AR32Bit
1858
  { 32, 32, 32, VTLists+4 },    // FP32Bit
1859
  { 32, 32, 32, VTLists+0 },    // GR32Bit
1860
  { 32, 32, 32, VTLists+0 },    // GRH32Bit
1861
  { 32, 32, 32, VTLists+0 },    // ADDR32Bit
1862
  { 32, 32, 32, VTLists+0 },    // CCR
1863
  { 64, 64, 64, VTLists+20 },    // AnyRegBit
1864
  { 64, 64, 64, VTLists+20 },    // AnyRegBit_with_subreg_h32_in_FP32Bit
1865
  { 64, 64, 64, VTLists+21 },    // VR64Bit
1866
  { 64, 64, 64, VTLists+20 },    // AnyRegBit_with_subreg_h64
1867
  { 64, 64, 64, VTLists+2 },    // CR64Bit
1868
  { 64, 64, 64, VTLists+6 },    // FP64Bit
1869
  { 64, 64, 64, VTLists+2 },    // GR64Bit
1870
  { 64, 64, 64, VTLists+2 },    // ADDR64Bit
1871
  { 128, 128, 128, VTLists+8 },    // VR128Bit
1872
  { 128, 128, 128, VTLists+27 },    // VF128Bit
1873
  { 128, 128, 128, VTLists+14 },    // FP128Bit
1874
  { 128, 128, 128, VTLists+34 },    // GR128Bit
1875
  { 128, 128, 128, VTLists+34 },    // ADDR128Bit
1876
};
1877
1878
static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
1879
1880
static const uint32_t GRX32BitSubClassMask[] = {
1881
  0x00000071, 
1882
  0x0018c000, // subreg_h32
1883
  0x00180000, // subreg_hh32
1884
  0x00180000, // subreg_hl32
1885
  0x0018c000, // subreg_l32
1886
};
1887
1888
static const uint32_t VR32BitSubClassMask[] = {
1889
  0x0000000a, 
1890
  0x00072e00, // subreg_h32
1891
  0x00040000, // subreg_hh32
1892
};
1893
1894
static const uint32_t AR32BitSubClassMask[] = {
1895
  0x00000004, 
1896
};
1897
1898
static const uint32_t FP32BitSubClassMask[] = {
1899
  0x00000008, 
1900
  0x00062a00, // subreg_h32
1901
  0x00040000, // subreg_hh32
1902
};
1903
1904
static const uint32_t GR32BitSubClassMask[] = {
1905
  0x00000050, 
1906
  0x00180000, // subreg_hl32
1907
  0x0018c000, // subreg_l32
1908
};
1909
1910
static const uint32_t GRH32BitSubClassMask[] = {
1911
  0x00000020, 
1912
  0x0018c000, // subreg_h32
1913
  0x00180000, // subreg_hh32
1914
};
1915
1916
static const uint32_t ADDR32BitSubClassMask[] = {
1917
  0x00000040, 
1918
  0x00100000, // subreg_hl32
1919
  0x00188000, // subreg_l32
1920
};
1921
1922
static const uint32_t CCRSubClassMask[] = {
1923
  0x00000080, 
1924
};
1925
1926
static const uint32_t AnyRegBitSubClassMask[] = {
1927
  0x0002eb00, 
1928
  0x001e0800, // subreg_h64
1929
  0x001c0000, // subreg_l64
1930
};
1931
1932
static const uint32_t AnyRegBit_with_subreg_h32_in_FP32BitSubClassMask[] = {
1933
  0x00022a00, 
1934
  0x00060800, // subreg_h64
1935
  0x00040000, // subreg_l64
1936
};
1937
1938
static const uint32_t VR64BitSubClassMask[] = {
1939
  0x00002400, 
1940
  0x00070800, // subreg_h64
1941
  0x00040000, // subreg_l64
1942
};
1943
1944
static const uint32_t AnyRegBit_with_subreg_h64SubClassMask[] = {
1945
  0x00020800, 
1946
};
1947
1948
static const uint32_t CR64BitSubClassMask[] = {
1949
  0x00001000, 
1950
};
1951
1952
static const uint32_t FP64BitSubClassMask[] = {
1953
  0x00002000, 
1954
  0x00060800, // subreg_h64
1955
  0x00040000, // subreg_l64
1956
};
1957
1958
static const uint32_t GR64BitSubClassMask[] = {
1959
  0x0000c000, 
1960
  0x00180000, // subreg_h64
1961
  0x00180000, // subreg_l64
1962
};
1963
1964
static const uint32_t ADDR64BitSubClassMask[] = {
1965
  0x00008000, 
1966
  0x00100000, // subreg_h64
1967
  0x00180000, // subreg_l64
1968
};
1969
1970
static const uint32_t VR128BitSubClassMask[] = {
1971
  0x00030000, 
1972
};
1973
1974
static const uint32_t VF128BitSubClassMask[] = {
1975
  0x00020000, 
1976
};
1977
1978
static const uint32_t FP128BitSubClassMask[] = {
1979
  0x00040000, 
1980
};
1981
1982
static const uint32_t GR128BitSubClassMask[] = {
1983
  0x00180000, 
1984
};
1985
1986
static const uint32_t ADDR128BitSubClassMask[] = {
1987
  0x00100000, 
1988
};
1989
1990
static const uint16_t SuperRegIdxSeqs[] = {
1991
  /* 0 */ 1, 3, 0,
1992
  /* 3 */ 1, 3, 4, 5, 0,
1993
  /* 8 */ 2, 6, 0,
1994
};
1995
1996
static const TargetRegisterClass *const FP32BitSuperclasses[] = {
1997
  &SystemZ::VR32BitRegClass,
1998
  nullptr
1999
};
2000
2001
static const TargetRegisterClass *const GR32BitSuperclasses[] = {
2002
  &SystemZ::GRX32BitRegClass,
2003
  nullptr
2004
};
2005
2006
static const TargetRegisterClass *const GRH32BitSuperclasses[] = {
2007
  &SystemZ::GRX32BitRegClass,
2008
  nullptr
2009
};
2010
2011
static const TargetRegisterClass *const ADDR32BitSuperclasses[] = {
2012
  &SystemZ::GRX32BitRegClass,
2013
  &SystemZ::GR32BitRegClass,
2014
  nullptr
2015
};
2016
2017
static const TargetRegisterClass *const AnyRegBit_with_subreg_h32_in_FP32BitSuperclasses[] = {
2018
  &SystemZ::AnyRegBitRegClass,
2019
  nullptr
2020
};
2021
2022
static const TargetRegisterClass *const AnyRegBit_with_subreg_h64Superclasses[] = {
2023
  &SystemZ::AnyRegBitRegClass,
2024
  &SystemZ::AnyRegBit_with_subreg_h32_in_FP32BitRegClass,
2025
  nullptr
2026
};
2027
2028
static const TargetRegisterClass *const FP64BitSuperclasses[] = {
2029
  &SystemZ::AnyRegBitRegClass,
2030
  &SystemZ::AnyRegBit_with_subreg_h32_in_FP32BitRegClass,
2031
  &SystemZ::VR64BitRegClass,
2032
  nullptr
2033
};
2034
2035
static const TargetRegisterClass *const GR64BitSuperclasses[] = {
2036
  &SystemZ::AnyRegBitRegClass,
2037
  nullptr
2038
};
2039
2040
static const TargetRegisterClass *const ADDR64BitSuperclasses[] = {
2041
  &SystemZ::AnyRegBitRegClass,
2042
  &SystemZ::GR64BitRegClass,
2043
  nullptr
2044
};
2045
2046
static const TargetRegisterClass *const VF128BitSuperclasses[] = {
2047
  &SystemZ::AnyRegBitRegClass,
2048
  &SystemZ::AnyRegBit_with_subreg_h32_in_FP32BitRegClass,
2049
  &SystemZ::AnyRegBit_with_subreg_h64RegClass,
2050
  &SystemZ::VR128BitRegClass,
2051
  nullptr
2052
};
2053
2054
static const TargetRegisterClass *const ADDR128BitSuperclasses[] = {
2055
  &SystemZ::GR128BitRegClass,
2056
  nullptr
2057
};
2058
2059
2060
namespace SystemZ {   // Register class instances
2061
  extern const TargetRegisterClass GRX32BitRegClass = {
2062
    &SystemZMCRegisterClasses[GRX32BitRegClassID],
2063
    GRX32BitSubClassMask,
2064
    SuperRegIdxSeqs + 3,
2065
    LaneBitmask(0x00000001),
2066
    0,
2067
    false, /* HasDisjunctSubRegs */
2068
    false, /* CoveredBySubRegs */
2069
    NullRegClasses,
2070
    nullptr
2071
  };
2072
2073
  extern const TargetRegisterClass VR32BitRegClass = {
2074
    &SystemZMCRegisterClasses[VR32BitRegClassID],
2075
    VR32BitSubClassMask,
2076
    SuperRegIdxSeqs + 0,
2077
    LaneBitmask(0x00000001),
2078
    0,
2079
    false, /* HasDisjunctSubRegs */
2080
    false, /* CoveredBySubRegs */
2081
    NullRegClasses,
2082
    nullptr
2083
  };
2084
2085
  extern const TargetRegisterClass AR32BitRegClass = {
2086
    &SystemZMCRegisterClasses[AR32BitRegClassID],
2087
    AR32BitSubClassMask,
2088
    SuperRegIdxSeqs + 2,
2089
    LaneBitmask(0x00000001),
2090
    0,
2091
    false, /* HasDisjunctSubRegs */
2092
    false, /* CoveredBySubRegs */
2093
    NullRegClasses,
2094
    nullptr
2095
  };
2096
2097
  extern const TargetRegisterClass FP32BitRegClass = {
2098
    &SystemZMCRegisterClasses[FP32BitRegClassID],
2099
    FP32BitSubClassMask,
2100
    SuperRegIdxSeqs + 0,
2101
    LaneBitmask(0x00000001),
2102
    0,
2103
    false, /* HasDisjunctSubRegs */
2104
    false, /* CoveredBySubRegs */
2105
    FP32BitSuperclasses,
2106
    nullptr
2107
  };
2108
2109
  extern const TargetRegisterClass GR32BitRegClass = {
2110
    &SystemZMCRegisterClasses[GR32BitRegClassID],
2111
    GR32BitSubClassMask,
2112
    SuperRegIdxSeqs + 5,
2113
    LaneBitmask(0x00000001),
2114
    0,
2115
    false, /* HasDisjunctSubRegs */
2116
    false, /* CoveredBySubRegs */
2117
    GR32BitSuperclasses,
2118
    nullptr
2119
  };
2120
2121
  extern const TargetRegisterClass GRH32BitRegClass = {
2122
    &SystemZMCRegisterClasses[GRH32BitRegClassID],
2123
    GRH32BitSubClassMask,
2124
    SuperRegIdxSeqs + 0,
2125
    LaneBitmask(0x00000001),
2126
    0,
2127
    false, /* HasDisjunctSubRegs */
2128
    false, /* CoveredBySubRegs */
2129
    GRH32BitSuperclasses,
2130
    nullptr
2131
  };
2132
2133
  extern const TargetRegisterClass ADDR32BitRegClass = {
2134
    &SystemZMCRegisterClasses[ADDR32BitRegClassID],
2135
    ADDR32BitSubClassMask,
2136
    SuperRegIdxSeqs + 5,
2137
    LaneBitmask(0x00000001),
2138
    0,
2139
    false, /* HasDisjunctSubRegs */
2140
    false, /* CoveredBySubRegs */
2141
    ADDR32BitSuperclasses,
2142
    nullptr
2143
  };
2144
2145
  extern const TargetRegisterClass CCRRegClass = {
2146
    &SystemZMCRegisterClasses[CCRRegClassID],
2147
    CCRSubClassMask,
2148
    SuperRegIdxSeqs + 2,
2149
    LaneBitmask(0x00000001),
2150
    0,
2151
    false, /* HasDisjunctSubRegs */
2152
    false, /* CoveredBySubRegs */
2153
    NullRegClasses,
2154
    nullptr
2155
  };
2156
2157
  extern const TargetRegisterClass AnyRegBitRegClass = {
2158
    &SystemZMCRegisterClasses[AnyRegBitRegClassID],
2159
    AnyRegBitSubClassMask,
2160
    SuperRegIdxSeqs + 8,
2161
    LaneBitmask(0x0000000F),
2162
    0,
2163
    true, /* HasDisjunctSubRegs */
2164
    false, /* CoveredBySubRegs */
2165
    NullRegClasses,
2166
    nullptr
2167
  };
2168
2169
  extern const TargetRegisterClass AnyRegBit_with_subreg_h32_in_FP32BitRegClass = {
2170
    &SystemZMCRegisterClasses[AnyRegBit_with_subreg_h32_in_FP32BitRegClassID],
2171
    AnyRegBit_with_subreg_h32_in_FP32BitSubClassMask,
2172
    SuperRegIdxSeqs + 8,
2173
    LaneBitmask(0x00000007),
2174
    0,
2175
    false, /* HasDisjunctSubRegs */
2176
    false, /* CoveredBySubRegs */
2177
    AnyRegBit_with_subreg_h32_in_FP32BitSuperclasses,
2178
    nullptr
2179
  };
2180
2181
  extern const TargetRegisterClass VR64BitRegClass = {
2182
    &SystemZMCRegisterClasses[VR64BitRegClassID],
2183
    VR64BitSubClassMask,
2184
    SuperRegIdxSeqs + 8,
2185
    LaneBitmask(0x00000001),
2186
    0,
2187
    false, /* HasDisjunctSubRegs */
2188
    false, /* CoveredBySubRegs */
2189
    NullRegClasses,
2190
    nullptr
2191
  };
2192
2193
  extern const TargetRegisterClass AnyRegBit_with_subreg_h64RegClass = {
2194
    &SystemZMCRegisterClasses[AnyRegBit_with_subreg_h64RegClassID],
2195
    AnyRegBit_with_subreg_h64SubClassMask,
2196
    SuperRegIdxSeqs + 2,
2197
    LaneBitmask(0x00000007),
2198
    0,
2199
    false, /* HasDisjunctSubRegs */
2200
    false, /* CoveredBySubRegs */
2201
    AnyRegBit_with_subreg_h64Superclasses,
2202
    nullptr
2203
  };
2204
2205
  extern const TargetRegisterClass CR64BitRegClass = {
2206
    &SystemZMCRegisterClasses[CR64BitRegClassID],
2207
    CR64BitSubClassMask,
2208
    SuperRegIdxSeqs + 2,
2209
    LaneBitmask(0x00000001),
2210
    0,
2211
    false, /* HasDisjunctSubRegs */
2212
    false, /* CoveredBySubRegs */
2213
    NullRegClasses,
2214
    nullptr
2215
  };
2216
2217
  extern const TargetRegisterClass FP64BitRegClass = {
2218
    &SystemZMCRegisterClasses[FP64BitRegClassID],
2219
    FP64BitSubClassMask,
2220
    SuperRegIdxSeqs + 8,
2221
    LaneBitmask(0x00000001),
2222
    0,
2223
    false, /* HasDisjunctSubRegs */
2224
    false, /* CoveredBySubRegs */
2225
    FP64BitSuperclasses,
2226
    nullptr
2227
  };
2228
2229
  extern const TargetRegisterClass GR64BitRegClass = {
2230
    &SystemZMCRegisterClasses[GR64BitRegClassID],
2231
    GR64BitSubClassMask,
2232
    SuperRegIdxSeqs + 8,
2233
    LaneBitmask(0x00000009),
2234
    0,
2235
    true, /* HasDisjunctSubRegs */
2236
    true, /* CoveredBySubRegs */
2237
    GR64BitSuperclasses,
2238
    nullptr
2239
  };
2240
2241
  extern const TargetRegisterClass ADDR64BitRegClass = {
2242
    &SystemZMCRegisterClasses[ADDR64BitRegClassID],
2243
    ADDR64BitSubClassMask,
2244
    SuperRegIdxSeqs + 8,
2245
    LaneBitmask(0x00000009),
2246
    0,
2247
    true, /* HasDisjunctSubRegs */
2248
    true, /* CoveredBySubRegs */
2249
    ADDR64BitSuperclasses,
2250
    nullptr
2251
  };
2252
2253
  extern const TargetRegisterClass VR128BitRegClass = {
2254
    &SystemZMCRegisterClasses[VR128BitRegClassID],
2255
    VR128BitSubClassMask,
2256
    SuperRegIdxSeqs + 2,
2257
    LaneBitmask(0x00000007),
2258
    0,
2259
    false, /* HasDisjunctSubRegs */
2260
    false, /* CoveredBySubRegs */
2261
    NullRegClasses,
2262
    nullptr
2263
  };
2264
2265
  extern const TargetRegisterClass VF128BitRegClass = {
2266
    &SystemZMCRegisterClasses[VF128BitRegClassID],
2267
    VF128BitSubClassMask,
2268
    SuperRegIdxSeqs + 2,
2269
    LaneBitmask(0x00000007),
2270
    0,
2271
    false, /* HasDisjunctSubRegs */
2272
    false, /* CoveredBySubRegs */
2273
    VF128BitSuperclasses,
2274
    nullptr
2275
  };
2276
2277
  extern const TargetRegisterClass FP128BitRegClass = {
2278
    &SystemZMCRegisterClasses[FP128BitRegClassID],
2279
    FP128BitSubClassMask,
2280
    SuperRegIdxSeqs + 2,
2281
    LaneBitmask(0x0000000F),
2282
    0,
2283
    true, /* HasDisjunctSubRegs */
2284
    true, /* CoveredBySubRegs */
2285
    NullRegClasses,
2286
    nullptr
2287
  };
2288
2289
  extern const TargetRegisterClass GR128BitRegClass = {
2290
    &SystemZMCRegisterClasses[GR128BitRegClassID],
2291
    GR128BitSubClassMask,
2292
    SuperRegIdxSeqs + 2,
2293
    LaneBitmask(0x0000000F),
2294
    0,
2295
    true, /* HasDisjunctSubRegs */
2296
    true, /* CoveredBySubRegs */
2297
    NullRegClasses,
2298
    nullptr
2299
  };
2300
2301
  extern const TargetRegisterClass ADDR128BitRegClass = {
2302
    &SystemZMCRegisterClasses[ADDR128BitRegClassID],
2303
    ADDR128BitSubClassMask,
2304
    SuperRegIdxSeqs + 2,
2305
    LaneBitmask(0x0000000F),
2306
    0,
2307
    true, /* HasDisjunctSubRegs */
2308
    true, /* CoveredBySubRegs */
2309
    ADDR128BitSuperclasses,
2310
    nullptr
2311
  };
2312
2313
} // end namespace SystemZ
2314
2315
namespace {
2316
  const TargetRegisterClass* const RegisterClasses[] = {
2317
    &SystemZ::GRX32BitRegClass,
2318
    &SystemZ::VR32BitRegClass,
2319
    &SystemZ::AR32BitRegClass,
2320
    &SystemZ::FP32BitRegClass,
2321
    &SystemZ::GR32BitRegClass,
2322
    &SystemZ::GRH32BitRegClass,
2323
    &SystemZ::ADDR32BitRegClass,
2324
    &SystemZ::CCRRegClass,
2325
    &SystemZ::AnyRegBitRegClass,
2326
    &SystemZ::AnyRegBit_with_subreg_h32_in_FP32BitRegClass,
2327
    &SystemZ::VR64BitRegClass,
2328
    &SystemZ::AnyRegBit_with_subreg_h64RegClass,
2329
    &SystemZ::CR64BitRegClass,
2330
    &SystemZ::FP64BitRegClass,
2331
    &SystemZ::GR64BitRegClass,
2332
    &SystemZ::ADDR64BitRegClass,
2333
    &SystemZ::VR128BitRegClass,
2334
    &SystemZ::VF128BitRegClass,
2335
    &SystemZ::FP128BitRegClass,
2336
    &SystemZ::GR128BitRegClass,
2337
    &SystemZ::ADDR128BitRegClass,
2338
  };
2339
} // end anonymous namespace
2340
2341
static const TargetRegisterInfoDesc SystemZRegInfoDesc[] = { // Extra Descriptors
2342
  { 0, false },
2343
  { 0, false },
2344
  { 0, false },
2345
  { 0, false },
2346
  { 0, false },
2347
  { 0, false },
2348
  { 0, false },
2349
  { 0, false },
2350
  { 0, false },
2351
  { 0, false },
2352
  { 0, false },
2353
  { 0, false },
2354
  { 0, false },
2355
  { 0, false },
2356
  { 0, false },
2357
  { 0, false },
2358
  { 0, false },
2359
  { 0, false },
2360
  { 0, false },
2361
  { 0, false },
2362
  { 0, false },
2363
  { 0, false },
2364
  { 0, false },
2365
  { 0, false },
2366
  { 0, false },
2367
  { 0, false },
2368
  { 0, false },
2369
  { 0, false },
2370
  { 0, false },
2371
  { 0, false },
2372
  { 0, false },
2373
  { 0, false },
2374
  { 0, false },
2375
  { 0, false },
2376
  { 0, true },
2377
  { 0, true },
2378
  { 0, true },
2379
  { 0, true },
2380
  { 0, true },
2381
  { 0, true },
2382
  { 0, true },
2383
  { 0, true },
2384
  { 0, true },
2385
  { 0, true },
2386
  { 0, true },
2387
  { 0, true },
2388
  { 0, true },
2389
  { 0, true },
2390
  { 0, true },
2391
  { 0, true },
2392
  { 0, true },
2393
  { 0, true },
2394
  { 0, true },
2395
  { 0, true },
2396
  { 0, true },
2397
  { 0, true },
2398
  { 0, true },
2399
  { 0, true },
2400
  { 0, true },
2401
  { 0, true },
2402
  { 0, true },
2403
  { 0, true },
2404
  { 0, true },
2405
  { 0, true },
2406
  { 0, true },
2407
  { 0, true },
2408
  { 0, true },
2409
  { 0, true },
2410
  { 0, true },
2411
  { 0, true },
2412
  { 0, true },
2413
  { 0, true },
2414
  { 0, true },
2415
  { 0, true },
2416
  { 0, true },
2417
  { 0, true },
2418
  { 0, true },
2419
  { 0, true },
2420
  { 0, true },
2421
  { 0, true },
2422
  { 0, true },
2423
  { 0, true },
2424
  { 0, true },
2425
  { 0, true },
2426
  { 0, true },
2427
  { 0, true },
2428
  { 0, true },
2429
  { 0, true },
2430
  { 0, true },
2431
  { 0, true },
2432
  { 0, true },
2433
  { 0, true },
2434
  { 0, true },
2435
  { 0, true },
2436
  { 0, true },
2437
  { 0, true },
2438
  { 0, true },
2439
  { 0, true },
2440
  { 0, true },
2441
  { 0, true },
2442
  { 0, true },
2443
  { 0, true },
2444
  { 0, true },
2445
  { 0, true },
2446
  { 0, true },
2447
  { 0, true },
2448
  { 0, true },
2449
  { 0, true },
2450
  { 0, true },
2451
  { 0, true },
2452
  { 0, true },
2453
  { 0, true },
2454
  { 0, true },
2455
  { 0, true },
2456
  { 0, true },
2457
  { 0, true },
2458
  { 0, true },
2459
  { 0, true },
2460
  { 0, true },
2461
  { 0, true },
2462
  { 0, true },
2463
  { 0, true },
2464
  { 0, true },
2465
  { 0, true },
2466
  { 0, true },
2467
  { 0, true },
2468
  { 0, true },
2469
  { 0, true },
2470
  { 0, true },
2471
  { 0, true },
2472
  { 0, true },
2473
  { 0, true },
2474
  { 0, true },
2475
  { 0, true },
2476
  { 0, true },
2477
  { 0, true },
2478
  { 0, true },
2479
  { 0, true },
2480
  { 0, true },
2481
  { 0, true },
2482
  { 0, true },
2483
  { 0, true },
2484
  { 0, true },
2485
  { 0, true },
2486
  { 0, true },
2487
  { 0, true },
2488
  { 0, true },
2489
  { 0, true },
2490
  { 0, true },
2491
  { 0, true },
2492
  { 0, true },
2493
  { 0, true },
2494
  { 0, true },
2495
  { 0, true },
2496
  { 0, true },
2497
  { 0, true },
2498
  { 0, true },
2499
  { 0, true },
2500
  { 0, true },
2501
  { 0, true },
2502
  { 0, true },
2503
  { 0, true },
2504
  { 0, true },
2505
  { 0, true },
2506
  { 0, true },
2507
  { 0, true },
2508
  { 0, true },
2509
  { 0, true },
2510
  { 0, true },
2511
  { 0, true },
2512
  { 0, true },
2513
  { 0, true },
2514
  { 0, true },
2515
  { 0, true },
2516
  { 0, true },
2517
  { 0, true },
2518
  { 0, true },
2519
  { 0, true },
2520
  { 0, true },
2521
  { 0, true },
2522
  { 0, true },
2523
  { 0, true },
2524
  { 0, true },
2525
  { 0, true },
2526
  { 0, true },
2527
  { 0, true },
2528
  { 0, true },
2529
  { 0, true },
2530
  { 0, true },
2531
  { 0, true },
2532
  { 0, true },
2533
  { 0, true },
2534
  { 0, true },
2535
  { 0, true },
2536
};
2537
87
unsigned SystemZGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
2538
87
  static const uint8_t RowMap[6] = {
2539
87
    0, 0, 0, 0, 0, 1, 
2540
87
  };
2541
87
  static const uint8_t Rows[2][6] = {
2542
87
    { 3, 0, 0, 0, 4, 0, },
2543
87
    { 1, 0, 0, 0, 5, 0, },
2544
87
  };
2545
87
2546
87
  --IdxA; assert(IdxA < 6);
2547
87
  --IdxB; assert(IdxB < 6);
2548
87
  return Rows[RowMap[IdxA]][IdxB];
2549
87
}
2550
2551
  struct MaskRolOp {
2552
    LaneBitmask Mask;
2553
    uint8_t  RotateLeft;
2554
  };
2555
  static const MaskRolOp LaneMaskComposeSequences[] = {
2556
    { LaneBitmask(0xFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
2557
    { LaneBitmask(0x00000001),  1 }, { LaneBitmask(0x00000008), 31 }, { LaneBitmask::getNone(), 0 },   // Sequence 2
2558
    { LaneBitmask(0xFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 5
2559
    { LaneBitmask(0xFFFFFFFF),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 7
2560
    { LaneBitmask(0xFFFFFFFF),  3 }, { LaneBitmask::getNone(), 0 }  // Sequence 9
2561
  };
2562
  static const MaskRolOp *const CompositeSequences[] = {
2563
    &LaneMaskComposeSequences[0], // to subreg_h32
2564
    &LaneMaskComposeSequences[2], // to subreg_h64
2565
    &LaneMaskComposeSequences[5], // to subreg_hh32
2566
    &LaneMaskComposeSequences[7], // to subreg_hl32
2567
    &LaneMaskComposeSequences[9], // to subreg_l32
2568
    &LaneMaskComposeSequences[0] // to subreg_l64
2569
  };
2570
2571
11
LaneBitmask SystemZGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
2572
11
  --IdxA; assert(IdxA < 6 && "Subregister index out of bounds");
2573
11
  LaneBitmask Result;
2574
26
  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); 
++Ops15
) {
2575
15
    LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
2576
15
    if (unsigned S = Ops->RotateLeft)
2577
13
      Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
2578
2
    else
2579
2
      Result |= LaneBitmask(M);
2580
15
  }
2581
11
  return Result;
2582
11
}
2583
2584
21
LaneBitmask SystemZGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
2585
21
  LaneMask &= getSubRegIndexLaneMask(IdxA);
2586
21
  --IdxA; assert(IdxA < 6 && "Subregister index out of bounds");
2587
21
  LaneBitmask Result;
2588
46
  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); 
++Ops25
) {
2589
25
    LaneBitmask::Type M = LaneMask.getAsInteger();
2590
25
    if (unsigned S = Ops->RotateLeft)
2591
16
      Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
2592
9
    else
2593
9
      Result |= LaneBitmask(M);
2594
25
  }
2595
21
  return Result;
2596
21
}
2597
2598
4.82k
const TargetRegisterClass *SystemZGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
2599
4.82k
  static const uint8_t Table[21][6] = {
2600
4.82k
    { // GRX32Bit
2601
4.82k
      0,  // subreg_h32
2602
4.82k
      0,  // subreg_h64
2603
4.82k
      0,  // subreg_hh32
2604
4.82k
      0,  // subreg_hl32
2605
4.82k
      0,  // subreg_l32
2606
4.82k
      0,  // subreg_l64
2607
4.82k
    },
2608
4.82k
    { // VR32Bit
2609
4.82k
      0,  // subreg_h32
2610
4.82k
      0,  // subreg_h64
2611
4.82k
      0,  // subreg_hh32
2612
4.82k
      0,  // subreg_hl32
2613
4.82k
      0,  // subreg_l32
2614
4.82k
      0,  // subreg_l64
2615
4.82k
    },
2616
4.82k
    { // AR32Bit
2617
4.82k
      0,  // subreg_h32
2618
4.82k
      0,  // subreg_h64
2619
4.82k
      0,  // subreg_hh32
2620
4.82k
      0,  // subreg_hl32
2621
4.82k
      0,  // subreg_l32
2622
4.82k
      0,  // subreg_l64
2623
4.82k
    },
2624
4.82k
    { // FP32Bit
2625
4.82k
      0,  // subreg_h32
2626
4.82k
      0,  // subreg_h64
2627
4.82k
      0,  // subreg_hh32
2628
4.82k
      0,  // subreg_hl32
2629
4.82k
      0,  // subreg_l32
2630
4.82k
      0,  // subreg_l64
2631
4.82k
    },
2632
4.82k
    { // GR32Bit
2633
4.82k
      0,  // subreg_h32
2634
4.82k
      0,  // subreg_h64
2635
4.82k
      0,  // subreg_hh32
2636
4.82k
      0,  // subreg_hl32
2637
4.82k
      0,  // subreg_l32
2638
4.82k
      0,  // subreg_l64
2639
4.82k
    },
2640
4.82k
    { // GRH32Bit
2641
4.82k
      0,  // subreg_h32
2642
4.82k
      0,  // subreg_h64
2643
4.82k
      0,  // subreg_hh32
2644
4.82k
      0,  // subreg_hl32
2645
4.82k
      0,  // subreg_l32
2646
4.82k
      0,  // subreg_l64
2647
4.82k
    },
2648
4.82k
    { // ADDR32Bit
2649
4.82k
      0,  // subreg_h32
2650
4.82k
      0,  // subreg_h64
2651
4.82k
      0,  // subreg_hh32
2652
4.82k
      0,  // subreg_hl32
2653
4.82k
      0,  // subreg_l32
2654
4.82k
      0,  // subreg_l64
2655
4.82k
    },
2656
4.82k
    { // CCR
2657
4.82k
      0,  // subreg_h32
2658
4.82k
      0,  // subreg_h64
2659
4.82k
      0,  // subreg_hh32
2660
4.82k
      0,  // subreg_hl32
2661
4.82k
      0,  // subreg_l32
2662
4.82k
      0,  // subreg_l64
2663
4.82k
    },
2664
4.82k
    { // AnyRegBit
2665
4.82k
      9,  // subreg_h32 -> AnyRegBit
2666
4.82k
      12, // subreg_h64 -> AnyRegBit_with_subreg_h64
2667
4.82k
      0,  // subreg_hh32
2668
4.82k
      0,  // subreg_hl32
2669
4.82k
      15, // subreg_l32 -> GR64Bit
2670
4.82k
      0,  // subreg_l64
2671
4.82k
    },
2672
4.82k
    { // AnyRegBit_with_subreg_h32_in_FP32Bit
2673
4.82k
      10, // subreg_h32 -> AnyRegBit_with_subreg_h32_in_FP32Bit
2674
4.82k
      12, // subreg_h64 -> AnyRegBit_with_subreg_h64
2675
4.82k
      0,  // subreg_hh32
2676
4.82k
      0,  // subreg_hl32
2677
4.82k
      0,  // subreg_l32
2678
4.82k
      0,  // subreg_l64
2679
4.82k
    },
2680
4.82k
    { // VR64Bit
2681
4.82k
      11, // subreg_h32 -> VR64Bit
2682
4.82k
      0,  // subreg_h64
2683
4.82k
      0,  // subreg_hh32
2684
4.82k
      0,  // subreg_hl32
2685
4.82k
      0,  // subreg_l32
2686
4.82k
      0,  // subreg_l64
2687
4.82k
    },
2688
4.82k
    { // AnyRegBit_with_subreg_h64
2689
4.82k
      12, // subreg_h32 -> AnyRegBit_with_subreg_h64
2690
4.82k
      12, // subreg_h64 -> AnyRegBit_with_subreg_h64
2691
4.82k
      0,  // subreg_hh32
2692
4.82k
      0,  // subreg_hl32
2693
4.82k
      0,  // subreg_l32
2694
4.82k
      0,  // subreg_l64
2695
4.82k
    },
2696
4.82k
    { // CR64Bit
2697
4.82k
      0,  // subreg_h32
2698
4.82k
      0,  // subreg_h64
2699
4.82k
      0,  // subreg_hh32
2700
4.82k
      0,  // subreg_hl32
2701
4.82k
      0,  // subreg_l32
2702
4.82k
      0,  // subreg_l64
2703
4.82k
    },
2704
4.82k
    { // FP64Bit
2705
4.82k
      14, // subreg_h32 -> FP64Bit
2706
4.82k
      0,  // subreg_h64
2707
4.82k
      0,  // subreg_hh32
2708
4.82k
      0,  // subreg_hl32
2709
4.82k
      0,  // subreg_l32
2710
4.82k
      0,  // subreg_l64
2711
4.82k
    },
2712
4.82k
    { // GR64Bit
2713
4.82k
      15, // subreg_h32 -> GR64Bit
2714
4.82k
      0,  // subreg_h64
2715
4.82k
      0,  // subreg_hh32
2716
4.82k
      0,  // subreg_hl32
2717
4.82k
      15, // subreg_l32 -> GR64Bit
2718
4.82k
      0,  // subreg_l64
2719
4.82k
    },
2720
4.82k
    { // ADDR64Bit
2721
4.82k
      16, // subreg_h32 -> ADDR64Bit
2722
4.82k
      0,  // subreg_h64
2723
4.82k
      0,  // subreg_hh32
2724
4.82k
      0,  // subreg_hl32
2725
4.82k
      16, // subreg_l32 -> ADDR64Bit
2726
4.82k
      0,  // subreg_l64
2727
4.82k
    },
2728
4.82k
    { // VR128Bit
2729
4.82k
      17, // subreg_h32 -> VR128Bit
2730
4.82k
      17, // subreg_h64 -> VR128Bit
2731
4.82k
      0,  // subreg_hh32
2732
4.82k
      0,  // subreg_hl32
2733
4.82k
      0,  // subreg_l32
2734
4.82k
      0,  // subreg_l64
2735
4.82k
    },
2736
4.82k
    { // VF128Bit
2737
4.82k
      18, // subreg_h32 -> VF128Bit
2738
4.82k
      18, // subreg_h64 -> VF128Bit
2739
4.82k
      0,  // subreg_hh32
2740
4.82k
      0,  // subreg_hl32
2741
4.82k
      0,  // subreg_l32
2742
4.82k
      0,  // subreg_l64
2743
4.82k
    },
2744
4.82k
    { // FP128Bit
2745
4.82k
      19, // subreg_h32 -> FP128Bit
2746
4.82k
      19, // subreg_h64 -> FP128Bit
2747
4.82k
      19, // subreg_hh32 -> FP128Bit
2748
4.82k
      0,  // subreg_hl32
2749
4.82k
      0,  // subreg_l32
2750
4.82k
      19, // subreg_l64 -> FP128Bit
2751
4.82k
    },
2752
4.82k
    { // GR128Bit
2753
4.82k
      20, // subreg_h32 -> GR128Bit
2754
4.82k
      20, // subreg_h64 -> GR128Bit
2755
4.82k
      20, // subreg_hh32 -> GR128Bit
2756
4.82k
      20, // subreg_hl32 -> GR128Bit
2757
4.82k
      20, // subreg_l32 -> GR128Bit
2758
4.82k
      20, // subreg_l64 -> GR128Bit
2759
4.82k
    },
2760
4.82k
    { // ADDR128Bit
2761
4.82k
      21, // subreg_h32 -> ADDR128Bit
2762
4.82k
      21, // subreg_h64 -> ADDR128Bit
2763
4.82k
      21, // subreg_hh32 -> ADDR128Bit
2764
4.82k
      21, // subreg_hl32 -> ADDR128Bit
2765
4.82k
      21, // subreg_l32 -> ADDR128Bit
2766
4.82k
      21, // subreg_l64 -> ADDR128Bit
2767
4.82k
    },
2768
4.82k
  };
2769
4.82k
  assert(RC && "Missing regclass");
2770
4.82k
  if (!Idx) 
return RC0
;
2771
4.82k
  --Idx;
2772
4.82k
  assert(Idx < 6 && "Bad subreg");
2773
4.82k
  unsigned TV = Table[RC->getID()][Idx];
2774
4.82k
  return TV ? getRegClass(TV - 1) : 
nullptr0
;
2775
4.82k
}
2776
2777
/// Get the weight in units of pressure for this register class.
2778
const RegClassWeight &SystemZGenRegisterInfo::
2779
118k
getRegClassWeight(const TargetRegisterClass *RC) const {
2780
118k
  static const RegClassWeight RCWeightTable[] = {
2781
118k
    {1, 32},    // GRX32Bit
2782
118k
    {1, 32},    // VR32Bit
2783
118k
    {0, 0},   // AR32Bit
2784
118k
    {1, 16},    // FP32Bit
2785
118k
    {1, 16},    // GR32Bit
2786
118k
    {1, 16},    // GRH32Bit
2787
118k
    {1, 15},    // ADDR32Bit
2788
118k
    {0, 0},   // CCR
2789
118k
    {1, 48},    // AnyRegBit
2790
118k
    {1, 16},    // AnyRegBit_with_subreg_h32_in_FP32Bit
2791
118k
    {1, 32},    // VR64Bit
2792
118k
    {1, 16},    // AnyRegBit_with_subreg_h64
2793
118k
    {0, 0},   // CR64Bit
2794
118k
    {1, 16},    // FP64Bit
2795
118k
    {2, 32},    // GR64Bit
2796
118k
    {2, 30},    // ADDR64Bit
2797
118k
    {1, 32},    // VR128Bit
2798
118k
    {1, 16},    // VF128Bit
2799
118k
    {2, 16},    // FP128Bit
2800
118k
    {4, 32},    // GR128Bit
2801
118k
    {4, 28},    // ADDR128Bit
2802
118k
  };
2803
118k
  return RCWeightTable[RC->getID()];
2804
118k
}
2805
2806
/// Get the weight in units of pressure for this register unit.
2807
unsigned SystemZGenRegisterInfo::
2808
18.0k
getRegUnitWeight(unsigned RegUnit) const {
2809
18.0k
  assert(RegUnit < 97 && "invalid register unit");
2810
18.0k
  // All register units have unit weight.
2811
18.0k
  return 1;
2812
18.0k
}
2813
2814
2815
// Get the number of dimensions of register pressure.
2816
13.8k
unsigned SystemZGenRegisterInfo::getNumRegPressureSets() const {
2817
13.8k
  return 5;
2818
13.8k
}
2819
2820
// Get the name of this register unit pressure set.
2821
const char *SystemZGenRegisterInfo::
2822
0
getRegPressureSetName(unsigned Idx) const {
2823
0
  static const char *const PressureNameTable[] = {
2824
0
    "FP32Bit",
2825
0
    "GR32Bit",
2826
0
    "GRH32Bit",
2827
0
    "GRX32Bit",
2828
0
    "VR32Bit",
2829
0
  };
2830
0
  return PressureNameTable[Idx];
2831
0
}
2832
2833
// Get the register unit pressure limit for this dimension.
2834
// This limit must be adjusted dynamically for reserved registers.
2835
unsigned SystemZGenRegisterInfo::
2836
37.1k
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
2837
37.1k
  static const uint8_t PressureLimitTable[] = {
2838
37.1k
    16,   // 0: FP32Bit
2839
37.1k
    16,   // 1: GR32Bit
2840
37.1k
    16,   // 2: GRH32Bit
2841
37.1k
    32,   // 3: GRX32Bit
2842
37.1k
    32,   // 4: VR32Bit
2843
37.1k
  };
2844
37.1k
  return PressureLimitTable[Idx];
2845
37.1k
}
2846
2847
/// Table of pressure sets per register class or unit.
2848
static const int RCSetsTable[] = {
2849
  /* 0 */ 1, 3, -1,
2850
  /* 3 */ 2, 3, -1,
2851
  /* 6 */ 0, 4, -1,
2852
};
2853
2854
/// Get the dimensions of register pressure impacted by this register class.
2855
/// Returns a -1 terminated array of pressure set IDs
2856
const int* SystemZGenRegisterInfo::
2857
132k
getRegClassPressureSets(const TargetRegisterClass *RC) const {
2858
132k
  static const uint8_t RCSetStartTable[] = {
2859
132k
    1,7,2,6,0,3,0,2,2,2,7,2,2,6,1,1,7,6,6,1,1,};
2860
132k
  return &RCSetsTable[RCSetStartTable[RC->getID()]];
2861
132k
}
2862
2863
/// Get the dimensions of register pressure impacted by this register unit.
2864
/// Returns a -1 terminated array of pressure set IDs
2865
const int* SystemZGenRegisterInfo::
2866
18.0k
getRegUnitPressureSets(unsigned RegUnit) const {
2867
18.0k
  assert(RegUnit < 97 && "invalid register unit");
2868
18.0k
  static const uint8_t RUSetStartTable[] = {
2869
18.0k
    2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,};
2870
18.0k
  return &RCSetsTable[RUSetStartTable[RegUnit]];
2871
18.0k
}
2872
2873
extern const MCRegisterDesc SystemZRegDesc[];
2874
extern const MCPhysReg SystemZRegDiffLists[];
2875
extern const LaneBitmask SystemZLaneMaskLists[];
2876
extern const char SystemZRegStrings[];
2877
extern const char SystemZRegClassStrings[];
2878
extern const MCPhysReg SystemZRegUnitRoots[][2];
2879
extern const uint16_t SystemZSubRegIdxLists[];
2880
extern const MCRegisterInfo::SubRegCoveredBits SystemZSubRegIdxRanges[];
2881
extern const uint16_t SystemZRegEncodingTable[];
2882
// SystemZ Dwarf<->LLVM register mappings.
2883
extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0Dwarf2L[];
2884
extern const unsigned SystemZDwarfFlavour0Dwarf2LSize;
2885
2886
extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0Dwarf2L[];
2887
extern const unsigned SystemZEHFlavour0Dwarf2LSize;
2888
2889
extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0L2Dwarf[];
2890
extern const unsigned SystemZDwarfFlavour0L2DwarfSize;
2891
2892
extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0L2Dwarf[];
2893
extern const unsigned SystemZEHFlavour0L2DwarfSize;
2894
2895
SystemZGenRegisterInfo::
2896
SystemZGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
2897
      unsigned PC, unsigned HwMode)
2898
  : TargetRegisterInfo(SystemZRegInfoDesc, RegisterClasses, RegisterClasses+21,
2899
             SubRegIndexNameTable, SubRegIndexLaneMaskTable,
2900
970
             LaneBitmask(0xFFFFFFF8), RegClassInfos, HwMode) {
2901
970
  InitMCRegisterInfo(SystemZRegDesc, 194, RA, PC,
2902
970
                     SystemZMCRegisterClasses, 21,
2903
970
                     SystemZRegUnitRoots,
2904
970
                     97,
2905
970
                     SystemZRegDiffLists,
2906
970
                     SystemZLaneMaskLists,
2907
970
                     SystemZRegStrings,
2908
970
                     SystemZRegClassStrings,
2909
970
                     SystemZSubRegIdxLists,
2910
970
                     7,
2911
970
                     SystemZSubRegIdxRanges,
2912
970
                     SystemZRegEncodingTable);
2913
970
2914
970
  switch (DwarfFlavour) {
2915
970
  default:
2916
0
    llvm_unreachable("Unknown DWARF flavour");
2917
970
  case 0:
2918
970
    mapDwarfRegsToLLVMRegs(SystemZDwarfFlavour0Dwarf2L, SystemZDwarfFlavour0Dwarf2LSize, false);
2919
970
    break;
2920
970
  }
2921
970
  switch (EHFlavour) {
2922
970
  default:
2923
0
    llvm_unreachable("Unknown DWARF flavour");
2924
970
  case 0:
2925
970
    mapDwarfRegsToLLVMRegs(SystemZEHFlavour0Dwarf2L, SystemZEHFlavour0Dwarf2LSize, true);
2926
970
    break;
2927
970
  }
2928
970
  switch (DwarfFlavour) {
2929
970
  default:
2930
0
    llvm_unreachable("Unknown DWARF flavour");
2931
970
  case 0:
2932
970
    mapLLVMRegsToDwarfRegs(SystemZDwarfFlavour0L2Dwarf, SystemZDwarfFlavour0L2DwarfSize, false);
2933
970
    break;
2934
970
  }
2935
970
  switch (EHFlavour) {
2936
970
  default:
2937
0
    llvm_unreachable("Unknown DWARF flavour");
2938
970
  case 0:
2939
970
    mapLLVMRegsToDwarfRegs(SystemZEHFlavour0L2Dwarf, SystemZEHFlavour0L2DwarfSize, true);
2940
970
    break;
2941
970
  }
2942
970
}
2943
2944
static const MCPhysReg CSR_SystemZ_SaveList[] = { SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 0 };
2945
static const uint32_t CSR_SystemZ_RegMask[] = { 0x00000000, 0x00000000, 0x0003fc00, 0x03fc03c0, 0x03ff0000, 0xe3ff03ff, 0x00000003, };
2946
static const MCPhysReg CSR_SystemZ_AllRegs_SaveList[] = { SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 0 };
2947
static const uint32_t CSR_SystemZ_AllRegs_RegMask[] = { 0x00000000, 0x00000000, 0x0003fffc, 0x03fffffc, 0xf3fff000, 0xfbfff3ff, 0x00000003, };
2948
static const MCPhysReg CSR_SystemZ_AllRegs_Vector_SaveList[] = { SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15, SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31, 0 };
2949
static const uint32_t CSR_SystemZ_AllRegs_Vector_RegMask[] = { 0x00000000, 0xfffffffc, 0xffffffff, 0xffffffff, 0xf3fff3ff, 0xfbfff3ff, 0x00000003, };
2950
static const MCPhysReg CSR_SystemZ_SwiftError_SaveList[] = { SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 0 };
2951
static const uint32_t CSR_SystemZ_SwiftError_RegMask[] = { 0x00000000, 0x00000000, 0x0003fc00, 0x03fc03c0, 0x03f70000, 0xa3f703f7, 0x00000003, };
2952
2953
2954
10
ArrayRef<const uint32_t *> SystemZGenRegisterInfo::getRegMasks() const {
2955
10
  static const uint32_t *const Masks[] = {
2956
10
    CSR_SystemZ_RegMask,
2957
10
    CSR_SystemZ_AllRegs_RegMask,
2958
10
    CSR_SystemZ_AllRegs_Vector_RegMask,
2959
10
    CSR_SystemZ_SwiftError_RegMask,
2960
10
  };
2961
10
  return makeArrayRef(Masks);
2962
10
}
2963
2964
10
ArrayRef<const char *> SystemZGenRegisterInfo::getRegMaskNames() const {
2965
10
  static const char *const Names[] = {
2966
10
    "CSR_SystemZ",
2967
10
    "CSR_SystemZ_AllRegs",
2968
10
    "CSR_SystemZ_AllRegs_Vector",
2969
10
    "CSR_SystemZ_SwiftError",
2970
10
  };
2971
10
  return makeArrayRef(Names);
2972
10
}
2973
2974
const SystemZFrameLowering *
2975
20.8k
SystemZGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
2976
20.8k
  return static_cast<const SystemZFrameLowering *>(
2977
20.8k
      MF.getSubtarget().getFrameLowering());
2978
20.8k
}
2979
2980
} // end namespace llvm
2981
2982
#endif // GET_REGINFO_TARGET_DESC
2983