Coverage Report

Created: 2018-07-20 23:04

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/SystemZ/SystemZGenRegisterInfo.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Register Enum Values                                                *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
#ifdef GET_REGINFO_ENUM
11
#undef GET_REGINFO_ENUM
12
13
namespace llvm {
14
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class MCRegisterClass;
16
extern const MCRegisterClass SystemZMCRegisterClasses[];
17
18
namespace SystemZ {
19
enum {
20
  NoRegister,
21
  CC = 1,
22
  A0 = 2,
23
  A1 = 3,
24
  A2 = 4,
25
  A3 = 5,
26
  A4 = 6,
27
  A5 = 7,
28
  A6 = 8,
29
  A7 = 9,
30
  A8 = 10,
31
  A9 = 11,
32
  A10 = 12,
33
  A11 = 13,
34
  A12 = 14,
35
  A13 = 15,
36
  A14 = 16,
37
  A15 = 17,
38
  C0 = 18,
39
  C1 = 19,
40
  C2 = 20,
41
  C3 = 21,
42
  C4 = 22,
43
  C5 = 23,
44
  C6 = 24,
45
  C7 = 25,
46
  C8 = 26,
47
  C9 = 27,
48
  C10 = 28,
49
  C11 = 29,
50
  C12 = 30,
51
  C13 = 31,
52
  C14 = 32,
53
  C15 = 33,
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  V0 = 34,
55
  V1 = 35,
56
  V2 = 36,
57
  V3 = 37,
58
  V4 = 38,
59
  V5 = 39,
60
  V6 = 40,
61
  V7 = 41,
62
  V8 = 42,
63
  V9 = 43,
64
  V10 = 44,
65
  V11 = 45,
66
  V12 = 46,
67
  V13 = 47,
68
  V14 = 48,
69
  V15 = 49,
70
  V16 = 50,
71
  V17 = 51,
72
  V18 = 52,
73
  V19 = 53,
74
  V20 = 54,
75
  V21 = 55,
76
  V22 = 56,
77
  V23 = 57,
78
  V24 = 58,
79
  V25 = 59,
80
  V26 = 60,
81
  V27 = 61,
82
  V28 = 62,
83
  V29 = 63,
84
  V30 = 64,
85
  V31 = 65,
86
  F0D = 66,
87
  F1D = 67,
88
  F2D = 68,
89
  F3D = 69,
90
  F4D = 70,
91
  F5D = 71,
92
  F6D = 72,
93
  F7D = 73,
94
  F8D = 74,
95
  F9D = 75,
96
  F10D = 76,
97
  F11D = 77,
98
  F12D = 78,
99
  F13D = 79,
100
  F14D = 80,
101
  F15D = 81,
102
  F16D = 82,
103
  F17D = 83,
104
  F18D = 84,
105
  F19D = 85,
106
  F20D = 86,
107
  F21D = 87,
108
  F22D = 88,
109
  F23D = 89,
110
  F24D = 90,
111
  F25D = 91,
112
  F26D = 92,
113
  F27D = 93,
114
  F28D = 94,
115
  F29D = 95,
116
  F30D = 96,
117
  F31D = 97,
118
  F0Q = 98,
119
  F1Q = 99,
120
  F4Q = 100,
121
  F5Q = 101,
122
  F8Q = 102,
123
  F9Q = 103,
124
  F12Q = 104,
125
  F13Q = 105,
126
  F0S = 106,
127
  F1S = 107,
128
  F2S = 108,
129
  F3S = 109,
130
  F4S = 110,
131
  F5S = 111,
132
  F6S = 112,
133
  F7S = 113,
134
  F8S = 114,
135
  F9S = 115,
136
  F10S = 116,
137
  F11S = 117,
138
  F12S = 118,
139
  F13S = 119,
140
  F14S = 120,
141
  F15S = 121,
142
  F16S = 122,
143
  F17S = 123,
144
  F18S = 124,
145
  F19S = 125,
146
  F20S = 126,
147
  F21S = 127,
148
  F22S = 128,
149
  F23S = 129,
150
  F24S = 130,
151
  F25S = 131,
152
  F26S = 132,
153
  F27S = 133,
154
  F28S = 134,
155
  F29S = 135,
156
  F30S = 136,
157
  F31S = 137,
158
  R0D = 138,
159
  R1D = 139,
160
  R2D = 140,
161
  R3D = 141,
162
  R4D = 142,
163
  R5D = 143,
164
  R6D = 144,
165
  R7D = 145,
166
  R8D = 146,
167
  R9D = 147,
168
  R10D = 148,
169
  R11D = 149,
170
  R12D = 150,
171
  R13D = 151,
172
  R14D = 152,
173
  R15D = 153,
174
  R0H = 154,
175
  R1H = 155,
176
  R2H = 156,
177
  R3H = 157,
178
  R4H = 158,
179
  R5H = 159,
180
  R6H = 160,
181
  R7H = 161,
182
  R8H = 162,
183
  R9H = 163,
184
  R10H = 164,
185
  R11H = 165,
186
  R12H = 166,
187
  R13H = 167,
188
  R14H = 168,
189
  R15H = 169,
190
  R0L = 170,
191
  R1L = 171,
192
  R2L = 172,
193
  R3L = 173,
194
  R4L = 174,
195
  R5L = 175,
196
  R6L = 176,
197
  R7L = 177,
198
  R8L = 178,
199
  R9L = 179,
200
  R10L = 180,
201
  R11L = 181,
202
  R12L = 182,
203
  R13L = 183,
204
  R14L = 184,
205
  R15L = 185,
206
  R0Q = 186,
207
  R2Q = 187,
208
  R4Q = 188,
209
  R6Q = 189,
210
  R8Q = 190,
211
  R10Q = 191,
212
  R12Q = 192,
213
  R14Q = 193,
214
  NUM_TARGET_REGS   // 194
215
};
216
} // end namespace SystemZ
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// Register classes
219
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namespace SystemZ {
221
enum {
222
  GRX32BitRegClassID = 0,
223
  VR32BitRegClassID = 1,
224
  AR32BitRegClassID = 2,
225
  FP32BitRegClassID = 3,
226
  GR32BitRegClassID = 4,
227
  GRH32BitRegClassID = 5,
228
  ADDR32BitRegClassID = 6,
229
  CCRRegClassID = 7,
230
  AnyRegBitRegClassID = 8,
231
  AnyRegBit_with_subreg_r32RegClassID = 9,
232
  VR64BitRegClassID = 10,
233
  AnyRegBit_with_subreg_r64RegClassID = 11,
234
  CR64BitRegClassID = 12,
235
  FP64BitRegClassID = 13,
236
  GR64BitRegClassID = 14,
237
  ADDR64BitRegClassID = 15,
238
  VR128BitRegClassID = 16,
239
  VF128BitRegClassID = 17,
240
  FP128BitRegClassID = 18,
241
  GR128BitRegClassID = 19,
242
  ADDR128BitRegClassID = 20,
243
244
  };
245
} // end namespace SystemZ
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// Subregister indices
249
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namespace SystemZ {
251
enum {
252
  NoSubRegister,
253
  subreg_h32, // 1
254
  subreg_h64, // 2
255
  subreg_hh32,  // 3
256
  subreg_hl32,  // 4
257
  subreg_hr32,  // 5
258
  subreg_l32, // 6
259
  subreg_l64, // 7
260
  subreg_r32, // 8
261
  subreg_r64, // 9
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  NUM_TARGET_SUBREGS
263
};
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} // end namespace SystemZ
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} // end namespace llvm
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#endif // GET_REGINFO_ENUM
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* MC Register Information                                                    *|
273
|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
276
\*===----------------------------------------------------------------------===*/
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#ifdef GET_REGINFO_MC_DESC
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#undef GET_REGINFO_MC_DESC
281
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namespace llvm {
283
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extern const MCPhysReg SystemZRegDiffLists[] = {
285
  /* 0 */ 64857, 1, 1, 1, 0,
286
  /* 5 */ 65325, 1, 0,
287
  /* 8 */ 65471, 2, 0,
288
  /* 11 */ 65473, 2, 0,
289
  /* 14 */ 65475, 2, 0,
290
  /* 17 */ 65477, 2, 0,
291
  /* 20 */ 32, 40, 0,
292
  /* 23 */ 65506, 40, 65494, 40, 0,
293
  /* 28 */ 65508, 40, 65494, 40, 0,
294
  /* 33 */ 65510, 40, 65494, 40, 0,
295
  /* 38 */ 65512, 40, 65494, 40, 0,
296
  /* 43 */ 65504, 40, 0,
297
  /* 46 */ 65520, 40, 0,
298
  /* 49 */ 65504, 41, 0,
299
  /* 52 */ 65520, 41, 0,
300
  /* 55 */ 65504, 42, 0,
301
  /* 58 */ 65520, 42, 0,
302
  /* 61 */ 65504, 43, 0,
303
  /* 64 */ 65520, 43, 0,
304
  /* 67 */ 65504, 44, 0,
305
  /* 70 */ 65520, 44, 0,
306
  /* 73 */ 65504, 45, 0,
307
  /* 76 */ 65520, 45, 0,
308
  /* 79 */ 65504, 46, 0,
309
  /* 82 */ 65520, 46, 0,
310
  /* 85 */ 65504, 47, 0,
311
  /* 88 */ 65520, 47, 0,
312
  /* 91 */ 65504, 48, 0,
313
  /* 94 */ 65520, 48, 0,
314
  /* 97 */ 65496, 65504, 56, 0,
315
  /* 101 */ 65496, 65504, 58, 0,
316
  /* 105 */ 65496, 65504, 60, 0,
317
  /* 109 */ 65496, 65504, 62, 0,
318
  /* 113 */ 65496, 65504, 64, 0,
319
  /* 117 */ 65261, 0,
320
  /* 119 */ 65294, 0,
321
  /* 121 */ 65463, 0,
322
  /* 123 */ 65503, 0,
323
  /* 125 */ 65496, 65504, 0,
324
  /* 128 */ 65489, 32, 65520, 65519, 32, 65520, 0,
325
  /* 135 */ 65490, 32, 65520, 65519, 32, 65520, 0,
326
  /* 142 */ 65491, 32, 65520, 65519, 32, 65520, 0,
327
  /* 149 */ 65492, 32, 65520, 65519, 32, 65520, 0,
328
  /* 156 */ 65493, 32, 65520, 65519, 32, 65520, 0,
329
  /* 163 */ 65494, 32, 65520, 65519, 32, 65520, 0,
330
  /* 170 */ 65495, 32, 65520, 65519, 32, 65520, 0,
331
  /* 177 */ 65496, 32, 65520, 65519, 32, 65520, 0,
332
  /* 184 */ 65535, 0,
333
};
334
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extern const LaneBitmask SystemZLaneMaskLists[] = {
336
  /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
337
  /* 2 */ LaneBitmask(0x00000004), LaneBitmask(0x00000002), LaneBitmask(0x00000010), LaneBitmask(0x00000001), LaneBitmask::getAll(),
338
  /* 7 */ LaneBitmask(0x00000008), LaneBitmask(0x00000020), LaneBitmask::getAll(),
339
};
340
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extern const uint16_t SystemZSubRegIdxLists[] = {
342
  /* 0 */ 6, 1, 0,
343
  /* 3 */ 7, 6, 1, 2, 4, 3, 0,
344
  /* 10 */ 7, 8, 2, 5, 0,
345
  /* 15 */ 9, 8, 0,
346
};
347
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extern const MCRegisterInfo::SubRegCoveredBits SystemZSubRegIdxRanges[] = {
349
  { 65535, 65535 },
350
  { 32, 32 }, // subreg_h32
351
  { 64, 64 }, // subreg_h64
352
  { 96, 32 }, // subreg_hh32
353
  { 64, 32 }, // subreg_hl32
354
  { 96, 32 }, // subreg_hr32
355
  { 0, 32 },  // subreg_l32
356
  { 0, 64 },  // subreg_l64
357
  { 32, 32 }, // subreg_r32
358
  { 64, 64 }, // subreg_r64
359
};
360
361
extern const char SystemZRegStrings[] = {
362
  /* 0 */ 'A', '1', '0', 0,
363
  /* 4 */ 'C', '1', '0', 0,
364
  /* 8 */ 'V', '1', '0', 0,
365
  /* 12 */ 'V', '2', '0', 0,
366
  /* 16 */ 'V', '3', '0', 0,
367
  /* 20 */ 'A', '0', 0,
368
  /* 23 */ 'C', '0', 0,
369
  /* 26 */ 'V', '0', 0,
370
  /* 29 */ 'A', '1', '1', 0,
371
  /* 33 */ 'C', '1', '1', 0,
372
  /* 37 */ 'V', '1', '1', 0,
373
  /* 41 */ 'V', '2', '1', 0,
374
  /* 45 */ 'V', '3', '1', 0,
375
  /* 49 */ 'A', '1', 0,
376
  /* 52 */ 'C', '1', 0,
377
  /* 55 */ 'V', '1', 0,
378
  /* 58 */ 'A', '1', '2', 0,
379
  /* 62 */ 'C', '1', '2', 0,
380
  /* 66 */ 'V', '1', '2', 0,
381
  /* 70 */ 'V', '2', '2', 0,
382
  /* 74 */ 'A', '2', 0,
383
  /* 77 */ 'C', '2', 0,
384
  /* 80 */ 'V', '2', 0,
385
  /* 83 */ 'A', '1', '3', 0,
386
  /* 87 */ 'C', '1', '3', 0,
387
  /* 91 */ 'V', '1', '3', 0,
388
  /* 95 */ 'V', '2', '3', 0,
389
  /* 99 */ 'A', '3', 0,
390
  /* 102 */ 'C', '3', 0,
391
  /* 105 */ 'V', '3', 0,
392
  /* 108 */ 'A', '1', '4', 0,
393
  /* 112 */ 'C', '1', '4', 0,
394
  /* 116 */ 'V', '1', '4', 0,
395
  /* 120 */ 'V', '2', '4', 0,
396
  /* 124 */ 'A', '4', 0,
397
  /* 127 */ 'C', '4', 0,
398
  /* 130 */ 'V', '4', 0,
399
  /* 133 */ 'A', '1', '5', 0,
400
  /* 137 */ 'C', '1', '5', 0,
401
  /* 141 */ 'V', '1', '5', 0,
402
  /* 145 */ 'V', '2', '5', 0,
403
  /* 149 */ 'A', '5', 0,
404
  /* 152 */ 'C', '5', 0,
405
  /* 155 */ 'V', '5', 0,
406
  /* 158 */ 'V', '1', '6', 0,
407
  /* 162 */ 'V', '2', '6', 0,
408
  /* 166 */ 'A', '6', 0,
409
  /* 169 */ 'C', '6', 0,
410
  /* 172 */ 'V', '6', 0,
411
  /* 175 */ 'V', '1', '7', 0,
412
  /* 179 */ 'V', '2', '7', 0,
413
  /* 183 */ 'A', '7', 0,
414
  /* 186 */ 'C', '7', 0,
415
  /* 189 */ 'V', '7', 0,
416
  /* 192 */ 'V', '1', '8', 0,
417
  /* 196 */ 'V', '2', '8', 0,
418
  /* 200 */ 'A', '8', 0,
419
  /* 203 */ 'C', '8', 0,
420
  /* 206 */ 'V', '8', 0,
421
  /* 209 */ 'V', '1', '9', 0,
422
  /* 213 */ 'V', '2', '9', 0,
423
  /* 217 */ 'A', '9', 0,
424
  /* 220 */ 'C', '9', 0,
425
  /* 223 */ 'V', '9', 0,
426
  /* 226 */ 'C', 'C', 0,
427
  /* 229 */ 'F', '1', '0', 'D', 0,
428
  /* 234 */ 'R', '1', '0', 'D', 0,
429
  /* 239 */ 'F', '2', '0', 'D', 0,
430
  /* 244 */ 'F', '3', '0', 'D', 0,
431
  /* 249 */ 'F', '0', 'D', 0,
432
  /* 253 */ 'R', '0', 'D', 0,
433
  /* 257 */ 'F', '1', '1', 'D', 0,
434
  /* 262 */ 'R', '1', '1', 'D', 0,
435
  /* 267 */ 'F', '2', '1', 'D', 0,
436
  /* 272 */ 'F', '3', '1', 'D', 0,
437
  /* 277 */ 'F', '1', 'D', 0,
438
  /* 281 */ 'R', '1', 'D', 0,
439
  /* 285 */ 'F', '1', '2', 'D', 0,
440
  /* 290 */ 'R', '1', '2', 'D', 0,
441
  /* 295 */ 'F', '2', '2', 'D', 0,
442
  /* 300 */ 'F', '2', 'D', 0,
443
  /* 304 */ 'R', '2', 'D', 0,
444
  /* 308 */ 'F', '1', '3', 'D', 0,
445
  /* 313 */ 'R', '1', '3', 'D', 0,
446
  /* 318 */ 'F', '2', '3', 'D', 0,
447
  /* 323 */ 'F', '3', 'D', 0,
448
  /* 327 */ 'R', '3', 'D', 0,
449
  /* 331 */ 'F', '1', '4', 'D', 0,
450
  /* 336 */ 'R', '1', '4', 'D', 0,
451
  /* 341 */ 'F', '2', '4', 'D', 0,
452
  /* 346 */ 'F', '4', 'D', 0,
453
  /* 350 */ 'R', '4', 'D', 0,
454
  /* 354 */ 'F', '1', '5', 'D', 0,
455
  /* 359 */ 'R', '1', '5', 'D', 0,
456
  /* 364 */ 'F', '2', '5', 'D', 0,
457
  /* 369 */ 'F', '5', 'D', 0,
458
  /* 373 */ 'R', '5', 'D', 0,
459
  /* 377 */ 'F', '1', '6', 'D', 0,
460
  /* 382 */ 'F', '2', '6', 'D', 0,
461
  /* 387 */ 'F', '6', 'D', 0,
462
  /* 391 */ 'R', '6', 'D', 0,
463
  /* 395 */ 'F', '1', '7', 'D', 0,
464
  /* 400 */ 'F', '2', '7', 'D', 0,
465
  /* 405 */ 'F', '7', 'D', 0,
466
  /* 409 */ 'R', '7', 'D', 0,
467
  /* 413 */ 'F', '1', '8', 'D', 0,
468
  /* 418 */ 'F', '2', '8', 'D', 0,
469
  /* 423 */ 'F', '8', 'D', 0,
470
  /* 427 */ 'R', '8', 'D', 0,
471
  /* 431 */ 'F', '1', '9', 'D', 0,
472
  /* 436 */ 'F', '2', '9', 'D', 0,
473
  /* 441 */ 'F', '9', 'D', 0,
474
  /* 445 */ 'R', '9', 'D', 0,
475
  /* 449 */ 'R', '1', '0', 'H', 0,
476
  /* 454 */ 'R', '0', 'H', 0,
477
  /* 458 */ 'R', '1', '1', 'H', 0,
478
  /* 463 */ 'R', '1', 'H', 0,
479
  /* 467 */ 'R', '1', '2', 'H', 0,
480
  /* 472 */ 'R', '2', 'H', 0,
481
  /* 476 */ 'R', '1', '3', 'H', 0,
482
  /* 481 */ 'R', '3', 'H', 0,
483
  /* 485 */ 'R', '1', '4', 'H', 0,
484
  /* 490 */ 'R', '4', 'H', 0,
485
  /* 494 */ 'R', '1', '5', 'H', 0,
486
  /* 499 */ 'R', '5', 'H', 0,
487
  /* 503 */ 'R', '6', 'H', 0,
488
  /* 507 */ 'R', '7', 'H', 0,
489
  /* 511 */ 'R', '8', 'H', 0,
490
  /* 515 */ 'R', '9', 'H', 0,
491
  /* 519 */ 'R', '1', '0', 'L', 0,
492
  /* 524 */ 'R', '0', 'L', 0,
493
  /* 528 */ 'R', '1', '1', 'L', 0,
494
  /* 533 */ 'R', '1', 'L', 0,
495
  /* 537 */ 'R', '1', '2', 'L', 0,
496
  /* 542 */ 'R', '2', 'L', 0,
497
  /* 546 */ 'R', '1', '3', 'L', 0,
498
  /* 551 */ 'R', '3', 'L', 0,
499
  /* 555 */ 'R', '1', '4', 'L', 0,
500
  /* 560 */ 'R', '4', 'L', 0,
501
  /* 564 */ 'R', '1', '5', 'L', 0,
502
  /* 569 */ 'R', '5', 'L', 0,
503
  /* 573 */ 'R', '6', 'L', 0,
504
  /* 577 */ 'R', '7', 'L', 0,
505
  /* 581 */ 'R', '8', 'L', 0,
506
  /* 585 */ 'R', '9', 'L', 0,
507
  /* 589 */ 'R', '1', '0', 'Q', 0,
508
  /* 594 */ 'F', '0', 'Q', 0,
509
  /* 598 */ 'R', '0', 'Q', 0,
510
  /* 602 */ 'F', '1', 'Q', 0,
511
  /* 606 */ 'F', '1', '2', 'Q', 0,
512
  /* 611 */ 'R', '1', '2', 'Q', 0,
513
  /* 616 */ 'R', '2', 'Q', 0,
514
  /* 620 */ 'F', '1', '3', 'Q', 0,
515
  /* 625 */ 'R', '1', '4', 'Q', 0,
516
  /* 630 */ 'F', '4', 'Q', 0,
517
  /* 634 */ 'R', '4', 'Q', 0,
518
  /* 638 */ 'F', '5', 'Q', 0,
519
  /* 642 */ 'R', '6', 'Q', 0,
520
  /* 646 */ 'F', '8', 'Q', 0,
521
  /* 650 */ 'R', '8', 'Q', 0,
522
  /* 654 */ 'F', '9', 'Q', 0,
523
  /* 658 */ 'F', '1', '0', 'S', 0,
524
  /* 663 */ 'F', '2', '0', 'S', 0,
525
  /* 668 */ 'F', '3', '0', 'S', 0,
526
  /* 673 */ 'F', '0', 'S', 0,
527
  /* 677 */ 'F', '1', '1', 'S', 0,
528
  /* 682 */ 'F', '2', '1', 'S', 0,
529
  /* 687 */ 'F', '3', '1', 'S', 0,
530
  /* 692 */ 'F', '1', 'S', 0,
531
  /* 696 */ 'F', '1', '2', 'S', 0,
532
  /* 701 */ 'F', '2', '2', 'S', 0,
533
  /* 706 */ 'F', '2', 'S', 0,
534
  /* 710 */ 'F', '1', '3', 'S', 0,
535
  /* 715 */ 'F', '2', '3', 'S', 0,
536
  /* 720 */ 'F', '3', 'S', 0,
537
  /* 724 */ 'F', '1', '4', 'S', 0,
538
  /* 729 */ 'F', '2', '4', 'S', 0,
539
  /* 734 */ 'F', '4', 'S', 0,
540
  /* 738 */ 'F', '1', '5', 'S', 0,
541
  /* 743 */ 'F', '2', '5', 'S', 0,
542
  /* 748 */ 'F', '5', 'S', 0,
543
  /* 752 */ 'F', '1', '6', 'S', 0,
544
  /* 757 */ 'F', '2', '6', 'S', 0,
545
  /* 762 */ 'F', '6', 'S', 0,
546
  /* 766 */ 'F', '1', '7', 'S', 0,
547
  /* 771 */ 'F', '2', '7', 'S', 0,
548
  /* 776 */ 'F', '7', 'S', 0,
549
  /* 780 */ 'F', '1', '8', 'S', 0,
550
  /* 785 */ 'F', '2', '8', 'S', 0,
551
  /* 790 */ 'F', '8', 'S', 0,
552
  /* 794 */ 'F', '1', '9', 'S', 0,
553
  /* 799 */ 'F', '2', '9', 'S', 0,
554
  /* 804 */ 'F', '9', 'S', 0,
555
};
556
557
extern const MCRegisterDesc SystemZRegDesc[] = { // Descriptors
558
  { 3, 0, 0, 0, 0, 0 },
559
  { 226, 4, 4, 2, 2945, 0 },
560
  { 20, 4, 4, 2, 2945, 0 },
561
  { 49, 4, 4, 2, 2945, 0 },
562
  { 74, 4, 4, 2, 2945, 0 },
563
  { 99, 4, 4, 2, 2945, 0 },
564
  { 124, 4, 4, 2, 2945, 0 },
565
  { 149, 4, 4, 2, 2945, 0 },
566
  { 166, 4, 4, 2, 2945, 0 },
567
  { 183, 4, 4, 2, 2945, 0 },
568
  { 200, 4, 4, 2, 2945, 0 },
569
  { 217, 4, 4, 2, 2945, 0 },
570
  { 0, 4, 4, 2, 2945, 0 },
571
  { 29, 4, 4, 2, 2945, 0 },
572
  { 58, 4, 4, 2, 2945, 0 },
573
  { 83, 4, 4, 2, 2945, 0 },
574
  { 108, 4, 4, 2, 2945, 0 },
575
  { 133, 4, 4, 2, 2945, 0 },
576
  { 23, 4, 4, 2, 2945, 0 },
577
  { 52, 4, 4, 2, 2945, 0 },
578
  { 77, 4, 4, 2, 2945, 0 },
579
  { 102, 4, 4, 2, 2945, 0 },
580
  { 127, 4, 4, 2, 2945, 0 },
581
  { 152, 4, 4, 2, 2945, 0 },
582
  { 169, 4, 4, 2, 2945, 0 },
583
  { 186, 4, 4, 2, 2945, 0 },
584
  { 203, 4, 4, 2, 2945, 0 },
585
  { 220, 4, 4, 2, 2945, 0 },
586
  { 4, 4, 4, 2, 2945, 0 },
587
  { 33, 4, 4, 2, 2945, 0 },
588
  { 62, 4, 4, 2, 2945, 0 },
589
  { 87, 4, 4, 2, 2945, 0 },
590
  { 112, 4, 4, 2, 2945, 0 },
591
  { 137, 4, 4, 2, 2945, 0 },
592
  { 26, 20, 4, 15, 2945, 8 },
593
  { 55, 20, 4, 15, 2945, 8 },
594
  { 80, 20, 4, 15, 2945, 8 },
595
  { 105, 20, 4, 15, 2945, 8 },
596
  { 130, 20, 4, 15, 2945, 8 },
597
  { 155, 20, 4, 15, 2945, 8 },
598
  { 172, 20, 4, 15, 2945, 8 },
599
  { 189, 20, 4, 15, 2945, 8 },
600
  { 206, 20, 4, 15, 2945, 8 },
601
  { 223, 20, 4, 15, 2945, 8 },
602
  { 8, 20, 4, 15, 2945, 8 },
603
  { 37, 20, 4, 15, 2945, 8 },
604
  { 66, 20, 4, 15, 2945, 8 },
605
  { 91, 20, 4, 15, 2945, 8 },
606
  { 116, 20, 4, 15, 2945, 8 },
607
  { 141, 20, 4, 15, 2945, 8 },
608
  { 158, 20, 4, 15, 2945, 8 },
609
  { 175, 20, 4, 15, 2945, 8 },
610
  { 192, 20, 4, 15, 2945, 8 },
611
  { 209, 20, 4, 15, 2945, 8 },
612
  { 12, 20, 4, 15, 2945, 8 },
613
  { 41, 20, 4, 15, 2945, 8 },
614
  { 70, 20, 4, 15, 2945, 8 },
615
  { 95, 20, 4, 15, 2945, 8 },
616
  { 120, 20, 4, 15, 2945, 8 },
617
  { 145, 20, 4, 15, 2945, 8 },
618
  { 162, 20, 4, 15, 2945, 8 },
619
  { 179, 20, 4, 15, 2945, 8 },
620
  { 196, 20, 4, 15, 2945, 8 },
621
  { 213, 20, 4, 15, 2945, 8 },
622
  { 16, 20, 4, 15, 2945, 8 },
623
  { 45, 20, 4, 15, 2945, 8 },
624
  { 249, 21, 114, 16, 1969, 8 },
625
  { 277, 21, 114, 16, 1969, 8 },
626
  { 300, 21, 110, 16, 1969, 8 },
627
  { 323, 21, 110, 16, 1969, 8 },
628
  { 346, 21, 110, 16, 1969, 8 },
629
  { 369, 21, 110, 16, 1969, 8 },
630
  { 387, 21, 106, 16, 1969, 8 },
631
  { 405, 21, 106, 16, 1969, 8 },
632
  { 423, 21, 106, 16, 1969, 8 },
633
  { 441, 21, 106, 16, 1969, 8 },
634
  { 229, 21, 102, 16, 1969, 8 },
635
  { 257, 21, 102, 16, 1969, 8 },
636
  { 285, 21, 102, 16, 1969, 8 },
637
  { 308, 21, 102, 16, 1969, 8 },
638
  { 331, 21, 98, 16, 1969, 8 },
639
  { 354, 21, 98, 16, 1969, 8 },
640
  { 377, 21, 126, 16, 1969, 8 },
641
  { 395, 21, 126, 16, 1969, 8 },
642
  { 413, 21, 126, 16, 1969, 8 },
643
  { 431, 21, 126, 16, 1969, 8 },
644
  { 239, 21, 126, 16, 1969, 8 },
645
  { 267, 21, 126, 16, 1969, 8 },
646
  { 295, 21, 126, 16, 1969, 8 },
647
  { 318, 21, 126, 16, 1969, 8 },
648
  { 341, 21, 126, 16, 1969, 8 },
649
  { 364, 21, 126, 16, 1969, 8 },
650
  { 382, 21, 126, 16, 1969, 8 },
651
  { 400, 21, 126, 16, 1969, 8 },
652
  { 418, 21, 126, 16, 1969, 8 },
653
  { 436, 21, 126, 16, 1969, 8 },
654
  { 244, 21, 126, 16, 1969, 8 },
655
  { 272, 21, 126, 16, 1969, 8 },
656
  { 594, 23, 4, 10, 129, 7 },
657
  { 602, 23, 4, 10, 129, 7 },
658
  { 630, 28, 4, 10, 177, 7 },
659
  { 638, 28, 4, 10, 177, 7 },
660
  { 646, 33, 4, 10, 225, 7 },
661
  { 654, 33, 4, 10, 225, 7 },
662
  { 606, 38, 4, 10, 273, 7 },
663
  { 620, 38, 4, 10, 273, 7 },
664
  { 673, 4, 113, 2, 1937, 0 },
665
  { 692, 4, 113, 2, 1937, 0 },
666
  { 706, 4, 109, 2, 1937, 0 },
667
  { 720, 4, 109, 2, 1937, 0 },
668
  { 734, 4, 109, 2, 1937, 0 },
669
  { 748, 4, 109, 2, 1937, 0 },
670
  { 762, 4, 105, 2, 1937, 0 },
671
  { 776, 4, 105, 2, 1937, 0 },
672
  { 790, 4, 105, 2, 1937, 0 },
673
  { 804, 4, 105, 2, 1937, 0 },
674
  { 658, 4, 101, 2, 1937, 0 },
675
  { 677, 4, 101, 2, 1937, 0 },
676
  { 696, 4, 101, 2, 1937, 0 },
677
  { 710, 4, 101, 2, 1937, 0 },
678
  { 724, 4, 97, 2, 1937, 0 },
679
  { 738, 4, 97, 2, 1937, 0 },
680
  { 752, 4, 125, 2, 1937, 0 },
681
  { 766, 4, 125, 2, 1937, 0 },
682
  { 780, 4, 125, 2, 1937, 0 },
683
  { 794, 4, 125, 2, 1937, 0 },
684
  { 663, 4, 125, 2, 1937, 0 },
685
  { 682, 4, 125, 2, 1937, 0 },
686
  { 701, 4, 125, 2, 1937, 0 },
687
  { 715, 4, 125, 2, 1937, 0 },
688
  { 729, 4, 125, 2, 1937, 0 },
689
  { 743, 4, 125, 2, 1937, 0 },
690
  { 757, 4, 125, 2, 1937, 0 },
691
  { 771, 4, 125, 2, 1937, 0 },
692
  { 785, 4, 125, 2, 1937, 0 },
693
  { 799, 4, 125, 2, 1937, 0 },
694
  { 668, 4, 125, 2, 1937, 0 },
695
  { 687, 4, 125, 2, 1937, 0 },
696
  { 253, 132, 92, 0, 82, 4 },
697
  { 281, 132, 86, 0, 82, 4 },
698
  { 304, 132, 86, 0, 82, 4 },
699
  { 327, 132, 80, 0, 82, 4 },
700
  { 350, 132, 80, 0, 82, 4 },
701
  { 373, 132, 74, 0, 82, 4 },
702
  { 391, 132, 74, 0, 82, 4 },
703
  { 409, 132, 68, 0, 82, 4 },
704
  { 427, 132, 68, 0, 82, 4 },
705
  { 445, 132, 62, 0, 82, 4 },
706
  { 234, 132, 62, 0, 82, 4 },
707
  { 262, 132, 56, 0, 82, 4 },
708
  { 290, 132, 56, 0, 82, 4 },
709
  { 313, 132, 50, 0, 82, 4 },
710
  { 336, 132, 50, 0, 82, 4 },
711
  { 359, 132, 21, 0, 82, 4 },
712
  { 454, 4, 94, 2, 1906, 0 },
713
  { 463, 4, 88, 2, 1906, 0 },
714
  { 472, 4, 88, 2, 1906, 0 },
715
  { 481, 4, 82, 2, 1906, 0 },
716
  { 490, 4, 82, 2, 1906, 0 },
717
  { 499, 4, 76, 2, 1906, 0 },
718
  { 503, 4, 76, 2, 1906, 0 },
719
  { 507, 4, 70, 2, 1906, 0 },
720
  { 511, 4, 70, 2, 1906, 0 },
721
  { 515, 4, 64, 2, 1906, 0 },
722
  { 449, 4, 64, 2, 1906, 0 },
723
  { 458, 4, 58, 2, 1906, 0 },
724
  { 467, 4, 58, 2, 1906, 0 },
725
  { 476, 4, 52, 2, 1906, 0 },
726
  { 485, 4, 52, 2, 1906, 0 },
727
  { 494, 4, 46, 2, 1906, 0 },
728
  { 524, 4, 91, 2, 1874, 0 },
729
  { 533, 4, 85, 2, 1874, 0 },
730
  { 542, 4, 85, 2, 1874, 0 },
731
  { 551, 4, 79, 2, 1874, 0 },
732
  { 560, 4, 79, 2, 1874, 0 },
733
  { 569, 4, 73, 2, 1874, 0 },
734
  { 573, 4, 73, 2, 1874, 0 },
735
  { 577, 4, 67, 2, 1874, 0 },
736
  { 581, 4, 67, 2, 1874, 0 },
737
  { 585, 4, 61, 2, 1874, 0 },
738
  { 519, 4, 61, 2, 1874, 0 },
739
  { 528, 4, 55, 2, 1874, 0 },
740
  { 537, 4, 55, 2, 1874, 0 },
741
  { 546, 4, 49, 2, 1874, 0 },
742
  { 555, 4, 49, 2, 1874, 0 },
743
  { 564, 4, 43, 2, 1874, 0 },
744
  { 598, 128, 4, 3, 4, 2 },
745
  { 616, 135, 4, 3, 4, 2 },
746
  { 634, 142, 4, 3, 4, 2 },
747
  { 642, 149, 4, 3, 4, 2 },
748
  { 650, 156, 4, 3, 4, 2 },
749
  { 589, 163, 4, 3, 4, 2 },
750
  { 611, 170, 4, 3, 4, 2 },
751
  { 625, 177, 4, 3, 4, 2 },
752
};
753
754
extern const MCPhysReg SystemZRegUnitRoots[][2] = {
755
  { SystemZ::CC },
756
  { SystemZ::A0 },
757
  { SystemZ::A1 },
758
  { SystemZ::A2 },
759
  { SystemZ::A3 },
760
  { SystemZ::A4 },
761
  { SystemZ::A5 },
762
  { SystemZ::A6 },
763
  { SystemZ::A7 },
764
  { SystemZ::A8 },
765
  { SystemZ::A9 },
766
  { SystemZ::A10 },
767
  { SystemZ::A11 },
768
  { SystemZ::A12 },
769
  { SystemZ::A13 },
770
  { SystemZ::A14 },
771
  { SystemZ::A15 },
772
  { SystemZ::C0 },
773
  { SystemZ::C1 },
774
  { SystemZ::C2 },
775
  { SystemZ::C3 },
776
  { SystemZ::C4 },
777
  { SystemZ::C5 },
778
  { SystemZ::C6 },
779
  { SystemZ::C7 },
780
  { SystemZ::C8 },
781
  { SystemZ::C9 },
782
  { SystemZ::C10 },
783
  { SystemZ::C11 },
784
  { SystemZ::C12 },
785
  { SystemZ::C13 },
786
  { SystemZ::C14 },
787
  { SystemZ::C15 },
788
  { SystemZ::F0S },
789
  { SystemZ::F1S },
790
  { SystemZ::F2S },
791
  { SystemZ::F3S },
792
  { SystemZ::F4S },
793
  { SystemZ::F5S },
794
  { SystemZ::F6S },
795
  { SystemZ::F7S },
796
  { SystemZ::F8S },
797
  { SystemZ::F9S },
798
  { SystemZ::F10S },
799
  { SystemZ::F11S },
800
  { SystemZ::F12S },
801
  { SystemZ::F13S },
802
  { SystemZ::F14S },
803
  { SystemZ::F15S },
804
  { SystemZ::F16S },
805
  { SystemZ::F17S },
806
  { SystemZ::F18S },
807
  { SystemZ::F19S },
808
  { SystemZ::F20S },
809
  { SystemZ::F21S },
810
  { SystemZ::F22S },
811
  { SystemZ::F23S },
812
  { SystemZ::F24S },
813
  { SystemZ::F25S },
814
  { SystemZ::F26S },
815
  { SystemZ::F27S },
816
  { SystemZ::F28S },
817
  { SystemZ::F29S },
818
  { SystemZ::F30S },
819
  { SystemZ::F31S },
820
  { SystemZ::R0L },
821
  { SystemZ::R0H },
822
  { SystemZ::R1L },
823
  { SystemZ::R1H },
824
  { SystemZ::R2L },
825
  { SystemZ::R2H },
826
  { SystemZ::R3L },
827
  { SystemZ::R3H },
828
  { SystemZ::R4L },
829
  { SystemZ::R4H },
830
  { SystemZ::R5L },
831
  { SystemZ::R5H },
832
  { SystemZ::R6L },
833
  { SystemZ::R6H },
834
  { SystemZ::R7L },
835
  { SystemZ::R7H },
836
  { SystemZ::R8L },
837
  { SystemZ::R8H },
838
  { SystemZ::R9L },
839
  { SystemZ::R9H },
840
  { SystemZ::R10L },
841
  { SystemZ::R10H },
842
  { SystemZ::R11L },
843
  { SystemZ::R11H },
844
  { SystemZ::R12L },
845
  { SystemZ::R12H },
846
  { SystemZ::R13L },
847
  { SystemZ::R13H },
848
  { SystemZ::R14L },
849
  { SystemZ::R14H },
850
  { SystemZ::R15L },
851
  { SystemZ::R15H },
852
};
853
854
namespace {     // Register classes...
855
  // GRX32Bit Register Class...
856
  const MCPhysReg GRX32Bit[] = {
857
    SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4H, SystemZ::R5H, SystemZ::R15L, SystemZ::R15H, SystemZ::R14L, SystemZ::R14H, SystemZ::R13L, SystemZ::R13H, SystemZ::R12L, SystemZ::R12H, SystemZ::R11L, SystemZ::R11H, SystemZ::R10L, SystemZ::R10H, SystemZ::R9L, SystemZ::R9H, SystemZ::R8L, SystemZ::R8H, SystemZ::R7L, SystemZ::R7H, SystemZ::R6L, SystemZ::R6H, 
858
  };
859
860
  // GRX32Bit Bit set.
861
  const uint8_t GRX32BitBits[] = {
862
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, 
863
  };
864
865
  // VR32Bit Register Class...
866
  const MCPhysReg VR32Bit[] = {
867
    SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S, SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S, SystemZ::F24S, SystemZ::F25S, SystemZ::F26S, SystemZ::F27S, SystemZ::F28S, SystemZ::F29S, SystemZ::F30S, SystemZ::F31S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S, 
868
  };
869
870
  // VR32Bit Bit set.
871
  const uint8_t VR32BitBits[] = {
872
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, 
873
  };
874
875
  // AR32Bit Register Class...
876
  const MCPhysReg AR32Bit[] = {
877
    SystemZ::A0, SystemZ::A1, SystemZ::A2, SystemZ::A3, SystemZ::A4, SystemZ::A5, SystemZ::A6, SystemZ::A7, SystemZ::A8, SystemZ::A9, SystemZ::A10, SystemZ::A11, SystemZ::A12, SystemZ::A13, SystemZ::A14, SystemZ::A15, 
878
  };
879
880
  // AR32Bit Bit set.
881
  const uint8_t AR32BitBits[] = {
882
    0xfc, 0xff, 0x03, 
883
  };
884
885
  // FP32Bit Register Class...
886
  const MCPhysReg FP32Bit[] = {
887
    SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S, 
888
  };
889
890
  // FP32Bit Bit set.
891
  const uint8_t FP32BitBits[] = {
892
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 
893
  };
894
895
  // GR32Bit Register Class...
896
  const MCPhysReg GR32Bit[] = {
897
    SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R15L, SystemZ::R14L, SystemZ::R13L, SystemZ::R12L, SystemZ::R11L, SystemZ::R10L, SystemZ::R9L, SystemZ::R8L, SystemZ::R7L, SystemZ::R6L, 
898
  };
899
900
  // GR32Bit Bit set.
901
  const uint8_t GR32BitBits[] = {
902
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 
903
  };
904
905
  // GRH32Bit Register Class...
906
  const MCPhysReg GRH32Bit[] = {
907
    SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4H, SystemZ::R5H, SystemZ::R15H, SystemZ::R14H, SystemZ::R13H, SystemZ::R12H, SystemZ::R11H, SystemZ::R10H, SystemZ::R9H, SystemZ::R8H, SystemZ::R7H, SystemZ::R6H, 
908
  };
909
910
  // GRH32Bit Bit set.
911
  const uint8_t GRH32BitBits[] = {
912
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 
913
  };
914
915
  // ADDR32Bit Register Class...
916
  const MCPhysReg ADDR32Bit[] = {
917
    SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R15L, SystemZ::R14L, SystemZ::R13L, SystemZ::R12L, SystemZ::R11L, SystemZ::R10L, SystemZ::R9L, SystemZ::R8L, SystemZ::R7L, SystemZ::R6L, 
918
  };
919
920
  // ADDR32Bit Bit set.
921
  const uint8_t ADDR32BitBits[] = {
922
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, 
923
  };
924
925
  // CCR Register Class...
926
  const MCPhysReg CCR[] = {
927
    SystemZ::CC, 
928
  };
929
930
  // CCR Bit set.
931
  const uint8_t CCRBits[] = {
932
    0x02, 
933
  };
934
935
  // AnyRegBit Register Class...
936
  const MCPhysReg AnyRegBit[] = {
937
    SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15, 
938
  };
939
940
  // AnyRegBit Bit set.
941
  const uint8_t AnyRegBitBits[] = {
942
    0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0xfc, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 
943
  };
944
945
  // AnyRegBit_with_subreg_r32 Register Class...
946
  const MCPhysReg AnyRegBit_with_subreg_r32[] = {
947
    SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15, 
948
  };
949
950
  // AnyRegBit_with_subreg_r32 Bit set.
951
  const uint8_t AnyRegBit_with_subreg_r32Bits[] = {
952
    0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0xfc, 0xff, 0x03, 
953
  };
954
955
  // VR64Bit Register Class...
956
  const MCPhysReg VR64Bit[] = {
957
    SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D, SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D, SystemZ::F24D, SystemZ::F25D, SystemZ::F26D, SystemZ::F27D, SystemZ::F28D, SystemZ::F29D, SystemZ::F30D, SystemZ::F31D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 
958
  };
959
960
  // VR64Bit Bit set.
961
  const uint8_t VR64BitBits[] = {
962
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, 
963
  };
964
965
  // AnyRegBit_with_subreg_r64 Register Class...
966
  const MCPhysReg AnyRegBit_with_subreg_r64[] = {
967
    SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15, 
968
  };
969
970
  // AnyRegBit_with_subreg_r64 Bit set.
971
  const uint8_t AnyRegBit_with_subreg_r64Bits[] = {
972
    0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 
973
  };
974
975
  // CR64Bit Register Class...
976
  const MCPhysReg CR64Bit[] = {
977
    SystemZ::C0, SystemZ::C1, SystemZ::C2, SystemZ::C3, SystemZ::C4, SystemZ::C5, SystemZ::C6, SystemZ::C7, SystemZ::C8, SystemZ::C9, SystemZ::C10, SystemZ::C11, SystemZ::C12, SystemZ::C13, SystemZ::C14, SystemZ::C15, 
978
  };
979
980
  // CR64Bit Bit set.
981
  const uint8_t CR64BitBits[] = {
982
    0x00, 0x00, 0xfc, 0xff, 0x03, 
983
  };
984
985
  // FP64Bit Register Class...
986
  const MCPhysReg FP64Bit[] = {
987
    SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 
988
  };
989
990
  // FP64Bit Bit set.
991
  const uint8_t FP64BitBits[] = {
992
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 
993
  };
994
995
  // GR64Bit Register Class...
996
  const MCPhysReg GR64Bit[] = {
997
    SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R15D, SystemZ::R14D, SystemZ::R13D, SystemZ::R12D, SystemZ::R11D, SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, SystemZ::R6D, 
998
  };
999
1000
  // GR64Bit Bit set.
1001
  const uint8_t GR64BitBits[] = {
1002
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 
1003
  };
1004
1005
  // ADDR64Bit Register Class...
1006
  const MCPhysReg ADDR64Bit[] = {
1007
    SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R15D, SystemZ::R14D, SystemZ::R13D, SystemZ::R12D, SystemZ::R11D, SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, SystemZ::R6D, 
1008
  };
1009
1010
  // ADDR64Bit Bit set.
1011
  const uint8_t ADDR64BitBits[] = {
1012
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, 
1013
  };
1014
1015
  // VR128Bit Register Class...
1016
  const MCPhysReg VR128Bit[] = {
1017
    SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15, 
1018
  };
1019
1020
  // VR128Bit Bit set.
1021
  const uint8_t VR128BitBits[] = {
1022
    0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, 
1023
  };
1024
1025
  // VF128Bit Register Class...
1026
  const MCPhysReg VF128Bit[] = {
1027
    SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15, 
1028
  };
1029
1030
  // VF128Bit Bit set.
1031
  const uint8_t VF128BitBits[] = {
1032
    0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 
1033
  };
1034
1035
  // FP128Bit Register Class...
1036
  const MCPhysReg FP128Bit[] = {
1037
    SystemZ::F0Q, SystemZ::F1Q, SystemZ::F4Q, SystemZ::F5Q, SystemZ::F8Q, SystemZ::F9Q, SystemZ::F12Q, SystemZ::F13Q, 
1038
  };
1039
1040
  // FP128Bit Bit set.
1041
  const uint8_t FP128BitBits[] = {
1042
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 
1043
  };
1044
1045
  // GR128Bit Register Class...
1046
  const MCPhysReg GR128Bit[] = {
1047
    SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, SystemZ::R12Q, SystemZ::R10Q, SystemZ::R8Q, SystemZ::R6Q, SystemZ::R14Q, 
1048
  };
1049
1050
  // GR128Bit Bit set.
1051
  const uint8_t GR128BitBits[] = {
1052
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 
1053
  };
1054
1055
  // ADDR128Bit Register Class...
1056
  const MCPhysReg ADDR128Bit[] = {
1057
    SystemZ::R2Q, SystemZ::R4Q, SystemZ::R12Q, SystemZ::R10Q, SystemZ::R8Q, SystemZ::R6Q, SystemZ::R14Q, 
1058
  };
1059
1060
  // ADDR128Bit Bit set.
1061
  const uint8_t ADDR128BitBits[] = {
1062
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 
1063
  };
1064
1065
} // end anonymous namespace
1066
1067
extern const char SystemZRegClassStrings[] = {
1068
  /* 0 */ 'A', 'n', 'y', 'R', 'e', 'g', 'B', 'i', 't', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'r', 'e', 'g', '_', 'r', '3', '2', 0,
1069
  /* 26 */ 'A', 'n', 'y', 'R', 'e', 'g', 'B', 'i', 't', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'r', 'e', 'g', '_', 'r', '6', '4', 0,
1070
  /* 52 */ 'C', 'C', 'R', 0,
1071
  /* 56 */ 'G', 'R', 'H', '3', '2', 'B', 'i', 't', 0,
1072
  /* 65 */ 'F', 'P', '3', '2', 'B', 'i', 't', 0,
1073
  /* 73 */ 'A', 'R', '3', '2', 'B', 'i', 't', 0,
1074
  /* 81 */ 'A', 'D', 'D', 'R', '3', '2', 'B', 'i', 't', 0,
1075
  /* 91 */ 'G', 'R', '3', '2', 'B', 'i', 't', 0,
1076
  /* 99 */ 'V', 'R', '3', '2', 'B', 'i', 't', 0,
1077
  /* 107 */ 'G', 'R', 'X', '3', '2', 'B', 'i', 't', 0,
1078
  /* 116 */ 'F', 'P', '6', '4', 'B', 'i', 't', 0,
1079
  /* 124 */ 'C', 'R', '6', '4', 'B', 'i', 't', 0,
1080
  /* 132 */ 'A', 'D', 'D', 'R', '6', '4', 'B', 'i', 't', 0,
1081
  /* 142 */ 'G', 'R', '6', '4', 'B', 'i', 't', 0,
1082
  /* 150 */ 'V', 'R', '6', '4', 'B', 'i', 't', 0,
1083
  /* 158 */ 'V', 'F', '1', '2', '8', 'B', 'i', 't', 0,
1084
  /* 167 */ 'F', 'P', '1', '2', '8', 'B', 'i', 't', 0,
1085
  /* 176 */ 'A', 'D', 'D', 'R', '1', '2', '8', 'B', 'i', 't', 0,
1086
  /* 187 */ 'G', 'R', '1', '2', '8', 'B', 'i', 't', 0,
1087
  /* 196 */ 'V', 'R', '1', '2', '8', 'B', 'i', 't', 0,
1088
  /* 205 */ 'A', 'n', 'y', 'R', 'e', 'g', 'B', 'i', 't', 0,
1089
};
1090
1091
extern const MCRegisterClass SystemZMCRegisterClasses[] = {
1092
  { GRX32Bit, GRX32BitBits, 107, 32, sizeof(GRX32BitBits), SystemZ::GRX32BitRegClassID, 4, 1, true },
1093
  { VR32Bit, VR32BitBits, 99, 32, sizeof(VR32BitBits), SystemZ::VR32BitRegClassID, 4, 1, true },
1094
  { AR32Bit, AR32BitBits, 73, 16, sizeof(AR32BitBits), SystemZ::AR32BitRegClassID, 4, 1, false },
1095
  { FP32Bit, FP32BitBits, 65, 16, sizeof(FP32BitBits), SystemZ::FP32BitRegClassID, 4, 1, true },
1096
  { GR32Bit, GR32BitBits, 91, 16, sizeof(GR32BitBits), SystemZ::GR32BitRegClassID, 4, 1, true },
1097
  { GRH32Bit, GRH32BitBits, 56, 16, sizeof(GRH32BitBits), SystemZ::GRH32BitRegClassID, 4, 1, true },
1098
  { ADDR32Bit, ADDR32BitBits, 81, 15, sizeof(ADDR32BitBits), SystemZ::ADDR32BitRegClassID, 4, 1, true },
1099
  { CCR, CCRBits, 52, 1, sizeof(CCRBits), SystemZ::CCRRegClassID, 4, -1, false },
1100
  { AnyRegBit, AnyRegBitBits, 205, 48, sizeof(AnyRegBitBits), SystemZ::AnyRegBitRegClassID, 8, 1, false },
1101
  { AnyRegBit_with_subreg_r32, AnyRegBit_with_subreg_r32Bits, 0, 32, sizeof(AnyRegBit_with_subreg_r32Bits), SystemZ::AnyRegBit_with_subreg_r32RegClassID, 8, 1, false },
1102
  { VR64Bit, VR64BitBits, 150, 32, sizeof(VR64BitBits), SystemZ::VR64BitRegClassID, 8, 1, true },
1103
  { AnyRegBit_with_subreg_r64, AnyRegBit_with_subreg_r64Bits, 26, 16, sizeof(AnyRegBit_with_subreg_r64Bits), SystemZ::AnyRegBit_with_subreg_r64RegClassID, 8, 1, false },
1104
  { CR64Bit, CR64BitBits, 124, 16, sizeof(CR64BitBits), SystemZ::CR64BitRegClassID, 8, 1, false },
1105
  { FP64Bit, FP64BitBits, 116, 16, sizeof(FP64BitBits), SystemZ::FP64BitRegClassID, 8, 1, true },
1106
  { GR64Bit, GR64BitBits, 142, 16, sizeof(GR64BitBits), SystemZ::GR64BitRegClassID, 8, 1, true },
1107
  { ADDR64Bit, ADDR64BitBits, 132, 15, sizeof(ADDR64BitBits), SystemZ::ADDR64BitRegClassID, 8, 1, true },
1108
  { VR128Bit, VR128BitBits, 196, 32, sizeof(VR128BitBits), SystemZ::VR128BitRegClassID, 16, 1, true },
1109
  { VF128Bit, VF128BitBits, 158, 16, sizeof(VF128BitBits), SystemZ::VF128BitRegClassID, 16, 1, true },
1110
  { FP128Bit, FP128BitBits, 167, 8, sizeof(FP128BitBits), SystemZ::FP128BitRegClassID, 16, 1, true },
1111
  { GR128Bit, GR128BitBits, 187, 8, sizeof(GR128BitBits), SystemZ::GR128BitRegClassID, 16, 1, true },
1112
  { ADDR128Bit, ADDR128BitBits, 176, 7, sizeof(ADDR128BitBits), SystemZ::ADDR128BitRegClassID, 16, 1, true },
1113
};
1114
1115
// SystemZ Dwarf<->LLVM register mappings.
1116
extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0Dwarf2L[] = {
1117
  { 0U, SystemZ::R0D },
1118
  { 1U, SystemZ::R1D },
1119
  { 2U, SystemZ::R2D },
1120
  { 3U, SystemZ::R3D },
1121
  { 4U, SystemZ::R4D },
1122
  { 5U, SystemZ::R5D },
1123
  { 6U, SystemZ::R6D },
1124
  { 7U, SystemZ::R7D },
1125
  { 8U, SystemZ::R8D },
1126
  { 9U, SystemZ::R9D },
1127
  { 10U, SystemZ::R10D },
1128
  { 11U, SystemZ::R11D },
1129
  { 12U, SystemZ::R12D },
1130
  { 13U, SystemZ::R13D },
1131
  { 14U, SystemZ::R14D },
1132
  { 15U, SystemZ::R15D },
1133
  { 16U, SystemZ::F0D },
1134
  { 17U, SystemZ::F2D },
1135
  { 18U, SystemZ::F4D },
1136
  { 19U, SystemZ::F6D },
1137
  { 20U, SystemZ::F1D },
1138
  { 21U, SystemZ::F3D },
1139
  { 22U, SystemZ::F5D },
1140
  { 23U, SystemZ::F7D },
1141
  { 24U, SystemZ::F8D },
1142
  { 25U, SystemZ::F10D },
1143
  { 26U, SystemZ::F12D },
1144
  { 27U, SystemZ::F14D },
1145
  { 28U, SystemZ::F9D },
1146
  { 29U, SystemZ::F11D },
1147
  { 30U, SystemZ::F13D },
1148
  { 31U, SystemZ::F15D },
1149
  { 32U, SystemZ::C0 },
1150
  { 33U, SystemZ::C1 },
1151
  { 34U, SystemZ::C2 },
1152
  { 35U, SystemZ::C3 },
1153
  { 36U, SystemZ::C4 },
1154
  { 37U, SystemZ::C5 },
1155
  { 38U, SystemZ::C6 },
1156
  { 39U, SystemZ::C7 },
1157
  { 40U, SystemZ::C8 },
1158
  { 41U, SystemZ::C9 },
1159
  { 42U, SystemZ::C10 },
1160
  { 43U, SystemZ::C11 },
1161
  { 44U, SystemZ::C12 },
1162
  { 45U, SystemZ::C13 },
1163
  { 46U, SystemZ::C14 },
1164
  { 47U, SystemZ::C15 },
1165
  { 48U, SystemZ::A0 },
1166
  { 49U, SystemZ::A1 },
1167
  { 50U, SystemZ::A2 },
1168
  { 51U, SystemZ::A3 },
1169
  { 52U, SystemZ::A4 },
1170
  { 53U, SystemZ::A5 },
1171
  { 54U, SystemZ::A6 },
1172
  { 55U, SystemZ::A7 },
1173
  { 56U, SystemZ::A8 },
1174
  { 57U, SystemZ::A9 },
1175
  { 58U, SystemZ::A10 },
1176
  { 59U, SystemZ::A11 },
1177
  { 60U, SystemZ::A12 },
1178
  { 61U, SystemZ::A13 },
1179
  { 62U, SystemZ::A14 },
1180
  { 63U, SystemZ::A15 },
1181
  { 68U, SystemZ::F16D },
1182
  { 69U, SystemZ::F18D },
1183
  { 70U, SystemZ::F20D },
1184
  { 71U, SystemZ::F22D },
1185
  { 72U, SystemZ::F17D },
1186
  { 73U, SystemZ::F19D },
1187
  { 74U, SystemZ::F21D },
1188
  { 75U, SystemZ::F23D },
1189
  { 76U, SystemZ::F24D },
1190
  { 77U, SystemZ::F26D },
1191
  { 78U, SystemZ::F28D },
1192
  { 79U, SystemZ::F30D },
1193
  { 80U, SystemZ::F25D },
1194
  { 81U, SystemZ::F27D },
1195
  { 82U, SystemZ::F29D },
1196
  { 83U, SystemZ::F31D },
1197
};
1198
extern const unsigned SystemZDwarfFlavour0Dwarf2LSize = array_lengthof(SystemZDwarfFlavour0Dwarf2L);
1199
1200
extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0Dwarf2L[] = {
1201
  { 0U, SystemZ::R0D },
1202
  { 1U, SystemZ::R1D },
1203
  { 2U, SystemZ::R2D },
1204
  { 3U, SystemZ::R3D },
1205
  { 4U, SystemZ::R4D },
1206
  { 5U, SystemZ::R5D },
1207
  { 6U, SystemZ::R6D },
1208
  { 7U, SystemZ::R7D },
1209
  { 8U, SystemZ::R8D },
1210
  { 9U, SystemZ::R9D },
1211
  { 10U, SystemZ::R10D },
1212
  { 11U, SystemZ::R11D },
1213
  { 12U, SystemZ::R12D },
1214
  { 13U, SystemZ::R13D },
1215
  { 14U, SystemZ::R14D },
1216
  { 15U, SystemZ::R15D },
1217
  { 16U, SystemZ::F0D },
1218
  { 17U, SystemZ::F2D },
1219
  { 18U, SystemZ::F4D },
1220
  { 19U, SystemZ::F6D },
1221
  { 20U, SystemZ::F1D },
1222
  { 21U, SystemZ::F3D },
1223
  { 22U, SystemZ::F5D },
1224
  { 23U, SystemZ::F7D },
1225
  { 24U, SystemZ::F8D },
1226
  { 25U, SystemZ::F10D },
1227
  { 26U, SystemZ::F12D },
1228
  { 27U, SystemZ::F14D },
1229
  { 28U, SystemZ::F9D },
1230
  { 29U, SystemZ::F11D },
1231
  { 30U, SystemZ::F13D },
1232
  { 31U, SystemZ::F15D },
1233
  { 32U, SystemZ::C0 },
1234
  { 33U, SystemZ::C1 },
1235
  { 34U, SystemZ::C2 },
1236
  { 35U, SystemZ::C3 },
1237
  { 36U, SystemZ::C4 },
1238
  { 37U, SystemZ::C5 },
1239
  { 38U, SystemZ::C6 },
1240
  { 39U, SystemZ::C7 },
1241
  { 40U, SystemZ::C8 },
1242
  { 41U, SystemZ::C9 },
1243
  { 42U, SystemZ::C10 },
1244
  { 43U, SystemZ::C11 },
1245
  { 44U, SystemZ::C12 },
1246
  { 45U, SystemZ::C13 },
1247
  { 46U, SystemZ::C14 },
1248
  { 47U, SystemZ::C15 },
1249
  { 48U, SystemZ::A0 },
1250
  { 49U, SystemZ::A1 },
1251
  { 50U, SystemZ::A2 },
1252
  { 51U, SystemZ::A3 },
1253
  { 52U, SystemZ::A4 },
1254
  { 53U, SystemZ::A5 },
1255
  { 54U, SystemZ::A6 },
1256
  { 55U, SystemZ::A7 },
1257
  { 56U, SystemZ::A8 },
1258
  { 57U, SystemZ::A9 },
1259
  { 58U, SystemZ::A10 },
1260
  { 59U, SystemZ::A11 },
1261
  { 60U, SystemZ::A12 },
1262
  { 61U, SystemZ::A13 },
1263
  { 62U, SystemZ::A14 },
1264
  { 63U, SystemZ::A15 },
1265
  { 68U, SystemZ::F16D },
1266
  { 69U, SystemZ::F18D },
1267
  { 70U, SystemZ::F20D },
1268
  { 71U, SystemZ::F22D },
1269
  { 72U, SystemZ::F17D },
1270
  { 73U, SystemZ::F19D },
1271
  { 74U, SystemZ::F21D },
1272
  { 75U, SystemZ::F23D },
1273
  { 76U, SystemZ::F24D },
1274
  { 77U, SystemZ::F26D },
1275
  { 78U, SystemZ::F28D },
1276
  { 79U, SystemZ::F30D },
1277
  { 80U, SystemZ::F25D },
1278
  { 81U, SystemZ::F27D },
1279
  { 82U, SystemZ::F29D },
1280
  { 83U, SystemZ::F31D },
1281
};
1282
extern const unsigned SystemZEHFlavour0Dwarf2LSize = array_lengthof(SystemZEHFlavour0Dwarf2L);
1283
1284
extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0L2Dwarf[] = {
1285
  { SystemZ::A0, 48U },
1286
  { SystemZ::A1, 49U },
1287
  { SystemZ::A2, 50U },
1288
  { SystemZ::A3, 51U },
1289
  { SystemZ::A4, 52U },
1290
  { SystemZ::A5, 53U },
1291
  { SystemZ::A6, 54U },
1292
  { SystemZ::A7, 55U },
1293
  { SystemZ::A8, 56U },
1294
  { SystemZ::A9, 57U },
1295
  { SystemZ::A10, 58U },
1296
  { SystemZ::A11, 59U },
1297
  { SystemZ::A12, 60U },
1298
  { SystemZ::A13, 61U },
1299
  { SystemZ::A14, 62U },
1300
  { SystemZ::A15, 63U },
1301
  { SystemZ::C0, 32U },
1302
  { SystemZ::C1, 33U },
1303
  { SystemZ::C2, 34U },
1304
  { SystemZ::C3, 35U },
1305
  { SystemZ::C4, 36U },
1306
  { SystemZ::C5, 37U },
1307
  { SystemZ::C6, 38U },
1308
  { SystemZ::C7, 39U },
1309
  { SystemZ::C8, 40U },
1310
  { SystemZ::C9, 41U },
1311
  { SystemZ::C10, 42U },
1312
  { SystemZ::C11, 43U },
1313
  { SystemZ::C12, 44U },
1314
  { SystemZ::C13, 45U },
1315
  { SystemZ::C14, 46U },
1316
  { SystemZ::C15, 47U },
1317
  { SystemZ::V0, 16U },
1318
  { SystemZ::V1, 20U },
1319
  { SystemZ::V2, 17U },
1320
  { SystemZ::V3, 21U },
1321
  { SystemZ::V4, 18U },
1322
  { SystemZ::V5, 22U },
1323
  { SystemZ::V6, 19U },
1324
  { SystemZ::V7, 23U },
1325
  { SystemZ::V8, 24U },
1326
  { SystemZ::V9, 28U },
1327
  { SystemZ::V10, 25U },
1328
  { SystemZ::V11, 29U },
1329
  { SystemZ::V12, 26U },
1330
  { SystemZ::V13, 30U },
1331
  { SystemZ::V14, 27U },
1332
  { SystemZ::V15, 31U },
1333
  { SystemZ::V16, 68U },
1334
  { SystemZ::V17, 72U },
1335
  { SystemZ::V18, 69U },
1336
  { SystemZ::V19, 73U },
1337
  { SystemZ::V20, 70U },
1338
  { SystemZ::V21, 74U },
1339
  { SystemZ::V22, 71U },
1340
  { SystemZ::V23, 75U },
1341
  { SystemZ::V24, 76U },
1342
  { SystemZ::V25, 80U },
1343
  { SystemZ::V26, 77U },
1344
  { SystemZ::V27, 81U },
1345
  { SystemZ::V28, 78U },
1346
  { SystemZ::V29, 82U },
1347
  { SystemZ::V30, 79U },
1348
  { SystemZ::V31, 83U },
1349
  { SystemZ::F0D, 16U },
1350
  { SystemZ::F1D, 20U },
1351
  { SystemZ::F2D, 17U },
1352
  { SystemZ::F3D, 21U },
1353
  { SystemZ::F4D, 18U },
1354
  { SystemZ::F5D, 22U },
1355
  { SystemZ::F6D, 19U },
1356
  { SystemZ::F7D, 23U },
1357
  { SystemZ::F8D, 24U },
1358
  { SystemZ::F9D, 28U },
1359
  { SystemZ::F10D, 25U },
1360
  { SystemZ::F11D, 29U },
1361
  { SystemZ::F12D, 26U },
1362
  { SystemZ::F13D, 30U },
1363
  { SystemZ::F14D, 27U },
1364
  { SystemZ::F15D, 31U },
1365
  { SystemZ::F16D, 68U },
1366
  { SystemZ::F17D, 72U },
1367
  { SystemZ::F18D, 69U },
1368
  { SystemZ::F19D, 73U },
1369
  { SystemZ::F20D, 70U },
1370
  { SystemZ::F21D, 74U },
1371
  { SystemZ::F22D, 71U },
1372
  { SystemZ::F23D, 75U },
1373
  { SystemZ::F24D, 76U },
1374
  { SystemZ::F25D, 80U },
1375
  { SystemZ::F26D, 77U },
1376
  { SystemZ::F27D, 81U },
1377
  { SystemZ::F28D, 78U },
1378
  { SystemZ::F29D, 82U },
1379
  { SystemZ::F30D, 79U },
1380
  { SystemZ::F31D, 83U },
1381
  { SystemZ::R0D, 0U },
1382
  { SystemZ::R1D, 1U },
1383
  { SystemZ::R2D, 2U },
1384
  { SystemZ::R3D, 3U },
1385
  { SystemZ::R4D, 4U },
1386
  { SystemZ::R5D, 5U },
1387
  { SystemZ::R6D, 6U },
1388
  { SystemZ::R7D, 7U },
1389
  { SystemZ::R8D, 8U },
1390
  { SystemZ::R9D, 9U },
1391
  { SystemZ::R10D, 10U },
1392
  { SystemZ::R11D, 11U },
1393
  { SystemZ::R12D, 12U },
1394
  { SystemZ::R13D, 13U },
1395
  { SystemZ::R14D, 14U },
1396
  { SystemZ::R15D, 15U },
1397
};
1398
extern const unsigned SystemZDwarfFlavour0L2DwarfSize = array_lengthof(SystemZDwarfFlavour0L2Dwarf);
1399
1400
extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0L2Dwarf[] = {
1401
  { SystemZ::A0, 48U },
1402
  { SystemZ::A1, 49U },
1403
  { SystemZ::A2, 50U },
1404
  { SystemZ::A3, 51U },
1405
  { SystemZ::A4, 52U },
1406
  { SystemZ::A5, 53U },
1407
  { SystemZ::A6, 54U },
1408
  { SystemZ::A7, 55U },
1409
  { SystemZ::A8, 56U },
1410
  { SystemZ::A9, 57U },
1411
  { SystemZ::A10, 58U },
1412
  { SystemZ::A11, 59U },
1413
  { SystemZ::A12, 60U },
1414
  { SystemZ::A13, 61U },
1415
  { SystemZ::A14, 62U },
1416
  { SystemZ::A15, 63U },
1417
  { SystemZ::C0, 32U },
1418
  { SystemZ::C1, 33U },
1419
  { SystemZ::C2, 34U },
1420
  { SystemZ::C3, 35U },
1421
  { SystemZ::C4, 36U },
1422
  { SystemZ::C5, 37U },
1423
  { SystemZ::C6, 38U },
1424
  { SystemZ::C7, 39U },
1425
  { SystemZ::C8, 40U },
1426
  { SystemZ::C9, 41U },
1427
  { SystemZ::C10, 42U },
1428
  { SystemZ::C11, 43U },
1429
  { SystemZ::C12, 44U },
1430
  { SystemZ::C13, 45U },
1431
  { SystemZ::C14, 46U },
1432
  { SystemZ::C15, 47U },
1433
  { SystemZ::V0, 16U },
1434
  { SystemZ::V1, 20U },
1435
  { SystemZ::V2, 17U },
1436
  { SystemZ::V3, 21U },
1437
  { SystemZ::V4, 18U },
1438
  { SystemZ::V5, 22U },
1439
  { SystemZ::V6, 19U },
1440
  { SystemZ::V7, 23U },
1441
  { SystemZ::V8, 24U },
1442
  { SystemZ::V9, 28U },
1443
  { SystemZ::V10, 25U },
1444
  { SystemZ::V11, 29U },
1445
  { SystemZ::V12, 26U },
1446
  { SystemZ::V13, 30U },
1447
  { SystemZ::V14, 27U },
1448
  { SystemZ::V15, 31U },
1449
  { SystemZ::V16, 68U },
1450
  { SystemZ::V17, 72U },
1451
  { SystemZ::V18, 69U },
1452
  { SystemZ::V19, 73U },
1453
  { SystemZ::V20, 70U },
1454
  { SystemZ::V21, 74U },
1455
  { SystemZ::V22, 71U },
1456
  { SystemZ::V23, 75U },
1457
  { SystemZ::V24, 76U },
1458
  { SystemZ::V25, 80U },
1459
  { SystemZ::V26, 77U },
1460
  { SystemZ::V27, 81U },
1461
  { SystemZ::V28, 78U },
1462
  { SystemZ::V29, 82U },
1463
  { SystemZ::V30, 79U },
1464
  { SystemZ::V31, 83U },
1465
  { SystemZ::F0D, 16U },
1466
  { SystemZ::F1D, 20U },
1467
  { SystemZ::F2D, 17U },
1468
  { SystemZ::F3D, 21U },
1469
  { SystemZ::F4D, 18U },
1470
  { SystemZ::F5D, 22U },
1471
  { SystemZ::F6D, 19U },
1472
  { SystemZ::F7D, 23U },
1473
  { SystemZ::F8D, 24U },
1474
  { SystemZ::F9D, 28U },
1475
  { SystemZ::F10D, 25U },
1476
  { SystemZ::F11D, 29U },
1477
  { SystemZ::F12D, 26U },
1478
  { SystemZ::F13D, 30U },
1479
  { SystemZ::F14D, 27U },
1480
  { SystemZ::F15D, 31U },
1481
  { SystemZ::F16D, 68U },
1482
  { SystemZ::F17D, 72U },
1483
  { SystemZ::F18D, 69U },
1484
  { SystemZ::F19D, 73U },
1485
  { SystemZ::F20D, 70U },
1486
  { SystemZ::F21D, 74U },
1487
  { SystemZ::F22D, 71U },
1488
  { SystemZ::F23D, 75U },
1489
  { SystemZ::F24D, 76U },
1490
  { SystemZ::F25D, 80U },
1491
  { SystemZ::F26D, 77U },
1492
  { SystemZ::F27D, 81U },
1493
  { SystemZ::F28D, 78U },
1494
  { SystemZ::F29D, 82U },
1495
  { SystemZ::F30D, 79U },
1496
  { SystemZ::F31D, 83U },
1497
  { SystemZ::R0D, 0U },
1498
  { SystemZ::R1D, 1U },
1499
  { SystemZ::R2D, 2U },
1500
  { SystemZ::R3D, 3U },
1501
  { SystemZ::R4D, 4U },
1502
  { SystemZ::R5D, 5U },
1503
  { SystemZ::R6D, 6U },
1504
  { SystemZ::R7D, 7U },
1505
  { SystemZ::R8D, 8U },
1506
  { SystemZ::R9D, 9U },
1507
  { SystemZ::R10D, 10U },
1508
  { SystemZ::R11D, 11U },
1509
  { SystemZ::R12D, 12U },
1510
  { SystemZ::R13D, 13U },
1511
  { SystemZ::R14D, 14U },
1512
  { SystemZ::R15D, 15U },
1513
};
1514
extern const unsigned SystemZEHFlavour0L2DwarfSize = array_lengthof(SystemZEHFlavour0L2Dwarf);
1515
1516
extern const uint16_t SystemZRegEncodingTable[] = {
1517
  0,
1518
  0,
1519
  0,
1520
  1,
1521
  2,
1522
  3,
1523
  4,
1524
  5,
1525
  6,
1526
  7,
1527
  8,
1528
  9,
1529
  10,
1530
  11,
1531
  12,
1532
  13,
1533
  14,
1534
  15,
1535
  0,
1536
  1,
1537
  2,
1538
  3,
1539
  4,
1540
  5,
1541
  6,
1542
  7,
1543
  8,
1544
  9,
1545
  10,
1546
  11,
1547
  12,
1548
  13,
1549
  14,
1550
  15,
1551
  0,
1552
  1,
1553
  2,
1554
  3,
1555
  4,
1556
  5,
1557
  6,
1558
  7,
1559
  8,
1560
  9,
1561
  10,
1562
  11,
1563
  12,
1564
  13,
1565
  14,
1566
  15,
1567
  16,
1568
  17,
1569
  18,
1570
  19,
1571
  20,
1572
  21,
1573
  22,
1574
  23,
1575
  24,
1576
  25,
1577
  26,
1578
  27,
1579
  28,
1580
  29,
1581
  30,
1582
  31,
1583
  0,
1584
  1,
1585
  2,
1586
  3,
1587
  4,
1588
  5,
1589
  6,
1590
  7,
1591
  8,
1592
  9,
1593
  10,
1594
  11,
1595
  12,
1596
  13,
1597
  14,
1598
  15,
1599
  16,
1600
  17,
1601
  18,
1602
  19,
1603
  20,
1604
  21,
1605
  22,
1606
  23,
1607
  24,
1608
  25,
1609
  26,
1610
  27,
1611
  28,
1612
  29,
1613
  30,
1614
  31,
1615
  0,
1616
  1,
1617
  4,
1618
  5,
1619
  8,
1620
  9,
1621
  12,
1622
  13,
1623
  0,
1624
  1,
1625
  2,
1626
  3,
1627
  4,
1628
  5,
1629
  6,
1630
  7,
1631
  8,
1632
  9,
1633
  10,
1634
  11,
1635
  12,
1636
  13,
1637
  14,
1638
  15,
1639
  16,
1640
  17,
1641
  18,
1642
  19,
1643
  20,
1644
  21,
1645
  22,
1646
  23,
1647
  24,
1648
  25,
1649
  26,
1650
  27,
1651
  28,
1652
  29,
1653
  30,
1654
  31,
1655
  0,
1656
  1,
1657
  2,
1658
  3,
1659
  4,
1660
  5,
1661
  6,
1662
  7,
1663
  8,
1664
  9,
1665
  10,
1666
  11,
1667
  12,
1668
  13,
1669
  14,
1670
  15,
1671
  0,
1672
  1,
1673
  2,
1674
  3,
1675
  4,
1676
  5,
1677
  6,
1678
  7,
1679
  8,
1680
  9,
1681
  10,
1682
  11,
1683
  12,
1684
  13,
1685
  14,
1686
  15,
1687
  0,
1688
  1,
1689
  2,
1690
  3,
1691
  4,
1692
  5,
1693
  6,
1694
  7,
1695
  8,
1696
  9,
1697
  10,
1698
  11,
1699
  12,
1700
  13,
1701
  14,
1702
  15,
1703
  0,
1704
  2,
1705
  4,
1706
  6,
1707
  8,
1708
  10,
1709
  12,
1710
  14,
1711
};
1712
1.00k
static inline void InitSystemZMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
1713
1.00k
  RI->InitMCRegisterInfo(SystemZRegDesc, 194, RA, PC, SystemZMCRegisterClasses, 21, SystemZRegUnitRoots, 97, SystemZRegDiffLists, SystemZLaneMaskLists, SystemZRegStrings, SystemZRegClassStrings, SystemZSubRegIdxLists, 10,
1714
1.00k
SystemZSubRegIdxRanges, SystemZRegEncodingTable);
1715
1.00k
1716
1.00k
  switch (DwarfFlavour) {
1717
1.00k
  default:
1718
0
    llvm_unreachable("Unknown DWARF flavour");
1719
1.00k
  case 0:
1720
1.00k
    RI->mapDwarfRegsToLLVMRegs(SystemZDwarfFlavour0Dwarf2L, SystemZDwarfFlavour0Dwarf2LSize, false);
1721
1.00k
    break;
1722
1.00k
  }
1723
1.00k
  switch (EHFlavour) {
1724
1.00k
  default:
1725
0
    llvm_unreachable("Unknown DWARF flavour");
1726
1.00k
  case 0:
1727
1.00k
    RI->mapDwarfRegsToLLVMRegs(SystemZEHFlavour0Dwarf2L, SystemZEHFlavour0Dwarf2LSize, true);
1728
1.00k
    break;
1729
1.00k
  }
1730
1.00k
  switch (DwarfFlavour) {
1731
1.00k
  default:
1732
0
    llvm_unreachable("Unknown DWARF flavour");
1733
1.00k
  case 0:
1734
1.00k
    RI->mapLLVMRegsToDwarfRegs(SystemZDwarfFlavour0L2Dwarf, SystemZDwarfFlavour0L2DwarfSize, false);
1735
1.00k
    break;
1736
1.00k
  }
1737
1.00k
  switch (EHFlavour) {
1738
1.00k
  default:
1739
0
    llvm_unreachable("Unknown DWARF flavour");
1740
1.00k
  case 0:
1741
1.00k
    RI->mapLLVMRegsToDwarfRegs(SystemZEHFlavour0L2Dwarf, SystemZEHFlavour0L2DwarfSize, true);
1742
1.00k
    break;
1743
1.00k
  }
1744
1.00k
}
1745
1746
} // end namespace llvm
1747
1748
#endif // GET_REGINFO_MC_DESC
1749
1750
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
1751
|*                                                                            *|
1752
|* Register Information Header Fragment                                       *|
1753
|*                                                                            *|
1754
|* Automatically generated file, do not edit!                                 *|
1755
|*                                                                            *|
1756
\*===----------------------------------------------------------------------===*/
1757
1758
1759
#ifdef GET_REGINFO_HEADER
1760
#undef GET_REGINFO_HEADER
1761
1762
#include "llvm/CodeGen/TargetRegisterInfo.h"
1763
1764
namespace llvm {
1765
1766
class SystemZFrameLowering;
1767
1768
struct SystemZGenRegisterInfo : public TargetRegisterInfo {
1769
  explicit SystemZGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
1770
      unsigned PC = 0, unsigned HwMode = 0);
1771
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
1772
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
1773
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
1774
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
1775
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
1776
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
1777
  unsigned getNumRegPressureSets() const override;
1778
  const char *getRegPressureSetName(unsigned Idx) const override;
1779
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
1780
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
1781
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
1782
  ArrayRef<const char *> getRegMaskNames() const override;
1783
  ArrayRef<const uint32_t *> getRegMasks() const override;
1784
  /// Devirtualized TargetFrameLowering.
1785
  static const SystemZFrameLowering *getFrameLowering(
1786
      const MachineFunction &MF);
1787
};
1788
1789
namespace SystemZ { // Register classes
1790
  extern const TargetRegisterClass GRX32BitRegClass;
1791
  extern const TargetRegisterClass VR32BitRegClass;
1792
  extern const TargetRegisterClass AR32BitRegClass;
1793
  extern const TargetRegisterClass FP32BitRegClass;
1794
  extern const TargetRegisterClass GR32BitRegClass;
1795
  extern const TargetRegisterClass GRH32BitRegClass;
1796
  extern const TargetRegisterClass ADDR32BitRegClass;
1797
  extern const TargetRegisterClass CCRRegClass;
1798
  extern const TargetRegisterClass AnyRegBitRegClass;
1799
  extern const TargetRegisterClass AnyRegBit_with_subreg_r32RegClass;
1800
  extern const TargetRegisterClass VR64BitRegClass;
1801
  extern const TargetRegisterClass AnyRegBit_with_subreg_r64RegClass;
1802
  extern const TargetRegisterClass CR64BitRegClass;
1803
  extern const TargetRegisterClass FP64BitRegClass;
1804
  extern const TargetRegisterClass GR64BitRegClass;
1805
  extern const TargetRegisterClass ADDR64BitRegClass;
1806
  extern const TargetRegisterClass VR128BitRegClass;
1807
  extern const TargetRegisterClass VF128BitRegClass;
1808
  extern const TargetRegisterClass FP128BitRegClass;
1809
  extern const TargetRegisterClass GR128BitRegClass;
1810
  extern const TargetRegisterClass ADDR128BitRegClass;
1811
} // end namespace SystemZ
1812
1813
} // end namespace llvm
1814
1815
#endif // GET_REGINFO_HEADER
1816
1817
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
1818
|*                                                                            *|
1819
|* Target Register and Register Classes Information                           *|
1820
|*                                                                            *|
1821
|* Automatically generated file, do not edit!                                 *|
1822
|*                                                                            *|
1823
\*===----------------------------------------------------------------------===*/
1824
1825
1826
#ifdef GET_REGINFO_TARGET_DESC
1827
#undef GET_REGINFO_TARGET_DESC
1828
1829
namespace llvm {
1830
1831
extern const MCRegisterClass SystemZMCRegisterClasses[];
1832
1833
static const MVT::SimpleValueType VTLists[] = {
1834
  /* 0 */ MVT::i32, MVT::Other,
1835
  /* 2 */ MVT::i64, MVT::Other,
1836
  /* 4 */ MVT::f32, MVT::Other,
1837
  /* 6 */ MVT::f64, MVT::Other,
1838
  /* 8 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::f128, MVT::Other,
1839
  /* 16 */ MVT::f32, MVT::v4i8, MVT::v2i16, MVT::Other,
1840
  /* 20 */ MVT::i64, MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v2f32, MVT::Other,
1841
  /* 27 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::Other,
1842
  /* 34 */ MVT::Untyped, MVT::Other,
1843
};
1844
1845
static const char *const SubRegIndexNameTable[] = { "subreg_h32", "subreg_h64", "subreg_hh32", "subreg_hl32", "subreg_hr32", "subreg_l32", "subreg_l64", "subreg_r32", "subreg_r64", "" };
1846
1847
1848
static const LaneBitmask SubRegIndexLaneMaskTable[] = {
1849
  LaneBitmask::getAll(),
1850
  LaneBitmask(0x00000001), // subreg_h32
1851
  LaneBitmask(0x0000000E), // subreg_h64
1852
  LaneBitmask(0x00000002), // subreg_hh32
1853
  LaneBitmask(0x00000004), // subreg_hl32
1854
  LaneBitmask(0x00000008), // subreg_hr32
1855
  LaneBitmask(0x00000010), // subreg_l32
1856
  LaneBitmask(0x00000031), // subreg_l64
1857
  LaneBitmask(0x00000020), // subreg_r32
1858
  LaneBitmask(0x00000020), // subreg_r64
1859
 };
1860
1861
1862
1863
static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
1864
  // Mode = 0 (Default)
1865
  { 32, 32, 32, VTLists+0 },    // GRX32Bit
1866
  { 32, 32, 32, VTLists+16 },    // VR32Bit
1867
  { 32, 32, 32, VTLists+0 },    // AR32Bit
1868
  { 32, 32, 32, VTLists+4 },    // FP32Bit
1869
  { 32, 32, 32, VTLists+0 },    // GR32Bit
1870
  { 32, 32, 32, VTLists+0 },    // GRH32Bit
1871
  { 32, 32, 32, VTLists+0 },    // ADDR32Bit
1872
  { 32, 32, 32, VTLists+0 },    // CCR
1873
  { 64, 64, 64, VTLists+20 },    // AnyRegBit
1874
  { 64, 64, 64, VTLists+20 },    // AnyRegBit_with_subreg_r32
1875
  { 64, 64, 64, VTLists+21 },    // VR64Bit
1876
  { 64, 64, 64, VTLists+20 },    // AnyRegBit_with_subreg_r64
1877
  { 64, 64, 64, VTLists+2 },    // CR64Bit
1878
  { 64, 64, 64, VTLists+6 },    // FP64Bit
1879
  { 64, 64, 64, VTLists+2 },    // GR64Bit
1880
  { 64, 64, 64, VTLists+2 },    // ADDR64Bit
1881
  { 128, 128, 128, VTLists+8 },    // VR128Bit
1882
  { 128, 128, 128, VTLists+27 },    // VF128Bit
1883
  { 128, 128, 128, VTLists+14 },    // FP128Bit
1884
  { 128, 128, 128, VTLists+34 },    // GR128Bit
1885
  { 128, 128, 128, VTLists+34 },    // ADDR128Bit
1886
};
1887
1888
static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
1889
1890
static const uint32_t GRX32BitSubClassMask[] = {
1891
  0x00000071, 
1892
  0x0018c000, // subreg_h32
1893
  0x00180000, // subreg_hh32
1894
  0x00180000, // subreg_hl32
1895
  0x0018c000, // subreg_l32
1896
};
1897
1898
static const uint32_t VR32BitSubClassMask[] = {
1899
  0x0000000a, 
1900
  0x00040000, // subreg_hr32
1901
  0x00072e00, // subreg_r32
1902
};
1903
1904
static const uint32_t AR32BitSubClassMask[] = {
1905
  0x00000004, 
1906
};
1907
1908
static const uint32_t FP32BitSubClassMask[] = {
1909
  0x00000008, 
1910
  0x00040000, // subreg_hr32
1911
  0x00062a00, // subreg_r32
1912
};
1913
1914
static const uint32_t GR32BitSubClassMask[] = {
1915
  0x00000050, 
1916
  0x00180000, // subreg_hl32
1917
  0x0018c000, // subreg_l32
1918
};
1919
1920
static const uint32_t GRH32BitSubClassMask[] = {
1921
  0x00000020, 
1922
  0x0018c000, // subreg_h32
1923
  0x00180000, // subreg_hh32
1924
};
1925
1926
static const uint32_t ADDR32BitSubClassMask[] = {
1927
  0x00000040, 
1928
  0x00100000, // subreg_hl32
1929
  0x00188000, // subreg_l32
1930
};
1931
1932
static const uint32_t CCRSubClassMask[] = {
1933
  0x00000080, 
1934
};
1935
1936
static const uint32_t AnyRegBitSubClassMask[] = {
1937
  0x0002eb00, 
1938
  0x001c0000, // subreg_h64
1939
  0x001c0000, // subreg_l64
1940
  0x00020800, // subreg_r64
1941
};
1942
1943
static const uint32_t AnyRegBit_with_subreg_r32SubClassMask[] = {
1944
  0x00022a00, 
1945
  0x00040000, // subreg_h64
1946
  0x00040000, // subreg_l64
1947
  0x00020800, // subreg_r64
1948
};
1949
1950
static const uint32_t VR64BitSubClassMask[] = {
1951
  0x00002400, 
1952
  0x00040000, // subreg_h64
1953
  0x00040000, // subreg_l64
1954
  0x00030800, // subreg_r64
1955
};
1956
1957
static const uint32_t AnyRegBit_with_subreg_r64SubClassMask[] = {
1958
  0x00020800, 
1959
};
1960
1961
static const uint32_t CR64BitSubClassMask[] = {
1962
  0x00001000, 
1963
};
1964
1965
static const uint32_t FP64BitSubClassMask[] = {
1966
  0x00002000, 
1967
  0x00040000, // subreg_h64
1968
  0x00040000, // subreg_l64
1969
  0x00020800, // subreg_r64
1970
};
1971
1972
static const uint32_t GR64BitSubClassMask[] = {
1973
  0x0000c000, 
1974
  0x00180000, // subreg_h64
1975
  0x00180000, // subreg_l64
1976
};
1977
1978
static const uint32_t ADDR64BitSubClassMask[] = {
1979
  0x00008000, 
1980
  0x00100000, // subreg_h64
1981
  0x00180000, // subreg_l64
1982
};
1983
1984
static const uint32_t VR128BitSubClassMask[] = {
1985
  0x00030000, 
1986
};
1987
1988
static const uint32_t VF128BitSubClassMask[] = {
1989
  0x00020000, 
1990
};
1991
1992
static const uint32_t FP128BitSubClassMask[] = {
1993
  0x00040000, 
1994
};
1995
1996
static const uint32_t GR128BitSubClassMask[] = {
1997
  0x00180000, 
1998
};
1999
2000
static const uint32_t ADDR128BitSubClassMask[] = {
2001
  0x00100000, 
2002
};
2003
2004
static const uint16_t SuperRegIdxSeqs[] = {
2005
  /* 0 */ 1, 3, 0,
2006
  /* 3 */ 1, 3, 4, 6, 0,
2007
  /* 8 */ 2, 7, 0,
2008
  /* 11 */ 5, 8, 0,
2009
  /* 14 */ 2, 7, 9, 0,
2010
};
2011
2012
static const TargetRegisterClass *const FP32BitSuperclasses[] = {
2013
  &SystemZ::VR32BitRegClass,
2014
  nullptr
2015
};
2016
2017
static const TargetRegisterClass *const GR32BitSuperclasses[] = {
2018
  &SystemZ::GRX32BitRegClass,
2019
  nullptr
2020
};
2021
2022
static const TargetRegisterClass *const GRH32BitSuperclasses[] = {
2023
  &SystemZ::GRX32BitRegClass,
2024
  nullptr
2025
};
2026
2027
static const TargetRegisterClass *const ADDR32BitSuperclasses[] = {
2028
  &SystemZ::GRX32BitRegClass,
2029
  &SystemZ::GR32BitRegClass,
2030
  nullptr
2031
};
2032
2033
static const TargetRegisterClass *const AnyRegBit_with_subreg_r32Superclasses[] = {
2034
  &SystemZ::AnyRegBitRegClass,
2035
  nullptr
2036
};
2037
2038
static const TargetRegisterClass *const AnyRegBit_with_subreg_r64Superclasses[] = {
2039
  &SystemZ::AnyRegBitRegClass,
2040
  &SystemZ::AnyRegBit_with_subreg_r32RegClass,
2041
  nullptr
2042
};
2043
2044
static const TargetRegisterClass *const FP64BitSuperclasses[] = {
2045
  &SystemZ::AnyRegBitRegClass,
2046
  &SystemZ::AnyRegBit_with_subreg_r32RegClass,
2047
  &SystemZ::VR64BitRegClass,
2048
  nullptr
2049
};
2050
2051
static const TargetRegisterClass *const GR64BitSuperclasses[] = {
2052
  &SystemZ::AnyRegBitRegClass,
2053
  nullptr
2054
};
2055
2056
static const TargetRegisterClass *const ADDR64BitSuperclasses[] = {
2057
  &SystemZ::AnyRegBitRegClass,
2058
  &SystemZ::GR64BitRegClass,
2059
  nullptr
2060
};
2061
2062
static const TargetRegisterClass *const VF128BitSuperclasses[] = {
2063
  &SystemZ::AnyRegBitRegClass,
2064
  &SystemZ::AnyRegBit_with_subreg_r32RegClass,
2065
  &SystemZ::AnyRegBit_with_subreg_r64RegClass,
2066
  &SystemZ::VR128BitRegClass,
2067
  nullptr
2068
};
2069
2070
static const TargetRegisterClass *const ADDR128BitSuperclasses[] = {
2071
  &SystemZ::GR128BitRegClass,
2072
  nullptr
2073
};
2074
2075
2076
namespace SystemZ {   // Register class instances
2077
  extern const TargetRegisterClass GRX32BitRegClass = {
2078
    &SystemZMCRegisterClasses[GRX32BitRegClassID],
2079
    GRX32BitSubClassMask,
2080
    SuperRegIdxSeqs + 3,
2081
    LaneBitmask(0x00000001),
2082
    0,
2083
    false, /* HasDisjunctSubRegs */
2084
    false, /* CoveredBySubRegs */
2085
    NullRegClasses,
2086
    nullptr
2087
  };
2088
2089
  extern const TargetRegisterClass VR32BitRegClass = {
2090
    &SystemZMCRegisterClasses[VR32BitRegClassID],
2091
    VR32BitSubClassMask,
2092
    SuperRegIdxSeqs + 11,
2093
    LaneBitmask(0x00000001),
2094
    0,
2095
    false, /* HasDisjunctSubRegs */
2096
    false, /* CoveredBySubRegs */
2097
    NullRegClasses,
2098
    nullptr
2099
  };
2100
2101
  extern const TargetRegisterClass AR32BitRegClass = {
2102
    &SystemZMCRegisterClasses[AR32BitRegClassID],
2103
    AR32BitSubClassMask,
2104
    SuperRegIdxSeqs + 2,
2105
    LaneBitmask(0x00000001),
2106
    0,
2107
    false, /* HasDisjunctSubRegs */
2108
    false, /* CoveredBySubRegs */
2109
    NullRegClasses,
2110
    nullptr
2111
  };
2112
2113
  extern const TargetRegisterClass FP32BitRegClass = {
2114
    &SystemZMCRegisterClasses[FP32BitRegClassID],
2115
    FP32BitSubClassMask,
2116
    SuperRegIdxSeqs + 11,
2117
    LaneBitmask(0x00000001),
2118
    0,
2119
    false, /* HasDisjunctSubRegs */
2120
    false, /* CoveredBySubRegs */
2121
    FP32BitSuperclasses,
2122
    nullptr
2123
  };
2124
2125
  extern const TargetRegisterClass GR32BitRegClass = {
2126
    &SystemZMCRegisterClasses[GR32BitRegClassID],
2127
    GR32BitSubClassMask,
2128
    SuperRegIdxSeqs + 5,
2129
    LaneBitmask(0x00000001),
2130
    0,
2131
    false, /* HasDisjunctSubRegs */
2132
    false, /* CoveredBySubRegs */
2133
    GR32BitSuperclasses,
2134
    nullptr
2135
  };
2136
2137
  extern const TargetRegisterClass GRH32BitRegClass = {
2138
    &SystemZMCRegisterClasses[GRH32BitRegClassID],
2139
    GRH32BitSubClassMask,
2140
    SuperRegIdxSeqs + 0,
2141
    LaneBitmask(0x00000001),
2142
    0,
2143
    false, /* HasDisjunctSubRegs */
2144
    false, /* CoveredBySubRegs */
2145
    GRH32BitSuperclasses,
2146
    nullptr
2147
  };
2148
2149
  extern const TargetRegisterClass ADDR32BitRegClass = {
2150
    &SystemZMCRegisterClasses[ADDR32BitRegClassID],
2151
    ADDR32BitSubClassMask,
2152
    SuperRegIdxSeqs + 5,
2153
    LaneBitmask(0x00000001),
2154
    0,
2155
    false, /* HasDisjunctSubRegs */
2156
    false, /* CoveredBySubRegs */
2157
    ADDR32BitSuperclasses,
2158
    nullptr
2159
  };
2160
2161
  extern const TargetRegisterClass CCRRegClass = {
2162
    &SystemZMCRegisterClasses[CCRRegClassID],
2163
    CCRSubClassMask,
2164
    SuperRegIdxSeqs + 2,
2165
    LaneBitmask(0x00000001),
2166
    0,
2167
    false, /* HasDisjunctSubRegs */
2168
    false, /* CoveredBySubRegs */
2169
    NullRegClasses,
2170
    nullptr
2171
  };
2172
2173
  extern const TargetRegisterClass AnyRegBitRegClass = {
2174
    &SystemZMCRegisterClasses[AnyRegBitRegClassID],
2175
    AnyRegBitSubClassMask,
2176
    SuperRegIdxSeqs + 14,
2177
    LaneBitmask(0x00000031),
2178
    0,
2179
    true, /* HasDisjunctSubRegs */
2180
    false, /* CoveredBySubRegs */
2181
    NullRegClasses,
2182
    nullptr
2183
  };
2184
2185
  extern const TargetRegisterClass AnyRegBit_with_subreg_r32RegClass = {
2186
    &SystemZMCRegisterClasses[AnyRegBit_with_subreg_r32RegClassID],
2187
    AnyRegBit_with_subreg_r32SubClassMask,
2188
    SuperRegIdxSeqs + 14,
2189
    LaneBitmask(0x00000020),
2190
    0,
2191
    false, /* HasDisjunctSubRegs */
2192
    false, /* CoveredBySubRegs */
2193
    AnyRegBit_with_subreg_r32Superclasses,
2194
    nullptr
2195
  };
2196
2197
  extern const TargetRegisterClass VR64BitRegClass = {
2198
    &SystemZMCRegisterClasses[VR64BitRegClassID],
2199
    VR64BitSubClassMask,
2200
    SuperRegIdxSeqs + 14,
2201
    LaneBitmask(0x00000020),
2202
    0,
2203
    false, /* HasDisjunctSubRegs */
2204
    false, /* CoveredBySubRegs */
2205
    NullRegClasses,
2206
    nullptr
2207
  };
2208
2209
  extern const TargetRegisterClass AnyRegBit_with_subreg_r64RegClass = {
2210
    &SystemZMCRegisterClasses[AnyRegBit_with_subreg_r64RegClassID],
2211
    AnyRegBit_with_subreg_r64SubClassMask,
2212
    SuperRegIdxSeqs + 2,
2213
    LaneBitmask(0x00000020),
2214
    0,
2215
    false, /* HasDisjunctSubRegs */
2216
    false, /* CoveredBySubRegs */
2217
    AnyRegBit_with_subreg_r64Superclasses,
2218
    nullptr
2219
  };
2220
2221
  extern const TargetRegisterClass CR64BitRegClass = {
2222
    &SystemZMCRegisterClasses[CR64BitRegClassID],
2223
    CR64BitSubClassMask,
2224
    SuperRegIdxSeqs + 2,
2225
    LaneBitmask(0x00000001),
2226
    0,
2227
    false, /* HasDisjunctSubRegs */
2228
    false, /* CoveredBySubRegs */
2229
    NullRegClasses,
2230
    nullptr
2231
  };
2232
2233
  extern const TargetRegisterClass FP64BitRegClass = {
2234
    &SystemZMCRegisterClasses[FP64BitRegClassID],
2235
    FP64BitSubClassMask,
2236
    SuperRegIdxSeqs + 14,
2237
    LaneBitmask(0x00000020),
2238
    0,
2239
    false, /* HasDisjunctSubRegs */
2240
    false, /* CoveredBySubRegs */
2241
    FP64BitSuperclasses,
2242
    nullptr
2243
  };
2244
2245
  extern const TargetRegisterClass GR64BitRegClass = {
2246
    &SystemZMCRegisterClasses[GR64BitRegClassID],
2247
    GR64BitSubClassMask,
2248
    SuperRegIdxSeqs + 8,
2249
    LaneBitmask(0x00000011),
2250
    0,
2251
    true, /* HasDisjunctSubRegs */
2252
    true, /* CoveredBySubRegs */
2253
    GR64BitSuperclasses,
2254
    nullptr
2255
  };
2256
2257
  extern const TargetRegisterClass ADDR64BitRegClass = {
2258
    &SystemZMCRegisterClasses[ADDR64BitRegClassID],
2259
    ADDR64BitSubClassMask,
2260
    SuperRegIdxSeqs + 8,
2261
    LaneBitmask(0x00000011),
2262
    0,
2263
    true, /* HasDisjunctSubRegs */
2264
    true, /* CoveredBySubRegs */
2265
    ADDR64BitSuperclasses,
2266
    nullptr
2267
  };
2268
2269
  extern const TargetRegisterClass VR128BitRegClass = {
2270
    &SystemZMCRegisterClasses[VR128BitRegClassID],
2271
    VR128BitSubClassMask,
2272
    SuperRegIdxSeqs + 2,
2273
    LaneBitmask(0x00000020),
2274
    0,
2275
    false, /* HasDisjunctSubRegs */
2276
    false, /* CoveredBySubRegs */
2277
    NullRegClasses,
2278
    nullptr
2279
  };
2280
2281
  extern const TargetRegisterClass VF128BitRegClass = {
2282
    &SystemZMCRegisterClasses[VF128BitRegClassID],
2283
    VF128BitSubClassMask,
2284
    SuperRegIdxSeqs + 2,
2285
    LaneBitmask(0x00000020),
2286
    0,
2287
    false, /* HasDisjunctSubRegs */
2288
    false, /* CoveredBySubRegs */
2289
    VF128BitSuperclasses,
2290
    nullptr
2291
  };
2292
2293
  extern const TargetRegisterClass FP128BitRegClass = {
2294
    &SystemZMCRegisterClasses[FP128BitRegClassID],
2295
    FP128BitSubClassMask,
2296
    SuperRegIdxSeqs + 2,
2297
    LaneBitmask(0x0000003F),
2298
    0,
2299
    true, /* HasDisjunctSubRegs */
2300
    true, /* CoveredBySubRegs */
2301
    NullRegClasses,
2302
    nullptr
2303
  };
2304
2305
  extern const TargetRegisterClass GR128BitRegClass = {
2306
    &SystemZMCRegisterClasses[GR128BitRegClassID],
2307
    GR128BitSubClassMask,
2308
    SuperRegIdxSeqs + 2,
2309
    LaneBitmask(0x0000003F),
2310
    0,
2311
    true, /* HasDisjunctSubRegs */
2312
    true, /* CoveredBySubRegs */
2313
    NullRegClasses,
2314
    nullptr
2315
  };
2316
2317
  extern const TargetRegisterClass ADDR128BitRegClass = {
2318
    &SystemZMCRegisterClasses[ADDR128BitRegClassID],
2319
    ADDR128BitSubClassMask,
2320
    SuperRegIdxSeqs + 2,
2321
    LaneBitmask(0x0000003F),
2322
    0,
2323
    true, /* HasDisjunctSubRegs */
2324
    true, /* CoveredBySubRegs */
2325
    ADDR128BitSuperclasses,
2326
    nullptr
2327
  };
2328
2329
} // end namespace SystemZ
2330
2331
namespace {
2332
  const TargetRegisterClass* const RegisterClasses[] = {
2333
    &SystemZ::GRX32BitRegClass,
2334
    &SystemZ::VR32BitRegClass,
2335
    &SystemZ::AR32BitRegClass,
2336
    &SystemZ::FP32BitRegClass,
2337
    &SystemZ::GR32BitRegClass,
2338
    &SystemZ::GRH32BitRegClass,
2339
    &SystemZ::ADDR32BitRegClass,
2340
    &SystemZ::CCRRegClass,
2341
    &SystemZ::AnyRegBitRegClass,
2342
    &SystemZ::AnyRegBit_with_subreg_r32RegClass,
2343
    &SystemZ::VR64BitRegClass,
2344
    &SystemZ::AnyRegBit_with_subreg_r64RegClass,
2345
    &SystemZ::CR64BitRegClass,
2346
    &SystemZ::FP64BitRegClass,
2347
    &SystemZ::GR64BitRegClass,
2348
    &SystemZ::ADDR64BitRegClass,
2349
    &SystemZ::VR128BitRegClass,
2350
    &SystemZ::VF128BitRegClass,
2351
    &SystemZ::FP128BitRegClass,
2352
    &SystemZ::GR128BitRegClass,
2353
    &SystemZ::ADDR128BitRegClass,
2354
  };
2355
} // end anonymous namespace
2356
2357
static const TargetRegisterInfoDesc SystemZRegInfoDesc[] = { // Extra Descriptors
2358
  { 0, false },
2359
  { 0, false },
2360
  { 0, false },
2361
  { 0, false },
2362
  { 0, false },
2363
  { 0, false },
2364
  { 0, false },
2365
  { 0, false },
2366
  { 0, false },
2367
  { 0, false },
2368
  { 0, false },
2369
  { 0, false },
2370
  { 0, false },
2371
  { 0, false },
2372
  { 0, false },
2373
  { 0, false },
2374
  { 0, false },
2375
  { 0, false },
2376
  { 0, false },
2377
  { 0, false },
2378
  { 0, false },
2379
  { 0, false },
2380
  { 0, false },
2381
  { 0, false },
2382
  { 0, false },
2383
  { 0, false },
2384
  { 0, false },
2385
  { 0, false },
2386
  { 0, false },
2387
  { 0, false },
2388
  { 0, false },
2389
  { 0, false },
2390
  { 0, false },
2391
  { 0, false },
2392
  { 0, true },
2393
  { 0, true },
2394
  { 0, true },
2395
  { 0, true },
2396
  { 0, true },
2397
  { 0, true },
2398
  { 0, true },
2399
  { 0, true },
2400
  { 0, true },
2401
  { 0, true },
2402
  { 0, true },
2403
  { 0, true },
2404
  { 0, true },
2405
  { 0, true },
2406
  { 0, true },
2407
  { 0, true },
2408
  { 0, true },
2409
  { 0, true },
2410
  { 0, true },
2411
  { 0, true },
2412
  { 0, true },
2413
  { 0, true },
2414
  { 0, true },
2415
  { 0, true },
2416
  { 0, true },
2417
  { 0, true },
2418
  { 0, true },
2419
  { 0, true },
2420
  { 0, true },
2421
  { 0, true },
2422
  { 0, true },
2423
  { 0, true },
2424
  { 0, true },
2425
  { 0, true },
2426
  { 0, true },
2427
  { 0, true },
2428
  { 0, true },
2429
  { 0, true },
2430
  { 0, true },
2431
  { 0, true },
2432
  { 0, true },
2433
  { 0, true },
2434
  { 0, true },
2435
  { 0, true },
2436
  { 0, true },
2437
  { 0, true },
2438
  { 0, true },
2439
  { 0, true },
2440
  { 0, true },
2441
  { 0, true },
2442
  { 0, true },
2443
  { 0, true },
2444
  { 0, true },
2445
  { 0, true },
2446
  { 0, true },
2447
  { 0, true },
2448
  { 0, true },
2449
  { 0, true },
2450
  { 0, true },
2451
  { 0, true },
2452
  { 0, true },
2453
  { 0, true },
2454
  { 0, true },
2455
  { 0, true },
2456
  { 0, true },
2457
  { 0, true },
2458
  { 0, true },
2459
  { 0, true },
2460
  { 0, true },
2461
  { 0, true },
2462
  { 0, true },
2463
  { 0, true },
2464
  { 0, true },
2465
  { 0, true },
2466
  { 0, true },
2467
  { 0, true },
2468
  { 0, true },
2469
  { 0, true },
2470
  { 0, true },
2471
  { 0, true },
2472
  { 0, true },
2473
  { 0, true },
2474
  { 0, true },
2475
  { 0, true },
2476
  { 0, true },
2477
  { 0, true },
2478
  { 0, true },
2479
  { 0, true },
2480
  { 0, true },
2481
  { 0, true },
2482
  { 0, true },
2483
  { 0, true },
2484
  { 0, true },
2485
  { 0, true },
2486
  { 0, true },
2487
  { 0, true },
2488
  { 0, true },
2489
  { 0, true },
2490
  { 0, true },
2491
  { 0, true },
2492
  { 0, true },
2493
  { 0, true },
2494
  { 0, true },
2495
  { 0, true },
2496
  { 0, true },
2497
  { 0, true },
2498
  { 0, true },
2499
  { 0, true },
2500
  { 0, true },
2501
  { 0, true },
2502
  { 0, true },
2503
  { 0, true },
2504
  { 0, true },
2505
  { 0, true },
2506
  { 0, true },
2507
  { 0, true },
2508
  { 0, true },
2509
  { 0, true },
2510
  { 0, true },
2511
  { 0, true },
2512
  { 0, true },
2513
  { 0, true },
2514
  { 0, true },
2515
  { 0, true },
2516
  { 0, true },
2517
  { 0, true },
2518
  { 0, true },
2519
  { 0, true },
2520
  { 0, true },
2521
  { 0, true },
2522
  { 0, true },
2523
  { 0, true },
2524
  { 0, true },
2525
  { 0, true },
2526
  { 0, true },
2527
  { 0, true },
2528
  { 0, true },
2529
  { 0, true },
2530
  { 0, true },
2531
  { 0, true },
2532
  { 0, true },
2533
  { 0, true },
2534
  { 0, true },
2535
  { 0, true },
2536
  { 0, true },
2537
  { 0, true },
2538
  { 0, true },
2539
  { 0, true },
2540
  { 0, true },
2541
  { 0, true },
2542
  { 0, true },
2543
  { 0, true },
2544
  { 0, true },
2545
  { 0, true },
2546
  { 0, true },
2547
  { 0, true },
2548
  { 0, true },
2549
  { 0, true },
2550
  { 0, true },
2551
  { 0, true },
2552
};
2553
89
unsigned SystemZGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
2554
89
  static const uint8_t RowMap[9] = {
2555
89
    0, 0, 0, 0, 0, 0, 1, 0, 1, 
2556
89
  };
2557
89
  static const uint8_t Rows[2][9] = {
2558
89
    { 3, 0, 0, 0, 0, 4, 0, 5, 0, },
2559
89
    { 1, 0, 0, 0, 0, 6, 0, 8, 0, },
2560
89
  };
2561
89
2562
89
  --IdxA; assert(IdxA < 9);
2563
89
  --IdxB; assert(IdxB < 9);
2564
89
  return Rows[RowMap[IdxA]][IdxB];
2565
89
}
2566
2567
  struct MaskRolOp {
2568
    LaneBitmask Mask;
2569
    uint8_t  RotateLeft;
2570
  };
2571
  static const MaskRolOp LaneMaskComposeSequences[] = {
2572
    { LaneBitmask(0xFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
2573
    { LaneBitmask(0x00000001),  1 }, { LaneBitmask(0x00000030), 30 }, { LaneBitmask::getNone(), 0 },   // Sequence 2
2574
    { LaneBitmask(0xFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 5
2575
    { LaneBitmask(0xFFFFFFFF),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 7
2576
    { LaneBitmask(0xFFFFFFFF),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 9
2577
    { LaneBitmask(0xFFFFFFFF),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 11
2578
    { LaneBitmask(0xFFFFFFFF),  5 }, { LaneBitmask::getNone(), 0 }  // Sequence 13
2579
  };
2580
  static const MaskRolOp *const CompositeSequences[] = {
2581
    &LaneMaskComposeSequences[0], // to subreg_h32
2582
    &LaneMaskComposeSequences[2], // to subreg_h64
2583
    &LaneMaskComposeSequences[5], // to subreg_hh32
2584
    &LaneMaskComposeSequences[7], // to subreg_hl32
2585
    &LaneMaskComposeSequences[9], // to subreg_hr32
2586
    &LaneMaskComposeSequences[11], // to subreg_l32
2587
    &LaneMaskComposeSequences[0], // to subreg_l64
2588
    &LaneMaskComposeSequences[13], // to subreg_r32
2589
    &LaneMaskComposeSequences[0] // to subreg_r64
2590
  };
2591
2592
0
LaneBitmask SystemZGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
2593
0
  --IdxA; assert(IdxA < 9 && "Subregister index out of bounds");
2594
0
  LaneBitmask Result;
2595
0
  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
2596
0
    LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
2597
0
    if (unsigned S = Ops->RotateLeft)
2598
0
      Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
2599
0
    else
2600
0
      Result |= LaneBitmask(M);
2601
0
  }
2602
0
  return Result;
2603
0
}
2604
2605
0
LaneBitmask SystemZGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
2606
0
  LaneMask &= getSubRegIndexLaneMask(IdxA);
2607
0
  --IdxA; assert(IdxA < 9 && "Subregister index out of bounds");
2608
0
  LaneBitmask Result;
2609
0
  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
2610
0
    LaneBitmask::Type M = LaneMask.getAsInteger();
2611
0
    if (unsigned S = Ops->RotateLeft)
2612
0
      Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
2613
0
    else
2614
0
      Result |= LaneBitmask(M);
2615
0
  }
2616
0
  return Result;
2617
0
}
2618
2619
4.21k
const TargetRegisterClass *SystemZGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
2620
4.21k
  static const uint8_t Table[21][9] = {
2621
4.21k
    { // GRX32Bit
2622
4.21k
      0,  // subreg_h32
2623
4.21k
      0,  // subreg_h64
2624
4.21k
      0,  // subreg_hh32
2625
4.21k
      0,  // subreg_hl32
2626
4.21k
      0,  // subreg_hr32
2627
4.21k
      0,  // subreg_l32
2628
4.21k
      0,  // subreg_l64
2629
4.21k
      0,  // subreg_r32
2630
4.21k
      0,  // subreg_r64
2631
4.21k
    },
2632
4.21k
    { // VR32Bit
2633
4.21k
      0,  // subreg_h32
2634
4.21k
      0,  // subreg_h64
2635
4.21k
      0,  // subreg_hh32
2636
4.21k
      0,  // subreg_hl32
2637
4.21k
      0,  // subreg_hr32
2638
4.21k
      0,  // subreg_l32
2639
4.21k
      0,  // subreg_l64
2640
4.21k
      0,  // subreg_r32
2641
4.21k
      0,  // subreg_r64
2642
4.21k
    },
2643
4.21k
    { // AR32Bit
2644
4.21k
      0,  // subreg_h32
2645
4.21k
      0,  // subreg_h64
2646
4.21k
      0,  // subreg_hh32
2647
4.21k
      0,  // subreg_hl32
2648
4.21k
      0,  // subreg_hr32
2649
4.21k
      0,  // subreg_l32
2650
4.21k
      0,  // subreg_l64
2651
4.21k
      0,  // subreg_r32
2652
4.21k
      0,  // subreg_r64
2653
4.21k
    },
2654
4.21k
    { // FP32Bit
2655
4.21k
      0,  // subreg_h32
2656
4.21k
      0,  // subreg_h64
2657
4.21k
      0,  // subreg_hh32
2658
4.21k
      0,  // subreg_hl32
2659
4.21k
      0,  // subreg_hr32
2660
4.21k
      0,  // subreg_l32
2661
4.21k
      0,  // subreg_l64
2662
4.21k
      0,  // subreg_r32
2663
4.21k
      0,  // subreg_r64
2664
4.21k
    },
2665
4.21k
    { // GR32Bit
2666
4.21k
      0,  // subreg_h32
2667
4.21k
      0,  // subreg_h64
2668
4.21k
      0,  // subreg_hh32
2669
4.21k
      0,  // subreg_hl32
2670
4.21k
      0,  // subreg_hr32
2671
4.21k
      0,  // subreg_l32
2672
4.21k
      0,  // subreg_l64
2673
4.21k
      0,  // subreg_r32
2674
4.21k
      0,  // subreg_r64
2675
4.21k
    },
2676
4.21k
    { // GRH32Bit
2677
4.21k
      0,  // subreg_h32
2678
4.21k
      0,  // subreg_h64
2679
4.21k
      0,  // subreg_hh32
2680
4.21k
      0,  // subreg_hl32
2681
4.21k
      0,  // subreg_hr32
2682
4.21k
      0,  // subreg_l32
2683
4.21k
      0,  // subreg_l64
2684
4.21k
      0,  // subreg_r32
2685
4.21k
      0,  // subreg_r64
2686
4.21k
    },
2687
4.21k
    { // ADDR32Bit
2688
4.21k
      0,  // subreg_h32
2689
4.21k
      0,  // subreg_h64
2690
4.21k
      0,  // subreg_hh32
2691
4.21k
      0,  // subreg_hl32
2692
4.21k
      0,  // subreg_hr32
2693
4.21k
      0,  // subreg_l32
2694
4.21k
      0,  // subreg_l64
2695
4.21k
      0,  // subreg_r32
2696
4.21k
      0,  // subreg_r64
2697
4.21k
    },
2698
4.21k
    { // CCR
2699
4.21k
      0,  // subreg_h32
2700
4.21k
      0,  // subreg_h64
2701
4.21k
      0,  // subreg_hh32
2702
4.21k
      0,  // subreg_hl32
2703
4.21k
      0,  // subreg_hr32
2704
4.21k
      0,  // subreg_l32
2705
4.21k
      0,  // subreg_l64
2706
4.21k
      0,  // subreg_r32
2707
4.21k
      0,  // subreg_r64
2708
4.21k
    },
2709
4.21k
    { // AnyRegBit
2710
4.21k
      15, // subreg_h32 -> GR64Bit
2711
4.21k
      0,  // subreg_h64
2712
4.21k
      0,  // subreg_hh32
2713
4.21k
      0,  // subreg_hl32
2714
4.21k
      0,  // subreg_hr32
2715
4.21k
      15, // subreg_l32 -> GR64Bit
2716
4.21k
      0,  // subreg_l64
2717
4.21k
      10, // subreg_r32 -> AnyRegBit_with_subreg_r32
2718
4.21k
      12, // subreg_r64 -> AnyRegBit_with_subreg_r64
2719
4.21k
    },
2720
4.21k
    { // AnyRegBit_with_subreg_r32
2721
4.21k
      0,  // subreg_h32
2722
4.21k
      0,  // subreg_h64
2723
4.21k
      0,  // subreg_hh32
2724
4.21k
      0,  // subreg_hl32
2725
4.21k
      0,  // subreg_hr32
2726
4.21k
      0,  // subreg_l32
2727
4.21k
      0,  // subreg_l64
2728
4.21k
      10, // subreg_r32 -> AnyRegBit_with_subreg_r32
2729
4.21k
      12, // subreg_r64 -> AnyRegBit_with_subreg_r64
2730
4.21k
    },
2731
4.21k
    { // VR64Bit
2732
4.21k
      0,  // subreg_h32
2733
4.21k
      0,  // subreg_h64
2734
4.21k
      0,  // subreg_hh32
2735
4.21k
      0,  // subreg_hl32
2736
4.21k
      0,  // subreg_hr32
2737
4.21k
      0,  // subreg_l32
2738
4.21k
      0,  // subreg_l64
2739
4.21k
      11, // subreg_r32 -> VR64Bit
2740
4.21k
      0,  // subreg_r64
2741
4.21k
    },
2742
4.21k
    { // AnyRegBit_with_subreg_r64
2743
4.21k
      0,  // subreg_h32
2744
4.21k
      0,  // subreg_h64
2745
4.21k
      0,  // subreg_hh32
2746
4.21k
      0,  // subreg_hl32
2747
4.21k
      0,  // subreg_hr32
2748
4.21k
      0,  // subreg_l32
2749
4.21k
      0,  // subreg_l64
2750
4.21k
      12, // subreg_r32 -> AnyRegBit_with_subreg_r64
2751
4.21k
      12, // subreg_r64 -> AnyRegBit_with_subreg_r64
2752
4.21k
    },
2753
4.21k
    { // CR64Bit
2754
4.21k
      0,  // subreg_h32
2755
4.21k
      0,  // subreg_h64
2756
4.21k
      0,  // subreg_hh32
2757
4.21k
      0,  // subreg_hl32
2758
4.21k
      0,  // subreg_hr32
2759
4.21k
      0,  // subreg_l32
2760
4.21k
      0,  // subreg_l64
2761
4.21k
      0,  // subreg_r32
2762
4.21k
      0,  // subreg_r64
2763
4.21k
    },
2764
4.21k
    { // FP64Bit
2765
4.21k
      0,  // subreg_h32
2766
4.21k
      0,  // subreg_h64
2767
4.21k
      0,  // subreg_hh32
2768
4.21k
      0,  // subreg_hl32
2769
4.21k
      0,  // subreg_hr32
2770
4.21k
      0,  // subreg_l32
2771
4.21k
      0,  // subreg_l64
2772
4.21k
      14, // subreg_r32 -> FP64Bit
2773
4.21k
      0,  // subreg_r64
2774
4.21k
    },
2775
4.21k
    { // GR64Bit
2776
4.21k
      15, // subreg_h32 -> GR64Bit
2777
4.21k
      0,  // subreg_h64
2778
4.21k
      0,  // subreg_hh32
2779
4.21k
      0,  // subreg_hl32
2780
4.21k
      0,  // subreg_hr32
2781
4.21k
      15, // subreg_l32 -> GR64Bit
2782
4.21k
      0,  // subreg_l64
2783
4.21k
      0,  // subreg_r32
2784
4.21k
      0,  // subreg_r64
2785
4.21k
    },
2786
4.21k
    { // ADDR64Bit
2787
4.21k
      16, // subreg_h32 -> ADDR64Bit
2788
4.21k
      0,  // subreg_h64
2789
4.21k
      0,  // subreg_hh32
2790
4.21k
      0,  // subreg_hl32
2791
4.21k
      0,  // subreg_hr32
2792
4.21k
      16, // subreg_l32 -> ADDR64Bit
2793
4.21k
      0,  // subreg_l64
2794
4.21k
      0,  // subreg_r32
2795
4.21k
      0,  // subreg_r64
2796
4.21k
    },
2797
4.21k
    { // VR128Bit
2798
4.21k
      0,  // subreg_h32
2799
4.21k
      0,  // subreg_h64
2800
4.21k
      0,  // subreg_hh32
2801
4.21k
      0,  // subreg_hl32
2802
4.21k
      0,  // subreg_hr32
2803
4.21k
      0,  // subreg_l32
2804
4.21k
      0,  // subreg_l64
2805
4.21k
      17, // subreg_r32 -> VR128Bit
2806
4.21k
      17, // subreg_r64 -> VR128Bit
2807
4.21k
    },
2808
4.21k
    { // VF128Bit
2809
4.21k
      0,  // subreg_h32
2810
4.21k
      0,  // subreg_h64
2811
4.21k
      0,  // subreg_hh32
2812
4.21k
      0,  // subreg_hl32
2813
4.21k
      0,  // subreg_hr32
2814
4.21k
      0,  // subreg_l32
2815
4.21k
      0,  // subreg_l64
2816
4.21k
      18, // subreg_r32 -> VF128Bit
2817
4.21k
      18, // subreg_r64 -> VF128Bit
2818
4.21k
    },
2819
4.21k
    { // FP128Bit
2820
4.21k
      0,  // subreg_h32
2821
4.21k
      19, // subreg_h64 -> FP128Bit
2822
4.21k
      0,  // subreg_hh32
2823
4.21k
      0,  // subreg_hl32
2824
4.21k
      19, // subreg_hr32 -> FP128Bit
2825
4.21k
      0,  // subreg_l32
2826
4.21k
      19, // subreg_l64 -> FP128Bit
2827
4.21k
      19, // subreg_r32 -> FP128Bit
2828
4.21k
      0,  // subreg_r64
2829
4.21k
    },
2830
4.21k
    { // GR128Bit
2831
4.21k
      20, // subreg_h32 -> GR128Bit
2832
4.21k
      20, // subreg_h64 -> GR128Bit
2833
4.21k
      20, // subreg_hh32 -> GR128Bit
2834
4.21k
      20, // subreg_hl32 -> GR128Bit
2835
4.21k
      0,  // subreg_hr32
2836
4.21k
      20, // subreg_l32 -> GR128Bit
2837
4.21k
      20, // subreg_l64 -> GR128Bit
2838
4.21k
      0,  // subreg_r32
2839
4.21k
      0,  // subreg_r64
2840
4.21k
    },
2841
4.21k
    { // ADDR128Bit
2842
4.21k
      21, // subreg_h32 -> ADDR128Bit
2843
4.21k
      21, // subreg_h64 -> ADDR128Bit
2844
4.21k
      21, // subreg_hh32 -> ADDR128Bit
2845
4.21k
      21, // subreg_hl32 -> ADDR128Bit
2846
4.21k
      0,  // subreg_hr32
2847
4.21k
      21, // subreg_l32 -> ADDR128Bit
2848
4.21k
      21, // subreg_l64 -> ADDR128Bit
2849
4.21k
      0,  // subreg_r32
2850
4.21k
      0,  // subreg_r64
2851
4.21k
    },
2852
4.21k
  };
2853
4.21k
  assert(RC && "Missing regclass");
2854
4.21k
  if (!Idx) 
return RC0
;
2855
4.21k
  --Idx;
2856
4.21k
  assert(Idx < 9 && "Bad subreg");
2857
4.21k
  unsigned TV = Table[RC->getID()][Idx];
2858
4.21k
  return TV ? getRegClass(TV - 1) : 
nullptr0
;
2859
4.21k
}
2860
2861
/// Get the weight in units of pressure for this register class.
2862
const RegClassWeight &SystemZGenRegisterInfo::
2863
107k
getRegClassWeight(const TargetRegisterClass *RC) const {
2864
107k
  static const RegClassWeight RCWeightTable[] = {
2865
107k
    {1, 32},    // GRX32Bit
2866
107k
    {1, 32},    // VR32Bit
2867
107k
    {0, 0},   // AR32Bit
2868
107k
    {1, 16},    // FP32Bit
2869
107k
    {1, 16},    // GR32Bit
2870
107k
    {1, 16},    // GRH32Bit
2871
107k
    {1, 15},    // ADDR32Bit
2872
107k
    {0, 0},   // CCR
2873
107k
    {1, 48},    // AnyRegBit
2874
107k
    {1, 16},    // AnyRegBit_with_subreg_r32
2875
107k
    {1, 32},    // VR64Bit
2876
107k
    {1, 16},    // AnyRegBit_with_subreg_r64
2877
107k
    {0, 0},   // CR64Bit
2878
107k
    {1, 16},    // FP64Bit
2879
107k
    {2, 32},    // GR64Bit
2880
107k
    {2, 30},    // ADDR64Bit
2881
107k
    {1, 32},    // VR128Bit
2882
107k
    {1, 16},    // VF128Bit
2883
107k
    {2, 16},    // FP128Bit
2884
107k
    {4, 32},    // GR128Bit
2885
107k
    {4, 28},    // ADDR128Bit
2886
107k
  };
2887
107k
  return RCWeightTable[RC->getID()];
2888
107k
}
2889
2890
/// Get the weight in units of pressure for this register unit.
2891
unsigned SystemZGenRegisterInfo::
2892
17.6k
getRegUnitWeight(unsigned RegUnit) const {
2893
17.6k
  assert(RegUnit < 97 && "invalid register unit");
2894
17.6k
  // All register units have unit weight.
2895
17.6k
  return 1;
2896
17.6k
}
2897
2898
2899
// Get the number of dimensions of register pressure.
2900
13.5k
unsigned SystemZGenRegisterInfo::getNumRegPressureSets() const {
2901
13.5k
  return 5;
2902
13.5k
}
2903
2904
// Get the name of this register unit pressure set.
2905
const char *SystemZGenRegisterInfo::
2906
0
getRegPressureSetName(unsigned Idx) const {
2907
0
  static const char *const PressureNameTable[] = {
2908
0
    "FP32Bit",
2909
0
    "GR32Bit",
2910
0
    "GRH32Bit",
2911
0
    "GRX32Bit",
2912
0
    "VR32Bit",
2913
0
  };
2914
0
  return PressureNameTable[Idx];
2915
0
}
2916
2917
// Get the register unit pressure limit for this dimension.
2918
// This limit must be adjusted dynamically for reserved registers.
2919
unsigned SystemZGenRegisterInfo::
2920
36.5k
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
2921
36.5k
  static const uint8_t PressureLimitTable[] = {
2922
36.5k
    16,   // 0: FP32Bit
2923
36.5k
    16,   // 1: GR32Bit
2924
36.5k
    16,   // 2: GRH32Bit
2925
36.5k
    32,   // 3: GRX32Bit
2926
36.5k
    32,   // 4: VR32Bit
2927
36.5k
  };
2928
36.5k
  return PressureLimitTable[Idx];
2929
36.5k
}
2930
2931
/// Table of pressure sets per register class or unit.
2932
static const int RCSetsTable[] = {
2933
  /* 0 */ 1, 3, -1,
2934
  /* 3 */ 2, 3, -1,
2935
  /* 6 */ 0, 4, -1,
2936
};
2937
2938
/// Get the dimensions of register pressure impacted by this register class.
2939
/// Returns a -1 terminated array of pressure set IDs
2940
const int* SystemZGenRegisterInfo::
2941
121k
getRegClassPressureSets(const TargetRegisterClass *RC) const {
2942
121k
  static const uint8_t RCSetStartTable[] = {
2943
121k
    1,7,2,6,0,3,0,2,2,2,7,2,2,6,1,1,7,6,6,1,1,};
2944
121k
  return &RCSetsTable[RCSetStartTable[RC->getID()]];
2945
121k
}
2946
2947
/// Get the dimensions of register pressure impacted by this register unit.
2948
/// Returns a -1 terminated array of pressure set IDs
2949
const int* SystemZGenRegisterInfo::
2950
17.6k
getRegUnitPressureSets(unsigned RegUnit) const {
2951
17.6k
  assert(RegUnit < 97 && "invalid register unit");
2952
17.6k
  static const uint8_t RUSetStartTable[] = {
2953
17.6k
    2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,0,3,};
2954
17.6k
  return &RCSetsTable[RUSetStartTable[RegUnit]];
2955
17.6k
}
2956
2957
extern const MCRegisterDesc SystemZRegDesc[];
2958
extern const MCPhysReg SystemZRegDiffLists[];
2959
extern const LaneBitmask SystemZLaneMaskLists[];
2960
extern const char SystemZRegStrings[];
2961
extern const char SystemZRegClassStrings[];
2962
extern const MCPhysReg SystemZRegUnitRoots[][2];
2963
extern const uint16_t SystemZSubRegIdxLists[];
2964
extern const MCRegisterInfo::SubRegCoveredBits SystemZSubRegIdxRanges[];
2965
extern const uint16_t SystemZRegEncodingTable[];
2966
// SystemZ Dwarf<->LLVM register mappings.
2967
extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0Dwarf2L[];
2968
extern const unsigned SystemZDwarfFlavour0Dwarf2LSize;
2969
2970
extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0Dwarf2L[];
2971
extern const unsigned SystemZEHFlavour0Dwarf2LSize;
2972
2973
extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0L2Dwarf[];
2974
extern const unsigned SystemZDwarfFlavour0L2DwarfSize;
2975
2976
extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0L2Dwarf[];
2977
extern const unsigned SystemZEHFlavour0L2DwarfSize;
2978
2979
SystemZGenRegisterInfo::
2980
SystemZGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
2981
      unsigned PC, unsigned HwMode)
2982
  : TargetRegisterInfo(SystemZRegInfoDesc, RegisterClasses, RegisterClasses+21,
2983
             SubRegIndexNameTable, SubRegIndexLaneMaskTable,
2984
947
             LaneBitmask(0xFFFFFFDF), RegClassInfos, HwMode) {
2985
947
  InitMCRegisterInfo(SystemZRegDesc, 194, RA, PC,
2986
947
                     SystemZMCRegisterClasses, 21,
2987
947
                     SystemZRegUnitRoots,
2988
947
                     97,
2989
947
                     SystemZRegDiffLists,
2990
947
                     SystemZLaneMaskLists,
2991
947
                     SystemZRegStrings,
2992
947
                     SystemZRegClassStrings,
2993
947
                     SystemZSubRegIdxLists,
2994
947
                     10,
2995
947
                     SystemZSubRegIdxRanges,
2996
947
                     SystemZRegEncodingTable);
2997
947
2998
947
  switch (DwarfFlavour) {
2999
947
  default:
3000
0
    llvm_unreachable("Unknown DWARF flavour");
3001
947
  case 0:
3002
947
    mapDwarfRegsToLLVMRegs(SystemZDwarfFlavour0Dwarf2L, SystemZDwarfFlavour0Dwarf2LSize, false);
3003
947
    break;
3004
947
  }
3005
947
  switch (EHFlavour) {
3006
947
  default:
3007
0
    llvm_unreachable("Unknown DWARF flavour");
3008
947
  case 0:
3009
947
    mapDwarfRegsToLLVMRegs(SystemZEHFlavour0Dwarf2L, SystemZEHFlavour0Dwarf2LSize, true);
3010
947
    break;
3011
947
  }
3012
947
  switch (DwarfFlavour) {
3013
947
  default:
3014
0
    llvm_unreachable("Unknown DWARF flavour");
3015
947
  case 0:
3016
947
    mapLLVMRegsToDwarfRegs(SystemZDwarfFlavour0L2Dwarf, SystemZDwarfFlavour0L2DwarfSize, false);
3017
947
    break;
3018
947
  }
3019
947
  switch (EHFlavour) {
3020
947
  default:
3021
0
    llvm_unreachable("Unknown DWARF flavour");
3022
947
  case 0:
3023
947
    mapLLVMRegsToDwarfRegs(SystemZEHFlavour0L2Dwarf, SystemZEHFlavour0L2DwarfSize, true);
3024
947
    break;
3025
947
  }
3026
947
}
3027
3028
static const MCPhysReg CSR_SystemZ_SaveList[] = { SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 0 };
3029
static const uint32_t CSR_SystemZ_RegMask[] = { 0x00000000, 0x00000000, 0x0003fc00, 0x03fc03c0, 0x03ff0000, 0xe3ff03ff, 0x00000003, };
3030
static const MCPhysReg CSR_SystemZ_AllRegs_SaveList[] = { SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 0 };
3031
static const uint32_t CSR_SystemZ_AllRegs_RegMask[] = { 0x00000000, 0x00000000, 0x0003fffc, 0x03fffffc, 0xf3fff000, 0xfbfff3ff, 0x00000003, };
3032
static const MCPhysReg CSR_SystemZ_AllRegs_Vector_SaveList[] = { SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15, SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31, 0 };
3033
static const uint32_t CSR_SystemZ_AllRegs_Vector_RegMask[] = { 0x00000000, 0xfffffffc, 0xffffffff, 0xffffffff, 0xf3fff3ff, 0xfbfff3ff, 0x00000003, };
3034
static const MCPhysReg CSR_SystemZ_SwiftError_SaveList[] = { SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 0 };
3035
static const uint32_t CSR_SystemZ_SwiftError_RegMask[] = { 0x00000000, 0x00000000, 0x0003fc00, 0x03fc03c0, 0x03f70000, 0xa3f703f7, 0x00000003, };
3036
3037
3038
10
ArrayRef<const uint32_t *> SystemZGenRegisterInfo::getRegMasks() const {
3039
10
  static const uint32_t *const Masks[] = {
3040
10
    CSR_SystemZ_RegMask,
3041
10
    CSR_SystemZ_AllRegs_RegMask,
3042
10
    CSR_SystemZ_AllRegs_Vector_RegMask,
3043
10
    CSR_SystemZ_SwiftError_RegMask,
3044
10
  };
3045
10
  return makeArrayRef(Masks);
3046
10
}
3047
3048
10
ArrayRef<const char *> SystemZGenRegisterInfo::getRegMaskNames() const {
3049
10
  static const char *const Names[] = {
3050
10
    "CSR_SystemZ",
3051
10
    "CSR_SystemZ_AllRegs",
3052
10
    "CSR_SystemZ_AllRegs_Vector",
3053
10
    "CSR_SystemZ_SwiftError",
3054
10
  };
3055
10
  return makeArrayRef(Names);
3056
10
}
3057
3058
const SystemZFrameLowering *
3059
20.5k
SystemZGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
3060
20.5k
  return static_cast<const SystemZFrameLowering *>(
3061
20.5k
      MF.getSubtarget().getFrameLowering());
3062
20.5k
}
3063
3064
} // end namespace llvm
3065
3066
#endif // GET_REGINFO_TARGET_DESC
3067