Coverage Report

Created: 2019-03-24 22:13

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/X86/X86GenAsmMatcher.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Assembly Matcher Source Fragment                                           *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
#ifdef GET_ASSEMBLER_HEADER
11
#undef GET_ASSEMBLER_HEADER
12
  // This should be included into the middle of the declaration of
13
  // your subclasses implementation of MCTargetAsmParser.
14
  FeatureBitset ComputeAvailableFeatures(const FeatureBitset& FB) const;
15
  void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
16
                       const OperandVector &Operands);
17
  void convertToMapAndConstraints(unsigned Kind,
18
                           const OperandVector &Operands) override;
19
  unsigned MatchInstructionImpl(const OperandVector &Operands,
20
                                MCInst &Inst,
21
                                uint64_t &ErrorInfo,
22
                                FeatureBitset &MissingFeatures,
23
                                bool matchingInlineAsm,
24
                                unsigned VariantID = 0);
25
  unsigned MatchInstructionImpl(const OperandVector &Operands,
26
                                MCInst &Inst,
27
                                uint64_t &ErrorInfo,
28
                                bool matchingInlineAsm,
29
0
                                unsigned VariantID = 0) {
30
0
    FeatureBitset MissingFeatures;
31
0
    return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
32
0
                                matchingInlineAsm, VariantID);
33
0
  }
34
35
#endif // GET_ASSEMBLER_HEADER_INFO
36
37
38
#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
39
#undef GET_OPERAND_DIAGNOSTIC_TYPES
40
41
#endif // GET_OPERAND_DIAGNOSTIC_TYPES
42
43
44
#ifdef GET_REGISTER_MATCHER
45
#undef GET_REGISTER_MATCHER
46
47
// Bits for subtarget features that participate in instruction matching.
48
enum SubtargetFeatureBits : uint8_t {
49
  Feature_Not64BitModeBit = 4,
50
  Feature_In64BitModeBit = 2,
51
  Feature_In16BitModeBit = 0,
52
  Feature_Not16BitModeBit = 3,
53
  Feature_In32BitModeBit = 1,
54
};
55
56
345k
static unsigned MatchRegisterName(StringRef Name) {
57
345k
  switch (Name.size()) {
58
345k
  
default: break395
;
59
345k
  case 2:  // 34 strings to match.
60
34.4k
    switch (Name[0]) {
61
34.4k
    
default: break141
;
62
34.4k
    case 'a':  // 3 strings to match.
63
1.10k
      switch (Name[1]) {
64
1.10k
      
default: break0
;
65
1.10k
      case 'h':  // 1 string to match.
66
4
        return 1;  // "ah"
67
1.10k
      case 'l':  // 1 string to match.
68
626
        return 2;  // "al"
69
1.10k
      case 'x':  // 1 string to match.
70
473
        return 3;  // "ax"
71
0
      }
72
0
      break;
73
340
    case 'b':  // 4 strings to match.
74
340
      switch (Name[1]) {
75
340
      
default: break0
;
76
340
      case 'h':  // 1 string to match.
77
0
        return 4;  // "bh"
78
340
      case 'l':  // 1 string to match.
79
134
        return 5;  // "bl"
80
340
      case 'p':  // 1 string to match.
81
17
        return 6;  // "bp"
82
340
      case 'x':  // 1 string to match.
83
189
        return 9;  // "bx"
84
0
      }
85
0
      break;
86
1.88k
    case 'c':  // 4 strings to match.
87
1.88k
      switch (Name[1]) {
88
1.88k
      
default: break0
;
89
1.88k
      case 'h':  // 1 string to match.
90
1
        return 10;  // "ch"
91
1.88k
      case 'l':  // 1 string to match.
92
1.19k
        return 11;  // "cl"
93
1.88k
      case 's':  // 1 string to match.
94
35
        return 12;  // "cs"
95
1.88k
      case 'x':  // 1 string to match.
96
655
        return 13;  // "cx"
97
0
      }
98
0
      break;
99
1.67k
    case 'd':  // 5 strings to match.
100
1.67k
      switch (Name[1]) {
101
1.67k
      
default: break0
;
102
1.67k
      case 'h':  // 1 string to match.
103
1
        return 15;  // "dh"
104
1.67k
      case 'i':  // 1 string to match.
105
1.35k
        return 16;  // "di"
106
1.67k
      case 'l':  // 1 string to match.
107
3
        return 19;  // "dl"
108
1.67k
      case 's':  // 1 string to match.
109
52
        return 20;  // "ds"
110
1.67k
      case 'x':  // 1 string to match.
111
270
        return 21;  // "dx"
112
0
      }
113
0
      break;
114
338
    case 'e':  // 1 string to match.
115
338
      if (Name[1] != 's')
116
0
        break;
117
338
      return 31;   // "es"
118
338
    case 'f':  // 1 string to match.
119
156
      if (Name[1] != 's')
120
0
        break;
121
156
      return 36;   // "fs"
122
167
    case 'g':  // 1 string to match.
123
167
      if (Name[1] != 's')
124
0
        break;
125
167
      return 37;   // "gs"
126
167
    case 'i':  // 1 string to match.
127
0
      if (Name[1] != 'p')
128
0
        break;
129
0
      return 47;   // "ip"
130
26.1k
    case 'k':  // 8 strings to match.
131
26.1k
      switch (Name[1]) {
132
26.1k
      
default: break0
;
133
26.1k
      case '0':  // 1 string to match.
134
5
        return 110;  // "k0"
135
26.1k
      case '1':  // 1 string to match.
136
3.38k
        return 111;  // "k1"
137
26.1k
      case '2':  // 1 string to match.
138
17.9k
        return 112;  // "k2"
139
26.1k
      case '3':  // 1 string to match.
140
1.27k
        return 113;  // "k3"
141
26.1k
      case '4':  // 1 string to match.
142
1.16k
        return 114;  // "k4"
143
26.1k
      case '5':  // 1 string to match.
144
1.00k
        return 115;  // "k5"
145
26.1k
      case '6':  // 1 string to match.
146
672
        return 116;  // "k6"
147
26.1k
      case '7':  // 1 string to match.
148
686
        return 117;  // "k7"
149
0
      }
150
0
      break;
151
621
    case 'r':  // 2 strings to match.
152
621
      switch (Name[1]) {
153
621
      
default: break6
;
154
621
      case '8':  // 1 string to match.
155
354
        return 126;  // "r8"
156
621
      case '9':  // 1 string to match.
157
261
        return 127;  // "r9"
158
6
      }
159
6
      break;
160
1.88k
    case 's':  // 4 strings to match.
161
1.88k
      switch (Name[1]) {
162
1.88k
      
default: break0
;
163
1.88k
      case 'i':  // 1 string to match.
164
711
        return 58;  // "si"
165
1.88k
      case 'p':  // 1 string to match.
166
2
        return 61;  // "sp"
167
1.88k
      case 's':  // 1 string to match.
168
20
        return 64;  // "ss"
169
1.88k
      case 't':  // 1 string to match.
170
1.14k
        return 134;  // "st"
171
0
      }
172
0
      break;
173
147
    }
174
147
    break;
175
130k
  case 3:  // 73 strings to match.
176
130k
    switch (Name[0]) {
177
130k
    
default: break319
;
178
130k
    case 'b':  // 1 string to match.
179
8
      if (memcmp(Name.data()+1, "pl", 2) != 0)
180
6
        break;
181
2
      return 8;  // "bpl"
182
21
    case 'c':  // 10 strings to match.
183
21
      if (Name[1] != 'r')
184
0
        break;
185
21
      switch (Name[2]) {
186
21
      
default: break0
;
187
21
      case '0':  // 1 string to match.
188
4
        return 70;  // "cr0"
189
21
      case '1':  // 1 string to match.
190
2
        return 71;  // "cr1"
191
21
      case '2':  // 1 string to match.
192
3
        return 72;  // "cr2"
193
21
      case '3':  // 1 string to match.
194
5
        return 73;  // "cr3"
195
21
      case '4':  // 1 string to match.
196
4
        return 74;  // "cr4"
197
21
      case '5':  // 1 string to match.
198
0
        return 75;  // "cr5"
199
21
      case '6':  // 1 string to match.
200
0
        return 76;  // "cr6"
201
21
      case '7':  // 1 string to match.
202
0
        return 77;  // "cr7"
203
21
      case '8':  // 1 string to match.
204
3
        return 78;  // "cr8"
205
21
      case '9':  // 1 string to match.
206
0
        return 79;  // "cr9"
207
0
      }
208
0
      break;
209
660
    case 'd':  // 11 strings to match.
210
660
      switch (Name[1]) {
211
660
      
default: break2
;
212
660
      case 'i':  // 1 string to match.
213
631
        if (Name[2] != 'l')
214
0
          break;
215
631
        return 18;   // "dil"
216
631
      case 'r':  // 10 strings to match.
217
27
        switch (Name[2]) {
218
27
        
default: break0
;
219
27
        case '0':  // 1 string to match.
220
3
          return 86;  // "dr0"
221
27
        case '1':  // 1 string to match.
222
5
          return 87;  // "dr1"
223
27
        case '2':  // 1 string to match.
224
3
          return 88;  // "dr2"
225
27
        case '3':  // 1 string to match.
226
3
          return 89;  // "dr3"
227
27
        case '4':  // 1 string to match.
228
2
          return 90;  // "dr4"
229
27
        case '5':  // 1 string to match.
230
2
          return 91;  // "dr5"
231
27
        case '6':  // 1 string to match.
232
4
          return 92;  // "dr6"
233
27
        case '7':  // 1 string to match.
234
3
          return 93;  // "dr7"
235
27
        case '8':  // 1 string to match.
236
2
          return 94;  // "dr8"
237
27
        case '9':  // 1 string to match.
238
0
          return 95;  // "dr9"
239
0
        }
240
0
        break;
241
2
      }
242
2
      break;
243
41.8k
    case 'e':  // 10 strings to match.
244
41.8k
      switch (Name[1]) {
245
41.8k
      
default: break0
;
246
41.8k
      case 'a':  // 1 string to match.
247
17.6k
        if (Name[2] != 'x')
248
0
          break;
249
17.6k
        return 22;   // "eax"
250
17.6k
      case 'b':  // 2 strings to match.
251
2.91k
        switch (Name[2]) {
252
2.91k
        
default: break0
;
253
2.91k
        case 'p':  // 1 string to match.
254
367
          return 23;  // "ebp"
255
2.91k
        case 'x':  // 1 string to match.
256
2.54k
          return 24;  // "ebx"
257
0
        }
258
0
        break;
259
3.41k
      case 'c':  // 1 string to match.
260
3.41k
        if (Name[2] != 'x')
261
0
          break;
262
3.41k
        return 25;   // "ecx"
263
16.2k
      case 'd':  // 2 strings to match.
264
16.2k
        switch (Name[2]) {
265
16.2k
        
default: break0
;
266
16.2k
        case 'i':  // 1 string to match.
267
1.84k
          return 26;  // "edi"
268
16.2k
        case 'x':  // 1 string to match.
269
14.3k
          return 27;  // "edx"
270
0
        }
271
0
        break;
272
26
      case 'i':  // 2 strings to match.
273
26
        switch (Name[2]) {
274
26
        
default: break0
;
275
26
        case 'p':  // 1 string to match.
276
13
          return 29;  // "eip"
277
26
        case 'z':  // 1 string to match.
278
13
          return 30;  // "eiz"
279
0
        }
280
0
        break;
281
1.60k
      case 's':  // 2 strings to match.
282
1.60k
        switch (Name[2]) {
283
1.60k
        
default: break0
;
284
1.60k
        case 'i':  // 1 string to match.
285
1.06k
          return 32;  // "esi"
286
1.60k
        case 'p':  // 1 string to match.
287
542
          return 33;  // "esp"
288
0
        }
289
0
        break;
290
0
      }
291
0
      break;
292
27
    case 'f':  // 8 strings to match.
293
27
      if (Name[1] != 'p')
294
27
        break;
295
0
      switch (Name[2]) {
296
0
      default: break;
297
0
      case '0':  // 1 string to match.
298
0
        return 102;  // "fp0"
299
0
      case '1':  // 1 string to match.
300
0
        return 103;  // "fp1"
301
0
      case '2':  // 1 string to match.
302
0
        return 104;  // "fp2"
303
0
      case '3':  // 1 string to match.
304
0
        return 105;  // "fp3"
305
0
      case '4':  // 1 string to match.
306
0
        return 106;  // "fp4"
307
0
      case '5':  // 1 string to match.
308
0
        return 107;  // "fp5"
309
0
      case '6':  // 1 string to match.
310
0
        return 108;  // "fp6"
311
0
      case '7':  // 1 string to match.
312
0
        return 109;  // "fp7"
313
0
      }
314
0
      break;
315
5.59k
    case 'm':  // 8 strings to match.
316
5.59k
      if (Name[1] != 'm')
317
4
        break;
318
5.58k
      switch (Name[2]) {
319
5.58k
      
default: break0
;
320
5.58k
      case '0':  // 1 string to match.
321
997
        return 118;  // "mm0"
322
5.58k
      case '1':  // 1 string to match.
323
74
        return 119;  // "mm1"
324
5.58k
      case '2':  // 1 string to match.
325
2.05k
        return 120;  // "mm2"
326
5.58k
      case '3':  // 1 string to match.
327
1.12k
        return 121;  // "mm3"
328
5.58k
      case '4':  // 1 string to match.
329
1.33k
        return 122;  // "mm4"
330
5.58k
      case '5':  // 1 string to match.
331
6
        return 123;  // "mm5"
332
5.58k
      case '6':  // 1 string to match.
333
2
        return 124;  // "mm6"
334
5.58k
      case '7':  // 1 string to match.
335
2
        return 125;  // "mm7"
336
0
      }
337
0
      break;
338
81.6k
    case 'r':  // 22 strings to match.
339
81.6k
      switch (Name[1]) {
340
81.6k
      
default: break4
;
341
81.6k
      case '1':  // 6 strings to match.
342
4.29k
        switch (Name[2]) {
343
4.29k
        
default: break0
;
344
4.29k
        case '0':  // 1 string to match.
345
125
          return 128;  // "r10"
346
4.29k
        case '1':  // 1 string to match.
347
96
          return 129;  // "r11"
348
4.29k
        case '2':  // 1 string to match.
349
44
          return 130;  // "r12"
350
4.29k
        case '3':  // 1 string to match.
351
75
          return 131;  // "r13"
352
4.29k
        case '4':  // 1 string to match.
353
3.40k
          return 132;  // "r14"
354
4.29k
        case '5':  // 1 string to match.
355
547
          return 133;  // "r15"
356
0
        }
357
0
        break;
358
12
      case '8':  // 3 strings to match.
359
12
        switch (Name[2]) {
360
12
        
default: break0
;
361
12
        case 'b':  // 1 string to match.
362
0
          return 238;  // "r8b"
363
12
        case 'd':  // 1 string to match.
364
12
          return 254;  // "r8d"
365
12
        case 'w':  // 1 string to match.
366
0
          return 262;  // "r8w"
367
0
        }
368
0
        break;
369
2
      case '9':  // 3 strings to match.
370
2
        switch (Name[2]) {
371
2
        
default: break0
;
372
2
        case 'b':  // 1 string to match.
373
1
          return 239;  // "r9b"
374
2
        case 'd':  // 1 string to match.
375
1
          return 255;  // "r9d"
376
2
        case 'w':  // 1 string to match.
377
0
          return 263;  // "r9w"
378
0
        }
379
0
        break;
380
31.6k
      case 'a':  // 1 string to match.
381
31.6k
        if (Name[2] != 'x')
382
0
          break;
383
31.6k
        return 48;   // "rax"
384
31.6k
      case 'b':  // 2 strings to match.
385
2.05k
        switch (Name[2]) {
386
2.05k
        
default: break0
;
387
2.05k
        case 'p':  // 1 string to match.
388
599
          return 49;  // "rbp"
389
2.05k
        case 'x':  // 1 string to match.
390
1.45k
          return 50;  // "rbx"
391
0
        }
392
0
        break;
393
6.91k
      case 'c':  // 1 string to match.
394
6.91k
        if (Name[2] != 'x')
395
0
          break;
396
6.91k
        return 51;   // "rcx"
397
33.5k
      case 'd':  // 2 strings to match.
398
33.5k
        switch (Name[2]) {
399
33.5k
        
default: break0
;
400
33.5k
        case 'i':  // 1 string to match.
401
2.10k
          return 52;  // "rdi"
402
33.5k
        case 'x':  // 1 string to match.
403
31.4k
          return 53;  // "rdx"
404
0
        }
405
0
        break;
406
460
      case 'i':  // 2 strings to match.
407
460
        switch (Name[2]) {
408
460
        
default: break0
;
409
460
        case 'p':  // 1 string to match.
410
452
          return 54;  // "rip"
411
460
        case 'z':  // 1 string to match.
412
8
          return 55;  // "riz"
413
0
        }
414
0
        break;
415
2.68k
      case 's':  // 2 strings to match.
416
2.68k
        switch (Name[2]) {
417
2.68k
        
default: break0
;
418
2.68k
        case 'i':  // 1 string to match.
419
1.04k
          return 56;  // "rsi"
420
2.68k
        case 'p':  // 1 string to match.
421
1.63k
          return 57;  // "rsp"
422
0
        }
423
0
        break;
424
4
      }
425
4
      break;
426
215
    case 's':  // 3 strings to match.
427
215
      switch (Name[1]) {
428
215
      
default: break13
;
429
215
      case 'i':  // 1 string to match.
430
200
        if (Name[2] != 'l')
431
0
          break;
432
200
        return 60;   // "sil"
433
200
      case 'p':  // 1 string to match.
434
2
        if (Name[2] != 'l')
435
0
          break;
436
2
        return 63;   // "spl"
437
2
      case 's':  // 1 string to match.
438
0
        if (Name[2] != 'p')
439
0
          break;
440
0
        return 65;  // "ssp"
441
13
      }
442
13
      break;
443
375
    }
444
375
    break;
445
100k
  case 4:  // 66 strings to match.
446
100k
    switch (Name[0]) {
447
100k
    
default: break244
;
448
100k
    case 'b':  // 4 strings to match.
449
26
      if (memcmp(Name.data()+1, "nd", 2) != 0)
450
2
        break;
451
24
      switch (Name[3]) {
452
24
      
default: break0
;
453
24
      case '0':  // 1 string to match.
454
3
        return 66;  // "bnd0"
455
24
      case '1':  // 1 string to match.
456
13
        return 67;  // "bnd1"
457
24
      case '2':  // 1 string to match.
458
3
        return 68;  // "bnd2"
459
24
      case '3':  // 1 string to match.
460
5
        return 69;  // "bnd3"
461
0
      }
462
0
      break;
463
1
    case 'c':  // 6 strings to match.
464
1
      if (memcmp(Name.data()+1, "r1", 2) != 0)
465
0
        break;
466
1
      switch (Name[3]) {
467
1
      
default: break0
;
468
1
      case '0':  // 1 string to match.
469
0
        return 80;  // "cr10"
470
1
      case '1':  // 1 string to match.
471
0
        return 81;  // "cr11"
472
1
      case '2':  // 1 string to match.
473
0
        return 82;  // "cr12"
474
1
      case '3':  // 1 string to match.
475
0
        return 83;  // "cr13"
476
1
      case '4':  // 1 string to match.
477
0
        return 84;  // "cr14"
478
1
      case '5':  // 1 string to match.
479
1
        return 85;  // "cr15"
480
0
      }
481
0
      break;
482
3
    case 'd':  // 6 strings to match.
483
3
      if (memcmp(Name.data()+1, "r1", 2) != 0)
484
2
        break;
485
1
      switch (Name[3]) {
486
1
      
default: break0
;
487
1
      case '0':  // 1 string to match.
488
0
        return 96;  // "dr10"
489
1
      case '1':  // 1 string to match.
490
0
        return 97;  // "dr11"
491
1
      case '2':  // 1 string to match.
492
0
        return 98;  // "dr12"
493
1
      case '3':  // 1 string to match.
494
0
        return 99;  // "dr13"
495
1
      case '4':  // 1 string to match.
496
0
        return 100;  // "dr14"
497
1
      case '5':  // 1 string to match.
498
1
        return 101;  // "dr15"
499
0
      }
500
0
      break;
501
0
    case 'f':  // 2 strings to match.
502
0
      if (Name[1] != 'p')
503
0
        break;
504
0
      switch (Name[2]) {
505
0
      default: break;
506
0
      case 'c':  // 1 string to match.
507
0
        if (Name[3] != 'r')
508
0
          break;
509
0
        return 34;   // "fpcr"
510
0
      case 's':  // 1 string to match.
511
0
        if (Name[3] != 'r')
512
0
          break;
513
0
        return 35;  // "fpsr"
514
0
      }
515
0
      break;
516
1.43k
    case 'r':  // 18 strings to match.
517
1.43k
      if (Name[1] != '1')
518
0
        break;
519
1.43k
      switch (Name[2]) {
520
1.43k
      
default: break0
;
521
1.43k
      case '0':  // 3 strings to match.
522
33
        switch (Name[3]) {
523
33
        
default: break0
;
524
33
        case 'b':  // 1 string to match.
525
0
          return 240;  // "r10b"
526
33
        case 'd':  // 1 string to match.
527
33
          return 256;  // "r10d"
528
33
        case 'w':  // 1 string to match.
529
0
          return 264;  // "r10w"
530
0
        }
531
0
        break;
532
31
      case '1':  // 3 strings to match.
533
31
        switch (Name[3]) {
534
31
        
default: break0
;
535
31
        case 'b':  // 1 string to match.
536
4
          return 241;  // "r11b"
537
31
        case 'd':  // 1 string to match.
538
18
          return 257;  // "r11d"
539
31
        case 'w':  // 1 string to match.
540
9
          return 265;  // "r11w"
541
0
        }
542
0
        break;
543
18
      case '2':  // 3 strings to match.
544
18
        switch (Name[3]) {
545
18
        
default: break0
;
546
18
        case 'b':  // 1 string to match.
547
0
          return 242;  // "r12b"
548
18
        case 'd':  // 1 string to match.
549
18
          return 258;  // "r12d"
550
18
        case 'w':  // 1 string to match.
551
0
          return 266;  // "r12w"
552
0
        }
553
0
        break;
554
930
      case '3':  // 3 strings to match.
555
930
        switch (Name[3]) {
556
930
        
default: break0
;
557
930
        case 'b':  // 1 string to match.
558
0
          return 243;  // "r13b"
559
930
        case 'd':  // 1 string to match.
560
898
          return 259;  // "r13d"
561
930
        case 'w':  // 1 string to match.
562
32
          return 267;  // "r13w"
563
0
        }
564
0
        break;
565
401
      case '4':  // 3 strings to match.
566
401
        switch (Name[3]) {
567
401
        
default: break0
;
568
401
        case 'b':  // 1 string to match.
569
216
          return 244;  // "r14b"
570
401
        case 'd':  // 1 string to match.
571
15
          return 260;  // "r14d"
572
401
        case 'w':  // 1 string to match.
573
170
          return 268;  // "r14w"
574
0
        }
575
0
        break;
576
24
      case '5':  // 3 strings to match.
577
24
        switch (Name[3]) {
578
24
        
default: break0
;
579
24
        case 'b':  // 1 string to match.
580
0
          return 245;  // "r15b"
581
24
        case 'd':  // 1 string to match.
582
24
          return 261;  // "r15d"
583
24
        case 'w':  // 1 string to match.
584
0
          return 269;  // "r15w"
585
0
        }
586
0
        break;
587
0
      }
588
0
      break;
589
55.4k
    case 'x':  // 10 strings to match.
590
55.4k
      if (memcmp(Name.data()+1, "mm", 2) != 0)
591
0
        break;
592
55.4k
      switch (Name[3]) {
593
55.4k
      
default: break0
;
594
55.4k
      case '0':  // 1 string to match.
595
7.62k
        return 142;  // "xmm0"
596
55.4k
      case '1':  // 1 string to match.
597
22.0k
        return 143;  // "xmm1"
598
55.4k
      case '2':  // 1 string to match.
599
11.6k
        return 144;  // "xmm2"
600
55.4k
      case '3':  // 1 string to match.
601
1.71k
        return 145;  // "xmm3"
602
55.4k
      case '4':  // 1 string to match.
603
350
        return 146;  // "xmm4"
604
55.4k
      case '5':  // 1 string to match.
605
3.41k
        return 147;  // "xmm5"
606
55.4k
      case '6':  // 1 string to match.
607
7.89k
        return 148;  // "xmm6"
608
55.4k
      case '7':  // 1 string to match.
609
301
        return 149;  // "xmm7"
610
55.4k
      case '8':  // 1 string to match.
611
295
        return 150;  // "xmm8"
612
55.4k
      case '9':  // 1 string to match.
613
120
        return 151;  // "xmm9"
614
0
      }
615
0
      break;
616
21.0k
    case 'y':  // 10 strings to match.
617
21.0k
      if (memcmp(Name.data()+1, "mm", 2) != 0)
618
0
        break;
619
21.0k
      switch (Name[3]) {
620
21.0k
      
default: break0
;
621
21.0k
      case '0':  // 1 string to match.
622
2.23k
        return 174;  // "ymm0"
623
21.0k
      case '1':  // 1 string to match.
624
3.41k
        return 175;  // "ymm1"
625
21.0k
      case '2':  // 1 string to match.
626
3.83k
        return 176;  // "ymm2"
627
21.0k
      case '3':  // 1 string to match.
628
535
        return 177;  // "ymm3"
629
21.0k
      case '4':  // 1 string to match.
630
3.87k
        return 178;  // "ymm4"
631
21.0k
      case '5':  // 1 string to match.
632
208
        return 179;  // "ymm5"
633
21.0k
      case '6':  // 1 string to match.
634
134
        return 180;  // "ymm6"
635
21.0k
      case '7':  // 1 string to match.
636
3.38k
        return 181;  // "ymm7"
637
21.0k
      case '8':  // 1 string to match.
638
24
        return 182;  // "ymm8"
639
21.0k
      case '9':  // 1 string to match.
640
3.39k
        return 183;  // "ymm9"
641
0
      }
642
0
      break;
643
22.2k
    case 'z':  // 10 strings to match.
644
22.2k
      if (memcmp(Name.data()+1, "mm", 2) != 0)
645
0
        break;
646
22.2k
      switch (Name[3]) {
647
22.2k
      
default: break0
;
648
22.2k
      case '0':  // 1 string to match.
649
34
        return 206;  // "zmm0"
650
22.2k
      case '1':  // 1 string to match.
651
988
        return 207;  // "zmm1"
652
22.2k
      case '2':  // 1 string to match.
653
15.8k
        return 208;  // "zmm2"
654
22.2k
      case '3':  // 1 string to match.
655
952
        return 209;  // "zmm3"
656
22.2k
      case '4':  // 1 string to match.
657
737
        return 210;  // "zmm4"
658
22.2k
      case '5':  // 1 string to match.
659
821
        return 211;  // "zmm5"
660
22.2k
      case '6':  // 1 string to match.
661
1.02k
        return 212;  // "zmm6"
662
22.2k
      case '7':  // 1 string to match.
663
637
        return 213;  // "zmm7"
664
22.2k
      case '8':  // 1 string to match.
665
593
        return 214;  // "zmm8"
666
22.2k
      case '9':  // 1 string to match.
667
602
        return 215;  // "zmm9"
668
0
      }
669
0
      break;
670
248
    }
671
248
    break;
672
79.5k
  case 5:  // 74 strings to match.
673
79.5k
    switch (Name[0]) {
674
79.5k
    
default: break63
;
675
79.5k
    case 'f':  // 1 string to match.
676
2
      if (memcmp(Name.data()+1, "lags", 4) != 0)
677
0
        break;
678
2
      return 28;   // "flags"
679
2
    case 's':  // 7 strings to match.
680
0
      if (memcmp(Name.data()+1, "t(", 2) != 0)
681
0
        break;
682
0
      switch (Name[3]) {
683
0
      default: break;
684
0
      case '1':  // 1 string to match.
685
0
        if (Name[4] != ')')
686
0
          break;
687
0
        return 135;  // "st(1)"
688
0
      case '2':  // 1 string to match.
689
0
        if (Name[4] != ')')
690
0
          break;
691
0
        return 136;  // "st(2)"
692
0
      case '3':  // 1 string to match.
693
0
        if (Name[4] != ')')
694
0
          break;
695
0
        return 137;  // "st(3)"
696
0
      case '4':  // 1 string to match.
697
0
        if (Name[4] != ')')
698
0
          break;
699
0
        return 138;  // "st(4)"
700
0
      case '5':  // 1 string to match.
701
0
        if (Name[4] != ')')
702
0
          break;
703
0
        return 139;  // "st(5)"
704
0
      case '6':  // 1 string to match.
705
0
        if (Name[4] != ')')
706
0
          break;
707
0
        return 140;  // "st(6)"
708
0
      case '7':  // 1 string to match.
709
0
        if (Name[4] != ')')
710
0
          break;
711
0
        return 141;  // "st(7)"
712
0
      }
713
0
      break;
714
30.1k
    case 'x':  // 22 strings to match.
715
30.1k
      if (memcmp(Name.data()+1, "mm", 2) != 0)
716
0
        break;
717
30.1k
      switch (Name[3]) {
718
30.1k
      
default: break0
;
719
30.1k
      case '1':  // 10 strings to match.
720
18.7k
        switch (Name[4]) {
721
18.7k
        
default: break0
;
722
18.7k
        case '0':  // 1 string to match.
723
526
          return 152;  // "xmm10"
724
18.7k
        case '1':  // 1 string to match.
725
690
          return 153;  // "xmm11"
726
18.7k
        case '2':  // 1 string to match.
727
937
          return 154;  // "xmm12"
728
18.7k
        case '3':  // 1 string to match.
729
821
          return 155;  // "xmm13"
730
18.7k
        case '4':  // 1 string to match.
731
397
          return 156;  // "xmm14"
732
18.7k
        case '5':  // 1 string to match.
733
10.1k
          return 157;  // "xmm15"
734
18.7k
        case '6':  // 1 string to match.
735
490
          return 158;  // "xmm16"
736
18.7k
        case '7':  // 1 string to match.
737
1.93k
          return 159;  // "xmm17"
738
18.7k
        case '8':  // 1 string to match.
739
837
          return 160;  // "xmm18"
740
18.7k
        case '9':  // 1 string to match.
741
1.98k
          return 161;  // "xmm19"
742
0
        }
743
0
        break;
744
10.5k
      case '2':  // 10 strings to match.
745
10.5k
        switch (Name[4]) {
746
10.5k
        
default: break0
;
747
10.5k
        case '0':  // 1 string to match.
748
1.07k
          return 162;  // "xmm20"
749
10.5k
        case '1':  // 1 string to match.
750
1.31k
          return 163;  // "xmm21"
751
10.5k
        case '2':  // 1 string to match.
752
1.02k
          return 164;  // "xmm22"
753
10.5k
        case '3':  // 1 string to match.
754
1.11k
          return 165;  // "xmm23"
755
10.5k
        case '4':  // 1 string to match.
756
953
          return 166;  // "xmm24"
757
10.5k
        case '5':  // 1 string to match.
758
1.01k
          return 167;  // "xmm25"
759
10.5k
        case '6':  // 1 string to match.
760
966
          return 168;  // "xmm26"
761
10.5k
        case '7':  // 1 string to match.
762
922
          return 169;  // "xmm27"
763
10.5k
        case '8':  // 1 string to match.
764
1.11k
          return 170;  // "xmm28"
765
10.5k
        case '9':  // 1 string to match.
766
1.05k
          return 171;  // "xmm29"
767
0
        }
768
0
        break;
769
871
      case '3':  // 2 strings to match.
770
871
        switch (Name[4]) {
771
871
        
default: break0
;
772
871
        case '0':  // 1 string to match.
773
637
          return 172;  // "xmm30"
774
871
        case '1':  // 1 string to match.
775
234
          return 173;  // "xmm31"
776
0
        }
777
0
        break;
778
0
      }
779
0
      break;
780
13.9k
    case 'y':  // 22 strings to match.
781
13.9k
      if (memcmp(Name.data()+1, "mm", 2) != 0)
782
0
        break;
783
13.9k
      switch (Name[3]) {
784
13.9k
      
default: break0
;
785
13.9k
      case '1':  // 10 strings to match.
786
5.13k
        switch (Name[4]) {
787
5.13k
        
default: break0
;
788
5.13k
        case '0':  // 1 string to match.
789
168
          return 184;  // "ymm10"
790
5.13k
        case '1':  // 1 string to match.
791
218
          return 185;  // "ymm11"
792
5.13k
        case '2':  // 1 string to match.
793
223
          return 186;  // "ymm12"
794
5.13k
        case '3':  // 1 string to match.
795
81
          return 187;  // "ymm13"
796
5.13k
        case '4':  // 1 string to match.
797
28
          return 188;  // "ymm14"
798
5.13k
        case '5':  // 1 string to match.
799
55
          return 189;  // "ymm15"
800
5.13k
        case '6':  // 1 string to match.
801
456
          return 190;  // "ymm16"
802
5.13k
        case '7':  // 1 string to match.
803
1.50k
          return 191;  // "ymm17"
804
5.13k
        case '8':  // 1 string to match.
805
607
          return 192;  // "ymm18"
806
5.13k
        case '9':  // 1 string to match.
807
1.79k
          return 193;  // "ymm19"
808
0
        }
809
0
        break;
810
8.18k
      case '2':  // 10 strings to match.
811
8.18k
        switch (Name[4]) {
812
8.18k
        
default: break0
;
813
8.18k
        case '0':  // 1 string to match.
814
834
          return 194;  // "ymm20"
815
8.18k
        case '1':  // 1 string to match.
816
1.00k
          return 195;  // "ymm21"
817
8.18k
        case '2':  // 1 string to match.
818
738
          return 196;  // "ymm22"
819
8.18k
        case '3':  // 1 string to match.
820
1.16k
          return 197;  // "ymm23"
821
8.18k
        case '4':  // 1 string to match.
822
692
          return 198;  // "ymm24"
823
8.18k
        case '5':  // 1 string to match.
824
833
          return 199;  // "ymm25"
825
8.18k
        case '6':  // 1 string to match.
826
834
          return 200;  // "ymm26"
827
8.18k
        case '7':  // 1 string to match.
828
641
          return 201;  // "ymm27"
829
8.18k
        case '8':  // 1 string to match.
830
778
          return 202;  // "ymm28"
831
8.18k
        case '9':  // 1 string to match.
832
660
          return 203;  // "ymm29"
833
0
        }
834
0
        break;
835
586
      case '3':  // 2 strings to match.
836
586
        switch (Name[4]) {
837
586
        
default: break0
;
838
586
        case '0':  // 1 string to match.
839
448
          return 204;  // "ymm30"
840
586
        case '1':  // 1 string to match.
841
138
          return 205;  // "ymm31"
842
0
        }
843
0
        break;
844
0
      }
845
0
      break;
846
35.3k
    case 'z':  // 22 strings to match.
847
35.3k
      if (memcmp(Name.data()+1, "mm", 2) != 0)
848
0
        break;
849
35.3k
      switch (Name[3]) {
850
35.3k
      
default: break0
;
851
35.3k
      case '1':  // 10 strings to match.
852
25.0k
        switch (Name[4]) {
853
25.0k
        
default: break0
;
854
25.0k
        case '0':  // 1 string to match.
855
587
          return 216;  // "zmm10"
856
25.0k
        case '1':  // 1 string to match.
857
460
          return 217;  // "zmm11"
858
25.0k
        case '2':  // 1 string to match.
859
677
          return 218;  // "zmm12"
860
25.0k
        case '3':  // 1 string to match.
861
504
          return 219;  // "zmm13"
862
25.0k
        case '4':  // 1 string to match.
863
738
          return 220;  // "zmm14"
864
25.0k
        case '5':  // 1 string to match.
865
456
          return 221;  // "zmm15"
866
25.0k
        case '6':  // 1 string to match.
867
1.05k
          return 222;  // "zmm16"
868
25.0k
        case '7':  // 1 string to match.
869
1.93k
          return 223;  // "zmm17"
870
25.0k
        case '8':  // 1 string to match.
871
940
          return 224;  // "zmm18"
872
25.0k
        case '9':  // 1 string to match.
873
17.6k
          return 225;  // "zmm19"
874
0
        }
875
0
        break;
876
9.91k
      case '2':  // 10 strings to match.
877
9.91k
        switch (Name[4]) {
878
9.91k
        
default: break0
;
879
9.91k
        case '0':  // 1 string to match.
880
798
          return 226;  // "zmm20"
881
9.91k
        case '1':  // 1 string to match.
882
1.18k
          return 227;  // "zmm21"
883
9.91k
        case '2':  // 1 string to match.
884
1.19k
          return 228;  // "zmm22"
885
9.91k
        case '3':  // 1 string to match.
886
943
          return 229;  // "zmm23"
887
9.91k
        case '4':  // 1 string to match.
888
875
          return 230;  // "zmm24"
889
9.91k
        case '5':  // 1 string to match.
890
1.16k
          return 231;  // "zmm25"
891
9.91k
        case '6':  // 1 string to match.
892
904
          return 232;  // "zmm26"
893
9.91k
        case '7':  // 1 string to match.
894
788
          return 233;  // "zmm27"
895
9.91k
        case '8':  // 1 string to match.
896
1.09k
          return 234;  // "zmm28"
897
9.91k
        case '9':  // 1 string to match.
898
957
          return 235;  // "zmm29"
899
0
        }
900
0
        break;
901
457
      case '3':  // 2 strings to match.
902
457
        switch (Name[4]) {
903
457
        
default: break0
;
904
457
        case '0':  // 1 string to match.
905
456
          return 236;  // "zmm30"
906
457
        case '1':  // 1 string to match.
907
1
          return 237;  // "zmm31"
908
0
        }
909
0
        break;
910
0
      }
911
0
      break;
912
63
    }
913
63
    break;
914
63
  case 7:  // 1 string to match.
915
38
    if (memcmp(Name.data()+0, "dirflag", 7) != 0)
916
38
      break;
917
0
    return 14;  // "dirflag"
918
1.26k
  }
919
1.26k
  return 0;
920
1.26k
}
921
922
#endif // GET_REGISTER_MATCHER
923
924
925
#ifdef GET_SUBTARGET_FEATURE_NAME
926
#undef GET_SUBTARGET_FEATURE_NAME
927
928
// User-level names for subtarget features that participate in
929
// instruction matching.
930
23
static const char *getSubtargetFeatureName(uint64_t Val) {
931
23
  switch(Val) {
932
23
  
case Feature_Not64BitModeBit: return "Not 64-bit mode"5
;
933
23
  
case Feature_In64BitModeBit: return "64-bit mode"18
;
934
23
  
case Feature_In16BitModeBit: return "16-bit mode"0
;
935
23
  
case Feature_Not16BitModeBit: return "Not 16-bit mode"0
;
936
23
  
case Feature_In32BitModeBit: return "32-bit mode"0
;
937
23
  
default: return "(unknown)"0
;
938
23
  }
939
23
}
940
941
#endif // GET_SUBTARGET_FEATURE_NAME
942
943
944
#ifdef GET_MATCHER_IMPLEMENTATION
945
#undef GET_MATCHER_IMPLEMENTATION
946
947
174k
static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID) {
948
174k
  switch (VariantID) {
949
174k
    case 0:
950
160k
      switch (Mnemonic.size()) {
951
160k
      
default: break24.8k
;
952
160k
      case 3:  // 6 strings to match.
953
11.3k
        switch (Mnemonic[0]) {
954
11.3k
        
default: break10.3k
;
955
11.3k
        case 'c':  // 4 strings to match.
956
129
          switch (Mnemonic[1]) {
957
129
          
default: break81
;
958
129
          case 'b':  // 1 string to match.
959
12
            if (Mnemonic[2] != 'w')
960
0
              break;
961
12
            Mnemonic = "cbtw";   // "cbw"
962
12
            return;
963
12
          case 'd':  // 1 string to match.
964
12
            if (Mnemonic[2] != 'q')
965
0
              break;
966
12
            Mnemonic = "cltd";   // "cdq"
967
12
            return;
968
12
          case 'q':  // 1 string to match.
969
12
            if (Mnemonic[2] != 'o')
970
0
              break;
971
12
            Mnemonic = "cqto";   // "cqo"
972
12
            return;
973
12
          case 'w':  // 1 string to match.
974
12
            if (Mnemonic[2] != 'd')
975
0
              break;
976
12
            Mnemonic = "cwtd";   // "cwd"
977
12
            return;
978
81
          }
979
81
          break;
980
266
        case 'p':  // 1 string to match.
981
266
          if (memcmp(Mnemonic.data()+1, "op", 2) != 0)
982
97
            break;
983
169
          if (Features.test(Feature_In16BitModeBit))   // "pop"
984
3
            Mnemonic = "popw";
985
166
          else if (Features.test(Feature_In32BitModeBit))
986
7
            Mnemonic = "popl";
987
159
          else if (Features.test(Feature_In64BitModeBit))
988
159
            Mnemonic = "popq";
989
169
          return;
990
568
        case 'r':  // 1 string to match.
991
568
          if (memcmp(Mnemonic.data()+1, "et", 2) != 0)
992
14
            break;
993
554
          if (Features.test(Feature_In16BitModeBit))   // "ret"
994
3
            Mnemonic = "retw";
995
551
          else if (Features.test(Feature_In32BitModeBit))
996
171
            Mnemonic = "retl";
997
380
          else if (Features.test(Feature_In64BitModeBit))
998
380
            Mnemonic = "retq";
999
554
          return;
1000
10.5k
        }
1001
10.5k
        break;
1002
42.4k
      case 4:  // 18 strings to match.
1003
42.4k
        switch (Mnemonic[0]) {
1004
42.4k
        
default: break10.4k
;
1005
42.4k
        case 'c':  // 3 strings to match.
1006
1.04k
          switch (Mnemonic[1]) {
1007
1.04k
          
default: break700
;
1008
1.04k
          case 'a':  // 1 string to match.
1009
307
            if (memcmp(Mnemonic.data()+2, "ll", 2) != 0)
1010
0
              break;
1011
307
            if (Features.test(Feature_In16BitModeBit))   // "call"
1012
2
              Mnemonic = "callw";
1013
305
            else if (Features.test(Feature_In32BitModeBit))
1014
85
              Mnemonic = "calll";
1015
220
            else if (Features.test(Feature_In64BitModeBit))
1016
220
              Mnemonic = "callq";
1017
307
            return;
1018
307
          case 'd':  // 1 string to match.
1019
12
            if (memcmp(Mnemonic.data()+2, "qe", 2) != 0)
1020
0
              break;
1021
12
            Mnemonic = "cltq";   // "cdqe"
1022
12
            return;
1023
23
          case 'w':  // 1 string to match.
1024
23
            if (memcmp(Mnemonic.data()+2, "de", 2) != 0)
1025
11
              break;
1026
12
            Mnemonic = "cwtl";   // "cwde"
1027
12
            return;
1028
711
          }
1029
711
          break;
1030
18.0k
        case 'i':  // 1 string to match.
1031
18.0k
          if (memcmp(Mnemonic.data()+1, "ret", 3) != 0)
1032
18.0k
            break;
1033
3
          if (Features.test(Feature_In16BitModeBit))   // "iret"
1034
1
            Mnemonic = "iretw";
1035
2
          else if (Features.test(Feature_Not16BitModeBit))
1036
2
            Mnemonic = "iretl";
1037
3
          return;
1038
6.38k
        case 'l':  // 3 strings to match.
1039
6.38k
          switch (Mnemonic[1]) {
1040
6.38k
          
default: break6.36k
;
1041
6.38k
          case 'g':  // 1 string to match.
1042
13
            if (memcmp(Mnemonic.data()+2, "dt", 2) != 0)
1043
0
              break;
1044
13
            if (Features.test(Feature_In16BitModeBit))   // "lgdt"
1045
4
              Mnemonic = "lgdtw";
1046
9
            else if (Features.test(Feature_In32BitModeBit))
1047
5
              Mnemonic = "lgdtl";
1048
4
            else if (Features.test(Feature_In64BitModeBit))
1049
4
              Mnemonic = "lgdtq";
1050
13
            return;
1051
13
          case 'i':  // 1 string to match.
1052
3
            if (memcmp(Mnemonic.data()+2, "dt", 2) != 0)
1053
0
              break;
1054
3
            if (Features.test(Feature_In16BitModeBit))   // "lidt"
1055
1
              Mnemonic = "lidtw";
1056
2
            else if (Features.test(Feature_In32BitModeBit))
1057
1
              Mnemonic = "lidtl";
1058
1
            else if (Features.test(Feature_In64BitModeBit))
1059
1
              Mnemonic = "lidtq";
1060
3
            return;
1061
10
          case 'r':  // 1 string to match.
1062
10
            if (memcmp(Mnemonic.data()+2, "et", 2) != 0)
1063
0
              break;
1064
10
            if (Features.test(Feature_In16BitModeBit))   // "lret"
1065
3
              Mnemonic = "lretw";
1066
7
            else if (Features.test(Feature_Not16BitModeBit))
1067
7
              Mnemonic = "lretl";
1068
10
            return;
1069
6.36k
          }
1070
6.36k
          break;
1071
6.36k
        case 'p':  // 3 strings to match.
1072
803
          switch (Mnemonic[1]) {
1073
803
          
default: break248
;
1074
803
          case 'o':  // 2 strings to match.
1075
303
            if (Mnemonic[2] != 'p')
1076
0
              break;
1077
303
            switch (Mnemonic[3]) {
1078
303
            
default: break295
;
1079
303
            case 'a':  // 1 string to match.
1080
3
              if (Features.test(Feature_In16BitModeBit))   // "popa"
1081
1
                Mnemonic = "popaw";
1082
2
              else if (Features.test(Feature_In32BitModeBit))
1083
2
                Mnemonic = "popal";
1084
3
              return;
1085
303
            case 'f':  // 1 string to match.
1086
5
              if (Features.test(Feature_In16BitModeBit))   // "popf"
1087
1
                Mnemonic = "popfw";
1088
4
              else if (Features.test(Feature_In32BitModeBit))
1089
3
                Mnemonic = "popfl";
1090
1
              else if (Features.test(Feature_In64BitModeBit))
1091
1
                Mnemonic = "popfq";
1092
5
              return;
1093
295
            }
1094
295
            break;
1095
295
          case 'u':  // 1 string to match.
1096
252
            if (memcmp(Mnemonic.data()+2, "sh", 2) != 0)
1097
0
              break;
1098
252
            if (Features.test(Feature_In16BitModeBit))   // "push"
1099
6
              Mnemonic = "pushw";
1100
246
            else if (Features.test(Feature_In32BitModeBit))
1101
17
              Mnemonic = "pushl";
1102
229
            else if (Features.test(Feature_In64BitModeBit))
1103
229
              Mnemonic = "pushq";
1104
252
            return;
1105
543
          }
1106
543
          break;
1107
2.20k
        case 'r':  // 1 string to match.
1108
2.20k
          if (memcmp(Mnemonic.data()+1, "etn", 3) != 0)
1109
2.19k
            break;
1110
6
          if (Features.test(Feature_In16BitModeBit))   // "retn"
1111
2
            Mnemonic = "retw";
1112
4
          else if (Features.test(Feature_In32BitModeBit))
1113
2
            Mnemonic = "retl";
1114
2
          else if (Features.test(Feature_In64BitModeBit))
1115
2
            Mnemonic = "retq";
1116
6
          return;
1117
3.53k
        case 's':  // 6 strings to match.
1118
3.53k
          switch (Mnemonic[1]) {
1119
3.53k
          
default: break2.99k
;
1120
3.53k
          case 'a':  // 4 strings to match.
1121
540
            if (Mnemonic[2] != 'l')
1122
487
              break;
1123
53
            switch (Mnemonic[3]) {
1124
53
            
default: break14
;
1125
53
            case 'b':  // 1 string to match.
1126
12
              Mnemonic = "shlb";   // "salb"
1127
12
              return;
1128
53
            case 'l':  // 1 string to match.
1129
21
              Mnemonic = "shll";   // "sall"
1130
21
              return;
1131
53
            case 'q':  // 1 string to match.
1132
2
              Mnemonic = "shlq";   // "salq"
1133
2
              return;
1134
53
            case 'w':  // 1 string to match.
1135
4
              Mnemonic = "shlw";   // "salw"
1136
4
              return;
1137
14
            }
1138
14
            break;
1139
14
          case 'g':  // 1 string to match.
1140
3
            if (memcmp(Mnemonic.data()+2, "dt", 2) != 0)
1141
0
              break;
1142
3
            if (Features.test(Feature_In16BitModeBit))   // "sgdt"
1143
1
              Mnemonic = "sgdtw";
1144
2
            else if (Features.test(Feature_In32BitModeBit))
1145
1
              Mnemonic = "sgdtl";
1146
1
            else if (Features.test(Feature_In64BitModeBit))
1147
1
              Mnemonic = "sgdtq";
1148
3
            return;
1149
3
          case 'i':  // 1 string to match.
1150
3
            if (memcmp(Mnemonic.data()+2, "dt", 2) != 0)
1151
0
              break;
1152
3
            if (Features.test(Feature_In16BitModeBit))   // "sidt"
1153
1
              Mnemonic = "sidtw";
1154
2
            else if (Features.test(Feature_In32BitModeBit))
1155
1
              Mnemonic = "sidtl";
1156
1
            else if (Features.test(Feature_In64BitModeBit))
1157
1
              Mnemonic = "sidtq";
1158
3
            return;
1159
3.49k
          }
1160
3.49k
          break;
1161
3.49k
        case 'u':  // 1 string to match.
1162
4
          if (memcmp(Mnemonic.data()+1, "d2a", 3) != 0)
1163
2
            break;
1164
2
          Mnemonic = "ud2";  // "ud2a"
1165
2
          return;
1166
41.8k
        }
1167
41.8k
        break;
1168
41.8k
      case 5:  // 9 strings to match.
1169
15.2k
        switch (Mnemonic[0]) {
1170
15.2k
        
default: break6.11k
;
1171
15.2k
        case 'f':  // 1 string to match.
1172
926
          if (memcmp(Mnemonic.data()+1, "ildq", 4) != 0)
1173
920
            break;
1174
6
          Mnemonic = "fildll";   // "fildq"
1175
6
          return;
1176
5.42k
        case 'p':  // 3 strings to match.
1177
5.42k
          switch (Mnemonic[1]) {
1178
5.42k
          
default: break5.04k
;
1179
5.42k
          case 'o':  // 1 string to match.
1180
38
            if (memcmp(Mnemonic.data()+2, "pfd", 3) != 0)
1181
36
              break;
1182
2
            Mnemonic = "popfl";  // "popfd"
1183
2
            return;
1184
342
          case 'u':  // 2 strings to match.
1185
342
            if (memcmp(Mnemonic.data()+2, "sh", 2) != 0)
1186
0
              break;
1187
342
            switch (Mnemonic[4]) {
1188
342
            
default: break336
;
1189
342
            case 'a':  // 1 string to match.
1190
2
              if (Features.test(Feature_In16BitModeBit))   // "pusha"
1191
1
                Mnemonic = "pushaw";
1192
1
              else if (Features.test(Feature_In32BitModeBit))
1193
1
                Mnemonic = "pushal";
1194
2
              return;
1195
342
            case 'f':  // 1 string to match.
1196
4
              if (Features.test(Feature_In16BitModeBit))   // "pushf"
1197
1
                Mnemonic = "pushfw";
1198
3
              else if (Features.test(Feature_In32BitModeBit))
1199
2
                Mnemonic = "pushfl";
1200
1
              else if (Features.test(Feature_In64BitModeBit))
1201
1
                Mnemonic = "pushfq";
1202
4
              return;
1203
336
            }
1204
336
            break;
1205
5.41k
          }
1206
5.41k
          break;
1207
5.41k
        case 's':  // 4 strings to match.
1208
1.52k
          if (memcmp(Mnemonic.data()+1, "mov", 3) != 0)
1209
1.52k
            break;
1210
4
          switch (Mnemonic[4]) {
1211
4
          
default: break0
;
1212
4
          case 'b':  // 1 string to match.
1213
1
            Mnemonic = "movsb";  // "smovb"
1214
1
            return;
1215
4
          case 'l':  // 1 string to match.
1216
1
            Mnemonic = "movsl";  // "smovl"
1217
1
            return;
1218
4
          case 'q':  // 1 string to match.
1219
1
            Mnemonic = "movsq";  // "smovq"
1220
1
            return;
1221
4
          case 'w':  // 1 string to match.
1222
1
            Mnemonic = "movsw";  // "smovw"
1223
1
            return;
1224
0
          }
1225
0
          break;
1226
1.29k
        case 'v':  // 1 string to match.
1227
1.29k
          if (memcmp(Mnemonic.data()+1, "errw", 4) != 0)
1228
1.29k
            break;
1229
2
          Mnemonic = "verr";   // "verrw"
1230
2
          return;
1231
15.2k
        }
1232
15.2k
        break;
1233
23.8k
      case 6:  // 15 strings to match.
1234
23.8k
        switch (Mnemonic[0]) {
1235
23.8k
        
default: break18.5k
;
1236
23.8k
        case 'c':  // 6 strings to match.
1237
881
          if (memcmp(Mnemonic.data()+1, "mov", 3) != 0)
1238
312
            break;
1239
569
          switch (Mnemonic[4]) {
1240
569
          
default: break565
;
1241
569
          case 'c':  // 3 strings to match.
1242
2
            switch (Mnemonic[5]) {
1243
2
            
default: break0
;
1244
2
            case 'l':  // 1 string to match.
1245
2
              Mnemonic = "cmovbl";   // "cmovcl"
1246
2
              return;
1247
2
            case 'q':  // 1 string to match.
1248
0
              Mnemonic = "cmovbq";   // "cmovcq"
1249
0
              return;
1250
2
            case 'w':  // 1 string to match.
1251
0
              Mnemonic = "cmovbw";   // "cmovcw"
1252
0
              return;
1253
0
            }
1254
0
            break;
1255
2
          case 'z':  // 3 strings to match.
1256
2
            switch (Mnemonic[5]) {
1257
2
            
default: break0
;
1258
2
            case 'l':  // 1 string to match.
1259
2
              Mnemonic = "cmovel";   // "cmovzl"
1260
2
              return;
1261
2
            case 'q':  // 1 string to match.
1262
0
              Mnemonic = "cmoveq";   // "cmovzq"
1263
0
              return;
1264
2
            case 'w':  // 1 string to match.
1265
0
              Mnemonic = "cmovew";   // "cmovzw"
1266
0
              return;
1267
0
            }
1268
0
            break;
1269
565
          }
1270
565
          break;
1271
1.05k
        case 'f':  // 4 strings to match.
1272
1.05k
          switch (Mnemonic[1]) {
1273
1.05k
          
default: break483
;
1274
1.05k
          case 'c':  // 2 strings to match.
1275
135
            if (memcmp(Mnemonic.data()+2, "mov", 3) != 0)
1276
86
              break;
1277
49
            switch (Mnemonic[5]) {
1278
49
            
default: break48
;
1279
49
            case 'a':  // 1 string to match.
1280
1
              Mnemonic = "fcmovnbe";   // "fcmova"
1281
1
              return;
1282
49
            case 'z':  // 1 string to match.
1283
0
              Mnemonic = "fcmove";   // "fcmovz"
1284
0
              return;
1285
48
            }
1286
48
            break;
1287
352
          case 'i':  // 1 string to match.
1288
352
            if (memcmp(Mnemonic.data()+2, "stpq", 4) != 0)
1289
352
              break;
1290
0
            Mnemonic = "fistpll";  // "fistpq"
1291
0
            return;
1292
87
          case 'l':  // 1 string to match.
1293
87
            if (memcmp(Mnemonic.data()+2, "dcww", 4) != 0)
1294
85
              break;
1295
2
            Mnemonic = "fldcw";  // "fldcww"
1296
2
            return;
1297
1.05k
          }
1298
1.05k
          break;
1299
1.05k
        case 'l':  // 2 strings to match.
1300
258
          if (memcmp(Mnemonic.data()+1, "eave", 4) != 0)
1301
253
            break;
1302
5
          switch (Mnemonic[5]) {
1303
5
          
default: break0
;
1304
5
          case 'l':  // 1 string to match.
1305
2
            if (Features.test(Feature_Not64BitModeBit))  // "leavel"
1306
2
              Mnemonic = "leave";
1307
2
            return;
1308
5
          case 'q':  // 1 string to match.
1309
3
            if (Features.test(Feature_In64BitModeBit))  // "leaveq"
1310
3
              Mnemonic = "leave";
1311
3
            return;
1312
0
          }
1313
0
          break;
1314
2.77k
        case 'p':  // 1 string to match.
1315
2.77k
          if (memcmp(Mnemonic.data()+1, "ushfd", 5) != 0)
1316
2.76k
            break;
1317
2
          Mnemonic = "pushfl";   // "pushfd"
1318
2
          return;
1319
350
        case 's':  // 1 string to match.
1320
350
          if (memcmp(Mnemonic.data()+1, "ysret", 5) != 0)
1321
347
            break;
1322
3
          Mnemonic = "sysretl";  // "sysret"
1323
3
          return;
1324
71
        case 'x':  // 1 string to match.
1325
71
          if (memcmp(Mnemonic.data()+1, "saveq", 5) != 0)
1326
71
            break;
1327
0
          Mnemonic = "xsave64";  // "xsaveq"
1328
0
          return;
1329
23.8k
        }
1330
23.8k
        break;
1331
23.8k
      case 7:  // 34 strings to match.
1332
18.2k
        switch (Mnemonic[0]) {
1333
18.2k
        
default: break16.9k
;
1334
18.2k
        case 'c':  // 24 strings to match.
1335
635
          if (memcmp(Mnemonic.data()+1, "mov", 3) != 0)
1336
32
            break;
1337
603
          switch (Mnemonic[4]) {
1338
603
          
default: break290
;
1339
603
          case 'n':  // 18 strings to match.
1340
313
            switch (Mnemonic[5]) {
1341
313
            
default: break284
;
1342
313
            case 'a':  // 3 strings to match.
1343
4
              switch (Mnemonic[6]) {
1344
4
              
default: break2
;
1345
4
              case 'l':  // 1 string to match.
1346
2
                Mnemonic = "cmovbel";  // "cmovnal"
1347
2
                return;
1348
4
              case 'q':  // 1 string to match.
1349
0
                Mnemonic = "cmovbeq";  // "cmovnaq"
1350
0
                return;
1351
4
              case 'w':  // 1 string to match.
1352
0
                Mnemonic = "cmovbew";  // "cmovnaw"
1353
0
                return;
1354
2
              }
1355
2
              break;
1356
2
            case 'b':  // 3 strings to match.
1357
2
              switch (Mnemonic[6]) {
1358
2
              
default: break0
;
1359
2
              case 'l':  // 1 string to match.
1360
2
                Mnemonic = "cmovael";  // "cmovnbl"
1361
2
                return;
1362
2
              case 'q':  // 1 string to match.
1363
0
                Mnemonic = "cmovaeq";  // "cmovnbq"
1364
0
                return;
1365
2
              case 'w':  // 1 string to match.
1366
0
                Mnemonic = "cmovaew";  // "cmovnbw"
1367
0
                return;
1368
0
              }
1369
0
              break;
1370
2
            case 'c':  // 3 strings to match.
1371
2
              switch (Mnemonic[6]) {
1372
2
              
default: break0
;
1373
2
              case 'l':  // 1 string to match.
1374
2
                Mnemonic = "cmovael";  // "cmovncl"
1375
2
                return;
1376
2
              case 'q':  // 1 string to match.
1377
0
                Mnemonic = "cmovaeq";  // "cmovncq"
1378
0
                return;
1379
2
              case 'w':  // 1 string to match.
1380
0
                Mnemonic = "cmovaew";  // "cmovncw"
1381
0
                return;
1382
0
              }
1383
0
              break;
1384
4
            case 'g':  // 3 strings to match.
1385
4
              switch (Mnemonic[6]) {
1386
4
              
default: break0
;
1387
4
              case 'l':  // 1 string to match.
1388
4
                Mnemonic = "cmovlel";  // "cmovngl"
1389
4
                return;
1390
4
              case 'q':  // 1 string to match.
1391
0
                Mnemonic = "cmovleq";  // "cmovngq"
1392
0
                return;
1393
4
              case 'w':  // 1 string to match.
1394
0
                Mnemonic = "cmovlew";  // "cmovngw"
1395
0
                return;
1396
0
              }
1397
0
              break;
1398
10
            case 'l':  // 3 strings to match.
1399
10
              switch (Mnemonic[6]) {
1400
10
              
default: break2
;
1401
10
              case 'l':  // 1 string to match.
1402
4
                Mnemonic = "cmovgel";  // "cmovnll"
1403
4
                return;
1404
10
              case 'q':  // 1 string to match.
1405
2
                Mnemonic = "cmovgeq";  // "cmovnlq"
1406
2
                return;
1407
10
              case 'w':  // 1 string to match.
1408
2
                Mnemonic = "cmovgew";  // "cmovnlw"
1409
2
                return;
1410
2
              }
1411
2
              break;
1412
7
            case 'z':  // 3 strings to match.
1413
7
              switch (Mnemonic[6]) {
1414
7
              
default: break1
;
1415
7
              case 'l':  // 1 string to match.
1416
3
                Mnemonic = "cmovnel";  // "cmovnzl"
1417
3
                return;
1418
7
              case 'q':  // 1 string to match.
1419
2
                Mnemonic = "cmovneq";  // "cmovnzq"
1420
2
                return;
1421
7
              case 'w':  // 1 string to match.
1422
1
                Mnemonic = "cmovnew";  // "cmovnzw"
1423
1
                return;
1424
1
              }
1425
1
              break;
1426
289
            }
1427
289
            break;
1428
289
          case 'p':  // 6 strings to match.
1429
0
            switch (Mnemonic[5]) {
1430
0
            default: break;
1431
0
            case 'e':  // 3 strings to match.
1432
0
              switch (Mnemonic[6]) {
1433
0
              default: break;
1434
0
              case 'l':  // 1 string to match.
1435
0
                Mnemonic = "cmovpl";   // "cmovpel"
1436
0
                return;
1437
0
              case 'q':  // 1 string to match.
1438
0
                Mnemonic = "cmovpq";   // "cmovpeq"
1439
0
                return;
1440
0
              case 'w':  // 1 string to match.
1441
0
                Mnemonic = "cmovpw";   // "cmovpew"
1442
0
                return;
1443
0
              }
1444
0
              break;
1445
0
            case 'o':  // 3 strings to match.
1446
0
              switch (Mnemonic[6]) {
1447
0
              default: break;
1448
0
              case 'l':  // 1 string to match.
1449
0
                Mnemonic = "cmovnpl";  // "cmovpol"
1450
0
                return;
1451
0
              case 'q':  // 1 string to match.
1452
0
                Mnemonic = "cmovnpq";  // "cmovpoq"
1453
0
                return;
1454
0
              case 'w':  // 1 string to match.
1455
0
                Mnemonic = "cmovnpw";  // "cmovpow"
1456
0
                return;
1457
0
              }
1458
0
              break;
1459
0
            }
1460
0
            break;
1461
579
          }
1462
579
          break;
1463
579
        case 'f':  // 6 strings to match.
1464
497
          switch (Mnemonic[1]) {
1465
497
          
default: break97
;
1466
497
          case 'c':  // 2 strings to match.
1467
66
            if (memcmp(Mnemonic.data()+2, "mov", 3) != 0)
1468
0
              break;
1469
66
            switch (Mnemonic[5]) {
1470
66
            
default: break16
;
1471
66
            case 'a':  // 1 string to match.
1472
1
              if (Mnemonic[6] != 'e')
1473
0
                break;
1474
1
              Mnemonic = "fcmovnb";  // "fcmovae"
1475
1
              return;
1476
49
            case 'n':  // 1 string to match.
1477
49
              if (Mnemonic[6] != 'a')
1478
48
                break;
1479
1
              Mnemonic = "fcmovbe";  // "fcmovna"
1480
1
              return;
1481
64
            }
1482
64
            break;
1483
258
          case 'i':  // 1 string to match.
1484
258
            if (memcmp(Mnemonic.data()+2, "sttpq", 5) != 0)
1485
258
              break;
1486
0
            Mnemonic = "fisttpll";   // "fisttpq"
1487
0
            return;
1488
29
          case 'n':  // 2 strings to match.
1489
29
            if (memcmp(Mnemonic.data()+2, "st", 2) != 0)
1490
0
              break;
1491
29
            switch (Mnemonic[4]) {
1492
29
            
default: break25
;
1493
29
            case 'c':  // 1 string to match.
1494
2
              if (memcmp(Mnemonic.data()+5, "ww", 2) != 0)
1495
0
                break;
1496
2
              Mnemonic = "fnstcw";   // "fnstcww"
1497
2
              return;
1498
2
            case 's':  // 1 string to match.
1499
2
              if (memcmp(Mnemonic.data()+5, "ww", 2) != 0)
1500
0
                break;
1501
2
              Mnemonic = "fnstsw";   // "fnstsww"
1502
2
              return;
1503
25
            }
1504
25
            break;
1505
47
          case 'x':  // 1 string to match.
1506
47
            if (memcmp(Mnemonic.data()+2, "saveq", 5) != 0)
1507
46
              break;
1508
1
            Mnemonic = "fxsave64";   // "fxsaveq"
1509
1
            return;
1510
490
          }
1511
490
          break;
1512
490
        case 's':  // 1 string to match.
1513
67
          if (memcmp(Mnemonic.data()+1, "ysexit", 6) != 0)
1514
64
            break;
1515
3
          Mnemonic = "sysexitl";   // "sysexit"
1516
3
          return;
1517
26
        case 'x':  // 3 strings to match.
1518
26
          switch (Mnemonic[1]) {
1519
26
          
default: break0
;
1520
26
          case 'r':  // 1 string to match.
1521
20
            if (memcmp(Mnemonic.data()+2, "storq", 5) != 0)
1522
20
              break;
1523
0
            Mnemonic = "xrstor64";   // "xrstorq"
1524
0
            return;
1525
6
          case 's':  // 2 strings to match.
1526
6
            if (memcmp(Mnemonic.data()+2, "ave", 3) != 0)
1527
0
              break;
1528
6
            switch (Mnemonic[5]) {
1529
6
            default: break;
1530
6
            case 'c':  // 1 string to match.
1531
0
              if (Mnemonic[6] != 'q')
1532
0
                break;
1533
0
              Mnemonic = "xsavec64";   // "xsavecq"
1534
0
              return;
1535
0
            case 's':  // 1 string to match.
1536
0
              if (Mnemonic[6] != 'q')
1537
0
                break;
1538
0
              Mnemonic = "xsaves64";   // "xsavesq"
1539
0
              return;
1540
6
            }
1541
6
            break;
1542
26
          }
1543
26
          break;
1544
18.1k
        }
1545
18.1k
        break;
1546
18.1k
      case 8:  // 15 strings to match.
1547
10.5k
        switch (Mnemonic[0]) {
1548
10.5k
        
default: break9.47k
;
1549
10.5k
        case 'c':  // 12 strings to match.
1550
960
          if (memcmp(Mnemonic.data()+1, "movn", 4) != 0)
1551
946
            break;
1552
14
          switch (Mnemonic[5]) {
1553
14
          
default: break0
;
1554
14
          case 'a':  // 3 strings to match.
1555
8
            if (Mnemonic[6] != 'e')
1556
0
              break;
1557
8
            switch (Mnemonic[7]) {
1558
8
            
default: break2
;
1559
8
            case 'l':  // 1 string to match.
1560
2
              Mnemonic = "cmovbl";   // "cmovnael"
1561
2
              return;
1562
8
            case 'q':  // 1 string to match.
1563
2
              Mnemonic = "cmovbq";   // "cmovnaeq"
1564
2
              return;
1565
8
            case 'w':  // 1 string to match.
1566
2
              Mnemonic = "cmovbw";   // "cmovnaew"
1567
2
              return;
1568
2
            }
1569
2
            break;
1570
2
          case 'b':  // 3 strings to match.
1571
2
            if (Mnemonic[6] != 'e')
1572
0
              break;
1573
2
            switch (Mnemonic[7]) {
1574
2
            
default: break0
;
1575
2
            case 'l':  // 1 string to match.
1576
2
              Mnemonic = "cmoval";   // "cmovnbel"
1577
2
              return;
1578
2
            case 'q':  // 1 string to match.
1579
0
              Mnemonic = "cmovaq";   // "cmovnbeq"
1580
0
              return;
1581
2
            case 'w':  // 1 string to match.
1582
0
              Mnemonic = "cmovaw";   // "cmovnbew"
1583
0
              return;
1584
0
            }
1585
0
            break;
1586
2
          case 'g':  // 3 strings to match.
1587
2
            if (Mnemonic[6] != 'e')
1588
0
              break;
1589
2
            switch (Mnemonic[7]) {
1590
2
            
default: break0
;
1591
2
            case 'l':  // 1 string to match.
1592
2
              Mnemonic = "cmovll";   // "cmovngel"
1593
2
              return;
1594
2
            case 'q':  // 1 string to match.
1595
0
              Mnemonic = "cmovlq";   // "cmovngeq"
1596
0
              return;
1597
2
            case 'w':  // 1 string to match.
1598
0
              Mnemonic = "cmovlw";   // "cmovngew"
1599
0
              return;
1600
0
            }
1601
0
            break;
1602
2
          case 'l':  // 3 strings to match.
1603
2
            if (Mnemonic[6] != 'e')
1604
0
              break;
1605
2
            switch (Mnemonic[7]) {
1606
2
            
default: break0
;
1607
2
            case 'l':  // 1 string to match.
1608
2
              Mnemonic = "cmovgl";   // "cmovnlel"
1609
2
              return;
1610
2
            case 'q':  // 1 string to match.
1611
0
              Mnemonic = "cmovgq";   // "cmovnleq"
1612
0
              return;
1613
2
            case 'w':  // 1 string to match.
1614
0
              Mnemonic = "cmovgw";   // "cmovnlew"
1615
0
              return;
1616
0
            }
1617
0
            break;
1618
2
          }
1619
2
          break;
1620
48
        case 'f':  // 2 strings to match.
1621
48
          switch (Mnemonic[1]) {
1622
48
          
default: break23
;
1623
48
          case 'c':  // 1 string to match.
1624
17
            if (memcmp(Mnemonic.data()+2, "movnae", 6) != 0)
1625
16
              break;
1626
1
            Mnemonic = "fcmovb";   // "fcmovnae"
1627
1
            return;
1628
8
          case 'x':  // 1 string to match.
1629
8
            if (memcmp(Mnemonic.data()+2, "rstorq", 6) != 0)
1630
7
              break;
1631
1
            Mnemonic = "fxrstor64";  // "fxrstorq"
1632
1
            return;
1633
46
          }
1634
46
          break;
1635
46
        case 'x':  // 1 string to match.
1636
42
          if (memcmp(Mnemonic.data()+1, "rstorsq", 7) != 0)
1637
42
            break;
1638
0
          Mnemonic = "xrstors64";  // "xrstorsq"
1639
0
          return;
1640
10.5k
        }
1641
10.5k
        break;
1642
14.0k
      case 9:  // 1 string to match.
1643
14.0k
        if (memcmp(Mnemonic.data()+0, "xsaveoptq", 9) != 0)
1644
14.0k
          break;
1645
0
        Mnemonic = "xsaveopt64";   // "xsaveoptq"
1646
0
        return;
1647
159k
      }
1648
159k
    break;
1649
159k
    case 1:
1650
13.8k
      switch (Mnemonic.size()) {
1651
13.8k
      
default: break6.84k
;
1652
13.8k
      case 3:  // 1 string to match.
1653
2.97k
        if (memcmp(Mnemonic.data()+0, "sal", 3) != 0)
1654
2.97k
          break;
1655
1
        Mnemonic = "shl";  // "sal"
1656
1
        return;
1657
400
      case 4:  // 7 strings to match.
1658
400
        switch (Mnemonic[0]) {
1659
400
        
default: break263
;
1660
400
        case 'l':  // 2 strings to match.
1661
41
          switch (Mnemonic[1]) {
1662
41
          
default: break9
;
1663
41
          case 'g':  // 1 string to match.
1664
16
            if (memcmp(Mnemonic.data()+2, "dt", 2) != 0)
1665
0
              break;
1666
16
            if (Features.test(Feature_In16BitModeBit))   // "lgdt"
1667
8
              Mnemonic = "lgdtw";
1668
8
            else if (Features.test(Feature_In32BitModeBit))
1669
8
              Mnemonic = "lgdtd";
1670
16
            return;
1671
16
          case 'i':  // 1 string to match.
1672
16
            if (memcmp(Mnemonic.data()+2, "dt", 2) != 0)
1673
0
              break;
1674
16
            if (Features.test(Feature_In16BitModeBit))   // "lidt"
1675
8
              Mnemonic = "lidtw";
1676
8
            else if (Features.test(Feature_In32BitModeBit))
1677
8
              Mnemonic = "lidtd";
1678
16
            return;
1679
9
          }
1680
9
          break;
1681
17
        case 'p':  // 2 strings to match.
1682
17
          if (memcmp(Mnemonic.data()+1, "op", 2) != 0)
1683
13
            break;
1684
4
          switch (Mnemonic[3]) {
1685
4
          
default: break0
;
1686
4
          case 'a':  // 1 string to match.
1687
3
            if (Features.test(Feature_In16BitModeBit))   // "popa"
1688
0
              Mnemonic = "popaw";
1689
3
            else if (Features.test(Feature_In32BitModeBit))
1690
3
              Mnemonic = "popal";
1691
3
            return;
1692
4
          case 'f':  // 1 string to match.
1693
1
            if (Features.test(Feature_In64BitModeBit))  // "popf"
1694
1
              Mnemonic = "popfq";
1695
1
            return;
1696
0
          }
1697
0
          break;
1698
3
        case 'r':  // 1 string to match.
1699
3
          if (memcmp(Mnemonic.data()+1, "etn", 3) != 0)
1700
3
            break;
1701
0
          Mnemonic = "ret";  // "retn"
1702
0
          return;
1703
76
        case 's':  // 2 strings to match.
1704
76
          switch (Mnemonic[1]) {
1705
76
          
default: break43
;
1706
76
          case 'g':  // 1 string to match.
1707
16
            if (memcmp(Mnemonic.data()+2, "dt", 2) != 0)
1708
0
              break;
1709
16
            if (Features.test(Feature_In16BitModeBit))   // "sgdt"
1710
8
              Mnemonic = "sgdtw";
1711
8
            else if (Features.test(Feature_In32BitModeBit))
1712
8
              Mnemonic = "sgdtd";
1713
16
            return;
1714
17
          case 'i':  // 1 string to match.
1715
17
            if (memcmp(Mnemonic.data()+2, "dt", 2) != 0)
1716
0
              break;
1717
17
            if (Features.test(Feature_In16BitModeBit))   // "sidt"
1718
8
              Mnemonic = "sidtw";
1719
9
            else if (Features.test(Feature_In32BitModeBit))
1720
8
              Mnemonic = "sidtd";
1721
17
            return;
1722
43
          }
1723
43
          break;
1724
331
        }
1725
331
        break;
1726
331
      case 5:  // 6 strings to match.
1727
299
        switch (Mnemonic[0]) {
1728
299
        
default: break252
;
1729
299
        case 'c':  // 2 strings to match.
1730
38
          if (memcmp(Mnemonic.data()+1, "mov", 3) != 0)
1731
36
            break;
1732
2
          switch (Mnemonic[4]) {
1733
2
          
default: break0
;
1734
2
          case 'c':  // 1 string to match.
1735
1
            Mnemonic = "cmovb";  // "cmovc"
1736
1
            return;
1737
2
          case 'z':  // 1 string to match.
1738
1
            Mnemonic = "cmove";  // "cmovz"
1739
1
            return;
1740
0
          }
1741
0
          break;
1742
9
        case 'p':  // 4 strings to match.
1743
9
          switch (Mnemonic[1]) {
1744
9
          
default: break0
;
1745
9
          case 'o':  // 2 strings to match.
1746
5
            if (Mnemonic[2] != 'p')
1747
0
              break;
1748
5
            switch (Mnemonic[3]) {
1749
5
            
default: break0
;
1750
5
            case 'a':  // 1 string to match.
1751
3
              if (Mnemonic[4] != 'd')
1752
0
                break;
1753
3
              if (Features.test(Feature_Not64BitModeBit))  // "popad"
1754
3
                Mnemonic = "popal";
1755
3
              return;
1756
3
            case 'f':  // 1 string to match.
1757
2
              if (Mnemonic[4] != 'w')
1758
1
                break;
1759
1
              if (Features.test(Feature_In32BitModeBit))   // "popfw"
1760
0
                Mnemonic = "popf";
1761
1
              else if (Features.test(Feature_In64BitModeBit))
1762
1
                Mnemonic = "popf";
1763
1
              return;
1764
1
            }
1765
1
            break;
1766
4
          case 'u':  // 2 strings to match.
1767
4
            if (memcmp(Mnemonic.data()+2, "sh", 2) != 0)
1768
0
              break;
1769
4
            switch (Mnemonic[4]) {
1770
4
            
default: break0
;
1771
4
            case 'a':  // 1 string to match.
1772
3
              if (Features.test(Feature_In16BitModeBit))   // "pusha"
1773
0
                Mnemonic = "pushaw";
1774
3
              else if (Features.test(Feature_In32BitModeBit))
1775
3
                Mnemonic = "pushal";
1776
3
              return;
1777
4
            case 'f':  // 1 string to match.
1778
1
              if (Features.test(Feature_In64BitModeBit))  // "pushf"
1779
1
                Mnemonic = "pushfq";
1780
1
              return;
1781
0
            }
1782
0
            break;
1783
1
          }
1784
1
          break;
1785
289
        }
1786
289
        break;
1787
1.94k
      case 6:  // 10 strings to match.
1788
1.94k
        switch (Mnemonic[0]) {
1789
1.94k
        
default: break1.93k
;
1790
1.94k
        case 'c':  // 8 strings to match.
1791
10
          if (memcmp(Mnemonic.data()+1, "mov", 3) != 0)
1792
2
            break;
1793
8
          switch (Mnemonic[4]) {
1794
8
          
default: break0
;
1795
8
          case 'n':  // 6 strings to match.
1796
6
            switch (Mnemonic[5]) {
1797
6
            
default: break0
;
1798
6
            case 'a':  // 1 string to match.
1799
1
              Mnemonic = "cmovbe";   // "cmovna"
1800
1
              return;
1801
6
            case 'b':  // 1 string to match.
1802
1
              Mnemonic = "cmovae";   // "cmovnb"
1803
1
              return;
1804
6
            case 'c':  // 1 string to match.
1805
1
              Mnemonic = "cmovae";   // "cmovnc"
1806
1
              return;
1807
6
            case 'g':  // 1 string to match.
1808
1
              Mnemonic = "cmovle";   // "cmovng"
1809
1
              return;
1810
6
            case 'l':  // 1 string to match.
1811
1
              Mnemonic = "cmovge";   // "cmovnl"
1812
1
              return;
1813
6
            case 'z':  // 1 string to match.
1814
1
              Mnemonic = "cmovne";   // "cmovnz"
1815
1
              return;
1816
0
            }
1817
0
            break;
1818
2
          case 'p':  // 2 strings to match.
1819
2
            switch (Mnemonic[5]) {
1820
2
            
default: break0
;
1821
2
            case 'e':  // 1 string to match.
1822
1
              Mnemonic = "cmovp";  // "cmovpe"
1823
1
              return;
1824
2
            case 'o':  // 1 string to match.
1825
1
              Mnemonic = "cmovnp";   // "cmovpo"
1826
1
              return;
1827
0
            }
1828
0
            break;
1829
0
          }
1830
0
          break;
1831
5
        case 'p':  // 2 strings to match.
1832
5
          if (memcmp(Mnemonic.data()+1, "ush", 3) != 0)
1833
1
            break;
1834
4
          switch (Mnemonic[4]) {
1835
4
          
default: break0
;
1836
4
          case 'a':  // 1 string to match.
1837
3
            if (Mnemonic[5] != 'd')
1838
0
              break;
1839
3
            if (Features.test(Feature_Not64BitModeBit))  // "pushad"
1840
3
              Mnemonic = "pushal";
1841
3
            return;
1842
3
          case 'f':  // 1 string to match.
1843
1
            if (Mnemonic[5] != 'w')
1844
0
              break;
1845
1
            if (Features.test(Feature_In32BitModeBit))   // "pushfw"
1846
0
              Mnemonic = "pushf";
1847
1
            else if (Features.test(Feature_In64BitModeBit))
1848
1
              Mnemonic = "pushf";
1849
1
            return;
1850
0
          }
1851
0
          break;
1852
1.93k
        }
1853
1.93k
        break;
1854
1.93k
      case 7:  // 6 strings to match.
1855
1.42k
        switch (Mnemonic[0]) {
1856
1.42k
        
default: break1.42k
;
1857
1.42k
        case 'a':  // 1 string to match.
1858
1
          if (memcmp(Mnemonic.data()+1, "cquire", 6) != 0)
1859
0
            break;
1860
1
          Mnemonic = "xacquire";   // "acquire"
1861
1
          return;
1862
4
        case 'c':  // 4 strings to match.
1863
4
          if (memcmp(Mnemonic.data()+1, "movn", 4) != 0)
1864
0
            break;
1865
4
          switch (Mnemonic[5]) {
1866
4
          
default: break0
;
1867
4
          case 'a':  // 1 string to match.
1868
1
            if (Mnemonic[6] != 'e')
1869
0
              break;
1870
1
            Mnemonic = "cmovb";  // "cmovnae"
1871
1
            return;
1872
1
          case 'b':  // 1 string to match.
1873
1
            if (Mnemonic[6] != 'e')
1874
0
              break;
1875
1
            Mnemonic = "cmova";  // "cmovnbe"
1876
1
            return;
1877
1
          case 'g':  // 1 string to match.
1878
1
            if (Mnemonic[6] != 'e')
1879
0
              break;
1880
1
            Mnemonic = "cmovl";  // "cmovnge"
1881
1
            return;
1882
1
          case 'l':  // 1 string to match.
1883
1
            if (Mnemonic[6] != 'e')
1884
0
              break;
1885
1
            Mnemonic = "cmovg";  // "cmovnle"
1886
1
            return;
1887
0
          }
1888
0
          break;
1889
1
        case 'r':  // 1 string to match.
1890
1
          if (memcmp(Mnemonic.data()+1, "elease", 6) != 0)
1891
0
            break;
1892
1
          Mnemonic = "xrelease";   // "release"
1893
1
          return;
1894
1.42k
        }
1895
1.42k
        break;
1896
13.7k
      }
1897
13.7k
    break;
1898
172k
  }
1899
172k
  switch (Mnemonic.size()) {
1900
172k
  
default: break56.1k
;
1901
172k
  case 2:  // 2 strings to match.
1902
207
    if (Mnemonic[0] != 'j')
1903
36
      break;
1904
171
    switch (Mnemonic[1]) {
1905
171
    
default: break131
;
1906
171
    case 'c':  // 1 string to match.
1907
10
      Mnemonic = "jb";   // "jc"
1908
10
      return;
1909
171
    case 'z':  // 1 string to match.
1910
30
      Mnemonic = "je";   // "jz"
1911
30
      return;
1912
131
    }
1913
131
    break;
1914
13.5k
  case 3:  // 8 strings to match.
1915
13.5k
    if (Mnemonic[0] != 'j')
1916
13.1k
      break;
1917
424
    switch (Mnemonic[1]) {
1918
424
    
default: break324
;
1919
424
    case 'n':  // 6 strings to match.
1920
98
      switch (Mnemonic[2]) {
1921
98
      
default: break65
;
1922
98
      case 'a':  // 1 string to match.
1923
1
        Mnemonic = "jbe";  // "jna"
1924
1
        return;
1925
98
      case 'b':  // 1 string to match.
1926
1
        Mnemonic = "jae";  // "jnb"
1927
1
        return;
1928
98
      case 'c':  // 1 string to match.
1929
13
        Mnemonic = "jae";  // "jnc"
1930
13
        return;
1931
98
      case 'g':  // 1 string to match.
1932
1
        Mnemonic = "jle";  // "jng"
1933
1
        return;
1934
98
      case 'l':  // 1 string to match.
1935
1
        Mnemonic = "jge";  // "jnl"
1936
1
        return;
1937
98
      case 'z':  // 1 string to match.
1938
16
        Mnemonic = "jne";  // "jnz"
1939
16
        return;
1940
65
      }
1941
65
      break;
1942
65
    case 'p':  // 2 strings to match.
1943
2
      switch (Mnemonic[2]) {
1944
2
      
default: break0
;
1945
2
      case 'e':  // 1 string to match.
1946
1
        Mnemonic = "jp";   // "jpe"
1947
1
        return;
1948
2
      case 'o':  // 1 string to match.
1949
1
        Mnemonic = "jnp";  // "jpo"
1950
1
        return;
1951
0
      }
1952
0
      break;
1953
389
    }
1954
389
    break;
1955
42.1k
  case 4:  // 8 strings to match.
1956
42.1k
    switch (Mnemonic[0]) {
1957
42.1k
    
default: break36.3k
;
1958
42.1k
    case 'j':  // 4 strings to match.
1959
52
      if (Mnemonic[1] != 'n')
1960
48
        break;
1961
4
      switch (Mnemonic[2]) {
1962
4
      
default: break0
;
1963
4
      case 'a':  // 1 string to match.
1964
1
        if (Mnemonic[3] != 'e')
1965
0
          break;
1966
1
        Mnemonic = "jb";   // "jnae"
1967
1
        return;
1968
1
      case 'b':  // 1 string to match.
1969
1
        if (Mnemonic[3] != 'e')
1970
0
          break;
1971
1
        Mnemonic = "ja";   // "jnbe"
1972
1
        return;
1973
1
      case 'g':  // 1 string to match.
1974
1
        if (Mnemonic[3] != 'e')
1975
0
          break;
1976
1
        Mnemonic = "jl";   // "jnge"
1977
1
        return;
1978
1
      case 'l':  // 1 string to match.
1979
1
        if (Mnemonic[3] != 'e')
1980
0
          break;
1981
1
        Mnemonic = "jg";   // "jnle"
1982
1
        return;
1983
0
      }
1984
0
      break;
1985
2.20k
    case 'r':  // 2 strings to match.
1986
2.20k
      if (memcmp(Mnemonic.data()+1, "ep", 2) != 0)
1987
2.20k
        break;
1988
2
      switch (Mnemonic[3]) {
1989
2
      
default: break0
;
1990
2
      case 'e':  // 1 string to match.
1991
1
        Mnemonic = "rep";  // "repe"
1992
1
        return;
1993
2
      case 'z':  // 1 string to match.
1994
1
        Mnemonic = "rep";  // "repz"
1995
1
        return;
1996
0
      }
1997
0
      break;
1998
3.53k
    case 's':  // 2 strings to match.
1999
3.53k
      if (memcmp(Mnemonic.data()+1, "et", 2) != 0)
2000
3.16k
        break;
2001
373
      switch (Mnemonic[3]) {
2002
373
      
default: break343
;
2003
373
      case 'c':  // 1 string to match.
2004
6
        Mnemonic = "setb";   // "setc"
2005
6
        return;
2006
373
      case 'z':  // 1 string to match.
2007
24
        Mnemonic = "sete";   // "setz"
2008
24
        return;
2009
343
      }
2010
343
      break;
2011
42.1k
    }
2012
42.1k
    break;
2013
42.1k
  case 5:  // 11 strings to match.
2014
15.5k
    switch (Mnemonic[0]) {
2015
15.5k
    
default: break12.4k
;
2016
15.5k
    case 'f':  // 1 string to match.
2017
955
      if (memcmp(Mnemonic.data()+1, "wait", 4) != 0)
2018
941
        break;
2019
14
      Mnemonic = "wait";   // "fwait"
2020
14
      return;
2021
333
    case 'l':  // 1 string to match.
2022
333
      if (memcmp(Mnemonic.data()+1, "oopz", 4) != 0)
2023
322
        break;
2024
11
      Mnemonic = "loope";  // "loopz"
2025
11
      return;
2026
294
    case 'r':  // 1 string to match.
2027
294
      if (memcmp(Mnemonic.data()+1, "epnz", 4) != 0)
2028
293
        break;
2029
1
      Mnemonic = "repne";  // "repnz"
2030
1
      return;
2031
1.53k
    case 's':  // 8 strings to match.
2032
1.53k
      if (memcmp(Mnemonic.data()+1, "et", 2) != 0)
2033
1.14k
        break;
2034
387
      switch (Mnemonic[3]) {
2035
387
      
default: break93
;
2036
387
      case 'n':  // 6 strings to match.
2037
288
        switch (Mnemonic[4]) {
2038
288
        
default: break161
;
2039
288
        case 'a':  // 1 string to match.
2040
25
          Mnemonic = "setbe";  // "setna"
2041
25
          return;
2042
288
        case 'b':  // 1 string to match.
2043
25
          Mnemonic = "setae";  // "setnb"
2044
25
          return;
2045
288
        case 'c':  // 1 string to match.
2046
3
          Mnemonic = "setae";  // "setnc"
2047
3
          return;
2048
288
        case 'g':  // 1 string to match.
2049
25
          Mnemonic = "setle";  // "setng"
2050
25
          return;
2051
288
        case 'l':  // 1 string to match.
2052
25
          Mnemonic = "setge";  // "setnl"
2053
25
          return;
2054
288
        case 'z':  // 1 string to match.
2055
24
          Mnemonic = "setne";  // "setnz"
2056
24
          return;
2057
161
        }
2058
161
        break;
2059
161
      case 'p':  // 2 strings to match.
2060
6
        switch (Mnemonic[4]) {
2061
6
        
default: break0
;
2062
6
        case 'e':  // 1 string to match.
2063
3
          Mnemonic = "setp";   // "setpe"
2064
3
          return;
2065
6
        case 'o':  // 1 string to match.
2066
3
          Mnemonic = "setnp";  // "setpo"
2067
3
          return;
2068
0
        }
2069
0
        break;
2070
254
      }
2071
254
      break;
2072
15.3k
    }
2073
15.3k
    break;
2074
25.8k
  case 6:  // 6 strings to match.
2075
25.8k
    switch (Mnemonic[0]) {
2076
25.8k
    
default: break24.1k
;
2077
25.8k
    case 'f':  // 1 string to match.
2078
1.09k
      if (memcmp(Mnemonic.data()+1, "comip", 5) != 0)
2079
1.09k
        break;
2080
3
      Mnemonic = "fcompi";   // "fcomip"
2081
3
      return;
2082
261
    case 'l':  // 1 string to match.
2083
261
      if (memcmp(Mnemonic.data()+1, "oopnz", 5) != 0)
2084
250
        break;
2085
11
      Mnemonic = "loopne";   // "loopnz"
2086
11
      return;
2087
352
    case 's':  // 4 strings to match.
2088
352
      if (memcmp(Mnemonic.data()+1, "etn", 3) != 0)
2089
338
        break;
2090
14
      switch (Mnemonic[4]) {
2091
14
      
default: break0
;
2092
14
      case 'a':  // 1 string to match.
2093
5
        if (Mnemonic[5] != 'e')
2094
0
          break;
2095
5
        Mnemonic = "setb";   // "setnae"
2096
5
        return;
2097
5
      case 'b':  // 1 string to match.
2098
3
        if (Mnemonic[5] != 'e')
2099
0
          break;
2100
3
        Mnemonic = "seta";   // "setnbe"
2101
3
        return;
2102
3
      case 'g':  // 1 string to match.
2103
3
        if (Mnemonic[5] != 'e')
2104
0
          break;
2105
3
        Mnemonic = "setl";   // "setnge"
2106
3
        return;
2107
3
      case 'l':  // 1 string to match.
2108
3
        if (Mnemonic[5] != 'e')
2109
0
          break;
2110
3
        Mnemonic = "setg";   // "setnle"
2111
3
        return;
2112
0
      }
2113
0
      break;
2114
25.7k
    }
2115
25.7k
    break;
2116
25.7k
  case 7:  // 1 string to match.
2117
19.5k
    if (memcmp(Mnemonic.data()+0, "fucomip", 7) != 0)
2118
19.5k
      break;
2119
3
    Mnemonic = "fucompi";  // "fucomip"
2120
3
    return;
2121
172k
  }
2122
172k
}
2123
2124
enum {
2125
  Tie0_1_1,
2126
  Tie0_2_2,
2127
  Tie0_3_3,
2128
  Tie0_4_4,
2129
  Tie1_1_1,
2130
  Tie1_2_2,
2131
  Tie1_3_3,
2132
  Tie1_4_4,
2133
};
2134
2135
static const uint8_t TiedAsmOperandTable[][3] = {
2136
  /* Tie0_1_1 */ { 0, 1, 1 },
2137
  /* Tie0_2_2 */ { 0, 2, 2 },
2138
  /* Tie0_3_3 */ { 0, 3, 3 },
2139
  /* Tie0_4_4 */ { 0, 4, 4 },
2140
  /* Tie1_1_1 */ { 1, 1, 1 },
2141
  /* Tie1_2_2 */ { 1, 2, 2 },
2142
  /* Tie1_3_3 */ { 1, 3, 3 },
2143
  /* Tie1_4_4 */ { 1, 4, 4 },
2144
};
2145
2146
namespace {
2147
enum OperatorConversionKind {
2148
  CVT_Done,
2149
  CVT_Reg,
2150
  CVT_Tied,
2151
  CVT_imm_95_10,
2152
  CVT_95_addImmOperands,
2153
  CVT_regAX,
2154
  CVT_regEAX,
2155
  CVT_regRAX,
2156
  CVT_95_Reg,
2157
  CVT_95_addMemOperands,
2158
  CVT_95_addAbsMemOperands,
2159
  CVT_95_addDstIdxOperands,
2160
  CVT_95_addSrcIdxOperands,
2161
  CVT_95_addGR32orGR64Operands,
2162
  CVT_regST1,
2163
  CVT_regST0,
2164
  CVT_95_addMemOffsOperands,
2165
  CVT_imm_95_17,
2166
  CVT_imm_95_1,
2167
  CVT_imm_95_16,
2168
  CVT_imm_95_0,
2169
  CVT_95_addAVX512RCOperands,
2170
  CVT_NUM_CONVERTERS
2171
};
2172
2173
enum InstructionConversionKind {
2174
  Convert_NoOperands,
2175
  Convert__imm_95_10,
2176
  Convert__Imm1_0,
2177
  Convert__Imm1_1,
2178
  Convert__regAX__Tie0_1_1__ImmSExti16i81_1,
2179
  Convert__regEAX__Tie0_1_1__ImmSExti32i81_1,
2180
  Convert__regRAX__Tie0_1_1__ImmSExti64i81_1,
2181
  Convert__ImmSExti64i321_1,
2182
  Convert__Reg1_0__Tie0_1_1__Reg1_1,
2183
  Convert__Reg1_0__Tie0_1_1__ImmSExti16i81_1,
2184
  Convert__Reg1_0__Tie0_1_1__Imm1_1,
2185
  Convert__Reg1_0__Tie0_1_1__Mem165_1,
2186
  Convert__Reg1_0__Tie0_1_1__ImmSExti32i81_1,
2187
  Convert__Reg1_0__Tie0_1_1__Mem325_1,
2188
  Convert__Reg1_0__Tie0_1_1__ImmSExti64i81_1,
2189
  Convert__Reg1_0__Tie0_1_1__ImmSExti64i321_1,
2190
  Convert__Reg1_0__Tie0_1_1__Mem645_1,
2191
  Convert__Reg1_0__Tie0_1_1__Mem85_1,
2192
  Convert__Mem165_0__Reg1_1,
2193
  Convert__Mem165_0__ImmSExti16i81_1,
2194
  Convert__Mem165_0__Imm1_1,
2195
  Convert__Mem325_0__Reg1_1,
2196
  Convert__Mem325_0__ImmSExti32i81_1,
2197
  Convert__Mem325_0__Imm1_1,
2198
  Convert__Mem645_0__Reg1_1,
2199
  Convert__Mem645_0__ImmSExti64i81_1,
2200
  Convert__Mem645_0__ImmSExti64i321_1,
2201
  Convert__Mem85_0__Reg1_1,
2202
  Convert__Mem85_0__Imm1_1,
2203
  Convert__Reg1_1__Tie0_2_2__Reg1_0,
2204
  Convert__Mem85_1__Reg1_0,
2205
  Convert__Reg1_1__Tie0_2_2__Imm1_0,
2206
  Convert__Mem85_1__Imm1_0,
2207
  Convert__Reg1_1__Tie0_2_2__Mem85_0,
2208
  Convert__Mem325_1__Reg1_0,
2209
  Convert__regEAX__Tie0_1_1__ImmSExti32i81_0,
2210
  Convert__Reg1_1__Tie0_2_2__ImmSExti32i81_0,
2211
  Convert__Mem325_1__ImmSExti32i81_0,
2212
  Convert__Mem325_1__Imm1_0,
2213
  Convert__Reg1_1__Tie0_2_2__Mem325_0,
2214
  Convert__Mem645_1__Reg1_0,
2215
  Convert__regRAX__Tie0_1_1__ImmSExti64i81_0,
2216
  Convert__Reg1_1__Tie0_2_2__ImmSExti64i81_0,
2217
  Convert__Mem645_1__ImmSExti64i81_0,
2218
  Convert__ImmSExti64i321_0,
2219
  Convert__Reg1_1__Tie0_2_2__ImmSExti64i321_0,
2220
  Convert__Mem645_1__ImmSExti64i321_0,
2221
  Convert__Reg1_1__Tie0_2_2__Mem645_0,
2222
  Convert__Mem165_1__Reg1_0,
2223
  Convert__regAX__Tie0_1_1__ImmSExti16i81_0,
2224
  Convert__Reg1_1__Tie0_2_2__ImmSExti16i81_0,
2225
  Convert__Mem165_1__ImmSExti16i81_0,
2226
  Convert__Mem165_1__Imm1_0,
2227
  Convert__Reg1_1__Tie0_2_2__Mem165_0,
2228
  Convert__Reg1_1__Tie0_1_1__Reg1_0,
2229
  Convert__Reg1_1__Tie0_1_1__Mem325_0,
2230
  Convert__Reg1_1__Tie0_1_1__Mem645_0,
2231
  Convert__Reg1_0__Tie0_1_1__Mem1285_1,
2232
  Convert__Reg1_1__Tie0_1_1__Mem1285_0,
2233
  Convert__Reg1_1__Reg1_0,
2234
  Convert__Reg1_0__Reg1_1,
2235
  Convert__Reg1_0__Mem1285_1,
2236
  Convert__Reg1_1__Mem1285_0,
2237
  Convert__Reg1_0__Reg1_1__ImmUnsignedi81_2,
2238
  Convert__Reg1_0__Mem1285_1__ImmUnsignedi81_2,
2239
  Convert__Reg1_2__Reg1_1__ImmUnsignedi81_0,
2240
  Convert__Reg1_2__Mem1285_1__ImmUnsignedi81_0,
2241
  Convert__Reg1_0__Reg1_1__Reg1_2,
2242
  Convert__Reg1_0__Reg1_1__Mem325_2,
2243
  Convert__Reg1_0__Reg1_1__Mem645_2,
2244
  Convert__Reg1_2__Reg1_1__Reg1_0,
2245
  Convert__Reg1_2__Reg1_1__Mem325_0,
2246
  Convert__Reg1_2__Reg1_1__Mem645_0,
2247
  Convert__Reg1_0__Reg1_1__Imm1_2,
2248
  Convert__Reg1_0__Mem325_1__Reg1_2,
2249
  Convert__Reg1_0__Mem325_1__Imm1_2,
2250
  Convert__Reg1_0__Reg1_1__ImmSExti64i321_2,
2251
  Convert__Reg1_0__Mem645_1__Reg1_2,
2252
  Convert__Reg1_0__Mem645_1__ImmSExti64i321_2,
2253
  Convert__Reg1_2__Mem325_1__Reg1_0,
2254
  Convert__Reg1_2__Reg1_1__Imm1_0,
2255
  Convert__Reg1_2__Mem325_1__Imm1_0,
2256
  Convert__Reg1_2__Mem645_1__Reg1_0,
2257
  Convert__Reg1_2__Reg1_1__ImmSExti64i321_0,
2258
  Convert__Reg1_2__Mem645_1__ImmSExti64i321_0,
2259
  Convert__Reg1_0__Mem325_1,
2260
  Convert__Reg1_0__Mem645_1,
2261
  Convert__Reg1_1__Mem325_0,
2262
  Convert__Reg1_1__Mem645_0,
2263
  Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmUnsignedi81_2,
2264
  Convert__Reg1_0__Tie0_1_1__Mem1285_1__ImmUnsignedi81_2,
2265
  Convert__Reg1_2__Tie0_1_1__Reg1_1__ImmUnsignedi81_0,
2266
  Convert__Reg1_2__Tie0_1_1__Mem1285_1__ImmUnsignedi81_0,
2267
  Convert__Reg1_1__Tie0_2_2__Mem1285_0,
2268
  Convert__Reg1_2__Tie0_1_1__Reg1_1,
2269
  Convert__Reg1_2__Tie0_1_1__Mem1285_1,
2270
  Convert__Reg1_0__Mem5_1,
2271
  Convert__Reg1_1__Mem5_0,
2272
  Convert__Mem1285_1__Reg1_0,
2273
  Convert__Mem1285_0__Reg1_1,
2274
  Convert__Mem5_1__Reg1_0,
2275
  Convert__Mem5_0__Reg1_1,
2276
  Convert__Reg1_0__Mem165_1,
2277
  Convert__Reg1_1__Mem165_0,
2278
  Convert__Reg1_0__Tie0_1_1,
2279
  Convert__Reg1_0__ImmUnsignedi81_1,
2280
  Convert__Mem165_0__ImmUnsignedi81_1,
2281
  Convert__Mem325_0__ImmUnsignedi81_1,
2282
  Convert__Mem645_0__ImmUnsignedi81_1,
2283
  Convert__Reg1_0__Tie0_1_1__ImmUnsignedi81_1,
2284
  Convert__Reg1_1__Tie0_2_2__ImmUnsignedi81_0,
2285
  Convert__Mem325_1__ImmUnsignedi81_0,
2286
  Convert__Mem645_1__ImmUnsignedi81_0,
2287
  Convert__Mem165_1__ImmUnsignedi81_0,
2288
  Convert__Reg1_1__ImmUnsignedi81_0,
2289
  Convert__Reg1_0,
2290
  Convert__AbsMem1_0,
2291
  Convert__Mem165_0,
2292
  Convert__Mem325_0,
2293
  Convert__Mem645_0,
2294
  Convert__Mem5_0,
2295
  Convert__Imm1_1__Imm1_0,
2296
  Convert__Reg1_1,
2297
  Convert__Mem325_1,
2298
  Convert__Mem645_1,
2299
  Convert__Mem165_1,
2300
  Convert__Mem85_0,
2301
  Convert__Reg1_0__Tie0_1_1__Reg1_0,
2302
  Convert__Reg1_1__Tie0_1_1__Mem165_0,
2303
  Convert__regAX__ImmSExti16i81_1,
2304
  Convert__regEAX__ImmSExti32i81_1,
2305
  Convert__regRAX__ImmSExti64i81_1,
2306
  Convert__Reg1_0__ImmSExti16i81_1,
2307
  Convert__Reg1_0__Imm1_1,
2308
  Convert__Reg1_0__ImmSExti32i81_1,
2309
  Convert__Reg1_0__ImmSExti64i81_1,
2310
  Convert__Reg1_0__ImmSExti64i321_1,
2311
  Convert__Reg1_0__Mem85_1,
2312
  Convert__Reg1_1__Imm1_0,
2313
  Convert__Reg1_1__Mem85_0,
2314
  Convert__regEAX__ImmSExti32i81_0,
2315
  Convert__Reg1_1__ImmSExti32i81_0,
2316
  Convert__regRAX__ImmSExti64i81_0,
2317
  Convert__Reg1_1__ImmSExti64i81_0,
2318
  Convert__Reg1_1__ImmSExti64i321_0,
2319
  Convert__DstIdx161_1__SrcIdx162_0,
2320
  Convert__DstIdx321_1__SrcIdx322_0,
2321
  Convert__DstIdx641_1__SrcIdx642_0,
2322
  Convert__DstIdx81_1__SrcIdx82_0,
2323
  Convert__DstIdx81_0__SrcIdx82_1,
2324
  Convert__Reg1_0__Tie0_1_1__Mem645_1__ImmUnsignedi81_2,
2325
  Convert__Reg1_2__Tie0_1_1__Mem645_1__ImmUnsignedi81_0,
2326
  Convert__DstIdx321_0__SrcIdx322_1,
2327
  Convert__DstIdx641_0__SrcIdx642_1,
2328
  Convert__Reg1_0__Tie0_1_1__Mem325_1__ImmUnsignedi81_2,
2329
  Convert__Reg1_2__Tie0_1_1__Mem325_1__ImmUnsignedi81_0,
2330
  Convert__DstIdx161_0__SrcIdx162_1,
2331
  Convert__regAX__ImmSExti16i81_0,
2332
  Convert__Reg1_1__ImmSExti16i81_0,
2333
  Convert__Mem1285_0,
2334
  Convert__Mem85_1,
2335
  Convert__Imm1_0__Imm1_1,
2336
  Convert__GR32orGR641_2__Reg1_1__ImmUnsignedi81_0,
2337
  Convert__Mem325_2__Reg1_1__ImmUnsignedi81_0,
2338
  Convert__GR32orGR641_0__Reg1_1__ImmUnsignedi81_2,
2339
  Convert__Mem325_0__Reg1_1__ImmUnsignedi81_2,
2340
  Convert__Reg1_0__Tie0_1_1__ImmUnsignedi81_1__ImmUnsignedi81_2,
2341
  Convert__Reg1_2__Tie0_3_3__ImmUnsignedi81_1__ImmUnsignedi81_0,
2342
  Convert__regST1,
2343
  Convert__regST0,
2344
  Convert__Mem805_0,
2345
  Convert__Reg1_0__Reg1_0__ImmSExti16i81_1,
2346
  Convert__Reg1_0__Reg1_0__Imm1_1,
2347
  Convert__Reg1_0__Reg1_0__ImmSExti32i81_1,
2348
  Convert__Reg1_0__Reg1_0__ImmSExti64i81_1,
2349
  Convert__Reg1_0__Reg1_0__ImmSExti64i321_1,
2350
  Convert__Reg1_0__Reg1_1__ImmSExti16i81_2,
2351
  Convert__Reg1_0__Mem165_1__ImmSExti16i81_2,
2352
  Convert__Reg1_0__Mem165_1__Imm1_2,
2353
  Convert__Reg1_0__Reg1_1__ImmSExti32i81_2,
2354
  Convert__Reg1_0__Mem325_1__ImmSExti32i81_2,
2355
  Convert__Reg1_0__Reg1_1__ImmSExti64i81_2,
2356
  Convert__Reg1_0__Mem645_1__ImmSExti64i81_2,
2357
  Convert__Reg1_1__Reg1_1__ImmSExti32i81_0,
2358
  Convert__Reg1_1__Reg1_1__Imm1_0,
2359
  Convert__Reg1_2__Reg1_1__ImmSExti32i81_0,
2360
  Convert__Reg1_2__Mem325_1__ImmSExti32i81_0,
2361
  Convert__Reg1_1__Reg1_1__ImmSExti64i81_0,
2362
  Convert__Reg1_1__Reg1_1__ImmSExti64i321_0,
2363
  Convert__Reg1_2__Reg1_1__ImmSExti64i81_0,
2364
  Convert__Reg1_2__Mem645_1__ImmSExti64i81_0,
2365
  Convert__Reg1_1__Reg1_1__ImmSExti16i81_0,
2366
  Convert__Reg1_2__Reg1_1__ImmSExti16i81_0,
2367
  Convert__Reg1_2__Mem165_1__ImmSExti16i81_0,
2368
  Convert__Reg1_2__Mem165_1__Imm1_0,
2369
  Convert__ImmUnsignedi81_1,
2370
  Convert__ImmUnsignedi81_0,
2371
  Convert__DstIdx161_0,
2372
  Convert__DstIdx321_0,
2373
  Convert__DstIdx81_0,
2374
  Convert__DstIdx81_1,
2375
  Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmUnsignedi81_2__ImmUnsignedi81_3,
2376
  Convert__Reg1_3__Tie0_4_4__Reg1_2__ImmUnsignedi81_1__ImmUnsignedi81_0,
2377
  Convert__DstIdx321_1,
2378
  Convert__DstIdx161_1,
2379
  Convert__Mem5_1,
2380
  Convert__SrcIdx162_0,
2381
  Convert__SrcIdx322_0,
2382
  Convert__SrcIdx642_0,
2383
  Convert__SrcIdx82_0,
2384
  Convert__SrcIdx82_1,
2385
  Convert__SrcIdx162_1,
2386
  Convert__SrcIdx322_1,
2387
  Convert__SrcIdx642_1,
2388
  Convert__MemOffs16_82_1,
2389
  Convert__MemOffs32_82_1,
2390
  Convert__MemOffs16_162_1,
2391
  Convert__MemOffs32_162_1,
2392
  Convert__MemOffs16_322_1,
2393
  Convert__MemOffs32_322_1,
2394
  Convert__MemOffs32_642_1,
2395
  Convert__MemOffs16_162_0,
2396
  Convert__MemOffs16_322_0,
2397
  Convert__MemOffs16_82_0,
2398
  Convert__MemOffs32_162_0,
2399
  Convert__MemOffs32_322_0,
2400
  Convert__MemOffs32_642_0,
2401
  Convert__MemOffs32_82_0,
2402
  Convert__MemOffs64_82_1,
2403
  Convert__MemOffs64_162_1,
2404
  Convert__MemOffs64_322_1,
2405
  Convert__MemOffs64_642_1,
2406
  Convert__MemOffs64_162_0,
2407
  Convert__MemOffs64_322_0,
2408
  Convert__MemOffs64_642_0,
2409
  Convert__MemOffs64_82_0,
2410
  Convert__Reg1_0__Mem5125_1,
2411
  Convert__Reg1_1__Mem5125_0,
2412
  Convert__GR32orGR641_1__Reg1_0,
2413
  Convert__GR32orGR641_0__Reg1_1,
2414
  Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_17,
2415
  Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_17,
2416
  Convert__Reg1_0__Tie0_1_1__Mem1285_1__imm_95_17,
2417
  Convert__Reg1_1__Tie0_2_2__Mem1285_0__imm_95_17,
2418
  Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_1,
2419
  Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_1,
2420
  Convert__Reg1_0__Tie0_1_1__Mem1285_1__imm_95_1,
2421
  Convert__Reg1_1__Tie0_2_2__Mem1285_0__imm_95_1,
2422
  Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_16,
2423
  Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_16,
2424
  Convert__Reg1_0__Tie0_1_1__Mem1285_1__imm_95_16,
2425
  Convert__Reg1_1__Tie0_2_2__Mem1285_0__imm_95_16,
2426
  Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_0,
2427
  Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_0,
2428
  Convert__Reg1_0__Tie0_1_1__Mem1285_1__imm_95_0,
2429
  Convert__Reg1_1__Tie0_2_2__Mem1285_0__imm_95_0,
2430
  Convert__Mem85_2__Reg1_1__ImmUnsignedi81_0,
2431
  Convert__Mem85_0__Reg1_1__ImmUnsignedi81_2,
2432
  Convert__Mem645_2__Reg1_1__ImmUnsignedi81_0,
2433
  Convert__Mem645_0__Reg1_1__ImmUnsignedi81_2,
2434
  Convert__Mem165_2__Reg1_1__ImmUnsignedi81_0,
2435
  Convert__Mem165_0__Reg1_1__ImmUnsignedi81_2,
2436
  Convert__Reg1_0__Tie0_1_1__GR32orGR641_1__ImmUnsignedi81_2,
2437
  Convert__Reg1_0__Tie0_1_1__Mem85_1__ImmUnsignedi81_2,
2438
  Convert__Reg1_2__Tie0_1_1__GR32orGR641_1__ImmUnsignedi81_0,
2439
  Convert__Reg1_2__Tie0_1_1__Mem85_1__ImmUnsignedi81_0,
2440
  Convert__Reg1_0__Tie0_1_1__Mem165_1__ImmUnsignedi81_2,
2441
  Convert__Reg1_2__Tie0_1_1__Mem165_1__ImmUnsignedi81_0,
2442
  Convert__Reg1_0__Mem645_1__ImmUnsignedi81_2,
2443
  Convert__Reg1_2__Mem645_1__ImmUnsignedi81_0,
2444
  Convert__Reg1_1__Tie0_1_1__ImmUnsignedi81_0,
2445
  Convert__ImmSExti64i81_0,
2446
  Convert__ImmSExti16i81_0,
2447
  Convert__ImmSExti32i81_0,
2448
  Convert__Mem85_0__ImmUnsignedi81_1,
2449
  Convert__Reg1_1__Tie0_1_1,
2450
  Convert__Mem85_1__ImmUnsignedi81_0,
2451
  Convert__Reg1_0__Mem325_1__ImmUnsignedi81_2,
2452
  Convert__Reg1_2__Mem325_1__ImmUnsignedi81_0,
2453
  Convert__DstIdx641_0,
2454
  Convert__DstIdx641_1,
2455
  Convert__Mem325_2__Reg1_1,
2456
  Convert__Mem645_2__Reg1_1,
2457
  Convert__Mem165_2__Reg1_1,
2458
  Convert__GR32orGR641_0,
2459
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem1285_2,
2460
  Convert__Reg1_2__Tie0_1_1__Reg1_1__Mem1285_0,
2461
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem1285_5,
2462
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__Mem1285_0,
2463
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem1285_6,
2464
  Convert__Reg1_0__Reg1_1__Mem1285_2,
2465
  Convert__Reg1_0__Reg1_1__Mem2565_2,
2466
  Convert__Reg1_0__Reg1_1__Mem5125_2,
2467
  Convert__Reg1_2__Reg1_1__Mem1285_0,
2468
  Convert__Reg1_2__Reg1_1__Mem2565_0,
2469
  Convert__Reg1_2__Reg1_1__Mem5125_0,
2470
  Convert__Reg1_0__Reg1_1__Reg1_2__AVX512RC1_3,
2471
  Convert__Reg1_3__Reg1_2__Reg1_1__AVX512RC1_0,
2472
  Convert__Reg1_3__Reg1_2__Mem645_0,
2473
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5,
2474
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__Reg1_0,
2475
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem2565_5,
2476
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem5125_5,
2477
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__Mem2565_0,
2478
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__Mem5125_0,
2479
  Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6,
2480
  Convert__Reg1_0__Reg1_2__Reg1_5__Mem1285_6,
2481
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem645_5,
2482
  Convert__Reg1_2__Reg1_4__Reg1_1__Reg1_0,
2483
  Convert__Reg1_0__Reg1_2__Reg1_5__Mem2565_6,
2484
  Convert__Reg1_0__Reg1_2__Reg1_5__Mem5125_6,
2485
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5__AVX512RC1_6,
2486
  Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Reg1_1__AVX512RC1_0,
2487
  Convert__Reg1_2__Reg1_4__Reg1_1__Mem1285_0,
2488
  Convert__Reg1_2__Reg1_4__Reg1_1__Mem2565_0,
2489
  Convert__Reg1_2__Reg1_4__Reg1_1__Mem5125_0,
2490
  Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem645_0,
2491
  Convert__Reg1_0__Reg1_2__Reg1_5__Mem645_6,
2492
  Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6__AVX512RC1_7,
2493
  Convert__Reg1_3__Reg1_5__Reg1_2__Reg1_1__AVX512RC1_0,
2494
  Convert__Reg1_3__Reg1_5__Reg1_2__Mem645_0,
2495
  Convert__Reg1_3__Reg1_2__Mem325_0,
2496
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem325_5,
2497
  Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem325_0,
2498
  Convert__Reg1_0__Reg1_2__Reg1_5__Mem325_6,
2499
  Convert__Reg1_3__Reg1_5__Reg1_2__Mem325_0,
2500
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__Mem645_0,
2501
  Convert__Reg1_2__Reg1_4__Reg1_1__Mem645_0,
2502
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__Mem325_0,
2503
  Convert__Reg1_2__Reg1_4__Reg1_1__Mem325_0,
2504
  Convert__Reg1_0__Reg1_1__Reg1_2__ImmUnsignedi81_3,
2505
  Convert__Reg1_0__Reg1_1__Mem1285_2__ImmUnsignedi81_3,
2506
  Convert__Reg1_0__Reg1_1__Mem2565_2__ImmUnsignedi81_3,
2507
  Convert__Reg1_0__Reg1_1__Mem5125_2__ImmUnsignedi81_3,
2508
  Convert__Reg1_3__Reg1_2__Reg1_1__ImmUnsignedi81_0,
2509
  Convert__Reg1_3__Reg1_2__Mem1285_1__ImmUnsignedi81_0,
2510
  Convert__Reg1_3__Reg1_2__Mem2565_1__ImmUnsignedi81_0,
2511
  Convert__Reg1_3__Reg1_2__Mem5125_1__ImmUnsignedi81_0,
2512
  Convert__Reg1_0__Reg1_1__Mem325_2__ImmUnsignedi81_4,
2513
  Convert__Reg1_4__Reg1_3__Mem325_1__ImmUnsignedi81_0,
2514
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5__ImmUnsignedi81_6,
2515
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem1285_5__ImmUnsignedi81_6,
2516
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem2565_5__ImmUnsignedi81_6,
2517
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem5125_5__ImmUnsignedi81_6,
2518
  Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Reg1_1__ImmUnsignedi81_0,
2519
  Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem1285_1__ImmUnsignedi81_0,
2520
  Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem2565_1__ImmUnsignedi81_0,
2521
  Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem5125_1__ImmUnsignedi81_0,
2522
  Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6__ImmUnsignedi81_7,
2523
  Convert__Reg1_0__Reg1_2__Reg1_5__Mem1285_6__ImmUnsignedi81_7,
2524
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem325_5__ImmUnsignedi81_7,
2525
  Convert__Reg1_0__Reg1_2__Reg1_5__Mem2565_6__ImmUnsignedi81_7,
2526
  Convert__Reg1_0__Reg1_2__Reg1_5__Mem5125_6__ImmUnsignedi81_7,
2527
  Convert__Reg1_3__Reg1_5__Reg1_2__Reg1_1__ImmUnsignedi81_0,
2528
  Convert__Reg1_3__Reg1_5__Reg1_2__Mem1285_1__ImmUnsignedi81_0,
2529
  Convert__Reg1_3__Reg1_5__Reg1_2__Mem2565_1__ImmUnsignedi81_0,
2530
  Convert__Reg1_4__Tie0_1_1__Reg1_6__Reg1_3__Mem325_1__ImmUnsignedi81_0,
2531
  Convert__Reg1_3__Reg1_5__Reg1_2__Mem5125_1__ImmUnsignedi81_0,
2532
  Convert__Reg1_0__Reg1_2__Reg1_5__Mem325_6__ImmUnsignedi81_8,
2533
  Convert__Reg1_4__Reg1_6__Reg1_3__Mem325_1__ImmUnsignedi81_0,
2534
  Convert__Reg1_0__Reg1_1__Mem645_2__ImmUnsignedi81_4,
2535
  Convert__Reg1_4__Reg1_3__Mem645_1__ImmUnsignedi81_0,
2536
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem645_5__ImmUnsignedi81_7,
2537
  Convert__Reg1_4__Tie0_1_1__Reg1_6__Reg1_3__Mem645_1__ImmUnsignedi81_0,
2538
  Convert__Reg1_0__Reg1_2__Reg1_5__Mem645_6__ImmUnsignedi81_8,
2539
  Convert__Reg1_4__Reg1_6__Reg1_3__Mem645_1__ImmUnsignedi81_0,
2540
  Convert__Reg1_0__Reg1_2__Reg1_4__Reg1_5,
2541
  Convert__Reg1_0__Reg1_2__Reg1_4__Mem1285_5,
2542
  Convert__Reg1_0__Reg1_2__Reg1_4__Mem2565_5,
2543
  Convert__Reg1_0__Reg1_2__Reg1_4__Mem5125_5,
2544
  Convert__Reg1_0__Reg1_2__Reg1_4__Mem645_5,
2545
  Convert__Reg1_0__Reg1_2__Reg1_4__Mem325_5,
2546
  Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0,
2547
  Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3,
2548
  Convert__Reg1_0__Reg1_1__Mem1285_2__Reg1_3,
2549
  Convert__Reg1_3__Reg1_2__Mem1285_1__Reg1_0,
2550
  Convert__Reg1_0__Reg1_1__Mem2565_2__Reg1_3,
2551
  Convert__Reg1_3__Reg1_2__Mem2565_1__Reg1_0,
2552
  Convert__Reg1_1__Tie0_1_1__Reg1_3__Reg1_0,
2553
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4,
2554
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem645_4,
2555
  Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem645_0,
2556
  Convert__Reg1_1__Reg1_3__Reg1_0,
2557
  Convert__Reg1_0__Reg1_2__Reg1_5,
2558
  Convert__Reg1_0__Reg1_2__Mem645_5,
2559
  Convert__Reg1_1__Reg1_3__Mem645_0,
2560
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem1285_4,
2561
  Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem1285_0,
2562
  Convert__Reg1_0__Reg1_2__Mem1285_5,
2563
  Convert__Reg1_1__Reg1_3__Mem1285_0,
2564
  Convert__Reg1_0__Mem2565_1,
2565
  Convert__Reg1_1__Mem2565_0,
2566
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem2565_4,
2567
  Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem2565_0,
2568
  Convert__Reg1_0__Reg1_2__Mem2565_5,
2569
  Convert__Reg1_1__Reg1_3__Mem2565_0,
2570
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem325_4,
2571
  Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem325_0,
2572
  Convert__Reg1_0__Reg1_2__Mem325_5,
2573
  Convert__Reg1_1__Reg1_3__Mem325_0,
2574
  Convert__Reg1_0__Reg1_1__Reg1_2__ImmUnsignedi81_4,
2575
  Convert__Reg1_4__Reg1_3__Reg1_2__ImmUnsignedi81_0,
2576
  Convert__Reg1_0__Reg1_2__Reg1_4__Reg1_5__ImmUnsignedi81_6,
2577
  Convert__Reg1_0__Reg1_2__Reg1_4__Mem1285_5__ImmUnsignedi81_6,
2578
  Convert__Reg1_0__Reg1_2__Reg1_4__Mem2565_5__ImmUnsignedi81_6,
2579
  Convert__Reg1_0__Reg1_2__Reg1_4__Mem5125_5__ImmUnsignedi81_6,
2580
  Convert__Reg1_0__Reg1_2__Reg1_4__Mem645_5__ImmUnsignedi81_7,
2581
  Convert__Reg1_0__Reg1_2__Reg1_4__Reg1_5__ImmUnsignedi81_7,
2582
  Convert__Reg1_4__Reg1_6__Reg1_3__Reg1_2__ImmUnsignedi81_0,
2583
  Convert__Reg1_0__Reg1_2__Reg1_4__Mem325_5__ImmUnsignedi81_7,
2584
  Convert__Reg1_0__Reg1_1__Mem645_2__ImmUnsignedi81_3,
2585
  Convert__Reg1_3__Reg1_2__Mem645_1__ImmUnsignedi81_0,
2586
  Convert__Reg1_0__Reg1_2__Reg1_4__Mem645_5__ImmUnsignedi81_6,
2587
  Convert__Reg1_3__Reg1_5__Reg1_2__Mem645_1__ImmUnsignedi81_0,
2588
  Convert__Reg1_0__Reg1_1__Mem325_2__ImmUnsignedi81_3,
2589
  Convert__Reg1_3__Reg1_2__Mem325_1__ImmUnsignedi81_0,
2590
  Convert__Reg1_0__Reg1_2__Reg1_4__Mem325_5__ImmUnsignedi81_6,
2591
  Convert__Reg1_3__Reg1_5__Reg1_2__Mem325_1__ImmUnsignedi81_0,
2592
  Convert__Reg1_2__Reg1_1,
2593
  Convert__Mem2565_1__Reg1_0,
2594
  Convert__Mem5125_1__Reg1_0,
2595
  Convert__Mem2565_0__Reg1_1,
2596
  Convert__Mem5125_0__Reg1_1,
2597
  Convert__Mem1285_1__Reg1_3__Reg1_0,
2598
  Convert__Mem2565_1__Reg1_3__Reg1_0,
2599
  Convert__Mem5125_1__Reg1_3__Reg1_0,
2600
  Convert__Mem1285_0__Reg1_2__Reg1_4,
2601
  Convert__Mem2565_0__Reg1_2__Reg1_4,
2602
  Convert__Mem5125_0__Reg1_2__Reg1_4,
2603
  Convert__Reg1_2__Mem325_0,
2604
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Mem325_0,
2605
  Convert__Reg1_2__Reg1_4__Mem325_0,
2606
  Convert__Reg1_0__Reg1_1__AVX512RC1_2,
2607
  Convert__Reg1_2__Reg1_1__AVX512RC1_0,
2608
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem5125_4,
2609
  Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem5125_0,
2610
  Convert__Reg1_0__Reg1_2__Mem5125_5,
2611
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__AVX512RC1_5,
2612
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__AVX512RC1_0,
2613
  Convert__Reg1_1__Reg1_3__Mem5125_0,
2614
  Convert__Reg1_0__Reg1_2__Reg1_5__AVX512RC1_6,
2615
  Convert__Reg1_2__Reg1_4__Reg1_1__AVX512RC1_0,
2616
  Convert__Reg1_2__Mem645_0,
2617
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Mem645_0,
2618
  Convert__Reg1_2__Reg1_4__Mem645_0,
2619
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1,
2620
  Convert__Reg1_2__Reg1_4__Reg1_1,
2621
  Convert__Mem1285_2__Reg1_1__ImmUnsignedi81_0,
2622
  Convert__Mem2565_2__Reg1_1__ImmUnsignedi81_0,
2623
  Convert__Mem1285_0__Reg1_1__ImmUnsignedi81_2,
2624
  Convert__Mem2565_0__Reg1_1__ImmUnsignedi81_2,
2625
  Convert__Reg1_0__Reg1_1__ImmUnsignedi81_3,
2626
  Convert__Reg1_3__Reg1_2__ImmUnsignedi81_0,
2627
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__ImmUnsignedi81_5,
2628
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__ImmUnsignedi81_0,
2629
  Convert__Mem645_2__Reg1_4__Reg1_1__ImmUnsignedi81_0,
2630
  Convert__Mem1285_2__Reg1_4__Reg1_1__ImmUnsignedi81_0,
2631
  Convert__Mem2565_2__Reg1_4__Reg1_1__ImmUnsignedi81_0,
2632
  Convert__Mem1285_0__Reg1_2__Reg1_4__ImmUnsignedi81_5,
2633
  Convert__Mem2565_0__Reg1_2__Reg1_4__ImmUnsignedi81_5,
2634
  Convert__Mem645_0__Reg1_2__Reg1_4__ImmUnsignedi81_5,
2635
  Convert__Reg1_0__Reg1_2__Reg1_5__ImmUnsignedi81_6,
2636
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__ImmUnsignedi81_6,
2637
  Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__ImmUnsignedi81_0,
2638
  Convert__Reg1_2__Reg1_4__Reg1_1__ImmUnsignedi81_0,
2639
  Convert__Reg1_0__Reg1_2__Reg1_5__ImmUnsignedi81_7,
2640
  Convert__Reg1_3__Reg1_5__Reg1_2__ImmUnsignedi81_0,
2641
  Convert__Reg1_0__Reg1_1__Reg1_3__AVX512RC1_2,
2642
  Convert__Reg1_3__Reg1_2__Reg1_0__AVX512RC1_1,
2643
  Convert__Reg1_3__Reg1_2__Reg1_1,
2644
  Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Reg1_1,
2645
  Convert__Reg1_3__Reg1_5__Reg1_2__Reg1_1,
2646
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmUnsignedi81_3,
2647
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem1285_2__ImmUnsignedi81_3,
2648
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem2565_2__ImmUnsignedi81_3,
2649
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem5125_2__ImmUnsignedi81_3,
2650
  Convert__Reg1_3__Tie0_1_1__Reg1_2__Reg1_1__ImmUnsignedi81_0,
2651
  Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem1285_1__ImmUnsignedi81_0,
2652
  Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem2565_1__ImmUnsignedi81_0,
2653
  Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem5125_1__ImmUnsignedi81_0,
2654
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem645_2__ImmUnsignedi81_4,
2655
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmUnsignedi81_4,
2656
  Convert__Reg1_4__Tie0_1_1__Reg1_3__Reg1_2__ImmUnsignedi81_0,
2657
  Convert__Reg1_4__Tie0_1_1__Reg1_3__Mem645_1__ImmUnsignedi81_0,
2658
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Reg1_6__ImmUnsignedi81_7,
2659
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem1285_6__ImmUnsignedi81_7,
2660
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem2565_6__ImmUnsignedi81_7,
2661
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem5125_6__ImmUnsignedi81_7,
2662
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5__ImmUnsignedi81_7,
2663
  Convert__Reg1_4__Tie0_1_1__Reg1_6__Reg1_3__Reg1_2__ImmUnsignedi81_0,
2664
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem645_6__ImmUnsignedi81_8,
2665
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Reg1_6__ImmUnsignedi81_8,
2666
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem325_2__ImmUnsignedi81_4,
2667
  Convert__Reg1_4__Tie0_1_1__Reg1_3__Mem325_1__ImmUnsignedi81_0,
2668
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem325_6__ImmUnsignedi81_8,
2669
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem645_2__ImmUnsignedi81_3,
2670
  Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem645_1__ImmUnsignedi81_0,
2671
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem645_5__ImmUnsignedi81_6,
2672
  Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem645_1__ImmUnsignedi81_0,
2673
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem645_6__ImmUnsignedi81_7,
2674
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem325_2__ImmUnsignedi81_3,
2675
  Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem325_1__ImmUnsignedi81_0,
2676
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem325_5__ImmUnsignedi81_6,
2677
  Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem325_1__ImmUnsignedi81_0,
2678
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem325_6__ImmUnsignedi81_7,
2679
  Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0,
2680
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2,
2681
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem2565_2,
2682
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem5125_2,
2683
  Convert__Reg1_2__Tie0_1_1__Reg1_1__Mem2565_0,
2684
  Convert__Reg1_2__Tie0_1_1__Reg1_1__Mem5125_0,
2685
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem645_2,
2686
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__AVX512RC1_3,
2687
  Convert__Reg1_3__Tie0_1_1__Reg1_2__Reg1_1__AVX512RC1_0,
2688
  Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem645_0,
2689
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Reg1_6,
2690
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem2565_6,
2691
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem5125_6,
2692
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem645_6,
2693
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Reg1_6__AVX512RC1_7,
2694
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem325_2,
2695
  Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem325_0,
2696
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem325_6,
2697
  Convert__Reg1_2__Tie0_1_1__Reg1_1__Mem645_0,
2698
  Convert__Reg1_2__Tie0_1_1__Reg1_1__Mem325_0,
2699
  Convert__Reg1_0__Reg1_1__Reg1_2__Mem1285_3,
2700
  Convert__Reg1_0__Reg1_1__Reg1_2__Mem2565_3,
2701
  Convert__Reg1_3__Reg1_2__Reg1_1__Mem1285_0,
2702
  Convert__Reg1_3__Reg1_2__Reg1_1__Mem2565_0,
2703
  Convert__Reg1_0__Reg1_1__Reg1_2__Mem645_3,
2704
  Convert__Reg1_0__Reg1_1__Mem645_2__Reg1_3,
2705
  Convert__Reg1_3__Reg1_2__Mem645_1__Reg1_0,
2706
  Convert__Reg1_3__Reg1_2__Reg1_1__Mem645_0,
2707
  Convert__Reg1_0__Reg1_1__Reg1_2__Mem325_3,
2708
  Convert__Reg1_0__Reg1_1__Mem325_2__Reg1_3,
2709
  Convert__Reg1_3__Reg1_2__Mem325_1__Reg1_0,
2710
  Convert__Reg1_3__Reg1_2__Reg1_1__Mem325_0,
2711
  Convert__Reg1_0__Mem2565_1__ImmUnsignedi81_2,
2712
  Convert__Reg1_0__Mem5125_1__ImmUnsignedi81_2,
2713
  Convert__Reg1_0__Mem645_1__ImmUnsignedi81_3,
2714
  Convert__Reg1_0__Reg1_2__Reg1_4__ImmUnsignedi81_5,
2715
  Convert__Reg1_0__Reg1_2__Mem1285_4__ImmUnsignedi81_5,
2716
  Convert__Reg1_0__Reg1_2__Mem2565_4__ImmUnsignedi81_5,
2717
  Convert__Reg1_0__Reg1_2__Mem5125_4__ImmUnsignedi81_5,
2718
  Convert__Reg1_0__Reg1_2__Mem645_4__ImmUnsignedi81_6,
2719
  Convert__Reg1_3__Mem645_1__ImmUnsignedi81_0,
2720
  Convert__Reg1_3__Reg1_5__Mem645_1__ImmUnsignedi81_0,
2721
  Convert__Reg1_2__Reg1_4__Mem1285_1__ImmUnsignedi81_0,
2722
  Convert__Reg1_2__Mem2565_1__ImmUnsignedi81_0,
2723
  Convert__Reg1_2__Reg1_4__Mem2565_1__ImmUnsignedi81_0,
2724
  Convert__Reg1_2__Mem5125_1__ImmUnsignedi81_0,
2725
  Convert__Reg1_2__Reg1_4__Mem5125_1__ImmUnsignedi81_0,
2726
  Convert__Reg1_0__Mem325_1__ImmUnsignedi81_3,
2727
  Convert__Reg1_0__Reg1_2__Mem325_4__ImmUnsignedi81_6,
2728
  Convert__Reg1_3__Mem325_1__ImmUnsignedi81_0,
2729
  Convert__Reg1_3__Reg1_5__Mem325_1__ImmUnsignedi81_0,
2730
  Convert__Reg1_0__Reg1_2__Mem645_4__ImmUnsignedi81_5,
2731
  Convert__Reg1_2__Reg1_4__Mem645_1__ImmUnsignedi81_0,
2732
  Convert__Reg1_0__Reg1_2__Mem325_4__ImmUnsignedi81_5,
2733
  Convert__Reg1_2__Reg1_4__Mem325_1__ImmUnsignedi81_0,
2734
  Convert__Reg1_2__Reg1_0__Tie0_1_1__Mem128_RC1285_1__Tie1_1_1,
2735
  Convert__Reg1_0__Reg1_2__Tie0_1_1__Mem128_RC1285_1__Tie1_3_3,
2736
  Convert__Reg1_2__Reg1_0__Tie0_1_1__Mem256_RC1285_1__Tie1_1_1,
2737
  Convert__Reg1_0__Reg1_2__Tie0_1_1__Mem256_RC1285_1__Tie1_3_3,
2738
  Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem128_RC128X5_4,
2739
  Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem256_RC128X5_4,
2740
  Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem512_RC256X5_4,
2741
  Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem128_RC128X5_0,
2742
  Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem256_RC128X5_0,
2743
  Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem512_RC256X5_0,
2744
  Convert__Reg1_2__Reg1_0__Tie0_1_1__Mem256_RC2565_1__Tie1_1_1,
2745
  Convert__Reg1_0__Reg1_2__Tie0_1_1__Mem256_RC2565_1__Tie1_3_3,
2746
  Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem256_RC256X5_4,
2747
  Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem512_RC5125_4,
2748
  Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem256_RC256X5_0,
2749
  Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem512_RC5125_0,
2750
  Convert__Reg1_1__Mem512_RC256X5_3,
2751
  Convert__Reg1_2__Mem512_RC256X5_0,
2752
  Convert__Reg1_1__Mem512_RC5125_3,
2753
  Convert__Reg1_2__Mem512_RC5125_0,
2754
  Convert__Reg1_1__Mem256_RC5125_3,
2755
  Convert__Reg1_2__Mem256_RC5125_0,
2756
  Convert__Reg1_2__Reg1_0__Tie0_1_1__Mem128_RC2565_1__Tie1_1_1,
2757
  Convert__Reg1_0__Reg1_2__Tie0_1_1__Mem128_RC2565_1__Tie1_3_3,
2758
  Convert__Reg1_2__Reg1_0__Tie0_1_1__Mem64_RC1285_1__Tie1_1_1,
2759
  Convert__Reg1_0__Reg1_2__Tie0_1_1__Mem64_RC1285_1__Tie1_3_3,
2760
  Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem128_RC256X5_4,
2761
  Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem64_RC128X5_4,
2762
  Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem256_RC5125_4,
2763
  Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem128_RC256X5_0,
2764
  Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem256_RC5125_0,
2765
  Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem64_RC128X5_0,
2766
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem1285_4__ImmUnsignedi81_5,
2767
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem2565_4__ImmUnsignedi81_5,
2768
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem5125_4__ImmUnsignedi81_5,
2769
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Mem1285_1__ImmUnsignedi81_0,
2770
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Mem2565_1__ImmUnsignedi81_0,
2771
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Mem5125_1__ImmUnsignedi81_0,
2772
  Convert__Reg1_0__Reg1_2__Mem1285_5__ImmUnsignedi81_6,
2773
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem645_4__ImmUnsignedi81_6,
2774
  Convert__Reg1_0__Reg1_2__Mem2565_5__ImmUnsignedi81_6,
2775
  Convert__Reg1_0__Reg1_2__Mem5125_5__ImmUnsignedi81_6,
2776
  Convert__Reg1_3__Tie0_1_1__Reg1_5__Mem645_1__ImmUnsignedi81_0,
2777
  Convert__Reg1_0__Reg1_2__Mem645_5__ImmUnsignedi81_7,
2778
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem325_4__ImmUnsignedi81_6,
2779
  Convert__Reg1_3__Tie0_1_1__Reg1_5__Mem325_1__ImmUnsignedi81_0,
2780
  Convert__Reg1_0__Reg1_2__Mem325_5__ImmUnsignedi81_7,
2781
  Convert__Reg1_0__Reg1_2__Reg1_5__Mem645_6__ImmUnsignedi81_7,
2782
  Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6__ImmUnsignedi81_8,
2783
  Convert__Reg1_0__Reg1_2__Reg1_5__Mem325_6__ImmUnsignedi81_7,
2784
  Convert__Reg1_0__Reg1_1__Mem85_2__ImmUnsignedi81_4,
2785
  Convert__Reg1_4__Reg1_3__Mem85_1__ImmUnsignedi81_0,
2786
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem85_5__ImmUnsignedi81_7,
2787
  Convert__Reg1_4__Tie0_1_1__Reg1_6__Reg1_3__Mem85_1__ImmUnsignedi81_0,
2788
  Convert__Reg1_0__Reg1_2__Reg1_5__Mem85_6__ImmUnsignedi81_8,
2789
  Convert__Reg1_4__Reg1_6__Reg1_3__Mem85_1__ImmUnsignedi81_0,
2790
  Convert__Mem1285_2__Reg1_1__Reg1_0,
2791
  Convert__Mem2565_2__Reg1_1__Reg1_0,
2792
  Convert__Mem1285_0__Reg1_1__Reg1_2,
2793
  Convert__Mem2565_0__Reg1_1__Reg1_2,
2794
  Convert__Reg1_0__Reg1_2__Reg1_4,
2795
  Convert__Mem645_1__Reg1_3__Reg1_0,
2796
  Convert__Mem645_0__Reg1_2__Reg1_4,
2797
  Convert__Reg1_2__Tie0_3_3__Reg1_4__Reg1_1__Reg1_0,
2798
  Convert__Mem325_1__Reg1_3__Reg1_0,
2799
  Convert__Mem325_0__Reg1_2__Reg1_4,
2800
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem85_4,
2801
  Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem85_0,
2802
  Convert__Reg1_0__Reg1_2__Mem85_5,
2803
  Convert__Reg1_1__Reg1_3__Mem85_0,
2804
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem165_4,
2805
  Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem165_0,
2806
  Convert__Reg1_0__Reg1_2__Mem165_5,
2807
  Convert__Reg1_1__Reg1_3__Mem165_0,
2808
  Convert__Reg1_2__Reg1_1__Reg1_0__imm_95_17,
2809
  Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_17,
2810
  Convert__Reg1_0__Reg1_1__Mem1285_2__imm_95_17,
2811
  Convert__Reg1_0__Reg1_1__Mem2565_2__imm_95_17,
2812
  Convert__Reg1_0__Reg1_1__Mem5125_2__imm_95_17,
2813
  Convert__Reg1_2__Reg1_1__Mem1285_0__imm_95_17,
2814
  Convert__Reg1_2__Reg1_1__Mem2565_0__imm_95_17,
2815
  Convert__Reg1_2__Reg1_1__Mem5125_0__imm_95_17,
2816
  Convert__Reg1_2__Reg1_1__Reg1_0__imm_95_1,
2817
  Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_1,
2818
  Convert__Reg1_0__Reg1_1__Mem1285_2__imm_95_1,
2819
  Convert__Reg1_0__Reg1_1__Mem2565_2__imm_95_1,
2820
  Convert__Reg1_0__Reg1_1__Mem5125_2__imm_95_1,
2821
  Convert__Reg1_2__Reg1_1__Mem1285_0__imm_95_1,
2822
  Convert__Reg1_2__Reg1_1__Mem2565_0__imm_95_1,
2823
  Convert__Reg1_2__Reg1_1__Mem5125_0__imm_95_1,
2824
  Convert__Reg1_2__Reg1_1__Reg1_0__imm_95_16,
2825
  Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16,
2826
  Convert__Reg1_0__Reg1_1__Mem1285_2__imm_95_16,
2827
  Convert__Reg1_0__Reg1_1__Mem2565_2__imm_95_16,
2828
  Convert__Reg1_0__Reg1_1__Mem5125_2__imm_95_16,
2829
  Convert__Reg1_2__Reg1_1__Mem1285_0__imm_95_16,
2830
  Convert__Reg1_2__Reg1_1__Mem2565_0__imm_95_16,
2831
  Convert__Reg1_2__Reg1_1__Mem5125_0__imm_95_16,
2832
  Convert__Reg1_2__Reg1_1__Reg1_0__imm_95_0,
2833
  Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0,
2834
  Convert__Reg1_0__Reg1_1__Mem1285_2__imm_95_0,
2835
  Convert__Reg1_0__Reg1_1__Mem2565_2__imm_95_0,
2836
  Convert__Reg1_0__Reg1_1__Mem5125_2__imm_95_0,
2837
  Convert__Reg1_2__Reg1_1__Mem1285_0__imm_95_0,
2838
  Convert__Reg1_2__Reg1_1__Mem2565_0__imm_95_0,
2839
  Convert__Reg1_2__Reg1_1__Mem5125_0__imm_95_0,
2840
  Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmUnsignedi81_4,
2841
  Convert__Reg1_0__Reg1_1__Reg1_2__Mem1285_3__ImmUnsignedi81_4,
2842
  Convert__Reg1_0__Reg1_1__Mem1285_2__Reg1_3__ImmUnsignedi81_4,
2843
  Convert__Reg1_0__Reg1_1__Reg1_2__Mem2565_3__ImmUnsignedi81_4,
2844
  Convert__Reg1_0__Reg1_1__Mem2565_2__Reg1_3__ImmUnsignedi81_4,
2845
  Convert__Reg1_4__Reg1_3__Reg1_2__Reg1_1__ImmUnsignedi81_0,
2846
  Convert__Reg1_4__Reg1_3__Mem1285_2__Reg1_1__ImmUnsignedi81_0,
2847
  Convert__Reg1_4__Reg1_3__Mem2565_2__Reg1_1__ImmUnsignedi81_0,
2848
  Convert__Reg1_4__Reg1_3__Reg1_2__Mem1285_1__ImmUnsignedi81_0,
2849
  Convert__Reg1_4__Reg1_3__Reg1_2__Mem2565_1__ImmUnsignedi81_0,
2850
  Convert__Reg1_0__Reg1_1__GR32orGR641_2__ImmUnsignedi81_3,
2851
  Convert__Reg1_0__Reg1_1__Mem85_2__ImmUnsignedi81_3,
2852
  Convert__Reg1_3__Reg1_2__GR32orGR641_1__ImmUnsignedi81_0,
2853
  Convert__Reg1_3__Reg1_2__Mem85_1__ImmUnsignedi81_0,
2854
  Convert__Reg1_0__Reg1_1__Mem165_2__ImmUnsignedi81_3,
2855
  Convert__Reg1_3__Reg1_2__Mem165_1__ImmUnsignedi81_0,
2856
  Convert__Mem165_1__Reg1_3__Reg1_0,
2857
  Convert__Mem165_0__Reg1_2__Reg1_4,
2858
  Convert__Reg1_2__Mem1285_1__Reg1_0,
2859
  Convert__Reg1_0__Mem1285_1__Reg1_2,
2860
  Convert__Reg1_3__Mem128_RC128X5_1__Tie0_4_4__Reg1_0,
2861
  Convert__Reg1_3__Mem256_RC256X5_1__Tie0_4_4__Reg1_0,
2862
  Convert__Reg1_3__Mem512_RC5125_1__Tie0_4_4__Reg1_0,
2863
  Convert__Reg1_2__Mem128_RC128X5_0__Tie0_3_3__Reg1_4,
2864
  Convert__Reg1_2__Mem256_RC256X5_0__Tie0_3_3__Reg1_4,
2865
  Convert__Reg1_2__Mem512_RC5125_0__Tie0_3_3__Reg1_4,
2866
  Convert__Reg1_3__Mem256_RC128X5_1__Tie0_4_4__Reg1_0,
2867
  Convert__Reg1_3__Mem512_RC256X5_1__Tie0_4_4__Reg1_0,
2868
  Convert__Reg1_2__Mem256_RC128X5_0__Tie0_3_3__Reg1_4,
2869
  Convert__Reg1_2__Mem512_RC256X5_0__Tie0_3_3__Reg1_4,
2870
  Convert__Reg1_3__Mem128_RC256X5_1__Tie0_4_4__Reg1_0,
2871
  Convert__Reg1_3__Mem64_RC128X5_1__Tie0_4_4__Reg1_0,
2872
  Convert__Reg1_3__Mem256_RC5125_1__Tie0_4_4__Reg1_0,
2873
  Convert__Reg1_2__Mem128_RC256X5_0__Tie0_3_3__Reg1_4,
2874
  Convert__Reg1_2__Mem256_RC5125_0__Tie0_3_3__Reg1_4,
2875
  Convert__Reg1_2__Mem64_RC128X5_0__Tie0_3_3__Reg1_4,
2876
  Convert__Reg1_0__Reg1_1__Tie0_1_1__Tie1_2_2,
2877
  Convert__Reg1_1__Reg1_0__Tie0_2_2__Tie1_1_1,
2878
  Convert__AbsMem161_0,
2879
  Convert__Reg1_1__Tie0_2_2,
2880
  Convert__regEAX__regEAX__Tie0_1_1__Tie1_1_1,
2881
  CVT_NUM_SIGNATURES
2882
};
2883
2884
} // end anonymous namespace
2885
2886
static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][13] = {
2887
  // Convert_NoOperands
2888
  { CVT_Done },
2889
  // Convert__imm_95_10
2890
  { CVT_imm_95_10, 0, CVT_Done },
2891
  // Convert__Imm1_0
2892
  { CVT_95_addImmOperands, 1, CVT_Done },
2893
  // Convert__Imm1_1
2894
  { CVT_95_addImmOperands, 2, CVT_Done },
2895
  // Convert__regAX__Tie0_1_1__ImmSExti16i81_1
2896
  { CVT_regAX, 0, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2897
  // Convert__regEAX__Tie0_1_1__ImmSExti32i81_1
2898
  { CVT_regEAX, 0, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2899
  // Convert__regRAX__Tie0_1_1__ImmSExti64i81_1
2900
  { CVT_regRAX, 0, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2901
  // Convert__ImmSExti64i321_1
2902
  { CVT_95_addImmOperands, 2, CVT_Done },
2903
  // Convert__Reg1_0__Tie0_1_1__Reg1_1
2904
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
2905
  // Convert__Reg1_0__Tie0_1_1__ImmSExti16i81_1
2906
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2907
  // Convert__Reg1_0__Tie0_1_1__Imm1_1
2908
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2909
  // Convert__Reg1_0__Tie0_1_1__Mem165_1
2910
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
2911
  // Convert__Reg1_0__Tie0_1_1__ImmSExti32i81_1
2912
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2913
  // Convert__Reg1_0__Tie0_1_1__Mem325_1
2914
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
2915
  // Convert__Reg1_0__Tie0_1_1__ImmSExti64i81_1
2916
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2917
  // Convert__Reg1_0__Tie0_1_1__ImmSExti64i321_1
2918
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2919
  // Convert__Reg1_0__Tie0_1_1__Mem645_1
2920
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
2921
  // Convert__Reg1_0__Tie0_1_1__Mem85_1
2922
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
2923
  // Convert__Mem165_0__Reg1_1
2924
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_Done },
2925
  // Convert__Mem165_0__ImmSExti16i81_1
2926
  { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2927
  // Convert__Mem165_0__Imm1_1
2928
  { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2929
  // Convert__Mem325_0__Reg1_1
2930
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_Done },
2931
  // Convert__Mem325_0__ImmSExti32i81_1
2932
  { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2933
  // Convert__Mem325_0__Imm1_1
2934
  { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2935
  // Convert__Mem645_0__Reg1_1
2936
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_Done },
2937
  // Convert__Mem645_0__ImmSExti64i81_1
2938
  { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2939
  // Convert__Mem645_0__ImmSExti64i321_1
2940
  { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2941
  // Convert__Mem85_0__Reg1_1
2942
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_Done },
2943
  // Convert__Mem85_0__Imm1_1
2944
  { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2945
  // Convert__Reg1_1__Tie0_2_2__Reg1_0
2946
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 1, CVT_Done },
2947
  // Convert__Mem85_1__Reg1_0
2948
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
2949
  // Convert__Reg1_1__Tie0_2_2__Imm1_0
2950
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 1, CVT_Done },
2951
  // Convert__Mem85_1__Imm1_0
2952
  { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2953
  // Convert__Reg1_1__Tie0_2_2__Mem85_0
2954
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addMemOperands, 1, CVT_Done },
2955
  // Convert__Mem325_1__Reg1_0
2956
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
2957
  // Convert__regEAX__Tie0_1_1__ImmSExti32i81_0
2958
  { CVT_regEAX, 0, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 1, CVT_Done },
2959
  // Convert__Reg1_1__Tie0_2_2__ImmSExti32i81_0
2960
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 1, CVT_Done },
2961
  // Convert__Mem325_1__ImmSExti32i81_0
2962
  { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2963
  // Convert__Mem325_1__Imm1_0
2964
  { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2965
  // Convert__Reg1_1__Tie0_2_2__Mem325_0
2966
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addMemOperands, 1, CVT_Done },
2967
  // Convert__Mem645_1__Reg1_0
2968
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
2969
  // Convert__regRAX__Tie0_1_1__ImmSExti64i81_0
2970
  { CVT_regRAX, 0, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 1, CVT_Done },
2971
  // Convert__Reg1_1__Tie0_2_2__ImmSExti64i81_0
2972
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 1, CVT_Done },
2973
  // Convert__Mem645_1__ImmSExti64i81_0
2974
  { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2975
  // Convert__ImmSExti64i321_0
2976
  { CVT_95_addImmOperands, 1, CVT_Done },
2977
  // Convert__Reg1_1__Tie0_2_2__ImmSExti64i321_0
2978
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 1, CVT_Done },
2979
  // Convert__Mem645_1__ImmSExti64i321_0
2980
  { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2981
  // Convert__Reg1_1__Tie0_2_2__Mem645_0
2982
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addMemOperands, 1, CVT_Done },
2983
  // Convert__Mem165_1__Reg1_0
2984
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
2985
  // Convert__regAX__Tie0_1_1__ImmSExti16i81_0
2986
  { CVT_regAX, 0, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 1, CVT_Done },
2987
  // Convert__Reg1_1__Tie0_2_2__ImmSExti16i81_0
2988
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 1, CVT_Done },
2989
  // Convert__Mem165_1__ImmSExti16i81_0
2990
  { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2991
  // Convert__Mem165_1__Imm1_0
2992
  { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2993
  // Convert__Reg1_1__Tie0_2_2__Mem165_0
2994
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addMemOperands, 1, CVT_Done },
2995
  // Convert__Reg1_1__Tie0_1_1__Reg1_0
2996
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 1, CVT_Done },
2997
  // Convert__Reg1_1__Tie0_1_1__Mem325_0
2998
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 1, CVT_Done },
2999
  // Convert__Reg1_1__Tie0_1_1__Mem645_0
3000
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 1, CVT_Done },
3001
  // Convert__Reg1_0__Tie0_1_1__Mem1285_1
3002
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
3003
  // Convert__Reg1_1__Tie0_1_1__Mem1285_0
3004
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 1, CVT_Done },
3005
  // Convert__Reg1_1__Reg1_0
3006
  { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
3007
  // Convert__Reg1_0__Reg1_1
3008
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
3009
  // Convert__Reg1_0__Mem1285_1
3010
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_Done },
3011
  // Convert__Reg1_1__Mem1285_0
3012
  { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3013
  // Convert__Reg1_0__Reg1_1__ImmUnsignedi81_2
3014
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3015
  // Convert__Reg1_0__Mem1285_1__ImmUnsignedi81_2
3016
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3017
  // Convert__Reg1_2__Reg1_1__ImmUnsignedi81_0
3018
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3019
  // Convert__Reg1_2__Mem1285_1__ImmUnsignedi81_0
3020
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3021
  // Convert__Reg1_0__Reg1_1__Reg1_2
3022
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
3023
  // Convert__Reg1_0__Reg1_1__Mem325_2
3024
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3025
  // Convert__Reg1_0__Reg1_1__Mem645_2
3026
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3027
  // Convert__Reg1_2__Reg1_1__Reg1_0
3028
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
3029
  // Convert__Reg1_2__Reg1_1__Mem325_0
3030
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3031
  // Convert__Reg1_2__Reg1_1__Mem645_0
3032
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3033
  // Convert__Reg1_0__Reg1_1__Imm1_2
3034
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3035
  // Convert__Reg1_0__Mem325_1__Reg1_2
3036
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_Reg, 3, CVT_Done },
3037
  // Convert__Reg1_0__Mem325_1__Imm1_2
3038
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3039
  // Convert__Reg1_0__Reg1_1__ImmSExti64i321_2
3040
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3041
  // Convert__Reg1_0__Mem645_1__Reg1_2
3042
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_Reg, 3, CVT_Done },
3043
  // Convert__Reg1_0__Mem645_1__ImmSExti64i321_2
3044
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3045
  // Convert__Reg1_2__Mem325_1__Reg1_0
3046
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
3047
  // Convert__Reg1_2__Reg1_1__Imm1_0
3048
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3049
  // Convert__Reg1_2__Mem325_1__Imm1_0
3050
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3051
  // Convert__Reg1_2__Mem645_1__Reg1_0
3052
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
3053
  // Convert__Reg1_2__Reg1_1__ImmSExti64i321_0
3054
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3055
  // Convert__Reg1_2__Mem645_1__ImmSExti64i321_0
3056
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3057
  // Convert__Reg1_0__Mem325_1
3058
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_Done },
3059
  // Convert__Reg1_0__Mem645_1
3060
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_Done },
3061
  // Convert__Reg1_1__Mem325_0
3062
  { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3063
  // Convert__Reg1_1__Mem645_0
3064
  { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3065
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmUnsignedi81_2
3066
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3067
  // Convert__Reg1_0__Tie0_1_1__Mem1285_1__ImmUnsignedi81_2
3068
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3069
  // Convert__Reg1_2__Tie0_1_1__Reg1_1__ImmUnsignedi81_0
3070
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3071
  // Convert__Reg1_2__Tie0_1_1__Mem1285_1__ImmUnsignedi81_0
3072
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3073
  // Convert__Reg1_1__Tie0_2_2__Mem1285_0
3074
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addMemOperands, 1, CVT_Done },
3075
  // Convert__Reg1_2__Tie0_1_1__Reg1_1
3076
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
3077
  // Convert__Reg1_2__Tie0_1_1__Mem1285_1
3078
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
3079
  // Convert__Reg1_0__Mem5_1
3080
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_Done },
3081
  // Convert__Reg1_1__Mem5_0
3082
  { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3083
  // Convert__Mem1285_1__Reg1_0
3084
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
3085
  // Convert__Mem1285_0__Reg1_1
3086
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_Done },
3087
  // Convert__Mem5_1__Reg1_0
3088
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
3089
  // Convert__Mem5_0__Reg1_1
3090
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_Done },
3091
  // Convert__Reg1_0__Mem165_1
3092
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_Done },
3093
  // Convert__Reg1_1__Mem165_0
3094
  { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3095
  // Convert__Reg1_0__Tie0_1_1
3096
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done },
3097
  // Convert__Reg1_0__ImmUnsignedi81_1
3098
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3099
  // Convert__Mem165_0__ImmUnsignedi81_1
3100
  { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
3101
  // Convert__Mem325_0__ImmUnsignedi81_1
3102
  { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
3103
  // Convert__Mem645_0__ImmUnsignedi81_1
3104
  { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
3105
  // Convert__Reg1_0__Tie0_1_1__ImmUnsignedi81_1
3106
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
3107
  // Convert__Reg1_1__Tie0_2_2__ImmUnsignedi81_0
3108
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 1, CVT_Done },
3109
  // Convert__Mem325_1__ImmUnsignedi81_0
3110
  { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3111
  // Convert__Mem645_1__ImmUnsignedi81_0
3112
  { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3113
  // Convert__Mem165_1__ImmUnsignedi81_0
3114
  { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3115
  // Convert__Reg1_1__ImmUnsignedi81_0
3116
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3117
  // Convert__Reg1_0
3118
  { CVT_95_Reg, 1, CVT_Done },
3119
  // Convert__AbsMem1_0
3120
  { CVT_95_addAbsMemOperands, 1, CVT_Done },
3121
  // Convert__Mem165_0
3122
  { CVT_95_addMemOperands, 1, CVT_Done },
3123
  // Convert__Mem325_0
3124
  { CVT_95_addMemOperands, 1, CVT_Done },
3125
  // Convert__Mem645_0
3126
  { CVT_95_addMemOperands, 1, CVT_Done },
3127
  // Convert__Mem5_0
3128
  { CVT_95_addMemOperands, 1, CVT_Done },
3129
  // Convert__Imm1_1__Imm1_0
3130
  { CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3131
  // Convert__Reg1_1
3132
  { CVT_95_Reg, 2, CVT_Done },
3133
  // Convert__Mem325_1
3134
  { CVT_95_addMemOperands, 2, CVT_Done },
3135
  // Convert__Mem645_1
3136
  { CVT_95_addMemOperands, 2, CVT_Done },
3137
  // Convert__Mem165_1
3138
  { CVT_95_addMemOperands, 2, CVT_Done },
3139
  // Convert__Mem85_0
3140
  { CVT_95_addMemOperands, 1, CVT_Done },
3141
  // Convert__Reg1_0__Tie0_1_1__Reg1_0
3142
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 1, CVT_Done },
3143
  // Convert__Reg1_1__Tie0_1_1__Mem165_0
3144
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 1, CVT_Done },
3145
  // Convert__regAX__ImmSExti16i81_1
3146
  { CVT_regAX, 0, CVT_95_addImmOperands, 2, CVT_Done },
3147
  // Convert__regEAX__ImmSExti32i81_1
3148
  { CVT_regEAX, 0, CVT_95_addImmOperands, 2, CVT_Done },
3149
  // Convert__regRAX__ImmSExti64i81_1
3150
  { CVT_regRAX, 0, CVT_95_addImmOperands, 2, CVT_Done },
3151
  // Convert__Reg1_0__ImmSExti16i81_1
3152
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3153
  // Convert__Reg1_0__Imm1_1
3154
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3155
  // Convert__Reg1_0__ImmSExti32i81_1
3156
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3157
  // Convert__Reg1_0__ImmSExti64i81_1
3158
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3159
  // Convert__Reg1_0__ImmSExti64i321_1
3160
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3161
  // Convert__Reg1_0__Mem85_1
3162
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_Done },
3163
  // Convert__Reg1_1__Imm1_0
3164
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3165
  // Convert__Reg1_1__Mem85_0
3166
  { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3167
  // Convert__regEAX__ImmSExti32i81_0
3168
  { CVT_regEAX, 0, CVT_95_addImmOperands, 1, CVT_Done },
3169
  // Convert__Reg1_1__ImmSExti32i81_0
3170
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3171
  // Convert__regRAX__ImmSExti64i81_0
3172
  { CVT_regRAX, 0, CVT_95_addImmOperands, 1, CVT_Done },
3173
  // Convert__Reg1_1__ImmSExti64i81_0
3174
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3175
  // Convert__Reg1_1__ImmSExti64i321_0
3176
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3177
  // Convert__DstIdx161_1__SrcIdx162_0
3178
  { CVT_95_addDstIdxOperands, 2, CVT_95_addSrcIdxOperands, 1, CVT_Done },
3179
  // Convert__DstIdx321_1__SrcIdx322_0
3180
  { CVT_95_addDstIdxOperands, 2, CVT_95_addSrcIdxOperands, 1, CVT_Done },
3181
  // Convert__DstIdx641_1__SrcIdx642_0
3182
  { CVT_95_addDstIdxOperands, 2, CVT_95_addSrcIdxOperands, 1, CVT_Done },
3183
  // Convert__DstIdx81_1__SrcIdx82_0
3184
  { CVT_95_addDstIdxOperands, 2, CVT_95_addSrcIdxOperands, 1, CVT_Done },
3185
  // Convert__DstIdx81_0__SrcIdx82_1
3186
  { CVT_95_addDstIdxOperands, 1, CVT_95_addSrcIdxOperands, 2, CVT_Done },
3187
  // Convert__Reg1_0__Tie0_1_1__Mem645_1__ImmUnsignedi81_2
3188
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3189
  // Convert__Reg1_2__Tie0_1_1__Mem645_1__ImmUnsignedi81_0
3190
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3191
  // Convert__DstIdx321_0__SrcIdx322_1
3192
  { CVT_95_addDstIdxOperands, 1, CVT_95_addSrcIdxOperands, 2, CVT_Done },
3193
  // Convert__DstIdx641_0__SrcIdx642_1
3194
  { CVT_95_addDstIdxOperands, 1, CVT_95_addSrcIdxOperands, 2, CVT_Done },
3195
  // Convert__Reg1_0__Tie0_1_1__Mem325_1__ImmUnsignedi81_2
3196
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3197
  // Convert__Reg1_2__Tie0_1_1__Mem325_1__ImmUnsignedi81_0
3198
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3199
  // Convert__DstIdx161_0__SrcIdx162_1
3200
  { CVT_95_addDstIdxOperands, 1, CVT_95_addSrcIdxOperands, 2, CVT_Done },
3201
  // Convert__regAX__ImmSExti16i81_0
3202
  { CVT_regAX, 0, CVT_95_addImmOperands, 1, CVT_Done },
3203
  // Convert__Reg1_1__ImmSExti16i81_0
3204
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3205
  // Convert__Mem1285_0
3206
  { CVT_95_addMemOperands, 1, CVT_Done },
3207
  // Convert__Mem85_1
3208
  { CVT_95_addMemOperands, 2, CVT_Done },
3209
  // Convert__Imm1_0__Imm1_1
3210
  { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
3211
  // Convert__GR32orGR641_2__Reg1_1__ImmUnsignedi81_0
3212
  { CVT_95_addGR32orGR64Operands, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3213
  // Convert__Mem325_2__Reg1_1__ImmUnsignedi81_0
3214
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3215
  // Convert__GR32orGR641_0__Reg1_1__ImmUnsignedi81_2
3216
  { CVT_95_addGR32orGR64Operands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3217
  // Convert__Mem325_0__Reg1_1__ImmUnsignedi81_2
3218
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3219
  // Convert__Reg1_0__Tie0_1_1__ImmUnsignedi81_1__ImmUnsignedi81_2
3220
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3221
  // Convert__Reg1_2__Tie0_3_3__ImmUnsignedi81_1__ImmUnsignedi81_0
3222
  { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3223
  // Convert__regST1
3224
  { CVT_regST1, 0, CVT_Done },
3225
  // Convert__regST0
3226
  { CVT_regST0, 0, CVT_Done },
3227
  // Convert__Mem805_0
3228
  { CVT_95_addMemOperands, 1, CVT_Done },
3229
  // Convert__Reg1_0__Reg1_0__ImmSExti16i81_1
3230
  { CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3231
  // Convert__Reg1_0__Reg1_0__Imm1_1
3232
  { CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3233
  // Convert__Reg1_0__Reg1_0__ImmSExti32i81_1
3234
  { CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3235
  // Convert__Reg1_0__Reg1_0__ImmSExti64i81_1
3236
  { CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3237
  // Convert__Reg1_0__Reg1_0__ImmSExti64i321_1
3238
  { CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3239
  // Convert__Reg1_0__Reg1_1__ImmSExti16i81_2
3240
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3241
  // Convert__Reg1_0__Mem165_1__ImmSExti16i81_2
3242
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3243
  // Convert__Reg1_0__Mem165_1__Imm1_2
3244
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3245
  // Convert__Reg1_0__Reg1_1__ImmSExti32i81_2
3246
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3247
  // Convert__Reg1_0__Mem325_1__ImmSExti32i81_2
3248
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3249
  // Convert__Reg1_0__Reg1_1__ImmSExti64i81_2
3250
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3251
  // Convert__Reg1_0__Mem645_1__ImmSExti64i81_2
3252
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3253
  // Convert__Reg1_1__Reg1_1__ImmSExti32i81_0
3254
  { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3255
  // Convert__Reg1_1__Reg1_1__Imm1_0
3256
  { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3257
  // Convert__Reg1_2__Reg1_1__ImmSExti32i81_0
3258
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3259
  // Convert__Reg1_2__Mem325_1__ImmSExti32i81_0
3260
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3261
  // Convert__Reg1_1__Reg1_1__ImmSExti64i81_0
3262
  { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3263
  // Convert__Reg1_1__Reg1_1__ImmSExti64i321_0
3264
  { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3265
  // Convert__Reg1_2__Reg1_1__ImmSExti64i81_0
3266
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3267
  // Convert__Reg1_2__Mem645_1__ImmSExti64i81_0
3268
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3269
  // Convert__Reg1_1__Reg1_1__ImmSExti16i81_0
3270
  { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3271
  // Convert__Reg1_2__Reg1_1__ImmSExti16i81_0
3272
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3273
  // Convert__Reg1_2__Mem165_1__ImmSExti16i81_0
3274
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3275
  // Convert__Reg1_2__Mem165_1__Imm1_0
3276
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3277
  // Convert__ImmUnsignedi81_1
3278
  { CVT_95_addImmOperands, 2, CVT_Done },
3279
  // Convert__ImmUnsignedi81_0
3280
  { CVT_95_addImmOperands, 1, CVT_Done },
3281
  // Convert__DstIdx161_0
3282
  { CVT_95_addDstIdxOperands, 1, CVT_Done },
3283
  // Convert__DstIdx321_0
3284
  { CVT_95_addDstIdxOperands, 1, CVT_Done },
3285
  // Convert__DstIdx81_0
3286
  { CVT_95_addDstIdxOperands, 1, CVT_Done },
3287
  // Convert__DstIdx81_1
3288
  { CVT_95_addDstIdxOperands, 2, CVT_Done },
3289
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmUnsignedi81_2__ImmUnsignedi81_3
3290
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3291
  // Convert__Reg1_3__Tie0_4_4__Reg1_2__ImmUnsignedi81_1__ImmUnsignedi81_0
3292
  { CVT_95_Reg, 4, CVT_Tied, Tie0_4_4, CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3293
  // Convert__DstIdx321_1
3294
  { CVT_95_addDstIdxOperands, 2, CVT_Done },
3295
  // Convert__DstIdx161_1
3296
  { CVT_95_addDstIdxOperands, 2, CVT_Done },
3297
  // Convert__Mem5_1
3298
  { CVT_95_addMemOperands, 2, CVT_Done },
3299
  // Convert__SrcIdx162_0
3300
  { CVT_95_addSrcIdxOperands, 1, CVT_Done },
3301
  // Convert__SrcIdx322_0
3302
  { CVT_95_addSrcIdxOperands, 1, CVT_Done },
3303
  // Convert__SrcIdx642_0
3304
  { CVT_95_addSrcIdxOperands, 1, CVT_Done },
3305
  // Convert__SrcIdx82_0
3306
  { CVT_95_addSrcIdxOperands, 1, CVT_Done },
3307
  // Convert__SrcIdx82_1
3308
  { CVT_95_addSrcIdxOperands, 2, CVT_Done },
3309
  // Convert__SrcIdx162_1
3310
  { CVT_95_addSrcIdxOperands, 2, CVT_Done },
3311
  // Convert__SrcIdx322_1
3312
  { CVT_95_addSrcIdxOperands, 2, CVT_Done },
3313
  // Convert__SrcIdx642_1
3314
  { CVT_95_addSrcIdxOperands, 2, CVT_Done },
3315
  // Convert__MemOffs16_82_1
3316
  { CVT_95_addMemOffsOperands, 2, CVT_Done },
3317
  // Convert__MemOffs32_82_1
3318
  { CVT_95_addMemOffsOperands, 2, CVT_Done },
3319
  // Convert__MemOffs16_162_1
3320
  { CVT_95_addMemOffsOperands, 2, CVT_Done },
3321
  // Convert__MemOffs32_162_1
3322
  { CVT_95_addMemOffsOperands, 2, CVT_Done },
3323
  // Convert__MemOffs16_322_1
3324
  { CVT_95_addMemOffsOperands, 2, CVT_Done },
3325
  // Convert__MemOffs32_322_1
3326
  { CVT_95_addMemOffsOperands, 2, CVT_Done },
3327
  // Convert__MemOffs32_642_1
3328
  { CVT_95_addMemOffsOperands, 2, CVT_Done },
3329
  // Convert__MemOffs16_162_0
3330
  { CVT_95_addMemOffsOperands, 1, CVT_Done },
3331
  // Convert__MemOffs16_322_0
3332
  { CVT_95_addMemOffsOperands, 1, CVT_Done },
3333
  // Convert__MemOffs16_82_0
3334
  { CVT_95_addMemOffsOperands, 1, CVT_Done },
3335
  // Convert__MemOffs32_162_0
3336
  { CVT_95_addMemOffsOperands, 1, CVT_Done },
3337
  // Convert__MemOffs32_322_0
3338
  { CVT_95_addMemOffsOperands, 1, CVT_Done },
3339
  // Convert__MemOffs32_642_0
3340
  { CVT_95_addMemOffsOperands, 1, CVT_Done },
3341
  // Convert__MemOffs32_82_0
3342
  { CVT_95_addMemOffsOperands, 1, CVT_Done },
3343
  // Convert__MemOffs64_82_1
3344
  { CVT_95_addMemOffsOperands, 2, CVT_Done },
3345
  // Convert__MemOffs64_162_1
3346
  { CVT_95_addMemOffsOperands, 2, CVT_Done },
3347
  // Convert__MemOffs64_322_1
3348
  { CVT_95_addMemOffsOperands, 2, CVT_Done },
3349
  // Convert__MemOffs64_642_1
3350
  { CVT_95_addMemOffsOperands, 2, CVT_Done },
3351
  // Convert__MemOffs64_162_0
3352
  { CVT_95_addMemOffsOperands, 1, CVT_Done },
3353
  // Convert__MemOffs64_322_0
3354
  { CVT_95_addMemOffsOperands, 1, CVT_Done },
3355
  // Convert__MemOffs64_642_0
3356
  { CVT_95_addMemOffsOperands, 1, CVT_Done },
3357
  // Convert__MemOffs64_82_0
3358
  { CVT_95_addMemOffsOperands, 1, CVT_Done },
3359
  // Convert__Reg1_0__Mem5125_1
3360
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_Done },
3361
  // Convert__Reg1_1__Mem5125_0
3362
  { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3363
  // Convert__GR32orGR641_1__Reg1_0
3364
  { CVT_95_addGR32orGR64Operands, 2, CVT_95_Reg, 1, CVT_Done },
3365
  // Convert__GR32orGR641_0__Reg1_1
3366
  { CVT_95_addGR32orGR64Operands, 1, CVT_95_Reg, 2, CVT_Done },
3367
  // Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_17
3368
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 1, CVT_imm_95_17, 0, CVT_Done },
3369
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_17
3370
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_imm_95_17, 0, CVT_Done },
3371
  // Convert__Reg1_0__Tie0_1_1__Mem1285_1__imm_95_17
3372
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_imm_95_17, 0, CVT_Done },
3373
  // Convert__Reg1_1__Tie0_2_2__Mem1285_0__imm_95_17
3374
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addMemOperands, 1, CVT_imm_95_17, 0, CVT_Done },
3375
  // Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_1
3376
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_Done },
3377
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_1
3378
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_imm_95_1, 0, CVT_Done },
3379
  // Convert__Reg1_0__Tie0_1_1__Mem1285_1__imm_95_1
3380
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_imm_95_1, 0, CVT_Done },
3381
  // Convert__Reg1_1__Tie0_2_2__Mem1285_0__imm_95_1
3382
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addMemOperands, 1, CVT_imm_95_1, 0, CVT_Done },
3383
  // Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_16
3384
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 1, CVT_imm_95_16, 0, CVT_Done },
3385
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_16
3386
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_imm_95_16, 0, CVT_Done },
3387
  // Convert__Reg1_0__Tie0_1_1__Mem1285_1__imm_95_16
3388
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_imm_95_16, 0, CVT_Done },
3389
  // Convert__Reg1_1__Tie0_2_2__Mem1285_0__imm_95_16
3390
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addMemOperands, 1, CVT_imm_95_16, 0, CVT_Done },
3391
  // Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_0
3392
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done },
3393
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_0
3394
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
3395
  // Convert__Reg1_0__Tie0_1_1__Mem1285_1__imm_95_0
3396
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_imm_95_0, 0, CVT_Done },
3397
  // Convert__Reg1_1__Tie0_2_2__Mem1285_0__imm_95_0
3398
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addMemOperands, 1, CVT_imm_95_0, 0, CVT_Done },
3399
  // Convert__Mem85_2__Reg1_1__ImmUnsignedi81_0
3400
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3401
  // Convert__Mem85_0__Reg1_1__ImmUnsignedi81_2
3402
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3403
  // Convert__Mem645_2__Reg1_1__ImmUnsignedi81_0
3404
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3405
  // Convert__Mem645_0__Reg1_1__ImmUnsignedi81_2
3406
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3407
  // Convert__Mem165_2__Reg1_1__ImmUnsignedi81_0
3408
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3409
  // Convert__Mem165_0__Reg1_1__ImmUnsignedi81_2
3410
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3411
  // Convert__Reg1_0__Tie0_1_1__GR32orGR641_1__ImmUnsignedi81_2
3412
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addGR32orGR64Operands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3413
  // Convert__Reg1_0__Tie0_1_1__Mem85_1__ImmUnsignedi81_2
3414
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3415
  // Convert__Reg1_2__Tie0_1_1__GR32orGR641_1__ImmUnsignedi81_0
3416
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addGR32orGR64Operands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3417
  // Convert__Reg1_2__Tie0_1_1__Mem85_1__ImmUnsignedi81_0
3418
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3419
  // Convert__Reg1_0__Tie0_1_1__Mem165_1__ImmUnsignedi81_2
3420
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3421
  // Convert__Reg1_2__Tie0_1_1__Mem165_1__ImmUnsignedi81_0
3422
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3423
  // Convert__Reg1_0__Mem645_1__ImmUnsignedi81_2
3424
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3425
  // Convert__Reg1_2__Mem645_1__ImmUnsignedi81_0
3426
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3427
  // Convert__Reg1_1__Tie0_1_1__ImmUnsignedi81_0
3428
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 1, CVT_Done },
3429
  // Convert__ImmSExti64i81_0
3430
  { CVT_95_addImmOperands, 1, CVT_Done },
3431
  // Convert__ImmSExti16i81_0
3432
  { CVT_95_addImmOperands, 1, CVT_Done },
3433
  // Convert__ImmSExti32i81_0
3434
  { CVT_95_addImmOperands, 1, CVT_Done },
3435
  // Convert__Mem85_0__ImmUnsignedi81_1
3436
  { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
3437
  // Convert__Reg1_1__Tie0_1_1
3438
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_Done },
3439
  // Convert__Mem85_1__ImmUnsignedi81_0
3440
  { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3441
  // Convert__Reg1_0__Mem325_1__ImmUnsignedi81_2
3442
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3443
  // Convert__Reg1_2__Mem325_1__ImmUnsignedi81_0
3444
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3445
  // Convert__DstIdx641_0
3446
  { CVT_95_addDstIdxOperands, 1, CVT_Done },
3447
  // Convert__DstIdx641_1
3448
  { CVT_95_addDstIdxOperands, 2, CVT_Done },
3449
  // Convert__Mem325_2__Reg1_1
3450
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_Done },
3451
  // Convert__Mem645_2__Reg1_1
3452
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_Done },
3453
  // Convert__Mem165_2__Reg1_1
3454
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_Done },
3455
  // Convert__GR32orGR641_0
3456
  { CVT_95_addGR32orGR64Operands, 1, CVT_Done },
3457
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem1285_2
3458
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3459
  // Convert__Reg1_2__Tie0_1_1__Reg1_1__Mem1285_0
3460
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3461
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem1285_5
3462
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3463
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__Mem1285_0
3464
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3465
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem1285_6
3466
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3467
  // Convert__Reg1_0__Reg1_1__Mem1285_2
3468
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3469
  // Convert__Reg1_0__Reg1_1__Mem2565_2
3470
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3471
  // Convert__Reg1_0__Reg1_1__Mem5125_2
3472
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3473
  // Convert__Reg1_2__Reg1_1__Mem1285_0
3474
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3475
  // Convert__Reg1_2__Reg1_1__Mem2565_0
3476
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3477
  // Convert__Reg1_2__Reg1_1__Mem5125_0
3478
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3479
  // Convert__Reg1_0__Reg1_1__Reg1_2__AVX512RC1_3
3480
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addAVX512RCOperands, 4, CVT_Done },
3481
  // Convert__Reg1_3__Reg1_2__Reg1_1__AVX512RC1_0
3482
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addAVX512RCOperands, 1, CVT_Done },
3483
  // Convert__Reg1_3__Reg1_2__Mem645_0
3484
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3485
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5
3486
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_Done },
3487
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__Reg1_0
3488
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
3489
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem2565_5
3490
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3491
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem5125_5
3492
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3493
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__Mem2565_0
3494
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3495
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__Mem5125_0
3496
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3497
  // Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6
3498
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_Done },
3499
  // Convert__Reg1_0__Reg1_2__Reg1_5__Mem1285_6
3500
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3501
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem645_5
3502
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3503
  // Convert__Reg1_2__Reg1_4__Reg1_1__Reg1_0
3504
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
3505
  // Convert__Reg1_0__Reg1_2__Reg1_5__Mem2565_6
3506
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3507
  // Convert__Reg1_0__Reg1_2__Reg1_5__Mem5125_6
3508
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3509
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5__AVX512RC1_6
3510
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addAVX512RCOperands, 7, CVT_Done },
3511
  // Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Reg1_1__AVX512RC1_0
3512
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addAVX512RCOperands, 1, CVT_Done },
3513
  // Convert__Reg1_2__Reg1_4__Reg1_1__Mem1285_0
3514
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3515
  // Convert__Reg1_2__Reg1_4__Reg1_1__Mem2565_0
3516
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3517
  // Convert__Reg1_2__Reg1_4__Reg1_1__Mem5125_0
3518
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3519
  // Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem645_0
3520
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3521
  // Convert__Reg1_0__Reg1_2__Reg1_5__Mem645_6
3522
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3523
  // Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6__AVX512RC1_7
3524
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addAVX512RCOperands, 8, CVT_Done },
3525
  // Convert__Reg1_3__Reg1_5__Reg1_2__Reg1_1__AVX512RC1_0
3526
  { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addAVX512RCOperands, 1, CVT_Done },
3527
  // Convert__Reg1_3__Reg1_5__Reg1_2__Mem645_0
3528
  { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3529
  // Convert__Reg1_3__Reg1_2__Mem325_0
3530
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3531
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem325_5
3532
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3533
  // Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem325_0
3534
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3535
  // Convert__Reg1_0__Reg1_2__Reg1_5__Mem325_6
3536
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3537
  // Convert__Reg1_3__Reg1_5__Reg1_2__Mem325_0
3538
  { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3539
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__Mem645_0
3540
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3541
  // Convert__Reg1_2__Reg1_4__Reg1_1__Mem645_0
3542
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3543
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__Mem325_0
3544
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3545
  // Convert__Reg1_2__Reg1_4__Reg1_1__Mem325_0
3546
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3547
  // Convert__Reg1_0__Reg1_1__Reg1_2__ImmUnsignedi81_3
3548
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
3549
  // Convert__Reg1_0__Reg1_1__Mem1285_2__ImmUnsignedi81_3
3550
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3551
  // Convert__Reg1_0__Reg1_1__Mem2565_2__ImmUnsignedi81_3
3552
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3553
  // Convert__Reg1_0__Reg1_1__Mem5125_2__ImmUnsignedi81_3
3554
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3555
  // Convert__Reg1_3__Reg1_2__Reg1_1__ImmUnsignedi81_0
3556
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3557
  // Convert__Reg1_3__Reg1_2__Mem1285_1__ImmUnsignedi81_0
3558
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3559
  // Convert__Reg1_3__Reg1_2__Mem2565_1__ImmUnsignedi81_0
3560
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3561
  // Convert__Reg1_3__Reg1_2__Mem5125_1__ImmUnsignedi81_0
3562
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3563
  // Convert__Reg1_0__Reg1_1__Mem325_2__ImmUnsignedi81_4
3564
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 5, CVT_Done },
3565
  // Convert__Reg1_4__Reg1_3__Mem325_1__ImmUnsignedi81_0
3566
  { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3567
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5__ImmUnsignedi81_6
3568
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addImmOperands, 7, CVT_Done },
3569
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem1285_5__ImmUnsignedi81_6
3570
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3571
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem2565_5__ImmUnsignedi81_6
3572
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3573
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem5125_5__ImmUnsignedi81_6
3574
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3575
  // Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Reg1_1__ImmUnsignedi81_0
3576
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3577
  // Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem1285_1__ImmUnsignedi81_0
3578
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3579
  // Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem2565_1__ImmUnsignedi81_0
3580
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3581
  // Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem5125_1__ImmUnsignedi81_0
3582
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3583
  // Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6__ImmUnsignedi81_7
3584
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addImmOperands, 8, CVT_Done },
3585
  // Convert__Reg1_0__Reg1_2__Reg1_5__Mem1285_6__ImmUnsignedi81_7
3586
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
3587
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem325_5__ImmUnsignedi81_7
3588
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 8, CVT_Done },
3589
  // Convert__Reg1_0__Reg1_2__Reg1_5__Mem2565_6__ImmUnsignedi81_7
3590
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
3591
  // Convert__Reg1_0__Reg1_2__Reg1_5__Mem5125_6__ImmUnsignedi81_7
3592
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
3593
  // Convert__Reg1_3__Reg1_5__Reg1_2__Reg1_1__ImmUnsignedi81_0
3594
  { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3595
  // Convert__Reg1_3__Reg1_5__Reg1_2__Mem1285_1__ImmUnsignedi81_0
3596
  { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3597
  // Convert__Reg1_3__Reg1_5__Reg1_2__Mem2565_1__ImmUnsignedi81_0
3598
  { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3599
  // Convert__Reg1_4__Tie0_1_1__Reg1_6__Reg1_3__Mem325_1__ImmUnsignedi81_0
3600
  { CVT_95_Reg, 5, CVT_Tied, Tie0_1_1, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3601
  // Convert__Reg1_3__Reg1_5__Reg1_2__Mem5125_1__ImmUnsignedi81_0
3602
  { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3603
  // Convert__Reg1_0__Reg1_2__Reg1_5__Mem325_6__ImmUnsignedi81_8
3604
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 9, CVT_Done },
3605
  // Convert__Reg1_4__Reg1_6__Reg1_3__Mem325_1__ImmUnsignedi81_0
3606
  { CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3607
  // Convert__Reg1_0__Reg1_1__Mem645_2__ImmUnsignedi81_4
3608
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 5, CVT_Done },
3609
  // Convert__Reg1_4__Reg1_3__Mem645_1__ImmUnsignedi81_0
3610
  { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3611
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem645_5__ImmUnsignedi81_7
3612
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 8, CVT_Done },
3613
  // Convert__Reg1_4__Tie0_1_1__Reg1_6__Reg1_3__Mem645_1__ImmUnsignedi81_0
3614
  { CVT_95_Reg, 5, CVT_Tied, Tie0_1_1, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3615
  // Convert__Reg1_0__Reg1_2__Reg1_5__Mem645_6__ImmUnsignedi81_8
3616
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 9, CVT_Done },
3617
  // Convert__Reg1_4__Reg1_6__Reg1_3__Mem645_1__ImmUnsignedi81_0
3618
  { CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3619
  // Convert__Reg1_0__Reg1_2__Reg1_4__Reg1_5
3620
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_Done },
3621
  // Convert__Reg1_0__Reg1_2__Reg1_4__Mem1285_5
3622
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3623
  // Convert__Reg1_0__Reg1_2__Reg1_4__Mem2565_5
3624
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3625
  // Convert__Reg1_0__Reg1_2__Reg1_4__Mem5125_5
3626
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3627
  // Convert__Reg1_0__Reg1_2__Reg1_4__Mem645_5
3628
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3629
  // Convert__Reg1_0__Reg1_2__Reg1_4__Mem325_5
3630
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3631
  // Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0
3632
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
3633
  // Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3
3634
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
3635
  // Convert__Reg1_0__Reg1_1__Mem1285_2__Reg1_3
3636
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_Reg, 4, CVT_Done },
3637
  // Convert__Reg1_3__Reg1_2__Mem1285_1__Reg1_0
3638
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
3639
  // Convert__Reg1_0__Reg1_1__Mem2565_2__Reg1_3
3640
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_Reg, 4, CVT_Done },
3641
  // Convert__Reg1_3__Reg1_2__Mem2565_1__Reg1_0
3642
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
3643
  // Convert__Reg1_1__Tie0_1_1__Reg1_3__Reg1_0
3644
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_Done },
3645
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4
3646
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_Done },
3647
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem645_4
3648
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_Done },
3649
  // Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem645_0
3650
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3651
  // Convert__Reg1_1__Reg1_3__Reg1_0
3652
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_Done },
3653
  // Convert__Reg1_0__Reg1_2__Reg1_5
3654
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_Done },
3655
  // Convert__Reg1_0__Reg1_2__Mem645_5
3656
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_Done },
3657
  // Convert__Reg1_1__Reg1_3__Mem645_0
3658
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3659
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem1285_4
3660
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_Done },
3661
  // Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem1285_0
3662
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3663
  // Convert__Reg1_0__Reg1_2__Mem1285_5
3664
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_Done },
3665
  // Convert__Reg1_1__Reg1_3__Mem1285_0
3666
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3667
  // Convert__Reg1_0__Mem2565_1
3668
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_Done },
3669
  // Convert__Reg1_1__Mem2565_0
3670
  { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3671
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem2565_4
3672
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_Done },
3673
  // Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem2565_0
3674
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3675
  // Convert__Reg1_0__Reg1_2__Mem2565_5
3676
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_Done },
3677
  // Convert__Reg1_1__Reg1_3__Mem2565_0
3678
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3679
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem325_4
3680
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_Done },
3681
  // Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem325_0
3682
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3683
  // Convert__Reg1_0__Reg1_2__Mem325_5
3684
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_Done },
3685
  // Convert__Reg1_1__Reg1_3__Mem325_0
3686
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3687
  // Convert__Reg1_0__Reg1_1__Reg1_2__ImmUnsignedi81_4
3688
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 5, CVT_Done },
3689
  // Convert__Reg1_4__Reg1_3__Reg1_2__ImmUnsignedi81_0
3690
  { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
3691
  // Convert__Reg1_0__Reg1_2__Reg1_4__Reg1_5__ImmUnsignedi81_6
3692
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addImmOperands, 7, CVT_Done },
3693
  // Convert__Reg1_0__Reg1_2__Reg1_4__Mem1285_5__ImmUnsignedi81_6
3694
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3695
  // Convert__Reg1_0__Reg1_2__Reg1_4__Mem2565_5__ImmUnsignedi81_6
3696
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3697
  // Convert__Reg1_0__Reg1_2__Reg1_4__Mem5125_5__ImmUnsignedi81_6
3698
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3699
  // Convert__Reg1_0__Reg1_2__Reg1_4__Mem645_5__ImmUnsignedi81_7
3700
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 8, CVT_Done },
3701
  // Convert__Reg1_0__Reg1_2__Reg1_4__Reg1_5__ImmUnsignedi81_7
3702
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addImmOperands, 8, CVT_Done },
3703
  // Convert__Reg1_4__Reg1_6__Reg1_3__Reg1_2__ImmUnsignedi81_0
3704
  { CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
3705
  // Convert__Reg1_0__Reg1_2__Reg1_4__Mem325_5__ImmUnsignedi81_7
3706
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 8, CVT_Done },
3707
  // Convert__Reg1_0__Reg1_1__Mem645_2__ImmUnsignedi81_3
3708
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3709
  // Convert__Reg1_3__Reg1_2__Mem645_1__ImmUnsignedi81_0
3710
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3711
  // Convert__Reg1_0__Reg1_2__Reg1_4__Mem645_5__ImmUnsignedi81_6
3712
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3713
  // Convert__Reg1_3__Reg1_5__Reg1_2__Mem645_1__ImmUnsignedi81_0
3714
  { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3715
  // Convert__Reg1_0__Reg1_1__Mem325_2__ImmUnsignedi81_3
3716
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3717
  // Convert__Reg1_3__Reg1_2__Mem325_1__ImmUnsignedi81_0
3718
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3719
  // Convert__Reg1_0__Reg1_2__Reg1_4__Mem325_5__ImmUnsignedi81_6
3720
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3721
  // Convert__Reg1_3__Reg1_5__Reg1_2__Mem325_1__ImmUnsignedi81_0
3722
  { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3723
  // Convert__Reg1_2__Reg1_1
3724
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Done },
3725
  // Convert__Mem2565_1__Reg1_0
3726
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
3727
  // Convert__Mem5125_1__Reg1_0
3728
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
3729
  // Convert__Mem2565_0__Reg1_1
3730
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_Done },
3731
  // Convert__Mem5125_0__Reg1_1
3732
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_Done },
3733
  // Convert__Mem1285_1__Reg1_3__Reg1_0
3734
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_Done },
3735
  // Convert__Mem2565_1__Reg1_3__Reg1_0
3736
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_Done },
3737
  // Convert__Mem5125_1__Reg1_3__Reg1_0
3738
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_Done },
3739
  // Convert__Mem1285_0__Reg1_2__Reg1_4
3740
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_Done },
3741
  // Convert__Mem2565_0__Reg1_2__Reg1_4
3742
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_Done },
3743
  // Convert__Mem5125_0__Reg1_2__Reg1_4
3744
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_Done },
3745
  // Convert__Reg1_2__Mem325_0
3746
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3747
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Mem325_0
3748
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addMemOperands, 1, CVT_Done },
3749
  // Convert__Reg1_2__Reg1_4__Mem325_0
3750
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 1, CVT_Done },
3751
  // Convert__Reg1_0__Reg1_1__AVX512RC1_2
3752
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addAVX512RCOperands, 3, CVT_Done },
3753
  // Convert__Reg1_2__Reg1_1__AVX512RC1_0
3754
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addAVX512RCOperands, 1, CVT_Done },
3755
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem5125_4
3756
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_Done },
3757
  // Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem5125_0
3758
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3759
  // Convert__Reg1_0__Reg1_2__Mem5125_5
3760
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_Done },
3761
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__AVX512RC1_5
3762
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addAVX512RCOperands, 6, CVT_Done },
3763
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__AVX512RC1_0
3764
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addAVX512RCOperands, 1, CVT_Done },
3765
  // Convert__Reg1_1__Reg1_3__Mem5125_0
3766
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3767
  // Convert__Reg1_0__Reg1_2__Reg1_5__AVX512RC1_6
3768
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addAVX512RCOperands, 7, CVT_Done },
3769
  // Convert__Reg1_2__Reg1_4__Reg1_1__AVX512RC1_0
3770
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addAVX512RCOperands, 1, CVT_Done },
3771
  // Convert__Reg1_2__Mem645_0
3772
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3773
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Mem645_0
3774
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addMemOperands, 1, CVT_Done },
3775
  // Convert__Reg1_2__Reg1_4__Mem645_0
3776
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 1, CVT_Done },
3777
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1
3778
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_Done },
3779
  // Convert__Reg1_2__Reg1_4__Reg1_1
3780
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_Done },
3781
  // Convert__Mem1285_2__Reg1_1__ImmUnsignedi81_0
3782
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3783
  // Convert__Mem2565_2__Reg1_1__ImmUnsignedi81_0
3784
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3785
  // Convert__Mem1285_0__Reg1_1__ImmUnsignedi81_2
3786
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3787
  // Convert__Mem2565_0__Reg1_1__ImmUnsignedi81_2
3788
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3789
  // Convert__Reg1_0__Reg1_1__ImmUnsignedi81_3
3790
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_Done },
3791
  // Convert__Reg1_3__Reg1_2__ImmUnsignedi81_0
3792
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
3793
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__ImmUnsignedi81_5
3794
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_Done },
3795
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__ImmUnsignedi81_0
3796
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3797
  // Convert__Mem645_2__Reg1_4__Reg1_1__ImmUnsignedi81_0
3798
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3799
  // Convert__Mem1285_2__Reg1_4__Reg1_1__ImmUnsignedi81_0
3800
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3801
  // Convert__Mem2565_2__Reg1_4__Reg1_1__ImmUnsignedi81_0
3802
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3803
  // Convert__Mem1285_0__Reg1_2__Reg1_4__ImmUnsignedi81_5
3804
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_Done },
3805
  // Convert__Mem2565_0__Reg1_2__Reg1_4__ImmUnsignedi81_5
3806
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_Done },
3807
  // Convert__Mem645_0__Reg1_2__Reg1_4__ImmUnsignedi81_5
3808
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_Done },
3809
  // Convert__Reg1_0__Reg1_2__Reg1_5__ImmUnsignedi81_6
3810
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addImmOperands, 7, CVT_Done },
3811
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__ImmUnsignedi81_6
3812
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addImmOperands, 7, CVT_Done },
3813
  // Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__ImmUnsignedi81_0
3814
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
3815
  // Convert__Reg1_2__Reg1_4__Reg1_1__ImmUnsignedi81_0
3816
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3817
  // Convert__Reg1_0__Reg1_2__Reg1_5__ImmUnsignedi81_7
3818
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addImmOperands, 8, CVT_Done },
3819
  // Convert__Reg1_3__Reg1_5__Reg1_2__ImmUnsignedi81_0
3820
  { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
3821
  // Convert__Reg1_0__Reg1_1__Reg1_3__AVX512RC1_2
3822
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addAVX512RCOperands, 3, CVT_Done },
3823
  // Convert__Reg1_3__Reg1_2__Reg1_0__AVX512RC1_1
3824
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addAVX512RCOperands, 2, CVT_Done },
3825
  // Convert__Reg1_3__Reg1_2__Reg1_1
3826
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Done },
3827
  // Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Reg1_1
3828
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Done },
3829
  // Convert__Reg1_3__Reg1_5__Reg1_2__Reg1_1
3830
  { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Done },
3831
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmUnsignedi81_3
3832
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
3833
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem1285_2__ImmUnsignedi81_3
3834
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3835
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem2565_2__ImmUnsignedi81_3
3836
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3837
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem5125_2__ImmUnsignedi81_3
3838
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3839
  // Convert__Reg1_3__Tie0_1_1__Reg1_2__Reg1_1__ImmUnsignedi81_0
3840
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3841
  // Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem1285_1__ImmUnsignedi81_0
3842
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3843
  // Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem2565_1__ImmUnsignedi81_0
3844
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3845
  // Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem5125_1__ImmUnsignedi81_0
3846
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3847
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem645_2__ImmUnsignedi81_4
3848
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 5, CVT_Done },
3849
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmUnsignedi81_4
3850
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 5, CVT_Done },
3851
  // Convert__Reg1_4__Tie0_1_1__Reg1_3__Reg1_2__ImmUnsignedi81_0
3852
  { CVT_95_Reg, 5, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
3853
  // Convert__Reg1_4__Tie0_1_1__Reg1_3__Mem645_1__ImmUnsignedi81_0
3854
  { CVT_95_Reg, 5, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3855
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Reg1_6__ImmUnsignedi81_7
3856
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addImmOperands, 8, CVT_Done },
3857
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem1285_6__ImmUnsignedi81_7
3858
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
3859
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem2565_6__ImmUnsignedi81_7
3860
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
3861
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem5125_6__ImmUnsignedi81_7
3862
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
3863
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5__ImmUnsignedi81_7
3864
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addImmOperands, 8, CVT_Done },
3865
  // Convert__Reg1_4__Tie0_1_1__Reg1_6__Reg1_3__Reg1_2__ImmUnsignedi81_0
3866
  { CVT_95_Reg, 5, CVT_Tied, Tie0_1_1, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
3867
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem645_6__ImmUnsignedi81_8
3868
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 9, CVT_Done },
3869
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Reg1_6__ImmUnsignedi81_8
3870
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addImmOperands, 9, CVT_Done },
3871
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem325_2__ImmUnsignedi81_4
3872
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 5, CVT_Done },
3873
  // Convert__Reg1_4__Tie0_1_1__Reg1_3__Mem325_1__ImmUnsignedi81_0
3874
  { CVT_95_Reg, 5, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3875
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem325_6__ImmUnsignedi81_8
3876
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 9, CVT_Done },
3877
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem645_2__ImmUnsignedi81_3
3878
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3879
  // Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem645_1__ImmUnsignedi81_0
3880
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3881
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem645_5__ImmUnsignedi81_6
3882
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3883
  // Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem645_1__ImmUnsignedi81_0
3884
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3885
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem645_6__ImmUnsignedi81_7
3886
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
3887
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem325_2__ImmUnsignedi81_3
3888
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3889
  // Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem325_1__ImmUnsignedi81_0
3890
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3891
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem325_5__ImmUnsignedi81_6
3892
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3893
  // Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem325_1__ImmUnsignedi81_0
3894
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3895
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem325_6__ImmUnsignedi81_7
3896
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
3897
  // Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0
3898
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
3899
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2
3900
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
3901
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem2565_2
3902
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3903
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem5125_2
3904
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3905
  // Convert__Reg1_2__Tie0_1_1__Reg1_1__Mem2565_0
3906
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3907
  // Convert__Reg1_2__Tie0_1_1__Reg1_1__Mem5125_0
3908
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3909
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem645_2
3910
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3911
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__AVX512RC1_3
3912
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addAVX512RCOperands, 4, CVT_Done },
3913
  // Convert__Reg1_3__Tie0_1_1__Reg1_2__Reg1_1__AVX512RC1_0
3914
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addAVX512RCOperands, 1, CVT_Done },
3915
  // Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem645_0
3916
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3917
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Reg1_6
3918
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_Done },
3919
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem2565_6
3920
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3921
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem5125_6
3922
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3923
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem645_6
3924
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3925
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Reg1_6__AVX512RC1_7
3926
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addAVX512RCOperands, 8, CVT_Done },
3927
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem325_2
3928
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3929
  // Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem325_0
3930
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3931
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem325_6
3932
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3933
  // Convert__Reg1_2__Tie0_1_1__Reg1_1__Mem645_0
3934
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3935
  // Convert__Reg1_2__Tie0_1_1__Reg1_1__Mem325_0
3936
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3937
  // Convert__Reg1_0__Reg1_1__Reg1_2__Mem1285_3
3938
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemOperands, 4, CVT_Done },
3939
  // Convert__Reg1_0__Reg1_1__Reg1_2__Mem2565_3
3940
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemOperands, 4, CVT_Done },
3941
  // Convert__Reg1_3__Reg1_2__Reg1_1__Mem1285_0
3942
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3943
  // Convert__Reg1_3__Reg1_2__Reg1_1__Mem2565_0
3944
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3945
  // Convert__Reg1_0__Reg1_1__Reg1_2__Mem645_3
3946
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemOperands, 4, CVT_Done },
3947
  // Convert__Reg1_0__Reg1_1__Mem645_2__Reg1_3
3948
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_Reg, 4, CVT_Done },
3949
  // Convert__Reg1_3__Reg1_2__Mem645_1__Reg1_0
3950
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
3951
  // Convert__Reg1_3__Reg1_2__Reg1_1__Mem645_0
3952
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3953
  // Convert__Reg1_0__Reg1_1__Reg1_2__Mem325_3
3954
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemOperands, 4, CVT_Done },
3955
  // Convert__Reg1_0__Reg1_1__Mem325_2__Reg1_3
3956
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_Reg, 4, CVT_Done },
3957
  // Convert__Reg1_3__Reg1_2__Mem325_1__Reg1_0
3958
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
3959
  // Convert__Reg1_3__Reg1_2__Reg1_1__Mem325_0
3960
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3961
  // Convert__Reg1_0__Mem2565_1__ImmUnsignedi81_2
3962
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3963
  // Convert__Reg1_0__Mem5125_1__ImmUnsignedi81_2
3964
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3965
  // Convert__Reg1_0__Mem645_1__ImmUnsignedi81_3
3966
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
3967
  // Convert__Reg1_0__Reg1_2__Reg1_4__ImmUnsignedi81_5
3968
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_Done },
3969
  // Convert__Reg1_0__Reg1_2__Mem1285_4__ImmUnsignedi81_5
3970
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
3971
  // Convert__Reg1_0__Reg1_2__Mem2565_4__ImmUnsignedi81_5
3972
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
3973
  // Convert__Reg1_0__Reg1_2__Mem5125_4__ImmUnsignedi81_5
3974
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
3975
  // Convert__Reg1_0__Reg1_2__Mem645_4__ImmUnsignedi81_6
3976
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 7, CVT_Done },
3977
  // Convert__Reg1_3__Mem645_1__ImmUnsignedi81_0
3978
  { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3979
  // Convert__Reg1_3__Reg1_5__Mem645_1__ImmUnsignedi81_0
3980
  { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3981
  // Convert__Reg1_2__Reg1_4__Mem1285_1__ImmUnsignedi81_0
3982
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3983
  // Convert__Reg1_2__Mem2565_1__ImmUnsignedi81_0
3984
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3985
  // Convert__Reg1_2__Reg1_4__Mem2565_1__ImmUnsignedi81_0
3986
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3987
  // Convert__Reg1_2__Mem5125_1__ImmUnsignedi81_0
3988
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3989
  // Convert__Reg1_2__Reg1_4__Mem5125_1__ImmUnsignedi81_0
3990
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3991
  // Convert__Reg1_0__Mem325_1__ImmUnsignedi81_3
3992
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
3993
  // Convert__Reg1_0__Reg1_2__Mem325_4__ImmUnsignedi81_6
3994
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 7, CVT_Done },
3995
  // Convert__Reg1_3__Mem325_1__ImmUnsignedi81_0
3996
  { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3997
  // Convert__Reg1_3__Reg1_5__Mem325_1__ImmUnsignedi81_0
3998
  { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3999
  // Convert__Reg1_0__Reg1_2__Mem645_4__ImmUnsignedi81_5
4000
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
4001
  // Convert__Reg1_2__Reg1_4__Mem645_1__ImmUnsignedi81_0
4002
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4003
  // Convert__Reg1_0__Reg1_2__Mem325_4__ImmUnsignedi81_5
4004
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
4005
  // Convert__Reg1_2__Reg1_4__Mem325_1__ImmUnsignedi81_0
4006
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4007
  // Convert__Reg1_2__Reg1_0__Tie0_1_1__Mem128_RC1285_1__Tie1_1_1
4008
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Tied, Tie1_1_1, CVT_Done },
4009
  // Convert__Reg1_0__Reg1_2__Tie0_1_1__Mem128_RC1285_1__Tie1_3_3
4010
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Tied, Tie1_3_3, CVT_Done },
4011
  // Convert__Reg1_2__Reg1_0__Tie0_1_1__Mem256_RC1285_1__Tie1_1_1
4012
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Tied, Tie1_1_1, CVT_Done },
4013
  // Convert__Reg1_0__Reg1_2__Tie0_1_1__Mem256_RC1285_1__Tie1_3_3
4014
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Tied, Tie1_3_3, CVT_Done },
4015
  // Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem128_RC128X5_4
4016
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_3_3, CVT_95_addMemOperands, 5, CVT_Done },
4017
  // Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem256_RC128X5_4
4018
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_3_3, CVT_95_addMemOperands, 5, CVT_Done },
4019
  // Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem512_RC256X5_4
4020
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_3_3, CVT_95_addMemOperands, 5, CVT_Done },
4021
  // Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem128_RC128X5_0
4022
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_4_4, CVT_95_addMemOperands, 1, CVT_Done },
4023
  // Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem256_RC128X5_0
4024
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_4_4, CVT_95_addMemOperands, 1, CVT_Done },
4025
  // Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem512_RC256X5_0
4026
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_4_4, CVT_95_addMemOperands, 1, CVT_Done },
4027
  // Convert__Reg1_2__Reg1_0__Tie0_1_1__Mem256_RC2565_1__Tie1_1_1
4028
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Tied, Tie1_1_1, CVT_Done },
4029
  // Convert__Reg1_0__Reg1_2__Tie0_1_1__Mem256_RC2565_1__Tie1_3_3
4030
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Tied, Tie1_3_3, CVT_Done },
4031
  // Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem256_RC256X5_4
4032
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_3_3, CVT_95_addMemOperands, 5, CVT_Done },
4033
  // Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem512_RC5125_4
4034
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_3_3, CVT_95_addMemOperands, 5, CVT_Done },
4035
  // Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem256_RC256X5_0
4036
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_4_4, CVT_95_addMemOperands, 1, CVT_Done },
4037
  // Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem512_RC5125_0
4038
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_4_4, CVT_95_addMemOperands, 1, CVT_Done },
4039
  // Convert__Reg1_1__Mem512_RC256X5_3
4040
  { CVT_95_Reg, 2, CVT_95_addMemOperands, 4, CVT_Done },
4041
  // Convert__Reg1_2__Mem512_RC256X5_0
4042
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
4043
  // Convert__Reg1_1__Mem512_RC5125_3
4044
  { CVT_95_Reg, 2, CVT_95_addMemOperands, 4, CVT_Done },
4045
  // Convert__Reg1_2__Mem512_RC5125_0
4046
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
4047
  // Convert__Reg1_1__Mem256_RC5125_3
4048
  { CVT_95_Reg, 2, CVT_95_addMemOperands, 4, CVT_Done },
4049
  // Convert__Reg1_2__Mem256_RC5125_0
4050
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
4051
  // Convert__Reg1_2__Reg1_0__Tie0_1_1__Mem128_RC2565_1__Tie1_1_1
4052
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Tied, Tie1_1_1, CVT_Done },
4053
  // Convert__Reg1_0__Reg1_2__Tie0_1_1__Mem128_RC2565_1__Tie1_3_3
4054
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Tied, Tie1_3_3, CVT_Done },
4055
  // Convert__Reg1_2__Reg1_0__Tie0_1_1__Mem64_RC1285_1__Tie1_1_1
4056
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Tied, Tie1_1_1, CVT_Done },
4057
  // Convert__Reg1_0__Reg1_2__Tie0_1_1__Mem64_RC1285_1__Tie1_3_3
4058
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Tied, Tie1_3_3, CVT_Done },
4059
  // Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem128_RC256X5_4
4060
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_3_3, CVT_95_addMemOperands, 5, CVT_Done },
4061
  // Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem64_RC128X5_4
4062
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_3_3, CVT_95_addMemOperands, 5, CVT_Done },
4063
  // Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem256_RC5125_4
4064
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_3_3, CVT_95_addMemOperands, 5, CVT_Done },
4065
  // Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem128_RC256X5_0
4066
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_4_4, CVT_95_addMemOperands, 1, CVT_Done },
4067
  // Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem256_RC5125_0
4068
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_4_4, CVT_95_addMemOperands, 1, CVT_Done },
4069
  // Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem64_RC128X5_0
4070
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_4_4, CVT_95_addMemOperands, 1, CVT_Done },
4071
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem1285_4__ImmUnsignedi81_5
4072
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
4073
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem2565_4__ImmUnsignedi81_5
4074
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
4075
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem5125_4__ImmUnsignedi81_5
4076
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
4077
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Mem1285_1__ImmUnsignedi81_0
4078
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4079
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Mem2565_1__ImmUnsignedi81_0
4080
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4081
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Mem5125_1__ImmUnsignedi81_0
4082
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4083
  // Convert__Reg1_0__Reg1_2__Mem1285_5__ImmUnsignedi81_6
4084
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
4085
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem645_4__ImmUnsignedi81_6
4086
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 7, CVT_Done },
4087
  // Convert__Reg1_0__Reg1_2__Mem2565_5__ImmUnsignedi81_6
4088
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
4089
  // Convert__Reg1_0__Reg1_2__Mem5125_5__ImmUnsignedi81_6
4090
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
4091
  // Convert__Reg1_3__Tie0_1_1__Reg1_5__Mem645_1__ImmUnsignedi81_0
4092
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 6, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4093
  // Convert__Reg1_0__Reg1_2__Mem645_5__ImmUnsignedi81_7
4094
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 8, CVT_Done },
4095
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem325_4__ImmUnsignedi81_6
4096
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 7, CVT_Done },
4097
  // Convert__Reg1_3__Tie0_1_1__Reg1_5__Mem325_1__ImmUnsignedi81_0
4098
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 6, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4099
  // Convert__Reg1_0__Reg1_2__Mem325_5__ImmUnsignedi81_7
4100
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 8, CVT_Done },
4101
  // Convert__Reg1_0__Reg1_2__Reg1_5__Mem645_6__ImmUnsignedi81_7
4102
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
4103
  // Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6__ImmUnsignedi81_8
4104
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addImmOperands, 9, CVT_Done },
4105
  // Convert__Reg1_0__Reg1_2__Reg1_5__Mem325_6__ImmUnsignedi81_7
4106
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
4107
  // Convert__Reg1_0__Reg1_1__Mem85_2__ImmUnsignedi81_4
4108
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 5, CVT_Done },
4109
  // Convert__Reg1_4__Reg1_3__Mem85_1__ImmUnsignedi81_0
4110
  { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4111
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem85_5__ImmUnsignedi81_7
4112
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 8, CVT_Done },
4113
  // Convert__Reg1_4__Tie0_1_1__Reg1_6__Reg1_3__Mem85_1__ImmUnsignedi81_0
4114
  { CVT_95_Reg, 5, CVT_Tied, Tie0_1_1, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4115
  // Convert__Reg1_0__Reg1_2__Reg1_5__Mem85_6__ImmUnsignedi81_8
4116
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 9, CVT_Done },
4117
  // Convert__Reg1_4__Reg1_6__Reg1_3__Mem85_1__ImmUnsignedi81_0
4118
  { CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4119
  // Convert__Mem1285_2__Reg1_1__Reg1_0
4120
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
4121
  // Convert__Mem2565_2__Reg1_1__Reg1_0
4122
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
4123
  // Convert__Mem1285_0__Reg1_1__Reg1_2
4124
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
4125
  // Convert__Mem2565_0__Reg1_1__Reg1_2
4126
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
4127
  // Convert__Reg1_0__Reg1_2__Reg1_4
4128
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_Done },
4129
  // Convert__Mem645_1__Reg1_3__Reg1_0
4130
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_Done },
4131
  // Convert__Mem645_0__Reg1_2__Reg1_4
4132
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_Done },
4133
  // Convert__Reg1_2__Tie0_3_3__Reg1_4__Reg1_1__Reg1_0
4134
  { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
4135
  // Convert__Mem325_1__Reg1_3__Reg1_0
4136
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_Done },
4137
  // Convert__Mem325_0__Reg1_2__Reg1_4
4138
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_Done },
4139
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem85_4
4140
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_Done },
4141
  // Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem85_0
4142
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
4143
  // Convert__Reg1_0__Reg1_2__Mem85_5
4144
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_Done },
4145
  // Convert__Reg1_1__Reg1_3__Mem85_0
4146
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
4147
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem165_4
4148
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_Done },
4149
  // Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem165_0
4150
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
4151
  // Convert__Reg1_0__Reg1_2__Mem165_5
4152
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_Done },
4153
  // Convert__Reg1_1__Reg1_3__Mem165_0
4154
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
4155
  // Convert__Reg1_2__Reg1_1__Reg1_0__imm_95_17
4156
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_imm_95_17, 0, CVT_Done },
4157
  // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_17
4158
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_17, 0, CVT_Done },
4159
  // Convert__Reg1_0__Reg1_1__Mem1285_2__imm_95_17
4160
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_17, 0, CVT_Done },
4161
  // Convert__Reg1_0__Reg1_1__Mem2565_2__imm_95_17
4162
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_17, 0, CVT_Done },
4163
  // Convert__Reg1_0__Reg1_1__Mem5125_2__imm_95_17
4164
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_17, 0, CVT_Done },
4165
  // Convert__Reg1_2__Reg1_1__Mem1285_0__imm_95_17
4166
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_17, 0, CVT_Done },
4167
  // Convert__Reg1_2__Reg1_1__Mem2565_0__imm_95_17
4168
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_17, 0, CVT_Done },
4169
  // Convert__Reg1_2__Reg1_1__Mem5125_0__imm_95_17
4170
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_17, 0, CVT_Done },
4171
  // Convert__Reg1_2__Reg1_1__Reg1_0__imm_95_1
4172
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_Done },
4173
  // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_1
4174
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_1, 0, CVT_Done },
4175
  // Convert__Reg1_0__Reg1_1__Mem1285_2__imm_95_1
4176
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_1, 0, CVT_Done },
4177
  // Convert__Reg1_0__Reg1_1__Mem2565_2__imm_95_1
4178
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_1, 0, CVT_Done },
4179
  // Convert__Reg1_0__Reg1_1__Mem5125_2__imm_95_1
4180
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_1, 0, CVT_Done },
4181
  // Convert__Reg1_2__Reg1_1__Mem1285_0__imm_95_1
4182
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_1, 0, CVT_Done },
4183
  // Convert__Reg1_2__Reg1_1__Mem2565_0__imm_95_1
4184
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_1, 0, CVT_Done },
4185
  // Convert__Reg1_2__Reg1_1__Mem5125_0__imm_95_1
4186
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_1, 0, CVT_Done },
4187
  // Convert__Reg1_2__Reg1_1__Reg1_0__imm_95_16
4188
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_imm_95_16, 0, CVT_Done },
4189
  // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16
4190
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_16, 0, CVT_Done },
4191
  // Convert__Reg1_0__Reg1_1__Mem1285_2__imm_95_16
4192
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_16, 0, CVT_Done },
4193
  // Convert__Reg1_0__Reg1_1__Mem2565_2__imm_95_16
4194
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_16, 0, CVT_Done },
4195
  // Convert__Reg1_0__Reg1_1__Mem5125_2__imm_95_16
4196
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_16, 0, CVT_Done },
4197
  // Convert__Reg1_2__Reg1_1__Mem1285_0__imm_95_16
4198
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_16, 0, CVT_Done },
4199
  // Convert__Reg1_2__Reg1_1__Mem2565_0__imm_95_16
4200
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_16, 0, CVT_Done },
4201
  // Convert__Reg1_2__Reg1_1__Mem5125_0__imm_95_16
4202
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_16, 0, CVT_Done },
4203
  // Convert__Reg1_2__Reg1_1__Reg1_0__imm_95_0
4204
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done },
4205
  // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0
4206
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
4207
  // Convert__Reg1_0__Reg1_1__Mem1285_2__imm_95_0
4208
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_0, 0, CVT_Done },
4209
  // Convert__Reg1_0__Reg1_1__Mem2565_2__imm_95_0
4210
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_0, 0, CVT_Done },
4211
  // Convert__Reg1_0__Reg1_1__Mem5125_2__imm_95_0
4212
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_0, 0, CVT_Done },
4213
  // Convert__Reg1_2__Reg1_1__Mem1285_0__imm_95_0
4214
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_0, 0, CVT_Done },
4215
  // Convert__Reg1_2__Reg1_1__Mem2565_0__imm_95_0
4216
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_0, 0, CVT_Done },
4217
  // Convert__Reg1_2__Reg1_1__Mem5125_0__imm_95_0
4218
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_0, 0, CVT_Done },
4219
  // Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmUnsignedi81_4
4220
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_Done },
4221
  // Convert__Reg1_0__Reg1_1__Reg1_2__Mem1285_3__ImmUnsignedi81_4
4222
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
4223
  // Convert__Reg1_0__Reg1_1__Mem1285_2__Reg1_3__ImmUnsignedi81_4
4224
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_Done },
4225
  // Convert__Reg1_0__Reg1_1__Reg1_2__Mem2565_3__ImmUnsignedi81_4
4226
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
4227
  // Convert__Reg1_0__Reg1_1__Mem2565_2__Reg1_3__ImmUnsignedi81_4
4228
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_Done },
4229
  // Convert__Reg1_4__Reg1_3__Reg1_2__Reg1_1__ImmUnsignedi81_0
4230
  { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
4231
  // Convert__Reg1_4__Reg1_3__Mem1285_2__Reg1_1__ImmUnsignedi81_0
4232
  { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
4233
  // Convert__Reg1_4__Reg1_3__Mem2565_2__Reg1_1__ImmUnsignedi81_0
4234
  { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
4235
  // Convert__Reg1_4__Reg1_3__Reg1_2__Mem1285_1__ImmUnsignedi81_0
4236
  { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4237
  // Convert__Reg1_4__Reg1_3__Reg1_2__Mem2565_1__ImmUnsignedi81_0
4238
  { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4239
  // Convert__Reg1_0__Reg1_1__GR32orGR641_2__ImmUnsignedi81_3
4240
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addGR32orGR64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
4241
  // Convert__Reg1_0__Reg1_1__Mem85_2__ImmUnsignedi81_3
4242
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
4243
  // Convert__Reg1_3__Reg1_2__GR32orGR641_1__ImmUnsignedi81_0
4244
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addGR32orGR64Operands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4245
  // Convert__Reg1_3__Reg1_2__Mem85_1__ImmUnsignedi81_0
4246
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4247
  // Convert__Reg1_0__Reg1_1__Mem165_2__ImmUnsignedi81_3
4248
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
4249
  // Convert__Reg1_3__Reg1_2__Mem165_1__ImmUnsignedi81_0
4250
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4251
  // Convert__Mem165_1__Reg1_3__Reg1_0
4252
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_Done },
4253
  // Convert__Mem165_0__Reg1_2__Reg1_4
4254
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_Done },
4255
  // Convert__Reg1_2__Mem1285_1__Reg1_0
4256
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
4257
  // Convert__Reg1_0__Mem1285_1__Reg1_2
4258
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_Reg, 3, CVT_Done },
4259
  // Convert__Reg1_3__Mem128_RC128X5_1__Tie0_4_4__Reg1_0
4260
  { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 1, CVT_Done },
4261
  // Convert__Reg1_3__Mem256_RC256X5_1__Tie0_4_4__Reg1_0
4262
  { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 1, CVT_Done },
4263
  // Convert__Reg1_3__Mem512_RC5125_1__Tie0_4_4__Reg1_0
4264
  { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 1, CVT_Done },
4265
  // Convert__Reg1_2__Mem128_RC128X5_0__Tie0_3_3__Reg1_4
4266
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4267
  // Convert__Reg1_2__Mem256_RC256X5_0__Tie0_3_3__Reg1_4
4268
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4269
  // Convert__Reg1_2__Mem512_RC5125_0__Tie0_3_3__Reg1_4
4270
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4271
  // Convert__Reg1_3__Mem256_RC128X5_1__Tie0_4_4__Reg1_0
4272
  { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 1, CVT_Done },
4273
  // Convert__Reg1_3__Mem512_RC256X5_1__Tie0_4_4__Reg1_0
4274
  { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 1, CVT_Done },
4275
  // Convert__Reg1_2__Mem256_RC128X5_0__Tie0_3_3__Reg1_4
4276
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4277
  // Convert__Reg1_2__Mem512_RC256X5_0__Tie0_3_3__Reg1_4
4278
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4279
  // Convert__Reg1_3__Mem128_RC256X5_1__Tie0_4_4__Reg1_0
4280
  { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 1, CVT_Done },
4281
  // Convert__Reg1_3__Mem64_RC128X5_1__Tie0_4_4__Reg1_0
4282
  { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 1, CVT_Done },
4283
  // Convert__Reg1_3__Mem256_RC5125_1__Tie0_4_4__Reg1_0
4284
  { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 1, CVT_Done },
4285
  // Convert__Reg1_2__Mem128_RC256X5_0__Tie0_3_3__Reg1_4
4286
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4287
  // Convert__Reg1_2__Mem256_RC5125_0__Tie0_3_3__Reg1_4
4288
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4289
  // Convert__Reg1_2__Mem64_RC128X5_0__Tie0_3_3__Reg1_4
4290
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4291
  // Convert__Reg1_0__Reg1_1__Tie0_1_1__Tie1_2_2
4292
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_2_2, CVT_Done },
4293
  // Convert__Reg1_1__Reg1_0__Tie0_2_2__Tie1_1_1
4294
  { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Tied, Tie0_2_2, CVT_Tied, Tie1_1_1, CVT_Done },
4295
  // Convert__AbsMem161_0
4296
  { CVT_95_addAbsMemOperands, 1, CVT_Done },
4297
  // Convert__Reg1_1__Tie0_2_2
4298
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_Done },
4299
  // Convert__regEAX__regEAX__Tie0_1_1__Tie1_1_1
4300
  { CVT_regEAX, 0, CVT_regEAX, 0, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_Done },
4301
};
4302
4303
void X86AsmParser::
4304
convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
4305
141k
                const OperandVector &Operands) {
4306
141k
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
4307
141k
  const uint8_t *Converter = ConversionTable[Kind];
4308
141k
  unsigned OpIdx;
4309
141k
  Inst.setOpcode(Opcode);
4310
542k
  for (const uint8_t *p = Converter; *p; 
p+= 2400k
) {
4311
400k
    OpIdx = *(p + 1);
4312
400k
    switch (*p) {
4313
400k
    
default: 0
llvm_unreachable0
("invalid conversion entry!");
4314
400k
    case CVT_Reg:
4315
0
      static_cast<X86Operand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
4316
0
      break;
4317
400k
    case CVT_Tied: {
4318
47.7k
      assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
4319
47.7k
                          std::begin(TiedAsmOperandTable)) &&
4320
47.7k
             "Tied operand not found");
4321
47.7k
      unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];
4322
47.7k
      if (TiedResOpnd != (uint8_t) -1)
4323
47.7k
        Inst.addOperand(Inst.getOperand(TiedResOpnd));
4324
47.7k
      break;
4325
400k
    }
4326
400k
    case CVT_imm_95_10:
4327
26
      Inst.addOperand(MCOperand::createImm(10));
4328
26
      break;
4329
400k
    case CVT_95_addImmOperands:
4330
22.1k
      static_cast<X86Operand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
4331
22.1k
      break;
4332
400k
    case CVT_regAX:
4333
37
      Inst.addOperand(MCOperand::createReg(X86::AX));
4334
37
      break;
4335
400k
    case CVT_regEAX:
4336
121
      Inst.addOperand(MCOperand::createReg(X86::EAX));
4337
121
      break;
4338
400k
    case CVT_regRAX:
4339
40
      Inst.addOperand(MCOperand::createReg(X86::RAX));
4340
40
      break;
4341
400k
    case CVT_95_Reg:
4342
236k
      static_cast<X86Operand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
4343
236k
      break;
4344
400k
    case CVT_95_addMemOperands:
4345
87.1k
      static_cast<X86Operand&>(*Operands[OpIdx]).addMemOperands(Inst, 5);
4346
87.1k
      break;
4347
400k
    case CVT_95_addAbsMemOperands:
4348
1.15k
      static_cast<X86Operand&>(*Operands[OpIdx]).addAbsMemOperands(Inst, 1);
4349
1.15k
      break;
4350
400k
    case CVT_95_addDstIdxOperands:
4351
546
      static_cast<X86Operand&>(*Operands[OpIdx]).addDstIdxOperands(Inst, 1);
4352
546
      break;
4353
400k
    case CVT_95_addSrcIdxOperands:
4354
499
      static_cast<X86Operand&>(*Operands[OpIdx]).addSrcIdxOperands(Inst, 2);
4355
499
      break;
4356
400k
    case CVT_95_addGR32orGR64Operands:
4357
349
      static_cast<X86Operand&>(*Operands[OpIdx]).addGR32orGR64Operands(Inst, 1);
4358
349
      break;
4359
400k
    case CVT_regST1:
4360
44
      Inst.addOperand(MCOperand::createReg(X86::ST1));
4361
44
      break;
4362
400k
    case CVT_regST0:
4363
12
      Inst.addOperand(MCOperand::createReg(X86::ST0));
4364
12
      break;
4365
400k
    case CVT_95_addMemOffsOperands:
4366
76
      static_cast<X86Operand&>(*Operands[OpIdx]).addMemOffsOperands(Inst, 2);
4367
76
      break;
4368
400k
    case CVT_imm_95_17:
4369
5
      Inst.addOperand(MCOperand::createImm(17));
4370
5
      break;
4371
400k
    case CVT_imm_95_1:
4372
4
      Inst.addOperand(MCOperand::createImm(1));
4373
4
      break;
4374
400k
    case CVT_imm_95_16:
4375
5
      Inst.addOperand(MCOperand::createImm(16));
4376
5
      break;
4377
400k
    case CVT_imm_95_0:
4378
4
      Inst.addOperand(MCOperand::createImm(0));
4379
4
      break;
4380
400k
    case CVT_95_addAVX512RCOperands:
4381
4.28k
      static_cast<X86Operand&>(*Operands[OpIdx]).addAVX512RCOperands(Inst, 1);
4382
4.28k
      break;
4383
400k
    }
4384
400k
  }
4385
141k
}
4386
4387
void X86AsmParser::
4388
convertToMapAndConstraints(unsigned Kind,
4389
436
                           const OperandVector &Operands) {
4390
436
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
4391
436
  unsigned NumMCOperands = 0;
4392
436
  const uint8_t *Converter = ConversionTable[Kind];
4393
1.18k
  for (const uint8_t *p = Converter; *p; 
p+= 2750
) {
4394
750
    switch (*p) {
4395
750
    
default: 0
llvm_unreachable0
("invalid conversion entry!");
4396
750
    case CVT_Reg:
4397
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4398
0
      Operands[*(p + 1)]->setConstraint("r");
4399
0
      ++NumMCOperands;
4400
0
      break;
4401
750
    case CVT_Tied:
4402
11
      ++NumMCOperands;
4403
11
      break;
4404
750
    case CVT_imm_95_10:
4405
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4406
0
      Operands[*(p + 1)]->setConstraint("");
4407
0
      ++NumMCOperands;
4408
0
      break;
4409
750
    case CVT_95_addImmOperands:
4410
113
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4411
113
      Operands[*(p + 1)]->setConstraint("m");
4412
113
      NumMCOperands += 1;
4413
113
      break;
4414
750
    case CVT_regAX:
4415
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4416
0
      Operands[*(p + 1)]->setConstraint("m");
4417
0
      ++NumMCOperands;
4418
0
      break;
4419
750
    case CVT_regEAX:
4420
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4421
0
      Operands[*(p + 1)]->setConstraint("m");
4422
0
      ++NumMCOperands;
4423
0
      break;
4424
750
    case CVT_regRAX:
4425
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4426
0
      Operands[*(p + 1)]->setConstraint("m");
4427
0
      ++NumMCOperands;
4428
0
      break;
4429
750
    case CVT_95_Reg:
4430
378
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4431
378
      Operands[*(p + 1)]->setConstraint("r");
4432
378
      NumMCOperands += 1;
4433
378
      break;
4434
750
    case CVT_95_addMemOperands:
4435
239
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4436
239
      Operands[*(p + 1)]->setConstraint("m");
4437
239
      NumMCOperands += 5;
4438
239
      break;
4439
750
    case CVT_95_addAbsMemOperands:
4440
8
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4441
8
      Operands[*(p + 1)]->setConstraint("m");
4442
8
      NumMCOperands += 1;
4443
8
      break;
4444
750
    case CVT_95_addDstIdxOperands:
4445
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4446
0
      Operands[*(p + 1)]->setConstraint("m");
4447
0
      NumMCOperands += 1;
4448
0
      break;
4449
750
    case CVT_95_addSrcIdxOperands:
4450
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4451
0
      Operands[*(p + 1)]->setConstraint("m");
4452
0
      NumMCOperands += 2;
4453
0
      break;
4454
750
    case CVT_95_addGR32orGR64Operands:
4455
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4456
0
      Operands[*(p + 1)]->setConstraint("m");
4457
0
      NumMCOperands += 1;
4458
0
      break;
4459
750
    case CVT_regST1:
4460
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4461
0
      Operands[*(p + 1)]->setConstraint("m");
4462
0
      ++NumMCOperands;
4463
0
      break;
4464
750
    case CVT_regST0:
4465
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4466
0
      Operands[*(p + 1)]->setConstraint("m");
4467
0
      ++NumMCOperands;
4468
0
      break;
4469
750
    case CVT_95_addMemOffsOperands:
4470
1
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4471
1
      Operands[*(p + 1)]->setConstraint("m");
4472
1
      NumMCOperands += 2;
4473
1
      break;
4474
750
    case CVT_imm_95_17:
4475
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4476
0
      Operands[*(p + 1)]->setConstraint("");
4477
0
      ++NumMCOperands;
4478
0
      break;
4479
750
    case CVT_imm_95_1:
4480
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4481
0
      Operands[*(p + 1)]->setConstraint("");
4482
0
      ++NumMCOperands;
4483
0
      break;
4484
750
    case CVT_imm_95_16:
4485
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4486
0
      Operands[*(p + 1)]->setConstraint("");
4487
0
      ++NumMCOperands;
4488
0
      break;
4489
750
    case CVT_imm_95_0:
4490
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4491
0
      Operands[*(p + 1)]->setConstraint("");
4492
0
      ++NumMCOperands;
4493
0
      break;
4494
750
    case CVT_95_addAVX512RCOperands:
4495
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4496
0
      Operands[*(p + 1)]->setConstraint("m");
4497
0
      NumMCOperands += 1;
4498
0
      break;
4499
750
    }
4500
750
  }
4501
436
}
4502
4503
namespace {
4504
4505
/// MatchClassKind - The kinds of classes which participate in
4506
/// instruction matching.
4507
enum MatchClassKind {
4508
  InvalidMatchClass = 0,
4509
  OptionalMatchClass = 1,
4510
  MCK__STAR_, // '*'
4511
  MCK__123_, // '{'
4512
  MCK__123_1to16_125_, // '{1to16}'
4513
  MCK__123_1to2_125_, // '{1to2}'
4514
  MCK__123_1to4_125_, // '{1to4}'
4515
  MCK__123_1to8_125_, // '{1to8}'
4516
  MCK__123_sae_125_, // '{sae}'
4517
  MCK__123_z_125_, // '{z}'
4518
  MCK__125_, // '}'
4519
  MCK_LAST_TOKEN = MCK__125_,
4520
  MCK_Reg77, // derived register class
4521
  MCK_Reg76, // derived register class
4522
  MCK_Reg73, // derived register class
4523
  MCK_Reg71, // derived register class
4524
  MCK_Reg69, // derived register class
4525
  MCK_Reg38, // derived register class
4526
  MCK_Reg36, // derived register class
4527
  MCK_Reg34, // derived register class
4528
  MCK_Reg32, // derived register class
4529
  MCK_AL, // register class 'AL'
4530
  MCK_AX, // register class 'AX'
4531
  MCK_CCR, // register class 'CCR'
4532
  MCK_CL, // register class 'CL'
4533
  MCK_CS, // register class 'CS'
4534
  MCK_DFCCR, // register class 'DFCCR'
4535
  MCK_DS, // register class 'DS'
4536
  MCK_DX, // register class 'DX'
4537
  MCK_EAX, // register class 'EAX'
4538
  MCK_EBX, // register class 'EBX'
4539
  MCK_ECX, // register class 'ECX'
4540
  MCK_EDX, // register class 'EDX'
4541
  MCK_ES, // register class 'ES'
4542
  MCK_FPCCR, // register class 'FPCCR'
4543
  MCK_FS, // register class 'FS'
4544
  MCK_GS, // register class 'GS'
4545
  MCK_RAX, // register class 'RAX'
4546
  MCK_RBX, // register class 'RBX'
4547
  MCK_RCX, // register class 'RCX'
4548
  MCK_RDX, // register class 'RDX'
4549
  MCK_RFP80_7, // register class 'RFP80_7'
4550
  MCK_SS, // register class 'SS'
4551
  MCK_ST0, // register class 'ST0'
4552
  MCK_XMM0, // register class 'XMM0'
4553
  MCK_Reg75, // derived register class
4554
  MCK_Reg74, // derived register class
4555
  MCK_Reg72, // derived register class
4556
  MCK_Reg70, // derived register class
4557
  MCK_Reg68, // derived register class
4558
  MCK_Reg66, // derived register class
4559
  MCK_Reg64, // derived register class
4560
  MCK_GR32_AD, // register class 'GR32_AD'
4561
  MCK_GR32_BPSP, // register class 'GR32_BPSP'
4562
  MCK_GR32_BSI, // register class 'GR32_BSI'
4563
  MCK_GR32_CB, // register class 'GR32_CB'
4564
  MCK_GR32_DC, // register class 'GR32_DC'
4565
  MCK_GR32_DIBP, // register class 'GR32_DIBP'
4566
  MCK_GR32_SIDI, // register class 'GR32_SIDI'
4567
  MCK_GR64_AD, // register class 'GR64_AD'
4568
  MCK_Reg41, // derived register class
4569
  MCK_Reg15, // derived register class
4570
  MCK_Reg55, // derived register class
4571
  MCK_BNDR, // register class 'BNDR'
4572
  MCK_GR16_ABCD, // register class 'GR16_ABCD'
4573
  MCK_GR32_ABCD, // register class 'GR32_ABCD'
4574
  MCK_GR32_TC, // register class 'GR32_TC'
4575
  MCK_GR64_ABCD, // register class 'GR64_ABCD'
4576
  MCK_GR8_ABCD_H, // register class 'GR8_ABCD_H'
4577
  MCK_GR8_ABCD_L, // register class 'GR8_ABCD_L'
4578
  MCK_Reg60, // derived register class
4579
  MCK_Reg49, // derived register class
4580
  MCK_Reg62, // derived register class
4581
  MCK_Reg50, // derived register class
4582
  MCK_SEGMENT_REG, // register class 'SEGMENT_REG'
4583
  MCK_Reg61, // derived register class
4584
  MCK_Reg58, // derived register class
4585
  MCK_Reg53, // derived register class
4586
  MCK_GR32_NOREX_NOSP, // register class 'GR32_NOREX_NOSP'
4587
  MCK_GR64_NOREX_NOSP, // register class 'GR64_NOREX_NOSP'
4588
  MCK_RFP32, // register class 'RFP32,RFP64,RFP80'
4589
  MCK_VK16WM, // register class 'VK16WM,VK1WM,VK2WM,VK4WM,VK8WM,VK32WM,VK64WM'
4590
  MCK_Reg93, // derived register class
4591
  MCK_Reg90, // derived register class
4592
  MCK_Reg59, // derived register class
4593
  MCK_Reg56, // derived register class
4594
  MCK_Reg54, // derived register class
4595
  MCK_Reg44, // derived register class
4596
  MCK_GR16_NOREX, // register class 'GR16_NOREX'
4597
  MCK_GR32_NOREX, // register class 'GR32_NOREX'
4598
  MCK_GR8_NOREX, // register class 'GR8_NOREX'
4599
  MCK_RST, // register class 'RST'
4600
  MCK_VK1, // register class 'VK1,VK16,VK2,VK4,VK8,VK32,VK64'
4601
  MCK_VR128H, // register class 'VR128H'
4602
  MCK_VR128L, // register class 'VR128L'
4603
  MCK_VR256H, // register class 'VR256H'
4604
  MCK_VR256L, // register class 'VR256L'
4605
  MCK_VR64, // register class 'VR64'
4606
  MCK_Reg51, // derived register class
4607
  MCK_Reg23, // derived register class
4608
  MCK_GR64_NOREX, // register class 'GR64_NOREX'
4609
  MCK_GR64_TCW64, // register class 'GR64_TCW64'
4610
  MCK_GR64_TC, // register class 'GR64_TC'
4611
  MCK_GRH8, // register class 'GRH8'
4612
  MCK_GR32_NOSP, // register class 'GR32_NOSP'
4613
  MCK_GR64_NOSP, // register class 'GR64_NOSP'
4614
  MCK_Reg91, // derived register class
4615
  MCK_Reg45, // derived register class
4616
  MCK_CONTROL_REG, // register class 'CONTROL_REG'
4617
  MCK_DEBUG_REG, // register class 'DEBUG_REG'
4618
  MCK_FR32, // register class 'FR32,FR64,VR128'
4619
  MCK_GR16, // register class 'GR16'
4620
  MCK_GR32, // register class 'GR32'
4621
  MCK_VR256, // register class 'VR256'
4622
  MCK_Reg20, // derived register class
4623
  MCK_GR64, // register class 'GR64'
4624
  MCK_GRH16, // register class 'GRH16'
4625
  MCK_LOW32_ADDR_ACCESS, // register class 'LOW32_ADDR_ACCESS'
4626
  MCK_LOW32_ADDR_ACCESS_RBP, // register class 'LOW32_ADDR_ACCESS_RBP'
4627
  MCK_GR8, // register class 'GR8'
4628
  MCK_FR32X, // register class 'FR32X,FR64X,VR128X'
4629
  MCK_VR256X, // register class 'VR256X'
4630
  MCK_VR512, // register class 'VR512'
4631
  MCK_LAST_REGISTER = MCK_VR512,
4632
  MCK_AVX512RC, // user defined class 'AVX512RCOperand'
4633
  MCK_ImmSExti64i8, // user defined class 'ImmSExti64i8AsmOperand'
4634
  MCK_ImmSExti16i8, // user defined class 'ImmSExti16i8AsmOperand'
4635
  MCK_ImmSExti32i8, // user defined class 'ImmSExti32i8AsmOperand'
4636
  MCK_ImmSExti64i32, // user defined class 'ImmSExti64i32AsmOperand'
4637
  MCK_Imm, // user defined class 'ImmAsmOperand'
4638
  MCK_ImmUnsignedi8, // user defined class 'ImmUnsignedi8AsmOperand'
4639
  MCK_GR32orGR64, // user defined class 'X86GR32orGR64AsmOperand'
4640
  MCK_AbsMem16, // user defined class 'X86AbsMem16AsmOperand'
4641
  MCK_DstIdx16, // user defined class 'X86DstIdx16Operand'
4642
  MCK_DstIdx32, // user defined class 'X86DstIdx32Operand'
4643
  MCK_DstIdx64, // user defined class 'X86DstIdx64Operand'
4644
  MCK_DstIdx8, // user defined class 'X86DstIdx8Operand'
4645
  MCK_MemOffs16_16, // user defined class 'X86MemOffs16_16AsmOperand'
4646
  MCK_MemOffs16_32, // user defined class 'X86MemOffs16_32AsmOperand'
4647
  MCK_MemOffs16_8, // user defined class 'X86MemOffs16_8AsmOperand'
4648
  MCK_MemOffs32_16, // user defined class 'X86MemOffs32_16AsmOperand'
4649
  MCK_MemOffs32_32, // user defined class 'X86MemOffs32_32AsmOperand'
4650
  MCK_MemOffs32_64, // user defined class 'X86MemOffs32_64AsmOperand'
4651
  MCK_MemOffs32_8, // user defined class 'X86MemOffs32_8AsmOperand'
4652
  MCK_MemOffs64_16, // user defined class 'X86MemOffs64_16AsmOperand'
4653
  MCK_MemOffs64_32, // user defined class 'X86MemOffs64_32AsmOperand'
4654
  MCK_MemOffs64_64, // user defined class 'X86MemOffs64_64AsmOperand'
4655
  MCK_MemOffs64_8, // user defined class 'X86MemOffs64_8AsmOperand'
4656
  MCK_SrcIdx16, // user defined class 'X86SrcIdx16Operand'
4657
  MCK_SrcIdx32, // user defined class 'X86SrcIdx32Operand'
4658
  MCK_SrcIdx64, // user defined class 'X86SrcIdx64Operand'
4659
  MCK_SrcIdx8, // user defined class 'X86SrcIdx8Operand'
4660
  MCK_AbsMem, // user defined class 'X86AbsMemAsmOperand'
4661
  MCK_Mem128, // user defined class 'X86Mem128AsmOperand'
4662
  MCK_Mem128_RC128, // user defined class 'X86Mem128_RC128Operand'
4663
  MCK_Mem128_RC128X, // user defined class 'X86Mem128_RC128XOperand'
4664
  MCK_Mem128_RC256, // user defined class 'X86Mem128_RC256Operand'
4665
  MCK_Mem128_RC256X, // user defined class 'X86Mem128_RC256XOperand'
4666
  MCK_Mem16, // user defined class 'X86Mem16AsmOperand'
4667
  MCK_Mem256, // user defined class 'X86Mem256AsmOperand'
4668
  MCK_Mem256_RC128, // user defined class 'X86Mem256_RC128Operand'
4669
  MCK_Mem256_RC128X, // user defined class 'X86Mem256_RC128XOperand'
4670
  MCK_Mem256_RC256, // user defined class 'X86Mem256_RC256Operand'
4671
  MCK_Mem256_RC256X, // user defined class 'X86Mem256_RC256XOperand'
4672
  MCK_Mem256_RC512, // user defined class 'X86Mem256_RC512Operand'
4673
  MCK_Mem32, // user defined class 'X86Mem32AsmOperand'
4674
  MCK_Mem512, // user defined class 'X86Mem512AsmOperand'
4675
  MCK_Mem512_RC256X, // user defined class 'X86Mem512_RC256XOperand'
4676
  MCK_Mem512_RC512, // user defined class 'X86Mem512_RC512Operand'
4677
  MCK_Mem64, // user defined class 'X86Mem64AsmOperand'
4678
  MCK_Mem64_RC128, // user defined class 'X86Mem64_RC128Operand'
4679
  MCK_Mem64_RC128X, // user defined class 'X86Mem64_RC128XOperand'
4680
  MCK_Mem80, // user defined class 'X86Mem80AsmOperand'
4681
  MCK_Mem8, // user defined class 'X86Mem8AsmOperand'
4682
  MCK_Mem, // user defined class 'X86MemAsmOperand'
4683
  NumMatchClassKinds
4684
};
4685
4686
}
4687
4688
836k
static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
4689
836k
  return MCTargetAsmParser::Match_InvalidOperand;
4690
836k
}
4691
4692
122k
static MatchClassKind matchTokenString(StringRef Name) {
4693
122k
  switch (Name.size()) {
4694
122k
  
default: break0
;
4695
122k
  case 1:  // 3 strings to match.
4696
68.6k
    switch (Name[0]) {
4697
68.6k
    
default: break0
;
4698
68.6k
    case '*':  // 1 string to match.
4699
334
      return MCK__STAR_;  // "*"
4700
68.6k
    case '{':  // 1 string to match.
4701
34.1k
      return MCK__123_;  // "{"
4702
68.6k
    case '}':  // 1 string to match.
4703
34.1k
      return MCK__125_;  // "}"
4704
0
    }
4705
0
    break;
4706
10.2k
  case 3:  // 1 string to match.
4707
10.2k
    if (memcmp(Name.data()+0, "{z}", 3) != 0)
4708
0
      break;
4709
10.2k
    return MCK__123_z_125_;  // "{z}"
4710
10.2k
  case 5:  // 1 string to match.
4711
796
    if (memcmp(Name.data()+0, "{sae}", 5) != 0)
4712
0
      break;
4713
796
    return MCK__123_sae_125_;  // "{sae}"
4714
29.0k
  case 6:  // 3 strings to match.
4715
29.0k
    if (memcmp(Name.data()+0, "{1to", 4) != 0)
4716
0
      break;
4717
29.0k
    switch (Name[4]) {
4718
29.0k
    
default: break0
;
4719
29.0k
    case '2':  // 1 string to match.
4720
1.05k
      if (Name[5] != '}')
4721
0
        break;
4722
1.05k
      return MCK__123_1to2_125_;   // "{1to2}"
4723
3.52k
    case '4':  // 1 string to match.
4724
3.52k
      if (Name[5] != '}')
4725
0
        break;
4726
3.52k
      return MCK__123_1to4_125_;   // "{1to4}"
4727
24.4k
    case '8':  // 1 string to match.
4728
24.4k
      if (Name[5] != '}')
4729
0
        break;
4730
24.4k
      return MCK__123_1to8_125_;  // "{1to8}"
4731
0
    }
4732
0
    break;
4733
13.8k
  case 7:  // 1 string to match.
4734
13.8k
    if (memcmp(Name.data()+0, "{1to16}", 7) != 0)
4735
0
      break;
4736
13.8k
    return MCK__123_1to16_125_;  // "{1to16}"
4737
0
  }
4738
0
  return InvalidMatchClass;
4739
0
}
4740
4741
/// isSubclass - Compute whether \p A is a subclass of \p B.
4742
1.85M
static bool isSubclass(MatchClassKind A, MatchClassKind B) {
4743
1.85M
  if (A == B)
4744
257k
    return true;
4745
1.59M
4746
1.59M
  switch (A) {
4747
1.59M
  default:
4748
796k
    return false;
4749
1.59M
4750
1.59M
  case MCK_Reg77:
4751
0
    switch (B) {
4752
0
    default: return false;
4753
0
    case MCK_Reg75: return true;
4754
0
    case MCK_Reg60: return true;
4755
0
    case MCK_Reg53: return true;
4756
0
    case MCK_Reg59: return true;
4757
0
    case MCK_GR64_NOREX: return true;
4758
0
    case MCK_GR64_TCW64: return true;
4759
0
    case MCK_GR64_TC: return true;
4760
0
    case MCK_GR64: return true;
4761
0
    case MCK_LOW32_ADDR_ACCESS: return true;
4762
0
    case MCK_LOW32_ADDR_ACCESS_RBP: return true;
4763
0
    }
4764
0
4765
3.11k
  case MCK_Reg76:
4766
3.11k
    switch (B) {
4767
3.11k
    
default: return false2.27k
;
4768
3.11k
    
case MCK_Reg74: return true0
;
4769
3.11k
    
case MCK_Reg55: return true0
;
4770
3.11k
    
case MCK_Reg60: return true0
;
4771
3.11k
    
case MCK_Reg50: return true0
;
4772
3.11k
    
case MCK_Reg58: return true0
;
4773
3.11k
    
case MCK_Reg53: return true0
;
4774
3.11k
    
case MCK_Reg59: return true0
;
4775
3.11k
    
case MCK_Reg56: return true0
;
4776
3.11k
    
case MCK_Reg44: return true0
;
4777
3.11k
    
case MCK_Reg51: return true0
;
4778
3.11k
    
case MCK_GR64_NOREX: return true0
;
4779
3.11k
    
case MCK_GR64_TCW64: return true0
;
4780
3.11k
    
case MCK_GR64_TC: return true0
;
4781
3.11k
    
case MCK_Reg45: return true0
;
4782
3.11k
    
case MCK_GR64: return true840
;
4783
0
    }
4784
0
4785
1.36k
  case MCK_Reg73:
4786
1.36k
    switch (B) {
4787
1.36k
    
default: return false975
;
4788
1.36k
    
case MCK_Reg75: return true0
;
4789
1.36k
    
case MCK_Reg74: return true0
;
4790
1.36k
    
case MCK_Reg72: return true0
;
4791
1.36k
    
case MCK_GR64_NOREX_NOSP: return true0
;
4792
1.36k
    
case MCK_Reg44: return true0
;
4793
1.36k
    
case MCK_Reg23: return true0
;
4794
1.36k
    
case MCK_GR64_NOREX: return true0
;
4795
1.36k
    
case MCK_GR64_NOSP: return true0
;
4796
1.36k
    
case MCK_Reg45: return true0
;
4797
1.36k
    
case MCK_Reg20: return true0
;
4798
1.36k
    
case MCK_GR64: return true389
;
4799
1.36k
    
case MCK_LOW32_ADDR_ACCESS_RBP: return true0
;
4800
0
    }
4801
0
4802
4.11k
  case MCK_Reg71:
4803
4.11k
    switch (B) {
4804
4.11k
    
default: return false2.12k
;
4805
4.11k
    
case MCK_Reg72: return true0
;
4806
4.11k
    
case MCK_Reg70: return true0
;
4807
4.11k
    
case MCK_Reg49: return true0
;
4808
4.11k
    
case MCK_Reg50: return true0
;
4809
4.11k
    
case MCK_Reg53: return true0
;
4810
4.11k
    
case MCK_GR64_NOREX_NOSP: return true0
;
4811
4.11k
    
case MCK_Reg54: return true0
;
4812
4.11k
    
case MCK_Reg44: return true0
;
4813
4.11k
    
case MCK_Reg51: return true0
;
4814
4.11k
    
case MCK_GR64_NOREX: return true0
;
4815
4.11k
    
case MCK_GR64_TC: return true0
;
4816
4.11k
    
case MCK_GR64_NOSP: return true0
;
4817
4.11k
    
case MCK_Reg45: return true0
;
4818
4.11k
    
case MCK_GR64: return true1.99k
;
4819
0
    }
4820
0
4821
2.00k
  case MCK_Reg69:
4822
2.00k
    switch (B) {
4823
2.00k
    
default: return false796
;
4824
2.00k
    
case MCK_Reg70: return true0
;
4825
2.00k
    
case MCK_Reg68: return true0
;
4826
2.00k
    
case MCK_Reg49: return true0
;
4827
2.00k
    
case MCK_Reg50: return true0
;
4828
2.00k
    
case MCK_Reg53: return true0
;
4829
2.00k
    
case MCK_GR64_NOREX_NOSP: return true0
;
4830
2.00k
    
case MCK_Reg54: return true0
;
4831
2.00k
    
case MCK_Reg44: return true0
;
4832
2.00k
    
case MCK_Reg51: return true0
;
4833
2.00k
    
case MCK_GR64_NOREX: return true0
;
4834
2.00k
    
case MCK_GR64_TC: return true0
;
4835
2.00k
    
case MCK_GR64_NOSP: return true0
;
4836
2.00k
    
case MCK_Reg45: return true0
;
4837
2.00k
    
case MCK_GR64: return true1.21k
;
4838
0
    }
4839
0
4840
364
  case MCK_Reg38:
4841
364
    switch (B) {
4842
364
    
default: return false219
;
4843
364
    
case MCK_GR32_BPSP: return true0
;
4844
364
    
case MCK_GR32_TC: return true0
;
4845
364
    
case MCK_GR32_NOREX: return true0
;
4846
364
    
case MCK_Reg23: return true0
;
4847
364
    
case MCK_GR32: return true145
;
4848
364
    
case MCK_Reg20: return true0
;
4849
364
    
case MCK_LOW32_ADDR_ACCESS: return true0
;
4850
364
    
case MCK_LOW32_ADDR_ACCESS_RBP: return true0
;
4851
0
    }
4852
0
4853
1.04k
  case MCK_Reg36:
4854
1.04k
    switch (B) {
4855
1.04k
    
default: return false554
;
4856
1.04k
    
case MCK_GR32_BPSP: return true0
;
4857
1.04k
    
case MCK_GR32_DIBP: return true0
;
4858
1.04k
    
case MCK_GR32_NOREX_NOSP: return true0
;
4859
1.04k
    
case MCK_GR32_NOREX: return true0
;
4860
1.04k
    
case MCK_Reg23: return true0
;
4861
1.04k
    
case MCK_GR32_NOSP: return true0
;
4862
1.04k
    
case MCK_GR32: return true495
;
4863
1.04k
    
case MCK_Reg20: return true0
;
4864
1.04k
    
case MCK_LOW32_ADDR_ACCESS: return true0
;
4865
1.04k
    
case MCK_LOW32_ADDR_ACCESS_RBP: return true0
;
4866
0
    }
4867
0
4868
3.73k
  case MCK_Reg34:
4869
3.73k
    switch (B) {
4870
3.73k
    
default: return false1.91k
;
4871
3.73k
    
case MCK_GR32_DIBP: return true0
;
4872
3.73k
    
case MCK_GR32_SIDI: return true0
;
4873
3.73k
    
case MCK_GR32_NOREX_NOSP: return true0
;
4874
3.73k
    
case MCK_GR32_NOREX: return true0
;
4875
3.73k
    
case MCK_Reg23: return true0
;
4876
3.73k
    
case MCK_GR32_NOSP: return true0
;
4877
3.73k
    
case MCK_GR32: return true1.81k
;
4878
3.73k
    
case MCK_Reg20: return true0
;
4879
3.73k
    
case MCK_LOW32_ADDR_ACCESS: return true0
;
4880
3.73k
    
case MCK_LOW32_ADDR_ACCESS_RBP: return true0
;
4881
0
    }
4882
0
4883
2.09k
  case MCK_Reg32:
4884
2.09k
    switch (B) {
4885
2.09k
    
default: return false959
;
4886
2.09k
    
case MCK_GR32_BSI: return true0
;
4887
2.09k
    
case MCK_GR32_SIDI: return true0
;
4888
2.09k
    
case MCK_GR32_NOREX_NOSP: return true0
;
4889
2.09k
    
case MCK_GR32_NOREX: return true0
;
4890
2.09k
    
case MCK_Reg23: return true0
;
4891
2.09k
    
case MCK_GR32_NOSP: return true0
;
4892
2.09k
    
case MCK_GR32: return true1.13k
;
4893
2.09k
    
case MCK_Reg20: return true0
;
4894
2.09k
    
case MCK_LOW32_ADDR_ACCESS: return true0
;
4895
2.09k
    
case MCK_LOW32_ADDR_ACCESS_RBP: return true0
;
4896
0
    }
4897
0
4898
7.26k
  case MCK_AL:
4899
7.26k
    switch (B) {
4900
7.26k
    
default: return false6.87k
;
4901
7.26k
    
case MCK_GR8_ABCD_L: return true0
;
4902
7.26k
    
case MCK_GR8_NOREX: return true0
;
4903
7.26k
    
case MCK_GR8: return true391
;
4904
0
    }
4905
0
4906
8.16k
  case MCK_AX:
4907
8.16k
    switch (B) {
4908
8.16k
    
default: return false7.84k
;
4909
8.16k
    
case MCK_GR16_ABCD: return true0
;
4910
8.16k
    
case MCK_GR16_NOREX: return true0
;
4911
8.16k
    
case MCK_GR16: return true318
;
4912
0
    }
4913
0
4914
5.18k
  case MCK_CL:
4915
5.18k
    switch (B) {
4916
5.18k
    
default: return false4.87k
;
4917
5.18k
    
case MCK_GR8_ABCD_L: return true0
;
4918
5.18k
    
case MCK_GR8_NOREX: return true0
;
4919
5.18k
    
case MCK_GR8: return true309
;
4920
0
    }
4921
0
4922
784
  case MCK_CS:
4923
784
    return B == MCK_SEGMENT_REG;
4924
0
4925
755
  case MCK_DS:
4926
755
    return B == MCK_SEGMENT_REG;
4927
0
4928
367
  case MCK_DX:
4929
367
    switch (B) {
4930
367
    
default: return false340
;
4931
367
    
case MCK_GR16_ABCD: return true0
;
4932
367
    
case MCK_GR16_NOREX: return true0
;
4933
367
    
case MCK_GR16: return true27
;
4934
0
    }
4935
0
4936
100k
  case MCK_EAX:
4937
100k
    switch (B) {
4938
100k
    
default: return false85.8k
;
4939
100k
    
case MCK_GR32_AD: return true0
;
4940
100k
    
case MCK_Reg15: return true0
;
4941
100k
    
case MCK_GR32_ABCD: return true0
;
4942
100k
    
case MCK_GR32_TC: return true0
;
4943
100k
    
case MCK_GR32_NOREX_NOSP: return true0
;
4944
100k
    
case MCK_GR32_NOREX: return true0
;
4945
100k
    
case MCK_Reg23: return true0
;
4946
100k
    
case MCK_GR32_NOSP: return true0
;
4947
100k
    
case MCK_GR32: return true14.8k
;
4948
100k
    
case MCK_Reg20: return true0
;
4949
100k
    
case MCK_LOW32_ADDR_ACCESS: return true0
;
4950
100k
    
case MCK_LOW32_ADDR_ACCESS_RBP: return true0
;