Coverage Report

Created: 2018-09-25 17:16

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/X86/X86GenAsmMatcher.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Assembly Matcher Source Fragment                                           *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
#ifdef GET_ASSEMBLER_HEADER
11
#undef GET_ASSEMBLER_HEADER
12
  // This should be included into the middle of the declaration of
13
  // your subclasses implementation of MCTargetAsmParser.
14
  uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;
15
  void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
16
                       const OperandVector &Operands);
17
  void convertToMapAndConstraints(unsigned Kind,
18
                           const OperandVector &Operands) override;
19
  unsigned MatchInstructionImpl(const OperandVector &Operands,
20
                                MCInst &Inst,
21
                                uint64_t &ErrorInfo,
22
                                bool matchingInlineAsm,
23
                                unsigned VariantID = 0);
24
#endif // GET_ASSEMBLER_HEADER_INFO
25
26
27
#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
28
#undef GET_OPERAND_DIAGNOSTIC_TYPES
29
30
#endif // GET_OPERAND_DIAGNOSTIC_TYPES
31
32
33
#ifdef GET_REGISTER_MATCHER
34
#undef GET_REGISTER_MATCHER
35
36
// Flags for subtarget features that participate in instruction matching.
37
enum SubtargetFeatureFlag : uint8_t {
38
  Feature_Not64BitMode = (1ULL << 4),
39
  Feature_In64BitMode = (1ULL << 2),
40
  Feature_In16BitMode = (1ULL << 0),
41
  Feature_Not16BitMode = (1ULL << 3),
42
  Feature_In32BitMode = (1ULL << 1),
43
  Feature_None = 0
44
};
45
46
319k
static unsigned MatchRegisterName(StringRef Name) {
47
319k
  switch (Name.size()) {
48
319k
  
default: break386
;
49
319k
  case 2:  // 33 strings to match.
50
35.7k
    switch (Name[0]) {
51
35.7k
    
default: break1.28k
;
52
35.7k
    case 'a':  // 3 strings to match.
53
1.34k
      switch (Name[1]) {
54
1.34k
      
default: break0
;
55
1.34k
      case 'h':  // 1 string to match.
56
4
        return 1;  // "ah"
57
1.34k
      case 'l':  // 1 string to match.
58
707
        return 2;  // "al"
59
1.34k
      case 'x':  // 1 string to match.
60
632
        return 3;  // "ax"
61
0
      }
62
0
      break;
63
322
    case 'b':  // 4 strings to match.
64
322
      switch (Name[1]) {
65
322
      
default: break0
;
66
322
      case 'h':  // 1 string to match.
67
0
        return 4;  // "bh"
68
322
      case 'l':  // 1 string to match.
69
129
        return 5;  // "bl"
70
322
      case 'p':  // 1 string to match.
71
15
        return 6;  // "bp"
72
322
      case 'x':  // 1 string to match.
73
178
        return 9;  // "bx"
74
0
      }
75
0
      break;
76
2.41k
    case 'c':  // 4 strings to match.
77
2.41k
      switch (Name[1]) {
78
2.41k
      
default: break0
;
79
2.41k
      case 'h':  // 1 string to match.
80
1
        return 10;  // "ch"
81
2.41k
      case 'l':  // 1 string to match.
82
1.77k
        return 11;  // "cl"
83
2.41k
      case 's':  // 1 string to match.
84
46
        return 12;  // "cs"
85
2.41k
      case 'x':  // 1 string to match.
86
599
        return 13;  // "cx"
87
0
      }
88
0
      break;
89
3.53k
    case 'd':  // 5 strings to match.
90
3.53k
      switch (Name[1]) {
91
3.53k
      
default: break0
;
92
3.53k
      case 'h':  // 1 string to match.
93
1
        return 15;  // "dh"
94
3.53k
      case 'i':  // 1 string to match.
95
2.96k
        return 16;  // "di"
96
3.53k
      case 'l':  // 1 string to match.
97
78
        return 19;  // "dl"
98
3.53k
      case 's':  // 1 string to match.
99
74
        return 20;  // "ds"
100
3.53k
      case 'x':  // 1 string to match.
101
413
        return 21;  // "dx"
102
0
      }
103
0
      break;
104
360
    case 'e':  // 1 string to match.
105
360
      if (Name[1] != 's')
106
0
        break;
107
360
      return 31;   // "es"
108
360
    case 'f':  // 1 string to match.
109
101
      if (Name[1] != 's')
110
0
        break;
111
101
      return 35;   // "fs"
112
210
    case 'g':  // 1 string to match.
113
210
      if (Name[1] != 's')
114
0
        break;
115
210
      return 36;   // "gs"
116
210
    case 'i':  // 1 string to match.
117
0
      if (Name[1] != 'p')
118
0
        break;
119
0
      return 46;   // "ip"
120
20.5k
    case 'k':  // 8 strings to match.
121
20.5k
      switch (Name[1]) {
122
20.5k
      
default: break0
;
123
20.5k
      case '0':  // 1 string to match.
124
5
        return 109;  // "k0"
125
20.5k
      case '1':  // 1 string to match.
126
1.32k
        return 110;  // "k1"
127
20.5k
      case '2':  // 1 string to match.
128
14.4k
        return 111;  // "k2"
129
20.5k
      case '3':  // 1 string to match.
130
1.27k
        return 112;  // "k3"
131
20.5k
      case '4':  // 1 string to match.
132
1.16k
        return 113;  // "k4"
133
20.5k
      case '5':  // 1 string to match.
134
1.00k
        return 114;  // "k5"
135
20.5k
      case '6':  // 1 string to match.
136
672
        return 115;  // "k6"
137
20.5k
      case '7':  // 1 string to match.
138
686
        return 116;  // "k7"
139
0
      }
140
0
      break;
141
738
    case 'r':  // 2 strings to match.
142
738
      switch (Name[1]) {
143
738
      
default: break6
;
144
738
      case '8':  // 1 string to match.
145
408
        return 125;  // "r8"
146
738
      case '9':  // 1 string to match.
147
324
        return 126;  // "r9"
148
6
      }
149
6
      break;
150
4.82k
    case 's':  // 3 strings to match.
151
4.82k
      switch (Name[1]) {
152
4.82k
      
default: break3.53k
;
153
4.82k
      case 'i':  // 1 string to match.
154
1.24k
        return 57;  // "si"
155
4.82k
      case 'p':  // 1 string to match.
156
0
        return 60;  // "sp"
157
4.82k
      case 's':  // 1 string to match.
158
42
        return 63;  // "ss"
159
3.53k
      }
160
3.53k
      break;
161
4.82k
    }
162
4.82k
    break;
163
127k
  case 3:  // 73 strings to match.
164
127k
    switch (Name[0]) {
165
127k
    
default: break594
;
166
127k
    case 'b':  // 1 string to match.
167
6
      if (memcmp(Name.data()+1, "pl", 2) != 0)
168
6
        break;
169
0
      return 8;  // "bpl"
170
21
    case 'c':  // 10 strings to match.
171
21
      if (Name[1] != 'r')
172
0
        break;
173
21
      switch (Name[2]) {
174
21
      
default: break0
;
175
21
      case '0':  // 1 string to match.
176
4
        return 69;  // "cr0"
177
21
      case '1':  // 1 string to match.
178
2
        return 70;  // "cr1"
179
21
      case '2':  // 1 string to match.
180
3
        return 71;  // "cr2"
181
21
      case '3':  // 1 string to match.
182
5
        return 72;  // "cr3"
183
21
      case '4':  // 1 string to match.
184
4
        return 73;  // "cr4"
185
21
      case '5':  // 1 string to match.
186
0
        return 74;  // "cr5"
187
21
      case '6':  // 1 string to match.
188
0
        return 75;  // "cr6"
189
21
      case '7':  // 1 string to match.
190
0
        return 76;  // "cr7"
191
21
      case '8':  // 1 string to match.
192
3
        return 77;  // "cr8"
193
21
      case '9':  // 1 string to match.
194
0
        return 78;  // "cr9"
195
0
      }
196
0
      break;
197
1.54k
    case 'd':  // 11 strings to match.
198
1.54k
      switch (Name[1]) {
199
1.54k
      
default: break2
;
200
1.54k
      case 'i':  // 1 string to match.
201
1.52k
        if (Name[2] != 'l')
202
0
          break;
203
1.52k
        return 18;   // "dil"
204
1.52k
      case 'r':  // 10 strings to match.
205
27
        switch (Name[2]) {
206
27
        
default: break0
;
207
27
        case '0':  // 1 string to match.
208
3
          return 85;  // "dr0"
209
27
        case '1':  // 1 string to match.
210
5
          return 86;  // "dr1"
211
27
        case '2':  // 1 string to match.
212
3
          return 87;  // "dr2"
213
27
        case '3':  // 1 string to match.
214
3
          return 88;  // "dr3"
215
27
        case '4':  // 1 string to match.
216
2
          return 89;  // "dr4"
217
27
        case '5':  // 1 string to match.
218
2
          return 90;  // "dr5"
219
27
        case '6':  // 1 string to match.
220
4
          return 91;  // "dr6"
221
27
        case '7':  // 1 string to match.
222
3
          return 92;  // "dr7"
223
27
        case '8':  // 1 string to match.
224
2
          return 93;  // "dr8"
225
27
        case '9':  // 1 string to match.
226
0
          return 94;  // "dr9"
227
0
        }
228
0
        break;
229
2
      }
230
2
      break;
231
41.4k
    case 'e':  // 10 strings to match.
232
41.4k
      switch (Name[1]) {
233
41.4k
      
default: break0
;
234
41.4k
      case 'a':  // 1 string to match.
235
16.6k
        if (Name[2] != 'x')
236
0
          break;
237
16.6k
        return 22;   // "eax"
238
16.6k
      case 'b':  // 2 strings to match.
239
2.98k
        switch (Name[2]) {
240
2.98k
        
default: break0
;
241
2.98k
        case 'p':  // 1 string to match.
242
355
          return 23;  // "ebp"
243
2.98k
        case 'x':  // 1 string to match.
244
2.63k
          return 24;  // "ebx"
245
0
        }
246
0
        break;
247
3.75k
      case 'c':  // 1 string to match.
248
3.75k
        if (Name[2] != 'x')
249
0
          break;
250
3.75k
        return 25;   // "ecx"
251
15.5k
      case 'd':  // 2 strings to match.
252
15.5k
        switch (Name[2]) {
253
15.5k
        
default: break0
;
254
15.5k
        case 'i':  // 1 string to match.
255
3.51k
          return 26;  // "edi"
256
15.5k
        case 'x':  // 1 string to match.
257
12.0k
          return 27;  // "edx"
258
0
        }
259
0
        break;
260
26
      case 'i':  // 2 strings to match.
261
26
        switch (Name[2]) {
262
26
        
default: break0
;
263
26
        case 'p':  // 1 string to match.
264
13
          return 29;  // "eip"
265
26
        case 'z':  // 1 string to match.
266
13
          return 30;  // "eiz"
267
0
        }
268
0
        break;
269
2.42k
      case 's':  // 2 strings to match.
270
2.42k
        switch (Name[2]) {
271
2.42k
        
default: break0
;
272
2.42k
        case 'i':  // 1 string to match.
273
1.64k
          return 32;  // "esi"
274
2.42k
        case 'p':  // 1 string to match.
275
782
          return 33;  // "esp"
276
0
        }
277
0
        break;
278
0
      }
279
0
      break;
280
27
    case 'f':  // 8 strings to match.
281
27
      if (Name[1] != 'p')
282
27
        break;
283
0
      switch (Name[2]) {
284
0
      default: break;
285
0
      case '0':  // 1 string to match.
286
0
        return 101;  // "fp0"
287
0
      case '1':  // 1 string to match.
288
0
        return 102;  // "fp1"
289
0
      case '2':  // 1 string to match.
290
0
        return 103;  // "fp2"
291
0
      case '3':  // 1 string to match.
292
0
        return 104;  // "fp3"
293
0
      case '4':  // 1 string to match.
294
0
        return 105;  // "fp4"
295
0
      case '5':  // 1 string to match.
296
0
        return 106;  // "fp5"
297
0
      case '6':  // 1 string to match.
298
0
        return 107;  // "fp6"
299
0
      case '7':  // 1 string to match.
300
0
        return 108;  // "fp7"
301
0
      }
302
0
      break;
303
4.87k
    case 'm':  // 8 strings to match.
304
4.87k
      if (Name[1] != 'm')
305
4
        break;
306
4.87k
      switch (Name[2]) {
307
4.87k
      
default: break0
;
308
4.87k
      case '0':  // 1 string to match.
309
883
        return 117;  // "mm0"
310
4.87k
      case '1':  // 1 string to match.
311
69
        return 118;  // "mm1"
312
4.87k
      case '2':  // 1 string to match.
313
1.79k
        return 119;  // "mm2"
314
4.87k
      case '3':  // 1 string to match.
315
1.12k
        return 120;  // "mm3"
316
4.87k
      case '4':  // 1 string to match.
317
990
        return 121;  // "mm4"
318
4.87k
      case '5':  // 1 string to match.
319
6
        return 122;  // "mm5"
320
4.87k
      case '6':  // 1 string to match.
321
2
        return 123;  // "mm6"
322
4.87k
      case '7':  // 1 string to match.
323
2
        return 124;  // "mm7"
324
0
      }
325
0
      break;
326
78.8k
    case 'r':  // 22 strings to match.
327
78.8k
      switch (Name[1]) {
328
78.8k
      
default: break4
;
329
78.8k
      case '1':  // 6 strings to match.
330
4.10k
        switch (Name[2]) {
331
4.10k
        
default: break0
;
332
4.10k
        case '0':  // 1 string to match.
333
178
          return 127;  // "r10"
334
4.10k
        case '1':  // 1 string to match.
335
96
          return 128;  // "r11"
336
4.10k
        case '2':  // 1 string to match.
337
44
          return 129;  // "r12"
338
4.10k
        case '3':  // 1 string to match.
339
41
          return 130;  // "r13"
340
4.10k
        case '4':  // 1 string to match.
341
3.38k
          return 131;  // "r14"
342
4.10k
        case '5':  // 1 string to match.
343
355
          return 132;  // "r15"
344
0
        }
345
0
        break;
346
12
      case '8':  // 3 strings to match.
347
12
        switch (Name[2]) {
348
12
        
default: break0
;
349
12
        case 'b':  // 1 string to match.
350
0
          return 237;  // "r8b"
351
12
        case 'd':  // 1 string to match.
352
12
          return 253;  // "r8d"
353
12
        case 'w':  // 1 string to match.
354
0
          return 261;  // "r8w"
355
0
        }
356
0
        break;
357
1
      case '9':  // 3 strings to match.
358
1
        switch (Name[2]) {
359
1
        
default: break0
;
360
1
        case 'b':  // 1 string to match.
361
0
          return 238;  // "r9b"
362
1
        case 'd':  // 1 string to match.
363
1
          return 254;  // "r9d"
364
1
        case 'w':  // 1 string to match.
365
0
          return 262;  // "r9w"
366
0
        }
367
0
        break;
368
25.4k
      case 'a':  // 1 string to match.
369
25.4k
        if (Name[2] != 'x')
370
0
          break;
371
25.4k
        return 47;   // "rax"
372
25.4k
      case 'b':  // 2 strings to match.
373
1.88k
        switch (Name[2]) {
374
1.88k
        
default: break0
;
375
1.88k
        case 'p':  // 1 string to match.
376
554
          return 48;  // "rbp"
377
1.88k
        case 'x':  // 1 string to match.
378
1.32k
          return 49;  // "rbx"
379
0
        }
380
0
        break;
381
6.85k
      case 'c':  // 1 string to match.
382
6.85k
        if (Name[2] != 'x')
383
0
          break;
384
6.85k
        return 50;   // "rcx"
385
35.0k
      case 'd':  // 2 strings to match.
386
35.0k
        switch (Name[2]) {
387
35.0k
        
default: break0
;
388
35.0k
        case 'i':  // 1 string to match.
389
5.18k
          return 51;  // "rdi"
390
35.0k
        case 'x':  // 1 string to match.
391
29.8k
          return 52;  // "rdx"
392
0
        }
393
0
        break;
394
436
      case 'i':  // 2 strings to match.
395
436
        switch (Name[2]) {
396
436
        
default: break0
;
397
436
        case 'p':  // 1 string to match.
398
428
          return 53;  // "rip"
399
436
        case 'z':  // 1 string to match.
400
8
          return 54;  // "riz"
401
0
        }
402
0
        break;
403
5.02k
      case 's':  // 2 strings to match.
404
5.02k
        switch (Name[2]) {
405
5.02k
        
default: break0
;
406
5.02k
        case 'i':  // 1 string to match.
407
3.47k
          return 55;  // "rsi"
408
5.02k
        case 'p':  // 1 string to match.
409
1.54k
          return 56;  // "rsp"
410
0
        }
411
0
        break;
412
4
      }
413
4
      break;
414
226
    case 's':  // 3 strings to match.
415
226
      switch (Name[1]) {
416
226
      
default: break13
;
417
226
      case 'i':  // 1 string to match.
418
213
        if (Name[2] != 'l')
419
0
          break;
420
213
        return 59;   // "sil"
421
213
      case 'p':  // 1 string to match.
422
0
        if (Name[2] != 'l')
423
0
          break;
424
0
        return 62;   // "spl"
425
0
      case 's':  // 1 string to match.
426
0
        if (Name[2] != 'p')
427
0
          break;
428
0
        return 64;  // "ssp"
429
13
      }
430
13
      break;
431
650
    }
432
650
    break;
433
88.1k
  case 4:  // 65 strings to match.
434
88.1k
    switch (Name[0]) {
435
88.1k
    
default: break243
;
436
88.1k
    case 'b':  // 4 strings to match.
437
26
      if (memcmp(Name.data()+1, "nd", 2) != 0)
438
2
        break;
439
24
      switch (Name[3]) {
440
24
      
default: break0
;
441
24
      case '0':  // 1 string to match.
442
3
        return 65;  // "bnd0"
443
24
      case '1':  // 1 string to match.
444
13
        return 66;  // "bnd1"
445
24
      case '2':  // 1 string to match.
446
3
        return 67;  // "bnd2"
447
24
      case '3':  // 1 string to match.
448
5
        return 68;  // "bnd3"
449
0
      }
450
0
      break;
451
1
    case 'c':  // 6 strings to match.
452
1
      if (memcmp(Name.data()+1, "r1", 2) != 0)
453
0
        break;
454
1
      switch (Name[3]) {
455
1
      
default: break0
;
456
1
      case '0':  // 1 string to match.
457
0
        return 79;  // "cr10"
458
1
      case '1':  // 1 string to match.
459
0
        return 80;  // "cr11"
460
1
      case '2':  // 1 string to match.
461
0
        return 81;  // "cr12"
462
1
      case '3':  // 1 string to match.
463
0
        return 82;  // "cr13"
464
1
      case '4':  // 1 string to match.
465
0
        return 83;  // "cr14"
466
1
      case '5':  // 1 string to match.
467
1
        return 84;  // "cr15"
468
0
      }
469
0
      break;
470
3
    case 'd':  // 6 strings to match.
471
3
      if (memcmp(Name.data()+1, "r1", 2) != 0)
472
2
        break;
473
1
      switch (Name[3]) {
474
1
      
default: break0
;
475
1
      case '0':  // 1 string to match.
476
0
        return 95;  // "dr10"
477
1
      case '1':  // 1 string to match.
478
0
        return 96;  // "dr11"
479
1
      case '2':  // 1 string to match.
480
0
        return 97;  // "dr12"
481
1
      case '3':  // 1 string to match.
482
0
        return 98;  // "dr13"
483
1
      case '4':  // 1 string to match.
484
0
        return 99;  // "dr14"
485
1
      case '5':  // 1 string to match.
486
1
        return 100;  // "dr15"
487
0
      }
488
0
      break;
489
0
    case 'f':  // 1 string to match.
490
0
      if (memcmp(Name.data()+1, "psw", 3) != 0)
491
0
        break;
492
0
      return 34;   // "fpsw"
493
1.18k
    case 'r':  // 18 strings to match.
494
1.18k
      if (Name[1] != '1')
495
0
        break;
496
1.18k
      switch (Name[2]) {
497
1.18k
      
default: break0
;
498
1.18k
      case '0':  // 3 strings to match.
499
33
        switch (Name[3]) {
500
33
        
default: break0
;
501
33
        case 'b':  // 1 string to match.
502
0
          return 239;  // "r10b"
503
33
        case 'd':  // 1 string to match.
504
33
          return 255;  // "r10d"
505
33
        case 'w':  // 1 string to match.
506
0
          return 263;  // "r10w"
507
0
        }
508
0
        break;
509
31
      case '1':  // 3 strings to match.
510
31
        switch (Name[3]) {
511
31
        
default: break0
;
512
31
        case 'b':  // 1 string to match.
513
4
          return 240;  // "r11b"
514
31
        case 'd':  // 1 string to match.
515
18
          return 256;  // "r11d"
516
31
        case 'w':  // 1 string to match.
517
9
          return 264;  // "r11w"
518
0
        }
519
0
        break;
520
18
      case '2':  // 3 strings to match.
521
18
        switch (Name[3]) {
522
18
        
default: break0
;
523
18
        case 'b':  // 1 string to match.
524
0
          return 241;  // "r12b"
525
18
        case 'd':  // 1 string to match.
526
18
          return 257;  // "r12d"
527
18
        case 'w':  // 1 string to match.
528
0
          return 265;  // "r12w"
529
0
        }
530
0
        break;
531
693
      case '3':  // 3 strings to match.
532
693
        switch (Name[3]) {
533
693
        
default: break0
;
534
693
        case 'b':  // 1 string to match.
535
0
          return 242;  // "r13b"
536
693
        case 'd':  // 1 string to match.
537
685
          return 258;  // "r13d"
538
693
        case 'w':  // 1 string to match.
539
8
          return 266;  // "r13w"
540
0
        }
541
0
        break;
542
396
      case '4':  // 3 strings to match.
543
396
        switch (Name[3]) {
544
396
        
default: break0
;
545
396
        case 'b':  // 1 string to match.
546
215
          return 243;  // "r14b"
547
396
        case 'd':  // 1 string to match.
548
12
          return 259;  // "r14d"
549
396
        case 'w':  // 1 string to match.
550
169
          return 267;  // "r14w"
551
0
        }
552
0
        break;
553
10
      case '5':  // 3 strings to match.
554
10
        switch (Name[3]) {
555
10
        
default: break0
;
556
10
        case 'b':  // 1 string to match.
557
0
          return 244;  // "r15b"
558
10
        case 'd':  // 1 string to match.
559
10
          return 260;  // "r15d"
560
10
        case 'w':  // 1 string to match.
561
0
          return 268;  // "r15w"
562
0
        }
563
0
        break;
564
0
      }
565
0
      break;
566
42.4k
    case 'x':  // 10 strings to match.
567
42.4k
      if (memcmp(Name.data()+1, "mm", 2) != 0)
568
0
        break;
569
42.4k
      switch (Name[3]) {
570
42.4k
      
default: break0
;
571
42.4k
      case '0':  // 1 string to match.
572
9.24k
        return 141;  // "xmm0"
573
42.4k
      case '1':  // 1 string to match.
574
11.5k
        return 142;  // "xmm1"
575
42.4k
      case '2':  // 1 string to match.
576
10.9k
        return 143;  // "xmm2"
577
42.4k
      case '3':  // 1 string to match.
578
1.37k
        return 144;  // "xmm3"
579
42.4k
      case '4':  // 1 string to match.
580
334
        return 145;  // "xmm4"
581
42.4k
      case '5':  // 1 string to match.
582
3.38k
        return 146;  // "xmm5"
583
42.4k
      case '6':  // 1 string to match.
584
4.93k
        return 147;  // "xmm6"
585
42.4k
      case '7':  // 1 string to match.
586
301
        return 148;  // "xmm7"
587
42.4k
      case '8':  // 1 string to match.
588
292
        return 149;  // "xmm8"
589
42.4k
      case '9':  // 1 string to match.
590
120
        return 150;  // "xmm9"
591
0
      }
592
0
      break;
593
21.8k
    case 'y':  // 10 strings to match.
594
21.8k
      if (memcmp(Name.data()+1, "mm", 2) != 0)
595
0
        break;
596
21.8k
      switch (Name[3]) {
597
21.8k
      
default: break0
;
598
21.8k
      case '0':  // 1 string to match.
599
2.95k
        return 173;  // "ymm0"
600
21.8k
      case '1':  // 1 string to match.
601
3.92k
        return 174;  // "ymm1"
602
21.8k
      case '2':  // 1 string to match.
603
3.91k
        return 175;  // "ymm2"
604
21.8k
      case '3':  // 1 string to match.
605
477
        return 176;  // "ymm3"
606
21.8k
      case '4':  // 1 string to match.
607
3.71k
        return 177;  // "ymm4"
608
21.8k
      case '5':  // 1 string to match.
609
201
        return 178;  // "ymm5"
610
21.8k
      case '6':  // 1 string to match.
611
127
        return 179;  // "ymm6"
612
21.8k
      case '7':  // 1 string to match.
613
3.25k
        return 180;  // "ymm7"
614
21.8k
      case '8':  // 1 string to match.
615
22
        return 181;  // "ymm8"
616
21.8k
      case '9':  // 1 string to match.
617
3.26k
        return 182;  // "ymm9"
618
0
      }
619
0
      break;
620
22.3k
    case 'z':  // 10 strings to match.
621
22.3k
      if (memcmp(Name.data()+1, "mm", 2) != 0)
622
0
        break;
623
22.3k
      switch (Name[3]) {
624
22.3k
      
default: break0
;
625
22.3k
      case '0':  // 1 string to match.
626
70
        return 205;  // "zmm0"
627
22.3k
      case '1':  // 1 string to match.
628
1.00k
        return 206;  // "zmm1"
629
22.3k
      case '2':  // 1 string to match.
630
15.8k
        return 207;  // "zmm2"
631
22.3k
      case '3':  // 1 string to match.
632
952
        return 208;  // "zmm3"
633
22.3k
      case '4':  // 1 string to match.
634
737
        return 209;  // "zmm4"
635
22.3k
      case '5':  // 1 string to match.
636
821
        return 210;  // "zmm5"
637
22.3k
      case '6':  // 1 string to match.
638
1.02k
        return 211;  // "zmm6"
639
22.3k
      case '7':  // 1 string to match.
640
637
        return 212;  // "zmm7"
641
22.3k
      case '8':  // 1 string to match.
642
593
        return 213;  // "zmm8"
643
22.3k
      case '9':  // 1 string to match.
644
602
        return 214;  // "zmm9"
645
0
      }
646
0
      break;
647
247
    }
648
247
    break;
649
67.6k
  case 5:  // 75 strings to match.
650
67.6k
    switch (Name[0]) {
651
67.6k
    
default: break59
;
652
67.6k
    case 'f':  // 1 string to match.
653
2
      if (memcmp(Name.data()+1, "lags", 4) != 0)
654
0
        break;
655
2
      return 28;   // "flags"
656
2
    case 's':  // 8 strings to match.
657
0
      if (memcmp(Name.data()+1, "t(", 2) != 0)
658
0
        break;
659
0
      switch (Name[3]) {
660
0
      default: break;
661
0
      case '0':  // 1 string to match.
662
0
        if (Name[4] != ')')
663
0
          break;
664
0
        return 133;  // "st(0)"
665
0
      case '1':  // 1 string to match.
666
0
        if (Name[4] != ')')
667
0
          break;
668
0
        return 134;  // "st(1)"
669
0
      case '2':  // 1 string to match.
670
0
        if (Name[4] != ')')
671
0
          break;
672
0
        return 135;  // "st(2)"
673
0
      case '3':  // 1 string to match.
674
0
        if (Name[4] != ')')
675
0
          break;
676
0
        return 136;  // "st(3)"
677
0
      case '4':  // 1 string to match.
678
0
        if (Name[4] != ')')
679
0
          break;
680
0
        return 137;  // "st(4)"
681
0
      case '5':  // 1 string to match.
682
0
        if (Name[4] != ')')
683
0
          break;
684
0
        return 138;  // "st(5)"
685
0
      case '6':  // 1 string to match.
686
0
        if (Name[4] != ')')
687
0
          break;
688
0
        return 139;  // "st(6)"
689
0
      case '7':  // 1 string to match.
690
0
        if (Name[4] != ')')
691
0
          break;
692
0
        return 140;  // "st(7)"
693
0
      }
694
0
      break;
695
23.0k
    case 'x':  // 22 strings to match.
696
23.0k
      if (memcmp(Name.data()+1, "mm", 2) != 0)
697
0
        break;
698
23.0k
      switch (Name[3]) {
699
23.0k
      
default: break0
;
700
23.0k
      case '1':  // 10 strings to match.
701
11.5k
        switch (Name[4]) {
702
11.5k
        
default: break0
;
703
11.5k
        case '0':  // 1 string to match.
704
526
          return 151;  // "xmm10"
705
11.5k
        case '1':  // 1 string to match.
706
690
          return 152;  // "xmm11"
707
11.5k
        case '2':  // 1 string to match.
708
937
          return 153;  // "xmm12"
709
11.5k
        case '3':  // 1 string to match.
710
821
          return 154;  // "xmm13"
711
11.5k
        case '4':  // 1 string to match.
712
380
          return 155;  // "xmm14"
713
11.5k
        case '5':  // 1 string to match.
714
4.85k
          return 156;  // "xmm15"
715
11.5k
        case '6':  // 1 string to match.
716
172
          return 157;  // "xmm16"
717
11.5k
        case '7':  // 1 string to match.
718
1.24k
          return 158;  // "xmm17"
719
11.5k
        case '8':  // 1 string to match.
720
837
          return 159;  // "xmm18"
721
11.5k
        case '9':  // 1 string to match.
722
1.12k
          return 160;  // "xmm19"
723
0
        }
724
0
        break;
725
10.5k
      case '2':  // 10 strings to match.
726
10.5k
        switch (Name[4]) {
727
10.5k
        
default: break0
;
728
10.5k
        case '0':  // 1 string to match.
729
1.07k
          return 161;  // "xmm20"
730
10.5k
        case '1':  // 1 string to match.
731
1.31k
          return 162;  // "xmm21"
732
10.5k
        case '2':  // 1 string to match.
733
1.02k
          return 163;  // "xmm22"
734
10.5k
        case '3':  // 1 string to match.
735
1.11k
          return 164;  // "xmm23"
736
10.5k
        case '4':  // 1 string to match.
737
953
          return 165;  // "xmm24"
738
10.5k
        case '5':  // 1 string to match.
739
1.01k
          return 166;  // "xmm25"
740
10.5k
        case '6':  // 1 string to match.
741
966
          return 167;  // "xmm26"
742
10.5k
        case '7':  // 1 string to match.
743
922
          return 168;  // "xmm27"
744
10.5k
        case '8':  // 1 string to match.
745
1.11k
          return 169;  // "xmm28"
746
10.5k
        case '9':  // 1 string to match.
747
1.05k
          return 170;  // "xmm29"
748
0
        }
749
0
        break;
750
871
      case '3':  // 2 strings to match.
751
871
        switch (Name[4]) {
752
871
        
default: break0
;
753
871
        case '0':  // 1 string to match.
754
637
          return 171;  // "xmm30"
755
871
        case '1':  // 1 string to match.
756
234
          return 172;  // "xmm31"
757
0
        }
758
0
        break;
759
0
      }
760
0
      break;
761
11.6k
    case 'y':  // 22 strings to match.
762
11.6k
      if (memcmp(Name.data()+1, "mm", 2) != 0)
763
0
        break;
764
11.6k
      switch (Name[3]) {
765
11.6k
      
default: break0
;
766
11.6k
      case '1':  // 10 strings to match.
767
2.91k
        switch (Name[4]) {
768
2.91k
        
default: break0
;
769
2.91k
        case '0':  // 1 string to match.
770
166
          return 183;  // "ymm10"
771
2.91k
        case '1':  // 1 string to match.
772
216
          return 184;  // "ymm11"
773
2.91k
        case '2':  // 1 string to match.
774
221
          return 185;  // "ymm12"
775
2.91k
        case '3':  // 1 string to match.
776
79
          return 186;  // "ymm13"
777
2.91k
        case '4':  // 1 string to match.
778
26
          return 187;  // "ymm14"
779
2.91k
        case '5':  // 1 string to match.
780
53
          return 188;  // "ymm15"
781
2.91k
        case '6':  // 1 string to match.
782
96
          return 189;  // "ymm16"
783
2.91k
        case '7':  // 1 string to match.
784
699
          return 190;  // "ymm17"
785
2.91k
        case '8':  // 1 string to match.
786
607
          return 191;  // "ymm18"
787
2.91k
        case '9':  // 1 string to match.
788
755
          return 192;  // "ymm19"
789
0
        }
790
0
        break;
791
8.18k
      case '2':  // 10 strings to match.
792
8.18k
        switch (Name[4]) {
793
8.18k
        
default: break0
;
794
8.18k
        case '0':  // 1 string to match.
795
834
          return 193;  // "ymm20"
796
8.18k
        case '1':  // 1 string to match.
797
1.00k
          return 194;  // "ymm21"
798
8.18k
        case '2':  // 1 string to match.
799
738
          return 195;  // "ymm22"
800
8.18k
        case '3':  // 1 string to match.
801
1.16k
          return 196;  // "ymm23"
802
8.18k
        case '4':  // 1 string to match.
803
692
          return 197;  // "ymm24"
804
8.18k
        case '5':  // 1 string to match.
805
833
          return 198;  // "ymm25"
806
8.18k
        case '6':  // 1 string to match.
807
834
          return 199;  // "ymm26"
808
8.18k
        case '7':  // 1 string to match.
809
641
          return 200;  // "ymm27"
810
8.18k
        case '8':  // 1 string to match.
811
778
          return 201;  // "ymm28"
812
8.18k
        case '9':  // 1 string to match.
813
660
          return 202;  // "ymm29"
814
0
        }
815
0
        break;
816
586
      case '3':  // 2 strings to match.
817
586
        switch (Name[4]) {
818
586
        
default: break0
;
819
586
        case '0':  // 1 string to match.
820
448
          return 203;  // "ymm30"
821
586
        case '1':  // 1 string to match.
822
138
          return 204;  // "ymm31"
823
0
        }
824
0
        break;
825
0
      }
826
0
      break;
827
32.8k
    case 'z':  // 22 strings to match.
828
32.8k
      if (memcmp(Name.data()+1, "mm", 2) != 0)
829
0
        break;
830
32.8k
      switch (Name[3]) {
831
32.8k
      
default: break0
;
832
32.8k
      case '1':  // 10 strings to match.
833
22.5k
        switch (Name[4]) {
834
22.5k
        
default: break0
;
835
22.5k
        case '0':  // 1 string to match.
836
587
          return 215;  // "zmm10"
837
22.5k
        case '1':  // 1 string to match.
838
460
          return 216;  // "zmm11"
839
22.5k
        case '2':  // 1 string to match.
840
677
          return 217;  // "zmm12"
841
22.5k
        case '3':  // 1 string to match.
842
504
          return 218;  // "zmm13"
843
22.5k
        case '4':  // 1 string to match.
844
738
          return 219;  // "zmm14"
845
22.5k
        case '5':  // 1 string to match.
846
456
          return 220;  // "zmm15"
847
22.5k
        case '6':  // 1 string to match.
848
635
          return 221;  // "zmm16"
849
22.5k
        case '7':  // 1 string to match.
850
1.04k
          return 222;  // "zmm17"
851
22.5k
        case '8':  // 1 string to match.
852
940
          return 223;  // "zmm18"
853
22.5k
        case '9':  // 1 string to match.
854
16.4k
          return 224;  // "zmm19"
855
0
        }
856
0
        break;
857
9.91k
      case '2':  // 10 strings to match.
858
9.91k
        switch (Name[4]) {
859
9.91k
        
default: break0
;
860
9.91k
        case '0':  // 1 string to match.
861
798
          return 225;  // "zmm20"
862
9.91k
        case '1':  // 1 string to match.
863
1.18k
          return 226;  // "zmm21"
864
9.91k
        case '2':  // 1 string to match.
865
1.19k
          return 227;  // "zmm22"
866
9.91k
        case '3':  // 1 string to match.
867
943
          return 228;  // "zmm23"
868
9.91k
        case '4':  // 1 string to match.
869
875
          return 229;  // "zmm24"
870
9.91k
        case '5':  // 1 string to match.
871
1.16k
          return 230;  // "zmm25"
872
9.91k
        case '6':  // 1 string to match.
873
904
          return 231;  // "zmm26"
874
9.91k
        case '7':  // 1 string to match.
875
788
          return 232;  // "zmm27"
876
9.91k
        case '8':  // 1 string to match.
877
1.09k
          return 233;  // "zmm28"
878
9.91k
        case '9':  // 1 string to match.
879
957
          return 234;  // "zmm29"
880
0
        }
881
0
        break;
882
457
      case '3':  // 2 strings to match.
883
457
        switch (Name[4]) {
884
457
        
default: break0
;
885
457
        case '0':  // 1 string to match.
886
456
          return 235;  // "zmm30"
887
457
        case '1':  // 1 string to match.
888
1
          return 236;  // "zmm31"
889
0
        }
890
0
        break;
891
0
      }
892
0
      break;
893
59
    }
894
59
    break;
895
59
  case 7:  // 1 string to match.
896
10
    if (memcmp(Name.data()+0, "dirflag", 7) != 0)
897
10
      break;
898
0
    return 14;  // "dirflag"
899
6.17k
  }
900
6.17k
  return 0;
901
6.17k
}
902
903
#endif // GET_REGISTER_MATCHER
904
905
906
#ifdef GET_SUBTARGET_FEATURE_NAME
907
#undef GET_SUBTARGET_FEATURE_NAME
908
909
// User-level names for subtarget features that participate in
910
// instruction matching.
911
20
static const char *getSubtargetFeatureName(uint64_t Val) {
912
20
  switch(Val) {
913
20
  
case Feature_Not64BitMode: return "Not 64-bit mode"5
;
914
20
  
case Feature_In64BitMode: return "64-bit mode"15
;
915
20
  
case Feature_In16BitMode: return "16-bit mode"0
;
916
20
  
case Feature_Not16BitMode: return "Not 16-bit mode"0
;
917
20
  
case Feature_In32BitMode: return "32-bit mode"0
;
918
20
  
default: return "(unknown)"0
;
919
20
  }
920
20
}
921
922
#endif // GET_SUBTARGET_FEATURE_NAME
923
924
925
#ifdef GET_MATCHER_IMPLEMENTATION
926
#undef GET_MATCHER_IMPLEMENTATION
927
928
172k
static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features, unsigned VariantID) {
929
172k
  switch (VariantID) {
930
172k
    case 0:
931
159k
      switch (Mnemonic.size()) {
932
159k
      
default: break22.2k
;
933
159k
      case 3:  // 6 strings to match.
934
12.1k
        switch (Mnemonic[0]) {
935
12.1k
        
default: break11.0k
;
936
12.1k
        case 'c':  // 4 strings to match.
937
202
          switch (Mnemonic[1]) {
938
202
          
default: break114
;
939
202
          case 'b':  // 1 string to match.
940
22
            if (Mnemonic[2] != 'w')
941
0
              break;
942
22
            Mnemonic = "cbtw";   // "cbw"
943
22
            return;
944
22
          case 'd':  // 1 string to match.
945
22
            if (Mnemonic[2] != 'q')
946
0
              break;
947
22
            Mnemonic = "cltd";   // "cdq"
948
22
            return;
949
22
          case 'q':  // 1 string to match.
950
22
            if (Mnemonic[2] != 'o')
951
0
              break;
952
22
            Mnemonic = "cqto";   // "cqo"
953
22
            return;
954
22
          case 'w':  // 1 string to match.
955
22
            if (Mnemonic[2] != 'd')
956
0
              break;
957
22
            Mnemonic = "cwtd";   // "cwd"
958
22
            return;
959
114
          }
960
114
          break;
961
327
        case 'p':  // 1 string to match.
962
327
          if (memcmp(Mnemonic.data()+1, "op", 2) != 0)
963
81
            break;
964
246
          if ((Features & Feature_In16BitMode) == Feature_In16BitMode)   // "pop"
965
3
            Mnemonic = "popw";
966
243
          else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
967
62
            Mnemonic = "popl";
968
181
          else if ((Features & Feature_In64BitMode) == Feature_In64BitMode)
969
181
            Mnemonic = "popq";
970
246
          return;
971
591
        case 'r':  // 1 string to match.
972
591
          if (memcmp(Mnemonic.data()+1, "et", 2) != 0)
973
14
            break;
974
577
          if ((Features & Feature_In16BitMode) == Feature_In16BitMode)   // "ret"
975
3
            Mnemonic = "retw";
976
574
          else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
977
208
            Mnemonic = "retl";
978
366
          else if ((Features & Feature_In64BitMode) == Feature_In64BitMode)
979
366
            Mnemonic = "retq";
980
577
          return;
981
11.2k
        }
982
11.2k
        break;
983
48.8k
      case 4:  // 18 strings to match.
984
48.8k
        switch (Mnemonic[0]) {
985
48.8k
        
default: break13.9k
;
986
48.8k
        case 'c':  // 3 strings to match.
987
1.32k
          switch (Mnemonic[1]) {
988
1.32k
          
default: break982
;
989
1.32k
          case 'a':  // 1 string to match.
990
289
            if (memcmp(Mnemonic.data()+2, "ll", 2) != 0)
991
0
              break;
992
289
            if ((Features & Feature_In16BitMode) == Feature_In16BitMode)   // "call"
993
2
              Mnemonic = "callw";
994
287
            else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
995
85
              Mnemonic = "calll";
996
202
            else if ((Features & Feature_In64BitMode) == Feature_In64BitMode)
997
202
              Mnemonic = "callq";
998
289
            return;
999
289
          case 'd':  // 1 string to match.
1000
22
            if (memcmp(Mnemonic.data()+2, "qe", 2) != 0)
1001
0
              break;
1002
22
            Mnemonic = "cltq";   // "cdqe"
1003
22
            return;
1004
33
          case 'w':  // 1 string to match.
1005
33
            if (memcmp(Mnemonic.data()+2, "de", 2) != 0)
1006
11
              break;
1007
22
            Mnemonic = "cwtl";   // "cwde"
1008
22
            return;
1009
993
          }
1010
993
          break;
1011
18.2k
        case 'i':  // 1 string to match.
1012
18.2k
          if (memcmp(Mnemonic.data()+1, "ret", 3) != 0)
1013
18.2k
            break;
1014
3
          if ((Features & Feature_In16BitMode) == Feature_In16BitMode)   // "iret"
1015
1
            Mnemonic = "iretw";
1016
2
          else if ((Features & Feature_Not16BitMode) == Feature_Not16BitMode)
1017
2
            Mnemonic = "iretl";
1018
3
          return;
1019
5.89k
        case 'l':  // 3 strings to match.
1020
5.89k
          switch (Mnemonic[1]) {
1021
5.89k
          
default: break5.82k
;
1022
5.89k
          case 'g':  // 1 string to match.
1023
13
            if (memcmp(Mnemonic.data()+2, "dt", 2) != 0)
1024
0
              break;
1025
13
            if ((Features & Feature_In16BitMode) == Feature_In16BitMode)   // "lgdt"
1026
4
              Mnemonic = "lgdtw";
1027
9
            else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1028
5
              Mnemonic = "lgdtl";
1029
4
            else if ((Features & Feature_In64BitMode) == Feature_In64BitMode)
1030
4
              Mnemonic = "lgdtq";
1031
13
            return;
1032
13
          case 'i':  // 1 string to match.
1033
3
            if (memcmp(Mnemonic.data()+2, "dt", 2) != 0)
1034
0
              break;
1035
3
            if ((Features & Feature_In16BitMode) == Feature_In16BitMode)   // "lidt"
1036
1
              Mnemonic = "lidtw";
1037
2
            else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1038
1
              Mnemonic = "lidtl";
1039
1
            else if ((Features & Feature_In64BitMode) == Feature_In64BitMode)
1040
1
              Mnemonic = "lidtq";
1041
3
            return;
1042
54
          case 'r':  // 1 string to match.
1043
54
            if (memcmp(Mnemonic.data()+2, "et", 2) != 0)
1044
0
              break;
1045
54
            if ((Features & Feature_In16BitMode) == Feature_In16BitMode)   // "lret"
1046
3
              Mnemonic = "lretw";
1047
51
            else if ((Features & Feature_Not16BitMode) == Feature_Not16BitMode)
1048
51
              Mnemonic = "lretl";
1049
54
            return;
1050
5.82k
          }
1051
5.82k
          break;
1052
5.82k
        case 'p':  // 3 strings to match.
1053
1.01k
          switch (Mnemonic[1]) {
1054
1.01k
          
default: break208
;
1055
1.01k
          case 'o':  // 2 strings to match.
1056
465
            if (Mnemonic[2] != 'p')
1057
0
              break;
1058
465
            switch (Mnemonic[3]) {
1059
465
            
default: break424
;
1060
465
            case 'a':  // 1 string to match.
1061
14
              if ((Features & Feature_In16BitMode) == Feature_In16BitMode)   // "popa"
1062
1
                Mnemonic = "popaw";
1063
13
              else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1064
13
                Mnemonic = "popal";
1065
14
              return;
1066
465
            case 'f':  // 1 string to match.
1067
27
              if ((Features & Feature_In16BitMode) == Feature_In16BitMode)   // "popf"
1068
1
                Mnemonic = "popfw";
1069
26
              else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1070
14
                Mnemonic = "popfl";
1071
12
              else if ((Features & Feature_In64BitMode) == Feature_In64BitMode)
1072
12
                Mnemonic = "popfq";
1073
27
              return;
1074
424
            }
1075
424
            break;
1076
424
          case 'u':  // 1 string to match.
1077
340
            if (memcmp(Mnemonic.data()+2, "sh", 2) != 0)
1078
0
              break;
1079
340
            if ((Features & Feature_In16BitMode) == Feature_In16BitMode)   // "push"
1080
6
              Mnemonic = "pushw";
1081
334
            else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1082
83
              Mnemonic = "pushl";
1083
251
            else if ((Features & Feature_In64BitMode) == Feature_In64BitMode)
1084
251
              Mnemonic = "pushq";
1085
340
            return;
1086
632
          }
1087
632
          break;
1088
3.19k
        case 'r':  // 1 string to match.
1089
3.19k
          if (memcmp(Mnemonic.data()+1, "etn", 3) != 0)
1090
3.18k
            break;
1091
6
          if ((Features & Feature_In16BitMode) == Feature_In16BitMode)   // "retn"
1092
2
            Mnemonic = "retw";
1093
4
          else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1094
2
            Mnemonic = "retl";
1095
2
          else if ((Features & Feature_In64BitMode) == Feature_In64BitMode)
1096
2
            Mnemonic = "retq";
1097
6
          return;
1098
5.25k
        case 's':  // 6 strings to match.
1099
5.25k
          switch (Mnemonic[1]) {
1100
5.25k
          
default: break4.43k
;
1101
5.25k
          case 'a':  // 4 strings to match.
1102
810
            if (Mnemonic[2] != 'l')
1103
747
              break;
1104
63
            switch (Mnemonic[3]) {
1105
63
            
default: break24
;
1106
63
            case 'b':  // 1 string to match.
1107
12
              Mnemonic = "shlb";   // "salb"
1108
12
              return;
1109
63
            case 'l':  // 1 string to match.
1110
21
              Mnemonic = "shll";   // "sall"
1111
21
              return;
1112
63
            case 'q':  // 1 string to match.
1113
2
              Mnemonic = "shlq";   // "salq"
1114
2
              return;
1115
63
            case 'w':  // 1 string to match.
1116
4
              Mnemonic = "shlw";   // "salw"
1117
4
              return;
1118
24
            }
1119
24
            break;
1120
24
          case 'g':  // 1 string to match.
1121
3
            if (memcmp(Mnemonic.data()+2, "dt", 2) != 0)
1122
0
              break;
1123
3
            if ((Features & Feature_In16BitMode) == Feature_In16BitMode)   // "sgdt"
1124
1
              Mnemonic = "sgdtw";
1125
2
            else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1126
1
              Mnemonic = "sgdtl";
1127
1
            else if ((Features & Feature_In64BitMode) == Feature_In64BitMode)
1128
1
              Mnemonic = "sgdtq";
1129
3
            return;
1130
3
          case 'i':  // 1 string to match.
1131
3
            if (memcmp(Mnemonic.data()+2, "dt", 2) != 0)
1132
0
              break;
1133
3
            if ((Features & Feature_In16BitMode) == Feature_In16BitMode)   // "sidt"
1134
1
              Mnemonic = "sidtw";
1135
2
            else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1136
1
              Mnemonic = "sidtl";
1137
1
            else if ((Features & Feature_In64BitMode) == Feature_In64BitMode)
1138
1
              Mnemonic = "sidtq";
1139
3
            return;
1140
5.20k
          }
1141
5.20k
          break;
1142
5.20k
        case 'u':  // 1 string to match.
1143
4
          if (memcmp(Mnemonic.data()+1, "d2a", 3) != 0)
1144
2
            break;
1145
2
          Mnemonic = "ud2";  // "ud2a"
1146
2
          return;
1147
47.9k
        }
1148
47.9k
        break;
1149
47.9k
      case 5:  // 9 strings to match.
1150
18.2k
        switch (Mnemonic[0]) {
1151
18.2k
        
default: break7.10k
;
1152
18.2k
        case 'f':  // 1 string to match.
1153
1.36k
          if (memcmp(Mnemonic.data()+1, "ildq", 4) != 0)
1154
1.36k
            break;
1155
6
          Mnemonic = "fildll";   // "fildq"
1156
6
          return;
1157
5.32k
        case 'p':  // 3 strings to match.
1158
5.32k
          switch (Mnemonic[1]) {
1159
5.32k
          
default: break4.72k
;
1160
5.32k
          case 'o':  // 1 string to match.
1161
40
            if (memcmp(Mnemonic.data()+2, "pfd", 3) != 0)
1162
38
              break;
1163
2
            Mnemonic = "popfl";  // "popfd"
1164
2
            return;
1165
556
          case 'u':  // 2 strings to match.
1166
556
            if (memcmp(Mnemonic.data()+2, "sh", 2) != 0)
1167
0
              break;
1168
556
            switch (Mnemonic[4]) {
1169
556
            
default: break517
;
1170
556
            case 'a':  // 1 string to match.
1171
13
              if ((Features & Feature_In16BitMode) == Feature_In16BitMode)   // "pusha"
1172
1
                Mnemonic = "pushaw";
1173
12
              else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1174
12
                Mnemonic = "pushal";
1175
13
              return;
1176
556
            case 'f':  // 1 string to match.
1177
26
              if ((Features & Feature_In16BitMode) == Feature_In16BitMode)   // "pushf"
1178
1
                Mnemonic = "pushfw";
1179
25
              else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1180
13
                Mnemonic = "pushfl";
1181
12
              else if ((Features & Feature_In64BitMode) == Feature_In64BitMode)
1182
12
                Mnemonic = "pushfq";
1183
26
              return;
1184
517
            }
1185
517
            break;
1186
5.28k
          }
1187
5.28k
          break;
1188
5.28k
        case 's':  // 4 strings to match.
1189
2.74k
          if (memcmp(Mnemonic.data()+1, "mov", 3) != 0)
1190
2.73k
            break;
1191
4
          switch (Mnemonic[4]) {
1192
4
          
default: break0
;
1193
4
          case 'b':  // 1 string to match.
1194
1
            Mnemonic = "movsb";  // "smovb"
1195
1
            return;
1196
4
          case 'l':  // 1 string to match.
1197
1
            Mnemonic = "movsl";  // "smovl"
1198
1
            return;
1199
4
          case 'q':  // 1 string to match.
1200
1
            Mnemonic = "movsq";  // "smovq"
1201
1
            return;
1202
4
          case 'w':  // 1 string to match.
1203
1
            Mnemonic = "movsw";  // "smovw"
1204
1
            return;
1205
0
          }
1206
0
          break;
1207
1.74k
        case 'v':  // 1 string to match.
1208
1.74k
          if (memcmp(Mnemonic.data()+1, "errw", 4) != 0)
1209
1.74k
            break;
1210
2
          Mnemonic = "verr";   // "verrw"
1211
2
          return;
1212
18.2k
        }
1213
18.2k
        break;
1214
18.7k
      case 6:  // 15 strings to match.
1215
18.7k
        switch (Mnemonic[0]) {
1216
18.7k
        
default: break13.2k
;
1217
18.7k
        case 'c':  // 6 strings to match.
1218
1.39k
          if (memcmp(Mnemonic.data()+1, "mov", 3) != 0)
1219
219
            break;
1220
1.18k
          switch (Mnemonic[4]) {
1221
1.18k
          
default: break1.04k
;
1222
1.18k
          case 'c':  // 3 strings to match.
1223
68
            switch (Mnemonic[5]) {
1224
68
            
default: break0
;
1225
68
            case 'l':  // 1 string to match.
1226
24
              Mnemonic = "cmovbl";   // "cmovcl"
1227
24
              return;
1228
68
            case 'q':  // 1 string to match.
1229
22
              Mnemonic = "cmovbq";   // "cmovcq"
1230
22
              return;
1231
68
            case 'w':  // 1 string to match.
1232
22
              Mnemonic = "cmovbw";   // "cmovcw"
1233
22
              return;
1234
0
            }
1235
0
            break;
1236
68
          case 'z':  // 3 strings to match.
1237
68
            switch (Mnemonic[5]) {
1238
68
            
default: break0
;
1239
68
            case 'l':  // 1 string to match.
1240
24
              Mnemonic = "cmovel";   // "cmovzl"
1241
24
              return;
1242
68
            case 'q':  // 1 string to match.
1243
22
              Mnemonic = "cmoveq";   // "cmovzq"
1244
22
              return;
1245
68
            case 'w':  // 1 string to match.
1246
22
              Mnemonic = "cmovew";   // "cmovzw"
1247
22
              return;
1248
0
            }
1249
0
            break;
1250
1.04k
          }
1251
1.04k
          break;
1252
1.57k
        case 'f':  // 4 strings to match.
1253
1.57k
          switch (Mnemonic[1]) {
1254
1.57k
          
default: break746
;
1255
1.57k
          case 'c':  // 2 strings to match.
1256
205
            if (memcmp(Mnemonic.data()+2, "mov", 3) != 0)
1257
126
              break;
1258
79
            switch (Mnemonic[5]) {
1259
79
            
default: break78
;
1260
79
            case 'a':  // 1 string to match.
1261
1
              Mnemonic = "fcmovnbe";   // "fcmova"
1262
1
              return;
1263
79
            case 'z':  // 1 string to match.
1264
0
              Mnemonic = "fcmove";   // "fcmovz"
1265
0
              return;
1266
78
            }
1267
78
            break;
1268
486
          case 'i':  // 1 string to match.
1269
486
            if (memcmp(Mnemonic.data()+2, "stpq", 4) != 0)
1270
486
              break;
1271
0
            Mnemonic = "fistpll";  // "fistpq"
1272
0
            return;
1273
137
          case 'l':  // 1 string to match.
1274
137
            if (memcmp(Mnemonic.data()+2, "dcww", 4) != 0)
1275
135
              break;
1276
2
            Mnemonic = "fldcw";  // "fldcww"
1277
2
            return;
1278
1.57k
          }
1279
1.57k
          break;
1280
1.57k
        case 'l':  // 2 strings to match.
1281
171
          if (memcmp(Mnemonic.data()+1, "eave", 4) != 0)
1282
166
            break;
1283
5
          switch (Mnemonic[5]) {
1284
5
          
default: break0
;
1285
5
          case 'l':  // 1 string to match.
1286
2
            if ((Features & Feature_Not64BitMode) == Feature_Not64BitMode)  // "leavel"
1287
2
              Mnemonic = "leave";
1288
2
            return;
1289
5
          case 'q':  // 1 string to match.
1290
3
            if ((Features & Feature_In64BitMode) == Feature_In64BitMode)  // "leaveq"
1291
3
              Mnemonic = "leave";
1292
3
            return;
1293
0
          }
1294
0
          break;
1295
1.98k
        case 'p':  // 1 string to match.
1296
1.98k
          if (memcmp(Mnemonic.data()+1, "ushfd", 5) != 0)
1297
1.98k
            break;
1298
2
          Mnemonic = "pushfl";   // "pushfd"
1299
2
          return;
1300
286
        case 's':  // 1 string to match.
1301
286
          if (memcmp(Mnemonic.data()+1, "ysret", 5) != 0)
1302
283
            break;
1303
3
          Mnemonic = "sysretl";  // "sysret"
1304
3
          return;
1305
73
        case 'x':  // 1 string to match.
1306
73
          if (memcmp(Mnemonic.data()+1, "saveq", 5) != 0)
1307
73
            break;
1308
0
          Mnemonic = "xsave64";  // "xsaveq"
1309
0
          return;
1310
18.6k
        }
1311
18.6k
        break;
1312
18.6k
      case 7:  // 34 strings to match.
1313
16.9k
        switch (Mnemonic[0]) {
1314
16.9k
        
default: break14.5k
;
1315
16.9k
        case 'c':  // 24 strings to match.
1316
1.63k
          if (memcmp(Mnemonic.data()+1, "mov", 3) != 0)
1317
31
            break;
1318
1.60k
          switch (Mnemonic[4]) {
1319
1.60k
          
default: break526
;
1320
1.60k
          case 'n':  // 18 strings to match.
1321
949
            switch (Mnemonic[5]) {
1322
949
            
default: break524
;
1323
949
            case 'a':  // 3 strings to match.
1324
70
              switch (Mnemonic[6]) {
1325
70
              
default: break2
;
1326
70
              case 'l':  // 1 string to match.
1327
24
                Mnemonic = "cmovbel";  // "cmovnal"
1328
24
                return;
1329
70
              case 'q':  // 1 string to match.
1330
22
                Mnemonic = "cmovbeq";  // "cmovnaq"
1331
22
                return;
1332
70
              case 'w':  // 1 string to match.
1333
22
                Mnemonic = "cmovbew";  // "cmovnaw"
1334
22
                return;
1335
2
              }
1336
2
              break;
1337
68
            case 'b':  // 3 strings to match.
1338
68
              switch (Mnemonic[6]) {
1339
68
              
default: break0
;
1340
68
              case 'l':  // 1 string to match.
1341
24
                Mnemonic = "cmovael";  // "cmovnbl"
1342
24
                return;
1343
68
              case 'q':  // 1 string to match.
1344
22
                Mnemonic = "cmovaeq";  // "cmovnbq"
1345
22
                return;
1346
68
              case 'w':  // 1 string to match.
1347
22
                Mnemonic = "cmovaew";  // "cmovnbw"
1348
22
                return;
1349
0
              }
1350
0
              break;
1351
68
            case 'c':  // 3 strings to match.
1352
68
              switch (Mnemonic[6]) {
1353
68
              
default: break0
;
1354
68
              case 'l':  // 1 string to match.
1355
24
                Mnemonic = "cmovael";  // "cmovncl"
1356
24
                return;
1357
68
              case 'q':  // 1 string to match.
1358
22
                Mnemonic = "cmovaeq";  // "cmovncq"
1359
22
                return;
1360
68
              case 'w':  // 1 string to match.
1361
22
                Mnemonic = "cmovaew";  // "cmovncw"
1362
22
                return;
1363
0
              }
1364
0
              break;
1365
70
            case 'g':  // 3 strings to match.
1366
70
              switch (Mnemonic[6]) {
1367
70
              
default: break0
;
1368
70
              case 'l':  // 1 string to match.
1369
26
                Mnemonic = "cmovlel";  // "cmovngl"
1370
26
                return;
1371
70
              case 'q':  // 1 string to match.
1372
22
                Mnemonic = "cmovleq";  // "cmovngq"
1373
22
                return;
1374
70
              case 'w':  // 1 string to match.
1375
22
                Mnemonic = "cmovlew";  // "cmovngw"
1376
22
                return;
1377
0
              }
1378
0
              break;
1379
76
            case 'l':  // 3 strings to match.
1380
76
              switch (Mnemonic[6]) {
1381
76
              
default: break2
;
1382
76
              case 'l':  // 1 string to match.
1383
26
                Mnemonic = "cmovgel";  // "cmovnll"
1384
26
                return;
1385
76
              case 'q':  // 1 string to match.
1386
24
                Mnemonic = "cmovgeq";  // "cmovnlq"
1387
24
                return;
1388
76
              case 'w':  // 1 string to match.
1389
24
                Mnemonic = "cmovgew";  // "cmovnlw"
1390
24
                return;
1391
2
              }
1392
2
              break;
1393
73
            case 'z':  // 3 strings to match.
1394
73
              switch (Mnemonic[6]) {
1395
73
              
default: break1
;
1396
73
              case 'l':  // 1 string to match.
1397
25
                Mnemonic = "cmovnel";  // "cmovnzl"
1398
25
                return;
1399
73
              case 'q':  // 1 string to match.
1400
24
                Mnemonic = "cmovneq";  // "cmovnzq"
1401
24
                return;
1402
73
              case 'w':  // 1 string to match.
1403
23
                Mnemonic = "cmovnew";  // "cmovnzw"
1404
23
                return;
1405
1
              }
1406
1
              break;
1407
529
            }
1408
529
            break;
1409
529
          case 'p':  // 6 strings to match.
1410
132
            switch (Mnemonic[5]) {
1411
132
            
default: break0
;
1412
132
            case 'e':  // 3 strings to match.
1413
66
              switch (Mnemonic[6]) {
1414
66
              
default: break0
;
1415
66
              case 'l':  // 1 string to match.
1416
22
                Mnemonic = "cmovpl";   // "cmovpel"
1417
22
                return;
1418
66
              case 'q':  // 1 string to match.
1419
22
                Mnemonic = "cmovpq";   // "cmovpeq"
1420
22
                return;
1421
66
              case 'w':  // 1 string to match.
1422
22
                Mnemonic = "cmovpw";   // "cmovpew"
1423
22
                return;
1424
0
              }
1425
0
              break;
1426
66
            case 'o':  // 3 strings to match.
1427
66
              switch (Mnemonic[6]) {
1428
66
              
default: break0
;
1429
66
              case 'l':  // 1 string to match.
1430
22
                Mnemonic = "cmovnpl";  // "cmovpol"
1431
22
                return;
1432
66
              case 'q':  // 1 string to match.
1433
22
                Mnemonic = "cmovnpq";  // "cmovpoq"
1434
22
                return;
1435
66
              case 'w':  // 1 string to match.
1436
22
                Mnemonic = "cmovnpw";  // "cmovpow"
1437
22
                return;
1438
0
              }
1439
0
              break;
1440
0
            }
1441
0
            break;
1442
1.05k
          }
1443
1.05k
          break;
1444
1.05k
        case 'f':  // 6 strings to match.
1445
714
          switch (Mnemonic[1]) {
1446
714
          
default: break157
;
1447
714
          case 'c':  // 2 strings to match.
1448
106
            if (memcmp(Mnemonic.data()+2, "mov", 3) != 0)
1449
0
              break;
1450
106
            switch (Mnemonic[5]) {
1451
106
            
default: break26
;
1452
106
            case 'a':  // 1 string to match.
1453
1
              if (Mnemonic[6] != 'e')
1454
0
                break;
1455
1
              Mnemonic = "fcmovnb";  // "fcmovae"
1456
1
              return;
1457
79
            case 'n':  // 1 string to match.
1458
79
              if (Mnemonic[6] != 'a')
1459
78
                break;
1460
1
              Mnemonic = "fcmovbe";  // "fcmovna"
1461
1
              return;
1462
104
            }
1463
104
            break;
1464
334
          case 'i':  // 1 string to match.
1465
334
            if (memcmp(Mnemonic.data()+2, "sttpq", 5) != 0)
1466
334
              break;
1467
0
            Mnemonic = "fisttpll";   // "fisttpq"
1468
0
            return;
1469
50
          case 'n':  // 2 strings to match.
1470
50
            if (memcmp(Mnemonic.data()+2, "st", 2) != 0)
1471
0
              break;
1472
50
            switch (Mnemonic[4]) {
1473
50
            
default: break46
;
1474
50
            case 'c':  // 1 string to match.
1475
2
              if (memcmp(Mnemonic.data()+5, "ww", 2) != 0)
1476
0
                break;
1477
2
              Mnemonic = "fnstcw";   // "fnstcww"
1478
2
              return;
1479
2
            case 's':  // 1 string to match.
1480
2
              if (memcmp(Mnemonic.data()+5, "ww", 2) != 0)
1481
0
                break;
1482
2
              Mnemonic = "fnstsw";   // "fnstsww"
1483
2
              return;
1484
46
            }
1485
46
            break;
1486
67
          case 'x':  // 1 string to match.
1487
67
            if (memcmp(Mnemonic.data()+2, "saveq", 5) != 0)
1488
66
              break;
1489
1
            Mnemonic = "fxsave64";   // "fxsaveq"
1490
1
            return;
1491
707
          }
1492
707
          break;
1493
707
        case 's':  // 1 string to match.
1494
53
          if (memcmp(Mnemonic.data()+1, "ysexit", 6) != 0)
1495
50
            break;
1496
3
          Mnemonic = "sysexitl";   // "sysexit"
1497
3
          return;
1498
26
        case 'x':  // 3 strings to match.
1499
26
          switch (Mnemonic[1]) {
1500
26
          
default: break0
;
1501
26
          case 'r':  // 1 string to match.
1502
20
            if (memcmp(Mnemonic.data()+2, "storq", 5) != 0)
1503
20
              break;
1504
0
            Mnemonic = "xrstor64";   // "xrstorq"
1505
0
            return;
1506
6
          case 's':  // 2 strings to match.
1507
6
            if (memcmp(Mnemonic.data()+2, "ave", 3) != 0)
1508
0
              break;
1509
6
            switch (Mnemonic[5]) {
1510
6
            default: break;
1511
6
            case 'c':  // 1 string to match.
1512
0
              if (Mnemonic[6] != 'q')
1513
0
                break;
1514
0
              Mnemonic = "xsavec64";   // "xsavecq"
1515
0
              return;
1516
0
            case 's':  // 1 string to match.
1517
0
              if (Mnemonic[6] != 'q')
1518
0
                break;
1519
0
              Mnemonic = "xsaves64";   // "xsavesq"
1520
0
              return;
1521
6
            }
1522
6
            break;
1523
26
          }
1524
26
          break;
1525
16.4k
        }
1526
16.4k
        break;
1527
16.4k
      case 8:  // 15 strings to match.
1528
9.66k
        switch (Mnemonic[0]) {
1529
9.66k
        
default: break8.50k
;
1530
9.66k
        case 'c':  // 12 strings to match.
1531
1.06k
          if (memcmp(Mnemonic.data()+1, "movn", 4) != 0)
1532
790
            break;
1533
278
          switch (Mnemonic[5]) {
1534
278
          
default: break0
;
1535
278
          case 'a':  // 3 strings to match.
1536
74
            if (Mnemonic[6] != 'e')
1537
0
              break;
1538
74
            switch (Mnemonic[7]) {
1539
74
            
default: break2
;
1540
74
            case 'l':  // 1 string to match.
1541
24
              Mnemonic = "cmovbl";   // "cmovnael"
1542
24
              return;
1543
74
            case 'q':  // 1 string to match.
1544
24
              Mnemonic = "cmovbq";   // "cmovnaeq"
1545
24
              return;
1546
74
            case 'w':  // 1 string to match.
1547
24
              Mnemonic = "cmovbw";   // "cmovnaew"
1548
24
              return;
1549
2
            }
1550
2
            break;
1551
68
          case 'b':  // 3 strings to match.
1552
68
            if (Mnemonic[6] != 'e')
1553
0
              break;
1554
68
            switch (Mnemonic[7]) {
1555
68
            
default: break0
;
1556
68
            case 'l':  // 1 string to match.
1557
24
              Mnemonic = "cmoval";   // "cmovnbel"
1558
24
              return;
1559
68
            case 'q':  // 1 string to match.
1560
22
              Mnemonic = "cmovaq";   // "cmovnbeq"
1561
22
              return;
1562
68
            case 'w':  // 1 string to match.
1563
22
              Mnemonic = "cmovaw";   // "cmovnbew"
1564
22
              return;
1565
0
            }
1566
0
            break;
1567
68
          case 'g':  // 3 strings to match.
1568
68
            if (Mnemonic[6] != 'e')
1569
0
              break;
1570
68
            switch (Mnemonic[7]) {
1571
68
            
default: break0
;
1572
68
            case 'l':  // 1 string to match.
1573
24
              Mnemonic = "cmovll";   // "cmovngel"
1574
24
              return;
1575
68
            case 'q':  // 1 string to match.
1576
22
              Mnemonic = "cmovlq";   // "cmovngeq"
1577
22
              return;
1578
68
            case 'w':  // 1 string to match.
1579
22
              Mnemonic = "cmovlw";   // "cmovngew"
1580
22
              return;
1581
0
            }
1582
0
            break;
1583
68
          case 'l':  // 3 strings to match.
1584
68
            if (Mnemonic[6] != 'e')
1585
0
              break;
1586
68
            switch (Mnemonic[7]) {
1587
68
            
default: break0
;
1588
68
            case 'l':  // 1 string to match.
1589
24
              Mnemonic = "cmovgl";   // "cmovnlel"
1590
24
              return;
1591
68
            case 'q':  // 1 string to match.
1592
22
              Mnemonic = "cmovgq";   // "cmovnleq"
1593
22
              return;
1594
68
            case 'w':  // 1 string to match.
1595
22
              Mnemonic = "cmovgw";   // "cmovnlew"
1596
22
              return;
1597
0
            }
1598
0
            break;
1599
2
          }
1600
2
          break;
1601
56
        case 'f':  // 2 strings to match.
1602
56
          switch (Mnemonic[1]) {
1603
56
          
default: break21
;
1604
56
          case 'c':  // 1 string to match.
1605
27
            if (memcmp(Mnemonic.data()+2, "movnae", 6) != 0)
1606
26
              break;
1607
1
            Mnemonic = "fcmovb";   // "fcmovnae"
1608
1
            return;
1609
8
          case 'x':  // 1 string to match.
1610
8
            if (memcmp(Mnemonic.data()+2, "rstorq", 6) != 0)
1611
7
              break;
1612
1
            Mnemonic = "fxrstor64";  // "fxrstorq"
1613
1
            return;
1614
54
          }
1615
54
          break;
1616
54
        case 'x':  // 1 string to match.
1617
42
          if (memcmp(Mnemonic.data()+1, "rstorsq", 7) != 0)
1618
42
            break;
1619
0
          Mnemonic = "xrstors64";  // "xrstorsq"
1620
0
          return;
1621
9.38k
        }
1622
9.38k
        break;
1623
12.1k
      case 9:  // 1 string to match.
1624
12.1k
        if (memcmp(Mnemonic.data()+0, "xsaveoptq", 9) != 0)
1625
12.1k
          break;
1626
0
        Mnemonic = "xsaveopt64";   // "xsaveoptq"
1627
0
        return;
1628
156k
      }
1629
156k
    break;
1630
156k
    case 1:
1631
13.8k
      switch (Mnemonic.size()) {
1632
13.8k
      
default: break6.84k
;
1633
13.8k
      case 3:  // 1 string to match.
1634
2.96k
        if (memcmp(Mnemonic.data()+0, "sal", 3) != 0)
1635
2.96k
          break;
1636
1
        Mnemonic = "shl";  // "sal"
1637
1
        return;
1638
401
      case 4:  // 7 strings to match.
1639
401
        switch (Mnemonic[0]) {
1640
401
        
default: break263
;
1641
401
        case 'l':  // 2 strings to match.
1642
41
          switch (Mnemonic[1]) {
1643
41
          
default: break9
;
1644
41
          case 'g':  // 1 string to match.
1645
16
            if (memcmp(Mnemonic.data()+2, "dt", 2) != 0)
1646
0
              break;
1647
16
            if ((Features & Feature_In16BitMode) == Feature_In16BitMode)   // "lgdt"
1648
8
              Mnemonic = "lgdtw";
1649
8
            else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1650
8
              Mnemonic = "lgdtd";
1651
16
            return;
1652
16
          case 'i':  // 1 string to match.
1653
16
            if (memcmp(Mnemonic.data()+2, "dt", 2) != 0)
1654
0
              break;
1655
16
            if ((Features & Feature_In16BitMode) == Feature_In16BitMode)   // "lidt"
1656
8
              Mnemonic = "lidtw";
1657
8
            else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1658
8
              Mnemonic = "lidtd";
1659
16
            return;
1660
9
          }
1661
9
          break;
1662
18
        case 'p':  // 2 strings to match.
1663
18
          if (memcmp(Mnemonic.data()+1, "op", 2) != 0)
1664
14
            break;
1665
4
          switch (Mnemonic[3]) {
1666
4
          
default: break0
;
1667
4
          case 'a':  // 1 string to match.
1668
3
            if ((Features & Feature_In16BitMode) == Feature_In16BitMode)   // "popa"
1669
0
              Mnemonic = "popaw";
1670
3
            else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1671
3
              Mnemonic = "popal";
1672
3
            return;
1673
4
          case 'f':  // 1 string to match.
1674
1
            if ((Features & Feature_In64BitMode) == Feature_In64BitMode)  // "popf"
1675
1
              Mnemonic = "popfq";
1676
1
            return;
1677
0
          }
1678
0
          break;
1679
3
        case 'r':  // 1 string to match.
1680
3
          if (memcmp(Mnemonic.data()+1, "etn", 3) != 0)
1681
3
            break;
1682
0
          Mnemonic = "ret";  // "retn"
1683
0
          return;
1684
76
        case 's':  // 2 strings to match.
1685
76
          switch (Mnemonic[1]) {
1686
76
          
default: break43
;
1687
76
          case 'g':  // 1 string to match.
1688
16
            if (memcmp(Mnemonic.data()+2, "dt", 2) != 0)
1689
0
              break;
1690
16
            if ((Features & Feature_In16BitMode) == Feature_In16BitMode)   // "sgdt"
1691
8
              Mnemonic = "sgdtw";
1692
8
            else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1693
8
              Mnemonic = "sgdtd";
1694
16
            return;
1695
17
          case 'i':  // 1 string to match.
1696
17
            if (memcmp(Mnemonic.data()+2, "dt", 2) != 0)
1697
0
              break;
1698
17
            if ((Features & Feature_In16BitMode) == Feature_In16BitMode)   // "sidt"
1699
8
              Mnemonic = "sidtw";
1700
9
            else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1701
8
              Mnemonic = "sidtd";
1702
17
            return;
1703
43
          }
1704
43
          break;
1705
332
        }
1706
332
        break;
1707
332
      case 5:  // 5 strings to match.
1708
296
        switch (Mnemonic[0]) {
1709
296
        
default: break252
;
1710
296
        case 'c':  // 2 strings to match.
1711
36
          if (memcmp(Mnemonic.data()+1, "mov", 3) != 0)
1712
34
            break;
1713
2
          switch (Mnemonic[4]) {
1714
2
          
default: break0
;
1715
2
          case 'c':  // 1 string to match.
1716
1
            Mnemonic = "cmovb";  // "cmovc"
1717
1
            return;
1718
2
          case 'z':  // 1 string to match.
1719
1
            Mnemonic = "cmove";  // "cmovz"
1720
1
            return;
1721
0
          }
1722
0
          break;
1723
8
        case 'p':  // 3 strings to match.
1724
8
          switch (Mnemonic[1]) {
1725
8
          
default: break0
;
1726
8
          case 'o':  // 1 string to match.
1727
4
            if (memcmp(Mnemonic.data()+2, "pad", 3) != 0)
1728
1
              break;
1729
3
            if ((Features & Feature_Not64BitMode) == Feature_Not64BitMode)  // "popad"
1730
3
              Mnemonic = "popal";
1731
3
            return;
1732
4
          case 'u':  // 2 strings to match.
1733
4
            if (memcmp(Mnemonic.data()+2, "sh", 2) != 0)
1734
0
              break;
1735
4
            switch (Mnemonic[4]) {
1736
4
            
default: break0
;
1737
4
            case 'a':  // 1 string to match.
1738
3
              if ((Features & Feature_In16BitMode) == Feature_In16BitMode)   // "pusha"
1739
0
                Mnemonic = "pushaw";
1740
3
              else if ((Features & Feature_In32BitMode) == Feature_In32BitMode)
1741
3
                Mnemonic = "pushal";
1742
3
              return;
1743
4
            case 'f':  // 1 string to match.
1744
1
              if ((Features & Feature_In64BitMode) == Feature_In64BitMode)  // "pushf"
1745
1
                Mnemonic = "pushfq";
1746
1
              return;
1747
0
            }
1748
0
            break;
1749
1
          }
1750
1
          break;
1751
287
        }
1752
287
        break;
1753
1.94k
      case 6:  // 9 strings to match.
1754
1.94k
        switch (Mnemonic[0]) {
1755
1.94k
        
default: break1.93k
;
1756
1.94k
        case 'c':  // 8 strings to match.
1757
10
          if (memcmp(Mnemonic.data()+1, "mov", 3) != 0)
1758
2
            break;
1759
8
          switch (Mnemonic[4]) {
1760
8
          
default: break0
;
1761
8
          case 'n':  // 6 strings to match.
1762
6
            switch (Mnemonic[5]) {
1763
6
            
default: break0
;
1764
6
            case 'a':  // 1 string to match.
1765
1
              Mnemonic = "cmovbe";   // "cmovna"
1766
1
              return;
1767
6
            case 'b':  // 1 string to match.
1768
1
              Mnemonic = "cmovae";   // "cmovnb"
1769
1
              return;
1770
6
            case 'c':  // 1 string to match.
1771
1
              Mnemonic = "cmovae";   // "cmovnc"
1772
1
              return;
1773
6
            case 'g':  // 1 string to match.
1774
1
              Mnemonic = "cmovle";   // "cmovng"
1775
1
              return;
1776
6
            case 'l':  // 1 string to match.
1777
1
              Mnemonic = "cmovge";   // "cmovnl"
1778
1
              return;
1779
6
            case 'z':  // 1 string to match.
1780
1
              Mnemonic = "cmovne";   // "cmovnz"
1781
1
              return;
1782
0
            }
1783
0
            break;
1784
2
          case 'p':  // 2 strings to match.
1785
2
            switch (Mnemonic[5]) {
1786
2
            
default: break0
;
1787
2
            case 'e':  // 1 string to match.
1788
1
              Mnemonic = "cmovp";  // "cmovpe"
1789
1
              return;
1790
2
            case 'o':  // 1 string to match.
1791
1
              Mnemonic = "cmovnp";   // "cmovpo"
1792
1
              return;
1793
0
            }
1794
0
            break;
1795
0
          }
1796
0
          break;
1797
4
        case 'p':  // 1 string to match.
1798
4
          if (memcmp(Mnemonic.data()+1, "ushad", 5) != 0)
1799
1
            break;
1800
3
          if ((Features & Feature_Not64BitMode) == Feature_Not64BitMode)  // "pushad"
1801
3
            Mnemonic = "pushal";
1802
3
          return;
1803
1.93k
        }
1804
1.93k
        break;
1805
1.93k
      case 7:  // 6 strings to match.
1806
1.42k
        switch (Mnemonic[0]) {
1807
1.42k
        
default: break1.42k
;
1808
1.42k
        case 'a':  // 1 string to match.
1809
1
          if (memcmp(Mnemonic.data()+1, "cquire", 6) != 0)
1810
0
            break;
1811
1
          Mnemonic = "xacquire";   // "acquire"
1812
1
          return;
1813
4
        case 'c':  // 4 strings to match.
1814
4
          if (memcmp(Mnemonic.data()+1, "movn", 4) != 0)
1815
0
            break;
1816
4
          switch (Mnemonic[5]) {
1817
4
          
default: break0
;
1818
4
          case 'a':  // 1 string to match.
1819
1
            if (Mnemonic[6] != 'e')
1820
0
              break;
1821
1
            Mnemonic = "cmovb";  // "cmovnae"
1822
1
            return;
1823
1
          case 'b':  // 1 string to match.
1824
1
            if (Mnemonic[6] != 'e')
1825
0
              break;
1826
1
            Mnemonic = "cmova";  // "cmovnbe"
1827
1
            return;
1828
1
          case 'g':  // 1 string to match.
1829
1
            if (Mnemonic[6] != 'e')
1830
0
              break;
1831
1
            Mnemonic = "cmovl";  // "cmovnge"
1832
1
            return;
1833
1
          case 'l':  // 1 string to match.
1834
1
            if (Mnemonic[6] != 'e')
1835
0
              break;
1836
1
            Mnemonic = "cmovg";  // "cmovnle"
1837
1
            return;
1838
0
          }
1839
0
          break;
1840
1
        case 'r':  // 1 string to match.
1841
1
          if (memcmp(Mnemonic.data()+1, "elease", 6) != 0)
1842
0
            break;
1843
1
          Mnemonic = "xrelease";   // "release"
1844
1
          return;
1845
1.42k
        }
1846
1.42k
        break;
1847
13.7k
      }
1848
13.7k
    break;
1849
170k
  }
1850
170k
  switch (Mnemonic.size()) {
1851
170k
  
default: break50.3k
;
1852
170k
  case 2:  // 2 strings to match.
1853
325
    if (Mnemonic[0] != 'j')
1854
36
      break;
1855
289
    switch (Mnemonic[1]) {
1856
289
    
default: break219
;
1857
289
    case 'c':  // 1 string to match.
1858
21
      Mnemonic = "jb";   // "jc"
1859
21
      return;
1860
289
    case 'z':  // 1 string to match.
1861
49
      Mnemonic = "je";   // "jz"
1862
49
      return;
1863
219
    }
1864
219
    break;
1865
14.2k
  case 3:  // 8 strings to match.
1866
14.2k
    if (Mnemonic[0] != 'j')
1867
13.6k
      break;
1868
601
    switch (Mnemonic[1]) {
1869
601
    
default: break359
;
1870
601
    case 'n':  // 6 strings to match.
1871
218
      switch (Mnemonic[2]) {
1872
218
      
default: break111
;
1873
218
      case 'a':  // 1 string to match.
1874
12
        Mnemonic = "jbe";  // "jna"
1875
12
        return;
1876
218
      case 'b':  // 1 string to match.
1877
12
        Mnemonic = "jae";  // "jnb"
1878
12
        return;
1879
218
      case 'c':  // 1 string to match.
1880
32
        Mnemonic = "jae";  // "jnc"
1881
32
        return;
1882
218
      case 'g':  // 1 string to match.
1883
12
        Mnemonic = "jle";  // "jng"
1884
12
        return;
1885
218
      case 'l':  // 1 string to match.
1886
12
        Mnemonic = "jge";  // "jnl"
1887
12
        return;
1888
218
      case 'z':  // 1 string to match.
1889
27
        Mnemonic = "jne";  // "jnz"
1890
27
        return;
1891
111
      }
1892
111
      break;
1893
111
    case 'p':  // 2 strings to match.
1894
24
      switch (Mnemonic[2]) {
1895
24
      
default: break0
;
1896
24
      case 'e':  // 1 string to match.
1897
12
        Mnemonic = "jp";   // "jpe"
1898
12
        return;
1899
24
      case 'o':  // 1 string to match.
1900
12
        Mnemonic = "jnp";  // "jpo"
1901
12
        return;
1902
0
      }
1903
0
      break;
1904
470
    }
1905
470
    break;
1906
48.3k
  case 4:  // 8 strings to match.
1907
48.3k
    switch (Mnemonic[0]) {
1908
48.3k
    
default: break39.7k
;
1909
48.3k
    case 'j':  // 4 strings to match.
1910
99
      if (Mnemonic[1] != 'n')
1911
51
        break;
1912
48
      switch (Mnemonic[2]) {
1913
48
      
default: break0
;
1914
48
      case 'a':  // 1 string to match.
1915
12
        if (Mnemonic[3] != 'e')
1916
0
          break;
1917
12
        Mnemonic = "jb";   // "jnae"
1918
12
        return;
1919
12
      case 'b':  // 1 string to match.
1920
12
        if (Mnemonic[3] != 'e')
1921
0
          break;
1922
12
        Mnemonic = "ja";   // "jnbe"
1923
12
        return;
1924
12
      case 'g':  // 1 string to match.
1925
12
        if (Mnemonic[3] != 'e')
1926
0
          break;
1927
12
        Mnemonic = "jl";   // "jnge"
1928
12
        return;
1929
12
      case 'l':  // 1 string to match.
1930
12
        if (Mnemonic[3] != 'e')
1931
0
          break;
1932
12
        Mnemonic = "jg";   // "jnle"
1933
12
        return;
1934
0
      }
1935
0
      break;
1936
3.18k
    case 'r':  // 2 strings to match.
1937
3.18k
      if (memcmp(Mnemonic.data()+1, "ep", 2) != 0)
1938
3.18k
        break;
1939
2
      switch (Mnemonic[3]) {
1940
2
      
default: break0
;
1941
2
      case 'e':  // 1 string to match.
1942
1
        Mnemonic = "rep";  // "repe"
1943
1
        return;
1944
2
      case 'z':  // 1 string to match.
1945
1
        Mnemonic = "rep";  // "repz"
1946
1
        return;
1947
0
      }
1948
0
      break;
1949
5.25k
    case 's':  // 2 strings to match.
1950
5.25k
      if (memcmp(Mnemonic.data()+1, "et", 2) != 0)
1951
4.76k
        break;
1952
488
      switch (Mnemonic[3]) {
1953
488
      
default: break438
;
1954
488
      case 'c':  // 1 string to match.
1955
6
        Mnemonic = "setb";   // "setc"
1956
6
        return;
1957
488
      case 'z':  // 1 string to match.
1958
44
        Mnemonic = "sete";   // "setz"
1959
44
        return;
1960
438
      }
1961
438
      break;
1962
48.2k
    }
1963
48.2k
    break;
1964
48.2k
  case 5:  // 11 strings to match.
1965
18.5k
    switch (Mnemonic[0]) {
1966
18.5k
    
default: break13.7k
;
1967
18.5k
    case 'f':  // 1 string to match.
1968
1.39k
      if (memcmp(Mnemonic.data()+1, "wait", 4) != 0)
1969
1.37k
        break;
1970
24
      Mnemonic = "wait";   // "fwait"
1971
24
      return;
1972
375
    case 'l':  // 1 string to match.
1973
375
      if (memcmp(Mnemonic.data()+1, "oopz", 4) != 0)
1974
364
        break;
1975
11
      Mnemonic = "loope";  // "loopz"
1976
11
      return;
1977
256
    case 'r':  // 1 string to match.
1978
256
      if (memcmp(Mnemonic.data()+1, "epnz", 4) != 0)
1979
255
        break;
1980
1
      Mnemonic = "repne";  // "repnz"
1981
1
      return;
1982
2.74k
    case 's':  // 8 strings to match.
1983
2.74k
      if (memcmp(Mnemonic.data()+1, "et", 2) != 0)
1984
2.19k
        break;
1985
547
      switch (Mnemonic[3]) {
1986
547
      
default: break137
;
1987
547
      case 'n':  // 6 strings to match.
1988
404
        switch (Mnemonic[4]) {
1989
404
        
default: break221
;
1990
404
        case 'a':  // 1 string to match.
1991
23
          Mnemonic = "setbe";  // "setna"
1992
23
          return;
1993
404
        case 'b':  // 1 string to match.
1994
45
          Mnemonic = "setae";  // "setnb"
1995
45
          return;
1996
404
        case 'c':  // 1 string to match.
1997
3
          Mnemonic = "setae";  // "setnc"
1998
3
          return;
1999
404
        case 'g':  // 1 string to match.
2000
23
          Mnemonic = "setle";  // "setng"
2001
23
          return;
2002
404
        case 'l':  // 1 string to match.
2003
45
          Mnemonic = "setge";  // "setnl"
2004
45
          return;
2005
404
        case 'z':  // 1 string to match.
2006
44
          Mnemonic = "setne";  // "setnz"
2007
44
          return;
2008
221
        }
2009
221
        break;
2010
221
      case 'p':  // 2 strings to match.
2011
6
        switch (Mnemonic[4]) {
2012
6
        
default: break0
;
2013
6
        case 'e':  // 1 string to match.
2014
3
          Mnemonic = "setp";   // "setpe"
2015
3
          return;
2016
6
        case 'o':  // 1 string to match.
2017
3
          Mnemonic = "setnp";  // "setpo"
2018
3
          return;
2019
0
        }
2020
0
        break;
2021
358
      }
2022
358
      break;
2023
18.2k
    }
2024
18.2k
    break;
2025
20.5k
  case 6:  // 6 strings to match.
2026
20.5k
    switch (Mnemonic[0]) {
2027
20.5k
    
default: break18.4k
;
2028
20.5k
    case 'f':  // 1 string to match.
2029
1.61k
      if (memcmp(Mnemonic.data()+1, "comip", 5) != 0)
2030
1.59k
        break;
2031
14
      Mnemonic = "fcompi";   // "fcomip"
2032
14
      return;
2033
174
    case 'l':  // 1 string to match.
2034
174
      if (memcmp(Mnemonic.data()+1, "oopnz", 5) != 0)
2035
163
        break;
2036
11
      Mnemonic = "loopne";   // "loopnz"
2037
11
      return;
2038
288
    case 's':  // 4 strings to match.
2039
288
      if (memcmp(Mnemonic.data()+1, "etn", 3) != 0)
2040
230
        break;
2041
58
      switch (Mnemonic[4]) {
2042
58
      
default: break0
;
2043
58
      case 'a':  // 1 string to match.
2044
5
        if (Mnemonic[5] != 'e')
2045
0
          break;
2046
5
        Mnemonic = "setb";   // "setnae"
2047
5
        return;
2048
25
      case 'b':  // 1 string to match.
2049
25
        if (Mnemonic[5] != 'e')
2050
0
          break;
2051
25
        Mnemonic = "seta";   // "setnbe"
2052
25
        return;
2053
25
      case 'g':  // 1 string to match.
2054
3
        if (Mnemonic[5] != 'e')
2055
0
          break;
2056
3
        Mnemonic = "setl";   // "setnge"
2057
3
        return;
2058
25
      case 'l':  // 1 string to match.
2059
25
        if (Mnemonic[5] != 'e')
2060
0
          break;
2061
25
        Mnemonic = "setg";   // "setnle"
2062
25
        return;
2063
0
      }
2064
0
      break;
2065
20.4k
    }
2066
20.4k
    break;
2067
20.4k
  case 7:  // 1 string to match.
2068
17.8k
    if (memcmp(Mnemonic.data()+0, "fucomip", 7) != 0)
2069
17.8k
      break;
2070
14
    Mnemonic = "fucompi";  // "fucomip"
2071
14
    return;
2072
170k
  }
2073
170k
}
2074
2075
enum {
2076
  Tie0_1_1,
2077
  Tie0_2_2,
2078
  Tie0_3_3,
2079
  Tie0_4_4,
2080
  Tie1_1_1,
2081
  Tie1_2_2,
2082
  Tie1_3_3,
2083
  Tie1_4_4,
2084
};
2085
2086
static const uint8_t TiedAsmOperandTable[][3] = {
2087
  /* Tie0_1_1 */ { 0, 1, 1 },
2088
  /* Tie0_2_2 */ { 0, 2, 2 },
2089
  /* Tie0_3_3 */ { 0, 3, 3 },
2090
  /* Tie0_4_4 */ { 0, 4, 4 },
2091
  /* Tie1_1_1 */ { 1, 1, 1 },
2092
  /* Tie1_2_2 */ { 1, 2, 2 },
2093
  /* Tie1_3_3 */ { 1, 3, 3 },
2094
  /* Tie1_4_4 */ { 1, 4, 4 },
2095
};
2096
2097
namespace {
2098
enum OperatorConversionKind {
2099
  CVT_Done,
2100
  CVT_Reg,
2101
  CVT_Tied,
2102
  CVT_imm_95_10,
2103
  CVT_95_addImmOperands,
2104
  CVT_regAX,
2105
  CVT_regEAX,
2106
  CVT_regRAX,
2107
  CVT_95_Reg,
2108
  CVT_95_addMemOperands,
2109
  CVT_95_addAbsMemOperands,
2110
  CVT_95_addDstIdxOperands,
2111
  CVT_95_addSrcIdxOperands,
2112
  CVT_95_addGR32orGR64Operands,
2113
  CVT_regST1,
2114
  CVT_regST0,
2115
  CVT_95_addMemOffsOperands,
2116
  CVT_imm_95_17,
2117
  CVT_imm_95_1,
2118
  CVT_imm_95_16,
2119
  CVT_imm_95_0,
2120
  CVT_95_addAVX512RCOperands,
2121
  CVT_NUM_CONVERTERS
2122
};
2123
2124
enum InstructionConversionKind {
2125
  Convert_NoOperands,
2126
  Convert__imm_95_10,
2127
  Convert__Imm1_0,
2128
  Convert__Imm1_1,
2129
  Convert__regAX__Tie0_1_1__ImmSExti16i81_1,
2130
  Convert__regEAX__Tie0_1_1__ImmSExti32i81_1,
2131
  Convert__regRAX__Tie0_1_1__ImmSExti64i81_1,
2132
  Convert__ImmSExti64i321_1,
2133
  Convert__Reg1_0__Tie0_1_1__Reg1_1,
2134
  Convert__Reg1_0__Tie0_1_1__ImmSExti16i81_1,
2135
  Convert__Reg1_0__Tie0_1_1__Imm1_1,
2136
  Convert__Reg1_0__Tie0_1_1__Mem165_1,
2137
  Convert__Reg1_0__Tie0_1_1__ImmSExti32i81_1,
2138
  Convert__Reg1_0__Tie0_1_1__Mem325_1,
2139
  Convert__Reg1_0__Tie0_1_1__ImmSExti64i81_1,
2140
  Convert__Reg1_0__Tie0_1_1__ImmSExti64i321_1,
2141
  Convert__Reg1_0__Tie0_1_1__Mem645_1,
2142
  Convert__Reg1_0__Tie0_1_1__Mem85_1,
2143
  Convert__Mem165_0__Reg1_1,
2144
  Convert__Mem165_0__ImmSExti16i81_1,
2145
  Convert__Mem165_0__Imm1_1,
2146
  Convert__Mem325_0__Reg1_1,
2147
  Convert__Mem325_0__ImmSExti32i81_1,
2148
  Convert__Mem325_0__Imm1_1,
2149
  Convert__Mem645_0__Reg1_1,
2150
  Convert__Mem645_0__ImmSExti64i81_1,
2151
  Convert__Mem645_0__ImmSExti64i321_1,
2152
  Convert__Mem85_0__Reg1_1,
2153
  Convert__Mem85_0__Imm1_1,
2154
  Convert__Reg1_1__Tie0_2_2__Reg1_0,
2155
  Convert__Mem85_1__Reg1_0,
2156
  Convert__Reg1_1__Tie0_2_2__Imm1_0,
2157
  Convert__Mem85_1__Imm1_0,
2158
  Convert__Reg1_1__Tie0_2_2__Mem85_0,
2159
  Convert__Mem325_1__Reg1_0,
2160
  Convert__regEAX__Tie0_1_1__ImmSExti32i81_0,
2161
  Convert__Reg1_1__Tie0_2_2__ImmSExti32i81_0,
2162
  Convert__Mem325_1__ImmSExti32i81_0,
2163
  Convert__Mem325_1__Imm1_0,
2164
  Convert__Reg1_1__Tie0_2_2__Mem325_0,
2165
  Convert__Mem645_1__Reg1_0,
2166
  Convert__regRAX__Tie0_1_1__ImmSExti64i81_0,
2167
  Convert__Reg1_1__Tie0_2_2__ImmSExti64i81_0,
2168
  Convert__Mem645_1__ImmSExti64i81_0,
2169
  Convert__ImmSExti64i321_0,
2170
  Convert__Reg1_1__Tie0_2_2__ImmSExti64i321_0,
2171
  Convert__Mem645_1__ImmSExti64i321_0,
2172
  Convert__Reg1_1__Tie0_2_2__Mem645_0,
2173
  Convert__Mem165_1__Reg1_0,
2174
  Convert__regAX__Tie0_1_1__ImmSExti16i81_0,
2175
  Convert__Reg1_1__Tie0_2_2__ImmSExti16i81_0,
2176
  Convert__Mem165_1__ImmSExti16i81_0,
2177
  Convert__Mem165_1__Imm1_0,
2178
  Convert__Reg1_1__Tie0_2_2__Mem165_0,
2179
  Convert__Reg1_1__Tie0_1_1__Reg1_0,
2180
  Convert__Reg1_1__Tie0_1_1__Mem325_0,
2181
  Convert__Reg1_1__Tie0_1_1__Mem645_0,
2182
  Convert__Reg1_0__Tie0_1_1__Mem1285_1,
2183
  Convert__Reg1_1__Tie0_1_1__Mem1285_0,
2184
  Convert__Reg1_1__Reg1_0,
2185
  Convert__Reg1_0__Reg1_1,
2186
  Convert__Reg1_0__Mem1285_1,
2187
  Convert__Reg1_1__Mem1285_0,
2188
  Convert__Reg1_0__Reg1_1__ImmUnsignedi81_2,
2189
  Convert__Reg1_0__Mem1285_1__ImmUnsignedi81_2,
2190
  Convert__Reg1_2__Reg1_1__ImmUnsignedi81_0,
2191
  Convert__Reg1_2__Mem1285_1__ImmUnsignedi81_0,
2192
  Convert__Reg1_0__Reg1_1__Reg1_2,
2193
  Convert__Reg1_0__Reg1_1__Mem325_2,
2194
  Convert__Reg1_0__Reg1_1__Mem645_2,
2195
  Convert__Reg1_2__Reg1_1__Reg1_0,
2196
  Convert__Reg1_2__Reg1_1__Mem325_0,
2197
  Convert__Reg1_2__Reg1_1__Mem645_0,
2198
  Convert__Reg1_0__Reg1_1__Imm1_2,
2199
  Convert__Reg1_0__Mem325_1__Reg1_2,
2200
  Convert__Reg1_0__Mem325_1__Imm1_2,
2201
  Convert__Reg1_0__Reg1_1__ImmSExti64i321_2,
2202
  Convert__Reg1_0__Mem645_1__Reg1_2,
2203
  Convert__Reg1_0__Mem645_1__ImmSExti64i321_2,
2204
  Convert__Reg1_2__Mem325_1__Reg1_0,
2205
  Convert__Reg1_2__Reg1_1__Imm1_0,
2206
  Convert__Reg1_2__Mem325_1__Imm1_0,
2207
  Convert__Reg1_2__Mem645_1__Reg1_0,
2208
  Convert__Reg1_2__Reg1_1__ImmSExti64i321_0,
2209
  Convert__Reg1_2__Mem645_1__ImmSExti64i321_0,
2210
  Convert__Reg1_0__Mem325_1,
2211
  Convert__Reg1_0__Mem645_1,
2212
  Convert__Reg1_1__Mem325_0,
2213
  Convert__Reg1_1__Mem645_0,
2214
  Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmUnsignedi81_2,
2215
  Convert__Reg1_0__Tie0_1_1__Mem1285_1__ImmUnsignedi81_2,
2216
  Convert__Reg1_2__Tie0_1_1__Reg1_1__ImmUnsignedi81_0,
2217
  Convert__Reg1_2__Tie0_1_1__Mem1285_1__ImmUnsignedi81_0,
2218
  Convert__Reg1_1__Tie0_2_2__Mem1285_0,
2219
  Convert__Reg1_2__Tie0_1_1__Reg1_1,
2220
  Convert__Reg1_2__Tie0_1_1__Mem1285_1,
2221
  Convert__Reg1_0__Mem5_1,
2222
  Convert__Reg1_1__Mem5_0,
2223
  Convert__Mem1285_1__Reg1_0,
2224
  Convert__Mem1285_0__Reg1_1,
2225
  Convert__Mem5_1__Reg1_0,
2226
  Convert__Mem5_0__Reg1_1,
2227
  Convert__Reg1_0__Mem165_1,
2228
  Convert__Reg1_1__Mem165_0,
2229
  Convert__Reg1_0__Tie0_1_1,
2230
  Convert__Reg1_0__ImmSExti16i81_1,
2231
  Convert__Reg1_0__ImmSExti32i81_1,
2232
  Convert__Reg1_0__ImmSExti64i81_1,
2233
  Convert__Reg1_1__ImmSExti32i81_0,
2234
  Convert__Reg1_1__ImmSExti64i81_0,
2235
  Convert__Reg1_1__ImmSExti16i81_0,
2236
  Convert__Reg1_0,
2237
  Convert__AbsMem1_0,
2238
  Convert__Mem165_0,
2239
  Convert__Mem325_0,
2240
  Convert__Mem645_0,
2241
  Convert__Mem5_0,
2242
  Convert__Imm1_1__Imm1_0,
2243
  Convert__Reg1_1,
2244
  Convert__Mem325_1,
2245
  Convert__Mem645_1,
2246
  Convert__Mem165_1,
2247
  Convert__Mem85_0,
2248
  Convert__Reg1_0__Tie0_1_1__Reg1_0,
2249
  Convert__Reg1_1__Tie0_1_1__Mem165_0,
2250
  Convert__regAX__ImmSExti16i81_1,
2251
  Convert__regEAX__ImmSExti32i81_1,
2252
  Convert__regRAX__ImmSExti64i81_1,
2253
  Convert__Reg1_0__Imm1_1,
2254
  Convert__Reg1_0__ImmSExti64i321_1,
2255
  Convert__Reg1_0__Mem85_1,
2256
  Convert__Reg1_3__Tie0_1_1__Reg1_2__Imm1_0,
2257
  Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_0,
2258
  Convert__Reg1_2__Tie0_1_1__Mem1285_3__Imm1_0,
2259
  Convert__Reg1_3__Tie0_1_1__Mem1285_2__Imm1_0,
2260
  Convert__Reg1_2__Tie0_1_1__Mem645_3__Imm1_0,
2261
  Convert__Reg1_3__Tie0_1_1__Mem645_2__Imm1_0,
2262
  Convert__Reg1_2__Tie0_1_1__Mem325_3__Imm1_0,
2263
  Convert__Reg1_3__Tie0_1_1__Mem325_2__Imm1_0,
2264
  Convert__Reg1_1__Imm1_0,
2265
  Convert__Reg1_1__Mem85_0,
2266
  Convert__regEAX__ImmSExti32i81_0,
2267
  Convert__regRAX__ImmSExti64i81_0,
2268
  Convert__Reg1_1__ImmSExti64i321_0,
2269
  Convert__DstIdx161_1__SrcIdx162_0,
2270
  Convert__DstIdx321_1__SrcIdx322_0,
2271
  Convert__DstIdx641_1__SrcIdx642_0,
2272
  Convert__DstIdx81_1__SrcIdx82_0,
2273
  Convert__DstIdx81_0__SrcIdx82_1,
2274
  Convert__Reg1_0__Tie0_1_1__Mem645_1__ImmUnsignedi81_2,
2275
  Convert__Reg1_2__Tie0_1_1__Mem645_1__ImmUnsignedi81_0,
2276
  Convert__DstIdx321_0__SrcIdx322_1,
2277
  Convert__DstIdx641_0__SrcIdx642_1,
2278
  Convert__Reg1_0__Tie0_1_1__Mem325_1__ImmUnsignedi81_2,
2279
  Convert__Reg1_2__Tie0_1_1__Mem325_1__ImmUnsignedi81_0,
2280
  Convert__DstIdx161_0__SrcIdx162_1,
2281
  Convert__regAX__ImmSExti16i81_0,
2282
  Convert__Mem1285_0,
2283
  Convert__Mem85_1,
2284
  Convert__Imm1_0__Imm1_1,
2285
  Convert__GR32orGR641_2__Reg1_1__ImmUnsignedi81_0,
2286
  Convert__Mem325_2__Reg1_1__ImmUnsignedi81_0,
2287
  Convert__GR32orGR641_0__Reg1_1__ImmUnsignedi81_2,
2288
  Convert__Mem325_0__Reg1_1__ImmUnsignedi81_2,
2289
  Convert__Reg1_0__Tie0_1_1__ImmUnsignedi81_1__ImmUnsignedi81_2,
2290
  Convert__Reg1_2__Tie0_3_3__ImmUnsignedi81_1__ImmUnsignedi81_0,
2291
  Convert__regST1,
2292
  Convert__regST0,
2293
  Convert__Mem805_0,
2294
  Convert__Reg1_0__Reg1_0__ImmSExti16i81_1,
2295
  Convert__Reg1_0__Reg1_0__Imm1_1,
2296
  Convert__Reg1_0__Reg1_0__ImmSExti32i81_1,
2297
  Convert__Reg1_0__Reg1_0__ImmSExti64i81_1,
2298
  Convert__Reg1_0__Reg1_0__ImmSExti64i321_1,
2299
  Convert__Reg1_0__Reg1_1__ImmSExti16i81_2,
2300
  Convert__Reg1_0__Mem165_1__ImmSExti16i81_2,
2301
  Convert__Reg1_0__Mem165_1__Imm1_2,
2302
  Convert__Reg1_0__Reg1_1__ImmSExti32i81_2,
2303
  Convert__Reg1_0__Mem325_1__ImmSExti32i81_2,
2304
  Convert__Reg1_0__Reg1_1__ImmSExti64i81_2,
2305
  Convert__Reg1_0__Mem645_1__ImmSExti64i81_2,
2306
  Convert__Reg1_1__Reg1_1__ImmSExti32i81_0,
2307
  Convert__Reg1_1__Reg1_1__Imm1_0,
2308
  Convert__Reg1_2__Reg1_1__ImmSExti32i81_0,
2309
  Convert__Reg1_2__Mem325_1__ImmSExti32i81_0,
2310
  Convert__Reg1_1__Reg1_1__ImmSExti64i81_0,
2311
  Convert__Reg1_1__Reg1_1__ImmSExti64i321_0,
2312
  Convert__Reg1_2__Reg1_1__ImmSExti64i81_0,
2313
  Convert__Reg1_2__Mem645_1__ImmSExti64i81_0,
2314
  Convert__Reg1_1__Reg1_1__ImmSExti16i81_0,
2315
  Convert__Reg1_2__Reg1_1__ImmSExti16i81_0,
2316
  Convert__Reg1_2__Mem165_1__ImmSExti16i81_0,
2317
  Convert__Reg1_2__Mem165_1__Imm1_0,
2318
  Convert__ImmUnsignedi81_1,
2319
  Convert__ImmUnsignedi81_0,
2320
  Convert__DstIdx161_0,
2321
  Convert__DstIdx321_0,
2322
  Convert__DstIdx81_0,
2323
  Convert__DstIdx81_1,
2324
  Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmUnsignedi81_2__ImmUnsignedi81_3,
2325
  Convert__Reg1_3__Tie0_4_4__Reg1_2__ImmUnsignedi81_1__ImmUnsignedi81_0,
2326
  Convert__DstIdx321_1,
2327
  Convert__DstIdx161_1,
2328
  Convert__Mem5_1,
2329
  Convert__SrcIdx162_0,
2330
  Convert__SrcIdx322_0,
2331
  Convert__SrcIdx642_0,
2332
  Convert__SrcIdx82_0,
2333
  Convert__SrcIdx82_1,
2334
  Convert__SrcIdx162_1,
2335
  Convert__SrcIdx322_1,
2336
  Convert__SrcIdx642_1,
2337
  Convert__MemOffs16_82_1,
2338
  Convert__MemOffs32_82_1,
2339
  Convert__MemOffs16_162_1,
2340
  Convert__MemOffs32_162_1,
2341
  Convert__MemOffs16_322_1,
2342
  Convert__MemOffs32_322_1,
2343
  Convert__MemOffs32_642_1,
2344
  Convert__MemOffs16_162_0,
2345
  Convert__MemOffs16_322_0,
2346
  Convert__MemOffs16_82_0,
2347
  Convert__MemOffs32_162_0,
2348
  Convert__MemOffs32_322_0,
2349
  Convert__MemOffs32_642_0,
2350
  Convert__MemOffs32_82_0,
2351
  Convert__MemOffs64_82_1,
2352
  Convert__MemOffs64_162_1,
2353
  Convert__MemOffs64_322_1,
2354
  Convert__MemOffs64_642_1,
2355
  Convert__MemOffs64_162_0,
2356
  Convert__MemOffs64_322_0,
2357
  Convert__MemOffs64_642_0,
2358
  Convert__MemOffs64_82_0,
2359
  Convert__Reg1_0__Mem5125_1,
2360
  Convert__Reg1_1__Mem5125_0,
2361
  Convert__GR32orGR641_1__Reg1_0,
2362
  Convert__GR32orGR641_0__Reg1_1,
2363
  Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_17,
2364
  Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_17,
2365
  Convert__Reg1_0__Tie0_1_1__Mem1285_1__imm_95_17,
2366
  Convert__Reg1_1__Tie0_2_2__Mem1285_0__imm_95_17,
2367
  Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_1,
2368
  Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_1,
2369
  Convert__Reg1_0__Tie0_1_1__Mem1285_1__imm_95_1,
2370
  Convert__Reg1_1__Tie0_2_2__Mem1285_0__imm_95_1,
2371
  Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_16,
2372
  Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_16,
2373
  Convert__Reg1_0__Tie0_1_1__Mem1285_1__imm_95_16,
2374
  Convert__Reg1_1__Tie0_2_2__Mem1285_0__imm_95_16,
2375
  Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_0,
2376
  Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_0,
2377
  Convert__Reg1_0__Tie0_1_1__Mem1285_1__imm_95_0,
2378
  Convert__Reg1_1__Tie0_2_2__Mem1285_0__imm_95_0,
2379
  Convert__Mem85_2__Reg1_1__ImmUnsignedi81_0,
2380
  Convert__Mem85_0__Reg1_1__ImmUnsignedi81_2,
2381
  Convert__Mem645_2__Reg1_1__ImmUnsignedi81_0,
2382
  Convert__Mem645_0__Reg1_1__ImmUnsignedi81_2,
2383
  Convert__Mem165_2__Reg1_1__ImmUnsignedi81_0,
2384
  Convert__Mem165_0__Reg1_1__ImmUnsignedi81_2,
2385
  Convert__Reg1_0__Tie0_1_1__GR32orGR641_1__ImmUnsignedi81_2,
2386
  Convert__Reg1_0__Tie0_1_1__Mem85_1__ImmUnsignedi81_2,
2387
  Convert__Reg1_2__Tie0_1_1__GR32orGR641_1__ImmUnsignedi81_0,
2388
  Convert__Reg1_2__Tie0_1_1__Mem85_1__ImmUnsignedi81_0,
2389
  Convert__Reg1_0__Tie0_1_1__Mem165_1__ImmUnsignedi81_2,
2390
  Convert__Reg1_2__Tie0_1_1__Mem165_1__ImmUnsignedi81_0,
2391
  Convert__Reg1_0__Mem645_1__ImmUnsignedi81_2,
2392
  Convert__Reg1_2__Mem645_1__ImmUnsignedi81_0,
2393
  Convert__Reg1_0__Tie0_1_1__ImmUnsignedi81_1,
2394
  Convert__Reg1_1__Tie0_1_1__ImmUnsignedi81_0,
2395
  Convert__ImmSExti64i81_0,
2396
  Convert__ImmSExti16i81_0,
2397
  Convert__ImmSExti32i81_0,
2398
  Convert__Mem165_0__ImmUnsignedi81_1,
2399
  Convert__Mem325_0__ImmUnsignedi81_1,
2400
  Convert__Mem645_0__ImmUnsignedi81_1,
2401
  Convert__Mem85_0__ImmUnsignedi81_1,
2402
  Convert__Reg1_1__Tie0_1_1,
2403
  Convert__Mem85_1__ImmUnsignedi81_0,
2404
  Convert__Mem325_1__ImmUnsignedi81_0,
2405
  Convert__Mem645_1__ImmUnsignedi81_0,
2406
  Convert__Mem165_1__ImmUnsignedi81_0,
2407
  Convert__Reg1_0__Mem325_1__ImmUnsignedi81_2,
2408
  Convert__Reg1_2__Mem325_1__ImmUnsignedi81_0,
2409
  Convert__DstIdx641_0,
2410
  Convert__DstIdx641_1,
2411
  Convert__Mem325_2__Reg1_1,
2412
  Convert__Mem645_2__Reg1_1,
2413
  Convert__Mem165_2__Reg1_1,
2414
  Convert__GR32orGR641_0,
2415
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem1285_2,
2416
  Convert__Reg1_2__Tie0_1_1__Reg1_1__Mem1285_0,
2417
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem1285_5,
2418
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__Mem1285_0,
2419
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem1285_6,
2420
  Convert__Reg1_0__Reg1_1__Mem1285_2,
2421
  Convert__Reg1_0__Reg1_1__Mem2565_2,
2422
  Convert__Reg1_0__Reg1_1__Mem5125_2,
2423
  Convert__Reg1_2__Reg1_1__Mem1285_0,
2424
  Convert__Reg1_2__Reg1_1__Mem2565_0,
2425
  Convert__Reg1_2__Reg1_1__Mem5125_0,
2426
  Convert__Reg1_0__Reg1_1__Reg1_2__AVX512RC1_3,
2427
  Convert__Reg1_3__Reg1_2__Reg1_1__AVX512RC1_0,
2428
  Convert__Reg1_3__Reg1_2__Mem645_0,
2429
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5,
2430
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__Reg1_0,
2431
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem2565_5,
2432
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem5125_5,
2433
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__Mem2565_0,
2434
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__Mem5125_0,
2435
  Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6,
2436
  Convert__Reg1_0__Reg1_2__Reg1_5__Mem1285_6,
2437
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem645_5,
2438
  Convert__Reg1_2__Reg1_4__Reg1_1__Reg1_0,
2439
  Convert__Reg1_0__Reg1_2__Reg1_5__Mem2565_6,
2440
  Convert__Reg1_0__Reg1_2__Reg1_5__Mem5125_6,
2441
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5__AVX512RC1_6,
2442
  Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Reg1_1__AVX512RC1_0,
2443
  Convert__Reg1_2__Reg1_4__Reg1_1__Mem1285_0,
2444
  Convert__Reg1_2__Reg1_4__Reg1_1__Mem2565_0,
2445
  Convert__Reg1_2__Reg1_4__Reg1_1__Mem5125_0,
2446
  Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem645_0,
2447
  Convert__Reg1_0__Reg1_2__Reg1_5__Mem645_6,
2448
  Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6__AVX512RC1_7,
2449
  Convert__Reg1_3__Reg1_5__Reg1_2__Reg1_1__AVX512RC1_0,
2450
  Convert__Reg1_3__Reg1_5__Reg1_2__Mem645_0,
2451
  Convert__Reg1_3__Reg1_2__Mem325_0,
2452
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem325_5,
2453
  Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem325_0,
2454
  Convert__Reg1_0__Reg1_2__Reg1_5__Mem325_6,
2455
  Convert__Reg1_3__Reg1_5__Reg1_2__Mem325_0,
2456
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__Mem645_0,
2457
  Convert__Reg1_2__Reg1_4__Reg1_1__Mem645_0,
2458
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__Mem325_0,
2459
  Convert__Reg1_2__Reg1_4__Reg1_1__Mem325_0,
2460
  Convert__Reg1_0__Reg1_1__Reg1_2__ImmUnsignedi81_3,
2461
  Convert__Reg1_0__Reg1_1__Mem1285_2__ImmUnsignedi81_3,
2462
  Convert__Reg1_0__Reg1_1__Mem2565_2__ImmUnsignedi81_3,
2463
  Convert__Reg1_0__Reg1_1__Mem5125_2__ImmUnsignedi81_3,
2464
  Convert__Reg1_3__Reg1_2__Reg1_1__ImmUnsignedi81_0,
2465
  Convert__Reg1_3__Reg1_2__Mem1285_1__ImmUnsignedi81_0,
2466
  Convert__Reg1_3__Reg1_2__Mem2565_1__ImmUnsignedi81_0,
2467
  Convert__Reg1_3__Reg1_2__Mem5125_1__ImmUnsignedi81_0,
2468
  Convert__Reg1_0__Reg1_1__Mem325_2__ImmUnsignedi81_4,
2469
  Convert__Reg1_4__Reg1_3__Mem325_1__ImmUnsignedi81_0,
2470
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5__ImmUnsignedi81_6,
2471
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem1285_5__ImmUnsignedi81_6,
2472
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem2565_5__ImmUnsignedi81_6,
2473
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem5125_5__ImmUnsignedi81_6,
2474
  Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Reg1_1__ImmUnsignedi81_0,
2475
  Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem1285_1__ImmUnsignedi81_0,
2476
  Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem2565_1__ImmUnsignedi81_0,
2477
  Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem5125_1__ImmUnsignedi81_0,
2478
  Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6__ImmUnsignedi81_7,
2479
  Convert__Reg1_0__Reg1_2__Reg1_5__Mem1285_6__ImmUnsignedi81_7,
2480
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem325_5__ImmUnsignedi81_7,
2481
  Convert__Reg1_0__Reg1_2__Reg1_5__Mem2565_6__ImmUnsignedi81_7,
2482
  Convert__Reg1_0__Reg1_2__Reg1_5__Mem5125_6__ImmUnsignedi81_7,
2483
  Convert__Reg1_3__Reg1_5__Reg1_2__Reg1_1__ImmUnsignedi81_0,
2484
  Convert__Reg1_3__Reg1_5__Reg1_2__Mem1285_1__ImmUnsignedi81_0,
2485
  Convert__Reg1_3__Reg1_5__Reg1_2__Mem2565_1__ImmUnsignedi81_0,
2486
  Convert__Reg1_4__Tie0_1_1__Reg1_6__Reg1_3__Mem325_1__ImmUnsignedi81_0,
2487
  Convert__Reg1_3__Reg1_5__Reg1_2__Mem5125_1__ImmUnsignedi81_0,
2488
  Convert__Reg1_0__Reg1_2__Reg1_5__Mem325_6__ImmUnsignedi81_8,
2489
  Convert__Reg1_4__Reg1_6__Reg1_3__Mem325_1__ImmUnsignedi81_0,
2490
  Convert__Reg1_0__Reg1_1__Mem645_2__ImmUnsignedi81_4,
2491
  Convert__Reg1_4__Reg1_3__Mem645_1__ImmUnsignedi81_0,
2492
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem645_5__ImmUnsignedi81_7,
2493
  Convert__Reg1_4__Tie0_1_1__Reg1_6__Reg1_3__Mem645_1__ImmUnsignedi81_0,
2494
  Convert__Reg1_0__Reg1_2__Reg1_5__Mem645_6__ImmUnsignedi81_8,
2495
  Convert__Reg1_4__Reg1_6__Reg1_3__Mem645_1__ImmUnsignedi81_0,
2496
  Convert__Reg1_0__Reg1_2__Reg1_4__Reg1_5,
2497
  Convert__Reg1_0__Reg1_2__Reg1_4__Mem1285_5,
2498
  Convert__Reg1_0__Reg1_2__Reg1_4__Mem2565_5,
2499
  Convert__Reg1_0__Reg1_2__Reg1_4__Mem5125_5,
2500
  Convert__Reg1_0__Reg1_2__Reg1_4__Mem645_5,
2501
  Convert__Reg1_0__Reg1_2__Reg1_4__Mem325_5,
2502
  Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0,
2503
  Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3,
2504
  Convert__Reg1_0__Reg1_1__Mem1285_2__Reg1_3,
2505
  Convert__Reg1_3__Reg1_2__Mem1285_1__Reg1_0,
2506
  Convert__Reg1_0__Reg1_1__Mem2565_2__Reg1_3,
2507
  Convert__Reg1_3__Reg1_2__Mem2565_1__Reg1_0,
2508
  Convert__Reg1_1__Tie0_1_1__Reg1_3__Reg1_0,
2509
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4,
2510
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem645_4,
2511
  Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem645_0,
2512
  Convert__Reg1_1__Reg1_3__Reg1_0,
2513
  Convert__Reg1_0__Reg1_2__Reg1_5,
2514
  Convert__Reg1_0__Reg1_2__Mem645_5,
2515
  Convert__Reg1_1__Reg1_3__Mem645_0,
2516
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem1285_4,
2517
  Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem1285_0,
2518
  Convert__Reg1_0__Reg1_2__Mem1285_5,
2519
  Convert__Reg1_1__Reg1_3__Mem1285_0,
2520
  Convert__Reg1_0__Mem2565_1,
2521
  Convert__Reg1_1__Mem2565_0,
2522
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem2565_4,
2523
  Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem2565_0,
2524
  Convert__Reg1_0__Reg1_2__Mem2565_5,
2525
  Convert__Reg1_1__Reg1_3__Mem2565_0,
2526
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem325_4,
2527
  Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem325_0,
2528
  Convert__Reg1_0__Reg1_2__Mem325_5,
2529
  Convert__Reg1_1__Reg1_3__Mem325_0,
2530
  Convert__Reg1_2__Reg1_3__Reg1_4__Imm1_0,
2531
  Convert__Reg1_2__Reg1_3__Mem1285_4__Imm1_0,
2532
  Convert__Reg1_2__Reg1_3__Mem2565_4__Imm1_0,
2533
  Convert__Reg1_2__Reg1_3__Mem5125_4__Imm1_0,
2534
  Convert__Reg1_4__Reg1_3__Reg1_2__Imm1_0,
2535
  Convert__Reg1_4__Reg1_3__Mem1285_2__Imm1_0,
2536
  Convert__Reg1_4__Reg1_3__Mem2565_2__Imm1_0,
2537
  Convert__Reg1_4__Reg1_3__Mem5125_2__Imm1_0,
2538
  Convert__Reg1_2__Reg1_3__Mem645_4__Imm1_0,
2539
  Convert__Reg1_4__Reg1_3__Mem645_2__Imm1_0,
2540
  Convert__Reg1_2__Reg1_3__Mem325_4__Imm1_0,
2541
  Convert__Reg1_4__Reg1_3__Mem325_2__Imm1_0,
2542
  Convert__Reg1_5__Reg1_4__Reg1_3__Imm1_0,
2543
  Convert__Reg1_5__Reg1_4__Mem645_2__Imm1_0,
2544
  Convert__Reg1_5__Reg1_4__Mem325_2__Imm1_0,
2545
  Convert__Reg1_2__Reg1_4__Reg1_6__Reg1_7__Imm1_0,
2546
  Convert__Reg1_2__Reg1_4__Reg1_6__Mem1285_7__Imm1_0,
2547
  Convert__Reg1_2__Reg1_4__Reg1_6__Mem2565_7__Imm1_0,
2548
  Convert__Reg1_2__Reg1_4__Reg1_6__Mem5125_7__Imm1_0,
2549
  Convert__Reg1_4__Reg1_6__Reg1_3__Reg1_2__Imm1_0,
2550
  Convert__Reg1_4__Reg1_6__Reg1_3__Mem1285_2__Imm1_0,
2551
  Convert__Reg1_4__Reg1_6__Reg1_3__Mem2565_2__Imm1_0,
2552
  Convert__Reg1_4__Reg1_6__Reg1_3__Mem5125_2__Imm1_0,
2553
  Convert__Reg1_2__Reg1_4__Reg1_6__Mem645_7__Imm1_0,
2554
  Convert__Reg1_4__Reg1_6__Reg1_3__Mem645_2__Imm1_0,
2555
  Convert__Reg1_2__Reg1_4__Reg1_6__Mem325_7__Imm1_0,
2556
  Convert__Reg1_4__Reg1_6__Reg1_3__Mem325_2__Imm1_0,
2557
  Convert__Reg1_5__Reg1_7__Reg1_4__Reg1_3__Imm1_0,
2558
  Convert__Reg1_5__Reg1_7__Reg1_4__Mem645_2__Imm1_0,
2559
  Convert__Reg1_5__Reg1_7__Reg1_4__Mem325_2__Imm1_0,
2560
  Convert__Reg1_0__Reg1_1__Reg1_2__ImmUnsignedi81_4,
2561
  Convert__Reg1_4__Reg1_3__Reg1_2__ImmUnsignedi81_0,
2562
  Convert__Reg1_0__Reg1_2__Reg1_4__Reg1_5__ImmUnsignedi81_6,
2563
  Convert__Reg1_0__Reg1_2__Reg1_4__Mem1285_5__ImmUnsignedi81_6,
2564
  Convert__Reg1_0__Reg1_2__Reg1_4__Mem2565_5__ImmUnsignedi81_6,
2565
  Convert__Reg1_0__Reg1_2__Reg1_4__Mem5125_5__ImmUnsignedi81_6,
2566
  Convert__Reg1_0__Reg1_2__Reg1_4__Mem645_5__ImmUnsignedi81_7,
2567
  Convert__Reg1_0__Reg1_2__Reg1_4__Reg1_5__ImmUnsignedi81_7,
2568
  Convert__Reg1_4__Reg1_6__Reg1_3__Reg1_2__ImmUnsignedi81_0,
2569
  Convert__Reg1_0__Reg1_2__Reg1_4__Mem325_5__ImmUnsignedi81_7,
2570
  Convert__Reg1_0__Reg1_1__Mem645_2__ImmUnsignedi81_3,
2571
  Convert__Reg1_3__Reg1_2__Mem645_1__ImmUnsignedi81_0,
2572
  Convert__Reg1_0__Reg1_2__Reg1_4__Mem645_5__ImmUnsignedi81_6,
2573
  Convert__Reg1_3__Reg1_5__Reg1_2__Mem645_1__ImmUnsignedi81_0,
2574
  Convert__Reg1_0__Reg1_1__Mem325_2__ImmUnsignedi81_3,
2575
  Convert__Reg1_3__Reg1_2__Mem325_1__ImmUnsignedi81_0,
2576
  Convert__Reg1_0__Reg1_2__Reg1_4__Mem325_5__ImmUnsignedi81_6,
2577
  Convert__Reg1_3__Reg1_5__Reg1_2__Mem325_1__ImmUnsignedi81_0,
2578
  Convert__Reg1_2__Reg1_1,
2579
  Convert__Mem2565_1__Reg1_0,
2580
  Convert__Mem5125_1__Reg1_0,
2581
  Convert__Mem2565_0__Reg1_1,
2582
  Convert__Mem5125_0__Reg1_1,
2583
  Convert__Mem1285_1__Reg1_3__Reg1_0,
2584
  Convert__Mem2565_1__Reg1_3__Reg1_0,
2585
  Convert__Mem5125_1__Reg1_3__Reg1_0,
2586
  Convert__Mem1285_0__Reg1_2__Reg1_4,
2587
  Convert__Mem2565_0__Reg1_2__Reg1_4,
2588
  Convert__Mem5125_0__Reg1_2__Reg1_4,
2589
  Convert__Reg1_2__Mem325_0,
2590
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Mem325_0,
2591
  Convert__Reg1_2__Reg1_4__Mem325_0,
2592
  Convert__Reg1_0__Reg1_1__AVX512RC1_2,
2593
  Convert__Reg1_2__Reg1_1__AVX512RC1_0,
2594
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem5125_4,
2595
  Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem5125_0,
2596
  Convert__Reg1_0__Reg1_2__Mem5125_5,
2597
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__AVX512RC1_5,
2598
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__AVX512RC1_0,
2599
  Convert__Reg1_1__Reg1_3__Mem5125_0,
2600
  Convert__Reg1_0__Reg1_2__Reg1_5__AVX512RC1_6,
2601
  Convert__Reg1_2__Reg1_4__Reg1_1__AVX512RC1_0,
2602
  Convert__Reg1_2__Mem645_0,
2603
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Mem645_0,
2604
  Convert__Reg1_2__Reg1_4__Mem645_0,
2605
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1,
2606
  Convert__Reg1_2__Reg1_4__Reg1_1,
2607
  Convert__Mem1285_2__Reg1_1__ImmUnsignedi81_0,
2608
  Convert__Mem2565_2__Reg1_1__ImmUnsignedi81_0,
2609
  Convert__Mem1285_0__Reg1_1__ImmUnsignedi81_2,
2610
  Convert__Mem2565_0__Reg1_1__ImmUnsignedi81_2,
2611
  Convert__Reg1_0__Reg1_1__ImmUnsignedi81_3,
2612
  Convert__Reg1_3__Reg1_2__ImmUnsignedi81_0,
2613
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__ImmUnsignedi81_5,
2614
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__ImmUnsignedi81_0,
2615
  Convert__Mem645_2__Reg1_4__Reg1_1__ImmUnsignedi81_0,
2616
  Convert__Mem1285_2__Reg1_4__Reg1_1__ImmUnsignedi81_0,
2617
  Convert__Mem2565_2__Reg1_4__Reg1_1__ImmUnsignedi81_0,
2618
  Convert__Mem1285_0__Reg1_2__Reg1_4__ImmUnsignedi81_5,
2619
  Convert__Mem2565_0__Reg1_2__Reg1_4__ImmUnsignedi81_5,
2620
  Convert__Mem645_0__Reg1_2__Reg1_4__ImmUnsignedi81_5,
2621
  Convert__Reg1_0__Reg1_2__Reg1_5__ImmUnsignedi81_6,
2622
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__ImmUnsignedi81_6,
2623
  Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__ImmUnsignedi81_0,
2624
  Convert__Reg1_2__Reg1_4__Reg1_1__ImmUnsignedi81_0,
2625
  Convert__Reg1_0__Reg1_2__Reg1_5__ImmUnsignedi81_7,
2626
  Convert__Reg1_3__Reg1_5__Reg1_2__ImmUnsignedi81_0,
2627
  Convert__Reg1_0__Reg1_1__Reg1_3__AVX512RC1_2,
2628
  Convert__Reg1_3__Reg1_2__Reg1_0__AVX512RC1_1,
2629
  Convert__Reg1_3__Reg1_2__Reg1_1,
2630
  Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Reg1_1,
2631
  Convert__Reg1_3__Reg1_5__Reg1_2__Reg1_1,
2632
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmUnsignedi81_3,
2633
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem1285_2__ImmUnsignedi81_3,
2634
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem2565_2__ImmUnsignedi81_3,
2635
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem5125_2__ImmUnsignedi81_3,
2636
  Convert__Reg1_3__Tie0_1_1__Reg1_2__Reg1_1__ImmUnsignedi81_0,
2637
  Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem1285_1__ImmUnsignedi81_0,
2638
  Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem2565_1__ImmUnsignedi81_0,
2639
  Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem5125_1__ImmUnsignedi81_0,
2640
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem645_2__ImmUnsignedi81_4,
2641
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmUnsignedi81_4,
2642
  Convert__Reg1_4__Tie0_1_1__Reg1_3__Reg1_2__ImmUnsignedi81_0,
2643
  Convert__Reg1_4__Tie0_1_1__Reg1_3__Mem645_1__ImmUnsignedi81_0,
2644
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Reg1_6__ImmUnsignedi81_7,
2645
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem1285_6__ImmUnsignedi81_7,
2646
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem2565_6__ImmUnsignedi81_7,
2647
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem5125_6__ImmUnsignedi81_7,
2648
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5__ImmUnsignedi81_7,
2649
  Convert__Reg1_4__Tie0_1_1__Reg1_6__Reg1_3__Reg1_2__ImmUnsignedi81_0,
2650
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem645_6__ImmUnsignedi81_8,
2651
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Reg1_6__ImmUnsignedi81_8,
2652
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem325_2__ImmUnsignedi81_4,
2653
  Convert__Reg1_4__Tie0_1_1__Reg1_3__Mem325_1__ImmUnsignedi81_0,
2654
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem325_6__ImmUnsignedi81_8,
2655
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem645_2__ImmUnsignedi81_3,
2656
  Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem645_1__ImmUnsignedi81_0,
2657
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem645_5__ImmUnsignedi81_6,
2658
  Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem645_1__ImmUnsignedi81_0,
2659
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem645_6__ImmUnsignedi81_7,
2660
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem325_2__ImmUnsignedi81_3,
2661
  Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem325_1__ImmUnsignedi81_0,
2662
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem325_5__ImmUnsignedi81_6,
2663
  Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem325_1__ImmUnsignedi81_0,
2664
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem325_6__ImmUnsignedi81_7,
2665
  Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0,
2666
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2,
2667
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem2565_2,
2668
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem5125_2,
2669
  Convert__Reg1_2__Tie0_1_1__Reg1_1__Mem2565_0,
2670
  Convert__Reg1_2__Tie0_1_1__Reg1_1__Mem5125_0,
2671
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem645_2,
2672
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__AVX512RC1_3,
2673
  Convert__Reg1_3__Tie0_1_1__Reg1_2__Reg1_1__AVX512RC1_0,
2674
  Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem645_0,
2675
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Reg1_6,
2676
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem2565_6,
2677
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem5125_6,
2678
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem645_6,
2679
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Reg1_6__AVX512RC1_7,
2680
  Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem325_2,
2681
  Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem325_0,
2682
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem325_6,
2683
  Convert__Reg1_2__Tie0_1_1__Reg1_1__Mem645_0,
2684
  Convert__Reg1_2__Tie0_1_1__Reg1_1__Mem325_0,
2685
  Convert__Reg1_0__Reg1_1__Reg1_2__Mem1285_3,
2686
  Convert__Reg1_0__Reg1_1__Reg1_2__Mem2565_3,
2687
  Convert__Reg1_3__Reg1_2__Reg1_1__Mem1285_0,
2688
  Convert__Reg1_3__Reg1_2__Reg1_1__Mem2565_0,
2689
  Convert__Reg1_0__Reg1_1__Reg1_2__Mem645_3,
2690
  Convert__Reg1_0__Reg1_1__Mem645_2__Reg1_3,
2691
  Convert__Reg1_3__Reg1_2__Mem645_1__Reg1_0,
2692
  Convert__Reg1_3__Reg1_2__Reg1_1__Mem645_0,
2693
  Convert__Reg1_0__Reg1_1__Reg1_2__Mem325_3,
2694
  Convert__Reg1_0__Reg1_1__Mem325_2__Reg1_3,
2695
  Convert__Reg1_3__Reg1_2__Mem325_1__Reg1_0,
2696
  Convert__Reg1_3__Reg1_2__Reg1_1__Mem325_0,
2697
  Convert__Reg1_0__Mem2565_1__ImmUnsignedi81_2,
2698
  Convert__Reg1_0__Mem5125_1__ImmUnsignedi81_2,
2699
  Convert__Reg1_0__Mem645_1__ImmUnsignedi81_3,
2700
  Convert__Reg1_0__Reg1_2__Reg1_4__ImmUnsignedi81_5,
2701
  Convert__Reg1_0__Reg1_2__Mem1285_4__ImmUnsignedi81_5,
2702
  Convert__Reg1_0__Reg1_2__Mem2565_4__ImmUnsignedi81_5,
2703
  Convert__Reg1_0__Reg1_2__Mem5125_4__ImmUnsignedi81_5,
2704
  Convert__Reg1_0__Reg1_2__Mem645_4__ImmUnsignedi81_6,
2705
  Convert__Reg1_3__Mem645_1__ImmUnsignedi81_0,
2706
  Convert__Reg1_3__Reg1_5__Mem645_1__ImmUnsignedi81_0,
2707
  Convert__Reg1_2__Reg1_4__Mem1285_1__ImmUnsignedi81_0,
2708
  Convert__Reg1_2__Mem2565_1__ImmUnsignedi81_0,
2709
  Convert__Reg1_2__Reg1_4__Mem2565_1__ImmUnsignedi81_0,
2710
  Convert__Reg1_2__Mem5125_1__ImmUnsignedi81_0,
2711
  Convert__Reg1_2__Reg1_4__Mem5125_1__ImmUnsignedi81_0,
2712
  Convert__Reg1_0__Mem325_1__ImmUnsignedi81_3,
2713
  Convert__Reg1_0__Reg1_2__Mem325_4__ImmUnsignedi81_6,
2714
  Convert__Reg1_3__Mem325_1__ImmUnsignedi81_0,
2715
  Convert__Reg1_3__Reg1_5__Mem325_1__ImmUnsignedi81_0,
2716
  Convert__Reg1_0__Reg1_2__Mem645_4__ImmUnsignedi81_5,
2717
  Convert__Reg1_2__Reg1_4__Mem645_1__ImmUnsignedi81_0,
2718
  Convert__Reg1_0__Reg1_2__Mem325_4__ImmUnsignedi81_5,
2719
  Convert__Reg1_2__Reg1_4__Mem325_1__ImmUnsignedi81_0,
2720
  Convert__Reg1_2__Reg1_0__Tie0_1_1__Mem128_RC1285_1__Tie1_1_1,
2721
  Convert__Reg1_0__Reg1_2__Tie0_1_1__Mem128_RC1285_1__Tie1_3_3,
2722
  Convert__Reg1_2__Reg1_0__Tie0_1_1__Mem256_RC1285_1__Tie1_1_1,
2723
  Convert__Reg1_0__Reg1_2__Tie0_1_1__Mem256_RC1285_1__Tie1_3_3,
2724
  Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem128_RC128X5_4,
2725
  Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem256_RC128X5_4,
2726
  Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem512_RC256X5_4,
2727
  Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem128_RC128X5_0,
2728
  Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem256_RC128X5_0,
2729
  Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem512_RC256X5_0,
2730
  Convert__Reg1_2__Reg1_0__Tie0_1_1__Mem256_RC2565_1__Tie1_1_1,
2731
  Convert__Reg1_0__Reg1_2__Tie0_1_1__Mem256_RC2565_1__Tie1_3_3,
2732
  Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem256_RC256X5_4,
2733
  Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem512_RC5125_4,
2734
  Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem256_RC256X5_0,
2735
  Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem512_RC5125_0,
2736
  Convert__Reg1_1__Mem512_RC256X5_3,
2737
  Convert__Reg1_2__Mem512_RC256X5_0,
2738
  Convert__Reg1_1__Mem512_RC5125_3,
2739
  Convert__Reg1_2__Mem512_RC5125_0,
2740
  Convert__Reg1_1__Mem256_RC5125_3,
2741
  Convert__Reg1_2__Mem256_RC5125_0,
2742
  Convert__Reg1_2__Reg1_0__Tie0_1_1__Mem128_RC2565_1__Tie1_1_1,
2743
  Convert__Reg1_0__Reg1_2__Tie0_1_1__Mem128_RC2565_1__Tie1_3_3,
2744
  Convert__Reg1_2__Reg1_0__Tie0_1_1__Mem64_RC1285_1__Tie1_1_1,
2745
  Convert__Reg1_0__Reg1_2__Tie0_1_1__Mem64_RC1285_1__Tie1_3_3,
2746
  Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem128_RC256X5_4,
2747
  Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem64_RC128X5_4,
2748
  Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem256_RC5125_4,
2749
  Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem128_RC256X5_0,
2750
  Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem256_RC5125_0,
2751
  Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem64_RC128X5_0,
2752
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem1285_4__ImmUnsignedi81_5,
2753
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem2565_4__ImmUnsignedi81_5,
2754
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem5125_4__ImmUnsignedi81_5,
2755
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Mem1285_1__ImmUnsignedi81_0,
2756
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Mem2565_1__ImmUnsignedi81_0,
2757
  Convert__Reg1_2__Tie0_1_1__Reg1_4__Mem5125_1__ImmUnsignedi81_0,
2758
  Convert__Reg1_0__Reg1_2__Mem1285_5__ImmUnsignedi81_6,
2759
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem645_4__ImmUnsignedi81_6,
2760
  Convert__Reg1_0__Reg1_2__Mem2565_5__ImmUnsignedi81_6,
2761
  Convert__Reg1_0__Reg1_2__Mem5125_5__ImmUnsignedi81_6,
2762
  Convert__Reg1_3__Tie0_1_1__Reg1_5__Mem645_1__ImmUnsignedi81_0,
2763
  Convert__Reg1_0__Reg1_2__Mem645_5__ImmUnsignedi81_7,
2764
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem325_4__ImmUnsignedi81_6,
2765
  Convert__Reg1_3__Tie0_1_1__Reg1_5__Mem325_1__ImmUnsignedi81_0,
2766
  Convert__Reg1_0__Reg1_2__Mem325_5__ImmUnsignedi81_7,
2767
  Convert__Reg1_0__Reg1_2__Reg1_5__Mem645_6__ImmUnsignedi81_7,
2768
  Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6__ImmUnsignedi81_8,
2769
  Convert__Reg1_0__Reg1_2__Reg1_5__Mem325_6__ImmUnsignedi81_7,
2770
  Convert__Reg1_0__Reg1_1__Mem85_2__ImmUnsignedi81_4,
2771
  Convert__Reg1_4__Reg1_3__Mem85_1__ImmUnsignedi81_0,
2772
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem85_5__ImmUnsignedi81_7,
2773
  Convert__Reg1_4__Tie0_1_1__Reg1_6__Reg1_3__Mem85_1__ImmUnsignedi81_0,
2774
  Convert__Reg1_0__Reg1_2__Reg1_5__Mem85_6__ImmUnsignedi81_8,
2775
  Convert__Reg1_4__Reg1_6__Reg1_3__Mem85_1__ImmUnsignedi81_0,
2776
  Convert__Mem1285_2__Reg1_1__Reg1_0,
2777
  Convert__Mem2565_2__Reg1_1__Reg1_0,
2778
  Convert__Mem1285_0__Reg1_1__Reg1_2,
2779
  Convert__Mem2565_0__Reg1_1__Reg1_2,
2780
  Convert__Reg1_0__Reg1_2__Reg1_4,
2781
  Convert__Mem645_1__Reg1_3__Reg1_0,
2782
  Convert__Mem645_0__Reg1_2__Reg1_4,
2783
  Convert__Reg1_2__Tie0_3_3__Reg1_4__Reg1_1__Reg1_0,
2784
  Convert__Mem325_1__Reg1_3__Reg1_0,
2785
  Convert__Mem325_0__Reg1_2__Reg1_4,
2786
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem85_4,
2787
  Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem85_0,
2788
  Convert__Reg1_0__Reg1_2__Mem85_5,
2789
  Convert__Reg1_1__Reg1_3__Mem85_0,
2790
  Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem165_4,
2791
  Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem165_0,
2792
  Convert__Reg1_0__Reg1_2__Mem165_5,
2793
  Convert__Reg1_1__Reg1_3__Mem165_0,
2794
  Convert__Reg1_2__Reg1_1__Reg1_0__imm_95_17,
2795
  Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_17,
2796
  Convert__Reg1_0__Reg1_1__Mem1285_2__imm_95_17,
2797
  Convert__Reg1_0__Reg1_1__Mem2565_2__imm_95_17,
2798
  Convert__Reg1_0__Reg1_1__Mem5125_2__imm_95_17,
2799
  Convert__Reg1_2__Reg1_1__Mem1285_0__imm_95_17,
2800
  Convert__Reg1_2__Reg1_1__Mem2565_0__imm_95_17,
2801
  Convert__Reg1_2__Reg1_1__Mem5125_0__imm_95_17,
2802
  Convert__Reg1_2__Reg1_1__Reg1_0__imm_95_1,
2803
  Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_1,
2804
  Convert__Reg1_0__Reg1_1__Mem1285_2__imm_95_1,
2805
  Convert__Reg1_0__Reg1_1__Mem2565_2__imm_95_1,
2806
  Convert__Reg1_0__Reg1_1__Mem5125_2__imm_95_1,
2807
  Convert__Reg1_2__Reg1_1__Mem1285_0__imm_95_1,
2808
  Convert__Reg1_2__Reg1_1__Mem2565_0__imm_95_1,
2809
  Convert__Reg1_2__Reg1_1__Mem5125_0__imm_95_1,
2810
  Convert__Reg1_2__Reg1_1__Reg1_0__imm_95_16,
2811
  Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16,
2812
  Convert__Reg1_0__Reg1_1__Mem1285_2__imm_95_16,
2813
  Convert__Reg1_0__Reg1_1__Mem2565_2__imm_95_16,
2814
  Convert__Reg1_0__Reg1_1__Mem5125_2__imm_95_16,
2815
  Convert__Reg1_2__Reg1_1__Mem1285_0__imm_95_16,
2816
  Convert__Reg1_2__Reg1_1__Mem2565_0__imm_95_16,
2817
  Convert__Reg1_2__Reg1_1__Mem5125_0__imm_95_16,
2818
  Convert__Reg1_2__Reg1_1__Reg1_0__imm_95_0,
2819
  Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0,
2820
  Convert__Reg1_0__Reg1_1__Mem1285_2__imm_95_0,
2821
  Convert__Reg1_0__Reg1_1__Mem2565_2__imm_95_0,
2822
  Convert__Reg1_0__Reg1_1__Mem5125_2__imm_95_0,
2823
  Convert__Reg1_2__Reg1_1__Mem1285_0__imm_95_0,
2824
  Convert__Reg1_2__Reg1_1__Mem2565_0__imm_95_0,
2825
  Convert__Reg1_2__Reg1_1__Mem5125_0__imm_95_0,
2826
  Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmUnsignedi81_4,
2827
  Convert__Reg1_0__Reg1_1__Reg1_2__Mem1285_3__ImmUnsignedi81_4,
2828
  Convert__Reg1_0__Reg1_1__Mem1285_2__Reg1_3__ImmUnsignedi81_4,
2829
  Convert__Reg1_0__Reg1_1__Reg1_2__Mem2565_3__ImmUnsignedi81_4,
2830
  Convert__Reg1_0__Reg1_1__Mem2565_2__Reg1_3__ImmUnsignedi81_4,
2831
  Convert__Reg1_4__Reg1_3__Reg1_2__Reg1_1__ImmUnsignedi81_0,
2832
  Convert__Reg1_4__Reg1_3__Mem1285_2__Reg1_1__ImmUnsignedi81_0,
2833
  Convert__Reg1_4__Reg1_3__Mem2565_2__Reg1_1__ImmUnsignedi81_0,
2834
  Convert__Reg1_4__Reg1_3__Reg1_2__Mem1285_1__ImmUnsignedi81_0,
2835
  Convert__Reg1_4__Reg1_3__Reg1_2__Mem2565_1__ImmUnsignedi81_0,
2836
  Convert__Reg1_0__Reg1_1__GR32orGR641_2__ImmUnsignedi81_3,
2837
  Convert__Reg1_0__Reg1_1__Mem85_2__ImmUnsignedi81_3,
2838
  Convert__Reg1_3__Reg1_2__GR32orGR641_1__ImmUnsignedi81_0,
2839
  Convert__Reg1_3__Reg1_2__Mem85_1__ImmUnsignedi81_0,
2840
  Convert__Reg1_0__Reg1_1__Mem165_2__ImmUnsignedi81_3,
2841
  Convert__Reg1_3__Reg1_2__Mem165_1__ImmUnsignedi81_0,
2842
  Convert__Mem165_1__Reg1_3__Reg1_0,
2843
  Convert__Mem165_0__Reg1_2__Reg1_4,
2844
  Convert__Reg1_2__Mem1285_1__Reg1_0,
2845
  Convert__Reg1_0__Mem1285_1__Reg1_2,
2846
  Convert__Reg1_3__Mem128_RC128X5_1__Tie0_4_4__Reg1_0,
2847
  Convert__Reg1_3__Mem256_RC256X5_1__Tie0_4_4__Reg1_0,
2848
  Convert__Reg1_3__Mem512_RC5125_1__Tie0_4_4__Reg1_0,
2849
  Convert__Reg1_2__Mem128_RC128X5_0__Tie0_3_3__Reg1_4,
2850
  Convert__Reg1_2__Mem256_RC256X5_0__Tie0_3_3__Reg1_4,
2851
  Convert__Reg1_2__Mem512_RC5125_0__Tie0_3_3__Reg1_4,
2852
  Convert__Reg1_3__Mem256_RC128X5_1__Tie0_4_4__Reg1_0,
2853
  Convert__Reg1_3__Mem512_RC256X5_1__Tie0_4_4__Reg1_0,
2854
  Convert__Reg1_2__Mem256_RC128X5_0__Tie0_3_3__Reg1_4,
2855
  Convert__Reg1_2__Mem512_RC256X5_0__Tie0_3_3__Reg1_4,
2856
  Convert__Reg1_3__Mem128_RC256X5_1__Tie0_4_4__Reg1_0,
2857
  Convert__Reg1_3__Mem64_RC128X5_1__Tie0_4_4__Reg1_0,
2858
  Convert__Reg1_3__Mem256_RC5125_1__Tie0_4_4__Reg1_0,
2859
  Convert__Reg1_2__Mem128_RC256X5_0__Tie0_3_3__Reg1_4,
2860
  Convert__Reg1_2__Mem256_RC5125_0__Tie0_3_3__Reg1_4,
2861
  Convert__Reg1_2__Mem64_RC128X5_0__Tie0_3_3__Reg1_4,
2862
  Convert__Reg1_0__Reg1_1__Tie0_1_1__Tie1_2_2,
2863
  Convert__Reg1_1__Reg1_0__Tie0_2_2__Tie1_1_1,
2864
  Convert__AbsMem161_0,
2865
  Convert__Reg1_1__Tie0_2_2,
2866
  Convert__regEAX__regEAX__Tie0_1_1__Tie1_1_1,
2867
  CVT_NUM_SIGNATURES
2868
};
2869
2870
} // end anonymous namespace
2871
2872
static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][13] = {
2873
  // Convert_NoOperands
2874
  { CVT_Done },
2875
  // Convert__imm_95_10
2876
  { CVT_imm_95_10, 0, CVT_Done },
2877
  // Convert__Imm1_0
2878
  { CVT_95_addImmOperands, 1, CVT_Done },
2879
  // Convert__Imm1_1
2880
  { CVT_95_addImmOperands, 2, CVT_Done },
2881
  // Convert__regAX__Tie0_1_1__ImmSExti16i81_1
2882
  { CVT_regAX, 0, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2883
  // Convert__regEAX__Tie0_1_1__ImmSExti32i81_1
2884
  { CVT_regEAX, 0, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2885
  // Convert__regRAX__Tie0_1_1__ImmSExti64i81_1
2886
  { CVT_regRAX, 0, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2887
  // Convert__ImmSExti64i321_1
2888
  { CVT_95_addImmOperands, 2, CVT_Done },
2889
  // Convert__Reg1_0__Tie0_1_1__Reg1_1
2890
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
2891
  // Convert__Reg1_0__Tie0_1_1__ImmSExti16i81_1
2892
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2893
  // Convert__Reg1_0__Tie0_1_1__Imm1_1
2894
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2895
  // Convert__Reg1_0__Tie0_1_1__Mem165_1
2896
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
2897
  // Convert__Reg1_0__Tie0_1_1__ImmSExti32i81_1
2898
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2899
  // Convert__Reg1_0__Tie0_1_1__Mem325_1
2900
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
2901
  // Convert__Reg1_0__Tie0_1_1__ImmSExti64i81_1
2902
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2903
  // Convert__Reg1_0__Tie0_1_1__ImmSExti64i321_1
2904
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
2905
  // Convert__Reg1_0__Tie0_1_1__Mem645_1
2906
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
2907
  // Convert__Reg1_0__Tie0_1_1__Mem85_1
2908
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
2909
  // Convert__Mem165_0__Reg1_1
2910
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_Done },
2911
  // Convert__Mem165_0__ImmSExti16i81_1
2912
  { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2913
  // Convert__Mem165_0__Imm1_1
2914
  { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2915
  // Convert__Mem325_0__Reg1_1
2916
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_Done },
2917
  // Convert__Mem325_0__ImmSExti32i81_1
2918
  { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2919
  // Convert__Mem325_0__Imm1_1
2920
  { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2921
  // Convert__Mem645_0__Reg1_1
2922
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_Done },
2923
  // Convert__Mem645_0__ImmSExti64i81_1
2924
  { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2925
  // Convert__Mem645_0__ImmSExti64i321_1
2926
  { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2927
  // Convert__Mem85_0__Reg1_1
2928
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_Done },
2929
  // Convert__Mem85_0__Imm1_1
2930
  { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
2931
  // Convert__Reg1_1__Tie0_2_2__Reg1_0
2932
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 1, CVT_Done },
2933
  // Convert__Mem85_1__Reg1_0
2934
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
2935
  // Convert__Reg1_1__Tie0_2_2__Imm1_0
2936
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 1, CVT_Done },
2937
  // Convert__Mem85_1__Imm1_0
2938
  { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2939
  // Convert__Reg1_1__Tie0_2_2__Mem85_0
2940
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addMemOperands, 1, CVT_Done },
2941
  // Convert__Mem325_1__Reg1_0
2942
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
2943
  // Convert__regEAX__Tie0_1_1__ImmSExti32i81_0
2944
  { CVT_regEAX, 0, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 1, CVT_Done },
2945
  // Convert__Reg1_1__Tie0_2_2__ImmSExti32i81_0
2946
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 1, CVT_Done },
2947
  // Convert__Mem325_1__ImmSExti32i81_0
2948
  { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2949
  // Convert__Mem325_1__Imm1_0
2950
  { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2951
  // Convert__Reg1_1__Tie0_2_2__Mem325_0
2952
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addMemOperands, 1, CVT_Done },
2953
  // Convert__Mem645_1__Reg1_0
2954
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
2955
  // Convert__regRAX__Tie0_1_1__ImmSExti64i81_0
2956
  { CVT_regRAX, 0, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 1, CVT_Done },
2957
  // Convert__Reg1_1__Tie0_2_2__ImmSExti64i81_0
2958
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 1, CVT_Done },
2959
  // Convert__Mem645_1__ImmSExti64i81_0
2960
  { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2961
  // Convert__ImmSExti64i321_0
2962
  { CVT_95_addImmOperands, 1, CVT_Done },
2963
  // Convert__Reg1_1__Tie0_2_2__ImmSExti64i321_0
2964
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 1, CVT_Done },
2965
  // Convert__Mem645_1__ImmSExti64i321_0
2966
  { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2967
  // Convert__Reg1_1__Tie0_2_2__Mem645_0
2968
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addMemOperands, 1, CVT_Done },
2969
  // Convert__Mem165_1__Reg1_0
2970
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
2971
  // Convert__regAX__Tie0_1_1__ImmSExti16i81_0
2972
  { CVT_regAX, 0, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 1, CVT_Done },
2973
  // Convert__Reg1_1__Tie0_2_2__ImmSExti16i81_0
2974
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 1, CVT_Done },
2975
  // Convert__Mem165_1__ImmSExti16i81_0
2976
  { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2977
  // Convert__Mem165_1__Imm1_0
2978
  { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
2979
  // Convert__Reg1_1__Tie0_2_2__Mem165_0
2980
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addMemOperands, 1, CVT_Done },
2981
  // Convert__Reg1_1__Tie0_1_1__Reg1_0
2982
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 1, CVT_Done },
2983
  // Convert__Reg1_1__Tie0_1_1__Mem325_0
2984
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 1, CVT_Done },
2985
  // Convert__Reg1_1__Tie0_1_1__Mem645_0
2986
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 1, CVT_Done },
2987
  // Convert__Reg1_0__Tie0_1_1__Mem1285_1
2988
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
2989
  // Convert__Reg1_1__Tie0_1_1__Mem1285_0
2990
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 1, CVT_Done },
2991
  // Convert__Reg1_1__Reg1_0
2992
  { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
2993
  // Convert__Reg1_0__Reg1_1
2994
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
2995
  // Convert__Reg1_0__Mem1285_1
2996
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_Done },
2997
  // Convert__Reg1_1__Mem1285_0
2998
  { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
2999
  // Convert__Reg1_0__Reg1_1__ImmUnsignedi81_2
3000
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3001
  // Convert__Reg1_0__Mem1285_1__ImmUnsignedi81_2
3002
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3003
  // Convert__Reg1_2__Reg1_1__ImmUnsignedi81_0
3004
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3005
  // Convert__Reg1_2__Mem1285_1__ImmUnsignedi81_0
3006
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3007
  // Convert__Reg1_0__Reg1_1__Reg1_2
3008
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
3009
  // Convert__Reg1_0__Reg1_1__Mem325_2
3010
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3011
  // Convert__Reg1_0__Reg1_1__Mem645_2
3012
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3013
  // Convert__Reg1_2__Reg1_1__Reg1_0
3014
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
3015
  // Convert__Reg1_2__Reg1_1__Mem325_0
3016
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3017
  // Convert__Reg1_2__Reg1_1__Mem645_0
3018
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3019
  // Convert__Reg1_0__Reg1_1__Imm1_2
3020
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3021
  // Convert__Reg1_0__Mem325_1__Reg1_2
3022
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_Reg, 3, CVT_Done },
3023
  // Convert__Reg1_0__Mem325_1__Imm1_2
3024
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3025
  // Convert__Reg1_0__Reg1_1__ImmSExti64i321_2
3026
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3027
  // Convert__Reg1_0__Mem645_1__Reg1_2
3028
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_Reg, 3, CVT_Done },
3029
  // Convert__Reg1_0__Mem645_1__ImmSExti64i321_2
3030
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3031
  // Convert__Reg1_2__Mem325_1__Reg1_0
3032
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
3033
  // Convert__Reg1_2__Reg1_1__Imm1_0
3034
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3035
  // Convert__Reg1_2__Mem325_1__Imm1_0
3036
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3037
  // Convert__Reg1_2__Mem645_1__Reg1_0
3038
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
3039
  // Convert__Reg1_2__Reg1_1__ImmSExti64i321_0
3040
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3041
  // Convert__Reg1_2__Mem645_1__ImmSExti64i321_0
3042
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3043
  // Convert__Reg1_0__Mem325_1
3044
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_Done },
3045
  // Convert__Reg1_0__Mem645_1
3046
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_Done },
3047
  // Convert__Reg1_1__Mem325_0
3048
  { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3049
  // Convert__Reg1_1__Mem645_0
3050
  { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3051
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmUnsignedi81_2
3052
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3053
  // Convert__Reg1_0__Tie0_1_1__Mem1285_1__ImmUnsignedi81_2
3054
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3055
  // Convert__Reg1_2__Tie0_1_1__Reg1_1__ImmUnsignedi81_0
3056
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3057
  // Convert__Reg1_2__Tie0_1_1__Mem1285_1__ImmUnsignedi81_0
3058
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3059
  // Convert__Reg1_1__Tie0_2_2__Mem1285_0
3060
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addMemOperands, 1, CVT_Done },
3061
  // Convert__Reg1_2__Tie0_1_1__Reg1_1
3062
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
3063
  // Convert__Reg1_2__Tie0_1_1__Mem1285_1
3064
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
3065
  // Convert__Reg1_0__Mem5_1
3066
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_Done },
3067
  // Convert__Reg1_1__Mem5_0
3068
  { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3069
  // Convert__Mem1285_1__Reg1_0
3070
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
3071
  // Convert__Mem1285_0__Reg1_1
3072
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_Done },
3073
  // Convert__Mem5_1__Reg1_0
3074
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
3075
  // Convert__Mem5_0__Reg1_1
3076
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_Done },
3077
  // Convert__Reg1_0__Mem165_1
3078
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_Done },
3079
  // Convert__Reg1_1__Mem165_0
3080
  { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3081
  // Convert__Reg1_0__Tie0_1_1
3082
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done },
3083
  // Convert__Reg1_0__ImmSExti16i81_1
3084
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3085
  // Convert__Reg1_0__ImmSExti32i81_1
3086
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3087
  // Convert__Reg1_0__ImmSExti64i81_1
3088
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3089
  // Convert__Reg1_1__ImmSExti32i81_0
3090
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3091
  // Convert__Reg1_1__ImmSExti64i81_0
3092
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3093
  // Convert__Reg1_1__ImmSExti16i81_0
3094
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3095
  // Convert__Reg1_0
3096
  { CVT_95_Reg, 1, CVT_Done },
3097
  // Convert__AbsMem1_0
3098
  { CVT_95_addAbsMemOperands, 1, CVT_Done },
3099
  // Convert__Mem165_0
3100
  { CVT_95_addMemOperands, 1, CVT_Done },
3101
  // Convert__Mem325_0
3102
  { CVT_95_addMemOperands, 1, CVT_Done },
3103
  // Convert__Mem645_0
3104
  { CVT_95_addMemOperands, 1, CVT_Done },
3105
  // Convert__Mem5_0
3106
  { CVT_95_addMemOperands, 1, CVT_Done },
3107
  // Convert__Imm1_1__Imm1_0
3108
  { CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3109
  // Convert__Reg1_1
3110
  { CVT_95_Reg, 2, CVT_Done },
3111
  // Convert__Mem325_1
3112
  { CVT_95_addMemOperands, 2, CVT_Done },
3113
  // Convert__Mem645_1
3114
  { CVT_95_addMemOperands, 2, CVT_Done },
3115
  // Convert__Mem165_1
3116
  { CVT_95_addMemOperands, 2, CVT_Done },
3117
  // Convert__Mem85_0
3118
  { CVT_95_addMemOperands, 1, CVT_Done },
3119
  // Convert__Reg1_0__Tie0_1_1__Reg1_0
3120
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 1, CVT_Done },
3121
  // Convert__Reg1_1__Tie0_1_1__Mem165_0
3122
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 1, CVT_Done },
3123
  // Convert__regAX__ImmSExti16i81_1
3124
  { CVT_regAX, 0, CVT_95_addImmOperands, 2, CVT_Done },
3125
  // Convert__regEAX__ImmSExti32i81_1
3126
  { CVT_regEAX, 0, CVT_95_addImmOperands, 2, CVT_Done },
3127
  // Convert__regRAX__ImmSExti64i81_1
3128
  { CVT_regRAX, 0, CVT_95_addImmOperands, 2, CVT_Done },
3129
  // Convert__Reg1_0__Imm1_1
3130
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3131
  // Convert__Reg1_0__ImmSExti64i321_1
3132
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3133
  // Convert__Reg1_0__Mem85_1
3134
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_Done },
3135
  // Convert__Reg1_3__Tie0_1_1__Reg1_2__Imm1_0
3136
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
3137
  // Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_0
3138
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 1, CVT_Done },
3139
  // Convert__Reg1_2__Tie0_1_1__Mem1285_3__Imm1_0
3140
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 4, CVT_95_addImmOperands, 1, CVT_Done },
3141
  // Convert__Reg1_3__Tie0_1_1__Mem1285_2__Imm1_0
3142
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3143
  // Convert__Reg1_2__Tie0_1_1__Mem645_3__Imm1_0
3144
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 4, CVT_95_addImmOperands, 1, CVT_Done },
3145
  // Convert__Reg1_3__Tie0_1_1__Mem645_2__Imm1_0
3146
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3147
  // Convert__Reg1_2__Tie0_1_1__Mem325_3__Imm1_0
3148
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 4, CVT_95_addImmOperands, 1, CVT_Done },
3149
  // Convert__Reg1_3__Tie0_1_1__Mem325_2__Imm1_0
3150
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3151
  // Convert__Reg1_1__Imm1_0
3152
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3153
  // Convert__Reg1_1__Mem85_0
3154
  { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3155
  // Convert__regEAX__ImmSExti32i81_0
3156
  { CVT_regEAX, 0, CVT_95_addImmOperands, 1, CVT_Done },
3157
  // Convert__regRAX__ImmSExti64i81_0
3158
  { CVT_regRAX, 0, CVT_95_addImmOperands, 1, CVT_Done },
3159
  // Convert__Reg1_1__ImmSExti64i321_0
3160
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3161
  // Convert__DstIdx161_1__SrcIdx162_0
3162
  { CVT_95_addDstIdxOperands, 2, CVT_95_addSrcIdxOperands, 1, CVT_Done },
3163
  // Convert__DstIdx321_1__SrcIdx322_0
3164
  { CVT_95_addDstIdxOperands, 2, CVT_95_addSrcIdxOperands, 1, CVT_Done },
3165
  // Convert__DstIdx641_1__SrcIdx642_0
3166
  { CVT_95_addDstIdxOperands, 2, CVT_95_addSrcIdxOperands, 1, CVT_Done },
3167
  // Convert__DstIdx81_1__SrcIdx82_0
3168
  { CVT_95_addDstIdxOperands, 2, CVT_95_addSrcIdxOperands, 1, CVT_Done },
3169
  // Convert__DstIdx81_0__SrcIdx82_1
3170
  { CVT_95_addDstIdxOperands, 1, CVT_95_addSrcIdxOperands, 2, CVT_Done },
3171
  // Convert__Reg1_0__Tie0_1_1__Mem645_1__ImmUnsignedi81_2
3172
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3173
  // Convert__Reg1_2__Tie0_1_1__Mem645_1__ImmUnsignedi81_0
3174
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3175
  // Convert__DstIdx321_0__SrcIdx322_1
3176
  { CVT_95_addDstIdxOperands, 1, CVT_95_addSrcIdxOperands, 2, CVT_Done },
3177
  // Convert__DstIdx641_0__SrcIdx642_1
3178
  { CVT_95_addDstIdxOperands, 1, CVT_95_addSrcIdxOperands, 2, CVT_Done },
3179
  // Convert__Reg1_0__Tie0_1_1__Mem325_1__ImmUnsignedi81_2
3180
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3181
  // Convert__Reg1_2__Tie0_1_1__Mem325_1__ImmUnsignedi81_0
3182
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3183
  // Convert__DstIdx161_0__SrcIdx162_1
3184
  { CVT_95_addDstIdxOperands, 1, CVT_95_addSrcIdxOperands, 2, CVT_Done },
3185
  // Convert__regAX__ImmSExti16i81_0
3186
  { CVT_regAX, 0, CVT_95_addImmOperands, 1, CVT_Done },
3187
  // Convert__Mem1285_0
3188
  { CVT_95_addMemOperands, 1, CVT_Done },
3189
  // Convert__Mem85_1
3190
  { CVT_95_addMemOperands, 2, CVT_Done },
3191
  // Convert__Imm1_0__Imm1_1
3192
  { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
3193
  // Convert__GR32orGR641_2__Reg1_1__ImmUnsignedi81_0
3194
  { CVT_95_addGR32orGR64Operands, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3195
  // Convert__Mem325_2__Reg1_1__ImmUnsignedi81_0
3196
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3197
  // Convert__GR32orGR641_0__Reg1_1__ImmUnsignedi81_2
3198
  { CVT_95_addGR32orGR64Operands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3199
  // Convert__Mem325_0__Reg1_1__ImmUnsignedi81_2
3200
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3201
  // Convert__Reg1_0__Tie0_1_1__ImmUnsignedi81_1__ImmUnsignedi81_2
3202
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3203
  // Convert__Reg1_2__Tie0_3_3__ImmUnsignedi81_1__ImmUnsignedi81_0
3204
  { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3205
  // Convert__regST1
3206
  { CVT_regST1, 0, CVT_Done },
3207
  // Convert__regST0
3208
  { CVT_regST0, 0, CVT_Done },
3209
  // Convert__Mem805_0
3210
  { CVT_95_addMemOperands, 1, CVT_Done },
3211
  // Convert__Reg1_0__Reg1_0__ImmSExti16i81_1
3212
  { CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3213
  // Convert__Reg1_0__Reg1_0__Imm1_1
3214
  { CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3215
  // Convert__Reg1_0__Reg1_0__ImmSExti32i81_1
3216
  { CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3217
  // Convert__Reg1_0__Reg1_0__ImmSExti64i81_1
3218
  { CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3219
  // Convert__Reg1_0__Reg1_0__ImmSExti64i321_1
3220
  { CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3221
  // Convert__Reg1_0__Reg1_1__ImmSExti16i81_2
3222
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3223
  // Convert__Reg1_0__Mem165_1__ImmSExti16i81_2
3224
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3225
  // Convert__Reg1_0__Mem165_1__Imm1_2
3226
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3227
  // Convert__Reg1_0__Reg1_1__ImmSExti32i81_2
3228
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3229
  // Convert__Reg1_0__Mem325_1__ImmSExti32i81_2
3230
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3231
  // Convert__Reg1_0__Reg1_1__ImmSExti64i81_2
3232
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3233
  // Convert__Reg1_0__Mem645_1__ImmSExti64i81_2
3234
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3235
  // Convert__Reg1_1__Reg1_1__ImmSExti32i81_0
3236
  { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3237
  // Convert__Reg1_1__Reg1_1__Imm1_0
3238
  { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3239
  // Convert__Reg1_2__Reg1_1__ImmSExti32i81_0
3240
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3241
  // Convert__Reg1_2__Mem325_1__ImmSExti32i81_0
3242
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3243
  // Convert__Reg1_1__Reg1_1__ImmSExti64i81_0
3244
  { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3245
  // Convert__Reg1_1__Reg1_1__ImmSExti64i321_0
3246
  { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3247
  // Convert__Reg1_2__Reg1_1__ImmSExti64i81_0
3248
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3249
  // Convert__Reg1_2__Mem645_1__ImmSExti64i81_0
3250
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3251
  // Convert__Reg1_1__Reg1_1__ImmSExti16i81_0
3252
  { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3253
  // Convert__Reg1_2__Reg1_1__ImmSExti16i81_0
3254
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3255
  // Convert__Reg1_2__Mem165_1__ImmSExti16i81_0
3256
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3257
  // Convert__Reg1_2__Mem165_1__Imm1_0
3258
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3259
  // Convert__ImmUnsignedi81_1
3260
  { CVT_95_addImmOperands, 2, CVT_Done },
3261
  // Convert__ImmUnsignedi81_0
3262
  { CVT_95_addImmOperands, 1, CVT_Done },
3263
  // Convert__DstIdx161_0
3264
  { CVT_95_addDstIdxOperands, 1, CVT_Done },
3265
  // Convert__DstIdx321_0
3266
  { CVT_95_addDstIdxOperands, 1, CVT_Done },
3267
  // Convert__DstIdx81_0
3268
  { CVT_95_addDstIdxOperands, 1, CVT_Done },
3269
  // Convert__DstIdx81_1
3270
  { CVT_95_addDstIdxOperands, 2, CVT_Done },
3271
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmUnsignedi81_2__ImmUnsignedi81_3
3272
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3273
  // Convert__Reg1_3__Tie0_4_4__Reg1_2__ImmUnsignedi81_1__ImmUnsignedi81_0
3274
  { CVT_95_Reg, 4, CVT_Tied, Tie0_4_4, CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3275
  // Convert__DstIdx321_1
3276
  { CVT_95_addDstIdxOperands, 2, CVT_Done },
3277
  // Convert__DstIdx161_1
3278
  { CVT_95_addDstIdxOperands, 2, CVT_Done },
3279
  // Convert__Mem5_1
3280
  { CVT_95_addMemOperands, 2, CVT_Done },
3281
  // Convert__SrcIdx162_0
3282
  { CVT_95_addSrcIdxOperands, 1, CVT_Done },
3283
  // Convert__SrcIdx322_0
3284
  { CVT_95_addSrcIdxOperands, 1, CVT_Done },
3285
  // Convert__SrcIdx642_0
3286
  { CVT_95_addSrcIdxOperands, 1, CVT_Done },
3287
  // Convert__SrcIdx82_0
3288
  { CVT_95_addSrcIdxOperands, 1, CVT_Done },
3289
  // Convert__SrcIdx82_1
3290
  { CVT_95_addSrcIdxOperands, 2, CVT_Done },
3291
  // Convert__SrcIdx162_1
3292
  { CVT_95_addSrcIdxOperands, 2, CVT_Done },
3293
  // Convert__SrcIdx322_1
3294
  { CVT_95_addSrcIdxOperands, 2, CVT_Done },
3295
  // Convert__SrcIdx642_1
3296
  { CVT_95_addSrcIdxOperands, 2, CVT_Done },
3297
  // Convert__MemOffs16_82_1
3298
  { CVT_95_addMemOffsOperands, 2, CVT_Done },
3299
  // Convert__MemOffs32_82_1
3300
  { CVT_95_addMemOffsOperands, 2, CVT_Done },
3301
  // Convert__MemOffs16_162_1
3302
  { CVT_95_addMemOffsOperands, 2, CVT_Done },
3303
  // Convert__MemOffs32_162_1
3304
  { CVT_95_addMemOffsOperands, 2, CVT_Done },
3305
  // Convert__MemOffs16_322_1
3306
  { CVT_95_addMemOffsOperands, 2, CVT_Done },
3307
  // Convert__MemOffs32_322_1
3308
  { CVT_95_addMemOffsOperands, 2, CVT_Done },
3309
  // Convert__MemOffs32_642_1
3310
  { CVT_95_addMemOffsOperands, 2, CVT_Done },
3311
  // Convert__MemOffs16_162_0
3312
  { CVT_95_addMemOffsOperands, 1, CVT_Done },
3313
  // Convert__MemOffs16_322_0
3314
  { CVT_95_addMemOffsOperands, 1, CVT_Done },
3315
  // Convert__MemOffs16_82_0
3316
  { CVT_95_addMemOffsOperands, 1, CVT_Done },
3317
  // Convert__MemOffs32_162_0
3318
  { CVT_95_addMemOffsOperands, 1, CVT_Done },
3319
  // Convert__MemOffs32_322_0
3320
  { CVT_95_addMemOffsOperands, 1, CVT_Done },
3321
  // Convert__MemOffs32_642_0
3322
  { CVT_95_addMemOffsOperands, 1, CVT_Done },
3323
  // Convert__MemOffs32_82_0
3324
  { CVT_95_addMemOffsOperands, 1, CVT_Done },
3325
  // Convert__MemOffs64_82_1
3326
  { CVT_95_addMemOffsOperands, 2, CVT_Done },
3327
  // Convert__MemOffs64_162_1
3328
  { CVT_95_addMemOffsOperands, 2, CVT_Done },
3329
  // Convert__MemOffs64_322_1
3330
  { CVT_95_addMemOffsOperands, 2, CVT_Done },
3331
  // Convert__MemOffs64_642_1
3332
  { CVT_95_addMemOffsOperands, 2, CVT_Done },
3333
  // Convert__MemOffs64_162_0
3334
  { CVT_95_addMemOffsOperands, 1, CVT_Done },
3335
  // Convert__MemOffs64_322_0
3336
  { CVT_95_addMemOffsOperands, 1, CVT_Done },
3337
  // Convert__MemOffs64_642_0
3338
  { CVT_95_addMemOffsOperands, 1, CVT_Done },
3339
  // Convert__MemOffs64_82_0
3340
  { CVT_95_addMemOffsOperands, 1, CVT_Done },
3341
  // Convert__Reg1_0__Mem5125_1
3342
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_Done },
3343
  // Convert__Reg1_1__Mem5125_0
3344
  { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3345
  // Convert__GR32orGR641_1__Reg1_0
3346
  { CVT_95_addGR32orGR64Operands, 2, CVT_95_Reg, 1, CVT_Done },
3347
  // Convert__GR32orGR641_0__Reg1_1
3348
  { CVT_95_addGR32orGR64Operands, 1, CVT_95_Reg, 2, CVT_Done },
3349
  // Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_17
3350
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 1, CVT_imm_95_17, 0, CVT_Done },
3351
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_17
3352
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_imm_95_17, 0, CVT_Done },
3353
  // Convert__Reg1_0__Tie0_1_1__Mem1285_1__imm_95_17
3354
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_imm_95_17, 0, CVT_Done },
3355
  // Convert__Reg1_1__Tie0_2_2__Mem1285_0__imm_95_17
3356
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addMemOperands, 1, CVT_imm_95_17, 0, CVT_Done },
3357
  // Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_1
3358
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_Done },
3359
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_1
3360
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_imm_95_1, 0, CVT_Done },
3361
  // Convert__Reg1_0__Tie0_1_1__Mem1285_1__imm_95_1
3362
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_imm_95_1, 0, CVT_Done },
3363
  // Convert__Reg1_1__Tie0_2_2__Mem1285_0__imm_95_1
3364
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addMemOperands, 1, CVT_imm_95_1, 0, CVT_Done },
3365
  // Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_16
3366
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 1, CVT_imm_95_16, 0, CVT_Done },
3367
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_16
3368
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_imm_95_16, 0, CVT_Done },
3369
  // Convert__Reg1_0__Tie0_1_1__Mem1285_1__imm_95_16
3370
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_imm_95_16, 0, CVT_Done },
3371
  // Convert__Reg1_1__Tie0_2_2__Mem1285_0__imm_95_16
3372
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addMemOperands, 1, CVT_imm_95_16, 0, CVT_Done },
3373
  // Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_0
3374
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done },
3375
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_0
3376
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
3377
  // Convert__Reg1_0__Tie0_1_1__Mem1285_1__imm_95_0
3378
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_imm_95_0, 0, CVT_Done },
3379
  // Convert__Reg1_1__Tie0_2_2__Mem1285_0__imm_95_0
3380
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addMemOperands, 1, CVT_imm_95_0, 0, CVT_Done },
3381
  // Convert__Mem85_2__Reg1_1__ImmUnsignedi81_0
3382
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3383
  // Convert__Mem85_0__Reg1_1__ImmUnsignedi81_2
3384
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3385
  // Convert__Mem645_2__Reg1_1__ImmUnsignedi81_0
3386
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3387
  // Convert__Mem645_0__Reg1_1__ImmUnsignedi81_2
3388
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3389
  // Convert__Mem165_2__Reg1_1__ImmUnsignedi81_0
3390
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3391
  // Convert__Mem165_0__Reg1_1__ImmUnsignedi81_2
3392
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3393
  // Convert__Reg1_0__Tie0_1_1__GR32orGR641_1__ImmUnsignedi81_2
3394
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addGR32orGR64Operands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3395
  // Convert__Reg1_0__Tie0_1_1__Mem85_1__ImmUnsignedi81_2
3396
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3397
  // Convert__Reg1_2__Tie0_1_1__GR32orGR641_1__ImmUnsignedi81_0
3398
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addGR32orGR64Operands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3399
  // Convert__Reg1_2__Tie0_1_1__Mem85_1__ImmUnsignedi81_0
3400
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3401
  // Convert__Reg1_0__Tie0_1_1__Mem165_1__ImmUnsignedi81_2
3402
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3403
  // Convert__Reg1_2__Tie0_1_1__Mem165_1__ImmUnsignedi81_0
3404
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3405
  // Convert__Reg1_0__Mem645_1__ImmUnsignedi81_2
3406
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3407
  // Convert__Reg1_2__Mem645_1__ImmUnsignedi81_0
3408
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3409
  // Convert__Reg1_0__Tie0_1_1__ImmUnsignedi81_1
3410
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
3411
  // Convert__Reg1_1__Tie0_1_1__ImmUnsignedi81_0
3412
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 1, CVT_Done },
3413
  // Convert__ImmSExti64i81_0
3414
  { CVT_95_addImmOperands, 1, CVT_Done },
3415
  // Convert__ImmSExti16i81_0
3416
  { CVT_95_addImmOperands, 1, CVT_Done },
3417
  // Convert__ImmSExti32i81_0
3418
  { CVT_95_addImmOperands, 1, CVT_Done },
3419
  // Convert__Mem165_0__ImmUnsignedi81_1
3420
  { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
3421
  // Convert__Mem325_0__ImmUnsignedi81_1
3422
  { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
3423
  // Convert__Mem645_0__ImmUnsignedi81_1
3424
  { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
3425
  // Convert__Mem85_0__ImmUnsignedi81_1
3426
  { CVT_95_addMemOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
3427
  // Convert__Reg1_1__Tie0_1_1
3428
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_Done },
3429
  // Convert__Mem85_1__ImmUnsignedi81_0
3430
  { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3431
  // Convert__Mem325_1__ImmUnsignedi81_0
3432
  { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3433
  // Convert__Mem645_1__ImmUnsignedi81_0
3434
  { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3435
  // Convert__Mem165_1__ImmUnsignedi81_0
3436
  { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3437
  // Convert__Reg1_0__Mem325_1__ImmUnsignedi81_2
3438
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3439
  // Convert__Reg1_2__Mem325_1__ImmUnsignedi81_0
3440
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3441
  // Convert__DstIdx641_0
3442
  { CVT_95_addDstIdxOperands, 1, CVT_Done },
3443
  // Convert__DstIdx641_1
3444
  { CVT_95_addDstIdxOperands, 2, CVT_Done },
3445
  // Convert__Mem325_2__Reg1_1
3446
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_Done },
3447
  // Convert__Mem645_2__Reg1_1
3448
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_Done },
3449
  // Convert__Mem165_2__Reg1_1
3450
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_Done },
3451
  // Convert__GR32orGR641_0
3452
  { CVT_95_addGR32orGR64Operands, 1, CVT_Done },
3453
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem1285_2
3454
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3455
  // Convert__Reg1_2__Tie0_1_1__Reg1_1__Mem1285_0
3456
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3457
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem1285_5
3458
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3459
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__Mem1285_0
3460
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3461
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem1285_6
3462
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3463
  // Convert__Reg1_0__Reg1_1__Mem1285_2
3464
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3465
  // Convert__Reg1_0__Reg1_1__Mem2565_2
3466
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3467
  // Convert__Reg1_0__Reg1_1__Mem5125_2
3468
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3469
  // Convert__Reg1_2__Reg1_1__Mem1285_0
3470
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3471
  // Convert__Reg1_2__Reg1_1__Mem2565_0
3472
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3473
  // Convert__Reg1_2__Reg1_1__Mem5125_0
3474
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3475
  // Convert__Reg1_0__Reg1_1__Reg1_2__AVX512RC1_3
3476
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addAVX512RCOperands, 4, CVT_Done },
3477
  // Convert__Reg1_3__Reg1_2__Reg1_1__AVX512RC1_0
3478
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addAVX512RCOperands, 1, CVT_Done },
3479
  // Convert__Reg1_3__Reg1_2__Mem645_0
3480
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3481
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5
3482
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_Done },
3483
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__Reg1_0
3484
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
3485
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem2565_5
3486
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3487
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem5125_5
3488
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3489
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__Mem2565_0
3490
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3491
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__Mem5125_0
3492
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3493
  // Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6
3494
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_Done },
3495
  // Convert__Reg1_0__Reg1_2__Reg1_5__Mem1285_6
3496
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3497
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem645_5
3498
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3499
  // Convert__Reg1_2__Reg1_4__Reg1_1__Reg1_0
3500
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
3501
  // Convert__Reg1_0__Reg1_2__Reg1_5__Mem2565_6
3502
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3503
  // Convert__Reg1_0__Reg1_2__Reg1_5__Mem5125_6
3504
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3505
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5__AVX512RC1_6
3506
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addAVX512RCOperands, 7, CVT_Done },
3507
  // Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Reg1_1__AVX512RC1_0
3508
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addAVX512RCOperands, 1, CVT_Done },
3509
  // Convert__Reg1_2__Reg1_4__Reg1_1__Mem1285_0
3510
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3511
  // Convert__Reg1_2__Reg1_4__Reg1_1__Mem2565_0
3512
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3513
  // Convert__Reg1_2__Reg1_4__Reg1_1__Mem5125_0
3514
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3515
  // Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem645_0
3516
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3517
  // Convert__Reg1_0__Reg1_2__Reg1_5__Mem645_6
3518
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3519
  // Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6__AVX512RC1_7
3520
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addAVX512RCOperands, 8, CVT_Done },
3521
  // Convert__Reg1_3__Reg1_5__Reg1_2__Reg1_1__AVX512RC1_0
3522
  { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addAVX512RCOperands, 1, CVT_Done },
3523
  // Convert__Reg1_3__Reg1_5__Reg1_2__Mem645_0
3524
  { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3525
  // Convert__Reg1_3__Reg1_2__Mem325_0
3526
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3527
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem325_5
3528
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3529
  // Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem325_0
3530
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3531
  // Convert__Reg1_0__Reg1_2__Reg1_5__Mem325_6
3532
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3533
  // Convert__Reg1_3__Reg1_5__Reg1_2__Mem325_0
3534
  { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3535
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__Mem645_0
3536
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3537
  // Convert__Reg1_2__Reg1_4__Reg1_1__Mem645_0
3538
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3539
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__Mem325_0
3540
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3541
  // Convert__Reg1_2__Reg1_4__Reg1_1__Mem325_0
3542
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3543
  // Convert__Reg1_0__Reg1_1__Reg1_2__ImmUnsignedi81_3
3544
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
3545
  // Convert__Reg1_0__Reg1_1__Mem1285_2__ImmUnsignedi81_3
3546
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3547
  // Convert__Reg1_0__Reg1_1__Mem2565_2__ImmUnsignedi81_3
3548
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3549
  // Convert__Reg1_0__Reg1_1__Mem5125_2__ImmUnsignedi81_3
3550
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3551
  // Convert__Reg1_3__Reg1_2__Reg1_1__ImmUnsignedi81_0
3552
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3553
  // Convert__Reg1_3__Reg1_2__Mem1285_1__ImmUnsignedi81_0
3554
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3555
  // Convert__Reg1_3__Reg1_2__Mem2565_1__ImmUnsignedi81_0
3556
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3557
  // Convert__Reg1_3__Reg1_2__Mem5125_1__ImmUnsignedi81_0
3558
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3559
  // Convert__Reg1_0__Reg1_1__Mem325_2__ImmUnsignedi81_4
3560
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 5, CVT_Done },
3561
  // Convert__Reg1_4__Reg1_3__Mem325_1__ImmUnsignedi81_0
3562
  { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3563
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5__ImmUnsignedi81_6
3564
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addImmOperands, 7, CVT_Done },
3565
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem1285_5__ImmUnsignedi81_6
3566
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3567
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem2565_5__ImmUnsignedi81_6
3568
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3569
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem5125_5__ImmUnsignedi81_6
3570
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3571
  // Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Reg1_1__ImmUnsignedi81_0
3572
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3573
  // Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem1285_1__ImmUnsignedi81_0
3574
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3575
  // Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem2565_1__ImmUnsignedi81_0
3576
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3577
  // Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem5125_1__ImmUnsignedi81_0
3578
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3579
  // Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6__ImmUnsignedi81_7
3580
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addImmOperands, 8, CVT_Done },
3581
  // Convert__Reg1_0__Reg1_2__Reg1_5__Mem1285_6__ImmUnsignedi81_7
3582
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
3583
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem325_5__ImmUnsignedi81_7
3584
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 8, CVT_Done },
3585
  // Convert__Reg1_0__Reg1_2__Reg1_5__Mem2565_6__ImmUnsignedi81_7
3586
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
3587
  // Convert__Reg1_0__Reg1_2__Reg1_5__Mem5125_6__ImmUnsignedi81_7
3588
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
3589
  // Convert__Reg1_3__Reg1_5__Reg1_2__Reg1_1__ImmUnsignedi81_0
3590
  { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3591
  // Convert__Reg1_3__Reg1_5__Reg1_2__Mem1285_1__ImmUnsignedi81_0
3592
  { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3593
  // Convert__Reg1_3__Reg1_5__Reg1_2__Mem2565_1__ImmUnsignedi81_0
3594
  { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3595
  // Convert__Reg1_4__Tie0_1_1__Reg1_6__Reg1_3__Mem325_1__ImmUnsignedi81_0
3596
  { CVT_95_Reg, 5, CVT_Tied, Tie0_1_1, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3597
  // Convert__Reg1_3__Reg1_5__Reg1_2__Mem5125_1__ImmUnsignedi81_0
3598
  { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3599
  // Convert__Reg1_0__Reg1_2__Reg1_5__Mem325_6__ImmUnsignedi81_8
3600
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 9, CVT_Done },
3601
  // Convert__Reg1_4__Reg1_6__Reg1_3__Mem325_1__ImmUnsignedi81_0
3602
  { CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3603
  // Convert__Reg1_0__Reg1_1__Mem645_2__ImmUnsignedi81_4
3604
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 5, CVT_Done },
3605
  // Convert__Reg1_4__Reg1_3__Mem645_1__ImmUnsignedi81_0
3606
  { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3607
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem645_5__ImmUnsignedi81_7
3608
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 8, CVT_Done },
3609
  // Convert__Reg1_4__Tie0_1_1__Reg1_6__Reg1_3__Mem645_1__ImmUnsignedi81_0
3610
  { CVT_95_Reg, 5, CVT_Tied, Tie0_1_1, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3611
  // Convert__Reg1_0__Reg1_2__Reg1_5__Mem645_6__ImmUnsignedi81_8
3612
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 9, CVT_Done },
3613
  // Convert__Reg1_4__Reg1_6__Reg1_3__Mem645_1__ImmUnsignedi81_0
3614
  { CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3615
  // Convert__Reg1_0__Reg1_2__Reg1_4__Reg1_5
3616
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_Done },
3617
  // Convert__Reg1_0__Reg1_2__Reg1_4__Mem1285_5
3618
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3619
  // Convert__Reg1_0__Reg1_2__Reg1_4__Mem2565_5
3620
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3621
  // Convert__Reg1_0__Reg1_2__Reg1_4__Mem5125_5
3622
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3623
  // Convert__Reg1_0__Reg1_2__Reg1_4__Mem645_5
3624
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3625
  // Convert__Reg1_0__Reg1_2__Reg1_4__Mem325_5
3626
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_Done },
3627
  // Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0
3628
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
3629
  // Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3
3630
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
3631
  // Convert__Reg1_0__Reg1_1__Mem1285_2__Reg1_3
3632
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_Reg, 4, CVT_Done },
3633
  // Convert__Reg1_3__Reg1_2__Mem1285_1__Reg1_0
3634
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
3635
  // Convert__Reg1_0__Reg1_1__Mem2565_2__Reg1_3
3636
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_Reg, 4, CVT_Done },
3637
  // Convert__Reg1_3__Reg1_2__Mem2565_1__Reg1_0
3638
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
3639
  // Convert__Reg1_1__Tie0_1_1__Reg1_3__Reg1_0
3640
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_Done },
3641
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4
3642
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_Done },
3643
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem645_4
3644
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_Done },
3645
  // Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem645_0
3646
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3647
  // Convert__Reg1_1__Reg1_3__Reg1_0
3648
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_Done },
3649
  // Convert__Reg1_0__Reg1_2__Reg1_5
3650
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_Done },
3651
  // Convert__Reg1_0__Reg1_2__Mem645_5
3652
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_Done },
3653
  // Convert__Reg1_1__Reg1_3__Mem645_0
3654
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3655
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem1285_4
3656
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_Done },
3657
  // Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem1285_0
3658
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3659
  // Convert__Reg1_0__Reg1_2__Mem1285_5
3660
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_Done },
3661
  // Convert__Reg1_1__Reg1_3__Mem1285_0
3662
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3663
  // Convert__Reg1_0__Mem2565_1
3664
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_Done },
3665
  // Convert__Reg1_1__Mem2565_0
3666
  { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3667
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem2565_4
3668
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_Done },
3669
  // Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem2565_0
3670
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3671
  // Convert__Reg1_0__Reg1_2__Mem2565_5
3672
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_Done },
3673
  // Convert__Reg1_1__Reg1_3__Mem2565_0
3674
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3675
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem325_4
3676
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_Done },
3677
  // Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem325_0
3678
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3679
  // Convert__Reg1_0__Reg1_2__Mem325_5
3680
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_Done },
3681
  // Convert__Reg1_1__Reg1_3__Mem325_0
3682
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3683
  // Convert__Reg1_2__Reg1_3__Reg1_4__Imm1_0
3684
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 1, CVT_Done },
3685
  // Convert__Reg1_2__Reg1_3__Mem1285_4__Imm1_0
3686
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 1, CVT_Done },
3687
  // Convert__Reg1_2__Reg1_3__Mem2565_4__Imm1_0
3688
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 1, CVT_Done },
3689
  // Convert__Reg1_2__Reg1_3__Mem5125_4__Imm1_0
3690
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 1, CVT_Done },
3691
  // Convert__Reg1_4__Reg1_3__Reg1_2__Imm1_0
3692
  { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
3693
  // Convert__Reg1_4__Reg1_3__Mem1285_2__Imm1_0
3694
  { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3695
  // Convert__Reg1_4__Reg1_3__Mem2565_2__Imm1_0
3696
  { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3697
  // Convert__Reg1_4__Reg1_3__Mem5125_2__Imm1_0
3698
  { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3699
  // Convert__Reg1_2__Reg1_3__Mem645_4__Imm1_0
3700
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 1, CVT_Done },
3701
  // Convert__Reg1_4__Reg1_3__Mem645_2__Imm1_0
3702
  { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3703
  // Convert__Reg1_2__Reg1_3__Mem325_4__Imm1_0
3704
  { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 1, CVT_Done },
3705
  // Convert__Reg1_4__Reg1_3__Mem325_2__Imm1_0
3706
  { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3707
  // Convert__Reg1_5__Reg1_4__Reg1_3__Imm1_0
3708
  { CVT_95_Reg, 6, CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addImmOperands, 1, CVT_Done },
3709
  // Convert__Reg1_5__Reg1_4__Mem645_2__Imm1_0
3710
  { CVT_95_Reg, 6, CVT_95_Reg, 5, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3711
  // Convert__Reg1_5__Reg1_4__Mem325_2__Imm1_0
3712
  { CVT_95_Reg, 6, CVT_95_Reg, 5, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3713
  // Convert__Reg1_2__Reg1_4__Reg1_6__Reg1_7__Imm1_0
3714
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_Reg, 8, CVT_95_addImmOperands, 1, CVT_Done },
3715
  // Convert__Reg1_2__Reg1_4__Reg1_6__Mem1285_7__Imm1_0
3716
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_addMemOperands, 8, CVT_95_addImmOperands, 1, CVT_Done },
3717
  // Convert__Reg1_2__Reg1_4__Reg1_6__Mem2565_7__Imm1_0
3718
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_addMemOperands, 8, CVT_95_addImmOperands, 1, CVT_Done },
3719
  // Convert__Reg1_2__Reg1_4__Reg1_6__Mem5125_7__Imm1_0
3720
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_addMemOperands, 8, CVT_95_addImmOperands, 1, CVT_Done },
3721
  // Convert__Reg1_4__Reg1_6__Reg1_3__Reg1_2__Imm1_0
3722
  { CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
3723
  // Convert__Reg1_4__Reg1_6__Reg1_3__Mem1285_2__Imm1_0
3724
  { CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3725
  // Convert__Reg1_4__Reg1_6__Reg1_3__Mem2565_2__Imm1_0
3726
  { CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3727
  // Convert__Reg1_4__Reg1_6__Reg1_3__Mem5125_2__Imm1_0
3728
  { CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3729
  // Convert__Reg1_2__Reg1_4__Reg1_6__Mem645_7__Imm1_0
3730
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_addMemOperands, 8, CVT_95_addImmOperands, 1, CVT_Done },
3731
  // Convert__Reg1_4__Reg1_6__Reg1_3__Mem645_2__Imm1_0
3732
  { CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3733
  // Convert__Reg1_2__Reg1_4__Reg1_6__Mem325_7__Imm1_0
3734
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_addMemOperands, 8, CVT_95_addImmOperands, 1, CVT_Done },
3735
  // Convert__Reg1_4__Reg1_6__Reg1_3__Mem325_2__Imm1_0
3736
  { CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3737
  // Convert__Reg1_5__Reg1_7__Reg1_4__Reg1_3__Imm1_0
3738
  { CVT_95_Reg, 6, CVT_95_Reg, 8, CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addImmOperands, 1, CVT_Done },
3739
  // Convert__Reg1_5__Reg1_7__Reg1_4__Mem645_2__Imm1_0
3740
  { CVT_95_Reg, 6, CVT_95_Reg, 8, CVT_95_Reg, 5, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3741
  // Convert__Reg1_5__Reg1_7__Reg1_4__Mem325_2__Imm1_0
3742
  { CVT_95_Reg, 6, CVT_95_Reg, 8, CVT_95_Reg, 5, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
3743
  // Convert__Reg1_0__Reg1_1__Reg1_2__ImmUnsignedi81_4
3744
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 5, CVT_Done },
3745
  // Convert__Reg1_4__Reg1_3__Reg1_2__ImmUnsignedi81_0
3746
  { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
3747
  // Convert__Reg1_0__Reg1_2__Reg1_4__Reg1_5__ImmUnsignedi81_6
3748
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addImmOperands, 7, CVT_Done },
3749
  // Convert__Reg1_0__Reg1_2__Reg1_4__Mem1285_5__ImmUnsignedi81_6
3750
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3751
  // Convert__Reg1_0__Reg1_2__Reg1_4__Mem2565_5__ImmUnsignedi81_6
3752
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3753
  // Convert__Reg1_0__Reg1_2__Reg1_4__Mem5125_5__ImmUnsignedi81_6
3754
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3755
  // Convert__Reg1_0__Reg1_2__Reg1_4__Mem645_5__ImmUnsignedi81_7
3756
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 8, CVT_Done },
3757
  // Convert__Reg1_0__Reg1_2__Reg1_4__Reg1_5__ImmUnsignedi81_7
3758
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addImmOperands, 8, CVT_Done },
3759
  // Convert__Reg1_4__Reg1_6__Reg1_3__Reg1_2__ImmUnsignedi81_0
3760
  { CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
3761
  // Convert__Reg1_0__Reg1_2__Reg1_4__Mem325_5__ImmUnsignedi81_7
3762
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 8, CVT_Done },
3763
  // Convert__Reg1_0__Reg1_1__Mem645_2__ImmUnsignedi81_3
3764
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3765
  // Convert__Reg1_3__Reg1_2__Mem645_1__ImmUnsignedi81_0
3766
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3767
  // Convert__Reg1_0__Reg1_2__Reg1_4__Mem645_5__ImmUnsignedi81_6
3768
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3769
  // Convert__Reg1_3__Reg1_5__Reg1_2__Mem645_1__ImmUnsignedi81_0
3770
  { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3771
  // Convert__Reg1_0__Reg1_1__Mem325_2__ImmUnsignedi81_3
3772
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3773
  // Convert__Reg1_3__Reg1_2__Mem325_1__ImmUnsignedi81_0
3774
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3775
  // Convert__Reg1_0__Reg1_2__Reg1_4__Mem325_5__ImmUnsignedi81_6
3776
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3777
  // Convert__Reg1_3__Reg1_5__Reg1_2__Mem325_1__ImmUnsignedi81_0
3778
  { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3779
  // Convert__Reg1_2__Reg1_1
3780
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Done },
3781
  // Convert__Mem2565_1__Reg1_0
3782
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
3783
  // Convert__Mem5125_1__Reg1_0
3784
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
3785
  // Convert__Mem2565_0__Reg1_1
3786
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_Done },
3787
  // Convert__Mem5125_0__Reg1_1
3788
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_Done },
3789
  // Convert__Mem1285_1__Reg1_3__Reg1_0
3790
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_Done },
3791
  // Convert__Mem2565_1__Reg1_3__Reg1_0
3792
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_Done },
3793
  // Convert__Mem5125_1__Reg1_3__Reg1_0
3794
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_Done },
3795
  // Convert__Mem1285_0__Reg1_2__Reg1_4
3796
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_Done },
3797
  // Convert__Mem2565_0__Reg1_2__Reg1_4
3798
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_Done },
3799
  // Convert__Mem5125_0__Reg1_2__Reg1_4
3800
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_Done },
3801
  // Convert__Reg1_2__Mem325_0
3802
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3803
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Mem325_0
3804
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addMemOperands, 1, CVT_Done },
3805
  // Convert__Reg1_2__Reg1_4__Mem325_0
3806
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 1, CVT_Done },
3807
  // Convert__Reg1_0__Reg1_1__AVX512RC1_2
3808
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addAVX512RCOperands, 3, CVT_Done },
3809
  // Convert__Reg1_2__Reg1_1__AVX512RC1_0
3810
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addAVX512RCOperands, 1, CVT_Done },
3811
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem5125_4
3812
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_Done },
3813
  // Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem5125_0
3814
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3815
  // Convert__Reg1_0__Reg1_2__Mem5125_5
3816
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_Done },
3817
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__AVX512RC1_5
3818
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addAVX512RCOperands, 6, CVT_Done },
3819
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__AVX512RC1_0
3820
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addAVX512RCOperands, 1, CVT_Done },
3821
  // Convert__Reg1_1__Reg1_3__Mem5125_0
3822
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
3823
  // Convert__Reg1_0__Reg1_2__Reg1_5__AVX512RC1_6
3824
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addAVX512RCOperands, 7, CVT_Done },
3825
  // Convert__Reg1_2__Reg1_4__Reg1_1__AVX512RC1_0
3826
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addAVX512RCOperands, 1, CVT_Done },
3827
  // Convert__Reg1_2__Mem645_0
3828
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3829
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Mem645_0
3830
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addMemOperands, 1, CVT_Done },
3831
  // Convert__Reg1_2__Reg1_4__Mem645_0
3832
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 1, CVT_Done },
3833
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1
3834
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_Done },
3835
  // Convert__Reg1_2__Reg1_4__Reg1_1
3836
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_Done },
3837
  // Convert__Mem1285_2__Reg1_1__ImmUnsignedi81_0
3838
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3839
  // Convert__Mem2565_2__Reg1_1__ImmUnsignedi81_0
3840
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3841
  // Convert__Mem1285_0__Reg1_1__ImmUnsignedi81_2
3842
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3843
  // Convert__Mem2565_0__Reg1_1__ImmUnsignedi81_2
3844
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3845
  // Convert__Reg1_0__Reg1_1__ImmUnsignedi81_3
3846
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_Done },
3847
  // Convert__Reg1_3__Reg1_2__ImmUnsignedi81_0
3848
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
3849
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__ImmUnsignedi81_5
3850
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_Done },
3851
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Reg1_1__ImmUnsignedi81_0
3852
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3853
  // Convert__Mem645_2__Reg1_4__Reg1_1__ImmUnsignedi81_0
3854
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3855
  // Convert__Mem1285_2__Reg1_4__Reg1_1__ImmUnsignedi81_0
3856
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3857
  // Convert__Mem2565_2__Reg1_4__Reg1_1__ImmUnsignedi81_0
3858
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3859
  // Convert__Mem1285_0__Reg1_2__Reg1_4__ImmUnsignedi81_5
3860
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_Done },
3861
  // Convert__Mem2565_0__Reg1_2__Reg1_4__ImmUnsignedi81_5
3862
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_Done },
3863
  // Convert__Mem645_0__Reg1_2__Reg1_4__ImmUnsignedi81_5
3864
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_Done },
3865
  // Convert__Reg1_0__Reg1_2__Reg1_5__ImmUnsignedi81_6
3866
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addImmOperands, 7, CVT_Done },
3867
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__ImmUnsignedi81_6
3868
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addImmOperands, 7, CVT_Done },
3869
  // Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__ImmUnsignedi81_0
3870
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
3871
  // Convert__Reg1_2__Reg1_4__Reg1_1__ImmUnsignedi81_0
3872
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3873
  // Convert__Reg1_0__Reg1_2__Reg1_5__ImmUnsignedi81_7
3874
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addImmOperands, 8, CVT_Done },
3875
  // Convert__Reg1_3__Reg1_5__Reg1_2__ImmUnsignedi81_0
3876
  { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
3877
  // Convert__Reg1_0__Reg1_1__Reg1_3__AVX512RC1_2
3878
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addAVX512RCOperands, 3, CVT_Done },
3879
  // Convert__Reg1_3__Reg1_2__Reg1_0__AVX512RC1_1
3880
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addAVX512RCOperands, 2, CVT_Done },
3881
  // Convert__Reg1_3__Reg1_2__Reg1_1
3882
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Done },
3883
  // Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Reg1_1
3884
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Done },
3885
  // Convert__Reg1_3__Reg1_5__Reg1_2__Reg1_1
3886
  { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Done },
3887
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmUnsignedi81_3
3888
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
3889
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem1285_2__ImmUnsignedi81_3
3890
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3891
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem2565_2__ImmUnsignedi81_3
3892
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3893
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem5125_2__ImmUnsignedi81_3
3894
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3895
  // Convert__Reg1_3__Tie0_1_1__Reg1_2__Reg1_1__ImmUnsignedi81_0
3896
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
3897
  // Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem1285_1__ImmUnsignedi81_0
3898
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3899
  // Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem2565_1__ImmUnsignedi81_0
3900
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3901
  // Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem5125_1__ImmUnsignedi81_0
3902
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3903
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem645_2__ImmUnsignedi81_4
3904
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 5, CVT_Done },
3905
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmUnsignedi81_4
3906
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 5, CVT_Done },
3907
  // Convert__Reg1_4__Tie0_1_1__Reg1_3__Reg1_2__ImmUnsignedi81_0
3908
  { CVT_95_Reg, 5, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
3909
  // Convert__Reg1_4__Tie0_1_1__Reg1_3__Mem645_1__ImmUnsignedi81_0
3910
  { CVT_95_Reg, 5, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3911
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Reg1_6__ImmUnsignedi81_7
3912
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addImmOperands, 8, CVT_Done },
3913
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem1285_6__ImmUnsignedi81_7
3914
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
3915
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem2565_6__ImmUnsignedi81_7
3916
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
3917
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem5125_6__ImmUnsignedi81_7
3918
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
3919
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5__ImmUnsignedi81_7
3920
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addImmOperands, 8, CVT_Done },
3921
  // Convert__Reg1_4__Tie0_1_1__Reg1_6__Reg1_3__Reg1_2__ImmUnsignedi81_0
3922
  { CVT_95_Reg, 5, CVT_Tied, Tie0_1_1, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
3923
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem645_6__ImmUnsignedi81_8
3924
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 9, CVT_Done },
3925
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Reg1_6__ImmUnsignedi81_8
3926
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addImmOperands, 9, CVT_Done },
3927
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem325_2__ImmUnsignedi81_4
3928
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 5, CVT_Done },
3929
  // Convert__Reg1_4__Tie0_1_1__Reg1_3__Mem325_1__ImmUnsignedi81_0
3930
  { CVT_95_Reg, 5, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3931
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem325_6__ImmUnsignedi81_8
3932
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 9, CVT_Done },
3933
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem645_2__ImmUnsignedi81_3
3934
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3935
  // Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem645_1__ImmUnsignedi81_0
3936
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3937
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem645_5__ImmUnsignedi81_6
3938
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3939
  // Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem645_1__ImmUnsignedi81_0
3940
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3941
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem645_6__ImmUnsignedi81_7
3942
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
3943
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem325_2__ImmUnsignedi81_3
3944
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3945
  // Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem325_1__ImmUnsignedi81_0
3946
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3947
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem325_5__ImmUnsignedi81_6
3948
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
3949
  // Convert__Reg1_3__Tie0_1_1__Reg1_5__Reg1_2__Mem325_1__ImmUnsignedi81_0
3950
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 6, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
3951
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem325_6__ImmUnsignedi81_7
3952
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
3953
  // Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0
3954
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
3955
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2
3956
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
3957
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem2565_2
3958
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3959
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem5125_2
3960
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3961
  // Convert__Reg1_2__Tie0_1_1__Reg1_1__Mem2565_0
3962
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3963
  // Convert__Reg1_2__Tie0_1_1__Reg1_1__Mem5125_0
3964
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3965
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem645_2
3966
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3967
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__AVX512RC1_3
3968
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addAVX512RCOperands, 4, CVT_Done },
3969
  // Convert__Reg1_3__Tie0_1_1__Reg1_2__Reg1_1__AVX512RC1_0
3970
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addAVX512RCOperands, 1, CVT_Done },
3971
  // Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem645_0
3972
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3973
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Reg1_6
3974
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_Done },
3975
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem2565_6
3976
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3977
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem5125_6
3978
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3979
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem645_6
3980
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3981
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Reg1_6__AVX512RC1_7
3982
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addAVX512RCOperands, 8, CVT_Done },
3983
  // Convert__Reg1_0__Tie0_1_1__Reg1_1__Mem325_2
3984
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_Done },
3985
  // Convert__Reg1_3__Tie0_1_1__Reg1_2__Mem325_0
3986
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
3987
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_5__Mem325_6
3988
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_Done },
3989
  // Convert__Reg1_2__Tie0_1_1__Reg1_1__Mem645_0
3990
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3991
  // Convert__Reg1_2__Tie0_1_1__Reg1_1__Mem325_0
3992
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3993
  // Convert__Reg1_0__Reg1_1__Reg1_2__Mem1285_3
3994
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemOperands, 4, CVT_Done },
3995
  // Convert__Reg1_0__Reg1_1__Reg1_2__Mem2565_3
3996
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemOperands, 4, CVT_Done },
3997
  // Convert__Reg1_3__Reg1_2__Reg1_1__Mem1285_0
3998
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
3999
  // Convert__Reg1_3__Reg1_2__Reg1_1__Mem2565_0
4000
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
4001
  // Convert__Reg1_0__Reg1_1__Reg1_2__Mem645_3
4002
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemOperands, 4, CVT_Done },
4003
  // Convert__Reg1_0__Reg1_1__Mem645_2__Reg1_3
4004
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_Reg, 4, CVT_Done },
4005
  // Convert__Reg1_3__Reg1_2__Mem645_1__Reg1_0
4006
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
4007
  // Convert__Reg1_3__Reg1_2__Reg1_1__Mem645_0
4008
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
4009
  // Convert__Reg1_0__Reg1_1__Reg1_2__Mem325_3
4010
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemOperands, 4, CVT_Done },
4011
  // Convert__Reg1_0__Reg1_1__Mem325_2__Reg1_3
4012
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_Reg, 4, CVT_Done },
4013
  // Convert__Reg1_3__Reg1_2__Mem325_1__Reg1_0
4014
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
4015
  // Convert__Reg1_3__Reg1_2__Reg1_1__Mem325_0
4016
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
4017
  // Convert__Reg1_0__Mem2565_1__ImmUnsignedi81_2
4018
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
4019
  // Convert__Reg1_0__Mem5125_1__ImmUnsignedi81_2
4020
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
4021
  // Convert__Reg1_0__Mem645_1__ImmUnsignedi81_3
4022
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
4023
  // Convert__Reg1_0__Reg1_2__Reg1_4__ImmUnsignedi81_5
4024
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_Done },
4025
  // Convert__Reg1_0__Reg1_2__Mem1285_4__ImmUnsignedi81_5
4026
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
4027
  // Convert__Reg1_0__Reg1_2__Mem2565_4__ImmUnsignedi81_5
4028
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
4029
  // Convert__Reg1_0__Reg1_2__Mem5125_4__ImmUnsignedi81_5
4030
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
4031
  // Convert__Reg1_0__Reg1_2__Mem645_4__ImmUnsignedi81_6
4032
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 7, CVT_Done },
4033
  // Convert__Reg1_3__Mem645_1__ImmUnsignedi81_0
4034
  { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4035
  // Convert__Reg1_3__Reg1_5__Mem645_1__ImmUnsignedi81_0
4036
  { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4037
  // Convert__Reg1_2__Reg1_4__Mem1285_1__ImmUnsignedi81_0
4038
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4039
  // Convert__Reg1_2__Mem2565_1__ImmUnsignedi81_0
4040
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4041
  // Convert__Reg1_2__Reg1_4__Mem2565_1__ImmUnsignedi81_0
4042
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4043
  // Convert__Reg1_2__Mem5125_1__ImmUnsignedi81_0
4044
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4045
  // Convert__Reg1_2__Reg1_4__Mem5125_1__ImmUnsignedi81_0
4046
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4047
  // Convert__Reg1_0__Mem325_1__ImmUnsignedi81_3
4048
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
4049
  // Convert__Reg1_0__Reg1_2__Mem325_4__ImmUnsignedi81_6
4050
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 7, CVT_Done },
4051
  // Convert__Reg1_3__Mem325_1__ImmUnsignedi81_0
4052
  { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4053
  // Convert__Reg1_3__Reg1_5__Mem325_1__ImmUnsignedi81_0
4054
  { CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4055
  // Convert__Reg1_0__Reg1_2__Mem645_4__ImmUnsignedi81_5
4056
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
4057
  // Convert__Reg1_2__Reg1_4__Mem645_1__ImmUnsignedi81_0
4058
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4059
  // Convert__Reg1_0__Reg1_2__Mem325_4__ImmUnsignedi81_5
4060
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
4061
  // Convert__Reg1_2__Reg1_4__Mem325_1__ImmUnsignedi81_0
4062
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4063
  // Convert__Reg1_2__Reg1_0__Tie0_1_1__Mem128_RC1285_1__Tie1_1_1
4064
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Tied, Tie1_1_1, CVT_Done },
4065
  // Convert__Reg1_0__Reg1_2__Tie0_1_1__Mem128_RC1285_1__Tie1_3_3
4066
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Tied, Tie1_3_3, CVT_Done },
4067
  // Convert__Reg1_2__Reg1_0__Tie0_1_1__Mem256_RC1285_1__Tie1_1_1
4068
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Tied, Tie1_1_1, CVT_Done },
4069
  // Convert__Reg1_0__Reg1_2__Tie0_1_1__Mem256_RC1285_1__Tie1_3_3
4070
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Tied, Tie1_3_3, CVT_Done },
4071
  // Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem128_RC128X5_4
4072
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_3_3, CVT_95_addMemOperands, 5, CVT_Done },
4073
  // Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem256_RC128X5_4
4074
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_3_3, CVT_95_addMemOperands, 5, CVT_Done },
4075
  // Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem512_RC256X5_4
4076
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_3_3, CVT_95_addMemOperands, 5, CVT_Done },
4077
  // Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem128_RC128X5_0
4078
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_4_4, CVT_95_addMemOperands, 1, CVT_Done },
4079
  // Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem256_RC128X5_0
4080
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_4_4, CVT_95_addMemOperands, 1, CVT_Done },
4081
  // Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem512_RC256X5_0
4082
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_4_4, CVT_95_addMemOperands, 1, CVT_Done },
4083
  // Convert__Reg1_2__Reg1_0__Tie0_1_1__Mem256_RC2565_1__Tie1_1_1
4084
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Tied, Tie1_1_1, CVT_Done },
4085
  // Convert__Reg1_0__Reg1_2__Tie0_1_1__Mem256_RC2565_1__Tie1_3_3
4086
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Tied, Tie1_3_3, CVT_Done },
4087
  // Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem256_RC256X5_4
4088
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_3_3, CVT_95_addMemOperands, 5, CVT_Done },
4089
  // Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem512_RC5125_4
4090
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_3_3, CVT_95_addMemOperands, 5, CVT_Done },
4091
  // Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem256_RC256X5_0
4092
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_4_4, CVT_95_addMemOperands, 1, CVT_Done },
4093
  // Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem512_RC5125_0
4094
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_4_4, CVT_95_addMemOperands, 1, CVT_Done },
4095
  // Convert__Reg1_1__Mem512_RC256X5_3
4096
  { CVT_95_Reg, 2, CVT_95_addMemOperands, 4, CVT_Done },
4097
  // Convert__Reg1_2__Mem512_RC256X5_0
4098
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
4099
  // Convert__Reg1_1__Mem512_RC5125_3
4100
  { CVT_95_Reg, 2, CVT_95_addMemOperands, 4, CVT_Done },
4101
  // Convert__Reg1_2__Mem512_RC5125_0
4102
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
4103
  // Convert__Reg1_1__Mem256_RC5125_3
4104
  { CVT_95_Reg, 2, CVT_95_addMemOperands, 4, CVT_Done },
4105
  // Convert__Reg1_2__Mem256_RC5125_0
4106
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Done },
4107
  // Convert__Reg1_2__Reg1_0__Tie0_1_1__Mem128_RC2565_1__Tie1_1_1
4108
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Tied, Tie1_1_1, CVT_Done },
4109
  // Convert__Reg1_0__Reg1_2__Tie0_1_1__Mem128_RC2565_1__Tie1_3_3
4110
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Tied, Tie1_3_3, CVT_Done },
4111
  // Convert__Reg1_2__Reg1_0__Tie0_1_1__Mem64_RC1285_1__Tie1_1_1
4112
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Tied, Tie1_1_1, CVT_Done },
4113
  // Convert__Reg1_0__Reg1_2__Tie0_1_1__Mem64_RC1285_1__Tie1_3_3
4114
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Tied, Tie1_3_3, CVT_Done },
4115
  // Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem128_RC256X5_4
4116
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_3_3, CVT_95_addMemOperands, 5, CVT_Done },
4117
  // Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem64_RC128X5_4
4118
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_3_3, CVT_95_addMemOperands, 5, CVT_Done },
4119
  // Convert__Reg1_0__Reg1_2__Tie0_1_1__Tie1_3_3__Mem256_RC5125_4
4120
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_3_3, CVT_95_addMemOperands, 5, CVT_Done },
4121
  // Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem128_RC256X5_0
4122
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_4_4, CVT_95_addMemOperands, 1, CVT_Done },
4123
  // Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem256_RC5125_0
4124
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_4_4, CVT_95_addMemOperands, 1, CVT_Done },
4125
  // Convert__Reg1_1__Reg1_3__Tie0_1_1__Tie1_4_4__Mem64_RC128X5_0
4126
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_4_4, CVT_95_addMemOperands, 1, CVT_Done },
4127
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem1285_4__ImmUnsignedi81_5
4128
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
4129
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem2565_4__ImmUnsignedi81_5
4130
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
4131
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem5125_4__ImmUnsignedi81_5
4132
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
4133
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Mem1285_1__ImmUnsignedi81_0
4134
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4135
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Mem2565_1__ImmUnsignedi81_0
4136
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4137
  // Convert__Reg1_2__Tie0_1_1__Reg1_4__Mem5125_1__ImmUnsignedi81_0
4138
  { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4139
  // Convert__Reg1_0__Reg1_2__Mem1285_5__ImmUnsignedi81_6
4140
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
4141
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem645_4__ImmUnsignedi81_6
4142
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 7, CVT_Done },
4143
  // Convert__Reg1_0__Reg1_2__Mem2565_5__ImmUnsignedi81_6
4144
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
4145
  // Convert__Reg1_0__Reg1_2__Mem5125_5__ImmUnsignedi81_6
4146
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
4147
  // Convert__Reg1_3__Tie0_1_1__Reg1_5__Mem645_1__ImmUnsignedi81_0
4148
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 6, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4149
  // Convert__Reg1_0__Reg1_2__Mem645_5__ImmUnsignedi81_7
4150
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 8, CVT_Done },
4151
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem325_4__ImmUnsignedi81_6
4152
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_95_addImmOperands, 7, CVT_Done },
4153
  // Convert__Reg1_3__Tie0_1_1__Reg1_5__Mem325_1__ImmUnsignedi81_0
4154
  { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 6, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4155
  // Convert__Reg1_0__Reg1_2__Mem325_5__ImmUnsignedi81_7
4156
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 8, CVT_Done },
4157
  // Convert__Reg1_0__Reg1_2__Reg1_5__Mem645_6__ImmUnsignedi81_7
4158
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
4159
  // Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6__ImmUnsignedi81_8
4160
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addImmOperands, 9, CVT_Done },
4161
  // Convert__Reg1_0__Reg1_2__Reg1_5__Mem325_6__ImmUnsignedi81_7
4162
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 8, CVT_Done },
4163
  // Convert__Reg1_0__Reg1_1__Mem85_2__ImmUnsignedi81_4
4164
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 5, CVT_Done },
4165
  // Convert__Reg1_4__Reg1_3__Mem85_1__ImmUnsignedi81_0
4166
  { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4167
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Mem85_5__ImmUnsignedi81_7
4168
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addMemOperands, 6, CVT_95_addImmOperands, 8, CVT_Done },
4169
  // Convert__Reg1_4__Tie0_1_1__Reg1_6__Reg1_3__Mem85_1__ImmUnsignedi81_0
4170
  { CVT_95_Reg, 5, CVT_Tied, Tie0_1_1, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4171
  // Convert__Reg1_0__Reg1_2__Reg1_5__Mem85_6__ImmUnsignedi81_8
4172
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addMemOperands, 7, CVT_95_addImmOperands, 9, CVT_Done },
4173
  // Convert__Reg1_4__Reg1_6__Reg1_3__Mem85_1__ImmUnsignedi81_0
4174
  { CVT_95_Reg, 5, CVT_95_Reg, 7, CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4175
  // Convert__Mem1285_2__Reg1_1__Reg1_0
4176
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
4177
  // Convert__Mem2565_2__Reg1_1__Reg1_0
4178
  { CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
4179
  // Convert__Mem1285_0__Reg1_1__Reg1_2
4180
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
4181
  // Convert__Mem2565_0__Reg1_1__Reg1_2
4182
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
4183
  // Convert__Reg1_0__Reg1_2__Reg1_4
4184
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_Done },
4185
  // Convert__Mem645_1__Reg1_3__Reg1_0
4186
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_Done },
4187
  // Convert__Mem645_0__Reg1_2__Reg1_4
4188
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_Done },
4189
  // Convert__Reg1_2__Tie0_3_3__Reg1_4__Reg1_1__Reg1_0
4190
  { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
4191
  // Convert__Mem325_1__Reg1_3__Reg1_0
4192
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_Done },
4193
  // Convert__Mem325_0__Reg1_2__Reg1_4
4194
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_Done },
4195
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem85_4
4196
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_Done },
4197
  // Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem85_0
4198
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
4199
  // Convert__Reg1_0__Reg1_2__Mem85_5
4200
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_Done },
4201
  // Convert__Reg1_1__Reg1_3__Mem85_0
4202
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
4203
  // Convert__Reg1_0__Tie0_1_1__Reg1_2__Mem165_4
4204
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addMemOperands, 5, CVT_Done },
4205
  // Convert__Reg1_1__Tie0_1_1__Reg1_3__Mem165_0
4206
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
4207
  // Convert__Reg1_0__Reg1_2__Mem165_5
4208
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMemOperands, 6, CVT_Done },
4209
  // Convert__Reg1_1__Reg1_3__Mem165_0
4210
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addMemOperands, 1, CVT_Done },
4211
  // Convert__Reg1_2__Reg1_1__Reg1_0__imm_95_17
4212
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_imm_95_17, 0, CVT_Done },
4213
  // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_17
4214
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_17, 0, CVT_Done },
4215
  // Convert__Reg1_0__Reg1_1__Mem1285_2__imm_95_17
4216
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_17, 0, CVT_Done },
4217
  // Convert__Reg1_0__Reg1_1__Mem2565_2__imm_95_17
4218
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_17, 0, CVT_Done },
4219
  // Convert__Reg1_0__Reg1_1__Mem5125_2__imm_95_17
4220
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_17, 0, CVT_Done },
4221
  // Convert__Reg1_2__Reg1_1__Mem1285_0__imm_95_17
4222
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_17, 0, CVT_Done },
4223
  // Convert__Reg1_2__Reg1_1__Mem2565_0__imm_95_17
4224
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_17, 0, CVT_Done },
4225
  // Convert__Reg1_2__Reg1_1__Mem5125_0__imm_95_17
4226
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_17, 0, CVT_Done },
4227
  // Convert__Reg1_2__Reg1_1__Reg1_0__imm_95_1
4228
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_Done },
4229
  // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_1
4230
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_1, 0, CVT_Done },
4231
  // Convert__Reg1_0__Reg1_1__Mem1285_2__imm_95_1
4232
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_1, 0, CVT_Done },
4233
  // Convert__Reg1_0__Reg1_1__Mem2565_2__imm_95_1
4234
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_1, 0, CVT_Done },
4235
  // Convert__Reg1_0__Reg1_1__Mem5125_2__imm_95_1
4236
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_1, 0, CVT_Done },
4237
  // Convert__Reg1_2__Reg1_1__Mem1285_0__imm_95_1
4238
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_1, 0, CVT_Done },
4239
  // Convert__Reg1_2__Reg1_1__Mem2565_0__imm_95_1
4240
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_1, 0, CVT_Done },
4241
  // Convert__Reg1_2__Reg1_1__Mem5125_0__imm_95_1
4242
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_1, 0, CVT_Done },
4243
  // Convert__Reg1_2__Reg1_1__Reg1_0__imm_95_16
4244
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_imm_95_16, 0, CVT_Done },
4245
  // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16
4246
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_16, 0, CVT_Done },
4247
  // Convert__Reg1_0__Reg1_1__Mem1285_2__imm_95_16
4248
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_16, 0, CVT_Done },
4249
  // Convert__Reg1_0__Reg1_1__Mem2565_2__imm_95_16
4250
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_16, 0, CVT_Done },
4251
  // Convert__Reg1_0__Reg1_1__Mem5125_2__imm_95_16
4252
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_16, 0, CVT_Done },
4253
  // Convert__Reg1_2__Reg1_1__Mem1285_0__imm_95_16
4254
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_16, 0, CVT_Done },
4255
  // Convert__Reg1_2__Reg1_1__Mem2565_0__imm_95_16
4256
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_16, 0, CVT_Done },
4257
  // Convert__Reg1_2__Reg1_1__Mem5125_0__imm_95_16
4258
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_16, 0, CVT_Done },
4259
  // Convert__Reg1_2__Reg1_1__Reg1_0__imm_95_0
4260
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done },
4261
  // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0
4262
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
4263
  // Convert__Reg1_0__Reg1_1__Mem1285_2__imm_95_0
4264
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_0, 0, CVT_Done },
4265
  // Convert__Reg1_0__Reg1_1__Mem2565_2__imm_95_0
4266
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_0, 0, CVT_Done },
4267
  // Convert__Reg1_0__Reg1_1__Mem5125_2__imm_95_0
4268
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_imm_95_0, 0, CVT_Done },
4269
  // Convert__Reg1_2__Reg1_1__Mem1285_0__imm_95_0
4270
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_0, 0, CVT_Done },
4271
  // Convert__Reg1_2__Reg1_1__Mem2565_0__imm_95_0
4272
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_0, 0, CVT_Done },
4273
  // Convert__Reg1_2__Reg1_1__Mem5125_0__imm_95_0
4274
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_imm_95_0, 0, CVT_Done },
4275
  // Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmUnsignedi81_4
4276
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_Done },
4277
  // Convert__Reg1_0__Reg1_1__Reg1_2__Mem1285_3__ImmUnsignedi81_4
4278
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
4279
  // Convert__Reg1_0__Reg1_1__Mem1285_2__Reg1_3__ImmUnsignedi81_4
4280
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_Done },
4281
  // Convert__Reg1_0__Reg1_1__Reg1_2__Mem2565_3__ImmUnsignedi81_4
4282
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
4283
  // Convert__Reg1_0__Reg1_1__Mem2565_2__Reg1_3__ImmUnsignedi81_4
4284
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_Done },
4285
  // Convert__Reg1_4__Reg1_3__Reg1_2__Reg1_1__ImmUnsignedi81_0
4286
  { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
4287
  // Convert__Reg1_4__Reg1_3__Mem1285_2__Reg1_1__ImmUnsignedi81_0
4288
  { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
4289
  // Convert__Reg1_4__Reg1_3__Mem2565_2__Reg1_1__ImmUnsignedi81_0
4290
  { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addMemOperands, 3, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
4291
  // Convert__Reg1_4__Reg1_3__Reg1_2__Mem1285_1__ImmUnsignedi81_0
4292
  { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4293
  // Convert__Reg1_4__Reg1_3__Reg1_2__Mem2565_1__ImmUnsignedi81_0
4294
  { CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4295
  // Convert__Reg1_0__Reg1_1__GR32orGR641_2__ImmUnsignedi81_3
4296
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addGR32orGR64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
4297
  // Convert__Reg1_0__Reg1_1__Mem85_2__ImmUnsignedi81_3
4298
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
4299
  // Convert__Reg1_3__Reg1_2__GR32orGR641_1__ImmUnsignedi81_0
4300
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addGR32orGR64Operands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4301
  // Convert__Reg1_3__Reg1_2__Mem85_1__ImmUnsignedi81_0
4302
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4303
  // Convert__Reg1_0__Reg1_1__Mem165_2__ImmUnsignedi81_3
4304
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMemOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
4305
  // Convert__Reg1_3__Reg1_2__Mem165_1__ImmUnsignedi81_0
4306
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
4307
  // Convert__Mem165_1__Reg1_3__Reg1_0
4308
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_Done },
4309
  // Convert__Mem165_0__Reg1_2__Reg1_4
4310
  { CVT_95_addMemOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_Done },
4311
  // Convert__Reg1_2__Mem1285_1__Reg1_0
4312
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
4313
  // Convert__Reg1_0__Mem1285_1__Reg1_2
4314
  { CVT_95_Reg, 1, CVT_95_addMemOperands, 2, CVT_95_Reg, 3, CVT_Done },
4315
  // Convert__Reg1_3__Mem128_RC128X5_1__Tie0_4_4__Reg1_0
4316
  { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 1, CVT_Done },
4317
  // Convert__Reg1_3__Mem256_RC256X5_1__Tie0_4_4__Reg1_0
4318
  { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 1, CVT_Done },
4319
  // Convert__Reg1_3__Mem512_RC5125_1__Tie0_4_4__Reg1_0
4320
  { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 1, CVT_Done },
4321
  // Convert__Reg1_2__Mem128_RC128X5_0__Tie0_3_3__Reg1_4
4322
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4323
  // Convert__Reg1_2__Mem256_RC256X5_0__Tie0_3_3__Reg1_4
4324
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4325
  // Convert__Reg1_2__Mem512_RC5125_0__Tie0_3_3__Reg1_4
4326
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4327
  // Convert__Reg1_3__Mem256_RC128X5_1__Tie0_4_4__Reg1_0
4328
  { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 1, CVT_Done },
4329
  // Convert__Reg1_3__Mem512_RC256X5_1__Tie0_4_4__Reg1_0
4330
  { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 1, CVT_Done },
4331
  // Convert__Reg1_2__Mem256_RC128X5_0__Tie0_3_3__Reg1_4
4332
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4333
  // Convert__Reg1_2__Mem512_RC256X5_0__Tie0_3_3__Reg1_4
4334
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4335
  // Convert__Reg1_3__Mem128_RC256X5_1__Tie0_4_4__Reg1_0
4336
  { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 1, CVT_Done },
4337
  // Convert__Reg1_3__Mem64_RC128X5_1__Tie0_4_4__Reg1_0
4338
  { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 1, CVT_Done },
4339
  // Convert__Reg1_3__Mem256_RC5125_1__Tie0_4_4__Reg1_0
4340
  { CVT_95_Reg, 4, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 1, CVT_Done },
4341
  // Convert__Reg1_2__Mem128_RC256X5_0__Tie0_3_3__Reg1_4
4342
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4343
  // Convert__Reg1_2__Mem256_RC5125_0__Tie0_3_3__Reg1_4
4344
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4345
  // Convert__Reg1_2__Mem64_RC128X5_0__Tie0_3_3__Reg1_4
4346
  { CVT_95_Reg, 3, CVT_95_addMemOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4347
  // Convert__Reg1_0__Reg1_1__Tie0_1_1__Tie1_2_2
4348
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_2_2, CVT_Done },
4349
  // Convert__Reg1_1__Reg1_0__Tie0_2_2__Tie1_1_1
4350
  { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Tied, Tie0_2_2, CVT_Tied, Tie1_1_1, CVT_Done },
4351
  // Convert__AbsMem161_0
4352
  { CVT_95_addAbsMemOperands, 1, CVT_Done },
4353
  // Convert__Reg1_1__Tie0_2_2
4354
  { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_Done },
4355
  // Convert__regEAX__regEAX__Tie0_1_1__Tie1_1_1
4356
  { CVT_regEAX, 0, CVT_regEAX, 0, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_Done },
4357
};
4358
4359
void X86AsmParser::
4360
convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
4361
138k
                const OperandVector &Operands) {
4362
138k
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
4363
138k
  const uint8_t *Converter = ConversionTable[Kind];
4364
138k
  unsigned OpIdx;
4365
138k
  Inst.setOpcode(Opcode);
4366
510k
  for (const uint8_t *p = Converter; *p; 
p+= 2371k
) {
4367
371k
    OpIdx = *(p + 1);
4368
371k
    switch (*p) {
4369
371k
    
default: 0
llvm_unreachable0
("invalid conversion entry!");
4370
371k
    case CVT_Reg:
4371
0
      static_cast<X86Operand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
4372
0
      break;
4373
371k
    case CVT_Tied: {
4374
46.3k
      assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
4375
46.3k
                          std::begin(TiedAsmOperandTable)) &&
4376
46.3k
             "Tied operand not found");
4377
46.3k
      unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];
4378
46.3k
      if (TiedResOpnd != (uint8_t) -1)
4379
46.3k
        Inst.addOperand(Inst.getOperand(TiedResOpnd));
4380
46.3k
      break;
4381
371k
    }
4382
371k
    case CVT_imm_95_10:
4383
46
      Inst.addOperand(MCOperand::createImm(10));
4384
46
      break;
4385
371k
    case CVT_95_addImmOperands:
4386
22.2k
      static_cast<X86Operand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
4387
22.2k
      break;
4388
371k
    case CVT_regAX:
4389
15
      Inst.addOperand(MCOperand::createReg(X86::AX));
4390
15
      break;
4391
371k
    case CVT_regEAX:
4392
98
      Inst.addOperand(MCOperand::createReg(X86::EAX));
4393
98
      break;
4394
371k
    case CVT_regRAX:
4395
18
      Inst.addOperand(MCOperand::createReg(X86::RAX));
4396
18
      break;
4397
371k
    case CVT_95_Reg:
4398
214k
      static_cast<X86Operand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
4399
214k
      break;
4400
371k
    case CVT_95_addMemOperands:
4401
81.9k
      static_cast<X86Operand&>(*Operands[OpIdx]).addMemOperands(Inst, 5);
4402
81.9k
      break;
4403
371k
    case CVT_95_addAbsMemOperands:
4404
1.53k
      static_cast<X86Operand&>(*Operands[OpIdx]).addAbsMemOperands(Inst, 1);
4405
1.53k
      break;
4406
371k
    case CVT_95_addDstIdxOperands:
4407
738
      static_cast<X86Operand&>(*Operands[OpIdx]).addDstIdxOperands(Inst, 1);
4408
738
      break;
4409
371k
    case CVT_95_addSrcIdxOperands:
4410
651
      static_cast<X86Operand&>(*Operands[OpIdx]).addSrcIdxOperands(Inst, 2);
4411
651
      break;
4412
371k
    case CVT_95_addGR32orGR64Operands:
4413
291
      static_cast<X86Operand&>(*Operands[OpIdx]).addGR32orGR64Operands(Inst, 1);
4414
291
      break;
4415
371k
    case CVT_regST1:
4416
164
      Inst.addOperand(MCOperand::createReg(X86::ST1));
4417
164
      break;
4418
371k
    case CVT_regST0:
4419
12
      Inst.addOperand(MCOperand::createReg(X86::ST0));
4420
12
      break;
4421
371k
    case CVT_95_addMemOffsOperands:
4422
76
      static_cast<X86Operand&>(*Operands[OpIdx]).addMemOffsOperands(Inst, 2);
4423
76
      break;
4424
371k
    case CVT_imm_95_17:
4425
5
      Inst.addOperand(MCOperand::createImm(17));
4426
5
      break;
4427
371k
    case CVT_imm_95_1:
4428
4
      Inst.addOperand(MCOperand::createImm(1));
4429
4
      break;
4430
371k
    case CVT_imm_95_16:
4431
5
      Inst.addOperand(MCOperand::createImm(16));
4432
5
      break;
4433
371k
    case CVT_imm_95_0:
4434
4
      Inst.addOperand(MCOperand::createImm(0));
4435
4
      break;
4436
371k
    case CVT_95_addAVX512RCOperands:
4437
2.85k
      static_cast<X86Operand&>(*Operands[OpIdx]).addAVX512RCOperands(Inst, 1);
4438
2.85k
      break;
4439
371k
    }
4440
371k
  }
4441
138k
}
4442
4443
void X86AsmParser::
4444
convertToMapAndConstraints(unsigned Kind,
4445
436
                           const OperandVector &Operands) {
4446
436
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
4447
436
  unsigned NumMCOperands = 0;
4448
436
  const uint8_t *Converter = ConversionTable[Kind];
4449
1.18k
  for (const uint8_t *p = Converter; *p; 
p+= 2750
) {
4450
750
    switch (*p) {
4451
750
    
default: 0
llvm_unreachable0
("invalid conversion entry!");
4452
750
    case CVT_Reg:
4453
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4454
0
      Operands[*(p + 1)]->setConstraint("r");
4455
0
      ++NumMCOperands;
4456
0
      break;
4457
750
    case CVT_Tied:
4458
11
      ++NumMCOperands;
4459
11
      break;
4460
750
    case CVT_imm_95_10:
4461
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4462
0
      Operands[*(p + 1)]->setConstraint("");
4463
0
      ++NumMCOperands;
4464
0
      break;
4465
750
    case CVT_95_addImmOperands:
4466
113
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4467
113
      Operands[*(p + 1)]->setConstraint("m");
4468
113
      NumMCOperands += 1;
4469
113
      break;
4470
750
    case CVT_regAX:
4471
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4472
0
      Operands[*(p + 1)]->setConstraint("m");
4473
0
      ++NumMCOperands;
4474
0
      break;
4475
750
    case CVT_regEAX:
4476
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4477
0
      Operands[*(p + 1)]->setConstraint("m");
4478
0
      ++NumMCOperands;
4479
0
      break;
4480
750
    case CVT_regRAX:
4481
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4482
0
      Operands[*(p + 1)]->setConstraint("m");
4483
0
      ++NumMCOperands;
4484
0
      break;
4485
750
    case CVT_95_Reg:
4486
378
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4487
378
      Operands[*(p + 1)]->setConstraint("r");
4488
378
      NumMCOperands += 1;
4489
378
      break;
4490
750
    case CVT_95_addMemOperands:
4491
239
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4492
239
      Operands[*(p + 1)]->setConstraint("m");
4493
239
      NumMCOperands += 5;
4494
239
      break;
4495
750
    case CVT_95_addAbsMemOperands:
4496
8
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4497
8
      Operands[*(p + 1)]->setConstraint("m");
4498
8
      NumMCOperands += 1;
4499
8
      break;
4500
750
    case CVT_95_addDstIdxOperands:
4501
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4502
0
      Operands[*(p + 1)]->setConstraint("m");
4503
0
      NumMCOperands += 1;
4504
0
      break;
4505
750
    case CVT_95_addSrcIdxOperands:
4506
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4507
0
      Operands[*(p + 1)]->setConstraint("m");
4508
0
      NumMCOperands += 2;
4509
0
      break;
4510
750
    case CVT_95_addGR32orGR64Operands:
4511
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4512
0
      Operands[*(p + 1)]->setConstraint("m");
4513
0
      NumMCOperands += 1;
4514
0
      break;
4515
750
    case CVT_regST1:
4516
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4517
0
      Operands[*(p + 1)]->setConstraint("m");
4518
0
      ++NumMCOperands;
4519
0
      break;
4520
750
    case CVT_regST0:
4521
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4522
0
      Operands[*(p + 1)]->setConstraint("m");
4523
0
      ++NumMCOperands;
4524
0
      break;
4525
750
    case CVT_95_addMemOffsOperands:
4526
1
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4527
1
      Operands[*(p + 1)]->setConstraint("m");
4528
1
      NumMCOperands += 2;
4529
1
      break;
4530
750
    case CVT_imm_95_17:
4531
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4532
0
      Operands[*(p + 1)]->setConstraint("");
4533
0
      ++NumMCOperands;
4534
0
      break;
4535
750
    case CVT_imm_95_1:
4536
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4537
0
      Operands[*(p + 1)]->setConstraint("");
4538
0
      ++NumMCOperands;
4539
0
      break;
4540
750
    case CVT_imm_95_16:
4541
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4542
0
      Operands[*(p + 1)]->setConstraint("");
4543
0
      ++NumMCOperands;
4544
0
      break;
4545
750
    case CVT_imm_95_0:
4546
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4547
0
      Operands[*(p + 1)]->setConstraint("");
4548
0
      ++NumMCOperands;
4549
0
      break;
4550
750
    case CVT_95_addAVX512RCOperands:
4551
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4552
0
      Operands[*(p + 1)]->setConstraint("m");
4553
0
      NumMCOperands += 1;
4554
0
      break;
4555
750
    }
4556
750
  }
4557
436
}
4558
4559
namespace {
4560
4561
/// MatchClassKind - The kinds of classes which participate in
4562
/// instruction matching.
4563
enum MatchClassKind {
4564
  InvalidMatchClass = 0,
4565
  OptionalMatchClass = 1,
4566
  MCK__STAR_, // '*'
4567
  MCK_b, // 'b'
4568
  MCK_d, // 'd'
4569
  MCK_pd, // 'pd'
4570
  MCK_ps, // 'ps'
4571
  MCK_q, // 'q'
4572
  MCK_sd, // 'sd'
4573
  MCK_ss, // 'ss'
4574
  MCK_ub, // 'ub'
4575
  MCK_ud, // 'ud'
4576
  MCK_uq, // 'uq'
4577
  MCK_uw, // 'uw'
4578
  MCK_w, // 'w'
4579
  MCK__123_, // '{'
4580
  MCK__123_1to16_125_, // '{1to16}'
4581
  MCK__123_1to2_125_, // '{1to2}'
4582
  MCK__123_1to4_125_, // '{1to4}'
4583
  MCK__123_1to8_125_, // '{1to8}'
4584
  MCK__123_sae_125_, // '{sae}'
4585
  MCK__123_z_125_, // '{z}'
4586
  MCK__125_, // '}'
4587
  MCK_LAST_TOKEN = MCK__125_,
4588
  MCK_Reg69, // derived register class
4589
  MCK_Reg66, // derived register class
4590
  MCK_Reg64, // derived register class
4591
  MCK_Reg62, // derived register class
4592
  MCK_Reg35, // derived register class
4593
  MCK_Reg33, // derived register class
4594
  MCK_Reg31, // derived register class
4595
  MCK_AL, // register class 'AL'
4596
  MCK_AX, // register class 'AX'
4597
  MCK_CCR, // register class 'CCR'
4598
  MCK_CL, // register class 'CL'
4599
  MCK_CS, // register class 'CS'
4600
  MCK_DFCCR, // register class 'DFCCR'
4601
  MCK_DS, // register class 'DS'
4602
  MCK_DX, // register class 'DX'
4603
  MCK_EAX, // register class 'EAX'
4604
  MCK_EBX, // register class 'EBX'
4605
  MCK_ECX, // register class 'ECX'
4606
  MCK_EDX, // register class 'EDX'
4607
  MCK_ES, // register class 'ES'
4608
  MCK_FPCCR, // register class 'FPCCR'
4609
  MCK_FS, // register class 'FS'
4610
  MCK_GS, // register class 'GS'
4611
  MCK_RAX, // register class 'RAX'
4612
  MCK_RBX, // register class 'RBX'
4613
  MCK_RCX, // register class 'RCX'
4614
  MCK_RDX, // register class 'RDX'
4615
  MCK_SS, // register class 'SS'
4616
  MCK_ST0, // register class 'ST0'
4617
  MCK_XMM0, // register class 'XMM0'
4618
  MCK_Reg68, // derived register class
4619
  MCK_Reg67, // derived register class
4620
  MCK_Reg65, // derived register class
4621
  MCK_Reg63, // derived register class
4622
  MCK_Reg61, // derived register class
4623
  MCK_Reg59, // derived register class
4624
  MCK_Reg57, // derived register class
4625
  MCK_GR32_AD, // register class 'GR32_AD'
4626
  MCK_GR32_BPSP, // register class 'GR32_BPSP'
4627
  MCK_GR32_BSI, // register class 'GR32_BSI'
4628
  MCK_GR32_CB, // register class 'GR32_CB'
4629
  MCK_GR32_DC, // register class 'GR32_DC'
4630
  MCK_GR32_DIBP, // register class 'GR32_DIBP'
4631
  MCK_GR32_SIDI, // register class 'GR32_SIDI'
4632
  MCK_GR64_AD, // register class 'GR64_AD'
4633
  MCK_Reg39, // derived register class
4634
  MCK_GR32_TC, // register class 'GR32_TC'
4635
  MCK_Reg55, // derived register class
4636
  MCK_BNDR, // register class 'BNDR'
4637
  MCK_GR16_ABCD, // register class 'GR16_ABCD'
4638
  MCK_GR32_ABCD, // register class 'GR32_ABCD'
4639
  MCK_GR64_ABCD, // register class 'GR64_ABCD'
4640
  MCK_GR8_ABCD_H, // register class 'GR8_ABCD_H'
4641
  MCK_GR8_ABCD_L, // register class 'GR8_ABCD_L'
4642
  MCK_Reg47, // derived register class
4643
  MCK_Reg53, // derived register class
4644
  MCK_Reg50, // derived register class
4645
  MCK_SEGMENT_REG, // register class 'SEGMENT_REG'
4646
  MCK_Reg54, // derived register class
4647
  MCK_Reg51, // derived register class
4648
  MCK_GR32_NOREX_NOSP, // register class 'GR32_NOREX_NOSP'
4649
  MCK_GR64_NOREX_NOSP, // register class 'GR64_NOREX_NOSP'
4650
  MCK_RFP32, // register class 'RFP32,RFP64,RFP80'
4651
  MCK_VK16WM, // register class 'VK16WM,VK1WM,VK2WM,VK4WM,VK8WM,VK32WM,VK64WM'
4652
  MCK_Reg84, // derived register class
4653
  MCK_Reg81, // derived register class
4654
  MCK_Reg48, // derived register class
4655
  MCK_Reg42, // derived register class
4656
  MCK_GR16_NOREX, // register class 'GR16_NOREX'
4657
  MCK_GR32_NOREX, // register class 'GR32_NOREX'
4658
  MCK_GR64_TCW64, // register class 'GR64_TCW64'
4659
  MCK_GR8_NOREX, // register class 'GR8_NOREX'
4660
  MCK_RST, // register class 'RST'
4661
  MCK_VK1, // register class 'VK1,VK16,VK2,VK4,VK8,VK32,VK64'
4662
  MCK_VR128H, // register class 'VR128H'
4663
  MCK_VR128L, // register class 'VR128L'
4664
  MCK_VR256H, // register class 'VR256H'
4665
  MCK_VR256L, // register class 'VR256L'
4666
  MCK_VR64, // register class 'VR64'
4667
  MCK_Reg23, // derived register class
4668
  MCK_GR64_NOREX, // register class 'GR64_NOREX'
4669
  MCK_GR64_TC, // register class 'GR64_TC'
4670
  MCK_GRH8, // register class 'GRH8'
4671
  MCK_GR32_NOSP, // register class 'GR32_NOSP'
4672
  MCK_GR64_NOSP, // register class 'GR64_NOSP'
4673
  MCK_Reg82, // derived register class
4674
  MCK_Reg43, // derived register class
4675
  MCK_CONTROL_REG, // register class 'CONTROL_REG'
4676
  MCK_DEBUG_REG, // register class 'DEBUG_REG'
4677
  MCK_FR32, // register class 'FR32,FR64,VR128'
4678
  MCK_GR16, // register class 'GR16'
4679
  MCK_GR32, // register class 'GR32'
4680
  MCK_VR256, // register class 'VR256'
4681
  MCK_Reg20, // derived register class
4682
  MCK_GR64, // register class 'GR64'
4683
  MCK_GRH16, // register class 'GRH16'
4684
  MCK_LOW32_ADDR_ACCESS, // register class 'LOW32_ADDR_ACCESS'
4685
  MCK_LOW32_ADDR_ACCESS_RBP, // register class 'LOW32_ADDR_ACCESS_RBP'
4686
  MCK_GR8, // register class 'GR8'
4687
  MCK_FR32X, // register class 'FR32X,FR64X,VR128X'
4688
  MCK_VR256X, // register class 'VR256X'
4689
  MCK_VR512, // register class 'VR512'
4690
  MCK_LAST_REGISTER = MCK_VR512,
4691
  MCK_AVX512RC, // user defined class 'AVX512RCOperand'
4692
  MCK_ImmSExti64i8, // user defined class 'ImmSExti64i8AsmOperand'
4693
  MCK_ImmSExti16i8, // user defined class 'ImmSExti16i8AsmOperand'
4694
  MCK_ImmSExti32i8, // user defined class 'ImmSExti32i8AsmOperand'
4695
  MCK_ImmSExti64i32, // user defined class 'ImmSExti64i32AsmOperand'
4696
  MCK_Imm, // user defined class 'ImmAsmOperand'
4697
  MCK_ImmUnsignedi8, // user defined class 'ImmUnsignedi8AsmOperand'
4698
  MCK_GR32orGR64, // user defined class 'X86GR32orGR64AsmOperand'
4699
  MCK_AbsMem16, // user defined class 'X86AbsMem16AsmOperand'
4700
  MCK_DstIdx16, // user defined class 'X86DstIdx16Operand'
4701
  MCK_DstIdx32, // user defined class 'X86DstIdx32Operand'
4702
  MCK_DstIdx64, // user defined class 'X86DstIdx64Operand'
4703
  MCK_DstIdx8, // user defined class 'X86DstIdx8Operand'
4704
  MCK_MemOffs16_16, // user defined class 'X86MemOffs16_16AsmOperand'
4705
  MCK_MemOffs16_32, // user defined class 'X86MemOffs16_32AsmOperand'
4706
  MCK_MemOffs16_8, // user defined class 'X86MemOffs16_8AsmOperand'
4707
  MCK_MemOffs32_16, // user defined class 'X86MemOffs32_16AsmOperand'
4708
  MCK_MemOffs32_32, // user defined class 'X86MemOffs32_32AsmOperand'
4709
  MCK_MemOffs32_64, // user defined class 'X86MemOffs32_64AsmOperand'
4710
  MCK_MemOffs32_8, // user defined class 'X86MemOffs32_8AsmOperand'
4711
  MCK_MemOffs64_16, // user defined class 'X86MemOffs64_16AsmOperand'
4712
  MCK_MemOffs64_32, // user defined class 'X86MemOffs64_32AsmOperand'
4713
  MCK_MemOffs64_64, // user defined class 'X86MemOffs64_64AsmOperand'
4714
  MCK_MemOffs64_8, // user defined class 'X86MemOffs64_8AsmOperand'
4715
  MCK_SrcIdx16, // user defined class 'X86SrcIdx16Operand'
4716
  MCK_SrcIdx32, // user defined class 'X86SrcIdx32Operand'
4717
  MCK_SrcIdx64, // user defined class 'X86SrcIdx64Operand'
4718
  MCK_SrcIdx8, // user defined class 'X86SrcIdx8Operand'
4719
  MCK_AbsMem, // user defined class 'X86AbsMemAsmOperand'
4720
  MCK_Mem128, // user defined class 'X86Mem128AsmOperand'
4721
  MCK_Mem128_RC128, // user defined class 'X86Mem128_RC128Operand'
4722
  MCK_Mem128_RC128X, // user defined class 'X86Mem128_RC128XOperand'
4723
  MCK_Mem128_RC256, // user defined class 'X86Mem128_RC256Operand'
4724
  MCK_Mem128_RC256X, // user defined class 'X86Mem128_RC256XOperand'
4725
  MCK_Mem16, // user defined class 'X86Mem16AsmOperand'
4726
  MCK_Mem256, // user defined class 'X86Mem256AsmOperand'
4727
  MCK_Mem256_RC128, // user defined class 'X86Mem256_RC128Operand'
4728
  MCK_Mem256_RC128X, // user defined class 'X86Mem256_RC128XOperand'
4729
  MCK_Mem256_RC256, // user defined class 'X86Mem256_RC256Operand'
4730
  MCK_Mem256_RC256X, // user defined class 'X86Mem256_RC256XOperand'
4731
  MCK_Mem256_RC512, // user defined class 'X86Mem256_RC512Operand'
4732
  MCK_Mem32, // user defined class 'X86Mem32AsmOperand'
4733
  MCK_Mem512, // user defined class 'X86Mem512AsmOperand'
4734
  MCK_Mem512_RC256X, // user defined class 'X86Mem512_RC256XOperand'
4735
  MCK_Mem512_RC512, // user defined class 'X86Mem512_RC512Operand'
4736
  MCK_Mem64, // user defined class 'X86Mem64AsmOperand'
4737
  MCK_Mem64_RC128, // user defined class 'X86Mem64_RC128Operand'
4738
  MCK_Mem64_RC128X, // user defined class 'X86Mem64_RC128XOperand'
4739
  MCK_Mem80, // user defined class 'X86Mem80AsmOperand'
4740
  MCK_Mem8, // user defined class 'X86Mem8AsmOperand'
4741
  MCK_Mem, // user defined class 'X86MemAsmOperand'
4742
  NumMatchClassKinds
4743
};
4744
4745
}
4746
4747
789k
static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
4748
789k
  return MCTargetAsmParser::Match_InvalidOperand;
4749
789k
}
4750
4751
139k
static MatchClassKind matchTokenString(StringRef Name) {
4752
139k
  switch (Name.size()) {
4753
139k
  
default: break0
;
4754
139k
  case 1:  // 7 strings to match.
4755
59.5k
    switch (Name[0]) {
4756
59.5k
    
default: break0
;
4757
59.5k
    case '*':  // 1 string to match.
4758
303
      return MCK__STAR_;  // "*"
4759
59.5k
    case 'b':  // 1 string to match.
4760
510
      return MCK_b;  // "b"
4761
59.5k
    case 'd':  // 1 string to match.
4762
1.97k
      return MCK_d;  // "d"
4763
59.5k
    case 'q':  // 1 string to match.
4764
2.34k
      return MCK_q;  // "q"
4765
59.5k
    case 'w':  // 1 string to match.
4766
2.31k
      return MCK_w;  // "w"
4767
59.5k
    case '{':  // 1 string to match.
4768
26.0k
      return MCK__123_;  // "{"
4769
59.5k
    case '}':  // 1 string to match.
4770
26.0k
      return MCK__125_;  // "}"
4771
0
    }
4772
0
    break;
4773
33.3k
  case 2:  // 8 strings to match.
4774
33.3k
    switch (Name[0]) {
4775
33.3k
    
default: break0
;
4776
33.3k
    case 'p':  // 2 strings to match.
4777
9.43k
      switch (Name[1]) {
4778
9.43k
      
default: break0
;
4779
9.43k
      case 'd':  // 1 string to match.
4780
3.79k
        return MCK_pd;  // "pd"
4781
9.43k
      case 's':  // 1 string to match.
4782
5.64k
        return MCK_ps;  // "ps"
4783
0
      }
4784
0
      break;
4785
4.90k
    case 's':  // 2 strings to match.
4786
4.90k
      switch (Name[1]) {
4787
4.90k
      
default: break0
;
4788
4.90k
      case 'd':  // 1 string to match.
4789
2.24k
        return MCK_sd;  // "sd"
4790
4.90k
      case 's':  // 1 string to match.
4791
2.66k
        return MCK_ss;  // "ss"
4792
0
      }
4793
0
      break;
4794
19.0k
    case 'u':  // 4 strings to match.
4795
19.0k
      switch (Name[1]) {
4796
19.0k
      
default: break0
;
4797
19.0k
      case 'b':  // 1 string to match.
4798
1.60k
        return MCK_ub;  // "ub"
4799
19.0k
      case 'd':  // 1 string to match.
4800
7.12k
        return MCK_ud;  // "ud"
4801
19.0k
      case 'q':  // 1 string to match.
4802
7.84k
        return MCK_uq;  // "uq"
4803
19.0k
      case 'w':  // 1 string to match.
4804
2.44k
        return MCK_uw;  // "uw"
4805
0
      }
4806
0
      break;
4807
0
    }
4808
0
    break;
4809
7.57k
  case 3:  // 1 string to match.
4810
7.57k
    if (memcmp(Name.data()+0, "{z}", 3) != 0)
4811
0
      break;
4812
7.57k
    return MCK__123_z_125_;  // "{z}"
4813
7.57k
  case 5:  // 1 string to match.
4814
508
    if (memcmp(Name.data()+0, "{sae}", 5) != 0)
4815
0
      break;
4816
508
    return MCK__123_sae_125_;  // "{sae}"
4817
25.4k
  case 6:  // 3 strings to match.
4818
25.4k
    if (memcmp(Name.data()+0, "{1to", 4) != 0)
4819
0
      break;
4820
25.4k
    switch (Name[4]) {
4821
25.4k
    
default: break0
;
4822
25.4k
    case '2':  // 1 string to match.
4823
590
      if (Name[5] != '}')
4824
0
        break;
4825
590
      return MCK__123_1to2_125_;   // "{1to2}"
4826
2.18k
    case '4':  // 1 string to match.
4827
2.18k
      if (Name[5] != '}')
4828
0
        break;
4829
2.18k
      return MCK__123_1to4_125_;   // "{1to4}"
4830
22.6k
    case '8':  // 1 string to match.
4831
22.6k
      if (Name[5] != '}')
4832
0
        break;
4833
22.6k
      return MCK__123_1to8_125_;  // "{1to8}"
4834
0
    }
4835
0
    break;
4836
13.1k
  case 7:  // 1 string to match.
4837
13.1k
    if (memcmp(Name.data()+0, "{1to16}", 7) != 0)
4838
0
      break;
4839
13.1k
    return MCK__123_1to16_125_;  // "{1to16}"
4840
0
  }
4841
0
  return InvalidMatchClass;
4842
0
}
4843
4844
/// isSubclass - Compute whether \p A is a subclass of \p B.
4845
1.77M
static bool isSubclass(MatchClassKind A, MatchClassKind B) {
4846
1.77M
  if (A == B)
4847
226k
    return true;
4848
1.54M
4849
1.54M
  switch (A) {
4850
1.54M
  default:
4851
791k
    return false;
4852
1.54M
4853
1.54M
  case MCK_Reg69:
4854
0
    switch (B) {
4855
0
    default: return false;
4856
0
    case MCK_Reg68: return true;
4857
0
    case MCK_Reg55: return true;
4858
0
    case MCK_Reg50: return true;
4859
0
    case MCK_Reg54: return true;
4860
0
    case MCK_GR64_TCW64: return true;
4861
0
    case MCK_GR64_NOREX: return true;
4862
0
    case MCK_GR64_TC: return true;
4863
0
    case MCK_GR64: return true;
4864
0
    case MCK_LOW32_ADDR_ACCESS: return true;
4865
0
    case MCK_LOW32_ADDR_ACCESS_RBP: return true;
4866
0
    }
4867
0
4868
1.26k
  case MCK_Reg66:
4869
1.26k
    switch (B) {
4870
1.26k
    
default: return false903
;
4871
1.26k
    
case MCK_Reg68: return true0
;
4872
1.26k
    
case MCK_Reg67: return true0
;
4873
1.26k
    
case MCK_Reg65: return true0
;
4874
1.26k
    
case MCK_GR64_NOREX_NOSP: return true0
;
4875
1.26k
    
case MCK_Reg42: return true0
;
4876
1.26k
    
case MCK_Reg23: return true0
;
4877
1.26k
    
case MCK_GR64_NOREX: return true0
;
4878
1.26k
    
case MCK_GR64_NOSP: return true0
;
4879
1.26k
    
case MCK_Reg43: return true0
;
4880
1.26k
    
case MCK_Reg20: return true0
;
4881
1.26k
    
case MCK_GR64: return true359
;
4882
1.26k
    
case MCK_LOW32_ADDR_ACCESS_RBP: return true0
;
4883
0
    }
4884
0
4885
6.04k
  case MCK_Reg64:
4886
6.04k
    switch (B) {
4887
6.04k
    
default: return false2.34k
;
4888
6.04k
    
case MCK_Reg65: return true0
;
4889
6.04k
    
case MCK_Reg63: return true0
;
4890
6.04k
    
case MCK_Reg47: return true0
;
4891
6.04k
    
case MCK_Reg50: return true0
;
4892
6.04k
    
case MCK_GR64_NOREX_NOSP: return true0
;
4893
6.04k
    
case MCK_Reg48: return true0
;
4894
6.04k
    
case MCK_Reg42: return true0
;
4895
6.04k
    
case MCK_GR64_NOREX: return true0
;
4896
6.04k
    
case MCK_GR64_TC: return true0
;
4897
6.04k
    
case MCK_GR64_NOSP: return true0
;
4898
6.04k
    
case MCK_Reg43: return true0
;
4899
6.04k
    
case MCK_GR64: return true3.70k
;
4900
0
    }
4901
0
4902
3.28k
  case MCK_Reg62:
4903
3.28k
    switch (B) {
4904
3.28k
    
default: return false1.54k
;
4905
3.28k
    
case MCK_Reg63: return true0
;
4906
3.28k
    
case MCK_Reg61: return true0
;
4907
3.28k
    
case MCK_Reg47: return true0
;
4908
3.28k
    
case MCK_Reg50: return true0
;
4909
3.28k
    
case MCK_GR64_NOREX_NOSP: return true0
;
4910
3.28k
    
case MCK_Reg48: return true0
;
4911
3.28k
    
case MCK_Reg42: return true0
;
4912
3.28k
    
case MCK_GR64_NOREX: return true0
;
4913
3.28k
    
case MCK_GR64_TC: return true0
;
4914
3.28k
    
case MCK_GR64_NOSP: return true0
;
4915
3.28k
    
case MCK_Reg43: return true0
;
4916
3.28k
    
case MCK_GR64: return true1.74k
;
4917
0
    }
4918
0
4919
1.02k
  case MCK_Reg35:
4920
1.02k
    switch (B) {
4921
1.02k
    
default: return false535
;
4922
1.02k
    
case MCK_GR32_BPSP: return true0
;
4923
1.02k
    
case MCK_GR32_DIBP: return true0
;
4924
1.02k
    
case MCK_GR32_NOREX_NOSP: return true0
;
4925
1.02k
    
case MCK_GR32_NOREX: return true0
;
4926
1.02k
    
case MCK_Reg23: return true0
;
4927
1.02k
    
case MCK_GR32_NOSP: return true0
;
4928
1.02k
    
case MCK_GR32: return true486
;
4929
1.02k
    
case MCK_Reg20: return true0
;
4930
1.02k
    
case MCK_LOW32_ADDR_ACCESS: return true0
;
4931
1.02k
    
case MCK_LOW32_ADDR_ACCESS_RBP: return true0
;
4932
0
    }
4933
0
4934
6.05k
  case MCK_Reg33:
4935
6.05k
    switch (B) {
4936
6.05k
    
default: return false2.36k
;
4937
6.05k
    
case MCK_GR32_DIBP: return true0
;
4938
6.05k
    
case MCK_GR32_SIDI: return true0
;
4939
6.05k
    
case MCK_GR32_NOREX_NOSP: return true0
;
4940
6.05k
    
case MCK_GR32_NOREX: return true0
;
4941
6.05k
    
case MCK_Reg23: return true0
;
4942
6.05k
    
case MCK_GR32_NOSP: return true0
;
4943
6.05k
    
case MCK_GR32: return true3.69k
;
4944
6.05k
    
case MCK_Reg20: return true0
;
4945
6.05k
    
case MCK_LOW32_ADDR_ACCESS: return true0
;
4946
6.05k
    
case MCK_LOW32_ADDR_ACCESS_RBP: return true0
;
4947
0
    }
4948
0
4949
3.64k
  case MCK_Reg31:
4950
3.64k
    switch (B) {
4951
3.64k
    
default: return false1.86k
;
4952
3.64k
    
case MCK_GR32_BSI: return true0
;
4953
3.64k
    
case MCK_GR32_SIDI: return true0
;
4954
3.64k
    
case MCK_GR32_NOREX_NOSP: return true0
;
4955
3.64k
    
case MCK_GR32_NOREX: return true0
;
4956
3.64k
    
case MCK_Reg23: return true0
;
4957
3.64k
    
case MCK_GR32_NOSP: return true0
;
4958
3.64k
    
case MCK_GR32: return true1.78k
;
4959
3.64k
    
case MCK_Reg20: return true0
;
4960
3.64k
    
case MCK_LOW32_ADDR_ACCESS: return true0
;
4961
3.64k
    
case MCK_LOW32_ADDR_ACCESS_RBP: return true0
;
4962
0
    }
4963
0
4964
7.32k
  case MCK_AL:
4965
7.32k
    switch (B) {
4966
7.32k
    
default: return false6.95k
;