Coverage Report

Created: 2019-02-15 18:59

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/X86/X86GenCallingConv.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Calling Convention Implementation Fragment                                 *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
10
                            MVT LocVT, CCValAssign::LocInfo LocInfo,
11
                            ISD::ArgFlagsTy ArgFlags, CCState &State);
12
bool llvm::CC_X86(unsigned ValNo, MVT ValVT,
13
                  MVT LocVT, CCValAssign::LocInfo LocInfo,
14
                  ISD::ArgFlagsTy ArgFlags, CCState &State);
15
static bool CC_X86_32(unsigned ValNo, MVT ValVT,
16
                      MVT LocVT, CCValAssign::LocInfo LocInfo,
17
                      ISD::ArgFlagsTy ArgFlags, CCState &State);
18
static bool CC_X86_32_C(unsigned ValNo, MVT ValVT,
19
                        MVT LocVT, CCValAssign::LocInfo LocInfo,
20
                        ISD::ArgFlagsTy ArgFlags, CCState &State);
21
static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT,
22
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
23
                             ISD::ArgFlagsTy ArgFlags, CCState &State);
24
static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT,
25
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
26
                             ISD::ArgFlagsTy ArgFlags, CCState &State);
27
static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT,
28
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
29
                               ISD::ArgFlagsTy ArgFlags, CCState &State);
30
static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT,
31
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
32
                          ISD::ArgFlagsTy ArgFlags, CCState &State);
33
static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
34
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
35
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
36
static bool CC_X86_32_Intr(unsigned ValNo, MVT ValVT,
37
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
38
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
39
static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT,
40
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
41
                          ISD::ArgFlagsTy ArgFlags, CCState &State);
42
static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
43
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
44
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
45
static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT,
46
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
47
                               ISD::ArgFlagsTy ArgFlags, CCState &State);
48
static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT,
49
                                      MVT LocVT, CCValAssign::LocInfo LocInfo,
50
                                      ISD::ArgFlagsTy ArgFlags, CCState &State);
51
static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT,
52
                                     MVT LocVT, CCValAssign::LocInfo LocInfo,
53
                                     ISD::ArgFlagsTy ArgFlags, CCState &State);
54
static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT,
55
                                   MVT LocVT, CCValAssign::LocInfo LocInfo,
56
                                   ISD::ArgFlagsTy ArgFlags, CCState &State);
57
static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT,
58
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
59
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
60
static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT,
61
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
62
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
63
static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT,
64
                                      MVT LocVT, CCValAssign::LocInfo LocInfo,
65
                                      ISD::ArgFlagsTy ArgFlags, CCState &State);
66
static bool CC_X86_64(unsigned ValNo, MVT ValVT,
67
                      MVT LocVT, CCValAssign::LocInfo LocInfo,
68
                      ISD::ArgFlagsTy ArgFlags, CCState &State);
69
static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
70
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
71
                             ISD::ArgFlagsTy ArgFlags, CCState &State);
72
static bool CC_X86_64_C(unsigned ValNo, MVT ValVT,
73
                        MVT LocVT, CCValAssign::LocInfo LocInfo,
74
                        ISD::ArgFlagsTy ArgFlags, CCState &State);
75
static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT,
76
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
77
                          ISD::ArgFlagsTy ArgFlags, CCState &State);
78
static bool CC_X86_64_HHVM(unsigned ValNo, MVT ValVT,
79
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
80
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
81
static bool CC_X86_64_HHVM_C(unsigned ValNo, MVT ValVT,
82
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
83
                             ISD::ArgFlagsTy ArgFlags, CCState &State);
84
static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
85
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
86
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
87
static bool CC_X86_64_Intr(unsigned ValNo, MVT ValVT,
88
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
89
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
90
static bool CC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT,
91
                                MVT LocVT, CCValAssign::LocInfo LocInfo,
92
                                ISD::ArgFlagsTy ArgFlags, CCState &State);
93
static bool CC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
94
                                  MVT LocVT, CCValAssign::LocInfo LocInfo,
95
                                  ISD::ArgFlagsTy ArgFlags, CCState &State);
96
static bool CC_X86_Win32_VectorCall(unsigned ValNo, MVT ValVT,
97
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
98
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
99
static bool CC_X86_Win64_C(unsigned ValNo, MVT ValVT,
100
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
101
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
102
static bool CC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
103
                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
104
                                 ISD::ArgFlagsTy ArgFlags, CCState &State);
105
static bool CC_X86_Win64_VectorCall(unsigned ValNo, MVT ValVT,
106
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
107
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
108
static bool RetCC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
109
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
110
                               ISD::ArgFlagsTy ArgFlags, CCState &State);
111
bool llvm::RetCC_X86(unsigned ValNo, MVT ValVT,
112
                     MVT LocVT, CCValAssign::LocInfo LocInfo,
113
                     ISD::ArgFlagsTy ArgFlags, CCState &State);
114
static bool RetCC_X86Common(unsigned ValNo, MVT ValVT,
115
                            MVT LocVT, CCValAssign::LocInfo LocInfo,
116
                            ISD::ArgFlagsTy ArgFlags, CCState &State);
117
static bool RetCC_X86_32(unsigned ValNo, MVT ValVT,
118
                         MVT LocVT, CCValAssign::LocInfo LocInfo,
119
                         ISD::ArgFlagsTy ArgFlags, CCState &State);
120
static bool RetCC_X86_32_C(unsigned ValNo, MVT ValVT,
121
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
122
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
123
static bool RetCC_X86_32_Fast(unsigned ValNo, MVT ValVT,
124
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
125
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
126
static bool RetCC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
127
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
128
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
129
static bool RetCC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
130
                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
131
                                 ISD::ArgFlagsTy ArgFlags, CCState &State);
132
static bool RetCC_X86_32_VectorCall(unsigned ValNo, MVT ValVT,
133
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
134
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
135
static bool RetCC_X86_64(unsigned ValNo, MVT ValVT,
136
                         MVT LocVT, CCValAssign::LocInfo LocInfo,
137
                         ISD::ArgFlagsTy ArgFlags, CCState &State);
138
static bool RetCC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
139
                                MVT LocVT, CCValAssign::LocInfo LocInfo,
140
                                ISD::ArgFlagsTy ArgFlags, CCState &State);
141
static bool RetCC_X86_64_C(unsigned ValNo, MVT ValVT,
142
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
143
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
144
static bool RetCC_X86_64_HHVM(unsigned ValNo, MVT ValVT,
145
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
146
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
147
static bool RetCC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
148
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
149
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
150
static bool RetCC_X86_64_Swift(unsigned ValNo, MVT ValVT,
151
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
152
                               ISD::ArgFlagsTy ArgFlags, CCState &State);
153
static bool RetCC_X86_64_Vectorcall(unsigned ValNo, MVT ValVT,
154
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
155
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
156
static bool RetCC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT,
157
                                   MVT LocVT, CCValAssign::LocInfo LocInfo,
158
                                   ISD::ArgFlagsTy ArgFlags, CCState &State);
159
static bool RetCC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
160
                                     MVT LocVT, CCValAssign::LocInfo LocInfo,
161
                                     ISD::ArgFlagsTy ArgFlags, CCState &State);
162
static bool RetCC_X86_Win64_C(unsigned ValNo, MVT ValVT,
163
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
164
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
165
static bool RetCC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
166
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
167
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
168
169
170
static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
171
                            MVT LocVT, CCValAssign::LocInfo LocInfo,
172
238
                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
173
238
174
238
  if (LocVT == MVT::i32) {
175
22
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
176
2
      static const MCPhysReg RegList1[] = {
177
2
        X86::ECX, X86::EDX, X86::R8D, X86::R9D
178
2
      };
179
2
      if (unsigned Reg = State.AllocateReg(RegList1)) {
180
2
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
181
2
        return false;
182
2
      }
183
236
    }
184
22
  }
185
236
186
236
  if (LocVT == MVT::i64) {
187
16
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
188
8
      static const MCPhysReg RegList2[] = {
189
8
        X86::RCX, X86::RDX, X86::R8, X86::R9
190
8
      };
191
8
      if (unsigned Reg = State.AllocateReg(RegList2)) {
192
8
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
193
8
        return false;
194
8
      }
195
228
    }
196
16
  }
197
228
198
228
  if (LocVT == MVT::i32) {
199
20
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
200
2
      static const MCPhysReg RegList3[] = {
201
2
        X86::EDI, X86::ESI, X86::EDX, X86::ECX
202
2
      };
203
2
      if (unsigned Reg = State.AllocateReg(RegList3)) {
204
2
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
205
2
        return false;
206
2
      }
207
226
    }
208
20
  }
209
226
210
226
  if (LocVT == MVT::i64) {
211
8
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
212
8
      static const MCPhysReg RegList4[] = {
213
8
        X86::RDI, X86::RSI, X86::RDX, X86::RCX
214
8
      };
215
8
      if (unsigned Reg = State.AllocateReg(RegList4)) {
216
8
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
217
8
        return false;
218
8
      }
219
218
    }
220
8
  }
221
218
222
218
  if (LocVT == MVT::i32) {
223
18
    unsigned Offset5 = State.AllocateStack(4, 4);
224
18
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
225
18
    return false;
226
18
  }
227
200
228
200
  if (LocVT == MVT::f32 ||
229
200
      LocVT == MVT::f64 ||
230
200
      LocVT == MVT::v4i32 ||
231
200
      LocVT == MVT::v2i64 ||
232
200
      LocVT == MVT::v4f32 ||
233
200
      
LocVT == MVT::v2f64128
) {
234
72
    static const MCPhysReg RegList6[] = {
235
72
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
236
72
    };
237
72
    if (unsigned Reg = State.AllocateReg(RegList6)) {
238
60
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
239
60
      return false;
240
60
    }
241
140
  }
242
140
243
140
  if (LocVT == MVT::v8f32 ||
244
140
      
LocVT == MVT::v4f64108
||
245
140
      
LocVT == MVT::v8i32108
||
246
140
      
LocVT == MVT::v4i64108
) {
247
32
    static const MCPhysReg RegList7[] = {
248
32
      X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
249
32
    };
250
32
    if (unsigned Reg = State.AllocateReg(RegList7)) {
251
32
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
252
32
      return false;
253
32
    }
254
108
  }
255
108
256
108
  if (LocVT == MVT::v16f32 ||
257
108
      
LocVT == MVT::v8f6452
||
258
108
      
LocVT == MVT::v16i3252
||
259
108
      
LocVT == MVT::v8i6436
) {
260
72
    static const MCPhysReg RegList8[] = {
261
72
      X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
262
72
    };
263
72
    if (unsigned Reg = State.AllocateReg(RegList8)) {
264
72
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
265
72
      return false;
266
72
    }
267
36
  }
268
36
269
36
  if (LocVT == MVT::v16i1 ||
270
36
      
LocVT == MVT::v8i112
) {
271
24
    if (unsigned Reg = State.AllocateReg(X86::K1)) {
272
24
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
273
24
      return false;
274
24
    }
275
12
  }
276
12
277
12
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
278
4
    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
279
4
      return false;
280
8
  }
281
8
282
8
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
283
4
    if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
284
4
      return false;
285
4
  }
286
4
287
4
  if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
288
4
    return false;
289
0
290
0
  return true;  // CC didn't match.
291
0
}
292
293
294
bool llvm::CC_X86(unsigned ValNo, MVT ValVT,
295
                  MVT LocVT, CCValAssign::LocInfo LocInfo,
296
608k
                  ISD::ArgFlagsTy ArgFlags, CCState &State) {
297
608k
298
608k
  if (State.getCallingConv() == CallingConv::Intel_OCL_BI) {
299
238
    if (!CC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
300
238
      return false;
301
608k
  }
302
608k
303
608k
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
304
493k
    if (!CC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
305
493k
      return false;
306
114k
  }
307
114k
308
114k
  if (!CC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
309
114k
    return false;
310
18.4E
311
18.4E
  return true;  // CC didn't match.
312
18.4E
}
313
314
315
static bool CC_X86_32(unsigned ValNo, MVT ValVT,
316
                      MVT LocVT, CCValAssign::LocInfo LocInfo,
317
114k
                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
318
114k
319
114k
  if (State.getCallingConv() == CallingConv::X86_INTR) {
320
16
    if (!CC_X86_32_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
321
16
      return false;
322
114k
  }
323
114k
324
114k
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetMCU()) {
325
126
    if (!CC_X86_32_MCU(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
326
126
      return false;
327
114k
  }
328
114k
329
114k
  if (State.getCallingConv() == CallingConv::X86_FastCall) {
330
206
    if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
331
200
      return false;
332
114k
  }
333
114k
334
114k
  if (State.getCallingConv() == CallingConv::X86_VectorCall) {
335
244
    if (!CC_X86_Win32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
336
244
      return false;
337
114k
  }
338
114k
339
114k
  if (State.getCallingConv() == CallingConv::X86_ThisCall) {
340
448
    if (!CC_X86_32_ThisCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
341
448
      return false;
342
113k
  }
343
113k
344
113k
  if (State.getCallingConv() == CallingConv::Fast) {
345
1.85k
    if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
346
1.85k
      return false;
347
111k
  }
348
111k
349
111k
  if (State.getCallingConv() == CallingConv::GHC) {
350
20
    if (!CC_X86_32_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
351
20
      return false;
352
111k
  }
353
111k
354
111k
  if (State.getCallingConv() == CallingConv::HiPE) {
355
42
    if (!CC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
356
42
      return false;
357
111k
  }
358
111k
359
111k
  if (State.getCallingConv() == CallingConv::X86_RegCall) {
360
209
    if (!CC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
361
206
      return false;
362
111k
  }
363
111k
364
111k
  if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
365
111k
    return false;
366
0
367
0
  return true;  // CC didn't match.
368
0
}
369
370
371
static bool CC_X86_32_C(unsigned ValNo, MVT ValVT,
372
                        MVT LocVT, CCValAssign::LocInfo LocInfo,
373
111k
                        ISD::ArgFlagsTy ArgFlags, CCState &State) {
374
111k
375
111k
  if (LocVT == MVT::i1 ||
376
111k
      
LocVT == MVT::i8111k
||
377
111k
      
LocVT == MVT::i16103k
||
378
111k
      
LocVT == MVT::v1i1101k
) {
379
10.5k
    LocVT = MVT::i32;
380
10.5k
    if (ArgFlags.isSExt())
381
88
        LocInfo = CCValAssign::SExt;
382
10.4k
    else if (ArgFlags.isZExt())
383
4.19k
        LocInfo = CCValAssign::ZExt;
384
6.22k
    else
385
6.22k
        LocInfo = CCValAssign::AExt;
386
10.5k
  }
387
111k
388
111k
  if (ArgFlags.isNest()) {
389
8
    if (unsigned Reg = State.AllocateReg(X86::ECX)) {
390
8
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
391
8
      return false;
392
8
    }
393
111k
  }
394
111k
395
111k
  if (!State.isVarArg()) {
396
107k
    if (ArgFlags.isInReg()) {
397
290
      if (LocVT == MVT::i32) {
398
266
        static const MCPhysReg RegList1[] = {
399
266
          X86::EAX, X86::EDX, X86::ECX
400
266
        };
401
266
        if (unsigned Reg = State.AllocateReg(RegList1)) {
402
257
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
403
257
          return false;
404
257
        }
405
111k
      }
406
290
    }
407
107k
  }
408
111k
409
111k
  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
410
111k
    return false;
411
0
412
0
  return true;  // CC didn't match.
413
0
}
414
415
416
static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT,
417
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
418
112k
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
419
112k
420
112k
  if (ArgFlags.isByVal()) {
421
216
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
422
216
    return false;
423
216
  }
424
111k
425
111k
  if (!State.isVarArg()) {
426
108k
    if (ArgFlags.isInReg()) {
427
62
      if (LocVT == MVT::f32 ||
428
62
          
LocVT == MVT::f6458
) {
429
8
        if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
430
0
          static const MCPhysReg RegList1[] = {
431
0
            X86::XMM0, X86::XMM1, X86::XMM2
432
0
          };
433
0
          if (unsigned Reg = State.AllocateReg(RegList1)) {
434
0
            State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
435
0
            return false;
436
0
          }
437
111k
        }
438
8
      }
439
62
    }
440
108k
  }
441
111k
442
111k
  if (!State.isVarArg()) {
443
108k
    if (LocVT == MVT::x86mmx) {
444
227
      static const MCPhysReg RegList2[] = {
445
227
        X86::MM0, X86::MM1, X86::MM2
446
227
      };
447
227
      if (unsigned Reg = State.AllocateReg(RegList2)) {
448
227
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
449
227
        return false;
450
227
      }
451
111k
    }
452
108k
  }
453
111k
454
111k
  if (LocVT == MVT::i32 ||
455
111k
      
LocVT == MVT::f3223.2k
) {
456
89.7k
    unsigned Offset3 = State.AllocateStack(4, 4);
457
89.7k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
458
89.7k
    return false;
459
89.7k
  }
460
21.8k
461
21.8k
  if (LocVT == MVT::f64) {
462
1.00k
    unsigned Offset4 = State.AllocateStack(8, 4);
463
1.00k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
464
1.00k
    return false;
465
1.00k
  }
466
20.8k
467
20.8k
  if (LocVT == MVT::f80) {
468
233
    unsigned Offset5 = State.AllocateStack(
469
233
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 4);
470
233
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
471
233
    return false;
472
233
  }
473
20.5k
474
20.5k
  if (LocVT == MVT::v2i1) {
475
22
    LocVT = MVT::v2i64;
476
22
    if (ArgFlags.isSExt())
477
0
        LocInfo = CCValAssign::SExt;
478
22
    else if (ArgFlags.isZExt())
479
0
        LocInfo = CCValAssign::ZExt;
480
22
    else
481
22
        LocInfo = CCValAssign::AExt;
482
22
  }
483
20.5k
484
20.5k
  if (LocVT == MVT::v4i1) {
485
24
    LocVT = MVT::v4i32;
486
24
    if (ArgFlags.isSExt())
487
0
        LocInfo = CCValAssign::SExt;
488
24
    else if (ArgFlags.isZExt())
489
0
        LocInfo = CCValAssign::ZExt;
490
24
    else
491
24
        LocInfo = CCValAssign::AExt;
492
24
  }
493
20.5k
494
20.5k
  if (LocVT == MVT::v8i1) {
495
17
    LocVT = MVT::v8i16;
496
17
    if (ArgFlags.isSExt())
497
0
        LocInfo = CCValAssign::SExt;
498
17
    else if (ArgFlags.isZExt())
499
0
        LocInfo = CCValAssign::ZExt;
500
17
    else
501
17
        LocInfo = CCValAssign::AExt;
502
17
  }
503
20.5k
504
20.5k
  if (LocVT == MVT::v16i1) {
505
31
    LocVT = MVT::v16i8;
506
31
    if (ArgFlags.isSExt())
507
0
        LocInfo = CCValAssign::SExt;
508
31
    else if (ArgFlags.isZExt())
509
0
        LocInfo = CCValAssign::ZExt;
510
31
    else
511
31
        LocInfo = CCValAssign::AExt;
512
31
  }
513
20.5k
514
20.5k
  if (LocVT == MVT::v32i1) {
515
5
    LocVT = MVT::v32i8;
516
5
    if (ArgFlags.isSExt())
517
0
        LocInfo = CCValAssign::SExt;
518
5
    else if (ArgFlags.isZExt())
519
0
        LocInfo = CCValAssign::ZExt;
520
5
    else
521
5
        LocInfo = CCValAssign::AExt;
522
5
  }
523
20.5k
524
20.5k
  if (LocVT == MVT::v64i1) {
525
1
    LocVT = MVT::v64i8;
526
1
    if (ArgFlags.isSExt())
527
0
        LocInfo = CCValAssign::SExt;
528
1
    else if (ArgFlags.isZExt())
529
0
        LocInfo = CCValAssign::ZExt;
530
1
    else
531
1
        LocInfo = CCValAssign::AExt;
532
1
  }
533
20.5k
534
20.5k
  if (LocVT == MVT::x86mmx) {
535
0
    unsigned Offset6 = State.AllocateStack(8, 4);
536
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
537
0
    return false;
538
0
  }
539
20.5k
540
20.5k
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()) {
541
4.05k
    if (!CC_X86_32_Vector_Darwin(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
542
4.05k
      return false;
543
16.5k
  }
544
16.5k
545
16.5k
  if (!CC_X86_32_Vector_Standard(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
546
16.5k
    return false;
547
6
548
6
  return true;  // CC didn't match.
549
6
}
550
551
552
static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT,
553
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
554
1.85k
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
555
1.85k
556
1.85k
  if (ArgFlags.isByVal()) {
557
94
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
558
94
    return false;
559
94
  }
560
1.76k
561
1.76k
  if (LocVT == MVT::i1 ||
562
1.76k
      LocVT == MVT::i8 ||
563
1.76k
      
LocVT == MVT::i161.64k
||
564
1.76k
      
LocVT == MVT::v1i11.64k
) {
565
112
    LocVT = MVT::i32;
566
112
    if (ArgFlags.isSExt())
567
8
        LocInfo = CCValAssign::SExt;
568
104
    else if (ArgFlags.isZExt())
569
102
        LocInfo = CCValAssign::ZExt;
570
2
    else
571
2
        LocInfo = CCValAssign::AExt;
572
112
  }
573
1.76k
574
1.76k
  if (ArgFlags.isNest()) {
575
0
    if (unsigned Reg = State.AllocateReg(X86::EAX)) {
576
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
577
0
      return false;
578
0
    }
579
1.76k
  }
580
1.76k
581
1.76k
  if (LocVT == MVT::i32) {
582
1.73k
    static const MCPhysReg RegList1[] = {
583
1.73k
      X86::ECX, X86::EDX
584
1.73k
    };
585
1.73k
    if (unsigned Reg = State.AllocateReg(RegList1)) {
586
1.29k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
587
1.29k
      return false;
588
1.29k
    }
589
461
  }
590
461
591
461
  if (!State.isVarArg()) {
592
461
    if (LocVT == MVT::f32 ||
593
461
        
LocVT == MVT::f64457
) {
594
18
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
595
8
        static const MCPhysReg RegList2[] = {
596
8
          X86::XMM0, X86::XMM1, X86::XMM2
597
8
        };
598
8
        if (unsigned Reg = State.AllocateReg(RegList2)) {
599
6
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
600
6
          return false;
601
6
        }
602
455
      }
603
18
    }
604
461
  }
605
455
606
455
  if (LocVT == MVT::f64) {
607
9
    unsigned Offset3 = State.AllocateStack(8, 8);
608
9
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
609
9
    return false;
610
9
  }
611
446
612
446
  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
613
446
    return false;
614
0
615
0
  return true;  // CC didn't match.
616
0
}
617
618
619
static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT,
620
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
621
266
                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
622
266
623
266
  if (LocVT == MVT::i1) {
624
0
    LocVT = MVT::i8;
625
0
    if (ArgFlags.isSExt())
626
0
        LocInfo = CCValAssign::SExt;
627
0
    else if (ArgFlags.isZExt())
628
0
        LocInfo = CCValAssign::ZExt;
629
0
    else
630
0
        LocInfo = CCValAssign::AExt;
631
0
  }
632
266
633
266
  if (ArgFlags.isNest()) {
634
0
    if (unsigned Reg = State.AllocateReg(X86::EAX)) {
635
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
636
0
      return false;
637
0
    }
638
266
  }
639
266
640
266
  if (ArgFlags.isInReg()) {
641
197
    if (LocVT == MVT::i8) {
642
4
      static const MCPhysReg RegList1[] = {
643
4
        X86::CL, X86::DL
644
4
      };
645
4
      if (unsigned Reg = State.AllocateReg(RegList1)) {
646
4
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
647
4
        return false;
648
4
      }
649
262
    }
650
197
  }
651
262
652
262
  if (ArgFlags.isInReg()) {
653
193
    if (LocVT == MVT::i16) {
654
0
      static const MCPhysReg RegList2[] = {
655
0
        X86::CX, X86::DX
656
0
      };
657
0
      if (unsigned Reg = State.AllocateReg(RegList2)) {
658
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
659
0
        return false;
660
0
      }
661
262
    }
662
193
  }
663
262
664
262
  if (ArgFlags.isInReg()) {
665
193
    if (LocVT == MVT::i32) {
666
178
      static const MCPhysReg RegList3[] = {
667
178
        X86::ECX, X86::EDX
668
178
      };
669
178
      if (unsigned Reg = State.AllocateReg(RegList3)) {
670
172
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
671
172
        return false;
672
172
      }
673
90
    }
674
193
  }
675
90
676
90
  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
677
84
    return false;
678
6
679
6
  return true;  // CC didn't match.
680
6
}
681
682
683
static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT,
684
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
685
20
                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
686
20
687
20
  if (LocVT == MVT::i8 ||
688
20
      LocVT == MVT::i16) {
689
0
    LocVT = MVT::i32;
690
0
    if (ArgFlags.isSExt())
691
0
        LocInfo = CCValAssign::SExt;
692
0
    else if (ArgFlags.isZExt())
693
0
        LocInfo = CCValAssign::ZExt;
694
0
    else
695
0
        LocInfo = CCValAssign::AExt;
696
0
  }
697
20
698
20
  if (LocVT == MVT::i32) {
699
20
    static const MCPhysReg RegList1[] = {
700
20
      X86::EBX, X86::EBP, X86::EDI, X86::ESI
701
20
    };
702
20
    if (unsigned Reg = State.AllocateReg(RegList1)) {
703
20
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
704
20
      return false;
705
20
    }
706
0
  }
707
0
708
0
  return true;  // CC didn't match.
709
0
}
710
711
712
static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
713
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
714
42
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
715
42
716
42
  if (LocVT == MVT::i8 ||
717
42
      LocVT == MVT::i16) {
718
0
    LocVT = MVT::i32;
719
0
    if (ArgFlags.isSExt())
720
0
        LocInfo = CCValAssign::SExt;
721
0
    else if (ArgFlags.isZExt())
722
0
        LocInfo = CCValAssign::ZExt;
723
0
    else
724
0
        LocInfo = CCValAssign::AExt;
725
0
  }
726
42
727
42
  if (LocVT == MVT::i32) {
728
42
    static const MCPhysReg RegList1[] = {
729
42
      X86::ESI, X86::EBP, X86::EAX, X86::EDX, X86::ECX
730
42
    };
731
42
    if (unsigned Reg = State.AllocateReg(RegList1)) {
732
41
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
733
41
      return false;
734
41
    }
735
1
  }
736
1
737
1
  if (LocVT == MVT::i32 ||
738
1
      
LocVT == MVT::f320
) {
739
1
    unsigned Offset2 = State.AllocateStack(4, 4);
740
1
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
741
1
    return false;
742
1
  }
743
0
744
0
  return true;  // CC didn't match.
745
0
}
746
747
748
static bool CC_X86_32_Intr(unsigned ValNo, MVT ValVT,
749
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
750
16
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
751
16
752
16
  unsigned Offset1 = State.AllocateStack(4, 4);
753
16
  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
754
16
  return false;
755
16
756
16
  
return true0
; // CC didn't match.
757
16
}
758
759
760
static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT,
761
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
762
126
                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
763
126
764
126
  if (ArgFlags.isByVal()) {
765
1
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
766
1
    return false;
767
1
  }
768
125
769
125
  if (LocVT == MVT::i1 ||
770
125
      LocVT == MVT::i8 ||
771
125
      
LocVT == MVT::i16113
||
772
125
      
LocVT == MVT::v1i1106
) {
773
19
    LocVT = MVT::i32;
774
19
    if (ArgFlags.isSExt())
775
0
        LocInfo = CCValAssign::SExt;
776
19
    else if (ArgFlags.isZExt())
777
3
        LocInfo = CCValAssign::ZExt;
778
16
    else
779
16
        LocInfo = CCValAssign::AExt;
780
19
  }
781
125
782
125
  if (!State.isVarArg()) {
783
124
    if (LocVT == MVT::i32) {
784
123
      if (CC_X86_32_MCUInReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
785
120
            return false;
786
5
    }
787
124
  }
788
5
789
5
  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
790
5
    return false;
791
0
792
0
  return true;  // CC didn't match.
793
0
}
794
795
796
static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
797
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
798
209
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
799
209
800
209
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
801
0
    if (ArgFlags.isByVal()) {
802
0
      State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
803
0
      return false;
804
0
    }
805
209
  }
806
209
807
209
  if (ArgFlags.isByVal()) {
808
0
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
809
0
    return false;
810
0
  }
811
209
812
209
  if (LocVT == MVT::i1 ||
813
209
      LocVT == MVT::i8 ||
814
209
      
LocVT == MVT::i16198
||
815
209
      
LocVT == MVT::v1i1194
) {
816
15
    LocVT = MVT::i32;
817
15
    if (ArgFlags.isSExt())
818
2
        LocInfo = CCValAssign::SExt;
819
13
    else if (ArgFlags.isZExt())
820
0
        LocInfo = CCValAssign::ZExt;
821
13
    else
822
13
        LocInfo = CCValAssign::AExt;
823
15
  }
824
209
825
209
  if (LocVT == MVT::v8i1 ||
826
209
      
LocVT == MVT::v16i1200
||
827
209
      
LocVT == MVT::v32i1191
) {
828
24
    LocVT = MVT::i32;
829
24
    if (ArgFlags.isSExt())
830
0
        LocInfo = CCValAssign::SExt;
831
24
    else if (ArgFlags.isZExt())
832
0
        LocInfo = CCValAssign::ZExt;
833
24
    else
834
24
        LocInfo = CCValAssign::AExt;
835
24
  }
836
209
837
209
  if (LocVT == MVT::i32) {
838
92
    static const MCPhysReg RegList1[] = {
839
92
      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI
840
92
    };
841
92
    if (unsigned Reg = State.AllocateReg(RegList1)) {
842
77
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
843
77
      return false;
844
77
    }
845
132
  }
846
132
847
132
  if (LocVT == MVT::i64) {
848
0
    if (unsigned Reg = State.AllocateReg(X86::RAX)) {
849
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
850
0
      return false;
851
0
    }
852
132
  }
853
132
854
132
  if (LocVT == MVT::v64i1) {
855
26
    LocVT = MVT::i64;
856
26
    if (ArgFlags.isSExt())
857
0
        LocInfo = CCValAssign::SExt;
858
26
    else if (ArgFlags.isZExt())
859
0
        LocInfo = CCValAssign::ZExt;
860
26
    else
861
26
        LocInfo = CCValAssign::AExt;
862
26
  }
863
132
864
132
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
865
0
    if (LocVT == MVT::i64) {
866
0
      if (unsigned Reg = State.AllocateReg(X86::RAX)) {
867
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
868
0
        return false;
869
0
      }
870
132
    }
871
0
  }
872
132
873
132
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
874
132
    if (LocVT == MVT::i64) {
875
26
      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
876
4
            return false;
877
128
    }
878
132
  }
879
128
880
128
  if (LocVT == MVT::f32 ||
881
128
      
LocVT == MVT::f64123
||
882
128
      
LocVT == MVT::f128118
) {
883
10
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
884
10
      static const MCPhysReg RegList2[] = {
885
10
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
886
10
      };
887
10
      if (unsigned Reg = State.AllocateReg(RegList2)) {
888
10
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
889
10
        return false;
890
10
      }
891
118
    }
892
10
  }
893
118
894
118
  if (LocVT == MVT::f80) {
895
3
    if (unsigned Reg = State.AllocateReg(X86::FP0)) {
896
3
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
897
3
      return false;
898
3
    }
899
115
  }
900
115
901
115
  if (LocVT == MVT::v16i8 ||
902
115
      LocVT == MVT::v8i16 ||
903
115
      LocVT == MVT::v4i32 ||
904
115
      
LocVT == MVT::v2i64110
||
905
115
      
LocVT == MVT::v4f32110
||
906
115
      
LocVT == MVT::v2f6474
) {
907
41
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
908
41
      static const MCPhysReg RegList3[] = {
909
41
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
910
41
      };
911
41
      if (unsigned Reg = State.AllocateReg(RegList3)) {
912
21
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
913
21
        return false;
914
21
      }
915
94
    }
916
41
  }
917
94
918
94
  if (LocVT == MVT::v32i8 ||
919
94
      LocVT == MVT::v16i16 ||
920
94
      LocVT == MVT::v8i32 ||
921
94
      
LocVT == MVT::v4i6489
||
922
94
      
LocVT == MVT::v8f3289
||
923
94
      
LocVT == MVT::v4f6489
) {
924
5
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
925
5
      static const MCPhysReg RegList4[] = {
926
5
        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
927
5
      };
928
5
      if (unsigned Reg = State.AllocateReg(RegList4)) {
929
5
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
930
5
        return false;
931
5
      }
932
89
    }
933
5
  }
934
89
935
89
  if (LocVT == MVT::v64i8 ||
936
89
      LocVT == MVT::v32i16 ||
937
89
      LocVT == MVT::v16i32 ||
938
89
      
LocVT == MVT::v8i6484
||
939
89
      
LocVT == MVT::v16f3284
||
940
89
      
LocVT == MVT::v8f6460
) {
941
29
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
942
29
      static const MCPhysReg RegList5[] = {
943
29
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
944
29
      };
945
29
      if (unsigned Reg = State.AllocateReg(RegList5)) {
946
19
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
947
19
        return false;
948
19
      }
949
70
    }
950
29
  }
951
70
952
70
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
953
0
    if (LocVT == MVT::i32 ||
954
0
        LocVT == MVT::i64 ||
955
0
        LocVT == MVT::f32 ||
956
0
        LocVT == MVT::f64) {
957
0
      unsigned Offset6 = State.AllocateStack(8, 8);
958
0
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
959
0
      return false;
960
0
    }
961
70
  }
962
70
963
70
  if (LocVT == MVT::i32 ||
964
70
      
LocVT == MVT::f3255
) {
965
15
    unsigned Offset7 = State.AllocateStack(4, 4);
966
15
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
967
15
    return false;
968
15
  }
969
55
970
55
  if (LocVT == MVT::i64 ||
971
55
      
LocVT == MVT::f6433
) {
972
22
    unsigned Offset8 = State.AllocateStack(8, 4);
973
22
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
974
22
    return false;
975
22
  }
976
33
977
33
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
978
0
    if (LocVT == MVT::x86mmx) {
979
0
      unsigned Offset9 = State.AllocateStack(8, 8);
980
0
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
981
0
      return false;
982
0
    }
983
33
  }
984
33
985
33
  if (LocVT == MVT::x86mmx) {
986
0
    unsigned Offset10 = State.AllocateStack(8, 4);
987
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
988
0
    return false;
989
0
  }
990
33
991
33
  if (LocVT == MVT::f80 ||
992
33
      LocVT == MVT::f128) {
993
0
    unsigned Offset11 = State.AllocateStack(
994
0
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 
995
0
      State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
996
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo));
997
0
    return false;
998
0
  }
999
33
1000
33
  if (LocVT == MVT::v16i8 ||
1001
33
      LocVT == MVT::v8i16 ||
1002
33
      LocVT == MVT::v4i32 ||
1003
33
      LocVT == MVT::v2i64 ||
1004
33
      LocVT == MVT::v4f32 ||
1005
33
      
LocVT == MVT::v2f6413
) {
1006
20
    unsigned Offset12 = State.AllocateStack(16, 16);
1007
20
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo));
1008
20
    return false;
1009
20
  }
1010
13
1011
13
  if (LocVT == MVT::v32i8 ||
1012
13
      LocVT == MVT::v16i16 ||
1013
13
      LocVT == MVT::v8i32 ||
1014
13
      LocVT == MVT::v4i64 ||
1015
13
      LocVT == MVT::v8f32 ||
1016
13
      LocVT == MVT::v4f64) {
1017
0
    unsigned Offset13 = State.AllocateStack(32, 32);
1018
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo));
1019
0
    return false;
1020
0
  }
1021
13
1022
13
  if (LocVT == MVT::v16i32 ||
1023
13
      LocVT == MVT::v8i64 ||
1024
13
      LocVT == MVT::v16f32 ||
1025
13
      
LocVT == MVT::v8f643
) {
1026
10
    unsigned Offset14 = State.AllocateStack(64, 64);
1027
10
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo));
1028
10
    return false;
1029
10
  }
1030
3
1031
3
  return true;  // CC didn't match.
1032
3
}
1033
1034
1035
static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT,
1036
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
1037
448
                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
1038
448
1039
448
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetCygMing()) {
1040
40
    if (!CC_X86_32_ThisCall_Mingw(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1041
40
      return false;
1042
408
  }
1043
408
1044
408
  if (!CC_X86_32_ThisCall_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1045
408
    return false;
1046
0
1047
0
  return true;  // CC didn't match.
1048
0
}
1049
1050
1051
static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT,
1052
                                      MVT LocVT, CCValAssign::LocInfo LocInfo,
1053
424
                                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1054
424
1055
424
  if (LocVT == MVT::i32) {
1056
414
    if (unsigned Reg = State.AllocateReg(X86::ECX)) {
1057
232
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1058
232
      return false;
1059
232
    }
1060
192
  }
1061
192
1062
192
  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1063
192
    return false;
1064
0
1065
0
  return true;  // CC didn't match.
1066
0
}
1067
1068
1069
static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT,
1070
                                     MVT LocVT, CCValAssign::LocInfo LocInfo,
1071
40
                                     ISD::ArgFlagsTy ArgFlags, CCState &State) {
1072
40
1073
40
  if (LocVT == MVT::i1 ||
1074
40
      LocVT == MVT::i8 ||
1075
40
      LocVT == MVT::i16 ||
1076
40
      LocVT == MVT::v1i1) {
1077
0
    LocVT = MVT::i32;
1078
0
    if (ArgFlags.isSExt())
1079
0
        LocInfo = CCValAssign::SExt;
1080
0
    else if (ArgFlags.isZExt())
1081
0
        LocInfo = CCValAssign::ZExt;
1082
0
    else
1083
0
        LocInfo = CCValAssign::AExt;
1084
0
  }
1085
40
1086
40
  if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1087
40
    return false;
1088
0
1089
0
  return true;  // CC didn't match.
1090
0
}
1091
1092
1093
static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT,
1094
                                   MVT LocVT, CCValAssign::LocInfo LocInfo,
1095
408
                                   ISD::ArgFlagsTy ArgFlags, CCState &State) {
1096
408
1097
408
  if (LocVT == MVT::i1 ||
1098
408
      LocVT == MVT::i8 ||
1099
408
      
LocVT == MVT::i16407
||
1100
408
      
LocVT == MVT::v1i1407
) {
1101
1
    LocVT = MVT::i32;
1102
1
    if (ArgFlags.isSExt())
1103
0
        LocInfo = CCValAssign::SExt;
1104
1
    else if (ArgFlags.isZExt())
1105
0
        LocInfo = CCValAssign::ZExt;
1106
1
    else
1107
1
        LocInfo = CCValAssign::AExt;
1108
1
  }
1109
408
1110
408
  if (ArgFlags.isSRet()) {
1111
24
    unsigned Offset1 = State.AllocateStack(4, 4);
1112
24
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1113
24
    return false;
1114
24
  }
1115
384
1116
384
  if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1117
384
    return false;
1118
0
1119
0
  return true;  // CC didn't match.
1120
0
}
1121
1122
1123
static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT,
1124
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
1125
249
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
1126
249
1127
249
  if (LocVT == MVT::v16i8 ||
1128
249
      
LocVT == MVT::v8i16247
||
1129
249
      
LocVT == MVT::v4i32224
||
1130
249
      
LocVT == MVT::v2i64204
||
1131
249
      
LocVT == MVT::v4f32195
||
1132
249
      
LocVT == MVT::v2f64120
) {
1133
151
    unsigned Offset1 = State.AllocateStack(16, 16);
1134
151
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1135
151
    return false;
1136
151
  }
1137
98
1138
98
  if (LocVT == MVT::v32i8 ||
1139
98
      
LocVT == MVT::v16i1696
||
1140
98
      
LocVT == MVT::v8i3294
||
1141
98
      
LocVT == MVT::v4i6487
||
1142
98
      
LocVT == MVT::v8f3284
||
1143
98
      
LocVT == MVT::v4f6466
) {
1144
42
    unsigned Offset2 = State.AllocateStack(32, 32);
1145
42
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1146
42
    return false;
1147
42
  }
1148
56
1149
56
  if (LocVT == MVT::v64i8 ||
1150
56
      
LocVT == MVT::v32i1646
||
1151
56
      
LocVT == MVT::v16i3240
||
1152
56
      
LocVT == MVT::v8i6439
||
1153
56
      
LocVT == MVT::v16f3222
||
1154
56
      
LocVT == MVT::v8f6417
) {
1155
50
    unsigned Offset3 = State.AllocateStack(64, 64);
1156
50
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
1157
50
    return false;
1158
50
  }
1159
6
1160
6
  return true;  // CC didn't match.
1161
6
}
1162
1163
1164
static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT,
1165
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
1166
4.05k
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
1167
4.05k
1168
4.05k
  if (!State.isVarArg()) {
1169
4.05k
    if (LocVT == MVT::v16i8 ||
1170
4.05k
        
LocVT == MVT::v8i163.68k
||
1171
4.05k
        
LocVT == MVT::v4i323.31k
||
1172
4.05k
        
LocVT == MVT::v2i642.94k
||
1173
4.05k
        
LocVT == MVT::v4f322.72k
||
1174
4.05k
        
LocVT == MVT::v2f642.03k
) {
1175
2.41k
      static const MCPhysReg RegList1[] = {
1176
2.41k
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1177
2.41k
      };
1178
2.41k
      if (unsigned Reg = State.AllocateReg(RegList1)) {
1179
2.40k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1180
2.40k
        return false;
1181
2.40k
      }
1182
1.64k
    }
1183
4.05k
  }
1184
1.64k
1185
1.64k
  if (!State.isVarArg()) {
1186
1.64k
    if (LocVT == MVT::v32i8 ||
1187
1.64k
        
LocVT == MVT::v16i161.56k
||
1188
1.64k
        
LocVT == MVT::v8i321.46k
||
1189
1.64k
        
LocVT == MVT::v4i641.36k
||
1190
1.64k
        
LocVT == MVT::v8f321.30k
||
1191
1.64k
        
LocVT == MVT::v4f641.22k
) {
1192
479
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1193
479
        static const MCPhysReg RegList2[] = {
1194
479
          X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
1195
479
        };
1196
479
        if (unsigned Reg = State.AllocateReg(RegList2)) {
1197
459
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1198
459
          return false;
1199
459
        }
1200
1.18k
      }
1201
479
    }
1202
1.64k
  }
1203
1.18k
1204
1.18k
  if (!State.isVarArg()) {
1205
1.18k
    if (LocVT == MVT::v64i8 ||
1206
1.18k
        
LocVT == MVT::v32i161.18k
||
1207
1.18k
        
LocVT == MVT::v16i321.17k
||
1208
1.18k
        
LocVT == MVT::v8i64871
||
1209
1.18k
        
LocVT == MVT::v16f32624
||
1210
1.18k
        
LocVT == MVT::v8f64242
) {
1211
1.16k
      static const MCPhysReg RegList3[] = {
1212
1.16k
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
1213
1.16k
      };
1214
1.16k
      if (unsigned Reg = State.AllocateReg(RegList3)) {
1215
1.15k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1216
1.15k
        return false;
1217
1.15k
      }
1218
30
    }
1219
1.18k
  }
1220
30
1221
30
  if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1222
30
    return false;
1223
0
1224
0
  return true;  // CC didn't match.
1225
0
}
1226
1227
1228
static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT,
1229
                                      MVT LocVT, CCValAssign::LocInfo LocInfo,
1230
16.5k
                                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1231
16.5k
1232
16.5k
  if (!State.isVarArg()) {
1233
16.5k
    if (LocVT == MVT::v16i8 ||
1234
16.5k
        
LocVT == MVT::v8i1615.8k
||
1235
16.5k
        
LocVT == MVT::v4i3214.9k
||
1236
16.5k
        
LocVT == MVT::v2i6413.8k
||
1237
16.5k
        
LocVT == MVT::v4f3211.5k
||
1238
16.5k
        
LocVT == MVT::v2f649.41k
) {
1239
8.71k
      static const MCPhysReg RegList1[] = {
1240
8.71k
        X86::XMM0, X86::XMM1, X86::XMM2
1241
8.71k
      };
1242
8.71k
      if (unsigned Reg = State.AllocateReg(RegList1)) {
1243
8.57k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1244
8.57k
        return false;
1245
8.57k
      }
1246
7.94k
    }
1247
16.5k
  }
1248
7.94k
1249
7.94k
  if (!State.isVarArg()) {
1250
7.94k
    if (LocVT == MVT::v32i8 ||
1251
7.94k
        
LocVT == MVT::v16i167.51k
||
1252
7.94k
        
LocVT == MVT::v8i326.90k
||
1253
7.94k
        
LocVT == MVT::v4i646.18k
||
1254
7.94k
        
LocVT == MVT::v8f324.98k
||
1255
7.94k
        
LocVT == MVT::v4f644.11k
) {
1256
4.47k
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1257
4.47k
        static const MCPhysReg RegList2[] = {
1258
4.47k
          X86::YMM0, X86::YMM1, X86::YMM2
1259
4.47k
        };
1260
4.47k
        if (unsigned Reg = State.AllocateReg(RegList2)) {
1261
4.44k
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1262
4.44k
          return false;
1263
4.44k
        }
1264
3.50k
      }
1265
4.47k
    }
1266
7.94k
  }
1267
3.50k
1268
3.50k
  if (!State.isVarArg()) {
1269
3.49k
    if (LocVT == MVT::v64i8 ||
1270
3.49k
        
LocVT == MVT::v32i163.27k
||
1271
3.49k
        
LocVT == MVT::v16i322.81k
||
1272
3.49k
        
LocVT == MVT::v8i642.48k
||
1273
3.49k
        
LocVT == MVT::v16f321.53k
||
1274
3.49k
        
LocVT == MVT::v8f64848
) {
1275
3.33k
      static const MCPhysReg RegList3[] = {
1276
3.33k
        X86::ZMM0, X86::ZMM1, X86::ZMM2
1277
3.33k
      };
1278
3.33k
      if (unsigned Reg = State.AllocateReg(RegList3)) {
1279
3.28k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1280
3.28k
        return false;
1281
3.28k
      }
1282
219
    }
1283
3.49k
  }
1284
219
1285
219
  if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1286
213
    return false;
1287
6
1288
6
  return true;  // CC didn't match.
1289
6
}
1290
1291
1292
static bool CC_X86_64(unsigned ValNo, MVT ValVT,
1293
                      MVT LocVT, CCValAssign::LocInfo LocInfo,
1294
493k
                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1295
493k
1296
493k
  if (State.getCallingConv() == CallingConv::GHC) {
1297
62
    if (!CC_X86_64_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1298
62
      return false;
1299
493k
  }
1300
493k
1301
493k
  if (State.getCallingConv() == CallingConv::HiPE) {
1302
42
    if (!CC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1303
42
      return false;
1304
493k
  }
1305
493k
1306
493k
  if (State.getCallingConv() == CallingConv::WebKit_JS) {
1307
69
    if (!CC_X86_64_WebKit_JS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1308
69
      return false;
1309
493k
  }
1310
493k
1311
493k
  if (State.getCallingConv() == CallingConv::AnyReg) {
1312
0
    if (!CC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1313
0
      return false;
1314
493k
  }
1315
493k
1316
493k
  if (State.getCallingConv() == CallingConv::Win64) {
1317
55
    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1318
55
      return false;
1319
493k
  }
1320
493k
1321
493k
  if (State.getCallingConv() == CallingConv::X86_64_SysV) {
1322
22
    if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1323
22
      return false;
1324
493k
  }
1325
493k
1326
493k
  if (State.getCallingConv() == CallingConv::X86_VectorCall) {
1327
152
    if (!CC_X86_Win64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1328
152
      return false;
1329
493k
  }
1330
493k
1331
493k
  if (State.getCallingConv() == CallingConv::HHVM) {
1332
112
    if (!CC_X86_64_HHVM(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1333
112
      return false;
1334
493k
  }
1335
493k
1336
493k
  if (State.getCallingConv() == CallingConv::HHVM_C) {
1337
25
    if (!CC_X86_64_HHVM_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1338
25
      return false;
1339
493k
  }
1340
493k
1341
493k
  if (State.getCallingConv() == CallingConv::X86_RegCall) {
1342
398
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
1343
204
      if (!CC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1344
201
        return false;
1345
493k
    }
1346
398
  }
1347
493k
1348
493k
  if (State.getCallingConv() == CallingConv::X86_RegCall) {
1349
197
    if (!CC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1350
191
      return false;
1351
492k
  }
1352
492k
1353
492k
  if (State.getCallingConv() == CallingConv::X86_INTR) {
1354
20
    if (!CC_X86_64_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1355
20
      return false;
1356
492k
  }
1357
492k
1358
492k
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
1359
2.88k
    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1360
2.87k
      return false;
1361
489k
  }
1362
489k
1363
489k
  if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1364
489k
    return false;
1365
214
1366
214
  return true;  // CC didn't match.
1367
214
}
1368
1369
1370
static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
1371
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
1372
0
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
1373
0
1374
0
  if (CC_X86_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1375
0
    return false;
1376
0
1377
0
  return true;  // CC didn't match.
1378
0
}
1379
1380
1381
static bool CC_X86_64_C(unsigned ValNo, MVT ValVT,
1382
                        MVT LocVT, CCValAssign::LocInfo LocInfo,
1383
489k
                        ISD::ArgFlagsTy ArgFlags, CCState &State) {
1384
489k
1385
489k
  if (ArgFlags.isByVal()) {
1386
597
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
1387
597
    return false;
1388
597
  }
1389
489k
1390
489k
  if (LocVT == MVT::i1 ||
1391
489k
      
LocVT == MVT::i8489k
||
1392
489k
      
LocVT == MVT::i16466k
||
1393
489k
      
LocVT == MVT::v1i1463k
) {
1394
25.9k
    LocVT = MVT::i32;
1395
25.9k
    if (ArgFlags.isSExt())
1396
419
        LocInfo = CCValAssign::SExt;
1397
25.5k
    else if (ArgFlags.isZExt())
1398
17.6k
        LocInfo = CCValAssign::ZExt;
1399
7.85k
    else
1400
7.85k
        LocInfo = CCValAssign::AExt;
1401
25.9k
  }
1402
489k
1403
489k
  if (ArgFlags.isNest()) {
1404
25
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTarget64BitILP32()) {
1405
2
      if (unsigned Reg = State.AllocateReg(X86::R10D)) {
1406
2
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1407
2
        return false;
1408
2
      }
1409
489k
    }
1410
25
  }
1411
489k
1412
489k
  if (ArgFlags.isNest()) {
1413
23
    if (unsigned Reg = State.AllocateReg(X86::R10)) {
1414
23
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1415
23
      return false;
1416
23
    }
1417
489k
  }
1418
489k
1419
489k
  if (ArgFlags.isSwiftSelf()) {
1420
40
    if (LocVT == MVT::i64) {
1421
40
      if (unsigned Reg = State.AllocateReg(X86::R13)) {
1422
40
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1423
40
        return false;
1424
40
      }
1425
489k
    }
1426
40
  }
1427
489k
1428
489k
  if (ArgFlags.isSwiftError()) {
1429
74
    if (LocVT == MVT::i64) {
1430
74
      if (unsigned Reg = State.AllocateReg(X86::R12)) {
1431
74
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1432
74
        return false;
1433
74
      }
1434
489k
    }
1435
74
  }
1436
489k
1437
489k
  if (State.getCallingConv() == CallingConv::Swift) {
1438
134
    if (ArgFlags.isSRet()) {
1439
6
      if (LocVT == MVT::i64) {
1440
6
        if (unsigned Reg = State.AllocateReg(X86::RAX)) {
1441
6
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1442
6
          return false;
1443
6
        }
1444
489k
      }
1445
6
    }
1446
134
  }
1447
489k
1448
489k
  if (LocVT == MVT::i32) {
1449
69.1k
    static const MCPhysReg RegList1[] = {
1450
69.1k
      X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1451
69.1k
    };
1452
69.1k
    if (unsigned Reg = State.AllocateReg(RegList1)) {
1453
59.3k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1454
59.3k
      return false;
1455
59.3k
    }
1456
429k
  }
1457
429k
1458
429k
  if (LocVT == MVT::i64) {
1459
306k
    static const MCPhysReg RegList2[] = {
1460
306k
      X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1461
306k
    };
1462
306k
    if (unsigned Reg = State.AllocateReg(RegList2)) {
1463
299k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1464
299k
      return false;
1465
299k
    }
1466
130k
  }
1467
130k
1468
130k
  if (LocVT == MVT::x86mmx) {
1469
215
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()) {
1470
12
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
1471
12
        LocVT = MVT::v2i64;
1472
12
        if (ArgFlags.isSExt())
1473
0
                LocInfo = CCValAssign::SExt;
1474
12
        else if (ArgFlags.isZExt())
1475
0
                LocInfo = CCValAssign::ZExt;
1476
12
        else
1477
12
                LocInfo = CCValAssign::AExt;
1478
12
      }
1479
12
    }
1480
215
  }
1481
130k
1482
130k
  if (LocVT == MVT::v2i1) {
1483
105
    LocVT = MVT::v2i64;
1484
105
    if (ArgFlags.isSExt())
1485
0
        LocInfo = CCValAssign::SExt;
1486
105
    else if (ArgFlags.isZExt())
1487
0
        LocInfo = CCValAssign::ZExt;
1488
105
    else
1489
105
        LocInfo = CCValAssign::AExt;
1490
105
  }
1491
130k
1492
130k
  if (LocVT == MVT::v4i1) {
1493
139
    LocVT = MVT::v4i32;
1494
139
    if (ArgFlags.isSExt())
1495
0
        LocInfo = CCValAssign::SExt;
1496
139
    else if (ArgFlags.isZExt())
1497
0
        LocInfo = CCValAssign::ZExt;
1498
139
    else
1499
139
        LocInfo = CCValAssign::AExt;
1500
139
  }
1501
130k
1502
130k
  if (LocVT == MVT::v8i1) {
1503
112
    LocVT = MVT::v8i16;
1504
112
    if (ArgFlags.isSExt())
1505
0
        LocInfo = CCValAssign::SExt;
1506
112
    else if (ArgFlags.isZExt())
1507
0
        LocInfo = CCValAssign::ZExt;
1508
112
    else
1509
112
        LocInfo = CCValAssign::AExt;
1510
112
  }
1511
130k
1512
130k
  if (LocVT == MVT::v16i1) {
1513
156
    LocVT = MVT::v16i8;
1514
156
    if (ArgFlags.isSExt())
1515
0
        LocInfo = CCValAssign::SExt;
1516
156
    else if (ArgFlags.isZExt())
1517
0
        LocInfo = CCValAssign::ZExt;
1518
156
    else
1519
156
        LocInfo = CCValAssign::AExt;
1520
156
  }
1521
130k
1522
130k
  if (LocVT == MVT::v32i1) {
1523
24
    LocVT = MVT::v32i8;
1524
24
    if (ArgFlags.isSExt())
1525
0
        LocInfo = CCValAssign::SExt;
1526
24
    else if (ArgFlags.isZExt())
1527
0
        LocInfo = CCValAssign::ZExt;
1528
24
    else
1529
24
        LocInfo = CCValAssign::AExt;
1530
24
  }
1531
130k
1532
130k
  if (LocVT == MVT::v64i1) {
1533
5
    LocVT = MVT::v64i8;
1534
5
    if (ArgFlags.isSExt())
1535
0
        LocInfo = CCValAssign::SExt;
1536
5
    else if (ArgFlags.isZExt())
1537
0
        LocInfo = CCValAssign::ZExt;
1538
5
    else
1539
5
        LocInfo = CCValAssign::AExt;
1540
5
  }
1541
130k
1542
130k
  if (LocVT == MVT::f32 ||
1543
130k
      
LocVT == MVT::f64127k
||
1544
130k
      
LocVT == MVT::f128124k
||
1545
130k
      
LocVT == MVT::v16i8123k
||
1546
130k
      
LocVT == MVT::v8i16115k
||
1547
130k
      
LocVT == MVT::v4i32105k
||
1548
130k
      
LocVT == MVT::v2i6492.6k
||
1549
130k
      
LocVT == MVT::v4f3279.7k
||
1550
130k
      
LocVT == MVT::v2f6470.5k
) {
1551
66.1k
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1552
66.1k
      static const MCPhysReg RegList3[] = {
1553
66.1k
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1554
66.1k
      };
1555
66.1k
      if (unsigned Reg = State.AllocateReg(RegList3)) {
1556
63.9k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1557
63.9k
        return false;
1558
63.9k
      }
1559
66.7k
    }
1560
66.1k
  }
1561
66.7k
1562
66.7k
  if (!State.isVarArg()) {
1563
65.8k
    if (LocVT == MVT::v32i8 ||
1564
65.8k
        
LocVT == MVT::v16i1660.8k
||
1565
65.8k
        
LocVT == MVT::v8i3254.6k
||
1566
65.8k
        
LocVT == MVT::v4i6448.6k
||
1567
65.8k
        
LocVT == MVT::v8f3242.1k
||
1568
65.8k
        
LocVT == MVT::v4f6437.3k
) {
1569
32.6k
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1570
32.6k
        static const MCPhysReg RegList4[] = {
1571
32.6k
          X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
1572
32.6k
        };
1573
32.6k
        if (unsigned Reg = State.AllocateReg(RegList4)) {
1574
32.5k
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1575
32.5k
          return false;
1576
32.5k
        }
1577
34.2k
      }
1578
32.6k
    }
1579
65.8k
  }
1580
34.2k
1581
34.2k
  if (!State.isVarArg()) {
1582
33.3k
    if (LocVT == MVT::v64i8 ||
1583
33.3k
        
LocVT == MVT::v32i1632.4k
||
1584
33.3k
        
LocVT == MVT::v16i3231.2k
||
1585
33.3k
        
LocVT == MVT::v8i6428.3k
||
1586
33.3k
        
LocVT == MVT::v16f3224.2k
||
1587
33.3k
        
LocVT == MVT::v8f6421.5k
) {
1588
14.2k
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
1589
14.2k
        static const MCPhysReg RegList5[] = {
1590
14.2k
          X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
1591
14.2k
        };
1592
14.2k
        if (unsigned Reg = State.AllocateReg(RegList5)) {
1593
14.2k
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1594
14.2k
          return false;
1595
14.2k
        }
1596
19.9k
      }
1597
14.2k
    }
1598
33.3k
  }
1599
19.9k
1600
19.9k
  if (LocVT == MVT::i32 ||
1601
19.9k
      
LocVT == MVT::i6410.1k
||
1602
19.9k
      
LocVT == MVT::f323.16k
||
1603
19.9k
      
LocVT == MVT::f643.11k
) {
1604
16.8k
    unsigned Offset6 = State.AllocateStack(8, 8);
1605
16.8k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
1606
16.8k
    return false;
1607
16.8k
  }
1608
3.11k
1609
3.11k
  if (LocVT == MVT::f80 ||
1610
3.11k
      
LocVT == MVT::f1282.52k
) {
1611
710
    unsigned Offset7 = State.AllocateStack(
1612
710
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 
1613
710
      State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
1614
710
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
1615
710
    return false;
1616
710
  }
1617
2.40k
1618
2.40k
  if (LocVT == MVT::v16i8 ||
1619
2.40k
      
LocVT == MVT::v8i162.29k
||
1620
2.40k
      
LocVT == MVT::v4i322.20k
||
1621
2.40k
      
LocVT == MVT::v2i642.07k
||
1622
2.40k
      
LocVT == MVT::v4f32499
||
1623
2.40k
      
LocVT == MVT::v2f64444
) {
1624
2.05k
    unsigned Offset8 = State.AllocateStack(16, 16);
1625
2.05k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
1626
2.05k
    return false;
1627
2.05k
  }
1628
343
1629
343
  if (LocVT == MVT::v32i8 ||
1630
343
      
LocVT == MVT::v16i16272
||
1631
343
      
LocVT == MVT::v8i32272
||
1632
343
      
LocVT == MVT::v4i64272
||
1633
343
      
LocVT == MVT::v8f32236
||
1634
343
      
LocVT == MVT::v4f64231
) {
1635
129
    unsigned Offset9 = State.AllocateStack(32, 32);
1636
129
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
1637
129
    return false;
1638
129
  }
1639
214
1640
214
  if (LocVT == MVT::v16i32 ||
1641
215
      LocVT == MVT::v8i64 ||
1642
215
      LocVT == MVT::v16f32 ||
1643
215
      LocVT == MVT::v8f64) {
1644
0
    unsigned Offset10 = State.AllocateStack(64, 64);
1645
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
1646
0
    return false;
1647
0
  }
1648
214
1649
214
  return true;  // CC didn't match.
1650
214
}
1651
1652
1653
static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT,
1654
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
1655
62
                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
1656
62
1657
62
  if (LocVT == MVT::i8 ||
1658
62
      LocVT == MVT::i16 ||
1659
62
      LocVT == MVT::i32) {
1660
0
    LocVT = MVT::i64;
1661
0
    if (ArgFlags.isSExt())
1662
0
        LocInfo = CCValAssign::SExt;
1663
0
    else if (ArgFlags.isZExt())
1664
0
        LocInfo = CCValAssign::ZExt;
1665
0
    else
1666
0
        LocInfo = CCValAssign::AExt;
1667
0
  }
1668
62
1669
62
  if (LocVT == MVT::i64) {
1670
56
    static const MCPhysReg RegList1[] = {
1671
56
      X86::R13, X86::RBP, X86::R12, X86::RBX, X86::R14, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R15
1672
56
    };
1673
56
    if (unsigned Reg = State.AllocateReg(RegList1)) {
1674
56
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1675
56
      return false;
1676
56
    }
1677
6
  }
1678
6
1679
6
  if (LocVT == MVT::f32 ||
1680
6
      
LocVT == MVT::f642
||
1681
6
      
LocVT == MVT::v16i80
||
1682
6
      
LocVT == MVT::v8i160
||
1683
6
      
LocVT == MVT::v4i320
||
1684
6
      
LocVT == MVT::v2i640
||
1685
6
      
LocVT == MVT::v4f320
||
1686
6
      
LocVT == MVT::v2f640
) {
1687
6
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1688
6
      static const MCPhysReg RegList2[] = {
1689
6
        X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6
1690
6
      };
1691
6
      if (unsigned Reg = State.AllocateReg(RegList2)) {
1692
6
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1693
6
        return false;
1694
6
      }
1695
0
    }
1696
6
  }
1697
0
1698
0
  if (LocVT == MVT::v32i8 ||
1699
0
      LocVT == MVT::v16i16 ||
1700
0
      LocVT == MVT::v8i32 ||
1701
0
      LocVT == MVT::v4i64 ||
1702
0
      LocVT == MVT::v8f32 ||
1703
0
      LocVT == MVT::v4f64) {
1704
0
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1705
0
      static const MCPhysReg RegList3[] = {
1706
0
        X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6
1707
0
      };
1708
0
      if (unsigned Reg = State.AllocateReg(RegList3)) {
1709
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1710
0
        return false;
1711
0
      }
1712
0
    }
1713
0
  }
1714
0
1715
0
  if (LocVT == MVT::v64i8 ||
1716
0
      LocVT == MVT::v32i16 ||
1717
0
      LocVT == MVT::v16i32 ||
1718
0
      LocVT == MVT::v8i64 ||
1719
0
      LocVT == MVT::v16f32 ||
1720
0
      LocVT == MVT::v8f64) {
1721
0
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
1722
0
      static const MCPhysReg RegList4[] = {
1723
0
        X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6
1724
0
      };
1725
0
      if (unsigned Reg = State.AllocateReg(RegList4)) {
1726
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1727
0
        return false;
1728
0
      }
1729
0
    }
1730
0
  }
1731
0
1732
0
  return true;  // CC didn't match.
1733
0
}
1734
1735
1736
static bool CC_X86_64_HHVM(unsigned ValNo, MVT ValVT,
1737
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
1738
112
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
1739
112
1740
112
  if (LocVT == MVT::i64) {
1741
112
    static const MCPhysReg RegList1[] = {
1742
112
      X86::RBX, X86::R12, X86::RBP, X86::R15, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9, X86::RAX, X86::R10, X86::R11, X86::R13, X86::R14
1743
112
    };
1744
112
    if (unsigned Reg = State.AllocateReg(RegList1)) {
1745
112
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1746
112
      return false;
1747
112
    }
1748
0
  }
1749
0
1750
0
  return true;  // CC didn't match.
1751
0
}
1752
1753
1754
static bool CC_X86_64_HHVM_C(unsigned ValNo, MVT ValVT,
1755
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
1756
25
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
1757
25
1758
25
  if (LocVT == MVT::i64) {
1759
24
    if (unsigned Reg = State.AllocateReg(X86::RBP)) {
1760
5
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1761
5
      return false;
1762
5
    }
1763
20
  }
1764
20
1765
20
  if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1766
20
    return false;
1767
0
1768
0
  return true;  // CC didn't match.
1769
0
}
1770
1771
1772
static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
1773
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
1774
42
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
1775
42
1776
42
  if (LocVT == MVT::i8 ||
1777
42
      LocVT == MVT::i16 ||
1778
42
      LocVT == MVT::i32) {
1779
6
    LocVT = MVT::i64;
1780
6
    if (ArgFlags.isSExt())
1781
0
        LocInfo = CCValAssign::SExt;
1782
6
    else if (ArgFlags.isZExt())
1783
0
        LocInfo = CCValAssign::ZExt;
1784
6
    else
1785
6
        LocInfo = CCValAssign::AExt;
1786
6
  }
1787
42
1788
42
  if (LocVT == MVT::i64) {
1789
42
    static const MCPhysReg RegList1[] = {
1790
42
      X86::R15, X86::RBP, X86::RSI, X86::RDX, X86::RCX, X86::R8
1791
42
    };
1792
42
    if (unsigned Reg = State.AllocateReg(RegList1)) {
1793
41
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1794
41
      return false;
1795
41
    }
1796
1
  }
1797
1
1798
1
  if (LocVT == MVT::i32 ||
1799
1
      LocVT == MVT::i64 ||
1800
1
      
LocVT == MVT::f320
||
1801
1
      
LocVT == MVT::f640
) {
1802
1
    unsigned Offset2 = State.AllocateStack(8, 8);
1803
1
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1804
1
    return false;
1805
1
  }
1806
0
1807
0
  return true;  // CC didn't match.
1808
0
}
1809
1810
1811
static bool CC_X86_64_Intr(unsigned ValNo, MVT ValVT,
1812
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
1813
20
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
1814
20
1815
20
  unsigned Offset1 = State.AllocateStack(8, 8);
1816
20
  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1817
20
  return false;
1818
20
1819
20
  
return true0
; // CC didn't match.
1820
20
}
1821
1822
1823
static bool CC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT,
1824
                                MVT LocVT, CCValAssign::LocInfo LocInfo,
1825
69
                                ISD::ArgFlagsTy ArgFlags, CCState &State) {
1826
69
1827
69
  if (LocVT == MVT::i8 ||
1828
69
      LocVT == MVT::i16) {
1829
0
    LocVT = MVT::i32;
1830
0
    if (ArgFlags.isSExt())
1831
0
        LocInfo = CCValAssign::SExt;
1832
0
    else if (ArgFlags.isZExt())
1833
0
        LocInfo = CCValAssign::ZExt;
1834
0
    else
1835
0
        LocInfo = CCValAssign::AExt;
1836
0
  }
1837
69
1838
69
  if (LocVT == MVT::i32) {
1839
26
    if (unsigned Reg = State.AllocateReg(X86::EAX)) {
1840
4
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1841
4
      return false;
1842
4
    }
1843
65
  }
1844
65
1845
65
  if (LocVT == MVT::i64) {
1846
43
    if (unsigned Reg = State.AllocateReg(X86::RAX)) {
1847
9
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1848
9
      return false;
1849
9
    }
1850
56
  }
1851
56
1852
56
  if (LocVT == MVT::i32 ||
1853
56
      
LocVT == MVT::f3234
) {
1854
22
    unsigned Offset1 = State.AllocateStack(4, 4);
1855
22
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1856
22
    return false;
1857
22
  }
1858
34
1859
34
  if (LocVT == MVT::i64 ||
1860
34
      
LocVT == MVT::f640
) {
1861
34
    unsigned Offset2 = State.AllocateStack(8, 8);
1862
34
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1863
34
    return false;
1864
34
  }
1865
0
1866
0
  return true;  // CC didn't match.
1867
0
}
1868
1869
1870
static bool CC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
1871
                                  MVT LocVT, CCValAssign::LocInfo LocInfo,
1872
197
                                  ISD::ArgFlagsTy ArgFlags, CCState &State) {
1873
197
1874
197
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
1875
197
    if (ArgFlags.isByVal()) {
1876
0
      State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
1877
0
      return false;
1878
0
    }
1879
197
  }
1880
197
1881
197
  if (ArgFlags.isByVal()) {
1882
0
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
1883
0
    return false;
1884
0
  }
1885
197
1886
197
  if (LocVT == MVT::i1 ||
1887
197
      LocVT == MVT::i8 ||
1888
197
      
LocVT == MVT::i16186
||
1889
197
      
LocVT == MVT::v1i1182
) {
1890
15
    LocVT = MVT::i32;
1891
15
    if (ArgFlags.isSExt())
1892
2
        LocInfo = CCValAssign::SExt;
1893
13
    else if (ArgFlags.isZExt())
1894
0
        LocInfo = CCValAssign::ZExt;
1895
13
    else
1896
13
        LocInfo = CCValAssign::AExt;
1897
15
  }
1898
197
1899
197
  if (LocVT == MVT::v8i1 ||
1900
197
      
LocVT == MVT::v16i1188
||
1901
197
      
LocVT == MVT::v32i1179
) {
1902
24
    LocVT = MVT::i32;
1903
24
    if (ArgFlags.isSExt())
1904
0
        LocInfo = CCValAssign::SExt;
1905
24
    else if (ArgFlags.isZExt())
1906
0
        LocInfo = CCValAssign::ZExt;
1907
24
    else
1908
24
        LocInfo = CCValAssign::AExt;
1909
24
  }
1910
197
1911
197
  if (LocVT == MVT::i32) {
1912
68
    static const MCPhysReg RegList1[] = {
1913
68
      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D
1914
68
    };
1915
68
    if (unsigned Reg = State.AllocateReg(RegList1)) {
1916
66
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1917
66
      return false;
1918
66
    }
1919
131
  }
1920
131
1921
131
  if (LocVT == MVT::i64) {
1922
9
    static const MCPhysReg RegList2[] = {
1923
9
      X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
1924
9
    };
1925
9
    if (unsigned Reg = State.AllocateReg(RegList2)) {
1926
9
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1927
9
      return false;
1928
9
    }
1929
122
  }
1930
122
1931
122
  if (LocVT == MVT::v64i1) {
1932
26
    LocVT = MVT::i64;
1933
26
    if (ArgFlags.isSExt())
1934
0
        LocInfo = CCValAssign::SExt;
1935
26
    else if (ArgFlags.isZExt())
1936
0
        LocInfo = CCValAssign::ZExt;
1937
26
    else
1938
26
        LocInfo = CCValAssign::AExt;
1939
26
  }
1940
122
1941
122
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
1942
122
    if (LocVT == MVT::i64) {
1943
26
      static const MCPhysReg RegList3[] = {
1944
26
        X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
1945
26
      };
1946
26
      if (unsigned Reg = State.AllocateReg(RegList3)) {
1947
22
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1948
22
        return false;
1949
22
      }
1950
100
    }
1951
122
  }
1952
100
1953
100
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
1954
0
    if (LocVT == MVT::i64) {
1955
0
      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1956
0
            return false;
1957
100
    }
1958
0
  }
1959
100
1960
100
  if (LocVT == MVT::f32 ||
1961
100
      
LocVT == MVT::f6495
||
1962
100
      
LocVT == MVT::f12890
) {
1963
10
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1964
10
      static const MCPhysReg RegList4[] = {
1965
10
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
1966
10
      };
1967
10
      if (unsigned Reg = State.AllocateReg(RegList4)) {
1968
10
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1969
10
        return false;
1970
10
      }
1971
90
    }
1972
10
  }
1973
90
1974
90
  if (LocVT == MVT::f80) {
1975
3
    if (unsigned Reg = State.AllocateReg(X86::FP0)) {
1976
3
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1977
3
      return false;
1978
3
    }
1979
87
  }
1980
87
1981
87
  if (LocVT == MVT::v16i8 ||
1982
87
      LocVT == MVT::v8i16 ||
1983
87
      LocVT == MVT::v4i32 ||
1984
87
      
LocVT == MVT::v2i6482
||
1985
87
      
LocVT == MVT::v4f3282
||
1986
87
      
LocVT == MVT::v2f6446
) {
1987
41
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1988
41
      static const MCPhysReg RegList5[] = {
1989
41
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
1990
41
      };
1991
41
      if (unsigned Reg = State.AllocateReg(RegList5)) {
1992
33
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1993
33
        return false;
1994
33
      }
1995
54
    }
1996
41
  }
1997
54
1998
54
  if (LocVT == MVT::v32i8 ||
1999
54
      LocVT == MVT::v16i16 ||
2000
54
      LocVT == MVT::v8i32 ||
2001
54
      
LocVT == MVT::v4i6449
||
2002
54
      
LocVT == MVT::v8f3249
||
2003
54
      
LocVT == MVT::v4f6449
) {
2004
5
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
2005
5
      static const MCPhysReg RegList6[] = {
2006
5
        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
2007
5
      };
2008
5
      if (unsigned Reg = State.AllocateReg(RegList6)) {
2009
5
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2010
5
        return false;
2011
5
      }
2012
49
    }
2013
5
  }
2014
49
2015
49
  if (LocVT == MVT::v64i8 ||
2016
49
      LocVT == MVT::v32i16 ||
2017
49
      LocVT == MVT::v16i32 ||
2018
49
      
LocVT == MVT::v8i6444
||
2019
49
      
LocVT == MVT::v16f3244
||
2020
49
      
LocVT == MVT::v8f6420
) {
2021
29
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
2022
29
      static const MCPhysReg RegList7[] = {
2023
29
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
2024
29
      };
2025
29
      if (unsigned Reg = State.AllocateReg(RegList7)) {
2026
27
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2027
27
        return false;
2028
27
      }
2029
22
    }
2030
29
  }
2031
22
2032
22
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2033
22
    if (LocVT == MVT::i32 ||
2034
22
        
LocVT == MVT::i6420
||
2035
22
        
LocVT == MVT::f3216
||
2036
22
        
LocVT == MVT::f6416
) {
2037
6
      unsigned Offset8 = State.AllocateStack(8, 8);
2038
6
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
2039
6
      return false;
2040
6
    }
2041
16
  }
2042
16
2043
16
  if (LocVT == MVT::i32 ||
2044
16
      LocVT == MVT::f32) {
2045
0
    unsigned Offset9 = State.AllocateStack(4, 4);
2046
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
2047
0
    return false;
2048
0
  }
2049
16
2050
16
  if (LocVT == MVT::i64 ||
2051
16
      LocVT == MVT::f64) {
2052
0
    unsigned Offset10 = State.AllocateStack(8, 4);
2053
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
2054
0
    return false;
2055
0
  }
2056
16
2057
16
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2058
16
    if (LocVT == MVT::x86mmx) {
2059
0
      unsigned Offset11 = State.AllocateStack(8, 8);
2060
0
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo));
2061
0
      return false;
2062
0
    }
2063
16
  }
2064
16
2065
16
  if (LocVT == MVT::x86mmx) {
2066
0
    unsigned Offset12 = State.AllocateStack(8, 4);
2067
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo));
2068
0
    return false;
2069
0
  }
2070
16
2071
16
  if (LocVT == MVT::f80 ||
2072
16
      LocVT == MVT::f128) {
2073
0
    unsigned Offset13 = State.AllocateStack(
2074
0
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 
2075
0
      State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
2076
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo));
2077
0
    return false;
2078
0
  }
2079
16
2080
16
  if (LocVT == MVT::v16i8 ||
2081
16
      LocVT == MVT::v8i16 ||
2082
16
      LocVT == MVT::v4i32 ||
2083
16
      LocVT == MVT::v2i64 ||
2084
16
      LocVT == MVT::v4f32 ||
2085
16
      
LocVT == MVT::v2f648
) {
2086
8
    unsigned Offset14 = State.AllocateStack(16, 16);
2087
8
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo));
2088
8
    return false;
2089
8
  }
2090
8
2091
8
  if (LocVT == MVT::v32i8 ||
2092
8
      LocVT == MVT::v16i16 ||
2093
8
      LocVT == MVT::v8i32 ||
2094
8
      LocVT == MVT::v4i64 ||
2095
8
      LocVT == MVT::v8f32 ||
2096
8
      LocVT == MVT::v4f64) {
2097
0
    unsigned Offset15 = State.AllocateStack(32, 32);
2098
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset15, LocVT, LocInfo));
2099
0
    return false;
2100
0
  }
2101
8
2102
8
  if (LocVT == MVT::v16i32 ||
2103
8
      LocVT == MVT::v8i64 ||
2104
8
      LocVT == MVT::v16f32 ||
2105
8
      
LocVT == MVT::v8f646
) {
2106
2
    unsigned Offset16 = State.AllocateStack(64, 64);
2107
2
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset16, LocVT, LocInfo));
2108
2
    return false;
2109
2
  }
2110
6
2111
6
  return true;  // CC didn't match.
2112
6
}
2113
2114
2115
static bool CC_X86_Win32_VectorCall(unsigned ValNo, MVT ValVT,
2116
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
2117
244
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
2118
244
2119
244
  if (CC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2120
184
    return false;
2121
60
2122
60
  if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2123
60
    return false;
2124
0
2125
0
  return true;  // CC didn't match.
2126
0
}
2127
2128
2129
static bool CC_X86_Win64_C(unsigned ValNo, MVT ValVT,
2130
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
2131
2.96k
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
2132
2.96k
2133
2.96k
  if (ArgFlags.isByVal()) {
2134
9
    LocVT = MVT::i64;
2135
9
    LocInfo = CCValAssign::Indirect;
2136
9
  }
2137
2.96k
2138
2.96k
  if (LocVT == MVT::i1 ||
2139
2.96k
      LocVT == MVT::v1i1) {
2140
0
    LocVT = MVT::i8;
2141
0
    if (ArgFlags.isSExt())
2142
0
        LocInfo = CCValAssign::SExt;
2143
0
    else if (ArgFlags.isZExt())
2144
0
        LocInfo = CCValAssign::ZExt;
2145
0
    else
2146
0
        LocInfo = CCValAssign::AExt;
2147
0
  }
2148
2.96k
2149
2.96k
  if (ArgFlags.isNest()) {
2150
2
    if (unsigned Reg = State.AllocateReg(X86::R10)) {
2151
2
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2152
2
      return false;
2153
2
    }
2154
2.96k
  }
2155
2.96k
2156
2.96k
  if (ArgFlags.isSwiftError()) {
2157
2
    if (LocVT == MVT::i64) {
2158
2
      if (unsigned Reg = State.AllocateReg(X86::R12)) {
2159
2
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2160
2
        return false;
2161
2
      }
2162
2.95k
    }
2163
2
  }
2164
2.95k
2165
2.95k
  if (LocVT == MVT::v16i8 ||
2166
2.95k
      
LocVT == MVT::v8i162.95k
||
2167
2.95k
      
LocVT == MVT::v4i322.95k
||
2168
2.95k
      
LocVT == MVT::v2i642.94k
||
2169
2.95k
      
LocVT == MVT::v4f322.94k
||
2170
2.95k
      
LocVT == MVT::v2f642.62k
) {
2171
623
    LocVT = MVT::i64;
2172
623
    LocInfo = CCValAssign::Indirect;
2173
623
  }
2174
2.95k
2175
2.95k
  if (LocVT == MVT::v32i8 ||
2176
2.95k
      LocVT == MVT::v16i16 ||
2177
2.95k
      LocVT == MVT::v8i32 ||
2178
2.95k
      
LocVT == MVT::v4i642.95k
||
2179
2.95k
      
LocVT == MVT::v8f322.95k
||
2180
2.95k
      
LocVT == MVT::v4f642.78k
) {
2181
322
    LocVT = MVT::i64;
2182
322
    LocInfo = CCValAssign::Indirect;
2183
322
  }
2184
2.95k
2185
2.95k
  if (LocVT == MVT::v16i32 ||
2186
2.95k
      LocVT == MVT::v16f32 ||
2187
2.95k
      
LocVT == MVT::v8f642.94k
||
2188
2.95k
      
LocVT == MVT::v8i642.94k
) {
2189
14
    LocVT = MVT::i64;
2190
14
    LocInfo = CCValAssign::Indirect;
2191
14
  }
2192
2.95k
2193
2.95k
  if (LocVT == MVT::f80) {
2194
24
    LocVT = MVT::i64;
2195
24
    LocInfo = CCValAssign::Indirect;
2196
24
  }
2197
2.95k
2198
2.95k
  if (LocVT == MVT::x86mmx) {
2199
0
    LocVT = MVT::i64;
2200
0
    LocInfo = CCValAssign::BCvt;
2201
0
  }
2202
2.95k
2203
2.95k
  if (LocVT == MVT::i8) {
2204
43
    static const MCPhysReg RegList1[] = {
2205
43
      X86::CL, X86::DL, X86::R8B, X86::R9B
2206
43
    };
2207
43
    static const MCPhysReg RegList2[] = {
2208
43
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2209
43
    };
2210
43
    if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
2211
39
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2212
39
      return false;
2213
39
    }
2214
2.91k
  }
2215
2.91k
2216
2.91k
  if (LocVT == MVT::i16) {
2217
70
    static const MCPhysReg RegList3[] = {
2218
70
      X86::CX, X86::DX, X86::R8W, X86::R9W
2219
70
    };
2220
70
    static const MCPhysReg RegList4[] = {
2221
70
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2222
70
    };
2223
70
    if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
2224
50
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2225
50
      return false;
2226
50
    }
2227
2.86k
  }
2228
2.86k
2229
2.86k
  if (LocVT == MVT::i32) {
2230
676
    static const MCPhysReg RegList5[] = {
2231
676
      X86::ECX, X86::EDX, X86::R8D, X86::R9D
2232
676
    };
2233
676
    static const MCPhysReg RegList6[] = {
2234
676
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2235
676
    };
2236
676
    if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) {
2237
591
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2238
591
      return false;
2239
591
    }
2240
2.27k
  }
2241
2.27k
2242
2.27k
  if (State.getCallingConv() == CallingConv::X86_ThisCall) {
2243
14
    if (ArgFlags.isSRet()) {
2244
0
      if (LocVT == MVT::i64) {
2245
0
        static const MCPhysReg RegList7[] = {
2246
0
          X86::RDX, X86::R8, X86::R9
2247
0
        };
2248
0
        static const MCPhysReg RegList8[] = {
2249
0
          X86::XMM1, X86::XMM2, X86::XMM3
2250
0
        };
2251
0
        if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
2252
0
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2253
0
          return false;
2254
0
        }
2255
2.27k
      }
2256
0
    }
2257
14
  }
2258
2.27k
2259
2.27k
  if (LocVT == MVT::i64) {
2260
2.02k
    static const MCPhysReg RegList9[] = {
2261
2.02k
      X86::RCX, X86::RDX, X86::R8, X86::R9
2262
2.02k
    };
2263
2.02k
    static const MCPhysReg RegList10[] = {
2264
2.02k
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2265
2.02k
    };
2266
2.02k
    if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) {
2267
1.93k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2268
1.93k
      return false;
2269
1.93k
    }
2270
340
  }
2271
340
2272
340
  if (LocVT == MVT::f32 ||
2273
340
      
LocVT == MVT::f64268
||
2274
340
      
LocVT == MVT::v16i8212
||
2275
340
      
LocVT == MVT::v8i16212
||
2276
340
      
LocVT == MVT::v4i32212
||
2277
340
      
LocVT == MVT::v2i64212
||
2278
340
      
LocVT == MVT::v4f32212
||
2279
340
      
LocVT == MVT::v2f64212
) {
2280
128
    static const MCPhysReg RegList11[] = {
2281
128
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2282
128
    };
2283
128
    static const MCPhysReg RegList12[] = {
2284
128
      X86::RCX, X86::RDX, X86::R8, X86::R9
2285
128
    };
2286
128
    if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) {
2287
105
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2288
105
      return false;
2289
105
    }
2290
235
  }
2291
235
2292
235
  if (LocVT == MVT::i8 ||
2293
235
      
LocVT == MVT::i16231
||
2294
235
      
LocVT == MVT::i32211
||
2295
235
      
LocVT == MVT::i64126
||
2296
235
      
LocVT == MVT::f3235
||
2297
235
      
LocVT == MVT::f6419
) {
2298
223
    unsigned Offset13 = State.AllocateStack(8, 8);
2299
223
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo));
2300
223
    return false;
2301
223
  }
2302
12
2303
12
  return true;  // CC didn't match.
2304
12
}
2305
2306
2307
static bool CC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
2308
                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
2309
204
                                 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2310
204
2311
204
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2312
204
    if (ArgFlags.isByVal()) {
2313
0
      State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
2314
0
      return false;
2315
0
    }
2316
204
  }
2317
204
2318
204
  if (ArgFlags.isByVal()) {
2319
0
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
2320
0
    return false;
2321
0
  }
2322
204
2323
204
  if (LocVT == MVT::i1 ||
2324
204
      LocVT == MVT::i8 ||
2325
204
      
LocVT == MVT::i16193
||
2326
204
      
LocVT == MVT::v1i1189
) {
2327
15
    LocVT = MVT::i32;
2328
15
    if (ArgFlags.isSExt())
2329
2
        LocInfo = CCValAssign::SExt;
2330
13
    else if (ArgFlags.isZExt())
2331
0
        LocInfo = CCValAssign::ZExt;
2332
13
    else
2333
13
        LocInfo = CCValAssign::AExt;
2334
15
  }
2335
204
2336
204
  if (LocVT == MVT::v8i1 ||
2337
204
      
LocVT == MVT::v16i1195
||
2338
204
      
LocVT == MVT::v32i1186
) {
2339
24
    LocVT = MVT::i32;
2340
24
    if (ArgFlags.isSExt())
2341
0
        LocInfo = CCValAssign::SExt;
2342
24
    else if (ArgFlags.isZExt())
2343
0
        LocInfo = CCValAssign::ZExt;
2344
24
    else
2345
24
        LocInfo = CCValAssign::AExt;
2346
24
  }
2347
204
2348
204
  if (LocVT == MVT::i32) {
2349
78
    static const MCPhysReg RegList1[] = {
2350
78
      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
2351
78
    };
2352
78
    if (unsigned Reg = State.AllocateReg(RegList1)) {
2353
78
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2354
78
      return false;
2355
78
    }
2356
126
  }
2357
126
2358
126
  if (LocVT == MVT::i64) {
2359
9
    static const MCPhysReg RegList2[] = {
2360
9
      X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
2361
9
    };
2362
9
    if (unsigned Reg = State.AllocateReg(RegList2)) {
2363
9
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2364
9
      return false;
2365
9
    }
2366
117
  }
2367
117
2368
117
  if (LocVT == MVT::v64i1) {
2369
26
    LocVT = MVT::i64;
2370
26
    if (ArgFlags.isSExt())
2371
0
        LocInfo = CCValAssign::SExt;
2372
26
    else if (ArgFlags.isZExt())
2373
0
        LocInfo = CCValAssign::ZExt;
2374
26
    else
2375
26
        LocInfo = CCValAssign::AExt;
2376
26
  }
2377
117
2378
117
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2379
117
    if (LocVT == MVT::i64) {
2380
26
      static const MCPhysReg RegList3[] = {
2381
26
        X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
2382
26
      };
2383
26
      if (unsigned Reg = State.AllocateReg(RegList3)) {
2384
24
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2385
24
        return false;
2386
24
      }
2387
93
    }
2388
117
  }
2389
93
2390
93
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
2391
0
    if (LocVT == MVT::i64) {
2392
0
      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2393
0
            return false;
2394
93
    }
2395
0
  }
2396
93
2397
93
  if (LocVT == MVT::f32 ||
2398
93
      
LocVT == MVT::f6488
||
2399
93
      
LocVT == MVT::f12883
) {
2400
10
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
2401
10
      static const MCPhysReg RegList4[] = {
2402
10
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2403
10
      };
2404
10
      if (unsigned Reg = State.AllocateReg(RegList4)) {
2405
10
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2406
10
        return false;
2407
10
      }
2408
83
    }
2409
10
  }
2410
83
2411
83
  if (LocVT == MVT::f80) {
2412
3
    if (unsigned Reg = State.AllocateReg(X86::FP0)) {
2413
3
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2414
3
      return false;
2415
3
    }
2416
80
  }
2417
80
2418
80
  if (LocVT == MVT::v16i8 ||
2419
80
      LocVT == MVT::v8i16 ||
2420
80
      LocVT == MVT::v4i32 ||
2421
80
      
LocVT == MVT::v2i6475
||
2422
80
      
LocVT == MVT::v4f3275
||
2423
80
      
LocVT == MVT::v2f6439
) {
2424
41
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
2425
41
      static const MCPhysReg RegList5[] = {
2426
41
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2427
41
      };
2428
41
      if (unsigned Reg = State.AllocateReg(RegList5)) {
2429
33
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2430
33
        return false;
2431
33
      }
2432
47
    }
2433
41
  }
2434
47
2435
47
  if (LocVT == MVT::v32i8 ||
2436
47
      LocVT == MVT::v16i16 ||
2437
47
      LocVT == MVT::v8i32 ||
2438
47
      
LocVT == MVT::v4i6442
||
2439
47
      
LocVT == MVT::v8f3242
||
2440
47
      
LocVT == MVT::v4f6442
) {
2441
5
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
2442
5
      static const MCPhysReg RegList6[] = {
2443
5
        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
2444
5
      };
2445
5
      if (unsigned Reg = State.AllocateReg(RegList6)) {
2446
5
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2447
5
        return false;
2448
5
      }
2449
42
    }
2450
5
  }
2451
42
2452
42
  if (LocVT == MVT::v64i8 ||
2453
42
      LocVT == MVT::v32i16 ||
2454
42
      LocVT == MVT::v16i32 ||
2455
42
      
LocVT == MVT::v8i6437
||
2456
42
      
LocVT == MVT::v16f3237
||
2457
42
      
LocVT == MVT::v8f6413
) {
2458
29
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
2459
29
      static const MCPhysReg RegList7[] = {
2460
29
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
2461
29
      };
2462
29
      if (unsigned Reg = State.AllocateReg(RegList7)) {
2463
27
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2464
27
        return false;
2465
27
      }
2466
15
    }
2467
29
  }
2468
15
2469
15
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2470
15
    if (LocVT == MVT::i32 ||
2471
15
        LocVT == MVT::i64 ||
2472
15
        
LocVT == MVT::f3213
||
2473
15
        
LocVT == MVT::f6413
) {
2474
2
      unsigned Offset8 = State.AllocateStack(8, 8);
2475
2
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
2476
2
      return false;
2477
2
    }
2478
13
  }
2479
13
2480
13
  if (LocVT == MVT::i32 ||
2481
13
      LocVT == MVT::f32) {
2482
0
    unsigned Offset9 = State.AllocateStack(4, 4);
2483
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
2484
0
    return false;
2485
0
  }
2486
13
2487
13
  if (LocVT == MVT::i64 ||
2488
13
      LocVT == MVT::f64) {
2489
0
    unsigned Offset10 = State.AllocateStack(8, 4);
2490
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
2491
0
    return false;
2492
0
  }
2493
13
2494
13
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2495
13
    if (LocVT == MVT::x86mmx) {
2496
0
      unsigned Offset11 = State.AllocateStack(8, 8);
2497
0
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo));
2498
0
      return false;
2499
0
    }
2500
13
  }
2501
13
2502
13
  if (LocVT == MVT::x86mmx) {
2503
0
    unsigned Offset12 = State.AllocateStack(8, 4);
2504
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo));
2505
0
    return false;
2506
0
  }
2507
13
2508
13
  if (LocVT == MVT::f80 ||
2509
13
      LocVT == MVT::f128) {
2510
0
    unsigned Offset13 = State.AllocateStack(
2511
0
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 
2512
0
      State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
2513
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo));
2514
0
    return false;
2515
0
  }
2516
13
2517
13
  if (LocVT == MVT::v16i8 ||
2518
13
      LocVT == MVT::v8i16 ||
2519
13
      LocVT == MVT::v4i32 ||
2520
13
      LocVT == MVT::v2i64 ||
2521
13
      LocVT == MVT::v4f32 ||
2522
13
      
LocVT == MVT::v2f645
) {
2523
8
    unsigned Offset14 = State.AllocateStack(16, 16);
2524
8
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo));
2525
8
    return false;
2526
8
  }
2527
5
2528
5
  if (LocVT == MVT::v32i8 ||
2529
5
      LocVT == MVT::v16i16 ||
2530
5
      LocVT == MVT::v8i32 ||
2531
5
      LocVT == MVT::v4i64 ||
2532
5
      LocVT == MVT::v8f32 ||
2533
5
      LocVT == MVT::v4f64) {
2534
0
    unsigned Offset15 = State.AllocateStack(32, 32);
2535
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset15, LocVT, LocInfo));
2536
0
    return false;
2537
0
  }
2538
5
2539
5
  if (LocVT == MVT::v16i32 ||
2540
5
      LocVT == MVT::v8i64 ||
2541
5
      LocVT == MVT::v16f32 ||
2542
5
      
LocVT == MVT::v8f643
) {
2543
2
    unsigned Offset16 = State.AllocateStack(64, 64);
2544
2
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset16, LocVT, LocInfo));
2545
2
    return false;
2546
2
  }
2547
3
2548
3
  return true;  // CC didn't match.
2549
3
}
2550
2551
2552
static bool CC_X86_Win64_VectorCall(unsigned ValNo, MVT ValVT,
2553
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
2554
152
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
2555
152
2556
152
  if (CC_X86_64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2557
135
    return false;
2558
17
2559
17
  if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2560
17
    return false;
2561
0
2562
0
  return true;  // CC didn't match.
2563
0
}
2564
2565
2566
static bool RetCC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
2567
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
2568
240
                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
2569
240
2570
240
  if (LocVT == MVT::f32 ||
2571
240
      LocVT == MVT::f64 ||
2572
240
      LocVT == MVT::v4i32 ||
2573
240
      LocVT == MVT::v2i64 ||
2574
240
      LocVT == MVT::v4f32 ||
2575
240
      
LocVT == MVT::v2f64152
) {
2576
88
    static const MCPhysReg RegList1[] = {
2577
88
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2578
88
    };
2579
88
    if (unsigned Reg = State.AllocateReg(RegList1)) {
2580
88
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2581
88
      return false;
2582
88
    }
2583
152
  }
2584
152
2585
152
  if (LocVT == MVT::v8f32 ||
2586
152
      
LocVT == MVT::v4f64104
||
2587
152
      
LocVT == MVT::v8i32104
||
2588
152
      
LocVT == MVT::v4i64104
) {
2589
48
    static const MCPhysReg RegList2[] = {
2590
48
      X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
2591
48
    };
2592
48
    if (unsigned Reg = State.AllocateReg(RegList2)) {
2593
48
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2594
48
      return false;
2595
48
    }
2596
104
  }
2597
104
2598
104
  if (LocVT == MVT::v16f32 ||
2599
104
      
LocVT == MVT::v8f648
||
2600
104
      
LocVT == MVT::v16i328
||
2601
104
      
LocVT == MVT::v8i648
) {
2602
96
    static const MCPhysReg RegList3[] = {
2603
96
      X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
2604
96
    };
2605
96
    if (unsigned Reg = State.AllocateReg(RegList3)) {
2606
96
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2607
96
      return false;
2608
96
    }
2609
8
  }
2610
8
2611
8
  if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2612
8
    return false;
2613
0
2614
0
  return true;  // CC didn't match.
2615
0
}
2616
2617
2618
bool llvm::RetCC_X86(unsigned ValNo, MVT ValVT,
2619
                     MVT LocVT, CCValAssign::LocInfo LocInfo,
2620
366k
                     ISD::ArgFlagsTy ArgFlags, CCState &State) {
2621
366k
2622
366k
  if (State.getCallingConv() == CallingConv::Intel_OCL_BI) {
2623
240
    if (!RetCC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2624
240
      return false;
2625
366k
  }
2626
366k
2627
366k
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2628
296k
    if (!RetCC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2629
295k
      return false;
2630
70.5k
  }
2631
70.5k
2632
70.5k
  if (!RetCC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2633
69.7k
    return false;
2634
783
2635
783
  return true;  // CC didn't match.
2636
783
}
2637
2638
2639
static bool RetCC_X86Common(unsigned ValNo, MVT ValVT,
2640
                            MVT LocVT, CCValAssign::LocInfo LocInfo,
2641
352k
                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
2642
352k
2643
352k
  if (LocVT == MVT::v1i1) {
2644
6
    LocVT = MVT::i8;
2645
6
    if (ArgFlags.isSExt())
2646
0
        LocInfo = CCValAssign::SExt;
2647
6
    else if (ArgFlags.isZExt())
2648
0
        LocInfo = CCValAssign::ZExt;
2649
6
    else
2650
6
        LocInfo = CCValAssign::AExt;
2651
6
  }
2652
352k
2653
352k
  if (LocVT == MVT::i1) {
2654
13
    LocVT = MVT::i8;
2655
13
    if (ArgFlags.isSExt())
2656
0
        LocInfo = CCValAssign::SExt;
2657
13
    else if (ArgFlags.isZExt())
2658
0
        LocInfo = CCValAssign::ZExt;
2659
13
    else
2660
13
        LocInfo = CCValAssign::AExt;
2661
13
  }
2662
352k
2663
352k
  if (LocVT == MVT::i8) {
2664
17.2k
    static const MCPhysReg RegList1[] = {
2665
17.2k
      X86::AL, X86::DL, X86::CL
2666
17.2k
    };
2667
17.2k
    if (unsigned Reg = State.AllocateReg(RegList1)) {
2668
17.1k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2669
17.1k
      return false;
2670
17.1k
    }
2671
335k
  }
2672
335k
2673
335k
  if (LocVT == MVT::i16) {
2674
4.79k
    static const MCPhysReg RegList2[] = {
2675
4.79k
      X86::AX, X86::DX, X86::CX
2676
4.79k
    };
2677
4.79k
    if (unsigned Reg = State.AllocateReg(RegList2)) {
2678
4.75k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2679
4.75k
      return false;
2680
4.75k
    }
2681
331k
  }
2682
331k
2683
331k
  if (LocVT == MVT::i32) {
2684
88.2k
    static const MCPhysReg RegList3[] = {
2685
88.2k
      X86::EAX, X86::EDX, X86::ECX
2686
88.2k
    };
2687
88.2k
    if (unsigned Reg = State.AllocateReg(RegList3)) {
2688
87.8k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2689
87.8k
      return false;
2690
87.8k
    }
2691
243k
  }
2692
243k
2693
243k
  if (LocVT == MVT::i64) {
2694
102k
    static const MCPhysReg RegList4[] = {
2695
102k
      X86::RAX, X86::RDX, X86::RCX
2696
102k
    };
2697
102k
    if (unsigned Reg = State.AllocateReg(RegList4)) {
2698
102k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2699
102k
      return false;
2700
102k
    }
2701
141k
  }
2702
141k
2703
141k
  if (LocVT == MVT::v2i1) {
2704
28
    LocVT = MVT::v2i64;
2705
28
    if (ArgFlags.isSExt())
2706
0
        LocInfo = CCValAssign::SExt;
2707
28
    else if (ArgFlags.isZExt())
2708
0
        LocInfo = CCValAssign::ZExt;
2709
28
    else
2710
28
        LocInfo = CCValAssign::AExt;
2711
28
  }
2712
141k
2713
141k
  if (LocVT == MVT::v4i1) {
2714
75
    LocVT = MVT::v4i32;
2715
75
    if (ArgFlags.isSExt())
2716
0
        LocInfo = CCValAssign::SExt;
2717
75
    else if (ArgFlags.isZExt())
2718
0
        LocInfo = CCValAssign::ZExt;
2719
75
    else
2720
75
        LocInfo = CCValAssign::AExt;
2721
75
  }
2722
141k
2723
141k
  if (LocVT == MVT::v8i1) {
2724
108
    LocVT = MVT::v8i16;
2725
108
    if (ArgFlags.isSExt())
2726
0
        LocInfo = CCValAssign::SExt;
2727
108
    else if (ArgFlags.isZExt())
2728
0
        LocInfo = CCValAssign::ZExt;
2729
108
    else
2730
108
        LocInfo = CCValAssign::AExt;
2731
108
  }
2732
141k
2733
141k
  if (LocVT == MVT::v16i1) {
2734
156
    LocVT = MVT::v16i8;
2735
156
    if (ArgFlags.isSExt())
2736
0
        LocInfo = CCValAssign::SExt;
2737
156
    else if (ArgFlags.isZExt())
2738
0
        LocInfo = CCValAssign::ZExt;
2739
156
    else
2740
156
        LocInfo = CCValAssign::AExt;
2741
156
  }
2742
141k
2743
141k
  if (LocVT == MVT::v32i1) {
2744
30
    LocVT = MVT::v32i8;
2745
30
    if (ArgFlags.isSExt())
2746
0
        LocInfo = CCValAssign::SExt;
2747
30
    else if (ArgFlags.isZExt())
2748
0
        LocInfo = CCValAssign::ZExt;
2749
30
    else
2750
30
        LocInfo = CCValAssign::AExt;
2751
30
  }
2752
141k
2753
141k
  if (LocVT == MVT::v64i1) {
2754
20
    LocVT = MVT::v64i8;
2755
20
    if (ArgFlags.isSExt())
2756
0
        LocInfo = CCValAssign::SExt;
2757
20
    else if (ArgFlags.isZExt())
2758
0
        LocInfo = CCValAssign::ZExt;
2759
20
    else
2760
20
        LocInfo = CCValAssign::AExt;
2761
20
  }
2762
141k
2763
141k
  if (LocVT == MVT::v16i8 ||
2764
141k
      
LocVT == MVT::v8i16129k
||
2765
141k
      
LocVT == MVT::v4i32115k
||
2766
141k
      
LocVT == MVT::v2i6498.7k
||
2767
141k
      
LocVT == MVT::v4f3284.2k
||
2768
141k
      
LocVT == MVT::v2f6469.4k
) {
2769
80.8k
    static const MCPhysReg RegList5[] = {
2770
80.8k
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2771
80.8k
    };
2772
80.8k
    if (unsigned Reg = State.AllocateReg(RegList5)) {
2773
80.6k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2774
80.6k
      return false;
2775
80.6k
    }
2776
60.3k
  }
2777
60.3k
2778
60.3k
  if (LocVT == MVT::v32i8 ||
2779
60.3k
      
LocVT == MVT::v16i1653.8k
||
2780
60.3k
      
LocVT == MVT::v8i3246.4k
||
2781
60.3k
      
LocVT == MVT::v4i6439.3k
||
2782
60.3k
      
LocVT == MVT::v8f3232.3k
||
2783
60.3k
      
LocVT == MVT::v4f6425.4k
) {
2784
40.5k
    static const MCPhysReg RegList6[] = {
2785
40.5k
      X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
2786
40.5k
    };
2787
40.5k
    if (unsigned Reg = State.AllocateReg(RegList6)) {
2788
40.5k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2789
40.5k
      return false;
2790
40.5k
    }
2791
19.8k
  }
2792
19.8k
2793
19.8k
  if (LocVT == MVT::v64i8 ||
2794
19.8k
      
LocVT == MVT::v32i1618.7k
||
2795
19.8k
      
LocVT == MVT::v16i3217.1k
||
2796
19.8k
      
LocVT == MVT::v8i6414.2k
||
2797
19.8k
      
LocVT == MVT::v16f3210.5k
||
2798
19.8k
      
LocVT == MVT::v8f646.48k
) {
2799
17.4k
    static const MCPhysReg RegList7[] = {
2800
17.4k
      X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
2801
17.4k
    };
2802
17.4k
    if (unsigned Reg = State.AllocateReg(RegList7)) {
2803
17.4k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2804
17.4k
      return false;
2805
17.4k
    }
2806
2.43k
  }
2807
2.43k
2808
2.43k
  if (LocVT == MVT::x86mmx) {
2809
6
    if (unsigned Reg = State.AllocateReg(X86::MM0)) {
2810
6
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2811
6
      return false;
2812
6
    }
2813
2.43k
  }
2814
2.43k
2815
2.43k
  if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
2816
2.38k
    if (LocVT == MVT::f80) {
2817
1.24k
      static const MCPhysReg RegList8[] = {
2818
1.24k
        X86::FP0, X86::FP1
2819
1.24k
      };
2820
1.24k
      if (unsigned Reg = State.AllocateReg(RegList8)) {
2821
1.24k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2822
1.24k
        return false;
2823
1.24k
      }
2824
1.18k
    }
2825
2.38k
  }
2826
1.18k
2827
1.18k
  return true;  // CC didn't match.
2828
1.18k
}
2829
2830
2831
static bool RetCC_X86_32(unsigned ValNo, MVT ValVT,
2832
                         MVT LocVT, CCValAssign::LocInfo LocInfo,
2833
70.5k
                         ISD::ArgFlagsTy ArgFlags, CCState &State) {
2834
70.5k
2835
70.5k
  if (State.getCallingConv() == CallingConv::Fast) {
2836
894
    if (!RetCC_X86_32_Fast(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2837
874
      return false;
2838
69.6k
  }
2839
69.6k
2840
69.6k
  if (State.getCallingConv() == CallingConv::HiPE) {
2841
30
    if (!RetCC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2842
30
      return false;
2843
69.6k
  }
2844
69.6k
2845
69.6k
  if (State.getCallingConv() == CallingConv::X86_VectorCall) {
2846
84
    if (!RetCC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2847
80
      return false;
2848
69.5k
  }
2849
69.5k
2850
69.5k
  if (State.getCallingConv() == CallingConv::X86_RegCall) {
2851
178
    if (!RetCC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2852
178
      return false;
2853
69.3k
  }
2854
69.3k
2855
69.3k
  if (!RetCC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2856
68.5k
    return false;
2857
783
2858
783
  return true;  // CC didn't match.
2859
783
}
2860
2861
2862
static bool RetCC_X86_32_C(unsigned ValNo, MVT ValVT,
2863
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
2864
69.3k
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
2865
69.3k
2866
69.3k
  if (ArgFlags.isInReg()) {
2867
24
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
2868
8
      if (LocVT == MVT::f32 ||
2869
8
          
LocVT == MVT::f644
) {
2870
8
        static const MCPhysReg RegList1[] = {
2871
8
          X86::XMM0, X86::XMM1, X86::XMM2
2872
8
        };
2873
8
        if (unsigned Reg = State.AllocateReg(RegList1)) {
2874
8
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2875
8
          return false;
2876
8
        }
2877
69.3k
      }
2878
8
    }
2879
24
  }
2880
69.3k
2881
69.3k
  if (LocVT == MVT::f32 ||
2882
69.3k
      
LocVT == MVT::f6468.1k
) {
2883
2.64k
    static const MCPhysReg RegList2[] = {
2884
2.64k
      X86::FP0, X86::FP1
2885
2.64k
    };
2886
2.64k
    if (unsigned Reg = State.AllocateReg(RegList2)) {
2887
2.46k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2888
2.46k
      return false;
2889
2.46k
    }
2890
66.8k
  }
2891
66.8k
2892
66.8k
  if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2893
66.1k
    return false;
2894
783
2895
783
  return true;  // CC didn't match.
2896
783
}
2897
2898
2899
static bool RetCC_X86_32_Fast(unsigned ValNo, MVT ValVT,
2900
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
2901
894
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
2902
894
2903
894
  if (LocVT == MVT::f32) {
2904
2
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
2905
2
      static const MCPhysReg RegList1[] = {
2906
2
        X86::XMM0, X86::XMM1, X86::XMM2
2907
2
      };
2908
2
      if (unsigned Reg = State.AllocateReg(RegList1)) {
2909
2
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2910
2
        return false;
2911
2
      }
2912
892
    }
2913
2
  }
2914
892
2915
892
  if (LocVT == MVT::f64) {
2916
25
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
2917
17
      static const MCPhysReg RegList2[] = {
2918
17
        X86::XMM0, X86::XMM1, X86::XMM2
2919
17
      };
2920
17
      if (unsigned Reg = State.AllocateReg(RegList2)) {
2921
11
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2922
11
        return false;
2923
11
      }
2924
881
    }
2925
25
  }
2926
881
2927
881
  if (LocVT == MVT::i8) {
2928
294
    static const MCPhysReg RegList3[] = {
2929
294
      X86::AL, X86::DL, X86::CL
2930
294
    };
2931
294
    if (unsigned Reg = State.AllocateReg(RegList3)) {
2932
294
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2933
294
      return false;
2934
294
    }
2935
587
  }
2936
587
2937
587
  if (LocVT == MVT::i16) {
2938
0
    static const MCPhysReg RegList4[] = {
2939
0
      X86::AX, X86::DX, X86::CX
2940
0
    };
2941
0
    if (unsigned Reg = State.AllocateReg(RegList4)) {
2942
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2943
0
      return false;
2944
0
    }
2945
587
  }
2946
587
2947
587
  if (LocVT == MVT::i32) {
2948
568
    static const MCPhysReg RegList5[] = {
2949
568
      X86::EAX, X86::EDX, X86::ECX
2950
568
    };
2951
568
    if (unsigned Reg = State.AllocateReg(RegList5)) {
2952
563
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2953
563
      return false;
2954
563
    }
2955
24
  }
2956
24
2957
24
  if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2958
4
    return false;
2959
20
2960
20
  return true;  // CC didn't match.
2961
20
}
2962
2963
2964
static bool RetCC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
2965
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
2966
30
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
2967
30
2968
30
  if (LocVT == MVT::i8 ||
2969
30
      LocVT == MVT::i16) {
2970
0
    LocVT = MVT::i32;
2971
0
    if (ArgFlags.isSExt())
2972
0
        LocInfo = CCValAssign::SExt;
2973
0
    else if (ArgFlags.isZExt())
2974
0
        LocInfo = CCValAssign::ZExt;
2975
0
    else
2976
0
        LocInfo = CCValAssign::AExt;
2977
0
  }
2978
30
2979
30
  if (LocVT == MVT::i32) {
2980
30
    static const MCPhysReg RegList1[] = {
2981
30
      X86::ESI, X86::EBP, X86::EAX, X86::EDX
2982
30
    };
2983
30
    if (unsigned Reg = State.AllocateReg(RegList1)) {
2984
30
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2985
30
      return false;
2986
30
    }
2987
0
  }
2988
0
2989
0
  return true;  // CC didn't match.
2990
0
}
2991
2992
2993
static bool RetCC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
2994
                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
2995
178
                                 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2996
178
2997
178
  if (LocVT == MVT::i1 ||
2998
178
      LocVT == MVT::v1i1 ||
2999
178
      LocVT == MVT::v8i1) {
3000
4
    LocVT = MVT::i8;
3001
4
    if (ArgFlags.isSExt())
3002
0
        LocInfo = CCValAssign::SExt;
3003
4
    else if (ArgFlags.isZExt())
3004
0
        LocInfo = CCValAssign::ZExt;
3005
4
    else
3006
4
        LocInfo = CCValAssign::AExt;
3007
4
  }
3008
178
3009
178
  if (LocVT == MVT::v16i1) {
3010
4
    LocVT = MVT::i16;
3011
4
    if (ArgFlags.isSExt())
3012
0
        LocInfo = CCValAssign::SExt;
3013
4
    else if (ArgFlags.isZExt())
3014
0
        LocInfo = CCValAssign::ZExt;
3015
4
    else
3016
4
        LocInfo = CCValAssign::AExt;
3017
4
  }
3018
178
3019
178
  if (LocVT == MVT::v32i1) {
3020
4
    LocVT = MVT::i32;
3021
4
    if (ArgFlags.isSExt())
3022
0
        LocInfo = CCValAssign::SExt;
3023
4
    else if (ArgFlags.isZExt())
3024
0
        LocInfo = CCValAssign::ZExt;
3025
4
    else
3026
4
        LocInfo = CCValAssign::AExt;
3027
4
  }
3028
178
3029
178
  if (LocVT == MVT::i8) {
3030
28
    static const MCPhysReg RegList1[] = {
3031
28
      X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL
3032
28
    };
3033
28
    if (unsigned Reg = State.AllocateReg(RegList1)) {
3034
28
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3035
28
      return false;
3036
28
    }
3037
150
  }
3038
150
3039
150
  if (LocVT == MVT::i16) {
3040
14
    static const MCPhysReg RegList2[] = {
3041
14
      X86::AX, X86::CX, X86::DX, X86::DI, X86::SI
3042
14
    };
3043
14
    if (unsigned Reg = State.AllocateReg(RegList2)) {
3044
14
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3045
14
      return false;
3046
14
    }
3047
136
  }
3048
136
3049
136
  if (LocVT == MVT::i32) {
3050
60
    static const MCPhysReg RegList3[] = {
3051
60
      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI
3052
60
    };
3053
60
    if (unsigned Reg = State.AllocateReg(RegList3)) {
3054
60
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3055
60
      return false;
3056
60
    }
3057
76
  }
3058
76
3059
76
  if (LocVT == MVT::i64) {
3060
0
    if (unsigned Reg = State.AllocateReg(X86::RAX)) {
3061
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3062
0
      return false;
3063
0
    }
3064
76
  }
3065
76
3066
76
  if (LocVT == MVT::v64i1) {
3067
4
    LocVT = MVT::i64;
3068
4
    if (ArgFlags.isSExt())
3069
0
        LocInfo = CCValAssign::SExt;
3070
4
    else if (ArgFlags.isZExt())
3071
0
        LocInfo = CCValAssign::ZExt;
3072
4
    else
3073
4
        LocInfo = CCValAssign::AExt;
3074
4
  }
3075
76
3076
76
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
3077
0
    if (LocVT == MVT::i64) {
3078
0
      if (unsigned Reg = State.AllocateReg(X86::RAX)) {
3079
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3080
0
        return false;
3081
0
      }
3082
76
    }
3083
0
  }
3084
76
3085
76
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
3086
76
    if (LocVT == MVT::i64) {
3087
4
      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3088
4
            return false;
3089
72
    }
3090
76
  }
3091
72
3092
72
  if (LocVT == MVT::f80) {
3093
6
    static const MCPhysReg RegList4[] = {
3094
6
      X86::FP0, X86::FP1
3095
6
    };
3096
6
    if (unsigned Reg = State.AllocateReg(RegList4)) {
3097
6
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3098
6
      return false;
3099
6
    }
3100
66
  }
3101
66
3102
66
  if (LocVT == MVT::f32 ||
3103
66
      
LocVT == MVT::f6458
||
3104
66
      
LocVT == MVT::f12850
) {
3105
16
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3106
16
      static const MCPhysReg RegList5[] = {
3107
16
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3108
16
      };
3109
16
      if (unsigned Reg = State.AllocateReg(RegList5)) {
3110
16
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3111
16
        return false;
3112
16
      }
3113
50
    }
3114
16
  }
3115
50
3116
50
  if (LocVT == MVT::v16i8 ||
3117
50
      LocVT == MVT::v8i16 ||
3118
50
      LocVT == MVT::v4i32 ||
3119
50
      
LocVT == MVT::v2i6444
||
3120
50
      
LocVT == MVT::v4f3244
||
3121
50
      
LocVT == MVT::v2f6420
) {
3122
30
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3123
30
      static const MCPhysReg RegList6[] = {
3124
30
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3125
30
      };
3126
30
      if (unsigned Reg = State.AllocateReg(RegList6)) {
3127
30
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3128
30
        return false;
3129
30
      }
3130
20
    }
3131
30
  }
3132
20
3133
20
  if (LocVT == MVT::v32i8 ||
3134
20
      LocVT == MVT::v16i16 ||
3135
20
      LocVT == MVT::v8i32 ||
3136
20
      
LocVT == MVT::v4i6414
||
3137
20
      
LocVT == MVT::v8f3214
||
3138
20
      
LocVT == MVT::v4f6414
) {
3139
6
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
3140
6
      static const MCPhysReg RegList7[] = {
3141
6
        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
3142
6
      };
3143
6
      if (unsigned Reg = State.AllocateReg(RegList7)) {
3144
6
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3145
6
        return false;
3146
6
      }
3147
14
    }
3148
6
  }
3149
14
3150
14
  if (LocVT == MVT::v64i8 ||
3151
14
      LocVT == MVT::v32i16 ||
3152
14
      LocVT == MVT::v16i32 ||
3153
14
      
LocVT == MVT::v8i648
||
3154
14
      
LocVT == MVT::v16f328
||
3155
14
      
LocVT == MVT::v8f640
) {
3156
14
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
3157
14
      static const MCPhysReg RegList8[] = {
3158
14
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
3159
14
      };
3160
14
      if (unsigned Reg = State.AllocateReg(RegList8)) {
3161
14
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3162
14
        return false;
3163
14
      }
3164
0
    }
3165
14
  }
3166
0
3167
0
  return true;  // CC didn't match.
3168
0
}
3169
3170
3171
static bool RetCC_X86_32_VectorCall(unsigned ValNo, MVT ValVT,
3172
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
3173
84
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
3174
84
3175
84
  if (LocVT == MVT::f32 ||
3176
84
      LocVT == MVT::f64 ||
3177
84
      
LocVT == MVT::f12856
) {
3178
28
    static const MCPhysReg RegList1[] = {
3179
28
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3180
28
    };
3181
28
    if (unsigned Reg = State.AllocateReg(RegList1)) {
3182
24
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3183
24
      return false;
3184
24
    }
3185
60
  }
3186
60
3187
60
  if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3188
56
    return false;
3189
4
3190
4
  return true;  // CC didn't match.
3191
4
}
3192
3193
3194
static bool RetCC_X86_64(unsigned ValNo, MVT ValVT,
3195
                         MVT LocVT, CCValAssign::LocInfo LocInfo,
3196
296k
                         ISD::ArgFlagsTy ArgFlags, CCState &State) {
3197
296k
3198
296k
  if (State.getCallingConv() == CallingConv::HiPE) {
3199
28
    if (!RetCC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3200
28
      return false;
3201
296k
  }
3202
296k
3203
296k
  if (State.getCallingConv() == CallingConv::WebKit_JS) {
3204
20
    if (!RetCC_X86_64_WebKit_JS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3205
20
      return false;
3206
296k
  }
3207
296k
3208
296k
  if (State.getCallingConv() == CallingConv::AnyReg) {
3209
0
    if (!RetCC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3210
0
      return false;
3211
296k
  }
3212
296k
3213
296k
  if (State.getCallingConv() == CallingConv::Swift) {
3214
411
    if (!RetCC_X86_64_Swift(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3215
406
      return false;
3216
295k
  }
3217
295k
3218
295k
  if (State.getCallingConv() == CallingConv::Win64) {
3219
35
    if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3220
34
      return false;
3221
295k
  }
3222
295k
3223
295k
  if (State.getCallingConv() == CallingConv::X86_64_SysV) {
3224
8
    if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3225
8
      return false;
3226
295k
  }
3227
295k
3228
295k
  if (State.getCallingConv() == CallingConv::X86_VectorCall) {
3229
60
    if (!RetCC_X86_64_Vectorcall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3230
58
      return false;
3231
295k
  }
3232
295k
3233
295k
  if (State.getCallingConv() == CallingConv::HHVM) {
3234
70
    if (!RetCC_X86_64_HHVM(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3235
70
      return false;
3236
295k
  }
3237
295k
3238
295k
  if (State.getCallingConv() == CallingConv::X86_RegCall) {
3239
342
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
3240
184
      if (!RetCC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3241
184
        return false;
3242
295k
    }
3243
342
  }
3244
295k
3245
295k
  if (State.getCallingConv() == CallingConv::X86_RegCall) {
3246
158
    if (!RetCC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3247
158
      return false;
3248
295k
  }
3249
295k
3250
295k
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
3251
2.65k
    if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3252
2.63k
      return false;
3253
292k
  }
3254
292k
3255
292k
  if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3256
292k
    return false;
3257
350
3258
350
  return true;  // CC didn't match.
3259
350
}
3260
3261
3262
static bool RetCC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
3263
                                MVT LocVT, CCValAssign::LocInfo LocInfo,
3264
0
                                ISD::ArgFlagsTy ArgFlags, CCState &State) {
3265
0
3266
0
  if (CC_X86_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3267
0
    return false;
3268
0
3269
0
  return true;  // CC didn't match.
3270
0
}
3271
3272
3273
static bool RetCC_X86_64_C(unsigned ValNo, MVT ValVT,
3274
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
3275
295k
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
3276
295k
3277
295k
  if (LocVT == MVT::f32) {
3278
4.29k
    static const MCPhysReg RegList1[] = {
3279
4.29k
      X86::XMM0, X86::XMM1
3280
4.29k
    };
3281
4.29k
    if (unsigned Reg = State.AllocateReg(RegList1)) {
3282
4.29k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3283
4.29k
      return false;
3284
4.29k
    }
3285
290k
  }
3286
290k
3287
290k
  if (LocVT == MVT::f64) {
3288
4.54k
    static const MCPhysReg RegList2[] = {
3289
4.54k
      X86::XMM0, X86::XMM1
3290
4.54k
    };
3291
4.54k
    if (unsigned Reg = State.AllocateReg(RegList2)) {
3292
4.47k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3293
4.47k
      return false;
3294
4.47k
    }
3295
286k
  }
3296
286k
3297
286k
  if (LocVT == MVT::f128) {
3298
308
    static const MCPhysReg RegList3[] = {
3299
308
      X86::XMM0, X86::XMM1
3300
308
    };
3301
308
    if (unsigned Reg = State.AllocateReg(RegList3)) {
3302
308
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3303
308
      return false;
3304
308
    }
3305
286k
  }
3306
286k
3307
286k
  if (LocVT == MVT::x86mmx) {
3308
204
    static const MCPhysReg RegList4[] = {
3309
204
      X86::XMM0, X86::XMM1
3310
204
    };
3311
204
    if (unsigned Reg = State.AllocateReg(RegList4)) {
3312
204
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3313
204
      return false;
3314
204
    }
3315
285k
  }
3316
285k
3317
285k
  if (ArgFlags.isSwiftError()) {
3318
26
    if (LocVT == MVT::i64) {
3319
26
      if (unsigned Reg = State.AllocateReg(X86::R12)) {
3320
26
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3321
26
        return false;
3322
26
      }
3323
285k
    }
3324
26
  }
3325
285k
3326
285k
  if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3327
285k
    return false;
3328
370
3329
370
  return true;  // CC didn't match.
3330
370
}
3331
3332
3333
static bool RetCC_X86_64_HHVM(unsigned ValNo, MVT ValVT,
3334
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
3335
70
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
3336
70
3337
70
  if (LocVT == MVT::i8 ||
3338
70
      LocVT == MVT::i16 ||
3339
70
      LocVT == MVT::i32) {
3340
0
    LocVT = MVT::i64;
3341
0
    if (ArgFlags.isSExt())
3342
0
        LocInfo = CCValAssign::SExt;
3343
0
    else if (ArgFlags.isZExt())
3344
0
        LocInfo = CCValAssign::ZExt;
3345
0
    else
3346
0
        LocInfo = CCValAssign::AExt;
3347
0
  }
3348
70
3349
70
  if (LocVT == MVT::i64) {
3350
70
    static const MCPhysReg RegList1[] = {
3351
70
      X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9, X86::RAX, X86::R10, X86::R11, X86::R13, X86::R14, X86::R15
3352
70
    };
3353
70
    if (unsigned Reg = State.AllocateReg(RegList1)) {
3354
70
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3355
70
      return false;
3356
70
    }
3357
0
  }
3358
0
3359
0
  return true;  // CC didn't match.
3360
0
}
3361
3362
3363
static bool RetCC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
3364
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
3365
28
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
3366
28
3367
28
  if (LocVT == MVT::i8 ||
3368
28
      LocVT == MVT::i16 ||
3369
28
      LocVT == MVT::i32) {
3370
10
    LocVT = MVT::i64;
3371
10
    if (ArgFlags.isSExt())
3372
0
        LocInfo = CCValAssign::SExt;
3373
10
    else if (ArgFlags.isZExt())
3374
0
        LocInfo = CCValAssign::ZExt;
3375
10
    else
3376
10
        LocInfo = CCValAssign::AExt;
3377
10
  }
3378
28
3379
28
  if (LocVT == MVT::i64) {
3380
28
    static const MCPhysReg RegList1[] = {
3381
28
      X86::R15, X86::RBP, X86::RAX, X86::RDX
3382
28
    };
3383
28
    if (unsigned Reg = State.AllocateReg(RegList1)) {
3384
28
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3385
28
      return false;
3386
28
    }
3387
0
  }
3388
0
3389
0
  return true;  // CC didn't match.
3390
0
}
3391
3392
3393
static bool RetCC_X86_64_Swift(unsigned ValNo, MVT ValVT,
3394
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
3395
411
                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
3396
411
3397
411
  if (ArgFlags.isSwiftError()) {
3398
54
    if (LocVT == MVT::i64) {
3399
54
      if (unsigned Reg = State.AllocateReg(X86::R12)) {
3400
54
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3401
54
        return false;
3402
54
      }
3403
357
    }
3404
54
  }
3405
357
3406
357
  if (LocVT == MVT::v1i1) {
3407
0
    LocVT = MVT::i8;
3408
0
    if (ArgFlags.isSExt())
3409
0
        LocInfo = CCValAssign::SExt;
3410
0
    else if (ArgFlags.isZExt())
3411
0
        LocInfo = CCValAssign::ZExt;
3412
0
    else
3413
0
        LocInfo = CCValAssign::AExt;
3414
0
  }
3415
357
3416
357
  if (LocVT == MVT::i1) {
3417
0
    LocVT = MVT::i8;
3418
0
    if (ArgFlags.isSExt())
3419
0
        LocInfo = CCValAssign::SExt;
3420
0
    else if (ArgFlags.isZExt())
3421
0
        LocInfo = CCValAssign::ZExt;
3422
0
    else
3423
0
        LocInfo = CCValAssign::AExt;
3424
0
  }
3425
357
3426
357
  if (LocVT == MVT::i8) {
3427
38
    static const MCPhysReg RegList1[] = {
3428
38
      X86::AL, X86::DL, X86::CL, X86::R8B
3429
38
    };
3430
38
    if (unsigned Reg = State.AllocateReg(RegList1)) {
3431
38
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3432
38
      return false;
3433
38
    }
3434
319
  }
3435
319
3436
319
  if (LocVT == MVT::i16) {
3437
4
    static const MCPhysReg RegList2[] = {
3438
4
      X86::AX, X86::DX, X86::CX, X86::R8W
3439
4
    };
3440
4
    if (unsigned Reg = State.AllocateReg(RegList2)) {
3441
4
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3442
4
      return false;
3443
4
    }
3444
315
  }
3445
315
3446
315
  if (LocVT == MVT::i32) {
3447
69
    static const MCPhysReg RegList3[] = {
3448
69
      X86::EAX, X86::EDX, X86::ECX, X86::R8D
3449
69
    };
3450
69
    if (unsigned Reg = State.AllocateReg(RegList3)) {
3451
64
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3452
64
      return false;
3453
64
    }
3454
251
  }
3455
251
3456
251
  if (LocVT == MVT::i64) {
3457
100
    static const MCPhysReg RegList4[] = {
3458
100
      X86::RAX, X86::RDX, X86::RCX, X86::R8
3459
100
    };
3460
100
    if (unsigned Reg = State.AllocateReg(RegList4)) {
3461
100
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3462
100
      return false;
3463
100
    }
3464
151
  }
3465
151
3466
151
  if (LocVT == MVT::f32) {
3467
54
    static const MCPhysReg RegList5[] = {
3468
54
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3469
54
    };
3470
54
    if (unsigned Reg = State.AllocateReg(RegList5)) {
3471
54
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3472
54
      return false;
3473
54
    }
3474
97
  }
3475
97
3476
97
  if (LocVT == MVT::f64) {
3477
56
    static const MCPhysReg RegList6[] = {
3478
56
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3479
56
    };
3480
56
    if (unsigned Reg = State.AllocateReg(RegList6)) {
3481
56
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3482
56
      return false;
3483
56
    }
3484
41
  }
3485
41
3486
41
  if (LocVT == MVT::f128) {
3487
0
    static const MCPhysReg RegList7[] = {
3488
0
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3489
0
    };
3490
0
    if (unsigned Reg = State.AllocateReg(RegList7)) {
3491
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3492
0
      return false;
3493
0
    }
3494
41
  }
3495
41
3496
41
  if (LocVT == MVT::x86mmx) {
3497
0
    static const MCPhysReg RegList8[] = {
3498
0
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3499
0
    };
3500
0
    if (unsigned Reg = State.AllocateReg(RegList8)) {
3501
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3502
0
      return false;
3503
0
    }
3504
41
  }
3505
41
3506
41
  if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3507
36
    return false;
3508
5
3509
5
  return true;  // CC didn't match.
3510
5
}
3511
3512
3513
static bool RetCC_X86_64_Vectorcall(unsigned ValNo, MVT ValVT,
3514
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
3515
60
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
3516
60
3517
60
  if (LocVT == MVT::f32 ||
3518
60
      LocVT == MVT::f64 ||
3519
60
      
LocVT == MVT::f12834
) {
3520
26
    static const MCPhysReg RegList1[] = {
3521
26
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3522
26
    };
3523
26
    if (unsigned Reg = State.AllocateReg(RegList1)) {
3524
24
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3525
24
      return false;
3526
24
    }
3527
36
  }
3528
36
3529
36
  if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3530
34
    return false;
3531
2
3532
2
  return true;  // CC didn't match.
3533
2
}
3534
3535
3536
static bool RetCC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT,
3537
                                   MVT LocVT, CCValAssign::LocInfo LocInfo,
3538
20
                                   ISD::ArgFlagsTy ArgFlags, CCState &State) {
3539
20
3540
20
  if (LocVT == MVT::i8 ||
3541
20
      LocVT == MVT::i16 ||
3542
20
      LocVT == MVT::i32) {
3543
8
    LocVT = MVT::i64;
3544
8
    if (ArgFlags.isSExt())
3545
0
        LocInfo = CCValAssign::SExt;
3546
8
    else if (ArgFlags.isZExt())
3547
0
        LocInfo = CCValAssign::ZExt;
3548
8
    else
3549
8
        LocInfo = CCValAssign::AExt;
3550
8
  }
3551
20
3552
20
  if (LocVT == MVT::i64) {
3553
20
    if (unsigned Reg = State.AllocateReg(X86::RAX)) {
3554
20
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3555
20
      return false;
3556
20
    }
3557
0
  }
3558
0
3559
0
  return true;  // CC didn't match.
3560
0
}
3561
3562
3563
static bool RetCC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
3564
                                     MVT LocVT, CCValAssign::LocInfo LocInfo,
3565
158
                                     ISD::ArgFlagsTy ArgFlags, CCState &State) {
3566
158
3567
158
  if (LocVT == MVT::i1 ||
3568
158
      LocVT == MVT::v1i1 ||
3569
158
      LocVT == MVT::v8i1) {
3570
4
    LocVT = MVT::i8;
3571
4
    if (ArgFlags.isSExt())
3572
0
        LocInfo = CCValAssign::SExt;
3573
4
    else if (ArgFlags.isZExt())
3574
0
        LocInfo = CCValAssign::ZExt;
3575
4
    else
3576
4
        LocInfo = CCValAssign::AExt;
3577
4
  }
3578
158
3579
158
  if (LocVT == MVT::v16i1) {
3580
4
    LocVT = MVT::i16;
3581
4
    if (ArgFlags.isSExt())
3582
0
        LocInfo = CCValAssign::SExt;
3583
4
    else if (ArgFlags.isZExt())
3584
0
        LocInfo = CCValAssign::ZExt;
3585
4
    else
3586
4
        LocInfo = CCValAssign::AExt;
3587
4
  }
3588
158
3589
158
  if (LocVT == MVT::v32i1) {
3590
4
    LocVT = MVT::i32;
3591
4
    if (ArgFlags.isSExt())
3592
0
        LocInfo = CCValAssign::SExt;
3593
4
    else if (ArgFlags.isZExt())
3594
0
        LocInfo = CCValAssign::ZExt;
3595
4
    else
3596
4
        LocInfo = CCValAssign::AExt;
3597
4
  }
3598
158
3599
158
  if (LocVT == MVT::i8) {
3600
28
    static const MCPhysReg RegList1[] = {
3601
28
      X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R12B, X86::R13B, X86::R14B, X86::R15B
3602
28
    };
3603
28
    if (unsigned Reg = State.AllocateReg(RegList1)) {
3604
28
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3605
28
      return false;
3606
28
    }
3607
130
  }
3608
130
3609
130
  if (LocVT == MVT::i16) {
3610
14
    static const MCPhysReg RegList2[] = {
3611
14
      X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R12W, X86::R13W, X86::R14W, X86::R15W
3612
14
    };
3613
14
    if (unsigned Reg = State.AllocateReg(RegList2)) {
3614
14
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3615
14
      return false;
3616
14
    }
3617
116
  }
3618
116
3619
116
  if (LocVT == MVT::i32) {
3620
22
    static const MCPhysReg RegList3[] = {
3621
22
      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D
3622
22
    };
3623
22
    if (unsigned Reg = State.AllocateReg(RegList3)) {
3624
22
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3625
22
      return false;
3626
22
    }
3627
94
  }
3628
94
3629
94
  if (LocVT == MVT::i64) {
3630
18
    static const MCPhysReg RegList4[] = {
3631
18
      X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
3632
18
    };
3633
18
    if (unsigned Reg = State.AllocateReg(RegList4)) {
3634
18
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3635
18
      return false;
3636
18
    }
3637
76
  }
3638
76
3639
76
  if (LocVT == MVT::v64i1) {
3640
4
    LocVT = MVT::i64;
3641
4
    if (ArgFlags.isSExt())
3642
0
        LocInfo = CCValAssign::SExt;
3643
4
    else if (ArgFlags.isZExt())
3644
0
        LocInfo = CCValAssign::ZExt;
3645
4
    else
3646
4
        LocInfo = CCValAssign::AExt;
3647
4
  }
3648
76
3649
76
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
3650
76
    if (LocVT == MVT::i64) {
3651
4
      static const MCPhysReg RegList5[] = {
3652
4
        X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
3653
4
      };
3654
4
      if (unsigned Reg = State.AllocateReg(RegList5)) {
3655
4
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3656
4
        return false;
3657
4
      }
3658
72
    }
3659
76
  }
3660
72
3661
72
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
3662
0
    if (LocVT == MVT::i64) {
3663
0
      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3664
0
            return false;
3665
72
    }
3666
0
  }
3667
72
3668
72
  if (LocVT == MVT::f80) {
3669
6
    static const MCPhysReg RegList6[] = {
3670
6
      X86::FP0, X86::FP1
3671
6
    };
3672
6
    if (unsigned Reg = State.AllocateReg(RegList6)) {
3673
6
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3674
6
      return false;
3675
6
    }
3676
66
  }
3677
66
3678
66
  if (LocVT == MVT::f32 ||
3679
66
      
LocVT == MVT::f6458
||
3680
66
      
LocVT == MVT::f12850
) {
3681
16
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3682
16
      static const MCPhysReg RegList7[] = {
3683
16
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
3684
16
      };
3685
16
      if (unsigned Reg = State.AllocateReg(RegList7)) {
3686
16
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3687
16
        return false;
3688
16
      }
3689
50
    }
3690
16
  }
3691
50
3692
50
  if (LocVT == MVT::v16i8 ||
3693
50
      LocVT == MVT::v8i16 ||
3694
50
      LocVT == MVT::v4i32 ||
3695
50
      
LocVT == MVT::v2i6444
||
3696
50
      
LocVT == MVT::v4f3244
||
3697
50
      
LocVT == MVT::v2f6420
) {
3698
30
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3699
30
      static const MCPhysReg RegList8[] = {
3700
30
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
3701
30
      };
3702
30
      if (unsigned Reg = State.AllocateReg(RegList8)) {
3703
30
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3704
30
        return false;
3705
30
      }
3706
20
    }
3707
30
  }
3708
20
3709
20
  if (LocVT == MVT::v32i8 ||
3710
20
      LocVT == MVT::v16i16 ||
3711
20
      LocVT == MVT::v8i32 ||
3712
20
      
LocVT == MVT::v4i6414
||
3713
20
      
LocVT == MVT::v8f3214
||
3714
20
      
LocVT == MVT::v4f6414
) {
3715
6
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
3716
6
      static const MCPhysReg RegList9[] = {
3717
6
        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
3718
6
      };
3719
6
      if (unsigned Reg = State.AllocateReg(RegList9)) {
3720
6
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3721
6
        return false;
3722
6
      }
3723
14
    }
3724
6
  }
3725
14
3726
14
  if (LocVT == MVT::v64i8 ||
3727
14
      LocVT == MVT::v32i16 ||
3728
14
      LocVT == MVT::v16i32 ||
3729
14
      
LocVT == MVT::v8i648
||
3730
14
      
LocVT == MVT::v16f328
||
3731
14
      
LocVT == MVT::v8f640
) {
3732
14
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
3733
14
      static const MCPhysReg RegList10[] = {
3734
14
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
3735
14
      };
3736
14
      if (unsigned Reg = State.AllocateReg(RegList10)) {
3737
14
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3738
14
        return false;
3739
14
      }
3740
0
    }
3741
14
  }
3742
0
3743
0
  return true;  // CC didn't match.
3744
0
}
3745
3746
3747
static bool RetCC_X86_Win64_C(unsigned ValNo, MVT ValVT,
3748
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
3749
2.72k
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
3750
2.72k
3751
2.72k
  if (LocVT == MVT::x86mmx) {
3752
0
    LocVT = MVT::i64;
3753
0
    LocInfo = CCValAssign::BCvt;
3754
0
  }
3755
2.72k
3756
2.72k
  if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3757
2.70k
    return false;
3758
19
3759
19
  return true;  // CC didn't match.
3760
19
}
3761
3762
3763
static bool RetCC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
3764
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
3765
184
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
3766
184
3767
184
  if (LocVT == MVT::i1 ||
3768
184
      LocVT == MVT::v1i1 ||
3769
184
      LocVT == MVT::v8i1) {
3770
4
    LocVT = MVT::i8;
3771
4
    if (ArgFlags.isSExt())
3772
0
        LocInfo = CCValAssign::SExt;
3773
4
    else if (ArgFlags.isZExt())
3774
0
        LocInfo = CCValAssign::ZExt;
3775
4
    else
3776
4
        LocInfo = CCValAssign::AExt;
3777
4
  }
3778
184
3779
184
  if (LocVT == MVT::v16i1) {
3780
4
    LocVT = MVT::i16;
3781
4
    if (ArgFlags.isSExt())
3782
0
        LocInfo = CCValAssign::SExt;
3783
4
    else if (ArgFlags.isZExt())
3784
0
        LocInfo = CCValAssign::ZExt;
3785
4
    else
3786
4
        LocInfo = CCValAssign::AExt;
3787
4
  }
3788
184
3789
184
  if (LocVT == MVT::v32i1) {
3790
4
    LocVT = MVT::i32;
3791
4
    if (ArgFlags.isSExt())
3792
0
        LocInfo = CCValAssign::SExt;
3793
4
    else if (ArgFlags.isZExt())
3794
0
        LocInfo = CCValAssign::ZExt;
3795
4
    else
3796
4
        LocInfo = CCValAssign::AExt;
3797
4
  }
3798
184
3799
184
  if (LocVT == MVT::i8) {
3800
28
    static const MCPhysReg RegList1[] = {
3801
28
      X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R12B, X86::R14B, X86::R15B
3802
28
    };
3803
28
    if (unsigned Reg = State.AllocateReg(RegList1)) {
3804
28
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3805
28
      return false;
3806
28
    }
3807
156
  }
3808
156
3809
156
  if (LocVT == MVT::i16) {
3810
14
    static const MCPhysReg RegList2[] = {
3811
14
      X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R12W, X86::R14W, X86::R15W
3812
14
    };
3813
14
    if (unsigned Reg = State.AllocateReg(RegList2)) {
3814
14
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3815
14
      return false;
3816
14
    }
3817
142
  }
3818
142
3819
142
  if (LocVT == MVT::i32) {
3820
30
    static const MCPhysReg RegList3[] = {
3821
30
      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
3822
30
    };
3823
30
    if (unsigned Reg = State.AllocateReg(RegList3)) {
3824
30
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3825
30
      return false;
3826
30
    }
3827
112
  }
3828
112
3829
112
  if (LocVT == MVT::i64) {
3830
36
    static const MCPhysReg RegList4[] = {
3831
36
      X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
3832
36
    };
3833
36
    if (unsigned Reg = State.AllocateReg(RegList4)) {
3834
36
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3835
36
      return false;
3836
36
    }
3837
76
  }
3838
76
3839
76
  if (LocVT == MVT::v64i1) {
3840
4
    LocVT = MVT::i64;
3841
4
    if (ArgFlags.isSExt())
3842
0
        LocInfo = CCValAssign::SExt;
3843
4
    else if (ArgFlags.isZExt())
3844
0
        LocInfo = CCValAssign::ZExt;
3845
4
    else
3846
4
        LocInfo = CCValAssign::AExt;
3847
4
  }
3848
76
3849
76
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
3850
76
    if (LocVT == MVT::i64) {
3851
4
      static const MCPhysReg RegList5[] = {
3852
4
        X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
3853
4
      };
3854
4
      if (unsigned Reg = State.AllocateReg(RegList5)) {
3855
4
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3856
4
        return false;
3857
4
      }
3858
72
    }
3859
76
  }
3860
72
3861
72
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
3862
0
    if (LocVT == MVT::i64) {
3863
0
      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3864
0
            return false;
3865
72
    }
3866
0
  }
3867
72
3868
72
  if (LocVT == MVT::f80) {
3869
6
    static const MCPhysReg RegList6[] = {
3870
6
      X86::FP0, X86::FP1
3871
6
    };
3872
6
    if (unsigned Reg = State.AllocateReg(RegList6)) {
3873
6
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3874
6
      return false;
3875
6
    }
3876
66
  }
3877
66
3878
66
  if (LocVT == MVT::f32 ||
3879
66
      
LocVT == MVT::f6458
||
3880
66
      
LocVT == MVT::f12850
) {
3881
16
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3882
16
      static const MCPhysReg RegList7[] = {
3883
16
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
3884
16
      };
3885
16
      if (unsigned Reg = State.AllocateReg(RegList7)) {
3886
16
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3887
16
        return false;
3888
16
      }
3889
50
    }
3890
16
  }
3891
50
3892
50
  if (LocVT == MVT::v16i8 ||
3893
50
      LocVT == MVT::v8i16 ||
3894
50
      LocVT == MVT::v4i32 ||
3895
50
      
LocVT == MVT::v2i6444
||
3896
50
      
LocVT == MVT::v4f3244
||
3897
50
      
LocVT == MVT::v2f6420
) {
3898
30
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3899
30
      static const MCPhysReg RegList8[] = {
3900
30
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
3901
30
      };
3902
30
      if (unsigned Reg = State.AllocateReg(RegList8)) {
3903
30
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3904
30
        return false;
3905
30
      }
3906
20
    }
3907
30
  }
3908
20
3909
20
  if (LocVT == MVT::v32i8 ||
3910
20
      LocVT == MVT::v16i16 ||
3911
20
      LocVT == MVT::v8i32 ||
3912
20
      
LocVT == MVT::v4i6414
||
3913
20
      
LocVT == MVT::v8f3214
||
3914
20
      
LocVT == MVT::v4f6414
) {
3915
6
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
3916
6
      static const MCPhysReg RegList9[] = {
3917
6
        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
3918
6
      };
3919
6
      if (unsigned Reg = State.AllocateReg(RegList9)) {
3920
6
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3921
6
        return false;
3922
6
      }
3923
14
    }
3924
6
  }
3925
14
3926
14
  if (LocVT == MVT::v64i8 ||
3927
14
      LocVT == MVT::v32i16 ||
3928
14
      LocVT == MVT::v16i32 ||
3929
14
      
LocVT == MVT::v8i648
||
3930
14
      
LocVT == MVT::v16f328
||
3931
14
      
LocVT == MVT::v8f640
) {
3932
14
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
3933
14
      static const MCPhysReg RegList10[] = {
3934
14
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
3935
14
      };
3936
14
      if (unsigned Reg = State.AllocateReg(RegList10)) {
3937
14
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3938
14
        return false;
3939
14
      }
3940
0
    }
3941
14
  }
3942
0
3943
0
  return true;  // CC didn't match.
3944
0
}