Coverage Report

Created: 2018-09-23 22:08

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/X86/X86GenCallingConv.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Calling Convention Implementation Fragment                                 *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
10
                            MVT LocVT, CCValAssign::LocInfo LocInfo,
11
                            ISD::ArgFlagsTy ArgFlags, CCState &State);
12
static bool CC_X86(unsigned ValNo, MVT ValVT,
13
                   MVT LocVT, CCValAssign::LocInfo LocInfo,
14
                   ISD::ArgFlagsTy ArgFlags, CCState &State);
15
static bool CC_X86_32(unsigned ValNo, MVT ValVT,
16
                      MVT LocVT, CCValAssign::LocInfo LocInfo,
17
                      ISD::ArgFlagsTy ArgFlags, CCState &State);
18
static bool CC_X86_32_C(unsigned ValNo, MVT ValVT,
19
                        MVT LocVT, CCValAssign::LocInfo LocInfo,
20
                        ISD::ArgFlagsTy ArgFlags, CCState &State);
21
static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT,
22
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
23
                             ISD::ArgFlagsTy ArgFlags, CCState &State);
24
static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT,
25
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
26
                             ISD::ArgFlagsTy ArgFlags, CCState &State);
27
static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT,
28
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
29
                               ISD::ArgFlagsTy ArgFlags, CCState &State);
30
static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT,
31
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
32
                          ISD::ArgFlagsTy ArgFlags, CCState &State);
33
static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
34
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
35
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
36
static bool CC_X86_32_Intr(unsigned ValNo, MVT ValVT,
37
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
38
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
39
static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT,
40
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
41
                          ISD::ArgFlagsTy ArgFlags, CCState &State);
42
static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
43
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
44
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
45
static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT,
46
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
47
                               ISD::ArgFlagsTy ArgFlags, CCState &State);
48
static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT,
49
                                      MVT LocVT, CCValAssign::LocInfo LocInfo,
50
                                      ISD::ArgFlagsTy ArgFlags, CCState &State);
51
static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT,
52
                                     MVT LocVT, CCValAssign::LocInfo LocInfo,
53
                                     ISD::ArgFlagsTy ArgFlags, CCState &State);
54
static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT,
55
                                   MVT LocVT, CCValAssign::LocInfo LocInfo,
56
                                   ISD::ArgFlagsTy ArgFlags, CCState &State);
57
static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT,
58
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
59
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
60
static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT,
61
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
62
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
63
static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT,
64
                                      MVT LocVT, CCValAssign::LocInfo LocInfo,
65
                                      ISD::ArgFlagsTy ArgFlags, CCState &State);
66
static bool CC_X86_64(unsigned ValNo, MVT ValVT,
67
                      MVT LocVT, CCValAssign::LocInfo LocInfo,
68
                      ISD::ArgFlagsTy ArgFlags, CCState &State);
69
static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
70
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
71
                             ISD::ArgFlagsTy ArgFlags, CCState &State);
72
static bool CC_X86_64_C(unsigned ValNo, MVT ValVT,
73
                        MVT LocVT, CCValAssign::LocInfo LocInfo,
74
                        ISD::ArgFlagsTy ArgFlags, CCState &State);
75
static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT,
76
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
77
                          ISD::ArgFlagsTy ArgFlags, CCState &State);
78
static bool CC_X86_64_HHVM(unsigned ValNo, MVT ValVT,
79
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
80
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
81
static bool CC_X86_64_HHVM_C(unsigned ValNo, MVT ValVT,
82
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
83
                             ISD::ArgFlagsTy ArgFlags, CCState &State);
84
static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
85
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
86
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
87
static bool CC_X86_64_Intr(unsigned ValNo, MVT ValVT,
88
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
89
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
90
static bool CC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT,
91
                                MVT LocVT, CCValAssign::LocInfo LocInfo,
92
                                ISD::ArgFlagsTy ArgFlags, CCState &State);
93
static bool CC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
94
                                  MVT LocVT, CCValAssign::LocInfo LocInfo,
95
                                  ISD::ArgFlagsTy ArgFlags, CCState &State);
96
static bool CC_X86_Win32_VectorCall(unsigned ValNo, MVT ValVT,
97
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
98
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
99
static bool CC_X86_Win64_C(unsigned ValNo, MVT ValVT,
100
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
101
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
102
static bool CC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
103
                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
104
                                 ISD::ArgFlagsTy ArgFlags, CCState &State);
105
static bool CC_X86_Win64_VectorCall(unsigned ValNo, MVT ValVT,
106
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
107
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
108
static bool RetCC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
109
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
110
                               ISD::ArgFlagsTy ArgFlags, CCState &State);
111
static bool RetCC_X86(unsigned ValNo, MVT ValVT,
112
                      MVT LocVT, CCValAssign::LocInfo LocInfo,
113
                      ISD::ArgFlagsTy ArgFlags, CCState &State);
114
static bool RetCC_X86Common(unsigned ValNo, MVT ValVT,
115
                            MVT LocVT, CCValAssign::LocInfo LocInfo,
116
                            ISD::ArgFlagsTy ArgFlags, CCState &State);
117
static bool RetCC_X86_32(unsigned ValNo, MVT ValVT,
118
                         MVT LocVT, CCValAssign::LocInfo LocInfo,
119
                         ISD::ArgFlagsTy ArgFlags, CCState &State);
120
static bool RetCC_X86_32_C(unsigned ValNo, MVT ValVT,
121
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
122
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
123
static bool RetCC_X86_32_Fast(unsigned ValNo, MVT ValVT,
124
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
125
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
126
static bool RetCC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
127
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
128
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
129
static bool RetCC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
130
                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
131
                                 ISD::ArgFlagsTy ArgFlags, CCState &State);
132
static bool RetCC_X86_32_VectorCall(unsigned ValNo, MVT ValVT,
133
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
134
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
135
static bool RetCC_X86_64(unsigned ValNo, MVT ValVT,
136
                         MVT LocVT, CCValAssign::LocInfo LocInfo,
137
                         ISD::ArgFlagsTy ArgFlags, CCState &State);
138
static bool RetCC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
139
                                MVT LocVT, CCValAssign::LocInfo LocInfo,
140
                                ISD::ArgFlagsTy ArgFlags, CCState &State);
141
static bool RetCC_X86_64_C(unsigned ValNo, MVT ValVT,
142
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
143
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
144
static bool RetCC_X86_64_HHVM(unsigned ValNo, MVT ValVT,
145
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
146
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
147
static bool RetCC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
148
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
149
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
150
static bool RetCC_X86_64_Swift(unsigned ValNo, MVT ValVT,
151
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
152
                               ISD::ArgFlagsTy ArgFlags, CCState &State);
153
static bool RetCC_X86_64_Vectorcall(unsigned ValNo, MVT ValVT,
154
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
155
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
156
static bool RetCC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT,
157
                                   MVT LocVT, CCValAssign::LocInfo LocInfo,
158
                                   ISD::ArgFlagsTy ArgFlags, CCState &State);
159
static bool RetCC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
160
                                     MVT LocVT, CCValAssign::LocInfo LocInfo,
161
                                     ISD::ArgFlagsTy ArgFlags, CCState &State);
162
static bool RetCC_X86_Win64_C(unsigned ValNo, MVT ValVT,
163
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
164
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
165
static bool RetCC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
166
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
167
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
168
169
170
static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
171
                            MVT LocVT, CCValAssign::LocInfo LocInfo,
172
238
                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
173
238
174
238
  if (LocVT == MVT::i32) {
175
22
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
176
2
      static const MCPhysReg RegList1[] = {
177
2
        X86::ECX, X86::EDX, X86::R8D, X86::R9D
178
2
      };
179
2
      if (unsigned Reg = State.AllocateReg(RegList1)) {
180
2
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
181
2
        return false;
182
2
      }
183
236
    }
184
22
  }
185
236
186
236
  if (LocVT == MVT::i64) {
187
16
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
188
8
      static const MCPhysReg RegList2[] = {
189
8
        X86::RCX, X86::RDX, X86::R8, X86::R9
190
8
      };
191
8
      if (unsigned Reg = State.AllocateReg(RegList2)) {
192
8
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
193
8
        return false;
194
8
      }
195
228
    }
196
16
  }
197
228
198
228
  if (LocVT == MVT::i32) {
199
20
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
200
2
      static const MCPhysReg RegList3[] = {
201
2
        X86::EDI, X86::ESI, X86::EDX, X86::ECX
202
2
      };
203
2
      if (unsigned Reg = State.AllocateReg(RegList3)) {
204
2
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
205
2
        return false;
206
2
      }
207
226
    }
208
20
  }
209
226
210
226
  if (LocVT == MVT::i64) {
211
8
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
212
8
      static const MCPhysReg RegList4[] = {
213
8
        X86::RDI, X86::RSI, X86::RDX, X86::RCX
214
8
      };
215
8
      if (unsigned Reg = State.AllocateReg(RegList4)) {
216
8
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
217
8
        return false;
218
8
      }
219
218
    }
220
8
  }
221
218
222
218
  if (LocVT == MVT::i32) {
223
18
    unsigned Offset5 = State.AllocateStack(4, 4);
224
18
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
225
18
    return false;
226
18
  }
227
200
228
200
  if (LocVT == MVT::f32 ||
229
200
      LocVT == MVT::f64 ||
230
200
      LocVT == MVT::v4i32 ||
231
200
      LocVT == MVT::v2i64 ||
232
200
      LocVT == MVT::v4f32 ||
233
200
      
LocVT == MVT::v2f64128
) {
234
72
    static const MCPhysReg RegList6[] = {
235
72
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
236
72
    };
237
72
    if (unsigned Reg = State.AllocateReg(RegList6)) {
238
60
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
239
60
      return false;
240
60
    }
241
140
  }
242
140
243
140
  if (LocVT == MVT::v8f32 ||
244
140
      
LocVT == MVT::v4f64108
||
245
140
      
LocVT == MVT::v8i32108
||
246
140
      
LocVT == MVT::v4i64108
) {
247
32
    static const MCPhysReg RegList7[] = {
248
32
      X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
249
32
    };
250
32
    if (unsigned Reg = State.AllocateReg(RegList7)) {
251
32
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
252
32
      return false;
253
32
    }
254
108
  }
255
108
256
108
  if (LocVT == MVT::v16f32 ||
257
108
      
LocVT == MVT::v8f6452
||
258
108
      
LocVT == MVT::v16i3252
||
259
108
      
LocVT == MVT::v8i6436
) {
260
72
    static const MCPhysReg RegList8[] = {
261
72
      X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
262
72
    };
263
72
    if (unsigned Reg = State.AllocateReg(RegList8)) {
264
72
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
265
72
      return false;
266
72
    }
267
36
  }
268
36
269
36
  if (LocVT == MVT::v16i1 ||
270
36
      
LocVT == MVT::v8i112
) {
271
24
    if (unsigned Reg = State.AllocateReg(X86::K1)) {
272
24
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
273
24
      return false;
274
24
    }
275
12
  }
276
12
277
12
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
278
4
    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
279
4
      return false;
280
8
  }
281
8
282
8
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
283
4
    if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
284
4
      return false;
285
4
  }
286
4
287
4
  if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
288
4
    return false;
289
0
290
0
  return true;  // CC didn't match.
291
0
}
Unexecuted instantiation: X86CallLowering.cpp:CC_Intel_OCL_BI(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86FastISel.cpp:CC_Intel_OCL_BI(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:CC_Intel_OCL_BI(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
172
238
                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
173
238
174
238
  if (LocVT == MVT::i32) {
175
22
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
176
2
      static const MCPhysReg RegList1[] = {
177
2
        X86::ECX, X86::EDX, X86::R8D, X86::R9D
178
2
      };
179
2
      if (unsigned Reg = State.AllocateReg(RegList1)) {
180
2
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
181
2
        return false;
182
2
      }
183
236
    }
184
22
  }
185
236
186
236
  if (LocVT == MVT::i64) {
187
16
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
188
8
      static const MCPhysReg RegList2[] = {
189
8
        X86::RCX, X86::RDX, X86::R8, X86::R9
190
8
      };
191
8
      if (unsigned Reg = State.AllocateReg(RegList2)) {
192
8
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
193
8
        return false;
194
8
      }
195
228
    }
196
16
  }
197
228
198
228
  if (LocVT == MVT::i32) {
199
20
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
200
2
      static const MCPhysReg RegList3[] = {
201
2
        X86::EDI, X86::ESI, X86::EDX, X86::ECX
202
2
      };
203
2
      if (unsigned Reg = State.AllocateReg(RegList3)) {
204
2
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
205
2
        return false;
206
2
      }
207
226
    }
208
20
  }
209
226
210
226
  if (LocVT == MVT::i64) {
211
8
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
212
8
      static const MCPhysReg RegList4[] = {
213
8
        X86::RDI, X86::RSI, X86::RDX, X86::RCX
214
8
      };
215
8
      if (unsigned Reg = State.AllocateReg(RegList4)) {
216
8
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
217
8
        return false;
218
8
      }
219
218
    }
220
8
  }
221
218
222
218
  if (LocVT == MVT::i32) {
223
18
    unsigned Offset5 = State.AllocateStack(4, 4);
224
18
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
225
18
    return false;
226
18
  }
227
200
228
200
  if (LocVT == MVT::f32 ||
229
200
      LocVT == MVT::f64 ||
230
200
      LocVT == MVT::v4i32 ||
231
200
      LocVT == MVT::v2i64 ||
232
200
      LocVT == MVT::v4f32 ||
233
200
      
LocVT == MVT::v2f64128
) {
234
72
    static const MCPhysReg RegList6[] = {
235
72
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
236
72
    };
237
72
    if (unsigned Reg = State.AllocateReg(RegList6)) {
238
60
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
239
60
      return false;
240
60
    }
241
140
  }
242
140
243
140
  if (LocVT == MVT::v8f32 ||
244
140
      
LocVT == MVT::v4f64108
||
245
140
      
LocVT == MVT::v8i32108
||
246
140
      
LocVT == MVT::v4i64108
) {
247
32
    static const MCPhysReg RegList7[] = {
248
32
      X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
249
32
    };
250
32
    if (unsigned Reg = State.AllocateReg(RegList7)) {
251
32
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
252
32
      return false;
253
32
    }
254
108
  }
255
108
256
108
  if (LocVT == MVT::v16f32 ||
257
108
      
LocVT == MVT::v8f6452
||
258
108
      
LocVT == MVT::v16i3252
||
259
108
      
LocVT == MVT::v8i6436
) {
260
72
    static const MCPhysReg RegList8[] = {
261
72
      X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
262
72
    };
263
72
    if (unsigned Reg = State.AllocateReg(RegList8)) {
264
72
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
265
72
      return false;
266
72
    }
267
36
  }
268
36
269
36
  if (LocVT == MVT::v16i1 ||
270
36
      
LocVT == MVT::v8i112
) {
271
24
    if (unsigned Reg = State.AllocateReg(X86::K1)) {
272
24
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
273
24
      return false;
274
24
    }
275
12
  }
276
12
277
12
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
278
4
    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
279
4
      return false;
280
8
  }
281
8
282
8
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
283
4
    if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
284
4
      return false;
285
4
  }
286
4
287
4
  if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
288
4
    return false;
289
0
290
0
  return true;  // CC didn't match.
291
0
}
292
293
294
static bool CC_X86(unsigned ValNo, MVT ValVT,
295
                   MVT LocVT, CCValAssign::LocInfo LocInfo,
296
648k
                   ISD::ArgFlagsTy ArgFlags, CCState &State) {
297
648k
298
648k
  if (State.getCallingConv() == CallingConv::Intel_OCL_BI) {
299
238
    if (!CC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
300
238
      return false;
301
647k
  }
302
647k
303
647k
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
304
483k
    if (!CC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
305
482k
      return false;
306
165k
  }
307
165k
308
165k
  if (!CC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
309
165k
    return false;
310
0
311
0
  return true;  // CC didn't match.
312
0
}
X86CallLowering.cpp:CC_X86(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
296
919
                   ISD::ArgFlagsTy ArgFlags, CCState &State) {
297
919
298
919
  if (State.getCallingConv() == CallingConv::Intel_OCL_BI) {
299
0
    if (!CC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
300
0
      return false;
301
919
  }
302
919
303
919
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
304
727
    if (!CC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
305
727
      return false;
306
192
  }
307
192
308
192
  if (!CC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
309
192
    return false;
310
0
311
0
  return true;  // CC didn't match.
312
0
}
X86FastISel.cpp:CC_X86(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
296
852
                   ISD::ArgFlagsTy ArgFlags, CCState &State) {
297
852
298
852
  if (State.getCallingConv() == CallingConv::Intel_OCL_BI) {
299
0
    if (!CC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
300
0
      return false;
301
852
  }
302
852
303
852
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
304
629
    if (!CC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
305
629
      return false;
306
223
  }
307
223
308
223
  if (!CC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
309
223
    return false;
310
0
311
0
  return true;  // CC didn't match.
312
0
}
X86ISelLowering.cpp:CC_X86(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
296
646k
                   ISD::ArgFlagsTy ArgFlags, CCState &State) {
297
646k
298
646k
  if (State.getCallingConv() == CallingConv::Intel_OCL_BI) {
299
238
    if (!CC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
300
238
      return false;
301
646k
  }
302
646k
303
646k
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
304
482k
    if (!CC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
305
480k
      return false;
306
165k
  }
307
165k
308
165k
  if (!CC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
309
165k
    return false;
310
0
311
0
  return true;  // CC didn't match.
312
0
}
313
314
315
static bool CC_X86_32(unsigned ValNo, MVT ValVT,
316
                      MVT LocVT, CCValAssign::LocInfo LocInfo,
317
165k
                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
318
165k
319
165k
  if (State.getCallingConv() == CallingConv::X86_INTR) {
320
16
    if (!CC_X86_32_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
321
16
      return false;
322
165k
  }
323
165k
324
165k
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetMCU()) {
325
126
    if (!CC_X86_32_MCU(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
326
126
      return false;
327
165k
  }
328
165k
329
165k
  if (State.getCallingConv() == CallingConv::X86_FastCall) {
330
202
    if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
331
196
      return false;
332
165k
  }
333
165k
334
165k
  if (State.getCallingConv() == CallingConv::X86_VectorCall) {
335
244
    if (!CC_X86_Win32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
336
244
      return false;
337
165k
  }
338
165k
339
165k
  if (State.getCallingConv() == CallingConv::X86_ThisCall) {
340
448
    if (!CC_X86_32_ThisCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
341
448
      return false;
342
164k
  }
343
164k
344
164k
  if (State.getCallingConv() == CallingConv::Fast) {
345
2.95k
    if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
346
2.95k
      return false;
347
161k
  }
348
161k
349
161k
  if (State.getCallingConv() == CallingConv::GHC) {
350
20
    if (!CC_X86_32_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
351
20
      return false;
352
161k
  }
353
161k
354
161k
  if (State.getCallingConv() == CallingConv::HiPE) {
355
42
    if (!CC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
356
42
      return false;
357
161k
  }
358
161k
359
161k
  if (State.getCallingConv() == CallingConv::X86_RegCall) {
360
200
    if (!CC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
361
200
      return false;
362
161k
  }
363
161k
364
161k
  if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
365
161k
    return false;
366
0
367
0
  return true;  // CC didn't match.
368
0
}
X86CallLowering.cpp:CC_X86_32(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
317
192
                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
318
192
319
192
  if (State.getCallingConv() == CallingConv::X86_INTR) {
320
0
    if (!CC_X86_32_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
321
0
      return false;
322
192
  }
323
192
324
192
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetMCU()) {
325
0
    if (!CC_X86_32_MCU(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
326
0
      return false;
327
192
  }
328
192
329
192
  if (State.getCallingConv() == CallingConv::X86_FastCall) {
330
0
    if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
331
0
      return false;
332
192
  }
333
192
334
192
  if (State.getCallingConv() == CallingConv::X86_VectorCall) {
335
0
    if (!CC_X86_Win32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
336
0
      return false;
337
192
  }
338
192
339
192
  if (State.getCallingConv() == CallingConv::X86_ThisCall) {
340
0
    if (!CC_X86_32_ThisCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
341
0
      return false;
342
192
  }
343
192
344
192
  if (State.getCallingConv() == CallingConv::Fast) {
345
0
    if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
346
0
      return false;
347
192
  }
348
192
349
192
  if (State.getCallingConv() == CallingConv::GHC) {
350
0
    if (!CC_X86_32_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
351
0
      return false;
352
192
  }
353
192
354
192
  if (State.getCallingConv() == CallingConv::HiPE) {
355
0
    if (!CC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
356
0
      return false;
357
192
  }
358
192
359
192
  if (State.getCallingConv() == CallingConv::X86_RegCall) {
360
0
    if (!CC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
361
0
      return false;
362
192
  }
363
192
364
192
  if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
365
192
    return false;
366
0
367
0
  return true;  // CC didn't match.
368
0
}
X86FastISel.cpp:CC_X86_32(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
317
223
                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
318
223
319
223
  if (State.getCallingConv() == CallingConv::X86_INTR) {
320
0
    if (!CC_X86_32_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
321
0
      return false;
322
223
  }
323
223
324
223
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetMCU()) {
325
0
    if (!CC_X86_32_MCU(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
326
0
      return false;
327
223
  }
328
223
329
223
  if (State.getCallingConv() == CallingConv::X86_FastCall) {
330
0
    if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
331
0
      return false;
332
223
  }
333
223
334
223
  if (State.getCallingConv() == CallingConv::X86_VectorCall) {
335
0
    if (!CC_X86_Win32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
336
0
      return false;
337
223
  }
338
223
339
223
  if (State.getCallingConv() == CallingConv::X86_ThisCall) {
340
60
    if (!CC_X86_32_ThisCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
341
60
      return false;
342
163
  }
343
163
344
163
  if (State.getCallingConv() == CallingConv::Fast) {
345
4
    if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
346
4
      return false;
347
159
  }
348
159
349
159
  if (State.getCallingConv() == CallingConv::GHC) {
350
0
    if (!CC_X86_32_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
351
0
      return false;
352
159
  }
353
159
354
159
  if (State.getCallingConv() == CallingConv::HiPE) {
355
0
    if (!CC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
356
0
      return false;
357
159
  }
358
159
359
159
  if (State.getCallingConv() == CallingConv::X86_RegCall) {
360
0
    if (!CC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
361
0
      return false;
362
159
  }
363
159
364
159
  if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
365
159
    return false;
366
0
367
0
  return true;  // CC didn't match.
368
0
}
X86ISelLowering.cpp:CC_X86_32(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
317
165k
                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
318
165k
319
165k
  if (State.getCallingConv() == CallingConv::X86_INTR) {
320
16
    if (!CC_X86_32_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
321
16
      return false;
322
165k
  }
323
165k
324
165k
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetMCU()) {
325
126
    if (!CC_X86_32_MCU(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
326
126
      return false;
327
165k
  }
328
165k
329
165k
  if (State.getCallingConv() == CallingConv::X86_FastCall) {
330
202
    if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
331
196
      return false;
332
165k
  }
333
165k
334
165k
  if (State.getCallingConv() == CallingConv::X86_VectorCall) {
335
244
    if (!CC_X86_Win32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
336
244
      return false;
337
164k
  }
338
164k
339
164k
  if (State.getCallingConv() == CallingConv::X86_ThisCall) {
340
388
    if (!CC_X86_32_ThisCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
341
388
      return false;
342
164k
  }
343
164k
344
164k
  if (State.getCallingConv() == CallingConv::Fast) {
345
2.95k
    if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
346
2.95k
      return false;
347
161k
  }
348
161k
349
161k
  if (State.getCallingConv() == CallingConv::GHC) {
350
20
    if (!CC_X86_32_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
351
20
      return false;
352
161k
  }
353
161k
354
161k
  if (State.getCallingConv() == CallingConv::HiPE) {
355
42
    if (!CC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
356
42
      return false;
357
161k
  }
358
161k
359
161k
  if (State.getCallingConv() == CallingConv::X86_RegCall) {
360
200
    if (!CC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
361
200
      return false;
362
161k
  }
363
161k
364
161k
  if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
365
161k
    return false;
366
0
367
0
  return true;  // CC didn't match.
368
0
}
369
370
371
static bool CC_X86_32_C(unsigned ValNo, MVT ValVT,
372
                        MVT LocVT, CCValAssign::LocInfo LocInfo,
373
161k
                        ISD::ArgFlagsTy ArgFlags, CCState &State) {
374
161k
375
161k
  if (LocVT == MVT::i1 ||
376
161k
      
LocVT == MVT::i8161k
||
377
161k
      
LocVT == MVT::i16151k
||
378
161k
      
LocVT == MVT::v1i1149k
) {
379
11.9k
    LocVT = MVT::i32;
380
11.9k
    if (ArgFlags.isSExt())
381
94
        LocInfo = CCValAssign::SExt;
382
11.8k
    else if (ArgFlags.isZExt())
383
6.76k
        LocInfo = CCValAssign::ZExt;
384
5.12k
    else
385
5.12k
        LocInfo = CCValAssign::AExt;
386
11.9k
  }
387
161k
388
161k
  if (ArgFlags.isNest()) {
389
8
    if (unsigned Reg = State.AllocateReg(X86::ECX)) {
390
8
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
391
8
      return false;
392
8
    }
393
161k
  }
394
161k
395
161k
  if (!State.isVarArg()) {
396
154k
    if (ArgFlags.isInReg()) {
397
288
      if (LocVT == MVT::i32) {
398
264
        static const MCPhysReg RegList1[] = {
399
264
          X86::EAX, X86::EDX, X86::ECX
400
264
        };
401
264
        if (unsigned Reg = State.AllocateReg(RegList1)) {
402
255
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
403
255
          return false;
404
255
        }
405
161k
      }
406
288
    }
407
154k
  }
408
161k
409
161k
  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
410
161k
    return false;
411
0
412
0
  return true;  // CC didn't match.
413
0
}
X86CallLowering.cpp:CC_X86_32_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
373
192
                        ISD::ArgFlagsTy ArgFlags, CCState &State) {
374
192
375
192
  if (LocVT == MVT::i1 ||
376
192
      
LocVT == MVT::i8190
||
377
192
      
LocVT == MVT::i16169
||
378
192
      
LocVT == MVT::v1i1162
) {
379
30
    LocVT = MVT::i32;
380
30
    if (ArgFlags.isSExt())
381
2
        LocInfo = CCValAssign::SExt;
382
28
    else if (ArgFlags.isZExt())
383
2
        LocInfo = CCValAssign::ZExt;
384
26
    else
385
26
        LocInfo = CCValAssign::AExt;
386
30
  }
387
192
388
192
  if (ArgFlags.isNest()) {
389
0
    if (unsigned Reg = State.AllocateReg(X86::ECX)) {
390
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
391
0
      return false;
392
0
    }
393
192
  }
394
192
395
192
  if (!State.isVarArg()) {
396
192
    if (ArgFlags.isInReg()) {
397
0
      if (LocVT == MVT::i32) {
398
0
        static const MCPhysReg RegList1[] = {
399
0
          X86::EAX, X86::EDX, X86::ECX
400
0
        };
401
0
        if (unsigned Reg = State.AllocateReg(RegList1)) {
402
0
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
403
0
          return false;
404
0
        }
405
192
      }
406
0
    }
407
192
  }
408
192
409
192
  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
410
192
    return false;
411
0
412
0
  return true;  // CC didn't match.
413
0
}
X86FastISel.cpp:CC_X86_32_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
373
159
                        ISD::ArgFlagsTy ArgFlags, CCState &State) {
374
159
375
159
  if (LocVT == MVT::i1 ||
376
159
      LocVT == MVT::i8 ||
377
159
      
LocVT == MVT::i16157
||
378
159
      
LocVT == MVT::v1i1157
) {
379
2
    LocVT = MVT::i32;
380
2
    if (ArgFlags.isSExt())
381
0
        LocInfo = CCValAssign::SExt;
382
2
    else if (ArgFlags.isZExt())
383
0
        LocInfo = CCValAssign::ZExt;
384
2
    else
385
2
        LocInfo = CCValAssign::AExt;
386
2
  }
387
159
388
159
  if (ArgFlags.isNest()) {
389
0
    if (unsigned Reg = State.AllocateReg(X86::ECX)) {
390
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
391
0
      return false;
392
0
    }
393
159
  }
394
159
395
159
  if (!State.isVarArg()) {
396
147
    if (ArgFlags.isInReg()) {
397
11
      if (LocVT == MVT::i32) {
398
11
        static const MCPhysReg RegList1[] = {
399
11
          X86::EAX, X86::EDX, X86::ECX
400
11
        };
401
11
        if (unsigned Reg = State.AllocateReg(RegList1)) {
402
11
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
403
11
          return false;
404
11
        }
405
148
      }
406
11
    }
407
147
  }
408
148
409
148
  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
410
148
    return false;
411
0
412
0
  return true;  // CC didn't match.
413
0
}
X86ISelLowering.cpp:CC_X86_32_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
373
161k
                        ISD::ArgFlagsTy ArgFlags, CCState &State) {
374
161k
375
161k
  if (LocVT == MVT::i1 ||
376
161k
      LocVT == MVT::i8 ||
377
161k
      
LocVT == MVT::i16151k
||
378
161k
      
LocVT == MVT::v1i1149k
) {
379
11.9k
    LocVT = MVT::i32;
380
11.9k
    if (ArgFlags.isSExt())
381
92
        LocInfo = CCValAssign::SExt;
382
11.8k
    else if (ArgFlags.isZExt())
383
6.75k
        LocInfo = CCValAssign::ZExt;
384
5.09k
    else
385
5.09k
        LocInfo = CCValAssign::AExt;
386
11.9k
  }
387
161k
388
161k
  if (ArgFlags.isNest()) {
389
8
    if (unsigned Reg = State.AllocateReg(X86::ECX)) {
390
8
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
391
8
      return false;
392
8
    }
393
161k
  }
394
161k
395
161k
  if (!State.isVarArg()) {
396
154k
    if (ArgFlags.isInReg()) {
397
277
      if (LocVT == MVT::i32) {
398
253
        static const MCPhysReg RegList1[] = {
399
253
          X86::EAX, X86::EDX, X86::ECX
400
253
        };
401
253
        if (unsigned Reg = State.AllocateReg(RegList1)) {
402
244
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
403
244
          return false;
404
244
        }
405
161k
      }
406
277
    }
407
154k
  }
408
161k
409
161k
  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
410
161k
    return false;
411
0
412
0
  return true;  // CC didn't match.
413
0
}
414
415
416
static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT,
417
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
418
162k
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
419
162k
420
162k
  if (ArgFlags.isByVal()) {
421
301
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
422
301
    return false;
423
301
  }
424
162k
425
162k
  if (!State.isVarArg()) {
426
155k
    if (ArgFlags.isInReg()) {
427
62
      if (LocVT == MVT::f32 ||
428
62
          
LocVT == MVT::f6458
) {
429
8
        if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
430
0
          static const MCPhysReg RegList1[] = {
431
0
            X86::XMM0, X86::XMM1, X86::XMM2
432
0
          };
433
0
          if (unsigned Reg = State.AllocateReg(RegList1)) {
434
0
            State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
435
0
            return false;
436
0
          }
437
162k
        }
438
8
      }
439
62
    }
440
155k
  }
441
162k
442
162k
  if (!State.isVarArg()) {
443
155k
    if (LocVT == MVT::x86mmx) {
444
1.86k
      static const MCPhysReg RegList2[] = {
445
1.86k
        X86::MM0, X86::MM1, X86::MM2
446
1.86k
      };
447
1.86k
      if (unsigned Reg = State.AllocateReg(RegList2)) {
448
1.86k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
449
1.86k
        return false;
450
1.86k
      }
451
160k
    }
452
155k
  }
453
160k
454
160k
  if (LocVT == MVT::i32 ||
455
160k
      
LocVT == MVT::f3221.0k
) {
456
140k
    unsigned Offset3 = State.AllocateStack(4, 4);
457
140k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
458
140k
    return false;
459
140k
  }
460
19.7k
461
19.7k
  if (LocVT == MVT::f64) {
462
936
    unsigned Offset4 = State.AllocateStack(8, 4);
463
936
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
464
936
    return false;
465
936
  }
466
18.8k
467
18.8k
  if (LocVT == MVT::f80) {
468
308
    unsigned Offset5 = State.AllocateStack(
469
308
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 4);
470
308
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
471
308
    return false;
472
308
  }
473
18.5k
474
18.5k
  if (LocVT == MVT::v2i1) {
475
22
    LocVT = MVT::v2i64;
476
22
    if (ArgFlags.isSExt())
477
0
        LocInfo = CCValAssign::SExt;
478
22
    else if (ArgFlags.isZExt())
479
0
        LocInfo = CCValAssign::ZExt;
480
22
    else
481
22
        LocInfo = CCValAssign::AExt;
482
22
  }
483
18.5k
484
18.5k
  if (LocVT == MVT::v4i1) {
485
21
    LocVT = MVT::v4i32;
486
21
    if (ArgFlags.isSExt())
487
0
        LocInfo = CCValAssign::SExt;
488
21
    else if (ArgFlags.isZExt())
489
0
        LocInfo = CCValAssign::ZExt;
490
21
    else
491
21
        LocInfo = CCValAssign::AExt;
492
21
  }
493
18.5k
494
18.5k
  if (LocVT == MVT::v8i1) {
495
17
    LocVT = MVT::v8i16;
496
17
    if (ArgFlags.isSExt())
497
0
        LocInfo = CCValAssign::SExt;
498
17
    else if (ArgFlags.isZExt())
499
0
        LocInfo = CCValAssign::ZExt;
500
17
    else
501
17
        LocInfo = CCValAssign::AExt;
502
17
  }
503
18.5k
504
18.5k
  if (LocVT == MVT::v16i1) {
505
30
    LocVT = MVT::v16i8;
506
30
    if (ArgFlags.isSExt())
507
0
        LocInfo = CCValAssign::SExt;
508
30
    else if (ArgFlags.isZExt())
509
0
        LocInfo = CCValAssign::ZExt;
510
30
    else
511
30
        LocInfo = CCValAssign::AExt;
512
30
  }
513
18.5k
514
18.5k
  if (LocVT == MVT::v32i1) {
515
5
    LocVT = MVT::v32i8;
516
5
    if (ArgFlags.isSExt())
517
0
        LocInfo = CCValAssign::SExt;
518
5
    else if (ArgFlags.isZExt())
519
0
        LocInfo = CCValAssign::ZExt;
520
5
    else
521
5
        LocInfo = CCValAssign::AExt;
522
5
  }
523
18.5k
524
18.5k
  if (LocVT == MVT::v64i1) {
525
1
    LocVT = MVT::v64i8;
526
1
    if (ArgFlags.isSExt())
527
0
        LocInfo = CCValAssign::SExt;
528
1
    else if (ArgFlags.isZExt())
529
0
        LocInfo = CCValAssign::ZExt;
530
1
    else
531
1
        LocInfo = CCValAssign::AExt;
532
1
  }
533
18.5k
534
18.5k
  if (LocVT == MVT::x86mmx) {
535
0
    unsigned Offset6 = State.AllocateStack(8, 4);
536
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
537
0
    return false;
538
0
  }
539
18.5k
540
18.5k
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()) {
541
4.35k
    if (!CC_X86_32_Vector_Darwin(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
542
4.35k
      return false;
543
14.1k
  }
544
14.1k
545
14.1k
  if (!CC_X86_32_Vector_Standard(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
546
14.1k
    return false;
547
6
548
6
  return true;  // CC didn't match.
549
6
}
X86CallLowering.cpp:CC_X86_32_Common(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
418
192
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
419
192
420
192
  if (ArgFlags.isByVal()) {
421
0
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
422
0
    return false;
423
0
  }
424
192
425
192
  if (!State.isVarArg()) {
426
192
    if (ArgFlags.isInReg()) {
427
0
      if (LocVT == MVT::f32 ||
428
0
          LocVT == MVT::f64) {
429
0
        if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
430
0
          static const MCPhysReg RegList1[] = {
431
0
            X86::XMM0, X86::XMM1, X86::XMM2
432
0
          };
433
0
          if (unsigned Reg = State.AllocateReg(RegList1)) {
434
0
            State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
435
0
            return false;
436
0
          }
437
192
        }
438
0
      }
439
0
    }
440
192
  }
441
192
442
192
  if (!State.isVarArg()) {
443
192
    if (LocVT == MVT::x86mmx) {
444
0
      static const MCPhysReg RegList2[] = {
445
0
        X86::MM0, X86::MM1, X86::MM2
446
0
      };
447
0
      if (unsigned Reg = State.AllocateReg(RegList2)) {
448
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
449
0
        return false;
450
0
      }
451
192
    }
452
192
  }
453
192
454
192
  if (LocVT == MVT::i32 ||
455
192
      
LocVT == MVT::f3230
) {
456
166
    unsigned Offset3 = State.AllocateStack(4, 4);
457
166
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
458
166
    return false;
459
166
  }
460
26
461
26
  if (LocVT == MVT::f64) {
462
4
    unsigned Offset4 = State.AllocateStack(8, 4);
463
4
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
464
4
    return false;
465
4
  }
466
22
467
22
  if (LocVT == MVT::f80) {
468
0
    unsigned Offset5 = State.AllocateStack(
469
0
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 4);
470
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
471
0
    return false;
472
0
  }
473
22
474
22
  if (LocVT == MVT::v2i1) {
475
0
    LocVT = MVT::v2i64;
476
0
    if (ArgFlags.isSExt())
477
0
        LocInfo = CCValAssign::SExt;
478
0
    else if (ArgFlags.isZExt())
479
0
        LocInfo = CCValAssign::ZExt;
480
0
    else
481
0
        LocInfo = CCValAssign::AExt;
482
0
  }
483
22
484
22
  if (LocVT == MVT::v4i1) {
485
0
    LocVT = MVT::v4i32;
486
0
    if (ArgFlags.isSExt())
487
0
        LocInfo = CCValAssign::SExt;
488
0
    else if (ArgFlags.isZExt())
489
0
        LocInfo = CCValAssign::ZExt;
490
0
    else
491
0
        LocInfo = CCValAssign::AExt;
492
0
  }
493
22
494
22
  if (LocVT == MVT::v8i1) {
495
0
    LocVT = MVT::v8i16;
496
0
    if (ArgFlags.isSExt())
497
0
        LocInfo = CCValAssign::SExt;
498
0
    else if (ArgFlags.isZExt())
499
0
        LocInfo = CCValAssign::ZExt;
500
0
    else
501
0
        LocInfo = CCValAssign::AExt;
502
0
  }
503
22
504
22
  if (LocVT == MVT::v16i1) {
505
0
    LocVT = MVT::v16i8;
506
0
    if (ArgFlags.isSExt())
507
0
        LocInfo = CCValAssign::SExt;
508
0
    else if (ArgFlags.isZExt())
509
0
        LocInfo = CCValAssign::ZExt;
510
0
    else
511
0
        LocInfo = CCValAssign::AExt;
512
0
  }
513
22
514
22
  if (LocVT == MVT::v32i1) {
515
0
    LocVT = MVT::v32i8;
516
0
    if (ArgFlags.isSExt())
517
0
        LocInfo = CCValAssign::SExt;
518
0
    else if (ArgFlags.isZExt())
519
0
        LocInfo = CCValAssign::ZExt;
520
0
    else
521
0
        LocInfo = CCValAssign::AExt;
522
0
  }
523
22
524
22
  if (LocVT == MVT::v64i1) {
525
0
    LocVT = MVT::v64i8;
526
0
    if (ArgFlags.isSExt())
527
0
        LocInfo = CCValAssign::SExt;
528
0
    else if (ArgFlags.isZExt())
529
0
        LocInfo = CCValAssign::ZExt;
530
0
    else
531
0
        LocInfo = CCValAssign::AExt;
532
0
  }
533
22
534
22
  if (LocVT == MVT::x86mmx) {
535
0
    unsigned Offset6 = State.AllocateStack(8, 4);
536
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
537
0
    return false;
538
0
  }
539
22
540
22
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()) {
541
0
    if (!CC_X86_32_Vector_Darwin(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
542
0
      return false;
543
22
  }
544
22
545
22
  if (!CC_X86_32_Vector_Standard(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
546
22
    return false;
547
0
548
0
  return true;  // CC didn't match.
549
0
}
X86FastISel.cpp:CC_X86_32_Common(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
418
167
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
419
167
420
167
  if (ArgFlags.isByVal()) {
421
4
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
422
4
    return false;
423
4
  }
424
163
425
163
  if (!State.isVarArg()) {
426
153
    if (ArgFlags.isInReg()) {
427
0
      if (LocVT == MVT::f32 ||
428
0
          LocVT == MVT::f64) {
429
0
        if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
430
0
          static const MCPhysReg RegList1[] = {
431
0
            X86::XMM0, X86::XMM1, X86::XMM2
432
0
          };
433
0
          if (unsigned Reg = State.AllocateReg(RegList1)) {
434
0
            State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
435
0
            return false;
436
0
          }
437
163
        }
438
0
      }
439
0
    }
440
153
  }
441
163
442
163
  if (!State.isVarArg()) {
443
153
    if (LocVT == MVT::x86mmx) {
444
1
      static const MCPhysReg RegList2[] = {
445
1
        X86::MM0, X86::MM1, X86::MM2
446
1
      };
447
1
      if (unsigned Reg = State.AllocateReg(RegList2)) {
448
1
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
449
1
        return false;
450
1
      }
451
162
    }
452
153
  }
453
162
454
162
  if (LocVT == MVT::i32 ||
455
162
      
LocVT == MVT::f325
) {
456
157
    unsigned Offset3 = State.AllocateStack(4, 4);
457
157
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
458
157
    return false;
459
157
  }
460
5
461
5
  if (LocVT == MVT::f64) {
462
0
    unsigned Offset4 = State.AllocateStack(8, 4);
463
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
464
0
    return false;
465
0
  }
466
5
467
5
  if (LocVT == MVT::f80) {
468
0
    unsigned Offset5 = State.AllocateStack(
469
0
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 4);
470
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
471
0
    return false;
472
0
  }
473
5
474
5
  if (LocVT == MVT::v2i1) {
475
0
    LocVT = MVT::v2i64;
476
0
    if (ArgFlags.isSExt())
477
0
        LocInfo = CCValAssign::SExt;
478
0
    else if (ArgFlags.isZExt())
479
0
        LocInfo = CCValAssign::ZExt;
480
0
    else
481
0
        LocInfo = CCValAssign::AExt;
482
0
  }
483
5
484
5
  if (LocVT == MVT::v4i1) {
485
0
    LocVT = MVT::v4i32;
486
0
    if (ArgFlags.isSExt())
487
0
        LocInfo = CCValAssign::SExt;
488
0
    else if (ArgFlags.isZExt())
489
0
        LocInfo = CCValAssign::ZExt;
490
0
    else
491
0
        LocInfo = CCValAssign::AExt;
492
0
  }
493
5
494
5
  if (LocVT == MVT::v8i1) {
495
0
    LocVT = MVT::v8i16;
496
0
    if (ArgFlags.isSExt())
497
0
        LocInfo = CCValAssign::SExt;
498
0
    else if (ArgFlags.isZExt())
499
0
        LocInfo = CCValAssign::ZExt;
500
0
    else
501
0
        LocInfo = CCValAssign::AExt;
502
0
  }
503
5
504
5
  if (LocVT == MVT::v16i1) {
505
0
    LocVT = MVT::v16i8;
506
0
    if (ArgFlags.isSExt())
507
0
        LocInfo = CCValAssign::SExt;
508
0
    else if (ArgFlags.isZExt())
509
0
        LocInfo = CCValAssign::ZExt;
510
0
    else
511
0
        LocInfo = CCValAssign::AExt;
512
0
  }
513
5
514
5
  if (LocVT == MVT::v32i1) {
515
0
    LocVT = MVT::v32i8;
516
0
    if (ArgFlags.isSExt())
517
0
        LocInfo = CCValAssign::SExt;
518
0
    else if (ArgFlags.isZExt())
519
0
        LocInfo = CCValAssign::ZExt;
520
0
    else
521
0
        LocInfo = CCValAssign::AExt;
522
0
  }
523
5
524
5
  if (LocVT == MVT::v64i1) {
525
0
    LocVT = MVT::v64i8;
526
0
    if (ArgFlags.isSExt())
527
0
        LocInfo = CCValAssign::SExt;
528
0
    else if (ArgFlags.isZExt())
529
0
        LocInfo = CCValAssign::ZExt;
530
0
    else
531
0
        LocInfo = CCValAssign::AExt;
532
0
  }
533
5
534
5
  if (LocVT == MVT::x86mmx) {
535
0
    unsigned Offset6 = State.AllocateStack(8, 4);
536
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
537
0
    return false;
538
0
  }
539
5
540
5
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()) {
541
5
    if (!CC_X86_32_Vector_Darwin(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
542
5
      return false;
543
0
  }
544
0
545
0
  if (!CC_X86_32_Vector_Standard(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
546
0
    return false;
547
0
548
0
  return true;  // CC didn't match.
549
0
}
X86ISelLowering.cpp:CC_X86_32_Common(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
418
162k
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
419
162k
420
162k
  if (ArgFlags.isByVal()) {
421
297
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
422
297
    return false;
423
297
  }
424
161k
425
161k
  if (!State.isVarArg()) {
426
154k
    if (ArgFlags.isInReg()) {
427
62
      if (LocVT == MVT::f32 ||
428
62
          
LocVT == MVT::f6458
) {
429
8
        if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
430
0
          static const MCPhysReg RegList1[] = {
431
0
            X86::XMM0, X86::XMM1, X86::XMM2
432
0
          };
433
0
          if (unsigned Reg = State.AllocateReg(RegList1)) {
434
0
            State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
435
0
            return false;
436
0
          }
437
161k
        }
438
8
      }
439
62
    }
440
154k
  }
441
161k
442
161k
  if (!State.isVarArg()) {
443
154k
    if (LocVT == MVT::x86mmx) {
444
1.86k
      static const MCPhysReg RegList2[] = {
445
1.86k
        X86::MM0, X86::MM1, X86::MM2
446
1.86k
      };
447
1.86k
      if (unsigned Reg = State.AllocateReg(RegList2)) {
448
1.86k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
449
1.86k
        return false;
450
1.86k
      }
451
159k
    }
452
154k
  }
453
159k
454
159k
  if (LocVT == MVT::i32 ||
455
159k
      
LocVT == MVT::f3221.0k
) {
456
140k
    unsigned Offset3 = State.AllocateStack(4, 4);
457
140k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
458
140k
    return false;
459
140k
  }
460
19.7k
461
19.7k
  if (LocVT == MVT::f64) {
462
932
    unsigned Offset4 = State.AllocateStack(8, 4);
463
932
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
464
932
    return false;
465
932
  }
466
18.8k
467
18.8k
  if (LocVT == MVT::f80) {
468
308
    unsigned Offset5 = State.AllocateStack(
469
308
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 4);
470
308
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
471
308
    return false;
472
308
  }
473
18.5k
474
18.5k
  if (LocVT == MVT::v2i1) {
475
22
    LocVT = MVT::v2i64;
476
22
    if (ArgFlags.isSExt())
477
0
        LocInfo = CCValAssign::SExt;
478
22
    else if (ArgFlags.isZExt())
479
0
        LocInfo = CCValAssign::ZExt;
480
22
    else
481
22
        LocInfo = CCValAssign::AExt;
482
22
  }
483
18.5k
484
18.5k
  if (LocVT == MVT::v4i1) {
485
21
    LocVT = MVT::v4i32;
486
21
    if (ArgFlags.isSExt())
487
0
        LocInfo = CCValAssign::SExt;
488
21
    else if (ArgFlags.isZExt())
489
0
        LocInfo = CCValAssign::ZExt;
490
21
    else
491
21
        LocInfo = CCValAssign::AExt;
492
21
  }
493
18.5k
494
18.5k
  if (LocVT == MVT::v8i1) {
495
17
    LocVT = MVT::v8i16;
496
17
    if (ArgFlags.isSExt())
497
0
        LocInfo = CCValAssign::SExt;
498
17
    else if (ArgFlags.isZExt())
499
0
        LocInfo = CCValAssign::ZExt;
500
17
    else
501
17
        LocInfo = CCValAssign::AExt;
502
17
  }
503
18.5k
504
18.5k
  if (LocVT == MVT::v16i1) {
505
30
    LocVT = MVT::v16i8;
506
30
    if (ArgFlags.isSExt())
507
0
        LocInfo = CCValAssign::SExt;
508
30
    else if (ArgFlags.isZExt())
509
0
        LocInfo = CCValAssign::ZExt;
510
30
    else
511
30
        LocInfo = CCValAssign::AExt;
512
30
  }
513
18.5k
514
18.5k
  if (LocVT == MVT::v32i1) {
515
5
    LocVT = MVT::v32i8;
516
5
    if (ArgFlags.isSExt())
517
0
        LocInfo = CCValAssign::SExt;
518
5
    else if (ArgFlags.isZExt())
519
0
        LocInfo = CCValAssign::ZExt;
520
5
    else
521
5
        LocInfo = CCValAssign::AExt;
522
5
  }
523
18.5k
524
18.5k
  if (LocVT == MVT::v64i1) {
525
1
    LocVT = MVT::v64i8;
526
1
    if (ArgFlags.isSExt())
527
0
        LocInfo = CCValAssign::SExt;
528
1
    else if (ArgFlags.isZExt())
529
0
        LocInfo = CCValAssign::ZExt;
530
1
    else
531
1
        LocInfo = CCValAssign::AExt;
532
1
  }
533
18.5k
534
18.5k
  if (LocVT == MVT::x86mmx) {
535
0
    unsigned Offset6 = State.AllocateStack(8, 4);
536
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
537
0
    return false;
538
0
  }
539
18.5k
540
18.5k
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()) {
541
4.34k
    if (!CC_X86_32_Vector_Darwin(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
542
4.34k
      return false;
543
14.1k
  }
544
14.1k
545
14.1k
  if (!CC_X86_32_Vector_Standard(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
546
14.1k
    return false;
547
6
548
6
  return true;  // CC didn't match.
549
6
}
550
551
552
static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT,
553
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
554
2.95k
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
555
2.95k
556
2.95k
  if (ArgFlags.isByVal()) {
557
133
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
558
133
    return false;
559
133
  }
560
2.82k
561
2.82k
  if (LocVT == MVT::i1 ||
562
2.82k
      LocVT == MVT::i8 ||
563
2.82k
      
LocVT == MVT::i162.63k
||
564
2.82k
      
LocVT == MVT::v1i12.63k
) {
565
184
    LocVT = MVT::i32;
566
184
    if (ArgFlags.isSExt())
567
11
        LocInfo = CCValAssign::SExt;
568
173
    else if (ArgFlags.isZExt())
569
171
        LocInfo = CCValAssign::ZExt;
570
2
    else
571
2
        LocInfo = CCValAssign::AExt;
572
184
  }
573
2.82k
574
2.82k
  if (ArgFlags.isNest()) {
575
0
    if (unsigned Reg = State.AllocateReg(X86::EAX)) {
576
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
577
0
      return false;
578
0
    }
579
2.82k
  }
580
2.82k
581
2.82k
  if (LocVT == MVT::i32) {
582
2.79k
    static const MCPhysReg RegList1[] = {
583
2.79k
      X86::ECX, X86::EDX
584
2.79k
    };
585
2.79k
    if (unsigned Reg = State.AllocateReg(RegList1)) {
586
2.14k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
587
2.14k
      return false;
588
2.14k
    }
589
674
  }
590
674
591
674
  if (!State.isVarArg()) {
592
674
    if (LocVT == MVT::f32 ||
593
674
        
LocVT == MVT::f64670
) {
594
18
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
595
8
        static const MCPhysReg RegList2[] = {
596
8
          X86::XMM0, X86::XMM1, X86::XMM2
597
8
        };
598
8
        if (unsigned Reg = State.AllocateReg(RegList2)) {
599
6
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
600
6
          return false;
601
6
        }
602
668
      }
603
18
    }
604
674
  }
605
668
606
668
  if (LocVT == MVT::f64) {
607
9
    unsigned Offset3 = State.AllocateStack(8, 8);
608
9
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
609
9
    return false;
610
9
  }
611
659
612
659
  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
613
659
    return false;
614
0
615
0
  return true;  // CC didn't match.
616
0
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_32_FastCC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86FastISel.cpp:CC_X86_32_FastCC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
554
4
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
555
4
556
4
  if (ArgFlags.isByVal()) {
557
0
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
558
0
    return false;
559
0
  }
560
4
561
4
  if (LocVT == MVT::i1 ||
562
4
      LocVT == MVT::i8 ||
563
4
      LocVT == MVT::i16 ||
564
4
      LocVT == MVT::v1i1) {
565
0
    LocVT = MVT::i32;
566
0
    if (ArgFlags.isSExt())
567
0
        LocInfo = CCValAssign::SExt;
568
0
    else if (ArgFlags.isZExt())
569
0
        LocInfo = CCValAssign::ZExt;
570
0
    else
571
0
        LocInfo = CCValAssign::AExt;
572
0
  }
573
4
574
4
  if (ArgFlags.isNest()) {
575
0
    if (unsigned Reg = State.AllocateReg(X86::EAX)) {
576
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
577
0
      return false;
578
0
    }
579
4
  }
580
4
581
4
  if (LocVT == MVT::i32) {
582
4
    static const MCPhysReg RegList1[] = {
583
4
      X86::ECX, X86::EDX
584
4
    };
585
4
    if (unsigned Reg = State.AllocateReg(RegList1)) {
586
4
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
587
4
      return false;
588
4
    }
589
0
  }
590
0
591
0
  if (!State.isVarArg()) {
592
0
    if (LocVT == MVT::f32 ||
593
0
        LocVT == MVT::f64) {
594
0
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
595
0
        static const MCPhysReg RegList2[] = {
596
0
          X86::XMM0, X86::XMM1, X86::XMM2
597
0
        };
598
0
        if (unsigned Reg = State.AllocateReg(RegList2)) {
599
0
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
600
0
          return false;
601
0
        }
602
0
      }
603
0
    }
604
0
  }
605
0
606
0
  if (LocVT == MVT::f64) {
607
0
    unsigned Offset3 = State.AllocateStack(8, 8);
608
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
609
0
    return false;
610
0
  }
611
0
612
0
  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
613
0
    return false;
614
0
615
0
  return true;  // CC didn't match.
616
0
}
X86ISelLowering.cpp:CC_X86_32_FastCC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
554
2.95k
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
555
2.95k
556
2.95k
  if (ArgFlags.isByVal()) {
557
133
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
558
133
    return false;
559
133
  }
560
2.81k
561
2.81k
  if (LocVT == MVT::i1 ||
562
2.81k
      LocVT == MVT::i8 ||
563
2.81k
      
LocVT == MVT::i162.63k
||
564
2.81k
      
LocVT == MVT::v1i12.63k
) {
565
184
    LocVT = MVT::i32;
566
184
    if (ArgFlags.isSExt())
567
11
        LocInfo = CCValAssign::SExt;
568
173
    else if (ArgFlags.isZExt())
569
171
        LocInfo = CCValAssign::ZExt;
570
2
    else
571
2
        LocInfo = CCValAssign::AExt;
572
184
  }
573
2.81k
574
2.81k
  if (ArgFlags.isNest()) {
575
0
    if (unsigned Reg = State.AllocateReg(X86::EAX)) {
576
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
577
0
      return false;
578
0
    }
579
2.81k
  }
580
2.81k
581
2.81k
  if (LocVT == MVT::i32) {
582
2.79k
    static const MCPhysReg RegList1[] = {
583
2.79k
      X86::ECX, X86::EDX
584
2.79k
    };
585
2.79k
    if (unsigned Reg = State.AllocateReg(RegList1)) {
586
2.14k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
587
2.14k
      return false;
588
2.14k
    }
589
674
  }
590
674
591
674
  if (!State.isVarArg()) {
592
674
    if (LocVT == MVT::f32 ||
593
674
        
LocVT == MVT::f64670
) {
594
18
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
595
8
        static const MCPhysReg RegList2[] = {
596
8
          X86::XMM0, X86::XMM1, X86::XMM2
597
8
        };
598
8
        if (unsigned Reg = State.AllocateReg(RegList2)) {
599
6
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
600
6
          return false;
601
6
        }
602
668
      }
603
18
    }
604
674
  }
605
668
606
668
  if (LocVT == MVT::f64) {
607
9
    unsigned Offset3 = State.AllocateStack(8, 8);
608
9
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
609
9
    return false;
610
9
  }
611
659
612
659
  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
613
659
    return false;
614
0
615
0
  return true;  // CC didn't match.
616
0
}
617
618
619
static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT,
620
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
621
262
                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
622
262
623
262
  if (LocVT == MVT::i1) {
624
0
    LocVT = MVT::i8;
625
0
    if (ArgFlags.isSExt())
626
0
        LocInfo = CCValAssign::SExt;
627
0
    else if (ArgFlags.isZExt())
628
0
        LocInfo = CCValAssign::ZExt;
629
0
    else
630
0
        LocInfo = CCValAssign::AExt;
631
0
  }
632
262
633
262
  if (ArgFlags.isNest()) {
634
0
    if (unsigned Reg = State.AllocateReg(X86::EAX)) {
635
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
636
0
      return false;
637
0
    }
638
262
  }
639
262
640
262
  if (ArgFlags.isInReg()) {
641
195
    if (LocVT == MVT::i8) {
642
4
      static const MCPhysReg RegList1[] = {
643
4
        X86::CL, X86::DL
644
4
      };
645
4
      if (unsigned Reg = State.AllocateReg(RegList1)) {
646
4
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
647
4
        return false;
648
4
      }
649
258
    }
650
195
  }
651
258
652
258
  if (ArgFlags.isInReg()) {
653
191
    if (LocVT == MVT::i16) {
654
0
      static const MCPhysReg RegList2[] = {
655
0
        X86::CX, X86::DX
656
0
      };
657
0
      if (unsigned Reg = State.AllocateReg(RegList2)) {
658
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
659
0
        return false;
660
0
      }
661
258
    }
662
191
  }
663
258
664
258
  if (ArgFlags.isInReg()) {
665
191
    if (LocVT == MVT::i32) {
666
176
      static const MCPhysReg RegList3[] = {
667
176
        X86::ECX, X86::EDX
668
176
      };
669
176
      if (unsigned Reg = State.AllocateReg(RegList3)) {
670
170
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
671
170
        return false;
672
170
      }
673
88
    }
674
191
  }
675
88
676
88
  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
677
82
    return false;
678
6
679
6
  return true;  // CC didn't match.
680
6
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_32_FastCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86FastISel.cpp:CC_X86_32_FastCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:CC_X86_32_FastCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
621
262
                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
622
262
623
262
  if (LocVT == MVT::i1) {
624
0
    LocVT = MVT::i8;
625
0
    if (ArgFlags.isSExt())
626
0
        LocInfo = CCValAssign::SExt;
627
0
    else if (ArgFlags.isZExt())
628
0
        LocInfo = CCValAssign::ZExt;
629
0
    else
630
0
        LocInfo = CCValAssign::AExt;
631
0
  }
632
262
633
262
  if (ArgFlags.isNest()) {
634
0
    if (unsigned Reg = State.AllocateReg(X86::EAX)) {
635
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
636
0
      return false;
637
0
    }
638
262
  }
639
262
640
262
  if (ArgFlags.isInReg()) {
641
195
    if (LocVT == MVT::i8) {
642
4
      static const MCPhysReg RegList1[] = {
643
4
        X86::CL, X86::DL
644
4
      };
645
4
      if (unsigned Reg = State.AllocateReg(RegList1)) {
646
4
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
647
4
        return false;
648
4
      }
649
258
    }
650
195
  }
651
258
652
258
  if (ArgFlags.isInReg()) {
653
191
    if (LocVT == MVT::i16) {
654
0
      static const MCPhysReg RegList2[] = {
655
0
        X86::CX, X86::DX
656
0
      };
657
0
      if (unsigned Reg = State.AllocateReg(RegList2)) {
658
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
659
0
        return false;
660
0
      }
661
258
    }
662
191
  }
663
258
664
258
  if (ArgFlags.isInReg()) {
665
191
    if (LocVT == MVT::i32) {
666
176
      static const MCPhysReg RegList3[] = {
667
176
        X86::ECX, X86::EDX
668
176
      };
669
176
      if (unsigned Reg = State.AllocateReg(RegList3)) {
670
170
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
671
170
        return false;
672
170
      }
673
88
    }
674
191
  }
675
88
676
88
  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
677
82
    return false;
678
6
679
6
  return true;  // CC didn't match.
680
6
}
681
682
683
static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT,
684
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
685
20
                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
686
20
687
20
  if (LocVT == MVT::i8 ||
688
20
      LocVT == MVT::i16) {
689
0
    LocVT = MVT::i32;
690
0
    if (ArgFlags.isSExt())
691
0
        LocInfo = CCValAssign::SExt;
692
0
    else if (ArgFlags.isZExt())
693
0
        LocInfo = CCValAssign::ZExt;
694
0
    else
695
0
        LocInfo = CCValAssign::AExt;
696
0
  }
697
20
698
20
  if (LocVT == MVT::i32) {
699
20
    static const MCPhysReg RegList1[] = {
700
20
      X86::EBX, X86::EBP, X86::EDI, X86::ESI
701
20
    };
702
20
    if (unsigned Reg = State.AllocateReg(RegList1)) {
703
20
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
704
20
      return false;
705
20
    }
706
0
  }
707
0
708
0
  return true;  // CC didn't match.
709
0
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_32_GHC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86FastISel.cpp:CC_X86_32_GHC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:CC_X86_32_GHC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
685
20
                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
686
20
687
20
  if (LocVT == MVT::i8 ||
688
20
      LocVT == MVT::i16) {
689
0
    LocVT = MVT::i32;
690
0
    if (ArgFlags.isSExt())
691
0
        LocInfo = CCValAssign::SExt;
692
0
    else if (ArgFlags.isZExt())
693
0
        LocInfo = CCValAssign::ZExt;
694
0
    else
695
0
        LocInfo = CCValAssign::AExt;
696
0
  }
697
20
698
20
  if (LocVT == MVT::i32) {
699
20
    static const MCPhysReg RegList1[] = {
700
20
      X86::EBX, X86::EBP, X86::EDI, X86::ESI
701
20
    };
702
20
    if (unsigned Reg = State.AllocateReg(RegList1)) {
703
20
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
704
20
      return false;
705
20
    }
706
0
  }
707
0
708
0
  return true;  // CC didn't match.
709
0
}
710
711
712
static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
713
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
714
42
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
715
42
716
42
  if (LocVT == MVT::i8 ||
717
42
      LocVT == MVT::i16) {
718
0
    LocVT = MVT::i32;
719
0
    if (ArgFlags.isSExt())
720
0
        LocInfo = CCValAssign::SExt;
721
0
    else if (ArgFlags.isZExt())
722
0
        LocInfo = CCValAssign::ZExt;
723
0
    else
724
0
        LocInfo = CCValAssign::AExt;
725
0
  }
726
42
727
42
  if (LocVT == MVT::i32) {
728
42
    static const MCPhysReg RegList1[] = {
729
42
      X86::ESI, X86::EBP, X86::EAX, X86::EDX, X86::ECX
730
42
    };
731
42
    if (unsigned Reg = State.AllocateReg(RegList1)) {
732
41
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
733
41
      return false;
734
41
    }
735
1
  }
736
1
737
1
  if (LocVT == MVT::i32 ||
738
1
      
LocVT == MVT::f320
) {
739
1
    unsigned Offset2 = State.AllocateStack(4, 4);
740
1
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
741
1
    return false;
742
1
  }
743
0
744
0
  return true;  // CC didn't match.
745
0
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_32_HiPE(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86FastISel.cpp:CC_X86_32_HiPE(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:CC_X86_32_HiPE(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
714
42
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
715
42
716
42
  if (LocVT == MVT::i8 ||
717
42
      LocVT == MVT::i16) {
718
0
    LocVT = MVT::i32;
719
0
    if (ArgFlags.isSExt())
720
0
        LocInfo = CCValAssign::SExt;
721
0
    else if (ArgFlags.isZExt())
722
0
        LocInfo = CCValAssign::ZExt;
723
0
    else
724
0
        LocInfo = CCValAssign::AExt;
725
0
  }
726
42
727
42
  if (LocVT == MVT::i32) {
728
42
    static const MCPhysReg RegList1[] = {
729
42
      X86::ESI, X86::EBP, X86::EAX, X86::EDX, X86::ECX
730
42
    };
731
42
    if (unsigned Reg = State.AllocateReg(RegList1)) {
732
41
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
733
41
      return false;
734
41
    }
735
1
  }
736
1
737
1
  if (LocVT == MVT::i32 ||
738
1
      
LocVT == MVT::f320
) {
739
1
    unsigned Offset2 = State.AllocateStack(4, 4);
740
1
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
741
1
    return false;
742
1
  }
743
0
744
0
  return true;  // CC didn't match.
745
0
}
746
747
748
static bool CC_X86_32_Intr(unsigned ValNo, MVT ValVT,
749
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
750
16
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
751
16
752
16
  unsigned Offset1 = State.AllocateStack(4, 4);
753
16
  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
754
16
  return false;
755
16
756
16
  
return true0
; // CC didn't match.
757
16
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_32_Intr(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86FastISel.cpp:CC_X86_32_Intr(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:CC_X86_32_Intr(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
750
16
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
751
16
752
16
  unsigned Offset1 = State.AllocateStack(4, 4);
753
16
  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
754
16
  return false;
755
16
756
16
  
return true0
; // CC didn't match.
757
16
}
758
759
760
static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT,
761
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
762
126
                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
763
126
764
126
  if (ArgFlags.isByVal()) {
765
1
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
766
1
    return false;
767
1
  }
768
125
769
125
  if (LocVT == MVT::i1 ||
770
125
      LocVT == MVT::i8 ||
771
125
      
LocVT == MVT::i16113
||
772
125
      
LocVT == MVT::v1i1106
) {
773
19
    LocVT = MVT::i32;
774
19
    if (ArgFlags.isSExt())
775
0
        LocInfo = CCValAssign::SExt;
776
19
    else if (ArgFlags.isZExt())
777
3
        LocInfo = CCValAssign::ZExt;
778
16
    else
779
16
        LocInfo = CCValAssign::AExt;
780
19
  }
781
125
782
125
  if (!State.isVarArg()) {
783
124
    if (LocVT == MVT::i32) {
784
123
      if (CC_X86_32_MCUInReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
785
120
            return false;
786
5
    }
787
124
  }
788
5
789
5
  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
790
5
    return false;
791
0
792
0
  return true;  // CC didn't match.
793
0
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_32_MCU(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86FastISel.cpp:CC_X86_32_MCU(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:CC_X86_32_MCU(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
762
126
                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
763
126
764
126
  if (ArgFlags.isByVal()) {
765
1
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
766
1
    return false;
767
1
  }
768
125
769
125
  if (LocVT == MVT::i1 ||
770
125
      LocVT == MVT::i8 ||
771
125
      
LocVT == MVT::i16113
||
772
125
      
LocVT == MVT::v1i1106
) {
773
19
    LocVT = MVT::i32;
774
19
    if (ArgFlags.isSExt())
775
0
        LocInfo = CCValAssign::SExt;
776
19
    else if (ArgFlags.isZExt())
777
3
        LocInfo = CCValAssign::ZExt;
778
16
    else
779
16
        LocInfo = CCValAssign::AExt;
780
19
  }
781
125
782
125
  if (!State.isVarArg()) {
783
124
    if (LocVT == MVT::i32) {
784
123
      if (CC_X86_32_MCUInReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
785
120
            return false;
786
5
    }
787
124
  }
788
5
789
5
  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
790
5
    return false;
791
0
792
0
  return true;  // CC didn't match.
793
0
}
794
795
796
static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
797
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
798
200
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
799
200
800
200
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
801
0
    if (ArgFlags.isByVal()) {
802
0
      State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
803
0
      return false;
804
0
    }
805
200
  }
806
200
807
200
  if (ArgFlags.isByVal()) {
808
0
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
809
0
    return false;
810
0
  }
811
200
812
200
  if (LocVT == MVT::i1 ||
813
200
      LocVT == MVT::i8 ||
814
200
      
LocVT == MVT::i16189
||
815
200
      
LocVT == MVT::v1i1185
) {
816
15
    LocVT = MVT::i32;
817
15
    if (ArgFlags.isSExt())
818
2
        LocInfo = CCValAssign::SExt;
819
13
    else if (ArgFlags.isZExt())
820
0
        LocInfo = CCValAssign::ZExt;
821
13
    else
822
13
        LocInfo = CCValAssign::AExt;
823
15
  }
824
200
825
200
  if (LocVT == MVT::v8i1 ||
826
200
      
LocVT == MVT::v16i1194
||
827
200
      
LocVT == MVT::v32i1188
) {
828
18
    LocVT = MVT::i32;
829
18
    if (ArgFlags.isSExt())
830
0
        LocInfo = CCValAssign::SExt;
831
18
    else if (ArgFlags.isZExt())
832
0
        LocInfo = CCValAssign::ZExt;
833
18
    else
834
18
        LocInfo = CCValAssign::AExt;
835
18
  }
836
200
837
200
  if (LocVT == MVT::i32) {
838
86
    static const MCPhysReg RegList1[] = {
839
86
      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI
840
86
    };
841
86
    if (unsigned Reg = State.AllocateReg(RegList1)) {
842
71
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
843
71
      return false;
844
71
    }
845
129
  }
846
129
847
129
  if (LocVT == MVT::i64) {
848
0
    if (unsigned Reg = State.AllocateReg(X86::RAX)) {
849
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
850
0
      return false;
851
0
    }
852
129
  }
853
129
854
129
  if (LocVT == MVT::v64i1) {
855
26
    LocVT = MVT::i64;
856
26
    if (ArgFlags.isSExt())
857
0
        LocInfo = CCValAssign::SExt;
858
26
    else if (ArgFlags.isZExt())
859
0
        LocInfo = CCValAssign::ZExt;
860
26
    else
861
26
        LocInfo = CCValAssign::AExt;
862
26
  }
863
129
864
129
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
865
0
    if (LocVT == MVT::i64) {
866
0
      if (unsigned Reg = State.AllocateReg(X86::RAX)) {
867
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
868
0
        return false;
869
0
      }
870
129
    }
871
0
  }
872
129
873
129
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
874
129
    if (LocVT == MVT::i64) {
875
26
      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
876
4
            return false;
877
125
    }
878
129
  }
879
125
880
125
  if (LocVT == MVT::f32 ||
881
125
      
LocVT == MVT::f64120
||
882
125
      
LocVT == MVT::f128115
) {
883
10
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
884
10
      static const MCPhysReg RegList2[] = {
885
10
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
886
10
      };
887
10
      if (unsigned Reg = State.AllocateReg(RegList2)) {
888
10
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
889
10
        return false;
890
10
      }
891
115
    }
892
10
  }
893
115
894
115
  if (LocVT == MVT::f80) {
895
3
    if (unsigned Reg = State.AllocateReg(X86::FP0)) {
896
3
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
897
3
      return false;
898
3
    }
899
112
  }
900
112
901
112
  if (LocVT == MVT::v16i8 ||
902
112
      LocVT == MVT::v8i16 ||
903
112
      LocVT == MVT::v4i32 ||
904
112
      
LocVT == MVT::v2i64107
||
905
112
      
LocVT == MVT::v4f32107
||
906
112
      
LocVT == MVT::v2f6471
) {
907
41
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
908
41
      static const MCPhysReg RegList3[] = {
909
41
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
910
41
      };
911
41
      if (unsigned Reg = State.AllocateReg(RegList3)) {
912
21
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
913
21
        return false;
914
21
      }
915
91
    }
916
41
  }
917
91
918
91
  if (LocVT == MVT::v32i8 ||
919
91
      LocVT == MVT::v16i16 ||
920
91
      LocVT == MVT::v8i32 ||
921
91
      
LocVT == MVT::v4i6486
||
922
91
      
LocVT == MVT::v8f3286
||
923
91
      
LocVT == MVT::v4f6486
) {
924
5
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
925
5
      static const MCPhysReg RegList4[] = {
926
5
        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
927
5
      };
928
5
      if (unsigned Reg = State.AllocateReg(RegList4)) {
929
5
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
930
5
        return false;
931
5
      }
932
86
    }
933
5
  }
934
86
935
86
  if (LocVT == MVT::v64i8 ||
936
86
      LocVT == MVT::v32i16 ||
937
86
      LocVT == MVT::v16i32 ||
938
86
      
LocVT == MVT::v8i6481
||
939
86
      
LocVT == MVT::v16f3281
||
940
86
      
LocVT == MVT::v8f6457
) {
941
29
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
942
29
      static const MCPhysReg RegList5[] = {
943
29
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
944
29
      };
945
29
      if (unsigned Reg = State.AllocateReg(RegList5)) {
946
19
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
947
19
        return false;
948
19
      }
949
67
    }
950
29
  }
951
67
952
67
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
953
0
    if (LocVT == MVT::i32 ||
954
0
        LocVT == MVT::i64 ||
955
0
        LocVT == MVT::f32 ||
956
0
        LocVT == MVT::f64) {
957
0
      unsigned Offset6 = State.AllocateStack(8, 8);
958
0
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
959
0
      return false;
960
0
    }
961
67
  }
962
67
963
67
  if (LocVT == MVT::i32 ||
964
67
      
LocVT == MVT::f3252
) {
965
15
    unsigned Offset7 = State.AllocateStack(4, 4);
966
15
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
967
15
    return false;
968
15
  }
969
52
970
52
  if (LocVT == MVT::i64 ||
971
52
      
LocVT == MVT::f6430
) {
972
22
    unsigned Offset8 = State.AllocateStack(8, 4);
973
22
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
974
22
    return false;
975
22
  }
976
30
977
30
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
978
0
    if (LocVT == MVT::x86mmx) {
979
0
      unsigned Offset9 = State.AllocateStack(8, 8);
980
0
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
981
0
      return false;
982
0
    }
983
30
  }
984
30
985
30
  if (LocVT == MVT::x86mmx) {
986
0
    unsigned Offset10 = State.AllocateStack(8, 4);
987
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
988
0
    return false;
989
0
  }
990
30
991
30
  if (LocVT == MVT::f80 ||
992
30
      LocVT == MVT::f128) {
993
0
    unsigned Offset11 = State.AllocateStack(
994
0
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 
995
0
      State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
996
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo));
997
0
    return false;
998
0
  }
999
30
1000
30
  if (LocVT == MVT::v16i8 ||
1001
30
      LocVT == MVT::v8i16 ||
1002
30
      LocVT == MVT::v4i32 ||
1003
30
      LocVT == MVT::v2i64 ||
1004
30
      LocVT == MVT::v4f32 ||
1005
30
      
LocVT == MVT::v2f6410
) {
1006
20
    unsigned Offset12 = State.AllocateStack(16, 16);
1007
20
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo));
1008
20
    return false;
1009
20
  }
1010
10
1011
10
  if (LocVT == MVT::v32i8 ||
1012
10
      LocVT == MVT::v16i16 ||
1013
10
      LocVT == MVT::v8i32 ||
1014
10
      LocVT == MVT::v4i64 ||
1015
10
      LocVT == MVT::v8f32 ||
1016
10
      LocVT == MVT::v4f64) {
1017
0
    unsigned Offset13 = State.AllocateStack(32, 32);
1018
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo));
1019
0
    return false;
1020
0
  }
1021
10
1022
10
  if (LocVT == MVT::v16i32 ||
1023
10
      LocVT == MVT::v8i64 ||
1024
10
      LocVT == MVT::v16f32 ||
1025
10
      
LocVT == MVT::v8f640
) {
1026
10
    unsigned Offset14 = State.AllocateStack(64, 64);
1027
10
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo));
1028
10
    return false;
1029
10
  }
1030
0
1031
0
  return true;  // CC didn't match.
1032
0
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_32_RegCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86FastISel.cpp:CC_X86_32_RegCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:CC_X86_32_RegCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
798
200
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
799
200
800
200
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
801
0
    if (ArgFlags.isByVal()) {
802
0
      State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
803
0
      return false;
804
0
    }
805
200
  }
806
200
807
200
  if (ArgFlags.isByVal()) {
808
0
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
809
0
    return false;
810
0
  }
811
200
812
200
  if (LocVT == MVT::i1 ||
813
200
      LocVT == MVT::i8 ||
814
200
      
LocVT == MVT::i16189
||
815
200
      
LocVT == MVT::v1i1185
) {
816
15
    LocVT = MVT::i32;
817
15
    if (ArgFlags.isSExt())
818
2
        LocInfo = CCValAssign::SExt;
819
13
    else if (ArgFlags.isZExt())
820
0
        LocInfo = CCValAssign::ZExt;
821
13
    else
822
13
        LocInfo = CCValAssign::AExt;
823
15
  }
824
200
825
200
  if (LocVT == MVT::v8i1 ||
826
200
      
LocVT == MVT::v16i1194
||
827
200
      
LocVT == MVT::v32i1188
) {
828
18
    LocVT = MVT::i32;
829
18
    if (ArgFlags.isSExt())
830
0
        LocInfo = CCValAssign::SExt;
831
18
    else if (ArgFlags.isZExt())
832
0
        LocInfo = CCValAssign::ZExt;
833
18
    else
834
18
        LocInfo = CCValAssign::AExt;
835
18
  }
836
200
837
200
  if (LocVT == MVT::i32) {
838
86
    static const MCPhysReg RegList1[] = {
839
86
      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI
840
86
    };
841
86
    if (unsigned Reg = State.AllocateReg(RegList1)) {
842
71
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
843
71
      return false;
844
71
    }
845
129
  }
846
129
847
129
  if (LocVT == MVT::i64) {
848
0
    if (unsigned Reg = State.AllocateReg(X86::RAX)) {
849
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
850
0
      return false;
851
0
    }
852
129
  }
853
129
854
129
  if (LocVT == MVT::v64i1) {
855
26
    LocVT = MVT::i64;
856
26
    if (ArgFlags.isSExt())
857
0
        LocInfo = CCValAssign::SExt;
858
26
    else if (ArgFlags.isZExt())
859
0
        LocInfo = CCValAssign::ZExt;
860
26
    else
861
26
        LocInfo = CCValAssign::AExt;
862
26
  }
863
129
864
129
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
865
0
    if (LocVT == MVT::i64) {
866
0
      if (unsigned Reg = State.AllocateReg(X86::RAX)) {
867
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
868
0
        return false;
869
0
      }
870
129
    }
871
0
  }
872
129
873
129
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
874
129
    if (LocVT == MVT::i64) {
875
26
      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
876
4
            return false;
877
125
    }
878
129
  }
879
125
880
125
  if (LocVT == MVT::f32 ||
881
125
      
LocVT == MVT::f64120
||
882
125
      
LocVT == MVT::f128115
) {
883
10
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
884
10
      static const MCPhysReg RegList2[] = {
885
10
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
886
10
      };
887
10
      if (unsigned Reg = State.AllocateReg(RegList2)) {
888
10
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
889
10
        return false;
890
10
      }
891
115
    }
892
10
  }
893
115
894
115
  if (LocVT == MVT::f80) {
895
3
    if (unsigned Reg = State.AllocateReg(X86::FP0)) {
896
3
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
897
3
      return false;
898
3
    }
899
112
  }
900
112
901
112
  if (LocVT == MVT::v16i8 ||
902
112
      LocVT == MVT::v8i16 ||
903
112
      LocVT == MVT::v4i32 ||
904
112
      
LocVT == MVT::v2i64107
||
905
112
      
LocVT == MVT::v4f32107
||
906
112
      
LocVT == MVT::v2f6471
) {
907
41
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
908
41
      static const MCPhysReg RegList3[] = {
909
41
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
910
41
      };
911
41
      if (unsigned Reg = State.AllocateReg(RegList3)) {
912
21
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
913
21
        return false;
914
21
      }
915
91
    }
916
41
  }
917
91
918
91
  if (LocVT == MVT::v32i8 ||
919
91
      LocVT == MVT::v16i16 ||
920
91
      LocVT == MVT::v8i32 ||
921
91
      
LocVT == MVT::v4i6486
||
922
91
      
LocVT == MVT::v8f3286
||
923
91
      
LocVT == MVT::v4f6486
) {
924
5
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
925
5
      static const MCPhysReg RegList4[] = {
926
5
        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
927
5
      };
928
5
      if (unsigned Reg = State.AllocateReg(RegList4)) {
929
5
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
930
5
        return false;
931
5
      }
932
86
    }
933
5
  }
934
86
935
86
  if (LocVT == MVT::v64i8 ||
936
86
      LocVT == MVT::v32i16 ||
937
86
      LocVT == MVT::v16i32 ||
938
86
      
LocVT == MVT::v8i6481
||
939
86
      
LocVT == MVT::v16f3281
||
940
86
      
LocVT == MVT::v8f6457
) {
941
29
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
942
29
      static const MCPhysReg RegList5[] = {
943
29
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
944
29
      };
945
29
      if (unsigned Reg = State.AllocateReg(RegList5)) {
946
19
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
947
19
        return false;
948
19
      }
949
67
    }
950
29
  }
951
67
952
67
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
953
0
    if (LocVT == MVT::i32 ||
954
0
        LocVT == MVT::i64 ||
955
0
        LocVT == MVT::f32 ||
956
0
        LocVT == MVT::f64) {
957
0
      unsigned Offset6 = State.AllocateStack(8, 8);
958
0
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
959
0
      return false;
960
0
    }
961
67
  }
962
67
963
67
  if (LocVT == MVT::i32 ||
964
67
      
LocVT == MVT::f3252
) {
965
15
    unsigned Offset7 = State.AllocateStack(4, 4);
966
15
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
967
15
    return false;
968
15
  }
969
52
970
52
  if (LocVT == MVT::i64 ||
971
52
      
LocVT == MVT::f6430
) {
972
22
    unsigned Offset8 = State.AllocateStack(8, 4);
973
22
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
974
22
    return false;
975
22
  }
976
30
977
30
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
978
0
    if (LocVT == MVT::x86mmx) {
979
0
      unsigned Offset9 = State.AllocateStack(8, 8);
980
0
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
981
0
      return false;
982
0
    }
983
30
  }
984
30
985
30
  if (LocVT == MVT::x86mmx) {
986
0
    unsigned Offset10 = State.AllocateStack(8, 4);
987
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
988
0
    return false;
989
0
  }
990
30
991
30
  if (LocVT == MVT::f80 ||
992
30
      LocVT == MVT::f128) {
993
0
    unsigned Offset11 = State.AllocateStack(
994
0
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 
995
0
      State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
996
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo));
997
0
    return false;
998
0
  }
999
30
1000
30
  if (LocVT == MVT::v16i8 ||
1001
30
      LocVT == MVT::v8i16 ||
1002
30
      LocVT == MVT::v4i32 ||
1003
30
      LocVT == MVT::v2i64 ||
1004
30
      LocVT == MVT::v4f32 ||
1005
30
      
LocVT == MVT::v2f6410
) {
1006
20
    unsigned Offset12 = State.AllocateStack(16, 16);
1007
20
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo));
1008
20
    return false;
1009
20
  }
1010
10
1011
10
  if (LocVT == MVT::v32i8 ||
1012
10
      LocVT == MVT::v16i16 ||
1013
10
      LocVT == MVT::v8i32 ||
1014
10
      LocVT == MVT::v4i64 ||
1015
10
      LocVT == MVT::v8f32 ||
1016
10
      LocVT == MVT::v4f64) {
1017
0
    unsigned Offset13 = State.AllocateStack(32, 32);
1018
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo));
1019
0
    return false;
1020
0
  }
1021
10
1022
10
  if (LocVT == MVT::v16i32 ||
1023
10
      LocVT == MVT::v8i64 ||
1024
10
      LocVT == MVT::v16f32 ||
1025
10
      
LocVT == MVT::v8f640
) {
1026
10
    unsigned Offset14 = State.AllocateStack(64, 64);
1027
10
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo));
1028
10
    return false;
1029
10
  }
1030
0
1031
0
  return true;  // CC didn't match.
1032
0
}
1033
1034
1035
static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT,
1036
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
1037
448
                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
1038
448
1039
448
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetCygMing()) {
1040
40
    if (!CC_X86_32_ThisCall_Mingw(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1041
40
      return false;
1042
408
  }
1043
408
1044
408
  if (!CC_X86_32_ThisCall_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1045
408
    return false;
1046
0
1047
0
  return true;  // CC didn't match.
1048
0
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_32_ThisCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86FastISel.cpp:CC_X86_32_ThisCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1037
60
                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
1038
60
1039
60
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetCygMing()) {
1040
12
    if (!CC_X86_32_ThisCall_Mingw(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1041
12
      return false;
1042
48
  }
1043
48
1044
48
  if (!CC_X86_32_ThisCall_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1045
48
    return false;
1046
0
1047
0
  return true;  // CC didn't match.
1048
0
}
X86ISelLowering.cpp:CC_X86_32_ThisCall(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1037
388
                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
1038
388
1039
388
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetCygMing()) {
1040
28
    if (!CC_X86_32_ThisCall_Mingw(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1041
28
      return false;
1042
360
  }
1043
360
1044
360
  if (!CC_X86_32_ThisCall_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1045
360
    return false;
1046
0
1047
0
  return true;  // CC didn't match.
1048
0
}
1049
1050
1051
static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT,
1052
                                      MVT LocVT, CCValAssign::LocInfo LocInfo,
1053
424
                                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1054
424
1055
424
  if (LocVT == MVT::i32) {
1056
414
    if (unsigned Reg = State.AllocateReg(X86::ECX)) {
1057
232
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1058
232
      return false;
1059
232
    }
1060
192
  }
1061
192
1062
192
  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1063
192
    return false;
1064
0
1065
0
  return true;  // CC didn't match.
1066
0
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_32_ThisCall_Common(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86FastISel.cpp:CC_X86_32_ThisCall_Common(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1053
54
                                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1054
54
1055
54
  if (LocVT == MVT::i32) {
1056
54
    if (unsigned Reg = State.AllocateReg(X86::ECX)) {
1057
35
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1058
35
      return false;
1059
35
    }
1060
19
  }
1061
19
1062
19
  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1063
19
    return false;
1064
0
1065
0
  return true;  // CC didn't match.
1066
0
}
X86ISelLowering.cpp:CC_X86_32_ThisCall_Common(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1053
370
                                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1054
370
1055
370
  if (LocVT == MVT::i32) {
1056
360
    if (unsigned Reg = State.AllocateReg(X86::ECX)) {
1057
197
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1058
197
      return false;
1059
197
    }
1060
173
  }
1061
173
1062
173
  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1063
173
    return false;
1064
0
1065
0
  return true;  // CC didn't match.
1066
0
}
1067
1068
1069
static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT,
1070
                                     MVT LocVT, CCValAssign::LocInfo LocInfo,
1071
40
                                     ISD::ArgFlagsTy ArgFlags, CCState &State) {
1072
40
1073
40
  if (LocVT == MVT::i1 ||
1074
40
      LocVT == MVT::i8 ||
1075
40
      LocVT == MVT::i16 ||
1076
40
      LocVT == MVT::v1i1) {
1077
0
    LocVT = MVT::i32;
1078
0
    if (ArgFlags.isSExt())
1079
0
        LocInfo = CCValAssign::SExt;
1080
0
    else if (ArgFlags.isZExt())
1081
0
        LocInfo = CCValAssign::ZExt;
1082
0
    else
1083
0
        LocInfo = CCValAssign::AExt;
1084
0
  }
1085
40
1086
40
  if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1087
40
    return false;
1088
0
1089
0
  return true;  // CC didn't match.
1090
0
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_32_ThisCall_Mingw(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86FastISel.cpp:CC_X86_32_ThisCall_Mingw(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1071
12
                                     ISD::ArgFlagsTy ArgFlags, CCState &State) {
1072
12
1073
12
  if (LocVT == MVT::i1 ||
1074
12
      LocVT == MVT::i8 ||
1075
12
      LocVT == MVT::i16 ||
1076
12
      LocVT == MVT::v1i1) {
1077
0
    LocVT = MVT::i32;
1078
0
    if (ArgFlags.isSExt())
1079
0
        LocInfo = CCValAssign::SExt;
1080
0
    else if (ArgFlags.isZExt())
1081
0
        LocInfo = CCValAssign::ZExt;
1082
0
    else
1083
0
        LocInfo = CCValAssign::AExt;
1084
0
  }
1085
12
1086
12
  if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1087
12
    return false;
1088
0
1089
0
  return true;  // CC didn't match.
1090
0
}
X86ISelLowering.cpp:CC_X86_32_ThisCall_Mingw(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1071
28
                                     ISD::ArgFlagsTy ArgFlags, CCState &State) {
1072
28
1073
28
  if (LocVT == MVT::i1 ||
1074
28
      LocVT == MVT::i8 ||
1075
28
      LocVT == MVT::i16 ||
1076
28
      LocVT == MVT::v1i1) {
1077
0
    LocVT = MVT::i32;
1078
0
    if (ArgFlags.isSExt())
1079
0
        LocInfo = CCValAssign::SExt;
1080
0
    else if (ArgFlags.isZExt())
1081
0
        LocInfo = CCValAssign::ZExt;
1082
0
    else
1083
0
        LocInfo = CCValAssign::AExt;
1084
0
  }
1085
28
1086
28
  if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1087
28
    return false;
1088
0
1089
0
  return true;  // CC didn't match.
1090
0
}
1091
1092
1093
static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT,
1094
                                   MVT LocVT, CCValAssign::LocInfo LocInfo,
1095
408
                                   ISD::ArgFlagsTy ArgFlags, CCState &State) {
1096
408
1097
408
  if (LocVT == MVT::i1 ||
1098
408
      LocVT == MVT::i8 ||
1099
408
      
LocVT == MVT::i16407
||
1100
408
      
LocVT == MVT::v1i1407
) {
1101
1
    LocVT = MVT::i32;
1102
1
    if (ArgFlags.isSExt())
1103
0
        LocInfo = CCValAssign::SExt;
1104
1
    else if (ArgFlags.isZExt())
1105
0
        LocInfo = CCValAssign::ZExt;
1106
1
    else
1107
1
        LocInfo = CCValAssign::AExt;
1108
1
  }
1109
408
1110
408
  if (ArgFlags.isSRet()) {
1111
24
    unsigned Offset1 = State.AllocateStack(4, 4);
1112
24
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1113
24
    return false;
1114
24
  }
1115
384
1116
384
  if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1117
384
    return false;
1118
0
1119
0
  return true;  // CC didn't match.
1120
0
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_32_ThisCall_Win(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86FastISel.cpp:CC_X86_32_ThisCall_Win(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1095
48
                                   ISD::ArgFlagsTy ArgFlags, CCState &State) {
1096
48
1097
48
  if (LocVT == MVT::i1 ||
1098
48
      LocVT == MVT::i8 ||
1099
48
      LocVT == MVT::i16 ||
1100
48
      LocVT == MVT::v1i1) {
1101
0
    LocVT = MVT::i32;
1102
0
    if (ArgFlags.isSExt())
1103
0
        LocInfo = CCValAssign::SExt;
1104
0
    else if (ArgFlags.isZExt())
1105
0
        LocInfo = CCValAssign::ZExt;
1106
0
    else
1107
0
        LocInfo = CCValAssign::AExt;
1108
0
  }
1109
48
1110
48
  if (ArgFlags.isSRet()) {
1111
6
    unsigned Offset1 = State.AllocateStack(4, 4);
1112
6
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1113
6
    return false;
1114
6
  }
1115
42
1116
42
  if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1117
42
    return false;
1118
0
1119
0
  return true;  // CC didn't match.
1120
0
}
X86ISelLowering.cpp:CC_X86_32_ThisCall_Win(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1095
360
                                   ISD::ArgFlagsTy ArgFlags, CCState &State) {
1096
360
1097
360
  if (LocVT == MVT::i1 ||
1098
360
      LocVT == MVT::i8 ||
1099
360
      
LocVT == MVT::i16359
||
1100
360
      
LocVT == MVT::v1i1359
) {
1101
1
    LocVT = MVT::i32;
1102
1
    if (ArgFlags.isSExt())
1103
0
        LocInfo = CCValAssign::SExt;
1104
1
    else if (ArgFlags.isZExt())
1105
0
        LocInfo = CCValAssign::ZExt;
1106
1
    else
1107
1
        LocInfo = CCValAssign::AExt;
1108
1
  }
1109
360
1110
360
  if (ArgFlags.isSRet()) {
1111
18
    unsigned Offset1 = State.AllocateStack(4, 4);
1112
18
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1113
18
    return false;
1114
18
  }
1115
342
1116
342
  if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1117
342
    return false;
1118
0
1119
0
  return true;  // CC didn't match.
1120
0
}
1121
1122
1123
static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT,
1124
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
1125
214
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
1126
214
1127
214
  if (LocVT == MVT::v16i8 ||
1128
214
      
LocVT == MVT::v8i16212
||
1129
214
      
LocVT == MVT::v4i32204
||
1130
214
      
LocVT == MVT::v2i64184
||
1131
214
      
LocVT == MVT::v4f32175
||
1132
214
      
LocVT == MVT::v2f64108
) {
1133
124
    unsigned Offset1 = State.AllocateStack(16, 16);
1134
124
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1135
124
    return false;
1136
124
  }
1137
90
1138
90
  if (LocVT == MVT::v32i8 ||
1139
90
      
LocVT == MVT::v16i1688
||
1140
90
      
LocVT == MVT::v8i3286
||
1141
90
      
LocVT == MVT::v4i6479
||
1142
90
      
LocVT == MVT::v8f3276
||
1143
90
      
LocVT == MVT::v4f6458
) {
1144
42
    unsigned Offset2 = State.AllocateStack(32, 32);
1145
42
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1146
42
    return false;
1147
42
  }
1148
48
1149
48
  if (LocVT == MVT::v64i8 ||
1150
48
      
LocVT == MVT::v32i1638
||
1151
48
      
LocVT == MVT::v16i3234
||
1152
48
      
LocVT == MVT::v8i6433
||
1153
48
      
LocVT == MVT::v16f3216
||
1154
48
      
LocVT == MVT::v8f6415
) {
1155
42
    unsigned Offset3 = State.AllocateStack(64, 64);
1156
42
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
1157
42
    return false;
1158
42
  }
1159
6
1160
6
  return true;  // CC didn't match.
1161
6
}
X86CallLowering.cpp:CC_X86_32_Vector_Common(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1125
3
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
1126
3
1127
3
  if (LocVT == MVT::v16i8 ||
1128
3
      LocVT == MVT::v8i16 ||
1129
3
      LocVT == MVT::v4i32 ||
1130
3
      
LocVT == MVT::v2i640
||
1131
3
      
LocVT == MVT::v4f320
||
1132
3
      
LocVT == MVT::v2f640
) {
1133
3
    unsigned Offset1 = State.AllocateStack(16, 16);
1134
3
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1135
3
    return false;
1136
3
  }
1137
0
1138
0
  if (LocVT == MVT::v32i8 ||
1139
0
      LocVT == MVT::v16i16 ||
1140
0
      LocVT == MVT::v8i32 ||
1141
0
      LocVT == MVT::v4i64 ||
1142
0
      LocVT == MVT::v8f32 ||
1143
0
      LocVT == MVT::v4f64) {
1144
0
    unsigned Offset2 = State.AllocateStack(32, 32);
1145
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1146
0
    return false;
1147
0
  }
1148
0
1149
0
  if (LocVT == MVT::v64i8 ||
1150
0
      LocVT == MVT::v32i16 ||
1151
0
      LocVT == MVT::v16i32 ||
1152
0
      LocVT == MVT::v8i64 ||
1153
0
      LocVT == MVT::v16f32 ||
1154
0
      LocVT == MVT::v8f64) {
1155
0
    unsigned Offset3 = State.AllocateStack(64, 64);
1156
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
1157
0
    return false;
1158
0
  }
1159
0
1160
0
  return true;  // CC didn't match.
1161
0
}
X86FastISel.cpp:CC_X86_32_Vector_Common(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1125
1
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
1126
1
1127
1
  if (LocVT == MVT::v16i8 ||
1128
1
      LocVT == MVT::v8i16 ||
1129
1
      LocVT == MVT::v4i32 ||
1130
1
      LocVT == MVT::v2i64 ||
1131
1
      LocVT == MVT::v4f32 ||
1132
1
      
LocVT == MVT::v2f640
) {
1133
1
    unsigned Offset1 = State.AllocateStack(16, 16);
1134
1
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1135
1
    return false;
1136
1
  }
1137
0
1138
0
  if (LocVT == MVT::v32i8 ||
1139
0
      LocVT == MVT::v16i16 ||
1140
0
      LocVT == MVT::v8i32 ||
1141
0
      LocVT == MVT::v4i64 ||
1142
0
      LocVT == MVT::v8f32 ||
1143
0
      LocVT == MVT::v4f64) {
1144
0
    unsigned Offset2 = State.AllocateStack(32, 32);
1145
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1146
0
    return false;
1147
0
  }
1148
0
1149
0
  if (LocVT == MVT::v64i8 ||
1150
0
      LocVT == MVT::v32i16 ||
1151
0
      LocVT == MVT::v16i32 ||
1152
0
      LocVT == MVT::v8i64 ||
1153
0
      LocVT == MVT::v16f32 ||
1154
0
      LocVT == MVT::v8f64) {
1155
0
    unsigned Offset3 = State.AllocateStack(64, 64);
1156
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
1157
0
    return false;
1158
0
  }
1159
0
1160
0
  return true;  // CC didn't match.
1161
0
}
X86ISelLowering.cpp:CC_X86_32_Vector_Common(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1125
210
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
1126
210
1127
210
  if (LocVT == MVT::v16i8 ||
1128
210
      
LocVT == MVT::v8i16208
||
1129
210
      
LocVT == MVT::v4i32200
||
1130
210
      
LocVT == MVT::v2i64183
||
1131
210
      
LocVT == MVT::v4f32174
||
1132
210
      
LocVT == MVT::v2f64108
) {
1133
120
    unsigned Offset1 = State.AllocateStack(16, 16);
1134
120
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1135
120
    return false;
1136
120
  }
1137
90
1138
90
  if (LocVT == MVT::v32i8 ||
1139
90
      
LocVT == MVT::v16i1688
||
1140
90
      
LocVT == MVT::v8i3286
||
1141
90
      
LocVT == MVT::v4i6479
||
1142
90
      
LocVT == MVT::v8f3276
||
1143
90
      
LocVT == MVT::v4f6458
) {
1144
42
    unsigned Offset2 = State.AllocateStack(32, 32);
1145
42
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1146
42
    return false;
1147
42
  }
1148
48
1149
48
  if (LocVT == MVT::v64i8 ||
1150
48
      
LocVT == MVT::v32i1638
||
1151
48
      
LocVT == MVT::v16i3234
||
1152
48
      
LocVT == MVT::v8i6433
||
1153
48
      
LocVT == MVT::v16f3216
||
1154
48
      
LocVT == MVT::v8f6415
) {
1155
42
    unsigned Offset3 = State.AllocateStack(64, 64);
1156
42
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
1157
42
    return false;
1158
42
  }
1159
6
1160
6
  return true;  // CC didn't match.
1161
6
}
1162
1163
1164
static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT,
1165
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
1166
4.35k
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
1167
4.35k
1168
4.35k
  if (!State.isVarArg()) {
1169
4.35k
    if (LocVT == MVT::v16i8 ||
1170
4.35k
        
LocVT == MVT::v8i163.98k
||
1171
4.35k
        
LocVT == MVT::v4i323.61k
||
1172
4.35k
        
LocVT == MVT::v2i643.18k
||
1173
4.35k
        
LocVT == MVT::v4f322.93k
||
1174
4.35k
        
LocVT == MVT::v2f642.23k
) {
1175
2.52k
      static const MCPhysReg RegList1[] = {
1176
2.52k
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1177
2.52k
      };
1178
2.52k
      if (unsigned Reg = State.AllocateReg(RegList1)) {
1179
2.51k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1180
2.51k
        return false;
1181
2.51k
      }
1182
1.83k
    }
1183
4.35k
  }
1184
1.83k
1185
1.83k
  if (!State.isVarArg()) {
1186
1.83k
    if (LocVT == MVT::v32i8 ||
1187
1.83k
        
LocVT == MVT::v16i161.70k
||
1188
1.83k
        
LocVT == MVT::v8i321.52k
||
1189
1.83k
        
LocVT == MVT::v4i641.34k
||
1190
1.83k
        
LocVT == MVT::v8f321.25k
||
1191
1.83k
        
LocVT == MVT::v4f641.15k
) {
1192
740
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1193
740
        static const MCPhysReg RegList2[] = {
1194
740
          X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
1195
740
        };
1196
740
        if (unsigned Reg = State.AllocateReg(RegList2)) {
1197
720
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1198
720
          return false;
1199
720
        }
1200
1.11k
      }
1201
740
    }
1202
1.83k
  }
1203
1.11k
1204
1.11k
  if (!State.isVarArg()) {
1205
1.11k
    if (LocVT == MVT::v64i8 ||
1206
1.11k
        
LocVT == MVT::v32i161.11k
||
1207
1.11k
        
LocVT == MVT::v16i321.10k
||
1208
1.11k
        
LocVT == MVT::v8i64830
||
1209
1.11k
        
LocVT == MVT::v16f32606
||
1210
1.11k
        
LocVT == MVT::v8f64234
) {
1211
1.08k
      static const MCPhysReg RegList3[] = {
1212
1.08k
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
1213
1.08k
      };
1214
1.08k
      if (unsigned Reg = State.AllocateReg(RegList3)) {
1215
1.08k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1216
1.08k
        return false;
1217
1.08k
      }
1218
30
    }
1219
1.11k
  }
1220
30
1221
30
  if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1222
30
    return false;
1223
0
1224
0
  return true;  // CC didn't match.
1225
0
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_32_Vector_Darwin(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86FastISel.cpp:CC_X86_32_Vector_Darwin(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1166
5
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
1167
5
1168
5
  if (!State.isVarArg()) {
1169
5
    if (LocVT == MVT::v16i8 ||
1170
5
        LocVT == MVT::v8i16 ||
1171
5
        LocVT == MVT::v4i32 ||
1172
5
        LocVT == MVT::v2i64 ||
1173
5
        LocVT == MVT::v4f32 ||
1174
5
        
LocVT == MVT::v2f640
) {
1175
5
      static const MCPhysReg RegList1[] = {
1176
5
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1177
5
      };
1178
5
      if (unsigned Reg = State.AllocateReg(RegList1)) {
1179
4
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1180
4
        return false;
1181
4
      }
1182
1
    }
1183
5
  }
1184
1
1185
1
  if (!State.isVarArg()) {
1186
1
    if (LocVT == MVT::v32i8 ||
1187
1
        LocVT == MVT::v16i16 ||
1188
1
        LocVT == MVT::v8i32 ||
1189
1
        LocVT == MVT::v4i64 ||
1190
1
        LocVT == MVT::v8f32 ||
1191
1
        LocVT == MVT::v4f64) {
1192
0
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1193
0
        static const MCPhysReg RegList2[] = {
1194
0
          X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
1195
0
        };
1196
0
        if (unsigned Reg = State.AllocateReg(RegList2)) {
1197
0
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1198
0
          return false;
1199
0
        }
1200
1
      }
1201
0
    }
1202
1
  }
1203
1
1204
1
  if (!State.isVarArg()) {
1205
1
    if (LocVT == MVT::v64i8 ||
1206
1
        LocVT == MVT::v32i16 ||
1207
1
        LocVT == MVT::v16i32 ||
1208
1
        LocVT == MVT::v8i64 ||
1209
1
        LocVT == MVT::v16f32 ||
1210
1
        LocVT == MVT::v8f64) {
1211
0
      static const MCPhysReg RegList3[] = {
1212
0
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
1213
0
      };
1214
0
      if (unsigned Reg = State.AllocateReg(RegList3)) {
1215
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1216
0
        return false;
1217
0
      }
1218
1
    }
1219
1
  }
1220
1
1221
1
  if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1222
1
    return false;
1223
0
1224
0
  return true;  // CC didn't match.
1225
0
}
X86ISelLowering.cpp:CC_X86_32_Vector_Darwin(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1166
4.34k
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
1167
4.34k
1168
4.34k
  if (!State.isVarArg()) {
1169
4.34k
    if (LocVT == MVT::v16i8 ||
1170
4.34k
        
LocVT == MVT::v8i163.97k
||
1171
4.34k
        
LocVT == MVT::v4i323.60k
||
1172
4.34k
        
LocVT == MVT::v2i643.18k
||
1173
4.34k
        
LocVT == MVT::v4f322.92k
||
1174
4.34k
        
LocVT == MVT::v2f642.23k
) {
1175
2.52k
      static const MCPhysReg RegList1[] = {
1176
2.52k
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1177
2.52k
      };
1178
2.52k
      if (unsigned Reg = State.AllocateReg(RegList1)) {
1179
2.51k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1180
2.51k
        return false;
1181
2.51k
      }
1182
1.83k
    }
1183
4.34k
  }
1184
1.83k
1185
1.83k
  if (!State.isVarArg()) {
1186
1.83k
    if (LocVT == MVT::v32i8 ||
1187
1.83k
        
LocVT == MVT::v16i161.70k
||
1188
1.83k
        
LocVT == MVT::v8i321.52k
||
1189
1.83k
        
LocVT == MVT::v4i641.34k
||
1190
1.83k
        
LocVT == MVT::v8f321.25k
||
1191
1.83k
        
LocVT == MVT::v4f641.15k
) {
1192
740
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1193
740
        static const MCPhysReg RegList2[] = {
1194
740
          X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
1195
740
        };
1196
740
        if (unsigned Reg = State.AllocateReg(RegList2)) {
1197
720
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1198
720
          return false;
1199
720
        }
1200
1.11k
      }
1201
740
    }
1202
1.83k
  }
1203
1.11k
1204
1.11k
  if (!State.isVarArg()) {
1205
1.11k
    if (LocVT == MVT::v64i8 ||
1206
1.11k
        
LocVT == MVT::v32i161.11k
||
1207
1.11k
        
LocVT == MVT::v16i321.10k
||
1208
1.11k
        
LocVT == MVT::v8i64829
||
1209
1.11k
        
LocVT == MVT::v16f32605
||
1210
1.11k
        
LocVT == MVT::v8f64233
) {
1211
1.08k
      static const MCPhysReg RegList3[] = {
1212
1.08k
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
1213
1.08k
      };
1214
1.08k
      if (unsigned Reg = State.AllocateReg(RegList3)) {
1215
1.08k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1216
1.08k
        return false;
1217
1.08k
      }
1218
29
    }
1219
1.11k
  }
1220
29
1221
29
  if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1222
29
    return false;
1223
0
1224
0
  return true;  // CC didn't match.
1225
0
}
1226
1227
1228
static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT,
1229
                                      MVT LocVT, CCValAssign::LocInfo LocInfo,
1230
14.1k
                                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1231
14.1k
1232
14.1k
  if (!State.isVarArg()) {
1233
14.1k
    if (LocVT == MVT::v16i8 ||
1234
14.1k
        
LocVT == MVT::v8i1613.6k
||
1235
14.1k
        
LocVT == MVT::v4i3213.0k
||
1236
14.1k
        
LocVT == MVT::v2i6412.1k
||
1237
14.1k
        
LocVT == MVT::v4f3210.1k
||
1238
14.1k
        
LocVT == MVT::v2f648.19k
) {
1239
7.41k
      static const MCPhysReg RegList1[] = {
1240
7.41k
        X86::XMM0, X86::XMM1, X86::XMM2
1241
7.41k
      };
1242
7.41k
      if (unsigned Reg = State.AllocateReg(RegList1)) {
1243
7.30k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1244
7.30k
        return false;
1245
7.30k
      }
1246
6.87k
    }
1247
14.1k
  }
1248
6.87k
1249
6.87k
  if (!State.isVarArg()) {
1250
6.87k
    if (LocVT == MVT::v32i8 ||
1251
6.87k
        
LocVT == MVT::v16i166.50k
||
1252
6.87k
        
LocVT == MVT::v8i326.02k
||
1253
6.87k
        
LocVT == MVT::v4i645.42k
||
1254
6.87k
        
LocVT == MVT::v8f324.32k
||
1255
6.87k
        
LocVT == MVT::v4f643.47k
) {
1256
4.01k
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1257
4.01k
        static const MCPhysReg RegList2[] = {
1258
4.01k
          X86::YMM0, X86::YMM1, X86::YMM2
1259
4.01k
        };
1260
4.01k
        if (unsigned Reg = State.AllocateReg(RegList2)) {
1261
3.99k
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1262
3.99k
          return false;
1263
3.99k
        }
1264
2.88k
      }
1265
4.01k
    }
1266
6.87k
  }
1267
2.88k
1268
2.88k
  if (!State.isVarArg()) {
1269
2.88k
    if (LocVT == MVT::v64i8 ||
1270
2.88k
        
LocVT == MVT::v32i162.65k
||
1271
2.88k
        
LocVT == MVT::v16i322.25k
||
1272
2.88k
        
LocVT == MVT::v8i642.04k
||
1273
2.88k
        
LocVT == MVT::v16f321.22k
||
1274
2.88k
        
LocVT == MVT::v8f64751
) {
1275
2.73k
      static const MCPhysReg RegList3[] = {
1276
2.73k
        X86::ZMM0, X86::ZMM1, X86::ZMM2
1277
2.73k
      };
1278
2.73k
      if (unsigned Reg = State.AllocateReg(RegList3)) {
1279
2.69k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1280
2.69k
        return false;
1281
2.69k
      }
1282
184
    }
1283
2.88k
  }
1284
184
1285
184
  if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1286
178
    return false;
1287
6
1288
6
  return true;  // CC didn't match.
1289
6
}
X86CallLowering.cpp:CC_X86_32_Vector_Standard(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1230
22
                                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1231
22
1232
22
  if (!State.isVarArg()) {
1233
22
    if (LocVT == MVT::v16i8 ||
1234
22
        LocVT == MVT::v8i16 ||
1235
22
        LocVT == MVT::v4i32 ||
1236
22
        
LocVT == MVT::v2i640
||
1237
22
        
LocVT == MVT::v4f320
||
1238
22
        
LocVT == MVT::v2f640
) {
1239
22
      static const MCPhysReg RegList1[] = {
1240
22
        X86::XMM0, X86::XMM1, X86::XMM2
1241
22
      };
1242
22
      if (unsigned Reg = State.AllocateReg(RegList1)) {
1243
19
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1244
19
        return false;
1245
19
      }
1246
3
    }
1247
22
  }
1248
3
1249
3
  if (!State.isVarArg()) {
1250
3
    if (LocVT == MVT::v32i8 ||
1251
3
        LocVT == MVT::v16i16 ||
1252
3
        LocVT == MVT::v8i32 ||
1253
3
        LocVT == MVT::v4i64 ||
1254
3
        LocVT == MVT::v8f32 ||
1255
3
        LocVT == MVT::v4f64) {
1256
0
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1257
0
        static const MCPhysReg RegList2[] = {
1258
0
          X86::YMM0, X86::YMM1, X86::YMM2
1259
0
        };
1260
0
        if (unsigned Reg = State.AllocateReg(RegList2)) {
1261
0
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1262
0
          return false;
1263
0
        }
1264
3
      }
1265
0
    }
1266
3
  }
1267
3
1268
3
  if (!State.isVarArg()) {
1269
3
    if (LocVT == MVT::v64i8 ||
1270
3
        LocVT == MVT::v32i16 ||
1271
3
        LocVT == MVT::v16i32 ||
1272
3
        LocVT == MVT::v8i64 ||
1273
3
        LocVT == MVT::v16f32 ||
1274
3
        LocVT == MVT::v8f64) {
1275
0
      static const MCPhysReg RegList3[] = {
1276
0
        X86::ZMM0, X86::ZMM1, X86::ZMM2
1277
0
      };
1278
0
      if (unsigned Reg = State.AllocateReg(RegList3)) {
1279
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1280
0
        return false;
1281
0
      }
1282
3
    }
1283
3
  }
1284
3
1285
3
  if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1286
3
    return false;
1287
0
1288
0
  return true;  // CC didn't match.
1289
0
}
Unexecuted instantiation: X86FastISel.cpp:CC_X86_32_Vector_Standard(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:CC_X86_32_Vector_Standard(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1230
14.1k
                                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1231
14.1k
1232
14.1k
  if (!State.isVarArg()) {
1233
14.1k
    if (LocVT == MVT::v16i8 ||
1234
14.1k
        
LocVT == MVT::v8i1613.6k
||
1235
14.1k
        
LocVT == MVT::v4i3213.0k
||
1236
14.1k
        
LocVT == MVT::v2i6412.1k
||
1237
14.1k
        
LocVT == MVT::v4f3210.1k
||
1238
14.1k
        
LocVT == MVT::v2f648.19k
) {
1239
7.39k
      static const MCPhysReg RegList1[] = {
1240
7.39k
        X86::XMM0, X86::XMM1, X86::XMM2
1241
7.39k
      };
1242
7.39k
      if (unsigned Reg = State.AllocateReg(RegList1)) {
1243
7.28k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1244
7.28k
        return false;
1245
7.28k
      }
1246
6.86k
    }
1247
14.1k
  }
1248
6.86k
1249
6.86k
  if (!State.isVarArg()) {
1250
6.86k
    if (LocVT == MVT::v32i8 ||
1251
6.86k
        
LocVT == MVT::v16i166.49k
||
1252
6.86k
        
LocVT == MVT::v8i326.02k
||
1253
6.86k
        
LocVT == MVT::v4i645.42k
||
1254
6.86k
        
LocVT == MVT::v8f324.31k
||
1255
6.86k
        
LocVT == MVT::v4f643.46k
) {
1256
4.01k
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1257
4.01k
        static const MCPhysReg RegList2[] = {
1258
4.01k
          X86::YMM0, X86::YMM1, X86::YMM2
1259
4.01k
        };
1260
4.01k
        if (unsigned Reg = State.AllocateReg(RegList2)) {
1261
3.99k
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1262
3.99k
          return false;
1263
3.99k
        }
1264
2.87k
      }
1265
4.01k
    }
1266
6.86k
  }
1267
2.87k
1268
2.87k
  if (!State.isVarArg()) {
1269
2.87k
    if (LocVT == MVT::v64i8 ||
1270
2.87k
        
LocVT == MVT::v32i162.65k
||
1271
2.87k
        
LocVT == MVT::v16i322.25k
||
1272
2.87k
        
LocVT == MVT::v8i642.04k
||
1273
2.87k
        
LocVT == MVT::v16f321.22k
||
1274
2.87k
        
LocVT == MVT::v8f64748
) {
1275
2.73k
      static const MCPhysReg RegList3[] = {
1276
2.73k
        X86::ZMM0, X86::ZMM1, X86::ZMM2
1277
2.73k
      };
1278
2.73k
      if (unsigned Reg = State.AllocateReg(RegList3)) {
1279
2.69k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1280
2.69k
        return false;
1281
2.69k
      }
1282
181
    }
1283
2.87k
  }
1284
181
1285
181
  if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1286
175
    return false;
1287
6
1288
6
  return true;  // CC didn't match.
1289
6
}
1290
1291
1292
static bool CC_X86_64(unsigned ValNo, MVT ValVT,
1293
                      MVT LocVT, CCValAssign::LocInfo LocInfo,
1294
483k
                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1295
483k
1296
483k
  if (State.getCallingConv() == CallingConv::GHC) {
1297
62
    if (!CC_X86_64_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1298
62
      return false;
1299
483k
  }
1300
483k
1301
483k
  if (State.getCallingConv() == CallingConv::HiPE) {
1302
42
    if (!CC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1303
42
      return false;
1304
483k
  }
1305
483k
1306
483k
  if (State.getCallingConv() == CallingConv::WebKit_JS) {
1307
69
    if (!CC_X86_64_WebKit_JS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1308
69
      return false;
1309
483k
  }
1310
483k
1311
483k
  if (State.getCallingConv() == CallingConv::AnyReg) {
1312
0
    if (!CC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1313
0
      return false;
1314
483k
  }
1315
483k
1316
483k
  if (State.getCallingConv() == CallingConv::Win64) {
1317
55
    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1318
55
      return false;
1319
483k
  }
1320
483k
1321
483k
  if (State.getCallingConv() == CallingConv::X86_64_SysV) {
1322
22
    if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1323
22
      return false;
1324
483k
  }
1325
483k
1326
483k
  if (State.getCallingConv() == CallingConv::X86_VectorCall) {
1327
152
    if (!CC_X86_Win64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1328
152
      return false;
1329
483k
  }
1330
483k
1331
483k
  if (State.getCallingConv() == CallingConv::HHVM) {
1332
112
    if (!CC_X86_64_HHVM(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1333
112
      return false;
1334
483k
  }
1335
483k
1336
483k
  if (State.getCallingConv() == CallingConv::HHVM_C) {
1337
25
    if (!CC_X86_64_HHVM_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1338
25
      return false;
1339
483k
  }
1340
483k
1341
483k
  if (State.getCallingConv() == CallingConv::X86_RegCall) {
1342
380
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
1343
195
      if (!CC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1344
195
        return false;
1345
483k
    }
1346
380
  }
1347
483k
1348
483k
  if (State.getCallingConv() == CallingConv::X86_RegCall) {
1349
185
    if (!CC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1350
185
      return false;
1351
482k
  }
1352
482k
1353
482k
  if (State.getCallingConv() == CallingConv::X86_INTR) {
1354
20
    if (!CC_X86_64_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1355
20
      return false;
1356
482k
  }
1357
482k
1358
482k
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
1359
2.83k
    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1360
2.82k
      return false;
1361
480k
  }
1362
480k
1363
480k
  if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1364
478k
    return false;
1365
1.85k
1366
1.85k
  return true;  // CC didn't match.
1367
1.85k
}
X86CallLowering.cpp:CC_X86_64(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1294
727
                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1295
727
1296
727
  if (State.getCallingConv() == CallingConv::GHC) {
1297
0
    if (!CC_X86_64_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1298
0
      return false;
1299
727
  }
1300
727
1301
727
  if (State.getCallingConv() == CallingConv::HiPE) {
1302
0
    if (!CC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1303
0
      return false;
1304
727
  }
1305
727
1306
727
  if (State.getCallingConv() == CallingConv::WebKit_JS) {
1307
0
    if (!CC_X86_64_WebKit_JS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1308
0
      return false;
1309
727
  }
1310
727
1311
727
  if (State.getCallingConv() == CallingConv::AnyReg) {
1312
0
    if (!CC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1313
0
      return false;
1314
727
  }
1315
727
1316
727
  if (State.getCallingConv() == CallingConv::Win64) {
1317
0
    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1318
0
      return false;
1319
727
  }
1320
727
1321
727
  if (State.getCallingConv() == CallingConv::X86_64_SysV) {
1322
0
    if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1323
0
      return false;
1324
727
  }
1325
727
1326
727
  if (State.getCallingConv() == CallingConv::X86_VectorCall) {
1327
0
    if (!CC_X86_Win64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1328
0
      return false;
1329
727
  }
1330
727
1331
727
  if (State.getCallingConv() == CallingConv::HHVM) {
1332
0
    if (!CC_X86_64_HHVM(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1333
0
      return false;
1334
727
  }
1335
727
1336
727
  if (State.getCallingConv() == CallingConv::HHVM_C) {
1337
0
    if (!CC_X86_64_HHVM_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1338
0
      return false;
1339
727
  }
1340
727
1341
727
  if (State.getCallingConv() == CallingConv::X86_RegCall) {
1342
0
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
1343
0
      if (!CC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1344
0
        return false;
1345
727
    }
1346
0
  }
1347
727
1348
727
  if (State.getCallingConv() == CallingConv::X86_RegCall) {
1349
0
    if (!CC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1350
0
      return false;
1351
727
  }
1352
727
1353
727
  if (State.getCallingConv() == CallingConv::X86_INTR) {
1354
0
    if (!CC_X86_64_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1355
0
      return false;
1356
727
  }
1357
727
1358
727
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
1359
0
    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1360
0
      return false;
1361
727
  }
1362
727
1363
727
  if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1364
727
    return false;
1365
0
1366
0
  return true;  // CC didn't match.
1367
0
}
X86FastISel.cpp:CC_X86_64(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1294
629
                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1295
629
1296
629
  if (State.getCallingConv() == CallingConv::GHC) {
1297
0
    if (!CC_X86_64_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1298
0
      return false;
1299
629
  }
1300
629
1301
629
  if (State.getCallingConv() == CallingConv::HiPE) {
1302
0
    if (!CC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1303
0
      return false;
1304
629
  }
1305
629
1306
629
  if (State.getCallingConv() == CallingConv::WebKit_JS) {
1307
20
    if (!CC_X86_64_WebKit_JS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1308
20
      return false;
1309
609
  }
1310
609
1311
609
  if (State.getCallingConv() == CallingConv::AnyReg) {
1312
0
    if (!CC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1313
0
      return false;
1314
609
  }
1315
609
1316
609
  if (State.getCallingConv() == CallingConv::Win64) {
1317
0
    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1318
0
      return false;
1319
609
  }
1320
609
1321
609
  if (State.getCallingConv() == CallingConv::X86_64_SysV) {
1322
0
    if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1323
0
      return false;
1324
609
  }
1325
609
1326
609
  if (State.getCallingConv() == CallingConv::X86_VectorCall) {
1327
0
    if (!CC_X86_Win64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1328
0
      return false;
1329
609
  }
1330
609
1331
609
  if (State.getCallingConv() == CallingConv::HHVM) {
1332
0
    if (!CC_X86_64_HHVM(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1333
0
      return false;
1334
609
  }
1335
609
1336
609
  if (State.getCallingConv() == CallingConv::HHVM_C) {
1337
0
    if (!CC_X86_64_HHVM_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1338
0
      return false;
1339
609
  }
1340
609
1341
609
  if (State.getCallingConv() == CallingConv::X86_RegCall) {
1342
0
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
1343
0
      if (!CC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1344
0
        return false;
1345
609
    }
1346
0
  }
1347
609
1348
609
  if (State.getCallingConv() == CallingConv::X86_RegCall) {
1349
0
    if (!CC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1350
0
      return false;
1351
609
  }
1352
609
1353
609
  if (State.getCallingConv() == CallingConv::X86_INTR) {
1354
0
    if (!CC_X86_64_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1355
0
      return false;
1356
609
  }
1357
609
1358
609
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
1359
9
    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1360
9
      return false;
1361
600
  }
1362
600
1363
600
  if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1364
600
    return false;
1365
0
1366
0
  return true;  // CC didn't match.
1367
0
}
X86ISelLowering.cpp:CC_X86_64(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1294
482k
                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1295
482k
1296
482k
  if (State.getCallingConv() == CallingConv::GHC) {
1297
62
    if (!CC_X86_64_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1298
62
      return false;
1299
482k
  }
1300
482k
1301
482k
  if (State.getCallingConv() == CallingConv::HiPE) {
1302
42
    if (!CC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1303
42
      return false;
1304
482k
  }
1305
482k
1306
482k
  if (State.getCallingConv() == CallingConv::WebKit_JS) {
1307
49
    if (!CC_X86_64_WebKit_JS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1308
49
      return false;
1309
482k
  }
1310
482k
1311
482k
  if (State.getCallingConv() == CallingConv::AnyReg) {
1312
0
    if (!CC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1313
0
      return false;
1314
482k
  }
1315
482k
1316
482k
  if (State.getCallingConv() == CallingConv::Win64) {
1317
55
    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1318
55
      return false;
1319
482k
  }
1320
482k
1321
482k
  if (State.getCallingConv() == CallingConv::X86_64_SysV) {
1322
22
    if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1323
22
      return false;
1324
482k
  }
1325
482k
1326
482k
  if (State.getCallingConv() == CallingConv::X86_VectorCall) {
1327
152
    if (!CC_X86_Win64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1328
152
      return false;
1329
482k
  }
1330
482k
1331
482k
  if (State.getCallingConv() == CallingConv::HHVM) {
1332
112
    if (!CC_X86_64_HHVM(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1333
112
      return false;
1334
482k
  }
1335
482k
1336
482k
  if (State.getCallingConv() == CallingConv::HHVM_C) {
1337
25
    if (!CC_X86_64_HHVM_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1338
25
      return false;
1339
481k
  }
1340
481k
1341
481k
  if (State.getCallingConv() == CallingConv::X86_RegCall) {
1342
380
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
1343
195
      if (!CC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1344
195
        return false;
1345
481k
    }
1346
380
  }
1347
481k
1348
481k
  if (State.getCallingConv() == CallingConv::X86_RegCall) {
1349
185
    if (!CC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1350
185
      return false;
1351
481k
  }
1352
481k
1353
481k
  if (State.getCallingConv() == CallingConv::X86_INTR) {
1354
20
    if (!CC_X86_64_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1355
20
      return false;
1356
481k
  }
1357
481k
1358
481k
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
1359
2.82k
    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1360
2.81k
      return false;
1361
478k
  }
1362
478k
1363
478k
  if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1364
476k
    return false;
1365
1.85k
1366
1.85k
  return true;  // CC didn't match.
1367
1.85k
}
1368
1369
1370
static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
1371
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
1372
0
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
1373
0
1374
0
  if (CC_X86_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1375
0
    return false;
1376
0
1377
0
  return true;  // CC didn't match.
1378
0
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_64_AnyReg(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86FastISel.cpp:CC_X86_64_AnyReg(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86ISelLowering.cpp:CC_X86_64_AnyReg(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
1379
1380
1381
static bool CC_X86_64_C(unsigned ValNo, MVT ValVT,
1382
                        MVT LocVT, CCValAssign::LocInfo LocInfo,
1383
480k
                        ISD::ArgFlagsTy ArgFlags, CCState &State) {
1384
480k
1385
480k
  if (ArgFlags.isByVal()) {
1386
511
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
1387
511
    return false;
1388
511
  }
1389
479k
1390
479k
  if (LocVT == MVT::i1 ||
1391
479k
      
LocVT == MVT::i8479k
||
1392
479k
      
LocVT == MVT::i16457k
||
1393
479k
      
LocVT == MVT::v1i1454k
) {
1394
25.6k
    LocVT = MVT::i32;
1395
25.6k
    if (ArgFlags.isSExt())
1396
385
        LocInfo = CCValAssign::SExt;
1397
25.2k
    else if (ArgFlags.isZExt())
1398
16.7k
        LocInfo = CCValAssign::ZExt;
1399
8.46k
    else
1400
8.46k
        LocInfo = CCValAssign::AExt;
1401
25.6k
  }
1402
479k
1403
479k
  if (ArgFlags.isNest()) {
1404
21
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTarget64BitILP32()) {
1405
2
      if (unsigned Reg = State.AllocateReg(X86::R10D)) {
1406
2
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1407
2
        return false;
1408
2
      }
1409
479k
    }
1410
21
  }
1411
479k
1412
479k
  if (ArgFlags.isNest()) {
1413
19
    if (unsigned Reg = State.AllocateReg(X86::R10)) {
1414
19
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1415
19
      return false;
1416
19
    }
1417
479k
  }
1418
479k
1419
479k
  if (ArgFlags.isSwiftSelf()) {
1420
40
    if (LocVT == MVT::i64) {
1421
40
      if (unsigned Reg = State.AllocateReg(X86::R13)) {
1422
40
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1423
40
        return false;
1424
40
      }
1425
479k
    }
1426
40
  }
1427
479k
1428
479k
  if (ArgFlags.isSwiftError()) {
1429
74
    if (LocVT == MVT::i64) {
1430
74
      if (unsigned Reg = State.AllocateReg(X86::R12)) {
1431
74
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1432
74
        return false;
1433
74
      }
1434
479k
    }
1435
74
  }
1436
479k
1437
479k
  if (State.getCallingConv() == CallingConv::Swift) {
1438
134
    if (ArgFlags.isSRet()) {
1439
6
      if (LocVT == MVT::i64) {
1440
6
        if (unsigned Reg = State.AllocateReg(X86::RAX)) {
1441
6
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1442
6
          return false;
1443
6
        }
1444
479k
      }
1445
6
    }
1446
134
  }
1447
479k
1448
479k
  if (LocVT == MVT::i32) {
1449
67.8k
    static const MCPhysReg RegList1[] = {
1450
67.8k
      X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1451
67.8k
    };
1452
67.8k
    if (unsigned Reg = State.AllocateReg(RegList1)) {
1453
58.8k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1454
58.8k
      return false;
1455
58.8k
    }
1456
420k
  }
1457
420k
1458
420k
  if (LocVT == MVT::i64) {
1459
299k
    static const MCPhysReg RegList2[] = {
1460
299k
      X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1461
299k
    };
1462
299k
    if (unsigned Reg = State.AllocateReg(RegList2)) {
1463
293k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1464
293k
      return false;
1465
293k
    }
1466
127k
  }
1467
127k
1468
127k
  if (LocVT == MVT::x86mmx) {
1469
1.85k
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()) {
1470
12
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
1471
12
        LocVT = MVT::v2i64;
1472
12
        if (ArgFlags.isSExt())
1473
0
                LocInfo = CCValAssign::SExt;
1474
12
        else if (ArgFlags.isZExt())
1475
0
                LocInfo = CCValAssign::ZExt;
1476
12
        else
1477
12
                LocInfo = CCValAssign::AExt;
1478
12
      }
1479
12
    }
1480
1.85k
  }
1481
127k
1482
127k
  if (LocVT == MVT::v2i1) {
1483
121
    LocVT = MVT::v2i64;
1484
121
    if (ArgFlags.isSExt())
1485
0
        LocInfo = CCValAssign::SExt;
1486
121
    else if (ArgFlags.isZExt())
1487
0
        LocInfo = CCValAssign::ZExt;
1488
121
    else
1489
121
        LocInfo = CCValAssign::AExt;
1490
121
  }
1491
127k
1492
127k
  if (LocVT == MVT::v4i1) {
1493
145
    LocVT = MVT::v4i32;
1494
145
    if (ArgFlags.isSExt())
1495
0
        LocInfo = CCValAssign::SExt;
1496
145
    else if (ArgFlags.isZExt())
1497
0
        LocInfo = CCValAssign::ZExt;
1498
145
    else
1499
145
        LocInfo = CCValAssign::AExt;
1500
145
  }
1501
127k
1502
127k
  if (LocVT == MVT::v8i1) {
1503
152
    LocVT = MVT::v8i16;
1504
152
    if (ArgFlags.isSExt())
1505
0
        LocInfo = CCValAssign::SExt;
1506
152
    else if (ArgFlags.isZExt())
1507
0
        LocInfo = CCValAssign::ZExt;
1508
152
    else
1509
152
        LocInfo = CCValAssign::AExt;
1510
152
  }
1511
127k
1512
127k
  if (LocVT == MVT::v16i1) {
1513
188
    LocVT = MVT::v16i8;
1514
188
    if (ArgFlags.isSExt())
1515
0
        LocInfo = CCValAssign::SExt;
1516
188
    else if (ArgFlags.isZExt())
1517
0
        LocInfo = CCValAssign::ZExt;
1518
188
    else
1519
188
        LocInfo = CCValAssign::AExt;
1520
188
  }
1521
127k
1522
127k
  if (LocVT == MVT::v32i1) {
1523
36
    LocVT = MVT::v32i8;
1524
36
    if (ArgFlags.isSExt())
1525
0
        LocInfo = CCValAssign::SExt;
1526
36
    else if (ArgFlags.isZExt())
1527
0
        LocInfo = CCValAssign::ZExt;
1528
36
    else
1529
36
        LocInfo = CCValAssign::AExt;
1530
36
  }
1531
127k
1532
127k
  if (LocVT == MVT::v64i1) {
1533
9
    LocVT = MVT::v64i8;
1534
9
    if (ArgFlags.isSExt())
1535
0
        LocInfo = CCValAssign::SExt;
1536
9
    else if (ArgFlags.isZExt())
1537
0
        LocInfo = CCValAssign::ZExt;
1538
9
    else
1539
9
        LocInfo = CCValAssign::AExt;
1540
9
  }
1541
127k
1542
127k
  if (LocVT == MVT::f32 ||
1543
127k
      
LocVT == MVT::f64123k
||
1544
127k
      
LocVT == MVT::f128120k
||
1545
127k
      
LocVT == MVT::v16i8119k
||
1546
127k
      
LocVT == MVT::v8i16112k
||
1547
127k
      
LocVT == MVT::v4i32103k
||
1548
127k
      
LocVT == MVT::v2i6492.9k
||
1549
127k
      
LocVT == MVT::v4f3281.8k
||
1550
127k
      
LocVT == MVT::v2f6471.3k
) {
1551
63.1k
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1552
63.0k
      static const MCPhysReg RegList3[] = {
1553
63.0k
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1554
63.0k
      };
1555
63.0k
      if (unsigned Reg = State.AllocateReg(RegList3)) {
1556
61.2k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1557
61.2k
        return false;
1558
61.2k
      }
1559
65.8k
    }
1560
63.1k
  }
1561
65.8k
1562
65.8k
  if (!State.isVarArg()) {
1563
65.0k
    if (LocVT == MVT::v32i8 ||
1564
65.0k
        
LocVT == MVT::v16i1660.4k
||
1565
65.0k
        
LocVT == MVT::v8i3254.8k
||
1566
65.0k
        
LocVT == MVT::v4i6449.5k
||
1567
65.0k
        
LocVT == MVT::v8f3243.9k
||
1568
65.0k
        
LocVT == MVT::v4f6438.3k
) {
1569
31.5k
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1570
31.5k
        static const MCPhysReg RegList4[] = {
1571
31.5k
          X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
1572
31.5k
        };
1573
31.5k
        if (unsigned Reg = State.AllocateReg(RegList4)) {
1574
31.4k
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1575
31.4k
          return false;
1576
31.4k
        }
1577
34.4k
      }
1578
31.5k
    }
1579
65.0k
  }
1580
34.4k
1581
34.4k
  if (!State.isVarArg()) {
1582
33.5k
    if (LocVT == MVT::v64i8 ||
1583
33.5k
        
LocVT == MVT::v32i1632.7k
||
1584
33.5k
        
LocVT == MVT::v16i3231.5k
||
1585
33.5k
        
LocVT == MVT::v8i6428.7k
||
1586
33.5k
        
LocVT == MVT::v16f3224.9k
||
1587
33.5k
        
LocVT == MVT::v8f6421.8k
) {
1588
14.5k
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
1589
14.5k
        static const MCPhysReg RegList5[] = {
1590
14.5k
          X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
1591
14.5k
        };
1592
14.5k
        if (unsigned Reg = State.AllocateReg(RegList5)) {
1593
14.5k
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1594
14.5k
          return false;
1595
14.5k
        }
1596
19.8k
      }
1597
14.5k
    }
1598
33.5k
  }
1599
19.8k
1600
19.8k
  if (LocVT == MVT::i32 ||
1601
19.8k
      
LocVT == MVT::i6410.8k
||
1602
19.8k
      
LocVT == MVT::f324.45k
||
1603
19.8k
      
LocVT == MVT::f644.40k
) {
1604
15.4k
    unsigned Offset6 = State.AllocateStack(8, 8);
1605
15.4k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
1606
15.4k
    return false;
1607
15.4k
  }
1608
4.40k
1609
4.40k
  if (LocVT == MVT::f80 ||
1610
4.40k
      
LocVT == MVT::f1283.82k
) {
1611
699
    unsigned Offset7 = State.AllocateStack(
1612
699
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 
1613
699
      State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
1614
699
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
1615
699
    return false;
1616
699
  }
1617
3.70k
1618
3.70k
  if (LocVT == MVT::v16i8 ||
1619
3.70k
      
LocVT == MVT::v8i163.59k
||
1620
3.70k
      
LocVT == MVT::v4i323.53k
||
1621
3.70k
      
LocVT == MVT::v2i643.46k
||
1622
3.70k
      
LocVT == MVT::v4f322.12k
||
1623
3.70k
      
LocVT == MVT::v2f642.08k
) {
1624
1.71k
    unsigned Offset8 = State.AllocateStack(16, 16);
1625
1.71k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
1626
1.71k
    return false;
1627
1.71k
  }
1628
1.98k
1629
1.98k
  if (LocVT == MVT::v32i8 ||
1630
1.98k
      
LocVT == MVT::v16i161.91k
||
1631
1.98k
      
LocVT == MVT::v8i321.91k
||
1632
1.98k
      
LocVT == MVT::v4i641.91k
||
1633
1.98k
      
LocVT == MVT::v8f321.87k
||
1634
1.98k
      
LocVT == MVT::v4f641.87k
) {
1635
129
    unsigned Offset9 = State.AllocateStack(32, 32);
1636
129
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
1637
129
    return false;
1638
129
  }
1639
1.85k
1640
1.85k
  if (LocVT == MVT::v16i32 ||
1641
1.85k
      LocVT == MVT::v8i64 ||
1642
1.85k
      LocVT == MVT::v16f32 ||
1643
1.85k
      LocVT == MVT::v8f64) {
1644
0
    unsigned Offset10 = State.AllocateStack(64, 64);
1645
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
1646
0
    return false;
1647
0
  }
1648
1.85k
1649
1.85k
  return true;  // CC didn't match.
1650
1.85k
}
X86CallLowering.cpp:CC_X86_64_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1383
727
                        ISD::ArgFlagsTy ArgFlags, CCState &State) {
1384
727
1385
727
  if (ArgFlags.isByVal()) {
1386
0
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
1387
0
    return false;
1388
0
  }
1389
727
1390
727
  if (LocVT == MVT::i1 ||
1391
727
      
LocVT == MVT::i8721
||
1392
727
      
LocVT == MVT::i16681
||
1393
727
      
LocVT == MVT::v1i1653
) {
1394
74
    LocVT = MVT::i32;
1395
74
    if (ArgFlags.isSExt())
1396
2
        LocInfo = CCValAssign::SExt;
1397
72
    else if (ArgFlags.isZExt())
1398
2
        LocInfo = CCValAssign::ZExt;
1399
70
    else
1400
70
        LocInfo = CCValAssign::AExt;
1401
74
  }
1402
727
1403
727
  if (ArgFlags.isNest()) {
1404
0
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTarget64BitILP32()) {
1405
0
      if (unsigned Reg = State.AllocateReg(X86::R10D)) {
1406
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1407
0
        return false;
1408
0
      }
1409
727
    }
1410
0
  }
1411
727
1412
727
  if (ArgFlags.isNest()) {
1413
0
    if (unsigned Reg = State.AllocateReg(X86::R10)) {
1414
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1415
0
      return false;
1416
0
    }
1417
727
  }
1418
727
1419
727
  if (ArgFlags.isSwiftSelf()) {
1420
0
    if (LocVT == MVT::i64) {
1421
0
      if (unsigned Reg = State.AllocateReg(X86::R13)) {
1422
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1423
0
        return false;
1424
0
      }
1425
727
    }
1426
0
  }
1427
727
1428
727
  if (ArgFlags.isSwiftError()) {
1429
0
    if (LocVT == MVT::i64) {
1430
0
      if (unsigned Reg = State.AllocateReg(X86::R12)) {
1431
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1432
0
        return false;
1433
0
      }
1434
727
    }
1435
0
  }
1436
727
1437
727
  if (State.getCallingConv() == CallingConv::Swift) {
1438
0
    if (ArgFlags.isSRet()) {
1439
0
      if (LocVT == MVT::i64) {
1440
0
        if (unsigned Reg = State.AllocateReg(X86::RAX)) {
1441
0
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1442
0
          return false;
1443
0
        }
1444
727
      }
1445
0
    }
1446
0
  }
1447
727
1448
727
  if (LocVT == MVT::i32) {
1449
256
    static const MCPhysReg RegList1[] = {
1450
256
      X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1451
256
    };
1452
256
    if (unsigned Reg = State.AllocateReg(RegList1)) {
1453
248
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1454
248
      return false;
1455
248
    }
1456
479
  }
1457
479
1458
479
  if (LocVT == MVT::i64) {
1459
199
    static const MCPhysReg RegList2[] = {
1460
199
      X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1461
199
    };
1462
199
    if (unsigned Reg = State.AllocateReg(RegList2)) {
1463
195
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1464
195
      return false;
1465
195
    }
1466
284
  }
1467
284
1468
284
  if (LocVT == MVT::x86mmx) {
1469
0
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()) {
1470
0
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
1471
0
        LocVT = MVT::v2i64;
1472
0
        if (ArgFlags.isSExt())
1473
0
                LocInfo = CCValAssign::SExt;
1474
0
        else if (ArgFlags.isZExt())
1475
0
                LocInfo = CCValAssign::ZExt;
1476
0
        else
1477
0
                LocInfo = CCValAssign::AExt;
1478
0
      }
1479
0
    }
1480
0
  }
1481
284
1482
284
  if (LocVT == MVT::v2i1) {
1483
0
    LocVT = MVT::v2i64;
1484
0
    if (ArgFlags.isSExt())
1485
0
        LocInfo = CCValAssign::SExt;
1486
0
    else if (ArgFlags.isZExt())
1487
0
        LocInfo = CCValAssign::ZExt;
1488
0
    else
1489
0
        LocInfo = CCValAssign::AExt;
1490
0
  }
1491
284
1492
284
  if (LocVT == MVT::v4i1) {
1493
0
    LocVT = MVT::v4i32;
1494
0
    if (ArgFlags.isSExt())
1495
0
        LocInfo = CCValAssign::SExt;
1496
0
    else if (ArgFlags.isZExt())
1497
0
        LocInfo = CCValAssign::ZExt;
1498
0
    else
1499
0
        LocInfo = CCValAssign::AExt;
1500
0
  }
1501
284
1502
284
  if (LocVT == MVT::v8i1) {
1503
0
    LocVT = MVT::v8i16;
1504
0
    if (ArgFlags.isSExt())
1505
0
        LocInfo = CCValAssign::SExt;
1506
0
    else if (ArgFlags.isZExt())
1507
0
        LocInfo = CCValAssign::ZExt;
1508
0
    else
1509
0
        LocInfo = CCValAssign::AExt;
1510
0
  }
1511
284
1512
284
  if (LocVT == MVT::v16i1) {
1513
0
    LocVT = MVT::v16i8;
1514
0
    if (ArgFlags.isSExt())
1515
0
        LocInfo = CCValAssign::SExt;
1516
0
    else if (ArgFlags.isZExt())
1517
0
        LocInfo = CCValAssign::ZExt;
1518
0
    else
1519
0
        LocInfo = CCValAssign::AExt;
1520
0
  }
1521
284
1522
284
  if (LocVT == MVT::v32i1) {
1523
0
    LocVT = MVT::v32i8;
1524
0
    if (ArgFlags.isSExt())
1525
0
        LocInfo = CCValAssign::SExt;
1526
0
    else if (ArgFlags.isZExt())
1527
0
        LocInfo = CCValAssign::ZExt;
1528
0
    else
1529
0
        LocInfo = CCValAssign::AExt;
1530
0
  }
1531
284
1532
284
  if (LocVT == MVT::v64i1) {
1533
0
    LocVT = MVT::v64i8;
1534
0
    if (ArgFlags.isSExt())
1535
0
        LocInfo = CCValAssign::SExt;
1536
0
    else if (ArgFlags.isZExt())
1537
0
        LocInfo = CCValAssign::ZExt;
1538
0
    else
1539
0
        LocInfo = CCValAssign::AExt;
1540
0
  }
1541
284
1542
284
  if (LocVT == MVT::f32 ||
1543
284
      
LocVT == MVT::f64244
||
1544
284
      
LocVT == MVT::f128208
||
1545
284
      
LocVT == MVT::v16i8208
||
1546
284
      
LocVT == MVT::v8i16200
||
1547
284
      
LocVT == MVT::v4i32190
||
1548
284
      
LocVT == MVT::v2i64138
||
1549
284
      
LocVT == MVT::v4f32128
||
1550
284
      
LocVT == MVT::v2f64112
) {
1551
172
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1552
172
      static const MCPhysReg RegList3[] = {
1553
172
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1554
172
      };
1555
172
      if (unsigned Reg = State.AllocateReg(RegList3)) {
1556
172
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1557
172
        return false;
1558
172
      }
1559
112
    }
1560
172
  }
1561
112
1562
112
  if (!State.isVarArg()) {
1563
112
    if (LocVT == MVT::v32i8 ||
1564
112
        
LocVT == MVT::v16i1696
||
1565
112
        
LocVT == MVT::v8i3278
||
1566
112
        
LocVT == MVT::v4i6456
||
1567
112
        
LocVT == MVT::v8f3238
||
1568
112
        
LocVT == MVT::v4f6438
) {
1569
74
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1570
74
        static const MCPhysReg RegList4[] = {
1571
74
          X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
1572
74
        };
1573
74
        if (unsigned Reg = State.AllocateReg(RegList4)) {
1574
74
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1575
74
          return false;
1576
74
        }
1577
38
      }
1578
74
    }
1579
112
  }
1580
38
1581
38
  if (!State.isVarArg()) {
1582
38
    if (LocVT == MVT::v64i8 ||
1583
38
        
LocVT == MVT::v32i1634
||
1584
38
        
LocVT == MVT::v16i3228
||
1585
38
        
LocVT == MVT::v8i6418
||
1586
38
        
LocVT == MVT::v16f3212
||
1587
38
        
LocVT == MVT::v8f6412
) {
1588
26
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
1589
26
        static const MCPhysReg RegList5[] = {
1590
26
          X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
1591
26
        };
1592
26
        if (unsigned Reg = State.AllocateReg(RegList5)) {
1593
26
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1594
26
          return false;
1595
26
        }
1596
12
      }
1597
26
    }
1598
38
  }
1599
12
1600
12
  if (LocVT == MVT::i32 ||
1601
12
      
LocVT == MVT::i644
||
1602
12
      
LocVT == MVT::f320
||
1603
12
      
LocVT == MVT::f640
) {
1604
12
    unsigned Offset6 = State.AllocateStack(8, 8);
1605
12
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
1606
12
    return false;
1607
12
  }
1608
0
1609
0
  if (LocVT == MVT::f80 ||
1610
0
      LocVT == MVT::f128) {
1611
0
    unsigned Offset7 = State.AllocateStack(
1612
0
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 
1613
0
      State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
1614
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
1615
0
    return false;
1616
0
  }
1617
0
1618
0
  if (LocVT == MVT::v16i8 ||
1619
0
      LocVT == MVT::v8i16 ||
1620
0
      LocVT == MVT::v4i32 ||
1621
0
      LocVT == MVT::v2i64 ||
1622
0
      LocVT == MVT::v4f32 ||
1623
0
      LocVT == MVT::v2f64) {
1624
0
    unsigned Offset8 = State.AllocateStack(16, 16);
1625
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
1626
0
    return false;
1627
0
  }
1628
0
1629
0
  if (LocVT == MVT::v32i8 ||
1630
0
      LocVT == MVT::v16i16 ||
1631
0
      LocVT == MVT::v8i32 ||
1632
0
      LocVT == MVT::v4i64 ||
1633
0
      LocVT == MVT::v8f32 ||
1634
0
      LocVT == MVT::v4f64) {
1635
0
    unsigned Offset9 = State.AllocateStack(32, 32);
1636
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
1637
0
    return false;
1638
0
  }
1639
0
1640
0
  if (LocVT == MVT::v16i32 ||
1641
0
      LocVT == MVT::v8i64 ||
1642
0
      LocVT == MVT::v16f32 ||
1643
0
      LocVT == MVT::v8f64) {
1644
0
    unsigned Offset10 = State.AllocateStack(64, 64);
1645
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
1646
0
    return false;
1647
0
  }
1648
0
1649
0
  return true;  // CC didn't match.
1650
0
}
X86FastISel.cpp:CC_X86_64_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1383
600
                        ISD::ArgFlagsTy ArgFlags, CCState &State) {
1384
600
1385
600
  if (ArgFlags.isByVal()) {
1386
5
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
1387
5
    return false;
1388
5
  }
1389
595
1390
595
  if (LocVT == MVT::i1 ||
1391
595
      LocVT == MVT::i8 ||
1392
595
      
LocVT == MVT::i16591
||
1393
595
      
LocVT == MVT::v1i1586
) {
1394
9
    LocVT = MVT::i32;
1395
9
    if (ArgFlags.isSExt())
1396
0
        LocInfo = CCValAssign::SExt;
1397
9
    else if (ArgFlags.isZExt())
1398
5
        LocInfo = CCValAssign::ZExt;
1399
4
    else
1400
4
        LocInfo = CCValAssign::AExt;
1401
9
  }
1402
595
1403
595
  if (ArgFlags.isNest()) {
1404
1
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTarget64BitILP32()) {
1405
0
      if (unsigned Reg = State.AllocateReg(X86::R10D)) {
1406
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1407
0
        return false;
1408
0
      }
1409
595
    }
1410
1
  }
1411
595
1412
595
  if (ArgFlags.isNest()) {
1413
1
    if (unsigned Reg = State.AllocateReg(X86::R10)) {
1414
1
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1415
1
      return false;
1416
1
    }
1417
594
  }
1418
594
1419
594
  if (ArgFlags.isSwiftSelf()) {
1420
3
    if (LocVT == MVT::i64) {
1421
3
      if (unsigned Reg = State.AllocateReg(X86::R13)) {
1422
3
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1423
3
        return false;
1424
3
      }
1425
591
    }
1426
3
  }
1427
591
1428
591
  if (ArgFlags.isSwiftError()) {
1429
0
    if (LocVT == MVT::i64) {
1430
0
      if (unsigned Reg = State.AllocateReg(X86::R12)) {
1431
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1432
0
        return false;
1433
0
      }
1434
591
    }
1435
0
  }
1436
591
1437
591
  if (State.getCallingConv() == CallingConv::Swift) {
1438
3
    if (ArgFlags.isSRet()) {
1439
0
      if (LocVT == MVT::i64) {
1440
0
        if (unsigned Reg = State.AllocateReg(X86::RAX)) {
1441
0
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1442
0
          return false;
1443
0
        }
1444
591
      }
1445
0
    }
1446
3
  }
1447
591
1448
591
  if (LocVT == MVT::i32) {
1449
259
    static const MCPhysReg RegList1[] = {
1450
259
      X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1451
259
    };
1452
259
    if (unsigned Reg = State.AllocateReg(RegList1)) {
1453
250
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1454
250
      return false;
1455
250
    }
1456
341
  }
1457
341
1458
341
  if (LocVT == MVT::i64) {
1459
316
    static const MCPhysReg RegList2[] = {
1460
316
      X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1461
316
    };
1462
316
    if (unsigned Reg = State.AllocateReg(RegList2)) {
1463
304
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1464
304
      return false;
1465
304
    }
1466
37
  }
1467
37
1468
37
  if (LocVT == MVT::x86mmx) {
1469
1
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()) {
1470
1
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
1471
1
        LocVT = MVT::v2i64;
1472
1
        if (ArgFlags.isSExt())
1473
0
                LocInfo = CCValAssign::SExt;
1474
1
        else if (ArgFlags.isZExt())
1475
0
                LocInfo = CCValAssign::ZExt;
1476
1
        else
1477
1
                LocInfo = CCValAssign::AExt;
1478
1
      }
1479
1
    }
1480
1
  }
1481
37
1482
37
  if (LocVT == MVT::v2i1) {
1483
0
    LocVT = MVT::v2i64;
1484
0
    if (ArgFlags.isSExt())
1485
0
        LocInfo = CCValAssign::SExt;
1486
0
    else if (ArgFlags.isZExt())
1487
0
        LocInfo = CCValAssign::ZExt;
1488
0
    else
1489
0
        LocInfo = CCValAssign::AExt;
1490
0
  }
1491
37
1492
37
  if (LocVT == MVT::v4i1) {
1493
0
    LocVT = MVT::v4i32;
1494
0
    if (ArgFlags.isSExt())
1495
0
        LocInfo = CCValAssign::SExt;
1496
0
    else if (ArgFlags.isZExt())
1497
0
        LocInfo = CCValAssign::ZExt;
1498
0
    else
1499
0
        LocInfo = CCValAssign::AExt;
1500
0
  }
1501
37
1502
37
  if (LocVT == MVT::v8i1) {
1503
0
    LocVT = MVT::v8i16;
1504
0
    if (ArgFlags.isSExt())
1505
0
        LocInfo = CCValAssign::SExt;
1506
0
    else if (ArgFlags.isZExt())
1507
0
        LocInfo = CCValAssign::ZExt;
1508
0
    else
1509
0
        LocInfo = CCValAssign::AExt;
1510
0
  }
1511
37
1512
37
  if (LocVT == MVT::v16i1) {
1513
0
    LocVT = MVT::v16i8;
1514
0
    if (ArgFlags.isSExt())
1515
0
        LocInfo = CCValAssign::SExt;
1516
0
    else if (ArgFlags.isZExt())
1517
0
        LocInfo = CCValAssign::ZExt;
1518
0
    else
1519
0
        LocInfo = CCValAssign::AExt;
1520
0
  }
1521
37
1522
37
  if (LocVT == MVT::v32i1) {
1523
0
    LocVT = MVT::v32i8;
1524
0
    if (ArgFlags.isSExt())
1525
0
        LocInfo = CCValAssign::SExt;
1526
0
    else if (ArgFlags.isZExt())
1527
0
        LocInfo = CCValAssign::ZExt;
1528
0
    else
1529
0
        LocInfo = CCValAssign::AExt;
1530
0
  }
1531
37
1532
37
  if (LocVT == MVT::v64i1) {
1533
0
    LocVT = MVT::v64i8;
1534
0
    if (ArgFlags.isSExt())
1535
0
        LocInfo = CCValAssign::SExt;
1536
0
    else if (ArgFlags.isZExt())
1537
0
        LocInfo = CCValAssign::ZExt;
1538
0
    else
1539
0
        LocInfo = CCValAssign::AExt;
1540
0
  }
1541
37
1542
37
  if (LocVT == MVT::f32 ||
1543
37
      
LocVT == MVT::f6436
||
1544
37
      
LocVT == MVT::f12825
||
1545
37
      
LocVT == MVT::v16i825
||
1546
37
      
LocVT == MVT::v8i1625
||
1547
37
      
LocVT == MVT::v4i3225
||
1548
37
      
LocVT == MVT::v2i6425
||
1549
37
      
LocVT == MVT::v4f3224
||
1550
37
      
LocVT == MVT::v2f6424
) {
1551
13
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1552
13
      static const MCPhysReg RegList3[] = {
1553
13
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1554
13
      };
1555
13
      if (unsigned Reg = State.AllocateReg(RegList3)) {
1556
13
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1557
13
        return false;
1558
13
      }
1559
24
    }
1560
13
  }
1561
24
1562
24
  if (!State.isVarArg()) {
1563
24
    if (LocVT == MVT::v32i8 ||
1564
24
        LocVT == MVT::v16i16 ||
1565
24
        LocVT == MVT::v8i32 ||
1566
24
        LocVT == MVT::v4i64 ||
1567
24
        
LocVT == MVT::v8f3223
||
1568
24
        
LocVT == MVT::v4f6422
) {
1569
3
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1570
3
        static const MCPhysReg RegList4[] = {
1571
3
          X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
1572
3
        };
1573
3
        if (unsigned Reg = State.AllocateReg(RegList4)) {
1574
3
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1575
3
          return false;
1576
3
        }
1577
21
      }
1578
3
    }
1579
24
  }
1580
21
1581
21
  if (!State.isVarArg()) {
1582
21
    if (LocVT == MVT::v64i8 ||
1583
21
        LocVT == MVT::v32i16 ||
1584
21
        LocVT == MVT::v16i32 ||
1585
21
        LocVT == MVT::v8i64 ||
1586
21
        LocVT == MVT::v16f32 ||
1587
21
        LocVT == MVT::v8f64) {
1588
0
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
1589
0
        static const MCPhysReg RegList5[] = {
1590
0
          X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
1591
0
        };
1592
0
        if (unsigned Reg = State.AllocateReg(RegList5)) {
1593
0
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1594
0
          return false;
1595
0
        }
1596
21
      }
1597
0
    }
1598
21
  }
1599
21
1600
21
  if (LocVT == MVT::i32 ||
1601
21
      
LocVT == MVT::i6412
||
1602
21
      
LocVT == MVT::f320
||
1603
21
      
LocVT == MVT::f640
) {
1604
21
    unsigned Offset6 = State.AllocateStack(8, 8);
1605
21
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
1606
21
    return false;
1607
21
  }
1608
0
1609
0
  if (LocVT == MVT::f80 ||
1610
0
      LocVT == MVT::f128) {
1611
0
    unsigned Offset7 = State.AllocateStack(
1612
0
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 
1613
0
      State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
1614
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
1615
0
    return false;
1616
0
  }
1617
0
1618
0
  if (LocVT == MVT::v16i8 ||
1619
0
      LocVT == MVT::v8i16 ||
1620
0
      LocVT == MVT::v4i32 ||
1621
0
      LocVT == MVT::v2i64 ||
1622
0
      LocVT == MVT::v4f32 ||
1623
0
      LocVT == MVT::v2f64) {
1624
0
    unsigned Offset8 = State.AllocateStack(16, 16);
1625
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
1626
0
    return false;
1627
0
  }
1628
0
1629
0
  if (LocVT == MVT::v32i8 ||
1630
0
      LocVT == MVT::v16i16 ||
1631
0
      LocVT == MVT::v8i32 ||
1632
0
      LocVT == MVT::v4i64 ||
1633
0
      LocVT == MVT::v8f32 ||
1634
0
      LocVT == MVT::v4f64) {
1635
0
    unsigned Offset9 = State.AllocateStack(32, 32);
1636
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
1637
0
    return false;
1638
0
  }
1639
0
1640
0
  if (LocVT == MVT::v16i32 ||
1641
0
      LocVT == MVT::v8i64 ||
1642
0
      LocVT == MVT::v16f32 ||
1643
0
      LocVT == MVT::v8f64) {
1644
0
    unsigned Offset10 = State.AllocateStack(64, 64);
1645
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
1646
0
    return false;
1647
0
  }
1648
0
1649
0
  return true;  // CC didn't match.
1650
0
}
X86ISelLowering.cpp:CC_X86_64_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1383
478k
                        ISD::ArgFlagsTy ArgFlags, CCState &State) {
1384
478k
1385
478k
  if (ArgFlags.isByVal()) {
1386
506
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
1387
506
    return false;
1388
506
  }
1389
478k
1390
478k
  if (LocVT == MVT::i1 ||
1391
478k
      LocVT == MVT::i8 ||
1392
478k
      
LocVT == MVT::i16456k
||
1393
478k
      
LocVT == MVT::v1i1452k
) {
1394
25.5k
    LocVT = MVT::i32;
1395
25.5k
    if (ArgFlags.isSExt())
1396
383
        LocInfo = CCValAssign::SExt;
1397
25.1k
    else if (ArgFlags.isZExt())
1398
16.7k
        LocInfo = CCValAssign::ZExt;
1399
8.39k
    else
1400
8.39k
        LocInfo = CCValAssign::AExt;
1401
25.5k
  }
1402
478k
1403
478k
  if (ArgFlags.isNest()) {
1404
20
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTarget64BitILP32()) {
1405
2
      if (unsigned Reg = State.AllocateReg(X86::R10D)) {
1406
2
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1407
2
        return false;
1408
2
      }
1409
478k
    }
1410
20
  }
1411
478k
1412
478k
  if (ArgFlags.isNest()) {
1413
18
    if (unsigned Reg = State.AllocateReg(X86::R10)) {
1414
18
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1415
18
      return false;
1416
18
    }
1417
478k
  }
1418
478k
1419
478k
  if (ArgFlags.isSwiftSelf()) {
1420
37
    if (LocVT == MVT::i64) {
1421
37
      if (unsigned Reg = State.AllocateReg(X86::R13)) {
1422
37
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1423
37
        return false;
1424
37
      }
1425
478k
    }
1426
37
  }
1427
478k
1428
478k
  if (ArgFlags.isSwiftError()) {
1429
74
    if (LocVT == MVT::i64) {
1430
74
      if (unsigned Reg = State.AllocateReg(X86::R12)) {
1431
74
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1432
74
        return false;
1433
74
      }
1434
478k
    }
1435
74
  }
1436
478k
1437
478k
  if (State.getCallingConv() == CallingConv::Swift) {
1438
131
    if (ArgFlags.isSRet()) {
1439
6
      if (LocVT == MVT::i64) {
1440
6
        if (unsigned Reg = State.AllocateReg(X86::RAX)) {
1441
6
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1442
6
          return false;
1443
6
        }
1444
478k
      }
1445
6
    }
1446
131
  }
1447
478k
1448
478k
  if (LocVT == MVT::i32) {
1449
67.3k
    static const MCPhysReg RegList1[] = {
1450
67.3k
      X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1451
67.3k
    };
1452
67.3k
    if (unsigned Reg = State.AllocateReg(RegList1)) {
1453
58.3k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1454
58.3k
      return false;
1455
58.3k
    }
1456
419k
  }
1457
419k
1458
419k
  if (LocVT == MVT::i64) {
1459
299k
    static const MCPhysReg RegList2[] = {
1460
299k
      X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1461
299k
    };
1462
299k
    if (unsigned Reg = State.AllocateReg(RegList2)) {
1463
293k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1464
293k
      return false;
1465
293k
    }
1466
126k
  }
1467
126k
1468
126k
  if (LocVT == MVT::x86mmx) {
1469
1.85k
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()) {
1470
11
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
1471
11
        LocVT = MVT::v2i64;
1472
11
        if (ArgFlags.isSExt())
1473
0
                LocInfo = CCValAssign::SExt;
1474
11
        else if (ArgFlags.isZExt())
1475
0
                LocInfo = CCValAssign::ZExt;
1476
11
        else
1477
11
                LocInfo = CCValAssign::AExt;
1478
11
      }
1479
11
    }
1480
1.85k
  }
1481
126k
1482
126k
  if (LocVT == MVT::v2i1) {
1483
121
    LocVT = MVT::v2i64;
1484
121
    if (ArgFlags.isSExt())
1485
0
        LocInfo = CCValAssign::SExt;
1486
121
    else if (ArgFlags.isZExt())
1487
0
        LocInfo = CCValAssign::ZExt;
1488
121
    else
1489
121
        LocInfo = CCValAssign::AExt;
1490
121
  }
1491
126k
1492
126k
  if (LocVT == MVT::v4i1) {
1493
145
    LocVT = MVT::v4i32;
1494
145
    if (ArgFlags.isSExt())
1495
0
        LocInfo = CCValAssign::SExt;
1496
145
    else if (ArgFlags.isZExt())
1497
0
        LocInfo = CCValAssign::ZExt;
1498
145
    else
1499
145
        LocInfo = CCValAssign::AExt;
1500
145
  }
1501
126k
1502
126k
  if (LocVT == MVT::v8i1) {
1503
152
    LocVT = MVT::v8i16;
1504
152
    if (ArgFlags.isSExt())
1505
0
        LocInfo = CCValAssign::SExt;
1506
152
    else if (ArgFlags.isZExt())
1507
0
        LocInfo = CCValAssign::ZExt;
1508
152
    else
1509
152
        LocInfo = CCValAssign::AExt;
1510
152
  }
1511
126k
1512
126k
  if (LocVT == MVT::v16i1) {
1513
188
    LocVT = MVT::v16i8;
1514
188
    if (ArgFlags.isSExt())
1515
0
        LocInfo = CCValAssign::SExt;
1516
188
    else if (ArgFlags.isZExt())
1517
0
        LocInfo = CCValAssign::ZExt;
1518
188
    else
1519
188
        LocInfo = CCValAssign::AExt;
1520
188
  }
1521
126k
1522
126k
  if (LocVT == MVT::v32i1) {
1523
36
    LocVT = MVT::v32i8;
1524
36
    if (ArgFlags.isSExt())
1525
0
        LocInfo = CCValAssign::SExt;
1526
36
    else if (ArgFlags.isZExt())
1527
0
        LocInfo = CCValAssign::ZExt;
1528
36
    else
1529
36
        LocInfo = CCValAssign::AExt;
1530
36
  }
1531
126k
1532
126k
  if (LocVT == MVT::v64i1) {
1533
9
    LocVT = MVT::v64i8;
1534
9
    if (ArgFlags.isSExt())
1535
0
        LocInfo = CCValAssign::SExt;
1536
9
    else if (ArgFlags.isZExt())
1537
0
        LocInfo = CCValAssign::ZExt;
1538
9
    else
1539
9
        LocInfo = CCValAssign::AExt;
1540
9
  }
1541
126k
1542
126k
  if (LocVT == MVT::f32 ||
1543
126k
      
LocVT == MVT::f64123k
||
1544
126k
      
LocVT == MVT::f128120k
||
1545
126k
      
LocVT == MVT::v16i8119k
||
1546
126k
      
LocVT == MVT::v8i16112k
||
1547
126k
      
LocVT == MVT::v4i32103k
||
1548
126k
      
LocVT == MVT::v2i6492.7k
||
1549
126k
      
LocVT == MVT::v4f3281.6k
||
1550
126k
      
LocVT == MVT::v2f6471.2k
) {
1551
62.9k
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1552
62.9k
      static const MCPhysReg RegList3[] = {
1553
62.9k
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1554
62.9k
      };
1555
62.9k
      if (unsigned Reg = State.AllocateReg(RegList3)) {
1556
61.0k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1557
61.0k
        return false;
1558
61.0k
      }
1559
65.7k
    }
1560
62.9k
  }
1561
65.7k
1562
65.7k
  if (!State.isVarArg()) {
1563
64.8k
    if (LocVT == MVT::v32i8 ||
1564
64.8k
        
LocVT == MVT::v16i1660.3k
||
1565
64.8k
        
LocVT == MVT::v8i3254.7k
||
1566
64.8k
        
LocVT == MVT::v4i6449.4k
||
1567
64.8k
        
LocVT == MVT::v8f3243.8k
||
1568
64.8k
        
LocVT == MVT::v4f6438.2k
) {
1569
31.4k
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1570
31.4k
        static const MCPhysReg RegList4[] = {
1571
31.4k
          X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
1572
31.4k
        };
1573
31.4k
        if (unsigned Reg = State.AllocateReg(RegList4)) {
1574
31.3k
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1575
31.3k
          return false;
1576
31.3k
        }
1577
34.3k
      }
1578
31.4k
    }
1579
64.8k
  }
1580
34.3k
1581
34.3k
  if (!State.isVarArg()) {
1582
33.5k
    if (LocVT == MVT::v64i8 ||
1583
33.5k
        
LocVT == MVT::v32i1632.7k
||
1584
33.5k
        
LocVT == MVT::v16i3231.5k
||
1585
33.5k
        
LocVT == MVT::v8i6428.6k
||
1586
33.5k
        
LocVT == MVT::v16f3224.8k
||
1587
33.5k
        
LocVT == MVT::v8f6421.7k
) {
1588
14.5k
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
1589
14.5k
        static const MCPhysReg RegList5[] = {
1590
14.5k
          X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
1591
14.5k
        };
1592
14.5k
        if (unsigned Reg = State.AllocateReg(RegList5)) {
1593
14.5k
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1594
14.5k
          return false;
1595
14.5k
        }
1596
19.8k
      }
1597
14.5k
    }
1598
33.5k
  }
1599
19.8k
1600
19.8k
  if (LocVT == MVT::i32 ||
1601
19.8k
      
LocVT == MVT::i6410.8k
||
1602
19.8k
      
LocVT == MVT::f324.45k
||
1603
19.8k
      
LocVT == MVT::f644.40k
) {
1604
15.4k
    unsigned Offset6 = State.AllocateStack(8, 8);
1605
15.4k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
1606
15.4k
    return false;
1607
15.4k
  }
1608
4.40k
1609
4.40k
  if (LocVT == MVT::f80 ||
1610
4.40k
      
LocVT == MVT::f1283.82k
) {
1611
699
    unsigned Offset7 = State.AllocateStack(
1612
699
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 
1613
699
      State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
1614
699
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
1615
699
    return false;
1616
699
  }
1617
3.70k
1618
3.70k
  if (LocVT == MVT::v16i8 ||
1619
3.70k
      
LocVT == MVT::v8i163.59k
||
1620
3.70k
      
LocVT == MVT::v4i323.53k
||
1621
3.70k
      
LocVT == MVT::v2i643.46k
||
1622
3.70k
      
LocVT == MVT::v4f322.12k
||
1623
3.70k
      
LocVT == MVT::v2f642.08k
) {
1624
1.71k
    unsigned Offset8 = State.AllocateStack(16, 16);
1625
1.71k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
1626
1.71k
    return false;
1627
1.71k
  }
1628
1.98k
1629
1.98k
  if (LocVT == MVT::v32i8 ||
1630
1.98k
      
LocVT == MVT::v16i161.91k
||
1631
1.98k
      
LocVT == MVT::v8i321.91k
||
1632
1.98k
      
LocVT == MVT::v4i641.91k
||
1633
1.98k
      
LocVT == MVT::v8f321.87k
||
1634
1.98k
      
LocVT == MVT::v4f641.87k
) {
1635
129
    unsigned Offset9 = State.AllocateStack(32, 32);
1636
129
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
1637
129
    return false;
1638
129
  }
1639
1.85k
1640
1.85k
  if (LocVT == MVT::v16i32 ||
1641
1.85k
      LocVT == MVT::v8i64 ||
1642
1.85k
      LocVT == MVT::v16f32 ||
1643
1.85k
      LocVT == MVT::v8f64) {
1644
0
    unsigned Offset10 = State.AllocateStack(64, 64);
1645
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
1646
0
    return false;
1647
0
  }
1648
1.85k
1649
1.85k
  return true;  // CC didn't match.
1650
1.85k
}
1651
1652
1653
static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT,
1654
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
1655
62
                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
1656
62
1657
62
  if (LocVT == MVT::i8 ||
1658
62
      LocVT == MVT::i16 ||
1659
62
      LocVT == MVT::i32) {
1660
0
    LocVT = MVT::i64;
1661
0
    if (ArgFlags.isSExt())
1662
0
        LocInfo = CCValAssign::SExt;
1663
0
    else if (ArgFlags.isZExt())
1664
0
        LocInfo = CCValAssign::ZExt;
1665
0
    else
1666
0
        LocInfo = CCValAssign::AExt;
1667
0
  }
1668
62
1669
62
  if (LocVT == MVT::i64) {
1670
56
    static const MCPhysReg RegList1[] = {
1671
56
      X86::R13, X86::RBP, X86::R12, X86::RBX, X86::R14, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R15
1672
56
    };
1673
56
    if (unsigned Reg = State.AllocateReg(RegList1)) {
1674
56
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1675
56
      return false;
1676
56
    }
1677
6
  }
1678
6
1679
6
  if (LocVT == MVT::f32 ||
1680
6
      
LocVT == MVT::f642
||
1681
6
      
LocVT == MVT::v16i80
||
1682
6
      
LocVT == MVT::v8i160
||
1683
6
      
LocVT == MVT::v4i320
||
1684
6
      
LocVT == MVT::v2i640
||
1685
6
      
LocVT == MVT::v4f320
||
1686
6
      
LocVT == MVT::v2f640
) {
1687
6
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1688
6
      static const MCPhysReg RegList2[] = {
1689
6
        X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6
1690
6
      };
1691
6
      if (unsigned Reg = State.AllocateReg(RegList2)) {
1692
6
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1693
6
        return false;
1694
6
      }
1695
0
    }
1696
6
  }
1697
0
1698
0
  if (LocVT == MVT::v32i8 ||
1699
0
      LocVT == MVT::v16i16 ||
1700
0
      LocVT == MVT::v8i32 ||
1701
0
      LocVT == MVT::v4i64 ||
1702
0
      LocVT == MVT::v8f32 ||
1703
0
      LocVT == MVT::v4f64) {
1704
0
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1705
0
      static const MCPhysReg RegList3[] = {
1706
0
        X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6
1707
0
      };
1708
0
      if (unsigned Reg = State.AllocateReg(RegList3)) {
1709
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1710
0
        return false;
1711
0
      }
1712
0
    }
1713
0
  }
1714
0
1715
0
  if (LocVT == MVT::v64i8 ||
1716
0
      LocVT == MVT::v32i16 ||
1717
0
      LocVT == MVT::v16i32 ||
1718
0
      LocVT == MVT::v8i64 ||
1719
0
      LocVT == MVT::v16f32 ||
1720
0
      LocVT == MVT::v8f64) {
1721
0
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
1722
0
      static const MCPhysReg RegList4[] = {
1723
0
        X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6
1724
0
      };
1725
0
      if (unsigned Reg = State.AllocateReg(RegList4)) {
1726
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1727
0
        return false;
1728
0
      }
1729
0
    }
1730
0
  }
1731
0
1732
0
  return true;  // CC didn't match.
1733
0
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_64_GHC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86FastISel.cpp:CC_X86_64_GHC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:CC_X86_64_GHC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1655
62
                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
1656
62
1657
62
  if (LocVT == MVT::i8 ||
1658
62
      LocVT == MVT::i16 ||
1659
62
      LocVT == MVT::i32) {
1660
0
    LocVT = MVT::i64;
1661
0
    if (ArgFlags.isSExt())
1662
0
        LocInfo = CCValAssign::SExt;
1663
0
    else if (ArgFlags.isZExt())
1664
0
        LocInfo = CCValAssign::ZExt;
1665
0
    else
1666
0
        LocInfo = CCValAssign::AExt;
1667
0
  }
1668
62
1669
62
  if (LocVT == MVT::i64) {
1670
56
    static const MCPhysReg RegList1[] = {
1671
56
      X86::R13, X86::RBP, X86::R12, X86::RBX, X86::R14, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R15
1672
56
    };
1673
56
    if (unsigned Reg = State.AllocateReg(RegList1)) {
1674
56
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1675
56
      return false;
1676
56
    }
1677
6
  }
1678
6
1679
6
  if (LocVT == MVT::f32 ||
1680
6
      
LocVT == MVT::f642
||
1681
6
      
LocVT == MVT::v16i80
||
1682
6
      
LocVT == MVT::v8i160
||
1683
6
      
LocVT == MVT::v4i320
||
1684
6
      
LocVT == MVT::v2i640
||
1685
6
      
LocVT == MVT::v4f320
||
1686
6
      
LocVT == MVT::v2f640
) {
1687
6
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1688
6
      static const MCPhysReg RegList2[] = {
1689
6
        X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6
1690
6
      };
1691
6
      if (unsigned Reg = State.AllocateReg(RegList2)) {
1692
6
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1693
6
        return false;
1694
6
      }
1695
0
    }
1696
6
  }
1697
0
1698
0
  if (LocVT == MVT::v32i8 ||
1699
0
      LocVT == MVT::v16i16 ||
1700
0
      LocVT == MVT::v8i32 ||
1701
0
      LocVT == MVT::v4i64 ||
1702
0
      LocVT == MVT::v8f32 ||
1703
0
      LocVT == MVT::v4f64) {
1704
0
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1705
0
      static const MCPhysReg RegList3[] = {
1706
0
        X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6
1707
0
      };
1708
0
      if (unsigned Reg = State.AllocateReg(RegList3)) {
1709
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1710
0
        return false;
1711
0
      }
1712
0
    }
1713
0
  }
1714
0
1715
0
  if (LocVT == MVT::v64i8 ||
1716
0
      LocVT == MVT::v32i16 ||
1717
0
      LocVT == MVT::v16i32 ||
1718
0
      LocVT == MVT::v8i64 ||
1719
0
      LocVT == MVT::v16f32 ||
1720
0
      LocVT == MVT::v8f64) {
1721
0
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
1722
0
      static const MCPhysReg RegList4[] = {
1723
0
        X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6
1724
0
      };
1725
0
      if (unsigned Reg = State.AllocateReg(RegList4)) {
1726
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1727
0
        return false;
1728
0
      }
1729
0
    }
1730
0
  }
1731
0
1732
0
  return true;  // CC didn't match.
1733
0
}
1734
1735
1736
static bool CC_X86_64_HHVM(unsigned ValNo, MVT ValVT,
1737
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
1738
112
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
1739
112
1740
112
  if (LocVT == MVT::i64) {
1741
112
    static const MCPhysReg RegList1[] = {
1742
112
      X86::RBX, X86::R12, X86::RBP, X86::R15, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9, X86::RAX, X86::R10, X86::R11, X86::R13, X86::R14
1743
112
    };
1744
112
    if (unsigned Reg = State.AllocateReg(RegList1)) {
1745
112
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1746
112
      return false;
1747
112
    }
1748
0
  }
1749
0
1750
0
  return true;  // CC didn't match.
1751
0
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_64_HHVM(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86FastISel.cpp:CC_X86_64_HHVM(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:CC_X86_64_HHVM(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1738
112
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
1739
112
1740
112
  if (LocVT == MVT::i64) {
1741
112
    static const MCPhysReg RegList1[] = {
1742
112
      X86::RBX, X86::R12, X86::RBP, X86::R15, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9, X86::RAX, X86::R10, X86::R11, X86::R13, X86::R14
1743
112
    };
1744
112
    if (unsigned Reg = State.AllocateReg(RegList1)) {
1745
112
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1746
112
      return false;
1747
112
    }
1748
0
  }
1749
0
1750
0
  return true;  // CC didn't match.
1751
0
}
1752
1753
1754
static bool CC_X86_64_HHVM_C(unsigned ValNo, MVT ValVT,
1755
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
1756
25
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
1757
25
1758
25
  if (LocVT == MVT::i64) {
1759
24
    if (unsigned Reg = State.AllocateReg(X86::RBP)) {
1760
5
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1761
5
      return false;
1762
5
    }
1763
20
  }
1764
20
1765
20
  if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1766
20
    return false;
1767
0
1768
0
  return true;  // CC didn't match.
1769
0
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_64_HHVM_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86FastISel.cpp:CC_X86_64_HHVM_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:CC_X86_64_HHVM_C(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1756
25
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
1757
25
1758
25
  if (LocVT == MVT::i64) {
1759
24
    if (unsigned Reg = State.AllocateReg(X86::RBP)) {
1760
5
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1761
5
      return false;
1762
5
    }
1763
20
  }
1764
20
1765
20
  if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1766
20
    return false;
1767
0
1768
0
  return true;  // CC didn't match.
1769
0
}
1770
1771
1772
static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
1773
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
1774
42
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
1775
42
1776
42
  if (LocVT == MVT::i8 ||
1777
42
      LocVT == MVT::i16 ||
1778
42
      LocVT == MVT::i32) {
1779
6
    LocVT = MVT::i64;
1780
6
    if (ArgFlags.isSExt())
1781
0
        LocInfo = CCValAssign::SExt;
1782
6
    else if (ArgFlags.isZExt())
1783
0
        LocInfo = CCValAssign::ZExt;
1784
6
    else
1785
6
        LocInfo = CCValAssign::AExt;
1786
6
  }
1787
42
1788
42
  if (LocVT == MVT::i64) {
1789
42
    static const MCPhysReg RegList1[] = {
1790
42
      X86::R15, X86::RBP, X86::RSI, X86::RDX, X86::RCX, X86::R8
1791
42
    };
1792
42
    if (unsigned Reg = State.AllocateReg(RegList1)) {
1793
41
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1794
41
      return false;
1795
41
    }
1796
1
  }
1797
1
1798
1
  if (LocVT == MVT::i32 ||
1799
1
      LocVT == MVT::i64 ||
1800
1
      
LocVT == MVT::f320
||
1801
1
      
LocVT == MVT::f640
) {
1802
1
    unsigned Offset2 = State.AllocateStack(8, 8);
1803
1
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1804
1
    return false;
1805
1
  }
1806
0
1807
0
  return true;  // CC didn't match.
1808
0
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_64_HiPE(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86FastISel.cpp:CC_X86_64_HiPE(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:CC_X86_64_HiPE(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1774
42
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
1775
42
1776
42
  if (LocVT == MVT::i8 ||
1777
42
      LocVT == MVT::i16 ||
1778
42
      LocVT == MVT::i32) {
1779
6
    LocVT = MVT::i64;
1780
6
    if (ArgFlags.isSExt())
1781
0
        LocInfo = CCValAssign::SExt;
1782
6
    else if (ArgFlags.isZExt())
1783
0
        LocInfo = CCValAssign::ZExt;
1784
6
    else
1785
6
        LocInfo = CCValAssign::AExt;
1786
6
  }
1787
42
1788
42
  if (LocVT == MVT::i64) {
1789
42
    static const MCPhysReg RegList1[] = {
1790
42
      X86::R15, X86::RBP, X86::RSI, X86::RDX, X86::RCX, X86::R8
1791
42
    };
1792
42
    if (unsigned Reg = State.AllocateReg(RegList1)) {
1793
41
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1794
41
      return false;
1795
41
    }
1796
1
  }
1797
1
1798
1
  if (LocVT == MVT::i32 ||
1799
1
      LocVT == MVT::i64 ||
1800
1
      
LocVT == MVT::f320
||
1801
1
      
LocVT == MVT::f640
) {
1802
1
    unsigned Offset2 = State.AllocateStack(8, 8);
1803
1
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1804
1
    return false;
1805
1
  }
1806
0
1807
0
  return true;  // CC didn't match.
1808
0
}
1809
1810
1811
static bool CC_X86_64_Intr(unsigned ValNo, MVT ValVT,
1812
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
1813
20
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
1814
20
1815
20
  unsigned Offset1 = State.AllocateStack(8, 8);
1816
20
  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1817
20
  return false;
1818
20
1819
20
  
return true0
; // CC didn't match.
1820
20
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_64_Intr(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Unexecuted instantiation: X86FastISel.cpp:CC_X86_64_Intr(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86ISelLowering.cpp:CC_X86_64_Intr(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1813
20
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
1814
20
1815
20
  unsigned Offset1 = State.AllocateStack(8, 8);
1816
20
  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1817
20
  return false;
1818
20
1819
20
  
return true0
; // CC didn't match.
1820
20
}
1821
1822
1823
static bool CC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT,
1824
                                MVT LocVT, CCValAssign::LocInfo LocInfo,
1825
69
                                ISD::ArgFlagsTy ArgFlags, CCState &State) {
1826
69
1827
69
  if (LocVT == MVT::i8 ||
1828
69
      LocVT == MVT::i16) {
1829
0
    LocVT = MVT::i32;
1830
0
    if (ArgFlags.isSExt())
1831
0
        LocInfo = CCValAssign::SExt;
1832
0
    else if (ArgFlags.isZExt())
1833
0
        LocInfo = CCValAssign::ZExt;
1834
0
    else
1835
0
        LocInfo = CCValAssign::AExt;
1836
0
  }
1837
69
1838
69
  if (LocVT == MVT::i32) {
1839
26
    if (unsigned Reg = State.AllocateReg(X86::EAX)) {
1840
4
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1841
4
      return false;
1842
4
    }
1843
65
  }
1844
65
1845
65
  if (LocVT == MVT::i64) {
1846
43
    if (unsigned Reg = State.AllocateReg(X86::RAX)) {
1847
9
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1848
9
      return false;
1849
9
    }
1850
56
  }
1851
56
1852
56
  if (LocVT == MVT::i32 ||
1853
56
      
LocVT == MVT::f3234
) {
1854
22
    unsigned Offset1 = State.AllocateStack(4, 4);
1855
22
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1856
22
    return false;
1857
22
  }
1858
34
1859
34
  if (LocVT == MVT::i64 ||
1860
34
      
LocVT == MVT::f640
) {
1861
34
    unsigned Offset2 = State.AllocateStack(8, 8);
1862
34
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1863
34
    return false;
1864
34
  }
1865
0
1866
0
  return true;  // CC didn't match.
1867
0
}
Unexecuted instantiation: X86CallLowering.cpp:CC_X86_64_WebKit_JS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
X86FastISel.cpp:CC_X86_64_WebKit_JS(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)
Line
Count
Source
1825
20
                                ISD::ArgFlagsTy ArgFlags, CCState &State) {
1826
20
1827
20
  if (LocVT == MVT::i8 ||
1828
20
      LocVT == MVT::i16) {
1829
0
    LocVT = MVT::i32;
1830
0
    if (ArgFlags.isSExt())
1831
0
        LocInfo = CCValAssign::SExt;
1832
0
    else if (ArgFlags.isZExt())
1833
0
        <