Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/clang-build/lib/Target/X86/X86GenCallingConv.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Calling Convention Implementation Fragment                                 *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
10
                            MVT LocVT, CCValAssign::LocInfo LocInfo,
11
                            ISD::ArgFlagsTy ArgFlags, CCState &State);
12
bool llvm::CC_X86(unsigned ValNo, MVT ValVT,
13
                  MVT LocVT, CCValAssign::LocInfo LocInfo,
14
                  ISD::ArgFlagsTy ArgFlags, CCState &State);
15
static bool CC_X86_32(unsigned ValNo, MVT ValVT,
16
                      MVT LocVT, CCValAssign::LocInfo LocInfo,
17
                      ISD::ArgFlagsTy ArgFlags, CCState &State);
18
static bool CC_X86_32_C(unsigned ValNo, MVT ValVT,
19
                        MVT LocVT, CCValAssign::LocInfo LocInfo,
20
                        ISD::ArgFlagsTy ArgFlags, CCState &State);
21
static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT,
22
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
23
                             ISD::ArgFlagsTy ArgFlags, CCState &State);
24
static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT,
25
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
26
                             ISD::ArgFlagsTy ArgFlags, CCState &State);
27
static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT,
28
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
29
                               ISD::ArgFlagsTy ArgFlags, CCState &State);
30
static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT,
31
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
32
                          ISD::ArgFlagsTy ArgFlags, CCState &State);
33
static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
34
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
35
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
36
static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT,
37
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
38
                          ISD::ArgFlagsTy ArgFlags, CCState &State);
39
static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
40
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
41
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
42
static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT,
43
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
44
                               ISD::ArgFlagsTy ArgFlags, CCState &State);
45
static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT,
46
                                      MVT LocVT, CCValAssign::LocInfo LocInfo,
47
                                      ISD::ArgFlagsTy ArgFlags, CCState &State);
48
static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT,
49
                                     MVT LocVT, CCValAssign::LocInfo LocInfo,
50
                                     ISD::ArgFlagsTy ArgFlags, CCState &State);
51
static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT,
52
                                   MVT LocVT, CCValAssign::LocInfo LocInfo,
53
                                   ISD::ArgFlagsTy ArgFlags, CCState &State);
54
static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT,
55
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
56
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
57
static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT,
58
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
59
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
60
static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT,
61
                                      MVT LocVT, CCValAssign::LocInfo LocInfo,
62
                                      ISD::ArgFlagsTy ArgFlags, CCState &State);
63
static bool CC_X86_64(unsigned ValNo, MVT ValVT,
64
                      MVT LocVT, CCValAssign::LocInfo LocInfo,
65
                      ISD::ArgFlagsTy ArgFlags, CCState &State);
66
static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
67
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
68
                             ISD::ArgFlagsTy ArgFlags, CCState &State);
69
static bool CC_X86_64_C(unsigned ValNo, MVT ValVT,
70
                        MVT LocVT, CCValAssign::LocInfo LocInfo,
71
                        ISD::ArgFlagsTy ArgFlags, CCState &State);
72
static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT,
73
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
74
                          ISD::ArgFlagsTy ArgFlags, CCState &State);
75
static bool CC_X86_64_HHVM(unsigned ValNo, MVT ValVT,
76
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
77
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
78
static bool CC_X86_64_HHVM_C(unsigned ValNo, MVT ValVT,
79
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
80
                             ISD::ArgFlagsTy ArgFlags, CCState &State);
81
static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
82
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
83
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
84
static bool CC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT,
85
                                MVT LocVT, CCValAssign::LocInfo LocInfo,
86
                                ISD::ArgFlagsTy ArgFlags, CCState &State);
87
static bool CC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
88
                                  MVT LocVT, CCValAssign::LocInfo LocInfo,
89
                                  ISD::ArgFlagsTy ArgFlags, CCState &State);
90
static bool CC_X86_Win32_VectorCall(unsigned ValNo, MVT ValVT,
91
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
92
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
93
static bool CC_X86_Win64_C(unsigned ValNo, MVT ValVT,
94
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
95
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
96
static bool CC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
97
                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
98
                                 ISD::ArgFlagsTy ArgFlags, CCState &State);
99
static bool CC_X86_Win64_VectorCall(unsigned ValNo, MVT ValVT,
100
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
101
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
102
static bool RetCC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
103
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
104
                               ISD::ArgFlagsTy ArgFlags, CCState &State);
105
bool llvm::RetCC_X86(unsigned ValNo, MVT ValVT,
106
                     MVT LocVT, CCValAssign::LocInfo LocInfo,
107
                     ISD::ArgFlagsTy ArgFlags, CCState &State);
108
static bool RetCC_X86Common(unsigned ValNo, MVT ValVT,
109
                            MVT LocVT, CCValAssign::LocInfo LocInfo,
110
                            ISD::ArgFlagsTy ArgFlags, CCState &State);
111
static bool RetCC_X86_32(unsigned ValNo, MVT ValVT,
112
                         MVT LocVT, CCValAssign::LocInfo LocInfo,
113
                         ISD::ArgFlagsTy ArgFlags, CCState &State);
114
static bool RetCC_X86_32_C(unsigned ValNo, MVT ValVT,
115
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
116
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
117
static bool RetCC_X86_32_Fast(unsigned ValNo, MVT ValVT,
118
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
119
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
120
static bool RetCC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
121
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
122
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
123
static bool RetCC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
124
                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
125
                                 ISD::ArgFlagsTy ArgFlags, CCState &State);
126
static bool RetCC_X86_32_VectorCall(unsigned ValNo, MVT ValVT,
127
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
128
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
129
static bool RetCC_X86_64(unsigned ValNo, MVT ValVT,
130
                         MVT LocVT, CCValAssign::LocInfo LocInfo,
131
                         ISD::ArgFlagsTy ArgFlags, CCState &State);
132
static bool RetCC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
133
                                MVT LocVT, CCValAssign::LocInfo LocInfo,
134
                                ISD::ArgFlagsTy ArgFlags, CCState &State);
135
static bool RetCC_X86_64_C(unsigned ValNo, MVT ValVT,
136
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
137
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
138
static bool RetCC_X86_64_HHVM(unsigned ValNo, MVT ValVT,
139
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
140
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
141
static bool RetCC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
142
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
143
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
144
static bool RetCC_X86_64_Swift(unsigned ValNo, MVT ValVT,
145
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
146
                               ISD::ArgFlagsTy ArgFlags, CCState &State);
147
static bool RetCC_X86_64_Vectorcall(unsigned ValNo, MVT ValVT,
148
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
149
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
150
static bool RetCC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT,
151
                                   MVT LocVT, CCValAssign::LocInfo LocInfo,
152
                                   ISD::ArgFlagsTy ArgFlags, CCState &State);
153
static bool RetCC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
154
                                     MVT LocVT, CCValAssign::LocInfo LocInfo,
155
                                     ISD::ArgFlagsTy ArgFlags, CCState &State);
156
static bool RetCC_X86_Win64_C(unsigned ValNo, MVT ValVT,
157
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
158
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
159
static bool RetCC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
160
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
161
                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
162
163
164
static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
165
                            MVT LocVT, CCValAssign::LocInfo LocInfo,
166
238
                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
167
238
168
238
  if (LocVT == MVT::i32) {
169
22
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
170
2
      static const MCPhysReg RegList1[] = {
171
2
        X86::ECX, X86::EDX, X86::R8D, X86::R9D
172
2
      };
173
2
      if (unsigned Reg = State.AllocateReg(RegList1)) {
174
2
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
175
2
        return false;
176
2
      }
177
236
    }
178
22
  }
179
236
180
236
  if (LocVT == MVT::i64) {
181
16
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
182
8
      static const MCPhysReg RegList2[] = {
183
8
        X86::RCX, X86::RDX, X86::R8, X86::R9
184
8
      };
185
8
      if (unsigned Reg = State.AllocateReg(RegList2)) {
186
8
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
187
8
        return false;
188
8
      }
189
228
    }
190
16
  }
191
228
192
228
  if (LocVT == MVT::i32) {
193
20
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
194
2
      static const MCPhysReg RegList3[] = {
195
2
        X86::EDI, X86::ESI, X86::EDX, X86::ECX
196
2
      };
197
2
      if (unsigned Reg = State.AllocateReg(RegList3)) {
198
2
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
199
2
        return false;
200
2
      }
201
226
    }
202
20
  }
203
226
204
226
  if (LocVT == MVT::i64) {
205
8
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
206
8
      static const MCPhysReg RegList4[] = {
207
8
        X86::RDI, X86::RSI, X86::RDX, X86::RCX
208
8
      };
209
8
      if (unsigned Reg = State.AllocateReg(RegList4)) {
210
8
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
211
8
        return false;
212
8
      }
213
218
    }
214
8
  }
215
218
216
218
  if (LocVT == MVT::i32) {
217
18
    unsigned Offset5 = State.AllocateStack(4, 4);
218
18
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
219
18
    return false;
220
18
  }
221
200
222
200
  if (LocVT == MVT::f32 ||
223
200
      LocVT == MVT::f64 ||
224
200
      LocVT == MVT::v4i32 ||
225
200
      LocVT == MVT::v2i64 ||
226
200
      LocVT == MVT::v4f32 ||
227
200
      
LocVT == MVT::v2f64128
) {
228
72
    static const MCPhysReg RegList6[] = {
229
72
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
230
72
    };
231
72
    if (unsigned Reg = State.AllocateReg(RegList6)) {
232
60
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
233
60
      return false;
234
60
    }
235
140
  }
236
140
237
140
  if (LocVT == MVT::v8f32 ||
238
140
      
LocVT == MVT::v4f64108
||
239
140
      
LocVT == MVT::v8i32108
||
240
140
      
LocVT == MVT::v4i64108
) {
241
32
    static const MCPhysReg RegList7[] = {
242
32
      X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
243
32
    };
244
32
    if (unsigned Reg = State.AllocateReg(RegList7)) {
245
32
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
246
32
      return false;
247
32
    }
248
108
  }
249
108
250
108
  if (LocVT == MVT::v16f32 ||
251
108
      
LocVT == MVT::v8f6452
||
252
108
      
LocVT == MVT::v16i3252
||
253
108
      
LocVT == MVT::v8i6436
) {
254
72
    static const MCPhysReg RegList8[] = {
255
72
      X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
256
72
    };
257
72
    if (unsigned Reg = State.AllocateReg(RegList8)) {
258
72
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
259
72
      return false;
260
72
    }
261
36
  }
262
36
263
36
  if (LocVT == MVT::v16i1 ||
264
36
      
LocVT == MVT::v8i112
) {
265
24
    if (unsigned Reg = State.AllocateReg(X86::K1)) {
266
24
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
267
24
      return false;
268
24
    }
269
12
  }
270
12
271
12
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
272
4
    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
273
4
      return false;
274
8
  }
275
8
276
8
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
277
4
    if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
278
4
      return false;
279
4
  }
280
4
281
4
  if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
282
4
    return false;
283
0
284
0
  return true;  // CC didn't match.
285
0
}
286
287
288
bool llvm::CC_X86(unsigned ValNo, MVT ValVT,
289
                  MVT LocVT, CCValAssign::LocInfo LocInfo,
290
597k
                  ISD::ArgFlagsTy ArgFlags, CCState &State) {
291
597k
292
597k
  if (State.getCallingConv() == CallingConv::Intel_OCL_BI) {
293
238
    if (!CC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
294
238
      return false;
295
597k
  }
296
597k
297
597k
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
298
488k
    if (!CC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
299
487k
      return false;
300
109k
  }
301
109k
302
109k
  if (!CC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
303
109k
    return false;
304
18.4E
305
18.4E
  return true;  // CC didn't match.
306
18.4E
}
307
308
309
static bool CC_X86_32(unsigned ValNo, MVT ValVT,
310
                      MVT LocVT, CCValAssign::LocInfo LocInfo,
311
109k
                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
312
109k
313
109k
  if (State.getCallingConv() == CallingConv::X86_INTR) {
314
26
    if (CC_X86_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
315
26
        return false;
316
109k
  }
317
109k
318
109k
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetMCU()) {
319
126
    if (!CC_X86_32_MCU(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
320
126
      return false;
321
109k
  }
322
109k
323
109k
  if (State.getCallingConv() == CallingConv::X86_FastCall) {
324
206
    if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
325
200
      return false;
326
109k
  }
327
109k
328
109k
  if (State.getCallingConv() == CallingConv::X86_VectorCall) {
329
244
    if (!CC_X86_Win32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
330
244
      return false;
331
109k
  }
332
109k
333
109k
  if (State.getCallingConv() == CallingConv::X86_ThisCall) {
334
453
    if (!CC_X86_32_ThisCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
335
453
      return false;
336
108k
  }
337
108k
338
108k
  if (State.getCallingConv() == CallingConv::Fast) {
339
1.94k
    if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
340
1.94k
      return false;
341
106k
  }
342
106k
343
106k
  if (State.getCallingConv() == CallingConv::GHC) {
344
20
    if (!CC_X86_32_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
345
20
      return false;
346
106k
  }
347
106k
348
106k
  if (State.getCallingConv() == CallingConv::HiPE) {
349
42
    if (!CC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
350
42
      return false;
351
106k
  }
352
106k
353
106k
  if (State.getCallingConv() == CallingConv::X86_RegCall) {
354
209
    if (!CC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
355
206
      return false;
356
106k
  }
357
106k
358
106k
  if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
359
106k
    return false;
360
0
361
0
  return true;  // CC didn't match.
362
0
}
363
364
365
static bool CC_X86_32_C(unsigned ValNo, MVT ValVT,
366
                        MVT LocVT, CCValAssign::LocInfo LocInfo,
367
106k
                        ISD::ArgFlagsTy ArgFlags, CCState &State) {
368
106k
369
106k
  if (LocVT == MVT::i1 ||
370
106k
      
LocVT == MVT::i8106k
||
371
106k
      
LocVT == MVT::i1698.7k
||
372
106k
      
LocVT == MVT::v1i196.4k
) {
373
10.1k
    LocVT = MVT::i32;
374
10.1k
    if (ArgFlags.isSExt())
375
88
        LocInfo = CCValAssign::SExt;
376
10.0k
    else if (ArgFlags.isZExt())
377
3.45k
        LocInfo = CCValAssign::ZExt;
378
6.58k
    else
379
6.58k
        LocInfo = CCValAssign::AExt;
380
10.1k
  }
381
106k
382
106k
  if (ArgFlags.isNest()) {
383
16
    if (unsigned Reg = State.AllocateReg(X86::ECX)) {
384
16
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
385
16
      return false;
386
16
    }
387
106k
  }
388
106k
389
106k
  if (!State.isVarArg()) {
390
102k
    if (ArgFlags.isInReg()) {
391
300
      if (LocVT == MVT::i32) {
392
276
        static const MCPhysReg RegList1[] = {
393
276
          X86::EAX, X86::EDX, X86::ECX
394
276
        };
395
276
        if (unsigned Reg = State.AllocateReg(RegList1)) {
396
267
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
397
267
          return false;
398
267
        }
399
106k
      }
400
300
    }
401
102k
  }
402
106k
403
106k
  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
404
106k
    return false;
405
0
406
0
  return true;  // CC didn't match.
407
0
}
408
409
410
static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT,
411
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
412
107k
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
413
107k
414
107k
  if (ArgFlags.isByVal()) {
415
218
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
416
218
    return false;
417
218
  }
418
106k
419
106k
  if (!State.isVarArg()) {
420
102k
    if (ArgFlags.isInReg()) {
421
62
      if (LocVT == MVT::f32 ||
422
62
          
LocVT == MVT::f6458
) {
423
8
        if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
424
0
          static const MCPhysReg RegList1[] = {
425
0
            X86::XMM0, X86::XMM1, X86::XMM2
426
0
          };
427
0
          if (unsigned Reg = State.AllocateReg(RegList1)) {
428
0
            State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
429
0
            return false;
430
0
          }
431
106k
        }
432
8
      }
433
62
    }
434
102k
  }
435
106k
436
106k
  if (!State.isVarArg()) {
437
102k
    if (LocVT == MVT::x86mmx) {
438
227
      static const MCPhysReg RegList2[] = {
439
227
        X86::MM0, X86::MM1, X86::MM2
440
227
      };
441
227
      if (unsigned Reg = State.AllocateReg(RegList2)) {
442
227
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
443
227
        return false;
444
227
      }
445
106k
    }
446
102k
  }
447
106k
448
106k
  if (LocVT == MVT::i32 ||
449
106k
      
LocVT == MVT::f3224.0k
) {
450
83.9k
    unsigned Offset3 = State.AllocateStack(4, 4);
451
83.9k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
452
83.9k
    return false;
453
83.9k
  }
454
22.6k
455
22.6k
  if (LocVT == MVT::f64) {
456
1.01k
    unsigned Offset4 = State.AllocateStack(8, 4);
457
1.01k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
458
1.01k
    return false;
459
1.01k
  }
460
21.6k
461
21.6k
  if (LocVT == MVT::f80) {
462
233
    unsigned Offset5 = State.AllocateStack(
463
233
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 4);
464
233
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
465
233
    return false;
466
233
  }
467
21.4k
468
21.4k
  if (LocVT == MVT::v2i1) {
469
22
    LocVT = MVT::v2i64;
470
22
    if (ArgFlags.isSExt())
471
0
        LocInfo = CCValAssign::SExt;
472
22
    else if (ArgFlags.isZExt())
473
0
        LocInfo = CCValAssign::ZExt;
474
22
    else
475
22
        LocInfo = CCValAssign::AExt;
476
22
  }
477
21.4k
478
21.4k
  if (LocVT == MVT::v4i1) {
479
24
    LocVT = MVT::v4i32;
480
24
    if (ArgFlags.isSExt())
481
0
        LocInfo = CCValAssign::SExt;
482
24
    else if (ArgFlags.isZExt())
483
0
        LocInfo = CCValAssign::ZExt;
484
24
    else
485
24
        LocInfo = CCValAssign::AExt;
486
24
  }
487
21.4k
488
21.4k
  if (LocVT == MVT::v8i1) {
489
17
    LocVT = MVT::v8i16;
490
17
    if (ArgFlags.isSExt())
491
0
        LocInfo = CCValAssign::SExt;
492
17
    else if (ArgFlags.isZExt())
493
0
        LocInfo = CCValAssign::ZExt;
494
17
    else
495
17
        LocInfo = CCValAssign::AExt;
496
17
  }
497
21.4k
498
21.4k
  if (LocVT == MVT::v16i1) {
499
33
    LocVT = MVT::v16i8;
500
33
    if (ArgFlags.isSExt())
501
0
        LocInfo = CCValAssign::SExt;
502
33
    else if (ArgFlags.isZExt())
503
0
        LocInfo = CCValAssign::ZExt;
504
33
    else
505
33
        LocInfo = CCValAssign::AExt;
506
33
  }
507
21.4k
508
21.4k
  if (LocVT == MVT::v32i1) {
509
5
    LocVT = MVT::v32i8;
510
5
    if (ArgFlags.isSExt())
511
0
        LocInfo = CCValAssign::SExt;
512
5
    else if (ArgFlags.isZExt())
513
0
        LocInfo = CCValAssign::ZExt;
514
5
    else
515
5
        LocInfo = CCValAssign::AExt;
516
5
  }
517
21.4k
518
21.4k
  if (LocVT == MVT::v64i1) {
519
1
    LocVT = MVT::v64i8;
520
1
    if (ArgFlags.isSExt())
521
0
        LocInfo = CCValAssign::SExt;
522
1
    else if (ArgFlags.isZExt())
523
0
        LocInfo = CCValAssign::ZExt;
524
1
    else
525
1
        LocInfo = CCValAssign::AExt;
526
1
  }
527
21.4k
528
21.4k
  if (LocVT == MVT::x86mmx) {
529
0
    unsigned Offset6 = State.AllocateStack(8, 4);
530
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
531
0
    return false;
532
0
  }
533
21.4k
534
21.4k
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()) {
535
4.07k
    if (!CC_X86_32_Vector_Darwin(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
536
4.07k
      return false;
537
17.3k
  }
538
17.3k
539
17.3k
  if (!CC_X86_32_Vector_Standard(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
540
17.3k
    return false;
541
6
542
6
  return true;  // CC didn't match.
543
6
}
544
545
546
static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT,
547
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
548
1.94k
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
549
1.94k
550
1.94k
  if (ArgFlags.isByVal()) {
551
94
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
552
94
    return false;
553
94
  }
554
1.84k
555
1.84k
  if (LocVT == MVT::i1 ||
556
1.84k
      LocVT == MVT::i8 ||
557
1.84k
      
LocVT == MVT::i161.73k
||
558
1.84k
      
LocVT == MVT::v1i11.73k
) {
559
112
    LocVT = MVT::i32;
560
112
    if (ArgFlags.isSExt())
561
8
        LocInfo = CCValAssign::SExt;
562
104
    else if (ArgFlags.isZExt())
563
102
        LocInfo = CCValAssign::ZExt;
564
2
    else
565
2
        LocInfo = CCValAssign::AExt;
566
112
  }
567
1.84k
568
1.84k
  if (ArgFlags.isNest()) {
569
0
    if (unsigned Reg = State.AllocateReg(X86::EAX)) {
570
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
571
0
      return false;
572
0
    }
573
1.84k
  }
574
1.84k
575
1.84k
  if (LocVT == MVT::i32) {
576
1.82k
    static const MCPhysReg RegList1[] = {
577
1.82k
      X86::ECX, X86::EDX
578
1.82k
    };
579
1.82k
    if (unsigned Reg = State.AllocateReg(RegList1)) {
580
1.37k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
581
1.37k
      return false;
582
1.37k
    }
583
471
  }
584
471
585
471
  if (!State.isVarArg()) {
586
471
    if (LocVT == MVT::f32 ||
587
471
        
LocVT == MVT::f64467
) {
588
18
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
589
8
        static const MCPhysReg RegList2[] = {
590
8
          X86::XMM0, X86::XMM1, X86::XMM2
591
8
        };
592
8
        if (unsigned Reg = State.AllocateReg(RegList2)) {
593
6
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
594
6
          return false;
595
6
        }
596
465
      }
597
18
    }
598
471
  }
599
465
600
465
  if (LocVT == MVT::f64) {
601
9
    unsigned Offset3 = State.AllocateStack(8, 8);
602
9
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
603
9
    return false;
604
9
  }
605
456
606
456
  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
607
456
    return false;
608
0
609
0
  return true;  // CC didn't match.
610
0
}
611
612
613
static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT,
614
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
615
266
                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
616
266
617
266
  if (LocVT == MVT::i1) {
618
0
    LocVT = MVT::i8;
619
0
    if (ArgFlags.isSExt())
620
0
        LocInfo = CCValAssign::SExt;
621
0
    else if (ArgFlags.isZExt())
622
0
        LocInfo = CCValAssign::ZExt;
623
0
    else
624
0
        LocInfo = CCValAssign::AExt;
625
0
  }
626
266
627
266
  if (ArgFlags.isNest()) {
628
0
    if (unsigned Reg = State.AllocateReg(X86::EAX)) {
629
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
630
0
      return false;
631
0
    }
632
266
  }
633
266
634
266
  if (ArgFlags.isInReg()) {
635
197
    if (LocVT == MVT::i8) {
636
4
      static const MCPhysReg RegList1[] = {
637
4
        X86::CL, X86::DL
638
4
      };
639
4
      if (unsigned Reg = State.AllocateReg(RegList1)) {
640
4
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
641
4
        return false;
642
4
      }
643
262
    }
644
197
  }
645
262
646
262
  if (ArgFlags.isInReg()) {
647
193
    if (LocVT == MVT::i16) {
648
0
      static const MCPhysReg RegList2[] = {
649
0
        X86::CX, X86::DX
650
0
      };
651
0
      if (unsigned Reg = State.AllocateReg(RegList2)) {
652
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
653
0
        return false;
654
0
      }
655
262
    }
656
193
  }
657
262
658
262
  if (ArgFlags.isInReg()) {
659
193
    if (LocVT == MVT::i32) {
660
178
      static const MCPhysReg RegList3[] = {
661
178
        X86::ECX, X86::EDX
662
178
      };
663
178
      if (unsigned Reg = State.AllocateReg(RegList3)) {
664
172
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
665
172
        return false;
666
172
      }
667
90
    }
668
193
  }
669
90
670
90
  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
671
84
    return false;
672
6
673
6
  return true;  // CC didn't match.
674
6
}
675
676
677
static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT,
678
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
679
20
                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
680
20
681
20
  if (LocVT == MVT::i8 ||
682
20
      LocVT == MVT::i16) {
683
0
    LocVT = MVT::i32;
684
0
    if (ArgFlags.isSExt())
685
0
        LocInfo = CCValAssign::SExt;
686
0
    else if (ArgFlags.isZExt())
687
0
        LocInfo = CCValAssign::ZExt;
688
0
    else
689
0
        LocInfo = CCValAssign::AExt;
690
0
  }
691
20
692
20
  if (LocVT == MVT::i32) {
693
20
    static const MCPhysReg RegList1[] = {
694
20
      X86::EBX, X86::EBP, X86::EDI, X86::ESI
695
20
    };
696
20
    if (unsigned Reg = State.AllocateReg(RegList1)) {
697
20
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
698
20
      return false;
699
20
    }
700
0
  }
701
0
702
0
  return true;  // CC didn't match.
703
0
}
704
705
706
static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
707
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
708
42
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
709
42
710
42
  if (LocVT == MVT::i8 ||
711
42
      LocVT == MVT::i16) {
712
0
    LocVT = MVT::i32;
713
0
    if (ArgFlags.isSExt())
714
0
        LocInfo = CCValAssign::SExt;
715
0
    else if (ArgFlags.isZExt())
716
0
        LocInfo = CCValAssign::ZExt;
717
0
    else
718
0
        LocInfo = CCValAssign::AExt;
719
0
  }
720
42
721
42
  if (LocVT == MVT::i32) {
722
42
    static const MCPhysReg RegList1[] = {
723
42
      X86::ESI, X86::EBP, X86::EAX, X86::EDX, X86::ECX
724
42
    };
725
42
    if (unsigned Reg = State.AllocateReg(RegList1)) {
726
41
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
727
41
      return false;
728
41
    }
729
1
  }
730
1
731
1
  if (LocVT == MVT::i32 ||
732
1
      
LocVT == MVT::f320
) {
733
1
    unsigned Offset2 = State.AllocateStack(4, 4);
734
1
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
735
1
    return false;
736
1
  }
737
0
738
0
  return true;  // CC didn't match.
739
0
}
740
741
742
static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT,
743
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
744
126
                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
745
126
746
126
  if (ArgFlags.isByVal()) {
747
1
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
748
1
    return false;
749
1
  }
750
125
751
125
  if (LocVT == MVT::i1 ||
752
125
      LocVT == MVT::i8 ||
753
125
      
LocVT == MVT::i16113
||
754
125
      
LocVT == MVT::v1i1106
) {
755
19
    LocVT = MVT::i32;
756
19
    if (ArgFlags.isSExt())
757
0
        LocInfo = CCValAssign::SExt;
758
19
    else if (ArgFlags.isZExt())
759
3
        LocInfo = CCValAssign::ZExt;
760
16
    else
761
16
        LocInfo = CCValAssign::AExt;
762
19
  }
763
125
764
125
  if (!State.isVarArg()) {
765
124
    if (LocVT == MVT::i32) {
766
123
      if (CC_X86_32_MCUInReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
767
120
            return false;
768
5
    }
769
124
  }
770
5
771
5
  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
772
5
    return false;
773
0
774
0
  return true;  // CC didn't match.
775
0
}
776
777
778
static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
779
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
780
209
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
781
209
782
209
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
783
0
    if (ArgFlags.isByVal()) {
784
0
      State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
785
0
      return false;
786
0
    }
787
209
  }
788
209
789
209
  if (ArgFlags.isByVal()) {
790
0
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
791
0
    return false;
792
0
  }
793
209
794
209
  if (LocVT == MVT::i1 ||
795
209
      LocVT == MVT::i8 ||
796
209
      
LocVT == MVT::i16198
||
797
209
      
LocVT == MVT::v1i1194
) {
798
15
    LocVT = MVT::i32;
799
15
    if (ArgFlags.isSExt())
800
2
        LocInfo = CCValAssign::SExt;
801
13
    else if (ArgFlags.isZExt())
802
0
        LocInfo = CCValAssign::ZExt;
803
13
    else
804
13
        LocInfo = CCValAssign::AExt;
805
15
  }
806
209
807
209
  if (LocVT == MVT::v8i1 ||
808
209
      
LocVT == MVT::v16i1200
||
809
209
      
LocVT == MVT::v32i1191
) {
810
24
    LocVT = MVT::i32;
811
24
    if (ArgFlags.isSExt())
812
0
        LocInfo = CCValAssign::SExt;
813
24
    else if (ArgFlags.isZExt())
814
0
        LocInfo = CCValAssign::ZExt;
815
24
    else
816
24
        LocInfo = CCValAssign::AExt;
817
24
  }
818
209
819
209
  if (LocVT == MVT::i32) {
820
92
    static const MCPhysReg RegList1[] = {
821
92
      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI
822
92
    };
823
92
    if (unsigned Reg = State.AllocateReg(RegList1)) {
824
77
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
825
77
      return false;
826
77
    }
827
132
  }
828
132
829
132
  if (LocVT == MVT::i64) {
830
0
    if (unsigned Reg = State.AllocateReg(X86::RAX)) {
831
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
832
0
      return false;
833
0
    }
834
132
  }
835
132
836
132
  if (LocVT == MVT::v64i1) {
837
26
    LocVT = MVT::i64;
838
26
    if (ArgFlags.isSExt())
839
0
        LocInfo = CCValAssign::SExt;
840
26
    else if (ArgFlags.isZExt())
841
0
        LocInfo = CCValAssign::ZExt;
842
26
    else
843
26
        LocInfo = CCValAssign::AExt;
844
26
  }
845
132
846
132
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
847
0
    if (LocVT == MVT::i64) {
848
0
      if (unsigned Reg = State.AllocateReg(X86::RAX)) {
849
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
850
0
        return false;
851
0
      }
852
132
    }
853
0
  }
854
132
855
132
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
856
132
    if (LocVT == MVT::i64) {
857
26
      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
858
4
            return false;
859
128
    }
860
132
  }
861
128
862
128
  if (LocVT == MVT::f32 ||
863
128
      
LocVT == MVT::f64123
||
864
128
      
LocVT == MVT::f128118
) {
865
10
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
866
10
      static const MCPhysReg RegList2[] = {
867
10
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
868
10
      };
869
10
      if (unsigned Reg = State.AllocateReg(RegList2)) {
870
10
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
871
10
        return false;
872
10
      }
873
118
    }
874
10
  }
875
118
876
118
  if (LocVT == MVT::f80) {
877
3
    if (unsigned Reg = State.AllocateReg(X86::FP0)) {
878
3
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
879
3
      return false;
880
3
    }
881
115
  }
882
115
883
115
  if (LocVT == MVT::v16i8 ||
884
115
      LocVT == MVT::v8i16 ||
885
115
      LocVT == MVT::v4i32 ||
886
115
      
LocVT == MVT::v2i64110
||
887
115
      
LocVT == MVT::v4f32110
||
888
115
      
LocVT == MVT::v2f6474
) {
889
41
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
890
41
      static const MCPhysReg RegList3[] = {
891
41
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
892
41
      };
893
41
      if (unsigned Reg = State.AllocateReg(RegList3)) {
894
21
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
895
21
        return false;
896
21
      }
897
94
    }
898
41
  }
899
94
900
94
  if (LocVT == MVT::v32i8 ||
901
94
      LocVT == MVT::v16i16 ||
902
94
      LocVT == MVT::v8i32 ||
903
94
      
LocVT == MVT::v4i6489
||
904
94
      
LocVT == MVT::v8f3289
||
905
94
      
LocVT == MVT::v4f6489
) {
906
5
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
907
5
      static const MCPhysReg RegList4[] = {
908
5
        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
909
5
      };
910
5
      if (unsigned Reg = State.AllocateReg(RegList4)) {
911
5
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
912
5
        return false;
913
5
      }
914
89
    }
915
5
  }
916
89
917
89
  if (LocVT == MVT::v64i8 ||
918
89
      LocVT == MVT::v32i16 ||
919
89
      LocVT == MVT::v16i32 ||
920
89
      
LocVT == MVT::v8i6484
||
921
89
      
LocVT == MVT::v16f3284
||
922
89
      
LocVT == MVT::v8f6460
) {
923
29
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
924
29
      static const MCPhysReg RegList5[] = {
925
29
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
926
29
      };
927
29
      if (unsigned Reg = State.AllocateReg(RegList5)) {
928
19
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
929
19
        return false;
930
19
      }
931
70
    }
932
29
  }
933
70
934
70
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
935
0
    if (LocVT == MVT::i32 ||
936
0
        LocVT == MVT::i64 ||
937
0
        LocVT == MVT::f32 ||
938
0
        LocVT == MVT::f64) {
939
0
      unsigned Offset6 = State.AllocateStack(8, 8);
940
0
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
941
0
      return false;
942
0
    }
943
70
  }
944
70
945
70
  if (LocVT == MVT::i32 ||
946
70
      
LocVT == MVT::f3255
) {
947
15
    unsigned Offset7 = State.AllocateStack(4, 4);
948
15
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
949
15
    return false;
950
15
  }
951
55
952
55
  if (LocVT == MVT::i64 ||
953
55
      
LocVT == MVT::f6433
) {
954
22
    unsigned Offset8 = State.AllocateStack(8, 4);
955
22
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
956
22
    return false;
957
22
  }
958
33
959
33
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
960
0
    if (LocVT == MVT::x86mmx) {
961
0
      unsigned Offset9 = State.AllocateStack(8, 8);
962
0
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
963
0
      return false;
964
0
    }
965
33
  }
966
33
967
33
  if (LocVT == MVT::x86mmx) {
968
0
    unsigned Offset10 = State.AllocateStack(8, 4);
969
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
970
0
    return false;
971
0
  }
972
33
973
33
  if (LocVT == MVT::f80 ||
974
33
      LocVT == MVT::f128) {
975
0
    unsigned Offset11 = State.AllocateStack(
976
0
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 
977
0
      State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
978
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo));
979
0
    return false;
980
0
  }
981
33
982
33
  if (LocVT == MVT::v16i8 ||
983
33
      LocVT == MVT::v8i16 ||
984
33
      LocVT == MVT::v4i32 ||
985
33
      LocVT == MVT::v2i64 ||
986
33
      LocVT == MVT::v4f32 ||
987
33
      
LocVT == MVT::v2f6413
) {
988
20
    unsigned Offset12 = State.AllocateStack(16, 16);
989
20
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo));
990
20
    return false;
991
20
  }
992
13
993
13
  if (LocVT == MVT::v32i8 ||
994
13
      LocVT == MVT::v16i16 ||
995
13
      LocVT == MVT::v8i32 ||
996
13
      LocVT == MVT::v4i64 ||
997
13
      LocVT == MVT::v8f32 ||
998
13
      LocVT == MVT::v4f64) {
999
0
    unsigned Offset13 = State.AllocateStack(32, 32);
1000
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo));
1001
0
    return false;
1002
0
  }
1003
13
1004
13
  if (LocVT == MVT::v64i8 ||
1005
13
      LocVT == MVT::v32i16 ||
1006
13
      LocVT == MVT::v16i32 ||
1007
13
      LocVT == MVT::v8i64 ||
1008
13
      LocVT == MVT::v16f32 ||
1009
13
      
LocVT == MVT::v8f643
) {
1010
10
    unsigned Offset14 = State.AllocateStack(64, 64);
1011
10
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo));
1012
10
    return false;
1013
10
  }
1014
3
1015
3
  return true;  // CC didn't match.
1016
3
}
1017
1018
1019
static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT,
1020
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
1021
453
                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
1022
453
1023
453
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetCygMing()) {
1024
40
    if (!CC_X86_32_ThisCall_Mingw(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1025
40
      return false;
1026
413
  }
1027
413
1028
413
  if (!CC_X86_32_ThisCall_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1029
413
    return false;
1030
0
1031
0
  return true;  // CC didn't match.
1032
0
}
1033
1034
1035
static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT,
1036
                                      MVT LocVT, CCValAssign::LocInfo LocInfo,
1037
429
                                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1038
429
1039
429
  if (LocVT == MVT::i32) {
1040
419
    if (unsigned Reg = State.AllocateReg(X86::ECX)) {
1041
235
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1042
235
      return false;
1043
235
    }
1044
194
  }
1045
194
1046
194
  if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1047
194
    return false;
1048
0
1049
0
  return true;  // CC didn't match.
1050
0
}
1051
1052
1053
static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT,
1054
                                     MVT LocVT, CCValAssign::LocInfo LocInfo,
1055
40
                                     ISD::ArgFlagsTy ArgFlags, CCState &State) {
1056
40
1057
40
  if (LocVT == MVT::i1 ||
1058
40
      LocVT == MVT::i8 ||
1059
40
      LocVT == MVT::i16 ||
1060
40
      LocVT == MVT::v1i1) {
1061
0
    LocVT = MVT::i32;
1062
0
    if (ArgFlags.isSExt())
1063
0
        LocInfo = CCValAssign::SExt;
1064
0
    else if (ArgFlags.isZExt())
1065
0
        LocInfo = CCValAssign::ZExt;
1066
0
    else
1067
0
        LocInfo = CCValAssign::AExt;
1068
0
  }
1069
40
1070
40
  if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1071
40
    return false;
1072
0
1073
0
  return true;  // CC didn't match.
1074
0
}
1075
1076
1077
static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT,
1078
                                   MVT LocVT, CCValAssign::LocInfo LocInfo,
1079
413
                                   ISD::ArgFlagsTy ArgFlags, CCState &State) {
1080
413
1081
413
  if (LocVT == MVT::i1 ||
1082
413
      LocVT == MVT::i8 ||
1083
413
      
LocVT == MVT::i16412
||
1084
413
      
LocVT == MVT::v1i1412
) {
1085
1
    LocVT = MVT::i32;
1086
1
    if (ArgFlags.isSExt())
1087
0
        LocInfo = CCValAssign::SExt;
1088
1
    else if (ArgFlags.isZExt())
1089
0
        LocInfo = CCValAssign::ZExt;
1090
1
    else
1091
1
        LocInfo = CCValAssign::AExt;
1092
1
  }
1093
413
1094
413
  if (ArgFlags.isSRet()) {
1095
24
    unsigned Offset1 = State.AllocateStack(4, 4);
1096
24
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1097
24
    return false;
1098
24
  }
1099
389
1100
389
  if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1101
389
    return false;
1102
0
1103
0
  return true;  // CC didn't match.
1104
0
}
1105
1106
1107
static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT,
1108
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
1109
250
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
1110
250
1111
250
  if (LocVT == MVT::v16i8 ||
1112
250
      
LocVT == MVT::v8i16248
||
1113
250
      
LocVT == MVT::v4i32225
||
1114
250
      
LocVT == MVT::v2i64204
||
1115
250
      
LocVT == MVT::v4f32195
||
1116
250
      
LocVT == MVT::v2f64119
) {
1117
153
    unsigned Offset1 = State.AllocateStack(16, 16);
1118
153
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1119
153
    return false;
1120
153
  }
1121
97
1122
97
  if (LocVT == MVT::v32i8 ||
1123
97
      
LocVT == MVT::v16i1694
||
1124
97
      
LocVT == MVT::v8i3291
||
1125
97
      
LocVT == MVT::v4i6484
||
1126
97
      
LocVT == MVT::v8f3281
||
1127
97
      
LocVT == MVT::v4f6463
) {
1128
45
    unsigned Offset2 = State.AllocateStack(32, 32);
1129
45
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1130
45
    return false;
1131
45
  }
1132
52
1133
52
  if (LocVT == MVT::v64i8 ||
1134
52
      LocVT == MVT::v32i16 ||
1135
52
      
LocVT == MVT::v16i3248
||
1136
52
      
LocVT == MVT::v8i6440
||
1137
52
      
LocVT == MVT::v16f3223
||
1138
52
      
LocVT == MVT::v8f6418
) {
1139
46
    unsigned Offset3 = State.AllocateStack(64, 64);
1140
46
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
1141
46
    return false;
1142
46
  }
1143
6
1144
6
  return true;  // CC didn't match.
1145
6
}
1146
1147
1148
static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT,
1149
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
1150
4.07k
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
1151
4.07k
1152
4.07k
  if (!State.isVarArg()) {
1153
4.07k
    if (LocVT == MVT::v16i8 ||
1154
4.07k
        
LocVT == MVT::v8i163.70k
||
1155
4.07k
        
LocVT == MVT::v4i323.33k
||
1156
4.07k
        
LocVT == MVT::v2i642.96k
||
1157
4.07k
        
LocVT == MVT::v4f322.74k
||
1158
4.07k
        
LocVT == MVT::v2f642.05k
) {
1159
2.42k
      static const MCPhysReg RegList1[] = {
1160
2.42k
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1161
2.42k
      };
1162
2.42k
      if (unsigned Reg = State.AllocateReg(RegList1)) {
1163
2.42k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1164
2.42k
        return false;
1165
2.42k
      }
1166
1.65k
    }
1167
4.07k
  }
1168
1.65k
1169
1.65k
  if (!State.isVarArg()) {
1170
1.65k
    if (LocVT == MVT::v32i8 ||
1171
1.65k
        
LocVT == MVT::v16i161.57k
||
1172
1.65k
        
LocVT == MVT::v8i321.47k
||
1173
1.65k
        
LocVT == MVT::v4i641.37k
||
1174
1.65k
        
LocVT == MVT::v8f321.31k
||
1175
1.65k
        
LocVT == MVT::v4f641.22k
) {
1176
487
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1177
487
        static const MCPhysReg RegList2[] = {
1178
487
          X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
1179
487
        };
1180
487
        if (unsigned Reg = State.AllocateReg(RegList2)) {
1181
467
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1182
467
          return false;
1183
467
        }
1184
1.19k
      }
1185
487
    }
1186
1.65k
  }
1187
1.19k
1188
1.19k
  if (!State.isVarArg()) {
1189
1.19k
    if (LocVT == MVT::v64i8 ||
1190
1.19k
        
LocVT == MVT::v32i161.18k
||
1191
1.19k
        
LocVT == MVT::v16i321.17k
||
1192
1.19k
        
LocVT == MVT::v8i64871
||
1193
1.19k
        
LocVT == MVT::v16f32624
||
1194
1.19k
        
LocVT == MVT::v8f64242
) {
1195
1.16k
      static const MCPhysReg RegList3[] = {
1196
1.16k
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
1197
1.16k
      };
1198
1.16k
      if (unsigned Reg = State.AllocateReg(RegList3)) {
1199
1.16k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1200
1.16k
        return false;
1201
1.16k
      }
1202
30
    }
1203
1.19k
  }
1204
30
1205
30
  if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1206
30
    return false;
1207
0
1208
0
  return true;  // CC didn't match.
1209
0
}
1210
1211
1212
static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT,
1213
                                      MVT LocVT, CCValAssign::LocInfo LocInfo,
1214
17.3k
                                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1215
17.3k
1216
17.3k
  if (!State.isVarArg()) {
1217
17.3k
    if (LocVT == MVT::v16i8 ||
1218
17.3k
        
LocVT == MVT::v8i1616.5k
||
1219
17.3k
        
LocVT == MVT::v4i3215.5k
||
1220
17.3k
        
LocVT == MVT::v2i6414.1k
||
1221
17.3k
        
LocVT == MVT::v4f3211.8k
||
1222
17.3k
        
LocVT == MVT::v2f649.58k
) {
1223
9.36k
      static const MCPhysReg RegList1[] = {
1224
9.36k
        X86::XMM0, X86::XMM1, X86::XMM2
1225
9.36k
      };
1226
9.36k
      if (unsigned Reg = State.AllocateReg(RegList1)) {
1227
9.22k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1228
9.22k
        return false;
1229
9.22k
      }
1230
8.10k
    }
1231
17.3k
  }
1232
8.10k
1233
8.10k
  if (!State.isVarArg()) {
1234
8.10k
    if (LocVT == MVT::v32i8 ||
1235
8.10k
        
LocVT == MVT::v16i167.65k
||
1236
8.10k
        
LocVT == MVT::v8i327.03k
||
1237
8.10k
        
LocVT == MVT::v4i646.30k
||
1238
8.10k
        
LocVT == MVT::v8f325.10k
||
1239
8.10k
        
LocVT == MVT::v4f644.20k
) {
1240
4.57k
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1241
4.57k
        static const MCPhysReg RegList2[] = {
1242
4.57k
          X86::YMM0, X86::YMM1, X86::YMM2
1243
4.57k
        };
1244
4.57k
        if (unsigned Reg = State.AllocateReg(RegList2)) {
1245
4.55k
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1246
4.55k
          return false;
1247
4.55k
        }
1248
3.55k
      }
1249
4.57k
    }
1250
8.10k
  }
1251
3.55k
1252
3.55k
  if (!State.isVarArg()) {
1253
3.55k
    if (LocVT == MVT::v64i8 ||
1254
3.55k
        
LocVT == MVT::v32i163.33k
||
1255
3.55k
        
LocVT == MVT::v16i322.86k
||
1256
3.55k
        
LocVT == MVT::v8i642.52k
||
1257
3.55k
        
LocVT == MVT::v16f321.56k
||
1258
3.55k
        
LocVT == MVT::v8f64859
) {
1259
3.37k
      static const MCPhysReg RegList3[] = {
1260
3.37k
        X86::ZMM0, X86::ZMM1, X86::ZMM2
1261
3.37k
      };
1262
3.37k
      if (unsigned Reg = State.AllocateReg(RegList3)) {
1263
3.33k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1264
3.33k
        return false;
1265
3.33k
      }
1266
220
    }
1267
3.55k
  }
1268
220
1269
220
  if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1270
214
    return false;
1271
6
1272
6
  return true;  // CC didn't match.
1273
6
}
1274
1275
1276
static bool CC_X86_64(unsigned ValNo, MVT ValVT,
1277
                      MVT LocVT, CCValAssign::LocInfo LocInfo,
1278
488k
                      ISD::ArgFlagsTy ArgFlags, CCState &State) {
1279
488k
1280
488k
  if (State.getCallingConv() == CallingConv::GHC) {
1281
62
    if (!CC_X86_64_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1282
62
      return false;
1283
487k
  }
1284
487k
1285
487k
  if (State.getCallingConv() == CallingConv::HiPE) {
1286
42
    if (!CC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1287
42
      return false;
1288
487k
  }
1289
487k
1290
487k
  if (State.getCallingConv() == CallingConv::WebKit_JS) {
1291
69
    if (!CC_X86_64_WebKit_JS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1292
69
      return false;
1293
487k
  }
1294
487k
1295
487k
  if (State.getCallingConv() == CallingConv::AnyReg) {
1296
0
    if (!CC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1297
0
      return false;
1298
487k
  }
1299
487k
1300
487k
  if (State.getCallingConv() == CallingConv::Win64) {
1301
55
    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1302
55
      return false;
1303
487k
  }
1304
487k
1305
487k
  if (State.getCallingConv() == CallingConv::X86_64_SysV) {
1306
22
    if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1307
22
      return false;
1308
487k
  }
1309
487k
1310
487k
  if (State.getCallingConv() == CallingConv::X86_VectorCall) {
1311
180
    if (!CC_X86_Win64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1312
180
      return false;
1313
487k
  }
1314
487k
1315
487k
  if (State.getCallingConv() == CallingConv::HHVM) {
1316
112
    if (!CC_X86_64_HHVM(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1317
112
      return false;
1318
487k
  }
1319
487k
1320
487k
  if (State.getCallingConv() == CallingConv::HHVM_C) {
1321
25
    if (!CC_X86_64_HHVM_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1322
25
      return false;
1323
487k
  }
1324
487k
1325
487k
  if (State.getCallingConv() == CallingConv::X86_RegCall) {
1326
398
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
1327
204
      if (!CC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1328
201
        return false;
1329
487k
    }
1330
398
  }
1331
487k
1332
487k
  if (State.getCallingConv() == CallingConv::X86_RegCall) {
1333
197
    if (!CC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1334
191
      return false;
1335
487k
  }
1336
487k
1337
487k
  if (State.getCallingConv() == CallingConv::X86_INTR) {
1338
30
    if (CC_X86_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1339
30
        return false;
1340
487k
  }
1341
487k
1342
487k
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
1343
3.09k
    if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1344
3.08k
      return false;
1345
483k
  }
1346
483k
1347
483k
  if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1348
483k
    return false;
1349
201
1350
201
  return true;  // CC didn't match.
1351
201
}
1352
1353
1354
static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
1355
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
1356
0
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
1357
0
1358
0
  if (CC_X86_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1359
0
    return false;
1360
0
1361
0
  return true;  // CC didn't match.
1362
0
}
1363
1364
1365
static bool CC_X86_64_C(unsigned ValNo, MVT ValVT,
1366
                        MVT LocVT, CCValAssign::LocInfo LocInfo,
1367
483k
                        ISD::ArgFlagsTy ArgFlags, CCState &State) {
1368
483k
1369
483k
  if (ArgFlags.isByVal()) {
1370
603
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
1371
603
    return false;
1372
603
  }
1373
483k
1374
483k
  if (LocVT == MVT::i1 ||
1375
483k
      
LocVT == MVT::i8483k
||
1376
483k
      
LocVT == MVT::i16462k
||
1377
483k
      
LocVT == MVT::v1i1458k
) {
1378
24.5k
    LocVT = MVT::i32;
1379
24.5k
    if (ArgFlags.isSExt())
1380
449
        LocInfo = CCValAssign::SExt;
1381
24.0k
    else if (ArgFlags.isZExt())
1382
15.5k
        LocInfo = CCValAssign::ZExt;
1383
8.50k
    else
1384
8.50k
        LocInfo = CCValAssign::AExt;
1385
24.5k
  }
1386
483k
1387
483k
  if (ArgFlags.isNest()) {
1388
38
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTarget64BitILP32()) {
1389
4
      if (unsigned Reg = State.AllocateReg(X86::R10D)) {
1390
4
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1391
4
        return false;
1392
4
      }
1393
483k
    }
1394
38
  }
1395
483k
1396
483k
  if (ArgFlags.isNest()) {
1397
34
    if (unsigned Reg = State.AllocateReg(X86::R10)) {
1398
34
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1399
34
      return false;
1400
34
    }
1401
483k
  }
1402
483k
1403
483k
  if (ArgFlags.isSwiftSelf()) {
1404
40
    if (LocVT == MVT::i64) {
1405
40
      if (unsigned Reg = State.AllocateReg(X86::R13)) {
1406
40
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1407
40
        return false;
1408
40
      }
1409
483k
    }
1410
40
  }
1411
483k
1412
483k
  if (ArgFlags.isSwiftError()) {
1413
74
    if (LocVT == MVT::i64) {
1414
74
      if (unsigned Reg = State.AllocateReg(X86::R12)) {
1415
74
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1416
74
        return false;
1417
74
      }
1418
483k
    }
1419
74
  }
1420
483k
1421
483k
  if (State.getCallingConv() == CallingConv::Swift) {
1422
134
    if (ArgFlags.isSRet()) {
1423
6
      if (LocVT == MVT::i64) {
1424
6
        if (unsigned Reg = State.AllocateReg(X86::RAX)) {
1425
6
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1426
6
          return false;
1427
6
        }
1428
483k
      }
1429
6
    }
1430
134
  }
1431
483k
1432
483k
  if (LocVT == MVT::i32) {
1433
66.7k
    static const MCPhysReg RegList1[] = {
1434
66.7k
      X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1435
66.7k
    };
1436
66.7k
    if (unsigned Reg = State.AllocateReg(RegList1)) {
1437
61.5k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1438
61.5k
      return false;
1439
61.5k
    }
1440
421k
  }
1441
421k
1442
421k
  if (LocVT == MVT::i64) {
1443
293k
    static const MCPhysReg RegList2[] = {
1444
293k
      X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1445
293k
    };
1446
293k
    if (unsigned Reg = State.AllocateReg(RegList2)) {
1447
290k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1448
290k
      return false;
1449
290k
    }
1450
130k
  }
1451
130k
1452
130k
  if (LocVT == MVT::x86mmx) {
1453
215
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()) {
1454
12
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
1455
12
        LocVT = MVT::v2i64;
1456
12
        if (ArgFlags.isSExt())
1457
0
                LocInfo = CCValAssign::SExt;
1458
12
        else if (ArgFlags.isZExt())
1459
0
                LocInfo = CCValAssign::ZExt;
1460
12
        else
1461
12
                LocInfo = CCValAssign::AExt;
1462
12
      }
1463
12
    }
1464
215
  }
1465
130k
1466
130k
  if (LocVT == MVT::v2i1) {
1467
106
    LocVT = MVT::v2i64;
1468
106
    if (ArgFlags.isSExt())
1469
0
        LocInfo = CCValAssign::SExt;
1470
106
    else if (ArgFlags.isZExt())
1471
0
        LocInfo = CCValAssign::ZExt;
1472
106
    else
1473
106
        LocInfo = CCValAssign::AExt;
1474
106
  }
1475
130k
1476
130k
  if (LocVT == MVT::v4i1) {
1477
150
    LocVT = MVT::v4i32;
1478
150
    if (ArgFlags.isSExt())
1479
0
        LocInfo = CCValAssign::SExt;
1480
150
    else if (ArgFlags.isZExt())
1481
0
        LocInfo = CCValAssign::ZExt;
1482
150
    else
1483
150
        LocInfo = CCValAssign::AExt;
1484
150
  }
1485
130k
1486
130k
  if (LocVT == MVT::v8i1) {
1487
119
    LocVT = MVT::v8i16;
1488
119
    if (ArgFlags.isSExt())
1489
0
        LocInfo = CCValAssign::SExt;
1490
119
    else if (ArgFlags.isZExt())
1491
0
        LocInfo = CCValAssign::ZExt;
1492
119
    else
1493
119
        LocInfo = CCValAssign::AExt;
1494
119
  }
1495
130k
1496
130k
  if (LocVT == MVT::v16i1) {
1497
161
    LocVT = MVT::v16i8;
1498
161
    if (ArgFlags.isSExt())
1499
0
        LocInfo = CCValAssign::SExt;
1500
161
    else if (ArgFlags.isZExt())
1501
0
        LocInfo = CCValAssign::ZExt;
1502
161
    else
1503
161
        LocInfo = CCValAssign::AExt;
1504
161
  }
1505
130k
1506
130k
  if (LocVT == MVT::v32i1) {
1507
24
    LocVT = MVT::v32i8;
1508
24
    if (ArgFlags.isSExt())
1509
0
        LocInfo = CCValAssign::SExt;
1510
24
    else if (ArgFlags.isZExt())
1511
0
        LocInfo = CCValAssign::ZExt;
1512
24
    else
1513
24
        LocInfo = CCValAssign::AExt;
1514
24
  }
1515
130k
1516
130k
  if (LocVT == MVT::v64i1) {
1517
5
    LocVT = MVT::v64i8;
1518
5
    if (ArgFlags.isSExt())
1519
0
        LocInfo = CCValAssign::SExt;
1520
5
    else if (ArgFlags.isZExt())
1521
0
        LocInfo = CCValAssign::ZExt;
1522
5
    else
1523
5
        LocInfo = CCValAssign::AExt;
1524
5
  }
1525
130k
1526
130k
  if (LocVT == MVT::f32 ||
1527
130k
      
LocVT == MVT::f64127k
||
1528
130k
      
LocVT == MVT::f128124k
||
1529
130k
      
LocVT == MVT::v16i8123k
||
1530
130k
      
LocVT == MVT::v8i16114k
||
1531
130k
      
LocVT == MVT::v4i32103k
||
1532
130k
      
LocVT == MVT::v2i6488.7k
||
1533
130k
      
LocVT == MVT::v4f3274.9k
||
1534
130k
      
LocVT == MVT::v2f6465.0k
) {
1535
72.1k
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1536
72.1k
      static const MCPhysReg RegList3[] = {
1537
72.1k
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1538
72.1k
      };
1539
72.1k
      if (unsigned Reg = State.AllocateReg(RegList3)) {
1540
69.6k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1541
69.6k
        return false;
1542
69.6k
      }
1543
61.1k
    }
1544
72.1k
  }
1545
61.1k
1546
61.1k
  if (!State.isVarArg()) {
1547
60.2k
    if (LocVT == MVT::v32i8 ||
1548
60.2k
        
LocVT == MVT::v16i1654.9k
||
1549
60.2k
        
LocVT == MVT::v8i3248.4k
||
1550
60.2k
        
LocVT == MVT::v4i6441.8k
||
1551
60.2k
        
LocVT == MVT::v8f3235.1k
||
1552
60.2k
        
LocVT == MVT::v4f6429.8k
) {
1553
34.7k
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1554
34.7k
        static const MCPhysReg RegList4[] = {
1555
34.7k
          X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
1556
34.7k
        };
1557
34.7k
        if (unsigned Reg = State.AllocateReg(RegList4)) {
1558
34.6k
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1559
34.6k
          return false;
1560
34.6k
        }
1561
26.4k
      }
1562
34.7k
    }
1563
60.2k
  }
1564
26.4k
1565
26.4k
  if (!State.isVarArg()) {
1566
25.5k
    if (LocVT == MVT::v64i8 ||
1567
25.5k
        
LocVT == MVT::v32i1624.5k
||
1568
25.5k
        
LocVT == MVT::v16i3223.1k
||
1569
25.5k
        
LocVT == MVT::v8i6420.0k
||
1570
25.5k
        
LocVT == MVT::v16f3215.7k
||
1571
25.5k
        
LocVT == MVT::v8f6412.9k
) {
1572
15.1k
      if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
1573
15.1k
        static const MCPhysReg RegList5[] = {
1574
15.1k
          X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
1575
15.1k
        };
1576
15.1k
        if (unsigned Reg = State.AllocateReg(RegList5)) {
1577
15.1k
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1578
15.1k
          return false;
1579
15.1k
        }
1580
11.2k
      }
1581
15.1k
    }
1582
25.5k
  }
1583
11.2k
1584
11.2k
  if (LocVT == MVT::i32 ||
1585
11.2k
      
LocVT == MVT::i646.06k
||
1586
11.2k
      
LocVT == MVT::f323.57k
||
1587
11.2k
      
LocVT == MVT::f643.50k
) {
1588
7.78k
    unsigned Offset6 = State.AllocateStack(8, 8);
1589
7.78k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
1590
7.78k
    return false;
1591
7.78k
  }
1592
3.50k
1593
3.50k
  if (LocVT == MVT::f80 ||
1594
3.50k
      
LocVT == MVT::f1282.85k
) {
1595
768
    unsigned Offset7 = State.AllocateStack(
1596
768
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 
1597
768
      State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
1598
768
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
1599
768
    return false;
1600
768
  }
1601
2.73k
1602
2.73k
  if (LocVT == MVT::v16i8 ||
1603
2.73k
      
LocVT == MVT::v8i162.59k
||
1604
2.73k
      
LocVT == MVT::v4i322.47k
||
1605
2.73k
      
LocVT == MVT::v2i642.23k
||
1606
2.73k
      
LocVT == MVT::v4f32631
||
1607
2.73k
      
LocVT == MVT::v2f64510
) {
1608
2.38k
    unsigned Offset8 = State.AllocateStack(16, 16);
1609
2.38k
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
1610
2.38k
    return false;
1611
2.38k
  }
1612
345
1613
345
  if (LocVT == MVT::v32i8 ||
1614
345
      
LocVT == MVT::v16i16274
||
1615
345
      
LocVT == MVT::v8i32274
||
1616
345
      
LocVT == MVT::v4i64274
||
1617
345
      
LocVT == MVT::v8f32238
||
1618
345
      
LocVT == MVT::v4f64233
) {
1619
129
    unsigned Offset9 = State.AllocateStack(32, 32);
1620
129
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
1621
129
    return false;
1622
129
  }
1623
216
1624
216
  if (LocVT == MVT::v64i8 ||
1625
216
      
LocVT == MVT::v32i16207
||
1626
216
      
LocVT == MVT::v16i32205
||
1627
216
      
LocVT == MVT::v8i64203
||
1628
216
      
LocVT == MVT::v16f32203
||
1629
216
      
LocVT == MVT::v8f64203
) {
1630
14
    unsigned Offset10 = State.AllocateStack(64, 64);
1631
14
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
1632
14
    return false;
1633
14
  }
1634
202
1635
202
  return true;  // CC didn't match.
1636
202
}
1637
1638
1639
static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT,
1640
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
1641
62
                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
1642
62
1643
62
  if (LocVT == MVT::i8 ||
1644
62
      LocVT == MVT::i16 ||
1645
62
      LocVT == MVT::i32) {
1646
0
    LocVT = MVT::i64;
1647
0
    if (ArgFlags.isSExt())
1648
0
        LocInfo = CCValAssign::SExt;
1649
0
    else if (ArgFlags.isZExt())
1650
0
        LocInfo = CCValAssign::ZExt;
1651
0
    else
1652
0
        LocInfo = CCValAssign::AExt;
1653
0
  }
1654
62
1655
62
  if (LocVT == MVT::i64) {
1656
56
    static const MCPhysReg RegList1[] = {
1657
56
      X86::R13, X86::RBP, X86::R12, X86::RBX, X86::R14, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R15
1658
56
    };
1659
56
    if (unsigned Reg = State.AllocateReg(RegList1)) {
1660
56
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1661
56
      return false;
1662
56
    }
1663
6
  }
1664
6
1665
6
  if (LocVT == MVT::f32 ||
1666
6
      
LocVT == MVT::f642
||
1667
6
      
LocVT == MVT::v16i80
||
1668
6
      
LocVT == MVT::v8i160
||
1669
6
      
LocVT == MVT::v4i320
||
1670
6
      
LocVT == MVT::v2i640
||
1671
6
      
LocVT == MVT::v4f320
||
1672
6
      
LocVT == MVT::v2f640
) {
1673
6
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1674
6
      static const MCPhysReg RegList2[] = {
1675
6
        X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6
1676
6
      };
1677
6
      if (unsigned Reg = State.AllocateReg(RegList2)) {
1678
6
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1679
6
        return false;
1680
6
      }
1681
0
    }
1682
6
  }
1683
0
1684
0
  if (LocVT == MVT::v32i8 ||
1685
0
      LocVT == MVT::v16i16 ||
1686
0
      LocVT == MVT::v8i32 ||
1687
0
      LocVT == MVT::v4i64 ||
1688
0
      LocVT == MVT::v8f32 ||
1689
0
      LocVT == MVT::v4f64) {
1690
0
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1691
0
      static const MCPhysReg RegList3[] = {
1692
0
        X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6
1693
0
      };
1694
0
      if (unsigned Reg = State.AllocateReg(RegList3)) {
1695
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1696
0
        return false;
1697
0
      }
1698
0
    }
1699
0
  }
1700
0
1701
0
  if (LocVT == MVT::v64i8 ||
1702
0
      LocVT == MVT::v32i16 ||
1703
0
      LocVT == MVT::v16i32 ||
1704
0
      LocVT == MVT::v8i64 ||
1705
0
      LocVT == MVT::v16f32 ||
1706
0
      LocVT == MVT::v8f64) {
1707
0
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
1708
0
      static const MCPhysReg RegList4[] = {
1709
0
        X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6
1710
0
      };
1711
0
      if (unsigned Reg = State.AllocateReg(RegList4)) {
1712
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1713
0
        return false;
1714
0
      }
1715
0
    }
1716
0
  }
1717
0
1718
0
  return true;  // CC didn't match.
1719
0
}
1720
1721
1722
static bool CC_X86_64_HHVM(unsigned ValNo, MVT ValVT,
1723
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
1724
112
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
1725
112
1726
112
  if (LocVT == MVT::i64) {
1727
112
    static const MCPhysReg RegList1[] = {
1728
112
      X86::RBX, X86::R12, X86::RBP, X86::R15, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9, X86::RAX, X86::R10, X86::R11, X86::R13, X86::R14
1729
112
    };
1730
112
    if (unsigned Reg = State.AllocateReg(RegList1)) {
1731
112
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1732
112
      return false;
1733
112
    }
1734
0
  }
1735
0
1736
0
  return true;  // CC didn't match.
1737
0
}
1738
1739
1740
static bool CC_X86_64_HHVM_C(unsigned ValNo, MVT ValVT,
1741
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
1742
25
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
1743
25
1744
25
  if (LocVT == MVT::i64) {
1745
24
    if (unsigned Reg = State.AllocateReg(X86::RBP)) {
1746
5
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1747
5
      return false;
1748
5
    }
1749
20
  }
1750
20
1751
20
  if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1752
20
    return false;
1753
0
1754
0
  return true;  // CC didn't match.
1755
0
}
1756
1757
1758
static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
1759
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
1760
42
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
1761
42
1762
42
  if (LocVT == MVT::i8 ||
1763
42
      LocVT == MVT::i16 ||
1764
42
      LocVT == MVT::i32) {
1765
6
    LocVT = MVT::i64;
1766
6
    if (ArgFlags.isSExt())
1767
0
        LocInfo = CCValAssign::SExt;
1768
6
    else if (ArgFlags.isZExt())
1769
0
        LocInfo = CCValAssign::ZExt;
1770
6
    else
1771
6
        LocInfo = CCValAssign::AExt;
1772
6
  }
1773
42
1774
42
  if (LocVT == MVT::i64) {
1775
42
    static const MCPhysReg RegList1[] = {
1776
42
      X86::R15, X86::RBP, X86::RSI, X86::RDX, X86::RCX, X86::R8
1777
42
    };
1778
42
    if (unsigned Reg = State.AllocateReg(RegList1)) {
1779
41
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1780
41
      return false;
1781
41
    }
1782
1
  }
1783
1
1784
1
  if (LocVT == MVT::i32 ||
1785
1
      LocVT == MVT::i64 ||
1786
1
      
LocVT == MVT::f320
||
1787
1
      
LocVT == MVT::f640
) {
1788
1
    unsigned Offset2 = State.AllocateStack(8, 8);
1789
1
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1790
1
    return false;
1791
1
  }
1792
0
1793
0
  return true;  // CC didn't match.
1794
0
}
1795
1796
1797
static bool CC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT,
1798
                                MVT LocVT, CCValAssign::LocInfo LocInfo,
1799
69
                                ISD::ArgFlagsTy ArgFlags, CCState &State) {
1800
69
1801
69
  if (LocVT == MVT::i8 ||
1802
69
      LocVT == MVT::i16) {
1803
0
    LocVT = MVT::i32;
1804
0
    if (ArgFlags.isSExt())
1805
0
        LocInfo = CCValAssign::SExt;
1806
0
    else if (ArgFlags.isZExt())
1807
0
        LocInfo = CCValAssign::ZExt;
1808
0
    else
1809
0
        LocInfo = CCValAssign::AExt;
1810
0
  }
1811
69
1812
69
  if (LocVT == MVT::i32) {
1813
26
    if (unsigned Reg = State.AllocateReg(X86::EAX)) {
1814
4
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1815
4
      return false;
1816
4
    }
1817
65
  }
1818
65
1819
65
  if (LocVT == MVT::i64) {
1820
43
    if (unsigned Reg = State.AllocateReg(X86::RAX)) {
1821
9
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1822
9
      return false;
1823
9
    }
1824
56
  }
1825
56
1826
56
  if (LocVT == MVT::i32 ||
1827
56
      
LocVT == MVT::f3234
) {
1828
22
    unsigned Offset1 = State.AllocateStack(4, 4);
1829
22
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
1830
22
    return false;
1831
22
  }
1832
34
1833
34
  if (LocVT == MVT::i64 ||
1834
34
      
LocVT == MVT::f640
) {
1835
34
    unsigned Offset2 = State.AllocateStack(8, 8);
1836
34
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
1837
34
    return false;
1838
34
  }
1839
0
1840
0
  return true;  // CC didn't match.
1841
0
}
1842
1843
1844
static bool CC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
1845
                                  MVT LocVT, CCValAssign::LocInfo LocInfo,
1846
197
                                  ISD::ArgFlagsTy ArgFlags, CCState &State) {
1847
197
1848
197
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
1849
197
    if (ArgFlags.isByVal()) {
1850
0
      State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
1851
0
      return false;
1852
0
    }
1853
197
  }
1854
197
1855
197
  if (ArgFlags.isByVal()) {
1856
0
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
1857
0
    return false;
1858
0
  }
1859
197
1860
197
  if (LocVT == MVT::i1 ||
1861
197
      LocVT == MVT::i8 ||
1862
197
      
LocVT == MVT::i16186
||
1863
197
      
LocVT == MVT::v1i1182
) {
1864
15
    LocVT = MVT::i32;
1865
15
    if (ArgFlags.isSExt())
1866
2
        LocInfo = CCValAssign::SExt;
1867
13
    else if (ArgFlags.isZExt())
1868
0
        LocInfo = CCValAssign::ZExt;
1869
13
    else
1870
13
        LocInfo = CCValAssign::AExt;
1871
15
  }
1872
197
1873
197
  if (LocVT == MVT::v8i1 ||
1874
197
      
LocVT == MVT::v16i1188
||
1875
197
      
LocVT == MVT::v32i1179
) {
1876
24
    LocVT = MVT::i32;
1877
24
    if (ArgFlags.isSExt())
1878
0
        LocInfo = CCValAssign::SExt;
1879
24
    else if (ArgFlags.isZExt())
1880
0
        LocInfo = CCValAssign::ZExt;
1881
24
    else
1882
24
        LocInfo = CCValAssign::AExt;
1883
24
  }
1884
197
1885
197
  if (LocVT == MVT::i32) {
1886
68
    static const MCPhysReg RegList1[] = {
1887
68
      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D
1888
68
    };
1889
68
    if (unsigned Reg = State.AllocateReg(RegList1)) {
1890
66
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1891
66
      return false;
1892
66
    }
1893
131
  }
1894
131
1895
131
  if (LocVT == MVT::i64) {
1896
9
    static const MCPhysReg RegList2[] = {
1897
9
      X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
1898
9
    };
1899
9
    if (unsigned Reg = State.AllocateReg(RegList2)) {
1900
9
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1901
9
      return false;
1902
9
    }
1903
122
  }
1904
122
1905
122
  if (LocVT == MVT::v64i1) {
1906
26
    LocVT = MVT::i64;
1907
26
    if (ArgFlags.isSExt())
1908
0
        LocInfo = CCValAssign::SExt;
1909
26
    else if (ArgFlags.isZExt())
1910
0
        LocInfo = CCValAssign::ZExt;
1911
26
    else
1912
26
        LocInfo = CCValAssign::AExt;
1913
26
  }
1914
122
1915
122
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
1916
122
    if (LocVT == MVT::i64) {
1917
26
      static const MCPhysReg RegList3[] = {
1918
26
        X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
1919
26
      };
1920
26
      if (unsigned Reg = State.AllocateReg(RegList3)) {
1921
22
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1922
22
        return false;
1923
22
      }
1924
100
    }
1925
122
  }
1926
100
1927
100
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
1928
0
    if (LocVT == MVT::i64) {
1929
0
      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
1930
0
            return false;
1931
100
    }
1932
0
  }
1933
100
1934
100
  if (LocVT == MVT::f32 ||
1935
100
      
LocVT == MVT::f6495
||
1936
100
      
LocVT == MVT::f12890
) {
1937
10
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1938
10
      static const MCPhysReg RegList4[] = {
1939
10
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
1940
10
      };
1941
10
      if (unsigned Reg = State.AllocateReg(RegList4)) {
1942
10
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1943
10
        return false;
1944
10
      }
1945
90
    }
1946
10
  }
1947
90
1948
90
  if (LocVT == MVT::f80) {
1949
3
    if (unsigned Reg = State.AllocateReg(X86::FP0)) {
1950
3
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1951
3
      return false;
1952
3
    }
1953
87
  }
1954
87
1955
87
  if (LocVT == MVT::v16i8 ||
1956
87
      LocVT == MVT::v8i16 ||
1957
87
      LocVT == MVT::v4i32 ||
1958
87
      
LocVT == MVT::v2i6482
||
1959
87
      
LocVT == MVT::v4f3282
||
1960
87
      
LocVT == MVT::v2f6446
) {
1961
41
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
1962
41
      static const MCPhysReg RegList5[] = {
1963
41
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
1964
41
      };
1965
41
      if (unsigned Reg = State.AllocateReg(RegList5)) {
1966
33
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1967
33
        return false;
1968
33
      }
1969
54
    }
1970
41
  }
1971
54
1972
54
  if (LocVT == MVT::v32i8 ||
1973
54
      LocVT == MVT::v16i16 ||
1974
54
      LocVT == MVT::v8i32 ||
1975
54
      
LocVT == MVT::v4i6449
||
1976
54
      
LocVT == MVT::v8f3249
||
1977
54
      
LocVT == MVT::v4f6449
) {
1978
5
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
1979
5
      static const MCPhysReg RegList6[] = {
1980
5
        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
1981
5
      };
1982
5
      if (unsigned Reg = State.AllocateReg(RegList6)) {
1983
5
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1984
5
        return false;
1985
5
      }
1986
49
    }
1987
5
  }
1988
49
1989
49
  if (LocVT == MVT::v64i8 ||
1990
49
      LocVT == MVT::v32i16 ||
1991
49
      LocVT == MVT::v16i32 ||
1992
49
      
LocVT == MVT::v8i6444
||
1993
49
      
LocVT == MVT::v16f3244
||
1994
49
      
LocVT == MVT::v8f6420
) {
1995
29
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
1996
29
      static const MCPhysReg RegList7[] = {
1997
29
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
1998
29
      };
1999
29
      if (unsigned Reg = State.AllocateReg(RegList7)) {
2000
27
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2001
27
        return false;
2002
27
      }
2003
22
    }
2004
29
  }
2005
22
2006
22
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2007
22
    if (LocVT == MVT::i32 ||
2008
22
        
LocVT == MVT::i6420
||
2009
22
        
LocVT == MVT::f3216
||
2010
22
        
LocVT == MVT::f6416
) {
2011
6
      unsigned Offset8 = State.AllocateStack(8, 8);
2012
6
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
2013
6
      return false;
2014
6
    }
2015
16
  }
2016
16
2017
16
  if (LocVT == MVT::i32 ||
2018
16
      LocVT == MVT::f32) {
2019
0
    unsigned Offset9 = State.AllocateStack(4, 4);
2020
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
2021
0
    return false;
2022
0
  }
2023
16
2024
16
  if (LocVT == MVT::i64 ||
2025
16
      LocVT == MVT::f64) {
2026
0
    unsigned Offset10 = State.AllocateStack(8, 4);
2027
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
2028
0
    return false;
2029
0
  }
2030
16
2031
16
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2032
16
    if (LocVT == MVT::x86mmx) {
2033
0
      unsigned Offset11 = State.AllocateStack(8, 8);
2034
0
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo));
2035
0
      return false;
2036
0
    }
2037
16
  }
2038
16
2039
16
  if (LocVT == MVT::x86mmx) {
2040
0
    unsigned Offset12 = State.AllocateStack(8, 4);
2041
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo));
2042
0
    return false;
2043
0
  }
2044
16
2045
16
  if (LocVT == MVT::f80 ||
2046
16
      LocVT == MVT::f128) {
2047
0
    unsigned Offset13 = State.AllocateStack(
2048
0
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 
2049
0
      State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
2050
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo));
2051
0
    return false;
2052
0
  }
2053
16
2054
16
  if (LocVT == MVT::v16i8 ||
2055
16
      LocVT == MVT::v8i16 ||
2056
16
      LocVT == MVT::v4i32 ||
2057
16
      LocVT == MVT::v2i64 ||
2058
16
      LocVT == MVT::v4f32 ||
2059
16
      
LocVT == MVT::v2f648
) {
2060
8
    unsigned Offset14 = State.AllocateStack(16, 16);
2061
8
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo));
2062
8
    return false;
2063
8
  }
2064
8
2065
8
  if (LocVT == MVT::v32i8 ||
2066
8
      LocVT == MVT::v16i16 ||
2067
8
      LocVT == MVT::v8i32 ||
2068
8
      LocVT == MVT::v4i64 ||
2069
8
      LocVT == MVT::v8f32 ||
2070
8
      LocVT == MVT::v4f64) {
2071
0
    unsigned Offset15 = State.AllocateStack(32, 32);
2072
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset15, LocVT, LocInfo));
2073
0
    return false;
2074
0
  }
2075
8
2076
8
  if (LocVT == MVT::v64i8 ||
2077
8
      LocVT == MVT::v32i16 ||
2078
8
      LocVT == MVT::v16i32 ||
2079
8
      LocVT == MVT::v8i64 ||
2080
8
      LocVT == MVT::v16f32 ||
2081
8
      
LocVT == MVT::v8f646
) {
2082
2
    unsigned Offset16 = State.AllocateStack(64, 64);
2083
2
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset16, LocVT, LocInfo));
2084
2
    return false;
2085
2
  }
2086
6
2087
6
  return true;  // CC didn't match.
2088
6
}
2089
2090
2091
static bool CC_X86_Win32_VectorCall(unsigned ValNo, MVT ValVT,
2092
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
2093
244
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
2094
244
2095
244
  if (CC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2096
184
    return false;
2097
60
2098
60
  if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2099
60
    return false;
2100
0
2101
0
  return true;  // CC didn't match.
2102
0
}
2103
2104
2105
static bool CC_X86_Win64_C(unsigned ValNo, MVT ValVT,
2106
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
2107
3.17k
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
2108
3.17k
2109
3.17k
  if (ArgFlags.isByVal()) {
2110
9
    LocVT = MVT::i64;
2111
9
    LocInfo = CCValAssign::Indirect;
2112
9
  }
2113
3.17k
2114
3.17k
  if (LocVT == MVT::i1 ||
2115
3.17k
      LocVT == MVT::v1i1) {
2116
0
    LocVT = MVT::i8;
2117
0
    if (ArgFlags.isSExt())
2118
0
        LocInfo = CCValAssign::SExt;
2119
0
    else if (ArgFlags.isZExt())
2120
0
        LocInfo = CCValAssign::ZExt;
2121
0
    else
2122
0
        LocInfo = CCValAssign::AExt;
2123
0
  }
2124
3.17k
2125
3.17k
  if (ArgFlags.isNest()) {
2126
4
    if (unsigned Reg = State.AllocateReg(X86::R10)) {
2127
4
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2128
4
      return false;
2129
4
    }
2130
3.17k
  }
2131
3.17k
2132
3.17k
  if (ArgFlags.isSwiftError()) {
2133
2
    if (LocVT == MVT::i64) {
2134
2
      if (unsigned Reg = State.AllocateReg(X86::R12)) {
2135
2
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2136
2
        return false;
2137
2
      }
2138
3.16k
    }
2139
2
  }
2140
3.16k
2141
3.16k
  if (LocVT == MVT::v16i8 ||
2142
3.16k
      
LocVT == MVT::v8i163.16k
||
2143
3.16k
      
LocVT == MVT::v4i323.16k
||
2144
3.16k
      
LocVT == MVT::v2i643.14k
||
2145
3.16k
      
LocVT == MVT::v4f323.14k
||
2146
3.16k
      
LocVT == MVT::v2f642.82k
) {
2147
632
    LocVT = MVT::i64;
2148
632
    LocInfo = CCValAssign::Indirect;
2149
632
  }
2150
3.16k
2151
3.16k
  if (LocVT == MVT::v32i8 ||
2152
3.16k
      LocVT == MVT::v16i16 ||
2153
3.16k
      LocVT == MVT::v8i32 ||
2154
3.16k
      
LocVT == MVT::v4i643.16k
||
2155
3.16k
      
LocVT == MVT::v8f323.16k
||
2156
3.16k
      
LocVT == MVT::v4f642.99k
) {
2157
331
    LocVT = MVT::i64;
2158
331
    LocInfo = CCValAssign::Indirect;
2159
331
  }
2160
3.16k
2161
3.16k
  if (LocVT == MVT::v64i8 ||
2162
3.16k
      LocVT == MVT::v32i16 ||
2163
3.16k
      LocVT == MVT::v16i32 ||
2164
3.16k
      LocVT == MVT::v16f32 ||
2165
3.16k
      
LocVT == MVT::v8f643.15k
||
2166
3.16k
      
LocVT == MVT::v8i643.15k
) {
2167
14
    LocVT = MVT::i64;
2168
14
    LocInfo = CCValAssign::Indirect;
2169
14
  }
2170
3.16k
2171
3.16k
  if (LocVT == MVT::f80) {
2172
24
    LocVT = MVT::i64;
2173
24
    LocInfo = CCValAssign::Indirect;
2174
24
  }
2175
3.16k
2176
3.16k
  if (LocVT == MVT::x86mmx) {
2177
0
    LocVT = MVT::i64;
2178
0
    LocInfo = CCValAssign::BCvt;
2179
0
  }
2180
3.16k
2181
3.16k
  if (LocVT == MVT::i8) {
2182
43
    static const MCPhysReg RegList1[] = {
2183
43
      X86::CL, X86::DL, X86::R8B, X86::R9B
2184
43
    };
2185
43
    static const MCPhysReg RegList2[] = {
2186
43
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2187
43
    };
2188
43
    if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
2189
39
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2190
39
      return false;
2191
39
    }
2192
3.12k
  }
2193
3.12k
2194
3.12k
  if (LocVT == MVT::i16) {
2195
70
    static const MCPhysReg RegList3[] = {
2196
70
      X86::CX, X86::DX, X86::R8W, X86::R9W
2197
70
    };
2198
70
    static const MCPhysReg RegList4[] = {
2199
70
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2200
70
    };
2201
70
    if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
2202
50
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2203
50
      return false;
2204
50
    }
2205
3.07k
  }
2206
3.07k
2207
3.07k
  if (LocVT == MVT::i32) {
2208
722
    static const MCPhysReg RegList5[] = {
2209
722
      X86::ECX, X86::EDX, X86::R8D, X86::R9D
2210
722
    };
2211
722
    static const MCPhysReg RegList6[] = {
2212
722
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2213
722
    };
2214
722
    if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) {
2215
631
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2216
631
      return false;
2217
631
    }
2218
2.44k
  }
2219
2.44k
2220
2.44k
  if (State.getCallingConv() == CallingConv::X86_ThisCall) {
2221
14
    if (ArgFlags.isSRet()) {
2222
0
      if (LocVT == MVT::i64) {
2223
0
        static const MCPhysReg RegList7[] = {
2224
0
          X86::RDX, X86::R8, X86::R9
2225
0
        };
2226
0
        static const MCPhysReg RegList8[] = {
2227
0
          X86::XMM1, X86::XMM2, X86::XMM3
2228
0
        };
2229
0
        if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
2230
0
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2231
0
          return false;
2232
0
        }
2233
2.44k
      }
2234
0
    }
2235
14
  }
2236
2.44k
2237
2.44k
  if (LocVT == MVT::i64) {
2238
2.18k
    static const MCPhysReg RegList9[] = {
2239
2.18k
      X86::RCX, X86::RDX, X86::R8, X86::R9
2240
2.18k
    };
2241
2.18k
    static const MCPhysReg RegList10[] = {
2242
2.18k
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2243
2.18k
    };
2244
2.18k
    if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) {
2245
2.09k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2246
2.09k
      return false;
2247
2.09k
    }
2248
356
  }
2249
356
2250
356
  if (LocVT == MVT::f32 ||
2251
356
      
LocVT == MVT::f64282
||
2252
356
      
LocVT == MVT::v16i8224
||
2253
356
      
LocVT == MVT::v8i16224
||
2254
356
      
LocVT == MVT::v4i32224
||
2255
356
      
LocVT == MVT::v2i64224
||
2256
356
      
LocVT == MVT::v4f32224
||
2257
356
      
LocVT == MVT::v2f64224
) {
2258
132
    static const MCPhysReg RegList11[] = {
2259
132
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2260
132
    };
2261
132
    static const MCPhysReg RegList12[] = {
2262
132
      X86::RCX, X86::RDX, X86::R8, X86::R9
2263
132
    };
2264
132
    if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) {
2265
109
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2266
109
      return false;
2267
109
    }
2268
247
  }
2269
247
2270
247
  if (LocVT == MVT::i8 ||
2271
247
      
LocVT == MVT::i16243
||
2272
247
      
LocVT == MVT::i32223
||
2273
247
      
LocVT == MVT::i64132
||
2274
247
      
LocVT == MVT::f3235
||
2275
247
      
LocVT == MVT::f6419
) {
2276
235
    unsigned Offset13 = State.AllocateStack(8, 8);
2277
235
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo));
2278
235
    return false;
2279
235
  }
2280
12
2281
12
  return true;  // CC didn't match.
2282
12
}
2283
2284
2285
static bool CC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
2286
                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
2287
204
                                 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2288
204
2289
204
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2290
204
    if (ArgFlags.isByVal()) {
2291
0
      State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
2292
0
      return false;
2293
0
    }
2294
204
  }
2295
204
2296
204
  if (ArgFlags.isByVal()) {
2297
0
    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
2298
0
    return false;
2299
0
  }
2300
204
2301
204
  if (LocVT == MVT::i1 ||
2302
204
      LocVT == MVT::i8 ||
2303
204
      
LocVT == MVT::i16193
||
2304
204
      
LocVT == MVT::v1i1189
) {
2305
15
    LocVT = MVT::i32;
2306
15
    if (ArgFlags.isSExt())
2307
2
        LocInfo = CCValAssign::SExt;
2308
13
    else if (ArgFlags.isZExt())
2309
0
        LocInfo = CCValAssign::ZExt;
2310
13
    else
2311
13
        LocInfo = CCValAssign::AExt;
2312
15
  }
2313
204
2314
204
  if (LocVT == MVT::v8i1 ||
2315
204
      
LocVT == MVT::v16i1195
||
2316
204
      
LocVT == MVT::v32i1186
) {
2317
24
    LocVT = MVT::i32;
2318
24
    if (ArgFlags.isSExt())
2319
0
        LocInfo = CCValAssign::SExt;
2320
24
    else if (ArgFlags.isZExt())
2321
0
        LocInfo = CCValAssign::ZExt;
2322
24
    else
2323
24
        LocInfo = CCValAssign::AExt;
2324
24
  }
2325
204
2326
204
  if (LocVT == MVT::i32) {
2327
78
    static const MCPhysReg RegList1[] = {
2328
78
      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
2329
78
    };
2330
78
    if (unsigned Reg = State.AllocateReg(RegList1)) {
2331
78
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2332
78
      return false;
2333
78
    }
2334
126
  }
2335
126
2336
126
  if (LocVT == MVT::i64) {
2337
9
    static const MCPhysReg RegList2[] = {
2338
9
      X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
2339
9
    };
2340
9
    if (unsigned Reg = State.AllocateReg(RegList2)) {
2341
9
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2342
9
      return false;
2343
9
    }
2344
117
  }
2345
117
2346
117
  if (LocVT == MVT::v64i1) {
2347
26
    LocVT = MVT::i64;
2348
26
    if (ArgFlags.isSExt())
2349
0
        LocInfo = CCValAssign::SExt;
2350
26
    else if (ArgFlags.isZExt())
2351
0
        LocInfo = CCValAssign::ZExt;
2352
26
    else
2353
26
        LocInfo = CCValAssign::AExt;
2354
26
  }
2355
117
2356
117
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2357
117
    if (LocVT == MVT::i64) {
2358
26
      static const MCPhysReg RegList3[] = {
2359
26
        X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
2360
26
      };
2361
26
      if (unsigned Reg = State.AllocateReg(RegList3)) {
2362
24
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2363
24
        return false;
2364
24
      }
2365
93
    }
2366
117
  }
2367
93
2368
93
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
2369
0
    if (LocVT == MVT::i64) {
2370
0
      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2371
0
            return false;
2372
93
    }
2373
0
  }
2374
93
2375
93
  if (LocVT == MVT::f32 ||
2376
93
      
LocVT == MVT::f6488
||
2377
93
      
LocVT == MVT::f12883
) {
2378
10
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
2379
10
      static const MCPhysReg RegList4[] = {
2380
10
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2381
10
      };
2382
10
      if (unsigned Reg = State.AllocateReg(RegList4)) {
2383
10
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2384
10
        return false;
2385
10
      }
2386
83
    }
2387
10
  }
2388
83
2389
83
  if (LocVT == MVT::f80) {
2390
3
    if (unsigned Reg = State.AllocateReg(X86::FP0)) {
2391
3
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2392
3
      return false;
2393
3
    }
2394
80
  }
2395
80
2396
80
  if (LocVT == MVT::v16i8 ||
2397
80
      LocVT == MVT::v8i16 ||
2398
80
      LocVT == MVT::v4i32 ||
2399
80
      
LocVT == MVT::v2i6475
||
2400
80
      
LocVT == MVT::v4f3275
||
2401
80
      
LocVT == MVT::v2f6439
) {
2402
41
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
2403
41
      static const MCPhysReg RegList5[] = {
2404
41
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
2405
41
      };
2406
41
      if (unsigned Reg = State.AllocateReg(RegList5)) {
2407
33
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2408
33
        return false;
2409
33
      }
2410
47
    }
2411
41
  }
2412
47
2413
47
  if (LocVT == MVT::v32i8 ||
2414
47
      LocVT == MVT::v16i16 ||
2415
47
      LocVT == MVT::v8i32 ||
2416
47
      
LocVT == MVT::v4i6442
||
2417
47
      
LocVT == MVT::v8f3242
||
2418
47
      
LocVT == MVT::v4f6442
) {
2419
5
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
2420
5
      static const MCPhysReg RegList6[] = {
2421
5
        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
2422
5
      };
2423
5
      if (unsigned Reg = State.AllocateReg(RegList6)) {
2424
5
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2425
5
        return false;
2426
5
      }
2427
42
    }
2428
5
  }
2429
42
2430
42
  if (LocVT == MVT::v64i8 ||
2431
42
      LocVT == MVT::v32i16 ||
2432
42
      LocVT == MVT::v16i32 ||
2433
42
      
LocVT == MVT::v8i6437
||
2434
42
      
LocVT == MVT::v16f3237
||
2435
42
      
LocVT == MVT::v8f6413
) {
2436
29
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
2437
29
      static const MCPhysReg RegList7[] = {
2438
29
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
2439
29
      };
2440
29
      if (unsigned Reg = State.AllocateReg(RegList7)) {
2441
27
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2442
27
        return false;
2443
27
      }
2444
15
    }
2445
29
  }
2446
15
2447
15
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2448
15
    if (LocVT == MVT::i32 ||
2449
15
        LocVT == MVT::i64 ||
2450
15
        
LocVT == MVT::f3213
||
2451
15
        
LocVT == MVT::f6413
) {
2452
2
      unsigned Offset8 = State.AllocateStack(8, 8);
2453
2
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
2454
2
      return false;
2455
2
    }
2456
13
  }
2457
13
2458
13
  if (LocVT == MVT::i32 ||
2459
13
      LocVT == MVT::f32) {
2460
0
    unsigned Offset9 = State.AllocateStack(4, 4);
2461
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo));
2462
0
    return false;
2463
0
  }
2464
13
2465
13
  if (LocVT == MVT::i64 ||
2466
13
      LocVT == MVT::f64) {
2467
0
    unsigned Offset10 = State.AllocateStack(8, 4);
2468
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo));
2469
0
    return false;
2470
0
  }
2471
13
2472
13
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2473
13
    if (LocVT == MVT::x86mmx) {
2474
0
      unsigned Offset11 = State.AllocateStack(8, 8);
2475
0
      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo));
2476
0
      return false;
2477
0
    }
2478
13
  }
2479
13
2480
13
  if (LocVT == MVT::x86mmx) {
2481
0
    unsigned Offset12 = State.AllocateStack(8, 4);
2482
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo));
2483
0
    return false;
2484
0
  }
2485
13
2486
13
  if (LocVT == MVT::f80 ||
2487
13
      LocVT == MVT::f128) {
2488
0
    unsigned Offset13 = State.AllocateStack(
2489
0
      State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 
2490
0
      State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext())));
2491
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo));
2492
0
    return false;
2493
0
  }
2494
13
2495
13
  if (LocVT == MVT::v16i8 ||
2496
13
      LocVT == MVT::v8i16 ||
2497
13
      LocVT == MVT::v4i32 ||
2498
13
      LocVT == MVT::v2i64 ||
2499
13
      LocVT == MVT::v4f32 ||
2500
13
      
LocVT == MVT::v2f645
) {
2501
8
    unsigned Offset14 = State.AllocateStack(16, 16);
2502
8
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo));
2503
8
    return false;
2504
8
  }
2505
5
2506
5
  if (LocVT == MVT::v32i8 ||
2507
5
      LocVT == MVT::v16i16 ||
2508
5
      LocVT == MVT::v8i32 ||
2509
5
      LocVT == MVT::v4i64 ||
2510
5
      LocVT == MVT::v8f32 ||
2511
5
      LocVT == MVT::v4f64) {
2512
0
    unsigned Offset15 = State.AllocateStack(32, 32);
2513
0
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset15, LocVT, LocInfo));
2514
0
    return false;
2515
0
  }
2516
5
2517
5
  if (LocVT == MVT::v64i8 ||
2518
5
      LocVT == MVT::v32i16 ||
2519
5
      LocVT == MVT::v16i32 ||
2520
5
      LocVT == MVT::v8i64 ||
2521
5
      LocVT == MVT::v16f32 ||
2522
5
      
LocVT == MVT::v8f643
) {
2523
2
    unsigned Offset16 = State.AllocateStack(64, 64);
2524
2
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset16, LocVT, LocInfo));
2525
2
    return false;
2526
2
  }
2527
3
2528
3
  return true;  // CC didn't match.
2529
3
}
2530
2531
2532
static bool CC_X86_Win64_VectorCall(unsigned ValNo, MVT ValVT,
2533
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
2534
180
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
2535
180
2536
180
  if (CC_X86_64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2537
161
    return false;
2538
19
2539
19
  if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2540
19
    return false;
2541
0
2542
0
  return true;  // CC didn't match.
2543
0
}
2544
2545
2546
static bool RetCC_Intel_OCL_BI(unsigned ValNo, MVT ValVT,
2547
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
2548
240
                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
2549
240
2550
240
  if (LocVT == MVT::f32 ||
2551
240
      LocVT == MVT::f64 ||
2552
240
      LocVT == MVT::v4i32 ||
2553
240
      LocVT == MVT::v2i64 ||
2554
240
      LocVT == MVT::v4f32 ||
2555
240
      
LocVT == MVT::v2f64152
) {
2556
88
    static const MCPhysReg RegList1[] = {
2557
88
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2558
88
    };
2559
88
    if (unsigned Reg = State.AllocateReg(RegList1)) {
2560
88
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2561
88
      return false;
2562
88
    }
2563
152
  }
2564
152
2565
152
  if (LocVT == MVT::v8f32 ||
2566
152
      
LocVT == MVT::v4f64104
||
2567
152
      
LocVT == MVT::v8i32104
||
2568
152
      
LocVT == MVT::v4i64104
) {
2569
48
    static const MCPhysReg RegList2[] = {
2570
48
      X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
2571
48
    };
2572
48
    if (unsigned Reg = State.AllocateReg(RegList2)) {
2573
48
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2574
48
      return false;
2575
48
    }
2576
104
  }
2577
104
2578
104
  if (LocVT == MVT::v16f32 ||
2579
104
      
LocVT == MVT::v8f648
||
2580
104
      
LocVT == MVT::v16i328
||
2581
104
      
LocVT == MVT::v8i648
) {
2582
96
    static const MCPhysReg RegList3[] = {
2583
96
      X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
2584
96
    };
2585
96
    if (unsigned Reg = State.AllocateReg(RegList3)) {
2586
96
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2587
96
      return false;
2588
96
    }
2589
8
  }
2590
8
2591
8
  if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2592
8
    return false;
2593
0
2594
0
  return true;  // CC didn't match.
2595
0
}
2596
2597
2598
bool llvm::RetCC_X86(unsigned ValNo, MVT ValVT,
2599
                     MVT LocVT, CCValAssign::LocInfo LocInfo,
2600
369k
                     ISD::ArgFlagsTy ArgFlags, CCState &State) {
2601
369k
2602
369k
  if (State.getCallingConv() == CallingConv::Intel_OCL_BI) {
2603
240
    if (!RetCC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2604
240
      return false;
2605
368k
  }
2606
368k
2607
368k
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
2608
299k
    if (!RetCC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2609
298k
      return false;
2610
70.0k
  }
2611
70.0k
2612
70.0k
  if (!RetCC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2613
69.2k
    return false;
2614
873
2615
873
  return true;  // CC didn't match.
2616
873
}
2617
2618
2619
static bool RetCC_X86Common(unsigned ValNo, MVT ValVT,
2620
                            MVT LocVT, CCValAssign::LocInfo LocInfo,
2621
353k
                            ISD::ArgFlagsTy ArgFlags, CCState &State) {
2622
353k
2623
353k
  if (LocVT == MVT::v1i1) {
2624
6
    LocVT = MVT::i8;
2625
6
    if (ArgFlags.isSExt())
2626
0
        LocInfo = CCValAssign::SExt;
2627
6
    else if (ArgFlags.isZExt())
2628
0
        LocInfo = CCValAssign::ZExt;
2629
6
    else
2630
6
        LocInfo = CCValAssign::AExt;
2631
6
  }
2632
353k
2633
353k
  if (LocVT == MVT::i1) {
2634
13
    LocVT = MVT::i8;
2635
13
    if (ArgFlags.isSExt())
2636
0
        LocInfo = CCValAssign::SExt;
2637
13
    else if (ArgFlags.isZExt())
2638
0
        LocInfo = CCValAssign::ZExt;
2639
13
    else
2640
13
        LocInfo = CCValAssign::AExt;
2641
13
  }
2642
353k
2643
353k
  if (LocVT == MVT::i8) {
2644
20.1k
    static const MCPhysReg RegList1[] = {
2645
20.1k
      X86::AL, X86::DL, X86::CL
2646
20.1k
    };
2647
20.1k
    if (unsigned Reg = State.AllocateReg(RegList1)) {
2648
20.0k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2649
20.0k
      return false;
2650
20.0k
    }
2651
333k
  }
2652
333k
2653
333k
  if (LocVT == MVT::i16) {
2654
5.25k
    static const MCPhysReg RegList2[] = {
2655
5.25k
      X86::AX, X86::DX, X86::CX
2656
5.25k
    };
2657
5.25k
    if (unsigned Reg = State.AllocateReg(RegList2)) {
2658
5.21k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2659
5.21k
      return false;
2660
5.21k
    }
2661
328k
  }
2662
328k
2663
328k
  if (LocVT == MVT::i32) {
2664
87.4k
    static const MCPhysReg RegList3[] = {
2665
87.4k
      X86::EAX, X86::EDX, X86::ECX
2666
87.4k
    };
2667
87.4k
    if (unsigned Reg = State.AllocateReg(RegList3)) {
2668
87.0k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2669
87.0k
      return false;
2670
87.0k
    }
2671
241k
  }
2672
241k
2673
241k
  if (LocVT == MVT::i64) {
2674
91.1k
    static const MCPhysReg RegList4[] = {
2675
91.1k
      X86::RAX, X86::RDX, X86::RCX
2676
91.1k
    };
2677
91.1k
    if (unsigned Reg = State.AllocateReg(RegList4)) {
2678
90.9k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2679
90.9k
      return false;
2680
90.9k
    }
2681
150k
  }
2682
150k
2683
150k
  if (LocVT == MVT::v2i1) {
2684
28
    LocVT = MVT::v2i64;
2685
28
    if (ArgFlags.isSExt())
2686
0
        LocInfo = CCValAssign::SExt;
2687
28
    else if (ArgFlags.isZExt())
2688
0
        LocInfo = CCValAssign::ZExt;
2689
28
    else
2690
28
        LocInfo = CCValAssign::AExt;
2691
28
  }
2692
150k
2693
150k
  if (LocVT == MVT::v4i1) {
2694
77
    LocVT = MVT::v4i32;
2695
77
    if (ArgFlags.isSExt())
2696
0
        LocInfo = CCValAssign::SExt;
2697
77
    else if (ArgFlags.isZExt())
2698
0
        LocInfo = CCValAssign::ZExt;
2699
77
    else
2700
77
        LocInfo = CCValAssign::AExt;
2701
77
  }
2702
150k
2703
150k
  if (LocVT == MVT::v8i1) {
2704
108
    LocVT = MVT::v8i16;
2705
108
    if (ArgFlags.isSExt())
2706
0
        LocInfo = CCValAssign::SExt;
2707
108
    else if (ArgFlags.isZExt())
2708
0
        LocInfo = CCValAssign::ZExt;
2709
108
    else
2710
108
        LocInfo = CCValAssign::AExt;
2711
108
  }
2712
150k
2713
150k
  if (LocVT == MVT::v16i1) {
2714
156
    LocVT = MVT::v16i8;
2715
156
    if (ArgFlags.isSExt())
2716
0
        LocInfo = CCValAssign::SExt;
2717
156
    else if (ArgFlags.isZExt())
2718
0
        LocInfo = CCValAssign::ZExt;
2719
156
    else
2720
156
        LocInfo = CCValAssign::AExt;
2721
156
  }
2722
150k
2723
150k
  if (LocVT == MVT::v32i1) {
2724
30
    LocVT = MVT::v32i8;
2725
30
    if (ArgFlags.isSExt())
2726
0
        LocInfo = CCValAssign::SExt;
2727
30
    else if (ArgFlags.isZExt())
2728
0
        LocInfo = CCValAssign::ZExt;
2729
30
    else
2730
30
        LocInfo = CCValAssign::AExt;
2731
30
  }
2732
150k
2733
150k
  if (LocVT == MVT::v64i1) {
2734
20
    LocVT = MVT::v64i8;
2735
20
    if (ArgFlags.isSExt())
2736
0
        LocInfo = CCValAssign::SExt;
2737
20
    else if (ArgFlags.isZExt())
2738
0
        LocInfo = CCValAssign::ZExt;
2739
20
    else
2740
20
        LocInfo = CCValAssign::AExt;
2741
20
  }
2742
150k
2743
150k
  if (LocVT == MVT::v16i8 ||
2744
150k
      
LocVT == MVT::v8i16138k
||
2745
150k
      
LocVT == MVT::v4i32123k
||
2746
150k
      
LocVT == MVT::v2i64104k
||
2747
150k
      
LocVT == MVT::v4f3288.5k
||
2748
150k
      
LocVT == MVT::v2f6473.1k
) {
2749
87.2k
    static const MCPhysReg RegList5[] = {
2750
87.2k
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
2751
87.2k
    };
2752
87.2k
    if (unsigned Reg = State.AllocateReg(RegList5)) {
2753
87.0k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2754
87.0k
      return false;
2755
87.0k
    }
2756
63.2k
  }
2757
63.2k
2758
63.2k
  if (LocVT == MVT::v32i8 ||
2759
63.2k
      
LocVT == MVT::v16i1656.5k
||
2760
63.2k
      
LocVT == MVT::v8i3248.7k
||
2761
63.2k
      
LocVT == MVT::v4i6441.3k
||
2762
63.2k
      
LocVT == MVT::v8f3234.0k
||
2763
63.2k
      
LocVT == MVT::v4f6426.8k
) {
2764
42.3k
    static const MCPhysReg RegList6[] = {
2765
42.3k
      X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
2766
42.3k
    };
2767
42.3k
    if (unsigned Reg = State.AllocateReg(RegList6)) {
2768
42.3k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2769
42.3k
      return false;
2770
42.3k
    }
2771
20.8k
  }
2772
20.8k
2773
20.8k
  if (LocVT == MVT::v64i8 ||
2774
20.8k
      
LocVT == MVT::v32i1619.6k
||
2775
20.8k
      
LocVT == MVT::v16i3217.8k
||
2776
20.8k
      
LocVT == MVT::v8i6414.8k
||
2777
20.8k
      
LocVT == MVT::v16f3210.8k
||
2778
20.8k
      
LocVT == MVT::v8f646.72k
) {
2779
18.3k
    static const MCPhysReg RegList7[] = {
2780
18.3k
      X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
2781
18.3k
    };
2782
18.3k
    if (unsigned Reg = State.AllocateReg(RegList7)) {
2783
18.3k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2784
18.3k
      return false;
2785
18.3k
    }
2786
2.57k
  }
2787
2.57k
2788
2.57k
  if (LocVT == MVT::x86mmx) {
2789
6
    if (unsigned Reg = State.AllocateReg(X86::MM0)) {
2790
6
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2791
6
      return false;
2792
6
    }
2793
2.57k
  }
2794
2.57k
2795
2.57k
  if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
2796
2.52k
    if (LocVT == MVT::f80) {
2797
1.28k
      static const MCPhysReg RegList8[] = {
2798
1.28k
        X86::FP0, X86::FP1
2799
1.28k
      };
2800
1.28k
      if (unsigned Reg = State.AllocateReg(RegList8)) {
2801
1.28k
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2802
1.28k
        return false;
2803
1.28k
      }
2804
1.28k
    }
2805
2.52k
  }
2806
1.28k
2807
1.28k
  return true;  // CC didn't match.
2808
1.28k
}
2809
2810
2811
static bool RetCC_X86_32(unsigned ValNo, MVT ValVT,
2812
                         MVT LocVT, CCValAssign::LocInfo LocInfo,
2813
70.0k
                         ISD::ArgFlagsTy ArgFlags, CCState &State) {
2814
70.0k
2815
70.0k
  if (State.getCallingConv() == CallingConv::Fast) {
2816
994
    if (!RetCC_X86_32_Fast(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2817
974
      return false;
2818
69.1k
  }
2819
69.1k
2820
69.1k
  if (State.getCallingConv() == CallingConv::HiPE) {
2821
30
    if (!RetCC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2822
30
      return false;
2823
69.0k
  }
2824
69.0k
2825
69.0k
  if (State.getCallingConv() == CallingConv::X86_VectorCall) {
2826
84
    if (!RetCC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2827
80
      return false;
2828
68.9k
  }
2829
68.9k
2830
68.9k
  if (State.getCallingConv() == CallingConv::X86_RegCall) {
2831
178
    if (!RetCC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2832
178
      return false;
2833
68.8k
  }
2834
68.8k
2835
68.8k
  if (!RetCC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2836
67.9k
    return false;
2837
869
2838
869
  return true;  // CC didn't match.
2839
869
}
2840
2841
2842
static bool RetCC_X86_32_C(unsigned ValNo, MVT ValVT,
2843
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
2844
68.8k
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
2845
68.8k
2846
68.8k
  if (ArgFlags.isInReg()) {
2847
24
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
2848
8
      if (LocVT == MVT::f32 ||
2849
8
          
LocVT == MVT::f644
) {
2850
8
        static const MCPhysReg RegList1[] = {
2851
8
          X86::XMM0, X86::XMM1, X86::XMM2
2852
8
        };
2853
8
        if (unsigned Reg = State.AllocateReg(RegList1)) {
2854
8
          State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2855
8
          return false;
2856
8
        }
2857
68.8k
      }
2858
8
    }
2859
24
  }
2860
68.8k
2861
68.8k
  if (LocVT == MVT::f32 ||
2862
68.8k
      
LocVT == MVT::f6467.3k
) {
2863
3.01k
    static const MCPhysReg RegList2[] = {
2864
3.01k
      X86::FP0, X86::FP1
2865
3.01k
    };
2866
3.01k
    if (unsigned Reg = State.AllocateReg(RegList2)) {
2867
2.84k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2868
2.84k
      return false;
2869
2.84k
    }
2870
65.9k
  }
2871
65.9k
2872
65.9k
  if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2873
65.0k
    return false;
2874
869
2875
869
  return true;  // CC didn't match.
2876
869
}
2877
2878
2879
static bool RetCC_X86_32_Fast(unsigned ValNo, MVT ValVT,
2880
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
2881
994
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
2882
994
2883
994
  if (LocVT == MVT::f32) {
2884
2
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
2885
2
      static const MCPhysReg RegList1[] = {
2886
2
        X86::XMM0, X86::XMM1, X86::XMM2
2887
2
      };
2888
2
      if (unsigned Reg = State.AllocateReg(RegList1)) {
2889
2
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2890
2
        return false;
2891
2
      }
2892
992
    }
2893
2
  }
2894
992
2895
992
  if (LocVT == MVT::f64) {
2896
25
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) {
2897
17
      static const MCPhysReg RegList2[] = {
2898
17
        X86::XMM0, X86::XMM1, X86::XMM2
2899
17
      };
2900
17
      if (unsigned Reg = State.AllocateReg(RegList2)) {
2901
11
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2902
11
        return false;
2903
11
      }
2904
981
    }
2905
25
  }
2906
981
2907
981
  if (LocVT == MVT::i8) {
2908
307
    static const MCPhysReg RegList3[] = {
2909
307
      X86::AL, X86::DL, X86::CL
2910
307
    };
2911
307
    if (unsigned Reg = State.AllocateReg(RegList3)) {
2912
307
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2913
307
      return false;
2914
307
    }
2915
674
  }
2916
674
2917
674
  if (LocVT == MVT::i16) {
2918
0
    static const MCPhysReg RegList4[] = {
2919
0
      X86::AX, X86::DX, X86::CX
2920
0
    };
2921
0
    if (unsigned Reg = State.AllocateReg(RegList4)) {
2922
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2923
0
      return false;
2924
0
    }
2925
674
  }
2926
674
2927
674
  if (LocVT == MVT::i32) {
2928
655
    static const MCPhysReg RegList5[] = {
2929
655
      X86::EAX, X86::EDX, X86::ECX
2930
655
    };
2931
655
    if (unsigned Reg = State.AllocateReg(RegList5)) {
2932
650
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2933
650
      return false;
2934
650
    }
2935
24
  }
2936
24
2937
24
  if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
2938
4
    return false;
2939
20
2940
20
  return true;  // CC didn't match.
2941
20
}
2942
2943
2944
static bool RetCC_X86_32_HiPE(unsigned ValNo, MVT ValVT,
2945
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
2946
30
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
2947
30
2948
30
  if (LocVT == MVT::i8 ||
2949
30
      LocVT == MVT::i16) {
2950
0
    LocVT = MVT::i32;
2951
0
    if (ArgFlags.isSExt())
2952
0
        LocInfo = CCValAssign::SExt;
2953
0
    else if (ArgFlags.isZExt())
2954
0
        LocInfo = CCValAssign::ZExt;
2955
0
    else
2956
0
        LocInfo = CCValAssign::AExt;
2957
0
  }
2958
30
2959
30
  if (LocVT == MVT::i32) {
2960
30
    static const MCPhysReg RegList1[] = {
2961
30
      X86::ESI, X86::EBP, X86::EAX, X86::EDX
2962
30
    };
2963
30
    if (unsigned Reg = State.AllocateReg(RegList1)) {
2964
30
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2965
30
      return false;
2966
30
    }
2967
0
  }
2968
0
2969
0
  return true;  // CC didn't match.
2970
0
}
2971
2972
2973
static bool RetCC_X86_32_RegCall(unsigned ValNo, MVT ValVT,
2974
                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
2975
178
                                 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2976
178
2977
178
  if (LocVT == MVT::i1 ||
2978
178
      LocVT == MVT::v1i1 ||
2979
178
      LocVT == MVT::v8i1) {
2980
4
    LocVT = MVT::i8;
2981
4
    if (ArgFlags.isSExt())
2982
0
        LocInfo = CCValAssign::SExt;
2983
4
    else if (ArgFlags.isZExt())
2984
0
        LocInfo = CCValAssign::ZExt;
2985
4
    else
2986
4
        LocInfo = CCValAssign::AExt;
2987
4
  }
2988
178
2989
178
  if (LocVT == MVT::v16i1) {
2990
4
    LocVT = MVT::i16;
2991
4
    if (ArgFlags.isSExt())
2992
0
        LocInfo = CCValAssign::SExt;
2993
4
    else if (ArgFlags.isZExt())
2994
0
        LocInfo = CCValAssign::ZExt;
2995
4
    else
2996
4
        LocInfo = CCValAssign::AExt;
2997
4
  }
2998
178
2999
178
  if (LocVT == MVT::v32i1) {
3000
4
    LocVT = MVT::i32;
3001
4
    if (ArgFlags.isSExt())
3002
0
        LocInfo = CCValAssign::SExt;
3003
4
    else if (ArgFlags.isZExt())
3004
0
        LocInfo = CCValAssign::ZExt;
3005
4
    else
3006
4
        LocInfo = CCValAssign::AExt;
3007
4
  }
3008
178
3009
178
  if (LocVT == MVT::i8) {
3010
28
    static const MCPhysReg RegList1[] = {
3011
28
      X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL
3012
28
    };
3013
28
    if (unsigned Reg = State.AllocateReg(RegList1)) {
3014
28
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3015
28
      return false;
3016
28
    }
3017
150
  }
3018
150
3019
150
  if (LocVT == MVT::i16) {
3020
14
    static const MCPhysReg RegList2[] = {
3021
14
      X86::AX, X86::CX, X86::DX, X86::DI, X86::SI
3022
14
    };
3023
14
    if (unsigned Reg = State.AllocateReg(RegList2)) {
3024
14
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3025
14
      return false;
3026
14
    }
3027
136
  }
3028
136
3029
136
  if (LocVT == MVT::i32) {
3030
60
    static const MCPhysReg RegList3[] = {
3031
60
      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI
3032
60
    };
3033
60
    if (unsigned Reg = State.AllocateReg(RegList3)) {
3034
60
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3035
60
      return false;
3036
60
    }
3037
76
  }
3038
76
3039
76
  if (LocVT == MVT::i64) {
3040
0
    if (unsigned Reg = State.AllocateReg(X86::RAX)) {
3041
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3042
0
      return false;
3043
0
    }
3044
76
  }
3045
76
3046
76
  if (LocVT == MVT::v64i1) {
3047
4
    LocVT = MVT::i64;
3048
4
    if (ArgFlags.isSExt())
3049
0
        LocInfo = CCValAssign::SExt;
3050
4
    else if (ArgFlags.isZExt())
3051
0
        LocInfo = CCValAssign::ZExt;
3052
4
    else
3053
4
        LocInfo = CCValAssign::AExt;
3054
4
  }
3055
76
3056
76
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
3057
0
    if (LocVT == MVT::i64) {
3058
0
      if (unsigned Reg = State.AllocateReg(X86::RAX)) {
3059
0
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3060
0
        return false;
3061
0
      }
3062
76
    }
3063
0
  }
3064
76
3065
76
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
3066
76
    if (LocVT == MVT::i64) {
3067
4
      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3068
4
            return false;
3069
72
    }
3070
76
  }
3071
72
3072
72
  if (LocVT == MVT::f80) {
3073
6
    static const MCPhysReg RegList4[] = {
3074
6
      X86::FP0, X86::FP1
3075
6
    };
3076
6
    if (unsigned Reg = State.AllocateReg(RegList4)) {
3077
6
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3078
6
      return false;
3079
6
    }
3080
66
  }
3081
66
3082
66
  if (LocVT == MVT::f32 ||
3083
66
      
LocVT == MVT::f6458
||
3084
66
      
LocVT == MVT::f12850
) {
3085
16
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3086
16
      static const MCPhysReg RegList5[] = {
3087
16
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3088
16
      };
3089
16
      if (unsigned Reg = State.AllocateReg(RegList5)) {
3090
16
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3091
16
        return false;
3092
16
      }
3093
50
    }
3094
16
  }
3095
50
3096
50
  if (LocVT == MVT::v16i8 ||
3097
50
      LocVT == MVT::v8i16 ||
3098
50
      LocVT == MVT::v4i32 ||
3099
50
      
LocVT == MVT::v2i6444
||
3100
50
      
LocVT == MVT::v4f3244
||
3101
50
      
LocVT == MVT::v2f6420
) {
3102
30
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3103
30
      static const MCPhysReg RegList6[] = {
3104
30
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3105
30
      };
3106
30
      if (unsigned Reg = State.AllocateReg(RegList6)) {
3107
30
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3108
30
        return false;
3109
30
      }
3110
20
    }
3111
30
  }
3112
20
3113
20
  if (LocVT == MVT::v32i8 ||
3114
20
      LocVT == MVT::v16i16 ||
3115
20
      LocVT == MVT::v8i32 ||
3116
20
      
LocVT == MVT::v4i6414
||
3117
20
      
LocVT == MVT::v8f3214
||
3118
20
      
LocVT == MVT::v4f6414
) {
3119
6
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
3120
6
      static const MCPhysReg RegList7[] = {
3121
6
        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7
3122
6
      };
3123
6
      if (unsigned Reg = State.AllocateReg(RegList7)) {
3124
6
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3125
6
        return false;
3126
6
      }
3127
14
    }
3128
6
  }
3129
14
3130
14
  if (LocVT == MVT::v64i8 ||
3131
14
      LocVT == MVT::v32i16 ||
3132
14
      LocVT == MVT::v16i32 ||
3133
14
      
LocVT == MVT::v8i648
||
3134
14
      
LocVT == MVT::v16f328
||
3135
14
      
LocVT == MVT::v8f640
) {
3136
14
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
3137
14
      static const MCPhysReg RegList8[] = {
3138
14
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7
3139
14
      };
3140
14
      if (unsigned Reg = State.AllocateReg(RegList8)) {
3141
14
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3142
14
        return false;
3143
14
      }
3144
0
    }
3145
14
  }
3146
0
3147
0
  return true;  // CC didn't match.
3148
0
}
3149
3150
3151
static bool RetCC_X86_32_VectorCall(unsigned ValNo, MVT ValVT,
3152
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
3153
84
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
3154
84
3155
84
  if (LocVT == MVT::f32 ||
3156
84
      LocVT == MVT::f64 ||
3157
84
      
LocVT == MVT::f12856
) {
3158
28
    static const MCPhysReg RegList1[] = {
3159
28
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3160
28
    };
3161
28
    if (unsigned Reg = State.AllocateReg(RegList1)) {
3162
24
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3163
24
      return false;
3164
24
    }
3165
60
  }
3166
60
3167
60
  if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3168
56
    return false;
3169
4
3170
4
  return true;  // CC didn't match.
3171
4
}
3172
3173
3174
static bool RetCC_X86_64(unsigned ValNo, MVT ValVT,
3175
                         MVT LocVT, CCValAssign::LocInfo LocInfo,
3176
299k
                         ISD::ArgFlagsTy ArgFlags, CCState &State) {
3177
299k
3178
299k
  if (State.getCallingConv() == CallingConv::HiPE) {
3179
28
    if (!RetCC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3180
28
      return false;
3181
299k
  }
3182
299k
3183
299k
  if (State.getCallingConv() == CallingConv::WebKit_JS) {
3184
20
    if (!RetCC_X86_64_WebKit_JS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3185
20
      return false;
3186
299k
  }
3187
299k
3188
299k
  if (State.getCallingConv() == CallingConv::AnyReg) {
3189
0
    if (!RetCC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3190
0
      return false;
3191
299k
  }
3192
299k
3193
299k
  if (State.getCallingConv() == CallingConv::Swift) {
3194
415
    if (!RetCC_X86_64_Swift(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3195
410
      return false;
3196
298k
  }
3197
298k
3198
298k
  if (State.getCallingConv() == CallingConv::Win64) {
3199
35
    if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3200
34
      return false;
3201
298k
  }
3202
298k
3203
298k
  if (State.getCallingConv() == CallingConv::X86_64_SysV) {
3204
8
    if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3205
8
      return false;
3206
298k
  }
3207
298k
3208
298k
  if (State.getCallingConv() == CallingConv::X86_VectorCall) {
3209
64
    if (!RetCC_X86_64_Vectorcall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3210
62
      return false;
3211
298k
  }
3212
298k
3213
298k
  if (State.getCallingConv() == CallingConv::HHVM) {
3214
70
    if (!RetCC_X86_64_HHVM(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3215
70
      return false;
3216
298k
  }
3217
298k
3218
298k
  if (State.getCallingConv() == CallingConv::X86_RegCall) {
3219
342
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
3220
184
      if (!RetCC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3221
184
        return false;
3222
298k
    }
3223
342
  }
3224
298k
3225
298k
  if (State.getCallingConv() == CallingConv::X86_RegCall) {
3226
158
    if (!RetCC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3227
158
      return false;
3228
298k
  }
3229
298k
3230
298k
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) {
3231
2.85k
    if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3232
2.83k
      return false;
3233
295k
  }
3234
295k
3235
295k
  if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3236
294k
    return false;
3237
372
3238
372
  return true;  // CC didn't match.
3239
372
}
3240
3241
3242
static bool RetCC_X86_64_AnyReg(unsigned ValNo, MVT ValVT,
3243
                                MVT LocVT, CCValAssign::LocInfo LocInfo,
3244
0
                                ISD::ArgFlagsTy ArgFlags, CCState &State) {
3245
0
3246
0
  if (CC_X86_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3247
0
    return false;
3248
0
3249
0
  return true;  // CC didn't match.
3250
0
}
3251
3252
3253
static bool RetCC_X86_64_C(unsigned ValNo, MVT ValVT,
3254
                           MVT LocVT, CCValAssign::LocInfo LocInfo,
3255
298k
                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
3256
298k
3257
298k
  if (LocVT == MVT::f32) {
3258
5.16k
    static const MCPhysReg RegList1[] = {
3259
5.16k
      X86::XMM0, X86::XMM1
3260
5.16k
    };
3261
5.16k
    if (unsigned Reg = State.AllocateReg(RegList1)) {
3262
5.16k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3263
5.16k
      return false;
3264
5.16k
    }
3265
293k
  }
3266
293k
3267
293k
  if (LocVT == MVT::f64) {
3268
5.14k
    static const MCPhysReg RegList2[] = {
3269
5.14k
      X86::XMM0, X86::XMM1
3270
5.14k
    };
3271
5.14k
    if (unsigned Reg = State.AllocateReg(RegList2)) {
3272
5.08k
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3273
5.08k
      return false;
3274
5.08k
    }
3275
288k
  }
3276
288k
3277
288k
  if (LocVT == MVT::f128) {
3278
308
    static const MCPhysReg RegList3[] = {
3279
308
      X86::XMM0, X86::XMM1
3280
308
    };
3281
308
    if (unsigned Reg = State.AllocateReg(RegList3)) {
3282
308
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3283
308
      return false;
3284
308
    }
3285
287k
  }
3286
287k
3287
287k
  if (LocVT == MVT::x86mmx) {
3288
204
    static const MCPhysReg RegList4[] = {
3289
204
      X86::XMM0, X86::XMM1
3290
204
    };
3291
204
    if (unsigned Reg = State.AllocateReg(RegList4)) {
3292
204
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3293
204
      return false;
3294
204
    }
3295
287k
  }
3296
287k
3297
287k
  if (ArgFlags.isSwiftError()) {
3298
26
    if (LocVT == MVT::i64) {
3299
26
      if (unsigned Reg = State.AllocateReg(X86::R12)) {
3300
26
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3301
26
        return false;
3302
26
      }
3303
287k
    }
3304
26
  }
3305
287k
3306
287k
  if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3307
287k
    return false;
3308
388
3309
388
  return true;  // CC didn't match.
3310
388
}
3311
3312
3313
static bool RetCC_X86_64_HHVM(unsigned ValNo, MVT ValVT,
3314
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
3315
70
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
3316
70
3317
70
  if (LocVT == MVT::i8 ||
3318
70
      LocVT == MVT::i16 ||
3319
70
      LocVT == MVT::i32) {
3320
0
    LocVT = MVT::i64;
3321
0
    if (ArgFlags.isSExt())
3322
0
        LocInfo = CCValAssign::SExt;
3323
0
    else if (ArgFlags.isZExt())
3324
0
        LocInfo = CCValAssign::ZExt;
3325
0
    else
3326
0
        LocInfo = CCValAssign::AExt;
3327
0
  }
3328
70
3329
70
  if (LocVT == MVT::i64) {
3330
70
    static const MCPhysReg RegList1[] = {
3331
70
      X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9, X86::RAX, X86::R10, X86::R11, X86::R13, X86::R14, X86::R15
3332
70
    };
3333
70
    if (unsigned Reg = State.AllocateReg(RegList1)) {
3334
70
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3335
70
      return false;
3336
70
    }
3337
0
  }
3338
0
3339
0
  return true;  // CC didn't match.
3340
0
}
3341
3342
3343
static bool RetCC_X86_64_HiPE(unsigned ValNo, MVT ValVT,
3344
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
3345
28
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
3346
28
3347
28
  if (LocVT == MVT::i8 ||
3348
28
      LocVT == MVT::i16 ||
3349
28
      LocVT == MVT::i32) {
3350
10
    LocVT = MVT::i64;
3351
10
    if (ArgFlags.isSExt())
3352
0
        LocInfo = CCValAssign::SExt;
3353
10
    else if (ArgFlags.isZExt())
3354
0
        LocInfo = CCValAssign::ZExt;
3355
10
    else
3356
10
        LocInfo = CCValAssign::AExt;
3357
10
  }
3358
28
3359
28
  if (LocVT == MVT::i64) {
3360
28
    static const MCPhysReg RegList1[] = {
3361
28
      X86::R15, X86::RBP, X86::RAX, X86::RDX
3362
28
    };
3363
28
    if (unsigned Reg = State.AllocateReg(RegList1)) {
3364
28
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3365
28
      return false;
3366
28
    }
3367
0
  }
3368
0
3369
0
  return true;  // CC didn't match.
3370
0
}
3371
3372
3373
static bool RetCC_X86_64_Swift(unsigned ValNo, MVT ValVT,
3374
                               MVT LocVT, CCValAssign::LocInfo LocInfo,
3375
415
                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
3376
415
3377
415
  if (ArgFlags.isSwiftError()) {
3378
54
    if (LocVT == MVT::i64) {
3379
54
      if (unsigned Reg = State.AllocateReg(X86::R12)) {
3380
54
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3381
54
        return false;
3382
54
      }
3383
361
    }
3384
54
  }
3385
361
3386
361
  if (LocVT == MVT::v1i1) {
3387
0
    LocVT = MVT::i8;
3388
0
    if (ArgFlags.isSExt())
3389
0
        LocInfo = CCValAssign::SExt;
3390
0
    else if (ArgFlags.isZExt())
3391
0
        LocInfo = CCValAssign::ZExt;
3392
0
    else
3393
0
        LocInfo = CCValAssign::AExt;
3394
0
  }
3395
361
3396
361
  if (LocVT == MVT::i1) {
3397
0
    LocVT = MVT::i8;
3398
0
    if (ArgFlags.isSExt())
3399
0
        LocInfo = CCValAssign::SExt;
3400
0
    else if (ArgFlags.isZExt())
3401
0
        LocInfo = CCValAssign::ZExt;
3402
0
    else
3403
0
        LocInfo = CCValAssign::AExt;
3404
0
  }
3405
361
3406
361
  if (LocVT == MVT::i8) {
3407
38
    static const MCPhysReg RegList1[] = {
3408
38
      X86::AL, X86::DL, X86::CL, X86::R8B
3409
38
    };
3410
38
    if (unsigned Reg = State.AllocateReg(RegList1)) {
3411
38
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3412
38
      return false;
3413
38
    }
3414
323
  }
3415
323
3416
323
  if (LocVT == MVT::i16) {
3417
4
    static const MCPhysReg RegList2[] = {
3418
4
      X86::AX, X86::DX, X86::CX, X86::R8W
3419
4
    };
3420
4
    if (unsigned Reg = State.AllocateReg(RegList2)) {
3421
4
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3422
4
      return false;
3423
4
    }
3424
319
  }
3425
319
3426
319
  if (LocVT == MVT::i32) {
3427
69
    static const MCPhysReg RegList3[] = {
3428
69
      X86::EAX, X86::EDX, X86::ECX, X86::R8D
3429
69
    };
3430
69
    if (unsigned Reg = State.AllocateReg(RegList3)) {
3431
64
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3432
64
      return false;
3433
64
    }
3434
255
  }
3435
255
3436
255
  if (LocVT == MVT::i64) {
3437
104
    static const MCPhysReg RegList4[] = {
3438
104
      X86::RAX, X86::RDX, X86::RCX, X86::R8
3439
104
    };
3440
104
    if (unsigned Reg = State.AllocateReg(RegList4)) {
3441
104
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3442
104
      return false;
3443
104
    }
3444
151
  }
3445
151
3446
151
  if (LocVT == MVT::f32) {
3447
54
    static const MCPhysReg RegList5[] = {
3448
54
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3449
54
    };
3450
54
    if (unsigned Reg = State.AllocateReg(RegList5)) {
3451
54
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3452
54
      return false;
3453
54
    }
3454
97
  }
3455
97
3456
97
  if (LocVT == MVT::f64) {
3457
56
    static const MCPhysReg RegList6[] = {
3458
56
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3459
56
    };
3460
56
    if (unsigned Reg = State.AllocateReg(RegList6)) {
3461
56
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3462
56
      return false;
3463
56
    }
3464
41
  }
3465
41
3466
41
  if (LocVT == MVT::f128) {
3467
0
    static const MCPhysReg RegList7[] = {
3468
0
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3469
0
    };
3470
0
    if (unsigned Reg = State.AllocateReg(RegList7)) {
3471
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3472
0
      return false;
3473
0
    }
3474
41
  }
3475
41
3476
41
  if (LocVT == MVT::x86mmx) {
3477
0
    static const MCPhysReg RegList8[] = {
3478
0
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3479
0
    };
3480
0
    if (unsigned Reg = State.AllocateReg(RegList8)) {
3481
0
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3482
0
      return false;
3483
0
    }
3484
41
  }
3485
41
3486
41
  if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3487
36
    return false;
3488
5
3489
5
  return true;  // CC didn't match.
3490
5
}
3491
3492
3493
static bool RetCC_X86_64_Vectorcall(unsigned ValNo, MVT ValVT,
3494
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
3495
64
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
3496
64
3497
64
  if (LocVT == MVT::f32 ||
3498
64
      LocVT == MVT::f64 ||
3499
64
      
LocVT == MVT::f12838
) {
3500
26
    static const MCPhysReg RegList1[] = {
3501
26
      X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
3502
26
    };
3503
26
    if (unsigned Reg = State.AllocateReg(RegList1)) {
3504
24
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3505
24
      return false;
3506
24
    }
3507
40
  }
3508
40
3509
40
  if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3510
38
    return false;
3511
2
3512
2
  return true;  // CC didn't match.
3513
2
}
3514
3515
3516
static bool RetCC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT,
3517
                                   MVT LocVT, CCValAssign::LocInfo LocInfo,
3518
20
                                   ISD::ArgFlagsTy ArgFlags, CCState &State) {
3519
20
3520
20
  if (LocVT == MVT::i8 ||
3521
20
      LocVT == MVT::i16 ||
3522
20
      LocVT == MVT::i32) {
3523
8
    LocVT = MVT::i64;
3524
8
    if (ArgFlags.isSExt())
3525
0
        LocInfo = CCValAssign::SExt;
3526
8
    else if (ArgFlags.isZExt())
3527
0
        LocInfo = CCValAssign::ZExt;
3528
8
    else
3529
8
        LocInfo = CCValAssign::AExt;
3530
8
  }
3531
20
3532
20
  if (LocVT == MVT::i64) {
3533
20
    if (unsigned Reg = State.AllocateReg(X86::RAX)) {
3534
20
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3535
20
      return false;
3536
20
    }
3537
0
  }
3538
0
3539
0
  return true;  // CC didn't match.
3540
0
}
3541
3542
3543
static bool RetCC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT,
3544
                                     MVT LocVT, CCValAssign::LocInfo LocInfo,
3545
158
                                     ISD::ArgFlagsTy ArgFlags, CCState &State) {
3546
158
3547
158
  if (LocVT == MVT::i1 ||
3548
158
      LocVT == MVT::v1i1 ||
3549
158
      LocVT == MVT::v8i1) {
3550
4
    LocVT = MVT::i8;
3551
4
    if (ArgFlags.isSExt())
3552
0
        LocInfo = CCValAssign::SExt;
3553
4
    else if (ArgFlags.isZExt())
3554
0
        LocInfo = CCValAssign::ZExt;
3555
4
    else
3556
4
        LocInfo = CCValAssign::AExt;
3557
4
  }
3558
158
3559
158
  if (LocVT == MVT::v16i1) {
3560
4
    LocVT = MVT::i16;
3561
4
    if (ArgFlags.isSExt())
3562
0
        LocInfo = CCValAssign::SExt;
3563
4
    else if (ArgFlags.isZExt())
3564
0
        LocInfo = CCValAssign::ZExt;
3565
4
    else
3566
4
        LocInfo = CCValAssign::AExt;
3567
4
  }
3568
158
3569
158
  if (LocVT == MVT::v32i1) {
3570
4
    LocVT = MVT::i32;
3571
4
    if (ArgFlags.isSExt())
3572
0
        LocInfo = CCValAssign::SExt;
3573
4
    else if (ArgFlags.isZExt())
3574
0
        LocInfo = CCValAssign::ZExt;
3575
4
    else
3576
4
        LocInfo = CCValAssign::AExt;
3577
4
  }
3578
158
3579
158
  if (LocVT == MVT::i8) {
3580
28
    static const MCPhysReg RegList1[] = {
3581
28
      X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R12B, X86::R13B, X86::R14B, X86::R15B
3582
28
    };
3583
28
    if (unsigned Reg = State.AllocateReg(RegList1)) {
3584
28
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3585
28
      return false;
3586
28
    }
3587
130
  }
3588
130
3589
130
  if (LocVT == MVT::i16) {
3590
14
    static const MCPhysReg RegList2[] = {
3591
14
      X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R12W, X86::R13W, X86::R14W, X86::R15W
3592
14
    };
3593
14
    if (unsigned Reg = State.AllocateReg(RegList2)) {
3594
14
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3595
14
      return false;
3596
14
    }
3597
116
  }
3598
116
3599
116
  if (LocVT == MVT::i32) {
3600
22
    static const MCPhysReg RegList3[] = {
3601
22
      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D
3602
22
    };
3603
22
    if (unsigned Reg = State.AllocateReg(RegList3)) {
3604
22
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3605
22
      return false;
3606
22
    }
3607
94
  }
3608
94
3609
94
  if (LocVT == MVT::i64) {
3610
18
    static const MCPhysReg RegList4[] = {
3611
18
      X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
3612
18
    };
3613
18
    if (unsigned Reg = State.AllocateReg(RegList4)) {
3614
18
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3615
18
      return false;
3616
18
    }
3617
76
  }
3618
76
3619
76
  if (LocVT == MVT::v64i1) {
3620
4
    LocVT = MVT::i64;
3621
4
    if (ArgFlags.isSExt())
3622
0
        LocInfo = CCValAssign::SExt;
3623
4
    else if (ArgFlags.isZExt())
3624
0
        LocInfo = CCValAssign::ZExt;
3625
4
    else
3626
4
        LocInfo = CCValAssign::AExt;
3627
4
  }
3628
76
3629
76
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
3630
76
    if (LocVT == MVT::i64) {
3631
4
      static const MCPhysReg RegList5[] = {
3632
4
        X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15
3633
4
      };
3634
4
      if (unsigned Reg = State.AllocateReg(RegList5)) {
3635
4
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3636
4
        return false;
3637
4
      }
3638
72
    }
3639
76
  }
3640
72
3641
72
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
3642
0
    if (LocVT == MVT::i64) {
3643
0
      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3644
0
            return false;
3645
72
    }
3646
0
  }
3647
72
3648
72
  if (LocVT == MVT::f80) {
3649
6
    static const MCPhysReg RegList6[] = {
3650
6
      X86::FP0, X86::FP1
3651
6
    };
3652
6
    if (unsigned Reg = State.AllocateReg(RegList6)) {
3653
6
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3654
6
      return false;
3655
6
    }
3656
66
  }
3657
66
3658
66
  if (LocVT == MVT::f32 ||
3659
66
      
LocVT == MVT::f6458
||
3660
66
      
LocVT == MVT::f12850
) {
3661
16
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3662
16
      static const MCPhysReg RegList7[] = {
3663
16
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
3664
16
      };
3665
16
      if (unsigned Reg = State.AllocateReg(RegList7)) {
3666
16
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3667
16
        return false;
3668
16
      }
3669
50
    }
3670
16
  }
3671
50
3672
50
  if (LocVT == MVT::v16i8 ||
3673
50
      LocVT == MVT::v8i16 ||
3674
50
      LocVT == MVT::v4i32 ||
3675
50
      
LocVT == MVT::v2i6444
||
3676
50
      
LocVT == MVT::v4f3244
||
3677
50
      
LocVT == MVT::v2f6420
) {
3678
30
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3679
30
      static const MCPhysReg RegList8[] = {
3680
30
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
3681
30
      };
3682
30
      if (unsigned Reg = State.AllocateReg(RegList8)) {
3683
30
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3684
30
        return false;
3685
30
      }
3686
20
    }
3687
30
  }
3688
20
3689
20
  if (LocVT == MVT::v32i8 ||
3690
20
      LocVT == MVT::v16i16 ||
3691
20
      LocVT == MVT::v8i32 ||
3692
20
      
LocVT == MVT::v4i6414
||
3693
20
      
LocVT == MVT::v8f3214
||
3694
20
      
LocVT == MVT::v4f6414
) {
3695
6
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
3696
6
      static const MCPhysReg RegList9[] = {
3697
6
        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
3698
6
      };
3699
6
      if (unsigned Reg = State.AllocateReg(RegList9)) {
3700
6
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3701
6
        return false;
3702
6
      }
3703
14
    }
3704
6
  }
3705
14
3706
14
  if (LocVT == MVT::v64i8 ||
3707
14
      LocVT == MVT::v32i16 ||
3708
14
      LocVT == MVT::v16i32 ||
3709
14
      
LocVT == MVT::v8i648
||
3710
14
      
LocVT == MVT::v16f328
||
3711
14
      
LocVT == MVT::v8f640
) {
3712
14
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
3713
14
      static const MCPhysReg RegList10[] = {
3714
14
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
3715
14
      };
3716
14
      if (unsigned Reg = State.AllocateReg(RegList10)) {
3717
14
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3718
14
        return false;
3719
14
      }
3720
0
    }
3721
14
  }
3722
0
3723
0
  return true;  // CC didn't match.
3724
0
}
3725
3726
3727
static bool RetCC_X86_Win64_C(unsigned ValNo, MVT ValVT,
3728
                              MVT LocVT, CCValAssign::LocInfo LocInfo,
3729
2.92k
                              ISD::ArgFlagsTy ArgFlags, CCState &State) {
3730
2.92k
3731
2.92k
  if (LocVT == MVT::x86mmx) {
3732
0
    LocVT = MVT::i64;
3733
0
    LocInfo = CCValAssign::BCvt;
3734
0
  }
3735
2.92k
3736
2.92k
  if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3737
2.90k
    return false;
3738
19
3739
19
  return true;  // CC didn't match.
3740
19
}
3741
3742
3743
static bool RetCC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT,
3744
                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
3745
184
                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
3746
184
3747
184
  if (LocVT == MVT::i1 ||
3748
184
      LocVT == MVT::v1i1 ||
3749
184
      LocVT == MVT::v8i1) {
3750
4
    LocVT = MVT::i8;
3751
4
    if (ArgFlags.isSExt())
3752
0
        LocInfo = CCValAssign::SExt;
3753
4
    else if (ArgFlags.isZExt())
3754
0
        LocInfo = CCValAssign::ZExt;
3755
4
    else
3756
4
        LocInfo = CCValAssign::AExt;
3757
4
  }
3758
184
3759
184
  if (LocVT == MVT::v16i1) {
3760
4
    LocVT = MVT::i16;
3761
4
    if (ArgFlags.isSExt())
3762
0
        LocInfo = CCValAssign::SExt;
3763
4
    else if (ArgFlags.isZExt())
3764
0
        LocInfo = CCValAssign::ZExt;
3765
4
    else
3766
4
        LocInfo = CCValAssign::AExt;
3767
4
  }
3768
184
3769
184
  if (LocVT == MVT::v32i1) {
3770
4
    LocVT = MVT::i32;
3771
4
    if (ArgFlags.isSExt())
3772
0
        LocInfo = CCValAssign::SExt;
3773
4
    else if (ArgFlags.isZExt())
3774
0
        LocInfo = CCValAssign::ZExt;
3775
4
    else
3776
4
        LocInfo = CCValAssign::AExt;
3777
4
  }
3778
184
3779
184
  if (LocVT == MVT::i8) {
3780
28
    static const MCPhysReg RegList1[] = {
3781
28
      X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R12B, X86::R14B, X86::R15B
3782
28
    };
3783
28
    if (unsigned Reg = State.AllocateReg(RegList1)) {
3784
28
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3785
28
      return false;
3786
28
    }
3787
156
  }
3788
156
3789
156
  if (LocVT == MVT::i16) {
3790
14
    static const MCPhysReg RegList2[] = {
3791
14
      X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R12W, X86::R14W, X86::R15W
3792
14
    };
3793
14
    if (unsigned Reg = State.AllocateReg(RegList2)) {
3794
14
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3795
14
      return false;
3796
14
    }
3797
142
  }
3798
142
3799
142
  if (LocVT == MVT::i32) {
3800
30
    static const MCPhysReg RegList3[] = {
3801
30
      X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D
3802
30
    };
3803
30
    if (unsigned Reg = State.AllocateReg(RegList3)) {
3804
30
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3805
30
      return false;
3806
30
    }
3807
112
  }
3808
112
3809
112
  if (LocVT == MVT::i64) {
3810
36
    static const MCPhysReg RegList4[] = {
3811
36
      X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
3812
36
    };
3813
36
    if (unsigned Reg = State.AllocateReg(RegList4)) {
3814
36
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3815
36
      return false;
3816
36
    }
3817
76
  }
3818
76
3819
76
  if (LocVT == MVT::v64i1) {
3820
4
    LocVT = MVT::i64;
3821
4
    if (ArgFlags.isSExt())
3822
0
        LocInfo = CCValAssign::SExt;
3823
4
    else if (ArgFlags.isZExt())
3824
0
        LocInfo = CCValAssign::ZExt;
3825
4
    else
3826
4
        LocInfo = CCValAssign::AExt;
3827
4
  }
3828
76
3829
76
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) {
3830
76
    if (LocVT == MVT::i64) {
3831
4
      static const MCPhysReg RegList5[] = {
3832
4
        X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15
3833
4
      };
3834
4
      if (unsigned Reg = State.AllocateReg(RegList5)) {
3835
4
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3836
4
        return false;
3837
4
      }
3838
72
    }
3839
76
  }
3840
72
3841
72
  if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) {
3842
0
    if (LocVT == MVT::i64) {
3843
0
      if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
3844
0
            return false;
3845
72
    }
3846
0
  }
3847
72
3848
72
  if (LocVT == MVT::f80) {
3849
6
    static const MCPhysReg RegList6[] = {
3850
6
      X86::FP0, X86::FP1
3851
6
    };
3852
6
    if (unsigned Reg = State.AllocateReg(RegList6)) {
3853
6
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3854
6
      return false;
3855
6
    }
3856
66
  }
3857
66
3858
66
  if (LocVT == MVT::f32 ||
3859
66
      
LocVT == MVT::f6458
||
3860
66
      
LocVT == MVT::f12850
) {
3861
16
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3862
16
      static const MCPhysReg RegList7[] = {
3863
16
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
3864
16
      };
3865
16
      if (unsigned Reg = State.AllocateReg(RegList7)) {
3866
16
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3867
16
        return false;
3868
16
      }
3869
50
    }
3870
16
  }
3871
50
3872
50
  if (LocVT == MVT::v16i8 ||
3873
50
      LocVT == MVT::v8i16 ||
3874
50
      LocVT == MVT::v4i32 ||
3875
50
      
LocVT == MVT::v2i6444
||
3876
50
      
LocVT == MVT::v4f3244
||
3877
50
      
LocVT == MVT::v2f6420
) {
3878
30
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) {
3879
30
      static const MCPhysReg RegList8[] = {
3880
30
        X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
3881
30
      };
3882
30
      if (unsigned Reg = State.AllocateReg(RegList8)) {
3883
30
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3884
30
        return false;
3885
30
      }
3886
20
    }
3887
30
  }
3888
20
3889
20
  if (LocVT == MVT::v32i8 ||
3890
20
      LocVT == MVT::v16i16 ||
3891
20
      LocVT == MVT::v8i32 ||
3892
20
      
LocVT == MVT::v4i6414
||
3893
20
      
LocVT == MVT::v8f3214
||
3894
20
      
LocVT == MVT::v4f6414
) {
3895
6
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) {
3896
6
      static const MCPhysReg RegList9[] = {
3897
6
        X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15
3898
6
      };
3899
6
      if (unsigned Reg = State.AllocateReg(RegList9)) {
3900
6
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3901
6
        return false;
3902
6
      }
3903
14
    }
3904
6
  }
3905
14
3906
14
  if (LocVT == MVT::v64i8 ||
3907
14
      LocVT == MVT::v32i16 ||
3908
14
      LocVT == MVT::v16i32 ||
3909
14
      
LocVT == MVT::v8i648
||
3910
14
      
LocVT == MVT::v16f328
||
3911
14
      
LocVT == MVT::v8f640
) {
3912
14
    if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) {
3913
14
      static const MCPhysReg RegList10[] = {
3914
14
        X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15
3915
14
      };
3916
14
      if (unsigned Reg = State.AllocateReg(RegList10)) {
3917
14
        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
3918
14
        return false;
3919
14
      }
3920
0
    }
3921
14
  }
3922
0
3923
0
  return true;  // CC didn't match.
3924
0
}